From: Nick Hainke Date: Thu, 4 May 2023 19:13:33 +0000 (+0200) Subject: treewide: remove files for building 5.10 kernel X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=1d3e71bd9710593cc0d7216b0ce9898b8e89aeef;p=openwrt%2Fstaging%2Fmans0n.git treewide: remove files for building 5.10 kernel All targets are bumped to 5.15. Remove the old 5.10 patches, configs and files using: find target/linux -iname '*-5.10' -exec rm -r {} \; Further, remove the 5.10 include. Signed-off-by: Nick Hainke --- diff --git a/include/kernel-5.10 b/include/kernel-5.10 deleted file mode 100644 index bc3926bb3d..0000000000 --- a/include/kernel-5.10 +++ /dev/null @@ -1,2 +0,0 @@ -LINUX_VERSION-5.10 = .179 -LINUX_KERNEL_HASH-5.10.179 = 1bbd445c154b053eea46acc883be548a98179988a9ed3a0b81bddfbf30a37e29 diff --git a/target/linux/apm821xx/config-5.10 b/target/linux/apm821xx/config-5.10 deleted file mode 100644 index 89d72e2641..0000000000 --- a/target/linux/apm821xx/config-5.10 +++ /dev/null @@ -1,244 +0,0 @@ -# CONFIG_40x is not set -CONFIG_44x=y -CONFIG_4xx=y -CONFIG_4xx_SOC=y -# CONFIG_ADVANCED_OPTIONS is not set -CONFIG_APM821xx=y -# CONFIG_APOLLO3G is not set -# CONFIG_ARCHES is not set -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS=11 -CONFIG_ARCH_MMAP_RND_BITS_MAX=17 -CONFIG_ARCH_MMAP_RND_BITS_MIN=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y -CONFIG_AUDIT_ARCH=y -# CONFIG_BAMBOO is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_MQ_PCI=y -CONFIG_BLUESTONE=y -CONFIG_BOOKE=y -CONFIG_BOOKE_WDT=y -# CONFIG_CANYONLANDS is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs noinitrd" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_PPC4XX=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_MD5_PPC is not set -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -# CONFIG_CRYPTO_SHA1_PPC is not set -CONFIG_DATA_SHIFT=12 -CONFIG_DMADEVICES=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_DW_DMAC=y -CONFIG_DW_DMAC_CORE=y -# CONFIG_E200 is not set -CONFIG_EARLY_PRINTK=y -# CONFIG_EBONY is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -# CONFIG_EIGER is not set -CONFIG_EXTRA_TARGETS="uImage" -CONFIG_FIXED_PHY=y -CONFIG_FORCE_PCI=y -# CONFIG_FSL_LBC is not set -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -# CONFIG_GEN_RTC is not set -# CONFIG_GLACIER is not set -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_PPC4XX=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IBM_IIC=y -CONFIG_IBM_EMAC=y -CONFIG_IBM_EMAC_EMAC4=y -CONFIG_IBM_EMAC_POLL_WEIGHT=32 -CONFIG_IBM_EMAC_RGMII=y -CONFIG_IBM_EMAC_RXB=128 -CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256 -CONFIG_IBM_EMAC_TAH=y -CONFIG_IBM_EMAC_TXB=128 -# CONFIG_ICON is not set -CONFIG_ILLEGAL_POINTER_VALUE=0 -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_ISA_DMA_API=y -# CONFIG_JFFS2_FS is not set -# CONFIG_KATMAI is not set -CONFIG_KERNEL_START=0xc0000000 -CONFIG_LEDS_TRIGGER_MTD=y -CONFIG_LEDS_TRIGGER_PATTERN=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MATH_EMULATION is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MIGRATION=y -CONFIG_MMU_GATHER_PAGE_SIZE=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -# CONFIG_MTD_CFI_GEOMETRY is not set -# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NOT_COHERENT_CACHE=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_IRQS=512 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND=y -CONFIG_PACKING=y -CONFIG_PAGE_OFFSET=0xc0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_ARCH_FALLBACKS=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYSICAL_START=0x00000000 -CONFIG_PHYS_64BIT=y -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PMU_SYSFS is not set -CONFIG_PPC=y -CONFIG_PPC32=y -CONFIG_PPC44x_SIMPLE=y -CONFIG_PPC4xx_GPIO=y -CONFIG_PPC4xx_MSI=y -CONFIG_PPC4xx_PCI_EXPRESS=y -# CONFIG_PPC64 is not set -# CONFIG_PPC_47x is not set -# CONFIG_PPC_85xx is not set -# CONFIG_PPC_8xx is not set -CONFIG_PPC_ADV_DEBUG_DACS=2 -CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y -CONFIG_PPC_ADV_DEBUG_DVCS=2 -CONFIG_PPC_ADV_DEBUG_IACS=4 -CONFIG_PPC_ADV_DEBUG_REGS=y -# CONFIG_PPC_BOOK3S_6xx is not set -CONFIG_PPC_DCR=y -CONFIG_PPC_DCR_NATIVE=y -# CONFIG_PPC_EARLY_DEBUG is not set -CONFIG_PPC_FPU=y -CONFIG_PPC_INDIRECT_PCI=y -# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set -CONFIG_PPC_MMU_NOHASH=y -CONFIG_PPC_MMU_NOHASH_32=y -CONFIG_PPC_MSI_BITMAP=y -CONFIG_PPC_PAGE_SHIFT=12 -# CONFIG_PPC_PTDUMP is not set -CONFIG_PPC_UDBG_16550=y -CONFIG_PPC_WERROR=y -CONFIG_PTE_64BIT=y -# CONFIG_RAINIER is not set -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGULATOR=y -CONFIG_RSEQ=y -# CONFIG_SAM440EP is not set -# CONFIG_SCOM_DEBUGFS is not set -# CONFIG_SEQUOIA is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SPARSE_IRQ=y -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_TAISHAN is not set -CONFIG_TASK_SIZE=0xc0000000 -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_THREAD_SHIFT=13 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_VDSO32=y -# CONFIG_VIRTIO_MENU is not set -# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set -# CONFIG_WARP is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_XILINX_SYSACE is not set -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_POWERPC=y -# CONFIG_YOSEMITE is not set -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/apm821xx/patches-5.10/100-dwc2-disable-powerdown.patch b/target/linux/apm821xx/patches-5.10/100-dwc2-disable-powerdown.patch deleted file mode 100644 index ede7d732ff..0000000000 --- a/target/linux/apm821xx/patches-5.10/100-dwc2-disable-powerdown.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 88ca61467a0897c79b1fbf8f5c30691b43b52613 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 26 Dec 2021 22:36:29 +0200 -Subject: [PATCH] dwc2: temporary force to be powered up all times - -the APM821xx's onchip dwc2 misbehaves with 5.4 and 5.10 -when a USB device gets connected. Instead of announcing -and setting up the USB devices it crashes and burns with: - -[ 22.023476] dwc2 4bff80000.usbotg: dwc2_restore_global_registers: no global registers to restore -[ 22.032245] dwc2 4bff80000.usbotg: dwc2_exit_partial_power_down: failed to restore registers -[ 22.040647] dwc2 4bff80000.usbotg: exit partial_power_down failed -[ 22.058765] dwc2 4bff80000.usbotg: HC died; cleaning up - -This is all seemingly fixed with dwc2 from a 5.16-rc6. - -Signed-off-by: Christian Lamparter ---- - ---- a/drivers/usb/dwc2/params.c -+++ b/drivers/usb/dwc2/params.c -@@ -137,6 +137,7 @@ static void dwc2_set_amcc_params(struct - struct dwc2_core_params *p = &hsotg->params; - - p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; -+ p->power_down = DWC2_POWER_DOWN_PARAM_NONE; - } - - static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) diff --git a/target/linux/apm821xx/patches-5.10/201-add-amcc-apollo3g-support.patch b/target/linux/apm821xx/patches-5.10/201-add-amcc-apollo3g-support.patch deleted file mode 100644 index e188954094..0000000000 --- a/target/linux/apm821xx/patches-5.10/201-add-amcc-apollo3g-support.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/powerpc/platforms/44x/Kconfig -+++ b/arch/powerpc/platforms/44x/Kconfig -@@ -121,6 +121,17 @@ config CANYONLANDS - help - This option enables support for the AMCC PPC460EX evaluation board. - -+config APOLLO3G -+ bool "Apollo3G" -+ depends on 44x -+ default n -+ select PPC44x_SIMPLE -+ select APM821xx -+ select IBM_EMAC_RGMII -+ select 460EX -+ help -+ This option enables support for the AMCC Apollo 3G board. -+ - config GLACIER - bool "Glacier" - depends on 44x ---- a/arch/powerpc/platforms/44x/ppc44x_simple.c -+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c -@@ -47,6 +47,7 @@ machine_device_initcall(ppc44x_simple, p - * board.c file for it rather than adding it to this list. - */ - static char *board[] __initdata = { -+ "amcc,apollo3g", - "amcc,arches", - "amcc,bamboo", - "apm,bluestone", diff --git a/target/linux/apm821xx/patches-5.10/300-fix-atheros-nics-on-apm82181.patch b/target/linux/apm821xx/patches-5.10/300-fix-atheros-nics-on-apm82181.patch deleted file mode 100644 index 110726d258..0000000000 --- a/target/linux/apm821xx/patches-5.10/300-fix-atheros-nics-on-apm82181.patch +++ /dev/null @@ -1,51 +0,0 @@ ---- a/arch/powerpc/platforms/4xx/pci.c -+++ b/arch/powerpc/platforms/4xx/pci.c -@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po - u32 val; - - /* -- * Do a software reset on PCIe ports. -- * This code is to fix the issue that pci drivers doesn't re-assign -- * bus number for PCIE devices after Uboot -- * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000 -- * PT quad port, SAS LSI 1064E) -+ * Only reset the PHY when no link is currently established. -+ * This is for the Atheros PCIe board which has problems to establish -+ * the link (again) after this PHY reset. All other currently tested -+ * PCIe boards don't show this problem. - */ -- -- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); -- mdelay(10); -+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); -+ if (!(val & 0x00001000)) { -+ /* -+ * Do a software reset on PCIe ports. -+ * This code is to fix the issue that pci drivers doesn't re-assign -+ * bus number for PCIE devices after Uboot -+ * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000 -+ * PT quad port, SAS LSI 1064E) -+ */ -+ -+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); -+ mdelay(10); -+ } - - if (port->endpoint) - val = PTYPE_LEGACY_ENDPOINT << 20; -@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po - mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); - mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); - -- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); -- mdelay(50); -- mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); -+ val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); -+ if (!(val & 0x00001000)) { -+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); -+ mdelay(50); -+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); -+ } - - mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, - mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | diff --git a/target/linux/apm821xx/patches-5.10/301-fix-memory-map-wndr4700.patch b/target/linux/apm821xx/patches-5.10/301-fix-memory-map-wndr4700.patch deleted file mode 100644 index 452d97e85a..0000000000 --- a/target/linux/apm821xx/patches-5.10/301-fix-memory-map-wndr4700.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/powerpc/platforms/4xx/pci.c -+++ b/arch/powerpc/platforms/4xx/pci.c -@@ -1902,9 +1902,9 @@ static void __init ppc4xx_configure_pcie - * if it works - */ - out_le32(mbase + PECFG_PIM0LAL, 0x00000000); -- out_le32(mbase + PECFG_PIM0LAH, 0x00000000); -+ out_le32(mbase + PECFG_PIM0LAH, 0x00000008); - out_le32(mbase + PECFG_PIM1LAL, 0x00000000); -- out_le32(mbase + PECFG_PIM1LAH, 0x00000000); -+ out_le32(mbase + PECFG_PIM1LAH, 0x0000000c); - out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); - out_le32(mbase + PECFG_PIM01SAL, 0x00000000); - diff --git a/target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch b/target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch deleted file mode 100644 index 754e902769..0000000000 --- a/target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch +++ /dev/null @@ -1,53 +0,0 @@ -From a0dc613140bab907a3d5787a7ae7b0638bf674d0 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Thu, 23 Jun 2016 20:28:20 +0200 -Subject: [PATCH] usb: xhci: force MSI for uPD720201 and - uPD720202 - -The APM82181 does not support MSI-X. When probed, it will -produce a noisy warning. - ---- - drivers/usb/host/pci-quirks.c | 362 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 362 insertions(+) - ---- a/drivers/usb/host/xhci-pci.c -+++ b/drivers/usb/host/xhci-pci.c -@@ -279,6 +279,7 @@ static void xhci_pci_quirks(struct devic - pdev->device == 0x0015) { - xhci->quirks |= XHCI_RESET_ON_RESUME; - xhci->quirks |= XHCI_ZERO_64B_REGS; -+ xhci->quirks |= XHCI_FORCE_MSI; - } - if (pdev->vendor == PCI_VENDOR_ID_VIA) - xhci->quirks |= XHCI_RESET_ON_RESUME; ---- a/drivers/usb/host/xhci.c -+++ b/drivers/usb/host/xhci.c -@@ -431,10 +431,14 @@ static int xhci_try_enable_msi(struct us - free_irq(hcd->irq, hcd); - hcd->irq = 0; - -- ret = xhci_setup_msix(xhci); -- if (ret) -- /* fall back to msi*/ -+ if (xhci->quirks & XHCI_FORCE_MSI) { - ret = xhci_setup_msi(xhci); -+ } else { -+ ret = xhci_setup_msix(xhci); -+ if (ret) -+ /* fall back to msi*/ -+ ret = xhci_setup_msi(xhci); -+ } - - if (!ret) { - hcd->msi_enabled = 1; ---- a/drivers/usb/host/xhci.h -+++ b/drivers/usb/host/xhci.h -@@ -1902,6 +1902,7 @@ struct xhci_hcd { - struct xhci_hub usb2_rhub; - struct xhci_hub usb3_rhub; - /* support xHCI 1.0 spec USB2 hardware LPM */ -+#define XHCI_FORCE_MSI (1 << 24) - unsigned hw_lpm_support:1; - /* Broken Suspend flag for SNPS Suspend resume issue */ - unsigned broken_suspend:1; diff --git a/target/linux/apm821xx/patches-5.10/803-hwmon-tc654-add-detection-routine.patch b/target/linux/apm821xx/patches-5.10/803-hwmon-tc654-add-detection-routine.patch deleted file mode 100644 index ad83ea2d86..0000000000 --- a/target/linux/apm821xx/patches-5.10/803-hwmon-tc654-add-detection-routine.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 694f9bfb8efaef8a33e8992015ff9d0866faf4a2 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 17 Dec 2017 17:27:15 +0100 -Subject: [PATCH 1/2] hwmon: tc654 add detection routine - -This patch adds a detection routine for the TC654/TC655 -chips. Both IDs are listed in the Datasheet. - -Signed-off-by: Christian Lamparter ---- - drivers/hwmon/tc654.c | 29 +++++++++++++++++++++++++++++ - 1 file changed, 29 insertions(+) - ---- a/drivers/hwmon/tc654.c -+++ b/drivers/hwmon/tc654.c -@@ -55,6 +55,11 @@ enum tc654_regs { - /* Register data is read (and cached) at most once per second. */ - #define TC654_UPDATE_INTERVAL HZ - -+/* Manufacturer and Version Identification Register Values */ -+#define TC654_MFR_ID_MICROCHIP 0x84 -+#define TC654_VER_ID 0x00 -+#define TC655_VER_ID 0x01 -+ - struct tc654_data { - struct i2c_client *client; - -@@ -481,6 +486,29 @@ static const struct i2c_device_id tc654_ - {} - }; - -+static int -+tc654_detect(struct i2c_client *new_client, struct i2c_board_info *info) -+{ -+ struct i2c_adapter *adapter = new_client->adapter; -+ int manufacturer, product; -+ -+ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) -+ return -ENODEV; -+ -+ manufacturer = i2c_smbus_read_byte_data(new_client, TC654_REG_MFR_ID); -+ if (manufacturer != TC654_MFR_ID_MICROCHIP) -+ return -ENODEV; -+ -+ product = i2c_smbus_read_byte_data(new_client, TC654_REG_VER_ID); -+ if (!((product == TC654_VER_ID) || (product == TC655_VER_ID))) -+ return -ENODEV; -+ -+ strlcpy(info->type, product == TC654_VER_ID ? "tc654" : "tc655", -+ I2C_NAME_SIZE); -+ return 0; -+} -+ -+ - MODULE_DEVICE_TABLE(i2c, tc654_id); - - static struct i2c_driver tc654_driver = { -@@ -489,6 +517,7 @@ static struct i2c_driver tc654_driver = - }, - .probe_new = tc654_probe, - .id_table = tc654_id, -+ .detect = tc654_detect, - }; - - module_i2c_driver(tc654_driver); diff --git a/target/linux/apm821xx/patches-5.10/804-hwmon-tc654-add-thermal_cooling-device.patch b/target/linux/apm821xx/patches-5.10/804-hwmon-tc654-add-thermal_cooling-device.patch deleted file mode 100644 index 466507a8fb..0000000000 --- a/target/linux/apm821xx/patches-5.10/804-hwmon-tc654-add-thermal_cooling-device.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 4d49367c5303e3ebd17502a45b74de280f6be539 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 13 Feb 2022 01:47:33 +0100 -Subject: hwmon: (tc654) Add thermal_cooling device support - -Adds thermal_cooling device support to the tc654/tc655 -driver. This make it possible to integrate it into a -device-tree supported thermal-zone node as a -cooling device. - -I have been using this patch as part of the Netgear WNDR4700 -Centria NAS Router support within OpenWrt since 2016. - -Signed-off-by: Christian Lamparter -Link: https://lore.kernel.org/r/20220213004733.2421193-1-chunkeey@gmail.com -Signed-off-by: Guenter Roeck ---- ---- a/drivers/hwmon/tc654.c -+++ b/drivers/hwmon/tc654.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - - enum tc654_regs { -@@ -384,28 +385,20 @@ static ssize_t pwm_show(struct device *d - return sprintf(buf, "%d\n", pwm); - } - --static ssize_t pwm_store(struct device *dev, struct device_attribute *da, -- const char *buf, size_t count) -+static int _set_pwm(struct tc654_data *data, unsigned long val) - { -- struct tc654_data *data = dev_get_drvdata(dev); - struct i2c_client *client = data->client; -- unsigned long val; - int ret; - -- if (kstrtoul(buf, 10, &val)) -- return -EINVAL; -- if (val > 255) -- return -EINVAL; -- - mutex_lock(&data->update_lock); - -- if (val == 0) -+ if (val == 0) { - data->config |= TC654_REG_CONFIG_SDM; -- else -+ data->duty_cycle = 0; -+ } else { - data->config &= ~TC654_REG_CONFIG_SDM; -- -- data->duty_cycle = find_closest(val, tc654_pwm_map, -- ARRAY_SIZE(tc654_pwm_map)); -+ data->duty_cycle = val - 1; -+ } - - ret = i2c_smbus_write_byte_data(client, TC654_REG_CONFIG, data->config); - if (ret < 0) -@@ -416,6 +409,24 @@ static ssize_t pwm_store(struct device * - - out: - mutex_unlock(&data->update_lock); -+ return ret; -+} -+ -+static ssize_t pwm_store(struct device *dev, struct device_attribute *da, -+ const char *buf, size_t count) -+{ -+ struct tc654_data *data = dev_get_drvdata(dev); -+ unsigned long val; -+ int ret; -+ -+ if (kstrtoul(buf, 10, &val)) -+ return -EINVAL; -+ if (val > 255) -+ return -EINVAL; -+ if (val > 0) -+ val = find_closest(val, tc654_pwm_map, ARRAY_SIZE(tc654_pwm_map)) + 1; -+ -+ ret = _set_pwm(data, val); - return ret < 0 ? ret : count; - } - -@@ -448,6 +459,58 @@ static struct attribute *tc654_attrs[] = - ATTRIBUTE_GROUPS(tc654); - - /* -+ * thermal cooling device functions -+ * -+ * Account for the "ShutDown Mode (SDM)" state by offsetting -+ * the 16 PWM duty cycle states by 1. -+ * -+ * State 0 = 0% PWM | Shutdown - Fan(s) are off -+ * State 1 = 30% PWM | duty_cycle = 0 -+ * State 2 = ~35% PWM | duty_cycle = 1 -+ * [...] -+ * State 15 = ~95% PWM | duty_cycle = 14 -+ * State 16 = 100% PWM | duty_cycle = 15 -+ */ -+#define TC654_MAX_COOLING_STATE 16 -+ -+static int tc654_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state) -+{ -+ *state = TC654_MAX_COOLING_STATE; -+ return 0; -+} -+ -+static int tc654_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state) -+{ -+ struct tc654_data *data = tc654_update_client(cdev->devdata); -+ -+ if (IS_ERR(data)) -+ return PTR_ERR(data); -+ -+ if (data->config & TC654_REG_CONFIG_SDM) -+ *state = 0; /* FAN is off */ -+ else -+ *state = data->duty_cycle + 1; /* offset PWM States by 1 */ -+ -+ return 0; -+} -+ -+static int tc654_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state) -+{ -+ struct tc654_data *data = tc654_update_client(cdev->devdata); -+ -+ if (IS_ERR(data)) -+ return PTR_ERR(data); -+ -+ return _set_pwm(data, clamp_val(state, 0, TC654_MAX_COOLING_STATE)); -+} -+ -+static const struct thermal_cooling_device_ops tc654_fan_cool_ops = { -+ .get_max_state = tc654_get_max_state, -+ .get_cur_state = tc654_get_cur_state, -+ .set_cur_state = tc654_set_cur_state, -+}; -+ -+/* - * device probe and removal - */ - -@@ -477,7 +540,18 @@ static int tc654_probe(struct i2c_client - hwmon_dev = - devm_hwmon_device_register_with_groups(dev, client->name, data, - tc654_groups); -- return PTR_ERR_OR_ZERO(hwmon_dev); -+ if (IS_ERR(hwmon_dev)) -+ return PTR_ERR(hwmon_dev); -+ -+ if (IS_ENABLED(CONFIG_THERMAL)) { -+ struct thermal_cooling_device *cdev; -+ -+ cdev = devm_thermal_of_cooling_device_register(dev, dev->of_node, client->name, -+ hwmon_dev, &tc654_fan_cool_ops); -+ return PTR_ERR_OR_ZERO(cdev); -+ } -+ -+ return 0; - } - - static const struct i2c_device_id tc654_id[] = { diff --git a/target/linux/apm821xx/patches-5.10/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch b/target/linux/apm821xx/patches-5.10/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch deleted file mode 100644 index 3d7cc39a63..0000000000 --- a/target/linux/apm821xx/patches-5.10/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch +++ /dev/null @@ -1,29 +0,0 @@ -From c9395ad54e2cabb87d408becc37566f3d8248933 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 1 Dec 2019 02:08:23 +0100 -Subject: [PATCH] powerpc: bootwrapper: force gzip as mkimage's compression - method - -Due to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to -instruct the mkimage to use the xz compression, which isn't -supported. This patch forces the gzip compression, which is -supported and doesn't matter because the generated uImage for -the apm821xx target gets ignored as the OpenWrt toolchain will -do separate U-Boot kernel images for each device individually. - -Signed-off-by: Christian Lamparter ---- - arch/powerpc/boot/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -251,7 +251,7 @@ compressor-$(CONFIG_KERNEL_LZO) := lzo - - # args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd - quiet_cmd_wrap = WRAP $@ -- cmd_wrap =$(CONFIG_SHELL) $(wrapper) -Z $(compressor-y) -c -o $@ -p $2 \ -+ cmd_wrap =$(CONFIG_SHELL) $(wrapper) -Z gzip -c -o $@ -p $2 \ - $(CROSSWRAP) $(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) \ - vmlinux - diff --git a/target/linux/archs38/config-5.10 b/target/linux/archs38/config-5.10 deleted file mode 100644 index 442f741328..0000000000 --- a/target/linux/archs38/config-5.10 +++ /dev/null @@ -1,277 +0,0 @@ -# CONFIG_16KSTACKS is not set -CONFIG_ARC=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y -CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y -CONFIG_ARCH_HAS_PTE_SPECIAL=y -CONFIG_ARCH_HAS_SETUP_DMA_OPS=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_ARC_BUILTIN_DTB_NAME="" -CONFIG_ARC_CACHE=y -CONFIG_ARC_CACHE_LINE_SHIFT=6 -CONFIG_ARC_CACHE_PAGES=y -CONFIG_ARC_CPU_HS=y -CONFIG_ARC_CURR_IN_REG=y -CONFIG_ARC_DBG=y -# CONFIG_ARC_DBG_TLB_PARANOIA is not set -CONFIG_ARC_DW2_UNWIND=y -CONFIG_ARC_HAS_ACCL_REGS=y -CONFIG_ARC_HAS_DCACHE=y -# CONFIG_ARC_HAS_DCCM is not set -CONFIG_ARC_HAS_DIV_REM=y -CONFIG_ARC_HAS_ICACHE=y -# CONFIG_ARC_HAS_ICCM is not set -CONFIG_ARC_HAS_LL64=y -CONFIG_ARC_HAS_LLSC=y -# CONFIG_ARC_HAS_PAE40 is not set -CONFIG_ARC_HAS_SWAPE=y -CONFIG_ARC_IRQ_NO_AUTOSAVE=y -CONFIG_ARC_KVADDR_SIZE=256 -CONFIG_ARC_MCIP=y -# CONFIG_ARC_METAWARE_HLINK is not set -CONFIG_ARC_MMU_V4=y -# CONFIG_ARC_PAGE_SIZE_16K is not set -# CONFIG_ARC_PAGE_SIZE_4K is not set -CONFIG_ARC_PAGE_SIZE_8K=y -CONFIG_ARC_PLAT_AXS10X=y -# CONFIG_ARC_PLAT_EZNPS is not set -# CONFIG_ARC_PLAT_TB10X is not set -# CONFIG_ARC_SMP_HALT_ON_RESET is not set -CONFIG_ARC_SOC_HSDK=y -CONFIG_ARC_TIMERS=y -CONFIG_ARC_TIMERS_64BIT=y -CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y -CONFIG_AXS103=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED=y -CONFIG_CC_HAS_KASAN_GENERIC=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y -CONFIG_CLK_HSDK=y -CONFIG_ARC_TUNE_MCPU="" -CONFIG_ARC_DSP_NONE=y -# CONFIG_ARC_FPU_SAVE_RESTORE is not set -# CONFIG_ARC_DSP_KERNEL is not set -# CONFIG_ARC_DSP_USERSPACE is not set -# CONFIG_ARC_DSP_AGU_USERSPACE is not set -# CONFIG_ARC_LPB_DISABLE is not set -# CONFIG_SPI_DW_DMA is not set -CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y -# CONFIG_HARDENED_USERCOPY is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_DMADEVICES=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DWMAC_ANARION=y -CONFIG_DWMAC_GENERIC=y -CONFIG_DW_APB_ICTL=y -CONFIG_DW_AXI_DMAC=y -CONFIG_EXT4_FS=y -# CONFIG_EZNPS_GIC is not set -CONFIG_FAT_FS=y -CONFIG_FB=y -CONFIG_FB_CMDLINE=y -CONFIG_FIXED_PHY=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_SNPS_CREG=y -CONFIG_GRACE_PERIOD=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_FUTEX_CMPXCHG=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PCI=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_IIO=y -CONFIG_IIO_BUFFER=y -CONFIG_IIO_KFIFO_BUF=y -CONFIG_IIO_ST_PRESS=y -CONFIG_IIO_ST_PRESS_I2C=y -CONFIG_IIO_ST_PRESS_SPI=y -CONFIG_IIO_ST_SENSORS_CORE=y -CONFIG_IIO_ST_SENSORS_I2C=y -CONFIG_IIO_ST_SENSORS_SPI=y -CONFIG_IIO_TRIGGER=y -CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_WORK=y -# CONFIG_ISA_ARCOMPACT is not set -CONFIG_ISA_ARCV2=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KERNEL_GZIP=y -CONFIG_LIBFDT=y -CONFIG_LINUX_LINK_BASE=0x90000000 -CONFIG_LINUX_RAM_BASE=0x80000000 -CONFIG_LOCKD=y -CONFIG_LOCKUP_DETECTOR=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MICREL_PHY=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_DW=y -# CONFIG_MMC_DW_BLUEFIELD is not set -# CONFIG_MMC_DW_EXYNOS is not set -# CONFIG_MMC_DW_HI3798CV200 is not set -# CONFIG_MMC_DW_K3 is not set -CONFIG_MMC_DW_PLTFM=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NAMESPACES=y -CONFIG_NATIONAL_PHY=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_NS=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NO_IOPORT_MAP=y -CONFIG_NR_CPUS=4 -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PPS=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_PTP_1588_CLOCK=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_RESET_AXS10X=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_HSDK=y -CONFIG_RESET_SIMPLE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_ARC=y -CONFIG_SERIAL_ARC_CONSOLE=y -CONFIG_SERIAL_ARC_NR_PORTS=1 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOFTLOCKUP_DETECTOR=y -CONFIG_SPI=y -CONFIG_SPI_DESIGNWARE=y -CONFIG_SPI_DW_MMIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -# CONFIG_STANDALONE is not set -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -# CONFIG_STMMAC_SELFTESTS is not set -CONFIG_SUNRPC=y -CONFIG_SWPHY=y -CONFIG_TASKS_RCU=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TI_ADC108S102=y -CONFIG_TREE_SRCU=y -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_USB_SUPPORT=y -# CONFIG_USER_NS is not set -CONFIG_VFAT_FS=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y diff --git a/target/linux/armvirt/32/config-5.10 b/target/linux/armvirt/32/config-5.10 deleted file mode 100644 index 3c6443bcbf..0000000000 --- a/target/linux/armvirt/32/config-5.10 +++ /dev/null @@ -1,75 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_VIRT=y -CONFIG_ARM=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_LPAE=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PSCI=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_CACHE_L2X0=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DMA_OPS=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HAVE_SMP=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_NEON=y -CONFIG_NR_CPUS=4 -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PERF_USE_VMALLOC=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SMP_ON_UP=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 diff --git a/target/linux/armvirt/64/config-5.10 b/target/linux/armvirt/64/config-5.10 deleted file mode 100644 index 275fe4571d..0000000000 --- a/target/linux/armvirt/64/config-5.10 +++ /dev/null @@ -1,154 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_VEXPRESS=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CNP=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_ERRATUM_1165522=y -CONFIG_ARM64_ERRATUM_1286807=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_MODULE_PLTS=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PAN=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_UAO=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM64_VHE=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_SBSA_WATCHDOG=y -CONFIG_ATOMIC64_SELFTEST=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BLK_PM=y -CONFIG_CAVIUM_TX2_ERRATUM_219=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CLK_SP810=y -CONFIG_CLK_VEXPRESS_OSC=y -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PM=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_BS=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CHACHA20=y -CONFIG_CRYPTO_CHACHA20_NEON=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64=y -CONFIG_CRYPTO_SIMD=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DRM=y -CONFIG_DRM_BOCHS=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_QXL=y -CONFIG_DRM_TTM=y -CONFIG_DRM_TTM_DMA_PAGE_POOL=y -CONFIG_DRM_TTM_HELPER=y -CONFIG_DRM_VIRTIO_GPU=y -CONFIG_DRM_VRAM_HELPER=y -CONFIG_FB=y -CONFIG_FB_ARMCLCD=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_FRAME_POINTER=y -CONFIG_FSL_ERRATUM_A008585=y -CONFIG_FUJITSU_ERRATUM_010001=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CSUM=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HDMI=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -# CONFIG_ICST is not set -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_KCMP=y -CONFIG_LCD_CLASS_DEVICE=m -# CONFIG_LCD_PLATFORM is not set -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MFD_VEXPRESS_SYSREG=y -CONFIG_MMC=y -CONFIG_MMC_ARMMMCI=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=64 -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_VEXPRESS=y -CONFIG_POWER_SUPPLY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_SMC91X=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SYNC_FILE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_VEXPRESS_CONFIG=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VIRTIO_DMA_SHARED_BUFFER=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/armvirt/config-5.10 b/target/linux/armvirt/config-5.10 deleted file mode 100644 index 9af7fe18ad..0000000000 --- a/target/linux/armvirt/config-5.10 +++ /dev/null @@ -1,155 +0,0 @@ -CONFIG_9P_FS=y -# CONFIG_9P_FS_POSIX_ACL is not set -# CONFIG_9P_FS_SECURITY is not set -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_PSCI_FW=y -CONFIG_BALLOON_COMPACTION=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_MQ_VIRTIO=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_RNG2=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FAILOVER=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_PL061=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HVC_DRIVER=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY_BALLOON=y -CONFIG_MIGRATION=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_9P=y -# CONFIG_NET_9P_DEBUG is not set -CONFIG_NET_9P_VIRTIO=y -CONFIG_NET_FAILOVER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_NET=y -CONFIG_PADATA=y -CONFIG_PAGE_REPORTING=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_ECAM=y -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_RATIONAL=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_PL031=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SCSI_VIRTIO=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SPARSE_IRQ=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_VIRTIO_MMIO=y -CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y -CONFIG_VIRTIO_NET=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y -CONFIG_XPS=y diff --git a/target/linux/at91/patches-5.10/101-ARM-at91-build-dtb-for-q5xr5.patch b/target/linux/at91/patches-5.10/101-ARM-at91-build-dtb-for-q5xr5.patch deleted file mode 100644 index 2bf8ca52ec..0000000000 --- a/target/linux/at91/patches-5.10/101-ARM-at91-build-dtb-for-q5xr5.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -41,6 +41,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ - at91-kizboxmini-mb.dtb \ - at91-kizboxmini-rd.dtb \ - at91-smartkiz.dtb \ -+ at91-q5xr5.dtb \ - at91-wb45n.dtb \ - at91sam9g15ek.dtb \ - at91sam9g25-gardena-smart-gateway.dtb \ diff --git a/target/linux/at91/patches-5.10/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch b/target/linux/at91/patches-5.10/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch deleted file mode 100644 index e684e5d4db..0000000000 --- a/target/linux/at91/patches-5.10/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 44bb7c72cdd830f54fe18e730205f892d9cbfe39 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 19 Nov 2020 17:43:08 +0200 -Subject: [PATCH 102/247] dt-bindings: clock: at91: add sama7g5 pll defines - -Add SAMA7G5 specific PLL defines to be referenced in a phandle as a -PMC_TYPE_CORE clock. - -Suggested-by: Claudiu Beznea -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c] -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 6 +++--- - include/dt-bindings/clock/at91.h | 10 ++++++++++ - 2 files changed, 13 insertions(+), 3 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -182,13 +182,13 @@ static const struct { - .p = "audiopll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .eid = PMC_I2S0_MUX, }, -+ .eid = PMC_AUDIOPMCPLL, }, - - { .n = "audiopll_diviock", - .p = "audiopll_fracck", - .l = &pll_layout_divio, - .t = PLL_TYPE_DIV, -- .eid = PMC_I2S1_MUX, }, -+ .eid = PMC_AUDIOIOPLL, }, - }, - - [PLL_ID_ETH] = { -@@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(str - if (IS_ERR(regmap)) - return; - -- sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1, -+ sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, - nck(sama7g5_systemck), - nck(sama7g5_periphck), - nck(sama7g5_gck), 8); ---- a/include/dt-bindings/clock/at91.h -+++ b/include/dt-bindings/clock/at91.h -@@ -25,6 +25,16 @@ - #define PMC_PLLBCK 8 - #define PMC_AUDIOPLLCK 9 - -+/* SAMA7G5 */ -+#define PMC_CPUPLL (PMC_MAIN + 1) -+#define PMC_SYSPLL (PMC_MAIN + 2) -+#define PMC_DDRPLL (PMC_MAIN + 3) -+#define PMC_IMGPLL (PMC_MAIN + 4) -+#define PMC_BAUDPLL (PMC_MAIN + 5) -+#define PMC_AUDIOPMCPLL (PMC_MAIN + 6) -+#define PMC_AUDIOIOPLL (PMC_MAIN + 7) -+#define PMC_ETHPLL (PMC_MAIN + 8) -+ - #ifndef AT91_PMC_MOSCS - #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ - #define AT91_PMC_LOCKA 1 /* PLLA Lock */ diff --git a/target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch b/target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch deleted file mode 100644 index cd50dee6e1..0000000000 --- a/target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 19 Nov 2020 17:43:09 +0200 -Subject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be - exported and referenced in DT - -Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock -from phandle in DT. - -Suggested-by: Claudiu Beznea -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -117,7 +117,8 @@ static const struct { - .p = "cpupll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, }, -+ .c = 1, -+ .eid = PMC_CPUPLL, }, - }, - - [PLL_ID_SYS] = { -@@ -131,7 +132,8 @@ static const struct { - .p = "syspll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, }, -+ .c = 1, -+ .eid = PMC_SYSPLL, }, - }, - - [PLL_ID_DDR] = { diff --git a/target/linux/at91/patches-5.10/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch b/target/linux/at91/patches-5.10/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch deleted file mode 100644 index 9feea82490..0000000000 --- a/target/linux/at91/patches-5.10/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch +++ /dev/null @@ -1,42 +0,0 @@ -From b2349278894bb381fa26a8717d3093d53f08fd36 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 19 Nov 2020 17:43:10 +0200 -Subject: [PATCH 104/247] clk: at91: clk-master: add 5th divisor for mck master - -clk-master can have 5 divisors with a field width of 3 bits -on some products. - -Change the mask and number of divisors accordingly. - -Reported-by: Mihai Sain -Signed-off-by: Eugen Hristev -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-master.c | 2 +- - drivers/clk/at91/pmc.h | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -15,7 +15,7 @@ - #define MASTER_PRES_MASK 0x7 - #define MASTER_PRES_MAX MASTER_PRES_MASK - #define MASTER_DIV_SHIFT 8 --#define MASTER_DIV_MASK 0x3 -+#define MASTER_DIV_MASK 0x7 - - #define PMC_MCR 0x30 - #define PMC_MCR_ID_MSK GENMASK(3, 0) ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -48,7 +48,7 @@ extern const struct clk_master_layout at - - struct clk_master_characteristics { - struct clk_range output; -- u32 divisors[4]; -+ u32 divisors[5]; - u8 have_div3_pres; - }; - diff --git a/target/linux/at91/patches-5.10/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch b/target/linux/at91/patches-5.10/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch deleted file mode 100644 index 55e7f913c2..0000000000 --- a/target/linux/at91/patches-5.10/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch +++ /dev/null @@ -1,36 +0,0 @@ -From c41f013e13962dcc78239d5e4834214d44556cfb Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 19 Nov 2020 17:43:11 +0200 -Subject: [PATCH 105/247] clk: at91: sama7g5: add 5th divisor for mck0 layout - and characteristics - -This SoC has the 5th divisor for the mck0 master clock. -Adapt the characteristics accordingly. - -Reported-by: Mihai Sain -Signed-off-by: Eugen Hristev -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -775,13 +775,13 @@ static const struct clk_pll_characterist - /* MCK0 characteristics. */ - static const struct clk_master_characteristics mck0_characteristics = { - .output = { .min = 140000000, .max = 200000000 }, -- .divisors = { 1, 2, 4, 3 }, -+ .divisors = { 1, 2, 4, 3, 5 }, - .have_div3_pres = 1, - }; - - /* MCK0 layout. */ - static const struct clk_master_layout mck0_layout = { -- .mask = 0x373, -+ .mask = 0x773, - .pres_shift = 4, - .offset = 0x28, - }; diff --git a/target/linux/at91/patches-5.10/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch b/target/linux/at91/patches-5.10/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch deleted file mode 100644 index fa76cbb5a3..0000000000 --- a/target/linux/at91/patches-5.10/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch +++ /dev/null @@ -1,510 +0,0 @@ -From 6fe2927863de96edf35d8357712dbf83a489f556 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:12 +0200 -Subject: [PATCH 106/247] clk: at91: clk-sam9x60-pll: allow runtime changes for - pll - -Allow runtime frequency changes for PLLs registered with proper flags. -This is necessary for CPU PLL on SAMA7G5 which is used by DVFS. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-sam9x60-pll.c | 145 +++++++++++++++++++++++++---- - drivers/clk/at91/pmc.h | 4 +- - drivers/clk/at91/sam9x60.c | 22 ++++- - drivers/clk/at91/sama7g5.c | 67 +++++++++---- - 4 files changed, 197 insertions(+), 41 deletions(-) - ---- a/drivers/clk/at91/clk-sam9x60-pll.c -+++ b/drivers/clk/at91/clk-sam9x60-pll.c -@@ -229,6 +229,57 @@ static int sam9x60_frac_pll_set_rate(str - return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); - } - -+static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ struct sam9x60_frac *frac = to_sam9x60_frac(core); -+ struct regmap *regmap = core->regmap; -+ unsigned long irqflags; -+ unsigned int val, cfrac, cmul; -+ long ret; -+ -+ ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); -+ if (ret <= 0) -+ return ret; -+ -+ spin_lock_irqsave(core->lock, irqflags); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, -+ core->id); -+ regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val); -+ cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift; -+ cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift; -+ -+ if (cmul == frac->mul && cfrac == frac->frac) -+ goto unlock; -+ -+ regmap_write(regmap, AT91_PMC_PLL_CTRL1, -+ (frac->mul << core->layout->mul_shift) | -+ (frac->frac << core->layout->frac_shift)); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, -+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, -+ AT91_PMC_PLL_UPDT_UPDATE | core->id); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, -+ AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL, -+ AT91_PMC_PLL_CTRL0_ENLOCK | -+ AT91_PMC_PLL_CTRL0_ENPLL); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, -+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, -+ AT91_PMC_PLL_UPDT_UPDATE | core->id); -+ -+ while (!sam9x60_pll_ready(regmap, core->id)) -+ cpu_relax(); -+ -+unlock: -+ spin_unlock_irqrestore(core->lock, irqflags); -+ -+ return ret; -+} -+ - static const struct clk_ops sam9x60_frac_pll_ops = { - .prepare = sam9x60_frac_pll_prepare, - .unprepare = sam9x60_frac_pll_unprepare, -@@ -238,6 +289,15 @@ static const struct clk_ops sam9x60_frac - .set_rate = sam9x60_frac_pll_set_rate, - }; - -+static const struct clk_ops sam9x60_frac_pll_ops_chg = { -+ .prepare = sam9x60_frac_pll_prepare, -+ .unprepare = sam9x60_frac_pll_unprepare, -+ .is_prepared = sam9x60_frac_pll_is_prepared, -+ .recalc_rate = sam9x60_frac_pll_recalc_rate, -+ .round_rate = sam9x60_frac_pll_round_rate, -+ .set_rate = sam9x60_frac_pll_set_rate_chg, -+}; -+ - static int sam9x60_div_pll_prepare(struct clk_hw *hw) - { - struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -@@ -384,6 +444,44 @@ static int sam9x60_div_pll_set_rate(stru - return 0; - } - -+static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ struct sam9x60_div *div = to_sam9x60_div(core); -+ struct regmap *regmap = core->regmap; -+ unsigned long irqflags; -+ unsigned int val, cdiv; -+ -+ div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; -+ -+ spin_lock_irqsave(core->lock, irqflags); -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, -+ core->id); -+ regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); -+ cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; -+ -+ /* Stop if nothing changed. */ -+ if (cdiv == div->div) -+ goto unlock; -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, -+ core->layout->div_mask, -+ (div->div << core->layout->div_shift)); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, -+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, -+ AT91_PMC_PLL_UPDT_UPDATE | core->id); -+ -+ while (!sam9x60_pll_ready(regmap, core->id)) -+ cpu_relax(); -+ -+unlock: -+ spin_unlock_irqrestore(core->lock, irqflags); -+ -+ return 0; -+} -+ - static const struct clk_ops sam9x60_div_pll_ops = { - .prepare = sam9x60_div_pll_prepare, - .unprepare = sam9x60_div_pll_unprepare, -@@ -393,17 +491,26 @@ static const struct clk_ops sam9x60_div_ - .set_rate = sam9x60_div_pll_set_rate, - }; - -+static const struct clk_ops sam9x60_div_pll_ops_chg = { -+ .prepare = sam9x60_div_pll_prepare, -+ .unprepare = sam9x60_div_pll_unprepare, -+ .is_prepared = sam9x60_div_pll_is_prepared, -+ .recalc_rate = sam9x60_div_pll_recalc_rate, -+ .round_rate = sam9x60_div_pll_round_rate, -+ .set_rate = sam9x60_div_pll_set_rate_chg, -+}; -+ - struct clk_hw * __init - sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, bool critical) -+ const struct clk_pll_layout *layout, u32 flags) - { - struct sam9x60_frac *frac; - struct clk_hw *hw; - struct clk_init_data init; -- unsigned long parent_rate, flags; -+ unsigned long parent_rate, irqflags; - unsigned int val; - int ret; - -@@ -417,10 +524,12 @@ sam9x60_clk_register_frac_pll(struct reg - init.name = name; - init.parent_names = &parent_name; - init.num_parents = 1; -- init.ops = &sam9x60_frac_pll_ops; -- init.flags = CLK_SET_RATE_GATE; -- if (critical) -- init.flags |= CLK_IS_CRITICAL; -+ if (flags & CLK_SET_RATE_GATE) -+ init.ops = &sam9x60_frac_pll_ops; -+ else -+ init.ops = &sam9x60_frac_pll_ops_chg; -+ -+ init.flags = flags; - - frac->core.id = id; - frac->core.hw.init = &init; -@@ -429,7 +538,7 @@ sam9x60_clk_register_frac_pll(struct reg - frac->core.regmap = regmap; - frac->core.lock = lock; - -- spin_lock_irqsave(frac->core.lock, flags); -+ spin_lock_irqsave(frac->core.lock, irqflags); - if (sam9x60_pll_ready(regmap, id)) { - regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, - AT91_PMC_PLL_UPDT_ID_MSK, id); -@@ -457,7 +566,7 @@ sam9x60_clk_register_frac_pll(struct reg - goto free; - } - } -- spin_unlock_irqrestore(frac->core.lock, flags); -+ spin_unlock_irqrestore(frac->core.lock, irqflags); - - hw = &frac->core.hw; - ret = clk_hw_register(NULL, hw); -@@ -469,7 +578,7 @@ sam9x60_clk_register_frac_pll(struct reg - return hw; - - free: -- spin_unlock_irqrestore(frac->core.lock, flags); -+ spin_unlock_irqrestore(frac->core.lock, irqflags); - kfree(frac); - return hw; - } -@@ -478,12 +587,12 @@ struct clk_hw * __init - sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, bool critical) -+ const struct clk_pll_layout *layout, u32 flags) - { - struct sam9x60_div *div; - struct clk_hw *hw; - struct clk_init_data init; -- unsigned long flags; -+ unsigned long irqflags; - unsigned int val; - int ret; - -@@ -497,11 +606,11 @@ sam9x60_clk_register_div_pll(struct regm - init.name = name; - init.parent_names = &parent_name; - init.num_parents = 1; -- init.ops = &sam9x60_div_pll_ops; -- init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -- CLK_SET_RATE_PARENT; -- if (critical) -- init.flags |= CLK_IS_CRITICAL; -+ if (flags & CLK_SET_RATE_GATE) -+ init.ops = &sam9x60_div_pll_ops; -+ else -+ init.ops = &sam9x60_div_pll_ops_chg; -+ init.flags = flags; - - div->core.id = id; - div->core.hw.init = &init; -@@ -510,14 +619,14 @@ sam9x60_clk_register_div_pll(struct regm - div->core.regmap = regmap; - div->core.lock = lock; - -- spin_lock_irqsave(div->core.lock, flags); -+ spin_lock_irqsave(div->core.lock, irqflags); - - regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, - AT91_PMC_PLL_UPDT_ID_MSK, id); - regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); - div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val); - -- spin_unlock_irqrestore(div->core.lock, flags); -+ spin_unlock_irqrestore(div->core.lock, irqflags); - - hw = &div->core.hw; - ret = clk_hw_register(NULL, hw); ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -190,14 +190,14 @@ struct clk_hw * __init - sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, bool critical); -+ const struct clk_pll_layout *layout, u32 flags); - - struct clk_hw * __init - sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, bool critical); -+ const struct clk_pll_layout *layout, u32 flags); - - struct clk_hw * __init - at91_clk_register_programmable(struct regmap *regmap, const char *name, ---- a/drivers/clk/at91/sam9x60.c -+++ b/drivers/clk/at91/sam9x60.c -@@ -224,13 +224,24 @@ static void __init sam9x60_pmc_setup(str - hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", - "mainck", sam9x60_pmc->chws[PMC_MAIN], - 0, &plla_characteristics, -- &pll_frac_layout, true); -+ &pll_frac_layout, -+ /* -+ * This feeds pllack_divck which -+ * feeds CPU. It should not be -+ * disabled. -+ */ -+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - - hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", - "pllack_fracck", 0, &plla_characteristics, -- &pll_div_layout, true); -+ &pll_div_layout, -+ /* -+ * This feeds CPU. It should not -+ * be disabled. -+ */ -+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -239,13 +250,16 @@ static void __init sam9x60_pmc_setup(str - hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", - "main_osc", main_osc_hw, 1, - &upll_characteristics, -- &pll_frac_layout, false); -+ &pll_frac_layout, CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - - hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", - "upllck_fracck", 1, &upll_characteristics, -- &pll_div_layout, false); -+ &pll_div_layout, -+ CLK_SET_RATE_GATE | -+ CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -95,15 +95,15 @@ static const struct clk_pll_layout pll_l - * @p: clock parent - * @l: clock layout - * @t: clock type -- * @f: true if clock is critical and cannot be disabled -+ * @f: clock flags - * @eid: export index in sama7g5->chws[] array - */ - static const struct { - const char *n; - const char *p; - const struct clk_pll_layout *l; -+ unsigned long f; - u8 t; -- u8 c; - u8 eid; - } sama7g5_plls[][PLL_ID_MAX] = { - [PLL_ID_CPU] = { -@@ -111,13 +111,18 @@ static const struct { - .p = "mainck", - .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, -- .c = 1, }, -+ /* -+ * This feeds cpupll_divpmcck which feeds CPU. It should -+ * not be disabled. -+ */ -+ .f = CLK_IS_CRITICAL, }, - - { .n = "cpupll_divpmcck", - .p = "cpupll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, -+ /* This feeds CPU. It should not be disabled. */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .eid = PMC_CPUPLL, }, - }, - -@@ -126,13 +131,22 @@ static const struct { - .p = "mainck", - .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, -- .c = 1, }, -+ /* -+ * This feeds syspll_divpmcck which may feed critial parts -+ * of the systems like timers. Therefore it should not be -+ * disabled. -+ */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, - - { .n = "syspll_divpmcck", - .p = "syspll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, -+ /* -+ * This may feed critial parts of the systems like timers. -+ * Therefore it should not be disabled. -+ */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, - .eid = PMC_SYSPLL, }, - }, - -@@ -141,55 +155,71 @@ static const struct { - .p = "mainck", - .l = &pll_layout_frac, - .t = PLL_TYPE_FRAC, -- .c = 1, }, -+ /* -+ * This feeds ddrpll_divpmcck which feeds DDR. It should not -+ * be disabled. -+ */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, - - { .n = "ddrpll_divpmcck", - .p = "ddrpll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -- .c = 1, }, -+ /* This feeds DDR. It should not be disabled. */ -+ .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, - }, - - [PLL_ID_IMG] = { - { .n = "imgpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -- .t = PLL_TYPE_FRAC, }, -+ .t = PLL_TYPE_FRAC, -+ .f = CLK_SET_RATE_GATE, }, - - { .n = "imgpll_divpmcck", - .p = "imgpll_fracck", - .l = &pll_layout_divpmc, -- .t = PLL_TYPE_DIV, }, -+ .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, }, - }, - - [PLL_ID_BAUD] = { - { .n = "baudpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -- .t = PLL_TYPE_FRAC, }, -+ .t = PLL_TYPE_FRAC, -+ .f = CLK_SET_RATE_GATE, }, - - { .n = "baudpll_divpmcck", - .p = "baudpll_fracck", - .l = &pll_layout_divpmc, -- .t = PLL_TYPE_DIV, }, -+ .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, }, - }, - - [PLL_ID_AUDIO] = { - { .n = "audiopll_fracck", - .p = "main_xtal", - .l = &pll_layout_frac, -- .t = PLL_TYPE_FRAC, }, -+ .t = PLL_TYPE_FRAC, -+ .f = CLK_SET_RATE_GATE, }, - - { .n = "audiopll_divpmcck", - .p = "audiopll_fracck", - .l = &pll_layout_divpmc, - .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, - .eid = PMC_AUDIOPMCPLL, }, - - { .n = "audiopll_diviock", - .p = "audiopll_fracck", - .l = &pll_layout_divio, - .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, - .eid = PMC_AUDIOIOPLL, }, - }, - -@@ -197,12 +227,15 @@ static const struct { - { .n = "ethpll_fracck", - .p = "main_xtal", - .l = &pll_layout_frac, -- .t = PLL_TYPE_FRAC, }, -+ .t = PLL_TYPE_FRAC, -+ .f = CLK_SET_RATE_GATE, }, - - { .n = "ethpll_divpmcck", - .p = "ethpll_fracck", - .l = &pll_layout_divpmc, -- .t = PLL_TYPE_DIV, }, -+ .t = PLL_TYPE_DIV, -+ .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | -+ CLK_SET_RATE_PARENT, }, - }, - }; - -@@ -890,7 +923,7 @@ static void __init sama7g5_pmc_setup(str - sama7g5_plls[i][j].p, parent_hw, i, - &pll_characteristics, - sama7g5_plls[i][j].l, -- sama7g5_plls[i][j].c); -+ sama7g5_plls[i][j].f); - break; - - case PLL_TYPE_DIV: -@@ -899,7 +932,7 @@ static void __init sama7g5_pmc_setup(str - sama7g5_plls[i][j].p, i, - &pll_characteristics, - sama7g5_plls[i][j].l, -- sama7g5_plls[i][j].c); -+ sama7g5_plls[i][j].f); - break; - - default: diff --git a/target/linux/at91/patches-5.10/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch b/target/linux/at91/patches-5.10/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch deleted file mode 100644 index 209c40cf2f..0000000000 --- a/target/linux/at91/patches-5.10/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch +++ /dev/null @@ -1,196 +0,0 @@ -From 7cfe2dfe5ac7c72b904e4b59b240caa42721ee07 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:13 +0200 -Subject: [PATCH 107/247] clk: at91: sama7g5: remove mck0 from parent list of - other clocks - -MCK0 is changed at runtime by DVFS. Due to this, since not all IPs -are glitch free aware at MCK0 changes, remove MCK0 from parent list -of other clocks (e.g. generic clock, programmable/system clock, MCKX). - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 55 ++++++++++++++++++-------------------- - 1 file changed, 26 insertions(+), 29 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -280,7 +280,7 @@ static const struct { - .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", }, - .ep_mux_table = { 5, 6, 7, }, - .ep_count = 3, -- .ep_chg_id = 6, }, -+ .ep_chg_id = 5, }, - - { .n = "mck4", - .id = 4, -@@ -313,7 +313,7 @@ static const struct { - }; - - /* Mux table for programmable clocks. */ --static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, }; -+static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; - - /** - * Peripheral clock description -@@ -436,7 +436,7 @@ static const struct { - .pp = { "audiopll_divpmcck", }, - .pp_mux_table = { 9, }, - .pp_count = 1, -- .pp_chg_id = 4, }, -+ .pp_chg_id = 3, }, - - { .n = "csi_gclk", - .id = 33, -@@ -548,7 +548,7 @@ static const struct { - .pp = { "ethpll_divpmcck", }, - .pp_mux_table = { 10, }, - .pp_count = 1, -- .pp_chg_id = 4, }, -+ .pp_chg_id = 3, }, - - { .n = "gmac1_gclk", - .id = 52, -@@ -580,7 +580,7 @@ static const struct { - .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, - .pp_mux_table = { 5, 9, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "i2smcc1_gclk", - .id = 58, -@@ -588,7 +588,7 @@ static const struct { - .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, - .pp_mux_table = { 5, 9, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "mcan0_gclk", - .id = 61, -@@ -730,7 +730,7 @@ static const struct { - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "sdmmc1_gclk", - .id = 81, -@@ -738,7 +738,7 @@ static const struct { - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "sdmmc2_gclk", - .id = 82, -@@ -746,7 +746,7 @@ static const struct { - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "spdifrx_gclk", - .id = 84, -@@ -754,7 +754,7 @@ static const struct { - .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, - .pp_mux_table = { 5, 9, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "spdiftx_gclk", - .id = 85, -@@ -762,7 +762,7 @@ static const struct { - .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, - .pp_mux_table = { 5, 9, }, - .pp_count = 2, -- .pp_chg_id = 5, }, -+ .pp_chg_id = 4, }, - - { .n = "tcb0_ch0_gclk", - .id = 88, -@@ -961,9 +961,8 @@ static void __init sama7g5_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = td_slck_name; - parent_names[2] = "mainck"; -- parent_names[3] = "mck0"; - for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { -- u8 num_parents = 4 + sama7g5_mckx[i].ep_count; -+ u8 num_parents = 3 + sama7g5_mckx[i].ep_count; - u32 *mux_table; - - mux_table = kmalloc_array(num_parents, sizeof(*mux_table), -@@ -971,10 +970,10 @@ static void __init sama7g5_pmc_setup(str - if (!mux_table) - goto err_free; - -- SAMA7G5_INIT_TABLE(mux_table, 4); -- SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_mckx[i].ep_mux_table, -+ SAMA7G5_INIT_TABLE(mux_table, 3); -+ SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, - sama7g5_mckx[i].ep_count); -- SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_mckx[i].ep, -+ SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep, - sama7g5_mckx[i].ep_count); - - hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, -@@ -997,20 +996,19 @@ static void __init sama7g5_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = td_slck_name; - parent_names[2] = "mainck"; -- parent_names[3] = "mck0"; -- parent_names[4] = "syspll_divpmcck"; -- parent_names[5] = "ddrpll_divpmcck"; -- parent_names[6] = "imgpll_divpmcck"; -- parent_names[7] = "baudpll_divpmcck"; -- parent_names[8] = "audiopll_divpmcck"; -- parent_names[9] = "ethpll_divpmcck"; -+ parent_names[3] = "syspll_divpmcck"; -+ parent_names[4] = "ddrpll_divpmcck"; -+ parent_names[5] = "imgpll_divpmcck"; -+ parent_names[6] = "baudpll_divpmcck"; -+ parent_names[7] = "audiopll_divpmcck"; -+ parent_names[8] = "ethpll_divpmcck"; - for (i = 0; i < 8; i++) { - char name[6]; - - snprintf(name, sizeof(name), "prog%d", i); - - hw = at91_clk_register_programmable(regmap, name, parent_names, -- 10, i, -+ 9, i, - &programmable_layout, - sama7g5_prog_mux_table); - if (IS_ERR(hw)) -@@ -1047,9 +1045,8 @@ static void __init sama7g5_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = td_slck_name; - parent_names[2] = "mainck"; -- parent_names[3] = "mck0"; - for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { -- u8 num_parents = 4 + sama7g5_gck[i].pp_count; -+ u8 num_parents = 3 + sama7g5_gck[i].pp_count; - u32 *mux_table; - - mux_table = kmalloc_array(num_parents, sizeof(*mux_table), -@@ -1057,10 +1054,10 @@ static void __init sama7g5_pmc_setup(str - if (!mux_table) - goto err_free; - -- SAMA7G5_INIT_TABLE(mux_table, 4); -- SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_gck[i].pp_mux_table, -+ SAMA7G5_INIT_TABLE(mux_table, 3); -+ SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, - sama7g5_gck[i].pp_count); -- SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_gck[i].pp, -+ SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp, - sama7g5_gck[i].pp_count); - - hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, diff --git a/target/linux/at91/patches-5.10/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch b/target/linux/at91/patches-5.10/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch deleted file mode 100644 index 2bc1907cfb..0000000000 --- a/target/linux/at91/patches-5.10/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 8b88f1e9918c173b24b43015cdb713cdde9e4d17 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:14 +0200 -Subject: [PATCH 108/247] clk: at91: sama7g5: decrease lower limit for MCK0 - rate - -On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and -CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is -also changed by DVFS to avoid over/under clocking of MCK0 consumers. -The lower limit is changed to be able to set MCK0 accordingly by -DVFS. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -807,7 +807,7 @@ static const struct clk_pll_characterist - - /* MCK0 characteristics. */ - static const struct clk_master_characteristics mck0_characteristics = { -- .output = { .min = 140000000, .max = 200000000 }, -+ .output = { .min = 50000000, .max = 200000000 }, - .divisors = { 1, 2, 4, 3, 5 }, - .have_div3_pres = 1, - }; diff --git a/target/linux/at91/patches-5.10/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch b/target/linux/at91/patches-5.10/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch deleted file mode 100644 index b11efc9d4e..0000000000 --- a/target/linux/at91/patches-5.10/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch +++ /dev/null @@ -1,221 +0,0 @@ -From 943ed75a2a5ab08582d3bc8025e8111903698763 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:15 +0200 -Subject: [PATCH 109/247] clk: at91: sama7g5: do not allow cpu pll to go higher - than 1GHz - -Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher -than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at -1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++--------- - 1 file changed, 47 insertions(+), 14 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_l - .endiv_shift = 30, - }; - -+/* -+ * CPU PLL output range. -+ * Notice: The upper limit has been setup to 1000000002 due to hardware -+ * block which cannot output exactly 1GHz. -+ */ -+static const struct clk_range cpu_pll_outputs[] = { -+ { .min = 2343750, .max = 1000000002 }, -+}; -+ -+/* PLL output range. */ -+static const struct clk_range pll_outputs[] = { -+ { .min = 2343750, .max = 1200000000 }, -+}; -+ -+/* CPU PLL characteristics. */ -+static const struct clk_pll_characteristics cpu_pll_characteristics = { -+ .input = { .min = 12000000, .max = 50000000 }, -+ .num_output = ARRAY_SIZE(cpu_pll_outputs), -+ .output = cpu_pll_outputs, -+}; -+ -+/* PLL characteristics. */ -+static const struct clk_pll_characteristics pll_characteristics = { -+ .input = { .min = 12000000, .max = 50000000 }, -+ .num_output = ARRAY_SIZE(pll_outputs), -+ .output = pll_outputs, -+}; -+ - /** - * PLL clocks description - * @n: clock name - * @p: clock parent - * @l: clock layout -+ * @c: clock characteristics - * @t: clock type - * @f: clock flags - * @eid: export index in sama7g5->chws[] array -@@ -102,6 +131,7 @@ static const struct { - const char *n; - const char *p; - const struct clk_pll_layout *l; -+ const struct clk_pll_characteristics *c; - unsigned long f; - u8 t; - u8 eid; -@@ -110,6 +140,7 @@ static const struct { - { .n = "cpupll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &cpu_pll_characteristics, - .t = PLL_TYPE_FRAC, - /* - * This feeds cpupll_divpmcck which feeds CPU. It should -@@ -120,6 +151,7 @@ static const struct { - { .n = "cpupll_divpmcck", - .p = "cpupll_fracck", - .l = &pll_layout_divpmc, -+ .c = &cpu_pll_characteristics, - .t = PLL_TYPE_DIV, - /* This feeds CPU. It should not be disabled. */ - .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, -@@ -130,6 +162,7 @@ static const struct { - { .n = "syspll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - /* - * This feeds syspll_divpmcck which may feed critial parts -@@ -141,6 +174,7 @@ static const struct { - { .n = "syspll_divpmcck", - .p = "syspll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - /* - * This may feed critial parts of the systems like timers. -@@ -154,6 +188,7 @@ static const struct { - { .n = "ddrpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - /* - * This feeds ddrpll_divpmcck which feeds DDR. It should not -@@ -164,6 +199,7 @@ static const struct { - { .n = "ddrpll_divpmcck", - .p = "ddrpll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - /* This feeds DDR. It should not be disabled. */ - .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, -@@ -173,12 +209,14 @@ static const struct { - { .n = "imgpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - .f = CLK_SET_RATE_GATE, }, - - { .n = "imgpll_divpmcck", - .p = "imgpll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, }, -@@ -188,12 +226,14 @@ static const struct { - { .n = "baudpll_fracck", - .p = "mainck", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - .f = CLK_SET_RATE_GATE, }, - - { .n = "baudpll_divpmcck", - .p = "baudpll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, }, -@@ -203,12 +243,14 @@ static const struct { - { .n = "audiopll_fracck", - .p = "main_xtal", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - .f = CLK_SET_RATE_GATE, }, - - { .n = "audiopll_divpmcck", - .p = "audiopll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, -@@ -217,6 +259,7 @@ static const struct { - { .n = "audiopll_diviock", - .p = "audiopll_fracck", - .l = &pll_layout_divio, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, -@@ -227,12 +270,14 @@ static const struct { - { .n = "ethpll_fracck", - .p = "main_xtal", - .l = &pll_layout_frac, -+ .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - .f = CLK_SET_RATE_GATE, }, - - { .n = "ethpll_divpmcck", - .p = "ethpll_fracck", - .l = &pll_layout_divpmc, -+ .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | - CLK_SET_RATE_PARENT, }, -@@ -793,18 +838,6 @@ static const struct { - .pp_chg_id = INT_MIN, }, - }; - --/* PLL output range. */ --static const struct clk_range pll_outputs[] = { -- { .min = 2343750, .max = 1200000000 }, --}; -- --/* PLL characteristics. */ --static const struct clk_pll_characteristics pll_characteristics = { -- .input = { .min = 12000000, .max = 50000000 }, -- .num_output = ARRAY_SIZE(pll_outputs), -- .output = pll_outputs, --}; -- - /* MCK0 characteristics. */ - static const struct clk_master_characteristics mck0_characteristics = { - .output = { .min = 50000000, .max = 200000000 }, -@@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(str - hw = sam9x60_clk_register_frac_pll(regmap, - &pmc_pll_lock, sama7g5_plls[i][j].n, - sama7g5_plls[i][j].p, parent_hw, i, -- &pll_characteristics, -+ sama7g5_plls[i][j].c, - sama7g5_plls[i][j].l, - sama7g5_plls[i][j].f); - break; -@@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(str - hw = sam9x60_clk_register_div_pll(regmap, - &pmc_pll_lock, sama7g5_plls[i][j].n, - sama7g5_plls[i][j].p, i, -- &pll_characteristics, -+ sama7g5_plls[i][j].c, - sama7g5_plls[i][j].l, - sama7g5_plls[i][j].f); - break; diff --git a/target/linux/at91/patches-5.10/110-clk-at91-clk-master-re-factor-master-clock.patch b/target/linux/at91/patches-5.10/110-clk-at91-clk-master-re-factor-master-clock.patch deleted file mode 100644 index a0eadd8886..0000000000 --- a/target/linux/at91/patches-5.10/110-clk-at91-clk-master-re-factor-master-clock.patch +++ /dev/null @@ -1,1230 +0,0 @@ -From 9109b768fe65994547ef464b13e508b22de3e89b Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:16 +0200 -Subject: [PATCH 110/247] clk: at91: clk-master: re-factor master clock - -Re-factor master clock driver by splitting it into 2 clocks: prescaller -and divider clocks. Based on registered clock flags the prescaler's rate -could be changed at runtime. This is necessary for platforms supporting -DVFS (e.g. SAMA7G5) where master clock could be changed at run-time. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/at91rm9200.c | 21 ++- - drivers/clk/at91/at91sam9260.c | 26 ++- - drivers/clk/at91/at91sam9g45.c | 32 +++- - drivers/clk/at91/at91sam9n12.c | 36 ++-- - drivers/clk/at91/at91sam9rl.c | 23 ++- - drivers/clk/at91/at91sam9x5.c | 28 ++- - drivers/clk/at91/clk-master.c | 335 ++++++++++++++++++++++++++++----- - drivers/clk/at91/dt-compat.c | 15 +- - drivers/clk/at91/pmc.h | 16 +- - drivers/clk/at91/sam9x60.c | 23 ++- - drivers/clk/at91/sama5d2.c | 42 +++-- - drivers/clk/at91/sama5d3.c | 38 ++-- - drivers/clk/at91/sama5d4.c | 40 ++-- - drivers/clk/at91/sama7g5.c | 13 +- - 14 files changed, 542 insertions(+), 146 deletions(-) - ---- a/drivers/clk/at91/at91rm9200.c -+++ b/drivers/clk/at91/at91rm9200.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(rm9200_mck_lock); -+ - struct sck { - char *n; - char *p; -@@ -137,9 +139,20 @@ static void __init at91rm9200_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "pllack"; - parent_names[3] = "pllbck"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91rm9200_master_layout, -- &rm9200_mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91rm9200_master_layout, -+ &rm9200_mck_characteristics, -+ &rm9200_mck_lock, CLK_SET_RATE_GATE, -+ INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91rm9200_master_layout, -+ &rm9200_mck_characteristics, -+ &rm9200_mck_lock, CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -181,7 +194,7 @@ static void __init at91rm9200_pmc_setup( - for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) { - hw = at91_clk_register_peripheral(regmap, - at91rm9200_periphck[i].n, -- "masterck", -+ "masterck_div", - at91rm9200_periphck[i].id); - if (IS_ERR(hw)) - goto err_free; ---- a/drivers/clk/at91/at91sam9260.c -+++ b/drivers/clk/at91/at91sam9260.c -@@ -32,6 +32,8 @@ struct at91sam926x_data { - bool has_slck; - }; - -+static DEFINE_SPINLOCK(at91sam9260_mck_lock); -+ - static const struct clk_master_characteristics sam9260_mck_characteristics = { - .output = { .min = 0, .max = 105000000 }, - .divisors = { 1, 2, 4, 0 }, -@@ -218,8 +220,8 @@ static const struct sck at91sam9261_syst - { .n = "pck1", .p = "prog1", .id = 9 }, - { .n = "pck2", .p = "prog2", .id = 10 }, - { .n = "pck3", .p = "prog3", .id = 11 }, -- { .n = "hclk0", .p = "masterck", .id = 16 }, -- { .n = "hclk1", .p = "masterck", .id = 17 }, -+ { .n = "hclk0", .p = "masterck_div", .id = 16 }, -+ { .n = "hclk1", .p = "masterck_div", .id = 17 }, - }; - - static const struct pck at91sam9261_periphck[] = { -@@ -413,9 +415,21 @@ static void __init at91sam926x_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "pllack"; - parent_names[3] = "pllbck"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91rm9200_master_layout, -- data->mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91rm9200_master_layout, -+ data->mck_characteristics, -+ &at91sam9260_mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91rm9200_master_layout, -+ data->mck_characteristics, -+ &at91sam9260_mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -457,7 +471,7 @@ static void __init at91sam926x_pmc_setup - for (i = 0; i < data->num_pck; i++) { - hw = at91_clk_register_peripheral(regmap, - data->pck[i].n, -- "masterck", -+ "masterck_div", - data->pck[i].id); - if (IS_ERR(hw)) - goto err_free; ---- a/drivers/clk/at91/at91sam9g45.c -+++ b/drivers/clk/at91/at91sam9g45.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(at91sam9g45_mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 0, .max = 133333333 }, - .divisors = { 1, 2, 4, 3 }, -@@ -40,10 +42,10 @@ static const struct { - char *p; - u8 id; - } at91sam9g45_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, - }; - - struct pck { -@@ -148,9 +150,21 @@ static void __init at91sam9g45_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91rm9200_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91rm9200_master_layout, -+ &mck_characteristics, -+ &at91sam9g45_mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91rm9200_master_layout, -+ &mck_characteristics, -+ &at91sam9g45_mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -166,7 +180,7 @@ static void __init at91sam9g45_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 2; i++) { - char name[6]; - -@@ -195,7 +209,7 @@ static void __init at91sam9g45_pmc_setup - for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) { - hw = at91_clk_register_peripheral(regmap, - at91sam9g45_periphck[i].n, -- "masterck", -+ "masterck_div", - at91sam9g45_periphck[i].id); - if (IS_ERR(hw)) - goto err_free; ---- a/drivers/clk/at91/at91sam9n12.c -+++ b/drivers/clk/at91/at91sam9n12.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(at91sam9n12_mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 0, .max = 133333333 }, - .divisors = { 1, 2, 4, 3 }, -@@ -54,12 +56,12 @@ static const struct { - char *p; - u8 id; - } at91sam9n12_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "lcdck", .p = "masterck", .id = 3 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "udpck", .p = "usbck", .id = 7 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "lcdck", .p = "masterck_div", .id = 3 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "udpck", .p = "usbck", .id = 7 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, - }; - - static const struct clk_pcr_layout at91sam9n12_pcr_layout = { -@@ -175,9 +177,21 @@ static void __init at91sam9n12_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "pllbck"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, -+ &at91sam9n12_mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, -+ &at91sam9n12_mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -191,7 +205,7 @@ static void __init at91sam9n12_pmc_setup - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "pllbck"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 2; i++) { - char name[6]; - -@@ -221,7 +235,7 @@ static void __init at91sam9n12_pmc_setup - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &at91sam9n12_pcr_layout, - at91sam9n12_periphck[i].n, -- "masterck", -+ "masterck_div", - at91sam9n12_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) ---- a/drivers/clk/at91/at91sam9rl.c -+++ b/drivers/clk/at91/at91sam9rl.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(sam9rl_mck_lock); -+ - static const struct clk_master_characteristics sam9rl_mck_characteristics = { - .output = { .min = 0, .max = 94000000 }, - .divisors = { 1, 2, 4, 0 }, -@@ -117,9 +119,20 @@ static void __init at91sam9rl_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "pllack"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91rm9200_master_layout, -- &sam9rl_mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91rm9200_master_layout, -+ &sam9rl_mck_characteristics, -+ &sam9rl_mck_lock, CLK_SET_RATE_GATE, -+ INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91rm9200_master_layout, -+ &sam9rl_mck_characteristics, -+ &sam9rl_mck_lock, CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -129,7 +142,7 @@ static void __init at91sam9rl_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "pllack"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 2; i++) { - char name[6]; - -@@ -158,7 +171,7 @@ static void __init at91sam9rl_pmc_setup( - for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) { - hw = at91_clk_register_peripheral(regmap, - at91sam9rl_periphck[i].n, -- "masterck", -+ "masterck_div", - at91sam9rl_periphck[i].id); - if (IS_ERR(hw)) - goto err_free; ---- a/drivers/clk/at91/at91sam9x5.c -+++ b/drivers/clk/at91/at91sam9x5.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 0, .max = 133333333 }, - .divisors = { 1, 2, 4, 3 }, -@@ -41,7 +43,7 @@ static const struct { - char *p; - u8 id; - } at91sam9x5_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, - { .n = "smdck", .p = "smdclk", .id = 4 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "udpck", .p = "usbck", .id = 7 }, -@@ -196,9 +198,19 @@ static void __init at91sam9x5_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -218,7 +230,7 @@ static void __init at91sam9x5_pmc_setup( - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 2; i++) { - char name[6]; - -@@ -245,7 +257,7 @@ static void __init at91sam9x5_pmc_setup( - } - - if (has_lcdck) { -- hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3); -+ hw = at91_clk_register_system(regmap, "lcdck", "masterck_div", 3); - if (IS_ERR(hw)) - goto err_free; - -@@ -256,7 +268,7 @@ static void __init at91sam9x5_pmc_setup( - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &at91sam9x5_pcr_layout, - at91sam9x5_periphck[i].n, -- "masterck", -+ "masterck_div", - at91sam9x5_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) -@@ -269,7 +281,7 @@ static void __init at91sam9x5_pmc_setup( - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &at91sam9x5_pcr_layout, - extra_pcks[i].n, -- "masterck", -+ "masterck_div", - extra_pcks[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -58,83 +58,309 @@ static inline bool clk_master_ready(stru - static int clk_master_prepare(struct clk_hw *hw) - { - struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; -+ -+ spin_lock_irqsave(master->lock, flags); - - while (!clk_master_ready(master)) - cpu_relax(); - -+ spin_unlock_irqrestore(master->lock, flags); -+ - return 0; - } - - static int clk_master_is_prepared(struct clk_hw *hw) - { - struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; -+ bool status; -+ -+ spin_lock_irqsave(master->lock, flags); -+ status = clk_master_ready(master); -+ spin_unlock_irqrestore(master->lock, flags); - -- return clk_master_ready(master); -+ return status; - } - --static unsigned long clk_master_recalc_rate(struct clk_hw *hw, -- unsigned long parent_rate) -+static unsigned long clk_master_div_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) - { -- u8 pres; - u8 div; -- unsigned long rate = parent_rate; -+ unsigned long flags, rate = parent_rate; - struct clk_master *master = to_clk_master(hw); - const struct clk_master_layout *layout = master->layout; - const struct clk_master_characteristics *characteristics = - master->characteristics; - unsigned int mckr; - -+ spin_lock_irqsave(master->lock, flags); - regmap_read(master->regmap, master->layout->offset, &mckr); -+ spin_unlock_irqrestore(master->lock, flags); -+ - mckr &= layout->mask; - -- pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; - div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; - -- if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) -- rate /= 3; -- else -- rate >>= pres; -- - rate /= characteristics->divisors[div]; - - if (rate < characteristics->output.min) -- pr_warn("master clk is underclocked"); -+ pr_warn("master clk div is underclocked"); - else if (rate > characteristics->output.max) -- pr_warn("master clk is overclocked"); -+ pr_warn("master clk div is overclocked"); - - return rate; - } - --static u8 clk_master_get_parent(struct clk_hw *hw) -+static const struct clk_ops master_div_ops = { -+ .prepare = clk_master_prepare, -+ .is_prepared = clk_master_is_prepared, -+ .recalc_rate = clk_master_div_recalc_rate, -+}; -+ -+static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ const struct clk_master_characteristics *characteristics = -+ master->characteristics; -+ unsigned long flags; -+ int div, i; -+ -+ div = DIV_ROUND_CLOSEST(parent_rate, rate); -+ if (div > ARRAY_SIZE(characteristics->divisors)) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { -+ if (!characteristics->divisors[i]) -+ break; -+ -+ if (div == characteristics->divisors[i]) { -+ div = i; -+ break; -+ } -+ } -+ -+ if (i == ARRAY_SIZE(characteristics->divisors)) -+ return -EINVAL; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_update_bits(master->regmap, master->layout->offset, -+ (MASTER_DIV_MASK << MASTER_DIV_SHIFT), -+ (div << MASTER_DIV_SHIFT)); -+ while (!clk_master_ready(master)) -+ cpu_relax(); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ return 0; -+} -+ -+static int clk_master_div_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ const struct clk_master_characteristics *characteristics = -+ master->characteristics; -+ struct clk_hw *parent; -+ unsigned long parent_rate, tmp_rate, best_rate = 0; -+ int i, best_diff = INT_MIN, tmp_diff; -+ -+ parent = clk_hw_get_parent(hw); -+ if (!parent) -+ return -EINVAL; -+ -+ parent_rate = clk_hw_get_rate(parent); -+ if (!parent_rate) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { -+ if (!characteristics->divisors[i]) -+ break; -+ -+ tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate, -+ characteristics->divisors[i]); -+ tmp_diff = abs(tmp_rate - req->rate); -+ -+ if (!best_rate || best_diff > tmp_diff) { -+ best_diff = tmp_diff; -+ best_rate = tmp_rate; -+ } -+ -+ if (!best_diff) -+ break; -+ } -+ -+ req->best_parent_rate = best_rate; -+ req->best_parent_hw = parent; -+ req->rate = best_rate; -+ -+ return 0; -+} -+ -+static const struct clk_ops master_div_ops_chg = { -+ .prepare = clk_master_prepare, -+ .is_prepared = clk_master_is_prepared, -+ .recalc_rate = clk_master_div_recalc_rate, -+ .determine_rate = clk_master_div_determine_rate, -+ .set_rate = clk_master_div_set_rate, -+}; -+ -+static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, -+ struct clk_hw *parent, -+ unsigned long parent_rate, -+ long *best_rate, -+ long *best_diff, -+ u32 div) -+{ -+ unsigned long tmp_rate, tmp_diff; -+ -+ if (div == MASTER_PRES_MAX) -+ tmp_rate = parent_rate / 3; -+ else -+ tmp_rate = parent_rate >> div; -+ -+ tmp_diff = abs(req->rate - tmp_rate); -+ -+ if (*best_diff < 0 || *best_diff >= tmp_diff) { -+ *best_rate = tmp_rate; -+ *best_diff = tmp_diff; -+ req->best_parent_rate = parent_rate; -+ req->best_parent_hw = parent; -+ } -+} -+ -+static int clk_master_pres_determine_rate(struct clk_hw *hw, -+ struct clk_rate_request *req) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ struct clk_rate_request req_parent = *req; -+ const struct clk_master_characteristics *characteristics = -+ master->characteristics; -+ struct clk_hw *parent; -+ long best_rate = LONG_MIN, best_diff = LONG_MIN; -+ u32 pres; -+ int i; -+ -+ if (master->chg_pid < 0) -+ return -EOPNOTSUPP; -+ -+ parent = clk_hw_get_parent_by_index(hw, master->chg_pid); -+ if (!parent) -+ return -EOPNOTSUPP; -+ -+ for (i = 0; i <= MASTER_PRES_MAX; i++) { -+ if (characteristics->have_div3_pres && i == MASTER_PRES_MAX) -+ pres = 3; -+ else -+ pres = 1 << i; -+ -+ req_parent.rate = req->rate * pres; -+ if (__clk_determine_rate(parent, &req_parent)) -+ continue; -+ -+ clk_sama7g5_master_best_diff(req, parent, req_parent.rate, -+ &best_diff, &best_rate, pres); -+ if (!best_diff) -+ break; -+ } -+ -+ return 0; -+} -+ -+static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; -+ unsigned int pres; -+ -+ pres = DIV_ROUND_CLOSEST(parent_rate, rate); -+ if (pres > MASTER_PRES_MAX) -+ return -EINVAL; -+ -+ else if (pres == 3) -+ pres = MASTER_PRES_MAX; -+ else -+ pres = ffs(pres) - 1; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_update_bits(master->regmap, master->layout->offset, -+ (MASTER_PRES_MASK << master->layout->pres_shift), -+ (pres << master->layout->pres_shift)); -+ -+ while (!clk_master_ready(master)) -+ cpu_relax(); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ return 0; -+} -+ -+static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ const struct clk_master_characteristics *characteristics = -+ master->characteristics; -+ unsigned long flags; -+ unsigned int val, pres; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_read(master->regmap, master->layout->offset, &val); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; -+ if (pres == 3 && characteristics->have_div3_pres) -+ pres = 3; -+ else -+ pres = (1 << pres); -+ -+ return DIV_ROUND_CLOSEST_ULL(parent_rate, pres); -+} -+ -+static u8 clk_master_pres_get_parent(struct clk_hw *hw) - { - struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; - unsigned int mckr; - -+ spin_lock_irqsave(master->lock, flags); - regmap_read(master->regmap, master->layout->offset, &mckr); -+ spin_unlock_irqrestore(master->lock, flags); - - return mckr & AT91_PMC_CSS; - } - --static const struct clk_ops master_ops = { -+static const struct clk_ops master_pres_ops = { - .prepare = clk_master_prepare, - .is_prepared = clk_master_is_prepared, -- .recalc_rate = clk_master_recalc_rate, -- .get_parent = clk_master_get_parent, -+ .recalc_rate = clk_master_pres_recalc_rate, -+ .get_parent = clk_master_pres_get_parent, - }; - --struct clk_hw * __init --at91_clk_register_master(struct regmap *regmap, -+static const struct clk_ops master_pres_ops_chg = { -+ .prepare = clk_master_prepare, -+ .is_prepared = clk_master_is_prepared, -+ .determine_rate = clk_master_pres_determine_rate, -+ .recalc_rate = clk_master_pres_recalc_rate, -+ .get_parent = clk_master_pres_get_parent, -+ .set_rate = clk_master_pres_set_rate, -+}; -+ -+static struct clk_hw * __init -+at91_clk_register_master_internal(struct regmap *regmap, - const char *name, int num_parents, - const char **parent_names, - const struct clk_master_layout *layout, -- const struct clk_master_characteristics *characteristics) -+ const struct clk_master_characteristics *characteristics, -+ const struct clk_ops *ops, spinlock_t *lock, u32 flags, -+ int chg_pid) - { - struct clk_master *master; - struct clk_init_data init; - struct clk_hw *hw; - int ret; - -- if (!name || !num_parents || !parent_names) -+ if (!name || !num_parents || !parent_names || !lock) - return ERR_PTR(-EINVAL); - - master = kzalloc(sizeof(*master), GFP_KERNEL); -@@ -142,15 +368,17 @@ at91_clk_register_master(struct regmap * - return ERR_PTR(-ENOMEM); - - init.name = name; -- init.ops = &master_ops; -+ init.ops = ops; - init.parent_names = parent_names; - init.num_parents = num_parents; -- init.flags = 0; -+ init.flags = flags; - - master->hw.init = &init; - master->layout = layout; - master->characteristics = characteristics; - master->regmap = regmap; -+ master->chg_pid = chg_pid; -+ master->lock = lock; - - hw = &master->hw; - ret = clk_hw_register(NULL, &master->hw); -@@ -162,37 +390,54 @@ at91_clk_register_master(struct regmap * - return hw; - } - --static unsigned long --clk_sama7g5_master_recalc_rate(struct clk_hw *hw, -- unsigned long parent_rate) -+struct clk_hw * __init -+at91_clk_register_master_pres(struct regmap *regmap, -+ const char *name, int num_parents, -+ const char **parent_names, -+ const struct clk_master_layout *layout, -+ const struct clk_master_characteristics *characteristics, -+ spinlock_t *lock, u32 flags, int chg_pid) - { -- struct clk_master *master = to_clk_master(hw); -+ const struct clk_ops *ops; - -- return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); -+ if (flags & CLK_SET_RATE_GATE) -+ ops = &master_pres_ops; -+ else -+ ops = &master_pres_ops_chg; -+ -+ return at91_clk_register_master_internal(regmap, name, num_parents, -+ parent_names, layout, -+ characteristics, ops, -+ lock, flags, chg_pid); - } - --static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, -- struct clk_hw *parent, -- unsigned long parent_rate, -- long *best_rate, -- long *best_diff, -- u32 div) -+struct clk_hw * __init -+at91_clk_register_master_div(struct regmap *regmap, -+ const char *name, const char *parent_name, -+ const struct clk_master_layout *layout, -+ const struct clk_master_characteristics *characteristics, -+ spinlock_t *lock, u32 flags) - { -- unsigned long tmp_rate, tmp_diff; -+ const struct clk_ops *ops; - -- if (div == MASTER_PRES_MAX) -- tmp_rate = parent_rate / 3; -+ if (flags & CLK_SET_RATE_GATE) -+ ops = &master_div_ops; - else -- tmp_rate = parent_rate >> div; -+ ops = &master_div_ops_chg; - -- tmp_diff = abs(req->rate - tmp_rate); -+ return at91_clk_register_master_internal(regmap, name, 1, -+ &parent_name, layout, -+ characteristics, ops, -+ lock, flags, -EINVAL); -+} - -- if (*best_diff < 0 || *best_diff >= tmp_diff) { -- *best_rate = tmp_rate; -- *best_diff = tmp_diff; -- req->best_parent_rate = parent_rate; -- req->best_parent_hw = parent; -- } -+static unsigned long -+clk_sama7g5_master_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ -+ return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); - } - - static int clk_sama7g5_master_determine_rate(struct clk_hw *hw, ---- a/drivers/clk/at91/dt-compat.c -+++ b/drivers/clk/at91/dt-compat.c -@@ -24,6 +24,8 @@ - - #define GCK_INDEX_DT_AUDIO_PLL 5 - -+static DEFINE_SPINLOCK(mck_lock); -+ - #ifdef CONFIG_HAVE_AT91_AUDIO_PLL - static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) - { -@@ -388,9 +390,16 @@ of_at91_clk_master_setup(struct device_n - if (IS_ERR(regmap)) - return; - -- hw = at91_clk_register_master(regmap, name, num_parents, -- parent_names, layout, -- characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents, -+ parent_names, layout, -+ characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto out_free_characteristics; -+ -+ hw = at91_clk_register_master_div(regmap, name, "masterck_pres", -+ layout, characteristics, -+ &mck_lock, CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto out_free_characteristics; - ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -155,10 +155,18 @@ at91_clk_register_sam9x5_main(struct reg - const char **parent_names, int num_parents); - - struct clk_hw * __init --at91_clk_register_master(struct regmap *regmap, const char *name, -- int num_parents, const char **parent_names, -- const struct clk_master_layout *layout, -- const struct clk_master_characteristics *characteristics); -+at91_clk_register_master_pres(struct regmap *regmap, const char *name, -+ int num_parents, const char **parent_names, -+ const struct clk_master_layout *layout, -+ const struct clk_master_characteristics *characteristics, -+ spinlock_t *lock, u32 flags, int chg_pid); -+ -+struct clk_hw * __init -+at91_clk_register_master_div(struct regmap *regmap, const char *name, -+ const char *parent_names, -+ const struct clk_master_layout *layout, -+ const struct clk_master_characteristics *characteristics, -+ spinlock_t *lock, u32 flags); - - struct clk_hw * __init - at91_clk_sama7g5_register_master(struct regmap *regmap, ---- a/drivers/clk/at91/sam9x60.c -+++ b/drivers/clk/at91/sam9x60.c -@@ -8,6 +8,7 @@ - #include "pmc.h" - - static DEFINE_SPINLOCK(pmc_pll_lock); -+static DEFINE_SPINLOCK(mck_lock); - - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 140000000, .max = 200000000 }, -@@ -76,11 +77,11 @@ static const struct { - char *p; - u8 id; - } sam9x60_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, - { .n = "uhpck", .p = "usbck", .id = 6 }, - { .n = "pck0", .p = "prog0", .id = 8 }, - { .n = "pck1", .p = "prog1", .id = 9 }, -- { .n = "qspick", .p = "masterck", .id = 19 }, -+ { .n = "qspick", .p = "masterck_div", .id = 19 }, - }; - - static const struct { -@@ -268,9 +269,17 @@ static void __init sam9x60_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = "mainck"; - parent_names[2] = "pllack_divck"; -- hw = at91_clk_register_master(regmap, "masterck", 3, parent_names, -- &sam9x60_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3, -+ parent_names, &sam9x60_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", &sam9x60_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -286,7 +295,7 @@ static void __init sam9x60_pmc_setup(str - parent_names[0] = md_slck_name; - parent_names[1] = td_slck_name; - parent_names[2] = "mainck"; -- parent_names[3] = "masterck"; -+ parent_names[3] = "masterck_div"; - parent_names[4] = "pllack_divck"; - parent_names[5] = "upllck_divck"; - for (i = 0; i < 2; i++) { -@@ -318,7 +327,7 @@ static void __init sam9x60_pmc_setup(str - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &sam9x60_pcr_layout, - sam9x60_periphck[i].n, -- "masterck", -+ "masterck_div", - sam9x60_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) ---- a/drivers/clk/at91/sama5d2.c -+++ b/drivers/clk/at91/sama5d2.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 124000000, .max = 166000000 }, - .divisors = { 1, 2, 4, 3 }, -@@ -40,14 +42,14 @@ static const struct { - char *p; - u8 id; - } sama5d2_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "lcdck", .p = "masterck", .id = 3 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "udpck", .p = "usbck", .id = 7 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -- { .n = "pck2", .p = "prog2", .id = 10 }, -- { .n = "iscck", .p = "masterck", .id = 18 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "lcdck", .p = "masterck_div", .id = 3 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "udpck", .p = "usbck", .id = 7 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "pck2", .p = "prog2", .id = 10 }, -+ { .n = "iscck", .p = "masterck_div", .id = 18 }, - }; - - static const struct { -@@ -235,15 +237,25 @@ static void __init sama5d2_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - - sama5d2_pmc->chws[PMC_MCK] = hw; - -- hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck"); -+ hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); - if (IS_ERR(hw)) - goto err_free; - -@@ -259,7 +271,7 @@ static void __init sama5d2_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - parent_names[5] = "audiopll_pmcck"; - for (i = 0; i < 3; i++) { - char name[6]; -@@ -290,7 +302,7 @@ static void __init sama5d2_pmc_setup(str - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &sama5d2_pcr_layout, - sama5d2_periphck[i].n, -- "masterck", -+ "masterck_div", - sama5d2_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) -@@ -317,7 +329,7 @@ static void __init sama5d2_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - parent_names[5] = "audiopll_pmcck"; - for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) { - hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, ---- a/drivers/clk/at91/sama5d3.c -+++ b/drivers/clk/at91/sama5d3.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 0, .max = 166000000 }, - .divisors = { 1, 2, 4, 3 }, -@@ -40,14 +42,14 @@ static const struct { - char *p; - u8 id; - } sama5d3_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "lcdck", .p = "masterck", .id = 3 }, -- { .n = "smdck", .p = "smdclk", .id = 4 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "udpck", .p = "usbck", .id = 7 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -- { .n = "pck2", .p = "prog2", .id = 10 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "lcdck", .p = "masterck_div", .id = 3 }, -+ { .n = "smdck", .p = "smdclk", .id = 4 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "udpck", .p = "usbck", .id = 7 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "pck2", .p = "prog2", .id = 10 }, - }; - - static const struct { -@@ -170,9 +172,19 @@ static void __init sama5d3_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - -@@ -192,7 +204,7 @@ static void __init sama5d3_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 3; i++) { - char name[6]; - -@@ -222,7 +234,7 @@ static void __init sama5d3_pmc_setup(str - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &sama5d3_pcr_layout, - sama5d3_periphck[i].n, -- "masterck", -+ "masterck_div", - sama5d3_periphck[i].id, - &sama5d3_periphck[i].r, - INT_MIN); ---- a/drivers/clk/at91/sama5d4.c -+++ b/drivers/clk/at91/sama5d4.c -@@ -7,6 +7,8 @@ - - #include "pmc.h" - -+static DEFINE_SPINLOCK(mck_lock); -+ - static const struct clk_master_characteristics mck_characteristics = { - .output = { .min = 125000000, .max = 200000000 }, - .divisors = { 1, 2, 4, 3 }, -@@ -39,14 +41,14 @@ static const struct { - char *p; - u8 id; - } sama5d4_systemck[] = { -- { .n = "ddrck", .p = "masterck", .id = 2 }, -- { .n = "lcdck", .p = "masterck", .id = 3 }, -- { .n = "smdck", .p = "smdclk", .id = 4 }, -- { .n = "uhpck", .p = "usbck", .id = 6 }, -- { .n = "udpck", .p = "usbck", .id = 7 }, -- { .n = "pck0", .p = "prog0", .id = 8 }, -- { .n = "pck1", .p = "prog1", .id = 9 }, -- { .n = "pck2", .p = "prog2", .id = 10 }, -+ { .n = "ddrck", .p = "masterck_div", .id = 2 }, -+ { .n = "lcdck", .p = "masterck_div", .id = 3 }, -+ { .n = "smdck", .p = "smdclk", .id = 4 }, -+ { .n = "uhpck", .p = "usbck", .id = 6 }, -+ { .n = "udpck", .p = "usbck", .id = 7 }, -+ { .n = "pck0", .p = "prog0", .id = 8 }, -+ { .n = "pck1", .p = "prog1", .id = 9 }, -+ { .n = "pck2", .p = "prog2", .id = 10 }, - }; - - static const struct { -@@ -185,15 +187,25 @@ static void __init sama5d4_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, -- &at91sam9x5_master_layout, -- &mck_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, -+ parent_names, -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE, INT_MIN); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "masterck_div", -+ "masterck_pres", -+ &at91sam9x5_master_layout, -+ &mck_characteristics, &mck_lock, -+ CLK_SET_RATE_GATE); - if (IS_ERR(hw)) - goto err_free; - - sama5d4_pmc->chws[PMC_MCK] = hw; - -- hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck"); -+ hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); - if (IS_ERR(hw)) - goto err_free; - -@@ -215,7 +227,7 @@ static void __init sama5d4_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "plladivck"; - parent_names[3] = "utmick"; -- parent_names[4] = "masterck"; -+ parent_names[4] = "masterck_div"; - for (i = 0; i < 3; i++) { - char name[6]; - -@@ -245,7 +257,7 @@ static void __init sama5d4_pmc_setup(str - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, - &sama5d4_pcr_layout, - sama5d4_periphck[i].n, -- "masterck", -+ "masterck_div", - sama5d4_periphck[i].id, - &range, INT_MIN); - if (IS_ERR(hw)) ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -32,6 +32,7 @@ - } while (0) - - static DEFINE_SPINLOCK(pmc_pll_lock); -+static DEFINE_SPINLOCK(pmc_mck0_lock); - static DEFINE_SPINLOCK(pmc_mckX_lock); - - /** -@@ -984,8 +985,16 @@ static void __init sama7g5_pmc_setup(str - parent_names[1] = "mainck"; - parent_names[2] = "cpupll_divpmcck"; - parent_names[3] = "syspll_divpmcck"; -- hw = at91_clk_register_master(regmap, "mck0", 4, parent_names, -- &mck0_layout, &mck0_characteristics); -+ hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, -+ &mck0_layout, &mck0_characteristics, -+ &pmc_mck0_lock, -+ CLK_SET_RATE_PARENT, 0); -+ if (IS_ERR(hw)) -+ goto err_free; -+ -+ hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", -+ &mck0_layout, &mck0_characteristics, -+ &pmc_mck0_lock, 0); - if (IS_ERR(hw)) - goto err_free; - diff --git a/target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch b/target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch deleted file mode 100644 index dc55e32027..0000000000 --- a/target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 36e97c421dd9f866e31fe14bcb7af01334791890 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 19 Nov 2020 17:43:17 +0200 -Subject: [PATCH 111/247] clk: at91: sama7g5: register cpu clock - -Register CPU clock as being the master clock prescaler. This would -be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider -between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the -frequencies supported by SAMA7G5 could be directly received from -CPUPLL + master clock prescaler and the extra divider would do no work in -case it would be enabled. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 13 ++++++------- - include/dt-bindings/clock/at91.h | 1 + - 2 files changed, 7 insertions(+), 7 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(str - if (IS_ERR(regmap)) - return; - -- sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, -+ sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1, - nck(sama7g5_systemck), - nck(sama7g5_periphck), - nck(sama7g5_gck), 8); -@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(str - } - } - -- parent_names[0] = md_slck_name; -- parent_names[1] = "mainck"; -- parent_names[2] = "cpupll_divpmcck"; -- parent_names[3] = "syspll_divpmcck"; -- hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names, -+ parent_names[0] = "cpupll_divpmcck"; -+ hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, - &mck0_layout, &mck0_characteristics, - &pmc_mck0_lock, - CLK_SET_RATE_PARENT, 0); - if (IS_ERR(hw)) - goto err_free; - -- hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres", -+ sama7g5_pmc->chws[PMC_CPU] = hw; -+ -+ hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", - &mck0_layout, &mck0_characteristics, - &pmc_mck0_lock, 0); - if (IS_ERR(hw)) ---- a/include/dt-bindings/clock/at91.h -+++ b/include/dt-bindings/clock/at91.h -@@ -34,6 +34,7 @@ - #define PMC_AUDIOPMCPLL (PMC_MAIN + 6) - #define PMC_AUDIOIOPLL (PMC_MAIN + 7) - #define PMC_ETHPLL (PMC_MAIN + 8) -+#define PMC_CPU (PMC_MAIN + 9) - - #ifndef AT91_PMC_MOSCS - #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ diff --git a/target/linux/at91/patches-5.10/112-clk-at91-Fix-the-declaration-of-the-clocks.patch b/target/linux/at91/patches-5.10/112-clk-at91-Fix-the-declaration-of-the-clocks.patch deleted file mode 100644 index e989ed207e..0000000000 --- a/target/linux/at91/patches-5.10/112-clk-at91-Fix-the-declaration-of-the-clocks.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 5a25e2437af0db535b17da352fb16680a8dfdeda Mon Sep 17 00:00:00 2001 -From: Tudor Ambarus -Date: Wed, 3 Feb 2021 17:43:32 +0200 -Subject: [PATCH 112/247] clk: at91: Fix the declaration of the clocks - -These are all "early clocks" that require initialization just at -of_clk_init() time. Use CLK_OF_DECLARE() to declare them. - -This also fixes a problem that was spotted when fw_devlink was -set to 'on' by default: the boards failed to boot. The reason is -that CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes -the consumers of the clock to be postponed by fw_devlink until -the second initialization routine of the clock has been completed. -One of the consumers of the clock is the timer, which is used as a -clocksource, and needs the clock initialized early. Postponing the -timers caused the fail at boot. - -Signed-off-by: Tudor Ambarus -Link: https://lore.kernel.org/r/20210203154332.470587-1-tudor.ambarus@microchip.com -Acked-by: Saravana Kannan -Tested-by: Eugen Hristev -Acked-by: Nicolas Ferre -Reviewed-by: Claudiu Beznea -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/at91rm9200.c | 3 +-- - drivers/clk/at91/at91sam9260.c | 16 ++++++++-------- - drivers/clk/at91/at91sam9g45.c | 3 +-- - drivers/clk/at91/at91sam9n12.c | 3 +-- - drivers/clk/at91/at91sam9rl.c | 3 ++- - drivers/clk/at91/at91sam9x5.c | 20 ++++++++++---------- - drivers/clk/at91/sama5d2.c | 3 ++- - drivers/clk/at91/sama5d3.c | 2 +- - drivers/clk/at91/sama5d4.c | 3 ++- - 9 files changed, 28 insertions(+), 28 deletions(-) - ---- a/drivers/clk/at91/at91rm9200.c -+++ b/drivers/clk/at91/at91rm9200.c -@@ -215,5 +215,4 @@ err_free: - * deferring properly. Once this is fixed, this can be switched to a platform - * driver. - */ --CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, "atmel,at91rm9200-pmc", -- at91rm9200_pmc_setup); -+CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup); ---- a/drivers/clk/at91/at91sam9260.c -+++ b/drivers/clk/at91/at91sam9260.c -@@ -491,26 +491,26 @@ static void __init at91sam9260_pmc_setup - { - at91sam926x_pmc_setup(np, &at91sam9260_data); - } --CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, "atmel,at91sam9260-pmc", -- at91sam9260_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup); - - static void __init at91sam9261_pmc_setup(struct device_node *np) - { - at91sam926x_pmc_setup(np, &at91sam9261_data); - } --CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, "atmel,at91sam9261-pmc", -- at91sam9261_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup); - - static void __init at91sam9263_pmc_setup(struct device_node *np) - { - at91sam926x_pmc_setup(np, &at91sam9263_data); - } --CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, "atmel,at91sam9263-pmc", -- at91sam9263_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup); - - static void __init at91sam9g20_pmc_setup(struct device_node *np) - { - at91sam926x_pmc_setup(np, &at91sam9g20_data); - } --CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", -- at91sam9g20_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup); ---- a/drivers/clk/at91/at91sam9g45.c -+++ b/drivers/clk/at91/at91sam9g45.c -@@ -228,5 +228,4 @@ err_free: - * The TCB is used as the clocksource so its clock is needed early. This means - * this can't be a platform driver. - */ --CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", -- at91sam9g45_pmc_setup); -+CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup); ---- a/drivers/clk/at91/at91sam9n12.c -+++ b/drivers/clk/at91/at91sam9n12.c -@@ -255,5 +255,4 @@ err_free: - * The TCB is used as the clocksource so its clock is needed early. This means - * this can't be a platform driver. - */ --CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", -- at91sam9n12_pmc_setup); -+CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup); ---- a/drivers/clk/at91/at91sam9rl.c -+++ b/drivers/clk/at91/at91sam9rl.c -@@ -186,4 +186,5 @@ static void __init at91sam9rl_pmc_setup( - err_free: - kfree(at91sam9rl_pmc); - } --CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup); ---- a/drivers/clk/at91/at91sam9x5.c -+++ b/drivers/clk/at91/at91sam9x5.c -@@ -302,33 +302,33 @@ static void __init at91sam9g15_pmc_setup - { - at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true); - } --CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", -- at91sam9g15_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup); - - static void __init at91sam9g25_pmc_setup(struct device_node *np) - { - at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false); - } --CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", -- at91sam9g25_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup); - - static void __init at91sam9g35_pmc_setup(struct device_node *np) - { - at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true); - } --CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", -- at91sam9g35_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup); - - static void __init at91sam9x25_pmc_setup(struct device_node *np) - { - at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false); - } --CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", -- at91sam9x25_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup); - - static void __init at91sam9x35_pmc_setup(struct device_node *np) - { - at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true); - } --CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", -- at91sam9x35_pmc_setup); -+ -+CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup); ---- a/drivers/clk/at91/sama5d2.c -+++ b/drivers/clk/at91/sama5d2.c -@@ -372,4 +372,5 @@ static void __init sama5d2_pmc_setup(str - err_free: - kfree(sama5d2_pmc); - } --CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup); -+ -+CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup); ---- a/drivers/clk/at91/sama5d3.c -+++ b/drivers/clk/at91/sama5d3.c -@@ -255,4 +255,4 @@ err_free: - * The TCB is used as the clocksource so its clock is needed early. This means - * this can't be a platform driver. - */ --CLK_OF_DECLARE_DRIVER(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup); -+CLK_OF_DECLARE(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup); ---- a/drivers/clk/at91/sama5d4.c -+++ b/drivers/clk/at91/sama5d4.c -@@ -286,4 +286,5 @@ static void __init sama5d4_pmc_setup(str - err_free: - kfree(sama5d4_pmc); - } --CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup); -+ -+CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup); diff --git a/target/linux/at91/patches-5.10/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch b/target/linux/at91/patches-5.10/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch deleted file mode 100644 index f3ebee10fe..0000000000 --- a/target/linux/at91/patches-5.10/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 268b36c42b7d1e480dd56ecfec626a46f4b5975e Mon Sep 17 00:00:00 2001 -From: Bhaskar Chowdhury -Date: Sat, 13 Mar 2021 11:02:22 +0530 -Subject: [PATCH 113/247] clk: at91: Trivial typo fixes in the file sama7g5.c - -s/critial/critical/ ......two different places -s/parrent/parent/ - -Signed-off-by: Bhaskar Chowdhury -Link: https://lore.kernel.org/r/20210313053222.14706-1-unixbhaskar@gmail.com -Acked-by: Randy Dunlap -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -166,7 +166,7 @@ static const struct { - .c = &pll_characteristics, - .t = PLL_TYPE_FRAC, - /* -- * This feeds syspll_divpmcck which may feed critial parts -+ * This feeds syspll_divpmcck which may feed critical parts - * of the systems like timers. Therefore it should not be - * disabled. - */ -@@ -178,7 +178,7 @@ static const struct { - .c = &pll_characteristics, - .t = PLL_TYPE_DIV, - /* -- * This may feed critial parts of the systems like timers. -+ * This may feed critical parts of the systems like timers. - * Therefore it should not be disabled. - */ - .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, -@@ -455,7 +455,7 @@ static const struct { - * @pp: PLL parents - * @pp_mux_table: PLL parents mux table - * @r: clock output range -- * @pp_chg_id: id in parrent array of changeable PLL parent -+ * @pp_chg_id: id in parent array of changeable PLL parent - * @pp_count: PLL parents count - * @id: clock id - */ diff --git a/target/linux/at91/patches-5.10/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch b/target/linux/at91/patches-5.10/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch deleted file mode 100644 index a9ceda533b..0000000000 --- a/target/linux/at91/patches-5.10/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 9997227090cf529675aeb775585ec9f6c2f0f131 Mon Sep 17 00:00:00 2001 -From: Randy Dunlap -Date: Thu, 19 Aug 2021 15:32:37 -0700 -Subject: [PATCH 114/247] clk: at91: sama7g5: remove all kernel-doc & - kernel-doc warnings - -Remove all "/**" kernel-doc markers from sama7g5.c since they are -all internal to this driver source file only. -This eliminates 14 warnings that were reported by the kernel test robot. - -Signed-off-by: Randy Dunlap -Reported-by: kernel test robot -Cc: Claudiu Beznea -Cc: Michael Turquette -Cc: Stephen Boyd -Cc: Eugen Hristev -Cc: linux-clk@vger.kernel.org -Cc: linux-arm-kernel@lists.infradead.org -Link: https://lore.kernel.org/r/20210819223237.20115-1-rdunlap@infradead.org -Reviewed-by: Claudiu Beznea -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -35,7 +35,7 @@ static DEFINE_SPINLOCK(pmc_pll_lock); - static DEFINE_SPINLOCK(pmc_mck0_lock); - static DEFINE_SPINLOCK(pmc_mckX_lock); - --/** -+/* - * PLL clocks identifiers - * @PLL_ID_CPU: CPU PLL identifier - * @PLL_ID_SYS: System PLL identifier -@@ -56,7 +56,7 @@ enum pll_ids { - PLL_ID_MAX, - }; - --/** -+/* - * PLL type identifiers - * @PLL_TYPE_FRAC: fractional PLL identifier - * @PLL_TYPE_DIV: divider PLL identifier -@@ -118,7 +118,7 @@ static const struct clk_pll_characterist - .output = pll_outputs, - }; - --/** -+/* - * PLL clocks description - * @n: clock name - * @p: clock parent -@@ -285,7 +285,7 @@ static const struct { - }, - }; - --/** -+/* - * Master clock (MCK[1..4]) description - * @n: clock name - * @ep: extra parents names array -@@ -337,7 +337,7 @@ static const struct { - .c = 1, }, - }; - --/** -+/* - * System clock description - * @n: clock name - * @p: clock parent name -@@ -361,7 +361,7 @@ static const struct { - /* Mux table for programmable clocks. */ - static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; - --/** -+/* - * Peripheral clock description - * @n: clock name - * @p: clock parent name -@@ -449,7 +449,7 @@ static const struct { - { .n = "uhphs_clk", .p = "mck1", .id = 106, }, - }; - --/** -+/* - * Generic clock description - * @n: clock name - * @pp: PLL parents diff --git a/target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch b/target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch deleted file mode 100644 index e474590053..0000000000 --- a/target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch +++ /dev/null @@ -1,179 +0,0 @@ -From 89f37ac2780d113d3c17d329726c0e92a1400744 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:32 +0200 -Subject: [PATCH 115/247] net: macb: add userio bits as platform configuration - -This is necessary for SAMA7G5 as it uses different values for -PHY interface and also introduces hdfctlen bit. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb.h | 10 +++++++++ - drivers/net/ethernet/cadence/macb_main.c | 28 ++++++++++++++++++++---- - 2 files changed, 34 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb.h -+++ b/drivers/net/ethernet/cadence/macb.h -@@ -1104,6 +1104,14 @@ struct macb_pm_data { - u32 usrio; - }; - -+struct macb_usrio_config { -+ u32 mii; -+ u32 rmii; -+ u32 rgmii; -+ u32 refclk; -+ u32 hdfctlen; -+}; -+ - struct macb_config { - u32 caps; - unsigned int dma_burst_length; -@@ -1112,6 +1120,7 @@ struct macb_config { - struct clk **rx_clk, struct clk **tsu_clk); - int (*init)(struct platform_device *pdev); - int jumbo_max_len; -+ const struct macb_usrio_config *usrio; - }; - - struct tsu_incr { -@@ -1244,6 +1253,7 @@ struct macb { - u32 rx_intr_mask; - - struct macb_pm_data pm_data; -+ const struct macb_usrio_config *usrio; - }; - - #ifdef CONFIG_MACB_USE_HWSTAMP ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -3828,15 +3828,15 @@ static int macb_init(struct platform_dev - if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { - val = 0; - if (phy_interface_mode_is_rgmii(bp->phy_interface)) -- val = GEM_BIT(RGMII); -+ val = bp->usrio->rgmii; - else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && - (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) -- val = MACB_BIT(RMII); -+ val = bp->usrio->rmii; - else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) -- val = MACB_BIT(MII); -+ val = bp->usrio->mii; - - if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) -- val |= MACB_BIT(CLKEN); -+ val |= bp->usrio->refclk; - - macb_or_gem_writel(bp, USRIO, val); - } -@@ -4354,6 +4354,13 @@ static int fu540_c000_init(struct platfo - return macb_init(pdev); - } - -+static const struct macb_usrio_config macb_default_usrio = { -+ .mii = MACB_BIT(MII), -+ .rmii = MACB_BIT(RMII), -+ .rgmii = GEM_BIT(RGMII), -+ .refclk = MACB_BIT(CLKEN), -+}; -+ - static const struct macb_config fu540_c000_config = { - .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | - MACB_CAPS_GEM_HAS_PTP, -@@ -4361,12 +4368,14 @@ static const struct macb_config fu540_c0 - .clk_init = fu540_c000_clk_init, - .init = fu540_c000_init, - .jumbo_max_len = 10240, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config at91sam9260_config = { - .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config sama5d3macb_config = { -@@ -4374,6 +4383,7 @@ static const struct macb_config sama5d3m - | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config pc302gem_config = { -@@ -4381,6 +4391,7 @@ static const struct macb_config pc302gem - .dma_burst_length = 16, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config sama5d2_config = { -@@ -4388,6 +4399,7 @@ static const struct macb_config sama5d2_ - .dma_burst_length = 16, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config sama5d3_config = { -@@ -4397,6 +4409,7 @@ static const struct macb_config sama5d3_ - .clk_init = macb_clk_init, - .init = macb_init, - .jumbo_max_len = 10240, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config sama5d4_config = { -@@ -4404,18 +4417,21 @@ static const struct macb_config sama5d4_ - .dma_burst_length = 4, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config emac_config = { - .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC, - .clk_init = at91ether_clk_init, - .init = at91ether_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config np4_config = { - .caps = MACB_CAPS_USRIO_DISABLED, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config zynqmp_config = { -@@ -4426,6 +4442,7 @@ static const struct macb_config zynqmp_c - .clk_init = macb_clk_init, - .init = macb_init, - .jumbo_max_len = 10240, -+ .usrio = &macb_default_usrio, - }; - - static const struct macb_config zynq_config = { -@@ -4434,6 +4451,7 @@ static const struct macb_config zynq_con - .dma_burst_length = 16, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - }; - - static const struct of_device_id macb_dt_ids[] = { -@@ -4554,6 +4572,8 @@ static int macb_probe(struct platform_de - bp->wol |= MACB_WOL_HAS_MAGIC_PACKET; - device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET); - -+ bp->usrio = macb_config->usrio; -+ - spin_lock_init(&bp->lock); - - /* setup capabilities */ diff --git a/target/linux/at91/patches-5.10/116-net-macb-add-capability-to-not-set-the-clock-rate.patch b/target/linux/at91/patches-5.10/116-net-macb-add-capability-to-not-set-the-clock-rate.patch deleted file mode 100644 index 87dde7ef60..0000000000 --- a/target/linux/at91/patches-5.10/116-net-macb-add-capability-to-not-set-the-clock-rate.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 1b15259551b701f416aa024050a2e619860bd0d8 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:33 +0200 -Subject: [PATCH 116/247] net: macb: add capability to not set the clock rate - -SAMA7G5's ethernet IPs TX clock could be provided by its generic clock or -by the external clock provided by the PHY. The internal IP logic divides -properly this clock depending on the link speed. The patch adds a new -capability so that macb_set_tx_clock() to not be called for IPs having -this capability (the clock rate, in case of generic clock, is set at the -boot time via device tree and the driver only enables it). - -Signed-off-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb.h | 1 + - drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++--------- - 2 files changed, 10 insertions(+), 9 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb.h -+++ b/drivers/net/ethernet/cadence/macb.h -@@ -658,6 +658,7 @@ - #define MACB_CAPS_GEM_HAS_PTP 0x00000040 - #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 - #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 -+#define MACB_CAPS_CLK_HW_CHG 0x04000000 - #define MACB_CAPS_MACB_IS_EMAC 0x08000000 - #define MACB_CAPS_FIFO_MODE 0x10000000 - #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -457,15 +457,14 @@ static void macb_init_buffers(struct mac - - /** - * macb_set_tx_clk() - Set a clock to a new frequency -- * @clk: Pointer to the clock to change -+ * @bp: pointer to struct macb - * @speed: New frequency in Hz -- * @dev: Pointer to the struct net_device - */ --static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev) -+static void macb_set_tx_clk(struct macb *bp, int speed) - { - long ferr, rate, rate_rounded; - -- if (!clk) -+ if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) - return; - - switch (speed) { -@@ -482,7 +481,7 @@ static void macb_set_tx_clk(struct clk * - return; - } - -- rate_rounded = clk_round_rate(clk, rate); -+ rate_rounded = clk_round_rate(bp->tx_clk, rate); - if (rate_rounded < 0) - return; - -@@ -492,11 +491,12 @@ static void macb_set_tx_clk(struct clk * - ferr = abs(rate_rounded - rate); - ferr = DIV_ROUND_UP(ferr, rate / 100000); - if (ferr > 5) -- netdev_warn(dev, "unable to generate target frequency: %ld Hz\n", -+ netdev_warn(bp->dev, -+ "unable to generate target frequency: %ld Hz\n", - rate); - -- if (clk_set_rate(clk, rate_rounded)) -- netdev_err(dev, "adjusting tx_clk failed.\n"); -+ if (clk_set_rate(bp->tx_clk, rate_rounded)) -+ netdev_err(bp->dev, "adjusting tx_clk failed.\n"); - } - - static void macb_validate(struct phylink_config *config, -@@ -649,7 +649,7 @@ static void macb_mac_link_up(struct phyl - if (rx_pause) - ctrl |= MACB_BIT(PAE); - -- macb_set_tx_clk(bp->tx_clk, speed, ndev); -+ macb_set_tx_clk(bp, speed); - - /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down - * cleared the pipeline and control registers. diff --git a/target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch b/target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch deleted file mode 100644 index 337343340c..0000000000 --- a/target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 935d9aae15ee245a1bc6e322cbef02566a8996cc Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:34 +0200 -Subject: [PATCH 117/247] net: macb: add function to disable all macb clocks - -Add function to disable all macb clocks. - -Signed-off-by: Claudiu Beznea -Suggested-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 38 +++++++++++++----------- - 1 file changed, 21 insertions(+), 17 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -3603,6 +3603,20 @@ static void macb_probe_queues(void __iom - *num_queues = hweight32(*queue_mask); - } - -+static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk, -+ struct clk *rx_clk, struct clk *tsu_clk) -+{ -+ struct clk_bulk_data clks[] = { -+ { .clk = tsu_clk, }, -+ { .clk = rx_clk, }, -+ { .clk = pclk, }, -+ { .clk = hclk, }, -+ { .clk = tx_clk }, -+ }; -+ -+ clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks); -+} -+ - static int macb_clk_init(struct platform_device *pdev, struct clk **pclk, - struct clk **hclk, struct clk **tx_clk, - struct clk **rx_clk, struct clk **tsu_clk) -@@ -4665,11 +4679,7 @@ err_out_free_netdev: - free_netdev(dev); - - err_disable_clocks: -- clk_disable_unprepare(tx_clk); -- clk_disable_unprepare(hclk); -- clk_disable_unprepare(pclk); -- clk_disable_unprepare(rx_clk); -- clk_disable_unprepare(tsu_clk); -+ macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk); - pm_runtime_disable(&pdev->dev); - pm_runtime_set_suspended(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); -@@ -4694,11 +4704,8 @@ static int macb_remove(struct platform_d - pm_runtime_disable(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); - if (!pm_runtime_suspended(&pdev->dev)) { -- clk_disable_unprepare(bp->tx_clk); -- clk_disable_unprepare(bp->hclk); -- clk_disable_unprepare(bp->pclk); -- clk_disable_unprepare(bp->rx_clk); -- clk_disable_unprepare(bp->tsu_clk); -+ macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, -+ bp->rx_clk, bp->tsu_clk); - pm_runtime_set_suspended(&pdev->dev); - } - phylink_destroy(bp->phylink); -@@ -4877,13 +4884,10 @@ static int __maybe_unused macb_runtime_s - struct net_device *netdev = dev_get_drvdata(dev); - struct macb *bp = netdev_priv(netdev); - -- if (!(device_may_wakeup(dev))) { -- clk_disable_unprepare(bp->tx_clk); -- clk_disable_unprepare(bp->hclk); -- clk_disable_unprepare(bp->pclk); -- clk_disable_unprepare(bp->rx_clk); -- } -- clk_disable_unprepare(bp->tsu_clk); -+ if (!(device_may_wakeup(dev))) -+ macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk); -+ else -+ macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk); - - return 0; - } diff --git a/target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch b/target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch deleted file mode 100644 index c66d334f3a..0000000000 --- a/target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 9692c07ee8bf8f68b74d553d861d092e33264781 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:35 +0200 -Subject: [PATCH 118/247] net: macb: unprepare clocks in case of failure - -Unprepare clocks in case of any failure in fu540_c000_clk_init(). - -Fixes: c218ad559020 ("macb: Add support for SiFive FU540-C000") -Signed-off-by: Claudiu Beznea -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 24 ++++++++++++++++++------ - 1 file changed, 18 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4335,8 +4335,10 @@ static int fu540_c000_clk_init(struct pl - return err; - - mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL); -- if (!mgmt) -- return -ENOMEM; -+ if (!mgmt) { -+ err = -ENOMEM; -+ goto err_disable_clks; -+ } - - init.name = "sifive-gemgxl-mgmt"; - init.ops = &fu540_c000_ops; -@@ -4347,16 +4349,26 @@ static int fu540_c000_clk_init(struct pl - mgmt->hw.init = &init; - - *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw); -- if (IS_ERR(*tx_clk)) -- return PTR_ERR(*tx_clk); -+ if (IS_ERR(*tx_clk)) { -+ err = PTR_ERR(*tx_clk); -+ goto err_disable_clks; -+ } - - err = clk_prepare_enable(*tx_clk); -- if (err) -+ if (err) { - dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); -- else -+ *tx_clk = NULL; -+ goto err_disable_clks; -+ } else { - dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name); -+ } - - return 0; -+ -+err_disable_clks: -+ macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk); -+ -+ return err; - } - - static int fu540_c000_init(struct platform_device *pdev) diff --git a/target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch b/target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch deleted file mode 100644 index 78a222e657..0000000000 --- a/target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 0085cd8576ceeaddeedf973b939b41ba96e3f77c Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:38 +0200 -Subject: [PATCH 119/247] net: macb: add support for sama7g5 gem interface - -Add support for SAMA7G5 gigabit ethernet interface. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4387,6 +4387,14 @@ static const struct macb_usrio_config ma - .refclk = MACB_BIT(CLKEN), - }; - -+static const struct macb_usrio_config sama7g5_usrio = { -+ .mii = 0, -+ .rmii = 1, -+ .rgmii = 2, -+ .refclk = BIT(2), -+ .hdfctlen = BIT(6), -+}; -+ - static const struct macb_config fu540_c000_config = { - .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO | - MACB_CAPS_GEM_HAS_PTP, -@@ -4480,6 +4488,14 @@ static const struct macb_config zynq_con - .usrio = &macb_default_usrio, - }; - -+static const struct macb_config sama7g5_gem_config = { -+ .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG, -+ .dma_burst_length = 16, -+ .clk_init = macb_clk_init, -+ .init = macb_init, -+ .usrio = &sama7g5_usrio, -+}; -+ - static const struct of_device_id macb_dt_ids[] = { - { .compatible = "cdns,at32ap7000-macb" }, - { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, -@@ -4497,6 +4513,7 @@ static const struct of_device_id macb_dt - { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, - { .compatible = "cdns,zynq-gem", .data = &zynq_config }, - { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, -+ { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, macb_dt_ids); diff --git a/target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch b/target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch deleted file mode 100644 index 5711add940..0000000000 --- a/target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch +++ /dev/null @@ -1,39 +0,0 @@ -From a42f90357cfcfcf5cdade4594ad79a1eae633a9f Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 9 Dec 2020 15:03:39 +0200 -Subject: [PATCH 120/247] net: macb: add support for sama7g5 emac interface - -Add support for SAMA7G5 10/100Mbps interface. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4496,6 +4496,14 @@ static const struct macb_config sama7g5_ - .usrio = &sama7g5_usrio, - }; - -+static const struct macb_config sama7g5_emac_config = { -+ .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_USRIO_HAS_CLKEN, -+ .dma_burst_length = 16, -+ .clk_init = macb_clk_init, -+ .init = macb_init, -+ .usrio = &sama7g5_usrio, -+}; -+ - static const struct of_device_id macb_dt_ids[] = { - { .compatible = "cdns,at32ap7000-macb" }, - { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config }, -@@ -4514,6 +4522,7 @@ static const struct of_device_id macb_dt - { .compatible = "cdns,zynq-gem", .data = &zynq_config }, - { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config }, - { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config }, -+ { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, macb_dt_ids); diff --git a/target/linux/at91/patches-5.10/121-ASoC-pcm5102a-Make-codec-selectable.patch b/target/linux/at91/patches-5.10/121-ASoC-pcm5102a-Make-codec-selectable.patch deleted file mode 100644 index 8c918fd779..0000000000 --- a/target/linux/at91/patches-5.10/121-ASoC-pcm5102a-Make-codec-selectable.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 5ac0e1f5577b266543756521b1a749003b0f3686 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 12 Oct 2020 17:19:11 +0300 -Subject: [PATCH 121/247] ASoC: pcm5102a: Make codec selectable - -The TI PCM5102A codec driver can be used with the generic sound card -drivers, so it should be selectable. For example, with the addition -of #sound-dai-cells = <0> property in DT, it can be used with simple/graph -card drivers. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20201012141911.3150996-1-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/codecs/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/sound/soc/codecs/Kconfig -+++ b/sound/soc/codecs/Kconfig -@@ -1007,7 +1007,7 @@ config SND_SOC_PCM3168A_SPI - select REGMAP_SPI - - config SND_SOC_PCM5102A -- tristate -+ tristate "Texas Instruments PCM5102A CODEC" - - config SND_SOC_PCM512x - tristate diff --git a/target/linux/at91/patches-5.10/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch b/target/linux/at91/patches-5.10/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch deleted file mode 100644 index 978b68184e..0000000000 --- a/target/linux/at91/patches-5.10/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f4389949bf422fe04775c17b833100fa0e95ea68 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Tue, 3 Nov 2020 12:05:54 +0200 -Subject: [PATCH 122/247] ASoC: atmel-i2s: do not warn if muxclk is missing - -Besides the fact that muxclk is optional, muxclk can be set using -assigned-clocks, removing the need to set it in driver. The warning is -thus unneeded, so we can transform it in a debug print, eventually to just -reflect that muxclk was not set by the driver. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20201103100554.1307190-1-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-i2s.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/sound/soc/atmel/atmel-i2s.c -+++ b/sound/soc/atmel/atmel-i2s.c -@@ -581,8 +581,8 @@ static int atmel_i2s_sama5d2_mck_init(st - err = PTR_ERR(muxclk); - if (err == -EPROBE_DEFER) - return -EPROBE_DEFER; -- dev_warn(dev->dev, -- "failed to get the I2S clock control: %d\n", err); -+ dev_dbg(dev->dev, -+ "failed to get the I2S clock control: %d\n", err); - return 0; - } - diff --git a/target/linux/at91/patches-5.10/123-regulator-mcp16502-add-linear_min_sel.patch b/target/linux/at91/patches-5.10/123-regulator-mcp16502-add-linear_min_sel.patch deleted file mode 100644 index ce97be4b77..0000000000 --- a/target/linux/at91/patches-5.10/123-regulator-mcp16502-add-linear_min_sel.patch +++ /dev/null @@ -1,25 +0,0 @@ -From f5a73f3bb600b96b6149f2115360e1d0d51fbac4 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:07 +0200 -Subject: [PATCH 123/247] regulator: mcp16502: add linear_min_sel - -Selectors b/w zero and VDD_LOW_SEL are not valid. Use linear_min_sel. - -Fixes: 919261c03e7ca ("regulator: mcp16502: add regulator driver for MCP16502") -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-4-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -93,6 +93,7 @@ static unsigned int mcp16502_of_map_mode - .owner = THIS_MODULE, \ - .n_voltages = MCP16502_VSEL + 1, \ - .linear_ranges = _ranges, \ -+ .linear_min_sel = VDD_LOW_SEL, \ - .n_linear_ranges = ARRAY_SIZE(_ranges), \ - .of_match = of_match_ptr(_name), \ - .of_map_mode = mcp16502_of_map_mode, \ diff --git a/target/linux/at91/patches-5.10/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch b/target/linux/at91/patches-5.10/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch deleted file mode 100644 index f371266c78..0000000000 --- a/target/linux/at91/patches-5.10/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 5295f4c122258a11fb6012b7e043248e681db5a2 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:08 +0200 -Subject: [PATCH 124/247] regulator: mcp16502: adapt for get/set on other - registers - -MCP16502 have multiple registers for each regulator (as described -in enum mcp16502_reg). Adapt the code to be able to get/set all these -registers. This is necessary for the following commits. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-5-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 43 ++++++++++++++++++++++-------------- - 1 file changed, 27 insertions(+), 16 deletions(-) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -54,13 +54,9 @@ - * This function is useful for iterating over all regulators and accessing their - * registers in a generic way or accessing a regulator device by its id. - */ --#define MCP16502_BASE(i) (((i) + 1) << 4) -+#define MCP16502_REG_BASE(i, r) ((((i) + 1) << 4) + MCP16502_REG_##r) - #define MCP16502_STAT_BASE(i) ((i) + 5) - --#define MCP16502_OFFSET_MODE_A 0 --#define MCP16502_OFFSET_MODE_LPM 1 --#define MCP16502_OFFSET_MODE_HIB 2 -- - #define MCP16502_OPMODE_ACTIVE REGULATOR_MODE_NORMAL - #define MCP16502_OPMODE_LPM REGULATOR_MODE_IDLE - #define MCP16502_OPMODE_HIB REGULATOR_MODE_STANDBY -@@ -75,6 +71,23 @@ - #define MCP16502_MIN_REG 0x0 - #define MCP16502_MAX_REG 0x65 - -+/** -+ * enum mcp16502_reg - MCP16502 regulators's registers -+ * @MCP16502_REG_A: active state register -+ * @MCP16502_REG_LPM: low power mode state register -+ * @MCP16502_REG_HIB: hibernate state register -+ * @MCP16502_REG_SEQ: startup sequence register -+ * @MCP16502_REG_CFG: configuration register -+ */ -+enum mcp16502_reg { -+ MCP16502_REG_A, -+ MCP16502_REG_LPM, -+ MCP16502_REG_HIB, -+ MCP16502_REG_HPM, -+ MCP16502_REG_SEQ, -+ MCP16502_REG_CFG, -+}; -+ - static unsigned int mcp16502_of_map_mode(unsigned int mode) - { - if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE) -@@ -144,22 +157,20 @@ static void mcp16502_gpio_set_mode(struc - } - - /* -- * mcp16502_get_reg() - get the PMIC's configuration register for opmode -+ * mcp16502_get_reg() - get the PMIC's state configuration register for opmode - * - * @rdev: the regulator whose register we are searching - * @opmode: the PMIC's operating mode ACTIVE, Low-power, Hibernate - */ --static int mcp16502_get_reg(struct regulator_dev *rdev, int opmode) -+static int mcp16502_get_state_reg(struct regulator_dev *rdev, int opmode) - { -- int reg = MCP16502_BASE(rdev_get_id(rdev)); -- - switch (opmode) { - case MCP16502_OPMODE_ACTIVE: -- return reg + MCP16502_OFFSET_MODE_A; -+ return MCP16502_REG_BASE(rdev_get_id(rdev), A); - case MCP16502_OPMODE_LPM: -- return reg + MCP16502_OFFSET_MODE_LPM; -+ return MCP16502_REG_BASE(rdev_get_id(rdev), LPM); - case MCP16502_OPMODE_HIB: -- return reg + MCP16502_OFFSET_MODE_HIB; -+ return MCP16502_REG_BASE(rdev_get_id(rdev), HIB); - default: - return -EINVAL; - } -@@ -179,7 +190,7 @@ static unsigned int mcp16502_get_mode(st - unsigned int val; - int ret, reg; - -- reg = mcp16502_get_reg(rdev, MCP16502_OPMODE_ACTIVE); -+ reg = mcp16502_get_state_reg(rdev, MCP16502_OPMODE_ACTIVE); - if (reg < 0) - return reg; - -@@ -210,7 +221,7 @@ static int _mcp16502_set_mode(struct reg - int val; - int reg; - -- reg = mcp16502_get_reg(rdev, op_mode); -+ reg = mcp16502_get_state_reg(rdev, op_mode); - if (reg < 0) - return reg; - -@@ -269,10 +280,10 @@ static int mcp16502_suspend_get_target_r - { - switch (pm_suspend_target_state) { - case PM_SUSPEND_STANDBY: -- return mcp16502_get_reg(rdev, MCP16502_OPMODE_LPM); -+ return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_LPM); - case PM_SUSPEND_ON: - case PM_SUSPEND_MEM: -- return mcp16502_get_reg(rdev, MCP16502_OPMODE_HIB); -+ return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_HIB); - default: - dev_err(&rdev->dev, "invalid suspend target: %d\n", - pm_suspend_target_state); diff --git a/target/linux/at91/patches-5.10/125-regulator-mcp16502-add-support-for-ramp-delay.patch b/target/linux/at91/patches-5.10/125-regulator-mcp16502-add-support-for-ramp-delay.patch deleted file mode 100644 index c91dd4a18b..0000000000 --- a/target/linux/at91/patches-5.10/125-regulator-mcp16502-add-support-for-ramp-delay.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 7f13433e11a3c88f1fd6417c4c5e5a6c98370b9a Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:09 +0200 -Subject: [PATCH 125/247] regulator: mcp16502: add support for ramp delay - -MCP16502 have configurable ramp delay support (via DVSR bits in -regulators' CFG register). - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-6-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 89 +++++++++++++++++++++++++++++++++++- - 1 file changed, 87 insertions(+), 2 deletions(-) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -22,8 +22,9 @@ - #define VDD_LOW_SEL 0x0D - #define VDD_HIGH_SEL 0x3F - --#define MCP16502_FLT BIT(7) --#define MCP16502_ENS BIT(0) -+#define MCP16502_FLT BIT(7) -+#define MCP16502_DVSR GENMASK(3, 2) -+#define MCP16502_ENS BIT(0) - - /* - * The PMIC has four sets of registers corresponding to four power modes: -@@ -88,6 +89,12 @@ enum mcp16502_reg { - MCP16502_REG_CFG, - }; - -+/* Ramp delay (uV/us) for buck1, ldo1, ldo2. */ -+static const int mcp16502_ramp_b1l12[] = { 6250, 3125, 2083, 1563 }; -+ -+/* Ramp delay (uV/us) for buck2, buck3, buck4. */ -+static const int mcp16502_ramp_b234[] = { 3125, 1563, 1042, 781 }; -+ - static unsigned int mcp16502_of_map_mode(unsigned int mode) - { - if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE) -@@ -271,6 +278,80 @@ static int mcp16502_get_status(struct re - return REGULATOR_STATUS_UNDEFINED; - } - -+static int mcp16502_set_voltage_time_sel(struct regulator_dev *rdev, -+ unsigned int old_sel, -+ unsigned int new_sel) -+{ -+ static const u8 us_ramp[] = { 8, 16, 24, 32 }; -+ int id = rdev_get_id(rdev); -+ unsigned int uV_delta, val; -+ int ret; -+ -+ ret = regmap_read(rdev->regmap, MCP16502_REG_BASE(id, CFG), &val); -+ if (ret) -+ return ret; -+ -+ val = (val & MCP16502_DVSR) >> 2; -+ uV_delta = abs(new_sel * rdev->desc->linear_ranges->step - -+ old_sel * rdev->desc->linear_ranges->step); -+ switch (id) { -+ case BUCK1: -+ case LDO1: -+ case LDO2: -+ ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val], -+ mcp16502_ramp_b1l12[val]); -+ break; -+ -+ case BUCK2: -+ case BUCK3: -+ case BUCK4: -+ ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val], -+ mcp16502_ramp_b234[val]); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ return ret; -+} -+ -+static int mcp16502_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay) -+{ -+ const int *ramp; -+ int id = rdev_get_id(rdev); -+ unsigned int i, size; -+ -+ switch (id) { -+ case BUCK1: -+ case LDO1: -+ case LDO2: -+ ramp = mcp16502_ramp_b1l12; -+ size = ARRAY_SIZE(mcp16502_ramp_b1l12); -+ break; -+ -+ case BUCK2: -+ case BUCK3: -+ case BUCK4: -+ ramp = mcp16502_ramp_b234; -+ size = ARRAY_SIZE(mcp16502_ramp_b234); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < size; i++) { -+ if (ramp[i] == ramp_delay) -+ break; -+ } -+ if (i == size) -+ return -EINVAL; -+ -+ return regmap_update_bits(rdev->regmap, MCP16502_REG_BASE(id, CFG), -+ MCP16502_DVSR, (i << 2)); -+} -+ - #ifdef CONFIG_SUSPEND - /* - * mcp16502_suspend_get_target_reg() - get the reg of the target suspend PMIC -@@ -365,6 +446,8 @@ static const struct regulator_ops mcp165 - .disable = regulator_disable_regmap, - .is_enabled = regulator_is_enabled_regmap, - .get_status = mcp16502_get_status, -+ .set_voltage_time_sel = mcp16502_set_voltage_time_sel, -+ .set_ramp_delay = mcp16502_set_ramp_delay, - - .set_mode = mcp16502_set_mode, - .get_mode = mcp16502_get_mode, -@@ -389,6 +472,8 @@ static const struct regulator_ops mcp165 - .disable = regulator_disable_regmap, - .is_enabled = regulator_is_enabled_regmap, - .get_status = mcp16502_get_status, -+ .set_voltage_time_sel = mcp16502_set_voltage_time_sel, -+ .set_ramp_delay = mcp16502_set_ramp_delay, - - #ifdef CONFIG_SUSPEND - .set_suspend_voltage = mcp16502_set_suspend_voltage, diff --git a/target/linux/at91/patches-5.10/126-regulator-mcp16502-remove-void-documentation-of-stru.patch b/target/linux/at91/patches-5.10/126-regulator-mcp16502-remove-void-documentation-of-stru.patch deleted file mode 100644 index f570e2805f..0000000000 --- a/target/linux/at91/patches-5.10/126-regulator-mcp16502-remove-void-documentation-of-stru.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 8dcbcb052f682478dcbfa7fc9abdd909e1deab87 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:10 +0200 -Subject: [PATCH 126/247] regulator: mcp16502: remove void documentation of - struct mcp16502 - -struct mcp16502 has no members called rdev or rmap. Remove the -documentation. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-7-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -135,8 +135,6 @@ enum { - - /* - * struct mcp16502 - PMIC representation -- * @rdev: the regulators belonging to this chip -- * @rmap: regmap to be used for I2C communication - * @lpm: LPM GPIO descriptor - */ - struct mcp16502 { diff --git a/target/linux/at91/patches-5.10/127-regulator-core-validate-selector-against-linear_min_.patch b/target/linux/at91/patches-5.10/127-regulator-core-validate-selector-against-linear_min_.patch deleted file mode 100644 index 78cfcfca3e..0000000000 --- a/target/linux/at91/patches-5.10/127-regulator-core-validate-selector-against-linear_min_.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 3aee4f22ed0a22d3d6d22fc49812c03d876c7637 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 17:21:05 +0200 -Subject: [PATCH 127/247] regulator: core: validate selector against - linear_min_sel - -There are regulators who's min selector is not zero. Selectors loops -(looping b/w zero and regulator::desc::n_voltages) might throw errors -because invalid selectors are used (lower than -regulator::desc::linear_min_sel). For this situations validate selectors -against regulator::desc::linear_min_sel. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605280870-32432-2-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/core.c | 9 +++++++-- - drivers/regulator/helpers.c | 3 ++- - 2 files changed, 9 insertions(+), 3 deletions(-) - ---- a/drivers/regulator/core.c -+++ b/drivers/regulator/core.c -@@ -3000,7 +3000,8 @@ static int _regulator_list_voltage(struc - return rdev->desc->fixed_uV; - - if (ops->list_voltage) { -- if (selector >= rdev->desc->n_voltages) -+ if (selector >= rdev->desc->n_voltages || -+ selector < rdev->desc->linear_min_sel) - return -EINVAL; - if (lock) - regulator_lock(rdev); -@@ -3151,7 +3152,8 @@ int regulator_list_hardware_vsel(struct - struct regulator_dev *rdev = regulator->rdev; - const struct regulator_ops *ops = rdev->desc->ops; - -- if (selector >= rdev->desc->n_voltages) -+ if (selector >= rdev->desc->n_voltages || -+ selector < rdev->desc->linear_min_sel) - return -EINVAL; - if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap) - return -EOPNOTSUPP; -@@ -4074,6 +4076,9 @@ int regulator_set_voltage_time(struct re - - for (i = 0; i < rdev->desc->n_voltages; i++) { - /* We only look for exact voltage matches here */ -+ if (i < rdev->desc->linear_min_sel) -+ continue; -+ - voltage = regulator_list_voltage(regulator, i); - if (voltage < 0) - return -EINVAL; ---- a/drivers/regulator/helpers.c -+++ b/drivers/regulator/helpers.c -@@ -647,7 +647,8 @@ int regulator_list_voltage_table(struct - return -EINVAL; - } - -- if (selector >= rdev->desc->n_voltages) -+ if (selector >= rdev->desc->n_voltages || -+ selector < rdev->desc->linear_min_sel) - return -EINVAL; - - return rdev->desc->volt_table[selector]; diff --git a/target/linux/at91/patches-5.10/128-regulator-core-do-not-continue-if-selector-match.patch b/target/linux/at91/patches-5.10/128-regulator-core-do-not-continue-if-selector-match.patch deleted file mode 100644 index 9c99302980..0000000000 --- a/target/linux/at91/patches-5.10/128-regulator-core-do-not-continue-if-selector-match.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 42b56e8bd343f34d5f2a601d8a8a05d8c861c08c Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 13 Nov 2020 19:56:04 +0200 -Subject: [PATCH 128/247] regulator: core: do not continue if selector match - -Do not continue if selector has already been located. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1605290164-11556-1-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/core.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/regulator/core.c -+++ b/drivers/regulator/core.c -@@ -4079,6 +4079,9 @@ int regulator_set_voltage_time(struct re - if (i < rdev->desc->linear_min_sel) - continue; - -+ if (old_sel >= 0 && new_sel >= 0) -+ break; -+ - voltage = regulator_list_voltage(regulator, i); - if (voltage < 0) - return -EINVAL; diff --git a/target/linux/at91/patches-5.10/129-regulator-core-return-zero-for-selectors-lower-than-.patch b/target/linux/at91/patches-5.10/129-regulator-core-return-zero-for-selectors-lower-than-.patch deleted file mode 100644 index 5c6267c033..0000000000 --- a/target/linux/at91/patches-5.10/129-regulator-core-return-zero-for-selectors-lower-than-.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0e933ffc049a0e181b5a6c3af1933976d6959ba9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 25 Nov 2020 19:25:47 +0200 -Subject: [PATCH 129/247] regulator: core: return zero for selectors lower than - linear_min_sel - -Selectors lower than linear_min_sel should not be considered invalid. -Thus return zero in case _regulator_list_voltage(), -regulator_list_hardware_vsel() or regulator_list_voltage_table() -receives such selectors as argument. - -Fixes: bdcd1177578c ("regulator: core: validate selector against linear_min_sel") -Reported-by: Jon Hunter -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1606325147-606-1-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/core.c | 10 ++++++---- - drivers/regulator/helpers.c | 5 +++-- - 2 files changed, 9 insertions(+), 6 deletions(-) - ---- a/drivers/regulator/core.c -+++ b/drivers/regulator/core.c -@@ -3000,9 +3000,10 @@ static int _regulator_list_voltage(struc - return rdev->desc->fixed_uV; - - if (ops->list_voltage) { -- if (selector >= rdev->desc->n_voltages || -- selector < rdev->desc->linear_min_sel) -+ if (selector >= rdev->desc->n_voltages) - return -EINVAL; -+ if (selector < rdev->desc->linear_min_sel) -+ return 0; - if (lock) - regulator_lock(rdev); - ret = ops->list_voltage(rdev, selector); -@@ -3152,9 +3153,10 @@ int regulator_list_hardware_vsel(struct - struct regulator_dev *rdev = regulator->rdev; - const struct regulator_ops *ops = rdev->desc->ops; - -- if (selector >= rdev->desc->n_voltages || -- selector < rdev->desc->linear_min_sel) -+ if (selector >= rdev->desc->n_voltages) - return -EINVAL; -+ if (selector < rdev->desc->linear_min_sel) -+ return 0; - if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap) - return -EOPNOTSUPP; - ---- a/drivers/regulator/helpers.c -+++ b/drivers/regulator/helpers.c -@@ -647,9 +647,10 @@ int regulator_list_voltage_table(struct - return -EINVAL; - } - -- if (selector >= rdev->desc->n_voltages || -- selector < rdev->desc->linear_min_sel) -+ if (selector >= rdev->desc->n_voltages) - return -EINVAL; -+ if (selector < rdev->desc->linear_min_sel) -+ return 0; - - return rdev->desc->volt_table[selector]; - } diff --git a/target/linux/at91/patches-5.10/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch b/target/linux/at91/patches-5.10/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch deleted file mode 100644 index 12679a20bd..0000000000 --- a/target/linux/at91/patches-5.10/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 763fe72f607d4e929d2c710c88e5c6978dd6ad97 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 7 Jan 2021 16:15:26 +0200 -Subject: [PATCH 130/247] regulator: mcp16502: lpm pin can be optional on some - platforms - -On some platform (e.g. SAMA7G5) LPM pin should be optional as it can -be controlled explicitly (via shutdown controller registers) in the -platform specific power saving code to decrease the power consumption -while suspended as this SoC pin may be connected to other devices that -could take power saving actions based on its value. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/1610028927-9842-3-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Mark Brown ---- - drivers/regulator/mcp16502.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/regulator/mcp16502.c -+++ b/drivers/regulator/mcp16502.c -@@ -550,7 +550,7 @@ static int mcp16502_probe(struct i2c_cli - config.regmap = rmap; - config.driver_data = mcp; - -- mcp->lpm = devm_gpiod_get(dev, "lpm", GPIOD_OUT_LOW); -+ mcp->lpm = devm_gpiod_get_optional(dev, "lpm", GPIOD_OUT_LOW); - if (IS_ERR(mcp->lpm)) { - dev_err(dev, "failed to get lpm pin: %ld\n", PTR_ERR(mcp->lpm)); - return PTR_ERR(mcp->lpm); diff --git a/target/linux/at91/patches-5.10/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch b/target/linux/at91/patches-5.10/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch deleted file mode 100644 index 78db5a0d32..0000000000 --- a/target/linux/at91/patches-5.10/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 7cb1dad7a7dfe4cfe55ebe86930dd6aef0de66b4 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 13 Nov 2020 15:24:29 +0200 -Subject: [PATCH 131/247] pinctrl: at91-pio4: add support for fewer lines on - last PIO bank - -Some products, like sama7g5, do not have a full last bank of PIO lines. -In this case for example, sama7g5 only has 8 lines for the PE bank. -PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines. -To cope with this situation, added a data attribute that is product dependent, -to specify the number of lines of the last bank. -In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK, -adjust the total number of lines accordingly. -This will avoid advertising 160 lines instead of the actual 136, as this -product supports, and to avoid reading/writing to invalid register addresses. - -Signed-off-by: Eugen Hristev -Acked-by: Ludovic Desroches -Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-at91-pio4.c | 18 ++++++++++++++++-- - 1 file changed, 16 insertions(+), 2 deletions(-) - ---- a/drivers/pinctrl/pinctrl-at91-pio4.c -+++ b/drivers/pinctrl/pinctrl-at91-pio4.c -@@ -71,8 +71,15 @@ - /* Custom pinconf parameters */ - #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1) - -+/** -+ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct -+ * @nbanks: number of PIO banks -+ * @last_bank_count: number of lines in the last bank (can be less than -+ * the rest of the banks). -+ */ - struct atmel_pioctrl_data { - unsigned nbanks; -+ unsigned last_bank_count; - }; - - struct atmel_group { -@@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pct - * We can have up to 16 banks. - */ - static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { -- .nbanks = 4, -+ .nbanks = 4, -+ .last_bank_count = ATMEL_PIO_NPINS_PER_BANK, - }; - - static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { -- .nbanks = 5, -+ .nbanks = 5, -+ .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ - }; - - static const struct of_device_id atmel_pctrl_of_match[] = { -@@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct pl - atmel_pioctrl_data = match->data; - atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks; - atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK; -+ /* if last bank has limited number of pins, adjust accordingly */ -+ if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) { -+ atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; -+ atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; -+ } - - atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(atmel_pioctrl->reg_base)) diff --git a/target/linux/at91/patches-5.10/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch b/target/linux/at91/patches-5.10/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch deleted file mode 100644 index ca1fa8cee5..0000000000 --- a/target/linux/at91/patches-5.10/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 1dccaa4c1e99cd8bd27684a2c87ec806d426c088 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 16 Oct 2020 12:37:25 +0300 -Subject: [PATCH 132/247] dmaengine: at_xdmac: adapt perid for mem2mem - operations - -The PERID in the CC register for mem2mem operations must match an unused -PERID. -The PERID field is 7 bits, but the selected value is 0x3f. -On later products we can have more reserved PERIDs for actual peripherals, -thus this needs to be increased to maximum size. -Changing the value to 0x7f, which is the maximum for 7 bits field. - -Signed-off-by: Eugen Hristev -Reviewed-by: Tudor Ambarus -Link: https://lore.kernel.org/r/20201016093725.289880-1-eugen.hristev@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/dma/at_xdmac.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/dma/at_xdmac.c -+++ b/drivers/dma/at_xdmac.c -@@ -865,7 +865,7 @@ at_xdmac_interleaved_queue_desc(struct d - * match the one of another channel. If not, it could lead to spurious - * flag status. - */ -- u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) -+ u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DIF(0) - | AT_XDMAC_CC_SIF(0) - | AT_XDMAC_CC_MBSIZE_SIXTEEN -@@ -1047,7 +1047,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan - * match the one of another channel. If not, it could lead to spurious - * flag status. - */ -- u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) -+ u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DAM_INCREMENTED_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM - | AT_XDMAC_CC_DIF(0) -@@ -1153,7 +1153,7 @@ static struct at_xdmac_desc *at_xdmac_me - * match the one of another channel. If not, it could lead to spurious - * flag status. - */ -- u32 chan_cc = AT_XDMAC_CC_PERID(0x3f) -+ u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DAM_UBS_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM - | AT_XDMAC_CC_DIF(0) diff --git a/target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch b/target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch deleted file mode 100644 index 6d338490fb..0000000000 --- a/target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch +++ /dev/null @@ -1,280 +0,0 @@ -From 613af756b93fe005d9db11ea26fd0318f239d5a2 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 16 Oct 2020 12:38:50 +0300 -Subject: [PATCH 133/247] dmaengine: at_xdmac: add support for sama7g5 based - at_xdmac - -SAMA7G5 SoC uses a slightly different variant of the AT_XDMAC. -Added support by a new compatible and a layout struct that copes -to the specific version considering the compatible string. -Only the differences in register map are present in the layout struct. -I reworked the register access for this part that has the differences. -Also the Source/Destination Interface bits are no longer valid for this -variant of the XDMAC. Thus, the layout also has a bool for specifying -whether these bits are required or not. - -Signed-off-by: Eugen Hristev -Link: https://lore.kernel.org/r/20201016093850.290053-1-eugen.hristev@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/dma/at_xdmac.c | 110 +++++++++++++++++++++++++++++++---------- - 1 file changed, 84 insertions(+), 26 deletions(-) - ---- a/drivers/dma/at_xdmac.c -+++ b/drivers/dma/at_xdmac.c -@@ -38,13 +38,6 @@ - #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */ - #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */ - #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */ --#define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */ --#define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */ --#define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */ --#define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */ --#define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */ --#define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */ --#define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */ - #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */ - - /* Channel relative registers offsets */ -@@ -151,8 +144,6 @@ - #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */ - #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */ - --#define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */ -- - /* Microblock control members */ - #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */ - #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */ -@@ -180,6 +171,27 @@ enum atc_status { - AT_XDMAC_CHAN_IS_PAUSED, - }; - -+struct at_xdmac_layout { -+ /* Global Channel Read Suspend Register */ -+ u8 grs; -+ /* Global Write Suspend Register */ -+ u8 gws; -+ /* Global Channel Read Write Suspend Register */ -+ u8 grws; -+ /* Global Channel Read Write Resume Register */ -+ u8 grwr; -+ /* Global Channel Software Request Register */ -+ u8 gswr; -+ /* Global channel Software Request Status Register */ -+ u8 gsws; -+ /* Global Channel Software Flush Request Register */ -+ u8 gswf; -+ /* Channel reg base */ -+ u8 chan_cc_reg_base; -+ /* Source/Destination Interface must be specified or not */ -+ bool sdif; -+}; -+ - /* ----- Channels ----- */ - struct at_xdmac_chan { - struct dma_chan chan; -@@ -213,6 +225,7 @@ struct at_xdmac { - struct clk *clk; - u32 save_gim; - struct dma_pool *at_xdmac_desc_pool; -+ const struct at_xdmac_layout *layout; - struct at_xdmac_chan chan[]; - }; - -@@ -245,9 +258,33 @@ struct at_xdmac_desc { - struct list_head xfer_node; - } __aligned(sizeof(u64)); - -+static const struct at_xdmac_layout at_xdmac_sama5d4_layout = { -+ .grs = 0x28, -+ .gws = 0x2C, -+ .grws = 0x30, -+ .grwr = 0x34, -+ .gswr = 0x38, -+ .gsws = 0x3C, -+ .gswf = 0x40, -+ .chan_cc_reg_base = 0x50, -+ .sdif = true, -+}; -+ -+static const struct at_xdmac_layout at_xdmac_sama7g5_layout = { -+ .grs = 0x30, -+ .gws = 0x38, -+ .grws = 0x40, -+ .grwr = 0x44, -+ .gswr = 0x48, -+ .gsws = 0x4C, -+ .gswf = 0x50, -+ .chan_cc_reg_base = 0x60, -+ .sdif = false, -+}; -+ - static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) - { -- return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40); -+ return atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40); - } - - #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg)) -@@ -343,8 +380,10 @@ static void at_xdmac_start_xfer(struct a - first->active_xfer = true; - - /* Tell xdmac where to get the first descriptor. */ -- reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys) -- | AT_XDMAC_CNDA_NDAIF(atchan->memif); -+ reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys); -+ if (atxdmac->layout->sdif) -+ reg |= AT_XDMAC_CNDA_NDAIF(atchan->memif); -+ - at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg); - - /* -@@ -539,6 +578,7 @@ static int at_xdmac_compute_chan_conf(st - enum dma_transfer_direction direction) - { - struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); -+ struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); - int csize, dwidth; - - if (direction == DMA_DEV_TO_MEM) { -@@ -546,12 +586,14 @@ static int at_xdmac_compute_chan_conf(st - AT91_XDMAC_DT_PERID(atchan->perid) - | AT_XDMAC_CC_DAM_INCREMENTED_AM - | AT_XDMAC_CC_SAM_FIXED_AM -- | AT_XDMAC_CC_DIF(atchan->memif) -- | AT_XDMAC_CC_SIF(atchan->perif) - | AT_XDMAC_CC_SWREQ_HWR_CONNECTED - | AT_XDMAC_CC_DSYNC_PER2MEM - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_TYPE_PER_TRAN; -+ if (atxdmac->layout->sdif) -+ atchan->cfg |= AT_XDMAC_CC_DIF(atchan->memif) | -+ AT_XDMAC_CC_SIF(atchan->perif); -+ - csize = ffs(atchan->sconfig.src_maxburst) - 1; - if (csize < 0) { - dev_err(chan2dev(chan), "invalid src maxburst value\n"); -@@ -569,12 +611,14 @@ static int at_xdmac_compute_chan_conf(st - AT91_XDMAC_DT_PERID(atchan->perid) - | AT_XDMAC_CC_DAM_FIXED_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM -- | AT_XDMAC_CC_DIF(atchan->perif) -- | AT_XDMAC_CC_SIF(atchan->memif) - | AT_XDMAC_CC_SWREQ_HWR_CONNECTED - | AT_XDMAC_CC_DSYNC_MEM2PER - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_TYPE_PER_TRAN; -+ if (atxdmac->layout->sdif) -+ atchan->cfg |= AT_XDMAC_CC_DIF(atchan->perif) | -+ AT_XDMAC_CC_SIF(atchan->memif); -+ - csize = ffs(atchan->sconfig.dst_maxburst) - 1; - if (csize < 0) { - dev_err(chan2dev(chan), "invalid src maxburst value\n"); -@@ -864,10 +908,12 @@ at_xdmac_interleaved_queue_desc(struct d - * ERRATA: Even if useless for memory transfers, the PERID has to not - * match the one of another channel. If not, it could lead to spurious - * flag status. -+ * For SAMA7G5x case, the SIF and DIF fields are no longer used. -+ * Thus, no need to have the SIF/DIF interfaces here. -+ * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as -+ * zero. - */ - u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) -- | AT_XDMAC_CC_DIF(0) -- | AT_XDMAC_CC_SIF(0) - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_TYPE_MEM_TRAN; - -@@ -1046,12 +1092,14 @@ at_xdmac_prep_dma_memcpy(struct dma_chan - * ERRATA: Even if useless for memory transfers, the PERID has to not - * match the one of another channel. If not, it could lead to spurious - * flag status. -+ * For SAMA7G5x case, the SIF and DIF fields are no longer used. -+ * Thus, no need to have the SIF/DIF interfaces here. -+ * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as -+ * zero. - */ - u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DAM_INCREMENTED_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM -- | AT_XDMAC_CC_DIF(0) -- | AT_XDMAC_CC_SIF(0) - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_TYPE_MEM_TRAN; - unsigned long irqflags; -@@ -1152,12 +1200,14 @@ static struct at_xdmac_desc *at_xdmac_me - * ERRATA: Even if useless for memory transfers, the PERID has to not - * match the one of another channel. If not, it could lead to spurious - * flag status. -+ * For SAMA7G5x case, the SIF and DIF fields are no longer used. -+ * Thus, no need to have the SIF/DIF interfaces here. -+ * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as -+ * zero. - */ - u32 chan_cc = AT_XDMAC_CC_PERID(0x7f) - | AT_XDMAC_CC_DAM_UBS_AM - | AT_XDMAC_CC_SAM_INCREMENTED_AM -- | AT_XDMAC_CC_DIF(0) -- | AT_XDMAC_CC_SIF(0) - | AT_XDMAC_CC_MBSIZE_SIXTEEN - | AT_XDMAC_CC_MEMSET_HW_MODE - | AT_XDMAC_CC_TYPE_MEM_TRAN; -@@ -1436,7 +1486,7 @@ at_xdmac_tx_status(struct dma_chan *chan - mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC; - value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM; - if ((desc->lld.mbr_cfg & mask) == value) { -- at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); -+ at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask); - while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) - cpu_relax(); - } -@@ -1494,7 +1544,7 @@ at_xdmac_tx_status(struct dma_chan *chan - * FIFO flush ensures that data are really written. - */ - if ((desc->lld.mbr_cfg & mask) == value) { -- at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); -+ at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask); - while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) - cpu_relax(); - } -@@ -1762,7 +1812,7 @@ static int at_xdmac_device_pause(struct - return 0; - - spin_lock_irqsave(&atchan->lock, flags); -- at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask); -+ at_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask); - while (at_xdmac_chan_read(atchan, AT_XDMAC_CC) - & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP)) - cpu_relax(); -@@ -1785,7 +1835,7 @@ static int at_xdmac_device_resume(struct - return 0; - } - -- at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask); -+ at_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask); - clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); - spin_unlock_irqrestore(&atchan->lock, flags); - -@@ -1992,6 +2042,10 @@ static int at_xdmac_probe(struct platfor - atxdmac->regs = base; - atxdmac->irq = irq; - -+ atxdmac->layout = of_device_get_match_data(&pdev->dev); -+ if (!atxdmac->layout) -+ return -ENODEV; -+ - atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk"); - if (IS_ERR(atxdmac->clk)) { - dev_err(&pdev->dev, "can't get dma_clk\n"); -@@ -2134,6 +2188,10 @@ static const struct dev_pm_ops atmel_xdm - static const struct of_device_id atmel_xdmac_dt_ids[] = { - { - .compatible = "atmel,sama5d4-dma", -+ .data = &at_xdmac_sama5d4_layout, -+ }, { -+ .compatible = "microchip,sama7g5-dma", -+ .data = &at_xdmac_sama7g5_layout, - }, { - /* sentinel */ - } diff --git a/target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch b/target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch deleted file mode 100644 index 463d03a35e..0000000000 --- a/target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 4833d6ea13a6d2c44a91247991a82c3eb6c1613e Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 16 Oct 2020 12:39:18 +0300 -Subject: [PATCH 134/247] dmaengine: at_xdmac: add AXI priority support and - recommended settings - -The sama7g5 version of the XDMAC supports priority configuration and -outstanding capabilities. -Add defines for the specific registers for this configuration, together -with recommended settings. -However the settings are very different if the XDMAC is a mem2mem or a -per2mem controller. -Thus, we need to differentiate according to device tree property. - -Signed-off-by: Eugen Hristev -Link: https://lore.kernel.org/r/20201016093918.290137-1-eugen.hristev@microchip.com -Signed-off-by: Vinod Koul ---- - drivers/dma/at_xdmac.c | 47 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 47 insertions(+) - ---- a/drivers/dma/at_xdmac.c -+++ b/drivers/dma/at_xdmac.c -@@ -30,7 +30,24 @@ - #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */ - #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */ - #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */ -+#define AT_XDMAC_WRHP(i) (((i) & 0xF) << 4) -+#define AT_XDMAC_WRMP(i) (((i) & 0xF) << 8) -+#define AT_XDMAC_WRLP(i) (((i) & 0xF) << 12) -+#define AT_XDMAC_RDHP(i) (((i) & 0xF) << 16) -+#define AT_XDMAC_RDMP(i) (((i) & 0xF) << 20) -+#define AT_XDMAC_RDLP(i) (((i) & 0xF) << 24) -+#define AT_XDMAC_RDSG(i) (((i) & 0xF) << 28) -+#define AT_XDMAC_GCFG_M2M (AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF)) -+#define AT_XDMAC_GCFG_P2M (AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \ -+ AT_XDMAC_WRHP(0x5)) - #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */ -+#define AT_XDMAC_PW0(i) (((i) & 0xF) << 0) -+#define AT_XDMAC_PW1(i) (((i) & 0xF) << 4) -+#define AT_XDMAC_PW2(i) (((i) & 0xF) << 8) -+#define AT_XDMAC_PW3(i) (((i) & 0xF) << 12) -+#define AT_XDMAC_GWAC_M2M 0 -+#define AT_XDMAC_GWAC_P2M (AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF)) -+ - #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */ - #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */ - #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */ -@@ -190,6 +207,8 @@ struct at_xdmac_layout { - u8 chan_cc_reg_base; - /* Source/Destination Interface must be specified or not */ - bool sdif; -+ /* AXI queue priority configuration supported */ -+ bool axi_config; - }; - - /* ----- Channels ----- */ -@@ -268,6 +287,7 @@ static const struct at_xdmac_layout at_x - .gswf = 0x40, - .chan_cc_reg_base = 0x50, - .sdif = true, -+ .axi_config = false, - }; - - static const struct at_xdmac_layout at_xdmac_sama7g5_layout = { -@@ -280,6 +300,7 @@ static const struct at_xdmac_layout at_x - .gswf = 0x50, - .chan_cc_reg_base = 0x60, - .sdif = false, -+ .axi_config = true, - }; - - static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) -@@ -2003,6 +2024,30 @@ static int atmel_xdmac_resume(struct dev - } - #endif /* CONFIG_PM_SLEEP */ - -+static void at_xdmac_axi_config(struct platform_device *pdev) -+{ -+ struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev); -+ bool dev_m2m = false; -+ u32 dma_requests; -+ -+ if (!atxdmac->layout->axi_config) -+ return; /* Not supported */ -+ -+ if (!of_property_read_u32(pdev->dev.of_node, "dma-requests", -+ &dma_requests)) { -+ dev_info(&pdev->dev, "controller in mem2mem mode.\n"); -+ dev_m2m = true; -+ } -+ -+ if (dev_m2m) { -+ at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M); -+ at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M); -+ } else { -+ at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M); -+ at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M); -+ } -+} -+ - static int at_xdmac_probe(struct platform_device *pdev) - { - struct at_xdmac *atxdmac; -@@ -2147,6 +2192,8 @@ static int at_xdmac_probe(struct platfor - dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n", - nr_channels, atxdmac->regs); - -+ at_xdmac_axi_config(pdev); -+ - return 0; - - err_dma_unregister: diff --git a/target/linux/at91/patches-5.10/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch b/target/linux/at91/patches-5.10/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch deleted file mode 100644 index 210d1bd2de..0000000000 --- a/target/linux/at91/patches-5.10/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 982347f757b85ef526afaf243867ddd515475e1b Mon Sep 17 00:00:00 2001 -From: Charles Keepax -Date: Mon, 4 Jan 2021 10:38:02 +0000 -Subject: [PATCH 135/247] net: macb: Correct usage of MACB_CAPS_CLK_HW_CHG flag - -A new flag MACB_CAPS_CLK_HW_CHG was added and all callers of -macb_set_tx_clk were gated on the presence of this flag. - -- if (!clk) -+ if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) - -However the flag was not added to anything other than the new -sama7g5_gem, turning that function call into a no op for all other -systems. This breaks the networking on Zynq. - -The commit message adding this states: a new capability so that -macb_set_tx_clock() to not be called for IPs having this -capability - -This strongly implies that present of the flag was intended to skip -the function not absence of the flag. Update the if statement to -this effect, which repairs the existing users. - -Fixes: daafa1d33cc9 ("net: macb: add capability to not set the clock rate") -Suggested-by: Andrew Lunn -Signed-off-by: Charles Keepax -Reviewed-by: Claudiu Beznea -Reviewed-by: Andrew Lunn -Link: https://lore.kernel.org/r/20210104103802.13091-1-ckeepax@opensource.cirrus.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/cadence/macb_main.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -464,7 +464,7 @@ static void macb_set_tx_clk(struct macb - { - long ferr, rate, rate_rounded; - -- if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG)) -+ if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG)) - return; - - switch (speed) { diff --git a/target/linux/at91/patches-5.10/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch b/target/linux/at91/patches-5.10/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch deleted file mode 100644 index 7c36d0f93a..0000000000 --- a/target/linux/at91/patches-5.10/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch +++ /dev/null @@ -1,43 +0,0 @@ -From a2eda4ef1e3d617cdd669e256e45e969fab62398 Mon Sep 17 00:00:00 2001 -From: Kai Stuhlemmer -Date: Thu, 8 Oct 2020 14:50:28 +0200 -Subject: [PATCH 136/247] ARM: at91: sam9x60 SiP types added to soc description - -Adding SAM9X60 SIP variants to the soc description list. - -Signed-off-by: Kai Stuhlemmer -Signed-off-by: Nicolas Ferre -Signed-off-by: Alexandre Belloni -Link: https://lore.kernel.org/r/20201008125028.21071-1-nicolas.ferre@microchip.com ---- - drivers/soc/atmel/soc.c | 6 ++++++ - drivers/soc/atmel/soc.h | 3 +++ - 2 files changed, 9 insertions(+) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -69,6 +69,12 @@ static const struct at91_soc __initconst - #endif - #ifdef CONFIG_SOC_SAM9X60 - AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"), -+ AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, -+ "sam9x60 64MiB DDR2 SiP", "sam9x60"), -+ AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, -+ "sam9x60 128MiB DDR2 SiP", "sam9x60"), -+ AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, -+ "sam9x60 8MiB SDRAM SiP", "sam9x60"), - #endif - #ifdef CONFIG_SOC_SAMA5 - AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, ---- a/drivers/soc/atmel/soc.h -+++ b/drivers/soc/atmel/soc.h -@@ -60,6 +60,9 @@ at91_soc_init(const struct at91_soc *soc - #define AT91SAM9CN11_EXID_MATCH 0x00000009 - - #define SAM9X60_EXID_MATCH 0x00000000 -+#define SAM9X60_D5M_EXID_MATCH 0x00000001 -+#define SAM9X60_D1G_EXID_MATCH 0x00000010 -+#define SAM9X60_D6K_EXID_MATCH 0x00000011 - - #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 - #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 diff --git a/target/linux/at91/patches-5.10/137-drivers-soc-atmel-use-GENMASK.patch b/target/linux/at91/patches-5.10/137-drivers-soc-atmel-use-GENMASK.patch deleted file mode 100644 index de99d562f4..0000000000 --- a/target/linux/at91/patches-5.10/137-drivers-soc-atmel-use-GENMASK.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 8d858d9c57a0210ca1ce9e5ba76fab8bdb4d7b39 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 22 Jan 2021 14:21:32 +0200 -Subject: [PATCH 137/247] drivers: soc: atmel: use GENMASK - -Use GENMASK() to define CIDR match mask. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611318097-8970-3-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -27,7 +27,7 @@ - #define AT91_CHIPID_EXID 0x04 - #define AT91_CIDR_VERSION(x) ((x) & 0x1f) - #define AT91_CIDR_EXT BIT(31) --#define AT91_CIDR_MATCH_MASK 0x7fffffe0 -+#define AT91_CIDR_MATCH_MASK GENMASK(30, 5) - - static const struct at91_soc __initconst socs[] = { - #ifdef CONFIG_SOC_AT91RM9200 diff --git a/target/linux/at91/patches-5.10/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch b/target/linux/at91/patches-5.10/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch deleted file mode 100644 index 885528a28e..0000000000 --- a/target/linux/at91/patches-5.10/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch +++ /dev/null @@ -1,26 +0,0 @@ -From ed871f95827e9b6d4ee9f9eafec4e18b87fb1a56 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 22 Jan 2021 14:21:33 +0200 -Subject: [PATCH 138/247] drivers: soc: atmel: fix "__initconst should be - placed after socs[]" warning - -Fix checkpatch.pl warning: "__initconst should be placed after socs[]". - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611318097-8970-4-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -29,7 +29,7 @@ - #define AT91_CIDR_EXT BIT(31) - #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) - --static const struct at91_soc __initconst socs[] = { -+static const struct at91_soc socs[] __initconst = { - #ifdef CONFIG_SOC_AT91RM9200 - AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"), - #endif diff --git a/target/linux/at91/patches-5.10/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch b/target/linux/at91/patches-5.10/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch deleted file mode 100644 index 72cdb46f11..0000000000 --- a/target/linux/at91/patches-5.10/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch +++ /dev/null @@ -1,348 +0,0 @@ -From 8f6f7ef363268f417f1729bb0b234326dd1e8e2a Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 22 Jan 2021 14:21:35 +0200 -Subject: [PATCH 139/247] drivers: soc: atmel: add per soc id and version match - masks - -SAMA7G5 has different masks for chip ID and chip version on CIDR -register compared to previous AT91 SoCs. For this the commit adapts -the code for SAMA7G5 addition by introducing 2 new members in -struct at91_soc and fill them properly and also preparing the -parsing of proper DT binding. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611318097-8970-6-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 199 +++++++++++++++++++++++++++------------- - drivers/soc/atmel/soc.h | 7 +- - 2 files changed, 140 insertions(+), 66 deletions(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -25,135 +25,200 @@ - #define AT91_DBGU_EXID 0x44 - #define AT91_CHIPID_CIDR 0x00 - #define AT91_CHIPID_EXID 0x04 --#define AT91_CIDR_VERSION(x) ((x) & 0x1f) -+#define AT91_CIDR_VERSION(x, m) ((x) & (m)) -+#define AT91_CIDR_VERSION_MASK GENMASK(4, 0) - #define AT91_CIDR_EXT BIT(31) - #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) - - static const struct at91_soc socs[] __initconst = { - #ifdef CONFIG_SOC_AT91RM9200 -- AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"), -+ AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"), - #endif - #ifdef CONFIG_SOC_AT91SAM9 -- AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL), -- AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL), -- AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL), -- AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL), -- AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL), -- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH, -+ AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL), -+ AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL), -+ AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL), -+ AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL), -+ AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL), -+ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH, - "at91sam9m11", "at91sam9g45"), -- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH, -+ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH, - "at91sam9m10", "at91sam9g45"), -- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH, -+ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH, - "at91sam9g46", "at91sam9g45"), -- AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH, -+ AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH, - "at91sam9g45", "at91sam9g45"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH, - "at91sam9g15", "at91sam9x5"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH, - "at91sam9g35", "at91sam9x5"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH, - "at91sam9x35", "at91sam9x5"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH, - "at91sam9g25", "at91sam9x5"), -- AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH, -+ AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH, - "at91sam9x25", "at91sam9x5"), -- AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH, -+ AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH, - "at91sam9cn12", "at91sam9n12"), -- AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH, -+ AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH, - "at91sam9n12", "at91sam9n12"), -- AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH, -+ AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH, - "at91sam9cn11", "at91sam9n12"), -- AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"), -- AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"), -- AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"), -+ AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"), -+ AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"), -+ AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"), - #endif - #ifdef CONFIG_SOC_SAM9X60 -- AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"), -+ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, -+ "sam9x60", "sam9x60"), - AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, -+ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, - "sam9x60 64MiB DDR2 SiP", "sam9x60"), - AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, -+ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, - "sam9x60 128MiB DDR2 SiP", "sam9x60"), - AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, -+ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, - "sam9x60 8MiB SDRAM SiP", "sam9x60"), - #endif - #ifdef CONFIG_SOC_SAMA5 -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, - "sama5d21", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH, - "sama5d22", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH, - "sama5d225c 16MiB SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH, - "sama5d23", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH, - "sama5d24", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH, - "sama5d24", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH, - "sama5d26", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH, - "sama5d27", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH, - "sama5d27", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH, - "sama5d27c 128MiB SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH, - "sama5d27c 64MiB SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH, - "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH, - "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH, - "sama5d28", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH, - "sama5d28", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH, - "sama5d28c 128MiB SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH, - "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"), -- AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH, -+ AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH, - "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH, - "sama5d31", "sama5d3"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH, - "sama5d33", "sama5d3"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH, - "sama5d34", "sama5d3"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH, - "sama5d35", "sama5d3"), -- AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH, -+ AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH, - "sama5d36", "sama5d3"), -- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH, -+ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH, - "sama5d41", "sama5d4"), -- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH, -+ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH, - "sama5d42", "sama5d4"), -- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH, -+ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH, - "sama5d43", "sama5d4"), -- AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH, -+ AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH, - "sama5d44", "sama5d4"), - #endif - #ifdef CONFIG_SOC_SAMV7 -- AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH, -+ AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH, - "same70q21", "same7"), -- AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH, -+ AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH, - "same70q20", "same7"), -- AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH, -+ AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK -+ AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH, - "same70q19", "same7"), -- AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH, -+ AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH, - "sams70q21", "sams7"), -- AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH, -+ AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH, - "sams70q20", "sams7"), -- AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH, -+ AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH, - "sams70q19", "sams7"), -- AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH, -+ AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH, - "samv71q21", "samv7"), -- AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH, -+ AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH, - "samv71q20", "samv7"), -- AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH, -+ AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH, - "samv71q19", "samv7"), -- AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH, -+ AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH, - "samv70q20", "samv7"), -- AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH, -+ AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH, - "samv70q19", "samv7"), - #endif - { /* sentinel */ }, -@@ -191,8 +256,12 @@ static int __init at91_get_cidr_exid_fro - { - struct device_node *np; - void __iomem *regs; -+ static const struct of_device_id chipids[] = { -+ { .compatible = "atmel,sama5d2-chipid" }, -+ { }, -+ }; - -- np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid"); -+ np = of_find_matching_node(NULL, chipids); - if (!np) - return -ENODEV; - -@@ -235,7 +304,7 @@ struct soc_device * __init at91_soc_init - } - - for (soc = socs; soc->name; soc++) { -- if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK)) -+ if (soc->cidr_match != (cidr & soc->cidr_mask)) - continue; - - if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid) -@@ -254,7 +323,7 @@ struct soc_device * __init at91_soc_init - soc_dev_attr->family = soc->family; - soc_dev_attr->soc_id = soc->name; - soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", -- AT91_CIDR_VERSION(cidr)); -+ AT91_CIDR_VERSION(cidr, soc->version_mask)); - soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { - kfree(soc_dev_attr->revision); -@@ -266,7 +335,7 @@ struct soc_device * __init at91_soc_init - if (soc->family) - pr_info("Detected SoC family: %s\n", soc->family); - pr_info("Detected SoC: %s, revision %X\n", soc->name, -- AT91_CIDR_VERSION(cidr)); -+ AT91_CIDR_VERSION(cidr, soc->version_mask)); - - return soc_dev; - } ---- a/drivers/soc/atmel/soc.h -+++ b/drivers/soc/atmel/soc.h -@@ -16,14 +16,19 @@ - - struct at91_soc { - u32 cidr_match; -+ u32 cidr_mask; -+ u32 version_mask; - u32 exid_match; - const char *name; - const char *family; - }; - --#define AT91_SOC(__cidr, __exid, __name, __family) \ -+#define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid, \ -+ __name, __family) \ - { \ - .cidr_match = (__cidr), \ -+ .cidr_mask = (__cidr_mask), \ -+ .version_mask = (__version_mask), \ - .exid_match = (__exid), \ - .name = (__name), \ - .family = (__family), \ diff --git a/target/linux/at91/patches-5.10/140-drivers-soc-atmel-add-support-for-sama7g5.patch b/target/linux/at91/patches-5.10/140-drivers-soc-atmel-add-support-for-sama7g5.patch deleted file mode 100644 index 3b21017673..0000000000 --- a/target/linux/at91/patches-5.10/140-drivers-soc-atmel-add-support-for-sama7g5.patch +++ /dev/null @@ -1,87 +0,0 @@ -From e20bb57fc51741677a6fcae04e564797fd18921b Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Fri, 22 Jan 2021 14:21:37 +0200 -Subject: [PATCH 140/247] drivers: soc: atmel: add support for sama7g5 - -Add support for SAMA7G5 SoCs. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611318097-8970-8-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 18 ++++++++++++++++++ - drivers/soc/atmel/soc.h | 6 ++++++ - 2 files changed, 24 insertions(+) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -27,8 +27,10 @@ - #define AT91_CHIPID_EXID 0x04 - #define AT91_CIDR_VERSION(x, m) ((x) & (m)) - #define AT91_CIDR_VERSION_MASK GENMASK(4, 0) -+#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0) - #define AT91_CIDR_EXT BIT(31) - #define AT91_CIDR_MATCH_MASK GENMASK(30, 5) -+#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5) - - static const struct at91_soc socs[] __initconst = { - #ifdef CONFIG_SOC_AT91RM9200 -@@ -221,6 +223,20 @@ static const struct at91_soc socs[] __in - AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH, - "samv70q19", "samv7"), - #endif -+#ifdef CONFIG_SOC_SAMA7 -+ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH, -+ "sama7g51", "sama7g5"), -+ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH, -+ "sama7g52", "sama7g5"), -+ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH, -+ "sama7g53", "sama7g5"), -+ AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, -+ AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH, -+ "sama7g54", "sama7g5"), -+#endif - { /* sentinel */ }, - }; - -@@ -258,6 +274,7 @@ static int __init at91_get_cidr_exid_fro - void __iomem *regs; - static const struct of_device_id chipids[] = { - { .compatible = "atmel,sama5d2-chipid" }, -+ { .compatible = "microchip,sama7g5-chipid" }, - { }, - }; - -@@ -345,6 +362,7 @@ static const struct of_device_id at91_so - { .compatible = "atmel,at91sam9", }, - { .compatible = "atmel,sama5", }, - { .compatible = "atmel,samv7", }, -+ { .compatible = "microchip,sama7g5", }, - { } - }; - ---- a/drivers/soc/atmel/soc.h -+++ b/drivers/soc/atmel/soc.h -@@ -48,6 +48,7 @@ at91_soc_init(const struct at91_soc *soc - #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 - #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 - #define SAM9X60_CIDR_MATCH 0x019b35a0 -+#define SAMA7G5_CIDR_MATCH 0x00162100 - - #define AT91SAM9M11_EXID_MATCH 0x00000001 - #define AT91SAM9M10_EXID_MATCH 0x00000002 -@@ -69,6 +70,11 @@ at91_soc_init(const struct at91_soc *soc - #define SAM9X60_D1G_EXID_MATCH 0x00000010 - #define SAM9X60_D6K_EXID_MATCH 0x00000011 - -+#define SAMA7G51_EXID_MATCH 0x3 -+#define SAMA7G52_EXID_MATCH 0x2 -+#define SAMA7G53_EXID_MATCH 0x1 -+#define SAMA7G54_EXID_MATCH 0x0 -+ - #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 - #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 - #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 diff --git a/target/linux/at91/patches-5.10/141-drivers-soc-atmel-add-spdx-license-identifier.patch b/target/linux/at91/patches-5.10/141-drivers-soc-atmel-add-spdx-license-identifier.patch deleted file mode 100644 index be238147d6..0000000000 --- a/target/linux/at91/patches-5.10/141-drivers-soc-atmel-add-spdx-license-identifier.patch +++ /dev/null @@ -1,49 +0,0 @@ -From acd4816cfa7811b13ca2864645f2de41031ccf4d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Tue, 26 Jan 2021 11:29:30 +0200 -Subject: [PATCH 141/247] drivers: soc: atmel: add spdx license identifier - -Add SPDX-License-Identifier. - -Signed-off-by: Claudiu Beznea -[nicolas.ferre@microhcip.com: remove license boilerplate now it's useless] -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/1611653376-24168-2-git-send-email-claudiu.beznea@microchip.com ---- - drivers/soc/atmel/soc.c | 6 +----- - drivers/soc/atmel/soc.h | 6 +----- - 2 files changed, 2 insertions(+), 10 deletions(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -1,13 +1,9 @@ -+// SPDX-License-Identifier: GPL-2.0-only - /* - * Copyright (C) 2015 Atmel - * - * Alexandre Belloni -Date: Thu, 4 Feb 2021 16:49:25 +0100 -Subject: [PATCH 142/247] drivers: soc: atmel: fix type for same7 - -A missing comma caused a build failure: - -drivers/soc/atmel/soc.c:196:24: error: too few arguments provided to function-like macro invocation - -Fixes: af3a10513cd6 ("drivers: soc: atmel: add per soc id and version match masks") -Signed-off-by: Arnd Bergmann -Acked-by: Alexandre Belloni -Signed-off-by: Arnd Bergmann ---- - drivers/soc/atmel/soc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/soc/atmel/soc.c -+++ b/drivers/soc/atmel/soc.c -@@ -191,7 +191,7 @@ static const struct at91_soc socs[] __in - AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK, - AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH, - "same70q20", "same7"), -- AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK -+ AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK, - AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH, - "same70q19", "same7"), - AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK, diff --git a/target/linux/at91/patches-5.10/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch b/target/linux/at91/patches-5.10/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch deleted file mode 100644 index 7b2462cd00..0000000000 --- a/target/linux/at91/patches-5.10/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch +++ /dev/null @@ -1,173 +0,0 @@ -From 5f090a664d62ceeaf9a0f482426e35cab18d65a9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Tue, 19 Jan 2021 14:59:25 +0200 -Subject: [PATCH 143/247] clocksource/drivers/timer-microchip-pit64b: Add - clocksource suspend/resume - -Add suspend/resume support for clocksource timer. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Daniel Lezcano -Link: https://lore.kernel.org/r/1611061165-30180-1-git-send-email-claudiu.beznea@microchip.com ---- - drivers/clocksource/timer-microchip-pit64b.c | 86 ++++++++++++++++---- - 1 file changed, 71 insertions(+), 15 deletions(-) - ---- a/drivers/clocksource/timer-microchip-pit64b.c -+++ b/drivers/clocksource/timer-microchip-pit64b.c -@@ -71,10 +71,24 @@ struct mchp_pit64b_clkevt { - struct clock_event_device clkevt; - }; - --#define to_mchp_pit64b_timer(x) \ -+#define clkevt_to_mchp_pit64b_timer(x) \ - ((struct mchp_pit64b_timer *)container_of(x,\ - struct mchp_pit64b_clkevt, clkevt)) - -+/** -+ * mchp_pit64b_clksrc - PIT64B clocksource data structure -+ * @timer: PIT64B timer -+ * @clksrc: clocksource -+ */ -+struct mchp_pit64b_clksrc { -+ struct mchp_pit64b_timer timer; -+ struct clocksource clksrc; -+}; -+ -+#define clksrc_to_mchp_pit64b_timer(x) \ -+ ((struct mchp_pit64b_timer *)container_of(x,\ -+ struct mchp_pit64b_clksrc, clksrc)) -+ - /* Base address for clocksource timer. */ - static void __iomem *mchp_pit64b_cs_base; - /* Default cycles for clockevent timer. */ -@@ -116,6 +130,36 @@ static inline void mchp_pit64b_reset(str - writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR); - } - -+static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer) -+{ -+ writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); -+ if (timer->mode & MCHP_PIT64B_MR_SGCLK) -+ clk_disable_unprepare(timer->gclk); -+ clk_disable_unprepare(timer->pclk); -+} -+ -+static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer) -+{ -+ clk_prepare_enable(timer->pclk); -+ if (timer->mode & MCHP_PIT64B_MR_SGCLK) -+ clk_prepare_enable(timer->gclk); -+} -+ -+static void mchp_pit64b_clksrc_suspend(struct clocksource *cs) -+{ -+ struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); -+ -+ mchp_pit64b_suspend(timer); -+} -+ -+static void mchp_pit64b_clksrc_resume(struct clocksource *cs) -+{ -+ struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); -+ -+ mchp_pit64b_resume(timer); -+ mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); -+} -+ - static u64 mchp_pit64b_clksrc_read(struct clocksource *cs) - { - return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); -@@ -128,7 +172,7 @@ static u64 notrace mchp_pit64b_sched_rea - - static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - - writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); - -@@ -137,7 +181,7 @@ static int mchp_pit64b_clkevt_shutdown(s - - static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - - mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, - MCHP_PIT64B_IER_PERIOD); -@@ -148,7 +192,7 @@ static int mchp_pit64b_clkevt_set_period - static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, - struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - - mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, - MCHP_PIT64B_IER_PERIOD); -@@ -158,21 +202,16 @@ static int mchp_pit64b_clkevt_set_next_e - - static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - -- writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); -- if (timer->mode & MCHP_PIT64B_MR_SGCLK) -- clk_disable_unprepare(timer->gclk); -- clk_disable_unprepare(timer->pclk); -+ mchp_pit64b_suspend(timer); - } - - static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) - { -- struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); -+ struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); - -- clk_prepare_enable(timer->pclk); -- if (timer->mode & MCHP_PIT64B_MR_SGCLK) -- clk_prepare_enable(timer->gclk); -+ mchp_pit64b_resume(timer); - } - - static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) -@@ -296,20 +335,37 @@ done: - static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, - u32 clk_rate) - { -+ struct mchp_pit64b_clksrc *cs; - int ret; - -+ cs = kzalloc(sizeof(*cs), GFP_KERNEL); -+ if (!cs) -+ return -ENOMEM; -+ - mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); - - mchp_pit64b_cs_base = timer->base; - -- ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate, -- 210, 64, mchp_pit64b_clksrc_read); -+ cs->timer.base = timer->base; -+ cs->timer.pclk = timer->pclk; -+ cs->timer.gclk = timer->gclk; -+ cs->timer.mode = timer->mode; -+ cs->clksrc.name = MCHP_PIT64B_NAME; -+ cs->clksrc.mask = CLOCKSOURCE_MASK(64); -+ cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; -+ cs->clksrc.rating = 210; -+ cs->clksrc.read = mchp_pit64b_clksrc_read; -+ cs->clksrc.suspend = mchp_pit64b_clksrc_suspend; -+ cs->clksrc.resume = mchp_pit64b_clksrc_resume; -+ -+ ret = clocksource_register_hz(&cs->clksrc, clk_rate); - if (ret) { - pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); - - /* Stop timer. */ - writel_relaxed(MCHP_PIT64B_CR_SWRST, - timer->base + MCHP_PIT64B_CR); -+ kfree(cs); - - return ret; - } diff --git a/target/linux/at91/patches-5.10/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch b/target/linux/at91/patches-5.10/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch deleted file mode 100644 index 072e13bcc6..0000000000 --- a/target/linux/at91/patches-5.10/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 0b20c174a17dcfa805ddac1301a5af7298877ec3 Mon Sep 17 00:00:00 2001 -From: Lars-Peter Clausen -Date: Wed, 6 Jan 2021 14:36:48 +0100 -Subject: [PATCH 144/247] ASoC: atmel-pdc: Use managed DMA buffer allocation - -Instead of manually managing its DMA buffers using -dma_{alloc,free}_coherent() lets the sound core take care of this using -managed buffers. - -On one hand this reduces the amount of boiler plate code, but the main -motivation for the change is to use the shared code where possible. This -makes it easier to argue about correctness and that the code does not -contain subtle bugs like data leakage or similar. - -Signed-off-by: Lars-Peter Clausen -Reviewed-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210106133650.13509-1-lars@metafoo.de -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-pcm-pdc.c | 78 ++------------------------------- - 1 file changed, 4 insertions(+), 74 deletions(-) - ---- a/sound/soc/atmel/atmel-pcm-pdc.c -+++ b/sound/soc/atmel/atmel-pcm-pdc.c -@@ -34,86 +34,21 @@ - #include "atmel-pcm.h" - - --static int atmel_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, -- int stream) --{ -- struct snd_pcm_substream *substream = pcm->streams[stream].substream; -- struct snd_dma_buffer *buf = &substream->dma_buffer; -- size_t size = ATMEL_SSC_DMABUF_SIZE; -- -- buf->dev.type = SNDRV_DMA_TYPE_DEV; -- buf->dev.dev = pcm->card->dev; -- buf->private_data = NULL; -- buf->area = dma_alloc_coherent(pcm->card->dev, size, -- &buf->addr, GFP_KERNEL); -- pr_debug("atmel-pcm: alloc dma buffer: area=%p, addr=%p, size=%zu\n", -- (void *)buf->area, (void *)(long)buf->addr, size); -- -- if (!buf->area) -- return -ENOMEM; -- -- buf->bytes = size; -- return 0; --} -- --static int atmel_pcm_mmap(struct snd_soc_component *component, -- struct snd_pcm_substream *substream, -- struct vm_area_struct *vma) --{ -- return remap_pfn_range(vma, vma->vm_start, -- substream->dma_buffer.addr >> PAGE_SHIFT, -- vma->vm_end - vma->vm_start, vma->vm_page_prot); --} -- - static int atmel_pcm_new(struct snd_soc_component *component, - struct snd_soc_pcm_runtime *rtd) - { - struct snd_card *card = rtd->card->snd_card; -- struct snd_pcm *pcm = rtd->pcm; - int ret; - - ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32)); - if (ret) - return ret; - -- if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) { -- pr_debug("atmel-pcm: allocating PCM playback DMA buffer\n"); -- ret = atmel_pcm_preallocate_dma_buffer(pcm, -- SNDRV_PCM_STREAM_PLAYBACK); -- if (ret) -- goto out; -- } -+ snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, -+ card->dev, ATMEL_SSC_DMABUF_SIZE, -+ ATMEL_SSC_DMABUF_SIZE); - -- if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) { -- pr_debug("atmel-pcm: allocating PCM capture DMA buffer\n"); -- ret = atmel_pcm_preallocate_dma_buffer(pcm, -- SNDRV_PCM_STREAM_CAPTURE); -- if (ret) -- goto out; -- } -- out: -- return ret; --} -- --static void atmel_pcm_free(struct snd_soc_component *component, -- struct snd_pcm *pcm) --{ -- struct snd_pcm_substream *substream; -- struct snd_dma_buffer *buf; -- int stream; -- -- for (stream = 0; stream < 2; stream++) { -- substream = pcm->streams[stream].substream; -- if (!substream) -- continue; -- -- buf = &substream->dma_buffer; -- if (!buf->area) -- continue; -- dma_free_coherent(pcm->card->dev, buf->bytes, -- buf->area, buf->addr); -- buf->area = NULL; -- } -+ return 0; - } - - /*--------------------------------------------------------------------------*\ -@@ -210,9 +145,6 @@ static int atmel_pcm_hw_params(struct sn - /* this may get called several times by oss emulation - * with different params */ - -- snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); -- runtime->dma_bytes = params_buffer_bytes(params); -- - prtd->params = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream); - prtd->params->dma_intr_handler = atmel_pcm_dma_irq; - -@@ -384,9 +316,7 @@ static const struct snd_soc_component_dr - .prepare = atmel_pcm_prepare, - .trigger = atmel_pcm_trigger, - .pointer = atmel_pcm_pointer, -- .mmap = atmel_pcm_mmap, - .pcm_construct = atmel_pcm_new, -- .pcm_destruct = atmel_pcm_free, - }; - - int atmel_pcm_pdc_platform_register(struct device *dev) diff --git a/target/linux/at91/patches-5.10/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch b/target/linux/at91/patches-5.10/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch deleted file mode 100644 index af1c01bf90..0000000000 --- a/target/linux/at91/patches-5.10/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch +++ /dev/null @@ -1,141 +0,0 @@ -From f39f2312a68ec0843adba08f9c9182ffa5624190 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 16 Dec 2020 14:57:33 +0200 -Subject: [PATCH 145/247] power: reset: at91-sama5d2_shdwc: add support for - sama7g5 - -Add support for SAMA7G5 by adding proper struct reg_config structure -and since SAMA7G5 is not currently on LPDDR setups the commit also -avoid the mapping of DDR controller. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Sebastian Reichel ---- - drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++------ - 1 file changed, 54 insertions(+), 18 deletions(-) - ---- a/drivers/power/reset/at91-sama5d2_shdwc.c -+++ b/drivers/power/reset/at91-sama5d2_shdwc.c -@@ -78,9 +78,15 @@ struct pmc_reg_config { - u8 mckr; - }; - -+struct ddrc_reg_config { -+ u32 type_offset; -+ u32 type_mask; -+}; -+ - struct reg_config { - struct shdwc_reg_config shdwc; - struct pmc_reg_config pmc; -+ struct ddrc_reg_config ddrc; - }; - - struct shdwc { -@@ -262,6 +268,10 @@ static const struct reg_config sama5d2_r - .pmc = { - .mckr = 0x30, - }, -+ .ddrc = { -+ .type_offset = AT91_DDRSDRC_MDR, -+ .type_mask = AT91_DDRSDRC_MD -+ }, - }; - - static const struct reg_config sam9x60_reg_config = { -@@ -275,6 +285,23 @@ static const struct reg_config sam9x60_r - .pmc = { - .mckr = 0x28, - }, -+ .ddrc = { -+ .type_offset = AT91_DDRSDRC_MDR, -+ .type_mask = AT91_DDRSDRC_MD -+ }, -+}; -+ -+static const struct reg_config sama7g5_reg_config = { -+ .shdwc = { -+ .wkup_pin_input = 0, -+ .mr_rtcwk_shift = 17, -+ .mr_rttwk_shift = 16, -+ .sr_rtcwk_shift = 5, -+ .sr_rttwk_shift = 4, -+ }, -+ .pmc = { -+ .mckr = 0x28, -+ }, - }; - - static const struct of_device_id at91_shdwc_of_match[] = { -@@ -285,6 +312,10 @@ static const struct of_device_id at91_sh - { - .compatible = "microchip,sam9x60-shdwc", - .data = &sam9x60_reg_config, -+ }, -+ { -+ .compatible = "microchip,sama7g5-shdwc", -+ .data = &sama7g5_reg_config, - }, { - /*sentinel*/ - } -@@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_ma - static const struct of_device_id at91_pmc_ids[] = { - { .compatible = "atmel,sama5d2-pmc" }, - { .compatible = "microchip,sam9x60-pmc" }, -+ { .compatible = "microchip,sama7g5-pmc" }, - { /* Sentinel. */ } - }; - -@@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struc - goto clk_disable; - } - -- np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc"); -- if (!np) { -- ret = -ENODEV; -- goto unmap; -- } -+ if (at91_shdwc->rcfg->ddrc.type_mask) { -+ np = of_find_compatible_node(NULL, NULL, -+ "atmel,sama5d3-ddramc"); -+ if (!np) { -+ ret = -ENODEV; -+ goto unmap; -+ } - -- at91_shdwc->mpddrc_base = of_iomap(np, 0); -- of_node_put(np); -+ at91_shdwc->mpddrc_base = of_iomap(np, 0); -+ of_node_put(np); - -- if (!at91_shdwc->mpddrc_base) { -- ret = -ENOMEM; -- goto unmap; -+ if (!at91_shdwc->mpddrc_base) { -+ ret = -ENOMEM; -+ goto unmap; -+ } -+ -+ ddr_type = readl(at91_shdwc->mpddrc_base + -+ at91_shdwc->rcfg->ddrc.type_offset) & -+ at91_shdwc->rcfg->ddrc.type_mask; -+ if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && -+ ddr_type != AT91_DDRSDRC_MD_LPDDR3) { -+ iounmap(at91_shdwc->mpddrc_base); -+ at91_shdwc->mpddrc_base = NULL; -+ } - } - - pm_power_off = at91_poweroff; - -- ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) & -- AT91_DDRSDRC_MD; -- if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 && -- ddr_type != AT91_DDRSDRC_MD_LPDDR3) { -- iounmap(at91_shdwc->mpddrc_base); -- at91_shdwc->mpddrc_base = NULL; -- } -- - return 0; - - unmap: diff --git a/target/linux/at91/patches-5.10/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch b/target/linux/at91/patches-5.10/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch deleted file mode 100644 index 84dea5a48a..0000000000 --- a/target/linux/at91/patches-5.10/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch +++ /dev/null @@ -1,121 +0,0 @@ -From bd819c78346012ae0627b1cd4f6ceb1b51162c71 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 27 Jan 2021 13:45:44 +0200 -Subject: [PATCH 146/247] pinctrl: at91-pio4: add support for slew-rate - -SAMA7G5 supports slew rate configuration. Adapt the driver for this. -For output switching frequencies lower than 50MHz the slew rate needs to -be enabled. Since most of the pins on SAMA7G5 fall into this category -enabled the slew rate by default. - -Signed-off-by: Claudiu Beznea -Acked-by: Ludovic Desroches -Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-at91-pio4.c | 27 +++++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/drivers/pinctrl/pinctrl-at91-pio4.c -+++ b/drivers/pinctrl/pinctrl-at91-pio4.c -@@ -36,6 +36,7 @@ - #define ATMEL_PIO_DIR_MASK BIT(8) - #define ATMEL_PIO_PUEN_MASK BIT(9) - #define ATMEL_PIO_PDEN_MASK BIT(10) -+#define ATMEL_PIO_SR_MASK BIT(11) - #define ATMEL_PIO_IFEN_MASK BIT(12) - #define ATMEL_PIO_IFSCEN_MASK BIT(13) - #define ATMEL_PIO_OPD_MASK BIT(14) -@@ -76,10 +77,12 @@ - * @nbanks: number of PIO banks - * @last_bank_count: number of lines in the last bank (can be less than - * the rest of the banks). -+ * @slew_rate_support: slew rate support - */ - struct atmel_pioctrl_data { - unsigned nbanks; - unsigned last_bank_count; -+ unsigned int slew_rate_support; - }; - - struct atmel_group { -@@ -117,6 +120,7 @@ struct atmel_pin { - * @pm_suspend_backup: backup/restore register values on suspend/resume - * @dev: device entry for the Atmel PIO controller. - * @node: node of the Atmel PIO controller. -+ * @slew_rate_support: slew rate support - */ - struct atmel_pioctrl { - void __iomem *reg_base; -@@ -138,6 +142,7 @@ struct atmel_pioctrl { - } *pm_suspend_backup; - struct device *dev; - struct device_node *node; -+ unsigned int slew_rate_support; - }; - - static const char * const atmel_functions[] = { -@@ -760,6 +765,13 @@ static int atmel_conf_pin_config_group_g - return -EINVAL; - arg = 1; - break; -+ case PIN_CONFIG_SLEW_RATE: -+ if (!atmel_pioctrl->slew_rate_support) -+ return -EOPNOTSUPP; -+ if (!(res & ATMEL_PIO_SR_MASK)) -+ return -EINVAL; -+ arg = 1; -+ break; - case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: - if (!(res & ATMEL_PIO_DRVSTR_MASK)) - return -EINVAL; -@@ -793,6 +805,10 @@ static int atmel_conf_pin_config_group_s - dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", - __func__, pin_id, configs[i]); - -+ /* Keep slew rate enabled by default. */ -+ if (atmel_pioctrl->slew_rate_support) -+ conf |= ATMEL_PIO_SR_MASK; -+ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - conf &= (~ATMEL_PIO_PUEN_MASK); -@@ -850,6 +866,13 @@ static int atmel_conf_pin_config_group_s - ATMEL_PIO_SODR); - } - break; -+ case PIN_CONFIG_SLEW_RATE: -+ if (!atmel_pioctrl->slew_rate_support) -+ break; -+ /* And remove it if explicitly requested. */ -+ if (arg == 0) -+ conf &= ~ATMEL_PIO_SR_MASK; -+ break; - case ATMEL_PIN_CONFIG_DRIVE_STRENGTH: - switch (arg) { - case ATMEL_PIO_DRVSTR_LO: -@@ -901,6 +924,8 @@ static void atmel_conf_pin_config_dbg_sh - seq_printf(s, "%s ", "open-drain"); - if (conf & ATMEL_PIO_SCHMITT_MASK) - seq_printf(s, "%s ", "schmitt"); -+ if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK)) -+ seq_printf(s, "%s ", "slew-rate"); - if (conf & ATMEL_PIO_DRVSTR_MASK) { - switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) { - case ATMEL_PIO_DRVSTR_ME: -@@ -994,6 +1019,7 @@ static const struct atmel_pioctrl_data a - static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { - .nbanks = 5, - .last_bank_count = 8, /* sama7g5 has only PE0 to PE7 */ -+ .slew_rate_support = 1, - }; - - static const struct of_device_id atmel_pctrl_of_match[] = { -@@ -1039,6 +1065,7 @@ static int atmel_pinctrl_probe(struct pl - atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK; - atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count; - } -+ atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support; - - atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(atmel_pioctrl->reg_base)) diff --git a/target/linux/at91/patches-5.10/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch b/target/linux/at91/patches-5.10/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch deleted file mode 100644 index 0be811cc97..0000000000 --- a/target/linux/at91/patches-5.10/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch +++ /dev/null @@ -1,340 +0,0 @@ -From 99629d1ad7e4e03ac3324d36b703220555b65566 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 27 Jan 2021 13:45:45 +0200 -Subject: [PATCH 147/247] pinctrl: at91-pio4: fix "Prefer 'unsigned int' to - bare use of 'unsigned'" - -Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl -warning. - -Signed-off-by: Claudiu Beznea -Acked-by: Ludovic Desroches -Link: https://lore.kernel.org/r/1611747945-29960-4-git-send-email-claudiu.beznea@microchip.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-at91-pio4.c | 110 ++++++++++++++-------------- - 1 file changed, 57 insertions(+), 53 deletions(-) - ---- a/drivers/pinctrl/pinctrl-at91-pio4.c -+++ b/drivers/pinctrl/pinctrl-at91-pio4.c -@@ -80,8 +80,8 @@ - * @slew_rate_support: slew rate support - */ - struct atmel_pioctrl_data { -- unsigned nbanks; -- unsigned last_bank_count; -+ unsigned int nbanks; -+ unsigned int last_bank_count; - unsigned int slew_rate_support; - }; - -@@ -91,11 +91,11 @@ struct atmel_group { - }; - - struct atmel_pin { -- unsigned pin_id; -- unsigned mux; -- unsigned ioset; -- unsigned bank; -- unsigned line; -+ unsigned int pin_id; -+ unsigned int mux; -+ unsigned int ioset; -+ unsigned int bank; -+ unsigned int line; - const char *device; - }; - -@@ -125,16 +125,16 @@ struct atmel_pin { - struct atmel_pioctrl { - void __iomem *reg_base; - struct clk *clk; -- unsigned nbanks; -+ unsigned int nbanks; - struct pinctrl_dev *pinctrl_dev; - struct atmel_group *groups; - const char * const *group_names; - struct atmel_pin **pins; -- unsigned npins; -+ unsigned int npins; - struct gpio_chip *gpio_chip; - struct irq_domain *irq_domain; - int *irqs; -- unsigned *pm_wakeup_sources; -+ unsigned int *pm_wakeup_sources; - struct { - u32 imr; - u32 odsr; -@@ -177,11 +177,11 @@ static void atmel_gpio_irq_ack(struct ir - */ - } - --static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type) -+static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type) - { - struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d); - struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq]; -- unsigned reg; -+ unsigned int reg; - - atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, - BIT(pin->line)); -@@ -268,7 +268,7 @@ static struct irq_chip atmel_gpio_irq_ch - .irq_set_wake = atmel_gpio_irq_set_wake, - }; - --static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -+static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - -@@ -316,11 +316,12 @@ static void atmel_gpio_irq_handler(struc - chained_irq_exit(chip, desc); - } - --static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -+static int atmel_gpio_direction_input(struct gpio_chip *chip, -+ unsigned int offset) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - struct atmel_pin *pin = atmel_pioctrl->pins[offset]; -- unsigned reg; -+ unsigned int reg; - - atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR, - BIT(pin->line)); -@@ -331,11 +332,11 @@ static int atmel_gpio_direction_input(st - return 0; - } - --static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) -+static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - struct atmel_pin *pin = atmel_pioctrl->pins[offset]; -- unsigned reg; -+ unsigned int reg; - - reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR); - -@@ -369,12 +370,13 @@ static int atmel_gpio_get_multiple(struc - return 0; - } - --static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset, -+static int atmel_gpio_direction_output(struct gpio_chip *chip, -+ unsigned int offset, - int value) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - struct atmel_pin *pin = atmel_pioctrl->pins[offset]; -- unsigned reg; -+ unsigned int reg; - - atmel_gpio_write(atmel_pioctrl, pin->bank, - value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR, -@@ -389,7 +391,7 @@ static int atmel_gpio_direction_output(s - return 0; - } - --static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) -+static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) - { - struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip); - struct atmel_pin *pin = atmel_pioctrl->pins[offset]; -@@ -445,11 +447,11 @@ static struct gpio_chip atmel_gpio_chip - - /* --- PINCTRL --- */ - static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev, -- unsigned pin_id) -+ unsigned int pin_id) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned bank = atmel_pioctrl->pins[pin_id]->bank; -- unsigned line = atmel_pioctrl->pins[pin_id]->line; -+ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; -+ unsigned int line = atmel_pioctrl->pins[pin_id]->line; - void __iomem *addr = atmel_pioctrl->reg_base - + bank * ATMEL_PIO_BANK_OFFSET; - -@@ -461,11 +463,11 @@ static unsigned int atmel_pin_config_rea - } - - static void atmel_pin_config_write(struct pinctrl_dev *pctldev, -- unsigned pin_id, u32 conf) -+ unsigned int pin_id, u32 conf) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned bank = atmel_pioctrl->pins[pin_id]->bank; -- unsigned line = atmel_pioctrl->pins[pin_id]->line; -+ unsigned int bank = atmel_pioctrl->pins[pin_id]->bank; -+ unsigned int line = atmel_pioctrl->pins[pin_id]->line; - void __iomem *addr = atmel_pioctrl->reg_base - + bank * ATMEL_PIO_BANK_OFFSET; - -@@ -483,7 +485,7 @@ static int atmel_pctl_get_groups_count(s - } - - static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev, -- unsigned selector) -+ unsigned int selector) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - -@@ -491,19 +493,20 @@ static const char *atmel_pctl_get_group_ - } - - static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev, -- unsigned selector, const unsigned **pins, -- unsigned *num_pins) -+ unsigned int selector, -+ const unsigned int **pins, -+ unsigned int *num_pins) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - -- *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin; -+ *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin; - *num_pins = 1; - - return 0; - } - - static struct atmel_group * --atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin) -+atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - int i; -@@ -524,7 +527,7 @@ static int atmel_pctl_xlate_pinfunc(stru - const char **func_name) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned pin_id, func_id; -+ unsigned int pin_id, func_id; - struct atmel_group *grp; - - pin_id = ATMEL_GET_PIN_NO(pinfunc); -@@ -554,10 +557,10 @@ static int atmel_pctl_xlate_pinfunc(stru - static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, -- unsigned *reserved_maps, -- unsigned *num_maps) -+ unsigned int *reserved_maps, -+ unsigned int *num_maps) - { -- unsigned num_pins, num_configs, reserve; -+ unsigned int num_pins, num_configs, reserve; - unsigned long *configs; - struct property *pins; - u32 pinfunc; -@@ -628,10 +631,10 @@ exit: - static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, -- unsigned *num_maps) -+ unsigned int *num_maps) - { - struct device_node *np; -- unsigned reserved_maps; -+ unsigned int reserved_maps; - int ret; - - *map = NULL; -@@ -679,13 +682,13 @@ static int atmel_pmx_get_functions_count - } - - static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev, -- unsigned selector) -+ unsigned int selector) - { - return atmel_functions[selector]; - } - - static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev, -- unsigned selector, -+ unsigned int selector, - const char * const **groups, - unsigned * const num_groups) - { -@@ -698,11 +701,11 @@ static int atmel_pmx_get_function_groups - } - - static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev, -- unsigned function, -- unsigned group) -+ unsigned int function, -+ unsigned int group) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned pin; -+ unsigned int pin; - u32 conf; - - dev_dbg(pctldev->dev, "enable function %s group %s\n", -@@ -726,13 +729,13 @@ static const struct pinmux_ops atmel_pmx - }; - - static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, -- unsigned group, -+ unsigned int group, - unsigned long *config) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); -- unsigned param = pinconf_to_config_param(*config), arg = 0; -+ unsigned int param = pinconf_to_config_param(*config), arg = 0; - struct atmel_group *grp = atmel_pioctrl->groups + group; -- unsigned pin_id = grp->pin; -+ unsigned int pin_id = grp->pin; - u32 res; - - res = atmel_pin_config_read(pctldev, pin_id); -@@ -786,21 +789,21 @@ static int atmel_conf_pin_config_group_g - } - - static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, -- unsigned group, -+ unsigned int group, - unsigned long *configs, -- unsigned num_configs) -+ unsigned int num_configs) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - struct atmel_group *grp = atmel_pioctrl->groups + group; -- unsigned bank, pin, pin_id = grp->pin; -+ unsigned int bank, pin, pin_id = grp->pin; - u32 mask, conf = 0; - int i; - - conf = atmel_pin_config_read(pctldev, pin_id); - - for (i = 0; i < num_configs; i++) { -- unsigned param = pinconf_to_config_param(configs[i]); -- unsigned arg = pinconf_to_config_argument(configs[i]); -+ unsigned int param = pinconf_to_config_param(configs[i]); -+ unsigned int arg = pinconf_to_config_argument(configs[i]); - - dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", - __func__, pin_id, configs[i]); -@@ -900,7 +903,8 @@ static int atmel_conf_pin_config_group_s - } - - static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, -- struct seq_file *s, unsigned pin_id) -+ struct seq_file *s, -+ unsigned int pin_id) - { - struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev); - u32 conf; -@@ -1108,8 +1112,8 @@ static int atmel_pinctrl_probe(struct pl - return -ENOMEM; - for (i = 0 ; i < atmel_pioctrl->npins; i++) { - struct atmel_group *group = atmel_pioctrl->groups + i; -- unsigned bank = ATMEL_PIO_BANK(i); -- unsigned line = ATMEL_PIO_LINE(i); -+ unsigned int bank = ATMEL_PIO_BANK(i); -+ unsigned int line = ATMEL_PIO_LINE(i); - - atmel_pioctrl->pins[i] = devm_kzalloc(dev, - sizeof(**atmel_pioctrl->pins), GFP_KERNEL); diff --git a/target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch b/target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch deleted file mode 100644 index ee09fe34ff..0000000000 --- a/target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 096f58e564aed56936ef6de42a44c3101e9b8ed1 Mon Sep 17 00:00:00 2001 -From: Atish Patra -Date: Wed, 3 Mar 2021 11:55:49 -0800 -Subject: [PATCH 148/247] net: macb: Add default usrio config to default gem - config - -There is no usrio config defined for default gem config leading to -a kernel panic devices that don't define a data. This issue can be -reprdouced with microchip polar fire soc where compatible string -is defined as "cdns,macb". - -Fixes: edac63861db7 ("add userio bits as platform configuration") - -Signed-off-by: Atish Patra -Acked-by: Nicolas Ferre -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/cadence/macb_main.c | 15 ++++++++------- - 1 file changed, 8 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -3865,6 +3865,13 @@ static int macb_init(struct platform_dev - return 0; - } - -+static const struct macb_usrio_config macb_default_usrio = { -+ .mii = MACB_BIT(MII), -+ .rmii = MACB_BIT(RMII), -+ .rgmii = GEM_BIT(RGMII), -+ .refclk = MACB_BIT(CLKEN), -+}; -+ - #if defined(CONFIG_OF) - /* 1518 rounded up */ - #define AT91ETHER_MAX_RBUFF_SZ 0x600 -@@ -4380,13 +4387,6 @@ static int fu540_c000_init(struct platfo - return macb_init(pdev); - } - --static const struct macb_usrio_config macb_default_usrio = { -- .mii = MACB_BIT(MII), -- .rmii = MACB_BIT(RMII), -- .rgmii = GEM_BIT(RGMII), -- .refclk = MACB_BIT(CLKEN), --}; -- - static const struct macb_usrio_config sama7g5_usrio = { - .mii = 0, - .rmii = 1, -@@ -4535,6 +4535,7 @@ static const struct macb_config default_ - .dma_burst_length = 16, - .clk_init = macb_clk_init, - .init = macb_init, -+ .usrio = &macb_default_usrio, - .jumbo_max_len = 10240, - }; - diff --git a/target/linux/at91/patches-5.10/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch b/target/linux/at91/patches-5.10/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch deleted file mode 100644 index cc7f6583aa..0000000000 --- a/target/linux/at91/patches-5.10/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch +++ /dev/null @@ -1,108 +0,0 @@ -From 746aba88c64e409cbc3757a5f81fad5b5c74bbcc Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Wed, 3 Mar 2021 12:41:49 +0000 -Subject: [PATCH 149/247] ARM: at91: pm: Move prototypes to mutually included - header -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Both the caller and the supplier's source file should have access to -the include file containing the prototypes. - -Fixes the following W=1 kernel build warning(s): - - drivers/pinctrl/pinctrl-at91.c:1637:6: warning: no previous prototype for ‘at91_pinctrl_gpio_suspend’ [-Wmissing-prototypes] - 1637 | void at91_pinctrl_gpio_suspend(void) - | ^~~~~~~~~~~~~~~~~~~~~~~~~ - drivers/pinctrl/pinctrl-at91.c:1661:6: warning: no previous prototype for ‘at91_pinctrl_gpio_resume’ [-Wmissing-prototypes] - 1661 | void at91_pinctrl_gpio_resume(void) - | ^~~~~~~~~~~~~~~~~~~~~~~~ - -Cc: Russell King -Cc: Nicolas Ferre -Cc: Alexandre Belloni -Cc: Ludovic Desroches -Signed-off-by: Lee Jones -Acked-by: Linus Walleij -Signed-off-by: Alexandre Belloni -Link: https://lore.kernel.org/r/20210303124149.3149511-1-lee.jones@linaro.org ---- - arch/arm/mach-at91/pm.c | 19 ++++++++----------- - drivers/pinctrl/pinctrl-at91.c | 2 ++ - include/soc/at91/pm.h | 16 ++++++++++++++++ - 3 files changed, 26 insertions(+), 11 deletions(-) - create mode 100644 include/soc/at91/pm.h - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -17,6 +17,8 @@ - #include - #include - -+#include -+ - #include - #include - #include -@@ -25,17 +27,6 @@ - #include "generic.h" - #include "pm.h" - --/* -- * FIXME: this is needed to communicate between the pinctrl driver and -- * the PM implementation in the machine. Possibly part of the PM -- * implementation should be moved down into the pinctrl driver and get -- * called as part of the generic suspend/resume path. -- */ --#ifdef CONFIG_PINCTRL_AT91 --extern void at91_pinctrl_gpio_suspend(void); --extern void at91_pinctrl_gpio_resume(void); --#endif -- - struct at91_soc_pm { - int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); - int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); -@@ -326,6 +317,12 @@ static void at91_pm_suspend(suspend_stat - static int at91_pm_enter(suspend_state_t state) - { - #ifdef CONFIG_PINCTRL_AT91 -+ /* -+ * FIXME: this is needed to communicate between the pinctrl driver and -+ * the PM implementation in the machine. Possibly part of the PM -+ * implementation should be moved down into the pinctrl driver and get -+ * called as part of the generic suspend/resume path. -+ */ - at91_pinctrl_gpio_suspend(); - #endif - ---- a/drivers/pinctrl/pinctrl-at91.c -+++ b/drivers/pinctrl/pinctrl-at91.c -@@ -23,6 +23,8 @@ - /* Since we request GPIOs from ourself */ - #include - -+#include -+ - #include "pinctrl-at91.h" - #include "core.h" - ---- /dev/null -+++ b/include/soc/at91/pm.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Atmel Power Management -+ * -+ * Copyright (C) 2020 Atmel -+ * -+ * Author: Lee Jones -+ */ -+ -+#ifndef __SOC_ATMEL_PM_H -+#define __SOC_ATMEL_PM_H -+ -+void at91_pinctrl_gpio_suspend(void); -+void at91_pinctrl_gpio_resume(void); -+ -+#endif /* __SOC_ATMEL_PM_H */ diff --git a/target/linux/at91/patches-5.10/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch b/target/linux/at91/patches-5.10/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch deleted file mode 100644 index 174d0b3ced..0000000000 --- a/target/linux/at91/patches-5.10/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch +++ /dev/null @@ -1,46 +0,0 @@ -From d6493e6f1c42f7ad350ea25e11f0e71fc32e6116 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 1 Mar 2021 19:09:00 +0200 -Subject: [PATCH 150/247] ASoC: mchp-i2s-mcc: Add compatible for SAMA7G5 - -Microchip's new SAMA7G5 includes an updated I2S-MCC compatible with the -previous version found on SAM9X60. The new controller includes 8 (4 * 2) -input and output data pins for up to 8 channels for I2S and Left-Justified -formats. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210301170905.835091-3-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/Kconfig | 3 +++ - sound/soc/atmel/mchp-i2s-mcc.c | 3 +++ - 2 files changed, 6 insertions(+) - ---- a/sound/soc/atmel/Kconfig -+++ b/sound/soc/atmel/Kconfig -@@ -126,10 +126,13 @@ config SND_MCHP_SOC_I2S_MCC - Say Y or M if you want to add support for I2S Multi-Channel ASoC - driver on the following Microchip platforms: - - sam9x60 -+ - sama7g5 - - The I2SMCC complies with the Inter-IC Sound (I2S) bus specification - and supports a Time Division Multiplexed (TDM) interface with - external multi-channel audio codecs. -+ Starting with sama7g5, I2S and Left-Justified multi-channel is -+ supported by using multiple data pins, output and input, without TDM. - - config SND_MCHP_SOC_SPDIFTX - tristate "Microchip ASoC driver for boards using S/PDIF TX" ---- a/sound/soc/atmel/mchp-i2s-mcc.c -+++ b/sound/soc/atmel/mchp-i2s-mcc.c -@@ -873,6 +873,9 @@ static const struct of_device_id mchp_i2 - { - .compatible = "microchip,sam9x60-i2smcc", - }, -+ { -+ .compatible = "microchip,sama7g5-i2smcc", -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids); diff --git a/target/linux/at91/patches-5.10/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch b/target/linux/at91/patches-5.10/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch deleted file mode 100644 index 5047e04d5b..0000000000 --- a/target/linux/at91/patches-5.10/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 5bef4e8125d09443b5486971d5550ed285cde4b1 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 1 Mar 2021 19:09:01 +0200 -Subject: [PATCH 151/247] ASoC: mchp-i2s-mcc: Add multi-channel support for I2S - and LEFT_J formats - -The latest I2S-MCC available in SAMA7G5 supports multi-channel for I2S and -Left-Justified formats. For this, the new version uses 8 (4 * 2) input and -output pins, with each pin being responsible for 2 channels. This sums up -to a total of 8 channels for synchronous capture and playback. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210301170905.835091-4-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/mchp-i2s-mcc.c | 38 ++++++++++++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/sound/soc/atmel/mchp-i2s-mcc.c -+++ b/sound/soc/atmel/mchp-i2s-mcc.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -225,6 +226,10 @@ static const struct regmap_config mchp_i - .max_register = MCHP_I2SMCC_VERSION, - }; - -+struct mchp_i2s_mcc_soc_data { -+ unsigned int data_pin_pair_num; -+}; -+ - struct mchp_i2s_mcc_dev { - struct wait_queue_head wq_txrdy; - struct wait_queue_head wq_rxrdy; -@@ -232,6 +237,7 @@ struct mchp_i2s_mcc_dev { - struct regmap *regmap; - struct clk *pclk; - struct clk *gclk; -+ const struct mchp_i2s_mcc_soc_data *soc; - struct snd_dmaengine_dai_dma_data playback; - struct snd_dmaengine_dai_dma_data capture; - unsigned int fmt; -@@ -549,6 +555,17 @@ static int mchp_i2s_mcc_hw_params(struct - } - - if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) { -+ /* for I2S and LEFT_J one pin is needed for every 2 channels */ -+ if (channels > dev->soc->data_pin_pair_num * 2) { -+ dev_err(dev->dev, -+ "unsupported number of audio channels: %d\n", -+ channels); -+ return -EINVAL; -+ } -+ -+ /* enable for interleaved format */ -+ mrb |= MCHP_I2SMCC_MRB_CRAMODE_REGULAR; -+ - switch (channels) { - case 1: - if (is_playback) -@@ -558,6 +575,12 @@ static int mchp_i2s_mcc_hw_params(struct - break; - case 2: - break; -+ case 4: -+ mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1; -+ break; -+ case 8: -+ mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2; -+ break; - default: - dev_err(dev->dev, "unsupported number of audio channels\n"); - return -EINVAL; -@@ -869,12 +892,22 @@ static const struct snd_soc_component_dr - }; - - #ifdef CONFIG_OF -+static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sam9x60 = { -+ .data_pin_pair_num = 1, -+}; -+ -+static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = { -+ .data_pin_pair_num = 4, -+}; -+ - static const struct of_device_id mchp_i2s_mcc_dt_ids[] = { - { - .compatible = "microchip,sam9x60-i2smcc", -+ .data = &mchp_i2s_mcc_sam9x60, - }, - { - .compatible = "microchip,sama7g5-i2smcc", -+ .data = &mchp_i2s_mcc_sama7g5, - }, - { /* sentinel */ } - }; -@@ -932,6 +965,11 @@ static int mchp_i2s_mcc_probe(struct pla - dev->gclk = NULL; - } - -+ dev->soc = of_device_get_match_data(&pdev->dev); -+ if (!dev->soc) { -+ dev_err(&pdev->dev, "failed to get soc data\n"); -+ return -ENODEV; -+ } - dev->dev = &pdev->dev; - dev->regmap = regmap; - platform_set_drvdata(pdev, dev); diff --git a/target/linux/at91/patches-5.10/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch b/target/linux/at91/patches-5.10/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch deleted file mode 100644 index 6d5a15d36b..0000000000 --- a/target/linux/at91/patches-5.10/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch +++ /dev/null @@ -1,108 +0,0 @@ -From 2bbdc5b38603384996271a8817b0578a2360af2f Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 1 Mar 2021 19:09:03 +0200 -Subject: [PATCH 152/247] ASoC: mchp-i2s-mcc: Add support to select TDM pins - -SAMA7G5's I2S-MCC has 4 pairs of DIN/DOUT pins. Since TDM only uses a -single pair of pins for synchronous capture and playback, the controller -needs to be told which of the pair is connected. This can be mentioned -using the "microchip,tdm-data-pair" property from DT. The property is -optional, useful only if TDM is used. If it's missing, DIN/DOUT 0 pins -will be used by default. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210301170905.835091-6-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/mchp-i2s-mcc.c | 52 +++++++++++++++++++++++++++++++--- - 1 file changed, 48 insertions(+), 4 deletions(-) - ---- a/sound/soc/atmel/mchp-i2s-mcc.c -+++ b/sound/soc/atmel/mchp-i2s-mcc.c -@@ -100,6 +100,8 @@ - #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT (7 << 1) - - #define MCHP_I2SMCC_MRA_WIRECFG_MASK GENMASK(5, 4) -+#define MCHP_I2SMCC_MRA_WIRECFG_TDM(pin) (((pin) << 4) & \ -+ MCHP_I2SMCC_MRA_WIRECFG_MASK) - #define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0 (0 << 4) - #define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1 (1 << 4) - #define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2 (2 << 4) -@@ -245,6 +247,7 @@ struct mchp_i2s_mcc_dev { - unsigned int frame_length; - int tdm_slots; - int channels; -+ u8 tdm_data_pair; - unsigned int gclk_use:1; - unsigned int gclk_running:1; - unsigned int tx_rdy:1; -@@ -589,6 +592,8 @@ static int mchp_i2s_mcc_hw_params(struct - if (!frame_length) - frame_length = 2 * params_physical_width(params); - } else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) { -+ mra |= MCHP_I2SMCC_MRA_WIRECFG_TDM(dev->tdm_data_pair); -+ - if (dev->tdm_slots) { - if (channels % 2 && channels * 2 <= dev->tdm_slots) { - /* -@@ -914,6 +919,45 @@ static const struct of_device_id mchp_i2 - MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids); - #endif - -+static int mchp_i2s_mcc_soc_data_parse(struct platform_device *pdev, -+ struct mchp_i2s_mcc_dev *dev) -+{ -+ int err; -+ -+ if (!dev->soc) { -+ dev_err(&pdev->dev, "failed to get soc data\n"); -+ return -ENODEV; -+ } -+ -+ if (dev->soc->data_pin_pair_num == 1) -+ return 0; -+ -+ err = of_property_read_u8(pdev->dev.of_node, "microchip,tdm-data-pair", -+ &dev->tdm_data_pair); -+ if (err < 0 && err != -EINVAL) { -+ dev_err(&pdev->dev, -+ "bad property data for 'microchip,tdm-data-pair': %d", -+ err); -+ return err; -+ } -+ if (err == -EINVAL) { -+ dev_info(&pdev->dev, -+ "'microchip,tdm-data-pair' not found; assuming DIN/DOUT 0 for TDM\n"); -+ dev->tdm_data_pair = 0; -+ } else { -+ if (dev->tdm_data_pair > dev->soc->data_pin_pair_num - 1) { -+ dev_err(&pdev->dev, -+ "invalid value for 'microchip,tdm-data-pair': %d\n", -+ dev->tdm_data_pair); -+ return -EINVAL; -+ } -+ dev_dbg(&pdev->dev, "TMD format on DIN/DOUT %d pins\n", -+ dev->tdm_data_pair); -+ } -+ -+ return 0; -+} -+ - static int mchp_i2s_mcc_probe(struct platform_device *pdev) - { - struct mchp_i2s_mcc_dev *dev; -@@ -966,10 +1010,10 @@ static int mchp_i2s_mcc_probe(struct pla - } - - dev->soc = of_device_get_match_data(&pdev->dev); -- if (!dev->soc) { -- dev_err(&pdev->dev, "failed to get soc data\n"); -- return -ENODEV; -- } -+ err = mchp_i2s_mcc_soc_data_parse(pdev, dev); -+ if (err < 0) -+ return err; -+ - dev->dev = &pdev->dev; - dev->regmap = regmap; - platform_set_drvdata(pdev, dev); diff --git a/target/linux/at91/patches-5.10/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch b/target/linux/at91/patches-5.10/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch deleted file mode 100644 index 24e0e4de4c..0000000000 --- a/target/linux/at91/patches-5.10/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch +++ /dev/null @@ -1,187 +0,0 @@ -From 36bb4f0ab8e7ef69cc11d4d888aa898223b0e901 Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Mon, 1 Mar 2021 19:09:04 +0200 -Subject: [PATCH 153/247] ASoC: mchp-i2s-mcc: Add FIFOs support - -I2S-MCC found on SAMA7G5 includes 2 FIFOs (capture and playback). When -FIFOs are enabled, bits I2SMCC_ISRA.TXLRDYx and I2SMCC_ISRA.TXRRDYx must -not be used. Bits I2SMCC_ISRB.TXFFRDY and I2SMCC_ISRB.RXFFRDY must be used -instead. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210301170905.835091-7-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/mchp-i2s-mcc.c | 76 +++++++++++++++++++++++++--------- - 1 file changed, 56 insertions(+), 20 deletions(-) - ---- a/sound/soc/atmel/mchp-i2s-mcc.c -+++ b/sound/soc/atmel/mchp-i2s-mcc.c -@@ -176,7 +176,7 @@ - */ - #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR (1 << 0) - --#define MCHP_I2SMCC_MRB_FIFOEN BIT(1) -+#define MCHP_I2SMCC_MRB_FIFOEN BIT(4) - - #define MCHP_I2SMCC_MRB_DMACHUNK_MASK GENMASK(9, 8) - #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \ -@@ -230,6 +230,7 @@ static const struct regmap_config mchp_i - - struct mchp_i2s_mcc_soc_data { - unsigned int data_pin_pair_num; -+ bool has_fifo; - }; - - struct mchp_i2s_mcc_dev { -@@ -257,7 +258,7 @@ struct mchp_i2s_mcc_dev { - static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id) - { - struct mchp_i2s_mcc_dev *dev = dev_id; -- u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0; -+ u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0, idrb = 0; - irqreturn_t ret = IRQ_NONE; - - regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra); -@@ -275,24 +276,36 @@ static irqreturn_t mchp_i2s_mcc_interrup - * Tx/Rx ready interrupts are enabled when stopping only, to assure - * availability and to disable clocks if necessary - */ -- idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) | -- MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); -- if (idra) -+ if (dev->soc->has_fifo) { -+ idrb |= pendingb & (MCHP_I2SMCC_INT_TXFFRDY | -+ MCHP_I2SMCC_INT_RXFFRDY); -+ } else { -+ idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) | -+ MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); -+ } -+ if (idra || idrb) - ret = IRQ_HANDLED; - -- if ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) && -- (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) == -- (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) { -+ if ((!dev->soc->has_fifo && -+ (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) && -+ (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) == -+ (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) || -+ (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_TXFFRDY)) { - dev->tx_rdy = 1; - wake_up_interruptible(&dev->wq_txrdy); - } -- if ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) && -- (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) == -- (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) { -+ if ((!dev->soc->has_fifo && -+ (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) && -+ (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) == -+ (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) || -+ (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_RXFFRDY)) { - dev->rx_rdy = 1; - wake_up_interruptible(&dev->wq_rxrdy); - } -- regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra); -+ if (dev->soc->has_fifo) -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, idrb); -+ else -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra); - - return ret; - } -@@ -664,6 +677,10 @@ static int mchp_i2s_mcc_hw_params(struct - } - } - -+ /* enable FIFO if available */ -+ if (dev->soc->has_fifo) -+ mrb |= MCHP_I2SMCC_MRB_FIFOEN; -+ - /* - * If we are already running, the wanted setup must be - * the same with the one that's currently ongoing -@@ -726,8 +743,13 @@ static int mchp_i2s_mcc_hw_free(struct s - if (err == 0) { - dev_warn_once(dev->dev, - "Timeout waiting for Tx ready\n"); -- regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, -- MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)); -+ if (dev->soc->has_fifo) -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, -+ MCHP_I2SMCC_INT_TXFFRDY); -+ else -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, -+ MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)); -+ - dev->tx_rdy = 1; - } - } else { -@@ -737,8 +759,12 @@ static int mchp_i2s_mcc_hw_free(struct s - if (err == 0) { - dev_warn_once(dev->dev, - "Timeout waiting for Rx ready\n"); -- regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, -- MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); -+ if (dev->soc->has_fifo) -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, -+ MCHP_I2SMCC_INT_RXFFRDY); -+ else -+ regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, -+ MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)); - dev->rx_rdy = 1; - } - } -@@ -765,7 +791,7 @@ static int mchp_i2s_mcc_trigger(struct s - struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai); - bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); - u32 cr = 0; -- u32 iera = 0; -+ u32 iera = 0, ierb = 0; - u32 sr; - int err; - -@@ -789,7 +815,10 @@ static int mchp_i2s_mcc_trigger(struct s - * Enable Tx Ready interrupts on all channels - * to assure all data is sent - */ -- iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels); -+ if (dev->soc->has_fifo) -+ ierb = MCHP_I2SMCC_INT_TXFFRDY; -+ else -+ iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels); - } else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) { - cr = MCHP_I2SMCC_CR_RXDIS; - dev->rx_rdy = 0; -@@ -797,7 +826,10 @@ static int mchp_i2s_mcc_trigger(struct s - * Enable Rx Ready interrupts on all channels - * to assure all data is received - */ -- iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels); -+ if (dev->soc->has_fifo) -+ ierb = MCHP_I2SMCC_INT_RXFFRDY; -+ else -+ iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels); - } - break; - default: -@@ -815,7 +847,10 @@ static int mchp_i2s_mcc_trigger(struct s - } - } - -- regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera); -+ if (dev->soc->has_fifo) -+ regmap_write(dev->regmap, MCHP_I2SMCC_IERB, ierb); -+ else -+ regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera); - regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr); - - return 0; -@@ -903,6 +938,7 @@ static struct mchp_i2s_mcc_soc_data mchp - - static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = { - .data_pin_pair_num = 4, -+ .has_fifo = true, - }; - - static const struct of_device_id mchp_i2s_mcc_dt_ids[] = { diff --git a/target/linux/at91/patches-5.10/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch b/target/linux/at91/patches-5.10/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch deleted file mode 100644 index c61e6b1c90..0000000000 --- a/target/linux/at91/patches-5.10/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch +++ /dev/null @@ -1,49 +0,0 @@ -From dc07cbae6e96843d26e8f10b16e901620bd16462 Mon Sep 17 00:00:00 2001 -From: Tudor Ambarus -Date: Fri, 9 Apr 2021 11:25:22 +0300 -Subject: [PATCH 154/247] pinctrl: at91-pio4: Fix slew rate disablement - -The slew rate was enabled by default for each configuration of the -pin. In case the pin had more than one configuration, even if -we set the slew rate as disabled in the device tree, the next pin -configuration would set again the slew rate enabled by default, -overwriting the slew rate disablement. -Instead of enabling the slew rate by default for each pin configuration, -enable the slew rate by default just once per pin, regardless of the -number of configurations. This way the slew rate disablement will also -work for cases where pins have multiple configurations. - -Fixes: c709135e576b ("pinctrl: at91-pio4: add support for slew-rate") -Signed-off-by: Tudor Ambarus -Reviewed-by: Claudiu Beznea -Acked-by: Ludovic Desroches -Link: https://lore.kernel.org/r/20210409082522.625168-1-tudor.ambarus@microchip.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/pinctrl-at91-pio4.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/pinctrl/pinctrl-at91-pio4.c -+++ b/drivers/pinctrl/pinctrl-at91-pio4.c -@@ -801,6 +801,10 @@ static int atmel_conf_pin_config_group_s - - conf = atmel_pin_config_read(pctldev, pin_id); - -+ /* Keep slew rate enabled by default. */ -+ if (atmel_pioctrl->slew_rate_support) -+ conf |= ATMEL_PIO_SR_MASK; -+ - for (i = 0; i < num_configs; i++) { - unsigned int param = pinconf_to_config_param(configs[i]); - unsigned int arg = pinconf_to_config_argument(configs[i]); -@@ -808,10 +812,6 @@ static int atmel_conf_pin_config_group_s - dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n", - __func__, pin_id, configs[i]); - -- /* Keep slew rate enabled by default. */ -- if (atmel_pioctrl->slew_rate_support) -- conf |= ATMEL_PIO_SR_MASK; -- - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - conf &= (~ATMEL_PIO_PUEN_MASK); diff --git a/target/linux/at91/patches-5.10/155-media-atmel-properly-get-pm_runtime.patch b/target/linux/at91/patches-5.10/155-media-atmel-properly-get-pm_runtime.patch deleted file mode 100644 index 58f90db46d..0000000000 --- a/target/linux/at91/patches-5.10/155-media-atmel-properly-get-pm_runtime.patch +++ /dev/null @@ -1,159 +0,0 @@ -From c7660cc977621c4a14d870d523918df067f0db39 Mon Sep 17 00:00:00 2001 -From: Mauro Carvalho Chehab -Date: Fri, 23 Apr 2021 16:47:42 +0200 -Subject: [PATCH 155/247] media: atmel: properly get pm_runtime - -There are several issues in the way the atmel driver handles -pm_runtime_get_sync(): - -- it doesn't check return codes; -- it doesn't properly decrement the usage_count on all places; -- it starts streaming even if pm_runtime_get_sync() fails. -- while it tries to get pm_runtime at the clock enable logic, - it doesn't check if the operation was suceeded. - -Replace all occurrences of it to use the new kAPI: -pm_runtime_resume_and_get(), which ensures that, if the -return code is not negative, the usage_count was incremented. - -With that, add additional checks when this is called, in order -to ensure that errors will be properly addressed. - -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 30 ++++++++++++++----- - drivers/media/platform/atmel/atmel-isi.c | 19 +++++++++--- - 2 files changed, 38 insertions(+), 11 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -294,9 +294,13 @@ static int isc_wait_clk_stable(struct cl - static int isc_clk_prepare(struct clk_hw *hw) - { - struct isc_clk *isc_clk = to_isc_clk(hw); -+ int ret; - -- if (isc_clk->id == ISC_ISPCK) -- pm_runtime_get_sync(isc_clk->dev); -+ if (isc_clk->id == ISC_ISPCK) { -+ ret = pm_runtime_resume_and_get(isc_clk->dev); -+ if (ret < 0) -+ return ret; -+ } - - return isc_wait_clk_stable(hw); - } -@@ -353,9 +357,13 @@ static int isc_clk_is_enabled(struct clk - { - struct isc_clk *isc_clk = to_isc_clk(hw); - u32 status; -+ int ret; - -- if (isc_clk->id == ISC_ISPCK) -- pm_runtime_get_sync(isc_clk->dev); -+ if (isc_clk->id == ISC_ISPCK) { -+ ret = pm_runtime_resume_and_get(isc_clk->dev); -+ if (ret < 0) -+ return 0; -+ } - - regmap_read(isc_clk->regmap, ISC_CLKSR, &status); - -@@ -807,7 +815,12 @@ static int isc_start_streaming(struct vb - goto err_start_stream; - } - -- pm_runtime_get_sync(isc->dev); -+ ret = pm_runtime_resume_and_get(isc->dev); -+ if (ret < 0) { -+ v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n", -+ ret); -+ goto err_pm_get; -+ } - - ret = isc_configure(isc); - if (unlikely(ret)) -@@ -838,7 +851,7 @@ static int isc_start_streaming(struct vb - - err_configure: - pm_runtime_put_sync(isc->dev); -- -+err_pm_get: - v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); - - err_start_stream: -@@ -1809,6 +1822,7 @@ static void isc_awb_work(struct work_str - u32 baysel; - unsigned long flags; - u32 min, max; -+ int ret; - - /* streaming is not active anymore */ - if (isc->stop) -@@ -1831,7 +1845,9 @@ static void isc_awb_work(struct work_str - ctrls->hist_id = hist_id; - baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT; - -- pm_runtime_get_sync(isc->dev); -+ ret = pm_runtime_resume_and_get(isc->dev); -+ if (ret < 0) -+ return; - - /* - * only update if we have all the required histograms and controls ---- a/drivers/media/platform/atmel/atmel-isi.c -+++ b/drivers/media/platform/atmel/atmel-isi.c -@@ -423,7 +423,9 @@ static int start_streaming(struct vb2_qu - struct frame_buffer *buf, *node; - int ret; - -- pm_runtime_get_sync(isi->dev); -+ ret = pm_runtime_resume_and_get(isi->dev); -+ if (ret < 0) -+ return ret; - - /* Enable stream on the sub device */ - ret = v4l2_subdev_call(isi->entity.subdev, video, s_stream, 1); -@@ -783,9 +785,10 @@ static int isi_enum_frameintervals(struc - return 0; - } - --static void isi_camera_set_bus_param(struct atmel_isi *isi) -+static int isi_camera_set_bus_param(struct atmel_isi *isi) - { - u32 cfg1 = 0; -+ int ret; - - /* set bus param for ISI */ - if (isi->pdata.hsync_act_low) -@@ -802,12 +805,16 @@ static void isi_camera_set_bus_param(str - cfg1 |= ISI_CFG1_THMASK_BEATS_16; - - /* Enable PM and peripheral clock before operate isi registers */ -- pm_runtime_get_sync(isi->dev); -+ ret = pm_runtime_resume_and_get(isi->dev); -+ if (ret < 0) -+ return ret; - - isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS); - isi_writel(isi, ISI_CFG1, cfg1); - - pm_runtime_put(isi->dev); -+ -+ return 0; - } - - /* -----------------------------------------------------------------------*/ -@@ -1086,7 +1093,11 @@ static int isi_graph_notify_complete(str - dev_err(isi->dev, "No supported mediabus format found\n"); - return ret; - } -- isi_camera_set_bus_param(isi); -+ ret = isi_camera_set_bus_param(isi); -+ if (ret) { -+ dev_err(isi->dev, "Can't wake up device\n"); -+ return ret; -+ } - - ret = isi_set_default_fmt(isi); - if (ret) { diff --git a/target/linux/at91/patches-5.10/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch b/target/linux/at91/patches-5.10/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch deleted file mode 100644 index f8bdcbef23..0000000000 --- a/target/linux/at91/patches-5.10/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch +++ /dev/null @@ -1,32 +0,0 @@ -From b074b4695004b793a9199716295cb76da6c41686 Mon Sep 17 00:00:00 2001 -From: Jiapeng Chong -Date: Mon, 17 May 2021 12:07:48 +0200 -Subject: [PATCH 156/247] media: atmel: atmel-isc: Remove redundant assignment - to i - -Variable i is being assigned a value however the assignment is -never read, so this redundant assignment can be removed. - -Clean up the following clang-analyzer warning: - -drivers/media/platform/atmel/atmel-isc-base.c:975:2: warning: Value -stored to 'i' is never read [clang-analyzer-deadcode.DeadStores]. - -Reported-by: Abaci Robot -Signed-off-by: Jiapeng Chong -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -972,7 +972,6 @@ static int isc_enum_fmt_vid_cap(struct f - - index -= ARRAY_SIZE(controller_formats); - -- i = 0; - supported_index = 0; - - for (i = 0; i < ARRAY_SIZE(formats_list); i++) { diff --git a/target/linux/at91/patches-5.10/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch b/target/linux/at91/patches-5.10/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch deleted file mode 100644 index 6f2d5879c7..0000000000 --- a/target/linux/at91/patches-5.10/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch +++ /dev/null @@ -1,187 +0,0 @@ -From c3f54d192dc7344c5216a3628b67c4bbccbf8c3c Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:56:59 +0200 -Subject: [PATCH 157/247] media: atmel: atmel-isc: specialize gamma table into - product specific - -Separate the gamma table from the isc base file into the specific sama5d2 -product file. -Add a pointer to the gamma table and entries count inside the platform -driver specific struct. - -[hverkuil: made isc_sama5d2_gamma_table static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 47 ++----------------- - drivers/media/platform/atmel/atmel-isc.h | 11 +++-- - .../media/platform/atmel/atmel-sama5d2-isc.c | 45 ++++++++++++++++++ - 3 files changed, 56 insertions(+), 47 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -176,48 +176,6 @@ struct isc_format formats_list[] = { - - }; - --/* Gamma table with gamma 1/2.2 */ --const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = { -- /* 0 --> gamma 1/1.8 */ -- { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A, -- 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012, -- 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F, -- 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E, -- 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C, -- 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B, -- 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A, -- 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A, -- 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A, -- 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009, -- 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 }, -- -- /* 1 --> gamma 1/2 */ -- { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B, -- 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013, -- 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F, -- 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D, -- 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B, -- 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A, -- 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A, -- 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009, -- 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009, -- 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009, -- 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 }, -- -- /* 2 --> gamma 1/2.2 */ -- { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B, -- 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012, -- 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F, -- 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C, -- 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B, -- 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A, -- 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009, -- 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009, -- 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008, -- 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007, -- 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 }, --}; -- - #define ISC_IS_FORMAT_RAW(mbus_code) \ - (((mbus_code) & 0xf000) == 0x3000) - -@@ -691,7 +649,7 @@ static void isc_set_pipeline(struct isc_ - - regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL); - -- gamma = &isc_gamma_table[ctrls->gamma_index][0]; -+ gamma = &isc->gamma_table[ctrls->gamma_index][0]; - regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES); - regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); - regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); -@@ -2085,7 +2043,8 @@ static int isc_ctrl_init(struct isc_devi - - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); -- v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2); -+ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, -+ isc->gamma_max); - isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, - V4L2_CID_AUTO_WHITE_BALANCE, - 0, 1, 1, 1); ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -186,6 +186,10 @@ struct isc_ctrls { - * - * @current_subdev: current subdevice: the sensor - * @subdev_entities: list of subdevice entitites -+ * -+ * @gamma_table: pointer to the table with gamma values, has -+ * gamma_max sets of GAMMA_ENTRIES entries each -+ * @gamma_max: maximum number of sets of inside the gamma_table - */ - struct isc_device { - struct regmap *regmap; -@@ -244,16 +248,17 @@ struct isc_device { - struct v4l2_ctrl *gr_off_ctrl; - struct v4l2_ctrl *gb_off_ctrl; - }; --}; - --#define GAMMA_MAX 2 - #define GAMMA_ENTRIES 64 -+ /* pointer to the defined gamma table */ -+ const u32 (*gamma_table)[GAMMA_ENTRIES]; -+ u32 gamma_max; -+}; - - #define ATMEL_ISC_NAME "atmel-isc" - - extern struct isc_format formats_list[]; - extern const struct isc_format controller_formats[]; --extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES]; - extern const struct regmap_config isc_regmap_config; - extern const struct v4l2_async_notifier_operations isc_async_ops; - ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -54,6 +54,48 @@ - - #define ISC_CLK_MAX_DIV 255 - -+/* Gamma table with gamma 1/2.2 */ -+static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { -+ /* 0 --> gamma 1/1.8 */ -+ { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A, -+ 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012, -+ 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F, -+ 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E, -+ 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C, -+ 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B, -+ 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A, -+ 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A, -+ 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A, -+ 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009, -+ 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 }, -+ -+ /* 1 --> gamma 1/2 */ -+ { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B, -+ 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013, -+ 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F, -+ 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D, -+ 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B, -+ 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A, -+ 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A, -+ 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009, -+ 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009, -+ 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009, -+ 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 }, -+ -+ /* 2 --> gamma 1/2.2 */ -+ { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B, -+ 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012, -+ 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F, -+ 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C, -+ 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B, -+ 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A, -+ 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009, -+ 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009, -+ 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008, -+ 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007, -+ 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 }, -+}; -+ - static int isc_parse_dt(struct device *dev, struct isc_device *isc) - { - struct device_node *np = dev->of_node; -@@ -171,6 +213,9 @@ static int atmel_isc_probe(struct platfo - return ret; - } - -+ isc->gamma_table = isc_sama5d2_gamma_table; -+ isc->gamma_max = 2; -+ - ret = isc_pipeline_init(isc); - if (ret) - return ret; diff --git a/target/linux/at91/patches-5.10/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch b/target/linux/at91/patches-5.10/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch deleted file mode 100644 index 5fd7be8098..0000000000 --- a/target/linux/at91/patches-5.10/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 0576e163d93d08a1ed112bd23f40478ef3fd323d Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:00 +0200 -Subject: [PATCH 158/247] media: atmel: atmel-isc: specialize driver name - constant - -The driver name constant must defined based on product driver, thus moving -the constant directly where it's required. This will allow each ISC based -product to define it's own name. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- - drivers/media/platform/atmel/atmel-isc.h | 2 -- - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 4 ++-- - 3 files changed, 4 insertions(+), 6 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -909,7 +909,7 @@ static int isc_querycap(struct file *fil - { - struct isc_device *isc = video_drvdata(file); - -- strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver)); -+ strscpy(cap->driver, "microchip-isc", sizeof(cap->driver)); - strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card)); - snprintf(cap->bus_info, sizeof(cap->bus_info), - "platform:%s", isc->v4l2_dev.name); -@@ -2261,7 +2261,7 @@ static int isc_async_complete(struct v4l - } - - /* Register video device */ -- strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name)); -+ strscpy(vdev->name, "microchip-isc", sizeof(vdev->name)); - vdev->release = video_device_release_empty; - vdev->fops = &isc_fops; - vdev->ioctl_ops = &isc_ioctl_ops; ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -255,8 +255,6 @@ struct isc_device { - u32 gamma_max; - }; - --#define ATMEL_ISC_NAME "atmel-isc" -- - extern struct isc_format formats_list[]; - extern const struct isc_format controller_formats[]; - extern const struct regmap_config isc_regmap_config; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -206,7 +206,7 @@ static int atmel_isc_probe(struct platfo - return irq; - - ret = devm_request_irq(dev, irq, isc_interrupt, 0, -- ATMEL_ISC_NAME, isc); -+ "atmel-sama5d2-isc", isc); - if (ret < 0) { - dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", - irq, ret); -@@ -378,7 +378,7 @@ static struct platform_driver atmel_isc_ - .probe = atmel_isc_probe, - .remove = atmel_isc_remove, - .driver = { -- .name = ATMEL_ISC_NAME, -+ .name = "atmel-sama5d2-isc", - .pm = &atmel_isc_dev_pm_ops, - .of_match_table = of_match_ptr(atmel_isc_of_match), - }, diff --git a/target/linux/at91/patches-5.10/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch b/target/linux/at91/patches-5.10/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch deleted file mode 100644 index c6ca456a56..0000000000 --- a/target/linux/at91/patches-5.10/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch +++ /dev/null @@ -1,45 +0,0 @@ -From de8fa25cdf3726c83ac0d7b3b1e28bcb6334aadd Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:01 +0200 -Subject: [PATCH 159/247] media: atmel: atmel-isc: add checks for limiting - frame sizes - -When calling the subdev, certain subdev drivers will overwrite the -frame size and adding sizes which are beyond the ISC's capabilities. -Thus we need to ensure the frame size is cropped to the maximum caps. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -1338,6 +1338,12 @@ static int isc_try_fmt(struct isc_device - - v4l2_fill_pix_format(pixfmt, &format.format); - -+ /* Limit to Atmel ISC hardware capabilities */ -+ if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -+ pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -+ if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -+ pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ - pixfmt->field = V4L2_FIELD_NONE; - pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; - pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height; -@@ -1373,6 +1379,12 @@ static int isc_set_fmt(struct isc_device - if (ret < 0) - return ret; - -+ /* Limit to Atmel ISC hardware capabilities */ -+ if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -+ pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -+ if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -+ pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ - isc->fmt = *f; - - if (isc->try_config.sd_format && isc->config.sd_format && diff --git a/target/linux/at91/patches-5.10/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch b/target/linux/at91/patches-5.10/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch deleted file mode 100644 index afa89ed916..0000000000 --- a/target/linux/at91/patches-5.10/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch +++ /dev/null @@ -1,131 +0,0 @@ -From b51819e17260af2ecc152b7dcd61e63bcaa35edf Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:02 +0200 -Subject: [PATCH 160/247] media: atmel: atmel-isc: specialize max width and max - height - -Move the max width and max height constants to the product specific driver -and have them in the device struct. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 28 +++++++++---------- - drivers/media/platform/atmel/atmel-isc.h | 9 ++++-- - .../media/platform/atmel/atmel-sama5d2-isc.c | 7 +++-- - 3 files changed, 25 insertions(+), 19 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -1216,8 +1216,8 @@ static void isc_try_fse(struct isc_devic - * just use the maximum ISC can receive. - */ - if (ret) { -- pad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH; -- pad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT; -+ pad_cfg->try_crop.width = isc->max_width; -+ pad_cfg->try_crop.height = isc->max_height; - } else { - pad_cfg->try_crop.width = fse.max_width; - pad_cfg->try_crop.height = fse.max_height; -@@ -1294,10 +1294,10 @@ static int isc_try_fmt(struct isc_device - isc->try_config.sd_format = sd_fmt; - - /* Limit to Atmel ISC hardware capabilities */ -- if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -- pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -- if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -- pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ if (pixfmt->width > isc->max_width) -+ pixfmt->width = isc->max_width; -+ if (pixfmt->height > isc->max_height) -+ pixfmt->height = isc->max_height; - - /* - * The mbus format is the one the subdev outputs. -@@ -1339,10 +1339,10 @@ static int isc_try_fmt(struct isc_device - v4l2_fill_pix_format(pixfmt, &format.format); - - /* Limit to Atmel ISC hardware capabilities */ -- if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -- pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -- if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -- pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ if (pixfmt->width > isc->max_width) -+ pixfmt->width = isc->max_width; -+ if (pixfmt->height > isc->max_height) -+ pixfmt->height = isc->max_height; - - pixfmt->field = V4L2_FIELD_NONE; - pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; -@@ -1380,10 +1380,10 @@ static int isc_set_fmt(struct isc_device - return ret; - - /* Limit to Atmel ISC hardware capabilities */ -- if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) -- pixfmt->width = ISC_MAX_SUPPORT_WIDTH; -- if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) -- pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; -+ if (f->fmt.pix.width > isc->max_width) -+ f->fmt.pix.width = isc->max_width; -+ if (f->fmt.pix.height > isc->max_height) -+ f->fmt.pix.height = isc->max_height; - - isc->fmt = *f; - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -10,9 +10,6 @@ - */ - #ifndef _ATMEL_ISC_H_ - --#define ISC_MAX_SUPPORT_WIDTH 2592 --#define ISC_MAX_SUPPORT_HEIGHT 1944 -- - #define ISC_CLK_MAX_DIV 255 - - enum isc_clk_id { -@@ -190,6 +187,9 @@ struct isc_ctrls { - * @gamma_table: pointer to the table with gamma values, has - * gamma_max sets of GAMMA_ENTRIES entries each - * @gamma_max: maximum number of sets of inside the gamma_table -+ * -+ * @max_width: maximum frame width, dependent on the internal RAM -+ * @max_height: maximum frame height, dependent on the internal RAM - */ - struct isc_device { - struct regmap *regmap; -@@ -253,6 +253,9 @@ struct isc_device { - /* pointer to the defined gamma table */ - const u32 (*gamma_table)[GAMMA_ENTRIES]; - u32 gamma_max; -+ -+ u32 max_width; -+ u32 max_height; - }; - - extern struct isc_format formats_list[]; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -49,8 +49,8 @@ - #include "atmel-isc-regs.h" - #include "atmel-isc.h" - --#define ISC_MAX_SUPPORT_WIDTH 2592 --#define ISC_MAX_SUPPORT_HEIGHT 1944 -+#define ISC_SAMA5D2_MAX_SUPPORT_WIDTH 2592 -+#define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT 1944 - - #define ISC_CLK_MAX_DIV 255 - -@@ -216,6 +216,9 @@ static int atmel_isc_probe(struct platfo - isc->gamma_table = isc_sama5d2_gamma_table; - isc->gamma_max = 2; - -+ isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; -+ isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; -+ - ret = isc_pipeline_init(isc); - if (ret) - return ret; diff --git a/target/linux/at91/patches-5.10/161-media-atmel-atmel-isc-specialize-dma-cfg.patch b/target/linux/at91/patches-5.10/161-media-atmel-atmel-isc-specialize-dma-cfg.patch deleted file mode 100644 index 410831771e..0000000000 --- a/target/linux/at91/patches-5.10/161-media-atmel-atmel-isc-specialize-dma-cfg.patch +++ /dev/null @@ -1,60 +0,0 @@ -From c42305f52560a1be6fc25a2f23579c7b323de654 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:03 +0200 -Subject: [PATCH 161/247] media: atmel: atmel-isc: specialize dma cfg - -The dma configuration (DCFG) is specific to the product. -Move this configuration in the product specific driver, and add the -field inside the driver struct. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 3 +-- - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 3 +++ - 3 files changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -724,8 +724,7 @@ static int isc_configure(struct isc_devi - rlp_mode = isc->config.rlp_cfg_mode; - pipeline = isc->config.bits_pipeline; - -- dcfg = isc->config.dcfg_imode | -- ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; -+ dcfg = isc->config.dcfg_imode | isc->dcfg; - - pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE; - mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -149,6 +149,7 @@ struct isc_ctrls { - * @hclock: Hclock clock input (refer datasheet) - * @ispck: iscpck clock (refer datasheet) - * @isc_clks: ISC clocks -+ * @dcfg: DMA master configuration, architecture dependent - * - * @dev: Registered device driver - * @v4l2_dev: v4l2 registered device -@@ -196,6 +197,7 @@ struct isc_device { - struct clk *hclock; - struct clk *ispck; - struct isc_clk isc_clks[2]; -+ u32 dcfg; - - struct device *dev; - struct v4l2_device v4l2_dev; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -219,6 +219,9 @@ static int atmel_isc_probe(struct platfo - isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; - isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; - -+ /* sama5d2-isc - 8 bits per beat */ -+ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; -+ - ret = isc_pipeline_init(isc); - if (ret) - return ret; diff --git a/target/linux/at91/patches-5.10/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch b/target/linux/at91/patches-5.10/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch deleted file mode 100644 index 7b8e8ed697..0000000000 --- a/target/linux/at91/patches-5.10/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 6ccda3cf6a102ac4f6e21386d0dd0fedfb066525 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:04 +0200 -Subject: [PATCH 162/247] media: atmel: atmel-isc: extract CSC submodule config - into separate function - -The CSC submodule is a part of the atmel-isc pipeline, and stands for -Color Space Conversion. It is used to apply a matrix transformation to -RGB pixels to convert them to the YUV components. -The CSC submodule should be initialized in the product specific driver -as it's product specific. Other products can implement it differently. - -[hverkuil: made isc_sama5d2_config_csc static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 8 +------- - drivers/media/platform/atmel/atmel-isc.h | 7 +++++++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 15 +++++++++++++++ - 3 files changed, 23 insertions(+), 7 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -654,13 +654,7 @@ static void isc_set_pipeline(struct isc_ - regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); - regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); - -- /* Convert RGB to YUV */ -- regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); -- regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); -- regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); -- regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); -- regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); -- regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); -+ isc->config_csc(isc); - - regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness); - regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast); ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -191,6 +191,9 @@ struct isc_ctrls { - * - * @max_width: maximum frame width, dependent on the internal RAM - * @max_height: maximum frame height, dependent on the internal RAM -+ * -+ * @config_csc: pointer to a function that initializes product -+ * specific CSC module - */ - struct isc_device { - struct regmap *regmap; -@@ -258,6 +261,10 @@ struct isc_device { - - u32 max_width; - u32 max_height; -+ -+ struct { -+ void (*config_csc)(struct isc_device *isc); -+ }; - }; - - extern struct isc_format formats_list[]; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -54,6 +54,19 @@ - - #define ISC_CLK_MAX_DIV 255 - -+static void isc_sama5d2_config_csc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Convert RGB to YUV */ -+ regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); -+ regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); -+ regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); -+ regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); -+ regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); -+ regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -219,6 +232,8 @@ static int atmel_isc_probe(struct platfo - isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; - isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; - -+ isc->config_csc = isc_sama5d2_config_csc; -+ - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; - diff --git a/target/linux/at91/patches-5.10/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch b/target/linux/at91/patches-5.10/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch deleted file mode 100644 index 832465363b..0000000000 --- a/target/linux/at91/patches-5.10/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 19dd7c72c6c457c147133a7dad8ab28d35538f99 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:05 +0200 -Subject: [PATCH 163/247] media: atmel: atmel-isc-base: add id to clock debug - message - -Add the clock id to the debug message regarding clock setup - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -281,8 +281,8 @@ static int isc_clk_enable(struct clk_hw - unsigned long flags; - unsigned int status; - -- dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n", -- __func__, isc_clk->div, isc_clk->parent_id); -+ dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n", -+ __func__, id, isc_clk->div, isc_clk->parent_id); - - spin_lock_irqsave(&isc_clk->lock, flags); - regmap_update_bits(regmap, ISC_CLKCFG, diff --git a/target/linux/at91/patches-5.10/164-media-atmel-atmel-isc-create-register-offsets-struct.patch b/target/linux/at91/patches-5.10/164-media-atmel-atmel-isc-create-register-offsets-struct.patch deleted file mode 100644 index bb599618d1..0000000000 --- a/target/linux/at91/patches-5.10/164-media-atmel-atmel-isc-create-register-offsets-struct.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 7a1b082cd81a2496e2687cee7ea1ef04a3020f48 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:06 +0200 -Subject: [PATCH 164/247] media: atmel: atmel-isc: create register offsets - struct - -Create a struct that holds register offsets that are product specific. -Add initially the CSC register. -This allows each product that contains a variant of the ISC to add their -own register offset. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 2 +- - drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ - drivers/media/platform/atmel/atmel-isc.h | 12 +++++++++++ - .../media/platform/atmel/atmel-sama5d2-isc.c | 20 +++++++++++++------ - 4 files changed, 30 insertions(+), 7 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2326,7 +2326,7 @@ int isc_pipeline_init(struct isc_device - REG_FIELD(ISC_GAM_CTRL, 1, 1), - REG_FIELD(ISC_GAM_CTRL, 2, 2), - REG_FIELD(ISC_GAM_CTRL, 3, 3), -- REG_FIELD(ISC_CSC_CTRL, 0, 0), -+ REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), - REG_FIELD(ISC_CBC_CTRL, 0, 0), - REG_FIELD(ISC_SUB422_CTRL, 0, 0), - REG_FIELD(ISC_SUB420_CTRL, 0, 0), ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -153,6 +153,9 @@ - /* ISC_Gamma Correction Green Entry Register */ - #define ISC_GAM_RENTRY 0x00000298 - -+/* Offset for CSC register specific to sama5d2 product */ -+#define ISC_SAMA5D2_CSC_OFFSET 0 -+ - /* Color Space Conversion Control Register */ - #define ISC_CSC_CTRL 0x00000398 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -144,6 +144,14 @@ struct isc_ctrls { - #define ISC_PIPE_LINE_NODE_NUM 11 - - /* -+ * struct isc_reg_offsets - ISC device register offsets -+ * @csc: Offset for the CSC register -+ */ -+struct isc_reg_offsets { -+ u32 csc; -+}; -+ -+/* - * struct isc_device - ISC device driver data/config struct - * @regmap: Register map - * @hclock: Hclock clock input (refer datasheet) -@@ -194,6 +202,8 @@ struct isc_ctrls { - * - * @config_csc: pointer to a function that initializes product - * specific CSC module -+ * -+ * @offsets: struct holding the product specific register offsets - */ - struct isc_device { - struct regmap *regmap; -@@ -265,6 +275,8 @@ struct isc_device { - struct { - void (*config_csc)(struct isc_device *isc); - }; -+ -+ struct isc_reg_offsets offsets; - }; - - extern struct isc_format formats_list[]; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -59,12 +59,18 @@ static void isc_sama5d2_config_csc(struc - struct regmap *regmap = isc->regmap; - - /* Convert RGB to YUV */ -- regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); -- regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); -- regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); -- regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); -- regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); -- regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); -+ regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, -+ 0x42 | (0x81 << 16)); -+ regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, -+ 0x19 | (0x10 << 16)); -+ regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, -+ 0xFDA | (0xFB6 << 16)); -+ regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, -+ 0x70 | (0x80 << 16)); -+ regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, -+ 0x70 | (0xFA2 << 16)); -+ regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, -+ 0xFEE | (0x80 << 16)); - } - - /* Gamma table with gamma 1/2.2 */ -@@ -234,6 +240,8 @@ static int atmel_isc_probe(struct platfo - - isc->config_csc = isc_sama5d2_config_csc; - -+ isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; -+ - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; - diff --git a/target/linux/at91/patches-5.10/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch b/target/linux/at91/patches-5.10/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch deleted file mode 100644 index fd7ed1e94d..0000000000 --- a/target/linux/at91/patches-5.10/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch +++ /dev/null @@ -1,80 +0,0 @@ -From aa31e58d80d233385fa3b972e6b85f293e2a9093 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:07 +0200 -Subject: [PATCH 165/247] media: atmel: atmel-isc: extract CBC submodule config - into separate function - -The CBC submodule is a part of the atmel-isc pipeline, and stands for -Contrast Brightness Control. It is used to apply gains and offsets to the -luma (Y) and chroma (U, V) components of the YUV elements. -The CBC submodule should be initialized in the product specific driver -as it's product specific. Other products can implement it differently - -[hverkuil: made isc_sama5d2_config_cbc static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 +--- - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 9 +++++++++ - 3 files changed, 13 insertions(+), 3 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -655,9 +655,7 @@ static void isc_set_pipeline(struct isc_ - regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); - - isc->config_csc(isc); -- -- regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness); -- regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast); -+ isc->config_cbc(isc); - } - - static int isc_update_profile(struct isc_device *isc) ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -202,6 +202,8 @@ struct isc_reg_offsets { - * - * @config_csc: pointer to a function that initializes product - * specific CSC module -+ * @config_cbc: pointer to a function that initializes product -+ * specific CBC module - * - * @offsets: struct holding the product specific register offsets - */ -@@ -274,6 +276,7 @@ struct isc_device { - - struct { - void (*config_csc)(struct isc_device *isc); -+ void (*config_cbc)(struct isc_device *isc); - }; - - struct isc_reg_offsets offsets; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -73,6 +73,14 @@ static void isc_sama5d2_config_csc(struc - 0xFEE | (0x80 << 16)); - } - -+static void isc_sama5d2_config_cbc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness); -+ regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -239,6 +247,7 @@ static int atmel_isc_probe(struct platfo - isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; - - isc->config_csc = isc_sama5d2_config_csc; -+ isc->config_cbc = isc_sama5d2_config_cbc; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - diff --git a/target/linux/at91/patches-5.10/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch b/target/linux/at91/patches-5.10/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch deleted file mode 100644 index 51659f54a4..0000000000 --- a/target/linux/at91/patches-5.10/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 52e4b779ae1af3e322d0c673375dcd51315739d4 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:08 +0200 -Subject: [PATCH 166/247] media: atmel: atmel-isc: add CBC to the reg offsets - struct - -The CBC submodule is a part of the atmel-isc pipeline, and stands for -Contrast Brightness Control. It is used to apply gains and offsets to the -luma (Y) and chroma (U, V) components of the YUV elements. -Add cbc to the reg offsets struct. This will allow different products -to have a different reg offset for this particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 2 +- - drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 7 +++++-- - 4 files changed, 11 insertions(+), 3 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2325,7 +2325,7 @@ int isc_pipeline_init(struct isc_device - REG_FIELD(ISC_GAM_CTRL, 2, 2), - REG_FIELD(ISC_GAM_CTRL, 3, 3), - REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), -- REG_FIELD(ISC_CBC_CTRL, 0, 0), -+ REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), - REG_FIELD(ISC_SUB422_CTRL, 0, 0), - REG_FIELD(ISC_SUB420_CTRL, 0, 0), - }; ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -177,6 +177,9 @@ - /* Color Space Conversion CRB OCR Register */ - #define ISC_CSC_CRB_OCR 0x000003b0 - -+/* Offset for CBC register specific to sama5d2 product */ -+#define ISC_SAMA5D2_CBC_OFFSET 0 -+ - /* Contrast And Brightness Control Register */ - #define ISC_CBC_CTRL 0x000003b4 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -146,9 +146,11 @@ struct isc_ctrls { - /* - * struct isc_reg_offsets - ISC device register offsets - * @csc: Offset for the CSC register -+ * @cbc: Offset for the CBC register - */ - struct isc_reg_offsets { - u32 csc; -+ u32 cbc; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -77,8 +77,10 @@ static void isc_sama5d2_config_cbc(struc - { - struct regmap *regmap = isc->regmap; - -- regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness); -- regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast); -+ regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, -+ isc->ctrls.brightness); -+ regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, -+ isc->ctrls.contrast); - } - - /* Gamma table with gamma 1/2.2 */ -@@ -250,6 +252,7 @@ static int atmel_isc_probe(struct platfo - isc->config_cbc = isc_sama5d2_config_cbc; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; -+ isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.10/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch b/target/linux/at91/patches-5.10/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch deleted file mode 100644 index 6d937fdeb7..0000000000 --- a/target/linux/at91/patches-5.10/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch +++ /dev/null @@ -1,80 +0,0 @@ -From aebb741058a63c3493f4139d11d6f290d5691e9b Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:09 +0200 -Subject: [PATCH 167/247] media: atmel: atmel-isc: add SUB422 and SUB420 to - register offsets - -The SUB submodules are a part of the atmel-isc pipeline, and stand for -Subsampling. They are used to subsample the original YUV 4:4:4 pixel ratio -aspect to either 4:2:2 or 4:2:0. -Add sub420 and sub422 to the reg offsets struct. -This will allow different products to have a different reg offset for these -particular modules. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- - drivers/media/platform/atmel/atmel-isc-regs.h | 4 ++++ - drivers/media/platform/atmel/atmel-isc.h | 4 ++++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 ++ - 4 files changed, 12 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2326,8 +2326,8 @@ int isc_pipeline_init(struct isc_device - REG_FIELD(ISC_GAM_CTRL, 3, 3), - REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), - REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), -- REG_FIELD(ISC_SUB422_CTRL, 0, 0), -- REG_FIELD(ISC_SUB420_CTRL, 0, 0), -+ REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), -+ REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0), - }; - - for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -194,9 +194,13 @@ - #define ISC_CBC_CONTRAST 0x000003c0 - #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) - -+/* Offset for SUB422 register specific to sama5d2 product */ -+#define ISC_SAMA5D2_SUB422_OFFSET 0 - /* Subsampling 4:4:4 to 4:2:2 Control Register */ - #define ISC_SUB422_CTRL 0x000003c4 - -+/* Offset for SUB420 register specific to sama5d2 product */ -+#define ISC_SAMA5D2_SUB420_OFFSET 0 - /* Subsampling 4:2:2 to 4:2:0 Control Register */ - #define ISC_SUB420_CTRL 0x000003cc - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -147,10 +147,14 @@ struct isc_ctrls { - * struct isc_reg_offsets - ISC device register offsets - * @csc: Offset for the CSC register - * @cbc: Offset for the CBC register -+ * @sub422: Offset for the SUB422 register -+ * @sub420: Offset for the SUB420 register - */ - struct isc_reg_offsets { - u32 csc; - u32 cbc; -+ u32 sub422; -+ u32 sub420; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -253,6 +253,8 @@ static int atmel_isc_probe(struct platfo - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; -+ isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; -+ isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.10/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch b/target/linux/at91/patches-5.10/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch deleted file mode 100644 index 050e2816c0..0000000000 --- a/target/linux/at91/patches-5.10/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch +++ /dev/null @@ -1,74 +0,0 @@ -From b432a8b0fc88de5b49236482053d8d372c68ee55 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:10 +0200 -Subject: [PATCH 168/247] media: atmel: atmel-isc: add RLP to register offsets - -The RLP submodule is a part of the atmel-isc pipeline, and stands for -Rounding,Limiting and Packaging. It used to extract specific data from the -ISC pipeline. For example if we want to output greyscale 8 bit, we would -use limiting to 8 bits, and packaging to Luma component only. -Add rlp to the reg offsets struct. -This will allow different products to have a different reg offset for this -particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- - drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + - 4 files changed, 7 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -726,8 +726,8 @@ static int isc_configure(struct isc_devi - - regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); - -- regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK, -- rlp_mode); -+ regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, -+ ISC_RLP_CFG_MODE_MASK, rlp_mode); - - regmap_write(regmap, ISC_DCFG, dcfg); - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -204,6 +204,8 @@ - /* Subsampling 4:2:2 to 4:2:0 Control Register */ - #define ISC_SUB420_CTRL 0x000003cc - -+/* Offset for RLP register specific to sama5d2 product */ -+#define ISC_SAMA5D2_RLP_OFFSET 0 - /* Rounding, Limiting and Packing Configuration Register */ - #define ISC_RLP_CFG 0x000003d0 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -149,12 +149,14 @@ struct isc_ctrls { - * @cbc: Offset for the CBC register - * @sub422: Offset for the SUB422 register - * @sub420: Offset for the SUB420 register -+ * @rlp: Offset for the RLP register - */ - struct isc_reg_offsets { - u32 csc; - u32 cbc; - u32 sub422; - u32 sub420; -+ u32 rlp; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -255,6 +255,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; - isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; - isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; -+ isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.10/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch b/target/linux/at91/patches-5.10/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch deleted file mode 100644 index 6ce49e67ff..0000000000 --- a/target/linux/at91/patches-5.10/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 8c19aa14b8303a0e7c4bae42f3f00f9a2a65b0db Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:11 +0200 -Subject: [PATCH 169/247] media: atmel: atmel-isc: add HIS to register offsets - -The HIS submodule is a part of the atmel-isc pipeline, and stands for -Histogram. This module performs a color histogram that can be read and used -by the main processor. -Add his to the reg offsets struct. -This will allow different products to have a different reg offset for this -particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 11 +++++++---- - drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + - 4 files changed, 12 insertions(+), 4 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -686,12 +686,13 @@ static void isc_set_histogram(struct isc - struct isc_ctrls *ctrls = &isc->ctrls; - - if (enable) { -- regmap_write(regmap, ISC_HIS_CFG, -+ regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, - ISC_HIS_CFG_MODE_GR | - (isc->config.sd_format->cfa_baycfg - << ISC_HIS_CFG_BAYSEL_SHIFT) | - ISC_HIS_CFG_RAR); -- regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN); -+ regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, -+ ISC_HIS_CTRL_EN); - regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE); - ctrls->hist_id = ISC_HIS_CFG_MODE_GR; - isc_update_profile(isc); -@@ -700,7 +701,8 @@ static void isc_set_histogram(struct isc - ctrls->hist_stat = HIST_ENABLED; - } else { - regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE); -- regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS); -+ regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, -+ ISC_HIS_CTRL_DIS); - - ctrls->hist_stat = HIST_DISABLED; - } -@@ -1836,7 +1838,8 @@ static void isc_awb_work(struct work_str - ctrls->awb = ISC_WB_NONE; - } - } -- regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR); -+ regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, -+ hist_id | baysel | ISC_HIS_CFG_RAR); - isc_update_profile(isc); - /* if awb has been disabled, we don't need to start another histogram */ - if (ctrls->awb) ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -224,6 +224,8 @@ - #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc - #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) - -+/* Offset for HIS register specific to sama5d2 product */ -+#define ISC_SAMA5D2_HIS_OFFSET 0 - /* Histogram Control Register */ - #define ISC_HIS_CTRL 0x000003d4 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -150,6 +150,7 @@ struct isc_ctrls { - * @sub422: Offset for the SUB422 register - * @sub420: Offset for the SUB420 register - * @rlp: Offset for the RLP register -+ * @his: Offset for the HIS related registers - */ - struct isc_reg_offsets { - u32 csc; -@@ -157,6 +158,7 @@ struct isc_reg_offsets { - u32 sub422; - u32 sub420; - u32 rlp; -+ u32 his; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -256,6 +256,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; - isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; - isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; -+ isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.10/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch b/target/linux/at91/patches-5.10/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch deleted file mode 100644 index ef7104e587..0000000000 --- a/target/linux/at91/patches-5.10/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 7173e54070a9b530c8c16e0a507be71385133abd Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:12 +0200 -Subject: [PATCH 170/247] media: atmel: atmel-isc: add DMA to register offsets - -The DMA submodule is a part of the atmel-isc pipeline, and stands for -Direct Memory Access. It acts like a master on the AXI bus of the SoC, and -can directly write the RAM area with the pixel data from the ISC internal -sram. -Add dma to the reg offsets struct. -This will allow different products to have a different reg offset for this -particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 19 ++++++++++++------- - drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - .../media/platform/atmel/atmel-sama5d2-isc.c | 1 + - 4 files changed, 18 insertions(+), 7 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -601,16 +601,20 @@ static void isc_start_dma(struct isc_dev - ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN); - - addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0); -- regmap_write(regmap, ISC_DAD0, addr0); -+ regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0); - - switch (isc->config.fourcc) { - case V4L2_PIX_FMT_YUV420: -- regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3); -- regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6); -+ regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, -+ addr0 + (sizeimage * 2) / 3); -+ regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, -+ addr0 + (sizeimage * 5) / 6); - break; - case V4L2_PIX_FMT_YUV422P: -- regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2); -- regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4); -+ regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, -+ addr0 + sizeimage / 2); -+ regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, -+ addr0 + (sizeimage * 3) / 4); - break; - default: - break; -@@ -618,7 +622,8 @@ static void isc_start_dma(struct isc_dev - - dctrl_dview = isc->config.dctrl_dview; - -- regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS); -+ regmap_write(regmap, ISC_DCTRL + isc->offsets.dma, -+ dctrl_dview | ISC_DCTRL_IE_IS); - spin_lock(&isc->awb_lock); - regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE); - spin_unlock(&isc->awb_lock); -@@ -731,7 +736,7 @@ static int isc_configure(struct isc_devi - regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, - ISC_RLP_CFG_MODE_MASK, rlp_mode); - -- regmap_write(regmap, ISC_DCFG, dcfg); -+ regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); - - /* Set the pipeline */ - isc_set_pipeline(isc, pipeline); ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -247,6 +247,9 @@ - - #define ISC_HIS_CFG_RAR BIT(8) - -+/* Offset for DMA register specific to sama5d2 product */ -+#define ISC_SAMA5D2_DMA_OFFSET 0 -+ - /* DMA Configuration Register */ - #define ISC_DCFG 0x000003e0 - #define ISC_DCFG_IMODE_PACKED8 0x0 ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -151,6 +151,7 @@ struct isc_ctrls { - * @sub420: Offset for the SUB420 register - * @rlp: Offset for the RLP register - * @his: Offset for the HIS related registers -+ * @dma: Offset for the DMA related registers - */ - struct isc_reg_offsets { - u32 csc; -@@ -159,6 +160,7 @@ struct isc_reg_offsets { - u32 sub420; - u32 rlp; - u32 his; -+ u32 dma; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -257,6 +257,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; - isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; - isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; -+ isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.10/171-media-atmel-atmel-isc-add-support-for-version-regist.patch b/target/linux/at91/patches-5.10/171-media-atmel-atmel-isc-add-support-for-version-regist.patch deleted file mode 100644 index b582945b99..0000000000 --- a/target/linux/at91/patches-5.10/171-media-atmel-atmel-isc-add-support-for-version-regist.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 0939b0a92acca11a5a3b0de5dd70434e17e40ed3 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:13 +0200 -Subject: [PATCH 171/247] media: atmel: atmel-isc: add support for version - register - -Add support for version register and print it at probe time. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-regs.h | 5 +++++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 5 +++++ - 3 files changed, 12 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -295,6 +295,11 @@ - /* DMA Address 2 Register */ - #define ISC_DAD2 0x000003fc - -+/* Offset for version register specific to sama5d2 product */ -+#define ISC_SAMA5D2_VERSION_OFFSET 0 -+/* Version Register */ -+#define ISC_VERSION 0x0000040c -+ - /* Histogram Entry */ - #define ISC_HIS_ENTRY 0x00000410 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -152,6 +152,7 @@ struct isc_ctrls { - * @rlp: Offset for the RLP register - * @his: Offset for the HIS related registers - * @dma: Offset for the DMA related registers -+ * @version: Offset for the version register - */ - struct isc_reg_offsets { - u32 csc; -@@ -161,6 +162,7 @@ struct isc_reg_offsets { - u32 rlp; - u32 his; - u32 dma; -+ u32 version; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -210,6 +210,7 @@ static int atmel_isc_probe(struct platfo - struct isc_subdev_entity *subdev_entity; - int irq; - int ret; -+ u32 ver; - - isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); - if (!isc) -@@ -258,6 +259,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; - isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; - isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; -+ isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; -@@ -346,6 +348,9 @@ static int atmel_isc_probe(struct platfo - pm_runtime_enable(dev); - pm_request_idle(dev); - -+ regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); -+ dev_info(dev, "Microchip ISC version %x\n", ver); -+ - return 0; - - cleanup_subdev: diff --git a/target/linux/at91/patches-5.10/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch b/target/linux/at91/patches-5.10/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch deleted file mode 100644 index c48301cf25..0000000000 --- a/target/linux/at91/patches-5.10/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch +++ /dev/null @@ -1,71 +0,0 @@ -From bce46a8a620a796ca3cfe5bff61baf6744074986 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:14 +0200 -Subject: [PATCH 172/247] media: atmel: atmel-isc: add his_entry to register - offsets - -Add his_entry to the reg offsets struct. -This will allow different products to have a different reg offset for this -particular module. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 3 ++- - drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ - drivers/media/platform/atmel/atmel-isc.h | 2 ++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + - 4 files changed, 7 insertions(+), 1 deletion(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -1684,7 +1684,8 @@ static void isc_hist_count(struct isc_de - *min = 0; - *max = HIST_ENTRIES; - -- regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES); -+ regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, -+ hist_entry, HIST_ENTRIES); - - *hist_count = 0; - /* ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -300,6 +300,8 @@ - /* Version Register */ - #define ISC_VERSION 0x0000040c - -+/* Offset for version register specific to sama5d2 product */ -+#define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 - /* Histogram Entry */ - #define ISC_HIS_ENTRY 0x00000410 - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -153,6 +153,7 @@ struct isc_ctrls { - * @his: Offset for the HIS related registers - * @dma: Offset for the DMA related registers - * @version: Offset for the version register -+ * @his_entry: Offset for the HIS entries registers - */ - struct isc_reg_offsets { - u32 csc; -@@ -163,6 +164,7 @@ struct isc_reg_offsets { - u32 his; - u32 dma; - u32 version; -+ u32 his_entry; - }; - - /* ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -260,6 +260,7 @@ static int atmel_isc_probe(struct platfo - isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; - isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; - isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; -+ isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; - - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; diff --git a/target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch b/target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch deleted file mode 100644 index f701ede09c..0000000000 --- a/target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 87b581b1197df5f77bd65819d0428f2404c6b764 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:15 +0200 -Subject: [PATCH 173/247] media: atmel: atmel-isc: add register description for - additional modules - -Add register description for additional pipeline modules: the -Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS) - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++ - 1 file changed, 67 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -90,6 +90,46 @@ - #define ISC_INT_DDONE BIT(8) - #define ISC_INT_HISDONE BIT(12) - -+/* ISC DPC Control Register */ -+#define ISC_DPC_CTRL 0x40 -+ -+#define ISC_DPC_CTRL_DPCEN BIT(0) -+#define ISC_DPC_CTRL_GDCEN BIT(1) -+#define ISC_DPC_CTRL_BLCEN BIT(2) -+ -+/* ISC DPC Config Register */ -+#define ISC_DPC_CFG 0x44 -+ -+#define ISC_DPC_CFG_BAYSEL_SHIFT 0 -+ -+#define ISC_DPC_CFG_EITPOL BIT(4) -+ -+#define ISC_DPC_CFG_TA_ENABLE BIT(14) -+#define ISC_DPC_CFG_TC_ENABLE BIT(13) -+#define ISC_DPC_CFG_TM_ENABLE BIT(12) -+ -+#define ISC_DPC_CFG_RE_MODE BIT(17) -+ -+#define ISC_DPC_CFG_GDCCLP_SHIFT 20 -+#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20) -+ -+#define ISC_DPC_CFG_BLOFF_SHIFT 24 -+#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24) -+ -+#define ISC_DPC_CFG_BAYCFG_SHIFT 0 -+#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0) -+/* ISC DPC Threshold Median Register */ -+#define ISC_DPC_THRESHM 0x48 -+ -+/* ISC DPC Threshold Closest Register */ -+#define ISC_DPC_THRESHC 0x4C -+ -+/* ISC DPC Threshold Average Register */ -+#define ISC_DPC_THRESHA 0x50 -+ -+/* ISC DPC STatus Register */ -+#define ISC_DPC_SR 0x54 -+ - /* ISC White Balance Control Register */ - #define ISC_WB_CTRL 0x00000058 - -@@ -153,6 +193,33 @@ - /* ISC_Gamma Correction Green Entry Register */ - #define ISC_GAM_RENTRY 0x00000298 - -+/* ISC VHXS Control Register */ -+#define ISC_VHXS_CTRL 0x398 -+ -+/* ISC VHXS Source Size Register */ -+#define ISC_VHXS_SS 0x39C -+ -+/* ISC VHXS Destination Size Register */ -+#define ISC_VHXS_DS 0x3A0 -+ -+/* ISC Vertical Factor Register */ -+#define ISC_VXS_FACT 0x3a4 -+ -+/* ISC Horizontal Factor Register */ -+#define ISC_HXS_FACT 0x3a8 -+ -+/* ISC Vertical Config Register */ -+#define ISC_VXS_CFG 0x3ac -+ -+/* ISC Horizontal Config Register */ -+#define ISC_HXS_CFG 0x3b0 -+ -+/* ISC Vertical Tap Register */ -+#define ISC_VXS_TAP 0x3b4 -+ -+/* ISC Horizontal Tap Register */ -+#define ISC_HXS_TAP 0x434 -+ - /* Offset for CSC register specific to sama5d2 product */ - #define ISC_SAMA5D2_CSC_OFFSET 0 - diff --git a/target/linux/at91/patches-5.10/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch b/target/linux/at91/patches-5.10/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch deleted file mode 100644 index 7cb5233c2e..0000000000 --- a/target/linux/at91/patches-5.10/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 58a6cc3c7eecd16208cd16b92b4eaf8385e69696 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:16 +0200 -Subject: [PATCH 174/247] media: atmel: atmel-isc: extend pipeline with extra - modules - -Newer ISC pipelines have the additional modules of -Defective Pixel Correction -> DPC itself, -Defective Pixel Correction -> Green Disparity Correction (DPC_GDC) -Defective Pixel Correction -> Black Level Correction (DPC_BLC) -Vertical and Horizontal Scaler -> VHXS - -Some products have this full pipeline (sama7g5), other products do not (sama5d2) - -Add the modules to the isc base, and also extend the register range to include -the modules. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 11 ++++++-- - drivers/media/platform/atmel/atmel-isc.h | 28 +++++++++++-------- - 2 files changed, 25 insertions(+), 14 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2324,8 +2324,14 @@ int isc_pipeline_init(struct isc_device - struct regmap_field *regs; - unsigned int i; - -- /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ -+ /* -+ * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC--> -+ * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420 -+ */ - const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = { -+ REG_FIELD(ISC_DPC_CTRL, 0, 0), -+ REG_FIELD(ISC_DPC_CTRL, 1, 1), -+ REG_FIELD(ISC_DPC_CTRL, 2, 2), - REG_FIELD(ISC_WB_CTRL, 0, 0), - REG_FIELD(ISC_CFA_CTRL, 0, 0), - REG_FIELD(ISC_CC_CTRL, 0, 0), -@@ -2333,6 +2339,7 @@ int isc_pipeline_init(struct isc_device - REG_FIELD(ISC_GAM_CTRL, 1, 1), - REG_FIELD(ISC_GAM_CTRL, 2, 2), - REG_FIELD(ISC_GAM_CTRL, 3, 3), -+ REG_FIELD(ISC_VHXS_CTRL, 0, 0), - REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), - REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), - REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), -@@ -2351,7 +2358,7 @@ int isc_pipeline_init(struct isc_device - } - - /* regmap configuration */ --#define ATMEL_ISC_REG_MAX 0xbfc -+#define ATMEL_ISC_REG_MAX 0xd5c - const struct regmap_config isc_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -67,17 +67,21 @@ struct isc_format { - }; - - /* Pipeline bitmap */ --#define WB_ENABLE BIT(0) --#define CFA_ENABLE BIT(1) --#define CC_ENABLE BIT(2) --#define GAM_ENABLE BIT(3) --#define GAM_BENABLE BIT(4) --#define GAM_GENABLE BIT(5) --#define GAM_RENABLE BIT(6) --#define CSC_ENABLE BIT(7) --#define CBC_ENABLE BIT(8) --#define SUB422_ENABLE BIT(9) --#define SUB420_ENABLE BIT(10) -+#define DPC_DPCENABLE BIT(0) -+#define DPC_GDCENABLE BIT(1) -+#define DPC_BLCENABLE BIT(2) -+#define WB_ENABLE BIT(3) -+#define CFA_ENABLE BIT(4) -+#define CC_ENABLE BIT(5) -+#define GAM_ENABLE BIT(6) -+#define GAM_BENABLE BIT(7) -+#define GAM_GENABLE BIT(8) -+#define GAM_RENABLE BIT(9) -+#define VHXS_ENABLE BIT(10) -+#define CSC_ENABLE BIT(11) -+#define CBC_ENABLE BIT(12) -+#define SUB422_ENABLE BIT(13) -+#define SUB420_ENABLE BIT(14) - - #define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE) - -@@ -141,7 +145,7 @@ struct isc_ctrls { - u32 hist_minmax[HIST_BAYER][2]; - }; - --#define ISC_PIPE_LINE_NODE_NUM 11 -+#define ISC_PIPE_LINE_NODE_NUM 15 - - /* - * struct isc_reg_offsets - ISC device register offsets diff --git a/target/linux/at91/patches-5.10/175-media-atmel-atmel-isc-add-CC-initialization-function.patch b/target/linux/at91/patches-5.10/175-media-atmel-atmel-isc-add-CC-initialization-function.patch deleted file mode 100644 index 69491d7d13..0000000000 --- a/target/linux/at91/patches-5.10/175-media-atmel-atmel-isc-add-CC-initialization-function.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 0db91d2a803221c313c9f2cd1d71050d7c5a7b5b Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:17 +0200 -Subject: [PATCH 175/247] media: atmel: atmel-isc: add CC initialization - function - -The CC submodule is a part of the atmel-isc pipeline, and stands for -Color Correction. It is used to apply gains and offsets to the -chroma (U, V) components of the YUV elements. -Implement the CC submodule initialization, as a product -specific function, which currently configures the neutral point in color -correction. - -[hverkuil: made isc_sama5d2_config_cc static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 1 + - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 14 ++++++++++++++ - 3 files changed, 18 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -661,6 +661,7 @@ static void isc_set_pipeline(struct isc_ - - isc->config_csc(isc); - isc->config_cbc(isc); -+ isc->config_cc(isc); - } - - static int isc_update_profile(struct isc_device *isc) ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -224,6 +224,8 @@ struct isc_reg_offsets { - * specific CSC module - * @config_cbc: pointer to a function that initializes product - * specific CBC module -+ * @config_cc: pointer to a function that initializes product -+ * specific CC module - * - * @offsets: struct holding the product specific register offsets - */ -@@ -297,6 +299,7 @@ struct isc_device { - struct { - void (*config_csc)(struct isc_device *isc); - void (*config_cbc)(struct isc_device *isc); -+ void (*config_cc)(struct isc_device *isc); - }; - - struct isc_reg_offsets offsets; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -83,6 +83,19 @@ static void isc_sama5d2_config_cbc(struc - isc->ctrls.contrast); - } - -+static void isc_sama5d2_config_cc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Configure each register at the neutral fixed point 1.0 or 0.0 */ -+ regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); -+ regmap_write(regmap, ISC_CC_RB_OR, 0); -+ regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); -+ regmap_write(regmap, ISC_CC_GB_OG, 0); -+ regmap_write(regmap, ISC_CC_BR_BG, 0); -+ regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -251,6 +264,7 @@ static int atmel_isc_probe(struct platfo - - isc->config_csc = isc_sama5d2_config_csc; - isc->config_cbc = isc_sama5d2_config_cbc; -+ isc->config_cc = isc_sama5d2_config_cc; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; diff --git a/target/linux/at91/patches-5.10/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch b/target/linux/at91/patches-5.10/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch deleted file mode 100644 index 35c839692c..0000000000 --- a/target/linux/at91/patches-5.10/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 0a75c502eac4f2ef71b6c3e0b3a01db1b3c37ba9 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:18 +0200 -Subject: [PATCH 176/247] media: atmel: atmel-isc: create product specific v4l2 - controls config - -Create product specific callback for initializing v4l2 controls. -Call this from v4l2 controls init function. - -[hverkuil: made isc_sama5d2_config_ctrls static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 5 +++-- - drivers/media/platform/atmel/atmel-isc.h | 5 +++++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 12 ++++++++++++ - 3 files changed, 20 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -2051,11 +2051,12 @@ static int isc_ctrl_init(struct isc_devi - if (ret < 0) - return ret; - -+ /* Initialize product specific controls. For example, contrast */ -+ isc->config_ctrls(isc, ops); -+ - ctrls->brightness = 0; -- ctrls->contrast = 256; - - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); -- v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, - isc->gamma_max); - isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -226,6 +226,8 @@ struct isc_reg_offsets { - * specific CBC module - * @config_cc: pointer to a function that initializes product - * specific CC module -+ * @config_ctrls: pointer to a functoin that initializes product -+ * specific v4l2 controls. - * - * @offsets: struct holding the product specific register offsets - */ -@@ -300,6 +302,9 @@ struct isc_device { - void (*config_csc)(struct isc_device *isc); - void (*config_cbc)(struct isc_device *isc); - void (*config_cc)(struct isc_device *isc); -+ -+ void (*config_ctrls)(struct isc_device *isc, -+ const struct v4l2_ctrl_ops *ops); - }; - - struct isc_reg_offsets offsets; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -96,6 +96,17 @@ static void isc_sama5d2_config_cc(struct - regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); - } - -+static void isc_sama5d2_config_ctrls(struct isc_device *isc, -+ const struct v4l2_ctrl_ops *ops) -+{ -+ struct isc_ctrls *ctrls = &isc->ctrls; -+ struct v4l2_ctrl_handler *hdl = &ctrls->handler; -+ -+ ctrls->contrast = 256; -+ -+ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -265,6 +276,7 @@ static int atmel_isc_probe(struct platfo - isc->config_csc = isc_sama5d2_config_csc; - isc->config_cbc = isc_sama5d2_config_cbc; - isc->config_cc = isc_sama5d2_config_cc; -+ isc->config_ctrls = isc_sama5d2_config_ctrls; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; diff --git a/target/linux/at91/patches-5.10/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch b/target/linux/at91/patches-5.10/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch deleted file mode 100644 index ef396f84cf..0000000000 --- a/target/linux/at91/patches-5.10/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch +++ /dev/null @@ -1,75 +0,0 @@ -From d53eb90044c19ba22b51978fcb007d9b5200b83a Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:19 +0200 -Subject: [PATCH 177/247] media: atmel: atmel-isc: create callback for DPC - submodule product specific - -The DPC submodule is a part of the atmel-isc pipeline, and stands for -Defective Pixel Correction. Its purpose is to detect defective pixels and -correct them if possible with the help of adjacent pixels. -Create a product specific callback for initializing the DPC submodule -of the pipeline. -For sama5d2 product, this module does not exist, thus this function is a noop. - -[hverkuil: made isc_sama5d2_config_dpc static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 1 + - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++ - 3 files changed, 10 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -659,6 +659,7 @@ static void isc_set_pipeline(struct isc_ - regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); - regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); - -+ isc->config_dpc(isc); - isc->config_csc(isc); - isc->config_cbc(isc); - isc->config_cc(isc); ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -220,6 +220,8 @@ struct isc_reg_offsets { - * @max_width: maximum frame width, dependent on the internal RAM - * @max_height: maximum frame height, dependent on the internal RAM - * -+ * @config_dpc: pointer to a function that initializes product -+ * specific DPC module - * @config_csc: pointer to a function that initializes product - * specific CSC module - * @config_cbc: pointer to a function that initializes product -@@ -299,6 +301,7 @@ struct isc_device { - u32 max_height; - - struct { -+ void (*config_dpc)(struct isc_device *isc); - void (*config_csc)(struct isc_device *isc); - void (*config_cbc)(struct isc_device *isc); - void (*config_cc)(struct isc_device *isc); ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -107,6 +107,11 @@ static void isc_sama5d2_config_ctrls(str - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); - } - -+static void isc_sama5d2_config_dpc(struct isc_device *isc) -+{ -+ /* This module is not present on sama5d2 pipeline */ -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -273,6 +278,7 @@ static int atmel_isc_probe(struct platfo - isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; - isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; - -+ isc->config_dpc = isc_sama5d2_config_dpc; - isc->config_csc = isc_sama5d2_config_csc; - isc->config_cbc = isc_sama5d2_config_cbc; - isc->config_cc = isc_sama5d2_config_cc; diff --git a/target/linux/at91/patches-5.10/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch b/target/linux/at91/patches-5.10/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch deleted file mode 100644 index a219704b31..0000000000 --- a/target/linux/at91/patches-5.10/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 96936a6753a13dea5a8f66de949e6594dd82ce22 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:20 +0200 -Subject: [PATCH 178/247] media: atmel: atmel-isc: create callback for GAM - submodule product specific - -The GAM submodule is a part of the atmel-isc pipeline, and stands for -Gamma Correction. It is used to apply the gamma curve to the incoming pixels. -Create a product specific callback for initializing the GAM submodule -of the pipeline. -For sama5d2 product, there is no special configuration at this moment, -thus this function is a noop. - -[hverkuil: made isc_sama5d2_config_gam static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 1 + - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++ - 3 files changed, 10 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -663,6 +663,7 @@ static void isc_set_pipeline(struct isc_ - isc->config_csc(isc); - isc->config_cbc(isc); - isc->config_cc(isc); -+ isc->config_gam(isc); - } - - static int isc_update_profile(struct isc_device *isc) ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -228,6 +228,8 @@ struct isc_reg_offsets { - * specific CBC module - * @config_cc: pointer to a function that initializes product - * specific CC module -+ * @config_gam: pointer to a function that initializes product -+ * specific GAMMA module - * @config_ctrls: pointer to a functoin that initializes product - * specific v4l2 controls. - * -@@ -305,6 +307,7 @@ struct isc_device { - void (*config_csc)(struct isc_device *isc); - void (*config_cbc)(struct isc_device *isc); - void (*config_cc)(struct isc_device *isc); -+ void (*config_gam)(struct isc_device *isc); - - void (*config_ctrls)(struct isc_device *isc, - const struct v4l2_ctrl_ops *ops); ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -112,6 +112,11 @@ static void isc_sama5d2_config_dpc(struc - /* This module is not present on sama5d2 pipeline */ - } - -+static void isc_sama5d2_config_gam(struct isc_device *isc) -+{ -+ /* No specific gamma configuration */ -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -282,6 +287,7 @@ static int atmel_isc_probe(struct platfo - isc->config_csc = isc_sama5d2_config_csc; - isc->config_cbc = isc_sama5d2_config_cbc; - isc->config_cc = isc_sama5d2_config_cc; -+ isc->config_gam = isc_sama5d2_config_gam; - isc->config_ctrls = isc_sama5d2_config_ctrls; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; diff --git a/target/linux/at91/patches-5.10/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch b/target/linux/at91/patches-5.10/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch deleted file mode 100644 index 8442925a7e..0000000000 --- a/target/linux/at91/patches-5.10/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch +++ /dev/null @@ -1,95 +0,0 @@ -From ece1d7059731e31875e6eb464da4fb4a16465305 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:21 +0200 -Subject: [PATCH 179/247] media: atmel: atmel-isc: create callback for RLP - submodule product specific - -The RLP submodule is a part of the atmel-isc pipeline, and stands for -Rounding,Limiting and Packaging. It used to extract specific data from the -ISC pipeline. For example if we want to output greyscale 8 bit, we would -use limiting to 8 bits, and packaging to Luma component only. - -Create a product specific callback for initializing the RLP submodule -of the pipeline - -[hverkuil: made isc_sama5d2_config_rlp static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 6 ++---- - drivers/media/platform/atmel/atmel-isc.h | 3 +++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 10 ++++++++++ - 3 files changed, 15 insertions(+), 4 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -719,11 +719,10 @@ static void isc_set_histogram(struct isc - static int isc_configure(struct isc_device *isc) - { - struct regmap *regmap = isc->regmap; -- u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline; -+ u32 pfe_cfg0, dcfg, mask, pipeline; - struct isc_subdev_entity *subdev = isc->current_subdev; - - pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps; -- rlp_mode = isc->config.rlp_cfg_mode; - pipeline = isc->config.bits_pipeline; - - dcfg = isc->config.dcfg_imode | isc->dcfg; -@@ -736,8 +735,7 @@ static int isc_configure(struct isc_devi - - regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); - -- regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, -- ISC_RLP_CFG_MODE_MASK, rlp_mode); -+ isc->config_rlp(isc); - - regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -230,6 +230,8 @@ struct isc_reg_offsets { - * specific CC module - * @config_gam: pointer to a function that initializes product - * specific GAMMA module -+ * @config_rlp: pointer to a function that initializes product -+ * specific RLP module - * @config_ctrls: pointer to a functoin that initializes product - * specific v4l2 controls. - * -@@ -308,6 +310,7 @@ struct isc_device { - void (*config_cbc)(struct isc_device *isc); - void (*config_cc)(struct isc_device *isc); - void (*config_gam)(struct isc_device *isc); -+ void (*config_rlp)(struct isc_device *isc); - - void (*config_ctrls)(struct isc_device *isc, - const struct v4l2_ctrl_ops *ops); ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -117,6 +117,15 @@ static void isc_sama5d2_config_gam(struc - /* No specific gamma configuration */ - } - -+static void isc_sama5d2_config_rlp(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ u32 rlp_mode = isc->config.rlp_cfg_mode; -+ -+ regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, -+ ISC_RLP_CFG_MODE_MASK, rlp_mode); -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -288,6 +297,7 @@ static int atmel_isc_probe(struct platfo - isc->config_cbc = isc_sama5d2_config_cbc; - isc->config_cc = isc_sama5d2_config_cc; - isc->config_gam = isc_sama5d2_config_gam; -+ isc->config_rlp = isc_sama5d2_config_rlp; - isc->config_ctrls = isc_sama5d2_config_ctrls; - - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; diff --git a/target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch b/target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch deleted file mode 100644 index 1c64cfca2e..0000000000 --- a/target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch +++ /dev/null @@ -1,440 +0,0 @@ -From dda51aa2e4524914d25022864466fa9d8713a5e9 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:22 +0200 -Subject: [PATCH 180/247] media: atmel: atmel-isc: move the formats list into - product specific code - -The list of input and output formats has to be product specific. -Move this list into the product specific code. -Have pointers to these arrays inside the device struct. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 167 ++---------------- - drivers/media/platform/atmel/atmel-isc.h | 12 +- - .../media/platform/atmel/atmel-sama5d2-isc.c | 136 ++++++++++++++ - 3 files changed, 165 insertions(+), 150 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 064 - MODULE_PARM_DESC(sensor_preferred, - "Sensor is preferred to output the specified format (1-on 0-off), default 1"); - --/* This is a list of the formats that the ISC can *output* */ --const struct isc_format controller_formats[] = { -- { -- .fourcc = V4L2_PIX_FMT_ARGB444, -- }, -- { -- .fourcc = V4L2_PIX_FMT_ARGB555, -- }, -- { -- .fourcc = V4L2_PIX_FMT_RGB565, -- }, -- { -- .fourcc = V4L2_PIX_FMT_ABGR32, -- }, -- { -- .fourcc = V4L2_PIX_FMT_XBGR32, -- }, -- { -- .fourcc = V4L2_PIX_FMT_YUV420, -- }, -- { -- .fourcc = V4L2_PIX_FMT_YUYV, -- }, -- { -- .fourcc = V4L2_PIX_FMT_YUV422P, -- }, -- { -- .fourcc = V4L2_PIX_FMT_GREY, -- }, -- { -- .fourcc = V4L2_PIX_FMT_Y10, -- }, --}; -- --/* This is a list of formats that the ISC can receive as *input* */ --struct isc_format formats_list[] = { -- { -- .fourcc = V4L2_PIX_FMT_SBGGR8, -- .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- .cfa_baycfg = ISC_BAY_CFG_BGBG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGBRG8, -- .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- .cfa_baycfg = ISC_BAY_CFG_GBGB, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGRBG8, -- .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- .cfa_baycfg = ISC_BAY_CFG_GRGR, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SRGGB8, -- .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- .cfa_baycfg = ISC_BAY_CFG_RGRG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SBGGR10, -- .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- .cfa_baycfg = ISC_BAY_CFG_RGRG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGBRG10, -- .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- .cfa_baycfg = ISC_BAY_CFG_GBGB, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGRBG10, -- .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- .cfa_baycfg = ISC_BAY_CFG_GRGR, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SRGGB10, -- .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- .cfa_baycfg = ISC_BAY_CFG_RGRG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SBGGR12, -- .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -- .cfa_baycfg = ISC_BAY_CFG_BGBG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGBRG12, -- .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -- .cfa_baycfg = ISC_BAY_CFG_GBGB, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SGRBG12, -- .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -- .cfa_baycfg = ISC_BAY_CFG_GRGR, -- }, -- { -- .fourcc = V4L2_PIX_FMT_SRGGB12, -- .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -- .cfa_baycfg = ISC_BAY_CFG_RGRG, -- }, -- { -- .fourcc = V4L2_PIX_FMT_GREY, -- .mbus_code = MEDIA_BUS_FMT_Y8_1X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- }, -- { -- .fourcc = V4L2_PIX_FMT_YUYV, -- .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- }, -- { -- .fourcc = V4L2_PIX_FMT_RGB565, -- .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, -- .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -- }, -- { -- .fourcc = V4L2_PIX_FMT_Y10, -- .mbus_code = MEDIA_BUS_FMT_Y10_1X10, -- .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -- }, -- --}; -- - #define ISC_IS_FORMAT_RAW(mbus_code) \ - (((mbus_code) & 0xf000) == 0x3000) - -@@ -919,24 +788,25 @@ static int isc_querycap(struct file *fil - static int isc_enum_fmt_vid_cap(struct file *file, void *priv, - struct v4l2_fmtdesc *f) - { -+ struct isc_device *isc = video_drvdata(file); - u32 index = f->index; - u32 i, supported_index; - -- if (index < ARRAY_SIZE(controller_formats)) { -- f->pixelformat = controller_formats[index].fourcc; -+ if (index < isc->controller_formats_size) { -+ f->pixelformat = isc->controller_formats[index].fourcc; - return 0; - } - -- index -= ARRAY_SIZE(controller_formats); -+ index -= isc->controller_formats_size; - - supported_index = 0; - -- for (i = 0; i < ARRAY_SIZE(formats_list); i++) { -- if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) || -- !formats_list[i].sd_support) -+ for (i = 0; i < isc->formats_list_size; i++) { -+ if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) || -+ !isc->formats_list[i].sd_support) - continue; - if (supported_index == index) { -- f->pixelformat = formats_list[i].fourcc; -+ f->pixelformat = isc->formats_list[i].fourcc; - return 0; - } - supported_index++; -@@ -1477,8 +1347,8 @@ static int isc_enum_framesizes(struct fi - if (isc->user_formats[i]->fourcc == fsize->pixel_format) - ret = 0; - -- for (i = 0; i < ARRAY_SIZE(controller_formats); i++) -- if (controller_formats[i].fourcc == fsize->pixel_format) -+ for (i = 0; i < isc->controller_formats_size; i++) -+ if (isc->controller_formats[i].fourcc == fsize->pixel_format) - ret = 0; - - if (ret) -@@ -1514,8 +1384,8 @@ static int isc_enum_frameintervals(struc - if (isc->user_formats[i]->fourcc == fival->pixel_format) - ret = 0; - -- for (i = 0; i < ARRAY_SIZE(controller_formats); i++) -- if (controller_formats[i].fourcc == fival->pixel_format) -+ for (i = 0; i < isc->controller_formats_size; i++) -+ if (isc->controller_formats[i].fourcc == fival->pixel_format) - ret = 0; - - if (ret) -@@ -2126,12 +1996,13 @@ static void isc_async_unbind(struct v4l2 - v4l2_ctrl_handler_free(&isc->ctrls.handler); - } - --static struct isc_format *find_format_by_code(unsigned int code, int *index) -+static struct isc_format *find_format_by_code(struct isc_device *isc, -+ unsigned int code, int *index) - { -- struct isc_format *fmt = &formats_list[0]; -+ struct isc_format *fmt = &isc->formats_list[0]; - unsigned int i; - -- for (i = 0; i < ARRAY_SIZE(formats_list); i++) { -+ for (i = 0; i < isc->formats_list_size; i++) { - if (fmt->mbus_code == code) { - *index = i; - return fmt; -@@ -2148,7 +2019,7 @@ static int isc_formats_init(struct isc_d - struct isc_format *fmt; - struct v4l2_subdev *subdev = isc->current_subdev->sd; - unsigned int num_fmts, i, j; -- u32 list_size = ARRAY_SIZE(formats_list); -+ u32 list_size = isc->formats_list_size; - struct v4l2_subdev_mbus_code_enum mbus_code = { - .which = V4L2_SUBDEV_FORMAT_ACTIVE, - }; -@@ -2158,7 +2029,7 @@ static int isc_formats_init(struct isc_d - NULL, &mbus_code)) { - mbus_code.index++; - -- fmt = find_format_by_code(mbus_code.code, &i); -+ fmt = find_format_by_code(isc, mbus_code.code, &i); - if (!fmt) { - v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n", - mbus_code.code); -@@ -2179,7 +2050,7 @@ static int isc_formats_init(struct isc_d - if (!isc->user_formats) - return -ENOMEM; - -- fmt = &formats_list[0]; -+ fmt = &isc->formats_list[0]; - for (i = 0, j = 0; i < list_size; i++) { - if (fmt->sd_support) - isc->user_formats[j++] = fmt; ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -236,6 +236,12 @@ struct isc_reg_offsets { - * specific v4l2 controls. - * - * @offsets: struct holding the product specific register offsets -+ * @controller_formats: pointer to the array of possible formats that the -+ * controller can output -+ * @formats_list: pointer to the array of possible formats that can -+ * be used as an input to the controller -+ * @controller_formats_size: size of controller_formats array -+ * @formats_list_size: size of formats_list array - */ - struct isc_device { - struct regmap *regmap; -@@ -317,10 +323,12 @@ struct isc_device { - }; - - struct isc_reg_offsets offsets; -+ const struct isc_format *controller_formats; -+ struct isc_format *formats_list; -+ u32 controller_formats_size; -+ u32 formats_list_size; - }; - --extern struct isc_format formats_list[]; --extern const struct isc_format controller_formats[]; - extern const struct regmap_config isc_regmap_config; - extern const struct v4l2_async_notifier_operations isc_async_ops; - ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -54,6 +54,137 @@ - - #define ISC_CLK_MAX_DIV 255 - -+/* This is a list of the formats that the ISC can *output* */ -+static const struct isc_format sama5d2_controller_formats[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_ARGB444, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_ARGB555, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_RGB565, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_ABGR32, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_XBGR32, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV420, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUYV, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV422P, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_GREY, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y10, -+ }, -+}; -+ -+/* This is a list of formats that the ISC can receive as *input* */ -+static struct isc_format sama5d2_formats_list[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR8, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_BGBG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG8, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG8, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB8, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR10, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG10, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG10, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB10, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR12, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_BGBG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG12, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG12, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB12, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_GREY, -+ .mbus_code = MEDIA_BUS_FMT_Y8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUYV, -+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_RGB565, -+ .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y10, -+ .mbus_code = MEDIA_BUS_FMT_Y10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ }, -+ -+}; -+ - static void isc_sama5d2_config_csc(struct isc_device *isc) - { - struct regmap *regmap = isc->regmap; -@@ -310,6 +441,11 @@ static int atmel_isc_probe(struct platfo - isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; - isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; - -+ isc->controller_formats = sama5d2_controller_formats; -+ isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats); -+ isc->formats_list = sama5d2_formats_list; -+ isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list); -+ - /* sama5d2-isc - 8 bits per beat */ - isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; - diff --git a/target/linux/at91/patches-5.10/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch b/target/linux/at91/patches-5.10/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch deleted file mode 100644 index 042fc609fe..0000000000 --- a/target/linux/at91/patches-5.10/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 8601f1fc0a9a22788bfa6369fbbf83b3828a5b42 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:23 +0200 -Subject: [PATCH 181/247] media: atmel: atmel-isc: create an adapt pipeline - callback for product specific - -Once the pipeline is set in the base code, create a callback that will adapt -the ISC pipeline to each product. -Create the adapt_pipeline callback that will be used in this fashion. - -[hverkuil: made isc_sama5d2_adapt_pipeline static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 4 ++++ - drivers/media/platform/atmel/atmel-isc.h | 5 +++++ - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 11 +++++++++++ - 3 files changed, 20 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -1059,6 +1059,10 @@ static int isc_try_configure_pipeline(st - default: - isc->try_config.bits_pipeline = 0x0; - } -+ -+ /* Tune the pipeline to product specific */ -+ isc->adapt_pipeline(isc); -+ - return 0; - } - ---- a/drivers/media/platform/atmel/atmel-isc.h -+++ b/drivers/media/platform/atmel/atmel-isc.h -@@ -235,6 +235,9 @@ struct isc_reg_offsets { - * @config_ctrls: pointer to a functoin that initializes product - * specific v4l2 controls. - * -+ * @adapt_pipeline: pointer to a function that adapts the pipeline bits -+ * to the product specific pipeline -+ * - * @offsets: struct holding the product specific register offsets - * @controller_formats: pointer to the array of possible formats that the - * controller can output -@@ -320,6 +323,8 @@ struct isc_device { - - void (*config_ctrls)(struct isc_device *isc, - const struct v4l2_ctrl_ops *ops); -+ -+ void (*adapt_pipeline)(struct isc_device *isc); - }; - - struct isc_reg_offsets offsets; ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -54,6 +54,10 @@ - - #define ISC_CLK_MAX_DIV 255 - -+#define ISC_SAMA5D2_PIPELINE \ -+ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ -+ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) -+ - /* This is a list of the formats that the ISC can *output* */ - static const struct isc_format sama5d2_controller_formats[] = { - { -@@ -257,6 +261,11 @@ static void isc_sama5d2_config_rlp(struc - ISC_RLP_CFG_MODE_MASK, rlp_mode); - } - -+static void isc_sama5d2_adapt_pipeline(struct isc_device *isc) -+{ -+ isc->try_config.bits_pipeline &= ISC_SAMA5D2_PIPELINE; -+} -+ - /* Gamma table with gamma 1/2.2 */ - static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ -@@ -431,6 +440,8 @@ static int atmel_isc_probe(struct platfo - isc->config_rlp = isc_sama5d2_config_rlp; - isc->config_ctrls = isc_sama5d2_config_ctrls; - -+ isc->adapt_pipeline = isc_sama5d2_adapt_pipeline; -+ - isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; - isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; - isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; diff --git a/target/linux/at91/patches-5.10/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch b/target/linux/at91/patches-5.10/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch deleted file mode 100644 index 00849c7d12..0000000000 --- a/target/linux/at91/patches-5.10/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch +++ /dev/null @@ -1,55 +0,0 @@ -From bf032d1a0105939b90072914d88181fbe6187f43 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:24 +0200 -Subject: [PATCH 182/247] media: atmel: atmel-isc-regs: add additional fields - for sama7g5 type pipeline - -Add additional fields for registers present in sama7g5 type pipeline. -Extend register masks for additional bits in sama7g5 type pipeline registers. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++-- - 1 file changed, 14 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -289,8 +289,18 @@ - #define ISC_RLP_CFG_MODE_ARGB32 0xa - #define ISC_RLP_CFG_MODE_YYCC 0xb - #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc -+#define ISC_RLP_CFG_MODE_YCYC 0xd - #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) - -+#define ISC_RLP_CFG_LSH BIT(5) -+ -+#define ISC_RLP_CFG_YMODE_YUYV (3 << 6) -+#define ISC_RLP_CFG_YMODE_YVYU (2 << 6) -+#define ISC_RLP_CFG_YMODE_VYUY (0 << 6) -+#define ISC_RLP_CFG_YMODE_UYVY (1 << 6) -+ -+#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6) -+ - /* Offset for HIS register specific to sama5d2 product */ - #define ISC_SAMA5D2_HIS_OFFSET 0 - /* Histogram Control Register */ -@@ -332,13 +342,15 @@ - #define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4) - #define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4) - #define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4) --#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4) -+#define ISC_DCFG_YMBSIZE_BEATS32 (0x4 << 4) -+#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4) - - #define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8) - #define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8) - #define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8) - #define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8) --#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8) -+#define ISC_DCFG_CMBSIZE_BEATS32 (0x4 << 8) -+#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8) - - /* DMA Control Register */ - #define ISC_DCTRL 0x000003e4 diff --git a/target/linux/at91/patches-5.10/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch b/target/linux/at91/patches-5.10/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch deleted file mode 100644 index 247c901558..0000000000 --- a/target/linux/at91/patches-5.10/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch +++ /dev/null @@ -1,145 +0,0 @@ -From fa9e6cd8f3ba4a277c06e4c1fb01cd69b3a57234 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:25 +0200 -Subject: [PATCH 183/247] media: atmel: atmel-isc-base: add support for more - formats and additional pipeline modules - -Add support for additional formats supported by newer pipelines, and for -additional pipeline modules. - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-isc-base.c | 48 +++++++++++++++---- - 1 file changed, 38 insertions(+), 10 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -855,6 +855,8 @@ static int isc_try_validate_formats(stru - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_YUV422P: - case V4L2_PIX_FMT_YUYV: -+ case V4L2_PIX_FMT_UYVY: -+ case V4L2_PIX_FMT_VYUY: - ret = 0; - yuv = true; - break; -@@ -869,6 +871,7 @@ static int isc_try_validate_formats(stru - break; - case V4L2_PIX_FMT_GREY: - case V4L2_PIX_FMT_Y10: -+ case V4L2_PIX_FMT_Y16: - ret = 0; - grey = true; - break; -@@ -899,6 +902,8 @@ static int isc_try_validate_formats(stru - */ - static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) - { -+ isc->try_config.rlp_cfg_mode = 0; -+ - switch (isc->try_config.fourcc) { - case V4L2_PIX_FMT_SBGGR8: - case V4L2_PIX_FMT_SGBRG8: -@@ -965,7 +970,19 @@ static int isc_try_configure_rlp_dma(str - isc->try_config.bpp = 16; - break; - case V4L2_PIX_FMT_YUYV: -- isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; -+ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; -+ isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; -+ isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; -+ isc->try_config.bpp = 16; -+ break; -+ case V4L2_PIX_FMT_UYVY: -+ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; -+ isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; -+ isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; -+ isc->try_config.bpp = 16; -+ break; -+ case V4L2_PIX_FMT_VYUY: -+ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; - isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; - isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; - isc->try_config.bpp = 16; -@@ -976,8 +993,11 @@ static int isc_try_configure_rlp_dma(str - isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; - isc->try_config.bpp = 8; - break; -+ case V4L2_PIX_FMT_Y16: -+ isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; -+ fallthrough; - case V4L2_PIX_FMT_Y10: -- isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10; -+ isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10; - isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; - isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; - isc->try_config.bpp = 16; -@@ -1011,7 +1031,8 @@ static int isc_try_configure_pipeline(st - /* if sensor format is RAW, we convert inside ISC */ - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | -- WB_ENABLE | GAM_ENABLES; -+ WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | -+ CC_ENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } -@@ -1020,8 +1041,9 @@ static int isc_try_configure_pipeline(st - /* if sensor format is RAW, we convert inside ISC */ - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | -- CSC_ENABLE | WB_ENABLE | GAM_ENABLES | -- SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE; -+ CSC_ENABLE | GAM_ENABLES | WB_ENABLE | -+ SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | -+ DPC_BLCENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } -@@ -1031,33 +1053,39 @@ static int isc_try_configure_pipeline(st - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | - CSC_ENABLE | WB_ENABLE | GAM_ENABLES | -- SUB422_ENABLE | CBC_ENABLE; -+ SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } - break; - case V4L2_PIX_FMT_YUYV: -+ case V4L2_PIX_FMT_UYVY: -+ case V4L2_PIX_FMT_VYUY: - /* if sensor format is RAW, we convert inside ISC */ - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | - CSC_ENABLE | WB_ENABLE | GAM_ENABLES | -- SUB422_ENABLE | CBC_ENABLE; -+ SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } - break; - case V4L2_PIX_FMT_GREY: -- if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { -+ case V4L2_PIX_FMT_Y16: - /* if sensor format is RAW, we convert inside ISC */ -+ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { - isc->try_config.bits_pipeline = CFA_ENABLE | - CSC_ENABLE | WB_ENABLE | GAM_ENABLES | -- CBC_ENABLE; -+ CBC_ENABLE | DPC_BLCENABLE; - } else { - isc->try_config.bits_pipeline = 0x0; - } - break; - default: -- isc->try_config.bits_pipeline = 0x0; -+ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) -+ isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE; -+ else -+ isc->try_config.bits_pipeline = 0x0; - } - - /* Tune the pipeline to product specific */ diff --git a/target/linux/at91/patches-5.10/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch b/target/linux/at91/patches-5.10/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch deleted file mode 100644 index 587f4862f2..0000000000 --- a/target/linux/at91/patches-5.10/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch +++ /dev/null @@ -1,26 +0,0 @@ -From b36d11efc134f9f1e2804270d08b9dbefdee4a0d Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:26 +0200 -Subject: [PATCH 184/247] media: atmel: atmel-isc-sama5d2: remove duplicate - define - -Remove a duplicate definition of clock max divider - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -52,8 +52,6 @@ - #define ISC_SAMA5D2_MAX_SUPPORT_WIDTH 2592 - #define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT 1944 - --#define ISC_CLK_MAX_DIV 255 -- - #define ISC_SAMA5D2_PIPELINE \ - (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ - CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) diff --git a/target/linux/at91/patches-5.10/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch b/target/linux/at91/patches-5.10/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch deleted file mode 100644 index a21ac2a7c0..0000000000 --- a/target/linux/at91/patches-5.10/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch +++ /dev/null @@ -1,810 +0,0 @@ -From 74fd7ea680cb1a3a43b51a7279aea45efdf9ec42 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Tue, 13 Apr 2021 12:57:29 +0200 -Subject: [PATCH 185/247] media: atmel: atmel-isc: add microchip-xisc driver - -Add driver for the extended variant of the isc, the microchip XISC -present on sama7g5 product. - -[hverkuil: drop MODULE_SUPPORTED_DEVICE, no longer exists] -[hverkuil: made isc_sama7g5_config_csc et al static] -[hverkuil: made sama7g5_controller_formats et al static] - -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/Makefile | 1 + - drivers/media/platform/atmel/Kconfig | 11 + - drivers/media/platform/atmel/Makefile | 2 + - drivers/media/platform/atmel/atmel-isc-base.c | 2 +- - drivers/media/platform/atmel/atmel-isc-regs.h | 26 + - .../media/platform/atmel/atmel-sama7g5-isc.c | 630 ++++++++++++++++++ - 6 files changed, 671 insertions(+), 1 deletion(-) - create mode 100644 drivers/media/platform/atmel/atmel-sama7g5-isc.c - ---- a/drivers/media/platform/Makefile -+++ b/drivers/media/platform/Makefile -@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_RCAR_VIN) += rcar-vi - - obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel/ - obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel/ -+obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel/ - - obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32/ - ---- a/drivers/media/platform/atmel/Kconfig -+++ b/drivers/media/platform/atmel/Kconfig -@@ -12,6 +12,17 @@ config VIDEO_ATMEL_ISC - This module makes the ATMEL Image Sensor Controller available - as a v4l2 device. - -+config VIDEO_ATMEL_XISC -+ tristate "ATMEL eXtended Image Sensor Controller (XISC) support" -+ depends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API -+ depends on ARCH_AT91 || COMPILE_TEST -+ select VIDEOBUF2_DMA_CONTIG -+ select REGMAP_MMIO -+ select V4L2_FWNODE -+ help -+ This module makes the ATMEL eXtended Image Sensor Controller -+ available as a v4l2 device. -+ - config VIDEO_ATMEL_ISI - tristate "ATMEL Image Sensor Interface (ISI) support" - depends on VIDEO_V4L2 && OF ---- a/drivers/media/platform/atmel/Makefile -+++ b/drivers/media/platform/atmel/Makefile -@@ -1,5 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0-only - atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o -+atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o - - obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o - obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o -+obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -600,7 +600,7 @@ static int isc_configure(struct isc_devi - mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | - ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW | - ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC | -- ISC_PFE_CFG0_CCIR656; -+ ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI; - - regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); - ---- a/drivers/media/platform/atmel/atmel-isc-regs.h -+++ b/drivers/media/platform/atmel/atmel-isc-regs.h -@@ -26,6 +26,7 @@ - #define ISC_PFE_CFG0_PPOL_LOW BIT(2) - #define ISC_PFE_CFG0_CCIR656 BIT(9) - #define ISC_PFE_CFG0_CCIR_CRC BIT(10) -+#define ISC_PFE_CFG0_MIPI BIT(14) - - #define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4) - #define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4) -@@ -184,6 +185,8 @@ - /* ISC Gamma Correction Control Register */ - #define ISC_GAM_CTRL 0x00000094 - -+#define ISC_GAM_CTRL_BIPART BIT(4) -+ - /* ISC_Gamma Correction Blue Entry Register */ - #define ISC_GAM_BENTRY 0x00000098 - -@@ -222,6 +225,8 @@ - - /* Offset for CSC register specific to sama5d2 product */ - #define ISC_SAMA5D2_CSC_OFFSET 0 -+/* Offset for CSC register specific to sama7g5 product */ -+#define ISC_SAMA7G5_CSC_OFFSET 0x11c - - /* Color Space Conversion Control Register */ - #define ISC_CSC_CTRL 0x00000398 -@@ -246,6 +251,8 @@ - - /* Offset for CBC register specific to sama5d2 product */ - #define ISC_SAMA5D2_CBC_OFFSET 0 -+/* Offset for CBC register specific to sama7g5 product */ -+#define ISC_SAMA7G5_CBC_OFFSET 0x11c - - /* Contrast And Brightness Control Register */ - #define ISC_CBC_CTRL 0x000003b4 -@@ -261,18 +268,30 @@ - #define ISC_CBC_CONTRAST 0x000003c0 - #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) - -+/* Hue Register */ -+#define ISC_CBCHS_HUE 0x4e0 -+/* Saturation Register */ -+#define ISC_CBCHS_SAT 0x4e4 -+ - /* Offset for SUB422 register specific to sama5d2 product */ - #define ISC_SAMA5D2_SUB422_OFFSET 0 -+/* Offset for SUB422 register specific to sama7g5 product */ -+#define ISC_SAMA7G5_SUB422_OFFSET 0x124 -+ - /* Subsampling 4:4:4 to 4:2:2 Control Register */ - #define ISC_SUB422_CTRL 0x000003c4 - - /* Offset for SUB420 register specific to sama5d2 product */ - #define ISC_SAMA5D2_SUB420_OFFSET 0 -+/* Offset for SUB420 register specific to sama7g5 product */ -+#define ISC_SAMA7G5_SUB420_OFFSET 0x124 - /* Subsampling 4:2:2 to 4:2:0 Control Register */ - #define ISC_SUB420_CTRL 0x000003cc - - /* Offset for RLP register specific to sama5d2 product */ - #define ISC_SAMA5D2_RLP_OFFSET 0 -+/* Offset for RLP register specific to sama7g5 product */ -+#define ISC_SAMA7G5_RLP_OFFSET 0x124 - /* Rounding, Limiting and Packing Configuration Register */ - #define ISC_RLP_CFG 0x000003d0 - -@@ -303,6 +322,8 @@ - - /* Offset for HIS register specific to sama5d2 product */ - #define ISC_SAMA5D2_HIS_OFFSET 0 -+/* Offset for HIS register specific to sama7g5 product */ -+#define ISC_SAMA7G5_HIS_OFFSET 0x124 - /* Histogram Control Register */ - #define ISC_HIS_CTRL 0x000003d4 - -@@ -326,6 +347,8 @@ - - /* Offset for DMA register specific to sama5d2 product */ - #define ISC_SAMA5D2_DMA_OFFSET 0 -+/* Offset for DMA register specific to sama7g5 product */ -+#define ISC_SAMA7G5_DMA_OFFSET 0x13c - - /* DMA Configuration Register */ - #define ISC_DCFG 0x000003e0 -@@ -376,11 +399,14 @@ - - /* Offset for version register specific to sama5d2 product */ - #define ISC_SAMA5D2_VERSION_OFFSET 0 -+#define ISC_SAMA7G5_VERSION_OFFSET 0x13c - /* Version Register */ - #define ISC_VERSION 0x0000040c - - /* Offset for version register specific to sama5d2 product */ - #define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 -+/* Offset for version register specific to sama7g5 product */ -+#define ISC_SAMA7G5_HIS_ENTRY_OFFSET 0x14c - /* Histogram Entry */ - #define ISC_HIS_ENTRY 0x00000410 - ---- /dev/null -+++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c -@@ -0,0 +1,630 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Microchip eXtended Image Sensor Controller (XISC) driver -+ * -+ * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries -+ * -+ * Author: Eugen Hristev -+ * -+ * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS -+ * -+ * ISC video pipeline integrates the following submodules: -+ * PFE: Parallel Front End to sample the camera sensor input stream -+ * DPC: Defective Pixel Correction with black offset correction, green disparity -+ * correction and defective pixel correction (3 modules total) -+ * WB: Programmable white balance in the Bayer domain -+ * CFA: Color filter array interpolation module -+ * CC: Programmable color correction -+ * GAM: Gamma correction -+ *VHXS: Vertical and Horizontal Scaler -+ * CSC: Programmable color space conversion -+ *CBHS: Contrast Brightness Hue and Saturation control -+ * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling -+ * RLP: This module performs rounding, range limiting -+ * and packing of the incoming data -+ * DMA: This module performs DMA master accesses to write frames to external RAM -+ * HIS: Histogram module performs statistic counters on the frames -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "atmel-isc-regs.h" -+#include "atmel-isc.h" -+ -+#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH 3264 -+#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT 2464 -+ -+#define ISC_SAMA7G5_PIPELINE \ -+ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ -+ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) -+ -+/* This is a list of the formats that the ISC can *output* */ -+static const struct isc_format sama7g5_controller_formats[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_ARGB444, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_ARGB555, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_RGB565, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_ABGR32, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_XBGR32, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV420, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_UYVY, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_VYUY, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUYV, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUV422P, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_GREY, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y10, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y16, -+ }, -+}; -+ -+/* This is a list of formats that the ISC can receive as *input* */ -+static struct isc_format sama7g5_formats_list[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR8, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_BGBG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG8, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG8, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB8, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR10, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG10, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG10, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB10, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SBGGR12, -+ .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_BGBG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGBRG12, -+ .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_GBGB, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SGRBG12, -+ .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_GRGR, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_SRGGB12, -+ .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, -+ .cfa_baycfg = ISC_BAY_CFG_RGRG, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_GREY, -+ .mbus_code = MEDIA_BUS_FMT_Y8_1X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_YUYV, -+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_UYVY, -+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_RGB565, -+ .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, -+ .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_Y10, -+ .mbus_code = MEDIA_BUS_FMT_Y10_1X10, -+ .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, -+ }, -+ -+}; -+ -+static void isc_sama7g5_config_csc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Convert RGB to YUV */ -+ regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, -+ 0x42 | (0x81 << 16)); -+ regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, -+ 0x19 | (0x10 << 16)); -+ regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, -+ 0xFDA | (0xFB6 << 16)); -+ regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, -+ 0x70 | (0x80 << 16)); -+ regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, -+ 0x70 | (0xFA2 << 16)); -+ regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, -+ 0xFEE | (0x80 << 16)); -+} -+ -+static void isc_sama7g5_config_cbc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Configure what is set via v4l2 ctrls */ -+ regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness); -+ regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast); -+ /* Configure Hue and Saturation as neutral midpoint */ -+ regmap_write(regmap, ISC_CBCHS_HUE, 0); -+ regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4)); -+} -+ -+static void isc_sama7g5_config_cc(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ /* Configure each register at the neutral fixed point 1.0 or 0.0 */ -+ regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); -+ regmap_write(regmap, ISC_CC_RB_OR, 0); -+ regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); -+ regmap_write(regmap, ISC_CC_GB_OG, 0); -+ regmap_write(regmap, ISC_CC_BR_BG, 0); -+ regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); -+} -+ -+static void isc_sama7g5_config_ctrls(struct isc_device *isc, -+ const struct v4l2_ctrl_ops *ops) -+{ -+ struct isc_ctrls *ctrls = &isc->ctrls; -+ struct v4l2_ctrl_handler *hdl = &ctrls->handler; -+ -+ ctrls->contrast = 16; -+ -+ v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16); -+} -+ -+static void isc_sama7g5_config_dpc(struct isc_device *isc) -+{ -+ u32 bay_cfg = isc->config.sd_format->cfa_baycfg; -+ struct regmap *regmap = isc->regmap; -+ -+ regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK, -+ (64 << ISC_DPC_CFG_BLOFF_SHIFT)); -+ regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK, -+ (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT)); -+} -+ -+static void isc_sama7g5_config_gam(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ -+ regmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART, -+ ISC_GAM_CTRL_BIPART); -+} -+ -+static void isc_sama7g5_config_rlp(struct isc_device *isc) -+{ -+ struct regmap *regmap = isc->regmap; -+ u32 rlp_mode = isc->config.rlp_cfg_mode; -+ -+ regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, -+ ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH | -+ ISC_RLP_CFG_YMODE_MASK, rlp_mode); -+} -+ -+static void isc_sama7g5_adapt_pipeline(struct isc_device *isc) -+{ -+ isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE; -+} -+ -+/* Gamma table with gamma 1/2.2 */ -+static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = { -+ /* index 0 --> gamma bipartite */ -+ { -+ 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, -+ 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, -+ 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, -+ 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, -+ 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, -+ 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, -+ 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, -+ 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, -+ 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, -+ 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, -+ 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, -+}; -+ -+static int xisc_parse_dt(struct device *dev, struct isc_device *isc) -+{ -+ struct device_node *np = dev->of_node; -+ struct device_node *epn = NULL; -+ struct isc_subdev_entity *subdev_entity; -+ unsigned int flags; -+ int ret; -+ bool mipi_mode; -+ -+ INIT_LIST_HEAD(&isc->subdev_entities); -+ -+ mipi_mode = of_property_read_bool(np, "microchip,mipi-mode"); -+ -+ while (1) { -+ struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 }; -+ -+ epn = of_graph_get_next_endpoint(np, epn); -+ if (!epn) -+ return 0; -+ -+ ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), -+ &v4l2_epn); -+ if (ret) { -+ ret = -EINVAL; -+ dev_err(dev, "Could not parse the endpoint\n"); -+ break; -+ } -+ -+ subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity), -+ GFP_KERNEL); -+ if (!subdev_entity) { -+ ret = -ENOMEM; -+ break; -+ } -+ subdev_entity->epn = epn; -+ -+ flags = v4l2_epn.bus.parallel.flags; -+ -+ if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) -+ subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW; -+ -+ if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) -+ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW; -+ -+ if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) -+ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW; -+ -+ if (v4l2_epn.bus_type == V4L2_MBUS_BT656) -+ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC | -+ ISC_PFE_CFG0_CCIR656; -+ -+ if (mipi_mode) -+ subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI; -+ -+ list_add_tail(&subdev_entity->list, &isc->subdev_entities); -+ } -+ of_node_put(epn); -+ -+ return ret; -+} -+ -+static int microchip_xisc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct isc_device *isc; -+ struct resource *res; -+ void __iomem *io_base; -+ struct isc_subdev_entity *subdev_entity; -+ int irq; -+ int ret; -+ u32 ver; -+ -+ isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); -+ if (!isc) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, isc); -+ isc->dev = dev; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ io_base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(io_base)) -+ return PTR_ERR(io_base); -+ -+ isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config); -+ if (IS_ERR(isc->regmap)) { -+ ret = PTR_ERR(isc->regmap); -+ dev_err(dev, "failed to init register map: %d\n", ret); -+ return ret; -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return irq; -+ -+ ret = devm_request_irq(dev, irq, isc_interrupt, 0, -+ "microchip-sama7g5-xisc", isc); -+ if (ret < 0) { -+ dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", -+ irq, ret); -+ return ret; -+ } -+ -+ isc->gamma_table = isc_sama7g5_gamma_table; -+ isc->gamma_max = 0; -+ -+ isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH; -+ isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; -+ -+ isc->config_dpc = isc_sama7g5_config_dpc; -+ isc->config_csc = isc_sama7g5_config_csc; -+ isc->config_cbc = isc_sama7g5_config_cbc; -+ isc->config_cc = isc_sama7g5_config_cc; -+ isc->config_gam = isc_sama7g5_config_gam; -+ isc->config_rlp = isc_sama7g5_config_rlp; -+ isc->config_ctrls = isc_sama7g5_config_ctrls; -+ -+ isc->adapt_pipeline = isc_sama7g5_adapt_pipeline; -+ -+ isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; -+ isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET; -+ isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET; -+ isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET; -+ isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET; -+ isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET; -+ isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET; -+ isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET; -+ isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET; -+ -+ isc->controller_formats = sama7g5_controller_formats; -+ isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats); -+ isc->formats_list = sama7g5_formats_list; -+ isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list); -+ -+ /* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */ -+ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32; -+ -+ ret = isc_pipeline_init(isc); -+ if (ret) -+ return ret; -+ -+ isc->hclock = devm_clk_get(dev, "hclock"); -+ if (IS_ERR(isc->hclock)) { -+ ret = PTR_ERR(isc->hclock); -+ dev_err(dev, "failed to get hclock: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(isc->hclock); -+ if (ret) { -+ dev_err(dev, "failed to enable hclock: %d\n", ret); -+ return ret; -+ } -+ -+ ret = isc_clk_init(isc); -+ if (ret) { -+ dev_err(dev, "failed to init isc clock: %d\n", ret); -+ goto unprepare_hclk; -+ } -+ -+ isc->ispck = isc->isc_clks[ISC_ISPCK].clk; -+ -+ ret = clk_prepare_enable(isc->ispck); -+ if (ret) { -+ dev_err(dev, "failed to enable ispck: %d\n", ret); -+ goto unprepare_hclk; -+ } -+ -+ /* ispck should be greater or equal to hclock */ -+ ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock)); -+ if (ret) { -+ dev_err(dev, "failed to set ispck rate: %d\n", ret); -+ goto unprepare_clk; -+ } -+ -+ ret = v4l2_device_register(dev, &isc->v4l2_dev); -+ if (ret) { -+ dev_err(dev, "unable to register v4l2 device.\n"); -+ goto unprepare_clk; -+ } -+ -+ ret = xisc_parse_dt(dev, isc); -+ if (ret) { -+ dev_err(dev, "fail to parse device tree\n"); -+ goto unregister_v4l2_device; -+ } -+ -+ if (list_empty(&isc->subdev_entities)) { -+ dev_err(dev, "no subdev found\n"); -+ ret = -ENODEV; -+ goto unregister_v4l2_device; -+ } -+ -+ list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { -+ struct v4l2_async_subdev *asd; -+ -+ v4l2_async_notifier_init(&subdev_entity->notifier); -+ -+ asd = v4l2_async_notifier_add_fwnode_remote_subdev( -+ &subdev_entity->notifier, -+ of_fwnode_handle(subdev_entity->epn), -+ struct v4l2_async_subdev); -+ -+ of_node_put(subdev_entity->epn); -+ subdev_entity->epn = NULL; -+ -+ if (IS_ERR(asd)) { -+ ret = PTR_ERR(asd); -+ goto cleanup_subdev; -+ } -+ -+ subdev_entity->notifier.ops = &isc_async_ops; -+ -+ ret = v4l2_async_notifier_register(&isc->v4l2_dev, -+ &subdev_entity->notifier); -+ if (ret) { -+ dev_err(dev, "fail to register async notifier\n"); -+ goto cleanup_subdev; -+ } -+ -+ if (video_is_registered(&isc->video_dev)) -+ break; -+ } -+ -+ pm_runtime_set_active(dev); -+ pm_runtime_enable(dev); -+ pm_request_idle(dev); -+ -+ regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); -+ dev_info(dev, "Microchip XISC version %x\n", ver); -+ -+ return 0; -+ -+cleanup_subdev: -+ isc_subdev_cleanup(isc); -+ -+unregister_v4l2_device: -+ v4l2_device_unregister(&isc->v4l2_dev); -+ -+unprepare_clk: -+ clk_disable_unprepare(isc->ispck); -+unprepare_hclk: -+ clk_disable_unprepare(isc->hclock); -+ -+ isc_clk_cleanup(isc); -+ -+ return ret; -+} -+ -+static int microchip_xisc_remove(struct platform_device *pdev) -+{ -+ struct isc_device *isc = platform_get_drvdata(pdev); -+ -+ pm_runtime_disable(&pdev->dev); -+ -+ isc_subdev_cleanup(isc); -+ -+ v4l2_device_unregister(&isc->v4l2_dev); -+ -+ clk_disable_unprepare(isc->ispck); -+ clk_disable_unprepare(isc->hclock); -+ -+ isc_clk_cleanup(isc); -+ -+ return 0; -+} -+ -+static int __maybe_unused xisc_runtime_suspend(struct device *dev) -+{ -+ struct isc_device *isc = dev_get_drvdata(dev); -+ -+ clk_disable_unprepare(isc->ispck); -+ clk_disable_unprepare(isc->hclock); -+ -+ return 0; -+} -+ -+static int __maybe_unused xisc_runtime_resume(struct device *dev) -+{ -+ struct isc_device *isc = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = clk_prepare_enable(isc->hclock); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(isc->ispck); -+ if (ret) -+ clk_disable_unprepare(isc->hclock); -+ -+ return ret; -+} -+ -+static const struct dev_pm_ops microchip_xisc_dev_pm_ops = { -+ SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL) -+}; -+ -+static const struct of_device_id microchip_xisc_of_match[] = { -+ { .compatible = "microchip,sama7g5-isc" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, microchip_xisc_of_match); -+ -+static struct platform_driver microchip_xisc_driver = { -+ .probe = microchip_xisc_probe, -+ .remove = microchip_xisc_remove, -+ .driver = { -+ .name = "microchip-sama7g5-xisc", -+ .pm = µchip_xisc_dev_pm_ops, -+ .of_match_table = of_match_ptr(microchip_xisc_of_match), -+ }, -+}; -+ -+module_platform_driver(microchip_xisc_driver); -+ -+MODULE_AUTHOR("Eugen Hristev "); -+MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/at91/patches-5.10/186-ASoC-atmel-fix-shadowed-variable.patch b/target/linux/at91/patches-5.10/186-ASoC-atmel-fix-shadowed-variable.patch deleted file mode 100644 index 7e88bb39ce..0000000000 --- a/target/linux/at91/patches-5.10/186-ASoC-atmel-fix-shadowed-variable.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 1b41c69264d7233a3e9a0aa36333ee22a5a049e9 Mon Sep 17 00:00:00 2001 -From: Pierre-Louis Bossart -Date: Fri, 26 Mar 2021 16:59:12 -0500 -Subject: [PATCH 186/247] ASoC: atmel: fix shadowed variable - -Fix cppcheck warning: - -sound/soc/atmel/atmel-classd.c:51:14: style: Local variable 'pwm_type' -shadows outer variable [shadowVariable] - const char *pwm_type; - ^ -sound/soc/atmel/atmel-classd.c:226:27: note: Shadowed declaration -static const char * const pwm_type[] = { - ^ -sound/soc/atmel/atmel-classd.c:51:14: note: Shadow variable - const char *pwm_type; - ^ - -Signed-off-by: Pierre-Louis Bossart -Reviewed-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210326215927.936377-3-pierre-louis.bossart@linux.intel.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-classd.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/sound/soc/atmel/atmel-classd.c -+++ b/sound/soc/atmel/atmel-classd.c -@@ -48,7 +48,7 @@ static struct atmel_classd_pdata *atmel_ - { - struct device_node *np = dev->of_node; - struct atmel_classd_pdata *pdata; -- const char *pwm_type; -+ const char *pwm_type_s; - int ret; - - if (!np) { -@@ -60,8 +60,8 @@ static struct atmel_classd_pdata *atmel_ - if (!pdata) - return ERR_PTR(-ENOMEM); - -- ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type); -- if ((ret == 0) && (strcmp(pwm_type, "diff") == 0)) -+ ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type_s); -+ if ((ret == 0) && (strcmp(pwm_type_s, "diff") == 0)) - pdata->pwm_type = CLASSD_MR_PWMTYP_DIFF; - else - pdata->pwm_type = CLASSD_MR_PWMTYP_SINGLE; diff --git a/target/linux/at91/patches-5.10/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch b/target/linux/at91/patches-5.10/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch deleted file mode 100644 index ed2ae1a979..0000000000 --- a/target/linux/at91/patches-5.10/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e53725fe0c7e6b52927280272f49fe5f4b4ef317 Mon Sep 17 00:00:00 2001 -From: Pierre-Louis Bossart -Date: Fri, 26 Mar 2021 16:59:13 -0500 -Subject: [PATCH 187/247] ASoC: atmel: atmel-i2s: remove useless initialization - -Cppcheck complains: - -sound/soc/atmel/atmel-i2s.c:628:6: style: Redundant initialization for 'err'. The initialized value is overwritten before it is read. [redundantInitialization] - err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0, - ^ -sound/soc/atmel/atmel-i2s.c:598:10: note: err is initialized - int err = -ENXIO; - ^ -sound/soc/atmel/atmel-i2s.c:628:6: note: err is overwritten - err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0, - ^ - -Signed-off-by: Pierre-Louis Bossart -Reviewed-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210326215927.936377-4-pierre-louis.bossart@linux.intel.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-i2s.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/sound/soc/atmel/atmel-i2s.c -+++ b/sound/soc/atmel/atmel-i2s.c -@@ -613,7 +613,7 @@ static int atmel_i2s_probe(struct platfo - struct regmap *regmap; - void __iomem *base; - int irq; -- int err = -ENXIO; -+ int err; - unsigned int pcm_flags = 0; - unsigned int version; - diff --git a/target/linux/at91/patches-5.10/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch b/target/linux/at91/patches-5.10/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch deleted file mode 100644 index bc8c7fa2b1..0000000000 --- a/target/linux/at91/patches-5.10/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch +++ /dev/null @@ -1,26 +0,0 @@ -From a6f337fdf68294cfae233724567cbeea0ae5148f Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Fri, 18 Jun 2021 18:07:40 +0300 -Subject: [PATCH 188/247] ASoC: atmel-i2s: Set symmetric sample bits - -The I2S needs to have the same sample bits for both capture and playback -streams. - -Fixes: b543e467d1a9 ("ASoC: atmel-i2s: add driver for the new Atmel I2S controller") -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210618150741.401739-1-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/atmel/atmel-i2s.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/sound/soc/atmel/atmel-i2s.c -+++ b/sound/soc/atmel/atmel-i2s.c -@@ -560,6 +560,7 @@ static struct snd_soc_dai_driver atmel_i - }, - .ops = &atmel_i2s_dai_ops, - .symmetric_rates = 1, -+ .symmetric_samplebits = 1, - }; - - static const struct snd_soc_component_driver atmel_i2s_component = { diff --git a/target/linux/at91/patches-5.10/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch b/target/linux/at91/patches-5.10/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch deleted file mode 100644 index b79ccadf92..0000000000 --- a/target/linux/at91/patches-5.10/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch +++ /dev/null @@ -1,46 +0,0 @@ -From ff83cc9f95aaba75991210312061b7fe52aaa400 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 27 May 2021 13:01:19 +0300 -Subject: [PATCH 189/247] watchdog: sama5d4_wdt: add support for sama7g5-wdt - -Add support for compatible sama7g5-wdt. -The sama7g5 wdt is the same hardware block as on sam9x60. -Adapt the driver to use the sam9x60/sama7g5 variant if either -of the two compatibles are selected (sam9x60-wdt/sama7g5-wdt). - -Signed-off-by: Eugen Hristev -Acked-by: Nicolas Ferre -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20210527100120.266796-2-eugen.hristev@microchip.com -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/sama5d4_wdt.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - ---- a/drivers/watchdog/sama5d4_wdt.c -+++ b/drivers/watchdog/sama5d4_wdt.c -@@ -268,8 +268,10 @@ static int sama5d4_wdt_probe(struct plat - wdd->min_timeout = MIN_WDT_TIMEOUT; - wdd->max_timeout = MAX_WDT_TIMEOUT; - wdt->last_ping = jiffies; -- wdt->sam9x60_support = of_device_is_compatible(dev->of_node, -- "microchip,sam9x60-wdt"); -+ -+ if (of_device_is_compatible(dev->of_node, "microchip,sam9x60-wdt") || -+ of_device_is_compatible(dev->of_node, "microchip,sama7g5-wdt")) -+ wdt->sam9x60_support = true; - - watchdog_set_drvdata(wdd, wdt); - -@@ -329,6 +331,10 @@ static const struct of_device_id sama5d4 - { - .compatible = "microchip,sam9x60-wdt", - }, -+ { -+ .compatible = "microchip,sama7g5-wdt", -+ }, -+ - { } - }; - MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match); diff --git a/target/linux/at91/patches-5.10/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch b/target/linux/at91/patches-5.10/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch deleted file mode 100644 index 60b4104442..0000000000 --- a/target/linux/at91/patches-5.10/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch +++ /dev/null @@ -1,135 +0,0 @@ -From dfcc0395f5e838c0b5c3fb93c9335b6a8892178a Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 5 Jul 2021 14:57:08 +0200 -Subject: [PATCH 190/247] media: atmel: fix build when ISC=m and XISC=y - -Building VIDEO_ATMEL_ISC as module and VIDEO_ATMEL_XISC as built-in -(or viceversa) causes build errors: - - or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o: in function `isc_async_complete': - atmel-isc-base.c:(.text+0x40d0): undefined reference to `__this_module' - or1k-linux-ld: atmel-isc-base.c:(.text+0x40f0): undefined reference to `__this_module' - or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(.rodata+0x390): undefined reference to `__this_module' - or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x4): undefined reference to `__this_module' - or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x18): undefined reference to `__this_module' - -This is caused by the file atmel-isc-base.c which is common code between -the two drivers. - -The solution is to create another Kconfig symbol that is automatically -selected and generates the module atmel-isc-base.ko. This module can be -loaded when both drivers are modules, or built-in when at least one of them -is built-in. - -Reported-by: kernel test robot -Fixes: c9aa973884a1 ("media: atmel: atmel-isc: add microchip-xisc driver") -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/platform/atmel/Kconfig | 8 ++++++++ - drivers/media/platform/atmel/Makefile | 5 +++-- - drivers/media/platform/atmel/atmel-isc-base.c | 11 +++++++++++ - 3 files changed, 22 insertions(+), 2 deletions(-) - ---- a/drivers/media/platform/atmel/Kconfig -+++ b/drivers/media/platform/atmel/Kconfig -@@ -8,6 +8,7 @@ config VIDEO_ATMEL_ISC - select VIDEOBUF2_DMA_CONTIG - select REGMAP_MMIO - select V4L2_FWNODE -+ select VIDEO_ATMEL_ISC_BASE - help - This module makes the ATMEL Image Sensor Controller available - as a v4l2 device. -@@ -19,10 +20,17 @@ config VIDEO_ATMEL_XISC - select VIDEOBUF2_DMA_CONTIG - select REGMAP_MMIO - select V4L2_FWNODE -+ select VIDEO_ATMEL_ISC_BASE - help - This module makes the ATMEL eXtended Image Sensor Controller - available as a v4l2 device. - -+config VIDEO_ATMEL_ISC_BASE -+ tristate -+ default n -+ help -+ ATMEL ISC and XISC common code base. -+ - config VIDEO_ATMEL_ISI - tristate "ATMEL Image Sensor Interface (ISI) support" - depends on VIDEO_V4L2 && OF ---- a/drivers/media/platform/atmel/Makefile -+++ b/drivers/media/platform/atmel/Makefile -@@ -1,7 +1,8 @@ - # SPDX-License-Identifier: GPL-2.0-only --atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o --atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o -+atmel-isc-objs = atmel-sama5d2-isc.o -+atmel-xisc-objs = atmel-sama7g5-isc.o - - obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o -+obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o - obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o - obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o ---- a/drivers/media/platform/atmel/atmel-isc-base.c -+++ b/drivers/media/platform/atmel/atmel-isc-base.c -@@ -378,6 +378,7 @@ int isc_clk_init(struct isc_device *isc) - - return 0; - } -+EXPORT_SYMBOL_GPL(isc_clk_init); - - void isc_clk_cleanup(struct isc_device *isc) - { -@@ -392,6 +393,7 @@ void isc_clk_cleanup(struct isc_device * - clk_unregister(isc_clk->clk); - } - } -+EXPORT_SYMBOL_GPL(isc_clk_cleanup); - - static int isc_queue_setup(struct vb2_queue *vq, - unsigned int *nbuffers, unsigned int *nplanes, -@@ -1575,6 +1577,7 @@ irqreturn_t isc_interrupt(int irq, void - - return ret; - } -+EXPORT_SYMBOL_GPL(isc_interrupt); - - static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max) - { -@@ -2209,6 +2212,7 @@ const struct v4l2_async_notifier_operati - .unbind = isc_async_unbind, - .complete = isc_async_complete, - }; -+EXPORT_SYMBOL_GPL(isc_async_ops); - - void isc_subdev_cleanup(struct isc_device *isc) - { -@@ -2221,6 +2225,7 @@ void isc_subdev_cleanup(struct isc_devic - - INIT_LIST_HEAD(&isc->subdev_entities); - } -+EXPORT_SYMBOL_GPL(isc_subdev_cleanup); - - int isc_pipeline_init(struct isc_device *isc) - { -@@ -2261,6 +2266,7 @@ int isc_pipeline_init(struct isc_device - - return 0; - } -+EXPORT_SYMBOL_GPL(isc_pipeline_init); - - /* regmap configuration */ - #define ATMEL_ISC_REG_MAX 0xd5c -@@ -2270,4 +2276,9 @@ const struct regmap_config isc_regmap_co - .val_bits = 32, - .max_register = ATMEL_ISC_REG_MAX, - }; -+EXPORT_SYMBOL_GPL(isc_regmap_config); - -+MODULE_AUTHOR("Songjun Wu"); -+MODULE_AUTHOR("Eugen Hristev"); -+MODULE_DESCRIPTION("Atmel ISC common code base"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/at91/patches-5.10/191-i2c-at91-remove-define-CONFIG_PM.patch b/target/linux/at91/patches-5.10/191-i2c-at91-remove-define-CONFIG_PM.patch deleted file mode 100644 index 27ee1b6d19..0000000000 --- a/target/linux/at91/patches-5.10/191-i2c-at91-remove-define-CONFIG_PM.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 023a6b46536dce41f2c5a7425826fc4da4509b8f Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 5 Jul 2021 15:15:16 +0300 -Subject: [PATCH 191/247] i2c: at91: remove #define CONFIG_PM - -Remove #define CONFIG_PM and use __maybe_unused for PM functions and -pm_ptr() for PM ops. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Codrin Ciubotariu -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-at91-core.c | 17 +++++------------ - 1 file changed, 5 insertions(+), 12 deletions(-) - ---- a/drivers/i2c/busses/i2c-at91-core.c -+++ b/drivers/i2c/busses/i2c-at91-core.c -@@ -286,9 +286,7 @@ static int at91_twi_remove(struct platfo - return 0; - } - --#ifdef CONFIG_PM -- --static int at91_twi_runtime_suspend(struct device *dev) -+static int __maybe_unused at91_twi_runtime_suspend(struct device *dev) - { - struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); - -@@ -299,7 +297,7 @@ static int at91_twi_runtime_suspend(stru - return 0; - } - --static int at91_twi_runtime_resume(struct device *dev) -+static int __maybe_unused at91_twi_runtime_resume(struct device *dev) - { - struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); - -@@ -308,7 +306,7 @@ static int at91_twi_runtime_resume(struc - return clk_prepare_enable(twi_dev->clk); - } - --static int at91_twi_suspend_noirq(struct device *dev) -+static int __maybe_unused at91_twi_suspend_noirq(struct device *dev) - { - if (!pm_runtime_status_suspended(dev)) - at91_twi_runtime_suspend(dev); -@@ -316,7 +314,7 @@ static int at91_twi_suspend_noirq(struct - return 0; - } - --static int at91_twi_resume_noirq(struct device *dev) -+static int __maybe_unused at91_twi_resume_noirq(struct device *dev) - { - struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); - int ret; -@@ -342,11 +340,6 @@ static const struct dev_pm_ops at91_twi_ - .runtime_resume = at91_twi_runtime_resume, - }; - --#define at91_twi_pm_ops (&at91_twi_pm) --#else --#define at91_twi_pm_ops NULL --#endif -- - static struct platform_driver at91_twi_driver = { - .probe = at91_twi_probe, - .remove = at91_twi_remove, -@@ -354,7 +347,7 @@ static struct platform_driver at91_twi_d - .driver = { - .name = "at91_i2c", - .of_match_table = of_match_ptr(atmel_twi_dt_ids), -- .pm = at91_twi_pm_ops, -+ .pm = pm_ptr(&at91_twi_pm), - }, - }; - diff --git a/target/linux/at91/patches-5.10/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch b/target/linux/at91/patches-5.10/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch deleted file mode 100644 index 6220c1dab2..0000000000 --- a/target/linux/at91/patches-5.10/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 1c906a59a60887e1b997ebab63f19f33a1c69a3e Mon Sep 17 00:00:00 2001 -From: Codrin Ciubotariu -Date: Tue, 3 Aug 2021 13:48:25 +0300 -Subject: [PATCH 192/247] ASoC: codecs: ad193x: add support for 96kHz and - 192kHz playback rates - -ad193x devices support 96KHz and 192KHz sampling rates, when PLL/MCLK is -referenced to 48kHz. -Tested on ad1934. - -Signed-off-by: Codrin Ciubotariu -Link: https://lore.kernel.org/r/20210803104825.2198335-1-codrin.ciubotariu@microchip.com -Signed-off-by: Mark Brown ---- - sound/soc/codecs/ad193x.c | 30 ++++++++++++++++++++++++++++-- - sound/soc/codecs/ad193x.h | 4 ++++ - 2 files changed, 32 insertions(+), 2 deletions(-) - ---- a/sound/soc/codecs/ad193x.c -+++ b/sound/soc/codecs/ad193x.c -@@ -316,6 +316,13 @@ static int ad193x_hw_params(struct snd_p - int word_len = 0, master_rate = 0; - struct snd_soc_component *component = dai->component; - struct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component); -+ bool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; -+ u8 dacc0; -+ -+ dev_dbg(dai->dev, "%s() rate=%u format=%#x width=%u channels=%u\n", -+ __func__, params_rate(params), params_format(params), -+ params_width(params), params_channels(params)); -+ - - /* bit size */ - switch (params_width(params)) { -@@ -346,6 +353,25 @@ static int ad193x_hw_params(struct snd_p - break; - } - -+ if (is_playback) { -+ switch (params_rate(params)) { -+ case 48000: -+ dacc0 = AD193X_DAC_SR_48; -+ break; -+ case 96000: -+ dacc0 = AD193X_DAC_SR_96; -+ break; -+ case 192000: -+ dacc0 = AD193X_DAC_SR_192; -+ break; -+ default: -+ dev_err(dai->dev, "invalid sampling rate: %d\n", params_rate(params)); -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL0, AD193X_DAC_SR_MASK, dacc0); -+ } -+ - regmap_update_bits(ad193x->regmap, AD193X_PLL_CLK_CTRL0, - AD193X_PLL_INPUT_MASK, master_rate); - -@@ -385,7 +411,7 @@ static struct snd_soc_dai_driver ad193x_ - .stream_name = "Playback", - .channels_min = 2, - .channels_max = 8, -- .rates = SNDRV_PCM_RATE_48000, -+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE, - }, -@@ -407,7 +433,7 @@ static struct snd_soc_dai_driver ad193x_ - .stream_name = "Playback", - .channels_min = 2, - .channels_max = 8, -- .rates = SNDRV_PCM_RATE_48000, -+ .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE, - }, ---- a/sound/soc/codecs/ad193x.h -+++ b/sound/soc/codecs/ad193x.h -@@ -37,6 +37,10 @@ int ad193x_probe(struct device *dev, str - #define AD193X_PLL_CLK_SRC_MCLK (1 << 1) - #define AD193X_DAC_CTRL0 0x02 - #define AD193X_DAC_POWERDOWN 0x01 -+#define AD193X_DAC_SR_MASK 0x06 -+#define AD193X_DAC_SR_48 (0 << 1) -+#define AD193X_DAC_SR_96 (1 << 1) -+#define AD193X_DAC_SR_192 (2 << 1) - #define AD193X_DAC_SERFMT_MASK 0xC0 - #define AD193X_DAC_SERFMT_STEREO (0 << 6) - #define AD193X_DAC_SERFMT_TDM (1 << 6) diff --git a/target/linux/at91/patches-5.10/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch b/target/linux/at91/patches-5.10/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch deleted file mode 100644 index a554a288a5..0000000000 --- a/target/linux/at91/patches-5.10/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 21261e30679118b96ed537d1cdf9e12682fc1b29 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Wed, 9 Jun 2021 15:00:28 +0200 -Subject: [PATCH 193/247] media: atmel: atmel-sama5d2-isc: fix YUYV format - -SAMA5D2 does not have the YCYC field for the RLP (rounding, limiting, -packaging) module. -The YCYC field is supposed to work with interleaved YUV formats like YUYV. -In SAMA5D2, we have to use YYCC field, which is used for both planar -formats like YUV420 and interleaved formats like YUYV. -Fix the according rlp callback to replace the generic YCYC field (which -makes more sense from a logical point of view) with the required YYCC -field. - -Fixes: debfa496871c ("media: atmel: atmel-isc-base: add support for more formats and additional pipeline modules") -Signed-off-by: Eugen Hristev -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../media/platform/atmel/atmel-sama5d2-isc.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c -+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c -@@ -255,6 +255,23 @@ static void isc_sama5d2_config_rlp(struc - struct regmap *regmap = isc->regmap; - u32 rlp_mode = isc->config.rlp_cfg_mode; - -+ /* -+ * In sama5d2, the YUV planar modes and the YUYV modes are treated -+ * in the same way in RLP register. -+ * Normally, YYCC mode should be Luma(n) - Color B(n) - Color R (n) -+ * and YCYC should be Luma(n + 1) - Color B (n) - Luma (n) - Color R (n) -+ * but in sama5d2, the YCYC mode does not exist, and YYCC must be -+ * selected for both planar and interleaved modes, as in fact -+ * both modes are supported. -+ * -+ * Thus, if the YCYC mode is selected, replace it with the -+ * sama5d2-compliant mode which is YYCC . -+ */ -+ if ((rlp_mode & ISC_RLP_CFG_MODE_YCYC) == ISC_RLP_CFG_MODE_YCYC) { -+ rlp_mode &= ~ISC_RLP_CFG_MODE_MASK; -+ rlp_mode |= ISC_RLP_CFG_MODE_YYCC; -+ } -+ - regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, - ISC_RLP_CFG_MODE_MASK, rlp_mode); - } diff --git a/target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch b/target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch deleted file mode 100644 index dd221f5be9..0000000000 --- a/target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 602f85ff15d45bd313f8f6600d72202a50fd83a9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 19 Jul 2021 11:03:17 +0300 -Subject: [PATCH 194/247] clk: at91: add register definition for sama7g5's - master clock - -Add register definitions for SAMA7G5's master clock. These would be -also used by architecture specific power saving code. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210719080317.1045832-3-claudiu.beznea@microchip.com ---- - include/linux/clk/at91_pmc.h | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/include/linux/clk/at91_pmc.h -+++ b/include/linux/clk/at91_pmc.h -@@ -137,6 +137,32 @@ - #define AT91_PMC_PLLADIV2_ON (1 << 12) - #define AT91_PMC_H32MXDIV BIT(24) - -+#define AT91_PMC_MCR_V2 0x30 /* Master Clock Register [SAMA7G5 only] */ -+#define AT91_PMC_MCR_V2_ID_MSK (0xF) -+#define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MSK) -+#define AT91_PMC_MCR_V2_CMD (1 << 7) -+#define AT91_PMC_MCR_V2_DIV (7 << 8) -+#define AT91_PMC_MCR_V2_DIV1 (0 << 8) -+#define AT91_PMC_MCR_V2_DIV2 (1 << 8) -+#define AT91_PMC_MCR_V2_DIV4 (2 << 8) -+#define AT91_PMC_MCR_V2_DIV8 (3 << 8) -+#define AT91_PMC_MCR_V2_DIV16 (4 << 8) -+#define AT91_PMC_MCR_V2_DIV32 (5 << 8) -+#define AT91_PMC_MCR_V2_DIV64 (6 << 8) -+#define AT91_PMC_MCR_V2_DIV3 (7 << 8) -+#define AT91_PMC_MCR_V2_CSS (0x1F << 16) -+#define AT91_PMC_MCR_V2_CSS_MD_SLCK (0 << 16) -+#define AT91_PMC_MCR_V2_CSS_TD_SLCK (1 << 16) -+#define AT91_PMC_MCR_V2_CSS_MAINCK (2 << 16) -+#define AT91_PMC_MCR_V2_CSS_MCK0 (3 << 16) -+#define AT91_PMC_MCR_V2_CSS_SYSPLL (5 << 16) -+#define AT91_PMC_MCR_V2_CSS_DDRPLL (6 << 16) -+#define AT91_PMC_MCR_V2_CSS_IMGPLL (7 << 16) -+#define AT91_PMC_MCR_V2_CSS_BAUDPLL (8 << 16) -+#define AT91_PMC_MCR_V2_CSS_AUDIOPLL (9 << 16) -+#define AT91_PMC_MCR_V2_CSS_ETHPLL (10 << 16) -+#define AT91_PMC_MCR_V2_EN (1 << 28) -+ - #define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ - - #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ diff --git a/target/linux/at91/patches-5.10/195-ARM-at91-add-new-SoC-sama7g5.patch b/target/linux/at91/patches-5.10/195-ARM-at91-add-new-SoC-sama7g5.patch deleted file mode 100644 index 1d6b45ac94..0000000000 --- a/target/linux/at91/patches-5.10/195-ARM-at91-add-new-SoC-sama7g5.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 32bac6971d0572f67758f9a8c8af7bf4592f1675 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 9 Apr 2021 14:31:15 +0300 -Subject: [PATCH 195/247] ARM: at91: add new SoC sama7g5 - -Add new SoC from at91 family : sama7g5 - -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: Select PLL, generic clock and UTMI support, add PM configs] -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210409113116.482199-1-eugen.hristev@microchip.com -Link: https://lore.kernel.org/r/20210719080317.1045832-2-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/Kconfig | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm/mach-at91/Kconfig -+++ b/arch/arm/mach-at91/Kconfig -@@ -57,6 +57,16 @@ config SOC_SAMA5D4 - help - Select this if you are using one of Microchip's SAMA5D4 family SoC. - -+config SOC_SAMA7G5 -+ bool "SAMA7G5 family" -+ depends on ARCH_MULTI_V7 -+ select HAVE_AT91_GENERATED_CLK -+ select HAVE_AT91_SAM9X60_PLL -+ select HAVE_AT91_UTMI -+ select SOC_SAMA7 -+ help -+ Select this if you are using one of Microchip's SAMA7G5 family SoC. -+ - config SOC_AT91RM9200 - bool "AT91RM9200" - depends on ARCH_MULTI_V4T -@@ -191,4 +201,12 @@ config SOC_SAMA5 - config ATMEL_PM - bool - -+config SOC_SAMA7 -+ bool -+ select ARM_GIC -+ select ATMEL_PM if PM -+ select ATMEL_SDRAMC -+ select MEMORY -+ select SOC_SAM_V7 -+ select SRAM if PM - endif diff --git a/target/linux/at91/patches-5.10/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch b/target/linux/at91/patches-5.10/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch deleted file mode 100644 index c99a2d5219..0000000000 --- a/target/linux/at91/patches-5.10/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 3de4879bf59b46a966ea226a67df70b88f43a23e Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Fri, 9 Apr 2021 14:31:16 +0300 -Subject: [PATCH 196/247] ARM: at91: debug: add sama7g5 low level debug uart - -Add sama7g5 SoC debug uart on Flexcom3. This is the UART that the -ROM bootloader uses. - -Signed-off-by: Eugen Hristev -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210409113116.482199-2-eugen.hristev@microchip.com -[claudiu.beznea: adapt to v5.10.27] -Signed-off-by: Claudiu Beznea ---- - arch/arm/Kconfig.debug | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm/Kconfig.debug -+++ b/arch/arm/Kconfig.debug -@@ -191,6 +191,14 @@ choice - their output to the USART1 port on SAMV7 based - machines. - -+ config DEBUG_AT91_SAMA7G5_FLEXCOM3 -+ bool "Kernel low-level debugging on SAMA7G5 FLEXCOM3" -+ select DEBUG_AT91_UART -+ depends on SOC_SAMA7G5 -+ help -+ Say Y here if you want kernel low-level debugging support -+ on the FLEXCOM3 port of SAMA7G5. -+ - config DEBUG_BCM2835 - bool "Kernel low-level debugging on BCM2835 PL011 UART" - depends on ARCH_BCM2835 && ARCH_MULTI_V6 -@@ -1731,6 +1739,7 @@ config DEBUG_UART_PHYS - default 0xd4017000 if DEBUG_MMP_UART2 - default 0xd4018000 if DEBUG_MMP_UART3 - default 0xe0000000 if DEBUG_SPEAR13XX -+ default 0xe1824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3 - default 0xe4007000 if DEBUG_HIP04_UART - default 0xe6c40000 if DEBUG_RMOBILE_SCIFA0 - default 0xe6c50000 if DEBUG_RMOBILE_SCIFA1 -@@ -1791,6 +1800,7 @@ config DEBUG_UART_VIRT - default 0xc8912000 if DEBUG_RV1108_UART0 - default 0xe0010fe0 if ARCH_RPC - default 0xf0000be0 if ARCH_EBSA110 -+ default 0xe0824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3 - default 0xf0010000 if DEBUG_ASM9260_UART - default 0xf0100000 if DEBUG_DIGICOLOR_UA0 - default 0xf01fb000 if DEBUG_NOMADIK_UART diff --git a/target/linux/at91/patches-5.10/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch b/target/linux/at91/patches-5.10/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch deleted file mode 100644 index dfd47d55d2..0000000000 --- a/target/linux/at91/patches-5.10/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch +++ /dev/null @@ -1,87 +0,0 @@ -From e41d00bdaa31b36fd314e927104082615aa4643a Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:47 +0300 -Subject: [PATCH 197/247] ARM: at91: pm: move pm_bu to soc_pm data structure - -Move pm_bu to soc_pm data structure. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-2-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 34 +++++++++++++++++++++------------- - 1 file changed, 21 insertions(+), 13 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -27,10 +27,25 @@ - #include "generic.h" - #include "pm.h" - -+/** -+ * struct at91_pm_bu - AT91 power management backup unit data structure -+ * @suspended: true if suspended to backup mode -+ * @reserved: reserved -+ * @canary: canary data for memory checking after exit from backup mode -+ * @resume: resume API -+ */ -+struct at91_pm_bu { -+ int suspended; -+ unsigned long reserved; -+ phys_addr_t canary; -+ phys_addr_t resume; -+}; -+ - struct at91_soc_pm { - int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); - int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); - const struct of_device_id *ws_ids; -+ struct at91_pm_bu *bu; - struct at91_pm_data data; - }; - -@@ -71,13 +86,6 @@ static int at91_pm_valid_state(suspend_s - - static int canary = 0xA5A5A5A5; - --static struct at91_pm_bu { -- int suspended; -- unsigned long reserved; -- phys_addr_t canary; -- phys_addr_t resume; --} *pm_bu; -- - struct wakeup_source_info { - unsigned int pmc_fsmr_bit; - unsigned int shdwc_mr_bit; -@@ -288,7 +296,7 @@ static int at91_suspend_finish(unsigned - static void at91_pm_suspend(suspend_state_t state) - { - if (soc_pm.data.mode == AT91_PM_BACKUP) { -- pm_bu->suspended = 1; -+ soc_pm.bu->suspended = 1; - - cpu_suspend(0, at91_suspend_finish); - -@@ -672,16 +680,16 @@ static int __init at91_pm_backup_init(vo - goto securam_fail; - } - -- pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); -- if (!pm_bu) { -+ soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu)); -+ if (!soc_pm.bu) { - pr_warn("%s: unable to alloc securam!\n", __func__); - ret = -ENOMEM; - goto securam_fail; - } - -- pm_bu->suspended = 0; -- pm_bu->canary = __pa_symbol(&canary); -- pm_bu->resume = __pa_symbol(cpu_resume); -+ soc_pm.bu->suspended = 0; -+ soc_pm.bu->canary = __pa_symbol(&canary); -+ soc_pm.bu->resume = __pa_symbol(cpu_resume); - - return 0; - diff --git a/target/linux/at91/patches-5.10/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch b/target/linux/at91/patches-5.10/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch deleted file mode 100644 index 5b484b7343..0000000000 --- a/target/linux/at91/patches-5.10/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch +++ /dev/null @@ -1,55 +0,0 @@ -From c8f2a8aaae41fa0a40ad88855ae82696098230d7 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:48 +0300 -Subject: [PATCH 198/247] ARM: at91: pm: move the setup of soc_pm.bu->suspended - -Move the setup of soc_pm.bu->suspended in platform_suspend::begin -function so that the PMC code in charge with clocks suspend/resume -to differentiate b/w standard PM mode and backup mode. - -Signed-off-by: Claudiu Beznea -Reviewed-by: Alexandre Belloni -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-3-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 15 ++++++++++++--- - 1 file changed, 12 insertions(+), 3 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -214,6 +214,8 @@ static int at91_sam9x60_config_pmc_ws(vo - */ - static int at91_pm_begin(suspend_state_t state) - { -+ int ret; -+ - switch (state) { - case PM_SUSPEND_MEM: - soc_pm.data.mode = soc_pm.data.suspend_mode; -@@ -227,7 +229,16 @@ static int at91_pm_begin(suspend_state_t - soc_pm.data.mode = -1; - } - -- return at91_pm_config_ws(soc_pm.data.mode, true); -+ ret = at91_pm_config_ws(soc_pm.data.mode, true); -+ if (ret) -+ return ret; -+ -+ if (soc_pm.data.mode == AT91_PM_BACKUP) -+ soc_pm.bu->suspended = 1; -+ else if (soc_pm.bu) -+ soc_pm.bu->suspended = 0; -+ -+ return 0; - } - - /* -@@ -296,8 +307,6 @@ static int at91_suspend_finish(unsigned - static void at91_pm_suspend(suspend_state_t state) - { - if (soc_pm.data.mode == AT91_PM_BACKUP) { -- soc_pm.bu->suspended = 1; -- - cpu_suspend(0, at91_suspend_finish); - - /* The SRAM is lost between suspend cycles */ diff --git a/target/linux/at91/patches-5.10/199-ARM-at91-pm-document-at91_soc_pm-structure.patch b/target/linux/at91/patches-5.10/199-ARM-at91-pm-document-at91_soc_pm-structure.patch deleted file mode 100644 index 965555a11d..0000000000 --- a/target/linux/at91/patches-5.10/199-ARM-at91-pm-document-at91_soc_pm-structure.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 59a4b3b9381b727f416d9cc52e60d0bc7d93ecae Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:49 +0300 -Subject: [PATCH 199/247] ARM: at91: pm: document at91_soc_pm structure - -Document at91_soc_pm structure. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-4-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -41,6 +41,14 @@ struct at91_pm_bu { - phys_addr_t resume; - }; - -+/** -+ * struct at91_soc_pm - AT91 SoC power management data structure -+ * @config_shdwc_ws: wakeup sources configuration function for SHDWC -+ * @config_pmc_ws: wakeup srouces configuration function for PMC -+ * @ws_ids: wakup sources of_device_id array -+ * @data: PM data to be used on last phase of suspend -+ * @bu: backup unit mapped data (for backup mode) -+ */ - struct at91_soc_pm { - int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); - int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); diff --git a/target/linux/at91/patches-5.10/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch b/target/linux/at91/patches-5.10/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch deleted file mode 100644 index f15095aafd..0000000000 --- a/target/linux/at91/patches-5.10/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch +++ /dev/null @@ -1,238 +0,0 @@ -From 0c4cbd38a705bdeab11de4c84ad0ce8c3de8a81d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:50 +0300 -Subject: [PATCH 200/247] ARM: at91: pm: check for different controllers in - at91_pm_modes_init() - -at91_pm_modes_init() checks for proper nodes in device tree and maps -them accordingly. Up to SAMA7G5 all AT91 SoCs had the same mapping -b/w power saving modes and different controllers needed in the -final/first steps of suspend/resume. SAMA7G5 is not aligned with the -old SoCs thus the code is adapted for this. This patch prepares -the field for next commits. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-5-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 143 +++++++++++++++++++++++++--------------- - 1 file changed, 91 insertions(+), 52 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -57,6 +57,18 @@ struct at91_soc_pm { - struct at91_pm_data data; - }; - -+/** -+ * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes -+ * @AT91_PM_IOMAP_SHDWC: SHDWC controller -+ * @AT91_PM_IOMAP_SFRBU: SFRBU controller -+ */ -+enum at91_pm_iomaps { -+ AT91_PM_IOMAP_SHDWC, -+ AT91_PM_IOMAP_SFRBU, -+}; -+ -+#define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name) -+ - static struct at91_soc_pm soc_pm = { - .data = { - .standby_mode = AT91_PM_STANDBY, -@@ -671,24 +683,15 @@ static int __init at91_pm_backup_init(vo - if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) - return 0; - -- np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); -- if (!np) { -- pr_warn("%s: failed to find sfrbu!\n", __func__); -- return ret; -- } -- -- soc_pm.data.sfrbu = of_iomap(np, 0); -- of_node_put(np); -- - np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); - if (!np) -- goto securam_fail_no_ref_dev; -+ return ret; - - pdev = of_find_device_by_node(np); - of_node_put(np); - if (!pdev) { - pr_warn("%s: failed to find securam device!\n", __func__); -- goto securam_fail_no_ref_dev; -+ return ret; - } - - sram_pool = gen_pool_get(&pdev->dev, NULL); -@@ -712,64 +715,92 @@ static int __init at91_pm_backup_init(vo - - securam_fail: - put_device(&pdev->dev); --securam_fail_no_ref_dev: -- iounmap(soc_pm.data.sfrbu); -- soc_pm.data.sfrbu = NULL; - return ret; - } - --static void __init at91_pm_use_default_mode(int pm_mode) --{ -- if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP) -- return; -- -- if (soc_pm.data.standby_mode == pm_mode) -- soc_pm.data.standby_mode = AT91_PM_ULP0; -- if (soc_pm.data.suspend_mode == pm_mode) -- soc_pm.data.suspend_mode = AT91_PM_ULP0; --} -- - static const struct of_device_id atmel_shdwc_ids[] = { - { .compatible = "atmel,sama5d2-shdwc" }, - { .compatible = "microchip,sam9x60-shdwc" }, - { /* sentinel. */ } - }; - --static void __init at91_pm_modes_init(void) -+static void __init at91_pm_modes_init(const u32 *maps, int len) - { - struct device_node *np; -- int ret; -+ int ret, mode; - -- if (!at91_is_pm_mode_active(AT91_PM_BACKUP) && -- !at91_is_pm_mode_active(AT91_PM_ULP1)) -- return; -+ ret = at91_pm_backup_init(); -+ if (ret) { -+ if (soc_pm.data.standby_mode == AT91_PM_BACKUP) -+ soc_pm.data.standby_mode = AT91_PM_ULP0; -+ if (soc_pm.data.suspend_mode == AT91_PM_BACKUP) -+ soc_pm.data.suspend_mode = AT91_PM_ULP0; -+ } -+ -+ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || -+ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) { -+ np = of_find_matching_node(NULL, atmel_shdwc_ids); -+ if (!np) { -+ pr_warn("%s: failed to find shdwc!\n", __func__); -+ -+ /* Use ULP0 if it doesn't needs SHDWC.*/ -+ if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC))) -+ mode = AT91_PM_ULP0; -+ else -+ mode = AT91_PM_STANDBY; -+ -+ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC)) -+ soc_pm.data.standby_mode = mode; -+ if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) -+ soc_pm.data.suspend_mode = mode; -+ } else { -+ soc_pm.data.shdwc = of_iomap(np, 0); -+ of_node_put(np); -+ } -+ } - -- np = of_find_matching_node(NULL, atmel_shdwc_ids); -- if (!np) { -- pr_warn("%s: failed to find shdwc!\n", __func__); -- goto ulp1_default; -+ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || -+ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) { -+ np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu"); -+ if (!np) { -+ pr_warn("%s: failed to find sfrbu!\n", __func__); -+ -+ /* -+ * Use ULP0 if it doesn't need SHDWC or if SHDWC -+ * was already located. -+ */ -+ if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) || -+ soc_pm.data.shdwc) -+ mode = AT91_PM_ULP0; -+ else -+ mode = AT91_PM_STANDBY; -+ -+ if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU)) -+ soc_pm.data.standby_mode = mode; -+ if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) -+ soc_pm.data.suspend_mode = mode; -+ } else { -+ soc_pm.data.sfrbu = of_iomap(np, 0); -+ of_node_put(np); -+ } - } - -- soc_pm.data.shdwc = of_iomap(np, 0); -- of_node_put(np); -+ /* Unmap all unnecessary. */ -+ if (soc_pm.data.shdwc && -+ !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) || -+ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) { -+ iounmap(soc_pm.data.shdwc); -+ soc_pm.data.shdwc = NULL; -+ } - -- ret = at91_pm_backup_init(); -- if (ret) { -- if (!at91_is_pm_mode_active(AT91_PM_ULP1)) -- goto unmap; -- else -- goto backup_default; -+ if (soc_pm.data.sfrbu && -+ !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) || -+ maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) { -+ iounmap(soc_pm.data.sfrbu); -+ soc_pm.data.sfrbu = NULL; - } - - return; -- --unmap: -- iounmap(soc_pm.data.shdwc); -- soc_pm.data.shdwc = NULL; --ulp1_default: -- at91_pm_use_default_mode(AT91_PM_ULP1); --backup_default: -- at91_pm_use_default_mode(AT91_PM_BACKUP); - } - - struct pmc_info { -@@ -936,13 +967,16 @@ void __init sam9x60_pm_init(void) - static const int modes[] __initconst = { - AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, - }; -+ static const int iomaps[] __initconst = { -+ [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), -+ }; - int ret; - - if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) - return; - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); -- at91_pm_modes_init(); -+ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); - ret = at91_dt_ramc(); - if (ret) - return; -@@ -999,13 +1033,18 @@ void __init sama5d2_pm_init(void) - AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, - AT91_PM_BACKUP, - }; -+ static const u32 iomaps[] __initconst = { -+ [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC), -+ [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) | -+ AT91_PM_IOMAP(SFRBU), -+ }; - int ret; - - if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) - return; - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); -- at91_pm_modes_init(); -+ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); - ret = at91_dt_ramc(); - if (ret) - return; diff --git a/target/linux/at91/patches-5.10/201-ARM-at91-pm-do-not-initialize-pdev.patch b/target/linux/at91/patches-5.10/201-ARM-at91-pm-do-not-initialize-pdev.patch deleted file mode 100644 index 413a95a968..0000000000 --- a/target/linux/at91/patches-5.10/201-ARM-at91-pm-do-not-initialize-pdev.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 31e25503bbad1fffd29fd074a46bd4858b65304f Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:51 +0300 -Subject: [PATCH 201/247] ARM: at91: pm: do not initialize pdev - -There is no need to initialize pdev. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-6-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -674,7 +674,7 @@ static int __init at91_pm_backup_init(vo - { - struct gen_pool *sram_pool; - struct device_node *np; -- struct platform_device *pdev = NULL; -+ struct platform_device *pdev; - int ret = -ENODEV; - - if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) diff --git a/target/linux/at91/patches-5.10/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch b/target/linux/at91/patches-5.10/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch deleted file mode 100644 index a313ab029a..0000000000 --- a/target/linux/at91/patches-5.10/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 8a7a4cf3860910e460e2c3ca467b1dabf7ce9827 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:52 +0300 -Subject: [PATCH 202/247] ARM: at91: pm: use r7 instead of tmp1 - -Use r7 instead of tmp1 in macros. This prepares the filed for -next commits. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-7-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 18 ++++++++++++------ - 1 file changed, 12 insertions(+), 6 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -31,30 +31,36 @@ tmp3 .req r6 - - /* - * Wait until master oscillator has stabilized. -+ * -+ * Side effects: overwrites r7 - */ - .macro wait_moscrdy --1: ldr tmp1, [pmc, #AT91_PMC_SR] -- tst tmp1, #AT91_PMC_MOSCS -+1: ldr r7, [pmc, #AT91_PMC_SR] -+ tst r7, #AT91_PMC_MOSCS - beq 1b - .endm - - /* - * Wait for main oscillator selection is done -+ * -+ * Side effects: overwrites r7 - */ - .macro wait_moscsels --1: ldr tmp1, [pmc, #AT91_PMC_SR] -- tst tmp1, #AT91_PMC_MOSCSELS -+1: ldr r7, [pmc, #AT91_PMC_SR] -+ tst r7, #AT91_PMC_MOSCSELS - beq 1b - .endm - - /* - * Put the processor to enter the idle state -+ * -+ * Side effects: overwrites r7 - */ - .macro at91_cpu_idle - - #if defined(CONFIG_CPU_V7) -- mov tmp1, #AT91_PMC_PCK -- str tmp1, [pmc, #AT91_PMC_SCDR] -+ mov r7, #AT91_PMC_PCK -+ str r7, [pmc, #AT91_PMC_SCDR] - - dsb - diff --git a/target/linux/at91/patches-5.10/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch b/target/linux/at91/patches-5.10/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch deleted file mode 100644 index a2edec371d..0000000000 --- a/target/linux/at91/patches-5.10/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch +++ /dev/null @@ -1,467 +0,0 @@ -From 892f6d2fb9c42d4ac451236639599f533c37b507 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:53 +0300 -Subject: [PATCH 203/247] ARM: at91: pm: avoid push and pop on stack while - memory is in self-refersh - -For the previous AT91 RAM controller and self-refresh procedure this -had no side effects. However, for SAMA7G5 the self-refresh procedure -doesn't allow this anymore as the RAM controller ports are closed -before switching it to self-refresh. This commits prepares the code -for the following ones adding self-refresh and PM support for SAMA7G5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-8-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 397 +++++++++++++++++--------------- - 1 file changed, 205 insertions(+), 192 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -75,98 +75,147 @@ tmp3 .req r6 - - .arm - --/* -- * void at91_suspend_sram_fn(struct at91_pm_data*) -- * @input param: -- * @r0: base address of struct at91_pm_data -+/** -+ * Enable self-refresh -+ * -+ * register usage: -+ * @r1: memory type -+ * @r2: base address of the sram controller -+ * @r3: temporary - */ --/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ -- .align 3 --ENTRY(at91_pm_suspend_in_sram) -- /* Save registers on stack */ -- stmfd sp!, {r4 - r12, lr} -+.macro at91_sramc_self_refresh_ena -+ ldr r1, .memtype -+ ldr r2, .sramc_base - -- /* Drain write buffer */ -- mov tmp1, #0 -- mcr p15, 0, tmp1, c7, c10, 4 -+ cmp r1, #AT91_MEMCTRL_MC -+ bne sr_ena_ddrc_sf - -- ldr tmp1, [r0, #PM_DATA_PMC] -- str tmp1, .pmc_base -- ldr tmp1, [r0, #PM_DATA_RAMC0] -- str tmp1, .sramc_base -- ldr tmp1, [r0, #PM_DATA_RAMC1] -- str tmp1, .sramc1_base -- ldr tmp1, [r0, #PM_DATA_MEMCTRL] -- str tmp1, .memtype -- ldr tmp1, [r0, #PM_DATA_MODE] -- str tmp1, .pm_mode -- ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] -- str tmp1, .mckr_offset -- ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -- str tmp1, .pmc_version -- /* Both ldrne below are here to preload their address in the TLB */ -- ldr tmp1, [r0, #PM_DATA_SHDWC] -- str tmp1, .shdwc -- cmp tmp1, #0 -- ldrne tmp2, [tmp1, #0] -- ldr tmp1, [r0, #PM_DATA_SFRBU] -- str tmp1, .sfrbu -- cmp tmp1, #0 -- ldrne tmp2, [tmp1, #0x10] -+ /* Active SDRAM self-refresh mode */ -+ mov r3, #1 -+ str r3, [r2, #AT91_MC_SDRAMC_SRR] -+ b sr_ena_exit - -- /* Active the self-refresh mode */ -- mov r0, #SRAMC_SELF_FRESH_ACTIVE -- bl at91_sramc_self_refresh -+sr_ena_ddrc_sf: -+ cmp r1, #AT91_MEMCTRL_DDRSDR -+ bne sr_ena_sdramc_sf - -- ldr r0, .pm_mode -- cmp r0, #AT91_PM_STANDBY -- beq standby -- cmp r0, #AT91_PM_BACKUP -- beq backup_mode -+ /* -+ * DDR Memory controller -+ */ - -- bl at91_ulp_mode -- b exit_suspend -+ /* LPDDR1 --> force DDR2 mode during self-refresh */ -+ ldr r3, [r2, #AT91_DDRSDRC_MDR] -+ str r3, .saved_sam9_mdr -+ bic r3, r3, #~AT91_DDRSDRC_MD -+ cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR -+ ldreq r3, [r2, #AT91_DDRSDRC_MDR] -+ biceq r3, r3, #AT91_DDRSDRC_MD -+ orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 -+ streq r3, [r2, #AT91_DDRSDRC_MDR] - --standby: -- /* Wait for interrupt */ -- ldr pmc, .pmc_base -- at91_cpu_idle -- b exit_suspend -+ /* Active DDRC self-refresh mode */ -+ ldr r3, [r2, #AT91_DDRSDRC_LPR] -+ str r3, .saved_sam9_lpr -+ bic r3, r3, #AT91_DDRSDRC_LPCB -+ orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH -+ str r3, [r2, #AT91_DDRSDRC_LPR] - --backup_mode: -- bl at91_backup_mode -- b exit_suspend -+ /* If using the 2nd ddr controller */ -+ ldr r2, .sramc1_base -+ cmp r2, #0 -+ beq sr_ena_no_2nd_ddrc - --exit_suspend: -- /* Exit the self-refresh mode */ -- mov r0, #SRAMC_SELF_FRESH_EXIT -- bl at91_sramc_self_refresh -+ ldr r3, [r2, #AT91_DDRSDRC_MDR] -+ str r3, .saved_sam9_mdr1 -+ bic r3, r3, #~AT91_DDRSDRC_MD -+ cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR -+ ldreq r3, [r2, #AT91_DDRSDRC_MDR] -+ biceq r3, r3, #AT91_DDRSDRC_MD -+ orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 -+ streq r3, [r2, #AT91_DDRSDRC_MDR] - -- /* Restore registers, and return */ -- ldmfd sp!, {r4 - r12, pc} --ENDPROC(at91_pm_suspend_in_sram) -+ /* Active DDRC self-refresh mode */ -+ ldr r3, [r2, #AT91_DDRSDRC_LPR] -+ str r3, .saved_sam9_lpr1 -+ bic r3, r3, #AT91_DDRSDRC_LPCB -+ orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH -+ str r3, [r2, #AT91_DDRSDRC_LPR] - --ENTRY(at91_backup_mode) -- /* Switch the master clock source to slow clock. */ -- ldr pmc, .pmc_base -- ldr tmp2, .mckr_offset -- ldr tmp1, [pmc, tmp2] -- bic tmp1, tmp1, #AT91_PMC_CSS -- str tmp1, [pmc, tmp2] -+sr_ena_no_2nd_ddrc: -+ b sr_ena_exit - -- wait_mckrdy -+ /* -+ * SDRAMC Memory controller -+ */ -+sr_ena_sdramc_sf: -+ /* Active SDRAMC self-refresh mode */ -+ ldr r3, [r2, #AT91_SDRAMC_LPR] -+ str r3, .saved_sam9_lpr -+ bic r3, r3, #AT91_SDRAMC_LPCB -+ orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH -+ str r3, [r2, #AT91_SDRAMC_LPR] - -- /*BUMEN*/ -- ldr r0, .sfrbu -- mov tmp1, #0x1 -- str tmp1, [r0, #0x10] -+ ldr r3, .saved_sam9_lpr -+ str r3, [r2, #AT91_SDRAMC_LPR] - -- /* Shutdown */ -- ldr r0, .shdwc -- mov tmp1, #0xA5000000 -- add tmp1, tmp1, #0x1 -- str tmp1, [r0, #0] --ENDPROC(at91_backup_mode) -+sr_ena_exit: -+.endm -+ -+/** -+ * Disable self-refresh -+ * -+ * register usage: -+ * @r1: memory type -+ * @r2: base address of the sram controller -+ * @r3: temporary -+ */ -+.macro at91_sramc_self_refresh_dis -+ ldr r1, .memtype -+ ldr r2, .sramc_base -+ -+ cmp r1, #AT91_MEMCTRL_MC -+ bne sr_dis_ddrc_exit_sf -+ -+ /* -+ * at91rm9200 Memory controller -+ */ -+ -+ /* -+ * For exiting the self-refresh mode, do nothing, -+ * automatically exit the self-refresh mode. -+ */ -+ b sr_dis_exit -+ -+sr_dis_ddrc_exit_sf: -+ cmp r1, #AT91_MEMCTRL_DDRSDR -+ bne sdramc_exit_sf -+ -+ /* DDR Memory controller */ -+ -+ /* Restore MDR in case of LPDDR1 */ -+ ldr r3, .saved_sam9_mdr -+ str r3, [r2, #AT91_DDRSDRC_MDR] -+ /* Restore LPR on AT91 with DDRAM */ -+ ldr r3, .saved_sam9_lpr -+ str r3, [r2, #AT91_DDRSDRC_LPR] -+ -+ /* If using the 2nd ddr controller */ -+ ldr r2, .sramc1_base -+ cmp r2, #0 -+ ldrne r3, .saved_sam9_mdr1 -+ strne r3, [r2, #AT91_DDRSDRC_MDR] -+ ldrne r3, .saved_sam9_lpr1 -+ strne r3, [r2, #AT91_DDRSDRC_LPR] -+ -+ b sr_dis_exit -+ -+sdramc_exit_sf: -+ /* SDRAMC Memory controller */ -+ ldr r3, .saved_sam9_lpr -+ str r3, [r2, #AT91_SDRAMC_LPR] -+ -+sr_dis_exit: -+.endm - - .macro at91_pm_ulp0_mode - ldr pmc, .pmc_base -@@ -503,7 +552,7 @@ ENDPROC(at91_backup_mode) - 2: - .endm - --ENTRY(at91_ulp_mode) -+.macro at91_ulp_mode - ldr pmc, .pmc_base - ldr tmp2, .mckr_offset - ldr tmp3, .pm_mode -@@ -552,133 +601,97 @@ ulp_exit: - - wait_mckrdy - -- mov pc, lr --ENDPROC(at91_ulp_mode) -- --/* -- * void at91_sramc_self_refresh(unsigned int is_active) -- * -- * @input param: -- * @r0: 1 - active self-refresh mode -- * 0 - exit self-refresh mode -- * register usage: -- * @r1: memory type -- * @r2: base address of the sram controller -- */ -- --ENTRY(at91_sramc_self_refresh) -- ldr r1, .memtype -- ldr r2, .sramc_base -- -- cmp r1, #AT91_MEMCTRL_MC -- bne ddrc_sf -- -- /* -- * at91rm9200 Memory controller -- */ -- -- /* -- * For exiting the self-refresh mode, do nothing, -- * automatically exit the self-refresh mode. -- */ -- tst r0, #SRAMC_SELF_FRESH_ACTIVE -- beq exit_sramc_sf -- -- /* Active SDRAM self-refresh mode */ -- mov r3, #1 -- str r3, [r2, #AT91_MC_SDRAMC_SRR] -- b exit_sramc_sf -- --ddrc_sf: -- cmp r1, #AT91_MEMCTRL_DDRSDR -- bne sdramc_sf -+.endm - -- /* -- * DDR Memory controller -- */ -- tst r0, #SRAMC_SELF_FRESH_ACTIVE -- beq ddrc_exit_sf -+.macro at91_backup_mode -+ /* Switch the master clock source to slow clock. */ -+ ldr pmc, .pmc_base -+ ldr tmp2, .mckr_offset -+ ldr tmp1, [pmc, tmp2] -+ bic tmp1, tmp1, #AT91_PMC_CSS -+ str tmp1, [pmc, tmp2] - -- /* LPDDR1 --> force DDR2 mode during self-refresh */ -- ldr r3, [r2, #AT91_DDRSDRC_MDR] -- str r3, .saved_sam9_mdr -- bic r3, r3, #~AT91_DDRSDRC_MD -- cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR -- ldreq r3, [r2, #AT91_DDRSDRC_MDR] -- biceq r3, r3, #AT91_DDRSDRC_MD -- orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 -- streq r3, [r2, #AT91_DDRSDRC_MDR] -+ wait_mckrdy - -- /* Active DDRC self-refresh mode */ -- ldr r3, [r2, #AT91_DDRSDRC_LPR] -- str r3, .saved_sam9_lpr -- bic r3, r3, #AT91_DDRSDRC_LPCB -- orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH -- str r3, [r2, #AT91_DDRSDRC_LPR] -+ /*BUMEN*/ -+ ldr r0, .sfrbu -+ mov tmp1, #0x1 -+ str tmp1, [r0, #0x10] - -- /* If using the 2nd ddr controller */ -- ldr r2, .sramc1_base -- cmp r2, #0 -- beq no_2nd_ddrc -+ /* Shutdown */ -+ ldr r0, .shdwc -+ mov tmp1, #0xA5000000 -+ add tmp1, tmp1, #0x1 -+ str tmp1, [r0, #0] -+.endm - -- ldr r3, [r2, #AT91_DDRSDRC_MDR] -- str r3, .saved_sam9_mdr1 -- bic r3, r3, #~AT91_DDRSDRC_MD -- cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR -- ldreq r3, [r2, #AT91_DDRSDRC_MDR] -- biceq r3, r3, #AT91_DDRSDRC_MD -- orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 -- streq r3, [r2, #AT91_DDRSDRC_MDR] -+/* -+ * void at91_suspend_sram_fn(struct at91_pm_data*) -+ * @input param: -+ * @r0: base address of struct at91_pm_data -+ */ -+/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ -+ .align 3 -+ENTRY(at91_pm_suspend_in_sram) -+ /* Save registers on stack */ -+ stmfd sp!, {r4 - r12, lr} - -- /* Active DDRC self-refresh mode */ -- ldr r3, [r2, #AT91_DDRSDRC_LPR] -- str r3, .saved_sam9_lpr1 -- bic r3, r3, #AT91_DDRSDRC_LPCB -- orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH -- str r3, [r2, #AT91_DDRSDRC_LPR] -+ /* Drain write buffer */ -+ mov tmp1, #0 -+ mcr p15, 0, tmp1, c7, c10, 4 - --no_2nd_ddrc: -- b exit_sramc_sf -+ ldr tmp1, [r0, #PM_DATA_PMC] -+ str tmp1, .pmc_base -+ ldr tmp1, [r0, #PM_DATA_RAMC0] -+ str tmp1, .sramc_base -+ ldr tmp1, [r0, #PM_DATA_RAMC1] -+ str tmp1, .sramc1_base -+ ldr tmp1, [r0, #PM_DATA_MEMCTRL] -+ str tmp1, .memtype -+ ldr tmp1, [r0, #PM_DATA_MODE] -+ str tmp1, .pm_mode -+ ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] -+ str tmp1, .mckr_offset -+ ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -+ str tmp1, .pmc_version -+ /* Both ldrne below are here to preload their address in the TLB */ -+ ldr tmp1, [r0, #PM_DATA_SHDWC] -+ str tmp1, .shdwc -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ ldr tmp1, [r0, #PM_DATA_SFRBU] -+ str tmp1, .sfrbu -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0x10] - --ddrc_exit_sf: -- /* Restore MDR in case of LPDDR1 */ -- ldr r3, .saved_sam9_mdr -- str r3, [r2, #AT91_DDRSDRC_MDR] -- /* Restore LPR on AT91 with DDRAM */ -- ldr r3, .saved_sam9_lpr -- str r3, [r2, #AT91_DDRSDRC_LPR] -+ /* Active the self-refresh mode */ -+ at91_sramc_self_refresh_ena - -- /* If using the 2nd ddr controller */ -- ldr r2, .sramc1_base -- cmp r2, #0 -- ldrne r3, .saved_sam9_mdr1 -- strne r3, [r2, #AT91_DDRSDRC_MDR] -- ldrne r3, .saved_sam9_lpr1 -- strne r3, [r2, #AT91_DDRSDRC_LPR] -+ ldr r0, .pm_mode -+ cmp r0, #AT91_PM_STANDBY -+ beq standby -+ cmp r0, #AT91_PM_BACKUP -+ beq backup_mode - -- b exit_sramc_sf -+ at91_ulp_mode -+ b exit_suspend - -- /* -- * SDRAMC Memory controller -- */ --sdramc_sf: -- tst r0, #SRAMC_SELF_FRESH_ACTIVE -- beq sdramc_exit_sf -+standby: -+ /* Wait for interrupt */ -+ ldr pmc, .pmc_base -+ at91_cpu_idle -+ b exit_suspend - -- /* Active SDRAMC self-refresh mode */ -- ldr r3, [r2, #AT91_SDRAMC_LPR] -- str r3, .saved_sam9_lpr -- bic r3, r3, #AT91_SDRAMC_LPCB -- orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH -- str r3, [r2, #AT91_SDRAMC_LPR] -+backup_mode: -+ at91_backup_mode - --sdramc_exit_sf: -- ldr r3, .saved_sam9_lpr -- str r3, [r2, #AT91_SDRAMC_LPR] -+exit_suspend: -+ /* Exit the self-refresh mode */ -+ at91_sramc_self_refresh_dis - --exit_sramc_sf: -- mov pc, lr --ENDPROC(at91_sramc_self_refresh) -+ /* Restore registers, and return */ -+ ldmfd sp!, {r4 - r12, pc} -+ENDPROC(at91_pm_suspend_in_sram) - - .pmc_base: - .word 0 diff --git a/target/linux/at91/patches-5.10/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch b/target/linux/at91/patches-5.10/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch deleted file mode 100644 index 4601d922d6..0000000000 --- a/target/linux/at91/patches-5.10/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 673d2519e9028dafb678fac29a990740958bed3c Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:54 +0300 -Subject: [PATCH 204/247] ARM: at91: pm: - s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/g - -Replace CONFIG_SOC_SAM9X60 with CONFIG_HAVE_AT91_SAM9X60_PLL as the -SAM9X60's PLL is also present on SAMA7G5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-9-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -422,7 +422,7 @@ sr_dis_exit: - cmp tmp1, #AT91_PMC_V1 - beq 1f - --#ifdef CONFIG_SOC_SAM9X60 -+#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL - /* Save PLLA settings. */ - ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT] - bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID -@@ -489,7 +489,7 @@ sr_dis_exit: - cmp tmp3, #AT91_PMC_V1 - beq 4f - --#ifdef CONFIG_SOC_SAM9X60 -+#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL - /* step 1. */ - ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] - bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID diff --git a/target/linux/at91/patches-5.10/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch b/target/linux/at91/patches-5.10/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch deleted file mode 100644 index 16e733727f..0000000000 --- a/target/linux/at91/patches-5.10/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch +++ /dev/null @@ -1,150 +0,0 @@ -From 67face049c62cb37cf93da26b7fea037228d1d3d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:55 +0300 -Subject: [PATCH 205/247] ARM: at91: pm: add support for waiting MCK1..4 - -SAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than -MCK 1..4. MCK 1..4 should also be saved/restored in the last phase of -suspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 48 ++++++++++++++++++++++++--------- - 1 file changed, 35 insertions(+), 13 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -22,11 +22,23 @@ tmp3 .req r6 - - /* - * Wait until master clock is ready (after switching master clock source) -+ * -+ * @r_mckid: register holding master clock identifier -+ * -+ * Side effects: overwrites r7, r8 - */ -- .macro wait_mckrdy --1: ldr tmp1, [pmc, #AT91_PMC_SR] -- tst tmp1, #AT91_PMC_MCKRDY -- beq 1b -+ .macro wait_mckrdy r_mckid -+#ifdef CONFIG_SOC_SAMA7 -+ cmp \r_mckid, #0 -+ beq 1f -+ mov r7, #AT91_PMC_MCKXRDY -+ b 2f -+#endif -+1: mov r7, #AT91_PMC_MCKRDY -+2: ldr r8, [pmc, #AT91_PMC_SR] -+ and r8, r7 -+ cmp r8, r7 -+ bne 2b - .endm - - /* -@@ -231,7 +243,9 @@ sr_dis_exit: - bic tmp1, tmp1, #AT91_PMC_PRES - orr tmp1, tmp1, #AT91_PMC_PRES_64 - str tmp1, [pmc, tmp3] -- wait_mckrdy -+ -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - b 1f - - 0: -@@ -267,10 +281,13 @@ sr_dis_exit: - bne 5f - - /* Set lowest prescaler for fast resume. */ -+ ldr tmp3, .mckr_offset - ldr tmp1, [pmc, tmp3] - bic tmp1, tmp1, #AT91_PMC_PRES - str tmp1, [pmc, tmp3] -- wait_mckrdy -+ -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - b 6f - - 5: /* Restore RC oscillator state */ -@@ -307,6 +324,7 @@ sr_dis_exit: - .macro at91_pm_ulp1_mode - ldr pmc, .pmc_base - ldr tmp2, .mckr_offset -+ mov tmp3, #0 - - /* Save RC oscillator state and check if it is enabled. */ - ldr tmp1, [pmc, #AT91_PMC_SR] -@@ -348,7 +366,7 @@ sr_dis_exit: - orr tmp1, tmp1, #AT91_PMC_CSS_MAIN - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ wait_mckrdy tmp3 - - /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] -@@ -361,7 +379,7 @@ sr_dis_exit: - nop - nop - -- wait_mckrdy -+ wait_mckrdy tmp3 - - /* Enable the crystal oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] -@@ -377,7 +395,7 @@ sr_dis_exit: - bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ wait_mckrdy tmp3 - - /* Switch main clock source to crystal oscillator */ - ldr tmp1, [pmc, #AT91_CKGR_MOR] -@@ -394,7 +412,7 @@ sr_dis_exit: - orr tmp1, tmp1, #AT91_PMC_CSS_MAIN - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ wait_mckrdy tmp3 - - /* Restore RC oscillator state */ - ldr tmp1, .saved_osc_status -@@ -573,10 +591,12 @@ sr_dis_exit: - save_mck: - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - - at91_plla_disable - -+ ldr tmp3, .pm_mode - cmp tmp3, #AT91_PM_ULP1 - beq ulp1_mode - -@@ -599,7 +619,8 @@ ulp_exit: - ldr tmp2, .saved_mckr - str tmp2, [pmc, tmp1] - -- wait_mckrdy -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - - .endm - -@@ -611,7 +632,8 @@ ulp_exit: - bic tmp1, tmp1, #AT91_PMC_CSS - str tmp1, [pmc, tmp2] - -- wait_mckrdy -+ mov tmp3, #0 -+ wait_mckrdy tmp3 - - /*BUMEN*/ - ldr r0, .sfrbu diff --git a/target/linux/at91/patches-5.10/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch b/target/linux/at91/patches-5.10/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch deleted file mode 100644 index 37a22885d7..0000000000 --- a/target/linux/at91/patches-5.10/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch +++ /dev/null @@ -1,53 +0,0 @@ -From c6b435625975d9a6daeffd81509a9877ddfb93b5 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:56 +0300 -Subject: [PATCH 206/247] ARM: at91: sfrbu: add sfrbu registers definitions for - sama7g5 - -Add SFRBU registers definitions for SAMA7G5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-11-claudiu.beznea@microchip.com ---- - include/soc/at91/sama7-sfrbu.h | 34 ++++++++++++++++++++++++++++++++++ - 1 file changed, 34 insertions(+) - create mode 100644 include/soc/at91/sama7-sfrbu.h - ---- /dev/null -+++ b/include/soc/at91/sama7-sfrbu.h -@@ -0,0 +1,34 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Microchip SAMA7 SFRBU registers offsets and bit definitions. -+ * -+ * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries -+ * -+ * Author: Claudu Beznea -+ */ -+ -+#ifndef __SAMA7_SFRBU_H__ -+#define __SAMA7_SFRBU_H__ -+ -+#ifdef CONFIG_SOC_SAMA7 -+ -+#define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */ -+#define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */ -+#define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */ -+#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ -+#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ -+ -+#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ -+#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ -+#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ -+#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ -+#define AT91_SFRBU_PD_VALUE_MSK (0x3) -+#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ -+ -+#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ -+#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ -+ -+#endif /* CONFIG_SOC_SAMA7 */ -+ -+#endif /* __SAMA7_SFRBU_H__ */ -+ diff --git a/target/linux/at91/patches-5.10/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch b/target/linux/at91/patches-5.10/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch deleted file mode 100644 index 1df310f216..0000000000 --- a/target/linux/at91/patches-5.10/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 0005be9abfcddf9a29c6d07afe06caa41560d424 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:57 +0300 -Subject: [PATCH 207/247] ARM: at91: ddr: add registers definitions for - sama7g5's ddr - -Add registers and bits definitions for SAMA7G5's UDDRC and DDR3PHY. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-12-claudiu.beznea@microchip.com ---- - include/soc/at91/sama7-ddr.h | 80 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 80 insertions(+) - create mode 100644 include/soc/at91/sama7-ddr.h - ---- /dev/null -+++ b/include/soc/at91/sama7-ddr.h -@@ -0,0 +1,80 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets -+ * and bit definitions. -+ * -+ * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries -+ * -+ * Author: Claudu Beznea -+ */ -+ -+#ifndef __SAMA7_DDR_H__ -+#define __SAMA7_DDR_H__ -+ -+#ifdef CONFIG_SOC_SAMA7 -+ -+/* DDR3PHY */ -+#define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */ -+#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ -+#define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */ -+#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ -+#define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */ -+#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ -+ -+#define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */ -+#define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */ -+#define DDR3PHY_PGCR_CKDV0 (1 << 12) /* CK Disable Value */ -+ -+#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */ -+#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */ -+ -+#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */ -+#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */ -+#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */ -+#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */ -+ -+#define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */ -+#define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */ -+ -+#define DDR3PHY_DSGCR (0x2C) /* DDR3PHY DDR System General Configuration Register */ -+#define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */ -+ -+#define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */ -+ -+/* UDDRC */ -+#define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */ -+#define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */ -+#define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PHY Master Request */ -+#define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control */ -+#define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */ -+#define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */ -+#define UDDRC_STAT_OPMODE_INIT (0x0 << 0) /* Init */ -+#define UDDRC_STAT_OPMODE_NORMAL (0x1 << 0) /* Normal */ -+#define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */ -+#define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */ -+#define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ -+ -+#define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ -+#define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */ -+ -+#define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ -+#define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */ -+ -+#define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */ -+#define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset */ -+ -+#define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */ -+#define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */ -+ -+#define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */ -+#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ -+ -+#define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */ -+#define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */ -+#define UDDRC_PCTRL_2 (0x5F0) /* UDDRC Port 2 Control Register */ -+#define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */ -+#define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */ -+ -+#endif /* CONFIG_SOC_SAMA7 */ -+ -+#endif /* __SAMA7_DDR_H__ */ diff --git a/target/linux/at91/patches-5.10/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch b/target/linux/at91/patches-5.10/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch deleted file mode 100644 index f8321e5042..0000000000 --- a/target/linux/at91/patches-5.10/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch +++ /dev/null @@ -1,274 +0,0 @@ -From 1bfd85d71703f80392a71043caf74f159bec97b8 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:58 +0300 -Subject: [PATCH 208/247] ARM: at91: pm: add self-refresh support for sama7g5 - -Add self-refresh support for SAMA7G5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.h | 2 + - arch/arm/mach-at91/pm_data-offsets.c | 2 + - arch/arm/mach-at91/pm_suspend.S | 199 +++++++++++++++++++++++++++ - 3 files changed, 203 insertions(+) - ---- a/arch/arm/mach-at91/pm.h -+++ b/arch/arm/mach-at91/pm.h -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - #define AT91_MEMCTRL_MC 0 - #define AT91_MEMCTRL_SDRAMC 1 -@@ -27,6 +28,7 @@ - struct at91_pm_data { - void __iomem *pmc; - void __iomem *ramc[2]; -+ void __iomem *ramc_phy; - unsigned long uhp_udp_mask; - unsigned int memctrl; - unsigned int mode; ---- a/arch/arm/mach-at91/pm_data-offsets.c -+++ b/arch/arm/mach-at91/pm_data-offsets.c -@@ -8,6 +8,8 @@ int main(void) - DEFINE(PM_DATA_PMC, offsetof(struct at91_pm_data, pmc)); - DEFINE(PM_DATA_RAMC0, offsetof(struct at91_pm_data, ramc[0])); - DEFINE(PM_DATA_RAMC1, offsetof(struct at91_pm_data, ramc[1])); -+ DEFINE(PM_DATA_RAMC_PHY, offsetof(struct at91_pm_data, -+ ramc_phy)); - DEFINE(PM_DATA_MEMCTRL, offsetof(struct at91_pm_data, memctrl)); - DEFINE(PM_DATA_MODE, offsetof(struct at91_pm_data, mode)); - DEFINE(PM_DATA_SHDWC, offsetof(struct at91_pm_data, shdwc)); ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -87,6 +87,200 @@ tmp3 .req r6 - - .arm - -+#ifdef CONFIG_SOC_SAMA7 -+/** -+ * Enable self-refresh -+ * -+ * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7 -+ */ -+.macro at91_sramc_self_refresh_ena -+ ldr r2, .sramc_base -+ ldr r3, .sramc_phy_base -+ ldr r7, .pm_mode -+ -+ dsb -+ -+ /* Disable all AXI ports. */ -+ ldr tmp1, [r2, #UDDRC_PCTRL_0] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_0] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_1] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_1] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_2] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_2] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_3] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_3] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_4] -+ bic tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_4] -+ -+sr_ena_1: -+ /* Wait for all ports to disable. */ -+ ldr tmp1, [r2, #UDDRC_PSTAT] -+ ldr tmp2, =UDDRC_PSTAT_ALL_PORTS -+ tst tmp1, tmp2 -+ bne sr_ena_1 -+ -+ /* Switch to self-refresh. */ -+ ldr tmp1, [r2, #UDDRC_PWRCTL] -+ orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW -+ str tmp1, [r2, #UDDRC_PWRCTL] -+ -+sr_ena_2: -+ /* Wait for self-refresh enter. */ -+ ldr tmp1, [r2, #UDDRC_STAT] -+ bic tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK -+ cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW -+ bne sr_ena_2 -+ -+ /* Put DDR PHY's DLL in bypass mode for non-backup modes. */ -+ cmp r7, #AT91_PM_BACKUP -+ beq sr_ena_3 -+ ldr tmp1, [r3, #DDR3PHY_PIR] -+ orr tmp1, tmp1, #DDR3PHY_PIR_DLLBYP -+ str tmp1, [r3, #DDR3PHY_PIR] -+ -+sr_ena_3: -+ /* Power down DDR PHY data receivers. */ -+ ldr tmp1, [r3, #DDR3PHY_DXCCR] -+ orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR -+ str tmp1, [r3, #DDR3PHY_DXCCR] -+ -+ /* Power down ADDR/CMD IO. */ -+ ldr tmp1, [r3, #DDR3PHY_ACIOCR] -+ orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD -+ orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 -+ orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 -+ str tmp1, [r3, #DDR3PHY_ACIOCR] -+ -+ /* Power down ODT. */ -+ ldr tmp1, [r3, #DDR3PHY_DSGCR] -+ orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 -+ str tmp1, [r3, #DDR3PHY_DSGCR] -+.endm -+ -+/** -+ * Disable self-refresh -+ * -+ * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3 -+ */ -+.macro at91_sramc_self_refresh_dis -+ ldr r2, .sramc_base -+ ldr r3, .sramc_phy_base -+ -+ /* Power up DDR PHY data receivers. */ -+ ldr tmp1, [r3, #DDR3PHY_DXCCR] -+ bic tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR -+ str tmp1, [r3, #DDR3PHY_DXCCR] -+ -+ /* Power up the output of CK and CS pins. */ -+ ldr tmp1, [r3, #DDR3PHY_ACIOCR] -+ bic tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD -+ bic tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0 -+ bic tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0 -+ str tmp1, [r3, #DDR3PHY_ACIOCR] -+ -+ /* Power up ODT. */ -+ ldr tmp1, [r3, #DDR3PHY_DSGCR] -+ bic tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0 -+ str tmp1, [r3, #DDR3PHY_DSGCR] -+ -+ /* Take DDR PHY's DLL out of bypass mode. */ -+ ldr tmp1, [r3, #DDR3PHY_PIR] -+ bic tmp1, tmp1, #DDR3PHY_PIR_DLLBYP -+ str tmp1, [r3, #DDR3PHY_PIR] -+ -+ /* Enable quasi-dynamic programming. */ -+ mov tmp1, #0 -+ str tmp1, [r2, #UDDRC_SWCTRL] -+ -+ /* De-assert SDRAM initialization. */ -+ ldr tmp1, [r2, #UDDRC_DFIMISC] -+ bic tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN -+ str tmp1, [r2, #UDDRC_DFIMISC] -+ -+ /* Quasi-dynamic programming done. */ -+ mov tmp1, #UDDRC_SWCTRL_SW_DONE -+ str tmp1, [r2, #UDDRC_SWCTRL] -+ -+sr_dis_1: -+ ldr tmp1, [r2, #UDDRC_SWSTAT] -+ tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK -+ beq sr_dis_1 -+ -+ /* DLL soft-reset + DLL lock wait + ITM reset */ -+ mov tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \ -+ DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST) -+ str tmp1, [r3, #DDR3PHY_PIR] -+ -+sr_dis_4: -+ /* Wait for it. */ -+ ldr tmp1, [r3, #DDR3PHY_PGSR] -+ tst tmp1, #DDR3PHY_PGSR_IDONE -+ beq sr_dis_4 -+ -+ /* Enable quasi-dynamic programming. */ -+ mov tmp1, #0 -+ str tmp1, [r2, #UDDRC_SWCTRL] -+ -+ /* Assert PHY init complete enable signal. */ -+ ldr tmp1, [r2, #UDDRC_DFIMISC] -+ orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN -+ str tmp1, [r2, #UDDRC_DFIMISC] -+ -+ /* Programming is done. Set sw_done. */ -+ mov tmp1, #UDDRC_SWCTRL_SW_DONE -+ str tmp1, [r2, #UDDRC_SWCTRL] -+ -+sr_dis_5: -+ /* Wait for it. */ -+ ldr tmp1, [r2, #UDDRC_SWSTAT] -+ tst tmp1, #UDDRC_SWSTAT_SW_DONE_ACK -+ beq sr_dis_5 -+ -+ /* Trigger self-refresh exit. */ -+ ldr tmp1, [r2, #UDDRC_PWRCTL] -+ bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW -+ str tmp1, [r2, #UDDRC_PWRCTL] -+ -+sr_dis_6: -+ /* Wait for self-refresh exit done. */ -+ ldr tmp1, [r2, #UDDRC_STAT] -+ bic tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK -+ cmp tmp1, #UDDRC_STAT_OPMODE_NORMAL -+ bne sr_dis_6 -+ -+ /* Enable all AXI ports. */ -+ ldr tmp1, [r2, #UDDRC_PCTRL_0] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_0] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_1] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_1] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_2] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_2] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_3] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_3] -+ -+ ldr tmp1, [r2, #UDDRC_PCTRL_4] -+ orr tmp1, tmp1, #0x1 -+ str tmp1, [r2, #UDDRC_PCTRL_4] -+ -+ dsb -+.endm -+#else - /** - * Enable self-refresh - * -@@ -228,6 +422,7 @@ sdramc_exit_sf: - - sr_dis_exit: - .endm -+#endif - - .macro at91_pm_ulp0_mode - ldr pmc, .pmc_base -@@ -668,6 +863,8 @@ ENTRY(at91_pm_suspend_in_sram) - str tmp1, .sramc_base - ldr tmp1, [r0, #PM_DATA_RAMC1] - str tmp1, .sramc1_base -+ ldr tmp1, [r0, #PM_DATA_RAMC_PHY] -+ str tmp1, .sramc_phy_base - ldr tmp1, [r0, #PM_DATA_MEMCTRL] - str tmp1, .memtype - ldr tmp1, [r0, #PM_DATA_MODE] -@@ -721,6 +918,8 @@ ENDPROC(at91_pm_suspend_in_sram) - .word 0 - .sramc1_base: - .word 0 -+.sramc_phy_base: -+ .word 0 - .shdwc: - .word 0 - .sfrbu: diff --git a/target/linux/at91/patches-5.10/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch b/target/linux/at91/patches-5.10/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch deleted file mode 100644 index 7c8614125c..0000000000 --- a/target/linux/at91/patches-5.10/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch +++ /dev/null @@ -1,165 +0,0 @@ -From 9ee7fd7aa956671727752dac6bd131cf511c1137 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:49:59 +0300 -Subject: [PATCH 209/247] ARM: at91: pm: add support for MCK1..4 save/restore - for ulp modes - -Add support for MCK1..4 save restore for ULP modes. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-14-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 126 ++++++++++++++++++++++++++++++++ - 1 file changed, 126 insertions(+) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -765,7 +765,122 @@ sr_dis_exit: - 2: - .endm - -+/** -+ * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock -+ * -+ * Side effects: overwrites tmp1, tmp2 -+ */ -+.macro at91_mckx_ps_enable -+#ifdef CONFIG_SOC_SAMA7 -+ ldr pmc, .pmc_base -+ -+ /* There are 4 MCKs we need to handle: MCK1..4 */ -+ mov tmp1, #1 -+e_loop: cmp tmp1, #5 -+ beq e_done -+ -+ /* Write MCK ID to retrieve the settings. */ -+ str tmp1, [pmc, #AT91_PMC_MCR_V2] -+ ldr tmp2, [pmc, #AT91_PMC_MCR_V2] -+ -+e_save_mck1: -+ cmp tmp1, #1 -+ bne e_save_mck2 -+ str tmp2, .saved_mck1 -+ b e_ps -+ -+e_save_mck2: -+ cmp tmp1, #2 -+ bne e_save_mck3 -+ str tmp2, .saved_mck2 -+ b e_ps -+ -+e_save_mck3: -+ cmp tmp1, #3 -+ bne e_save_mck4 -+ str tmp2, .saved_mck3 -+ b e_ps -+ -+e_save_mck4: -+ str tmp2, .saved_mck4 -+ -+e_ps: -+ /* Use CSS=MAINCK and DIV=1. */ -+ bic tmp2, tmp2, #AT91_PMC_MCR_V2_CSS -+ bic tmp2, tmp2, #AT91_PMC_MCR_V2_DIV -+ orr tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK -+ orr tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1 -+ str tmp2, [pmc, #AT91_PMC_MCR_V2] -+ -+ wait_mckrdy tmp1 -+ -+ add tmp1, tmp1, #1 -+ b e_loop -+ -+e_done: -+#endif -+.endm -+ -+/** -+ * at91_mckx_ps_restore: restore MCK1..4 settings -+ * -+ * Side effects: overwrites tmp1, tmp2 -+ */ -+.macro at91_mckx_ps_restore -+#ifdef CONFIG_SOC_SAMA7 -+ ldr pmc, .pmc_base -+ -+ /* There are 4 MCKs we need to handle: MCK1..4 */ -+ mov tmp1, #1 -+r_loop: cmp tmp1, #5 -+ beq r_done -+ -+r_save_mck1: -+ cmp tmp1, #1 -+ bne r_save_mck2 -+ ldr tmp2, .saved_mck1 -+ b r_ps -+ -+r_save_mck2: -+ cmp tmp1, #2 -+ bne r_save_mck3 -+ ldr tmp2, .saved_mck2 -+ b r_ps -+ -+r_save_mck3: -+ cmp tmp1, #3 -+ bne r_save_mck4 -+ ldr tmp2, .saved_mck3 -+ b r_ps -+ -+r_save_mck4: -+ ldr tmp2, .saved_mck4 -+ -+r_ps: -+ /* Write MCK ID to retrieve the settings. */ -+ str tmp1, [pmc, #AT91_PMC_MCR_V2] -+ ldr tmp3, [pmc, #AT91_PMC_MCR_V2] -+ -+ /* We need to restore CSS and DIV. */ -+ bic tmp3, tmp3, #AT91_PMC_MCR_V2_CSS -+ bic tmp3, tmp3, #AT91_PMC_MCR_V2_DIV -+ orr tmp3, tmp3, tmp2 -+ bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK -+ orr tmp3, tmp3, tmp1 -+ orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD -+ str tmp2, [pmc, #AT91_PMC_MCR_V2] -+ -+ wait_mckrdy tmp1 -+ -+ add tmp1, tmp1, #1 -+ b r_loop -+r_done: -+#endif -+.endm -+ - .macro at91_ulp_mode -+ at91_mckx_ps_enable -+ - ldr pmc, .pmc_base - ldr tmp2, .mckr_offset - ldr tmp3, .pm_mode -@@ -817,6 +932,7 @@ ulp_exit: - mov tmp3, #0 - wait_mckrdy tmp3 - -+ at91_mckx_ps_restore - .endm - - .macro at91_backup_mode -@@ -946,6 +1062,16 @@ ENDPROC(at91_pm_suspend_in_sram) - .word 0 - .saved_osc_status: - .word 0 -+#ifdef CONFIG_SOC_SAMA7 -+.saved_mck1: -+ .word 0 -+.saved_mck2: -+ .word 0 -+.saved_mck3: -+ .word 0 -+.saved_mck4: -+ .word 0 -+#endif - - ENTRY(at91_pm_suspend_in_sram_sz) - .word .-at91_pm_suspend_in_sram diff --git a/target/linux/at91/patches-5.10/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch b/target/linux/at91/patches-5.10/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch deleted file mode 100644 index ede839bf70..0000000000 --- a/target/linux/at91/patches-5.10/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch +++ /dev/null @@ -1,79 +0,0 @@ -From b2073cc043612bf95b115bd94103cfb2936f05bf Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:00 +0300 -Subject: [PATCH 210/247] ARM: at91: pm: add support for 2.5V LDO regulator - control - -Add support to disable/enable 2.5V LDO regulator when entering/exiting -any ULP mode. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-15-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.h | 1 + - arch/arm/mach-at91/pm_suspend.S | 29 +++++++++++++++++++++++++++++ - 2 files changed, 30 insertions(+) - ---- a/arch/arm/mach-at91/pm.h -+++ b/arch/arm/mach-at91/pm.h -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - - #define AT91_MEMCTRL_MC 0 - #define AT91_MEMCTRL_SDRAMC 1 ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -83,6 +83,29 @@ tmp3 .req r6 - - .endm - -+/** -+ * Set state for 2.5V low power regulator -+ * @ena: 0 - disable regulator -+ * 1 - enable regulator -+ * -+ * Side effects: overwrites r7, r8, r9, r10 -+ */ -+ .macro at91_2_5V_reg_set_low_power ena -+#ifdef CONFIG_SOC_SAMA7 -+ ldr r7, .sfrbu -+ mov r8, #\ena -+ ldr r9, [r7, #AT91_SFRBU_25LDOCR] -+ orr r9, r9, #AT91_SFRBU_25LDOCR_LP -+ cmp r8, #1 -+ beq lp_done_\ena -+ bic r9, r9, #AT91_SFRBU_25LDOCR_LP -+lp_done_\ena: -+ ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY -+ orr r9, r9, r10 -+ str r9, [r7, #AT91_SFRBU_25LDOCR] -+#endif -+ .endm -+ - .text - - .arm -@@ -906,6 +929,9 @@ save_mck: - - at91_plla_disable - -+ /* Enable low power mode for 2.5V regulator. */ -+ at91_2_5V_reg_set_low_power 1 -+ - ldr tmp3, .pm_mode - cmp tmp3, #AT91_PM_ULP1 - beq ulp1_mode -@@ -918,6 +944,9 @@ ulp1_mode: - b ulp_exit - - ulp_exit: -+ /* Disable low power mode for 2.5V regulator. */ -+ at91_2_5V_reg_set_low_power 0 -+ - ldr pmc, .pmc_base - - at91_plla_enable diff --git a/target/linux/at91/patches-5.10/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch b/target/linux/at91/patches-5.10/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch deleted file mode 100644 index 886f81e7ad..0000000000 --- a/target/linux/at91/patches-5.10/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 2b522a22243938dd7613e09c954172b1fa6217f5 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:01 +0300 -Subject: [PATCH 211/247] ARM: at91: pm: wait for ddr power mode off - -Wait for DDR power mode off before shutting down the core. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-16-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -980,6 +980,11 @@ ulp_exit: - mov tmp1, #0x1 - str tmp1, [r0, #0x10] - -+ /* Wait for it. */ -+1: ldr tmp1, [r0, #0x10] -+ tst tmp1, #0x1 -+ beq 1b -+ - /* Shutdown */ - ldr r0, .shdwc - mov tmp1, #0xA5000000 diff --git a/target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch b/target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch deleted file mode 100644 index e496245061..0000000000 --- a/target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 3f55310c00b8c478da1458704027036c1a414973 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:03 +0300 -Subject: [PATCH 212/247] ARM: at91: pm: add sama7g5 ddr controller - -Add SAMA7G5 DDR controller to the list of DDR controller compatibles. -At the moment there is no standby support. Adapt the code for this. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -548,6 +548,7 @@ static const struct of_device_id ramc_id - { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, - { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, - { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, -+ { .compatible = "microchip,sama7g5-uddrc", }, - { /*sentinel*/ } - }; - -@@ -569,9 +570,11 @@ static __init int at91_dt_ramc(void) - } - - ramc = of_id->data; -- if (!standby) -- standby = ramc->idle; -- soc_pm.data.memctrl = ramc->memctrl; -+ if (ramc) { -+ if (!standby) -+ standby = ramc->idle; -+ soc_pm.data.memctrl = ramc->memctrl; -+ } - - idx++; - } diff --git a/target/linux/at91/patches-5.10/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch b/target/linux/at91/patches-5.10/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch deleted file mode 100644 index 89dcacec92..0000000000 --- a/target/linux/at91/patches-5.10/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch +++ /dev/null @@ -1,94 +0,0 @@ -From bbbbf16c44f34a2d563fa7d71de64ffe3b4b82dc Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:04 +0300 -Subject: [PATCH 213/247] ARM: at91: pm: add sama7g5 ddr phy controller - -SAMA7G5 self-refresh procedure accesses also the DDR PHY registers. -Adapt the code so that the at91_dt_ramc() to look also for DDR PHYs, -in case it is mandatory. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 27 +++++++++++++++++++++------ - 1 file changed, 21 insertions(+), 6 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -552,7 +552,12 @@ static const struct of_device_id ramc_id - { /*sentinel*/ } - }; - --static __init int at91_dt_ramc(void) -+static const struct of_device_id ramc_phy_ids[] __initconst = { -+ { .compatible = "microchip,sama7g5-ddr3phy", }, -+ { /* Sentinel. */ }, -+}; -+ -+static __init void at91_dt_ramc(bool phy_mandatory) - { - struct device_node *np; - const struct of_device_id *of_id; -@@ -585,6 +590,16 @@ static __init int at91_dt_ramc(void) - goto unmap_ramc; - } - -+ /* Lookup for DDR PHY node, if any. */ -+ for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { -+ soc_pm.data.ramc_phy = of_iomap(np, 0); -+ if (!soc_pm.data.ramc_phy) -+ panic(pr_fmt("unable to map ramc phy cpu registers\n")); -+ } -+ -+ if (phy_mandatory && !soc_pm.data.ramc_phy) -+ panic(pr_fmt("DDR PHY is mandatory!\n")); -+ - if (!standby) { - pr_warn("ramc no standby function available\n"); - return 0; -@@ -953,7 +968,7 @@ void __init at91rm9200_pm_init(void) - soc_pm.data.standby_mode = AT91_PM_STANDBY; - soc_pm.data.suspend_mode = AT91_PM_ULP0; - -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - -@@ -980,7 +995,7 @@ void __init sam9x60_pm_init(void) - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); - at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - -@@ -1005,7 +1020,7 @@ void __init at91sam9_pm_init(void) - soc_pm.data.standby_mode = AT91_PM_STANDBY; - soc_pm.data.suspend_mode = AT91_PM_ULP0; - -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - -@@ -1023,7 +1038,7 @@ void __init sama5_pm_init(void) - return; - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - -@@ -1048,7 +1063,7 @@ void __init sama5d2_pm_init(void) - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); - at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); -- ret = at91_dt_ramc(); -+ ret = at91_dt_ramc(false); - if (ret) - return; - diff --git a/target/linux/at91/patches-5.10/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch b/target/linux/at91/patches-5.10/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch deleted file mode 100644 index a46b5acb22..0000000000 --- a/target/linux/at91/patches-5.10/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch +++ /dev/null @@ -1,151 +0,0 @@ -From b355bb98eae3e343969fc5a0203e0dab472a6acd Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:05 +0300 -Subject: [PATCH 214/247] ARM: at91: pm: save ddr phy calibration data to - securam - -The resuming from backup mode is done with the help of bootloader. -The bootloader reconfigure the DDR controller and DDR PHY controller. -To speed-up the resuming process save the PHY calibration data into -SECURAM before suspending (securam is powered on backup mode). -This data will be later used by bootloader in DDR PHY reconfiguration -process. Also, in the process or recalibration the first 8 words of -the memory may get corrupted. To solve this, these 8 words are saved -in the securam and restored by bootloader in the process of PHY -configuration. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-20-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 60 ++++++++++++++++++++++++++++++++++++++++- - 1 file changed, 59 insertions(+), 1 deletion(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -27,18 +28,23 @@ - #include "generic.h" - #include "pm.h" - -+#define BACKUP_DDR_PHY_CALIBRATION (9) -+ - /** - * struct at91_pm_bu - AT91 power management backup unit data structure - * @suspended: true if suspended to backup mode - * @reserved: reserved - * @canary: canary data for memory checking after exit from backup mode - * @resume: resume API -+ * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words -+ * of the memory - */ - struct at91_pm_bu { - int suspended; - unsigned long reserved; - phys_addr_t canary; - phys_addr_t resume; -+ unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; - }; - - /** -@@ -48,6 +54,7 @@ struct at91_pm_bu { - * @ws_ids: wakup sources of_device_id array - * @data: PM data to be used on last phase of suspend - * @bu: backup unit mapped data (for backup mode) -+ * @memcs: memory chip select - */ - struct at91_soc_pm { - int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); -@@ -55,6 +62,7 @@ struct at91_soc_pm { - const struct of_device_id *ws_ids; - struct at91_pm_bu *bu; - struct at91_pm_data data; -+ void *memcs; - }; - - /** -@@ -316,6 +324,19 @@ extern u32 at91_pm_suspend_in_sram_sz; - - static int at91_suspend_finish(unsigned long val) - { -+ int i; -+ -+ if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) { -+ /* -+ * The 1st 8 words of memory might get corrupted in the process -+ * of DDR PHY recalibration; it is saved here in securam and it -+ * will be restored later, after recalibration, by bootloader -+ */ -+ for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++) -+ soc_pm.bu->ddr_phy_calibration[i] = -+ *((unsigned int *)soc_pm.memcs + (i - 1)); -+ } -+ - flush_cache_all(); - outer_disable(); - -@@ -688,12 +709,40 @@ static bool __init at91_is_pm_mode_activ - soc_pm.data.suspend_mode == pm_mode); - } - -+static int __init at91_pm_backup_scan_memcs(unsigned long node, -+ const char *uname, int depth, -+ void *data) -+{ -+ const char *type; -+ const __be32 *reg; -+ int *located = data; -+ int size; -+ -+ /* Memory node already located. */ -+ if (*located) -+ return 0; -+ -+ type = of_get_flat_dt_prop(node, "device_type", NULL); -+ -+ /* We are scanning "memory" nodes only. */ -+ if (!type || strcmp(type, "memory")) -+ return 0; -+ -+ reg = of_get_flat_dt_prop(node, "reg", &size); -+ if (reg) { -+ soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg)); -+ *located = 1; -+ } -+ -+ return 0; -+} -+ - static int __init at91_pm_backup_init(void) - { - struct gen_pool *sram_pool; - struct device_node *np; - struct platform_device *pdev; -- int ret = -ENODEV; -+ int ret = -ENODEV, located = 0; - - if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) - return -EPERM; -@@ -728,6 +777,15 @@ static int __init at91_pm_backup_init(vo - soc_pm.bu->suspended = 0; - soc_pm.bu->canary = __pa_symbol(&canary); - soc_pm.bu->resume = __pa_symbol(cpu_resume); -+ if (soc_pm.data.ramc_phy) { -+ of_scan_flat_dt(at91_pm_backup_scan_memcs, &located); -+ if (!located) -+ goto securam_fail; -+ -+ /* DDR3PHY_ZQ0SR0 */ -+ soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy + -+ 0x188); -+ } - - return 0; - diff --git a/target/linux/at91/patches-5.10/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch b/target/linux/at91/patches-5.10/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch deleted file mode 100644 index cc5f4aec0a..0000000000 --- a/target/linux/at91/patches-5.10/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 62be32b56ff31b2cd048a53fac40a165c5bc66cd Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:06 +0300 -Subject: [PATCH 215/247] ARM: at91: pm: add backup mode support for SAMA7G5 - -Adapt at91_pm_backup_init() to work for SAMA7G5. Also, set the LPM pin -to shutdown controller. This will signal to PMIC that it needs to switch -to the state corresponding to backup mode. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-21-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 3 ++- - arch/arm/mach-at91/pm_suspend.S | 7 +++++++ - 2 files changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -744,7 +744,8 @@ static int __init at91_pm_backup_init(vo - struct platform_device *pdev; - int ret = -ENODEV, located = 0; - -- if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) -+ if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && -+ !IS_ENABLED(CONFIG_SOC_SAMA7G5)) - return -EPERM; - - if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -106,6 +106,12 @@ lp_done_\ena: - #endif - .endm - -+ .macro at91_backup_set_lpm reg -+#ifdef CONFIG_SOC_SAMA7 -+ orr \reg, \reg, #0x200000 -+#endif -+ .endm -+ - .text - - .arm -@@ -989,6 +995,7 @@ ulp_exit: - ldr r0, .shdwc - mov tmp1, #0xA5000000 - add tmp1, tmp1, #0x1 -+ at91_backup_set_lpm tmp1 - str tmp1, [r0, #0] - .endm - diff --git a/target/linux/at91/patches-5.10/216-ARM-at91-pm-add-sama7g5-s-pmc.patch b/target/linux/at91/patches-5.10/216-ARM-at91-pm-add-sama7g5-s-pmc.patch deleted file mode 100644 index a471195fbc..0000000000 --- a/target/linux/at91/patches-5.10/216-ARM-at91-pm-add-sama7g5-s-pmc.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e9855ac00e8d9a2c41cea42b4f38a2b0b010bef3 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:07 +0300 -Subject: [PATCH 216/247] ARM: at91: pm: add sama7g5's pmc - -Add SAMA7G5's PMC to compatible list. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-22-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -912,6 +912,11 @@ static const struct pmc_info pmc_infos[] - .mckr = 0x28, - .version = AT91_PMC_V2, - }, -+ { -+ .mckr = 0x28, -+ .version = AT91_PMC_V2, -+ }, -+ - }; - - static const struct of_device_id atmel_pmc_ids[] __initconst = { -@@ -927,6 +932,7 @@ static const struct of_device_id atmel_p - { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, - { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, - { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, -+ { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, - { /* sentinel */ }, - }; - diff --git a/target/linux/at91/patches-5.10/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch b/target/linux/at91/patches-5.10/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch deleted file mode 100644 index dca065971b..0000000000 --- a/target/linux/at91/patches-5.10/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch +++ /dev/null @@ -1,63 +0,0 @@ -From dea645bce478cc72a2bf2413ec873927d1471442 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Thu, 15 Apr 2021 13:50:08 +0300 -Subject: [PATCH 217/247] ARM: at91: sama7: introduce sama7 SoC family - -Introduce new family of SoCs, sama7, and first SoC, sama7g5. - -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: keep only the sama7_dt] -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-23-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/Makefile | 1 + - arch/arm/mach-at91/sama7.c | 32 ++++++++++++++++++++++++++++++++ - 2 files changed, 33 insertions(+) - create mode 100644 arch/arm/mach-at91/sama7.c - ---- a/arch/arm/mach-at91/Makefile -+++ b/arch/arm/mach-at91/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_AT91RM9200) += at91rm92 - obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o - obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o - obj-$(CONFIG_SOC_SAMA5) += sama5.o -+obj-$(CONFIG_SOC_SAMA7) += sama7.o - obj-$(CONFIG_SOC_SAMV7) += samv7.o - - # Power Management ---- /dev/null -+++ b/arch/arm/mach-at91/sama7.c -@@ -0,0 +1,32 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Setup code for SAMA7 -+ * -+ * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries -+ * -+ */ -+ -+#include -+#include -+ -+#include -+#include -+ -+#include "generic.h" -+ -+static void __init sama7_dt_device_init(void) -+{ -+ of_platform_default_populate(NULL, NULL, NULL); -+} -+ -+static const char *const sama7_dt_board_compat[] __initconst = { -+ "microchip,sama7", -+ NULL -+}; -+ -+DT_MACHINE_START(sama7_dt, "Microchip SAMA7") -+ /* Maintainer: Microchip */ -+ .init_machine = sama7_dt_device_init, -+ .dt_compat = sama7_dt_board_compat, -+MACHINE_END -+ diff --git a/target/linux/at91/patches-5.10/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch b/target/linux/at91/patches-5.10/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch deleted file mode 100644 index aada9c9679..0000000000 --- a/target/linux/at91/patches-5.10/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch +++ /dev/null @@ -1,96 +0,0 @@ -From aba3984dc7a405d20b83bff603d23719d0e26bc7 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:09 +0300 -Subject: [PATCH 218/247] ARM: at91: pm: add pm support for SAMA7G5 - -Add support for SAMA7G5 power management modes: standby, ulp0, ulp1, backup. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-24-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/generic.h | 2 ++ - arch/arm/mach-at91/pm.c | 37 ++++++++++++++++++++++++++++++++++++ - arch/arm/mach-at91/sama7.c | 1 + - 3 files changed, 40 insertions(+) - ---- a/arch/arm/mach-at91/generic.h -+++ b/arch/arm/mach-at91/generic.h -@@ -14,12 +14,14 @@ extern void __init at91sam9_pm_init(void - extern void __init sam9x60_pm_init(void); - extern void __init sama5_pm_init(void); - extern void __init sama5d2_pm_init(void); -+extern void __init sama7_pm_init(void); - #else - static inline void __init at91rm9200_pm_init(void) { } - static inline void __init at91sam9_pm_init(void) { } - static inline void __init sam9x60_pm_init(void) { } - static inline void __init sama5_pm_init(void) { } - static inline void __init sama5d2_pm_init(void) { } -+static inline void __init sama7_pm_init(void) { } - #endif - - #endif /* _AT91_GENERIC_H */ ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -152,6 +152,17 @@ static const struct of_device_id sam9x60 - { /* sentinel */ } - }; - -+static const struct of_device_id sama7g5_ws_ids[] = { -+ { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, -+ { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, -+ { .compatible = "usb-ohci", .data = &ws_info[2] }, -+ { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, -+ { .compatible = "usb-ehci", .data = &ws_info[2] }, -+ { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, -+ { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, -+ { /* sentinel */ } -+}; -+ - static int at91_pm_config_ws(unsigned int pm_mode, bool set) - { - const struct wakeup_source_info *wsi; -@@ -1139,6 +1150,32 @@ void __init sama5d2_pm_init(void) - soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; - } - -+void __init sama7_pm_init(void) -+{ -+ static const int modes[] __initconst = { -+ AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, -+ }; -+ static const u32 iomaps[] __initconst = { -+ [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU), -+ [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) | -+ AT91_PM_IOMAP(SHDWC), -+ [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | -+ AT91_PM_IOMAP(SHDWC), -+ }; -+ -+ if (!IS_ENABLED(CONFIG_SOC_SAMA7)) -+ return; -+ -+ at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); -+ -+ at91_dt_ramc(true); -+ at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); -+ at91_pm_init(NULL); -+ -+ soc_pm.ws_ids = sama7g5_ws_ids; -+ soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; -+} -+ - static int __init at91_pm_modes_select(char *str) - { - char *s; ---- a/arch/arm/mach-at91/sama7.c -+++ b/arch/arm/mach-at91/sama7.c -@@ -17,6 +17,7 @@ - static void __init sama7_dt_device_init(void) - { - of_platform_default_populate(NULL, NULL, NULL); -+ sama7_pm_init(); - } - - static const char *const sama7_dt_board_compat[] __initconst = { diff --git a/target/linux/at91/patches-5.10/219-ARM-at91-pm-add-sama7g5-shdwc.patch b/target/linux/at91/patches-5.10/219-ARM-at91-pm-add-sama7g5-shdwc.patch deleted file mode 100644 index 062274c18f..0000000000 --- a/target/linux/at91/patches-5.10/219-ARM-at91-pm-add-sama7g5-shdwc.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 84ff37cc98e6aaefe27d6edd5e3ced2be99d9833 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 15 Apr 2021 13:50:10 +0300 -Subject: [PATCH 219/247] ARM: at91: pm: add sama7g5 shdwc - -Add SAMA7G5 SHDWC. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210415105010.569620-25-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -809,6 +809,7 @@ securam_fail: - static const struct of_device_id atmel_shdwc_ids[] = { - { .compatible = "atmel,sama5d2-shdwc" }, - { .compatible = "microchip,sam9x60-shdwc" }, -+ { .compatible = "microchip,sama7g5-shdwc" }, - { /* sentinel. */ } - }; - diff --git a/target/linux/at91/patches-5.10/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch b/target/linux/at91/patches-5.10/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch deleted file mode 100644 index fdb45afa7d..0000000000 --- a/target/linux/at91/patches-5.10/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch +++ /dev/null @@ -1,233 +0,0 @@ -From 2223a85aed2d892bd7c13053f27e777c743e5332 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 28 Jun 2021 15:04:51 +0300 -Subject: [PATCH 220/247] ARM: configs: at91: add defconfig for sama7 family of - SoCs - -Add defconfig for sama7 SoC family. - -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: add clocks, ethernet, timers, power] -Signed-off-by: Claudiu Beznea -[codrin.ciubotariu@microchip.com: add audio] -Signed-off-by: Codrin Ciubotariu -[nicolas.ferre@microchip.com: atags not set, mtd tests, spi gpio] -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210628120452.74408-3-eugen.hristev@microchip.com ---- - arch/arm/configs/sama7_defconfig | 209 +++++++++++++++++++++++++++++++ - 1 file changed, 209 insertions(+) - create mode 100644 arch/arm/configs/sama7_defconfig - ---- /dev/null -+++ b/arch/arm/configs/sama7_defconfig -@@ -0,0 +1,209 @@ -+# CONFIG_LOCALVERSION_AUTO is not set -+# CONFIG_SWAP is not set -+CONFIG_SYSVIPC=y -+CONFIG_NO_HZ_IDLE=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_LOG_BUF_SHIFT=16 -+CONFIG_CGROUPS=y -+CONFIG_CGROUP_DEBUG=y -+CONFIG_NAMESPACES=y -+CONFIG_SYSFS_DEPRECATED=y -+CONFIG_SYSFS_DEPRECATED_V2=y -+CONFIG_BLK_DEV_INITRD=y -+# CONFIG_FHANDLE is not set -+# CONFIG_IO_URING is not set -+CONFIG_KALLSYMS_ALL=y -+CONFIG_EMBEDDED=y -+# CONFIG_VM_EVENT_COUNTERS is not set -+CONFIG_SLAB=y -+CONFIG_ARCH_AT91=y -+CONFIG_SOC_SAMA7G5=y -+CONFIG_ATMEL_CLOCKSOURCE_TCB=y -+# CONFIG_CACHE_L2X0 is not set -+# CONFIG_ARM_PATCH_IDIV is not set -+# CONFIG_CPU_SW_DOMAIN_PAN is not set -+CONFIG_FORCE_MAX_ZONEORDER=15 -+CONFIG_UACCESS_WITH_MEMCPY=y -+# CONFIG_ATAGS is not set -+CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel" -+CONFIG_VFP=y -+CONFIG_NEON=y -+CONFIG_KERNEL_MODE_NEON=y -+CONFIG_MODULES=y -+CONFIG_MODULE_FORCE_LOAD=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODULE_FORCE_UNLOAD=y -+# CONFIG_BLK_DEV_BSG is not set -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_EFI_PARTITION is not set -+# CONFIG_COREDUMP is not set -+# CONFIG_COMPACTION is not set -+CONFIG_CMA=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+# CONFIG_INET_DIAG is not set -+CONFIG_IPV6_SIT_6RD=y -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_VLAN_FILTERING=y -+CONFIG_NET_DSA=m -+CONFIG_VLAN_8021Q=m -+CONFIG_CAN=y -+CONFIG_CAN_M_CAN=y -+CONFIG_CAN_M_CAN_PLATFORM=y -+CONFIG_BT=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=y -+CONFIG_BT_HCIBTUSB=y -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_H4=y -+CONFIG_BT_HCIVHCI=y -+CONFIG_CFG80211=m -+# CONFIG_CFG80211_DEFAULT_PS is not set -+CONFIG_CFG80211_DEBUGFS=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=m -+CONFIG_MAC80211_LEDS=y -+CONFIG_RFKILL=y -+CONFIG_RFKILL_INPUT=y -+CONFIG_PCCARD=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+# CONFIG_STANDALONE is not set -+# CONFIG_PREVENT_FIRMWARE_BUILD is not set -+# CONFIG_ALLOW_DEV_COREDUMP is not set -+CONFIG_MTD=y -+CONFIG_MTD_TESTS=m -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_COUNT=1 -+CONFIG_BLK_DEV_RAM_SIZE=8192 -+CONFIG_EEPROM_AT24=y -+CONFIG_SCSI=y -+CONFIG_BLK_DEV_SD=y -+CONFIG_NETDEVICES=y -+CONFIG_MACB=y -+CONFIG_MICREL_PHY=y -+CONFIG_INPUT_EVDEV=y -+CONFIG_KEYBOARD_GPIO=y -+# CONFIG_INPUT_MOUSE is not set -+CONFIG_LEGACY_PTY_COUNT=4 -+CONFIG_SERIAL_ATMEL=y -+CONFIG_SERIAL_ATMEL_CONSOLE=y -+CONFIG_HW_RANDOM=y -+CONFIG_I2C=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_AT91=y -+CONFIG_SPI=y -+CONFIG_SPI_MEM=y -+CONFIG_SPI_ATMEL=y -+CONFIG_SPI_GPIO=y -+CONFIG_PINCTRL_AT91=y -+CONFIG_PINCTRL_AT91PIO4=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_POWER_RESET=y -+CONFIG_POWER_RESET_AT91_RESET=y -+CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y -+# CONFIG_HWMON is not set -+CONFIG_WATCHDOG=y -+CONFIG_SAMA5D4_WATCHDOG=y -+CONFIG_MFD_ATMEL_FLEXCOM=y -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_MCP16502=y -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_SUPPORT_FILTER=y -+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_PLATFORM_SUPPORT=y -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_IMX219=m -+CONFIG_VIDEO_IMX274=m -+CONFIG_VIDEO_OV5647=m -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_SOC=y -+CONFIG_SND_ATMEL_SOC=y -+CONFIG_SND_SOC_MIKROE_PROTO=m -+CONFIG_SND_MCHP_SOC_I2S_MCC=y -+CONFIG_SND_MCHP_SOC_SPDIFTX=y -+CONFIG_SND_MCHP_SOC_SPDIFRX=y -+CONFIG_SND_SOC_PCM5102A=y -+CONFIG_SND_SOC_SPDIF=y -+CONFIG_SND_SIMPLE_CARD=y -+CONFIG_USB=y -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+CONFIG_USB_DYNAMIC_MINORS=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_UAS=y -+CONFIG_USB_GADGET=y -+CONFIG_U_SERIAL_CONSOLE=y -+CONFIG_USB_ATMEL_USBA=m -+CONFIG_USB_CONFIGFS=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_UVC=y -+CONFIG_USB_G_SERIAL=m -+CONFIG_MMC=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_AT91=y -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_RTC_CLASS=y -+# CONFIG_RTC_NVMEM is not set -+CONFIG_RTC_DRV_AT91RM9200=y -+CONFIG_RTC_DRV_AT91SAM9=y -+CONFIG_DMADEVICES=y -+CONFIG_AT_XDMAC=y -+CONFIG_DMATEST=y -+CONFIG_STAGING=y -+CONFIG_MICROCHIP_PIT64B=y -+# CONFIG_IOMMU_SUPPORT is not set -+# CONFIG_ATMEL_EBI is not set -+CONFIG_IIO=y -+CONFIG_IIO_SW_TRIGGER=y -+CONFIG_AT91_SAMA5D2_ADC=y -+CONFIG_PWM=y -+CONFIG_PWM_ATMEL=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT3_FS=y -+CONFIG_FANOTIFY=y -+CONFIG_VFAT_FS=y -+CONFIG_TMPFS=y -+CONFIG_NFS_FS=y -+CONFIG_ROOT_NFS=y -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_850=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_UTF8=y -+CONFIG_LSM="N" -+CONFIG_CRYPTO_DEFLATE=y -+CONFIG_CRYPTO_LZO=y -+# CONFIG_CRYPTO_HW is not set -+CONFIG_CRC_CCITT=y -+CONFIG_CRC_ITU_T=y -+CONFIG_DMA_CMA=y -+CONFIG_CMA_SIZE_MBYTES=32 -+CONFIG_CMA_ALIGNMENT=9 -+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -+CONFIG_DEBUG_FS=y -+# CONFIG_DEBUG_MISC is not set -+# CONFIG_SCHED_DEBUG is not set -+CONFIG_STACKTRACE=y -+# CONFIG_FTRACE is not set -+CONFIG_DEBUG_USER=y -+# CONFIG_RUNTIME_TESTING_MENU is not set diff --git a/target/linux/at91/patches-5.10/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch b/target/linux/at91/patches-5.10/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch deleted file mode 100644 index 6c95d4a0f5..0000000000 --- a/target/linux/at91/patches-5.10/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a62536054548e85da84ed835dc87baa8e5e99b41 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 28 Jun 2021 15:04:52 +0300 -Subject: [PATCH 221/247] ARM: multi_v7_defconfig: add sama7g5 SoC - -Add the Microchip SAMA7G5 ARM v7 Cortex-A7 based SoC to multi_v7_defconfig. -Also add it's clock timer, the PIT64B. - -Signed-off-by: Eugen Hristev -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210628120452.74408-4-eugen.hristev@microchip.com ---- - arch/arm/configs/multi_v7_defconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/configs/multi_v7_defconfig -+++ b/arch/arm/configs/multi_v7_defconfig -@@ -15,6 +15,7 @@ CONFIG_ARCH_AT91=y - CONFIG_SOC_SAMA5D2=y - CONFIG_SOC_SAMA5D3=y - CONFIG_SOC_SAMA5D4=y -+CONFIG_SOC_SAMA7G5=y - CONFIG_ARCH_BCM=y - CONFIG_ARCH_BCM_CYGNUS=y - CONFIG_ARCH_BCM_HR2=y -@@ -967,6 +968,7 @@ CONFIG_APQ_MMCC_8084=y - CONFIG_MSM_GCC_8660=y - CONFIG_MSM_MMCC_8960=y - CONFIG_MSM_MMCC_8974=y -+CONFIG_MICROCHIP_PIT64B=y - CONFIG_BCM2835_MBOX=y - CONFIG_ROCKCHIP_IOMMU=y - CONFIG_TEGRA_IOMMU_GART=y diff --git a/target/linux/at91/patches-5.10/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch b/target/linux/at91/patches-5.10/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch deleted file mode 100644 index b79ce5ab2e..0000000000 --- a/target/linux/at91/patches-5.10/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch +++ /dev/null @@ -1,2154 +0,0 @@ -From 969b39d51b7df0869cca9983b06cefb59dae72b0 Mon Sep 17 00:00:00 2001 -From: Eugen Hristev -Date: Mon, 28 Jun 2021 15:04:50 +0300 -Subject: [PATCH 222/247] ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek - -Add Device Tree for sama7g5 SoC and associated board sama7g5-ek - -Signed-off-by: Eugen Hristev -[claudiu.beznea@microchip.com: add clocks, ethernet, timers, power] -Signed-off-by: Claudiu Beznea -[codrin.ciubotariu@microchip.com: add audio] -Signed-off-by: Codrin Ciubotariu -[nicolas.ferre@microchip.com: removed eeproms, reorder i2s dma chans] -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210628120452.74408-2-eugen.hristev@microchip.com -[claudiu.beznea: adapt to kernel v5.10] -Signed-off-by: Claudiu Beznea ---- - arch/arm/boot/dts/Makefile | 2 + - arch/arm/boot/dts/at91-sama7g5ek.dts | 656 +++++++++++++++++++ - arch/arm/boot/dts/sama7g5-pinfunc.h | 923 +++++++++++++++++++++++++++ - arch/arm/boot/dts/sama7g5.dtsi | 528 +++++++++++++++ - 4 files changed, 2109 insertions(+) - create mode 100644 arch/arm/boot/dts/at91-sama7g5ek.dts - create mode 100644 arch/arm/boot/dts/sama7g5-pinfunc.h - create mode 100644 arch/arm/boot/dts/sama7g5.dtsi - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -79,6 +79,8 @@ dtb-$(CONFIG_ARCH_ATLAS6) += \ - atlas6-evb.dtb - dtb-$(CONFIG_ARCH_ATLAS7) += \ - atlas7-evb.dtb -+dtb-$(CONFIG_SOC_SAMA7G5) += \ -+ at91-sama7g5ek.dtb - dtb-$(CONFIG_ARCH_AXXIA) += \ - axm5516-amarillo.dtb - dtb-$(CONFIG_ARCH_BCM2835) += \ ---- /dev/null -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -0,0 +1,656 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board -+ * -+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries -+ * -+ * Author: Eugen Hristev -+ * Author: Claudiu Beznea -+ * -+ */ -+/dts-v1/; -+#include "sama7g5-pinfunc.h" -+#include "sama7g5.dtsi" -+#include -+#include -+ -+/ { -+ model = "Microchip SAMA7G5-EK"; -+ compatible = "microchip,sama7g5ek", "microchip,sama7g5", "microchip,sama7"; -+ -+ chosen { -+ bootargs = "rw root=/dev/mmcblk1p2 rootfstype=ext4 rootwait"; -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ aliases { -+ serial0 = &uart3; -+ serial1 = &uart4; -+ serial2 = &uart7; -+ serial3 = &uart0; -+ i2c0 = &i2c1; -+ i2c1 = &i2c8; -+ i2c2 = &i2c9; -+ }; -+ -+ clocks { -+ slow_xtal { -+ clock-frequency = <32768>; -+ }; -+ -+ main_xtal { -+ clock-frequency = <24000000>; -+ }; -+ }; -+ -+ gpio_keys { -+ compatible = "gpio-keys"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_key_gpio_default>; -+ -+ bp1 { -+ label = "PB_USER"; -+ gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_led_gpio_default>; -+ status = "okay"; /* Conflict with pwm. */ -+ -+ red_led { -+ label = "red"; -+ gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ green_led { -+ label = "green"; -+ gpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ blue_led { -+ label = "blue"; -+ gpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ /* 512 M */ -+ memory@60000000 { -+ device_type = "memory"; -+ reg = <0x60000000 0x20000000>; -+ }; -+ -+ sound: sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "sama7g5ek audio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ simple-audio-card,dai-link@0 { -+ reg = <0>; -+ cpu { -+ sound-dai = <&spdiftx>; -+ }; -+ codec { -+ sound-dai = <&spdif_out>; -+ }; -+ }; -+ simple-audio-card,dai-link@1 { -+ reg = <1>; -+ cpu { -+ sound-dai = <&spdifrx>; -+ }; -+ codec { -+ sound-dai = <&spdif_in>; -+ }; -+ }; -+ }; -+ -+ spdif_in: spdif-in { -+ #sound-dai-cells = <0>; -+ compatible = "linux,spdif-dir"; -+ }; -+ -+ spdif_out: spdif-out { -+ #sound-dai-cells = <0>; -+ compatible = "linux,spdif-dit"; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vddcpu>; -+}; -+ -+&dma0 { -+ status = "okay"; -+}; -+ -+&dma1 { -+ status = "okay"; -+}; -+ -+&dma2 { -+ status = "okay"; -+}; -+ -+&flx0 { -+ atmel,flexcom-mode = ; -+ status = "disabled"; -+ -+ uart0: serial@200 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flx0_default>; -+ status = "disabled"; -+ }; -+}; -+ -+&flx1 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ i2c1: i2c@600 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1_default>; -+ i2c-analog-filter; -+ i2c-digital-filter; -+ i2c-digital-filter-width-ns = <35>; -+ status = "okay"; -+ -+ mcp16502@5b { -+ compatible = "microchip,mcp16502"; -+ reg = <0x5b>; -+ status = "okay"; -+ -+ regulators { -+ vdd_3v3: VDD_IO { -+ regulator-name = "VDD_IO"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <3700000>; -+ regulator-initial-mode = <2>; -+ regulator-allowed-modes = <2>, <4>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-mode = <4>; -+ }; -+ }; -+ -+ vddioddr: VDD_DDR { -+ regulator-name = "VDD_DDR"; -+ regulator-min-microvolt = <1300000>; -+ regulator-max-microvolt = <1450000>; -+ regulator-initial-mode = <2>; -+ regulator-allowed-modes = <2>, <4>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ }; -+ -+ vddcore: VDD_CORE { -+ regulator-name = "VDD_CORE"; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1850000>; -+ regulator-initial-mode = <2>; -+ regulator-allowed-modes = <2>, <4>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-mode = <4>; -+ }; -+ }; -+ -+ vddcpu: VDD_OTHER { -+ regulator-name = "VDD_OTHER"; -+ regulator-min-microvolt = <1125000>; -+ regulator-max-microvolt = <1850000>; -+ regulator-initial-mode = <2>; -+ regulator-allowed-modes = <2>, <4>; -+ regulator-ramp-delay = <3125>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ regulator-mode = <4>; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-mode = <4>; -+ }; -+ }; -+ -+ vldo1: LDO1 { -+ regulator-name = "LDO1"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <3700000>; -+ regulator-always-on; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vldo2: LDO2 { -+ regulator-name = "LDO2"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <3700000>; -+ -+ regulator-state-standby { -+ regulator-on-in-suspend; -+ }; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&flx3 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ uart3: serial@200 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flx3_default>; -+ status = "okay"; -+ }; -+}; -+ -+&flx4 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ uart4: serial@200 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flx4_default>; -+ status = "okay"; -+ }; -+}; -+ -+&flx7 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ uart7: serial@200 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flx7_default>; -+ status = "okay"; -+ }; -+}; -+ -+&flx8 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ i2c8: i2c@600 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c8_default>; -+ i2c-analog-filter; -+ i2c-digital-filter; -+ i2c-digital-filter-width-ns = <35>; -+ status = "okay"; -+ }; -+}; -+ -+&flx9 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ i2c9: i2c@600 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c9_default>; -+ i2c-analog-filter; -+ i2c-digital-filter; -+ i2c-digital-filter-width-ns = <35>; -+ status = "okay"; -+ }; -+}; -+ -+&flx11 { -+ atmel,flexcom-mode = ; -+ status = "okay"; -+ -+ spi11: spi@400 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; -+ status = "okay"; -+ }; -+}; -+ -+&gmac0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; -+ phy-mode = "rgmii-id"; -+ status = "okay"; -+ -+ ethernet-phy@7 { -+ reg = <0x7>; -+ interrupt-parent = <&pioA>; -+ interrupts = ; -+ }; -+}; -+ -+&gmac1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>; -+ phy-mode = "rmii"; -+ status = "okay"; -+ -+ ethernet-phy@0 { -+ reg = <0x0>; -+ interrupt-parent = <&pioA>; -+ interrupts = ; -+ }; -+}; -+ -+&i2s0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2s0_default>; -+}; -+ -+&pioA { -+ pinctrl_flx0_default: flx0_default { -+ pinmux = , -+ , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_flx3_default: flx3_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_flx4_default: flx4_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_flx7_default: flx7_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac0_default: gmac0_default { -+ pinmux = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac0_txck_default: gmac0_txck_default { -+ pinmux = ; -+ bias-pull-up; -+ }; -+ -+ pinctrl_gmac0_phy_irq: gmac0_phy_irq { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac1_default: gmac1_default { -+ pinmux = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac1_phy_irq: gmac1_phy_irq { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_i2c1_default: i2c1_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_i2c8_default: i2c8_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_i2c9_default: i2c9_default { -+ pinmux = , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_i2s0_default: i2s0_default { -+ pinmux = , -+ , -+ , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_key_gpio_default: key_gpio_default { -+ pinmux = ; -+ bias-pull-up; -+ }; -+ -+ pinctrl_led_gpio_default: led_gpio_default { -+ pinmux = , -+ , -+ ; -+ bias-pull-up; -+ }; -+ -+ pinctrl_mikrobus1_an_default: mikrobus1_an_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus2_an_default: mikrobus2_an_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_mikrobus1_spi: mikrobus1_spi { -+ pinmux = , -+ , -+ ; -+ bias-disable; -+ }; -+ -+ pinctrl_sdmmc0_default: sdmmc0_default { -+ cmd_data { -+ pinmux = , -+ , -+ , -+ , -+ , -+ , -+ , -+ , -+ ; -+ bias-pull-up; -+ }; -+ -+ ck_cd_rstn_vddsel { -+ pinmux = , -+ , -+ ; -+ bias-pull-up; -+ }; -+ }; -+ -+ pinctrl_sdmmc1_default: sdmmc1_default { -+ cmd_data { -+ pinmux = , -+ , -+ , -+ , -+ ; -+ bias-pull-up; -+ }; -+ -+ ck_cd_rstn_vddsel { -+ pinmux = , -+ , -+ , -+ ; -+ bias-pull-up; -+ }; -+ }; -+ -+ pinctrl_sdmmc2_default: sdmmc2_default { -+ cmd_data { -+ pinmux = , -+ , -+ , -+ , -+ ; -+ bias-pull-up; -+ }; -+ -+ ck { -+ pinmux = ; -+ bias-pull-up; -+ }; -+ }; -+ -+ pinctrl_spdifrx_default: spdifrx_default { -+ pinmux = ; -+ bias-disable; -+ }; -+ -+ pinctrl_spdiftx_default: spdiftx_default { -+ pinmux = ; -+ bias-disable; -+ }; -+}; -+ -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>; -+ status = "disabled"; /* Conflict with leds. */ -+}; -+ -+&rtt { -+ atmel,rtt-rtc-time-reg = <&gpbr 0x0>; -+}; -+ -+&sdmmc0 { -+ bus-width = <8>; -+ non-removable; -+ no-1-8-v; -+ sdhci-caps-mask = <0x0 0x00200000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sdmmc0_default>; -+ status = "okay"; -+}; -+ -+&sdmmc1 { -+ bus-width = <4>; -+ no-1-8-v; -+ sdhci-caps-mask = <0x0 0x00200000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sdmmc1_default>; -+ status = "okay"; -+}; -+ -+&sdmmc2 { -+ bus-width = <4>; -+ no-1-8-v; -+ sdhci-caps-mask = <0x0 0x00200000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_sdmmc2_default>; -+}; -+ -+&spdifrx { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdifrx_default>; -+ status = "okay"; -+}; -+ -+&spdiftx { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdiftx_default>; -+ status = "okay"; -+}; -+ -+&trng { -+ status = "okay"; -+}; -+ -+&vddout25 { -+ vin-supply = <&vdd_3v3>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/sama7g5-pinfunc.h -@@ -0,0 +1,923 @@ -+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -+#define PINMUX_PIN(no, func, ioset) \ -+(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) -+ -+#define PIN_PA0 0 -+#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) -+#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) -+#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1) -+#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1) -+#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2) -+#define PIN_PA1 1 -+#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) -+#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) -+#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1) -+#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1) -+#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1) -+#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3) -+#define PIN_PA2 2 -+#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) -+#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) -+#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1) -+#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1) -+#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1) -+#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3) -+#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3) -+#define PIN_PA3 3 -+#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) -+#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) -+#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1) -+#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1) -+#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1) -+#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3) -+#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3) -+#define PIN_PA4 4 -+#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) -+#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) -+#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1) -+#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1) -+#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1) -+#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3) -+#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3) -+#define PIN_PA5 5 -+#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) -+#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1) -+#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1) -+#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1) -+#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1) -+#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3) -+#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3) -+#define PIN_PA6 6 -+#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) -+#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1) -+#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1) -+#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1) -+#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1) -+#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3) -+#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3) -+#define PIN_PA7 7 -+#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) -+#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1) -+#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1) -+#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1) -+#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1) -+#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3) -+#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3) -+#define PIN_PA8 8 -+#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) -+#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1) -+#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1) -+#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1) -+#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1) -+#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3) -+#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3) -+#define PIN_PA9 9 -+#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) -+#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1) -+#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1) -+#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1) -+#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1) -+#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1) -+#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3) -+#define PIN_PA10 10 -+#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) -+#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1) -+#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1) -+#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1) -+#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1) -+#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1) -+#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3) -+#define PIN_PA11 11 -+#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) -+#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) -+#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1) -+#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1) -+#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1) -+#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3) -+#define PIN_PA12 12 -+#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) -+#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) -+#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1) -+#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1) -+#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3) -+#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3) -+#define PIN_PA13 13 -+#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) -+#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1) -+#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1) -+#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1) -+#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3) -+#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3) -+#define PIN_PA14 14 -+#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) -+#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1) -+#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1) -+#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1) -+#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3) -+#define PIN_PA15 15 -+#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) -+#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1) -+#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1) -+#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1) -+#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1) -+#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1) -+#define PIN_PA16 16 -+#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) -+#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1) -+#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1) -+#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1) -+#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1) -+#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1) -+#define PIN_PA17 17 -+#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) -+#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1) -+#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1) -+#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1) -+#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1) -+#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1) -+#define PIN_PA18 18 -+#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) -+#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1) -+#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1) -+#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1) -+#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1) -+#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1) -+#define PIN_PA19 19 -+#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) -+#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1) -+#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1) -+#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1) -+#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1) -+#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1) -+#define PIN_PA20 20 -+#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) -+#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1) -+#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1) -+#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1) -+#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1) -+#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1) -+#define PIN_PA21 21 -+#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) -+#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1) -+#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1) -+#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1) -+#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1) -+#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1) -+#define PIN_PA22 22 -+#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) -+#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1) -+#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1) -+#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1) -+#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1) -+#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1) -+#define PIN_PA23 23 -+#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) -+#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1) -+#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1) -+#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1) -+#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1) -+#define PIN_PA24 24 -+#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) -+#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1) -+#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1) -+#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1) -+#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1) -+#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1) -+#define PIN_PA25 25 -+#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) -+#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1) -+#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1) -+#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1) -+#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1) -+#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1) -+#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3) -+#define PIN_PA26 26 -+#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) -+#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1) -+#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1) -+#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1) -+#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1) -+#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1) -+#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3) -+#define PIN_PA27 27 -+#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) -+#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1) -+#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1) -+#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1) -+#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1) -+#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1) -+#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3) -+#define PIN_PA28 28 -+#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) -+#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1) -+#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1) -+#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1) -+#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1) -+#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1) -+#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3) -+#define PIN_PA29 29 -+#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) -+#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1) -+#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1) -+#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1) -+#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1) -+#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1) -+#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3) -+#define PIN_PA30 30 -+#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) -+#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1) -+#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1) -+#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1) -+#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1) -+#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1) -+#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3) -+#define PIN_PA31 31 -+#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) -+#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1) -+#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1) -+#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1) -+#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1) -+#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1) -+#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3) -+#define PIN_PB0 32 -+#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) -+#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1) -+#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2) -+#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1) -+#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1) -+#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2) -+#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3) -+#define PIN_PB1 33 -+#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) -+#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1) -+#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2) -+#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1) -+#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1) -+#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2) -+#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3) -+#define PIN_PB2 34 -+#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) -+#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1) -+#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) -+#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) -+#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) -+#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3) -+#define PIN_PB3 35 -+#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) -+#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1) -+#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1) -+#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2) -+#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1) -+#define PIN_PB4 36 -+#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) -+#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1) -+#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1) -+#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2) -+#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1) -+#define PIN_PB5 37 -+#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) -+#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1) -+#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1) -+#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2) -+#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1) -+#define PIN_PB6 38 -+#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) -+#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1) -+#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1) -+#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2) -+#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1) -+#define PIN_PB7 39 -+#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) -+#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1) -+#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1) -+#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2) -+#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1) -+#define PIN_PB8 40 -+#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) -+#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1) -+#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1) -+#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2) -+#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1) -+#define PIN_PB9 41 -+#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) -+#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1) -+#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1) -+#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1) -+#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1) -+#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2) -+#define PIN_PB10 42 -+#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) -+#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1) -+#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1) -+#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1) -+#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1) -+#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2) -+#define PIN_PB11 43 -+#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) -+#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1) -+#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1) -+#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1) -+#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1) -+#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2) -+#define PIN_PB12 44 -+#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) -+#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1) -+#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1) -+#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1) -+#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1) -+#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2) -+#define PIN_PB13 45 -+#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) -+#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1) -+#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1) -+#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1) -+#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1) -+#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2) -+#define PIN_PB14 46 -+#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) -+#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1) -+#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1) -+#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1) -+#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2) -+#define PIN_PB15 47 -+#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) -+#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1) -+#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1) -+#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1) -+#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2) -+#define PIN_PB16 48 -+#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) -+#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1) -+#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1) -+#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1) -+#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1) -+#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2) -+#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2) -+#define PIN_PB17 49 -+#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) -+#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1) -+#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1) -+#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1) -+#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1) -+#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2) -+#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2) -+#define PIN_PB18 50 -+#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) -+#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1) -+#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1) -+#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1) -+#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1) -+#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2) -+#define PIN_PB19 51 -+#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) -+#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1) -+#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1) -+#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1) -+#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1) -+#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2) -+#define PIN_PB20 52 -+#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) -+#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1) -+#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1) -+#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1) -+#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2) -+#define PIN_PB21 53 -+#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) -+#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1) -+#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1) -+#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1) -+#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1) -+#define PIN_PB22 54 -+#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) -+#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1) -+#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1) -+#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1) -+#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1) -+#define PIN_PB23 55 -+#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) -+#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1) -+#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1) -+#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1) -+#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1) -+#define PIN_PB24 56 -+#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) -+#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1) -+#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1) -+#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1) -+#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1) -+#define PIN_PB25 57 -+#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) -+#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1) -+#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1) -+#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1) -+#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1) -+#define PIN_PB26 58 -+#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) -+#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1) -+#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1) -+#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1) -+#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1) -+#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1) -+#define PIN_PB27 59 -+#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) -+#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1) -+#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1) -+#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1) -+#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1) -+#define PIN_PB28 60 -+#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) -+#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1) -+#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2) -+#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1) -+#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4) -+#define PIN_PB29 61 -+#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) -+#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1) -+#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2) -+#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2) -+#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2) -+#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1) -+#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4) -+#define PIN_PB30 62 -+#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) -+#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1) -+#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2) -+#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2) -+#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1) -+#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1) -+#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4) -+#define PIN_PB31 63 -+#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) -+#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1) -+#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2) -+#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2) -+#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1) -+#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1) -+#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4) -+#define PIN_PC0 64 -+#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) -+#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1) -+#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2) -+#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1) -+#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1) -+#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4) -+#define PIN_PC1 65 -+#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) -+#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1) -+#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2) -+#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1) -+#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1) -+#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4) -+#define PIN_PC2 66 -+#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) -+#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1) -+#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2) -+#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1) -+#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1) -+#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4) -+#define PIN_PC3 67 -+#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) -+#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1) -+#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2) -+#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1) -+#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1) -+#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4) -+#define PIN_PC4 68 -+#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) -+#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1) -+#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2) -+#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2) -+#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1) -+#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1) -+#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4) -+#define PIN_PC5 69 -+#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) -+#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1) -+#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2) -+#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2) -+#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1) -+#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1) -+#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4) -+#define PIN_PC6 70 -+#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) -+#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2) -+#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2) -+#define PIN_PC7 71 -+#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) -+#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1) -+#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2) -+#define PIN_PC8 72 -+#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) -+#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) -+#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2) -+#define PIN_PC9 73 -+#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) -+#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1) -+#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2) -+#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4) -+#define PIN_PC10 74 -+#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) -+#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1) -+#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2) -+#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4) -+#define PIN_PC11 75 -+#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) -+#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1) -+#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2) -+#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4) -+#define PIN_PC12 76 -+#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) -+#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1) -+#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2) -+#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4) -+#define PIN_PC13 77 -+#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) -+#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1) -+#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2) -+#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4) -+#define PIN_PC14 78 -+#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) -+#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1) -+#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2) -+#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4) -+#define PIN_PC15 79 -+#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) -+#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1) -+#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2) -+#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4) -+#define PIN_PC16 80 -+#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) -+#define PIN_PC16__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1) -+#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2) -+#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4) -+#define PIN_PC17 81 -+#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) -+#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1) -+#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3) -+#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4) -+#define PIN_PC18 82 -+#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) -+#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) -+#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2) -+#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4) -+#define PIN_PC19 83 -+#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) -+#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1) -+#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2) -+#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4) -+#define PIN_PC20 84 -+#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) -+#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1) -+#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2) -+#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4) -+#define PIN_PC21 85 -+#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) -+#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1) -+#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2) -+#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2) -+#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5) -+#define PIN_PC22 86 -+#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) -+#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1) -+#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2) -+#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2) -+#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5) -+#define PIN_PC23 87 -+#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) -+#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1) -+#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3) -+#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2) -+#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5) -+#define PIN_PC24 88 -+#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) -+#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3) -+#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3) -+#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2) -+#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5) -+#define PIN_PC25 89 -+#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) -+#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1) -+#define PIN_PC26 90 -+#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) -+#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1) -+#define PIN_PC27 91 -+#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) -+#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1) -+#define PIN_PC28 92 -+#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) -+#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1) -+#define PIN_PC29 93 -+#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) -+#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1) -+#define PIN_PC30 94 -+#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) -+#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2) -+#define PIN_PC31 95 -+#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) -+#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2) -+#define PIN_PD0 96 -+#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) -+#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2) -+#define PIN_PD1 97 -+#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) -+#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2) -+#define PIN_PD2 98 -+#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) -+#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1) -+#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2) -+#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1) -+#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2) -+#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2) -+#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5) -+#define PIN_PD3 99 -+#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) -+#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1) -+#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2) -+#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1) -+#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2) -+#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2) -+#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5) -+#define PIN_PD4 100 -+#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) -+#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1) -+#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2) -+#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1) -+#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2) -+#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2) -+#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5) -+#define PIN_PD5 101 -+#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) -+#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1) -+#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2) -+#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1) -+#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2) -+#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2) -+#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5) -+#define PIN_PD6 102 -+#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) -+#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1) -+#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2) -+#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3) -+#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2) -+#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2) -+#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5) -+#define PIN_PD7 103 -+#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) -+#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1) -+#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2) -+#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2) -+#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2) -+#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2) -+#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5) -+#define PIN_PD8 104 -+#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) -+#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) -+#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) -+#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) -+#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) -+#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) -+#define PIN_PD9 105 -+#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) -+#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1) -+#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2) -+#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2) -+#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2) -+#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5) -+#define PIN_PD10 106 -+#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) -+#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1) -+#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2) -+#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2) -+#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2) -+#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2) -+#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3) -+#define PIN_PD11 107 -+#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) -+#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1) -+#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2) -+#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2) -+#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2) -+#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2) -+#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3) -+#define PIN_PD12 108 -+#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) -+#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2) -+#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2) -+#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2) -+#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2) -+#define PIN_PD13 109 -+#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) -+#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2) -+#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2) -+#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4) -+#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2) -+#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2) -+#define PIN_PD14 110 -+#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) -+#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2) -+#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2) -+#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4) -+#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2) -+#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2) -+#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5) -+#define PIN_PD15 111 -+#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) -+#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2) -+#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2) -+#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4) -+#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2) -+#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2) -+#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5) -+#define PIN_PD16 112 -+#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) -+#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2) -+#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2) -+#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4) -+#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2) -+#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2) -+#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5) -+#define PIN_PD17 113 -+#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) -+#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2) -+#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2) -+#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4) -+#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2) -+#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2) -+#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5) -+#define PIN_PD18 114 -+#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) -+#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2) -+#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2) -+#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4) -+#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2) -+#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2) -+#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5) -+#define PIN_PD19 115 -+#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) -+#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2) -+#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2) -+#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4) -+#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2) -+#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2) -+#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5) -+#define PIN_PD20 116 -+#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) -+#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) -+#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) -+#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) -+#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) -+#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) -+#define PIN_PD21 117 -+#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) -+#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3) -+#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2) -+#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2) -+#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5) -+#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1) -+#define PIN_PD22 118 -+#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) -+#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2) -+#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4) -+#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2) -+#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2) -+#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1) -+#define PIN_PD23 119 -+#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) -+#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2) -+#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4) -+#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2) -+#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2) -+#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2) -+#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1) -+#define PIN_PD24 120 -+#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) -+#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2) -+#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4) -+#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2) -+#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2) -+#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1) -+#define PIN_PD25 121 -+#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) -+#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2) -+#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2) -+#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4) -+#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2) -+#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2) -+#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1) -+#define PIN_PD26 122 -+#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) -+#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2) -+#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2) -+#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3) -+#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2) -+#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2) -+#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1) -+#define PIN_PD27 123 -+#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) -+#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2) -+#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2) -+#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3) -+#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2) -+#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2) -+#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1) -+#define PIN_PD28 124 -+#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) -+#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2) -+#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2) -+#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3) -+#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2) -+#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2) -+#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5) -+#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1) -+#define PIN_PD29 125 -+#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) -+#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2) -+#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2) -+#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3) -+#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2) -+#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2) -+#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5) -+#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1) -+#define PIN_PD30 126 -+#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) -+#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2) -+#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2) -+#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3) -+#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2) -+#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2) -+#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5) -+#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1) -+#define PIN_PD31 127 -+#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) -+#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2) -+#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2) -+#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3) -+#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2) -+#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2) -+#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5) -+#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1) -+#define PIN_PE0 128 -+#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) -+#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2) -+#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2) -+#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3) -+#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2) -+#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2) -+#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5) -+#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1) -+#define PIN_PE1 129 -+#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) -+#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2) -+#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2) -+#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3) -+#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2) -+#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2) -+#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5) -+#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1) -+#define PIN_PE2 130 -+#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) -+#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5) -+#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2) -+#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3) -+#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2) -+#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2) -+#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1) -+#define PIN_PE3 131 -+#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) -+#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5) -+#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4) -+#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3) -+#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2) -+#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2) -+#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1) -+#define PIN_PE4 132 -+#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) -+#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5) -+#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4) -+#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3) -+#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2) -+#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2) -+#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1) -+#define PIN_PE5 133 -+#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) -+#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5) -+#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4) -+#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3) -+#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2) -+#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2) -+#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1) -+#define PIN_PE6 134 -+#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) -+#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5) -+#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4) -+#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3) -+#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2) -+#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2) -+#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1) -+#define PIN_PE7 135 -+#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) -+#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5) -+#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4) -+#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) -+#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) -+#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) ---- /dev/null -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -0,0 +1,528 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC -+ * -+ * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries -+ * -+ * Author: Eugen Hristev -+ * Author: Claudiu Beznea -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ model = "Microchip SAMA7G5 family SoC"; -+ compatible = "microchip,sama7g5"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ interrupt-parent = <&gic>; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a7"; -+ reg = <0x0>; -+ }; -+ }; -+ -+ clocks { -+ slow_xtal: slow_xtal { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ }; -+ -+ main_xtal: main_xtal { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ }; -+ -+ usb_clk: usb_clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <48000000>; -+ }; -+ }; -+ -+ vddout25: fixed-regulator-vddout25 { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VDDOUT25"; -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; -+ regulator-boot-on; -+ status = "disabled"; -+ }; -+ -+ ns_sram: sram@100000 { -+ compatible = "mmio-sram"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x100000 0x20000>; -+ ranges; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ secumod: secumod@e0004000 { -+ compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; -+ reg = <0xe0004000 0x4000>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ sfrbu: sfr@e0008000 { -+ compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; -+ reg = <0xe0008000 0x20>; -+ }; -+ -+ pioA: pinctrl@e0014000 { -+ compatible = "microchip,sama7g5-pinctrl"; -+ reg = <0xe0014000 0x800>; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; -+ }; -+ -+ pmc: pmc@e0018000 { -+ compatible = "microchip,sama7g5-pmc", "syscon"; -+ reg = <0xe0018000 0x200>; -+ interrupts = ; -+ #clock-cells = <2>; -+ clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; -+ clock-names = "td_slck", "md_slck", "main_xtal"; -+ }; -+ -+ rtt: rtt@e001d020 { -+ compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; -+ reg = <0xe001d020 0x30>; -+ interrupts = ; -+ clocks = <&clk32k 0>; -+ }; -+ -+ clk32k: clock-controller@e001d050 { -+ compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; -+ reg = <0xe001d050 0x4>; -+ clocks = <&slow_xtal>; -+ #clock-cells = <1>; -+ }; -+ -+ gpbr: gpbr@e001d060 { -+ compatible = "microchip,sama7g5-gpbr", "syscon"; -+ reg = <0xe001d060 0x48>; -+ }; -+ -+ ps_wdt: watchdog@e001d180 { -+ compatible = "microchip,sama7g5-wdt"; -+ reg = <0xe001d180 0x24>; -+ interrupts = ; -+ clocks = <&clk32k 0>; -+ }; -+ -+ sdmmc0: mmc@e1204000 { -+ compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; -+ reg = <0xe1204000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; -+ clock-names = "hclock", "multclk"; -+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; -+ assigned-clocks = <&pmc PMC_TYPE_GCK 80>; -+ assigned-clock-rates = <200000000>; -+ microchip,sdcal-inverted; -+ status = "disabled"; -+ }; -+ -+ sdmmc1: mmc@e1208000 { -+ compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; -+ reg = <0xe1208000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; -+ clock-names = "hclock", "multclk"; -+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; -+ assigned-clocks = <&pmc PMC_TYPE_GCK 81>; -+ assigned-clock-rates = <200000000>; -+ microchip,sdcal-inverted; -+ status = "disabled"; -+ }; -+ -+ sdmmc2: mmc@e120c000 { -+ compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; -+ reg = <0xe120c000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; -+ clock-names = "hclock", "multclk"; -+ assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; -+ assigned-clocks = <&pmc PMC_TYPE_GCK 82>; -+ assigned-clock-rates = <200000000>; -+ microchip,sdcal-inverted; -+ status = "disabled"; -+ }; -+ -+ pwm: pwm@e1604000 { -+ compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; -+ reg = <0xe1604000 0x4000>; -+ interrupts = ; -+ #pwm-cells = <3>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; -+ status = "disabled"; -+ }; -+ -+ spdifrx: spdifrx@e1614000 { -+ #sound-dai-cells = <0>; -+ compatible = "microchip,sama7g5-spdifrx"; -+ reg = <0xe1614000 0x4000>; -+ interrupts = ; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; -+ dma-names = "rx"; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; -+ clock-names = "pclk", "gclk"; -+ status = "disabled"; -+ }; -+ -+ spdiftx: spdiftx@e1618000 { -+ #sound-dai-cells = <0>; -+ compatible = "microchip,sama7g5-spdiftx"; -+ reg = <0xe1618000 0x4000>; -+ interrupts = ; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; -+ dma-names = "tx"; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; -+ clock-names = "pclk", "gclk"; -+ }; -+ -+ i2s0: i2s@e161c000 { -+ compatible = "microchip,sama7g5-i2smcc"; -+ #sound-dai-cells = <0>; -+ reg = <0xe161c000 0x4000>; -+ interrupts = ; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; -+ dma-names = "tx", "rx"; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; -+ clock-names = "pclk", "gclk"; -+ status = "disabled"; -+ }; -+ -+ i2s1: i2s@e1620000 { -+ compatible = "microchip,sama7g5-i2smcc"; -+ #sound-dai-cells = <0>; -+ reg = <0xe1620000 0x4000>; -+ interrupts = ; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; -+ dma-names = "tx", "rx"; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; -+ clock-names = "pclk", "gclk"; -+ status = "disabled"; -+ }; -+ -+ pit64b0: timer@e1800000 { -+ compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; -+ reg = <0xe1800000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; -+ clock-names = "pclk", "gclk"; -+ }; -+ -+ pit64b1: timer@e1804000 { -+ compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; -+ reg = <0xe1804000 0x4000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; -+ clock-names = "pclk", "gclk"; -+ }; -+ -+ flx0: flexcom@e1818000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe1818000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe1818000 0x800>; -+ status = "disabled"; -+ -+ uart0: serial@200 { -+ compatible = "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; -+ clock-names = "usart"; -+ dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, -+ <&dma1 AT91_XDMAC_DT_PERID(5)>; -+ dma-names = "tx", "rx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx1: flexcom@e181c000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe181c000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe181c000 0x800>; -+ status = "disabled"; -+ -+ i2c1: i2c@600 { -+ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; -+ atmel,fifo-size = <32>; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, -+ <&dma0 AT91_XDMAC_DT_PERID(8)>; -+ dma-names = "rx", "tx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx3: flexcom@e1824000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe1824000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe1824000 0x800>; -+ status = "disabled"; -+ -+ uart3: serial@200 { -+ compatible = "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; -+ clock-names = "usart"; -+ dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, -+ <&dma1 AT91_XDMAC_DT_PERID(11)>; -+ dma-names = "tx", "rx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ trng: rng@e2010000 { -+ compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; -+ reg = <0xe2010000 0x100>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; -+ status = "disabled"; -+ }; -+ -+ flx4: flexcom@e2018000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe2018000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe2018000 0x800>; -+ status = "disabled"; -+ -+ uart4: serial@200 { -+ compatible = "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; -+ clock-names = "usart"; -+ dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, -+ <&dma1 AT91_XDMAC_DT_PERID(13)>; -+ dma-names = "tx", "rx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ atmel,fifo-size = <16>; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx7: flexcom@e2024000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe2024000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe2024000 0x800>; -+ status = "disabled"; -+ -+ uart7: serial@200 { -+ compatible = "atmel,at91sam9260-usart"; -+ reg = <0x200 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; -+ clock-names = "usart"; -+ dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, -+ <&dma1 AT91_XDMAC_DT_PERID(19)>; -+ dma-names = "tx", "rx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ atmel,fifo-size = <16>; -+ status = "disabled"; -+ }; -+ }; -+ -+ gmac0: ethernet@e2800000 { -+ compatible = "microchip,sama7g5-gem"; -+ reg = <0xe2800000 0x1000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; -+ clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; -+ assigned-clocks = <&pmc PMC_TYPE_GCK 51>; -+ assigned-clock-rates = <125000000>; -+ status = "disabled"; -+ }; -+ -+ gmac1: ethernet@e2804000 { -+ compatible = "microchip,sama7g5-emac"; -+ reg = <0xe2804000 0x1000>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; -+ clock-names = "pclk", "hclk"; -+ status = "disabled"; -+ }; -+ -+ dma0: dma-controller@e2808000 { -+ compatible = "microchip,sama7g5-dma"; -+ reg = <0xe2808000 0x1000>; -+ interrupts = ; -+ #dma-cells = <1>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; -+ clock-names = "dma_clk"; -+ status = "disabled"; -+ }; -+ -+ dma1: dma-controller@e280c000 { -+ compatible = "microchip,sama7g5-dma"; -+ reg = <0xe280c000 0x1000>; -+ interrupts = ; -+ #dma-cells = <1>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; -+ clock-names = "dma_clk"; -+ status = "disabled"; -+ }; -+ -+ /* Place dma2 here despite it's address */ -+ dma2: dma-controller@e1200000 { -+ compatible = "microchip,sama7g5-dma"; -+ reg = <0xe1200000 0x1000>; -+ interrupts = ; -+ #dma-cells = <1>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; -+ clock-names = "dma_clk"; -+ dma-requests = <0>; -+ status = "disabled"; -+ }; -+ -+ flx8: flexcom@e2818000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe2818000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe2818000 0x800>; -+ status = "disabled"; -+ -+ i2c8: i2c@600 { -+ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; -+ atmel,fifo-size = <32>; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, -+ <&dma0 AT91_XDMAC_DT_PERID(22)>; -+ dma-names = "rx", "tx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx9: flexcom@e281c000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe281c000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe281c000 0x800>; -+ status = "disabled"; -+ -+ i2c9: i2c@600 { -+ compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; -+ reg = <0x600 0x200>; -+ interrupts = ; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; -+ atmel,fifo-size = <32>; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, -+ <&dma0 AT91_XDMAC_DT_PERID(24)>; -+ dma-names = "rx", "tx"; -+ atmel,use-dma-rx; -+ atmel,use-dma-tx; -+ status = "disabled"; -+ }; -+ }; -+ -+ flx11: flexcom@e2824000 { -+ compatible = "atmel,sama5d2-flexcom"; -+ reg = <0xe2824000 0x200>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0xe2824000 0x800>; -+ status = "disabled"; -+ -+ spi11: spi@400 { -+ compatible = "atmel,at91rm9200-spi"; -+ reg = <0x400 0x200>; -+ interrupts = ; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; -+ clock-names = "spi_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ atmel,fifo-size = <32>; -+ dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, -+ <&dma0 AT91_XDMAC_DT_PERID(28)>; -+ dma-names = "rx", "tx"; -+ status = "disabled"; -+ }; -+ }; -+ -+ gic: interrupt-controller@e8c11000 { -+ compatible = "arm,cortex-a7-gic"; -+ #interrupt-cells = <3>; -+ #address-cells = <0>; -+ interrupt-controller; -+ interrupt-parent; -+ reg = <0xe8c11000 0x1000>, -+ <0xe8c12000 0x2000>; -+ }; -+ }; -+}; diff --git a/target/linux/at91/patches-5.10/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch b/target/linux/at91/patches-5.10/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch deleted file mode 100644 index 68bf447a03..0000000000 --- a/target/linux/at91/patches-5.10/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 76dbc56ad65350d78d12bd9b36b00c36fb27addf Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 23 Aug 2021 16:19:12 +0300 -Subject: [PATCH 223/247] ARM: at91: pm: do not panic if ram controllers are - not enabled - -In case PM is enabled but there is no RAM controller information -in DT the code will panic. Avoid such scenarios by not initializing -platform specific PM code in case RAM controller is not provided -via DT. - -Reported-by: Eugen Hristev -Fixes: 827de1f123ba0 ("ARM: at91: remove at91_dt_initialize and machine init_early()") -Fixes: 892e1f4a3ae58 ("ARM: at91: pm: add sama7g5 ddr phy controller") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210823131915.23857-2-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 22 ++++++++++++++++------ - 1 file changed, 16 insertions(+), 6 deletions(-) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -589,7 +589,7 @@ static const struct of_device_id ramc_ph - { /* Sentinel. */ }, - }; - --static __init void at91_dt_ramc(bool phy_mandatory) -+static __init int at91_dt_ramc(bool phy_mandatory) - { - struct device_node *np; - const struct of_device_id *of_id; -@@ -625,12 +625,18 @@ static __init void at91_dt_ramc(bool phy - /* Lookup for DDR PHY node, if any. */ - for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) { - soc_pm.data.ramc_phy = of_iomap(np, 0); -- if (!soc_pm.data.ramc_phy) -- panic(pr_fmt("unable to map ramc phy cpu registers\n")); -+ if (!soc_pm.data.ramc_phy) { -+ pr_err("unable to map ramc phy cpu registers\n"); -+ ret = -ENOMEM; -+ goto unmap_ramc; -+ } - } - -- if (phy_mandatory && !soc_pm.data.ramc_phy) -- panic(pr_fmt("DDR PHY is mandatory!\n")); -+ if (phy_mandatory && !soc_pm.data.ramc_phy) { -+ pr_err("DDR PHY is mandatory!\n"); -+ ret = -ENODEV; -+ goto unmap_ramc; -+ } - - if (!standby) { - pr_warn("ramc no standby function available\n"); -@@ -1163,13 +1169,17 @@ void __init sama7_pm_init(void) - [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) | - AT91_PM_IOMAP(SHDWC), - }; -+ int ret; - - if (!IS_ENABLED(CONFIG_SOC_SAMA7)) - return; - - at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); - -- at91_dt_ramc(true); -+ ret = at91_dt_ramc(true); -+ if (ret) -+ return; -+ - at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); - at91_pm_init(NULL); - diff --git a/target/linux/at91/patches-5.10/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch b/target/linux/at91/patches-5.10/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch deleted file mode 100644 index 11c0f2c1e3..0000000000 --- a/target/linux/at91/patches-5.10/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch +++ /dev/null @@ -1,36 +0,0 @@ -From cf96a88e44f1fde9f1a30ab335329ff9e895e6f8 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 23 Aug 2021 16:19:13 +0300 -Subject: [PATCH 224/247] ARM: dts: at91: sama7g5: add ram controllers - -Add RAM and RAMC PHY controllers. These are necessary for platform -specific power management code. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210823131915.23857-3-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/arch/arm/boot/dts/sama7g5.dtsi -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -515,6 +515,18 @@ - }; - }; - -+ uddrc: uddrc@e3800000 { -+ compatible = "microchip,sama7g5-uddrc"; -+ reg = <0xe3800000 0x4000>; -+ status = "okay"; -+ }; -+ -+ ddr3phy: ddr3phy@e3804000 { -+ compatible = "microchip,sama7g5-ddr3phy"; -+ reg = <0xe3804000 0x1000>; -+ status = "okay"; -+ }; -+ - gic: interrupt-controller@e8c11000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; diff --git a/target/linux/at91/patches-5.10/225-ARM-dts-at91-sama7g5-add-securam-node.patch b/target/linux/at91/patches-5.10/225-ARM-dts-at91-sama7g5-add-securam-node.patch deleted file mode 100644 index f264f5c129..0000000000 --- a/target/linux/at91/patches-5.10/225-ARM-dts-at91-sama7g5-add-securam-node.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 1da1aae0b207d6a5ac7c3070b8d7c6ef61a32d71 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 23 Aug 2021 16:19:14 +0300 -Subject: [PATCH 225/247] ARM: dts: at91: sama7g5: add securam node - -Add securam node. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210823131915.23857-4-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/arch/arm/boot/dts/sama7g5.dtsi -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -75,6 +75,17 @@ - #size-cells = <1>; - ranges; - -+ securam: securam@e0000000 { -+ compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; -+ reg = <0xe0000000 0x4000>; -+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0xe0000000 0x4000>; -+ no-memory-wc; -+ status = "okay"; -+ }; -+ - secumod: secumod@e0004000 { - compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; - reg = <0xe0004000 0x4000>; diff --git a/target/linux/at91/patches-5.10/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch b/target/linux/at91/patches-5.10/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch deleted file mode 100644 index da941918a1..0000000000 --- a/target/linux/at91/patches-5.10/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 372fa27d07f66f97a4bf45621c1b840ce8417a85 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 23 Aug 2021 16:19:15 +0300 -Subject: [PATCH 226/247] ARM: dts: at91: sama7g5: add shdwc node - -Add shutdown controller node and enable it. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210823131915.23857-5-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/at91-sama7g5ek.dts | 9 +++++++++ - arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++ - 2 files changed, 20 insertions(+) - ---- a/arch/arm/boot/dts/at91-sama7g5ek.dts -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -634,6 +634,15 @@ - pinctrl-0 = <&pinctrl_sdmmc2_default>; - }; - -+&shdwc { -+ atmel,shdwc-debouncer = <976>; -+ status = "okay"; -+ -+ input@0 { -+ reg = <0>; -+ }; -+}; -+ - &spdifrx { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdifrx_default>; ---- a/arch/arm/boot/dts/sama7g5.dtsi -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -122,6 +122,17 @@ - clock-names = "td_slck", "md_slck", "main_xtal"; - }; - -+ shdwc: shdwc@e001d010 { -+ compatible = "microchip,sama7g5-shdwc", "syscon"; -+ reg = <0xe001d010 0x10>; -+ clocks = <&clk32k 0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ atmel,wakeup-rtc-timer; -+ atmel,wakeup-rtt-timer; -+ status = "disabled"; -+ }; -+ - rtt: rtt@e001d020 { - compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; - reg = <0xe001d020 0x30>; diff --git a/target/linux/at91/patches-5.10/227-ARM-dts-at91-sama7g5-add-chipid.patch b/target/linux/at91/patches-5.10/227-ARM-dts-at91-sama7g5-add-chipid.patch deleted file mode 100644 index 3e307e418e..0000000000 --- a/target/linux/at91/patches-5.10/227-ARM-dts-at91-sama7g5-add-chipid.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d216c1ecf978574216ece8140146c8dc0ea400e3 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 8 Sep 2021 12:43:29 +0300 -Subject: [PATCH 227/247] ARM: dts: at91: sama7g5: add chipid - -Add chipid node for sama7g5. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210908094329.182477-1-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/sama7g5.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm/boot/dts/sama7g5.dtsi -+++ b/arch/arm/boot/dts/sama7g5.dtsi -@@ -159,6 +159,11 @@ - clocks = <&clk32k 0>; - }; - -+ chipid@e0020000 { -+ compatible = "microchip,sama7g5-chipid"; -+ reg = <0xe0020000 0x8>; -+ }; -+ - sdmmc0: mmc@e1204000 { - compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; - reg = <0xe1204000 0x4000>; diff --git a/target/linux/at91/patches-5.10/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch b/target/linux/at91/patches-5.10/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch deleted file mode 100644 index 02532b4722..0000000000 --- a/target/linux/at91/patches-5.10/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 2cd84ddf0e9623c6bc723b1df368cd8b16a3a8e2 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 30 Aug 2021 13:09:27 +0300 -Subject: [PATCH 228/247] ARM: at91: pm: switch backup area to vbat in backup - mode - -Backup area is now switched to VDDIN33 at boot (with the help of -bootloader). When switching to backup mode we need to switch backup area -to VBAT as all the other power sources are cut off. The resuming from -backup mode is done with the help of bootloader, so there is no need to -do something particular in Linux to restore backup area power source. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210830100927.22711-1-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm.c | 52 +++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 52 insertions(+) - ---- a/arch/arm/mach-at91/pm.c -+++ b/arch/arm/mach-at91/pm.c -@@ -47,12 +47,26 @@ struct at91_pm_bu { - unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION]; - }; - -+/* -+ * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU -+ * @pswbu: power switch BU control registers -+ */ -+struct at91_pm_sfrbu_regs { -+ struct { -+ u32 key; -+ u32 ctrl; -+ u32 state; -+ u32 softsw; -+ } pswbu; -+}; -+ - /** - * struct at91_soc_pm - AT91 SoC power management data structure - * @config_shdwc_ws: wakeup sources configuration function for SHDWC - * @config_pmc_ws: wakeup srouces configuration function for PMC - * @ws_ids: wakup sources of_device_id array - * @data: PM data to be used on last phase of suspend -+ * @sfrbu_regs: SFRBU registers mapping - * @bu: backup unit mapped data (for backup mode) - * @memcs: memory chip select - */ -@@ -62,6 +76,7 @@ struct at91_soc_pm { - const struct of_device_id *ws_ids; - struct at91_pm_bu *bu; - struct at91_pm_data data; -+ struct at91_pm_sfrbu_regs sfrbu_regs; - void *memcs; - }; - -@@ -356,9 +371,36 @@ static int at91_suspend_finish(unsigned - return 0; - } - -+static void at91_pm_switch_ba_to_vbat(void) -+{ -+ unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu); -+ unsigned int val; -+ -+ /* Just for safety. */ -+ if (!soc_pm.data.sfrbu) -+ return; -+ -+ val = readl(soc_pm.data.sfrbu + offset); -+ -+ /* Already on VBAT. */ -+ if (!(val & soc_pm.sfrbu_regs.pswbu.state)) -+ return; -+ -+ val &= ~soc_pm.sfrbu_regs.pswbu.softsw; -+ val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl; -+ writel(val, soc_pm.data.sfrbu + offset); -+ -+ /* Wait for update. */ -+ val = readl(soc_pm.data.sfrbu + offset); -+ while (val & soc_pm.sfrbu_regs.pswbu.state) -+ val = readl(soc_pm.data.sfrbu + offset); -+} -+ - static void at91_pm_suspend(suspend_state_t state) - { - if (soc_pm.data.mode == AT91_PM_BACKUP) { -+ at91_pm_switch_ba_to_vbat(); -+ - cpu_suspend(0, at91_suspend_finish); - - /* The SRAM is lost between suspend cycles */ -@@ -1155,6 +1197,11 @@ void __init sama5d2_pm_init(void) - soc_pm.ws_ids = sama5d2_ws_ids; - soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; - soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws; -+ -+ soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); -+ soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); -+ soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); -+ soc_pm.sfrbu_regs.pswbu.state = BIT(3); - } - - void __init sama7_pm_init(void) -@@ -1185,6 +1232,11 @@ void __init sama7_pm_init(void) - - soc_pm.ws_ids = sama7g5_ws_ids; - soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; -+ -+ soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); -+ soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0); -+ soc_pm.sfrbu_regs.pswbu.softsw = BIT(1); -+ soc_pm.sfrbu_regs.pswbu.state = BIT(2); - } - - static int __init at91_pm_modes_select(char *str) diff --git a/target/linux/at91/patches-5.10/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch b/target/linux/at91/patches-5.10/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch deleted file mode 100644 index b5074b58a0..0000000000 --- a/target/linux/at91/patches-5.10/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch +++ /dev/null @@ -1,42 +0,0 @@ -From e5f87471392b344b1261d1eaf93fd44710587ea9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 30 Sep 2021 18:42:17 +0300 -Subject: [PATCH 229/247] ARM: dts: at91: sama7g5ek: add suspend voltage for - ddr3l rail - -SAMA7G5-EK board has DDR3L type of memory soldered. This needs 1.35V. The -1.35V for DDR3L rail at run-time is selected by the proper configuration -on SELV2 pin (for 1.35V it needs to be in high-z state). When suspended -the MCP16502 PMIC soldered on SAMA7G5-EK will use different sets of -configuration registers to provide proper voltages on its rail. Run-time -configuration registers could be configured differently than suspend -configuration register for MCP16502 (VSEL2 affects only run-time -configuration). In suspend states the DDR3L memory soldered on SAMA7G5-EK -switches to self-refresh. Even on self-refresh it needs to be powered by -a 1.35V rail. Thus, make sure the PMIC is configured properly when system -is suspended. - -Fixes: 7540629e2fc7 (ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210930154219.2214051-2-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/at91-sama7g5ek.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/boot/dts/at91-sama7g5ek.dts -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -196,11 +196,13 @@ - - regulator-state-standby { - regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1350000>; - regulator-mode = <4>; - }; - - regulator-state-mem { - regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1350000>; - regulator-mode = <4>; - }; - }; diff --git a/target/linux/at91/patches-5.10/230-ARM-at91-pm-group-constants-and-addresses-loading.patch b/target/linux/at91/patches-5.10/230-ARM-at91-pm-group-constants-and-addresses-loading.patch deleted file mode 100644 index e952f6c377..0000000000 --- a/target/linux/at91/patches-5.10/230-ARM-at91-pm-group-constants-and-addresses-loading.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 12330a9f6b99622e3c21ddcc720b02431b8a6e2d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 30 Sep 2021 18:42:18 +0300 -Subject: [PATCH 230/247] ARM: at91: pm: group constants and addresses loading - -Group constants and addresses loading. This commit prepares the field for -the next one. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210930154219.2214051-3-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 17 +++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -1014,6 +1014,15 @@ ENTRY(at91_pm_suspend_in_sram) - mov tmp1, #0 - mcr p15, 0, tmp1, c7, c10, 4 - -+ ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] -+ str tmp1, .mckr_offset -+ ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -+ str tmp1, .pmc_version -+ ldr tmp1, [r0, #PM_DATA_MEMCTRL] -+ str tmp1, .memtype -+ ldr tmp1, [r0, #PM_DATA_MODE] -+ str tmp1, .pm_mode -+ - ldr tmp1, [r0, #PM_DATA_PMC] - str tmp1, .pmc_base - ldr tmp1, [r0, #PM_DATA_RAMC0] -@@ -1022,14 +1031,6 @@ ENTRY(at91_pm_suspend_in_sram) - str tmp1, .sramc1_base - ldr tmp1, [r0, #PM_DATA_RAMC_PHY] - str tmp1, .sramc_phy_base -- ldr tmp1, [r0, #PM_DATA_MEMCTRL] -- str tmp1, .memtype -- ldr tmp1, [r0, #PM_DATA_MODE] -- str tmp1, .pm_mode -- ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] -- str tmp1, .mckr_offset -- ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -- str tmp1, .pmc_version - /* Both ldrne below are here to preload their address in the TLB */ - ldr tmp1, [r0, #PM_DATA_SHDWC] - str tmp1, .shdwc diff --git a/target/linux/at91/patches-5.10/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch b/target/linux/at91/patches-5.10/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch deleted file mode 100644 index bd7fb4e39e..0000000000 --- a/target/linux/at91/patches-5.10/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 6075bbc75e55258a762d618cd459dbe0dd38aff9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Thu, 30 Sep 2021 18:42:19 +0300 -Subject: [PATCH 231/247] ARM: at91: pm: preload base address of controllers in - tlb - -In suspend/resume procedure for AT91 architecture different controllers -(PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings -for power saving. Commit f0bbf17958e8 ("ARM: at91: pm: add self-refresh -support for sama7g5") introduced the access to RAMC PHY controller for -SAMA7G5. The access to this controller is done after RAMC ports are -closed, thus any TLB walk necessary for RAMC PHY virtual address will -fail. In the development branch this was not encountered. However, on -current kernel the issue is reproducible. - -To solve the issue the previous mechanism of pre-loading the TLB with -the RAMC PHY virtual address has been used. However, only the addition -of this new pre-load breaks the functionality for ARMv5 based -devices (SAM9X60). This behavior has been encountered previously -while debugging this code and using the same mechanism for pre-loading -address for different controllers (e.g. pin controller, the assumption -being that other requested translations are replaced from TLB). - -To solve this new issue the TLB flush + the extension of pre-loading -the rest of controllers to TLB (e.g. PMC, RAMC) has been added. The -rest of the controllers should have been pre-loaded previously, anyway. - -Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") -Depends-on: e42cbbe5c9a2 ("ARM: at91: pm: group constants and addresses loading") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com ---- - arch/arm/mach-at91/pm_suspend.S | 25 ++++++++++++++++++++++++- - 1 file changed, 24 insertions(+), 1 deletion(-) - ---- a/arch/arm/mach-at91/pm_suspend.S -+++ b/arch/arm/mach-at91/pm_suspend.S -@@ -1014,6 +1014,10 @@ ENTRY(at91_pm_suspend_in_sram) - mov tmp1, #0 - mcr p15, 0, tmp1, c7, c10, 4 - -+ /* Flush tlb. */ -+ mov r4, #0 -+ mcr p15, 0, r4, c8, c7, 0 -+ - ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] - str tmp1, .mckr_offset - ldr tmp1, [r0, #PM_DATA_PMC_VERSION] -@@ -1023,23 +1027,42 @@ ENTRY(at91_pm_suspend_in_sram) - ldr tmp1, [r0, #PM_DATA_MODE] - str tmp1, .pm_mode - -+ /* -+ * ldrne below are here to preload their address in the TLB as access -+ * to RAM may be limited while in self-refresh. -+ */ - ldr tmp1, [r0, #PM_DATA_PMC] - str tmp1, .pmc_base -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ - ldr tmp1, [r0, #PM_DATA_RAMC0] - str tmp1, .sramc_base -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ - ldr tmp1, [r0, #PM_DATA_RAMC1] - str tmp1, .sramc1_base -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ -+#ifndef CONFIG_SOC_SAM_V4_V5 -+ /* ldrne below are here to preload their address in the TLB */ - ldr tmp1, [r0, #PM_DATA_RAMC_PHY] - str tmp1, .sramc_phy_base -- /* Both ldrne below are here to preload their address in the TLB */ -+ cmp tmp1, #0 -+ ldrne tmp2, [tmp1, #0] -+ - ldr tmp1, [r0, #PM_DATA_SHDWC] - str tmp1, .shdwc - cmp tmp1, #0 - ldrne tmp2, [tmp1, #0] -+ - ldr tmp1, [r0, #PM_DATA_SFRBU] - str tmp1, .sfrbu - cmp tmp1, #0 - ldrne tmp2, [tmp1, #0x10] -+#endif - - /* Active the self-refresh mode */ - at91_sramc_self_refresh_ena diff --git a/target/linux/at91/patches-5.10/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch b/target/linux/at91/patches-5.10/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch deleted file mode 100644 index 9b59d9521f..0000000000 --- a/target/linux/at91/patches-5.10/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 98d2c4ca97dde30616fa78ad5677825b1966cec6 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 15 Sep 2021 10:48:35 +0300 -Subject: [PATCH 232/247] ARM: dts: at91: sama7g5ek: use proper slew-rate - settings for GMACs - -Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain -GMAC's MDIO pins should be configured with slew-rate enabled, while the -data + signaling pins should be configured with slew-rate disabled when -GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets -the slew-rate as enabled for all pins. Adapt the device tree to comply -with these. - -Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------ - 1 file changed, 22 insertions(+), 6 deletions(-) - ---- a/arch/arm/boot/dts/at91-sama7g5ek.dts -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -355,7 +355,10 @@ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>; -+ pinctrl-0 = <&pinctrl_gmac0_default -+ &pinctrl_gmac0_mdio_default -+ &pinctrl_gmac0_txck_default -+ &pinctrl_gmac0_phy_irq>; - phy-mode = "rgmii-id"; - status = "okay"; - -@@ -370,7 +373,9 @@ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>; -+ pinctrl-0 = <&pinctrl_gmac1_default -+ &pinctrl_gmac1_mdio_default -+ &pinctrl_gmac1_phy_irq>; - phy-mode = "rmii"; - status = "okay"; - -@@ -425,14 +430,20 @@ - , - , - , -- , -- , - ; -+ slew-rate = <0>; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac0_mdio_default: gmac0_mdio_default { -+ pinmux = , -+ ; - bias-disable; - }; - - pinctrl_gmac0_txck_default: gmac0_txck_default { - pinmux = ; -+ slew-rate = <0>; - bias-pull-up; - }; - -@@ -449,8 +460,13 @@ - , - , - , -- , -- , -+ ; -+ slew-rate = <0>; -+ bias-disable; -+ }; -+ -+ pinctrl_gmac1_mdio_default: gmac1_mdio_default { -+ pinmux = , - ; - bias-disable; - }; diff --git a/target/linux/at91/patches-5.10/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch b/target/linux/at91/patches-5.10/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch deleted file mode 100644 index 61ed933f02..0000000000 --- a/target/linux/at91/patches-5.10/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 4c0b77276307d2cba8ae2595cbae4cc916c84c36 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 15 Sep 2021 10:48:36 +0300 -Subject: [PATCH 233/247] ARM: dts: at91: sama7g5ek: to not touch slew-rate for - SDMMC pins - -With commit c709135e576b ("pinctrl: at91-pio4: add support for slew-rate") -and commit cbde6c823bfa ("pinctrl: at91-pio4: Fix slew rate disablement") -the slew-rate is enabled by default for each configured pin. The datasheet -specifies at chapter "Output Driver AC Characteristics" that HSIO -drivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate -setting but are rather calibrated against an external 1% resistor mounted -on the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal -frequency and the external load, it is possible to adjust their target -output impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled -at the moment in device tree). - -Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek") -Signed-off-by: Claudiu Beznea -Signed-off-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20210915074836.6574-3-claudiu.beznea@microchip.com ---- - arch/arm/boot/dts/at91-sama7g5ek.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm/boot/dts/at91-sama7g5ek.dts -+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts -@@ -558,6 +558,7 @@ - , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - -@@ -565,6 +566,7 @@ - pinmux = , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - }; -@@ -576,6 +578,7 @@ - , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - -@@ -584,6 +587,7 @@ - , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - }; -@@ -595,11 +599,13 @@ - , - , - ; -+ slew-rate = <0>; - bias-pull-up; - }; - - ck { - pinmux = ; -+ slew-rate = <0>; - bias-pull-up; - }; - }; diff --git a/target/linux/at91/patches-5.10/234-clk-at91-re-factor-clocks-suspend-resume.patch b/target/linux/at91/patches-5.10/234-clk-at91-re-factor-clocks-suspend-resume.patch deleted file mode 100644 index 5d399f6535..0000000000 --- a/target/linux/at91/patches-5.10/234-clk-at91-re-factor-clocks-suspend-resume.patch +++ /dev/null @@ -1,1342 +0,0 @@ -From 65bb4687b2a5c6f02f44345540c3389d6e7523e7 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:05 +0300 -Subject: [PATCH 234/247] clk: at91: re-factor clocks suspend/resume - -SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where -most of the SoC's components are powered off (including PMC). Resuming -from this mode is done with the help of bootloader. Peripherals are not -aware of the power saving mode thus most of them are disabling clocks in -proper suspend API and re-enable them in resume API without taking into -account the previously setup rate. Moreover some of the peripherals are -acting as wakeup sources and are not disabling the clocks in this -scenario, when suspending. Since backup mode cuts the power for -peripherals, in resume part these clocks needs to be re-configured. - -The initial PMC suspend/resume code was designed only for SAMA5D2's PMC -(as it was the only one supporting backup mode). SAMA7G supports also -backup mode and its PMC is different (few new functionalities, different -registers offsets, different offsets in registers for each -functionalities). To address both SAMA5D2 and SAMA7G5 PMC add -.save_context()/.resume_context() support to each clocks driver and call -this from PMC driver. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-generated.c | 46 +++++-- - drivers/clk/at91/clk-main.c | 66 ++++++++++ - drivers/clk/at91/clk-master.c | 194 ++++++++++++++++++++++++++-- - drivers/clk/at91/clk-peripheral.c | 40 +++++- - drivers/clk/at91/clk-pll.c | 39 ++++++ - drivers/clk/at91/clk-programmable.c | 29 ++++- - drivers/clk/at91/clk-sam9x60-pll.c | 68 +++++++++- - drivers/clk/at91/clk-system.c | 20 +++ - drivers/clk/at91/clk-usb.c | 27 ++++ - drivers/clk/at91/clk-utmi.c | 39 ++++++ - drivers/clk/at91/pmc.c | 147 +-------------------- - drivers/clk/at91/pmc.h | 24 ++-- - 12 files changed, 558 insertions(+), 181 deletions(-) - ---- a/drivers/clk/at91/clk-generated.c -+++ b/drivers/clk/at91/clk-generated.c -@@ -27,6 +27,7 @@ struct clk_generated { - u32 id; - u32 gckdiv; - const struct clk_pcr_layout *layout; -+ struct at91_clk_pms pms; - u8 parent_id; - int chg_pid; - }; -@@ -34,25 +35,35 @@ struct clk_generated { - #define to_clk_generated(hw) \ - container_of(hw, struct clk_generated, hw) - --static int clk_generated_enable(struct clk_hw *hw) -+static int clk_generated_set(struct clk_generated *gck, int status) - { -- struct clk_generated *gck = to_clk_generated(hw); - unsigned long flags; -- -- pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", -- __func__, gck->gckdiv, gck->parent_id); -+ unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0; - - spin_lock_irqsave(gck->lock, flags); - regmap_write(gck->regmap, gck->layout->offset, - (gck->id & gck->layout->pid_mask)); - regmap_update_bits(gck->regmap, gck->layout->offset, - AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | -- gck->layout->cmd | AT91_PMC_PCR_GCKEN, -+ gck->layout->cmd | enable, - field_prep(gck->layout->gckcss_mask, gck->parent_id) | - gck->layout->cmd | - FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | -- AT91_PMC_PCR_GCKEN); -+ enable); - spin_unlock_irqrestore(gck->lock, flags); -+ -+ return 0; -+} -+ -+static int clk_generated_enable(struct clk_hw *hw) -+{ -+ struct clk_generated *gck = to_clk_generated(hw); -+ -+ pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", -+ __func__, gck->gckdiv, gck->parent_id); -+ -+ clk_generated_set(gck, 1); -+ - return 0; - } - -@@ -249,6 +260,23 @@ static int clk_generated_set_rate(struct - return 0; - } - -+static int clk_generated_save_context(struct clk_hw *hw) -+{ -+ struct clk_generated *gck = to_clk_generated(hw); -+ -+ gck->pms.status = clk_generated_is_enabled(&gck->hw); -+ -+ return 0; -+} -+ -+static void clk_generated_restore_context(struct clk_hw *hw) -+{ -+ struct clk_generated *gck = to_clk_generated(hw); -+ -+ if (gck->pms.status) -+ clk_generated_set(gck, gck->pms.status); -+} -+ - static const struct clk_ops generated_ops = { - .enable = clk_generated_enable, - .disable = clk_generated_disable, -@@ -258,6 +286,8 @@ static const struct clk_ops generated_op - .get_parent = clk_generated_get_parent, - .set_parent = clk_generated_set_parent, - .set_rate = clk_generated_set_rate, -+ .save_context = clk_generated_save_context, -+ .restore_context = clk_generated_restore_context, - }; - - /** -@@ -324,8 +354,6 @@ at91_clk_register_generated(struct regma - if (ret) { - kfree(gck); - hw = ERR_PTR(ret); -- } else { -- pmc_register_id(id); - } - - return hw; ---- a/drivers/clk/at91/clk-main.c -+++ b/drivers/clk/at91/clk-main.c -@@ -28,6 +28,7 @@ - struct clk_main_osc { - struct clk_hw hw; - struct regmap *regmap; -+ struct at91_clk_pms pms; - }; - - #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw) -@@ -37,6 +38,7 @@ struct clk_main_rc_osc { - struct regmap *regmap; - unsigned long frequency; - unsigned long accuracy; -+ struct at91_clk_pms pms; - }; - - #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw) -@@ -51,6 +53,7 @@ struct clk_rm9200_main { - struct clk_sam9x5_main { - struct clk_hw hw; - struct regmap *regmap; -+ struct at91_clk_pms pms; - u8 parent; - }; - -@@ -120,10 +123,29 @@ static int clk_main_osc_is_prepared(stru - return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp); - } - -+static int clk_main_osc_save_context(struct clk_hw *hw) -+{ -+ struct clk_main_osc *osc = to_clk_main_osc(hw); -+ -+ osc->pms.status = clk_main_osc_is_prepared(hw); -+ -+ return 0; -+} -+ -+static void clk_main_osc_restore_context(struct clk_hw *hw) -+{ -+ struct clk_main_osc *osc = to_clk_main_osc(hw); -+ -+ if (osc->pms.status) -+ clk_main_osc_prepare(hw); -+} -+ - static const struct clk_ops main_osc_ops = { - .prepare = clk_main_osc_prepare, - .unprepare = clk_main_osc_unprepare, - .is_prepared = clk_main_osc_is_prepared, -+ .save_context = clk_main_osc_save_context, -+ .restore_context = clk_main_osc_restore_context, - }; - - struct clk_hw * __init -@@ -240,12 +262,31 @@ static unsigned long clk_main_rc_osc_rec - return osc->accuracy; - } - -+static int clk_main_rc_osc_save_context(struct clk_hw *hw) -+{ -+ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); -+ -+ osc->pms.status = clk_main_rc_osc_is_prepared(hw); -+ -+ return 0; -+} -+ -+static void clk_main_rc_osc_restore_context(struct clk_hw *hw) -+{ -+ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); -+ -+ if (osc->pms.status) -+ clk_main_rc_osc_prepare(hw); -+} -+ - static const struct clk_ops main_rc_osc_ops = { - .prepare = clk_main_rc_osc_prepare, - .unprepare = clk_main_rc_osc_unprepare, - .is_prepared = clk_main_rc_osc_is_prepared, - .recalc_rate = clk_main_rc_osc_recalc_rate, - .recalc_accuracy = clk_main_rc_osc_recalc_accuracy, -+ .save_context = clk_main_rc_osc_save_context, -+ .restore_context = clk_main_rc_osc_restore_context, - }; - - struct clk_hw * __init -@@ -465,12 +506,37 @@ static u8 clk_sam9x5_main_get_parent(str - return clk_main_parent_select(status); - } - -+static int clk_sam9x5_main_save_context(struct clk_hw *hw) -+{ -+ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); -+ -+ clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw); -+ clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw); -+ -+ return 0; -+} -+ -+static void clk_sam9x5_main_restore_context(struct clk_hw *hw) -+{ -+ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); -+ int ret; -+ -+ ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent); -+ if (ret) -+ return; -+ -+ if (clkmain->pms.status) -+ clk_sam9x5_main_prepare(hw); -+} -+ - static const struct clk_ops sam9x5_main_ops = { - .prepare = clk_sam9x5_main_prepare, - .is_prepared = clk_sam9x5_main_is_prepared, - .recalc_rate = clk_sam9x5_main_recalc_rate, - .set_parent = clk_sam9x5_main_set_parent, - .get_parent = clk_sam9x5_main_get_parent, -+ .save_context = clk_sam9x5_main_save_context, -+ .restore_context = clk_sam9x5_main_restore_context, - }; - - struct clk_hw * __init ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -37,6 +37,7 @@ struct clk_master { - spinlock_t *lock; - const struct clk_master_layout *layout; - const struct clk_master_characteristics *characteristics; -+ struct at91_clk_pms pms; - u32 *mux_table; - u32 mckr; - int chg_pid; -@@ -112,10 +113,52 @@ static unsigned long clk_master_div_reca - return rate; - } - -+static int clk_master_div_save_context(struct clk_hw *hw) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ struct clk_hw *parent_hw = clk_hw_get_parent(hw); -+ unsigned long flags; -+ unsigned int mckr, div; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_read(master->regmap, master->layout->offset, &mckr); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ mckr &= master->layout->mask; -+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; -+ div = master->characteristics->divisors[div]; -+ -+ master->pms.parent_rate = clk_hw_get_rate(parent_hw); -+ master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div); -+ -+ return 0; -+} -+ -+static void clk_master_div_restore_context(struct clk_hw *hw) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; -+ unsigned int mckr; -+ u8 div; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_read(master->regmap, master->layout->offset, &mckr); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ mckr &= master->layout->mask; -+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; -+ div = master->characteristics->divisors[div]; -+ -+ if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate)) -+ pr_warn("MCKR DIV not configured properly by firmware!\n"); -+} -+ - static const struct clk_ops master_div_ops = { - .prepare = clk_master_prepare, - .is_prepared = clk_master_is_prepared, - .recalc_rate = clk_master_div_recalc_rate, -+ .save_context = clk_master_div_save_context, -+ .restore_context = clk_master_div_restore_context, - }; - - static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, -@@ -125,7 +168,9 @@ static int clk_master_div_set_rate(struc - const struct clk_master_characteristics *characteristics = - master->characteristics; - unsigned long flags; -+ unsigned int mckr, tmp; - int div, i; -+ int ret; - - div = DIV_ROUND_CLOSEST(parent_rate, rate); - if (div > ARRAY_SIZE(characteristics->divisors)) -@@ -145,11 +190,24 @@ static int clk_master_div_set_rate(struc - return -EINVAL; - - spin_lock_irqsave(master->lock, flags); -- regmap_update_bits(master->regmap, master->layout->offset, -- (MASTER_DIV_MASK << MASTER_DIV_SHIFT), -- (div << MASTER_DIV_SHIFT)); -+ ret = regmap_read(master->regmap, master->layout->offset, &mckr); -+ if (ret) -+ goto unlock; -+ -+ tmp = mckr & master->layout->mask; -+ tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; -+ if (tmp == div) -+ goto unlock; -+ -+ mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT); -+ mckr |= (div << MASTER_DIV_SHIFT); -+ ret = regmap_write(master->regmap, master->layout->offset, mckr); -+ if (ret) -+ goto unlock; -+ - while (!clk_master_ready(master)) - cpu_relax(); -+unlock: - spin_unlock_irqrestore(master->lock, flags); - - return 0; -@@ -197,12 +255,25 @@ static int clk_master_div_determine_rate - return 0; - } - -+static void clk_master_div_restore_context_chg(struct clk_hw *hw) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ int ret; -+ -+ ret = clk_master_div_set_rate(hw, master->pms.rate, -+ master->pms.parent_rate); -+ if (ret) -+ pr_warn("Failed to restore MCK DIV clock\n"); -+} -+ - static const struct clk_ops master_div_ops_chg = { - .prepare = clk_master_prepare, - .is_prepared = clk_master_is_prepared, - .recalc_rate = clk_master_div_recalc_rate, - .determine_rate = clk_master_div_determine_rate, - .set_rate = clk_master_div_set_rate, -+ .save_context = clk_master_div_save_context, -+ .restore_context = clk_master_div_restore_context_chg, - }; - - static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, -@@ -272,7 +343,8 @@ static int clk_master_pres_set_rate(stru - { - struct clk_master *master = to_clk_master(hw); - unsigned long flags; -- unsigned int pres; -+ unsigned int pres, mckr, tmp; -+ int ret; - - pres = DIV_ROUND_CLOSEST(parent_rate, rate); - if (pres > MASTER_PRES_MAX) -@@ -284,15 +356,27 @@ static int clk_master_pres_set_rate(stru - pres = ffs(pres) - 1; - - spin_lock_irqsave(master->lock, flags); -- regmap_update_bits(master->regmap, master->layout->offset, -- (MASTER_PRES_MASK << master->layout->pres_shift), -- (pres << master->layout->pres_shift)); -+ ret = regmap_read(master->regmap, master->layout->offset, &mckr); -+ if (ret) -+ goto unlock; -+ -+ mckr &= master->layout->mask; -+ tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK; -+ if (pres == tmp) -+ goto unlock; -+ -+ mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift); -+ mckr |= (pres << master->layout->pres_shift); -+ ret = regmap_write(master->regmap, master->layout->offset, mckr); -+ if (ret) -+ goto unlock; - - while (!clk_master_ready(master)) - cpu_relax(); -+unlock: - spin_unlock_irqrestore(master->lock, flags); - -- return 0; -+ return ret; - } - - static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, -@@ -330,11 +414,68 @@ static u8 clk_master_pres_get_parent(str - return mckr & AT91_PMC_CSS; - } - -+static int clk_master_pres_save_context(struct clk_hw *hw) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ struct clk_hw *parent_hw = clk_hw_get_parent(hw); -+ unsigned long flags; -+ unsigned int val, pres; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_read(master->regmap, master->layout->offset, &val); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ val &= master->layout->mask; -+ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; -+ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) -+ pres = 3; -+ else -+ pres = (1 << pres); -+ -+ master->pms.parent = val & AT91_PMC_CSS; -+ master->pms.parent_rate = clk_hw_get_rate(parent_hw); -+ master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres); -+ -+ return 0; -+} -+ -+static void clk_master_pres_restore_context(struct clk_hw *hw) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; -+ unsigned int val, pres; -+ -+ spin_lock_irqsave(master->lock, flags); -+ regmap_read(master->regmap, master->layout->offset, &val); -+ spin_unlock_irqrestore(master->lock, flags); -+ -+ val &= master->layout->mask; -+ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; -+ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres) -+ pres = 3; -+ else -+ pres = (1 << pres); -+ -+ if (master->pms.rate != -+ DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) || -+ (master->pms.parent != (val & AT91_PMC_CSS))) -+ pr_warn("MCKR PRES was not configured properly by firmware!\n"); -+} -+ -+static void clk_master_pres_restore_context_chg(struct clk_hw *hw) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ -+ clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate); -+} -+ - static const struct clk_ops master_pres_ops = { - .prepare = clk_master_prepare, - .is_prepared = clk_master_is_prepared, - .recalc_rate = clk_master_pres_recalc_rate, - .get_parent = clk_master_pres_get_parent, -+ .save_context = clk_master_pres_save_context, -+ .restore_context = clk_master_pres_restore_context, - }; - - static const struct clk_ops master_pres_ops_chg = { -@@ -344,6 +485,8 @@ static const struct clk_ops master_pres_ - .recalc_rate = clk_master_pres_recalc_rate, - .get_parent = clk_master_pres_get_parent, - .set_rate = clk_master_pres_set_rate, -+ .save_context = clk_master_pres_save_context, -+ .restore_context = clk_master_pres_restore_context_chg, - }; - - static struct clk_hw * __init -@@ -539,20 +682,21 @@ static int clk_sama7g5_master_set_parent - return 0; - } - --static int clk_sama7g5_master_enable(struct clk_hw *hw) -+static void clk_sama7g5_master_set(struct clk_master *master, -+ unsigned int status) - { -- struct clk_master *master = to_clk_master(hw); - unsigned long flags; - unsigned int val, cparent; -+ unsigned int enable = status ? PMC_MCR_EN : 0; - - spin_lock_irqsave(master->lock, flags); - - regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); - regmap_read(master->regmap, PMC_MCR, &val); - regmap_update_bits(master->regmap, PMC_MCR, -- PMC_MCR_EN | PMC_MCR_CSS | PMC_MCR_DIV | -+ enable | PMC_MCR_CSS | PMC_MCR_DIV | - PMC_MCR_CMD | PMC_MCR_ID_MSK, -- PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) | -+ enable | (master->parent << PMC_MCR_CSS_SHIFT) | - (master->div << MASTER_DIV_SHIFT) | - PMC_MCR_CMD | PMC_MCR_ID(master->id)); - -@@ -563,6 +707,13 @@ static int clk_sama7g5_master_enable(str - cpu_relax(); - - spin_unlock_irqrestore(master->lock, flags); -+} -+ -+static int clk_sama7g5_master_enable(struct clk_hw *hw) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ -+ clk_sama7g5_master_set(master, 1); - - return 0; - } -@@ -620,6 +771,23 @@ static int clk_sama7g5_master_set_rate(s - return 0; - } - -+static int clk_sama7g5_master_save_context(struct clk_hw *hw) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ -+ master->pms.status = clk_sama7g5_master_is_enabled(hw); -+ -+ return 0; -+} -+ -+static void clk_sama7g5_master_restore_context(struct clk_hw *hw) -+{ -+ struct clk_master *master = to_clk_master(hw); -+ -+ if (master->pms.status) -+ clk_sama7g5_master_set(master, master->pms.status); -+} -+ - static const struct clk_ops sama7g5_master_ops = { - .enable = clk_sama7g5_master_enable, - .disable = clk_sama7g5_master_disable, -@@ -629,6 +797,8 @@ static const struct clk_ops sama7g5_mast - .set_rate = clk_sama7g5_master_set_rate, - .get_parent = clk_sama7g5_master_get_parent, - .set_parent = clk_sama7g5_master_set_parent, -+ .save_context = clk_sama7g5_master_save_context, -+ .restore_context = clk_sama7g5_master_restore_context, - }; - - struct clk_hw * __init ---- a/drivers/clk/at91/clk-peripheral.c -+++ b/drivers/clk/at91/clk-peripheral.c -@@ -37,6 +37,7 @@ struct clk_sam9x5_peripheral { - u32 id; - u32 div; - const struct clk_pcr_layout *layout; -+ struct at91_clk_pms pms; - bool auto_div; - int chg_pid; - }; -@@ -155,10 +156,11 @@ static void clk_sam9x5_peripheral_autodi - periph->div = shift; - } - --static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) -+static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph, -+ unsigned int status) - { -- struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); - unsigned long flags; -+ unsigned int enable = status ? AT91_PMC_PCR_EN : 0; - - if (periph->id < PERIPHERAL_ID_MIN) - return 0; -@@ -168,15 +170,21 @@ static int clk_sam9x5_peripheral_enable( - (periph->id & periph->layout->pid_mask)); - regmap_update_bits(periph->regmap, periph->layout->offset, - periph->layout->div_mask | periph->layout->cmd | -- AT91_PMC_PCR_EN, -+ enable, - field_prep(periph->layout->div_mask, periph->div) | -- periph->layout->cmd | -- AT91_PMC_PCR_EN); -+ periph->layout->cmd | enable); - spin_unlock_irqrestore(periph->lock, flags); - - return 0; - } - -+static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) -+{ -+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); -+ -+ return clk_sam9x5_peripheral_set(periph, 1); -+} -+ - static void clk_sam9x5_peripheral_disable(struct clk_hw *hw) - { - struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); -@@ -393,6 +401,23 @@ static int clk_sam9x5_peripheral_set_rat - return -EINVAL; - } - -+static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw) -+{ -+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); -+ -+ periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw); -+ -+ return 0; -+} -+ -+static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw) -+{ -+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); -+ -+ if (periph->pms.status) -+ clk_sam9x5_peripheral_set(periph, periph->pms.status); -+} -+ - static const struct clk_ops sam9x5_peripheral_ops = { - .enable = clk_sam9x5_peripheral_enable, - .disable = clk_sam9x5_peripheral_disable, -@@ -400,6 +425,8 @@ static const struct clk_ops sam9x5_perip - .recalc_rate = clk_sam9x5_peripheral_recalc_rate, - .round_rate = clk_sam9x5_peripheral_round_rate, - .set_rate = clk_sam9x5_peripheral_set_rate, -+ .save_context = clk_sam9x5_peripheral_save_context, -+ .restore_context = clk_sam9x5_peripheral_restore_context, - }; - - static const struct clk_ops sam9x5_peripheral_chg_ops = { -@@ -409,6 +436,8 @@ static const struct clk_ops sam9x5_perip - .recalc_rate = clk_sam9x5_peripheral_recalc_rate, - .determine_rate = clk_sam9x5_peripheral_determine_rate, - .set_rate = clk_sam9x5_peripheral_set_rate, -+ .save_context = clk_sam9x5_peripheral_save_context, -+ .restore_context = clk_sam9x5_peripheral_restore_context, - }; - - struct clk_hw * __init -@@ -460,7 +489,6 @@ at91_clk_register_sam9x5_peripheral(stru - hw = ERR_PTR(ret); - } else { - clk_sam9x5_peripheral_autodiv(periph); -- pmc_register_id(id); - } - - return hw; ---- a/drivers/clk/at91/clk-pll.c -+++ b/drivers/clk/at91/clk-pll.c -@@ -40,6 +40,7 @@ struct clk_pll { - u16 mul; - const struct clk_pll_layout *layout; - const struct clk_pll_characteristics *characteristics; -+ struct at91_clk_pms pms; - }; - - static inline bool clk_pll_ready(struct regmap *regmap, int id) -@@ -260,6 +261,42 @@ static int clk_pll_set_rate(struct clk_h - return 0; - } - -+static int clk_pll_save_context(struct clk_hw *hw) -+{ -+ struct clk_pll *pll = to_clk_pll(hw); -+ struct clk_hw *parent_hw = clk_hw_get_parent(hw); -+ -+ pll->pms.parent_rate = clk_hw_get_rate(parent_hw); -+ pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate); -+ pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id)); -+ -+ return 0; -+} -+ -+static void clk_pll_restore_context(struct clk_hw *hw) -+{ -+ struct clk_pll *pll = to_clk_pll(hw); -+ unsigned long calc_rate; -+ unsigned int pllr, pllr_out, pllr_count; -+ u8 out = 0; -+ -+ if (pll->characteristics->out) -+ out = pll->characteristics->out[pll->range]; -+ -+ regmap_read(pll->regmap, PLL_REG(pll->id), &pllr); -+ -+ calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) * -+ (PLL_MUL(pllr, pll->layout) + 1); -+ pllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT; -+ pllr_out = (pllr >> PLL_OUT_SHIFT) & out; -+ -+ if (pll->pms.rate != calc_rate || -+ pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) || -+ pllr_count != PLL_MAX_COUNT || -+ (out && pllr_out != out)) -+ pr_warn("PLLAR was not configured properly by firmware\n"); -+} -+ - static const struct clk_ops pll_ops = { - .prepare = clk_pll_prepare, - .unprepare = clk_pll_unprepare, -@@ -267,6 +304,8 @@ static const struct clk_ops pll_ops = { - .recalc_rate = clk_pll_recalc_rate, - .round_rate = clk_pll_round_rate, - .set_rate = clk_pll_set_rate, -+ .save_context = clk_pll_save_context, -+ .restore_context = clk_pll_restore_context, - }; - - struct clk_hw * __init ---- a/drivers/clk/at91/clk-programmable.c -+++ b/drivers/clk/at91/clk-programmable.c -@@ -24,6 +24,7 @@ struct clk_programmable { - u32 *mux_table; - u8 id; - const struct clk_programmable_layout *layout; -+ struct at91_clk_pms pms; - }; - - #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw) -@@ -177,12 +178,38 @@ static int clk_programmable_set_rate(str - return 0; - } - -+static int clk_programmable_save_context(struct clk_hw *hw) -+{ -+ struct clk_programmable *prog = to_clk_programmable(hw); -+ struct clk_hw *parent_hw = clk_hw_get_parent(hw); -+ -+ prog->pms.parent = clk_programmable_get_parent(hw); -+ prog->pms.parent_rate = clk_hw_get_rate(parent_hw); -+ prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate); -+ -+ return 0; -+} -+ -+static void clk_programmable_restore_context(struct clk_hw *hw) -+{ -+ struct clk_programmable *prog = to_clk_programmable(hw); -+ int ret; -+ -+ ret = clk_programmable_set_parent(hw, prog->pms.parent); -+ if (ret) -+ return; -+ -+ clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate); -+} -+ - static const struct clk_ops programmable_ops = { - .recalc_rate = clk_programmable_recalc_rate, - .determine_rate = clk_programmable_determine_rate, - .get_parent = clk_programmable_get_parent, - .set_parent = clk_programmable_set_parent, - .set_rate = clk_programmable_set_rate, -+ .save_context = clk_programmable_save_context, -+ .restore_context = clk_programmable_restore_context, - }; - - struct clk_hw * __init -@@ -221,8 +248,6 @@ at91_clk_register_programmable(struct re - if (ret) { - kfree(prog); - hw = ERR_PTR(ret); -- } else { -- pmc_register_pck(id); - } - - return hw; ---- a/drivers/clk/at91/clk-sam9x60-pll.c -+++ b/drivers/clk/at91/clk-sam9x60-pll.c -@@ -38,12 +38,14 @@ struct sam9x60_pll_core { - - struct sam9x60_frac { - struct sam9x60_pll_core core; -+ struct at91_clk_pms pms; - u32 frac; - u16 mul; - }; - - struct sam9x60_div { - struct sam9x60_pll_core core; -+ struct at91_clk_pms pms; - u8 div; - }; - -@@ -75,9 +77,8 @@ static unsigned long sam9x60_frac_pll_re - DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); - } - --static int sam9x60_frac_pll_prepare(struct clk_hw *hw) -+static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) - { -- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); - struct sam9x60_frac *frac = to_sam9x60_frac(core); - struct regmap *regmap = core->regmap; - unsigned int val, cfrac, cmul; -@@ -141,6 +142,13 @@ unlock: - return 0; - } - -+static int sam9x60_frac_pll_prepare(struct clk_hw *hw) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ -+ return sam9x60_frac_pll_set(core); -+} -+ - static void sam9x60_frac_pll_unprepare(struct clk_hw *hw) - { - struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -@@ -280,6 +288,25 @@ unlock: - return ret; - } - -+static int sam9x60_frac_pll_save_context(struct clk_hw *hw) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ struct sam9x60_frac *frac = to_sam9x60_frac(core); -+ -+ frac->pms.status = sam9x60_pll_ready(core->regmap, core->id); -+ -+ return 0; -+} -+ -+static void sam9x60_frac_pll_restore_context(struct clk_hw *hw) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ struct sam9x60_frac *frac = to_sam9x60_frac(core); -+ -+ if (frac->pms.status) -+ sam9x60_frac_pll_set(core); -+} -+ - static const struct clk_ops sam9x60_frac_pll_ops = { - .prepare = sam9x60_frac_pll_prepare, - .unprepare = sam9x60_frac_pll_unprepare, -@@ -287,6 +314,8 @@ static const struct clk_ops sam9x60_frac - .recalc_rate = sam9x60_frac_pll_recalc_rate, - .round_rate = sam9x60_frac_pll_round_rate, - .set_rate = sam9x60_frac_pll_set_rate, -+ .save_context = sam9x60_frac_pll_save_context, -+ .restore_context = sam9x60_frac_pll_restore_context, - }; - - static const struct clk_ops sam9x60_frac_pll_ops_chg = { -@@ -296,11 +325,12 @@ static const struct clk_ops sam9x60_frac - .recalc_rate = sam9x60_frac_pll_recalc_rate, - .round_rate = sam9x60_frac_pll_round_rate, - .set_rate = sam9x60_frac_pll_set_rate_chg, -+ .save_context = sam9x60_frac_pll_save_context, -+ .restore_context = sam9x60_frac_pll_restore_context, - }; - --static int sam9x60_div_pll_prepare(struct clk_hw *hw) -+static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) - { -- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); - struct sam9x60_div *div = to_sam9x60_div(core); - struct regmap *regmap = core->regmap; - unsigned long flags; -@@ -334,6 +364,13 @@ unlock: - return 0; - } - -+static int sam9x60_div_pll_prepare(struct clk_hw *hw) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ -+ return sam9x60_div_pll_set(core); -+} -+ - static void sam9x60_div_pll_unprepare(struct clk_hw *hw) - { - struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -@@ -482,6 +519,25 @@ unlock: - return 0; - } - -+static int sam9x60_div_pll_save_context(struct clk_hw *hw) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ struct sam9x60_div *div = to_sam9x60_div(core); -+ -+ div->pms.status = sam9x60_div_pll_is_prepared(hw); -+ -+ return 0; -+} -+ -+static void sam9x60_div_pll_restore_context(struct clk_hw *hw) -+{ -+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); -+ struct sam9x60_div *div = to_sam9x60_div(core); -+ -+ if (div->pms.status) -+ sam9x60_div_pll_set(core); -+} -+ - static const struct clk_ops sam9x60_div_pll_ops = { - .prepare = sam9x60_div_pll_prepare, - .unprepare = sam9x60_div_pll_unprepare, -@@ -489,6 +545,8 @@ static const struct clk_ops sam9x60_div_ - .recalc_rate = sam9x60_div_pll_recalc_rate, - .round_rate = sam9x60_div_pll_round_rate, - .set_rate = sam9x60_div_pll_set_rate, -+ .save_context = sam9x60_div_pll_save_context, -+ .restore_context = sam9x60_div_pll_restore_context, - }; - - static const struct clk_ops sam9x60_div_pll_ops_chg = { -@@ -498,6 +556,8 @@ static const struct clk_ops sam9x60_div_ - .recalc_rate = sam9x60_div_pll_recalc_rate, - .round_rate = sam9x60_div_pll_round_rate, - .set_rate = sam9x60_div_pll_set_rate_chg, -+ .save_context = sam9x60_div_pll_save_context, -+ .restore_context = sam9x60_div_pll_restore_context, - }; - - struct clk_hw * __init ---- a/drivers/clk/at91/clk-system.c -+++ b/drivers/clk/at91/clk-system.c -@@ -20,6 +20,7 @@ - struct clk_system { - struct clk_hw hw; - struct regmap *regmap; -+ struct at91_clk_pms pms; - u8 id; - }; - -@@ -77,10 +78,29 @@ static int clk_system_is_prepared(struct - return !!(status & (1 << sys->id)); - } - -+static int clk_system_save_context(struct clk_hw *hw) -+{ -+ struct clk_system *sys = to_clk_system(hw); -+ -+ sys->pms.status = clk_system_is_prepared(hw); -+ -+ return 0; -+} -+ -+static void clk_system_restore_context(struct clk_hw *hw) -+{ -+ struct clk_system *sys = to_clk_system(hw); -+ -+ if (sys->pms.status) -+ clk_system_prepare(&sys->hw); -+} -+ - static const struct clk_ops system_ops = { - .prepare = clk_system_prepare, - .unprepare = clk_system_unprepare, - .is_prepared = clk_system_is_prepared, -+ .save_context = clk_system_save_context, -+ .restore_context = clk_system_restore_context, - }; - - struct clk_hw * __init ---- a/drivers/clk/at91/clk-usb.c -+++ b/drivers/clk/at91/clk-usb.c -@@ -24,6 +24,7 @@ - struct at91sam9x5_clk_usb { - struct clk_hw hw; - struct regmap *regmap; -+ struct at91_clk_pms pms; - u32 usbs_mask; - u8 num_parents; - }; -@@ -148,12 +149,38 @@ static int at91sam9x5_clk_usb_set_rate(s - return 0; - } - -+static int at91sam9x5_usb_save_context(struct clk_hw *hw) -+{ -+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); -+ struct clk_hw *parent_hw = clk_hw_get_parent(hw); -+ -+ usb->pms.parent = at91sam9x5_clk_usb_get_parent(hw); -+ usb->pms.parent_rate = clk_hw_get_rate(parent_hw); -+ usb->pms.rate = at91sam9x5_clk_usb_recalc_rate(hw, usb->pms.parent_rate); -+ -+ return 0; -+} -+ -+static void at91sam9x5_usb_restore_context(struct clk_hw *hw) -+{ -+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); -+ int ret; -+ -+ ret = at91sam9x5_clk_usb_set_parent(hw, usb->pms.parent); -+ if (ret) -+ return; -+ -+ at91sam9x5_clk_usb_set_rate(hw, usb->pms.rate, usb->pms.parent_rate); -+} -+ - static const struct clk_ops at91sam9x5_usb_ops = { - .recalc_rate = at91sam9x5_clk_usb_recalc_rate, - .determine_rate = at91sam9x5_clk_usb_determine_rate, - .get_parent = at91sam9x5_clk_usb_get_parent, - .set_parent = at91sam9x5_clk_usb_set_parent, - .set_rate = at91sam9x5_clk_usb_set_rate, -+ .save_context = at91sam9x5_usb_save_context, -+ .restore_context = at91sam9x5_usb_restore_context, - }; - - static int at91sam9n12_clk_usb_enable(struct clk_hw *hw) ---- a/drivers/clk/at91/clk-utmi.c -+++ b/drivers/clk/at91/clk-utmi.c -@@ -23,6 +23,7 @@ struct clk_utmi { - struct clk_hw hw; - struct regmap *regmap_pmc; - struct regmap *regmap_sfr; -+ struct at91_clk_pms pms; - }; - - #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw) -@@ -113,11 +114,30 @@ static unsigned long clk_utmi_recalc_rat - return UTMI_RATE; - } - -+static int clk_utmi_save_context(struct clk_hw *hw) -+{ -+ struct clk_utmi *utmi = to_clk_utmi(hw); -+ -+ utmi->pms.status = clk_utmi_is_prepared(hw); -+ -+ return 0; -+} -+ -+static void clk_utmi_restore_context(struct clk_hw *hw) -+{ -+ struct clk_utmi *utmi = to_clk_utmi(hw); -+ -+ if (utmi->pms.status) -+ clk_utmi_prepare(hw); -+} -+ - static const struct clk_ops utmi_ops = { - .prepare = clk_utmi_prepare, - .unprepare = clk_utmi_unprepare, - .is_prepared = clk_utmi_is_prepared, - .recalc_rate = clk_utmi_recalc_rate, -+ .save_context = clk_utmi_save_context, -+ .restore_context = clk_utmi_restore_context, - }; - - static struct clk_hw * __init -@@ -232,10 +252,29 @@ static int clk_utmi_sama7g5_is_prepared( - return 0; - } - -+static int clk_utmi_sama7g5_save_context(struct clk_hw *hw) -+{ -+ struct clk_utmi *utmi = to_clk_utmi(hw); -+ -+ utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw); -+ -+ return 0; -+} -+ -+static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw) -+{ -+ struct clk_utmi *utmi = to_clk_utmi(hw); -+ -+ if (utmi->pms.status) -+ clk_utmi_sama7g5_prepare(hw); -+} -+ - static const struct clk_ops sama7g5_utmi_ops = { - .prepare = clk_utmi_sama7g5_prepare, - .is_prepared = clk_utmi_sama7g5_is_prepared, - .recalc_rate = clk_utmi_recalc_rate, -+ .save_context = clk_utmi_sama7g5_save_context, -+ .restore_context = clk_utmi_sama7g5_restore_context, - }; - - struct clk_hw * __init ---- a/drivers/clk/at91/pmc.c -+++ b/drivers/clk/at91/pmc.c -@@ -3,6 +3,7 @@ - * Copyright (C) 2013 Boris BREZILLON - */ - -+#include - #include - #include - #include -@@ -14,8 +15,6 @@ - - #include - --#include -- - #include "pmc.h" - - #define PMC_MAX_IDS 128 -@@ -111,147 +110,19 @@ struct pmc_data *pmc_data_allocate(unsig - } - - #ifdef CONFIG_PM --static struct regmap *pmcreg; -- --static u8 registered_ids[PMC_MAX_IDS]; --static u8 registered_pcks[PMC_MAX_PCKS]; -- --static struct --{ -- u32 scsr; -- u32 pcsr0; -- u32 uckr; -- u32 mor; -- u32 mcfr; -- u32 pllar; -- u32 mckr; -- u32 usb; -- u32 imr; -- u32 pcsr1; -- u32 pcr[PMC_MAX_IDS]; -- u32 audio_pll0; -- u32 audio_pll1; -- u32 pckr[PMC_MAX_PCKS]; --} pmc_cache; -- --/* -- * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored -- * without alteration in the table, and 0 is for unused clocks. -- */ --void pmc_register_id(u8 id) -+static int at91_pmc_suspend(void) - { -- int i; -- -- for (i = 0; i < PMC_MAX_IDS; i++) { -- if (registered_ids[i] == 0) { -- registered_ids[i] = id; -- break; -- } -- if (registered_ids[i] == id) -- break; -- } -+ return clk_save_context(); - } - --/* -- * As Programmable Clock 0 is valid on AT91 chips, there is an offset -- * of 1 between the stored value and the real clock ID. -- */ --void pmc_register_pck(u8 pck) -+static void at91_pmc_resume(void) - { -- int i; -- -- for (i = 0; i < PMC_MAX_PCKS; i++) { -- if (registered_pcks[i] == 0) { -- registered_pcks[i] = pck + 1; -- break; -- } -- if (registered_pcks[i] == (pck + 1)) -- break; -- } --} -- --static int pmc_suspend(void) --{ -- int i; -- u8 num; -- -- regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr); -- regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0); -- regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr); -- regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor); -- regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr); -- regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar); -- regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr); -- regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb); -- regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr); -- regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1); -- -- for (i = 0; registered_ids[i]; i++) { -- regmap_write(pmcreg, AT91_PMC_PCR, -- (registered_ids[i] & AT91_PMC_PCR_PID_MASK)); -- regmap_read(pmcreg, AT91_PMC_PCR, -- &pmc_cache.pcr[registered_ids[i]]); -- } -- for (i = 0; registered_pcks[i]; i++) { -- num = registered_pcks[i] - 1; -- regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]); -- } -- -- return 0; --} -- --static bool pmc_ready(unsigned int mask) --{ -- unsigned int status; -- -- regmap_read(pmcreg, AT91_PMC_SR, &status); -- -- return ((status & mask) == mask) ? 1 : 0; --} -- --static void pmc_resume(void) --{ -- int i; -- u8 num; -- u32 tmp; -- u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA; -- -- regmap_read(pmcreg, AT91_PMC_MCKR, &tmp); -- if (pmc_cache.mckr != tmp) -- pr_warn("MCKR was not configured properly by the firmware\n"); -- regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp); -- if (pmc_cache.pllar != tmp) -- pr_warn("PLLAR was not configured properly by the firmware\n"); -- -- regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr); -- regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0); -- regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr); -- regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor); -- regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr); -- regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb); -- regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr); -- regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1); -- -- for (i = 0; registered_ids[i]; i++) { -- regmap_write(pmcreg, AT91_PMC_PCR, -- pmc_cache.pcr[registered_ids[i]] | -- AT91_PMC_PCR_CMD); -- } -- for (i = 0; registered_pcks[i]; i++) { -- num = registered_pcks[i] - 1; -- regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]); -- } -- -- if (pmc_cache.uckr & AT91_PMC_UPLLEN) -- mask |= AT91_PMC_LOCKU; -- -- while (!pmc_ready(mask)) -- cpu_relax(); -+ clk_restore_context(); - } - - static struct syscore_ops pmc_syscore_ops = { -- .suspend = pmc_suspend, -- .resume = pmc_resume, -+ .suspend = at91_pmc_suspend, -+ .resume = at91_pmc_resume, - }; - - static const struct of_device_id sama5d2_pmc_dt_ids[] = { -@@ -271,11 +142,7 @@ static int __init pmc_register_ops(void) - of_node_put(np); - return -ENODEV; - } -- -- pmcreg = device_node_to_regmap(np); - of_node_put(np); -- if (IS_ERR(pmcreg)) -- return PTR_ERR(pmcreg); - - register_syscore_ops(&pmc_syscore_ops); - ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -13,6 +13,8 @@ - #include - #include - -+#include -+ - extern spinlock_t pmc_pcr_lock; - - struct pmc_data { -@@ -98,6 +100,20 @@ struct clk_pcr_layout { - u32 pid_mask; - }; - -+/** -+ * struct at91_clk_pms - Power management state for AT91 clock -+ * @rate: clock rate -+ * @parent_rate: clock parent rate -+ * @status: clock status (enabled or disabled) -+ * @parent: clock parent index -+ */ -+struct at91_clk_pms { -+ unsigned long rate; -+ unsigned long parent_rate; -+ unsigned int status; -+ unsigned int parent; -+}; -+ - #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) - #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - -@@ -248,12 +264,4 @@ struct clk_hw * __init - at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, - const char *parent_name); - --#ifdef CONFIG_PM --void pmc_register_id(u8 id); --void pmc_register_pck(u8 pck); --#else --static inline void pmc_register_id(u8 id) {} --static inline void pmc_register_pck(u8 pck) {} --#endif -- - #endif /* __PMC_H_ */ diff --git a/target/linux/at91/patches-5.10/235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch b/target/linux/at91/patches-5.10/235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch deleted file mode 100644 index 19f1f6fdf2..0000000000 --- a/target/linux/at91/patches-5.10/235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 63a0c32028148e91ea91cfbf95841c4ecd69d21b Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:06 +0300 -Subject: [PATCH 235/247] clk: at91: pmc: execute suspend/resume only for - backup mode - -Before going to backup mode architecture specific PM code sets the first -word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()). -Thus take this into account when suspending/resuming clocks. This will -avoid executing unnecessary instructions when suspending to non backup -modes. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/pmc.c | 39 +++++++++++++++++++++++++++++++++++++++ - 1 file changed, 39 insertions(+) - ---- a/drivers/clk/at91/pmc.c -+++ b/drivers/clk/at91/pmc.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -110,13 +111,35 @@ struct pmc_data *pmc_data_allocate(unsig - } - - #ifdef CONFIG_PM -+ -+/* Address in SECURAM that say if we suspend to backup mode. */ -+static void __iomem *at91_pmc_backup_suspend; -+ - static int at91_pmc_suspend(void) - { -+ unsigned int backup; -+ -+ if (!at91_pmc_backup_suspend) -+ return 0; -+ -+ backup = readl_relaxed(at91_pmc_backup_suspend); -+ if (!backup) -+ return 0; -+ - return clk_save_context(); - } - - static void at91_pmc_resume(void) - { -+ unsigned int backup; -+ -+ if (!at91_pmc_backup_suspend) -+ return; -+ -+ backup = readl_relaxed(at91_pmc_backup_suspend); -+ if (!backup) -+ return; -+ - clk_restore_context(); - } - -@@ -144,6 +167,22 @@ static int __init pmc_register_ops(void) - } - of_node_put(np); - -+ np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam"); -+ if (!np) -+ return -ENODEV; -+ -+ if (!of_device_is_available(np)) { -+ of_node_put(np); -+ return -ENODEV; -+ } -+ of_node_put(np); -+ -+ at91_pmc_backup_suspend = of_iomap(np, 0); -+ if (!at91_pmc_backup_suspend) { -+ pr_warn("%s(): unable to map securam\n", __func__); -+ return -ENOMEM; -+ } -+ - register_syscore_ops(&pmc_syscore_ops); - - return 0; diff --git a/target/linux/at91/patches-5.10/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch b/target/linux/at91/patches-5.10/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch deleted file mode 100644 index 046acec453..0000000000 --- a/target/linux/at91/patches-5.10/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 50edd53c26177e95995533b7d649801086a52f6c Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:07 +0300 -Subject: [PATCH 236/247] clk: at91: sama7g5: add securam's peripheral clock - -Add SECURAM's peripheral clock. - -Signed-off-by: Claudiu Beznea -Acked-by: Nicolas Ferre -Link: https://lore.kernel.org/r/20211011112719.3951784-4-claudiu.beznea@microchip.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -377,6 +377,7 @@ static const struct { - u8 id; - } sama7g5_periphck[] = { - { .n = "pioA_clk", .p = "mck0", .id = 11, }, -+ { .n = "securam_clk", .p = "mck0", .id = 18, }, - { .n = "sfr_clk", .p = "mck1", .id = 19, }, - { .n = "hsmc_clk", .p = "mck1", .id = 21, }, - { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, diff --git a/target/linux/at91/patches-5.10/237-clk-at91-clk-master-add-register-definition-for-sama.patch b/target/linux/at91/patches-5.10/237-clk-at91-clk-master-add-register-definition-for-sama.patch deleted file mode 100644 index 726d9b33e4..0000000000 --- a/target/linux/at91/patches-5.10/237-clk-at91-clk-master-add-register-definition-for-sama.patch +++ /dev/null @@ -1,124 +0,0 @@ -From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:08 +0300 -Subject: [PATCH 237/247] clk: at91: clk-master: add register definition for - sama7g5's master clock - -SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the -register at offset 0x30 (relative to PMC). In the last/first phase of -suspend/resume procedure (which is architecture specific) the parent -of master clocks are changed (via assembly code) for more power saving -(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable -and at91_mckx_ps_restore). Thus the macros corresponding to register -at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S. -commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's -master clock") introduced the proper macros but didn't adapted the -clk-master.c as well. Thus, this commit adapt the clk-master.c to use -the macros introduced in commit ec03f18cc222 ("clk: at91: add register -definition for sama7g5's master clock"). - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-master.c | 50 ++++++++++++++++------------------- - 1 file changed, 23 insertions(+), 27 deletions(-) - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -17,15 +17,7 @@ - #define MASTER_DIV_SHIFT 8 - #define MASTER_DIV_MASK 0x7 - --#define PMC_MCR 0x30 --#define PMC_MCR_ID_MSK GENMASK(3, 0) --#define PMC_MCR_CMD BIT(7) --#define PMC_MCR_DIV GENMASK(10, 8) --#define PMC_MCR_CSS GENMASK(20, 16) - #define PMC_MCR_CSS_SHIFT (16) --#define PMC_MCR_EN BIT(28) -- --#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK) - - #define MASTER_MAX_ID 4 - -@@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struc - { - unsigned long flags; - unsigned int val, cparent; -- unsigned int enable = status ? PMC_MCR_EN : 0; -+ unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; - - spin_lock_irqsave(master->lock, flags); - -- regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id)); -- regmap_read(master->regmap, PMC_MCR, &val); -- regmap_update_bits(master->regmap, PMC_MCR, -- enable | PMC_MCR_CSS | PMC_MCR_DIV | -- PMC_MCR_CMD | PMC_MCR_ID_MSK, -+ regmap_write(master->regmap, AT91_PMC_MCR_V2, -+ AT91_PMC_MCR_V2_ID(master->id)); -+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); -+ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, -+ enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | -+ AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, - enable | (master->parent << PMC_MCR_CSS_SHIFT) | - (master->div << MASTER_DIV_SHIFT) | -- PMC_MCR_CMD | PMC_MCR_ID(master->id)); -+ AT91_PMC_MCR_V2_CMD | -+ AT91_PMC_MCR_V2_ID(master->id)); - -- cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; -+ cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; - - /* Wait here only if parent is being changed. */ - while ((cparent != master->parent) && !clk_master_ready(master)) -@@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(s - - spin_lock_irqsave(master->lock, flags); - -- regmap_write(master->regmap, PMC_MCR, master->id); -- regmap_update_bits(master->regmap, PMC_MCR, -- PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK, -- PMC_MCR_CMD | PMC_MCR_ID(master->id)); -+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); -+ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, -+ AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD | -+ AT91_PMC_MCR_V2_ID_MSK, -+ AT91_PMC_MCR_V2_CMD | -+ AT91_PMC_MCR_V2_ID(master->id)); - - spin_unlock_irqrestore(master->lock, flags); - } -@@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled - - spin_lock_irqsave(master->lock, flags); - -- regmap_write(master->regmap, PMC_MCR, master->id); -- regmap_read(master->regmap, PMC_MCR, &val); -+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); -+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); - - spin_unlock_irqrestore(master->lock, flags); - -- return !!(val & PMC_MCR_EN); -+ return !!(val & AT91_PMC_MCR_V2_EN); - } - - static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, -@@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct - master->mux_table = mux_table; - - spin_lock_irqsave(master->lock, flags); -- regmap_write(master->regmap, PMC_MCR, master->id); -- regmap_read(master->regmap, PMC_MCR, &val); -- master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT; -- master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT; -+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id); -+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val); -+ master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; -+ master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT; - spin_unlock_irqrestore(master->lock, flags); - - hw = &master->hw; diff --git a/target/linux/at91/patches-5.10/238-clk-at91-clk-master-improve-readability-by-using-loc.patch b/target/linux/at91/patches-5.10/238-clk-at91-clk-master-improve-readability-by-using-loc.patch deleted file mode 100644 index a5b57a67ad..0000000000 --- a/target/linux/at91/patches-5.10/238-clk-at91-clk-master-improve-readability-by-using-loc.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 17b53ad1574cb5f41789993289d3d94f7a50f0ce Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:09 +0300 -Subject: [PATCH 238/247] clk: at91: clk-master: improve readability by using - local variables - -Improve readability in clk_sama7g5_master_set() by using local -variables. - -Suggested-by: Nicolas Ferre -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-master.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -680,6 +680,8 @@ static void clk_sama7g5_master_set(struc - unsigned long flags; - unsigned int val, cparent; - unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0; -+ unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT; -+ unsigned int div = master->div << MASTER_DIV_SHIFT; - - spin_lock_irqsave(master->lock, flags); - -@@ -689,9 +691,7 @@ static void clk_sama7g5_master_set(struc - regmap_update_bits(master->regmap, AT91_PMC_MCR_V2, - enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV | - AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK, -- enable | (master->parent << PMC_MCR_CSS_SHIFT) | -- (master->div << MASTER_DIV_SHIFT) | -- AT91_PMC_MCR_V2_CMD | -+ enable | parent | div | AT91_PMC_MCR_V2_CMD | - AT91_PMC_MCR_V2_ID(master->id)); - - cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT; diff --git a/target/linux/at91/patches-5.10/239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch b/target/linux/at91/patches-5.10/239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch deleted file mode 100644 index 2918de1700..0000000000 --- a/target/linux/at91/patches-5.10/239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 8a38e0dda46c9d941a61d8b2e6c14704531b7871 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:10 +0300 -Subject: [PATCH 239/247] clk: at91: pmc: add sama7g5 to the list of available - pmcs - -Add SAMA7G5 to the list of available PMCs such that the suspend/resume -code for clocks to be used on backup mode. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/pmc.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/pmc.c -+++ b/drivers/clk/at91/pmc.c -@@ -148,8 +148,9 @@ static struct syscore_ops pmc_syscore_op - .resume = at91_pmc_resume, - }; - --static const struct of_device_id sama5d2_pmc_dt_ids[] = { -+static const struct of_device_id pmc_dt_ids[] = { - { .compatible = "atmel,sama5d2-pmc" }, -+ { .compatible = "microchip,sama7g5-pmc", }, - { /* sentinel */ } - }; - -@@ -157,7 +158,7 @@ static int __init pmc_register_ops(void) - { - struct device_node *np; - -- np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids); -+ np = of_find_matching_node(NULL, pmc_dt_ids); - if (!np) - return -ENODEV; - diff --git a/target/linux/at91/patches-5.10/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch b/target/linux/at91/patches-5.10/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch deleted file mode 100644 index c78883c8d6..0000000000 --- a/target/linux/at91/patches-5.10/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch +++ /dev/null @@ -1,39 +0,0 @@ -From bb8e6ca274763fa98613dbe8b0833348a1d8fe4d Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:12 +0300 -Subject: [PATCH 240/247] clk: at91: clk-master: check if div or pres is zero - -Check if div or pres is zero before using it as argument for ffs(). -In case div is zero ffs() will return 0 and thus substracting from -zero will lead to invalid values to be setup in registers. - -Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") -Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5") -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-master.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -344,7 +344,7 @@ static int clk_master_pres_set_rate(stru - - else if (pres == 3) - pres = MASTER_PRES_MAX; -- else -+ else if (pres) - pres = ffs(pres) - 1; - - spin_lock_irqsave(master->lock, flags); -@@ -757,7 +757,7 @@ static int clk_sama7g5_master_set_rate(s - - if (div == 3) - div = MASTER_PRES_MAX; -- else -+ else if (div) - div = ffs(div) - 1; - - spin_lock_irqsave(master->lock, flags); diff --git a/target/linux/at91/patches-5.10/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch b/target/linux/at91/patches-5.10/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch deleted file mode 100644 index 14fa690769..0000000000 --- a/target/linux/at91/patches-5.10/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 27c11c09346b7b9f67eeb39db1b943f4a9742ff3 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:13 +0300 -Subject: [PATCH 241/247] clk: at91: clk-master: mask mckr against layout->mask - -Mask values read/written from/to MCKR against layout->mask as this -mask may be different b/w PMC versions. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-master.c | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -186,8 +186,8 @@ static int clk_master_div_set_rate(struc - if (ret) - goto unlock; - -- tmp = mckr & master->layout->mask; -- tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; -+ mckr &= master->layout->mask; -+ tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; - if (tmp == div) - goto unlock; - -@@ -384,6 +384,7 @@ static unsigned long clk_master_pres_rec - regmap_read(master->regmap, master->layout->offset, &val); - spin_unlock_irqrestore(master->lock, flags); - -+ val &= master->layout->mask; - pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; - if (pres == 3 && characteristics->have_div3_pres) - pres = 3; -@@ -403,6 +404,8 @@ static u8 clk_master_pres_get_parent(str - regmap_read(master->regmap, master->layout->offset, &mckr); - spin_unlock_irqrestore(master->lock, flags); - -+ mckr &= master->layout->mask; -+ - return mckr & AT91_PMC_CSS; - } - diff --git a/target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch b/target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch deleted file mode 100644 index 950ca26afd..0000000000 --- a/target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 4375cd63b55860f5e82618dc5f50846b3129842a Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:14 +0300 -Subject: [PATCH 242/247] clk: at91: clk-master: fix prescaler logic - -When prescaler value read from register is MASTER_PRES_MAX it means -that the input clock will be divided by 3. Fix the code to reflect -this. - -Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-master.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_rec - - val &= master->layout->mask; - pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK; -- if (pres == 3 && characteristics->have_div3_pres) -+ if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres) - pres = 3; - else - pres = (1 << pres); diff --git a/target/linux/at91/patches-5.10/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch b/target/linux/at91/patches-5.10/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch deleted file mode 100644 index 678303da37..0000000000 --- a/target/linux/at91/patches-5.10/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch +++ /dev/null @@ -1,312 +0,0 @@ -From e76d2af5009f52aa02d3db7ae32d150ad66398f9 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:15 +0300 -Subject: [PATCH 243/247] clk: at91: clk-sam9x60-pll: add notifier for div part - of PLL - -SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts: -one fractional part and one divider. On SAMA7G5 the CPU PLL could be -changed at run-time to implement DVFS. The hardware clock tree on -SAMA7G5 for CPU PLL is as follows: - - +---- div1 ----------------> cpuck - | -FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0 - -The div1 block is not implemented in Linux; on prescaler block it has -been discovered a bug on some scenarios and will be removed from Linux -in next commits. Thus, the final clock tree that will be used in Linux -will be as follows: - - +-----------> cpuck - | -FRAC PLL ---> DIV PLL -+-> div0 ---> mck0 - -It has been proposed in [1] to not introduce a new CPUFreq driver but -to overload the proper clock drivers with proper operation such that -cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement -clock notifiers which applies safe dividers before FRAC PLL is changed. -The current commit treats only the DIV PLL by adding a notifier that -sets a safe divider on PRE_RATE_CHANGE events. The safe divider is -provided by initialization clock code (sama7g5.c). The div0 is treated -in next commits (to keep the changes as clean as possible). - -[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/ - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++++++++++++++------- - drivers/clk/at91/pmc.h | 3 +- - drivers/clk/at91/sam9x60.c | 6 +- - drivers/clk/at91/sama7g5.c | 13 +++- - 4 files changed, 95 insertions(+), 29 deletions(-) - ---- a/drivers/clk/at91/clk-sam9x60-pll.c -+++ b/drivers/clk/at91/clk-sam9x60-pll.c -@@ -5,6 +5,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -47,12 +48,15 @@ struct sam9x60_div { - struct sam9x60_pll_core core; - struct at91_clk_pms pms; - u8 div; -+ u8 safe_div; - }; - - #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw) - #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core) - #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core) - -+static struct sam9x60_div *notifier_div; -+ - static inline bool sam9x60_pll_ready(struct regmap *regmap, int id) - { - unsigned int status; -@@ -329,6 +333,26 @@ static const struct clk_ops sam9x60_frac - .restore_context = sam9x60_frac_pll_restore_context, - }; - -+/* This function should be called with spinlock acquired. */ -+static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, -+ bool enable) -+{ -+ struct regmap *regmap = core->regmap; -+ u32 ena_msk = enable ? core->layout->endiv_mask : 0; -+ u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0; -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, -+ core->layout->div_mask | ena_msk, -+ (div << core->layout->div_shift) | ena_val); -+ -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, -+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, -+ AT91_PMC_PLL_UPDT_UPDATE | core->id); -+ -+ while (!sam9x60_pll_ready(regmap, core->id)) -+ cpu_relax(); -+} -+ - static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) - { - struct sam9x60_div *div = to_sam9x60_div(core); -@@ -346,17 +370,7 @@ static int sam9x60_div_pll_set(struct sa - if (!!(val & core->layout->endiv_mask) && cdiv == div->div) - goto unlock; - -- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, -- core->layout->div_mask | core->layout->endiv_mask, -- (div->div << core->layout->div_shift) | -- (1 << core->layout->endiv_shift)); -- -- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, -- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, -- AT91_PMC_PLL_UPDT_UPDATE | core->id); -- -- while (!sam9x60_pll_ready(regmap, core->id)) -- cpu_relax(); -+ sam9x60_div_pll_set_div(core, div->div, 1); - - unlock: - spin_unlock_irqrestore(core->lock, flags); -@@ -502,16 +516,7 @@ static int sam9x60_div_pll_set_rate_chg( - if (cdiv == div->div) - goto unlock; - -- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, -- core->layout->div_mask, -- (div->div << core->layout->div_shift)); -- -- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, -- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK, -- AT91_PMC_PLL_UPDT_UPDATE | core->id); -- -- while (!sam9x60_pll_ready(regmap, core->id)) -- cpu_relax(); -+ sam9x60_div_pll_set_div(core, div->div, 0); - - unlock: - spin_unlock_irqrestore(core->lock, irqflags); -@@ -538,6 +543,48 @@ static void sam9x60_div_pll_restore_cont - sam9x60_div_pll_set(core); - } - -+static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier, -+ unsigned long code, void *data) -+{ -+ struct sam9x60_div *div = notifier_div; -+ struct sam9x60_pll_core core = div->core; -+ struct regmap *regmap = core.regmap; -+ unsigned long irqflags; -+ u32 val, cdiv; -+ int ret = NOTIFY_DONE; -+ -+ if (code != PRE_RATE_CHANGE) -+ return ret; -+ -+ /* -+ * We switch to safe divider to avoid overclocking of other domains -+ * feed by us while the frac PLL (our parent) is changed. -+ */ -+ div->div = div->safe_div; -+ -+ spin_lock_irqsave(core.lock, irqflags); -+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK, -+ core.id); -+ regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val); -+ cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; -+ -+ /* Stop if nothing changed. */ -+ if (cdiv == div->safe_div) -+ goto unlock; -+ -+ sam9x60_div_pll_set_div(&core, div->div, 0); -+ ret = NOTIFY_OK; -+ -+unlock: -+ spin_unlock_irqrestore(core.lock, irqflags); -+ -+ return ret; -+} -+ -+static struct notifier_block sam9x60_div_pll_notifier = { -+ .notifier_call = sam9x60_div_pll_notifier_fn, -+}; -+ - static const struct clk_ops sam9x60_div_pll_ops = { - .prepare = sam9x60_div_pll_prepare, - .unprepare = sam9x60_div_pll_unprepare, -@@ -647,7 +694,8 @@ struct clk_hw * __init - sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, u32 flags) -+ const struct clk_pll_layout *layout, u32 flags, -+ u32 safe_div) - { - struct sam9x60_div *div; - struct clk_hw *hw; -@@ -656,9 +704,13 @@ sam9x60_clk_register_div_pll(struct regm - unsigned int val; - int ret; - -- if (id > PLL_MAX_ID || !lock) -+ /* We only support one changeable PLL. */ -+ if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div)) - return ERR_PTR(-EINVAL); - -+ if (safe_div >= PLL_DIV_MAX) -+ safe_div = PLL_DIV_MAX - 1; -+ - div = kzalloc(sizeof(*div), GFP_KERNEL); - if (!div) - return ERR_PTR(-ENOMEM); -@@ -678,6 +730,7 @@ sam9x60_clk_register_div_pll(struct regm - div->core.layout = layout; - div->core.regmap = regmap; - div->core.lock = lock; -+ div->safe_div = safe_div; - - spin_lock_irqsave(div->core.lock, irqflags); - -@@ -693,6 +746,9 @@ sam9x60_clk_register_div_pll(struct regm - if (ret) { - kfree(div); - hw = ERR_PTR(ret); -+ } else if (div->safe_div) { -+ notifier_div = div; -+ clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier); - } - - return hw; ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -214,7 +214,8 @@ struct clk_hw * __init - sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, u8 id, - const struct clk_pll_characteristics *characteristics, -- const struct clk_pll_layout *layout, u32 flags); -+ const struct clk_pll_layout *layout, u32 flags, -+ u32 safe_div); - - struct clk_hw * __init - sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, ---- a/drivers/clk/at91/sam9x60.c -+++ b/drivers/clk/at91/sam9x60.c -@@ -242,7 +242,7 @@ static void __init sam9x60_pmc_setup(str - * This feeds CPU. It should not - * be disabled. - */ -- CLK_IS_CRITICAL | CLK_SET_RATE_GATE); -+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - -@@ -260,7 +260,7 @@ static void __init sam9x60_pmc_setup(str - &pll_div_layout, - CLK_SET_RATE_GATE | - CLK_SET_PARENT_GATE | -- CLK_SET_RATE_PARENT); -+ CLK_SET_RATE_PARENT, 0); - if (IS_ERR(hw)) - goto err_free; - -@@ -279,7 +279,7 @@ static void __init sam9x60_pmc_setup(str - hw = at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", &sam9x60_master_layout, - &mck_characteristics, &mck_lock, -- CLK_SET_RATE_GATE); -+ CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -127,6 +127,8 @@ static const struct clk_pll_characterist - * @t: clock type - * @f: clock flags - * @eid: export index in sama7g5->chws[] array -+ * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE -+ * notification - */ - static const struct { - const char *n; -@@ -136,6 +138,7 @@ static const struct { - unsigned long f; - u8 t; - u8 eid; -+ u8 safe_div; - } sama7g5_plls[][PLL_ID_MAX] = { - [PLL_ID_CPU] = { - { .n = "cpupll_fracck", -@@ -156,7 +159,12 @@ static const struct { - .t = PLL_TYPE_DIV, - /* This feeds CPU. It should not be disabled. */ - .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, -- .eid = PMC_CPUPLL, }, -+ .eid = PMC_CPUPLL, -+ /* -+ * Safe div=15 should be safe even for switching b/w 1GHz and -+ * 90MHz (frac pll might go up to 1.2GHz). -+ */ -+ .safe_div = 15, }, - }, - - [PLL_ID_SYS] = { -@@ -967,7 +975,8 @@ static void __init sama7g5_pmc_setup(str - sama7g5_plls[i][j].p, i, - sama7g5_plls[i][j].c, - sama7g5_plls[i][j].l, -- sama7g5_plls[i][j].f); -+ sama7g5_plls[i][j].f, -+ sama7g5_plls[i][j].safe_div); - break; - - default: diff --git a/target/linux/at91/patches-5.10/244-clk-at91-clk-master-add-notifier-for-divider.patch b/target/linux/at91/patches-5.10/244-clk-at91-clk-master-add-notifier-for-divider.patch deleted file mode 100644 index 35262db6cb..0000000000 --- a/target/linux/at91/patches-5.10/244-clk-at91-clk-master-add-notifier-for-divider.patch +++ /dev/null @@ -1,519 +0,0 @@ -From 75d5d1d584ae73ba0c36d1d7255db6153ca4d3f3 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:16 +0300 -Subject: [PATCH 244/247] clk: at91: clk-master: add notifier for divider - -SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same -parent with cpuck as seen in the following clock tree: - - +----------> cpuck - | -FRAC PLL ---> DIV PLL -+-> DIV ---> mck0 - -mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking -while changing FRAC PLL or DIV PLL the commit implements a notifier for -mck0 which applies a safe divider to register (maximum value of the divider -which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not -overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE -events. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/at91rm9200.c | 2 +- - drivers/clk/at91/at91sam9260.c | 2 +- - drivers/clk/at91/at91sam9g45.c | 2 +- - drivers/clk/at91/at91sam9n12.c | 2 +- - drivers/clk/at91/at91sam9rl.c | 2 +- - drivers/clk/at91/at91sam9x5.c | 2 +- - drivers/clk/at91/clk-master.c | 244 +++++++++++++++++++++++---------- - drivers/clk/at91/dt-compat.c | 2 +- - drivers/clk/at91/pmc.h | 2 +- - drivers/clk/at91/sama5d2.c | 2 +- - drivers/clk/at91/sama5d3.c | 2 +- - drivers/clk/at91/sama5d4.c | 2 +- - drivers/clk/at91/sama7g5.c | 2 +- - 13 files changed, 186 insertions(+), 82 deletions(-) - ---- a/drivers/clk/at91/at91rm9200.c -+++ b/drivers/clk/at91/at91rm9200.c -@@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup( - "masterck_pres", - &at91rm9200_master_layout, - &rm9200_mck_characteristics, -- &rm9200_mck_lock, CLK_SET_RATE_GATE); -+ &rm9200_mck_lock, CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/at91sam9260.c -+++ b/drivers/clk/at91/at91sam9260.c -@@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup - &at91rm9200_master_layout, - data->mck_characteristics, - &at91sam9260_mck_lock, -- CLK_SET_RATE_GATE); -+ CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/at91sam9g45.c -+++ b/drivers/clk/at91/at91sam9g45.c -@@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup - &at91rm9200_master_layout, - &mck_characteristics, - &at91sam9g45_mck_lock, -- CLK_SET_RATE_GATE); -+ CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/at91sam9n12.c -+++ b/drivers/clk/at91/at91sam9n12.c -@@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup - &at91sam9x5_master_layout, - &mck_characteristics, - &at91sam9n12_mck_lock, -- CLK_SET_RATE_GATE); -+ CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/at91sam9rl.c -+++ b/drivers/clk/at91/at91sam9rl.c -@@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup( - "masterck_pres", - &at91rm9200_master_layout, - &sam9rl_mck_characteristics, -- &sam9rl_mck_lock, CLK_SET_RATE_GATE); -+ &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/at91sam9x5.c -+++ b/drivers/clk/at91/at91sam9x5.c -@@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup( - "masterck_pres", - &at91sam9x5_master_layout, - &mck_characteristics, &mck_lock, -- CLK_SET_RATE_GATE); -+ CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/clk-master.c -+++ b/drivers/clk/at91/clk-master.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -36,8 +37,12 @@ struct clk_master { - u8 id; - u8 parent; - u8 div; -+ u32 safe_div; - }; - -+/* MCK div reference to be used by notifier. */ -+static struct clk_master *master_div; -+ - static inline bool clk_master_ready(struct clk_master *master) - { - unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY; -@@ -153,107 +158,81 @@ static const struct clk_ops master_div_o - .restore_context = clk_master_div_restore_context, - }; - --static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate, -- unsigned long parent_rate) -+/* This function must be called with lock acquired. */ -+static int clk_master_div_set(struct clk_master *master, -+ unsigned long parent_rate, int div) - { -- struct clk_master *master = to_clk_master(hw); - const struct clk_master_characteristics *characteristics = - master->characteristics; -- unsigned long flags; -- unsigned int mckr, tmp; -- int div, i; -+ unsigned long rate = parent_rate; -+ unsigned int max_div = 0, div_index = 0, max_div_index = 0; -+ unsigned int i, mckr, tmp; - int ret; - -- div = DIV_ROUND_CLOSEST(parent_rate, rate); -- if (div > ARRAY_SIZE(characteristics->divisors)) -- return -EINVAL; -- - for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { - if (!characteristics->divisors[i]) - break; - -- if (div == characteristics->divisors[i]) { -- div = i; -- break; -+ if (div == characteristics->divisors[i]) -+ div_index = i; -+ -+ if (max_div < characteristics->divisors[i]) { -+ max_div = characteristics->divisors[i]; -+ max_div_index = i; - } - } - -- if (i == ARRAY_SIZE(characteristics->divisors)) -- return -EINVAL; -+ if (div > max_div) -+ div_index = max_div_index; - -- spin_lock_irqsave(master->lock, flags); - ret = regmap_read(master->regmap, master->layout->offset, &mckr); - if (ret) -- goto unlock; -+ return ret; - - mckr &= master->layout->mask; - tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; -- if (tmp == div) -- goto unlock; -+ if (tmp == div_index) -+ return 0; -+ -+ rate /= characteristics->divisors[div_index]; -+ if (rate < characteristics->output.min) -+ pr_warn("master clk div is underclocked"); -+ else if (rate > characteristics->output.max) -+ pr_warn("master clk div is overclocked"); - - mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT); -- mckr |= (div << MASTER_DIV_SHIFT); -+ mckr |= (div_index << MASTER_DIV_SHIFT); - ret = regmap_write(master->regmap, master->layout->offset, mckr); - if (ret) -- goto unlock; -+ return ret; - - while (!clk_master_ready(master)) - cpu_relax(); --unlock: -- spin_unlock_irqrestore(master->lock, flags); -+ -+ master->div = characteristics->divisors[div_index]; - - return 0; - } - --static int clk_master_div_determine_rate(struct clk_hw *hw, -- struct clk_rate_request *req) -+static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw, -+ unsigned long parent_rate) - { - struct clk_master *master = to_clk_master(hw); -- const struct clk_master_characteristics *characteristics = -- master->characteristics; -- struct clk_hw *parent; -- unsigned long parent_rate, tmp_rate, best_rate = 0; -- int i, best_diff = INT_MIN, tmp_diff; -- -- parent = clk_hw_get_parent(hw); -- if (!parent) -- return -EINVAL; -- -- parent_rate = clk_hw_get_rate(parent); -- if (!parent_rate) -- return -EINVAL; - -- for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { -- if (!characteristics->divisors[i]) -- break; -- -- tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate, -- characteristics->divisors[i]); -- tmp_diff = abs(tmp_rate - req->rate); -- -- if (!best_rate || best_diff > tmp_diff) { -- best_diff = tmp_diff; -- best_rate = tmp_rate; -- } -- -- if (!best_diff) -- break; -- } -- -- req->best_parent_rate = best_rate; -- req->best_parent_hw = parent; -- req->rate = best_rate; -- -- return 0; -+ return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div); - } - - static void clk_master_div_restore_context_chg(struct clk_hw *hw) - { - struct clk_master *master = to_clk_master(hw); -+ unsigned long flags; - int ret; - -- ret = clk_master_div_set_rate(hw, master->pms.rate, -- master->pms.parent_rate); -+ spin_lock_irqsave(master->lock, flags); -+ ret = clk_master_div_set(master, master->pms.parent_rate, -+ DIV_ROUND_CLOSEST(master->pms.parent_rate, -+ master->pms.rate)); -+ spin_unlock_irqrestore(master->lock, flags); - if (ret) - pr_warn("Failed to restore MCK DIV clock\n"); - } -@@ -261,13 +240,116 @@ static void clk_master_div_restore_conte - static const struct clk_ops master_div_ops_chg = { - .prepare = clk_master_prepare, - .is_prepared = clk_master_is_prepared, -- .recalc_rate = clk_master_div_recalc_rate, -- .determine_rate = clk_master_div_determine_rate, -- .set_rate = clk_master_div_set_rate, -+ .recalc_rate = clk_master_div_recalc_rate_chg, - .save_context = clk_master_div_save_context, - .restore_context = clk_master_div_restore_context_chg, - }; - -+static int clk_master_div_notifier_fn(struct notifier_block *notifier, -+ unsigned long code, void *data) -+{ -+ const struct clk_master_characteristics *characteristics = -+ master_div->characteristics; -+ struct clk_notifier_data *cnd = data; -+ unsigned long flags, new_parent_rate, new_rate; -+ unsigned int mckr, div, new_div = 0; -+ int ret, i; -+ long tmp_diff; -+ long best_diff = -1; -+ -+ spin_lock_irqsave(master_div->lock, flags); -+ switch (code) { -+ case PRE_RATE_CHANGE: -+ /* -+ * We want to avoid any overclocking of MCK DIV domain. To do -+ * this we set a safe divider (the underclocking is not of -+ * interest as we can go as low as 32KHz). The relation -+ * b/w this clock and its parents are as follows: -+ * -+ * FRAC PLL -> DIV PLL -> MCK DIV -+ * -+ * With the proper safe divider we should be good even with FRAC -+ * PLL at its maximum value. -+ */ -+ ret = regmap_read(master_div->regmap, master_div->layout->offset, -+ &mckr); -+ if (ret) { -+ ret = NOTIFY_STOP_MASK; -+ goto unlock; -+ } -+ -+ mckr &= master_div->layout->mask; -+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; -+ -+ /* Switch to safe divider. */ -+ clk_master_div_set(master_div, -+ cnd->old_rate * characteristics->divisors[div], -+ master_div->safe_div); -+ break; -+ -+ case POST_RATE_CHANGE: -+ /* -+ * At this point we want to restore MCK DIV domain to its maximum -+ * allowed rate. -+ */ -+ ret = regmap_read(master_div->regmap, master_div->layout->offset, -+ &mckr); -+ if (ret) { -+ ret = NOTIFY_STOP_MASK; -+ goto unlock; -+ } -+ -+ mckr &= master_div->layout->mask; -+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; -+ new_parent_rate = cnd->new_rate * characteristics->divisors[div]; -+ -+ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) { -+ if (!characteristics->divisors[i]) -+ break; -+ -+ new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate, -+ characteristics->divisors[i]); -+ -+ tmp_diff = characteristics->output.max - new_rate; -+ if (tmp_diff < 0) -+ continue; -+ -+ if (best_diff < 0 || best_diff > tmp_diff) { -+ new_div = characteristics->divisors[i]; -+ best_diff = tmp_diff; -+ } -+ -+ if (!tmp_diff) -+ break; -+ } -+ -+ if (!new_div) { -+ ret = NOTIFY_STOP_MASK; -+ goto unlock; -+ } -+ -+ /* Update the div to preserve MCK DIV clock rate. */ -+ clk_master_div_set(master_div, new_parent_rate, -+ new_div); -+ -+ ret = NOTIFY_OK; -+ break; -+ -+ default: -+ ret = NOTIFY_DONE; -+ break; -+ } -+ -+unlock: -+ spin_unlock_irqrestore(master_div->lock, flags); -+ -+ return ret; -+} -+ -+static struct notifier_block clk_master_div_notifier = { -+ .notifier_call = clk_master_div_notifier_fn, -+}; -+ - static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, - struct clk_hw *parent, - unsigned long parent_rate, -@@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct - struct clk_master *master; - struct clk_init_data init; - struct clk_hw *hw; -+ unsigned int mckr; -+ unsigned long irqflags; - int ret; - - if (!name || !num_parents || !parent_names || !lock) -@@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct - master->chg_pid = chg_pid; - master->lock = lock; - -+ if (ops == &master_div_ops_chg) { -+ spin_lock_irqsave(master->lock, irqflags); -+ regmap_read(master->regmap, master->layout->offset, &mckr); -+ spin_unlock_irqrestore(master->lock, irqflags); -+ -+ mckr &= layout->mask; -+ mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; -+ master->div = characteristics->divisors[mckr]; -+ } -+ - hw = &master->hw; - ret = clk_hw_register(NULL, &master->hw); - if (ret) { -@@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regm - const char *name, const char *parent_name, - const struct clk_master_layout *layout, - const struct clk_master_characteristics *characteristics, -- spinlock_t *lock, u32 flags) -+ spinlock_t *lock, u32 flags, u32 safe_div) - { - const struct clk_ops *ops; -+ struct clk_hw *hw; - - if (flags & CLK_SET_RATE_GATE) - ops = &master_div_ops; - else - ops = &master_div_ops_chg; - -- return at91_clk_register_master_internal(regmap, name, 1, -- &parent_name, layout, -- characteristics, ops, -- lock, flags, -EINVAL); -+ hw = at91_clk_register_master_internal(regmap, name, 1, -+ &parent_name, layout, -+ characteristics, ops, -+ lock, flags, -EINVAL); -+ -+ if (!IS_ERR(hw) && safe_div) { -+ master_div = to_clk_master(hw); -+ master_div->safe_div = safe_div; -+ clk_notifier_register(hw->clk, -+ &clk_master_div_notifier); -+ } -+ -+ return hw; - } - - static unsigned long ---- a/drivers/clk/at91/dt-compat.c -+++ b/drivers/clk/at91/dt-compat.c -@@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_n - - hw = at91_clk_register_master_div(regmap, name, "masterck_pres", - layout, characteristics, -- &mck_lock, CLK_SET_RATE_GATE); -+ &mck_lock, CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto out_free_characteristics; - ---- a/drivers/clk/at91/pmc.h -+++ b/drivers/clk/at91/pmc.h -@@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regm - const char *parent_names, - const struct clk_master_layout *layout, - const struct clk_master_characteristics *characteristics, -- spinlock_t *lock, u32 flags); -+ spinlock_t *lock, u32 flags, u32 safe_div); - - struct clk_hw * __init - at91_clk_sama7g5_register_master(struct regmap *regmap, ---- a/drivers/clk/at91/sama5d2.c -+++ b/drivers/clk/at91/sama5d2.c -@@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(str - "masterck_pres", - &at91sam9x5_master_layout, - &mck_characteristics, &mck_lock, -- CLK_SET_RATE_GATE); -+ CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/sama5d3.c -+++ b/drivers/clk/at91/sama5d3.c -@@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(str - "masterck_pres", - &at91sam9x5_master_layout, - &mck_characteristics, &mck_lock, -- CLK_SET_RATE_GATE); -+ CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/sama5d4.c -+++ b/drivers/clk/at91/sama5d4.c -@@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(str - "masterck_pres", - &at91sam9x5_master_layout, - &mck_characteristics, &mck_lock, -- CLK_SET_RATE_GATE); -+ CLK_SET_RATE_GATE, 0); - if (IS_ERR(hw)) - goto err_free; - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -1003,7 +1003,7 @@ static void __init sama7g5_pmc_setup(str - - hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", - &mck0_layout, &mck0_characteristics, -- &pmc_mck0_lock, 0); -+ &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); - if (IS_ERR(hw)) - goto err_free; - diff --git a/target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch b/target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch deleted file mode 100644 index 1ae5076da9..0000000000 --- a/target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 91a49481af7332853c4c921d46aded8210572210 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:17 +0300 -Subject: [PATCH 245/247] clk: at91: sama7g5: remove prescaler part of master - clock - -On SAMA7G5 the prescaler part of master clock has been implemented as a -changeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit -must be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is -done. Driver polls for this bit until it becomes 1. On SAMA7G5 it has -been discovered that in some conditions the PMC_SR.MCKRDY is not rising -but the rate it provides it's stable. The workaround is to add a timeout -when polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler -will be removed from Linux clock tree as all the frequencies for CPU could -be obtained from PLL and also there will be less overhead when changing -frequency via DVFS. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 11 +---------- - 1 file changed, 1 insertion(+), 10 deletions(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -992,16 +992,7 @@ static void __init sama7g5_pmc_setup(str - } - - parent_names[0] = "cpupll_divpmcck"; -- hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names, -- &mck0_layout, &mck0_characteristics, -- &pmc_mck0_lock, -- CLK_SET_RATE_PARENT, 0); -- if (IS_ERR(hw)) -- goto err_free; -- -- sama7g5_pmc->chws[PMC_CPU] = hw; -- -- hw = at91_clk_register_master_div(regmap, "mck0", "cpuck", -+ hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck", - &mck0_layout, &mck0_characteristics, - &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); - if (IS_ERR(hw)) diff --git a/target/linux/at91/patches-5.10/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch b/target/linux/at91/patches-5.10/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch deleted file mode 100644 index 922cf0b69c..0000000000 --- a/target/linux/at91/patches-5.10/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 9fd5a49f6da9de5da83f4a53eccefad647ab15ed Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:18 +0300 -Subject: [PATCH 246/247] clk: at91: sama7g5: set low limit for mck0 at 32KHz - -MCK0 could go as low as 32KHz. Set this limit. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -Signed-off-by: Stephen Boyd ---- - drivers/clk/at91/sama7g5.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/at91/sama7g5.c -+++ b/drivers/clk/at91/sama7g5.c -@@ -850,7 +850,7 @@ static const struct { - - /* MCK0 characteristics. */ - static const struct clk_master_characteristics mck0_characteristics = { -- .output = { .min = 50000000, .max = 200000000 }, -+ .output = { .min = 32768, .max = 200000000 }, - .divisors = { 1, 2, 4, 3, 5 }, - .have_div3_pres = 1, - }; diff --git a/target/linux/at91/patches-5.10/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch b/target/linux/at91/patches-5.10/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch deleted file mode 100644 index 436fa18362..0000000000 --- a/target/linux/at91/patches-5.10/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch +++ /dev/null @@ -1,32 +0,0 @@ -From fe07791494a78d5a4be1363385e6ba7940740644 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Mon, 11 Oct 2021 14:27:19 +0300 -Subject: [PATCH 247/247] clk: use clk_core_get_rate_recalc() in clk_rate_get() - -In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get() -will return the cached rate. Thus, use clk_core_get_rate_recalc() which -takes proper action when clock flags contains CLK_GET_RATE_NOCACHE. - -Signed-off-by: Claudiu Beznea -Link: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.com -Acked-by: Nicolas Ferre -[sboyd@kernel.org: Grab prepare lock around operation] -Signed-off-by: Stephen Boyd ---- - drivers/clk/clk.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/clk/clk.c -+++ b/drivers/clk/clk.c -@@ -3116,7 +3116,10 @@ static int clk_rate_get(void *data, u64 - { - struct clk_core *core = data; - -- *val = core->rate; -+ clk_prepare_lock(); -+ *val = clk_core_get_rate_recalc(core); -+ clk_prepare_unlock(); -+ - return 0; - } - diff --git a/target/linux/at91/patches-5.10/99-scripts-fix-compilation-error.patch b/target/linux/at91/patches-5.10/99-scripts-fix-compilation-error.patch deleted file mode 100644 index 711c7dfbcc..0000000000 --- a/target/linux/at91/patches-5.10/99-scripts-fix-compilation-error.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 6d18eaaaff92f928eab6fad2708b6d28785b4872 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 13 Oct 2021 08:32:07 +0300 -Subject: [PATCH] scripts: fix compilation error - -Signed-off-by: Claudiu Beznea ---- - scripts/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/scripts/Makefile -+++ b/scripts/Makefile -@@ -21,7 +21,7 @@ HOSTCFLAGS_asn1_compiler.o = -I$(srctree - HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS) - HOSTLDLIBS_sign-file = $(CRYPTO_LIBS) - HOSTCFLAGS_extract-cert.o = $(CRYPTO_CFLAGS) --HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) -+HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) -lpthread - - ifdef CONFIG_UNWINDER_ORC - ifeq ($(ARCH),x86_64) diff --git a/target/linux/at91/sam9x/config-5.10 b/target/linux/at91/sam9x/config-5.10 deleted file mode 100644 index 73ee93f2ae..0000000000 --- a/target/linux/at91/sam9x/config-5.10 +++ /dev/null @@ -1,312 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_AT91=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_MULTI_V4 is not set -CONFIG_ARCH_MULTI_V4T=y -CONFIG_ARCH_MULTI_V4_V5=y -CONFIG_ARCH_MULTI_V5=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -# CONFIG_AT91RM9200_WATCHDOG is not set -CONFIG_AT91SAM9X_WATCHDOG=y -# CONFIG_AT91_ADC is not set -CONFIG_AT91_SAMA5D2_ADC=y -CONFIG_AT91_SOC_ID=y -# CONFIG_AT91_SOC_SFR is not set -CONFIG_ATMEL_AIC5_IRQ=y -CONFIG_ATMEL_AIC_IRQ=y -CONFIG_ATMEL_CLOCKSOURCE_PIT=y -CONFIG_ATMEL_CLOCKSOURCE_TCB=y -CONFIG_ATMEL_EBI=y -CONFIG_ATMEL_PIT=y -CONFIG_ATMEL_PM=y -CONFIG_ATMEL_SDRAMC=y -CONFIG_ATMEL_SSC=y -CONFIG_ATMEL_ST=y -CONFIG_ATMEL_TCB_CLKSRC=y -CONFIG_ATMEL_TCLIB=y -CONFIG_AT_HDMAC=y -CONFIG_AT_XDMAC=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_PM=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_AT91=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CPU_32v4T=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV4T=y -CONFIG_CPU_ABRT_EV5TJ=y -CONFIG_CPU_ARM920T=y -CONFIG_CPU_ARM926T=y -# CONFIG_CPU_CACHE_ROUND_ROBIN is not set -CONFIG_CPU_CACHE_V4WT=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -CONFIG_CPU_NO_EFFICIENT_FFS=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_PM=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V4WBI=y -CONFIG_CPU_USE_DOMAINS=y -CONFIG_CRC16=y -CONFIG_CRC7=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_EXT4_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_ATMEL=y -CONFIG_HZ=128 -CONFIG_HZ_FIXED=128 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_AT91=y -# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_GPIO=y -CONFIG_IIO=y -CONFIG_IIO_BUFFER=y -CONFIG_IIO_KFIFO_BUF=y -CONFIG_IIO_TRIGGER=y -CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACB=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MFD_AT91_USART=y -CONFIG_MFD_ATMEL_FLEXCOM=y -CONFIG_MFD_ATMEL_HLCDC=y -CONFIG_MFD_ATMEL_SMC=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MICREL_PHY=y -CONFIG_MICROCHIP_PIT64B=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_ATMELMCI=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_AT91=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_DATAFLASH=y -# CONFIG_MTD_DATAFLASH_OTP is not set -# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -# CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_GLUEBI=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_KUSER_HELPERS=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NLS=y -CONFIG_NVMEM=y -# CONFIG_NVMEM_MICROCHIP_OTPC is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_AT91=y -# CONFIG_PINCTRL_AT91PIO4 is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_SLEEP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_AT91_POWEROFF=y -CONFIG_POWER_RESET_AT91_RESET=y -CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y -CONFIG_POWER_SUPPLY=y -CONFIG_PWM=y -CONFIG_PWM_ATMEL=y -CONFIG_PWM_ATMEL_HLCDC_PWM=y -CONFIG_PWM_ATMEL_TCB=y -CONFIG_PWM_SYSFS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AT91RM9200=y -CONFIG_RTC_DRV_AT91SAM9=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SAMA5D4_WATCHDOG=y -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_ATMEL=y -CONFIG_SERIAL_ATMEL_CONSOLE=y -CONFIG_SERIAL_ATMEL_PDC=y -# CONFIG_SERIAL_ATMEL_TTYAT is not set -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SOC_AT91RM9200=y -CONFIG_SOC_AT91SAM9=y -CONFIG_SOC_BUS=y -CONFIG_SOC_SAM9X60=y -CONFIG_SOC_SAM_V4_V5=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -# CONFIG_SPI_AT91_USART is not set -CONFIG_SPI_ATMEL=y -CONFIG_SPI_ATMEL_QUADSPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPLIT_PTLOCK_CPUS=999999 -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_ACM=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_AT91 is not set -# CONFIG_USB_ATMEL_USBA is not set -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_AT91=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_GADGET=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_AT91=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_SERIAL=y -# CONFIG_USB_SERIAL_CONSOLE is not set -CONFIG_USB_SERIAL_FTDI_SIO=y -CONFIG_USB_SERIAL_PL2303=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_XXHASH=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/at91/sama5/config-5.10 b/target/linux/at91/sama5/config-5.10 deleted file mode 100644 index 42db74c621..0000000000 --- a/target/linux/at91/sama5/config-5.10 +++ /dev/null @@ -1,488 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_AT91=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_AT91_CPUIDLE=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_AT91SAM9X_WATCHDOG=y -CONFIG_AT91_ADC=y -CONFIG_AT91_SAMA5D2_ADC=y -CONFIG_AT91_SOC_ID=y -# CONFIG_AT91_SOC_SFR is not set -CONFIG_ATMEL_AIC5_IRQ=y -# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set -CONFIG_ATMEL_CLOCKSOURCE_TCB=y -CONFIG_ATMEL_EBI=y -CONFIG_ATMEL_PM=y -CONFIG_ATMEL_SDRAMC=y -CONFIG_ATMEL_SSC=y -CONFIG_ATMEL_TCB_CLKSRC=y -CONFIG_ATMEL_TCLIB=y -CONFIG_AT_HDMAC=y -CONFIG_AT_XDMAC=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BATTERY_ACT8945A=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=4 -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_CACHE_L2X0=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_AT91=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_COREDUMP=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DEBUG_USER=y -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DNOTIFY=y -CONFIG_DRM=y -CONFIG_DRM_ATMEL_HLCDC=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_KMS_CMA_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_SIMPLE=y -CONFIG_DTC=y -CONFIG_DVB_CORE=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_ELF_CORE=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -CONFIG_FAT_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FORCE_MAX_ZONEORDER=15 -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_ATMEL=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_AT91=y -# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_IIO=y -CONFIG_IIO_BUFFER=y -CONFIG_IIO_KFIFO_BUF=y -CONFIG_IIO_TRIGGER=y -CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -# CONFIG_JFFS2_FS is not set -CONFIG_KCMP=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_XZ is not set -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_QT1070=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACB=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MANDATORY_FILE_LOCKING=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_TEST_SUPPORT=y -CONFIG_MEDIA_TUNER=y -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_ACT8945A=y -CONFIG_MFD_AT91_USART=y -CONFIG_MFD_ATMEL_FLEXCOM=y -CONFIG_MFD_ATMEL_HLCDC=y -CONFIG_MFD_ATMEL_SMC=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MICREL_PHY=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_ATMELMCI=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_AT91=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -# CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -# CONFIG_NEON is not set -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NVMEM=y -# CONFIG_NVMEM_MICROCHIP_OTPC is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_AT91=y -CONFIG_PINCTRL_AT91PIO4=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_SLEEP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_AT91_POWEROFF=y -CONFIG_POWER_RESET_AT91_RESET=y -CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y -CONFIG_POWER_SUPPLY=y -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_PRINTK_TIME=y -CONFIG_PROC_VMCORE=y -CONFIG_PWM=y -CONFIG_PWM_ATMEL=y -CONFIG_PWM_ATMEL_HLCDC_PWM=y -CONFIG_PWM_ATMEL_TCB=y -CONFIG_PWM_SYSFS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_ACT8865=y -CONFIG_REGULATOR_ACT8945A=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AT91RM9200=y -# CONFIG_RTC_DRV_AT91SAM9 is not set -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_SAMA5D4_WATCHDOG=y -CONFIG_SCSI=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_ATMEL=y -CONFIG_SERIAL_ATMEL_CONSOLE=y -CONFIG_SERIAL_ATMEL_PDC=y -# CONFIG_SERIAL_ATMEL_TTYAT is not set -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SND=y -CONFIG_SND_ARM=y -# CONFIG_SND_AT73C213 is not set -# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set -# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set -CONFIG_SND_ATMEL_SOC=y -CONFIG_SND_ATMEL_SOC_CLASSD=y -CONFIG_SND_ATMEL_SOC_DMA=y -CONFIG_SND_ATMEL_SOC_I2S=y -CONFIG_SND_ATMEL_SOC_PDC=y -# CONFIG_SND_ATMEL_SOC_PDMIC is not set -CONFIG_SND_ATMEL_SOC_SSC=y -CONFIG_SND_ATMEL_SOC_SSC_DMA=y -# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set -# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set -CONFIG_SND_ATMEL_SOC_WM8904=y -# CONFIG_SND_COMPRESS_OFFLOAD is not set -CONFIG_SND_DMAENGINE_PCM=y -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -# CONFIG_SND_MCHP_SOC_I2S_MCC is not set -# CONFIG_SND_MCHP_SOC_SPDIFRX is not set -# CONFIG_SND_MCHP_SOC_SPDIFTX is not set -CONFIG_SND_PCM=y -CONFIG_SND_PCM_TIMER=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -CONFIG_SND_SOC_MIKROE_PROTO=y -# CONFIG_SND_SOC_PCM5102A is not set -CONFIG_SND_SOC_WM8731=y -CONFIG_SND_SOC_WM8904=y -CONFIG_SND_SPI=y -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_TIMER=y -CONFIG_SOC_BUS=y -CONFIG_SOC_SAMA5=y -CONFIG_SOC_SAMA5D2=y -CONFIG_SOC_SAMA5D3=y -CONFIG_SOC_SAMA5D4=y -# CONFIG_SOC_SAMA7G5 is not set -CONFIG_SOC_SAM_V7=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -# CONFIG_SPI_AT91_USART is not set -CONFIG_SPI_ATMEL=y -CONFIG_SPI_ATMEL_QUADSPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SQUASHFS is not set -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -# CONFIG_STANDALONE is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -# CONFIG_SWP_EMULATE is not set -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y -CONFIG_TOUCHSCREEN_PROPERTIES=y -CONFIG_UACCESS_WITH_MEMCPY=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_ACM=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -# CONFIG_USB_AT91 is not set -# CONFIG_USB_ATMEL_USBA is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_AT91=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_GADGET=y -CONFIG_USB_HID=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_AT91=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -# CONFIG_USB_PWC is not set -CONFIG_USB_SERIAL=y -# CONFIG_USB_SERIAL_CONSOLE is not set -CONFIG_USB_SERIAL_FTDI_SIO=y -CONFIG_USB_SERIAL_PL2303=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEOMODE_HELPERS=y -# CONFIG_VIDEO_CPIA2 is not set -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L2_I2C=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XXHASH=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/at91/sama7/config-5.10 b/target/linux/at91/sama7/config-5.10 deleted file mode 100644 index dbf7914a6a..0000000000 --- a/target/linux/at91/sama7/config-5.10 +++ /dev/null @@ -1,396 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_ALLOW_DEV_COREDUMP is not set -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_AT91=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_PATCH_IDIV is not set -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -# CONFIG_AT91SAM9X_WATCHDOG is not set -# CONFIG_AT91_ADC is not set -CONFIG_AT91_SAMA5D2_ADC=y -CONFIG_AT91_SOC_ID=y -# CONFIG_AT91_SOC_SFR is not set -CONFIG_ATMEL_CLOCKSOURCE_TCB=y -# CONFIG_ATMEL_EBI is not set -CONFIG_ATMEL_SDRAMC=y -CONFIG_ATMEL_TCB_CLKSRC=y -# CONFIG_ATMEL_TCLIB is not set -# CONFIG_AT_HDMAC is not set -CONFIG_AT_XDMAC=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=1 -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_SCSI_REQUEST=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CAN=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=9 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=256 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel" -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_AT91=y -# CONFIG_COMPACTION is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_SPECTRE=y -# CONFIG_CPU_SW_DOMAIN_PAN is not set -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y -CONFIG_DEBUG_AT91_UART=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/at91.S" -CONFIG_DEBUG_UART_PHYS=0xe1824200 -CONFIG_DEBUG_UART_VIRT=0xe0824200 -# CONFIG_DEBUG_UNCOMPRESS is not set -CONFIG_DEBUG_USER=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_CMA=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -# CONFIG_EFI_PARTITION is not set -CONFIG_EXT4_FS=y -CONFIG_FANOTIFY=y -CONFIG_FAT_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FORCE_MAX_ZONEORDER=15 -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GRACE_PERIOD=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_AT91=y -# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_IIO=y -CONFIG_IIO_BUFFER=y -CONFIG_IIO_CONFIGFS=y -# CONFIG_IIO_HRTIMER_TRIGGER is not set -CONFIG_IIO_KFIFO_BUF=y -CONFIG_IIO_SW_TRIGGER=y -# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set -CONFIG_IIO_TRIGGER=y -CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_BOOTP is not set -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_RARP is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCKD=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_LSM="N" -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACB=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_SUPPORT_FILTER=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_AT91_USART=y -CONFIG_MFD_ATMEL_FLEXCOM=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MICREL_PHY=y -CONFIG_MICROCHIP_PIT64B=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -# CONFIG_MMC_ATMELMCI is not set -CONFIG_MMC_BLOCK=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_AT91=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NEON=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NFS_FS=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NVMEM=y -# CONFIG_NVMEM_MICROCHIP_OTPC is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCCARD=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_AT91=y -CONFIG_PINCTRL_AT91PIO4=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_AT91_POWEROFF is not set -CONFIG_POWER_RESET_AT91_RESET=y -CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_PRINTK_TIME=y -CONFIG_PWM=y -CONFIG_PWM_ATMEL=y -CONFIG_PWM_SYSFS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MCP16502=y -CONFIG_ROOT_NFS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_AT91RM9200=y -CONFIG_RTC_DRV_AT91SAM9=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_SAMA5D4_WATCHDOG=y -CONFIG_SCSI=y -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_ATMEL=y -CONFIG_SERIAL_ATMEL_CONSOLE=y -CONFIG_SERIAL_ATMEL_PDC=y -# CONFIG_SERIAL_ATMEL_TTYAT is not set -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SND=y -CONFIG_SND_ATMEL_SOC=y -# CONFIG_SND_ATMEL_SOC_CLASSD is not set -# CONFIG_SND_ATMEL_SOC_I2S is not set -# CONFIG_SND_ATMEL_SOC_PDMIC is not set -# CONFIG_SND_COMPRESS_OFFLOAD is not set -CONFIG_SND_DMAENGINE_PCM=y -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -CONFIG_SND_MCHP_SOC_I2S_MCC=y -CONFIG_SND_MCHP_SOC_SPDIFRX=y -CONFIG_SND_MCHP_SOC_SPDIFTX=y -CONFIG_SND_PCM=y -CONFIG_SND_SIMPLE_CARD=y -CONFIG_SND_SIMPLE_CARD_UTILS=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_MIKROE_PROTO is not set -CONFIG_SND_SOC_PCM5102A=y -CONFIG_SND_SOC_SPDIF=y -CONFIG_SOC_BUS=y -# CONFIG_SOC_SAMA5D2 is not set -# CONFIG_SOC_SAMA5D3 is not set -# CONFIG_SOC_SAMA5D4 is not set -CONFIG_SOC_SAMA7=y -CONFIG_SOC_SAMA7G5=y -CONFIG_SOC_SAM_V7=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -# CONFIG_SPI_AT91_USART is not set -CONFIG_SPI_ATMEL=y -# CONFIG_SPI_ATMEL_QUADSPI is not set -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -# CONFIG_STANDALONE is not set -CONFIG_SUNRPC=y -# CONFIG_SWAP is not set -CONFIG_SWPHY=y -# CONFIG_SWP_EMULATE is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_UACCESS_WITH_MEMCPY=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USE_OF=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -# CONFIG_VIDEO_ATMEL_XISC is not set -CONFIG_VIDEO_DEV=y -CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L2_I2C=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/ath25/config-5.10 b/target/linux/ath25/config-5.10 deleted file mode 100644 index ef764820e4..0000000000 --- a/target/linux/ath25/config-5.10 +++ /dev/null @@ -1,128 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_AR2315_WDT=y -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ATH25=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -# CONFIG_COMMON_CLK is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R1=y -CONFIG_CPU_MIPSR1=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FORCE_PCI=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_AR2315=y -CONFIG_GPIO_AR5312=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IP17XX_PHY=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LEDS_GPIO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y -CONFIG_MIPS_EBPF_JIT=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_AR2315=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -# CONFIG_MTD_CFI_GEOMETRY is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_MYLOADER_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3 -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MVSWITCH_PHY=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_AR231X=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -# CONFIG_OF is not set -CONFIG_PCI=y -CONFIG_PCI_AR2315=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SOC_AR2315=y -CONFIG_SOC_AR5312=y -CONFIG_SRCU=y -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_TARGET_ISA_REV=1 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y diff --git a/target/linux/ath25/patches-5.10/107-ar5312_gpio.patch b/target/linux/ath25/patches-5.10/107-ar5312_gpio.patch deleted file mode 100644 index a1efdbeeae..0000000000 --- a/target/linux/ath25/patches-5.10/107-ar5312_gpio.patch +++ /dev/null @@ -1,212 +0,0 @@ ---- a/arch/mips/ath25/Kconfig -+++ b/arch/mips/ath25/Kconfig -@@ -2,6 +2,7 @@ - config SOC_AR5312 - bool "Atheros AR5312/AR2312+ SoC support" - depends on ATH25 -+ select GPIO_AR5312 - default y - - config SOC_AR2315 ---- a/arch/mips/ath25/ar5312.c -+++ b/arch/mips/ath25/ar5312.c -@@ -23,6 +23,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -178,6 +179,22 @@ static struct platform_device ar5312_phy - .num_resources = 1, - }; - -+static struct resource ar5312_gpio_res[] = { -+ { -+ .name = "ar5312-gpio", -+ .flags = IORESOURCE_MEM, -+ .start = AR5312_GPIO_BASE, -+ .end = AR5312_GPIO_BASE + AR5312_GPIO_SIZE - 1, -+ }, -+}; -+ -+static struct platform_device ar5312_gpio = { -+ .name = "ar5312-gpio", -+ .id = -1, -+ .resource = ar5312_gpio_res, -+ .num_resources = ARRAY_SIZE(ar5312_gpio_res), -+}; -+ - static void __init ar5312_flash_init(void) - { - void __iomem *flashctl_base; -@@ -245,6 +262,8 @@ void __init ar5312_init_devices(void) - - platform_device_register(&ar5312_physmap_flash); - -+ platform_device_register(&ar5312_gpio); -+ - switch (ath25_soc) { - case ATH25_SOC_AR5312: - if (!ath25_board.radio) ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -142,6 +142,13 @@ config GPIO_AMDPT - driver for GPIO functionality on Promontory IOHub - Require ACPI ASL code to enumerate as a platform device. - -+config GPIO_AR5312 -+ bool "AR5312 SoC GPIO support" -+ default y if SOC_AR5312 -+ depends on SOC_AR5312 -+ help -+ Say yes here to enable GPIO support for Atheros AR5312/AR2312+ SoCs. -+ - config GPIO_ASPEED - tristate "Aspeed GPIO support" - depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-alt - obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o - obj-$(CONFIG_GPIO_AMD_FCH) += gpio-amd-fch.o - obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o -+obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o - obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o - obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o - obj-$(CONFIG_GPIO_ASPEED_SGPIO) += gpio-aspeed-sgpio.o ---- /dev/null -+++ b/drivers/gpio/gpio-ar5312.c -@@ -0,0 +1,121 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * Copyright (C) 2012 Alexandros C. Couloumbis -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#define DRIVER_NAME "ar5312-gpio" -+ -+#define AR5312_GPIO_DO 0x00 /* output register */ -+#define AR5312_GPIO_DI 0x04 /* intput register */ -+#define AR5312_GPIO_CR 0x08 /* control register */ -+ -+#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */ -+#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */ -+#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ -+#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ -+ -+#define AR5312_GPIO_NUM 8 -+ -+static void __iomem *ar5312_mem; -+ -+static inline u32 ar5312_gpio_reg_read(unsigned reg) -+{ -+ return __raw_readl(ar5312_mem + reg); -+} -+ -+static inline void ar5312_gpio_reg_write(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar5312_mem + reg); -+} -+ -+static inline void ar5312_gpio_reg_mask(unsigned reg, u32 mask, u32 val) -+{ -+ ar5312_gpio_reg_write(reg, (ar5312_gpio_reg_read(reg) & ~mask) | val); -+} -+ -+static int ar5312_gpio_get_val(struct gpio_chip *chip, unsigned gpio) -+{ -+ return (ar5312_gpio_reg_read(AR5312_GPIO_DI) >> gpio) & 1; -+} -+ -+static void ar5312_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val) -+{ -+ u32 reg = ar5312_gpio_reg_read(AR5312_GPIO_DO); -+ -+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio); -+ ar5312_gpio_reg_write(AR5312_GPIO_DO, reg); -+} -+ -+static int ar5312_gpio_dir_in(struct gpio_chip *chip, unsigned gpio) -+{ -+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 0, 1 << gpio); -+ return 0; -+} -+ -+static int ar5312_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val) -+{ -+ ar5312_gpio_reg_mask(AR5312_GPIO_CR, 1 << gpio, 0); -+ ar5312_gpio_set_val(chip, gpio, val); -+ return 0; -+} -+ -+static struct gpio_chip ar5312_gpio_chip = { -+ .label = DRIVER_NAME, -+ .direction_input = ar5312_gpio_dir_in, -+ .direction_output = ar5312_gpio_dir_out, -+ .set = ar5312_gpio_set_val, -+ .get = ar5312_gpio_get_val, -+ .base = 0, -+ .ngpio = AR5312_GPIO_NUM, -+}; -+ -+static int ar5312_gpio_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ int ret; -+ -+ if (ar5312_mem) -+ return -EBUSY; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ ar5312_mem = devm_ioremap_resource(dev, res); -+ if (IS_ERR(ar5312_mem)) -+ return PTR_ERR(ar5312_mem); -+ -+ ar5312_gpio_chip.parent = dev; -+ ret = gpiochip_add(&ar5312_gpio_chip); -+ if (ret) { -+ dev_err(dev, "failed to add gpiochip\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver ar5312_gpio_driver = { -+ .probe = ar5312_gpio_probe, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ } -+}; -+ -+static int __init ar5312_gpio_init(void) -+{ -+ return platform_driver_register(&ar5312_gpio_driver); -+} -+subsys_initcall(ar5312_gpio_init); ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -219,6 +219,7 @@ config ATH25 - select CEVT_R4K - select CSRC_R4K - select DMA_NONCOHERENT -+ select GPIOLIB - select IRQ_MIPS_CPU - select IRQ_DOMAIN - select SYS_HAS_CPU_MIPS32_R1 diff --git a/target/linux/ath25/patches-5.10/108-ar2315_gpio.patch b/target/linux/ath25/patches-5.10/108-ar2315_gpio.patch deleted file mode 100644 index 10289086e8..0000000000 --- a/target/linux/ath25/patches-5.10/108-ar2315_gpio.patch +++ /dev/null @@ -1,363 +0,0 @@ ---- a/arch/mips/ath25/Kconfig -+++ b/arch/mips/ath25/Kconfig -@@ -8,6 +8,7 @@ config SOC_AR5312 - config SOC_AR2315 - bool "Atheros AR2315+ SoC support" - depends on ATH25 -+ select GPIO_AR2315 - default y - - config PCI_AR2315 ---- a/arch/mips/ath25/ar2315.c -+++ b/arch/mips/ath25/ar2315.c -@@ -22,6 +22,8 @@ - #include - #include - #include -+#include -+#include - #include - #include - #include -@@ -165,11 +167,42 @@ void __init ar2315_arch_init_irq(void) - ar2315_misc_irq_domain = domain; - } - -+static struct resource ar2315_gpio_res[] = { -+ { -+ .name = "ar2315-gpio", -+ .flags = IORESOURCE_MEM, -+ .start = AR2315_RST_BASE + AR2315_GPIO, -+ .end = AR2315_RST_BASE + AR2315_GPIO + 0x10 - 1, -+ }, -+ { -+ .name = "ar2315-gpio", -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "ar2315-gpio-irq-base", -+ .flags = IORESOURCE_IRQ, -+ .start = AR231X_GPIO_IRQ_BASE, -+ .end = AR231X_GPIO_IRQ_BASE, -+ } -+}; -+ -+static struct platform_device ar2315_gpio = { -+ .id = -1, -+ .name = "ar2315-gpio", -+ .resource = ar2315_gpio_res, -+ .num_resources = ARRAY_SIZE(ar2315_gpio_res) -+}; -+ - void __init ar2315_init_devices(void) - { - /* Find board configuration */ - ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE); - -+ ar2315_gpio_res[1].start = irq_create_mapping(ar2315_misc_irq_domain, -+ AR2315_MISC_IRQ_GPIO); -+ ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; -+ platform_device_register(&ar2315_gpio); -+ - ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0); - } - -@@ -185,8 +218,8 @@ static void ar2315_restart(char *command - /* Cold reset does not work on the AR2315/6, use the GPIO reset bits - * a workaround. Give it some time to attempt a gpio based hardware - * reset (atheros reference design workaround) */ -- -- /* TODO: implement the GPIO reset workaround */ -+ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset"); -+ mdelay(100); - - /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic - * workaround. Attempt to jump to the mips reset location - ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -142,6 +142,13 @@ config GPIO_AMDPT - driver for GPIO functionality on Promontory IOHub - Require ACPI ASL code to enumerate as a platform device. - -+config GPIO_AR2315 -+ bool "AR2315 SoC GPIO support" -+ default y if SOC_AR2315 -+ depends on SOC_AR2315 -+ help -+ Say yes here to enable GPIO support for Atheros AR2315+ SoCs. -+ - config GPIO_AR5312 - bool "AR5312 SoC GPIO support" - default y if SOC_AR5312 ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_GPIO_ALTERA) += gpio-alt - obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o - obj-$(CONFIG_GPIO_AMD_FCH) += gpio-amd-fch.o - obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o -+obj-$(CONFIG_GPIO_AR2315) += gpio-ar2315.o - obj-$(CONFIG_GPIO_AR5312) += gpio-ar5312.o - obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o - obj-$(CONFIG_GPIO_ASPEED) += gpio-aspeed.o ---- /dev/null -+++ b/drivers/gpio/gpio-ar2315.c -@@ -0,0 +1,233 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ * Copyright (C) 2012 Alexandros C. Couloumbis -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define DRIVER_NAME "ar2315-gpio" -+ -+#define AR2315_GPIO_DI 0x0000 -+#define AR2315_GPIO_DO 0x0008 -+#define AR2315_GPIO_DIR 0x0010 -+#define AR2315_GPIO_INT 0x0018 -+ -+#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */ -+#define AR2315_GPIO_DIR_I(x) (0) /* input */ -+ -+#define AR2315_GPIO_INT_NUM_M 0x3F /* mask for GPIO num */ -+#define AR2315_GPIO_INT_TRIG(x) ((x) << 6) /* interrupt trigger */ -+#define AR2315_GPIO_INT_TRIG_M (0x3 << 6) /* mask for int trig */ -+ -+#define AR2315_GPIO_INT_TRIG_OFF 0 /* Triggerring off */ -+#define AR2315_GPIO_INT_TRIG_LOW 1 /* Low Level Triggered */ -+#define AR2315_GPIO_INT_TRIG_HIGH 2 /* High Level Triggered */ -+#define AR2315_GPIO_INT_TRIG_EDGE 3 /* Edge Triggered */ -+ -+#define AR2315_GPIO_NUM 22 -+ -+static u32 ar2315_gpio_intmask; -+static u32 ar2315_gpio_intval; -+static unsigned ar2315_gpio_irq_base; -+static void __iomem *ar2315_mem; -+ -+static inline u32 ar2315_gpio_reg_read(unsigned reg) -+{ -+ return __raw_readl(ar2315_mem + reg); -+} -+ -+static inline void ar2315_gpio_reg_write(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar2315_mem + reg); -+} -+ -+static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val) -+{ -+ ar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val); -+} -+ -+static void ar2315_gpio_irq_handler(struct irq_desc *desc) -+{ -+ u32 pend; -+ int bit = -1; -+ -+ /* only do one gpio interrupt at a time */ -+ pend = ar2315_gpio_reg_read(AR2315_GPIO_DI); -+ pend ^= ar2315_gpio_intval; -+ pend &= ar2315_gpio_intmask; -+ -+ if (pend) { -+ bit = fls(pend) - 1; -+ pend &= ~(1 << bit); -+ ar2315_gpio_intval ^= (1 << bit); -+ } -+ -+ /* Enable interrupt with edge detection */ -+ if ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) != -+ AR2315_GPIO_DIR_I(bit)) -+ return; -+ -+ if (bit >= 0) -+ generic_handle_irq(ar2315_gpio_irq_base + bit); -+} -+ -+static void ar2315_gpio_int_setup(unsigned gpio, int trig) -+{ -+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT); -+ -+ reg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M); -+ reg |= gpio | AR2315_GPIO_INT_TRIG(trig); -+ ar2315_gpio_reg_write(AR2315_GPIO_INT, reg); -+} -+ -+static void ar2315_gpio_irq_unmask(struct irq_data *d) -+{ -+ unsigned gpio = d->irq - ar2315_gpio_irq_base; -+ u32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR); -+ -+ /* Enable interrupt with edge detection */ -+ if ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio)) -+ return; -+ -+ ar2315_gpio_intmask |= (1 << gpio); -+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE); -+} -+ -+static void ar2315_gpio_irq_mask(struct irq_data *d) -+{ -+ unsigned gpio = d->irq - ar2315_gpio_irq_base; -+ -+ /* Disable interrupt */ -+ ar2315_gpio_intmask &= ~(1 << gpio); -+ ar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF); -+} -+ -+static struct irq_chip ar2315_gpio_irq_chip = { -+ .name = DRIVER_NAME, -+ .irq_unmask = ar2315_gpio_irq_unmask, -+ .irq_mask = ar2315_gpio_irq_mask, -+}; -+ -+static void ar2315_gpio_irq_init(unsigned irq) -+{ -+ unsigned i; -+ -+ ar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI); -+ for (i = 0; i < AR2315_GPIO_NUM; i++) { -+ unsigned _irq = ar2315_gpio_irq_base + i; -+ -+ irq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip, -+ handle_level_irq); -+ } -+ irq_set_chained_handler(irq, ar2315_gpio_irq_handler); -+} -+ -+static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio) -+{ -+ return (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1; -+} -+ -+static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val) -+{ -+ u32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO); -+ -+ reg = val ? reg | (1 << gpio) : reg & ~(1 << gpio); -+ ar2315_gpio_reg_write(AR2315_GPIO_DO, reg); -+} -+ -+static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio) -+{ -+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0); -+ return 0; -+} -+ -+static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val) -+{ -+ ar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio); -+ ar2315_gpio_set_val(chip, gpio, val); -+ return 0; -+} -+ -+static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) -+{ -+ return ar2315_gpio_irq_base + gpio; -+} -+ -+static struct gpio_chip ar2315_gpio_chip = { -+ .label = DRIVER_NAME, -+ .direction_input = ar2315_gpio_dir_in, -+ .direction_output = ar2315_gpio_dir_out, -+ .set = ar2315_gpio_set_val, -+ .get = ar2315_gpio_get_val, -+ .to_irq = ar2315_gpio_to_irq, -+ .base = 0, -+ .ngpio = AR2315_GPIO_NUM, -+}; -+ -+static int ar2315_gpio_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ unsigned irq; -+ int ret; -+ -+ if (ar2315_mem) -+ return -EBUSY; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, -+ "ar2315-gpio-irq-base"); -+ if (!res) { -+ dev_err(dev, "not found GPIO IRQ base\n"); -+ return -ENXIO; -+ } -+ ar2315_gpio_irq_base = res->start; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME); -+ if (!res) { -+ dev_err(dev, "not found IRQ number\n"); -+ return -ENXIO; -+ } -+ irq = res->start; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME); -+ ar2315_mem = devm_ioremap_resource(dev, res); -+ if (IS_ERR(ar2315_mem)) -+ return PTR_ERR(ar2315_mem); -+ -+ ar2315_gpio_chip.parent = dev; -+ ret = gpiochip_add(&ar2315_gpio_chip); -+ if (ret) { -+ dev_err(dev, "failed to add gpiochip\n"); -+ return ret; -+ } -+ -+ ar2315_gpio_irq_init(irq); -+ -+ return 0; -+} -+ -+static struct platform_driver ar2315_gpio_driver = { -+ .probe = ar2315_gpio_probe, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ } -+}; -+ -+static int __init ar2315_gpio_init(void) -+{ -+ return platform_driver_register(&ar2315_gpio_driver); -+} -+subsys_initcall(ar2315_gpio_init); ---- a/arch/mips/ath25/devices.h -+++ b/arch/mips/ath25/devices.h -@@ -4,6 +4,11 @@ - - #include - -+#define AR231X_GPIO_IRQ_BASE 0x30 -+ -+/* GPIO number for AR2315/16 reset issue workaround */ -+#define AR2315_RESET_GPIO 5 -+ - #define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S) - - #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */ ---- a/arch/mips/ath25/ar2315_regs.h -+++ b/arch/mips/ath25/ar2315_regs.h -@@ -315,6 +315,9 @@ - #define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018 - #define AR2315_MEM_CFG_BANKADDR_BITS_S 3 - -+/* GPIO MMR base address */ -+#define AR2315_GPIO 0x0088 -+ - /* - * Local Bus Interface Registers - */ diff --git a/target/linux/ath25/patches-5.10/110-ar2313_ethernet.patch b/target/linux/ath25/patches-5.10/110-ar2313_ethernet.patch deleted file mode 100644 index 72b8660baa..0000000000 --- a/target/linux/ath25/patches-5.10/110-ar2313_ethernet.patch +++ /dev/null @@ -1,1735 +0,0 @@ ---- a/drivers/net/ethernet/atheros/Makefile -+++ b/drivers/net/ethernet/atheros/Makefile -@@ -9,3 +9,4 @@ obj-$(CONFIG_ATL2) += atlx/ - obj-$(CONFIG_ATL1E) += atl1e/ - obj-$(CONFIG_ATL1C) += atl1c/ - obj-$(CONFIG_ALX) += alx/ -+obj-$(CONFIG_NET_AR231X) += ar231x/ ---- a/drivers/net/ethernet/atheros/Kconfig -+++ b/drivers/net/ethernet/atheros/Kconfig -@@ -6,7 +6,7 @@ - config NET_VENDOR_ATHEROS - bool "Atheros devices" - default y -- depends on (PCI || ATH79) -+ depends on (PCI || ATH25 || ATH79) - help - If you have a network (Ethernet) card belonging to this class, say Y. - -@@ -87,4 +87,10 @@ config ALX - To compile this driver as a module, choose M here. The module - will be called alx. - -+config NET_AR231X -+ tristate "Atheros AR231X built-in Ethernet support" -+ depends on ATH25 -+ help -+ Support for the AR231x/531x ethernet controller -+ - endif # NET_VENDOR_ATHEROS ---- /dev/null -+++ b/drivers/net/ethernet/atheros/ar231x/Makefile -@@ -0,0 +1 @@ -+obj-$(CONFIG_NET_AR231X) += ar231x.o ---- /dev/null -+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c -@@ -0,0 +1,1119 @@ -+/* -+ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Additional credits: -+ * This code is taken from John Taylor's Sibyte driver and then -+ * modified for the AR2313. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define AR2313_MTU 1692 -+#define AR2313_PRIOS 1 -+#define AR2313_QUEUES (2*AR2313_PRIOS) -+#define AR2313_DESCR_ENTRIES 64 -+ -+#ifndef min -+#define min(a, b) (((a) < (b)) ? (a) : (b)) -+#endif -+ -+#ifndef SMP_CACHE_BYTES -+#define SMP_CACHE_BYTES L1_CACHE_BYTES -+#endif -+ -+#define AR2313_MBOX_SET_BIT 0x8 -+ -+#include "ar231x.h" -+ -+/** -+ * New interrupt handler strategy: -+ * -+ * An old interrupt handler worked using the traditional method of -+ * replacing an skbuff with a new one when a packet arrives. However -+ * the rx rings do not need to contain a static number of buffer -+ * descriptors, thus it makes sense to move the memory allocation out -+ * of the main interrupt handler and do it in a bottom half handler -+ * and only allocate new buffers when the number of buffers in the -+ * ring is below a certain threshold. In order to avoid starving the -+ * NIC under heavy load it is however necessary to force allocation -+ * when hitting a minimum threshold. The strategy for alloction is as -+ * follows: -+ * -+ * RX_LOW_BUF_THRES - allocate buffers in the bottom half -+ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate -+ * the buffers in the interrupt handler -+ * RX_RING_THRES - maximum number of buffers in the rx ring -+ * -+ * One advantagous side effect of this allocation approach is that the -+ * entire rx processing can be done without holding any spin lock -+ * since the rx rings and registers are totally independent of the tx -+ * ring and its registers. This of course includes the kmalloc's of -+ * new skb's. Thus start_xmit can run in parallel with rx processing -+ * and the memory allocation on SMP systems. -+ * -+ * Note that running the skb reallocation in a bottom half opens up -+ * another can of races which needs to be handled properly. In -+ * particular it can happen that the interrupt handler tries to run -+ * the reallocation while the bottom half is either running on another -+ * CPU or was interrupted on the same CPU. To get around this the -+ * driver uses bitops to prevent the reallocation routines from being -+ * reentered. -+ * -+ * TX handling can also be done without holding any spin lock, wheee -+ * this is fun! since tx_csm is only written to by the interrupt -+ * handler. -+ */ -+ -+/** -+ * Threshold values for RX buffer allocation - the low water marks for -+ * when to start refilling the rings are set to 75% of the ring -+ * sizes. It seems to make sense to refill the rings entirely from the -+ * intrrupt handler once it gets below the panic threshold, that way -+ * we don't risk that the refilling is moved to another CPU when the -+ * one running the interrupt handler just got the slab code hot in its -+ * cache. -+ */ -+#define RX_RING_SIZE AR2313_DESCR_ENTRIES -+#define RX_PANIC_THRES (RX_RING_SIZE/4) -+#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) -+#define CRC_LEN 4 -+#define RX_OFFSET 2 -+ -+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) -+#define VLAN_HDR 4 -+#else -+#define VLAN_HDR 0 -+#endif -+ -+#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \ -+ RX_OFFSET) -+ -+#ifdef MODULE -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); -+MODULE_DESCRIPTION("AR231x Ethernet driver"); -+#endif -+ -+#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) -+ -+/* prototypes */ -+static void ar231x_halt(struct net_device *dev); -+static void rx_tasklet_func(unsigned long data); -+static void rx_tasklet_cleanup(struct net_device *dev); -+static void ar231x_multicast_list(struct net_device *dev); -+static void ar231x_tx_timeout(struct net_device *dev, unsigned int txqueue); -+ -+static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); -+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, -+ u16 value); -+static int ar231x_mdiobus_reset(struct mii_bus *bus); -+static int ar231x_mdiobus_probe(struct net_device *dev); -+static void ar231x_adjust_link(struct net_device *dev); -+ -+#ifndef ERR -+#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) -+#endif -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+static void -+ar231x_netpoll(struct net_device *dev) -+{ -+ unsigned long flags; -+ -+ local_irq_save(flags); -+ ar231x_interrupt(dev->irq, dev); -+ local_irq_restore(flags); -+} -+#endif -+ -+static const struct net_device_ops ar231x_ops = { -+ .ndo_open = ar231x_open, -+ .ndo_stop = ar231x_close, -+ .ndo_start_xmit = ar231x_start_xmit, -+ .ndo_set_rx_mode = ar231x_multicast_list, -+ .ndo_do_ioctl = ar231x_ioctl, -+ .ndo_validate_addr = eth_validate_addr, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_tx_timeout = ar231x_tx_timeout, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = ar231x_netpoll, -+#endif -+}; -+ -+static int ar231x_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct ar231x_private *sp; -+ struct resource *res; -+ unsigned long ar_eth_base; -+ char buf[64]; -+ -+ dev = alloc_etherdev(sizeof(struct ar231x_private)); -+ -+ if (dev == NULL) { -+ printk(KERN_ERR -+ "ar231x: Unable to allocate net_device structure!\n"); -+ return -ENOMEM; -+ } -+ -+ platform_set_drvdata(pdev, dev); -+ -+ SET_NETDEV_DEV(dev, &pdev->dev); -+ -+ sp = netdev_priv(dev); -+ sp->dev = dev; -+ sp->pdev = pdev; -+ sp->cfg = pdev->dev.platform_data; -+ -+ sprintf(buf, "eth%d_membase", pdev->id); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); -+ if (!res) -+ return -ENODEV; -+ -+ sp->link = 0; -+ ar_eth_base = res->start; -+ -+ sprintf(buf, "eth%d_irq", pdev->id); -+ dev->irq = platform_get_irq_byname(pdev, buf); -+ -+ spin_lock_init(&sp->lock); -+ -+ dev->features |= NETIF_F_HIGHDMA; -+ dev->netdev_ops = &ar231x_ops; -+ -+ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long)dev); -+ tasklet_disable(&sp->rx_tasklet); -+ -+ sp->eth_regs = ioremap(ar_eth_base, sizeof(*sp->eth_regs)); -+ if (!sp->eth_regs) { -+ printk("Can't remap eth registers\n"); -+ return -ENXIO; -+ } -+ -+ /** -+ * When there's only one MAC, PHY regs are typically on ENET0, -+ * even though the MAC might be on ENET1. -+ * So remap PHY regs separately. -+ */ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii"); -+ if (!res) { -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, -+ "eth1_mii"); -+ if (!res) -+ return -ENODEV; -+ } -+ sp->phy_regs = ioremap(res->start, resource_size(res)); -+ if (!sp->phy_regs) { -+ printk("Can't remap phy registers\n"); -+ return -ENXIO; -+ } -+ -+ sp->dma_regs = ioremap(ar_eth_base + 0x1000, -+ sizeof(*sp->dma_regs)); -+ if (!sp->dma_regs) { -+ printk("Can't remap DMA registers\n"); -+ return -ENXIO; -+ } -+ dev->base_addr = ar_eth_base + 0x1000; -+ -+ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); -+ sp->name[sizeof(sp->name) - 1] = '\0'; -+ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); -+ -+ if (ar231x_init(dev)) { -+ /* ar231x_init() calls ar231x_init_cleanup() on error */ -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ if (register_netdev(dev)) { -+ printk("%s: register_netdev failed\n", __func__); -+ return -1; -+ } -+ -+ printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr, -+ dev->irq); -+ -+ sp->mii_bus = mdiobus_alloc(); -+ if (sp->mii_bus == NULL) -+ return -1; -+ -+ sp->mii_bus->priv = dev; -+ sp->mii_bus->read = ar231x_mdiobus_read; -+ sp->mii_bus->write = ar231x_mdiobus_write; -+ sp->mii_bus->reset = ar231x_mdiobus_reset; -+ sp->mii_bus->name = "ar231x_eth_mii"; -+ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); -+ -+ mdiobus_register(sp->mii_bus); -+ -+ if (ar231x_mdiobus_probe(dev) != 0) { -+ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static void ar231x_multicast_list(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int filter; -+ -+ filter = sp->eth_regs->mac_control; -+ -+ if (dev->flags & IFF_PROMISC) -+ filter |= MAC_CONTROL_PR; -+ else -+ filter &= ~MAC_CONTROL_PR; -+ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) -+ filter |= MAC_CONTROL_PM; -+ else -+ filter &= ~MAC_CONTROL_PM; -+ -+ sp->eth_regs->mac_control = filter; -+} -+ -+static void rx_tasklet_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ /** -+ * Tasklet may be scheduled. Need to get it removed from the list -+ * since we're about to free the struct. -+ */ -+ -+ sp->unloading = 1; -+ tasklet_enable(&sp->rx_tasklet); -+ tasklet_kill(&sp->rx_tasklet); -+} -+ -+static int ar231x_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ mdiobus_unregister(sp->mii_bus); -+ mdiobus_free(sp->mii_bus); -+ kfree(dev); -+ return 0; -+} -+ -+/** -+ * Restart the AR2313 ethernet controller. -+ */ -+static int ar231x_restart(struct net_device *dev) -+{ -+ /* disable interrupts */ -+ disable_irq(dev->irq); -+ -+ /* stop mac */ -+ ar231x_halt(dev); -+ -+ /* initialize */ -+ ar231x_init(dev); -+ -+ /* enable interrupts */ -+ enable_irq(dev->irq); -+ -+ return 0; -+} -+ -+static struct platform_driver ar231x_driver = { -+ .driver.name = "ar231x-eth", -+ .probe = ar231x_probe, -+ .remove = ar231x_remove, -+}; -+ -+module_platform_driver(ar231x_driver); -+ -+static void ar231x_free_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ if (sp->rx_ring != NULL) { -+ kfree((void *)KSEG0ADDR(sp->rx_ring)); -+ sp->rx_ring = NULL; -+ sp->tx_ring = NULL; -+ } -+} -+ -+static int ar231x_allocate_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int size; -+ int j; -+ ar231x_descr_t *space; -+ -+ if (sp->rx_ring != NULL) { -+ printk("%s: already done.\n", __func__); -+ return 0; -+ } -+ -+ size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES); -+ space = kmalloc(size, GFP_KERNEL); -+ if (space == NULL) -+ return 1; -+ -+ /* invalidate caches */ -+ dma_cache_inv((unsigned int)space, size); -+ -+ /* now convert pointer to KSEG1 */ -+ space = (ar231x_descr_t *)KSEG1ADDR(space); -+ -+ memset((void *)space, 0, size); -+ -+ sp->rx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ sp->tx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ /* Initialize the transmit Descriptors */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ ar231x_descr_t *td = &sp->tx_ring[j]; -+ -+ td->status = 0; -+ td->devcs = DMA_TX1_CHAINED; -+ td->addr = 0; -+ td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]); -+ } -+ -+ return 0; -+} -+ -+/** -+ * Generic cleanup handling data allocated during init. Used when the -+ * module is unloaded or if an error occurs during initialization -+ */ -+static void ar231x_init_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb; -+ int j; -+ -+ ar231x_free_descriptors(dev); -+ -+ if (sp->eth_regs) -+ iounmap((void *)sp->eth_regs); -+ if (sp->dma_regs) -+ iounmap((void *)sp->dma_regs); -+ if (sp->phy_regs) -+ iounmap((void *)sp->phy_regs); -+ -+ if (sp->rx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->rx_skb[j]; -+ if (skb) { -+ sp->rx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->rx_skb); -+ sp->rx_skb = NULL; -+ } -+ -+ if (sp->tx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ sp->tx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->tx_skb); -+ sp->tx_skb = NULL; -+ } -+} -+ -+static int ar231x_reset_reg(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ unsigned int flags; -+ -+ sp->cfg->reset_set(sp->cfg->reset_mac); -+ mdelay(10); -+ sp->cfg->reset_clear(sp->cfg->reset_mac); -+ mdelay(10); -+ sp->cfg->reset_set(sp->cfg->reset_phy); -+ mdelay(10); -+ sp->cfg->reset_clear(sp->cfg->reset_phy); -+ mdelay(10); -+ -+ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); -+ mdelay(10); -+ sp->dma_regs->bus_mode = -+ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); -+ -+ /* enable interrupts */ -+ sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS | -+ DMA_STATUS_RI | DMA_STATUS_TI | -+ DMA_STATUS_FBE; -+ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); -+ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); -+ sp->dma_regs->control = -+ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); -+ -+ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); -+ sp->eth_regs->vlan_tag = (0x8100); -+ -+ /* Enable Ethernet Interface */ -+ flags = (MAC_CONTROL_TE | /* transmit enable */ -+ MAC_CONTROL_PM | /* pass mcast */ -+ MAC_CONTROL_F | /* full duplex */ -+ MAC_CONTROL_HBD); /* heart beat disabled */ -+ -+ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ -+ flags |= MAC_CONTROL_PR; -+ } -+ sp->eth_regs->mac_control = flags; -+ -+ /* Set all Ethernet station address registers to their initial values */ -+ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF); -+ -+ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ return 0; -+} -+ -+static int ar231x_init(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int ecode = 0; -+ -+ /* Allocate descriptors */ -+ if (ar231x_allocate_descriptors(dev)) { -+ printk("%s: %s: ar231x_allocate_descriptors failed\n", -+ dev->name, __func__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ -+ /* Get the memory for the skb rings */ -+ if (sp->rx_skb == NULL) { -+ sp->rx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->rx_skb)) { -+ printk("%s: %s: rx_skb kmalloc failed\n", -+ dev->name, __func__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ if (sp->tx_skb == NULL) { -+ sp->tx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->tx_skb)) { -+ printk("%s: %s: tx_skb kmalloc failed\n", -+ dev->name, __func__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ /** -+ * Set tx_csm before we start receiving interrupts, otherwise -+ * the interrupt handler might think it is supposed to process -+ * tx ints before we are up and running, which may cause a null -+ * pointer access in the int handler. -+ */ -+ sp->rx_skbprd = 0; -+ sp->cur_rx = 0; -+ sp->tx_prd = 0; -+ sp->tx_csm = 0; -+ -+ /* Zero the stats before starting the interface */ -+ memset(&dev->stats, 0, sizeof(dev->stats)); -+ -+ /** -+ * We load the ring here as there seem to be no way to tell the -+ * firmware to wipe the ring without re-initializing it. -+ */ -+ ar231x_load_rx_ring(dev, RX_RING_SIZE); -+ -+ /* Init hardware */ -+ ar231x_reset_reg(dev); -+ -+ /* Get the IRQ */ -+ ecode = request_irq(dev->irq, &ar231x_interrupt, 0, -+ dev->name, dev); -+ if (ecode) { -+ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", -+ dev->name, __func__, dev->irq); -+ goto init_error; -+ } -+ -+ tasklet_enable(&sp->rx_tasklet); -+ -+ return 0; -+ -+init_error: -+ ar231x_init_cleanup(dev); -+ return ecode; -+} -+ -+/** -+ * Load the rx ring. -+ * -+ * Loading rings is safe without holding the spin lock since this is -+ * done only before the device is enabled, thus no interrupts are -+ * generated and by the interrupt handler/tasklet handler. -+ */ -+static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ short i, idx; -+ -+ idx = sp->rx_skbprd; -+ -+ for (i = 0; i < nr_bufs; i++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *rd; -+ -+ if (sp->rx_skb[idx]) -+ break; -+ -+ skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE); -+ if (!skb) { -+ printk("\n\n\n\n %s: No memory in system\n\n\n\n", -+ __func__); -+ break; -+ } -+ -+ /* Make sure IP header starts on a fresh cache line */ -+ skb->dev = dev; -+ sp->rx_skb[idx] = skb; -+ -+ rd = (ar231x_descr_t *)&sp->rx_ring[idx]; -+ -+ /* initialize dma descriptor */ -+ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rd->addr = virt_to_phys(skb->data); -+ rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]); -+ rd->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ if (i) -+ sp->rx_skbprd = idx; -+} -+ -+#define AR2313_MAX_PKTS_PER_CALL 64 -+ -+static int ar231x_rx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb, *skb_new; -+ ar231x_descr_t *rxdesc; -+ unsigned int status; -+ u32 idx; -+ int pkts = 0; -+ int rval; -+ -+ idx = sp->cur_rx; -+ -+ /* process at most the entire ring and then wait for another int */ -+ while (1) { -+ rxdesc = &sp->rx_ring[idx]; -+ status = rxdesc->status; -+ -+ if (status & DMA_RX_OWN) { -+ /* SiByte owns descriptor or descr not yet filled in */ -+ rval = 0; -+ break; -+ } -+ -+ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { -+ rval = 1; -+ break; -+ } -+ -+ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { -+ dev->stats.rx_errors++; -+ dev->stats.rx_dropped++; -+ -+ /* add statistics counters */ -+ if (status & DMA_RX_ERR_CRC) -+ dev->stats.rx_crc_errors++; -+ if (status & DMA_RX_ERR_COL) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_LENGTH) -+ dev->stats.rx_length_errors++; -+ if (status & DMA_RX_ERR_RUNT) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_DESC) -+ dev->stats.rx_over_errors++; -+ -+ } else { -+ /* alloc new buffer. */ -+ skb_new = netdev_alloc_skb_ip_align(dev, -+ AR2313_BUFSIZE); -+ if (skb_new != NULL) { -+ skb = sp->rx_skb[idx]; -+ /* set skb */ -+ skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) & -+ 0x3fff) - CRC_LEN); -+ -+ dev->stats.rx_bytes += skb->len; -+ skb->protocol = eth_type_trans(skb, dev); -+ /* pass the packet to upper layers */ -+ netif_rx(skb); -+ -+ skb_new->dev = dev; -+ /* reset descriptor's curr_addr */ -+ rxdesc->addr = virt_to_phys(skb_new->data); -+ -+ dev->stats.rx_packets++; -+ sp->rx_skb[idx] = skb_new; -+ } else { -+ dev->stats.rx_dropped++; -+ } -+ } -+ -+ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rxdesc->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ sp->cur_rx = idx; -+ -+ return rval; -+} -+ -+static void ar231x_tx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ u32 idx; -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ unsigned int status = 0; -+ -+ idx = sp->tx_csm; -+ -+ while (idx != sp->tx_prd) { -+ txdesc = &sp->tx_ring[idx]; -+ status = txdesc->status; -+ -+ if (status & DMA_TX_OWN) { -+ /* ar231x dma still owns descr */ -+ break; -+ } -+ /* done with this descriptor */ -+ dma_unmap_single(&sp->pdev->dev, txdesc->addr, -+ txdesc->devcs & DMA_TX1_BSIZE_MASK, -+ DMA_TO_DEVICE); -+ txdesc->status = 0; -+ -+ if (status & DMA_TX_ERROR) { -+ dev->stats.tx_errors++; -+ dev->stats.tx_dropped++; -+ if (status & DMA_TX_ERR_UNDER) -+ dev->stats.tx_fifo_errors++; -+ if (status & DMA_TX_ERR_HB) -+ dev->stats.tx_heartbeat_errors++; -+ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) -+ dev->stats.tx_carrier_errors++; -+ if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL | -+ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) -+ dev->stats.tx_aborted_errors++; -+ } else { -+ /* transmit OK */ -+ dev->stats.tx_packets++; -+ } -+ -+ skb = sp->tx_skb[idx]; -+ sp->tx_skb[idx] = NULL; -+ idx = DSC_NEXT(idx); -+ dev->stats.tx_bytes += skb->len; -+ dev_kfree_skb_irq(skb); -+ } -+ -+ sp->tx_csm = idx; -+} -+ -+static void rx_tasklet_func(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *)data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ if (sp->unloading) -+ return; -+ -+ if (ar231x_rx_int(dev)) { -+ tasklet_hi_schedule(&sp->rx_tasklet); -+ } else { -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sp->lock, flags); -+ sp->dma_regs->intr_ena |= DMA_STATUS_RI; -+ spin_unlock_irqrestore(&sp->lock, flags); -+ } -+} -+ -+static void rx_schedule(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; -+ -+ tasklet_hi_schedule(&sp->rx_tasklet); -+} -+ -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id) -+{ -+ struct net_device *dev = (struct net_device *)dev_id; -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int status, enabled; -+ -+ /* clear interrupt */ -+ /* Don't clear RI bit if currently disabled */ -+ status = sp->dma_regs->status; -+ enabled = sp->dma_regs->intr_ena; -+ sp->dma_regs->status = status & enabled; -+ -+ if (status & DMA_STATUS_NIS) { -+ /* normal status */ -+ /** -+ * Don't schedule rx processing if interrupt -+ * is already disabled. -+ */ -+ if (status & enabled & DMA_STATUS_RI) { -+ /* receive interrupt */ -+ rx_schedule(dev); -+ } -+ if (status & DMA_STATUS_TI) { -+ /* transmit interrupt */ -+ ar231x_tx_int(dev); -+ } -+ } -+ -+ /* abnormal status */ -+ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) -+ ar231x_restart(dev); -+ -+ return IRQ_HANDLED; -+} -+ -+static int ar231x_open(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ -+ /* reset the hardware, in case the MAC address changed */ -+ ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF); -+ -+ ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ dev->mtu = 1500; -+ netif_start_queue(dev); -+ -+ sp->eth_regs->mac_control |= MAC_CONTROL_RE; -+ -+ phy_start(sp->phy_dev); -+ -+ return 0; -+} -+ -+static void ar231x_tx_timeout(struct net_device *dev, unsigned int txqueue) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sp->lock, flags); -+ ar231x_restart(dev); -+ spin_unlock_irqrestore(&sp->lock, flags); -+} -+ -+static void ar231x_halt(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int j; -+ -+ tasklet_disable(&sp->rx_tasklet); -+ -+ /* kill the MAC */ -+ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ -+ MAC_CONTROL_TE); /* disable Transmits */ -+ /* stop dma */ -+ sp->dma_regs->control = 0; -+ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; -+ -+ /* place phy and MAC in reset */ -+ sp->cfg->reset_set(sp->cfg->reset_mac); -+ sp->cfg->reset_set(sp->cfg->reset_phy); -+ -+ /* free buffers on tx ring */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ -+ txdesc = &sp->tx_ring[j]; -+ txdesc->descr = 0; -+ -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ dev_kfree_skb(skb); -+ sp->tx_skb[j] = NULL; -+ } -+ } -+} -+ -+/** -+ * close should do nothing. Here's why. It's called when -+ * 'ifconfig bond0 down' is run. If it calls free_irq then -+ * the irq is gone forever ! When bond0 is made 'up' again, -+ * the ar231x_open () does not call request_irq (). Worse, -+ * the call to ar231x_halt() generates a WDOG reset due to -+ * the write to reset register and the box reboots. -+ * Commenting this out is good since it allows the -+ * system to resume when bond0 is made up again. -+ */ -+static int ar231x_close(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+#if 0 -+ /* Disable interrupts */ -+ disable_irq(dev->irq); -+ -+ /** -+ * Without (or before) releasing irq and stopping hardware, this -+ * is an absolute non-sense, by the way. It will be reset instantly -+ * by the first irq. -+ */ -+ netif_stop_queue(dev); -+ -+ /* stop the MAC and DMA engines */ -+ ar231x_halt(dev); -+ -+ /* release the interrupt */ -+ free_irq(dev->irq, dev); -+ -+#endif -+ -+ phy_stop(sp->phy_dev); -+ -+ return 0; -+} -+ -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ ar231x_descr_t *td; -+ u32 idx; -+ -+ idx = sp->tx_prd; -+ td = &sp->tx_ring[idx]; -+ -+ if (td->status & DMA_TX_OWN) { -+ /* free skbuf and lie to the caller that we sent it out */ -+ dev->stats.tx_dropped++; -+ dev_kfree_skb(skb); -+ -+ /* restart transmitter in case locked */ -+ sp->dma_regs->xmt_poll = 0; -+ return 0; -+ } -+ -+ /* Setup the transmit descriptor. */ -+ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | -+ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); -+ td->addr = dma_map_single(&sp->pdev->dev, skb->data, skb->len, DMA_TO_DEVICE); -+ td->status = DMA_TX_OWN; -+ -+ /* kick transmitter last */ -+ sp->dma_regs->xmt_poll = 0; -+ -+ sp->tx_skb[idx] = skb; -+ idx = DSC_NEXT(idx); -+ sp->tx_prd = idx; -+ -+ return 0; -+} -+ -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ switch (cmd) { -+ case SIOCGMIIPHY: -+ case SIOCGMIIREG: -+ case SIOCSMIIREG: -+ return phy_mii_ioctl(sp->phy_dev, ifr, cmd); -+ -+ default: -+ break; -+ } -+ -+ return -EOPNOTSUPP; -+} -+ -+static void ar231x_adjust_link(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct phy_device *phydev = sp->phy_dev; -+ u32 mc; -+ -+ if (!phydev->link) { -+ if (sp->link) { -+ pr_info("%s: link down\n", dev->name); -+ sp->link = 0; -+ } -+ return; -+ } -+ sp->link = 1; -+ -+ pr_info("%s: link up (%uMbps/%s duplex)\n", dev->name, -+ phydev->speed, phydev->duplex ? "full" : "half"); -+ -+ mc = sp->eth_regs->mac_control; -+ if (phydev->duplex) -+ mc = (mc | MAC_CONTROL_F) & ~MAC_CONTROL_DRO; -+ else -+ mc = (mc | MAC_CONTROL_DRO) & ~MAC_CONTROL_F; -+ sp->eth_regs->mac_control = mc; -+ sp->duplex = phydev->duplex; -+} -+ -+#define MII_ADDR(phy, reg) \ -+ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) -+ -+static int -+ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile MII *ethernet = sp->phy_regs; -+ -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); -+ while (ethernet->mii_addr & MII_ADDR_BUSY) -+ ; -+ return ethernet->mii_data >> MII_DATA_SHIFT; -+} -+ -+static int -+ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile MII *ethernet = sp->phy_regs; -+ -+ while (ethernet->mii_addr & MII_ADDR_BUSY) -+ ; -+ ethernet->mii_data = value << MII_DATA_SHIFT; -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_reset(struct mii_bus *bus) -+{ -+ struct net_device *const dev = bus->priv; -+ -+ ar231x_reset_reg(dev); -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_probe(struct net_device *dev) -+{ -+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; -+ struct ar231x_private *const sp = netdev_priv(dev); -+ struct phy_device *phydev = NULL; -+ -+ /* find the first (lowest address) PHY on the current MAC's MII bus */ -+ phydev = phy_find_first(sp->mii_bus); -+ if (!phydev) { -+ printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name); -+ return -1; -+ } -+ -+ /* now we are supposed to have a proper phydev, to attach to... */ -+ BUG_ON(phydev->attached_dev); -+ -+ phydev = phy_connect(dev, phydev_name(phydev), &ar231x_adjust_link, -+ PHY_INTERFACE_MODE_MII); -+ if (IS_ERR(phydev)) { -+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); -+ return PTR_ERR(phydev); -+ } -+ -+ /* mask with MAC supported features */ -+ linkmode_set_bit_array(phy_10_100_features_array, -+ ARRAY_SIZE(phy_10_100_features_array), -+ mask); -+ linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask); -+ linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask); -+ linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask); -+ -+ linkmode_and(phydev->supported, phydev->supported, mask); -+ linkmode_copy(phydev->advertising, phydev->supported); -+ -+ sp->phy_dev = phydev; -+ -+ printk(KERN_INFO "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", -+ dev->name, phydev->drv->name, phydev_name(phydev)); -+ -+ return 0; -+} -+ ---- /dev/null -+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h -@@ -0,0 +1,282 @@ -+/* -+ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#ifndef _AR2313_H_ -+#define _AR2313_H_ -+ -+#include -+#include -+#include -+#include -+ -+/* probe link timer - 5 secs */ -+#define LINK_TIMER (5*HZ) -+ -+#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) -+#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) -+#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) -+ -+#define AR2313_TX_TIMEOUT (HZ/4) -+ -+/* Rings */ -+#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) -+#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) -+ -+#define AR2313_MBGET 2 -+#define AR2313_MBSET 3 -+#define AR2313_PCI_RECONFIG 4 -+#define AR2313_PCI_DUMP 5 -+#define AR2313_TEST_PANIC 6 -+#define AR2313_TEST_NULLPTR 7 -+#define AR2313_READ_DATA 8 -+#define AR2313_WRITE_DATA 9 -+#define AR2313_GET_VERSION 10 -+#define AR2313_TEST_HANG 11 -+#define AR2313_SYNC 12 -+ -+#define DMA_RX_ERR_CRC BIT(1) -+#define DMA_RX_ERR_DRIB BIT(2) -+#define DMA_RX_ERR_MII BIT(3) -+#define DMA_RX_EV2 BIT(5) -+#define DMA_RX_ERR_COL BIT(6) -+#define DMA_RX_LONG BIT(7) -+#define DMA_RX_LS BIT(8) /* last descriptor */ -+#define DMA_RX_FS BIT(9) /* first descriptor */ -+#define DMA_RX_MF BIT(10) /* multicast frame */ -+#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ -+#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ -+#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ -+#define DMA_RX_ERROR BIT(15) /* error summary */ -+#define DMA_RX_LEN_MASK 0x3fff0000 -+#define DMA_RX_LEN_SHIFT 16 -+#define DMA_RX_FILT BIT(30) -+#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ -+ -+#define DMA_RX1_BSIZE_MASK 0x000007ff -+#define DMA_RX1_BSIZE_SHIFT 0 -+#define DMA_RX1_CHAINED BIT(24) -+#define DMA_RX1_RER BIT(25) -+ -+#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ -+#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ -+#define DMA_TX_COL_MASK 0x78 -+#define DMA_TX_COL_SHIFT 3 -+#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ -+#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ -+#define DMA_TX_ERR_LATE BIT(9) /* late collision */ -+#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ -+#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ -+#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ -+#define DMA_TX_ERROR BIT(15) /* frame aborted */ -+#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ -+ -+#define DMA_TX1_BSIZE_MASK 0x000007ff -+#define DMA_TX1_BSIZE_SHIFT 0 -+#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ -+#define DMA_TX1_TER BIT(25) /* transmit end of ring */ -+#define DMA_TX1_FS BIT(29) /* first segment */ -+#define DMA_TX1_LS BIT(30) /* last segment */ -+#define DMA_TX1_IC BIT(31) /* interrupt on completion */ -+ -+#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ -+ -+#define MAC_CONTROL_RE BIT(2) /* receive enable */ -+#define MAC_CONTROL_TE BIT(3) /* transmit enable */ -+#define MAC_CONTROL_DC BIT(5) /* Deferral check */ -+#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ -+#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ -+#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ -+#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ -+#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ -+#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ -+#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ -+#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ -+#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ -+#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */ -+#define MAC_CONTROL_PM BIT(19) /* pass multicast */ -+#define MAC_CONTROL_F BIT(20) /* full-duplex */ -+#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ -+#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ -+#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ -+#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */ -+ -+#define MII_ADDR_BUSY BIT(0) -+#define MII_ADDR_WRITE BIT(1) -+#define MII_ADDR_REG_SHIFT 6 -+#define MII_ADDR_PHY_SHIFT 11 -+#define MII_DATA_SHIFT 0 -+ -+#define FLOW_CONTROL_FCE BIT(1) -+ -+#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ -+#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ -+#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ -+#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ -+ -+#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ -+#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ -+#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ -+#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ -+#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ -+#define DMA_STATUS_RI BIT(6) /* receive interrupt */ -+#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ -+#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ -+#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ -+#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ -+#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ -+#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ -+#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ -+#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ -+#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ -+#define DMA_STATUS_EB_SHIFT 23 /* error bits */ -+ -+#define DMA_CONTROL_SR BIT(1) /* start receive */ -+#define DMA_CONTROL_ST BIT(13) /* start transmit */ -+#define DMA_CONTROL_SF BIT(21) /* store and forward */ -+ -+typedef struct { -+ volatile unsigned int status; /* OWN, Device control and status. */ -+ volatile unsigned int devcs; /* pkt Control bits + Length */ -+ volatile unsigned int addr; /* Current Address. */ -+ volatile unsigned int descr; /* Next descriptor in chain. */ -+} ar231x_descr_t; -+ -+/** -+ * New Combo structure for Both Eth0 AND eth1 -+ * -+ * Don't directly access MII related regs since phy chip could be actually -+ * connected to another ethernet block. -+ */ -+typedef struct { -+ volatile unsigned int mac_control; /* 0x00 */ -+ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ -+ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ -+ volatile unsigned int __mii_addr; /* 0x14 */ -+ volatile unsigned int __mii_data; /* 0x18 */ -+ volatile unsigned int flow_control; /* 0x1c */ -+ volatile unsigned int vlan_tag; /* 0x20 */ -+ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ -+ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ -+} ETHERNET_STRUCT; -+ -+typedef struct { -+ volatile unsigned int mii_addr; -+ volatile unsigned int mii_data; -+} MII; -+ -+/******************************************************************** -+ * Interrupt controller -+ ********************************************************************/ -+ -+typedef struct { -+ volatile unsigned int wdog_control; /* 0x08 */ -+ volatile unsigned int wdog_timer; /* 0x0c */ -+ volatile unsigned int misc_status; /* 0x10 */ -+ volatile unsigned int misc_mask; /* 0x14 */ -+ volatile unsigned int global_status; /* 0x18 */ -+ volatile unsigned int reserved; /* 0x1c */ -+ volatile unsigned int reset_control; /* 0x20 */ -+} INTERRUPT; -+ -+/******************************************************************** -+ * DMA controller -+ ********************************************************************/ -+typedef struct { -+ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ -+ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ -+ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ -+ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ -+ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ -+ volatile unsigned int status; /* 0x14 (CSR5) */ -+ volatile unsigned int control; /* 0x18 (CSR6) */ -+ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ -+ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ -+ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ -+ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ -+ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ -+} DMA; -+ -+/** -+ * Struct private for the Sibyte. -+ * -+ * Elements are grouped so variables used by the tx handling goes -+ * together, and will go into the same cache lines etc. in order to -+ * avoid cache line contention between the rx and tx handling on SMP. -+ * -+ * Frequently accessed variables are put at the beginning of the -+ * struct to help the compiler generate better/shorter code. -+ */ -+struct ar231x_private { -+ struct net_device *dev; -+ struct platform_device *pdev; -+ int version; -+ u32 mb[2]; -+ -+ volatile MII *phy_regs; -+ volatile ETHERNET_STRUCT *eth_regs; -+ volatile DMA *dma_regs; -+ struct ar231x_eth *cfg; -+ -+ spinlock_t lock; /* Serialise access to device */ -+ -+ /* RX and TX descriptors, must be adjacent */ -+ ar231x_descr_t *rx_ring; -+ ar231x_descr_t *tx_ring; -+ -+ struct sk_buff **rx_skb; -+ struct sk_buff **tx_skb; -+ -+ /* RX elements */ -+ u32 rx_skbprd; -+ u32 cur_rx; -+ -+ /* TX elements */ -+ u32 tx_prd; -+ u32 tx_csm; -+ -+ /* Misc elements */ -+ char name[48]; -+ struct { -+ u32 address; -+ u32 length; -+ char *mapping; -+ } desc; -+ -+ unsigned short link; /* 0 - link down, 1 - link up */ -+ unsigned short duplex; /* 0 - half, 1 - full */ -+ -+ struct tasklet_struct rx_tasklet; -+ int unloading; -+ -+ struct phy_device *phy_dev; -+ struct mii_bus *mii_bus; -+}; -+ -+/* Prototypes */ -+static int ar231x_init(struct net_device *dev); -+#ifdef TX_TIMEOUT -+static void ar231x_tx_timeout(struct net_device *dev); -+#endif -+static int ar231x_restart(struct net_device *dev); -+static void ar231x_load_rx_ring(struct net_device *dev, int bufs); -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id); -+static int ar231x_open(struct net_device *dev); -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); -+static int ar231x_close(struct net_device *dev); -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); -+static void ar231x_init_cleanup(struct net_device *dev); -+ -+#endif /* _AR2313_H_ */ ---- a/arch/mips/ath25/ar2315_regs.h -+++ b/arch/mips/ath25/ar2315_regs.h -@@ -57,6 +57,9 @@ - #define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */ - #define AR2315_PCI_EXT_SIZE 0x40000000 - -+/* MII registers offset inside Ethernet MMR region */ -+#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14) -+ - /* - * Configuration registers - */ ---- a/arch/mips/ath25/ar5312_regs.h -+++ b/arch/mips/ath25/ar5312_regs.h -@@ -64,6 +64,10 @@ - #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ - #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ - -+/* MII registers offset inside Ethernet MMR region */ -+#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14) -+#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14) -+ - /* Reset/Timer Block Address Map */ - #define AR5312_TIMER 0x0000 /* countdown timer */ - #define AR5312_RELOAD 0x0004 /* timer reload value */ ---- a/arch/mips/ath25/ar2315.c -+++ b/arch/mips/ath25/ar2315.c -@@ -132,6 +132,8 @@ static void ar2315_irq_dispatch(void) - - if (pending & CAUSEF_IP3) - do_IRQ(AR2315_IRQ_WLAN0); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR2315_IRQ_ENET0); - #ifdef CONFIG_PCI_AR2315 - else if (pending & CAUSEF_IP5) - do_IRQ(AR2315_IRQ_LCBUS_PCI); -@@ -167,6 +169,29 @@ void __init ar2315_arch_init_irq(void) - ar2315_misc_irq_domain = domain; - } - -+static void ar2315_device_reset_set(u32 mask) -+{ -+ u32 val; -+ -+ val = ar2315_rst_reg_read(AR2315_RESET); -+ ar2315_rst_reg_write(AR2315_RESET, val | mask); -+} -+ -+static void ar2315_device_reset_clear(u32 mask) -+{ -+ u32 val; -+ -+ val = ar2315_rst_reg_read(AR2315_RESET); -+ ar2315_rst_reg_write(AR2315_RESET, val & ~mask); -+} -+ -+static struct ar231x_eth ar2315_eth_data = { -+ .reset_set = ar2315_device_reset_set, -+ .reset_clear = ar2315_device_reset_clear, -+ .reset_mac = AR2315_RESET_ENET0, -+ .reset_phy = AR2315_RESET_EPHY0, -+}; -+ - static struct resource ar2315_gpio_res[] = { - { - .name = "ar2315-gpio", -@@ -203,6 +228,11 @@ void __init ar2315_init_devices(void) - ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; - platform_device_register(&ar2315_gpio); - -+ ar2315_eth_data.macaddr = ath25_board.config->enet0_mac; -+ ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii", -+ AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0, -+ &ar2315_eth_data); -+ - ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0); - } - ---- a/arch/mips/ath25/ar5312.c -+++ b/arch/mips/ath25/ar5312.c -@@ -128,6 +128,10 @@ static void ar5312_irq_dispatch(void) - - if (pending & CAUSEF_IP2) - do_IRQ(AR5312_IRQ_WLAN0); -+ else if (pending & CAUSEF_IP3) -+ do_IRQ(AR5312_IRQ_ENET0); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR5312_IRQ_ENET1); - else if (pending & CAUSEF_IP5) - do_IRQ(AR5312_IRQ_WLAN1); - else if (pending & CAUSEF_IP6) -@@ -161,6 +165,36 @@ void __init ar5312_arch_init_irq(void) - ar5312_misc_irq_domain = domain; - } - -+static void ar5312_device_reset_set(u32 mask) -+{ -+ u32 val; -+ -+ val = ar5312_rst_reg_read(AR5312_RESET); -+ ar5312_rst_reg_write(AR5312_RESET, val | mask); -+} -+ -+static void ar5312_device_reset_clear(u32 mask) -+{ -+ u32 val; -+ -+ val = ar5312_rst_reg_read(AR5312_RESET); -+ ar5312_rst_reg_write(AR5312_RESET, val & ~mask); -+} -+ -+static struct ar231x_eth ar5312_eth0_data = { -+ .reset_set = ar5312_device_reset_set, -+ .reset_clear = ar5312_device_reset_clear, -+ .reset_mac = AR5312_RESET_ENET0, -+ .reset_phy = AR5312_RESET_EPHY0, -+}; -+ -+static struct ar231x_eth ar5312_eth1_data = { -+ .reset_set = ar5312_device_reset_set, -+ .reset_clear = ar5312_device_reset_clear, -+ .reset_mac = AR5312_RESET_ENET1, -+ .reset_phy = AR5312_RESET_EPHY1, -+}; -+ - static struct physmap_flash_data ar5312_flash_data = { - .width = 2, - }; -@@ -241,6 +275,7 @@ static void __init ar5312_flash_init(voi - void __init ar5312_init_devices(void) - { - struct ath25_boarddata *config; -+ u8 *c; - - ar5312_flash_init(); - -@@ -264,8 +299,30 @@ void __init ar5312_init_devices(void) - - platform_device_register(&ar5312_gpio); - -+ /* Fix up MAC addresses if necessary */ -+ if (is_broadcast_ether_addr(config->enet0_mac)) -+ ether_addr_copy(config->enet0_mac, config->enet1_mac); -+ -+ /* If ENET0 and ENET1 have the same mac address, -+ * increment the one from ENET1 */ -+ if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) { -+ c = config->enet1_mac + 5; -+ while ((c >= config->enet1_mac) && !(++(*c))) -+ c--; -+ } -+ - switch (ath25_soc) { - case ATH25_SOC_AR5312: -+ ar5312_eth0_data.macaddr = config->enet0_mac; -+ ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii", -+ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0, -+ &ar5312_eth0_data); -+ -+ ar5312_eth1_data.macaddr = config->enet1_mac; -+ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii", -+ AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1, -+ &ar5312_eth1_data); -+ - if (!ath25_board.radio) - return; - -@@ -274,8 +331,18 @@ void __init ar5312_init_devices(void) - - ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0); - break; -+ /* -+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC -+ * of ENET1. Atheros calls it 'twisted' for a reason :) -+ */ - case ATH25_SOC_AR2312: - case ATH25_SOC_AR2313: -+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; -+ ar5312_eth1_data.macaddr = config->enet0_mac; -+ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii", -+ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1, -+ &ar5312_eth1_data); -+ - if (!ath25_board.radio) - return; - break; ---- a/arch/mips/ath25/devices.h -+++ b/arch/mips/ath25/devices.h -@@ -33,6 +33,8 @@ extern struct ar231x_board_config ath25_ - extern void (*ath25_irq_dispatch)(void); - - int ath25_find_config(phys_addr_t offset, unsigned long size); -+int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base, -+ int irq, void *pdata); - void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk); - int ath25_add_wmac(int nr, u32 base, int irq); - ---- a/arch/mips/ath25/devices.c -+++ b/arch/mips/ath25/devices.c -@@ -13,6 +13,51 @@ - struct ar231x_board_config ath25_board; - enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN; - -+static struct resource ath25_eth0_res[] = { -+ { -+ .name = "eth0_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth0_mii", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth0_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct resource ath25_eth1_res[] = { -+ { -+ .name = "eth1_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth1_mii", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth1_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device ath25_eth[] = { -+ { -+ .id = 0, -+ .name = "ar231x-eth", -+ .resource = ath25_eth0_res, -+ .num_resources = ARRAY_SIZE(ath25_eth0_res) -+ }, -+ { -+ .id = 1, -+ .name = "ar231x-eth", -+ .resource = ath25_eth1_res, -+ .num_resources = ARRAY_SIZE(ath25_eth1_res) -+ } -+}; -+ - static struct resource ath25_wmac0_res[] = { - { - .name = "wmac0_membase", -@@ -71,6 +116,25 @@ const char *get_system_type(void) - return soc_type_strings[ath25_soc]; - } - -+int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name, -+ u32 mii_base, int irq, void *pdata) -+{ -+ struct resource *res; -+ -+ ath25_eth[nr].dev.platform_data = pdata; -+ res = &ath25_eth[nr].resource[0]; -+ res->start = base; -+ res->end = base + 0x2000 - 1; -+ res++; -+ res->name = mii_name; -+ res->start = mii_base; -+ res->end = mii_base + 8 - 1; -+ res++; -+ res->start = irq; -+ res->end = irq; -+ return platform_device_register(&ath25_eth[nr]); -+} -+ - void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk) - { - #ifdef CONFIG_SERIAL_8250_CONSOLE ---- a/arch/mips/include/asm/mach-ath25/ath25_platform.h -+++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h -@@ -71,4 +71,15 @@ struct ar231x_board_config { - const char *radio; - }; - -+/* -+ * Platform device information for the Ethernet MAC -+ */ -+struct ar231x_eth { -+ void (*reset_set)(u32); -+ void (*reset_clear)(u32); -+ u32 reset_mac; -+ u32 reset_phy; -+ char *macaddr; -+}; -+ - #endif /* __ASM_MACH_ATH25_PLATFORM_H */ diff --git a/target/linux/ath25/patches-5.10/120-spiflash.patch b/target/linux/ath25/patches-5.10/120-spiflash.patch deleted file mode 100644 index 6b869d9fcd..0000000000 --- a/target/linux/ath25/patches-5.10/120-spiflash.patch +++ /dev/null @@ -1,631 +0,0 @@ ---- a/drivers/mtd/devices/Kconfig -+++ b/drivers/mtd/devices/Kconfig -@@ -114,6 +114,10 @@ config MTD_BCM47XXSFLASH - registered by bcma as platform devices. This enables driver for - serial flash memories. - -+config MTD_AR2315 -+ tristate "Atheros AR2315+ SPI Flash support" -+ depends on SOC_AR2315 -+ - config MTD_SLRAM - tristate "Uncached system RAM" - help ---- a/drivers/mtd/devices/Makefile -+++ b/drivers/mtd/devices/Makefile -@@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataf - obj-$(CONFIG_MTD_MCHP23K256) += mchp23k256.o - obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o - obj-$(CONFIG_MTD_SST25L) += sst25l.o -+obj-$(CONFIG_MTD_AR2315) += ar2315.o - obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o - obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o - obj-$(CONFIG_MTD_POWERNV_FLASH) += powernv_flash.o ---- /dev/null -+++ b/drivers/mtd/devices/ar2315.c -@@ -0,0 +1,456 @@ -+ -+/* -+ * MTD driver for the SPI Flash Memory support on Atheros AR2315 -+ * -+ * Copyright (c) 2005-2006 Atheros Communications Inc. -+ * Copyright (C) 2006-2007 FON Technology, SL. -+ * Copyright (C) 2006-2007 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * Copyright (C) 2012 Alexandros C. Couloumbis -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ar2315_spiflash.h" -+ -+#define DRIVER_NAME "ar2315-spiflash" -+ -+#define busy_wait(_priv, _condition, _wait) do { \ -+ while (_condition) { \ -+ if (_wait > 1) \ -+ msleep(_wait); \ -+ else if ((_wait == 1) && need_resched()) \ -+ schedule(); \ -+ else \ -+ udelay(1); \ -+ } \ -+} while (0) -+ -+enum { -+ FLASH_NONE, -+ FLASH_1MB, -+ FLASH_2MB, -+ FLASH_4MB, -+ FLASH_8MB, -+ FLASH_16MB, -+}; -+ -+/* Flash configuration table */ -+struct flashconfig { -+ u32 byte_cnt; -+ u32 sector_cnt; -+ u32 sector_size; -+}; -+ -+static const struct flashconfig flashconfig_tbl[] = { -+ [FLASH_NONE] = { 0, 0, 0}, -+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, -+ STM_1MB_SECTOR_SIZE}, -+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, -+ STM_2MB_SECTOR_SIZE}, -+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, -+ STM_4MB_SECTOR_SIZE}, -+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, -+ STM_8MB_SECTOR_SIZE}, -+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, -+ STM_16MB_SECTOR_SIZE} -+}; -+ -+/* Mapping of generic opcodes to STM serial flash opcodes */ -+enum { -+ SPI_WRITE_ENABLE, -+ SPI_WRITE_DISABLE, -+ SPI_RD_STATUS, -+ SPI_WR_STATUS, -+ SPI_RD_DATA, -+ SPI_FAST_RD_DATA, -+ SPI_PAGE_PROGRAM, -+ SPI_SECTOR_ERASE, -+ SPI_BULK_ERASE, -+ SPI_DEEP_PWRDOWN, -+ SPI_RD_SIG, -+}; -+ -+struct opcodes { -+ __u16 code; -+ __s8 tx_cnt; -+ __s8 rx_cnt; -+}; -+ -+static const struct opcodes stm_opcodes[] = { -+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, -+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, -+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, -+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, -+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, -+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, -+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, -+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, -+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, -+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, -+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, -+}; -+ -+/* Driver private data structure */ -+struct spiflash_priv { -+ struct mtd_info mtd; -+ void __iomem *readaddr; /* memory mapped data for read */ -+ void __iomem *mmraddr; /* memory mapped register space */ -+ struct mutex lock; /* serialize registers access */ -+}; -+ -+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) -+ -+enum { -+ FL_READY, -+ FL_READING, -+ FL_ERASING, -+ FL_WRITING -+}; -+ -+/*****************************************************************************/ -+ -+static u32 -+spiflash_read_reg(struct spiflash_priv *priv, int reg) -+{ -+ return ioread32(priv->mmraddr + reg); -+} -+ -+static void -+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) -+{ -+ iowrite32(data, priv->mmraddr + reg); -+} -+ -+static u32 -+spiflash_wait_busy(struct spiflash_priv *priv) -+{ -+ u32 reg; -+ -+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & -+ SPI_CTL_BUSY, 0); -+ return reg; -+} -+ -+static u32 -+spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr) -+{ -+ const struct opcodes *op; -+ u32 reg, mask; -+ -+ op = &stm_opcodes[opcode]; -+ reg = spiflash_wait_busy(priv); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, -+ ((u32)op->code) | (addr << 8)); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); -+ -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ spiflash_wait_busy(priv); -+ -+ if (!op->rx_cnt) -+ return 0; -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); -+ -+ switch (op->rx_cnt) { -+ case 1: -+ mask = 0x000000ff; -+ break; -+ case 2: -+ mask = 0x0000ffff; -+ break; -+ case 3: -+ mask = 0x00ffffff; -+ break; -+ default: -+ mask = 0xffffffff; -+ break; -+ } -+ reg &= mask; -+ -+ return reg; -+} -+ -+/* -+ * Probe SPI flash device -+ * Function returns 0 for failure. -+ * and flashconfig_tbl array index for success. -+ */ -+static int -+spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv) -+{ -+ u32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); -+ int flash_size; -+ -+ switch (sig) { -+ case STM_8MBIT_SIGNATURE: -+ flash_size = FLASH_1MB; -+ break; -+ case STM_16MBIT_SIGNATURE: -+ flash_size = FLASH_2MB; -+ break; -+ case STM_32MBIT_SIGNATURE: -+ flash_size = FLASH_4MB; -+ break; -+ case STM_64MBIT_SIGNATURE: -+ flash_size = FLASH_8MB; -+ break; -+ case STM_128MBIT_SIGNATURE: -+ flash_size = FLASH_16MB; -+ break; -+ default: -+ dev_warn(&pdev->dev, "read of flash device signature failed!\n"); -+ return 0; -+ } -+ -+ return flash_size; -+} -+ -+static void -+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) -+{ -+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & -+ SPI_STATUS_WIP, timeout); -+} -+ -+static int -+spiflash_erase(struct mtd_info *mtd, struct erase_info *instr) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ const struct opcodes *op; -+ u32 temp, reg; -+ -+ if (instr->addr + instr->len > mtd->size) -+ return -EINVAL; -+ -+ mutex_lock(&priv->lock); -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ reg = spiflash_wait_busy(priv); -+ -+ op = &stm_opcodes[SPI_SECTOR_ERASE]; -+ temp = ((u32)instr->addr << 8) | (u32)(op->code); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= op->tx_cnt | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 20); -+ -+ mutex_unlock(&priv->lock); -+ -+ return 0; -+} -+ -+static int -+spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, -+ u_char *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ -+ if (!len) -+ return 0; -+ -+ if (from + len > mtd->size) -+ return -EINVAL; -+ -+ *retlen = len; -+ -+ mutex_lock(&priv->lock); -+ -+ memcpy_fromio(buf, priv->readaddr + from, len); -+ -+ mutex_unlock(&priv->lock); -+ -+ return 0; -+} -+ -+static int -+spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, -+ const u8 *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ u32 opcode, bytes_left; -+ -+ *retlen = 0; -+ -+ if (!len) -+ return 0; -+ -+ if (to + len > mtd->size) -+ return -EINVAL; -+ -+ bytes_left = len; -+ -+ do { -+ u32 read_len, reg, page_offset, spi_data = 0; -+ -+ read_len = min(bytes_left, sizeof(u32)); -+ -+ /* 32-bit writes cannot span across a page boundary -+ * (256 bytes). This types of writes require two page -+ * program operations to handle it correctly. The STM part -+ * will write the overflow data to the beginning of the -+ * current page as opposed to the subsequent page. -+ */ -+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; -+ -+ if (page_offset > STM_PAGE_SIZE) -+ read_len -= (page_offset - STM_PAGE_SIZE); -+ -+ mutex_lock(&priv->lock); -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ spi_data = 0; -+ switch (read_len) { -+ case 4: -+ spi_data |= buf[3] << 24; -+ /* fall through */ -+ case 3: -+ spi_data |= buf[2] << 16; -+ /* fall through */ -+ case 2: -+ spi_data |= buf[1] << 8; -+ /* fall through */ -+ case 1: -+ spi_data |= buf[0] & 0xff; -+ break; -+ default: -+ break; -+ } -+ -+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); -+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | -+ (to & 0x00ffffff) << 8; -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= (read_len + 4) | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 1); -+ -+ mutex_unlock(&priv->lock); -+ -+ bytes_left -= read_len; -+ to += read_len; -+ buf += read_len; -+ -+ *retlen += read_len; -+ } while (bytes_left != 0); -+ -+ return 0; -+} -+ -+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS -+static const char * const part_probe_types[] = { -+ "cmdlinepart", "RedBoot", "MyLoader", NULL -+}; -+#endif -+ -+static int -+spiflash_probe(struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv; -+ struct mtd_info *mtd; -+ struct resource *res; -+ int index; -+ int result = 0; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ mutex_init(&priv->lock); -+ mtd = &priv->mtd; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ priv->mmraddr = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(priv->mmraddr)) { -+ dev_warn(&pdev->dev, "failed to map flash MMR\n"); -+ return PTR_ERR(priv->mmraddr); -+ } -+ -+ index = spiflash_probe_chip(pdev, priv); -+ if (!index) { -+ dev_warn(&pdev->dev, "found no flash device\n"); -+ return -ENODEV; -+ } -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ priv->readaddr = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(priv->readaddr)) { -+ dev_warn(&pdev->dev, "failed to map flash read mem\n"); -+ return PTR_ERR(priv->readaddr); -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ mtd->name = "spiflash"; -+ mtd->type = MTD_NORFLASH; -+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); -+ mtd->size = flashconfig_tbl[index].byte_cnt; -+ mtd->erasesize = flashconfig_tbl[index].sector_size; -+ mtd->writesize = 1; -+ mtd->numeraseregions = 0; -+ mtd->eraseregions = NULL; -+ mtd->_erase = spiflash_erase; -+ mtd->_read = spiflash_read; -+ mtd->_write = spiflash_write; -+ mtd->owner = THIS_MODULE; -+ -+ dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10); -+ -+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS -+ /* parse redboot partitions */ -+ -+ result = mtd_device_parse_register(mtd, part_probe_types, -+ NULL, NULL, 0); -+#endif -+ -+ return result; -+} -+ -+static int -+spiflash_remove(struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv = platform_get_drvdata(pdev); -+ -+ mtd_device_unregister(&priv->mtd); -+ -+ return 0; -+} -+ -+static struct platform_driver spiflash_driver = { -+ .driver.name = DRIVER_NAME, -+ .probe = spiflash_probe, -+ .remove = spiflash_remove, -+}; -+ -+module_platform_driver(spiflash_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("OpenWrt.org"); -+MODULE_AUTHOR("Atheros Communications Inc"); -+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros AR2315+ SOC"); -+MODULE_ALIAS("platform:" DRIVER_NAME); -+ ---- /dev/null -+++ b/drivers/mtd/devices/ar2315_spiflash.h -@@ -0,0 +1,106 @@ -+/* -+ * Atheros AR2315 SPI Flash Memory support header file. -+ * -+ * Copyright (c) 2005, Atheros Communications Inc. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#ifndef __AR2315_SPIFLASH_H -+#define __AR2315_SPIFLASH_H -+ -+#define STM_PAGE_SIZE 256 -+ -+#define SFI_WRITE_BUFFER_SIZE 4 -+#define SFI_FLASH_ADDR_MASK 0x00ffffff -+ -+#define STM_8MBIT_SIGNATURE 0x13 -+#define STM_M25P80_BYTE_COUNT 1048576 -+#define STM_M25P80_SECTOR_COUNT 16 -+#define STM_M25P80_SECTOR_SIZE 0x10000 -+ -+#define STM_16MBIT_SIGNATURE 0x14 -+#define STM_M25P16_BYTE_COUNT 2097152 -+#define STM_M25P16_SECTOR_COUNT 32 -+#define STM_M25P16_SECTOR_SIZE 0x10000 -+ -+#define STM_32MBIT_SIGNATURE 0x15 -+#define STM_M25P32_BYTE_COUNT 4194304 -+#define STM_M25P32_SECTOR_COUNT 64 -+#define STM_M25P32_SECTOR_SIZE 0x10000 -+ -+#define STM_64MBIT_SIGNATURE 0x16 -+#define STM_M25P64_BYTE_COUNT 8388608 -+#define STM_M25P64_SECTOR_COUNT 128 -+#define STM_M25P64_SECTOR_SIZE 0x10000 -+ -+#define STM_128MBIT_SIGNATURE 0x17 -+#define STM_M25P128_BYTE_COUNT 16777216 -+#define STM_M25P128_SECTOR_COUNT 256 -+#define STM_M25P128_SECTOR_SIZE 0x10000 -+ -+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT -+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT -+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE -+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT -+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT -+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE -+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT -+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT -+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE -+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT -+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT -+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE -+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT -+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT -+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE -+ -+/* -+ * ST Microelectronics Opcodes for Serial Flash -+ */ -+ -+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ -+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ -+#define STM_OP_RD_STATUS 0x05 /* Read Status */ -+#define STM_OP_WR_STATUS 0x01 /* Write Status */ -+#define STM_OP_RD_DATA 0x03 /* Read Data */ -+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ -+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ -+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ -+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ -+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ -+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ -+ -+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ -+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ -+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ -+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ -+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ -+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ -+ -+/* -+ * SPI Flash Interface Registers -+ */ -+ -+#define SPI_FLASH_CTL 0x00 -+#define SPI_FLASH_OPCODE 0x04 -+#define SPI_FLASH_DATA 0x08 -+ -+#define SPI_CTL_START 0x00000100 -+#define SPI_CTL_BUSY 0x00010000 -+#define SPI_CTL_TXCNT_MASK 0x0000000f -+#define SPI_CTL_RXCNT_MASK 0x000000f0 -+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff -+#define SPI_CTL_SIZE_MASK 0x00060000 -+ -+#define SPI_CTL_CLK_SEL_MASK 0x03000000 -+#define SPI_OPCODE_MASK 0x000000ff -+ -+#define SPI_STATUS_WIP STM_STATUS_WIP -+ -+#endif ---- a/arch/mips/ath25/ar2315.c -+++ b/arch/mips/ath25/ar2315.c -@@ -218,6 +218,28 @@ static struct platform_device ar2315_gpi - .num_resources = ARRAY_SIZE(ar2315_gpio_res) - }; - -+static struct resource ar2315_spiflash_res[] = { -+ { -+ .name = "spiflash_read", -+ .flags = IORESOURCE_MEM, -+ .start = AR2315_SPI_READ_BASE, -+ .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1, -+ }, -+ { -+ .name = "spiflash_mmr", -+ .flags = IORESOURCE_MEM, -+ .start = AR2315_SPI_MMR_BASE, -+ .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1, -+ }, -+}; -+ -+static struct platform_device ar2315_spiflash = { -+ .id = 0, -+ .name = "ar2315-spiflash", -+ .resource = ar2315_spiflash_res, -+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) -+}; -+ - void __init ar2315_init_devices(void) - { - /* Find board configuration */ -@@ -228,6 +250,8 @@ void __init ar2315_init_devices(void) - ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; - platform_device_register(&ar2315_gpio); - -+ platform_device_register(&ar2315_spiflash); -+ - ar2315_eth_data.macaddr = ath25_board.config->enet0_mac; - ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii", - AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0, diff --git a/target/linux/ath25/patches-5.10/130-watchdog.patch b/target/linux/ath25/patches-5.10/130-watchdog.patch deleted file mode 100644 index 1c8c9a9677..0000000000 --- a/target/linux/ath25/patches-5.10/130-watchdog.patch +++ /dev/null @@ -1,277 +0,0 @@ ---- /dev/null -+++ b/drivers/watchdog/ar2315-wtd.c -@@ -0,0 +1,209 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see . -+ * -+ * Copyright (C) 2008 John Crispin -+ * Based on EP93xx and ifxmips wdt driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRIVER_NAME "ar2315-wdt" -+ -+#define CLOCK_RATE 40000000 -+#define HEARTBEAT(x) (x < 1 || x > 90 ? 20 : x) -+ -+#define WDT_REG_TIMER 0x00 -+#define WDT_REG_CTRL 0x04 -+ -+#define WDT_CTRL_ACT_NONE 0x00000000 /* No action */ -+#define WDT_CTRL_ACT_NMI 0x00000001 /* NMI on watchdog */ -+#define WDT_CTRL_ACT_RESET 0x00000002 /* reset on watchdog */ -+ -+static int wdt_timeout = 20; -+static int started; -+static int in_use; -+static void __iomem *wdt_base; -+ -+static inline void ar2315_wdt_wr(unsigned reg, u32 val) -+{ -+ iowrite32(val, wdt_base + reg); -+} -+ -+static void -+ar2315_wdt_enable(void) -+{ -+ ar2315_wdt_wr(WDT_REG_TIMER, wdt_timeout * CLOCK_RATE); -+} -+ -+static ssize_t -+ar2315_wdt_write(struct file *file, const char __user *data, size_t len, -+ loff_t *ppos) -+{ -+ if (len) -+ ar2315_wdt_enable(); -+ return len; -+} -+ -+static int -+ar2315_wdt_open(struct inode *inode, struct file *file) -+{ -+ if (in_use) -+ return -EBUSY; -+ ar2315_wdt_enable(); -+ in_use = 1; -+ started = 1; -+ return nonseekable_open(inode, file); -+} -+ -+static int -+ar2315_wdt_release(struct inode *inode, struct file *file) -+{ -+ in_use = 0; -+ return 0; -+} -+ -+static irqreturn_t -+ar2315_wdt_interrupt(int irq, void *dev) -+{ -+ struct platform_device *pdev = (struct platform_device *)dev; -+ -+ if (started) { -+ dev_crit(&pdev->dev, "watchdog expired, rebooting system\n"); -+ emergency_restart(); -+ } else { -+ ar2315_wdt_wr(WDT_REG_CTRL, 0); -+ ar2315_wdt_wr(WDT_REG_TIMER, 0); -+ } -+ return IRQ_HANDLED; -+} -+ -+static struct watchdog_info ident = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, -+ .identity = "ar2315 Watchdog", -+}; -+ -+static long -+ar2315_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int new_wdt_timeout; -+ int ret = -ENOIOCTLCMD; -+ -+ switch (cmd) { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((void __user *)arg, &ident, sizeof(ident)) ? -+ -EFAULT : 0; -+ break; -+ case WDIOC_KEEPALIVE: -+ ar2315_wdt_enable(); -+ ret = 0; -+ break; -+ case WDIOC_SETTIMEOUT: -+ ret = get_user(new_wdt_timeout, (int __user *)arg); -+ if (ret) -+ break; -+ wdt_timeout = HEARTBEAT(new_wdt_timeout); -+ ar2315_wdt_enable(); -+ break; -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int __user *)arg); -+ break; -+ } -+ return ret; -+} -+ -+static const struct file_operations ar2315_wdt_fops = { -+ .owner = THIS_MODULE, -+ .llseek = no_llseek, -+ .write = ar2315_wdt_write, -+ .unlocked_ioctl = ar2315_wdt_ioctl, -+ .open = ar2315_wdt_open, -+ .release = ar2315_wdt_release, -+}; -+ -+static struct miscdevice ar2315_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ar2315_wdt_fops, -+}; -+ -+static int -+ar2315_wdt_probe(struct platform_device *dev) -+{ -+ struct resource *mem_res, *irq_res; -+ int ret = 0; -+ -+ if (wdt_base) -+ return -EBUSY; -+ -+ irq_res = platform_get_resource(dev, IORESOURCE_IRQ, 0); -+ if (!irq_res) { -+ dev_err(&dev->dev, "no IRQ resource\n"); -+ return -ENOENT; -+ } -+ -+ mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); -+ wdt_base = devm_ioremap_resource(&dev->dev, mem_res); -+ if (IS_ERR(wdt_base)) -+ return PTR_ERR(wdt_base); -+ -+ ret = devm_request_irq(&dev->dev, irq_res->start, ar2315_wdt_interrupt, -+ 0, DRIVER_NAME, dev); -+ if (ret) { -+ dev_err(&dev->dev, "failed to register inetrrupt\n"); -+ goto out; -+ } -+ -+ ret = misc_register(&ar2315_wdt_miscdev); -+ if (ret) -+ dev_err(&dev->dev, "failed to register miscdev\n"); -+ -+out: -+ return ret; -+} -+ -+static int -+ar2315_wdt_remove(struct platform_device *dev) -+{ -+ misc_deregister(&ar2315_wdt_miscdev); -+ return 0; -+} -+ -+static struct platform_driver ar2315_wdt_driver = { -+ .probe = ar2315_wdt_probe, -+ .remove = ar2315_wdt_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+module_platform_driver(ar2315_wdt_driver); -+ -+MODULE_DESCRIPTION("Atheros AR2315 hardware watchdog driver"); -+MODULE_AUTHOR("John Crispin "); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:" DRIVER_NAME); ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -1873,6 +1873,13 @@ config PIC32_DMT - To compile this driver as a loadable module, choose M here. - The module will be called pic32-dmt. - -+config AR2315_WDT -+ tristate "Atheros AR2315+ WiSoCs Watchdog Timer" -+ depends on ATH25 -+ help -+ Hardware driver for the built-in watchdog timer on the Atheros -+ AR2315/AR2316 WiSoCs. -+ - # PARISC Architecture - - # POWERPC Architecture ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -164,6 +164,7 @@ obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o - obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o -+obj-$(CONFIG_AR2315_WDT) += ar2315-wtd.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o - obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o - octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o ---- a/arch/mips/ath25/ar2315.c -+++ b/arch/mips/ath25/ar2315.c -@@ -218,6 +218,24 @@ static struct platform_device ar2315_gpi - .num_resources = ARRAY_SIZE(ar2315_gpio_res) - }; - -+static struct resource ar2315_wdt_res[] = { -+ { -+ .flags = IORESOURCE_MEM, -+ .start = AR2315_RST_BASE + AR2315_WDT_TIMER, -+ .end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1, -+ }, -+ { -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device ar2315_wdt = { -+ .id = 0, -+ .name = "ar2315-wdt", -+ .resource = ar2315_wdt_res, -+ .num_resources = ARRAY_SIZE(ar2315_wdt_res) -+}; -+ - static struct resource ar2315_spiflash_res[] = { - { - .name = "spiflash_read", -@@ -250,6 +268,11 @@ void __init ar2315_init_devices(void) - ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; - platform_device_register(&ar2315_gpio); - -+ ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain, -+ AR2315_MISC_IRQ_WATCHDOG); -+ ar2315_wdt_res[1].end = ar2315_wdt_res[1].start; -+ platform_device_register(&ar2315_wdt); -+ - platform_device_register(&ar2315_spiflash); - - ar2315_eth_data.macaddr = ath25_board.config->enet0_mac; diff --git a/target/linux/ath25/patches-5.10/140-redboot_boardconfig.patch b/target/linux/ath25/patches-5.10/140-redboot_boardconfig.patch deleted file mode 100644 index 07d75b9fba..0000000000 --- a/target/linux/ath25/patches-5.10/140-redboot_boardconfig.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/drivers/mtd/parsers/redboot.c -+++ b/drivers/mtd/parsers/redboot.c -@@ -16,6 +16,8 @@ - #include - #include - -+#define BOARD_CONFIG_PART "boardconfig" -+ - struct fis_image_desc { - unsigned char name[16]; // Null terminated name - uint32_t flash_base; // Address within FLASH of image -@@ -73,6 +75,7 @@ static int parse_redboot_partitions(stru - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) - { -+ unsigned long max_offset = 0; - int nrparts = 0; - struct fis_image_desc *buf; - struct mtd_partition *parts; -@@ -240,14 +243,15 @@ static int parse_redboot_partitions(stru - } - } - #endif -- parts = kzalloc(sizeof(*parts)*nrparts + nulllen + namelen, GFP_KERNEL); -+ parts = kzalloc(sizeof(*parts) * (nrparts + 1) + nulllen + namelen + -+ sizeof(BOARD_CONFIG_PART), GFP_KERNEL); - - if (!parts) { - ret = -ENOMEM; - goto out; - } - -- nullname = (char *)&parts[nrparts]; -+ nullname = (char *)&parts[nrparts + 1]; - #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED - if (nulllen > 0) { - strcpy(nullname, nullstring); -@@ -266,6 +270,8 @@ static int parse_redboot_partitions(stru - } - #endif - for ( ; iimg->size; - parts[i].offset = fl->img->flash_base; - parts[i].name = names; -@@ -299,6 +305,13 @@ static int parse_redboot_partitions(stru - fl = fl->next; - kfree(tmp_fl); - } -+ if (master->size - max_offset >= master->erasesize) { -+ parts[nrparts].size = master->size - max_offset; -+ parts[nrparts].offset = max_offset; -+ parts[nrparts].name = names; -+ strcpy(names, BOARD_CONFIG_PART); -+ nrparts++; -+ } - ret = nrparts; - *pparts = parts; - out: diff --git a/target/linux/ath25/patches-5.10/141-redboot_partition_scan.patch b/target/linux/ath25/patches-5.10/141-redboot_partition_scan.patch deleted file mode 100644 index 68019f90ea..0000000000 --- a/target/linux/ath25/patches-5.10/141-redboot_partition_scan.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/drivers/mtd/parsers/redboot.c -+++ b/drivers/mtd/parsers/redboot.c -@@ -94,12 +94,18 @@ static int parse_redboot_partitions(stru - - parse_redboot_of(master); - -+ buf = vmalloc(master->erasesize); -+ if (!buf) -+ return -ENOMEM; -+ -+ restart: - if ( directory < 0 ) { - offset = master->size + directory * master->erasesize; - while (mtd_block_isbad(master, offset)) { - if (!offset) { - nogood: - printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ vfree(buf); - return -EIO; - } - offset -= master->erasesize; -@@ -112,10 +118,6 @@ static int parse_redboot_partitions(stru - goto nogood; - } - } -- buf = vmalloc(master->erasesize); -- -- if (!buf) -- return -ENOMEM; - - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); -@@ -188,6 +190,11 @@ static int parse_redboot_partitions(stru - } - if (i == numslots) { - /* Didn't find it */ -+ if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block */ -+ directory++; -+ goto restart; -+ } - printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", - master->name); - ret = 0; diff --git a/target/linux/ath25/patches-5.10/142-redboot_various_erase_size_fix.patch b/target/linux/ath25/patches-5.10/142-redboot_various_erase_size_fix.patch deleted file mode 100644 index c3b73eabe9..0000000000 --- a/target/linux/ath25/patches-5.10/142-redboot_various_erase_size_fix.patch +++ /dev/null @@ -1,72 +0,0 @@ ---- a/drivers/mtd/parsers/redboot.c -+++ b/drivers/mtd/parsers/redboot.c -@@ -71,6 +71,22 @@ static void parse_redboot_of(struct mtd_ - directory = dirblock; - } - -+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) -+{ -+ struct mtd_erase_region_info *regions = mtd->eraseregions; -+ int i; -+ -+ for (i = 0; i < mtd->numeraseregions; i++) { -+ if (regions[i].offset + -+ regions[i].numblocks * regions[i].erasesize <= offset) -+ continue; -+ -+ return regions[i].erasesize; -+ } -+ -+ return mtd->erasesize; -+} -+ - static int parse_redboot_partitions(struct mtd_info *master, - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) -@@ -87,6 +103,7 @@ static int parse_redboot_partitions(stru - int namelen = 0; - int nulllen = 0; - int numslots; -+ int first_slot; - unsigned long offset; - #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED - static char nullstring[] = "unallocated"; -@@ -201,7 +218,10 @@ static int parse_redboot_partitions(stru - goto out; - } - -- for (i = 0; i < numslots; i++) { -+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / -+ sizeof(struct fis_image_desc); -+ -+ for (i = first_slot; i < first_slot + numslots; i++) { - struct fis_list *new_fl, **prev; - - if (buf[i].name[0] == 0xff) { -@@ -277,12 +297,13 @@ static int parse_redboot_partitions(stru - } - #endif - for ( ; iimg->size; - parts[i].offset = fl->img->flash_base; - parts[i].name = names; - -+ if (max_offset < parts[i].offset + parts[i].size) -+ max_offset = parts[i].offset + parts[i].size; -+ - strcpy(names, fl->img->name); - #ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY - if (!memcmp(names, "RedBoot", 8) || -@@ -312,7 +333,9 @@ static int parse_redboot_partitions(stru - fl = fl->next; - kfree(tmp_fl); - } -- if (master->size - max_offset >= master->erasesize) { -+ -+ if (master->size - max_offset >= -+ mtd_get_offset_erasesize(master, max_offset)) { - parts[nrparts].size = master->size - max_offset; - parts[nrparts].offset = max_offset; - parts[nrparts].name = names; diff --git a/target/linux/ath25/patches-5.10/210-reset_button.patch b/target/linux/ath25/patches-5.10/210-reset_button.patch deleted file mode 100644 index b3f7a14cda..0000000000 --- a/target/linux/ath25/patches-5.10/210-reset_button.patch +++ /dev/null @@ -1,71 +0,0 @@ ---- a/arch/mips/ath25/Makefile -+++ b/arch/mips/ath25/Makefile -@@ -8,7 +8,7 @@ - # Copyright (C) 2006-2009 Felix Fietkau - # - --obj-y += board.o prom.o devices.o -+obj-y += board.o prom.o devices.o reset.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - ---- /dev/null -+++ b/arch/mips/ath25/reset.c -@@ -0,0 +1,57 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+ -+static int __init -+ar231x_init_reset(void) -+{ -+ struct platform_device *pdev; -+ struct gpio_keys_platform_data pdata; -+ struct gpio_keys_button *p; -+ int err; -+ -+ if (ath25_board.config->reset_config_gpio == 0xffff) -+ return -ENODEV; -+ -+ p = kzalloc(sizeof(*p), GFP_KERNEL); -+ if (!p) -+ goto err; -+ -+ p->desc = "reset"; -+ p->type = EV_KEY; -+ p->code = KEY_RESTART; -+ p->debounce_interval = 60; -+ p->gpio = ath25_board.config->reset_config_gpio; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ pdata.poll_interval = 20; -+ pdata.buttons = p; -+ pdata.nbuttons = 1; -+ -+ pdev = platform_device_alloc("gpio-keys-polled", 0); -+ if (!pdev) -+ goto err_free; -+ -+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -+ if (err) -+ goto err_put_pdev; -+ -+ err = platform_device_add(pdev); -+ if (err) -+ goto err_put_pdev; -+ -+ return 0; -+ -+err_put_pdev: -+ platform_device_put(pdev); -+err_free: -+ kfree(p); -+err: -+ return -ENOMEM; -+} -+ -+device_initcall(ar231x_init_reset); diff --git a/target/linux/ath25/patches-5.10/220-enet_micrel_workaround.patch b/target/linux/ath25/patches-5.10/220-enet_micrel_workaround.patch deleted file mode 100644 index 2bd0815631..0000000000 --- a/target/linux/ath25/patches-5.10/220-enet_micrel_workaround.patch +++ /dev/null @@ -1,111 +0,0 @@ ---- a/drivers/net/ethernet/atheros/ar231x/ar231x.c -+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c -@@ -135,6 +135,7 @@ static int ar231x_mdiobus_write(struct m - static int ar231x_mdiobus_reset(struct mii_bus *bus); - static int ar231x_mdiobus_probe(struct net_device *dev); - static void ar231x_adjust_link(struct net_device *dev); -+static bool no_phy; - - #ifndef ERR - #define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) -@@ -166,6 +167,32 @@ static const struct net_device_ops ar231 - #endif - }; - -+static int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id) -+{ -+ int phy_reg; -+ -+ /** -+ * Grab the bits from PHYIR1, and put them -+ * in the upper half. -+ */ -+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID1); -+ -+ if (phy_reg < 0) -+ return -EIO; -+ -+ *phy_id = (phy_reg & 0xffff) << 16; -+ -+ /* Grab the bits from PHYIR2, and put them in the lower half */ -+ phy_reg = mdiobus_read(bus, addr, MII_PHYSID2); -+ -+ if (phy_reg < 0) -+ return -EIO; -+ -+ *phy_id |= (phy_reg & 0xffff); -+ -+ return 0; -+} -+ - static int ar231x_probe(struct platform_device *pdev) - { - struct net_device *dev; -@@ -273,6 +300,24 @@ static int ar231x_probe(struct platform_ - - mdiobus_register(sp->mii_bus); - -+ /** -+ * Workaround for Micrel switch, which is only available on -+ * one PHY and cannot be configured through MDIO. -+ */ -+ if (!no_phy) { -+ u32 phy_id = 0; -+ -+ get_phy_id(sp->mii_bus, 1, &phy_id); -+ if (phy_id == 0x00221450) -+ no_phy = true; -+ } -+ if (no_phy) { -+ sp->link = 1; -+ netif_carrier_on(dev); -+ return 0; -+ } -+ no_phy = true; -+ - if (ar231x_mdiobus_probe(dev) != 0) { - printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); - rx_tasklet_cleanup(dev); -@@ -326,8 +371,10 @@ static int ar231x_remove(struct platform - rx_tasklet_cleanup(dev); - ar231x_init_cleanup(dev); - unregister_netdev(dev); -- mdiobus_unregister(sp->mii_bus); -- mdiobus_free(sp->mii_bus); -+ if (sp->mii_bus) { -+ mdiobus_unregister(sp->mii_bus); -+ mdiobus_free(sp->mii_bus); -+ } - kfree(dev); - return 0; - } -@@ -870,7 +917,8 @@ static int ar231x_open(struct net_device - - sp->eth_regs->mac_control |= MAC_CONTROL_RE; - -- phy_start(sp->phy_dev); -+ if (sp->phy_dev) -+ phy_start(sp->phy_dev); - - return 0; - } -@@ -951,7 +999,8 @@ static int ar231x_close(struct net_devic - - #endif - -- phy_stop(sp->phy_dev); -+ if (sp->phy_dev) -+ phy_stop(sp->phy_dev); - - return 0; - } -@@ -995,6 +1044,9 @@ static int ar231x_ioctl(struct net_devic - { - struct ar231x_private *sp = netdev_priv(dev); - -+ if (!sp->phy_dev) -+ return -ENODEV; -+ - switch (cmd) { - case SIOCGMIIPHY: - case SIOCGMIIREG: diff --git a/target/linux/ath25/patches-5.10/330-board_leds.patch b/target/linux/ath25/patches-5.10/330-board_leds.patch deleted file mode 100644 index a683d01111..0000000000 --- a/target/linux/ath25/patches-5.10/330-board_leds.patch +++ /dev/null @@ -1,116 +0,0 @@ ---- a/arch/mips/ath25/ar2315.c -+++ b/arch/mips/ath25/ar2315.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -258,6 +259,50 @@ static struct platform_device ar2315_spi - .num_resources = ARRAY_SIZE(ar2315_spiflash_res) - }; - -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar2315_leds[6]; -+static struct gpio_led_platform_data ar2315_led_data = { -+ .leds = (void *)ar2315_leds, -+}; -+ -+static struct platform_device ar2315_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev = { -+ .platform_data = (void *)&ar2315_led_data, -+ } -+}; -+ -+static void __init ar2315_init_gpio_leds(void) -+{ -+ static char led_names[6][6]; -+ int i, led = 0; -+ -+ ar2315_led_data.num_leds = 0; -+ for (i = 1; i < 8; i++) { -+ if ((i == AR2315_RESET_GPIO) || -+ (i == ath25_board.config->reset_config_gpio)) -+ continue; -+ -+ if (i == ath25_board.config->sys_led_gpio) -+ strcpy(led_names[led], "wlan"); -+ else -+ sprintf(led_names[led], "gpio%d", i); -+ -+ ar2315_leds[led].name = led_names[led]; -+ ar2315_leds[led].gpio = i; -+ ar2315_leds[led].active_low = 0; -+ led++; -+ } -+ ar2315_led_data.num_leds = led; -+ platform_device_register(&ar2315_gpio_leds); -+} -+#else -+static inline void ar2315_init_gpio_leds(void) -+{ -+} -+#endif -+ - void __init ar2315_init_devices(void) - { - /* Find board configuration */ -@@ -268,6 +313,8 @@ void __init ar2315_init_devices(void) - ar2315_gpio_res[1].end = ar2315_gpio_res[1].start; - platform_device_register(&ar2315_gpio); - -+ ar2315_init_gpio_leds(); -+ - ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain, - AR2315_MISC_IRQ_WATCHDOG); - ar2315_wdt_res[1].end = ar2315_wdt_res[1].start; ---- a/arch/mips/ath25/ar5312.c -+++ b/arch/mips/ath25/ar5312.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -229,6 +230,23 @@ static struct platform_device ar5312_gpi - .num_resources = ARRAY_SIZE(ar5312_gpio_res), - }; - -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar5312_leds[] = { -+ { .name = "wlan", .gpio = 0, .active_low = 1, }, -+}; -+ -+static const struct gpio_led_platform_data ar5312_led_data = { -+ .num_leds = ARRAY_SIZE(ar5312_leds), -+ .leds = (void *)ar5312_leds, -+}; -+ -+static struct platform_device ar5312_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev.platform_data = (void *)&ar5312_led_data, -+}; -+#endif -+ - static void __init ar5312_flash_init(void) - { - void __iomem *flashctl_base; -@@ -299,6 +317,11 @@ void __init ar5312_init_devices(void) - - platform_device_register(&ar5312_gpio); - -+#ifdef CONFIG_LEDS_GPIO -+ ar5312_leds[0].gpio = config->sys_led_gpio; -+ platform_device_register(&ar5312_gpio_leds); -+#endif -+ - /* Fix up MAC addresses if necessary */ - if (is_broadcast_ether_addr(config->enet0_mac)) - ether_addr_copy(config->enet0_mac, config->enet1_mac); diff --git a/target/linux/ath25/patches-5.10/700-swconfig_mvswitch.patch b/target/linux/ath25/patches-5.10/700-swconfig_mvswitch.patch deleted file mode 100644 index 79a4d1c1a0..0000000000 --- a/target/linux/ath25/patches-5.10/700-swconfig_mvswitch.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -95,6 +95,10 @@ config IP17XX_PHY - tristate "Driver for IC+ IP17xx switches" - select SWCONFIG - -+config MVSWITCH_PHY -+ tristate "Driver for Marvell 88E6060 switches" -+ select ETHERNET_PACKET_MANGLE -+ - config PSB6970_PHY - tristate "Lantiq XWAY Tantos (PSB6970) Ethernet switch" - select SWCONFIG ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -31,6 +31,7 @@ ar8xxx-y += ar8216.o - ar8xxx-y += ar8327.o - obj-$(CONFIG_SWCONFIG_B53) += b53/ - obj-$(CONFIG_IP17XX_PHY) += ip17xx.o -+obj-$(CONFIG_MVSWITCH_PHY) += mvswitch.o - obj-$(CONFIG_PSB6970_PHY) += psb6970.o - obj-$(CONFIG_RTL8306_PHY) += rtl8306.o - obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o diff --git a/target/linux/ath79/config-5.10 b/target/linux/ath79/config-5.10 deleted file mode 100644 index 04eec4375f..0000000000 --- a/target/linux/ath79/config-5.10 +++ /dev/null @@ -1,203 +0,0 @@ -CONFIG_AG71XX=y -# CONFIG_AG71XX_DEBUG is not set -CONFIG_AG71XX_DEBUG_FS=y -CONFIG_AR8216_PHY=y -CONFIG_AR8216_PHY_LEDS=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_AT803X_PHY=y -CONFIG_ATH79=y -CONFIG_ATH79_WDT=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -# CONFIG_CRYPTO_CHACHA_MIPS is not set -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -# CONFIG_CRYPTO_POLY1305_MIPS is not set -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_74X164=y -CONFIG_GPIO_ATH79=y -CONFIG_GPIO_GENERIC=y -# CONFIG_GPIO_LATCH is not set -# CONFIG_GPIO_RB91X_KEY is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -# CONFIG_KERNEL_ZSTD is not set -CONFIG_LEDS_GPIO=y -# CONFIG_LEDS_RESET is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_GPIO=y -CONFIG_MEMFD_CREATE=y -# CONFIG_MFD_RB4XX_CPLD is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -# CONFIG_MIPS_GENERIC_KERNEL is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_CFI_I2 is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -CONFIG_MTD_PARSER_CYBERTAN=y -# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_ELF_FW=y -CONFIG_MTD_SPLIT_LZMA_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_SPLIT_WRGG_FW=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI=y -CONFIG_PCI_AR71XX=y -CONFIG_PCI_AR724X=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -# CONFIG_PHY_AR7100_USB is not set -# CONFIG_PHY_AR7200_USB is not set -# CONFIG_PHY_ATH79_USB is not set -CONFIG_PINCTRL=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_RESET_ATH79=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_AR933X=y -CONFIG_SERIAL_AR933X_CONSOLE=y -CONFIG_SERIAL_AR933X_NR_UARTS=2 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SPI=y -CONFIG_SPI_AR934X=y -CONFIG_SPI_ATH79=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_RB4XX is not set -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y diff --git a/target/linux/ath79/patches-5.10/0003-leds-add-reset-controller-based-driver.patch b/target/linux/ath79/patches-5.10/0003-leds-add-reset-controller-based-driver.patch deleted file mode 100644 index 4a721f2af2..0000000000 --- a/target/linux/ath79/patches-5.10/0003-leds-add-reset-controller-based-driver.patch +++ /dev/null @@ -1,186 +0,0 @@ -From ecbd9c87f073f097d9fe56390353e64e963e866a Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 10:03:03 +0100 -Subject: [PATCH 03/27] leds: add reset-controller based driver - -Signed-off-by: John Crispin ---- - drivers/leds/Kconfig | 11 ++++ - drivers/leds/Makefile | 1 + - drivers/leds/leds-reset.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 149 insertions(+) - create mode 100644 drivers/leds/leds-reset.c - ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -931,6 +931,17 @@ config LEDS_ACER_A500 - - source "drivers/leds/blink/Kconfig" - -+config LEDS_RESET -+ tristate "LED support for reset-controller API" -+ depends on LEDS_CLASS -+ depends on RESET_CONTROLLER -+ help -+ This option enables support for LEDs connected to pins driven by reset -+ controllers. Yes, DNI actual built HW like that. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called leds-reset. -+ - comment "LED Triggers" - source "drivers/leds/trigger/Kconfig" - ---- /dev/null -+++ b/drivers/leds/leds-reset.c -@@ -0,0 +1,140 @@ -+/* -+ * Copyright (C) 2018 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct reset_led_data { -+ struct led_classdev cdev; -+ struct reset_control *rst; -+}; -+ -+static inline struct reset_led_data * -+ cdev_to_reset_led_data(struct led_classdev *led_cdev) -+{ -+ return container_of(led_cdev, struct reset_led_data, cdev); -+} -+ -+static void reset_led_set(struct led_classdev *led_cdev, -+ enum led_brightness value) -+{ -+ struct reset_led_data *led_dat = cdev_to_reset_led_data(led_cdev); -+ -+ if (value == LED_OFF) -+ reset_control_assert(led_dat->rst); -+ else -+ reset_control_deassert(led_dat->rst); -+} -+ -+struct reset_leds_priv { -+ int num_leds; -+ struct reset_led_data leds[]; -+}; -+ -+static inline int sizeof_reset_leds_priv(int num_leds) -+{ -+ return sizeof(struct reset_leds_priv) + -+ (sizeof(struct reset_led_data) * num_leds); -+} -+ -+static struct reset_leds_priv *reset_leds_create(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct fwnode_handle *child; -+ struct reset_leds_priv *priv; -+ int count, ret; -+ -+ count = device_get_child_node_count(dev); -+ if (!count) -+ return ERR_PTR(-ENODEV); -+ -+ priv = devm_kzalloc(dev, sizeof_reset_leds_priv(count), GFP_KERNEL); -+ if (!priv) -+ return ERR_PTR(-ENOMEM); -+ -+ device_for_each_child_node(dev, child) { -+ struct reset_led_data *led = &priv->leds[priv->num_leds]; -+ struct device_node *np = to_of_node(child); -+ -+ ret = fwnode_property_read_string(child, "label", &led->cdev.name); -+ if (!led->cdev.name) { -+ fwnode_handle_put(child); -+ return ERR_PTR(-EINVAL); -+ } -+ led->rst = __of_reset_control_get(np, NULL, 0, 0, 0, true); -+ if (IS_ERR(led->rst)) -+ return ERR_PTR(-EINVAL); -+ -+ fwnode_property_read_string(child, "linux,default-trigger", -+ &led->cdev.default_trigger); -+ -+ led->cdev.brightness_set = reset_led_set; -+ ret = devm_led_classdev_register(&pdev->dev, &led->cdev); -+ if (ret < 0) -+ return ERR_PTR(ret); -+ led->cdev.dev->of_node = np; -+ priv->num_leds++; -+ } -+ -+ return priv; -+} -+ -+static const struct of_device_id of_reset_leds_match[] = { -+ { .compatible = "reset-leds", }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, of_reset_leds_match); -+ -+static int reset_led_probe(struct platform_device *pdev) -+{ -+ struct reset_leds_priv *priv; -+ -+ priv = reset_leds_create(pdev); -+ if (IS_ERR(priv)) -+ return PTR_ERR(priv); -+ -+ platform_set_drvdata(pdev, priv); -+ -+ return 0; -+} -+ -+static void reset_led_shutdown(struct platform_device *pdev) -+{ -+ struct reset_leds_priv *priv = platform_get_drvdata(pdev); -+ int i; -+ -+ for (i = 0; i < priv->num_leds; i++) { -+ struct reset_led_data *led = &priv->leds[i]; -+ -+ if (!(led->cdev.flags & LED_RETAIN_AT_SHUTDOWN)) -+ reset_led_set(&led->cdev, LED_OFF); -+ } -+} -+ -+static struct platform_driver reset_led_driver = { -+ .probe = reset_led_probe, -+ .shutdown = reset_led_shutdown, -+ .driver = { -+ .name = "leds-reset", -+ .of_match_table = of_reset_leds_match, -+ }, -+}; -+ -+module_platform_driver(reset_led_driver); -+ -+MODULE_AUTHOR("John Crispin "); -+MODULE_DESCRIPTION("reset controller LED driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:leds-reset"); ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -93,6 +93,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA) += leds - obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o - obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o - obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o -+obj-$(CONFIG_LEDS_RESET) += leds-reset.o - - # LED SPI Drivers - obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o diff --git a/target/linux/ath79/patches-5.10/0004-phy-add-ath79-usb-phys.patch b/target/linux/ath79/patches-5.10/0004-phy-add-ath79-usb-phys.patch deleted file mode 100644 index 56c3d61887..0000000000 --- a/target/linux/ath79/patches-5.10/0004-phy-add-ath79-usb-phys.patch +++ /dev/null @@ -1,333 +0,0 @@ -From 08c9d6ceef01893678a5d2e8a15517c745417f21 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 10:04:05 +0100 -Subject: [PATCH 04/27] phy: add ath79 usb phys - -Signed-off-by: John Crispin ---- - drivers/phy/Kconfig | 16 ++++++ - drivers/phy/Makefile | 2 + - drivers/phy/phy-ar7100-usb.c | 124 +++++++++++++++++++++++++++++++++++++++++++ - drivers/phy/phy-ar7200-usb.c | 108 +++++++++++++++++++++++++++++++++++++ - 4 files changed, 250 insertions(+) - create mode 100644 drivers/phy/phy-ar7100-usb.c - create mode 100644 drivers/phy/phy-ar7200-usb.c - ---- a/drivers/phy/Kconfig -+++ b/drivers/phy/Kconfig -@@ -24,6 +24,22 @@ config GENERIC_PHY_MIPI_DPHY - Provides a number of helpers a core functions for MIPI D-PHY - drivers to us. - -+config PHY_AR7100_USB -+ tristate "Atheros AR7100 USB PHY driver" -+ depends on ATH79 || COMPILE_TEST -+ default y if USB_EHCI_HCD_PLATFORM -+ select GENERIC_PHY -+ help -+ Enable this to support the USB PHY on Atheros AR7100 SoCs. -+ -+config PHY_AR7200_USB -+ tristate "Atheros AR7200 USB PHY driver" -+ depends on ATH79 || COMPILE_TEST -+ default y if USB_EHCI_HCD_PLATFORM -+ select GENERIC_PHY -+ help -+ Enable this to support the USB PHY on Atheros AR7200 SoCs. -+ - config PHY_LPC18XX_USB_OTG - tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver" - depends on OF && (ARCH_LPC18XX || COMPILE_TEST) ---- a/drivers/phy/Makefile -+++ b/drivers/phy/Makefile -@@ -4,6 +4,8 @@ - # - - obj-$(CONFIG_GENERIC_PHY) += phy-core.o -+obj-$(CONFIG_PHY_AR7100_USB) += phy-ar7100-usb.o -+obj-$(CONFIG_PHY_AR7200_USB) += phy-ar7200-usb.o - obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o - obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o - obj-$(CONFIG_PHY_XGENE) += phy-xgene.o ---- /dev/null -+++ b/drivers/phy/phy-ar7100-usb.c -@@ -0,0 +1,140 @@ -+/* -+ * Copyright (C) 2018 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct ar7100_usb_phy { -+ struct reset_control *rst_phy; -+ struct reset_control *rst_host; -+ struct reset_control *rst_ohci_dll; -+ void __iomem *io_base; -+ struct phy *phy; -+ int gpio; -+}; -+ -+static int ar7100_usb_phy_power_off(struct phy *phy) -+{ -+ struct ar7100_usb_phy *priv = phy_get_drvdata(phy); -+ int err = 0; -+ -+ err |= reset_control_assert(priv->rst_host); -+ err |= reset_control_assert(priv->rst_phy); -+ err |= reset_control_assert(priv->rst_ohci_dll); -+ -+ return err; -+} -+ -+static int ar7100_usb_phy_power_on(struct phy *phy) -+{ -+ struct ar7100_usb_phy *priv = phy_get_drvdata(phy); -+ int err = 0; -+ -+ err |= ar7100_usb_phy_power_off(phy); -+ mdelay(100); -+ err |= reset_control_deassert(priv->rst_ohci_dll); -+ err |= reset_control_deassert(priv->rst_phy); -+ err |= reset_control_deassert(priv->rst_host); -+ mdelay(500); -+ iowrite32(0xf0000, priv->io_base + AR71XX_USB_CTRL_REG_CONFIG); -+ iowrite32(0x20c00, priv->io_base + AR71XX_USB_CTRL_REG_FLADJ); -+ -+ return err; -+} -+ -+static const struct phy_ops ar7100_usb_phy_ops = { -+ .power_on = ar7100_usb_phy_power_on, -+ .power_off = ar7100_usb_phy_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static int ar7100_usb_phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct resource *res; -+ struct ar7100_usb_phy *priv; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ priv->io_base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(priv->io_base)) -+ return PTR_ERR(priv->io_base); -+ -+ priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy"); -+ if (IS_ERR(priv->rst_phy)) { -+ dev_err(&pdev->dev, "phy reset is missing\n"); -+ return PTR_ERR(priv->rst_phy); -+ } -+ -+ priv->rst_host = devm_reset_control_get(&pdev->dev, "usb-host"); -+ if (IS_ERR(priv->rst_host)) { -+ dev_err(&pdev->dev, "host reset is missing\n"); -+ return PTR_ERR(priv->rst_host); -+ } -+ -+ priv->rst_ohci_dll = devm_reset_control_get(&pdev->dev, "usb-ohci-dll"); -+ if (IS_ERR(priv->rst_ohci_dll)) { -+ dev_err(&pdev->dev, "ohci-dll reset is missing\n"); -+ return PTR_ERR(priv->rst_host); -+ } -+ -+ priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7100_usb_phy_ops); -+ if (IS_ERR(priv->phy)) { -+ dev_err(&pdev->dev, "failed to create PHY\n"); -+ return PTR_ERR(priv->phy); -+ } -+ -+ priv->gpio = of_get_gpio(pdev->dev.of_node, 0); -+ if (priv->gpio >= 0) { -+ int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev)); -+ -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request gpio\n"); -+ return ret; -+ } -+ gpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev)); -+ gpio_set_value(priv->gpio, 1); -+ } -+ -+ phy_set_drvdata(priv->phy, priv); -+ -+ phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); -+ -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id ar7100_usb_phy_of_match[] = { -+ { .compatible = "qca,ar7100-usb-phy" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, ar7100_usb_phy_of_match); -+ -+static struct platform_driver ar7100_usb_phy_driver = { -+ .probe = ar7100_usb_phy_probe, -+ .driver = { -+ .of_match_table = ar7100_usb_phy_of_match, -+ .name = "ar7100-usb-phy", -+ } -+}; -+module_platform_driver(ar7100_usb_phy_driver); -+ -+MODULE_DESCRIPTION("ATH79 USB PHY driver"); -+MODULE_AUTHOR("Alban Bedel "); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/phy/phy-ar7200-usb.c -@@ -0,0 +1,136 @@ -+/* -+ * Copyright (C) 2015 Alban Bedel -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+struct ar7200_usb_phy { -+ struct reset_control *rst_phy; -+ struct reset_control *rst_phy_analog; -+ struct reset_control *suspend_override; -+ struct phy *phy; -+ int gpio; -+}; -+ -+static int ar7200_usb_phy_power_on(struct phy *phy) -+{ -+ struct ar7200_usb_phy *priv = phy_get_drvdata(phy); -+ int err = 0; -+ -+ if (priv->suspend_override) -+ err = reset_control_assert(priv->suspend_override); -+ if (priv->rst_phy) -+ err |= reset_control_deassert(priv->rst_phy); -+ if (priv->rst_phy_analog) -+ err |= reset_control_deassert(priv->rst_phy_analog); -+ -+ return err; -+} -+ -+static int ar7200_usb_phy_power_off(struct phy *phy) -+{ -+ struct ar7200_usb_phy *priv = phy_get_drvdata(phy); -+ int err = 0; -+ -+ if (priv->suspend_override) -+ err = reset_control_deassert(priv->suspend_override); -+ if (priv->rst_phy) -+ err |= reset_control_assert(priv->rst_phy); -+ if (priv->rst_phy_analog) -+ err |= reset_control_assert(priv->rst_phy_analog); -+ -+ return err; -+} -+ -+static const struct phy_ops ar7200_usb_phy_ops = { -+ .power_on = ar7200_usb_phy_power_on, -+ .power_off = ar7200_usb_phy_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static int ar7200_usb_phy_probe(struct platform_device *pdev) -+{ -+ struct phy_provider *phy_provider; -+ struct ar7200_usb_phy *priv; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->rst_phy = devm_reset_control_get(&pdev->dev, "usb-phy"); -+ if (IS_ERR(priv->rst_phy)) { -+ if (PTR_ERR(priv->rst_phy) != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "phy reset is missing\n"); -+ return PTR_ERR(priv->rst_phy); -+ } -+ -+ priv->rst_phy_analog = devm_reset_control_get_optional( -+ &pdev->dev, "usb-phy-analog"); -+ if (IS_ERR(priv->rst_phy_analog)) { -+ if (PTR_ERR(priv->rst_phy_analog) == -ENOENT) -+ priv->rst_phy_analog = NULL; -+ else -+ return PTR_ERR(priv->rst_phy_analog); -+ } -+ -+ priv->suspend_override = devm_reset_control_get_optional( -+ &pdev->dev, "usb-suspend-override"); -+ if (IS_ERR(priv->suspend_override)) { -+ if (PTR_ERR(priv->suspend_override) == -ENOENT) -+ priv->suspend_override = NULL; -+ else -+ return PTR_ERR(priv->suspend_override); -+ } -+ -+ priv->phy = devm_phy_create(&pdev->dev, NULL, &ar7200_usb_phy_ops); -+ if (IS_ERR(priv->phy)) { -+ dev_err(&pdev->dev, "failed to create PHY\n"); -+ return PTR_ERR(priv->phy); -+ } -+ -+ priv->gpio = of_get_gpio(pdev->dev.of_node, 0); -+ if (priv->gpio >= 0) { -+ int ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev)); -+ -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request gpio\n"); -+ return ret; -+ } -+ gpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev)); -+ gpio_set_value(priv->gpio, 1); -+ } -+ -+ phy_set_drvdata(priv->phy, priv); -+ -+ phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id ar7200_usb_phy_of_match[] = { -+ { .compatible = "qca,ar7200-usb-phy" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, ar7200_usb_phy_of_match); -+ -+static struct platform_driver ar7200_usb_phy_driver = { -+ .probe = ar7200_usb_phy_probe, -+ .driver = { -+ .of_match_table = ar7200_usb_phy_of_match, -+ .name = "ar7200-usb-phy", -+ } -+}; -+module_platform_driver(ar7200_usb_phy_driver); -+ -+MODULE_DESCRIPTION("ATH79 USB PHY driver"); -+MODULE_AUTHOR("Alban Bedel "); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/ath79/patches-5.10/0005-usb-add-more-OF-quirk-properties.patch b/target/linux/ath79/patches-5.10/0005-usb-add-more-OF-quirk-properties.patch deleted file mode 100644 index d6d8cb6952..0000000000 --- a/target/linux/ath79/patches-5.10/0005-usb-add-more-OF-quirk-properties.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 2201818e5bd33f389beceb3943fdfcf5a698fc5b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 10:01:43 +0100 -Subject: [PATCH 05/27] usb: add more OF/quirk properties - -Signed-off-by: John Crispin ---- - drivers/usb/host/ehci-platform.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/usb/host/ehci-platform.c -+++ b/drivers/usb/host/ehci-platform.c -@@ -277,6 +277,11 @@ static int ehci_platform_probe(struct pl - ehci = hcd_to_ehci(hcd); - - if (pdata == &ehci_platform_defaults && dev->dev.of_node) { -+ of_property_read_u32(dev->dev.of_node, "caps-offset", &pdata->caps_offset); -+ -+ if (of_property_read_bool(dev->dev.of_node, "has-synopsys-hc-bug")) -+ pdata->has_synopsys_hc_bug = 1; -+ - if (of_property_read_bool(dev->dev.of_node, "big-endian-regs")) - ehci->big_endian_mmio = 1; - diff --git a/target/linux/ath79/patches-5.10/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch b/target/linux/ath79/patches-5.10/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch deleted file mode 100644 index ceda511c21..0000000000 --- a/target/linux/ath79/patches-5.10/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch +++ /dev/null @@ -1,168 +0,0 @@ -From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 09:55:13 +0100 -Subject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for - QCA9556 SoCs - -Signed-off-by: John Crispin ---- - drivers/irqchip/Makefile | 1 + - drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++ - 2 files changed, 143 insertions(+) - create mode 100644 drivers/irqchip/irq-ath79-intc.c - ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -4,6 +4,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o - obj-$(CONFIG_AL_FIC) += irq-al-fic.o - obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o - obj-$(CONFIG_ATH79) += irq-ath79-cpu.o -+obj-$(CONFIG_ATH79) += irq-ath79-intc.o - obj-$(CONFIG_ATH79) += irq-ath79-misc.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o - obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o ---- /dev/null -+++ b/drivers/irqchip/irq-ath79-intc.c -@@ -0,0 +1,142 @@ -+/* -+ * Atheros AR71xx/AR724x/AR913x specific interrupt handling -+ * -+ * Copyright (C) 2018 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#define ATH79_MAX_INTC_CASCADE 3 -+ -+struct ath79_intc { -+ struct irq_chip chip; -+ u32 irq; -+ u32 pending_mask; -+ u32 int_status; -+ u32 irq_mask[ATH79_MAX_INTC_CASCADE]; -+ u32 irq_wb_chan[ATH79_MAX_INTC_CASCADE]; -+}; -+ -+static void ath79_intc_irq_handler(struct irq_desc *desc) -+{ -+ struct irq_domain *domain = irq_desc_get_handler_data(desc); -+ struct ath79_intc *intc = domain->host_data; -+ u32 pending; -+ -+ pending = ath79_reset_rr(intc->int_status); -+ pending &= intc->pending_mask; -+ -+ if (pending) { -+ int i; -+ -+ for (i = 0; i < domain->hwirq_max; i++) -+ if (pending & intc->irq_mask[i]) { -+ if (intc->irq_wb_chan[i] != 0xffffffff) -+ ath79_ddr_wb_flush(intc->irq_wb_chan[i]); -+ generic_handle_irq(irq_find_mapping(domain, i)); -+ } -+ } else { -+ spurious_interrupt(); -+ } -+} -+ -+static void ath79_intc_irq_enable(struct irq_data *d) -+{ -+ struct ath79_intc *intc = d->domain->host_data; -+ enable_irq(intc->irq); -+} -+ -+static void ath79_intc_irq_disable(struct irq_data *d) -+{ -+ struct ath79_intc *intc = d->domain->host_data; -+ disable_irq(intc->irq); -+} -+ -+static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -+{ -+ struct ath79_intc *intc = d->host_data; -+ -+ irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops ath79_irq_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = ath79_intc_map, -+}; -+ -+static int __init ath79_intc_of_init( -+ struct device_node *node, struct device_node *parent) -+{ -+ struct irq_domain *domain; -+ struct ath79_intc *intc; -+ int cnt, cntwb, i, err; -+ -+ cnt = of_property_count_u32_elems(node, "qca,pending-bits"); -+ if (cnt > ATH79_MAX_INTC_CASCADE) -+ panic("Too many INTC pending bits\n"); -+ -+ intc = kzalloc(sizeof(*intc), GFP_KERNEL); -+ if (!intc) -+ panic("Failed to allocate INTC memory\n"); -+ intc->chip = dummy_irq_chip; -+ intc->chip.name = "INTC"; -+ intc->chip.irq_disable = ath79_intc_irq_disable; -+ intc->chip.irq_enable = ath79_intc_irq_enable; -+ -+ if (of_property_read_u32(node, "qca,int-status-addr", &intc->int_status) < 0) { -+ panic("Missing address of interrupt status register\n"); -+ } -+ -+ of_property_read_u32_array(node, "qca,pending-bits", intc->irq_mask, cnt); -+ for (i = 0; i < cnt; i++) { -+ intc->pending_mask |= intc->irq_mask[i]; -+ intc->irq_wb_chan[i] = 0xffffffff; -+ } -+ -+ cntwb = of_count_phandle_with_args( -+ node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); -+ -+ for (i = 0; i < cntwb; i++) { -+ struct of_phandle_args args; -+ u32 irq = i; -+ -+ of_property_read_u32_index( -+ node, "qca,ddr-wb-channel-interrupts", i, &irq); -+ if (irq >= ATH79_MAX_INTC_CASCADE) -+ continue; -+ -+ err = of_parse_phandle_with_args( -+ node, "qca,ddr-wb-channels", -+ "#qca,ddr-wb-channel-cells", -+ i, &args); -+ if (err) -+ return err; -+ -+ intc->irq_wb_chan[irq] = args.args[0]; -+ } -+ -+ intc->irq = irq_of_parse_and_map(node, 0); -+ if (!intc->irq) -+ panic("Failed to get INTC IRQ"); -+ -+ domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc); -+ irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain); -+ -+ return 0; -+} -+IRQCHIP_DECLARE(ath79_intc, "qca,ar9340-intc", -+ ath79_intc_of_init); diff --git a/target/linux/ath79/patches-5.10/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch b/target/linux/ath79/patches-5.10/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch deleted file mode 100644 index 13117d9a8e..0000000000 --- a/target/linux/ath79/patches-5.10/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch +++ /dev/null @@ -1,23 +0,0 @@ -From e029f998594f151008ecbfa024e2957edd2a5189 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 6 Mar 2018 09:58:19 +0100 -Subject: [PATCH 08/33] irqchip/irq-ath79-cpu: drop !OF init helper - -Signed-off-by: John Crispin ---- - drivers/irqchip/irq-ath79-cpu.c | 7 ------- - 1 file changed, 7 deletions(-) - ---- a/drivers/irqchip/irq-ath79-cpu.c -+++ b/drivers/irqchip/irq-ath79-cpu.c -@@ -85,10 +85,3 @@ static int __init ar79_cpu_intc_of_init( - } - IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc", - ar79_cpu_intc_of_init); -- --void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3) --{ -- irq_wb_chan[2] = irq_wb_chan2; -- irq_wb_chan[3] = irq_wb_chan3; -- mips_cpu_irq_init(); --} diff --git a/target/linux/ath79/patches-5.10/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch b/target/linux/ath79/patches-5.10/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch deleted file mode 100644 index bf7eb691a5..0000000000 --- a/target/linux/ath79/patches-5.10/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 25 Jun 2018 15:52:10 +0200 -Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc - -With the driver being converted from platform_data to pure OF, we need to -also add some docs. - -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: John Crispin ---- - .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt -@@ -0,0 +1,38 @@ -+* Qualcomm Atheros AR7100 PCI express root complex -+ -+Required properties: -+- compatible: should contain "qcom,ar7100-pci" to identify the core. -+- reg: Should contain the register ranges as listed in the reg-names property. -+- reg-names: Definition: Must include the following entries -+ - "cfg_base" IO Memory -+- #address-cells: set to <3> -+- #size-cells: set to <2> -+- ranges: ranges for the PCI memory and I/O regions -+- interrupt-map-mask and interrupt-map: standard PCI -+ properties to define the mapping of the PCIe interface to interrupt -+ numbers. -+- #interrupt-cells: set to <1> -+- interrupt-controller: define to enable the builtin IRQ cascade. -+ -+Optional properties: -+- interrupt-parent: phandle to the MIPS IRQ controller -+ -+* Example for ar7100 -+ pcie-controller@180c0000 { -+ compatible = "qca,ar7100-pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0x0>; -+ reg = <0x17010000 0x100>; -+ reg-names = "cfg_base"; -+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 -+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; -+ interrupt-parent = <&cpuintc>; -+ interrupts = <2>; -+ -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ -+ interrupt-map-mask = <0 0 0 1>; -+ interrupt-map = <0 0 0 0 &pcie0 0>; -+ }; diff --git a/target/linux/ath79/patches-5.10/0018-MIPS-pci-ar71xx-convert-to-OF.patch b/target/linux/ath79/patches-5.10/0018-MIPS-pci-ar71xx-convert-to-OF.patch deleted file mode 100644 index e600a4f0d9..0000000000 --- a/target/linux/ath79/patches-5.10/0018-MIPS-pci-ar71xx-convert-to-OF.patch +++ /dev/null @@ -1,202 +0,0 @@ -From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:07:23 +0200 -Subject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF - -With the ath79 target getting converted to pure OF, we can drop all the -platform data code and add the missing OF bits to the driver. We also add -a irq domain for the PCI/e controllers cascade, thus making it usable from -dts files. - -Signed-off-by: John Crispin ---- - arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++----------------------- - 1 file changed, 41 insertions(+), 41 deletions(-) - ---- a/arch/mips/pci/pci-ar71xx.c -+++ b/arch/mips/pci/pci-ar71xx.c -@@ -15,8 +15,11 @@ - #include - #include - #include -+#include - #include - #include -+#include -+#include - - #include - #include -@@ -46,12 +49,13 @@ - #define AR71XX_PCI_IRQ_COUNT 5 - - struct ar71xx_pci_controller { -+ struct device_node *np; - void __iomem *cfg_base; - int irq; -- int irq_base; - struct pci_controller pci_ctrl; - struct resource io_res; - struct resource mem_res; -+ struct irq_domain *domain; - }; - - /* Byte lane enable bits */ -@@ -225,29 +229,30 @@ static struct pci_ops ar71xx_pci_ops = { - - static void ar71xx_pci_irq_handler(struct irq_desc *desc) - { -- struct ar71xx_pci_controller *apc; - void __iomem *base = ath79_reset_base; -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc); - u32 pending; - -- apc = irq_desc_get_handler_data(desc); -- -+ chained_irq_enter(chip, desc); - pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); - - if (pending & AR71XX_PCI_INT_DEV0) -- generic_handle_irq(apc->irq_base + 0); -+ generic_handle_irq(irq_linear_revmap(apc->domain, 1)); - - else if (pending & AR71XX_PCI_INT_DEV1) -- generic_handle_irq(apc->irq_base + 1); -+ generic_handle_irq(irq_linear_revmap(apc->domain, 2)); - - else if (pending & AR71XX_PCI_INT_DEV2) -- generic_handle_irq(apc->irq_base + 2); -+ generic_handle_irq(irq_linear_revmap(apc->domain, 3)); - - else if (pending & AR71XX_PCI_INT_CORE) -- generic_handle_irq(apc->irq_base + 4); -+ generic_handle_irq(irq_linear_revmap(apc->domain, 4)); - - else - spurious_interrupt(); -+ chained_irq_exit(chip, desc); - } - - static void ar71xx_pci_irq_unmask(struct irq_data *d) -@@ -258,7 +263,7 @@ static void ar71xx_pci_irq_unmask(struct - u32 t; - - apc = irq_data_get_irq_chip_data(d); -- irq = d->irq - apc->irq_base; -+ irq = irq_linear_revmap(apc->domain, d->irq); - - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); - __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -@@ -275,7 +280,7 @@ static void ar71xx_pci_irq_mask(struct i - u32 t; - - apc = irq_data_get_irq_chip_data(d); -- irq = d->irq - apc->irq_base; -+ irq = irq_linear_revmap(apc->domain, d->irq); - - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); - __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -@@ -291,24 +296,31 @@ static struct irq_chip ar71xx_pci_irq_ch - .irq_mask_ack = ar71xx_pci_irq_mask, - }; - -+static int ar71xx_pci_irq_map(struct irq_domain *d, -+ unsigned int irq, irq_hw_number_t hw) -+{ -+ struct ar71xx_pci_controller *apc = d->host_data; -+ -+ irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq); -+ irq_set_chip_data(irq, apc); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops ar71xx_pci_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = ar71xx_pci_irq_map, -+}; -+ - static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) - { - void __iomem *base = ath79_reset_base; -- int i; - - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); - -- BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); -- -- apc->irq_base = ATH79_PCI_IRQ_BASE; -- for (i = apc->irq_base; -- i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) { -- irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, -- handle_level_irq); -- irq_set_chip_data(i, apc); -- } -- -+ apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT, -+ &ar71xx_pci_domain_ops, apc); - irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler, - apc); - } -@@ -325,6 +337,11 @@ static void ar71xx_pci_reset(void) - mdelay(100); - } - -+static const struct of_device_id ar71xx_pci_ids[] = { -+ { .compatible = "qca,ar7100-pci" }, -+ {}, -+}; -+ - static int ar71xx_pci_probe(struct platform_device *pdev) - { - struct ar71xx_pci_controller *apc; -@@ -345,26 +362,6 @@ static int ar71xx_pci_probe(struct platf - if (apc->irq < 0) - return -EINVAL; - -- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base"); -- if (!res) -- return -EINVAL; -- -- apc->io_res.parent = res; -- apc->io_res.name = "PCI IO space"; -- apc->io_res.start = res->start; -- apc->io_res.end = res->end; -- apc->io_res.flags = IORESOURCE_IO; -- -- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base"); -- if (!res) -- return -EINVAL; -- -- apc->mem_res.parent = res; -- apc->mem_res.name = "PCI memory space"; -- apc->mem_res.start = res->start; -- apc->mem_res.end = res->end; -- apc->mem_res.flags = IORESOURCE_MEM; -- - ar71xx_pci_reset(); - - /* setup COMMAND register */ -@@ -377,9 +374,11 @@ static int ar71xx_pci_probe(struct platf - - ar71xx_pci_irq_init(apc); - -+ apc->np = pdev->dev.of_node; - apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; - apc->pci_ctrl.mem_resource = &apc->mem_res; - apc->pci_ctrl.io_resource = &apc->io_res; -+ pci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node); - - register_pci_controller(&apc->pci_ctrl); - -@@ -390,6 +389,7 @@ static struct platform_driver ar71xx_pci - .probe = ar71xx_pci_probe, - .driver = { - .name = "ar71xx-pci", -+ .of_match_table = of_match_ptr(ar71xx_pci_ids), - }, - }; - diff --git a/target/linux/ath79/patches-5.10/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch b/target/linux/ath79/patches-5.10/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch deleted file mode 100644 index a0af79cb4d..0000000000 --- a/target/linux/ath79/patches-5.10/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch +++ /dev/null @@ -1,61 +0,0 @@ -From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 25 Jun 2018 15:52:02 +0200 -Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc - -With the driver being converted from platform_data to pure OF, we need to -also add some docs. - -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: John Crispin ---- - .../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++ - 1 file changed, 42 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt -@@ -0,0 +1,42 @@ -+* Qualcomm Atheros AR724X PCI express root complex -+ -+Required properties: -+- compatible: should contain "qcom,ar7240-pci" to identify the core. -+- reg: Should contain the register ranges as listed in the reg-names property. -+- reg-names: Definition: Must include the following entries -+ - "crp_base" Configuration registers -+ - "ctrl_base" Control registers -+ - "cfg_base" IO Memory -+- #address-cells: set to <3> -+- #size-cells: set to <2> -+- ranges: ranges for the PCI memory and I/O regions -+- interrupt-map-mask and interrupt-map: standard PCI -+ properties to define the mapping of the PCIe interface to interrupt -+ numbers. -+- #interrupt-cells: set to <1> -+- interrupt-parent: phandle to the MIPS IRQ controller -+ -+Optional properties: -+- interrupt-controller: define to enable the builtin IRQ cascade. -+ -+* Example for qca9557 -+ pcie-controller@180c0000 { -+ compatible = "qcom,ar7240-pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0x0>; -+ reg = <0x180c0000 0x1000>, -+ <0x180f0000 0x100>, -+ <0x14000000 0x1000>; -+ reg-names = "crp_base", "ctrl_base", "cfg_base"; -+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 -+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>; -+ interrupt-parent = <&intc2>; -+ interrupts = <1>; -+ -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ -+ interrupt-map-mask = <0 0 0 1>; -+ interrupt-map = <0 0 0 0 &pcie0 0>; -+ }; diff --git a/target/linux/ath79/patches-5.10/0020-MIPS-pci-ar724x-convert-to-OF.patch b/target/linux/ath79/patches-5.10/0020-MIPS-pci-ar724x-convert-to-OF.patch deleted file mode 100644 index 2772c53392..0000000000 --- a/target/linux/ath79/patches-5.10/0020-MIPS-pci-ar724x-convert-to-OF.patch +++ /dev/null @@ -1,205 +0,0 @@ -From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:07:37 +0200 -Subject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF - -With the ath79 target getting converted to pure OF, we can drop all the -platform data code and add the missing OF bits to the driver. We also add -a irq domain for the PCI/e controllers cascade, thus making it usable from -dts files. - -Signed-off-by: John Crispin ---- - arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------ - 1 file changed, 42 insertions(+), 46 deletions(-) - ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -11,8 +11,11 @@ - #include - #include - #include -+#include - #include - #include -+#include -+#include - - #define AR724X_PCI_REG_APP 0x00 - #define AR724X_PCI_REG_RESET 0x18 -@@ -42,17 +45,20 @@ struct ar724x_pci_controller { - void __iomem *crp_base; - - int irq; -- int irq_base; - - bool link_up; - bool bar0_is_cached; - u32 bar0_value; - -+ struct device_node *np; - struct pci_controller pci_controller; -+ struct irq_domain *domain; - struct resource io_res; - struct resource mem_res; - }; - -+static struct irq_chip ar724x_pci_irq_chip; -+ - static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc) - { - u32 reset; -@@ -228,35 +234,31 @@ static struct pci_ops ar724x_pci_ops = { - - static void ar724x_pci_irq_handler(struct irq_desc *desc) - { -- struct ar724x_pci_controller *apc; -- void __iomem *base; -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc); - u32 pending; - -- apc = irq_desc_get_handler_data(desc); -- base = apc->ctrl_base; -- -- pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & -- __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ chained_irq_enter(chip, desc); -+ pending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) & -+ __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK); - - if (pending & AR724X_PCI_INT_DEV0) -- generic_handle_irq(apc->irq_base + 0); -- -+ generic_handle_irq(irq_linear_revmap(apc->domain, 1)); - else - spurious_interrupt(); -+ chained_irq_exit(chip, desc); - } - - static void ar724x_pci_irq_unmask(struct irq_data *d) - { - struct ar724x_pci_controller *apc; - void __iomem *base; -- int offset; - u32 t; - - apc = irq_data_get_irq_chip_data(d); - base = apc->ctrl_base; -- offset = apc->irq_base - d->irq; - -- switch (offset) { -+ switch (irq_linear_revmap(apc->domain, d->irq)) { - case 0: - t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); - __raw_writel(t | AR724X_PCI_INT_DEV0, -@@ -270,14 +272,12 @@ static void ar724x_pci_irq_mask(struct i - { - struct ar724x_pci_controller *apc; - void __iomem *base; -- int offset; - u32 t; - - apc = irq_data_get_irq_chip_data(d); - base = apc->ctrl_base; -- offset = apc->irq_base - d->irq; - -- switch (offset) { -+ switch (irq_linear_revmap(apc->domain, d->irq)) { - case 0: - t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); - __raw_writel(t & ~AR724X_PCI_INT_DEV0, -@@ -302,26 +302,34 @@ static struct irq_chip ar724x_pci_irq_ch - .irq_mask_ack = ar724x_pci_irq_mask, - }; - -+static int ar724x_pci_irq_map(struct irq_domain *d, -+ unsigned int irq, irq_hw_number_t hw) -+{ -+ struct ar724x_pci_controller *apc = d->host_data; -+ -+ irq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq); -+ irq_set_chip_data(irq, apc); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops ar724x_pci_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = ar724x_pci_irq_map, -+}; -+ - static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc, - int id) - { - void __iomem *base; -- int i; - - base = apc->ctrl_base; - - __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); - __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); - -- apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT); -- -- for (i = apc->irq_base; -- i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) { -- irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, -- handle_level_irq); -- irq_set_chip_data(i, apc); -- } -- -+ apc->domain = irq_domain_add_linear(apc->np, 2, -+ &ar724x_pci_domain_ops, apc); - irq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler, - apc); - } -@@ -388,29 +396,11 @@ static int ar724x_pci_probe(struct platf - if (apc->irq < 0) - return -EINVAL; - -- res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base"); -- if (!res) -- return -EINVAL; -- -- apc->io_res.parent = res; -- apc->io_res.name = "PCI IO space"; -- apc->io_res.start = res->start; -- apc->io_res.end = res->end; -- apc->io_res.flags = IORESOURCE_IO; -- -- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base"); -- if (!res) -- return -EINVAL; -- -- apc->mem_res.parent = res; -- apc->mem_res.name = "PCI memory space"; -- apc->mem_res.start = res->start; -- apc->mem_res.end = res->end; -- apc->mem_res.flags = IORESOURCE_MEM; -- -+ apc->np = pdev->dev.of_node; - apc->pci_controller.pci_ops = &ar724x_pci_ops; - apc->pci_controller.io_resource = &apc->io_res; - apc->pci_controller.mem_resource = &apc->mem_res; -+ pci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node); - - /* - * Do the full PCIE Root Complex Initialization Sequence if the PCIe -@@ -432,10 +422,16 @@ static int ar724x_pci_probe(struct platf - return 0; - } - -+static const struct of_device_id ar724x_pci_ids[] = { -+ { .compatible = "qcom,ar7240-pci" }, -+ {}, -+}; -+ - static struct platform_driver ar724x_pci_driver = { - .probe = ar724x_pci_probe, - .driver = { - .name = "ar724x-pci", -+ .of_match_table = of_match_ptr(ar724x_pci_ids), - }, - }; - diff --git a/target/linux/ath79/patches-5.10/0032-MIPS-ath79-sanitize-symbols.patch b/target/linux/ath79/patches-5.10/0032-MIPS-ath79-sanitize-symbols.patch deleted file mode 100644 index 40cd1689a0..0000000000 --- a/target/linux/ath79/patches-5.10/0032-MIPS-ath79-sanitize-symbols.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 3fc8585cf76022dba7496627074d42af88c30718 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 23 Jun 2018 15:16:55 +0200 -Subject: [PATCH 32/33] MIPS: ath79: sanitize symbols - -We no longer need to select which SoCs are supported as the whole arch -code is always built. So lets drop all the SoC symbols - -Signed-off-by: John Crispin ---- - arch/mips/Kconfig | 2 ++ - arch/mips/ath79/Kconfig | 44 +++++--------------------------------------- - arch/mips/pci/Makefile | 2 +- - 3 files changed, 8 insertions(+), 40 deletions(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -245,6 +245,8 @@ config ATH79 - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_MIPS16 - select SYS_SUPPORTS_ZBOOT_UART_PROM -+ select HAVE_PCI -+ select USB_ARCH_HAS_EHCI - select USE_OF - select USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM - help ---- a/arch/mips/ath79/Kconfig -+++ b/arch/mips/ath79/Kconfig -@@ -1,48 +1,14 @@ - # SPDX-License-Identifier: GPL-2.0 - if ATH79 - --config SOC_AR71XX -- select HAVE_PCI -- def_bool n -- --config SOC_AR724X -- select HAVE_PCI -- select PCI_AR724X if PCI -- def_bool n -- --config SOC_AR913X -- def_bool n -- --config SOC_AR933X -- def_bool n -- --config SOC_AR934X -- select HAVE_PCI -- select PCI_AR724X if PCI -- def_bool n -- --config SOC_QCA955X -- select HAVE_PCI -- select PCI_AR724X if PCI -+config PCI_AR71XX -+ bool "PCI support for AR7100 type SoCs" -+ depends on PCI - def_bool n - - config PCI_AR724X -- def_bool n -- --config ATH79_DEV_GPIO_BUTTONS -- def_bool n -- --config ATH79_DEV_LEDS_GPIO -- def_bool n -- --config ATH79_DEV_SPI -- def_bool n -- --config ATH79_DEV_USB -- def_bool n -- --config ATH79_DEV_WMAC -- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) -+ bool "PCI support for AR724x type SoCs" -+ depends on PCI - def_bool n - - endif ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -21,7 +21,7 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o - ops-bcm63xx.o - obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o - obj-$(CONFIG_PCI_AR2315) += pci-ar2315.o --obj-$(CONFIG_SOC_AR71XX) += pci-ar71xx.o -+obj-$(CONFIG_PCI_AR71XX) += pci-ar71xx.o - obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o - obj-$(CONFIG_PCI_XTALK_BRIDGE) += pci-xtalk-bridge.o - # diff --git a/target/linux/ath79/patches-5.10/0033-spi-ath79-drop-pdata-support.patch b/target/linux/ath79/patches-5.10/0033-spi-ath79-drop-pdata-support.patch deleted file mode 100644 index 162a82bda3..0000000000 --- a/target/linux/ath79/patches-5.10/0033-spi-ath79-drop-pdata-support.patch +++ /dev/null @@ -1,70 +0,0 @@ -From c4e197bbcecc7233aa9e553e7047fa50e4e1fe77 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 25 Jun 2018 15:52:34 +0200 -Subject: [PATCH 33/33] spi: ath79: drop pdata support - -The target is being converted to pure OF. We can therefore drop all of the -platform data code from the driver. - -Cc: linux-spi@vger.kernel.org -Acked-by: Mark Brown -Signed-off-by: John Crispin ---- - include/linux/platform_data/spi-ath79.h | 16 ------------------- - drivers/spi/spi-ath79.c | 8 -------- - 2 files changed, 27 deletions(-) - delete mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h - ---- a/include/linux/platform_data/spi-ath79.h -+++ /dev/null -@@ -1,16 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ --/* -- * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller -- * -- * Copyright (C) 2008-2010 Gabor Juhos -- */ -- --#ifndef _ATH79_SPI_PLATFORM_H --#define _ATH79_SPI_PLATFORM_H -- --struct ath79_spi_platform_data { -- unsigned bus_num; -- unsigned num_chipselect; --}; -- --#endif /* _ATH79_SPI_PLATFORM_H */ ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -19,7 +19,6 @@ - #include - #include - #include --#include - - #define DRV_NAME "ath79-spi" - -@@ -138,7 +137,6 @@ static int ath79_spi_probe(struct platfo - { - struct spi_master *master; - struct ath79_spi *sp; -- struct ath79_spi_platform_data *pdata; - unsigned long rate; - int ret; - -@@ -152,15 +150,9 @@ static int ath79_spi_probe(struct platfo - master->dev.of_node = pdev->dev.of_node; - platform_set_drvdata(pdev, sp); - -- pdata = dev_get_platdata(&pdev->dev); -- - master->use_gpio_descriptors = true; - master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); - master->flags = SPI_MASTER_GPIO_SS; -- if (pdata) { -- master->bus_num = pdata->bus_num; -- master->num_chipselect = pdata->num_chipselect; -- } - - sp->bitbang.master = master; - sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ath79/patches-5.10/0034-MIPS-ath79-ath9k-exports.patch b/target/linux/ath79/patches-5.10/0034-MIPS-ath79-ath9k-exports.patch deleted file mode 100644 index e460fe58f3..0000000000 --- a/target/linux/ath79/patches-5.10/0034-MIPS-ath79-ath9k-exports.patch +++ /dev/null @@ -1,36 +0,0 @@ -From: John Crispin -Subject: [PATCH] ath79: make ahb wifi work - -Submitted-by: John Crispin ---- - arch/mips/ath79/common.c | 3 +++ - mips/include/asm/mach-ath79/ath79.h | 1+ - 1 file changed, 4 insertions(+) - ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -31,11 +31,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq); - - enum ath79_soc_type ath79_soc; - unsigned int ath79_soc_rev; -+EXPORT_SYMBOL_GPL(ath79_soc_rev); - - void __iomem *ath79_pll_base; - void __iomem *ath79_reset_base; - EXPORT_SYMBOL_GPL(ath79_reset_base); --static void __iomem *ath79_ddr_base; -+void __iomem *ath79_ddr_base; -+EXPORT_SYMBOL_GPL(ath79_ddr_base); - static void __iomem *ath79_ddr_wb_flush_base; - static void __iomem *ath79_ddr_pci_win_base; - ---- a/arch/mips/include/asm/mach-ath79/ath79.h -+++ b/arch/mips/include/asm/mach-ath79/ath79.h -@@ -149,6 +149,7 @@ void ath79_ddr_wb_flush(unsigned int reg - void ath79_ddr_set_pci_windows(void); - - extern void __iomem *ath79_pll_base; -+extern void __iomem *ath79_ddr_base; - extern void __iomem *ath79_reset_base; - - static inline void ath79_pll_wr(unsigned reg, u32 val) diff --git a/target/linux/ath79/patches-5.10/0036-MIPS-ath79-remove-irq-code-from-pci.patch b/target/linux/ath79/patches-5.10/0036-MIPS-ath79-remove-irq-code-from-pci.patch deleted file mode 100644 index 4732d1b2c8..0000000000 --- a/target/linux/ath79/patches-5.10/0036-MIPS-ath79-remove-irq-code-from-pci.patch +++ /dev/null @@ -1,149 +0,0 @@ -From: John Crispin -Subject: ath79: fix remove irq code from pci driver patch - -This patch got mangled in the void while rebasing it. - -Submitted-by: John Crispin ---- - arch/mips/pci/pci-ar71xx.c | 107 ------------------ - 1 file changed, 141 deletions(-) - ---- a/arch/mips/pci/pci-ar71xx.c -+++ b/arch/mips/pci/pci-ar71xx.c -@@ -51,11 +51,9 @@ - struct ar71xx_pci_controller { - struct device_node *np; - void __iomem *cfg_base; -- int irq; - struct pci_controller pci_ctrl; - struct resource io_res; - struct resource mem_res; -- struct irq_domain *domain; - }; - - /* Byte lane enable bits */ -@@ -227,104 +225,6 @@ static struct pci_ops ar71xx_pci_ops = { - .write = ar71xx_pci_write_config, - }; - --static void ar71xx_pci_irq_handler(struct irq_desc *desc) --{ -- void __iomem *base = ath79_reset_base; -- struct irq_chip *chip = irq_desc_get_chip(desc); -- struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc); -- u32 pending; -- -- chained_irq_enter(chip, desc); -- pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & -- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- -- if (pending & AR71XX_PCI_INT_DEV0) -- generic_handle_irq(irq_linear_revmap(apc->domain, 1)); -- -- else if (pending & AR71XX_PCI_INT_DEV1) -- generic_handle_irq(irq_linear_revmap(apc->domain, 2)); -- -- else if (pending & AR71XX_PCI_INT_DEV2) -- generic_handle_irq(irq_linear_revmap(apc->domain, 3)); -- -- else if (pending & AR71XX_PCI_INT_CORE) -- generic_handle_irq(irq_linear_revmap(apc->domain, 4)); -- -- else -- spurious_interrupt(); -- chained_irq_exit(chip, desc); --} -- --static void ar71xx_pci_irq_unmask(struct irq_data *d) --{ -- struct ar71xx_pci_controller *apc; -- unsigned int irq; -- void __iomem *base = ath79_reset_base; -- u32 t; -- -- apc = irq_data_get_irq_chip_data(d); -- irq = irq_linear_revmap(apc->domain, d->irq); -- -- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- -- /* flush write */ -- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); --} -- --static void ar71xx_pci_irq_mask(struct irq_data *d) --{ -- struct ar71xx_pci_controller *apc; -- unsigned int irq; -- void __iomem *base = ath79_reset_base; -- u32 t; -- -- apc = irq_data_get_irq_chip_data(d); -- irq = irq_linear_revmap(apc->domain, d->irq); -- -- t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- -- /* flush write */ -- __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); --} -- --static struct irq_chip ar71xx_pci_irq_chip = { -- .name = "AR71XX PCI", -- .irq_mask = ar71xx_pci_irq_mask, -- .irq_unmask = ar71xx_pci_irq_unmask, -- .irq_mask_ack = ar71xx_pci_irq_mask, --}; -- --static int ar71xx_pci_irq_map(struct irq_domain *d, -- unsigned int irq, irq_hw_number_t hw) --{ -- struct ar71xx_pci_controller *apc = d->host_data; -- -- irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq); -- irq_set_chip_data(irq, apc); -- -- return 0; --} -- --static const struct irq_domain_ops ar71xx_pci_domain_ops = { -- .xlate = irq_domain_xlate_onecell, -- .map = ar71xx_pci_irq_map, --}; -- --static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) --{ -- void __iomem *base = ath79_reset_base; -- -- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); -- __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); -- -- apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT, -- &ar71xx_pci_domain_ops, apc); -- irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler, -- apc); --} -- - static void ar71xx_pci_reset(void) - { - ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); -@@ -358,10 +258,6 @@ static int ar71xx_pci_probe(struct platf - if (IS_ERR(apc->cfg_base)) - return PTR_ERR(apc->cfg_base); - -- apc->irq = platform_get_irq(pdev, 0); -- if (apc->irq < 0) -- return -EINVAL; -- - ar71xx_pci_reset(); - - /* setup COMMAND register */ -@@ -372,8 +268,6 @@ static int ar71xx_pci_probe(struct platf - /* clear bus errors */ - ar71xx_pci_check_error(apc, 1); - -- ar71xx_pci_irq_init(apc); -- - apc->np = pdev->dev.of_node; - apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; - apc->pci_ctrl.mem_resource = &apc->mem_res; diff --git a/target/linux/ath79/patches-5.10/0037-missing-registers.patch b/target/linux/ath79/patches-5.10/0037-missing-registers.patch deleted file mode 100644 index 0e6ac52ade..0000000000 --- a/target/linux/ath79/patches-5.10/0037-missing-registers.patch +++ /dev/null @@ -1,20 +0,0 @@ -From: Christian Lamparter -Subject: [PATCH] ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for - - ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344 - - Signed-off-by: Christian Lamparter - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1226,6 +1226,10 @@ - #define AR934X_ETH_CFG_RDV_DELAY BIT(16) - #define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 - #define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 -+#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18 -+#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3 -+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20 - - /* - * QCA953X GMAC Interface diff --git a/target/linux/ath79/patches-5.10/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch b/target/linux/ath79/patches-5.10/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch deleted file mode 100644 index bc09062dc5..0000000000 --- a/target/linux/ath79/patches-5.10/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Mon, 18 Mar 2019 00:54:06 +0100 -Subject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers - -This adds missing GMAC register definitions for the Qualcomm Atheros -QCA955X series MIPS SoCs. - -They originate from the platforms U-Boot code and the AVM FRITZ!WLAN -Repeater 450E's GPL tarball. - -Signed-off-by: David Bauer ---- - .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1246,7 +1246,12 @@ - */ - - #define QCA955X_GMAC_REG_ETH_CFG 0x00 -+#define QCA955X_GMAC_REG_SGMII_RESET 0x14 - #define QCA955X_GMAC_REG_SGMII_SERDES 0x18 -+#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c -+#define QCA955X_GMAC_REG_MR_AN_STATUS 0x20 -+#define QCA955X_GMAC_REG_SGMII_CONFIG 0x34 -+#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58 - - #define QCA955X_ETH_CFG_RGMII_EN BIT(0) - #define QCA955X_ETH_CFG_MII_GE0 BIT(1) -@@ -1268,9 +1273,58 @@ - #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 - #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 - -+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET 0 -+#define QCA955X_SGMII_RESET_RX_CLK_N BIT(0) -+#define QCA955X_SGMII_RESET_TX_CLK_N BIT(1) -+#define QCA955X_SGMII_RESET_RX_125M_N BIT(2) -+#define QCA955X_SGMII_RESET_TX_125M_N BIT(3) -+#define QCA955X_SGMII_RESET_HW_RX_125M_N BIT(4) -+ - #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15) - #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23 - #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf -+ -+#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) -+#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) -+#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9) -+#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11) -+#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) -+#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) -+#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14) -+#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) -+ -+#define QCA955X_MR_AN_STATUS_EXT_CAP BIT(0) -+#define QCA955X_MR_AN_STATUS_LINK_UP BIT(2) -+#define QCA955X_MR_AN_STATUS_AN_ABILITY BIT(3) -+#define QCA955X_MR_AN_STATUS_REMOTE_FAULT BIT(4) -+#define QCA955X_MR_AN_STATUS_AN_COMPLETE BIT(5) -+#define QCA955X_MR_AN_STATUS_NO_PREAMBLE BIT(6) -+#define QCA955X_MR_AN_STATUS_BASE_PAGE BIT(7) -+ -+#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 -+#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 -+#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE BIT(3) -+#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED BIT(4) -+#define QCA955X_SGMII_CONFIG_FORCE_SPEED BIT(5) -+#define QCA955X_SGMII_CONFIG_SPEED_SHIFT 6 -+#define QCA955X_SGMII_CONFIG_SPEED_MASK 0xc0 -+#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK BIT(8) -+#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED BIT(9) -+#define QCA955X_SGMII_CONFIG_MDIO_ENABLE BIT(10) -+#define QCA955X_SGMII_CONFIG_MDIO_PULSE BIT(11) -+#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE BIT(12) -+#define QCA955X_SGMII_CONFIG_PRBS_ENABLE BIT(13) -+#define QCA955X_SGMII_CONFIG_BERT_ENABLE BIT(14) -+ -+#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff -+#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0 -+#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff00 -+#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8 -+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff0000 -+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 -+#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf000000 -+#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24 -+ - /* - * QCA956X GMAC Interface - */ diff --git a/target/linux/ath79/patches-5.10/0039-MIPS-ath79-export-UART1-reference-clock.patch b/target/linux/ath79/patches-5.10/0039-MIPS-ath79-export-UART1-reference-clock.patch deleted file mode 100644 index b24ff21692..0000000000 --- a/target/linux/ath79/patches-5.10/0039-MIPS-ath79-export-UART1-reference-clock.patch +++ /dev/null @@ -1,67 +0,0 @@ -From: Daniel Golle -Subject: [PATCH] ath79: add support for Atheros AR934x HS UART - -AR934x chips also got the 'old' qca,ar9330-uart in addition to the -'new' ns16550a compatible one. Add support for UART1 clock selector as -well as device-tree bindings in ar934x.dtsi to make use of that uart. - -Reported-by: Piotr Dymacz -Submitted-by: Daniel Golle ---- - arch/mips/ath79/clock.c | 7 +++++++ - .../mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + - include/dt-bindings/clock/ath79-clk.h | 3 ++- - 3 files changed, 10 insertions(+), 1 deletion(-) - ---- a/arch/mips/ath79/clock.c -+++ b/arch/mips/ath79/clock.c -@@ -40,6 +40,7 @@ static const char * const clk_names[ATH7 - [ATH79_CLK_AHB] = "ahb", - [ATH79_CLK_REF] = "ref", - [ATH79_CLK_MDIO] = "mdio", -+ [ATH79_CLK_UART1] = "uart1", - }; - - static const char * __init ath79_clk_name(int type) -@@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo - if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) - ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000); - -+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL) -+ ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000); -+ - iounmap(dpll_base); - } - -@@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt( - if (!clks[ATH79_CLK_MDIO]) - clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF]; - -+ if (!clks[ATH79_CLK_UART1]) -+ clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF]; -+ - if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { - pr_err("%pOF: could not register clk provider\n", np); - goto err_iounmap; ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -348,6 +348,7 @@ - #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - - #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) -+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7) - - #define QCA953X_PLL_CPU_CONFIG_REG 0x00 - #define QCA953X_PLL_DDR_CONFIG_REG 0x04 ---- a/include/dt-bindings/clock/ath79-clk.h -+++ b/include/dt-bindings/clock/ath79-clk.h -@@ -11,7 +11,8 @@ - #define ATH79_CLK_AHB 2 - #define ATH79_CLK_REF 3 - #define ATH79_CLK_MDIO 4 -+#define ATH79_CLK_UART1 5 - --#define ATH79_CLK_END 5 -+#define ATH79_CLK_END 6 - - #endif /* __DT_BINDINGS_ATH79_CLK_H */ diff --git a/target/linux/ath79/patches-5.10/004-register_gpio_driver_earlier.patch b/target/linux/ath79/patches-5.10/004-register_gpio_driver_earlier.patch deleted file mode 100644 index 154de918a5..0000000000 --- a/target/linux/ath79/patches-5.10/004-register_gpio_driver_earlier.patch +++ /dev/null @@ -1,26 +0,0 @@ -From: John Crispin -Subject: ath79: Register GPIO driver earlier - -HACK: register the GPIO driver earlier to ensure that gpio_request calls -from mach files succeed. - -Submitted-by: John Crispin ---- - drivers/gpio/gpio-ath79.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/gpio/gpio-ath79.c -+++ b/drivers/gpio/gpio-ath79.c -@@ -306,7 +306,11 @@ static struct platform_driver ath79_gpio - .probe = ath79_gpio_probe, - }; - --module_platform_driver(ath79_gpio_driver); -+static int __init ath79_gpio_init(void) -+{ -+ return platform_driver_register(&ath79_gpio_driver); -+} -+postcore_initcall(ath79_gpio_init); - - MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support"); - MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ath79/patches-5.10/0040-ath79-sgmii-config.patch b/target/linux/ath79/patches-5.10/0040-ath79-sgmii-config.patch deleted file mode 100644 index 4c2b94899a..0000000000 --- a/target/linux/ath79/patches-5.10/0040-ath79-sgmii-config.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: David Bauer -Subject: [PATCH] ath79: force SGMII SerDes mode to MAC operation - -The mode on the SGMII SerDes on the QCA9563 is 1000 Base-X by default. -This only allows for 1000 Mbit/s links, however when used with an SGMII -PHY in 100 Mbit/s link mode, the link remains dead. - -This strictly has nothing to do with the SerDes calibration, however it -is done at the same point in the QCA reference U-Boot which is the -blueprint for everything happening here. As the current state is more or -less a hack, this should be fine. - -This fixes the issues outlined above on a TP-Link EAP-225 Outdoor. - -Reported-by: Tom Herbers -Tested-by: Tom Herbers -Submitted-by: David Bauer ---- - arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 + - 1 files changed, 1 insertion(+) - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -1376,5 +1376,6 @@ - - #define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0 - #define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7 -+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC 0x2 - - #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch b/target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch deleted file mode 100644 index e99d067c48..0000000000 --- a/target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a449cd03db4d0e1d292b3734f7676634cfd94f53 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sun, 25 Oct 2020 01:14:22 +0200 -Subject: [PATCH] mtd: spi-nor: use 4 bit locking for MX25L12805D - -Macronix MX25L12805D supports locking with 4 block -protection bits in its status register. Add the corresponding -flag in order to clear these bits when unloking the flash. - -Otherwise, the flash might not be writable depending on the state -left by the bootloader. - -Tested-on: Ubiquiti UniFi AC Lite (ath79) - -Fixes commit 62593cf40b23 ("mtd: spi-nor: refactor block protection functions") - -Signed-off-by: David Bauer ---- - drivers/mtd/spi-nor/macronix.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/macronix.c -+++ b/drivers/mtd/spi-nor/macronix.c -@@ -51,7 +51,8 @@ static const struct flash_info macronix_ - { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) }, - { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) }, - { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, -- { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K) }, -+ { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K | -+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) }, - { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, - { "mx25r1635f", INFO(0xc22815, 0, 64 * 1024, 32, - SECT_4K | SPI_NOR_DUAL_READ | diff --git a/target/linux/ath79/patches-5.10/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch b/target/linux/ath79/patches-5.10/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch deleted file mode 100644 index f596ddb733..0000000000 --- a/target/linux/ath79/patches-5.10/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch +++ /dev/null @@ -1,130 +0,0 @@ -From: David Bauer -Date: Sat, 11 Apr 2020 14:03:12 +0200 -Subject: MIPS: pci-ar724x: add QCA9550 reset sequence - -The QCA9550 family of SoCs have a slightly different reset -sequence compared to older chips. - -Normally the bootloader performs this sequence, however -some bootloader implementation expect the operating system -to clear the reset. - -Also get the resets from OF to support handling of the second -PCIe root-complex on the QCA9558. - -Signed-off-by: David Bauer - ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -391,6 +391,7 @@ - #define QCA955X_PLL_CPU_CONFIG_REG 0x00 - #define QCA955X_PLL_DDR_CONFIG_REG 0x04 - #define QCA955X_PLL_CLK_CTRL_REG 0x08 -+#define QCA955X_PLL_PCIE_CONFIG_REG 0x0c - #define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 - #define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 - #define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c -@@ -476,6 +477,9 @@ - #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) - #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -+#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD BIT(30) -+#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS BIT(16) -+ - #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5) - #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6) - #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7) ---- a/arch/mips/pci/pci-ar724x.c -+++ b/arch/mips/pci/pci-ar724x.c -@@ -8,6 +8,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -55,6 +56,9 @@ struct ar724x_pci_controller { - struct irq_domain *domain; - struct resource io_res; - struct resource mem_res; -+ -+ struct reset_control *hc_reset; -+ struct reset_control *phy_reset; - }; - - static struct irq_chip ar724x_pci_irq_chip; -@@ -340,18 +344,30 @@ static void ar724x_pci_hw_init(struct ar - int wait = 0; - - /* deassert PCIe host controller and PCIe PHY reset */ -- ath79_device_reset_clear(AR724X_RESET_PCIE); -- ath79_device_reset_clear(AR724X_RESET_PCIE_PHY); -+ reset_control_deassert(apc->hc_reset); -+ reset_control_deassert(apc->phy_reset); - -- /* remove the reset of the PCIE PLL */ -- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; -- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -- -- /* deassert bypass for the PCIE PLL */ -- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; -- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -+ if (of_device_is_compatible(apc->np, "qcom,qca9550-pci")) { -+ /* remove the reset of the PCIE PLL */ -+ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG); -+ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD; -+ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl); -+ -+ /* deassert bypass for the PCIE PLL */ -+ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG); -+ ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS; -+ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl); -+ } else { -+ /* remove the reset of the PCIE PLL */ -+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET; -+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -+ -+ /* deassert bypass for the PCIE PLL */ -+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG); -+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS; -+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl); -+ } - - /* set PCIE Application Control to ready */ - app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP); -@@ -396,6 +412,14 @@ static int ar724x_pci_probe(struct platf - if (apc->irq < 0) - return -EINVAL; - -+ apc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, "hc"); -+ if (IS_ERR(apc->hc_reset)) -+ return PTR_ERR(apc->hc_reset); -+ -+ apc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, "phy"); -+ if (IS_ERR(apc->phy_reset)) -+ return PTR_ERR(apc->phy_reset); -+ - apc->np = pdev->dev.of_node; - apc->pci_controller.pci_ops = &ar724x_pci_ops; - apc->pci_controller.io_resource = &apc->io_res; -@@ -406,7 +430,7 @@ static int ar724x_pci_probe(struct platf - * Do the full PCIE Root Complex Initialization Sequence if the PCIe - * host controller is in reset. - */ -- if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE) -+ if (reset_control_status(apc->hc_reset)) - ar724x_pci_hw_init(apc); - - apc->link_up = ar724x_pci_check_link(apc); -@@ -424,6 +448,7 @@ static int ar724x_pci_probe(struct platf - - static const struct of_device_id ar724x_pci_ids[] = { - { .compatible = "qcom,ar7240-pci" }, -+ { .compatible = "qcom,qca9550-pci" }, - {}, - }; - diff --git a/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch deleted file mode 100644 index 99985eba40..0000000000 --- a/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch +++ /dev/null @@ -1,54 +0,0 @@ -From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001 -From: Abhimanyu Vishwakarma -Date: Sat, 25 Feb 2017 16:42:50 +0000 -Subject: mtd: nor: support mtd name from device tree - -Signed-off-by: Abhimanyu Vishwakarma ---- - drivers/mtd/spi-nor/spi-nor.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -3152,6 +3152,7 @@ int spi_nor_scan(struct spi_nor *nor, co - struct device *dev = nor->dev; - struct mtd_info *mtd = &nor->mtd; - struct device_node *np = spi_nor_get_flash_node(nor); -+ const char __maybe_unused *of_mtd_name = NULL; - int ret; - int i; - -@@ -3206,7 +3207,12 @@ int spi_nor_scan(struct spi_nor *nor, co - if (ret) - return ret; - -- if (!mtd->name) -+#ifdef CONFIG_MTD_OF_PARTS -+ of_property_read_string(np, "linux,mtd-name", &of_mtd_name); -+#endif -+ if (of_mtd_name) -+ mtd->name = of_mtd_name; -+ else if (!mtd->name) - mtd->name = dev_name(dev); - mtd->priv = nor; - mtd->type = MTD_NORFLASH; ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -850,6 +850,17 @@ out_error: - */ - static void mtd_set_dev_defaults(struct mtd_info *mtd) - { -+#ifdef CONFIG_MTD_OF_PARTS -+ const char __maybe_unused *of_mtd_name = NULL; -+ struct device_node *np; -+ -+ np = mtd_get_of_node(mtd); -+ if (np && !mtd->name) { -+ of_property_read_string(np, "linux,mtd-name", &of_mtd_name); -+ if (of_mtd_name) -+ mtd->name = of_mtd_name; -+ } else -+#endif - if (mtd->dev.parent) { - if (!mtd->owner && mtd->dev.parent->driver) - mtd->owner = mtd->dev.parent->driver->owner; diff --git a/target/linux/ath79/patches-5.10/402-v5.17-spi-ar934x-fix-transfer-and-word-delays.patch b/target/linux/ath79/patches-5.10/402-v5.17-spi-ar934x-fix-transfer-and-word-delays.patch deleted file mode 100644 index 7ce6df6d7b..0000000000 --- a/target/linux/ath79/patches-5.10/402-v5.17-spi-ar934x-fix-transfer-and-word-delays.patch +++ /dev/null @@ -1,27 +0,0 @@ -From c70282457c380db7deb57c81a6894debc8f88efa Mon Sep 17 00:00:00 2001 -From: Oskari Lemmela -Date: Wed, 22 Dec 2021 07:59:58 +0200 -Subject: [PATCH] spi: ar934x: fix transfer and word delays - -Add missing delay between transferred messages and words. - -Signed-off-by: Oskari Lemmela -Link: https://lore.kernel.org/r/20211222055958.1383233-3-oskari@lemmela.net -Signed-off-by: Mark Brown ---- - drivers/spi/spi-ar934x.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/spi/spi-ar934x.c -+++ b/drivers/spi/spi-ar934x.c -@@ -137,8 +137,10 @@ static int ar934x_spi_transfer_one_messa - reg >>= 8; - } - } -+ spi_delay_exec(&t->word_delay, t); - } - m->actual_length += t->len; -+ spi_transfer_delay_exec(t); - } - - msg_done: diff --git a/target/linux/ath79/patches-5.10/403-v5.17-spi-ar934x-fix-transfer-size.patch b/target/linux/ath79/patches-5.10/403-v5.17-spi-ar934x-fix-transfer-size.patch deleted file mode 100644 index 87f5da2c60..0000000000 --- a/target/linux/ath79/patches-5.10/403-v5.17-spi-ar934x-fix-transfer-size.patch +++ /dev/null @@ -1,62 +0,0 @@ -From ebe33e5a98dcf14a9630845f3f10c193584ac054 Mon Sep 17 00:00:00 2001 -From: Oskari Lemmela -Date: Wed, 22 Dec 2021 07:59:57 +0200 -Subject: [PATCH] spi: ar934x: fix transfer size - -If bits_per_word is configured, transfer only word amount -of data per iteration. - -Signed-off-by: Oskari Lemmela -Link: https://lore.kernel.org/r/20211222055958.1383233-2-oskari@lemmela.net -Signed-off-by: Mark Brown ---- - drivers/spi/spi-ar934x.c | 16 +++++++++++----- - 1 file changed, 11 insertions(+), 5 deletions(-) - ---- a/drivers/spi/spi-ar934x.c -+++ b/drivers/spi/spi-ar934x.c -@@ -82,7 +82,7 @@ static int ar934x_spi_transfer_one_messa - struct spi_device *spi = m->spi; - unsigned long trx_done, trx_cur; - int stat = 0; -- u8 term = 0; -+ u8 bpw, term = 0; - int div, i; - u32 reg; - const u8 *tx_buf; -@@ -90,6 +90,11 @@ static int ar934x_spi_transfer_one_messa - - m->actual_length = 0; - list_for_each_entry(t, &m->transfers, transfer_list) { -+ if (t->bits_per_word >= 8 && t->bits_per_word < 32) -+ bpw = t->bits_per_word >> 3; -+ else -+ bpw = 4; -+ - if (t->speed_hz) - div = ar934x_spi_clk_div(sp, t->speed_hz); - else -@@ -105,10 +110,10 @@ static int ar934x_spi_transfer_one_messa - iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL); - iowrite32(0, sp->base + AR934X_SPI_DATAOUT); - -- for (trx_done = 0; trx_done < t->len; trx_done += 4) { -+ for (trx_done = 0; trx_done < t->len; trx_done += bpw) { - trx_cur = t->len - trx_done; -- if (trx_cur > 4) -- trx_cur = 4; -+ if (trx_cur > bpw) -+ trx_cur = bpw; - else if (list_is_last(&t->transfer_list, &m->transfers)) - term = 1; - -@@ -193,7 +198,8 @@ static int ar934x_spi_probe(struct platf - ctlr->mode_bits = SPI_LSB_FIRST; - ctlr->setup = ar934x_spi_setup; - ctlr->transfer_one_message = ar934x_spi_transfer_one_message; -- ctlr->bits_per_word_mask = SPI_BPW_MASK(8); -+ ctlr->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(24) | -+ SPI_BPW_MASK(16) | SPI_BPW_MASK(8); - ctlr->dev.of_node = pdev->dev.of_node; - ctlr->num_chipselect = 3; - diff --git a/target/linux/ath79/patches-5.10/404-mtd-cybertan-trx-parser.patch b/target/linux/ath79/patches-5.10/404-mtd-cybertan-trx-parser.patch deleted file mode 100644 index 4e8e536e29..0000000000 --- a/target/linux/ath79/patches-5.10/404-mtd-cybertan-trx-parser.patch +++ /dev/null @@ -1,45 +0,0 @@ -From: Christian Lamparter -Subject: [PATCH] ath79: port cybertan_part from ar71xx - -This patch ports the cybertan_part code from ar71xx and converts the -driver to a DT-supported mtd parser. As a result, it will no longer -add the u-boot, nvram and art partitions, which were never part of -the special Cybertan header. - -Instead these partitions have to be specified in the DT, which has the -upside of making it possible to add properties (i.e.: read-only), labels -and references to these important partitions. - -Submitted-by: Christian Lamparter ---- - drivers/mtd/parsers/Makefile | 1 + - drivers/mtd/parsers/Kconfig | 8 ++++++++ - 2 files changed, 9 insertions(+) - ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o - ofpart-y += ofpart_core.o - ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908) += ofpart_bcm4908.o - ofpart-$(CONFIG_MTD_OF_PARTS_LINKSYS_NS)+= ofpart_linksys_ns.o -+obj-$(CONFIG_MTD_PARSER_CYBERTAN) += parser_cybertan.o - obj-$(CONFIG_MTD_PARSER_IMAGETAG) += parser_imagetag.o - obj-$(CONFIG_MTD_AFS_PARTS) += afs.o - obj-$(CONFIG_MTD_PARSER_TPLINK_SAFELOADER) += tplink_safeloader.o ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -102,6 +102,14 @@ config MTD_OF_PARTS_LINKSYS_NS - two "firmware" partitions. Currently used firmware has to be detected - using CFE environment variable. - -+config MTD_PARSER_CYBERTAN -+ tristate "Parser for Cybertan format partitions" -+ depends on MTD && (ATH79 || COMPILE_TEST) -+ help -+ Cybertan has a proprietory header than encompasses a Broadcom trx -+ header. This driver will parse the header and take care of the -+ special offsets that result in the extra headers. -+ - config MTD_PARSER_IMAGETAG - tristate "Parser for BCM963XX Image Tag format partitions" - depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST diff --git a/target/linux/ath79/patches-5.10/410-spi-ath79-Implement-the-spi_mem-interface.patch b/target/linux/ath79/patches-5.10/410-spi-ath79-Implement-the-spi_mem-interface.patch deleted file mode 100644 index 51a71c6ef2..0000000000 --- a/target/linux/ath79/patches-5.10/410-spi-ath79-Implement-the-spi_mem-interface.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 8d8cdb4a6ccee5b62cc0dc64651c3946364514dc Mon Sep 17 00:00:00 2001 -From: Luiz Angelo Daros de Luca -Date: Mon, 10 Feb 2020 16:11:27 -0300 -Subject: [PATCH] spi: ath79: Implement the spi_mem interface - -Signed-off-by: Luiz Angelo Daros de Luca ---- - drivers/spi/spi-ath79.c | 35 +++++++++++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -133,6 +134,39 @@ static u32 ath79_spi_txrx_mode0(struct s - return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); - } - -+static int ath79_exec_mem_op(struct spi_mem *mem, -+ const struct spi_mem_op *op) -+{ -+ struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi); -+ -+ /* Ensures that reading is performed on device connected -+ to hardware cs0 */ -+ if (mem->spi->chip_select || mem->spi->cs_gpiod) -+ return -ENOTSUPP; -+ -+ /* Only use for fast-read op. */ -+ if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN || -+ op->addr.nbytes != 3 || op->dummy.nbytes != 1) -+ return -ENOTSUPP; -+ -+ /* disable GPIO mode */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); -+ -+ memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes); -+ -+ /* enable GPIO mode */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); -+ -+ /* restore IOC register */ -+ ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); -+ -+ return 0; -+} -+ -+static const struct spi_controller_mem_ops ath79_mem_ops = { -+ .exec_op = ath79_exec_mem_op, -+}; -+ - static int ath79_spi_probe(struct platform_device *pdev) - { - struct spi_master *master; -@@ -164,6 +198,7 @@ static int ath79_spi_probe(struct platfo - ret = PTR_ERR(sp->base); - goto err_put_master; - } -+ master->mem_ops = &ath79_mem_ops; - - sp->clk = devm_clk_get(&pdev->dev, "ahb"); - if (IS_ERR(sp->clk)) { diff --git a/target/linux/ath79/patches-5.10/412-spi-ath79-set-number-of-chipselect-lines.patch b/target/linux/ath79/patches-5.10/412-spi-ath79-set-number-of-chipselect-lines.patch deleted file mode 100644 index 614bcbcded..0000000000 --- a/target/linux/ath79/patches-5.10/412-spi-ath79-set-number-of-chipselect-lines.patch +++ /dev/null @@ -1,26 +0,0 @@ -From e2e9f6d9f9bd7449ff113c157b639ce1a24b9d3f Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sat, 24 Apr 2021 16:14:48 +0200 -Subject: [PATCH 2/2] spi: ath79: set number of chipselect lines - -All chipsets from AR7100 up to QCA9563 have three dedicated chipselect -lines for the integrated SPI controller. Remove the number of -chipselects from the platform data, as there is no need to manually set -this to a different value. - -Signed-off-by: David Bauer ---- - drivers/spi/spi-ath79.c | 2 +- - include/linux/platform_data/spi-ath79.h | 1 - - 2 files changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/spi/spi-ath79.c -+++ b/drivers/spi/spi-ath79.c -@@ -187,6 +187,7 @@ static int ath79_spi_probe(struct platfo - master->use_gpio_descriptors = true; - master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); - master->flags = SPI_MASTER_GPIO_SS; -+ master->num_chipselect = 3; - - sp->bitbang.master = master; - sp->bitbang.chipselect = ath79_spi_chipselect; diff --git a/target/linux/ath79/patches-5.10/420-net-use-downstream-ag71xx.patch b/target/linux/ath79/patches-5.10/420-net-use-downstream-ag71xx.patch deleted file mode 100644 index 65867c1cd5..0000000000 --- a/target/linux/ath79/patches-5.10/420-net-use-downstream-ag71xx.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: John Crispin -Subject: [PATCH] ath79: add new OF only target for QCA MIPS silicon - -This target aims to replace ar71xx mid-term. The big part that is still -missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik -subtargets will follow. - -Submitted-by: John Crispin ---- - drivers/net/ethernet/atheros/Kconfig | 8 +------- - drivers/net/ethernet/atheros/Makefile | 2 +- - 2 files changed, 2 insertions(+), 8 deletions(-) - ---- a/drivers/net/ethernet/atheros/Kconfig -+++ b/drivers/net/ethernet/atheros/Kconfig -@@ -17,13 +17,7 @@ config NET_VENDOR_ATHEROS - - if NET_VENDOR_ATHEROS - --config AG71XX -- tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support" -- depends on ATH79 -- select PHYLINK -- help -- If you wish to compile a kernel for AR7XXX/91XXX and enable -- ethernet support, then you should always answer Y to this. -+source "drivers/net/ethernet/atheros/ag71xx/Kconfig" - - config ATL2 - tristate "Atheros L2 Fast Ethernet support" ---- a/drivers/net/ethernet/atheros/Makefile -+++ b/drivers/net/ethernet/atheros/Makefile -@@ -3,7 +3,7 @@ - # Makefile for the Atheros network device drivers. - # - --obj-$(CONFIG_AG71XX) += ag71xx.o -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_ATL1) += atlx/ - obj-$(CONFIG_ATL2) += atlx/ - obj-$(CONFIG_ATL1E) += atl1e/ diff --git a/target/linux/ath79/patches-5.10/425-at803x-allow-sgmii-aneg-override.patch b/target/linux/ath79/patches-5.10/425-at803x-allow-sgmii-aneg-override.patch deleted file mode 100644 index ef1e5a6b4a..0000000000 --- a/target/linux/ath79/patches-5.10/425-at803x-allow-sgmii-aneg-override.patch +++ /dev/null @@ -1,32 +0,0 @@ -From: David Bauer -Subject: [PATCH] ath79: allow to override AR8033 SGMII aneg status - -In order to make the QCA955x SGMII workaround work, the unsuccessful -SGMII autonegotiation on the AR8033 should not block the PHY -state-machine. - -Otherwise, the ag71xx driver never becomes aware of the copper-side -link-establishment and the workaround is never executed. - -Submitted-by: David Bauer -Submitted-by: Adrian Schmutzler ---- - drivers/net/phy/at803x.c-override.patch | 7 +++++++ - 1 files changed, 7 insertions(+) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -959,6 +959,13 @@ static int at803x_aneg_done(struct phy_d - if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) { - phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n"); - aneg_done = 0; -+#ifdef CONFIG_OF_MDIO -+ if (phydev->mdio.dev.of_node && -+ of_property_read_bool(phydev->mdio.dev.of_node, -+ "at803x-override-sgmii-link-check")) { -+ aneg_done = 1; -+ } -+#endif - } - /* switch back to copper page */ - phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL); diff --git a/target/linux/ath79/patches-5.10/430-drivers-link-spi-before-mtd.patch b/target/linux/ath79/patches-5.10/430-drivers-link-spi-before-mtd.patch deleted file mode 100644 index cba537408a..0000000000 --- a/target/linux/ath79/patches-5.10/430-drivers-link-spi-before-mtd.patch +++ /dev/null @@ -1,20 +0,0 @@ -From: Gabor Juhos -Subject: [PATCH] ar71xx: Link SPI before MTD - -SVN-Revision: 22863 ---- - drivers/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/Makefile -+++ b/drivers/Makefile -@@ -81,8 +81,8 @@ obj-y += scsi/ - obj-y += nvme/ - obj-$(CONFIG_ATA) += ata/ - obj-$(CONFIG_TARGET_CORE) += target/ --obj-$(CONFIG_MTD) += mtd/ - obj-$(CONFIG_SPI) += spi/ -+obj-$(CONFIG_MTD) += mtd/ - obj-$(CONFIG_SPMI) += spmi/ - obj-$(CONFIG_HSI) += hsi/ - obj-$(CONFIG_SLIMBUS) += slimbus/ diff --git a/target/linux/ath79/patches-5.10/440-mtd-ar934x-nand-driver.patch b/target/linux/ath79/patches-5.10/440-mtd-ar934x-nand-driver.patch deleted file mode 100644 index 366cf5118e..0000000000 --- a/target/linux/ath79/patches-5.10/440-mtd-ar934x-nand-driver.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: Gabor Juhos -Subject: ar71xx: ar934x_nfc: experimental NAND Flash Controller driver for AR934x - -SVN-Revision: 33385 ---- - drivers/mtd/nand/raw/Kconfig | 8 ++++++++ - drivers/mtd/nand/raw/Makefile | 1 + - 2 files changed, 9 insertions(+) - ---- a/drivers/mtd/nand/raw/Kconfig -+++ b/drivers/mtd/nand/raw/Kconfig -@@ -556,4 +556,12 @@ config MTD_NAND_DISKONCHIP_BBTWRITE - load time (assuming you build diskonchip as a module) with the module - parameter "inftl_bbt_write=1". - -+config MTD_NAND_AR934X -+ tristate "Support for NAND controller on Qualcomm Atheros AR934x/QCA955x SoCs" -+ depends on ATH79 || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ Enables support for NAND controller on Qualcomm Atheros SoCs. -+ This controller is found on AR934x and QCA955x SoCs. -+ - endif # MTD_RAW_NAND ---- a/drivers/mtd/nand/raw/Makefile -+++ b/drivers/mtd/nand/raw/Makefile -@@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm - obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o - obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o - obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o -+obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o - - nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o - nand-objs += nand_onfi.o diff --git a/target/linux/ath79/patches-5.10/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch b/target/linux/ath79/patches-5.10/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch deleted file mode 100644 index 3b8fee2269..0000000000 --- a/target/linux/ath79/patches-5.10/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch +++ /dev/null @@ -1,109 +0,0 @@ -From: Gabor Juhos -Subject: [PATCH] ar71xx: swizzle address for PCI byte/word access on AR71xx - -Closes #11683. - -SVN-Revision: 32639 ---- - .../mips/include/asm/mach-ath79/mangle-port.h | 111 ++++++++++++++++++ - 1 file changed, 111 insertions(+) - create mode 100644 arch/mips/include/asm/mach-ath79/mangle-port.h - ---- /dev/null -+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h -@@ -0,0 +1,37 @@ -+/* -+ * Copyright (C) 2012 Gabor Juhos -+ * -+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H -+#define __ASM_MACH_ATH79_MANGLE_PORT_H -+ -+#ifdef CONFIG_PCI_AR71XX -+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port); -+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port); -+#else -+#define ath79_pci_swizzle_b(port) (port) -+#define ath79_pci_swizzle_w(port) (port) -+#endif -+ -+#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port) -+#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port) -+#define __swizzle_addr_l(port) (port) -+#define __swizzle_addr_q(port) (port) -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) (x) -+# define __mem_ioswabw(a, x) cpu_to_le16(x) -+# define ioswabl(a, x) (x) -+# define __mem_ioswabl(a, x) cpu_to_le32(x) -+# define ioswabq(a, x) (x) -+# define __mem_ioswabq(a, x) cpu_to_le64(x) -+ -+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */ ---- a/arch/mips/pci/pci-ar71xx.c -+++ b/arch/mips/pci/pci-ar71xx.c -@@ -68,6 +68,45 @@ static const u32 ar71xx_pci_read_mask[8] - 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 - }; - -+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port); -+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port); -+ -+static inline bool ar71xx_is_pci_addr(unsigned long port) -+{ -+ unsigned long phys = CPHYSADDR(port); -+ -+ return (phys >= AR71XX_PCI_MEM_BASE && -+ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE); -+} -+ -+static unsigned long ar71xx_pci_swizzle_b(unsigned long port) -+{ -+ return ar71xx_is_pci_addr(port) ? port ^ 3 : port; -+} -+ -+static unsigned long ar71xx_pci_swizzle_w(unsigned long port) -+{ -+ return ar71xx_is_pci_addr(port) ? port ^ 2 : port; -+} -+ -+unsigned long ath79_pci_swizzle_b(unsigned long port) -+{ -+ if (__ath79_pci_swizzle_b) -+ return __ath79_pci_swizzle_b(port); -+ -+ return port; -+} -+EXPORT_SYMBOL(ath79_pci_swizzle_b); -+ -+unsigned long ath79_pci_swizzle_w(unsigned long port) -+{ -+ if (__ath79_pci_swizzle_w) -+ return __ath79_pci_swizzle_w(port); -+ -+ return port; -+} -+EXPORT_SYMBOL(ath79_pci_swizzle_w); -+ - static inline u32 ar71xx_pci_get_ble(int where, int size, int local) - { - u32 t; -@@ -276,6 +315,9 @@ static int ar71xx_pci_probe(struct platf - - register_pci_controller(&apc->pci_ctrl); - -+ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b; -+ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w; -+ - return 0; - } - diff --git a/target/linux/ath79/patches-5.10/900-mdio_bitbang_ignore_ta_value.patch b/target/linux/ath79/patches-5.10/900-mdio_bitbang_ignore_ta_value.patch deleted file mode 100644 index d35b53638a..0000000000 --- a/target/linux/ath79/patches-5.10/900-mdio_bitbang_ignore_ta_value.patch +++ /dev/null @@ -1,44 +0,0 @@ -From: Jonas Gorski -Subject: ar71xx: add a workaround for ar8316 not always driving the TA bit to low - -AR8316 behind a GPIO bitbanged MDIO bus fails to drive the turnaround bit -to low despite returning a valid value. Ignore it and just use the -returned value anyway. - -SVN-Revision: 28422 ---- - drivers/net/mdio/mdio-bitbang.c | 16 ++----------------- - 1 file changed, 2 insertions(+), 14 deletions(-) - ---- a/drivers/net/mdio/mdio-bitbang.c -+++ b/drivers/net/mdio/mdio-bitbang.c -@@ -152,7 +152,7 @@ static int mdiobb_cmd_addr(struct mdiobb - static int mdiobb_read(struct mii_bus *bus, int phy, int reg) - { - struct mdiobb_ctrl *ctrl = bus->priv; -- int ret, i; -+ int ret; - - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); -@@ -162,19 +162,7 @@ static int mdiobb_read(struct mii_bus *b - - ctrl->ops->set_mdio_dir(ctrl, 0); - -- /* check the turnaround bit: the PHY should be driving it to zero, if this -- * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that -- */ -- if (mdiobb_get_bit(ctrl) != 0 && -- !(bus->phy_ignore_ta_mask & (1 << phy))) { -- /* PHY didn't drive TA low -- flush any bits it -- * may be trying to send. -- */ -- for (i = 0; i < 32; i++) -- mdiobb_get_bit(ctrl); -- -- return 0xffff; -- } -+ mdiobb_get_bit(ctrl); - - ret = mdiobb_get_num(ctrl, 16); - mdiobb_get_bit(ctrl); diff --git a/target/linux/ath79/patches-5.10/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch b/target/linux/ath79/patches-5.10/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch deleted file mode 100644 index e6fae3349d..0000000000 --- a/target/linux/ath79/patches-5.10/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001 -From: Jonas Gorski -Date: Tue, 16 Jun 2015 13:15:08 +0200 -Subject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command - -It seems some phys have some maximum timings for accessing the MDIO line, -resulting in bit errors under cpu stress. Prevent this from happening by -disabling interrupts when sending commands. - -Signed-off-by: Jonas Gorski ---- - drivers/net/mdio/mdio-bitbang.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/net/mdio/mdio-bitbang.c -+++ b/drivers/net/mdio/mdio-bitbang.c -@@ -15,6 +15,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -153,7 +154,9 @@ static int mdiobb_read(struct mii_bus *b - { - struct mdiobb_ctrl *ctrl = bus->priv; - int ret; -+ unsigned long flags; - -+ local_irq_save(flags); - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); -@@ -166,13 +169,17 @@ static int mdiobb_read(struct mii_bus *b - - ret = mdiobb_get_num(ctrl, 16); - mdiobb_get_bit(ctrl); -+ local_irq_restore(flags); -+ - return ret; - } - - static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) - { - struct mdiobb_ctrl *ctrl = bus->priv; -+ unsigned long flags; - -+ local_irq_save(flags); - if (reg & MII_ADDR_C45) { - reg = mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); -@@ -187,6 +194,8 @@ static int mdiobb_write(struct mii_bus * - - ctrl->ops->set_mdio_dir(ctrl, 0); - mdiobb_get_bit(ctrl); -+ local_irq_restore(flags); -+ - return 0; - } - diff --git a/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch deleted file mode 100644 index 2ec0c2b9ac..0000000000 --- a/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch +++ /dev/null @@ -1,903 +0,0 @@ -From: Felix Fietkau -Subject: [PATCH] ar71xx: fix unaligned access in a few more places - -SVN-Revision: 35130 ---- - arch/mips/include/asm/checksum.h | 83 +++--------------- - include/uapi/linux/ip.h | 2 +- - include/uapi/linux/ipv6.h | 2 +- - include/uapi/linux/tcp.h | 4 ++-- - include/uapi/linux/udp.h | 2 +- - net/netfilter/nf_conntrack_core.c | 4 ++-- - include/uapi/linux/icmp.h | 2 +- - include/uapi/linux/in6.h | 2 +- - net/ipv6/tcp_ipv6.c | 9 +++-- - net/ipv6/datagram.c | 6 ++-- - net/ipv6/exthdrs.c | 2 +- - include/linux/types.h | 5 +++ - net/ipv4/af_inet.c | 4 ++-- - net/ipv4/tcp_output.c | 69 +++++++++-------- - include/uapi/linux/igmp.h | 8 +++--- - net/core/flow_dissector.c | 2 +- - include/uapi/linux/icmpv6.h | 2 +- - include/net/ndisc.h | 10 ++++---- - net/sched/cls_u32.c | 6 +++--- - net/ipv6/ip6_offload.c | 2 +- - include/net/addrconf.h | 2 +- - include/net/inet_ecn.h | 4 ++-- - include/net/ipv6.h | 23 +++++---- - include/net/secure_seq.h | 1 + - include/uapi/linux/in.h | 2 +- - net/ipv6/ip6_fib.h | 2 +- - net/netfilter/nf_conntrack_proto_tcp.c | 2 +- - net/xfrm/xfrm_input.c | 4 ++-- - net/ipv4/tcp_input.c | 12 ++++--- - include/uapi/linux/if_pppox.h | 1 + - net/ipv6/netfilter/nf_log_ipv6.c | 4 ++-- - include/net/neighbour.h | 6 +++-- - include/uapi/linux/netfilter_arp/arp_tables.h | 2 +- - net/core/utils.c | 10 +++++-- - include/linux/etherdevice.h | 11 ++++--- - net/ipv4/tcp_offload.c | 6 +++--- - net/ipv6/netfilter/ip6table_mangle.c | 4 ++-- - 37 file changed, 171 insertions(+), 141 deletions(-) - ---- a/arch/mips/include/asm/checksum.h -+++ b/arch/mips/include/asm/checksum.h -@@ -100,26 +100,30 @@ static inline __sum16 ip_fast_csum(const - const unsigned int *stop = word + ihl; - unsigned int csum; - int carry; -+ unsigned int w; - -- csum = word[0]; -- csum += word[1]; -- carry = (csum < word[1]); -+ csum = net_hdr_word(word++); -+ -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- csum += word[2]; -- carry = (csum < word[2]); -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- csum += word[3]; -- carry = (csum < word[3]); -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- word += 4; - do { -- csum += *word; -- carry = (csum < *word); -+ w = net_hdr_word(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; -- word++; - } while (word != stop); - - return csum_fold(csum); -@@ -180,73 +184,6 @@ static inline __sum16 ip_compute_csum(co - return csum_fold(csum_partial(buff, len, 0)); - } - --#define _HAVE_ARCH_IPV6_CSUM --static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, -- const struct in6_addr *daddr, -- __u32 len, __u8 proto, -- __wsum sum) --{ -- __wsum tmp; -- -- __asm__( -- " .set push # csum_ipv6_magic\n" -- " .set noreorder \n" -- " .set noat \n" -- " addu %0, %5 # proto (long in network byte order)\n" -- " sltu $1, %0, %5 \n" -- " addu %0, $1 \n" -- -- " addu %0, %6 # csum\n" -- " sltu $1, %0, %6 \n" -- " lw %1, 0(%2) # four words source address\n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 4(%2) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 8(%2) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 12(%2) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 0(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 4(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 8(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " lw %1, 12(%3) \n" -- " addu %0, $1 \n" -- " addu %0, %1 \n" -- " sltu $1, %0, %1 \n" -- -- " addu %0, $1 # Add final carry\n" -- " .set pop" -- : "=&r" (sum), "=&r" (tmp) -- : "r" (saddr), "r" (daddr), -- "0" (htonl(len)), "r" (htonl(proto)), "r" (sum)); -- -- return csum_fold(sum); --} -- - #include - #endif /* CONFIG_GENERIC_CSUM */ - ---- a/include/uapi/linux/ip.h -+++ b/include/uapi/linux/ip.h -@@ -106,7 +106,7 @@ struct iphdr { - __be32 daddr; - ); - /*The options start here. */ --}; -+} __attribute__((packed, aligned(2))); - - - struct ip_auth_hdr { ---- a/include/uapi/linux/ipv6.h -+++ b/include/uapi/linux/ipv6.h -@@ -135,7 +135,7 @@ struct ipv6hdr { - struct in6_addr saddr; - struct in6_addr daddr; - ); --}; -+} __attribute__((packed, aligned(2))); - - - /* index values for the variables in ipv6_devconf */ ---- a/include/uapi/linux/tcp.h -+++ b/include/uapi/linux/tcp.h -@@ -55,7 +55,7 @@ struct tcphdr { - __be16 window; - __sum16 check; - __be16 urg_ptr; --}; -+} __attribute__((packed, aligned(2))); - - /* - * The union cast uses a gcc extension to avoid aliasing problems -@@ -65,7 +65,7 @@ struct tcphdr { - union tcp_word_hdr { - struct tcphdr hdr; - __be32 words[5]; --}; -+} __attribute__((packed, aligned(2))); - - #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) - ---- a/include/uapi/linux/udp.h -+++ b/include/uapi/linux/udp.h -@@ -25,7 +25,7 @@ struct udphdr { - __be16 dest; - __be16 len; - __sum16 check; --}; -+} __attribute__((packed, aligned(2))); - - /* UDP socket options */ - #define UDP_CORK 1 /* Never send partially complete segments */ ---- a/net/netfilter/nf_conntrack_core.c -+++ b/net/netfilter/nf_conntrack_core.c -@@ -271,8 +271,8 @@ nf_ct_get_tuple(const struct sk_buff *sk - - switch (l3num) { - case NFPROTO_IPV4: -- tuple->src.u3.ip = ap[0]; -- tuple->dst.u3.ip = ap[1]; -+ tuple->src.u3.ip = net_hdr_word(ap++); -+ tuple->dst.u3.ip = net_hdr_word(ap); - break; - case NFPROTO_IPV6: - memcpy(tuple->src.u3.ip6, ap, sizeof(tuple->src.u3.ip6)); ---- a/include/uapi/linux/icmp.h -+++ b/include/uapi/linux/icmp.h -@@ -83,7 +83,7 @@ struct icmphdr { - } frag; - __u8 reserved[4]; - } un; --}; -+} __attribute__((packed, aligned(2))); - - - /* ---- a/include/uapi/linux/in6.h -+++ b/include/uapi/linux/in6.h -@@ -43,7 +43,7 @@ struct in6_addr { - #define s6_addr16 in6_u.u6_addr16 - #define s6_addr32 in6_u.u6_addr32 - #endif --}; -+} __attribute__((packed, aligned(2))); - #endif /* __UAPI_DEF_IN6_ADDR */ - - #if __UAPI_DEF_SOCKADDR_IN6 ---- a/net/ipv6/tcp_ipv6.c -+++ b/net/ipv6/tcp_ipv6.c -@@ -35,6 +35,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -927,10 +928,10 @@ static void tcp_v6_send_response(const s - topt = (__be32 *)(t1 + 1); - - if (tsecr) { -- *topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -- (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP); -- *topt++ = htonl(tsval); -- *topt++ = htonl(tsecr); -+ put_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -+ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++); -+ put_unaligned_be32(tsval, topt++); -+ put_unaligned_be32(tsecr, topt++); - } - - #ifdef CONFIG_TCP_MD5SIG ---- a/net/ipv6/datagram.c -+++ b/net/ipv6/datagram.c -@@ -492,7 +492,7 @@ int ipv6_recv_error(struct sock *sk, str - ipv6_iface_scope_id(&sin->sin6_addr, - IP6CB(skb)->iif); - } else { -- ipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset), -+ ipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset), - &sin->sin6_addr); - sin->sin6_scope_id = 0; - } -@@ -846,12 +846,12 @@ int ip6_datagram_send_ctl(struct net *ne - } - - if (fl6->flowlabel&IPV6_FLOWINFO_MASK) { -- if ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) { -+ if ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) { - err = -EINVAL; - goto exit_f; - } - } -- fl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg); -+ fl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg)); - break; - - case IPV6_2292HOPOPTS: ---- a/net/ipv6/exthdrs.c -+++ b/net/ipv6/exthdrs.c -@@ -948,7 +948,7 @@ static bool ipv6_hop_jumbo(struct sk_buf - goto drop; - } - -- pkt_len = ntohl(*(__be32 *)(nh + optoff + 2)); -+ pkt_len = ntohl(net_hdr_word(nh + optoff + 2)); - if (pkt_len <= IPV6_MAXPLEN) { - __IP6_INC_STATS(net, idev, IPSTATS_MIB_INHDRERRORS); - icmpv6_param_prob(skb, ICMPV6_HDR_FIELD, optoff+2); ---- a/include/linux/types.h -+++ b/include/linux/types.h -@@ -227,5 +227,11 @@ typedef void (*swap_func_t)(void *a, voi - typedef int (*cmp_r_func_t)(const void *a, const void *b, const void *priv); - typedef int (*cmp_func_t)(const void *a, const void *b); - -+struct net_hdr_word { -+ u32 words[1]; -+} __attribute__((packed, aligned(2))); -+ -+#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0]) -+ - #endif /* __ASSEMBLY__ */ - #endif /* _LINUX_TYPES_H */ ---- a/net/ipv4/af_inet.c -+++ b/net/ipv4/af_inet.c -@@ -1469,8 +1469,8 @@ struct sk_buff *inet_gro_receive(struct - if (unlikely(ip_fast_csum((u8 *)iph, 5))) - goto out_unlock; - -- id = ntohl(*(__be32 *)&iph->id); -- flush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF)); -+ id = ntohl(net_hdr_word(&iph->id)); -+ flush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF)); - id >>= 16; - - list_for_each_entry(p, head, list) { ---- a/net/ipv4/tcp_output.c -+++ b/net/ipv4/tcp_output.c -@@ -609,48 +609,53 @@ static void tcp_options_write(__be32 *pt - u16 options = opts->options; /* mungable copy */ - - if (unlikely(OPTION_MD5 & options)) { -- *ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -- (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -+ (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG); - /* overload cookie hash location */ - opts->hash_location = (__u8 *)ptr; - ptr += 4; - } - - if (unlikely(opts->mss)) { -- *ptr++ = htonl((TCPOPT_MSS << 24) | -- (TCPOLEN_MSS << 16) | -- opts->mss); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) | -+ opts->mss); - } - - if (likely(OPTION_TS & options)) { - if (unlikely(OPTION_SACK_ADVERTISE & options)) { -- *ptr++ = htonl((TCPOPT_SACK_PERM << 24) | -- (TCPOLEN_SACK_PERM << 16) | -- (TCPOPT_TIMESTAMP << 8) | -- TCPOLEN_TIMESTAMP); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_SACK_PERM << 24) | -+ (TCPOLEN_SACK_PERM << 16) | -+ (TCPOPT_TIMESTAMP << 8) | -+ TCPOLEN_TIMESTAMP); - options &= ~OPTION_SACK_ADVERTISE; - } else { -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_NOP << 16) | -- (TCPOPT_TIMESTAMP << 8) | -- TCPOLEN_TIMESTAMP); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_NOP << 16) | -+ (TCPOPT_TIMESTAMP << 8) | -+ TCPOLEN_TIMESTAMP); - } -- *ptr++ = htonl(opts->tsval); -- *ptr++ = htonl(opts->tsecr); -+ net_hdr_word(ptr++) = htonl(opts->tsval); -+ net_hdr_word(ptr++) = htonl(opts->tsecr); - } - - if (unlikely(OPTION_SACK_ADVERTISE & options)) { -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_NOP << 16) | -- (TCPOPT_SACK_PERM << 8) | -- TCPOLEN_SACK_PERM); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_NOP << 16) | -+ (TCPOPT_SACK_PERM << 8) | -+ TCPOLEN_SACK_PERM); - } - - if (unlikely(OPTION_WSCALE & options)) { -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_WINDOW << 16) | -- (TCPOLEN_WINDOW << 8) | -- opts->ws); -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_WINDOW << 16) | -+ (TCPOLEN_WINDOW << 8) | -+ opts->ws); - } - - if (unlikely(opts->num_sack_blocks)) { -@@ -658,16 +663,17 @@ static void tcp_options_write(__be32 *pt - tp->duplicate_sack : tp->selective_acks; - int this_sack; - -- *ptr++ = htonl((TCPOPT_NOP << 24) | -- (TCPOPT_NOP << 16) | -- (TCPOPT_SACK << 8) | -- (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * -+ net_hdr_word(ptr++) = -+ htonl((TCPOPT_NOP << 24) | -+ (TCPOPT_NOP << 16) | -+ (TCPOPT_SACK << 8) | -+ (TCPOLEN_SACK_BASE + (opts->num_sack_blocks * - TCPOLEN_SACK_PERBLOCK))); - - for (this_sack = 0; this_sack < opts->num_sack_blocks; - ++this_sack) { -- *ptr++ = htonl(sp[this_sack].start_seq); -- *ptr++ = htonl(sp[this_sack].end_seq); -+ net_hdr_word(ptr++) = htonl(sp[this_sack].start_seq); -+ net_hdr_word(ptr++) = htonl(sp[this_sack].end_seq); - } - - tp->rx_opt.dsack = 0; -@@ -680,13 +686,14 @@ static void tcp_options_write(__be32 *pt - - if (foc->exp) { - len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len; -- *ptr = htonl((TCPOPT_EXP << 24) | (len << 16) | -+ net_hdr_word(ptr) = -+ htonl((TCPOPT_EXP << 24) | (len << 16) | - TCPOPT_FASTOPEN_MAGIC); - p += TCPOLEN_EXP_FASTOPEN_BASE; - } else { - len = TCPOLEN_FASTOPEN_BASE + foc->len; -- *p++ = TCPOPT_FASTOPEN; -- *p++ = len; -+ net_hdr_word(p++) = TCPOPT_FASTOPEN; -+ net_hdr_word(p++) = len; - } - - memcpy(p, foc->val, foc->len); ---- a/include/uapi/linux/igmp.h -+++ b/include/uapi/linux/igmp.h -@@ -33,7 +33,7 @@ struct igmphdr { - __u8 code; /* For newer IGMP */ - __sum16 csum; - __be32 group; --}; -+} __attribute__((packed, aligned(2))); - - /* V3 group record types [grec_type] */ - #define IGMPV3_MODE_IS_INCLUDE 1 -@@ -49,7 +49,7 @@ struct igmpv3_grec { - __be16 grec_nsrcs; - __be32 grec_mca; - __be32 grec_src[0]; --}; -+} __attribute__((packed, aligned(2))); - - struct igmpv3_report { - __u8 type; -@@ -58,7 +58,7 @@ struct igmpv3_report { - __be16 resv2; - __be16 ngrec; - struct igmpv3_grec grec[0]; --}; -+} __attribute__((packed, aligned(2))); - - struct igmpv3_query { - __u8 type; -@@ -79,7 +79,7 @@ struct igmpv3_query { - __u8 qqic; - __be16 nsrcs; - __be32 srcs[0]; --}; -+} __attribute__((packed, aligned(2))); - - #define IGMP_HOST_MEMBERSHIP_QUERY 0x11 /* From RFC1112 */ - #define IGMP_HOST_MEMBERSHIP_REPORT 0x12 /* Ditto */ ---- a/net/core/flow_dissector.c -+++ b/net/core/flow_dissector.c -@@ -128,7 +128,7 @@ __be32 __skb_flow_get_ports(const struct - ports = __skb_header_pointer(skb, thoff + poff, - sizeof(_ports), data, hlen, &_ports); - if (ports) -- return *ports; -+ return (__be32)net_hdr_word(ports); - } - - return 0; ---- a/include/uapi/linux/icmpv6.h -+++ b/include/uapi/linux/icmpv6.h -@@ -78,7 +78,7 @@ struct icmp6hdr { - #define icmp6_addrconf_other icmp6_dataun.u_nd_ra.other - #define icmp6_rt_lifetime icmp6_dataun.u_nd_ra.rt_lifetime - #define icmp6_router_pref icmp6_dataun.u_nd_ra.router_pref --}; -+} __attribute__((packed, aligned(2))); - - - #define ICMPV6_ROUTER_PREF_LOW 0x3 ---- a/include/net/ndisc.h -+++ b/include/net/ndisc.h -@@ -93,7 +93,7 @@ struct ra_msg { - struct icmp6hdr icmph; - __be32 reachable_time; - __be32 retrans_timer; --}; -+} __attribute__((packed, aligned(2))); - - struct rd_msg { - struct icmp6hdr icmph; -@@ -372,10 +372,10 @@ static inline u32 ndisc_hashfn(const voi - { - const u32 *p32 = pkey; - -- return (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) + -- (p32[1] * hash_rnd[1]) + -- (p32[2] * hash_rnd[2]) + -- (p32[3] * hash_rnd[3])); -+ return (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) + -+ (net_hdr_word(&p32[1]) * hash_rnd[1]) + -+ (net_hdr_word(&p32[2]) * hash_rnd[2]) + -+ (net_hdr_word(&p32[3]) * hash_rnd[3])); - } - - static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey) ---- a/net/sched/cls_u32.c -+++ b/net/sched/cls_u32.c -@@ -155,7 +155,7 @@ next_knode: - data = skb_header_pointer(skb, toff, 4, &hdata); - if (!data) - goto out; -- if ((*data ^ key->val) & key->mask) { -+ if ((net_hdr_word(data) ^ key->val) & key->mask) { - n = rcu_dereference_bh(n->next); - goto next_knode; - } -@@ -206,8 +206,8 @@ check_terminal: - &hdata); - if (!data) - goto out; -- sel = ht->divisor & u32_hash_fold(*data, &n->sel, -- n->fshift); -+ sel = ht->divisor & u32_hash_fold(net_hdr_word(data), -+ &n->sel, n->fshift); - } - if (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT))) - goto next_ht; ---- a/net/ipv6/ip6_offload.c -+++ b/net/ipv6/ip6_offload.c -@@ -240,7 +240,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff * - continue; - - iph2 = (struct ipv6hdr *)(p->data + off); -- first_word = *(__be32 *)iph ^ *(__be32 *)iph2; -+ first_word = net_hdr_word(iph) ^ net_hdr_word(iph2); - - /* All fields must match except length and Traffic Class. - * XXX skbs on the gro_list have all been parsed and pulled ---- a/include/net/addrconf.h -+++ b/include/net/addrconf.h -@@ -47,7 +47,7 @@ struct prefix_info { - __be32 reserved2; - - struct in6_addr prefix; --}; -+} __attribute__((packed, aligned(2))); - - #include - #include ---- a/include/net/inet_ecn.h -+++ b/include/net/inet_ecn.h -@@ -140,9 +140,9 @@ static inline int IP6_ECN_set_ce(struct - if (INET_ECN_is_not_ect(ipv6_get_dsfield(iph))) - return 0; - -- from = *(__be32 *)iph; -+ from = net_hdr_word(iph); - to = from | htonl(INET_ECN_CE << 20); -- *(__be32 *)iph = to; -+ net_hdr_word(iph) = to; - if (skb->ip_summed == CHECKSUM_COMPLETE) - skb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from), - (__force __wsum)to); ---- a/include/net/ipv6.h -+++ b/include/net/ipv6.h -@@ -146,7 +146,7 @@ struct frag_hdr { - __u8 reserved; - __be16 frag_off; - __be32 identification; --}; -+} __attribute__((packed, aligned(2))); - - #define IP6_MF 0x0001 - #define IP6_OFFSET 0xFFF8 -@@ -560,8 +560,8 @@ static inline void __ipv6_addr_set_half( - } - #endif - #endif -- addr[0] = wh; -- addr[1] = wl; -+ net_hdr_word(&addr[0]) = wh; -+ net_hdr_word(&addr[1]) = wl; - } - - static inline void ipv6_addr_set(struct in6_addr *addr, -@@ -620,6 +620,8 @@ static inline bool ipv6_prefix_equal(con - const __be32 *a1 = addr1->s6_addr32; - const __be32 *a2 = addr2->s6_addr32; - unsigned int pdw, pbi; -+ /* Used for last <32-bit fraction of prefix */ -+ u32 pbia1, pbia2; - - /* check complete u32 in prefix */ - pdw = prefixlen >> 5; -@@ -628,7 +630,9 @@ static inline bool ipv6_prefix_equal(con - - /* check incomplete u32 in prefix */ - pbi = prefixlen & 0x1f; -- if (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi)))) -+ pbia1 = net_hdr_word(&a1[pdw]); -+ pbia2 = net_hdr_word(&a2[pdw]); -+ if (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi)))) - return false; - - return true; -@@ -749,13 +753,13 @@ static inline void ipv6_addr_set_v4mappe - */ - static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen) - { -- const __be32 *a1 = token1, *a2 = token2; -+ const struct in6_addr *a1 = token1, *a2 = token2; - int i; - - addrlen >>= 2; - - for (i = 0; i < addrlen; i++) { -- __be32 xb = a1[i] ^ a2[i]; -+ __be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i]; - if (xb) - return i * 32 + 31 - __fls(ntohl(xb)); - } -@@ -941,17 +945,18 @@ static inline int ip6_multipath_hash_pol - static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass, - __be32 flowlabel) - { -- *(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel; -+ net_hdr_word((__be32 *)hdr) = -+ htonl(0x60000000 | (tclass << 20)) | flowlabel; - } - - static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr) - { -- return *(__be32 *)hdr & IPV6_FLOWINFO_MASK; -+ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK; - } - - static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr) - { -- return *(__be32 *)hdr & IPV6_FLOWLABEL_MASK; -+ return net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK; - } - - static inline u8 ip6_tclass(__be32 flowinfo) ---- a/include/net/secure_seq.h -+++ b/include/net/secure_seq.h -@@ -3,6 +3,7 @@ - #define _NET_SECURE_SEQ - - #include -+#include - - u64 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport); - u64 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, ---- a/include/uapi/linux/in.h -+++ b/include/uapi/linux/in.h -@@ -88,7 +88,7 @@ enum { - /* Internet address. */ - struct in_addr { - __be32 s_addr; --}; -+} __attribute__((packed, aligned(2))); - #endif - - #define IP_TOS 1 ---- a/net/ipv6/ip6_fib.c -+++ b/net/ipv6/ip6_fib.c -@@ -140,7 +140,7 @@ static __be32 addr_bit_set(const void *t - * See include/asm-generic/bitops/le.h. - */ - return (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) & -- addr[fn_bit >> 5]; -+ net_hdr_word(&addr[fn_bit >> 5]); - } - - struct fib6_info *fib6_info_alloc(gfp_t gfp_flags, bool with_fib6_nh) ---- a/net/netfilter/nf_conntrack_proto_tcp.c -+++ b/net/netfilter/nf_conntrack_proto_tcp.c -@@ -412,7 +412,7 @@ static void tcp_sack(const struct sk_buf - - /* Fast path for timestamp-only option */ - if (length == TCPOLEN_TSTAMP_ALIGNED -- && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24) -+ && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24) - | (TCPOPT_NOP << 16) - | (TCPOPT_TIMESTAMP << 8) - | TCPOLEN_TIMESTAMP)) ---- a/net/xfrm/xfrm_input.c -+++ b/net/xfrm/xfrm_input.c -@@ -165,8 +165,8 @@ int xfrm_parse_spi(struct sk_buff *skb, - if (!pskb_may_pull(skb, hlen)) - return -EINVAL; - -- *spi = *(__be32 *)(skb_transport_header(skb) + offset); -- *seq = *(__be32 *)(skb_transport_header(skb) + offset_seq); -+ *spi = net_hdr_word(skb_transport_header(skb) + offset); -+ *seq = net_hdr_word(skb_transport_header(skb) + offset_seq); - return 0; - } - EXPORT_SYMBOL(xfrm_parse_spi); ---- a/net/ipv4/tcp_input.c -+++ b/net/ipv4/tcp_input.c -@@ -4128,14 +4128,16 @@ static bool tcp_parse_aligned_timestamp( - { - const __be32 *ptr = (const __be32 *)(th + 1); - -- if (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) -- | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { -+ if (net_hdr_word(ptr) == -+ htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) | -+ (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) { - tp->rx_opt.saw_tstamp = 1; - ++ptr; -- tp->rx_opt.rcv_tsval = ntohl(*ptr); -+ tp->rx_opt.rcv_tsval = get_unaligned_be32(ptr); - ++ptr; -- if (*ptr) -- tp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset; -+ if (net_hdr_word(ptr)) -+ tp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) - -+ tp->tsoffset; - else - tp->rx_opt.rcv_tsecr = 0; - return true; ---- a/include/uapi/linux/if_pppox.h -+++ b/include/uapi/linux/if_pppox.h -@@ -51,6 +51,7 @@ struct pppoe_addr { - */ - struct pptp_addr { - __u16 call_id; -+ __u16 pad; - struct in_addr sin_addr; - }; - ---- a/net/ipv6/netfilter/nf_log_ipv6.c -+++ b/net/ipv6/netfilter/nf_log_ipv6.c -@@ -63,9 +63,9 @@ static void dump_ipv6_packet(struct net - /* Max length: 44 "LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF " */ - nf_log_buf_add(m, "LEN=%zu TC=%u HOPLIMIT=%u FLOWLBL=%u ", - ntohs(ih->payload_len) + sizeof(struct ipv6hdr), -- (ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20, -+ (ntohl(net_hdr_word(ih)) & 0x0ff00000) >> 20, - ih->hop_limit, -- (ntohl(*(__be32 *)ih) & 0x000fffff)); -+ (ntohl(net_hdr_word(ih)) & 0x000fffff)); - - fragment = 0; - ptr = ip6hoff + sizeof(struct ipv6hdr); ---- a/include/net/neighbour.h -+++ b/include/net/neighbour.h -@@ -275,8 +275,10 @@ static inline bool neigh_key_eq128(const - const u32 *n32 = (const u32 *)n->primary_key; - const u32 *p32 = pkey; - -- return ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) | -- (n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0; -+ return ((n32[0] ^ net_hdr_word(&p32[0])) | -+ (n32[1] ^ net_hdr_word(&p32[1])) | -+ (n32[2] ^ net_hdr_word(&p32[2])) | -+ (n32[3] ^ net_hdr_word(&p32[3]))) == 0; - } - - static inline struct neighbour *___neigh_lookup_noref( ---- a/include/uapi/linux/netfilter_arp/arp_tables.h -+++ b/include/uapi/linux/netfilter_arp/arp_tables.h -@@ -70,7 +70,7 @@ struct arpt_arp { - __u8 flags; - /* Inverse flags */ - __u16 invflags; --}; -+} __attribute__((aligned(4))); - - /* Values for "flag" field in struct arpt_ip (general arp structure). - * No flags defined yet. ---- a/net/core/utils.c -+++ b/net/core/utils.c -@@ -460,8 +460,14 @@ void inet_proto_csum_replace16(__sum16 * - bool pseudohdr) - { - __be32 diff[] = { -- ~from[0], ~from[1], ~from[2], ~from[3], -- to[0], to[1], to[2], to[3], -+ ~net_hdr_word(&from[0]), -+ ~net_hdr_word(&from[1]), -+ ~net_hdr_word(&from[2]), -+ ~net_hdr_word(&from[3]), -+ net_hdr_word(&to[0]), -+ net_hdr_word(&to[1]), -+ net_hdr_word(&to[2]), -+ net_hdr_word(&to[3]), - }; - if (skb->ip_summed != CHECKSUM_PARTIAL) { - *sum = csum_fold(csum_partial(diff, sizeof(diff), ---- a/include/linux/etherdevice.h -+++ b/include/linux/etherdevice.h -@@ -513,7 +513,7 @@ static inline bool is_etherdev_addr(cons - * @b: Pointer to Ethernet header - * - * Compare two Ethernet headers, returns 0 if equal. -- * This assumes that the network header (i.e., IP header) is 4-byte -+ * This assumes that the network header (i.e., IP header) is 2-byte - * aligned OR the platform can handle unaligned access. This is the - * case for all packets coming into netif_receive_skb or similar - * entry points. -@@ -536,11 +536,12 @@ static inline unsigned long compare_ethe - fold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6); - return fold; - #else -- u32 *a32 = (u32 *)((u8 *)a + 2); -- u32 *b32 = (u32 *)((u8 *)b + 2); -+ const u16 *a16 = a; -+ const u16 *b16 = b; - -- return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | -- (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]); -+ return (a16[0] ^ b16[0]) | (a16[1] ^ b16[1]) | (a16[2] ^ b16[2]) | -+ (a16[3] ^ b16[3]) | (a16[4] ^ b16[4]) | (a16[5] ^ b16[5]) | -+ (a16[6] ^ b16[6]); - #endif - } - ---- a/net/ipv4/tcp_offload.c -+++ b/net/ipv4/tcp_offload.c -@@ -223,7 +223,7 @@ struct sk_buff *tcp_gro_receive(struct l - - th2 = tcp_hdr(p); - -- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) { -+ if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) { - NAPI_GRO_CB(p)->same_flow = 0; - continue; - } -@@ -241,8 +241,8 @@ found: - ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH)); - flush |= (__force int)(th->ack_seq ^ th2->ack_seq); - for (i = sizeof(*th); i < thlen; i += 4) -- flush |= *(u32 *)((u8 *)th + i) ^ -- *(u32 *)((u8 *)th2 + i); -+ flush |= net_hdr_word((u8 *)th + i) ^ -+ net_hdr_word((u8 *)th2 + i); - - /* When we receive our second frame we can made a decision on if we - * continue this flow as an atomic flow with a fixed ID or if we use ---- a/net/ipv6/netfilter/ip6table_mangle.c -+++ b/net/ipv6/netfilter/ip6table_mangle.c -@@ -47,7 +47,7 @@ ip6t_mangle_out(struct sk_buff *skb, con - hop_limit = ipv6_hdr(skb)->hop_limit; - - /* flowlabel and prio (includes version, which shouldn't change either */ -- flowlabel = *((u_int32_t *)ipv6_hdr(skb)); -+ flowlabel = net_hdr_word(ipv6_hdr(skb)); - - ret = ip6t_do_table(skb, state, state->net->ipv6.ip6table_mangle); - -@@ -56,7 +56,7 @@ ip6t_mangle_out(struct sk_buff *skb, con - !ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) || - skb->mark != mark || - ipv6_hdr(skb)->hop_limit != hop_limit || -- flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) { -+ flowlabel != net_hdr_word(ipv6_hdr(skb)))) { - err = ip6_route_me_harder(state->net, state->sk, skb); - if (err < 0) - ret = NF_DROP_ERR(err); diff --git a/target/linux/ath79/patches-5.10/920-mikrotik-rb4xx.patch b/target/linux/ath79/patches-5.10/920-mikrotik-rb4xx.patch deleted file mode 100644 index 5cd522cacb..0000000000 --- a/target/linux/ath79/patches-5.10/920-mikrotik-rb4xx.patch +++ /dev/null @@ -1,121 +0,0 @@ -From: Christopher Hill -Subject: [PATCH] ath79: add Mikrotik rb4xx series drivers - -This adds 3 Mikrotik rb4xx series drivers as follows: - -rb4xx-cpld: This is in the mfd subsystem, and is the parent CPLD device -that interfaces between the SoC SPI bus and its two children below. -rb4xx-gpio: This is the GPIO expander. -rb4xx-nand: This is the NAND driver. - -The history of this code comes in three phases. - -1. The first is a May 2015 attempt to push the equivalient ar71xx rb4xx -drivers upstream. See https://lore.kernel.org/patchwork/patch/940880/. - -Module-author: Gabor Juhos -Module-author: Imre Kaloz -Module-author: Bert Vermeulen - -2. Next several ar71xx patches were applied bringing the code current. - -commit 7bbf4117c6fe4b764d9d7c62fb2bcf6dd93bff2c -Submitted-by: Hauke Mehrtens - -commit af79fdbe4af32a287798b579141204bda056b8aa -commit 889272d92db689fd9c910243635e44c9d8323095 -commit e21cb649a235180563363b8af5ba8296b9ac0baa -commit 7c09fa4a7492ca436f2c94bd9a465b7c5bbeed6f -Submitted-by: Felix Fietkau - -3. Finally a heavy refactor to split the driver into the three new -subsystems, and updated to work with the device tree configuration, plus -updates and review feedback incorporated - -Reviewed-by: Thibaut VARÈNE -Submitted-by: Christopher Hill ---- - drivers/mfd/Kconfig | 8 ++++++++ - drivers/mfd/Makefile | 1 + - drivers/gpio/Kconfig | 6 ++++++ - drivers/gpio/Makefile | 1 + - drivers/mtd/nand/raw/Kconfig | 7 +++++++ - drivers/mtd/nand/raw/Makefile | 1 + - 6 files changed, 24 insertions(+) - ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -2142,6 +2142,14 @@ config RAVE_SP_CORE - Select this to get support for the Supervisory Processor - device found on several devices in RAVE line of hardware. - -+config MFD_RB4XX_CPLD -+ tristate "CPLD driver for Mikrotik RB4xx series boards" -+ select MFD_CORE -+ depends on ATH79 || COMPILE_TEST -+ help -+ Enables support for the CPLD chip (NAND & GPIO) on Mikrotik -+ Routerboard RB4xx series. -+ - config SGI_MFD_IOC3 - tristate "SGI IOC3 core driver" - depends on PCI && MIPS && 64BIT ---- a/drivers/mfd/Makefile -+++ b/drivers/mfd/Makefile -@@ -264,6 +264,7 @@ obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-b - obj-$(CONFIG_MFD_STMFX) += stmfx.o - obj-$(CONFIG_MFD_KHADAS_MCU) += khadas-mcu.o - -+obj-$(CONFIG_MFD_RB4XX_CPLD) += rb4xx-cpld.o - obj-$(CONFIG_SGI_MFD_IOC3) += ioc3.o - obj-$(CONFIG_MFD_SIMPLE_MFD_I2C) += simple-mfd-i2c.o - obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -1520,6 +1520,12 @@ config GPIO_SODAVILLE - help - Say Y here to support Intel Sodaville GPIO. - -+config GPIO_RB4XX -+ tristate "GPIO expander for Mikrotik RB4xx series boards" -+ depends on MFD_RB4XX_CPLD -+ help -+ GPIO driver for Mikrotik Routerboard RB4xx series. -+ - endmenu - - menu "SPI GPIO expanders" ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -121,6 +121,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061. - obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o - obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o - obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o -+obj-$(CONFIG_GPIO_RB4XX) += gpio-rb4xx.o - obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o - obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o - obj-$(CONFIG_GPIO_RDA) += gpio-rda.o ---- a/drivers/mtd/nand/raw/Kconfig -+++ b/drivers/mtd/nand/raw/Kconfig -@@ -564,4 +564,11 @@ config MTD_NAND_AR934X - Enables support for NAND controller on Qualcomm Atheros SoCs. - This controller is found on AR934x and QCA955x SoCs. - -+config MTD_NAND_RB4XX -+ tristate "Support for NAND driver for Mikrotik RB4xx series boards" -+ depends on MFD_RB4XX_CPLD -+ help -+ Enables support for the NAND flash chip on Mikrotik Routerboard -+ RB4xx series. -+ - endif # MTD_RAW_NAND ---- a/drivers/mtd/nand/raw/Makefile -+++ b/drivers/mtd/nand/raw/Makefile -@@ -59,6 +59,7 @@ obj-$(CONFIG_MTD_NAND_MESON) += meson_n - obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o - obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o - obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o -+obj-$(CONFIG_MTD_NAND_RB4XX) += nand_rb4xx.o - - nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o - nand-objs += nand_onfi.o diff --git a/target/linux/ath79/patches-5.10/930-ar8216-make-reg-access-atomic.patch b/target/linux/ath79/patches-5.10/930-ar8216-make-reg-access-atomic.patch deleted file mode 100644 index 02f763534e..0000000000 --- a/target/linux/ath79/patches-5.10/930-ar8216-make-reg-access-atomic.patch +++ /dev/null @@ -1,59 +0,0 @@ -From b3797d1a92afe97c173b00fdb7824cedba24eef0 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 20 Sep 2020 01:00:45 +0800 -Subject: [PATCH] ath79: ar8216: make switch register access atomic - -due to some unknown reason these register accesses sometimes fail -on the integrated switch without this patch. - -THIS ONLY WORKS ON ATH79 AND MAY BREAK THE DRIVER ON OTHER PLATFORMS! -The mdio bus on ath79 works in polling mode and doesn't rely on -any interrupt. This patch breaks the driver on any mdio master -with interrupts used. - ---- ---- a/drivers/net/phy/ar8216.c -+++ b/drivers/net/phy/ar8216.c -@@ -252,6 +252,7 @@ ar8xxx_mii_write32(struct ar8xxx_priv *p - u32 - ar8xxx_read(struct ar8xxx_priv *priv, int reg) - { -+ unsigned long flags; - struct mii_bus *bus = priv->mii_bus; - u16 r1, r2, page; - u32 val; -@@ -259,11 +260,13 @@ ar8xxx_read(struct ar8xxx_priv *priv, in - split_addr((u32) reg, &r1, &r2, &page); - - mutex_lock(&bus->mdio_lock); -+ local_irq_save(flags); - - bus->write(bus, 0x18, 0, page); - wait_for_page_switch(); - val = ar8xxx_mii_read32(priv, 0x10 | r2, r1); - -+ local_irq_restore(flags); - mutex_unlock(&bus->mdio_lock); - - return val; -@@ -272,17 +275,20 @@ ar8xxx_read(struct ar8xxx_priv *priv, in - void - ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val) - { -+ unsigned long flags; - struct mii_bus *bus = priv->mii_bus; - u16 r1, r2, page; - - split_addr((u32) reg, &r1, &r2, &page); - - mutex_lock(&bus->mdio_lock); -+ local_irq_save(flags); - - bus->write(bus, 0x18, 0, page); - wait_for_page_switch(); - ar8xxx_mii_write32(priv, 0x10 | r2, r1, val); - -+ local_irq_restore(flags); - mutex_unlock(&bus->mdio_lock); - } - diff --git a/target/linux/ath79/patches-5.10/939-mikrotik-rb91x.patch b/target/linux/ath79/patches-5.10/939-mikrotik-rb91x.patch deleted file mode 100644 index 7990061cbd..0000000000 --- a/target/linux/ath79/patches-5.10/939-mikrotik-rb91x.patch +++ /dev/null @@ -1,97 +0,0 @@ -From: Denis Kalashnikov -Subject: [PATCH] ath79: add support for reset key on MikroTik RB912UAG-2HPnD - -On MikroTik RB91x board series a reset key shares SoC gpio -line #15 with NAND ALE and NAND IO7. So we need a custom -gpio driver to manage this non-trivial connection schema. -Also rb91x-nand needs to have an ability to disable a polling -of the key while it works with NAND. - -While we've been integrating rb91x-key into a firmware, we've -figured out that: -* In the gpio-latch driver we need to add a "cansleep" suffix to -several gpiolib calls, -* When gpio-latch and rb91x-nand fail to get a gpio and an error -is -EPROBE_DEFER, they shouldn't report about this, since this -actually is not an error and occurs when the gpio-latch probe -function is called before the rb91x-key probe. -We fix these related things here too. - -Submitted-by: Denis Kalashnikov -Reviewed-by: Sergey Ryazanov -Tested-by: Koen Vandeputte ---- - drivers/gpio/Kconfig | 11 +++++++++++ - drivers/gpio/Makefile | 2 ++ - drivers/mtd/nand/raw/Kconfig | 6 ++++++ - drivers/mtd/nand/raw/Makefile | 1 + - 7 files changed, 20 insertions(+) - ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -341,6 +341,13 @@ config GPIO_IXP4XX - IXP4xx series of chips. - - If unsure, say N. -+ -+config GPIO_LATCH -+ tristate "MikroTik RouterBOARD GPIO latch support" -+ depends on ATH79 -+ help -+ GPIO driver for latch on some MikroTik RouterBOARDs. -+ - config GPIO_LOGICVC - tristate "Xylon LogiCVC GPIO support" - depends on MFD_SYSCON && OF -@@ -495,6 +502,10 @@ config GPIO_REG - A 32-bit single register GPIO fixed in/out implementation. This - can be used to represent any register as a set of GPIO signals. - -+config GPIO_RB91X_KEY -+ tristate "MikroTik RB91x board series reset key support" -+ depends on ATH79 -+ - config GPIO_SAMA5D2_PIOBU - tristate "SAMA5D2 PIOBU GPIO support" - depends on MFD_SYSCON ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -73,6 +73,7 @@ obj-$(CONFIG_GPIO_IT87) += gpio-it87.o - obj-$(CONFIG_GPIO_IXP4XX) += gpio-ixp4xx.o - obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o - obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o -+obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o - obj-$(CONFIG_GPIO_LOGICVC) += gpio-logicvc.o - obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o - obj-$(CONFIG_GPIO_LOONGSON) += gpio-loongson.o -@@ -122,6 +123,7 @@ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio - obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o - obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o - obj-$(CONFIG_GPIO_RB4XX) += gpio-rb4xx.o -+obj-$(CONFIG_GPIO_RB91X_KEY) += gpio-rb91x-key.o - obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o - obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o - obj-$(CONFIG_GPIO_RDA) += gpio-rda.o ---- a/drivers/mtd/nand/raw/Kconfig -+++ b/drivers/mtd/nand/raw/Kconfig -@@ -571,4 +571,10 @@ config MTD_NAND_RB4XX - Enables support for the NAND flash chip on Mikrotik Routerboard - RB4xx series. - -+config MTD_NAND_RB91X -+ tristate "MikroTik RB91x NAND driver support" -+ depends on ATH79 && MTD_RAW_NAND -+ help -+ Enables support for the NAND flash chip on MikroTik RB91x series. -+ - endif # MTD_RAW_NAND ---- a/drivers/mtd/nand/raw/Makefile -+++ b/drivers/mtd/nand/raw/Makefile -@@ -60,6 +60,7 @@ obj-$(CONFIG_MTD_NAND_CADENCE) += caden - obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o - obj-$(CONFIG_MTD_NAND_AR934X) += ar934x_nand.o - obj-$(CONFIG_MTD_NAND_RB4XX) += nand_rb4xx.o -+obj-$(CONFIG_MTD_NAND_RB91X) += rb91x_nand.o - - nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o - nand-objs += nand_onfi.o diff --git a/target/linux/ath79/patches-5.10/940-ath79-add-support-for-booting-QCN550x.patch b/target/linux/ath79/patches-5.10/940-ath79-add-support-for-booting-QCN550x.patch deleted file mode 100644 index cf77433634..0000000000 --- a/target/linux/ath79/patches-5.10/940-ath79-add-support-for-booting-QCN550x.patch +++ /dev/null @@ -1,48 +0,0 @@ -From: Wenli Looi -Date: Sun, 20 Jun 2021 23:32:28 -0700 -Subject: [PATCH] ath79: add support for booting QCN550x - -Based on wikidevi, QCN550x is a "Dragonfly" like QCA9561 and QCA9563. -Treating it as QCA956x seems to work. -Tested on Netgear EX7300v2 which boots successfully with -the same CPU clock as the stock firmware. - -Link: https://wikidevi.wi-cat.ru/Qualcomm#bgn -Link: https://wikidevi.wi-cat.ru/Qualcomm_Atheros#.28a.29bgn_2 -Signed-off-by: Wenli Looi - ---- a/arch/mips/ath79/early_printk.c -+++ b/arch/mips/ath79/early_printk.c -@@ -121,6 +121,7 @@ static void prom_putchar_init(void) - case REV_ID_MAJOR_QCA9558: - case REV_ID_MAJOR_TP9343: - case REV_ID_MAJOR_QCA956X: -+ case REV_ID_MAJOR_QCN550X: - _prom_putchar = prom_putchar_ar71xx; - break; - ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -168,6 +168,12 @@ static void __init ath79_detect_sys_type - rev = id & QCA956X_REV_ID_REVISION_MASK; - break; - -+ case REV_ID_MAJOR_QCN550X: -+ ath79_soc = ATH79_SOC_QCA956X; -+ chip = "550X"; -+ rev = id & QCA956X_REV_ID_REVISION_MASK; -+ break; -+ - case REV_ID_MAJOR_TP9343: - ath79_soc = ATH79_SOC_TP9343; - chip = "9343"; ---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h -@@ -867,6 +867,7 @@ - #define REV_ID_MAJOR_QCA9558 0x1130 - #define REV_ID_MAJOR_TP9343 0x0150 - #define REV_ID_MAJOR_QCA956X 0x1150 -+#define REV_ID_MAJOR_QCN550X 0x2170 - - #define AR71XX_REV_ID_MINOR_MASK 0x3 - #define AR71XX_REV_ID_MINOR_AR7130 0x0 diff --git a/target/linux/bcm47xx/config-5.10 b/target/linux/bcm47xx/config-5.10 deleted file mode 100644 index bee300d9c0..0000000000 --- a/target/linux/bcm47xx/config-5.10 +++ /dev/null @@ -1,213 +0,0 @@ -CONFIG_ARCH_BINFMT_ELF_STATE=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DISCARD_MEMBLOCK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_BCM47XX=y -CONFIG_BCM47XX_BCMA=y -CONFIG_BCM47XX_NVRAM=y -CONFIG_BCM47XX_SPROM=y -CONFIG_BCM47XX_SSB=y -CONFIG_BCM47XX_WDT=y -CONFIG_BCMA=y -CONFIG_BCMA_BLOCKIO=y -CONFIG_BCMA_DEBUG=y -CONFIG_BCMA_DRIVER_GMAC_CMN=y -CONFIG_BCMA_DRIVER_GPIO=y -CONFIG_BCMA_DRIVER_MIPS=y -CONFIG_BCMA_DRIVER_PCI=y -CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y -CONFIG_BCMA_HOST_PCI=y -CONFIG_BCMA_HOST_PCI_POSSIBLE=y -CONFIG_BCMA_HOST_SOC=y -CONFIG_BCMA_NFLASH=y -CONFIG_BCMA_PFLASH=y -CONFIG_BCMA_SFLASH=y -# CONFIG_BGMAC_BCMA is not set -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="noinitrd console=ttyS0,115200" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -# CONFIG_COMMON_CLK is not set -CONFIG_COMPAT_32BIT_TIME=y -# CONFIG_CPU_BMIPS is not set -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -CONFIG_CPU_MIPSR1=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_R4K_FPU=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_DIRECT_OPS=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y -CONFIG_DMA_NONCOHERENT_MMAP=y -CONFIG_DMA_NONCOHERENT_OPS=y -# CONFIG_EARLY_PRINTK is not set -CONFIG_FIXED_PHY=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_WDT=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_COMPILER_H=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_CBPF_JIT=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LEDS_GPIO_REGISTER=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_BCM47XXSFLASH=y -CONFIG_MTD_BCM47XX_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_BCM47XXNFLASH=y -CONFIG_MTD_NAND_BRCMNAND=y -CONFIG_MTD_NAND_BRCMNAND_BCMA=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_PHYSMAP=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NO_EXCEPT_FILL=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -# CONFIG_OF is not set -CONFIG_PCI=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SRCU=y -CONFIG_SSB=y -CONFIG_SSB_B43_PCI_BRIDGE=y -CONFIG_SSB_BLOCKIO=y -CONFIG_SSB_DRIVER_EXTIF=y -CONFIG_SSB_DRIVER_GIGE=y -CONFIG_SSB_DRIVER_GPIO=y -CONFIG_SSB_DRIVER_MIPS=y -CONFIG_SSB_DRIVER_PCICORE=y -CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y -CONFIG_SSB_EMBEDDED=y -CONFIG_SSB_HOST_SOC=y -CONFIG_SSB_PCICORE_HOSTMODE=y -CONFIG_SSB_PCIHOST=y -CONFIG_SSB_PCIHOST_POSSIBLE=y -CONFIG_SSB_SERIAL=y -CONFIG_SSB_SFLASH=y -CONFIG_SSB_SPROM=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_B53=y -# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set -CONFIG_SWCONFIG_B53_PHY_DRIVER=y -CONFIG_SWCONFIG_B53_PHY_FIXUP=y -# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_BMIPS=y -CONFIG_SYS_HAS_CPU_BMIPS32_3300=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/bcm47xx/patches-5.10/030-v5.17-0001-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch b/target/linux/bcm47xx/patches-5.10/030-v5.17-0001-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch deleted file mode 100644 index 921825be5c..0000000000 --- a/target/linux/bcm47xx/patches-5.10/030-v5.17-0001-MIPS-BCM47XX-Define-Linksys-WRT310N-V2-buttons.patch +++ /dev/null @@ -1,40 +0,0 @@ -From eea175eedf3e2f71b9538d21e643e7a1be4923df Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Thu, 6 Jan 2022 19:51:37 -0800 -Subject: [PATCH] MIPS: BCM47XX: Define Linksys WRT310N V2 buttons - -Update the buttons registration code to register the two buttons (WPS, -system rester) using the existing BCM47XX_BOARD_LINKSYS_WRT310NV2 board -entry. - -Signed-off-by: Florian Fainelli -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/bcm47xx/buttons.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/mips/bcm47xx/buttons.c -+++ b/arch/mips/bcm47xx/buttons.c -@@ -277,6 +277,12 @@ bcm47xx_buttons_linksys_wrt310nv1[] __in - }; - - static const struct gpio_keys_button -+bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = { -+ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), -+ BCM47XX_GPIO_KEY(6, KEY_RESTART), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = { - BCM47XX_GPIO_KEY(5, KEY_WIMAX), - BCM47XX_GPIO_KEY(6, KEY_RESTART), -@@ -608,6 +614,9 @@ int __init bcm47xx_buttons_register(void - case BCM47XX_BOARD_LINKSYS_WRT310NV1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1); - break; -+ case BCM47XX_BOARD_LINKSYS_WRT310NV2: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2); -+ break; - case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: - err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2); - break; diff --git a/target/linux/bcm47xx/patches-5.10/030-v5.17-0002-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch b/target/linux/bcm47xx/patches-5.10/030-v5.17-0002-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch deleted file mode 100644 index 3fb013a585..0000000000 --- a/target/linux/bcm47xx/patches-5.10/030-v5.17-0002-MIPS-BCM47XX-Add-board-entry-for-Linksys-WRT320N-v1.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 3829e4f10a232964cc728c0479c8097922e5e073 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Thu, 6 Jan 2022 19:51:38 -0800 -Subject: [PATCH] MIPS: BCM47XX: Add board entry for Linksys WRT320N v1 - -This router is based on a Broadcom BCM4717A1 chipset and supports -802.11n Wi-Fi. Add a board entry for that router and register LEDs and -buttons accordingly. - -Signed-off-by: Florian Fainelli -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/bcm47xx/board.c | 1 + - arch/mips/bcm47xx/buttons.c | 9 +++++++++ - arch/mips/bcm47xx/leds.c | 10 ++++++++++ - arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + - 4 files changed, 21 insertions(+) - ---- a/arch/mips/bcm47xx/board.c -+++ b/arch/mips/bcm47xx/board.c -@@ -141,6 +141,7 @@ struct bcm47xx_board_type_list2 bcm47xx_ - {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"}, - {{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"}, -+ {{BCM47XX_BOARD_LINKSYS_WRT320N_V1, "Linksys WRT320N V1"}, "WRT320N", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"}, ---- a/arch/mips/bcm47xx/buttons.c -+++ b/arch/mips/bcm47xx/buttons.c -@@ -283,6 +283,12 @@ bcm47xx_buttons_linksys_wrt310n_v2[] __i - }; - - static const struct gpio_keys_button -+bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = { -+ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), -+ BCM47XX_GPIO_KEY(8, KEY_RESTART), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = { - BCM47XX_GPIO_KEY(5, KEY_WIMAX), - BCM47XX_GPIO_KEY(6, KEY_RESTART), -@@ -617,6 +623,9 @@ int __init bcm47xx_buttons_register(void - case BCM47XX_BOARD_LINKSYS_WRT310NV2: - err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2); - break; -+ case BCM47XX_BOARD_LINKSYS_WRT320N_V1: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1); -+ break; - case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: - err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2); - break; ---- a/arch/mips/bcm47xx/leds.c -+++ b/arch/mips/bcm47xx/leds.c -@@ -314,6 +314,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initc - }; - - static const struct gpio_led -+bcm47xx_leds_linksys_wrt320n_v1[] __initconst = { -+ BCM47XX_GPIO_LED(1, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON), -+ BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), -+}; -+ -+static const struct gpio_led - bcm47xx_leds_linksys_wrt54g_generic[] __initconst = { - BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF), - BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), -@@ -689,6 +696,9 @@ void __init bcm47xx_leds_register(void) - case BCM47XX_BOARD_LINKSYS_WRT310NV1: - bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1); - break; -+ case BCM47XX_BOARD_LINKSYS_WRT320N_V1: -+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1); -+ break; - case BCM47XX_BOARD_LINKSYS_WRT54G3GV2: - bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2); - break; ---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -@@ -72,6 +72,7 @@ enum bcm47xx_board { - BCM47XX_BOARD_LINKSYS_WRT300NV11, - BCM47XX_BOARD_LINKSYS_WRT310NV1, - BCM47XX_BOARD_LINKSYS_WRT310NV2, -+ BCM47XX_BOARD_LINKSYS_WRT320N_V1, - BCM47XX_BOARD_LINKSYS_WRT54G3GV2, - BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, - BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, diff --git a/target/linux/bcm47xx/patches-5.10/030-v5.17-0003-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch b/target/linux/bcm47xx/patches-5.10/030-v5.17-0003-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch deleted file mode 100644 index c09140e99d..0000000000 --- a/target/linux/bcm47xx/patches-5.10/030-v5.17-0003-MIPS-BCM47XX-Add-LEDs-and-buttons-for-Asus-RTN-10U.patch +++ /dev/null @@ -1,67 +0,0 @@ -From aecf89f2f8e8a604c33085c230a1f04ea325de64 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Thu, 6 Jan 2022 19:51:39 -0800 -Subject: [PATCH] MIPS: BCM47XX: Add LEDs and buttons for Asus RTN-10U - -Add the definitions for the buttons and LEDs used on the Asus RTN-10U -router. - -Signed-off-by: Florian Fainelli -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/bcm47xx/buttons.c | 9 +++++++++ - arch/mips/bcm47xx/leds.c | 11 +++++++++++ - 2 files changed, 20 insertions(+) - ---- a/arch/mips/bcm47xx/buttons.c -+++ b/arch/mips/bcm47xx/buttons.c -@@ -27,6 +27,12 @@ - /* Asus */ - - static const struct gpio_keys_button -+bcm47xx_buttons_asus_rtn10u[] __initconst = { -+ BCM47XX_GPIO_KEY(20, KEY_WPS_BUTTON), -+ BCM47XX_GPIO_KEY(21, KEY_RESTART), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_asus_rtn12[] __initconst = { - BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), - BCM47XX_GPIO_KEY(1, KEY_RESTART), -@@ -490,6 +496,9 @@ int __init bcm47xx_buttons_register(void - int err; - - switch (board) { -+ case BCM47XX_BOARD_ASUS_RTN10U: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn10u); -+ break; - case BCM47XX_BOARD_ASUS_RTN12: - err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12); - break; ---- a/arch/mips/bcm47xx/leds.c -+++ b/arch/mips/bcm47xx/leds.c -@@ -30,6 +30,14 @@ - /* Asus */ - - static const struct gpio_led -+bcm47xx_leds_asus_rtn10u[] __initconst = { -+ BCM47XX_GPIO_LED(5, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(6, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON), -+ BCM47XX_GPIO_LED(7, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(8, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF), -+}; -+ -+static const struct gpio_led - bcm47xx_leds_asus_rtn12[] __initconst = { - BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), - BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), -@@ -563,6 +571,9 @@ void __init bcm47xx_leds_register(void) - enum bcm47xx_board board = bcm47xx_board_get(); - - switch (board) { -+ case BCM47XX_BOARD_ASUS_RTN10U: -+ bcm47xx_set_pdata(bcm47xx_leds_asus_rtn10u); -+ break; - case BCM47XX_BOARD_ASUS_RTN12: - bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12); - break; diff --git a/target/linux/bcm47xx/patches-5.10/030-v5.17-0004-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch b/target/linux/bcm47xx/patches-5.10/030-v5.17-0004-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch deleted file mode 100644 index 8740942d6f..0000000000 --- a/target/linux/bcm47xx/patches-5.10/030-v5.17-0004-MIPS-BCM47XX-Add-support-for-Netgear-R6300-v1.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 15e690af5cc3cd8f5d14ee2aa3a093f80196110e Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Thu, 6 Jan 2022 19:51:40 -0800 -Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear R6300 v1 - -Add support for the Netgear R6300 v1 Wi-Fi router using a Broadcom -BCM4706 chipset and supporting 802.11n and 802.11ac. - -Signed-off-by: Florian Fainelli -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/bcm47xx/board.c | 1 + - arch/mips/bcm47xx/buttons.c | 8 ++++++++ - arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + - 3 files changed, 10 insertions(+) - ---- a/arch/mips/bcm47xx/board.c -+++ b/arch/mips/bcm47xx/board.c -@@ -162,6 +162,7 @@ struct bcm47xx_board_type_list1 bcm47xx_ - {{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"}, - {{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"}, - {{BCM47XX_BOARD_NETGEAR_R6200_V1, "Netgear R6200 V1"}, "U12H192T00_NETGEAR"}, -+ {{BCM47XX_BOARD_NETGEAR_R6300_V1, "Netgear R6300 V1"}, "U12H218T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"}, ---- a/arch/mips/bcm47xx/buttons.c -+++ b/arch/mips/bcm47xx/buttons.c -@@ -410,6 +410,11 @@ bcm47xx_buttons_netgear_r6200_v1[] __ini - }; - - static const struct gpio_keys_button -+bcm47xx_buttons_netgear_r6300_v1[] __initconst = { -+ BCM47XX_GPIO_KEY(6, KEY_RESTART), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_netgear_wndr3400v1[] __initconst = { - BCM47XX_GPIO_KEY(4, KEY_RESTART), - BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), -@@ -701,6 +706,9 @@ int __init bcm47xx_buttons_register(void - case BCM47XX_BOARD_NETGEAR_R6200_V1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6200_v1); - break; -+ case BCM47XX_BOARD_NETGEAR_R6300_V1: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1); -+ break; - case BCM47XX_BOARD_NETGEAR_WNDR3400V1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1); - break; ---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -@@ -100,6 +100,7 @@ enum bcm47xx_board { - BCM47XX_BOARD_MOTOROLA_WR850GV2V3, - - BCM47XX_BOARD_NETGEAR_R6200_V1, -+ BCM47XX_BOARD_NETGEAR_R6300_V1, - BCM47XX_BOARD_NETGEAR_WGR614V8, - BCM47XX_BOARD_NETGEAR_WGR614V9, - BCM47XX_BOARD_NETGEAR_WGR614_V10, diff --git a/target/linux/bcm47xx/patches-5.10/030-v5.17-0005-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch b/target/linux/bcm47xx/patches-5.10/030-v5.17-0005-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch deleted file mode 100644 index 6975bce952..0000000000 --- a/target/linux/bcm47xx/patches-5.10/030-v5.17-0005-MIPS-BCM47XX-Add-support-for-Netgear-WN2500RP-v1-v2.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 4da27b6d550427a0560a15df36de99cb17629216 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Thu, 6 Jan 2022 19:51:41 -0800 -Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear WN2500RP v1 & v2 - -Add support for the Netgear WN2500 RP v1 and v2 Wi-Fi range extenders -based on the BCM5357 chipset and supporting 802.11n and 802.11ac. - -Signed-off-by: Florian Fainelli -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/bcm47xx/board.c | 2 ++ - arch/mips/bcm47xx/buttons.c | 9 +++++++++ - arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 2 ++ - 3 files changed, 13 insertions(+) - ---- a/arch/mips/bcm47xx/board.c -+++ b/arch/mips/bcm47xx/board.c -@@ -166,6 +166,8 @@ struct bcm47xx_board_type_list1 bcm47xx_ - {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"}, -+ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V1, "Netgear WN2500RP V1"}, "U12H197T00_NETGEAR"}, -+ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V2, "Netgear WN2500RP V2"}, "U12H294T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"}, ---- a/arch/mips/bcm47xx/buttons.c -+++ b/arch/mips/bcm47xx/buttons.c -@@ -415,6 +415,12 @@ bcm47xx_buttons_netgear_r6300_v1[] __ini - }; - - static const struct gpio_keys_button -+bcm47xx_buttons_netgear_wn2500rp_v1[] __initconst = { -+ BCM47XX_GPIO_KEY(12, KEY_RESTART), -+ BCM47XX_GPIO_KEY(31, KEY_WPS_BUTTON), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_netgear_wndr3400v1[] __initconst = { - BCM47XX_GPIO_KEY(4, KEY_RESTART), - BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), -@@ -709,6 +715,9 @@ int __init bcm47xx_buttons_register(void - case BCM47XX_BOARD_NETGEAR_R6300_V1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1); - break; -+ case BCM47XX_BOARD_NETGEAR_WN2500RP_V1: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wn2500rp_v1); -+ break; - case BCM47XX_BOARD_NETGEAR_WNDR3400V1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1); - break; ---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -@@ -104,6 +104,8 @@ enum bcm47xx_board { - BCM47XX_BOARD_NETGEAR_WGR614V8, - BCM47XX_BOARD_NETGEAR_WGR614V9, - BCM47XX_BOARD_NETGEAR_WGR614_V10, -+ BCM47XX_BOARD_NETGEAR_WN2500RP_V1, -+ BCM47XX_BOARD_NETGEAR_WN2500RP_V2, - BCM47XX_BOARD_NETGEAR_WNDR3300, - BCM47XX_BOARD_NETGEAR_WNDR3400V1, - BCM47XX_BOARD_NETGEAR_WNDR3400V2, diff --git a/target/linux/bcm47xx/patches-5.10/031-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch b/target/linux/bcm47xx/patches-5.10/031-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch deleted file mode 100644 index 8c2233c804..0000000000 --- a/target/linux/bcm47xx/patches-5.10/031-v6.0-MIPS-BCM47XX-Add-support-for-Netgear-WNR3500L-v2.patch +++ /dev/null @@ -1,109 +0,0 @@ -From c022e87162219d67d687df22c977d1c2fc95fb42 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Thu, 14 Jul 2022 14:13:01 -0700 -Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear WNR3500L v2 - -Add support for the Netgear WNR3500L v2 router based on the BCM47186 -chipset and supporting 802.11n Wi-Fi. - -Signed-off-by: Florian Fainelli -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/bcm47xx/board.c | 2 ++ - arch/mips/bcm47xx/buttons.c | 10 ++++++++++ - arch/mips/bcm47xx/leds.c | 11 +++++++++++ - arch/mips/bcm47xx/workarounds.c | 1 + - arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + - 5 files changed, 25 insertions(+) - ---- a/arch/mips/bcm47xx/board.c -+++ b/arch/mips/bcm47xx/board.c -@@ -181,6 +181,7 @@ struct bcm47xx_board_type_list1 bcm47xx_ - {{BCM47XX_BOARD_NETGEAR_WNR1000_V3, "Netgear WNR1000 V3"}, "U12H139T50_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"}, -+ {{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "U12H172T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"}, -@@ -195,6 +196,7 @@ struct bcm47xx_board_type_list3 bcm47xx_ - {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, - {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, - {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"}, -+ {{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "0x052b", "3500L", "02"}, - {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, "Linksys WRT54G/GS/GL"}, "0x0101", "42", "0x10"}, - {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, "Linksys WRT54G/GS/GL"}, "0x0467", "42", "0x10"}, - {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708, "Linksys WRT54G/GS/GL"}, "0x0708", "42", "0x10"}, ---- a/arch/mips/bcm47xx/buttons.c -+++ b/arch/mips/bcm47xx/buttons.c -@@ -460,6 +460,13 @@ bcm47xx_buttons_netgear_wnr3500lv1[] __i - }; - - static const struct gpio_keys_button -+bcm47xx_buttons_netgear_wnr3500lv2[] __initconst = { -+ BCM47XX_GPIO_KEY(4, KEY_RESTART), -+ BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), -+ BCM47XX_GPIO_KEY(8, KEY_RFKILL), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_netgear_wnr834bv2[] __initconst = { - BCM47XX_GPIO_KEY(6, KEY_RESTART), - }; -@@ -736,6 +743,9 @@ int __init bcm47xx_buttons_register(void - case BCM47XX_BOARD_NETGEAR_WNR3500L: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv1); - break; -+ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv2); -+ break; - case BCM47XX_BOARD_NETGEAR_WNR834BV2: - err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr834bv2); - break; ---- a/arch/mips/bcm47xx/leds.c -+++ b/arch/mips/bcm47xx/leds.c -@@ -528,6 +528,14 @@ bcm47xx_leds_netgear_wnr3500lv1[] __init - }; - - static const struct gpio_led -+bcm47xx_leds_netgear_wnr3500lv2[] __initconst = { -+ BCM47XX_GPIO_LED(0, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(1, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), -+ BCM47XX_GPIO_LED(3, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON), -+ BCM47XX_GPIO_LED(7, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF), -+}; -+ -+static const struct gpio_led - bcm47xx_leds_netgear_wnr834bv2[] __initconst = { - BCM47XX_GPIO_LED(2, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON), - BCM47XX_GPIO_LED(3, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF), -@@ -791,6 +799,9 @@ void __init bcm47xx_leds_register(void) - case BCM47XX_BOARD_NETGEAR_WNR3500L: - bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv1); - break; -+ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2: -+ bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv2); -+ break; - case BCM47XX_BOARD_NETGEAR_WNR834BV2: - bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2); - break; ---- a/arch/mips/bcm47xx/workarounds.c -+++ b/arch/mips/bcm47xx/workarounds.c -@@ -22,6 +22,7 @@ void __init bcm47xx_workarounds(void) - - switch (board) { - case BCM47XX_BOARD_NETGEAR_WNR3500L: -+ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2: - bcm47xx_workarounds_enable_usb_power(12); - break; - case BCM47XX_BOARD_NETGEAR_WNDR3400V2: ---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -@@ -118,6 +118,7 @@ enum bcm47xx_board { - BCM47XX_BOARD_NETGEAR_WNR1000_V3, - BCM47XX_BOARD_NETGEAR_WNR2000, - BCM47XX_BOARD_NETGEAR_WNR3500L, -+ BCM47XX_BOARD_NETGEAR_WNR3500L_V2, - BCM47XX_BOARD_NETGEAR_WNR3500U, - BCM47XX_BOARD_NETGEAR_WNR3500V2, - BCM47XX_BOARD_NETGEAR_WNR3500V2VC, diff --git a/target/linux/bcm47xx/patches-5.10/032-v6.3-MIPS-BCM47XX-Add-support-for-Linksys-E2500-V3.patch b/target/linux/bcm47xx/patches-5.10/032-v6.3-MIPS-BCM47XX-Add-support-for-Linksys-E2500-V3.patch deleted file mode 100644 index 4faecdc7d5..0000000000 --- a/target/linux/bcm47xx/patches-5.10/032-v6.3-MIPS-BCM47XX-Add-support-for-Linksys-E2500-V3.patch +++ /dev/null @@ -1,65 +0,0 @@ -From fc605b914167de75432c3b5aae239fb191e84a31 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 8 Feb 2023 08:03:01 +0100 -Subject: [PATCH] MIPS: BCM47XX: Add support for Linksys E2500 V3 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's a BCM5358 based home WiFi router. 16 MiB flash, 64 MiB RAM, BCM5325 -switch, on-SoC 802.11n radio. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/bcm47xx/board.c | 1 + - arch/mips/bcm47xx/buttons.c | 9 +++++++++ - arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + - 3 files changed, 11 insertions(+) - ---- a/arch/mips/bcm47xx/board.c -+++ b/arch/mips/bcm47xx/board.c -@@ -130,6 +130,7 @@ struct bcm47xx_board_type_list2 bcm47xx_ - {{BCM47XX_BOARD_LINKSYS_E1000V21, "Linksys E1000 V2.1"}, "E1000", "2.1"}, - {{BCM47XX_BOARD_LINKSYS_E1200V2, "Linksys E1200 V2"}, "E1200", "2.0"}, - {{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"}, -+ {{BCM47XX_BOARD_LINKSYS_E2500V3, "Linksys E2500 V3"}, "E2500", "1.0"}, - /* like WRT610N v2.0 */ - {{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"}, - {{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"}, ---- a/arch/mips/bcm47xx/buttons.c -+++ b/arch/mips/bcm47xx/buttons.c -@@ -223,6 +223,12 @@ bcm47xx_buttons_linksys_e2000v1[] __init - }; - - static const struct gpio_keys_button -+bcm47xx_buttons_linksys_e2500v3[] __initconst = { -+ BCM47XX_GPIO_KEY(9, KEY_WPS_BUTTON), -+ BCM47XX_GPIO_KEY(10, KEY_RESTART), -+}; -+ -+static const struct gpio_keys_button - bcm47xx_buttons_linksys_e3000v1[] __initconst = { - BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), - BCM47XX_GPIO_KEY(6, KEY_RESTART), -@@ -617,6 +623,9 @@ int __init bcm47xx_buttons_register(void - case BCM47XX_BOARD_LINKSYS_E2000V1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2000v1); - break; -+ case BCM47XX_BOARD_LINKSYS_E2500V3: -+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2500v3); -+ break; - case BCM47XX_BOARD_LINKSYS_E3000V1: - err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3000v1); - break; ---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -@@ -61,6 +61,7 @@ enum bcm47xx_board { - BCM47XX_BOARD_LINKSYS_E1000V21, - BCM47XX_BOARD_LINKSYS_E1200V2, - BCM47XX_BOARD_LINKSYS_E2000V1, -+ BCM47XX_BOARD_LINKSYS_E2500V3, - BCM47XX_BOARD_LINKSYS_E3000V1, - BCM47XX_BOARD_LINKSYS_E3200V1, - BCM47XX_BOARD_LINKSYS_E4200V1, diff --git a/target/linux/bcm47xx/patches-5.10/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch b/target/linux/bcm47xx/patches-5.10/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch deleted file mode 100644 index 8efda10809..0000000000 --- a/target/linux/bcm47xx/patches-5.10/100-v5.18-mtd-rawnand-brcmnand-Assign-soc-as-early-as-possible.patch +++ /dev/null @@ -1,33 +0,0 @@ -From: Florian Fainelli -Subject: [PATCH v3 1/9] mtd: rawnand: brcmnand: Assign soc as early as possible -Date: Fri, 07 Jan 2022 10:46:06 -0800 -Content-Type: text/plain; charset="utf-8" - -In order to key off the brcmnand_probe() code in subsequent changes -depending upon ctrl->soc, assign that variable as early as possible, -instead of much later when we have checked that it is non-NULL. - -Signed-off-by: Florian Fainelli ---- - drivers/mtd/nand/raw/brcmnand/brcmnand.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -2949,6 +2949,7 @@ int brcmnand_probe(struct platform_devic - - dev_set_drvdata(dev, ctrl); - ctrl->dev = dev; -+ ctrl->soc = soc; - - init_completion(&ctrl->done); - init_completion(&ctrl->dma_done); -@@ -3089,8 +3090,6 @@ int brcmnand_probe(struct platform_devic - * interesting ways - */ - if (soc) { -- ctrl->soc = soc; -- - ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, - DRV_NAME, ctrl); - diff --git a/target/linux/bcm47xx/patches-5.10/101-v5.18-mtd-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch b/target/linux/bcm47xx/patches-5.10/101-v5.18-mtd-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch deleted file mode 100644 index 23f5df3015..0000000000 --- a/target/linux/bcm47xx/patches-5.10/101-v5.18-mtd-rawnand-brcmnand-Allow-SoC-to-provide-I-O-operations.patch +++ /dev/null @@ -1,150 +0,0 @@ -From: Florian Fainelli -Subject: [PATCH v3 2/9] mtd: rawnand: brcmnand: Allow SoC to provide I/O operations -Date: Fri, 07 Jan 2022 10:46:07 -0800 -Content-Type: text/plain; charset="utf-8" - -Allow a brcmnand_soc instance to provide a custom set of I/O operations -which we will require when using this driver on a BCMA bus which is not -directly memory mapped I/O. Update the nand_{read,write}_reg accordingly -to use the SoC operations if provided. - -To minimize the penalty on other SoCs which do support standard MMIO -accesses, we use a static key which is disabled by default and gets -enabled if a soc implementation does provide I/O operations. - -Signed-off-by: Florian Fainelli ---- - drivers/mtd/nand/raw/brcmnand/brcmnand.c | 28 +++++++++++++++++++++-- - drivers/mtd/nand/raw/brcmnand/brcmnand.h | 29 ++++++++++++++++++++++++ - 2 files changed, 55 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -25,6 +25,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -207,6 +208,8 @@ enum { - - struct brcmnand_host; - -+static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key); -+ - struct brcmnand_controller { - struct device *dev; - struct nand_controller controller; -@@ -589,15 +592,25 @@ enum { - INTFC_CTLR_READY = BIT(31), - }; - -+static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl) -+{ -+ return static_branch_unlikely(&brcmnand_soc_has_ops_key); -+} -+ - static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) - { -+ if (brcmnand_non_mmio_ops(ctrl)) -+ return brcmnand_soc_read(ctrl->soc, offs); - return brcmnand_readl(ctrl->nand_base + offs); - } - - static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, - u32 val) - { -- brcmnand_writel(val, ctrl->nand_base + offs); -+ if (brcmnand_non_mmio_ops(ctrl)) -+ brcmnand_soc_write(ctrl->soc, val, offs); -+ else -+ brcmnand_writel(val, ctrl->nand_base + offs); - } - - static int brcmnand_revision_init(struct brcmnand_controller *ctrl) -@@ -763,13 +776,18 @@ static inline void brcmnand_rmw_reg(stru - - static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) - { -+ if (brcmnand_non_mmio_ops(ctrl)) -+ return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR); - return __raw_readl(ctrl->nand_fc + word * 4); - } - - static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, - int word, u32 val) - { -- __raw_writel(val, ctrl->nand_fc + word * 4); -+ if (brcmnand_non_mmio_ops(ctrl)) -+ brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR); -+ else -+ __raw_writel(val, ctrl->nand_fc + word * 4); - } - - static inline void edu_writel(struct brcmnand_controller *ctrl, -@@ -2951,6 +2969,12 @@ int brcmnand_probe(struct platform_devic - ctrl->dev = dev; - ctrl->soc = soc; - -+ /* Enable the static key if the soc provides I/O operations indicating -+ * that a non-memory mapped IO access path must be used -+ */ -+ if (brcmnand_soc_has_ops(ctrl->soc)) -+ static_branch_enable(&brcmnand_soc_has_ops_key); -+ - init_completion(&ctrl->done); - init_completion(&ctrl->dma_done); - init_completion(&ctrl->edu_done); ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.h -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.h -@@ -11,12 +11,25 @@ - - struct platform_device; - struct dev_pm_ops; -+struct brcmnand_io_ops; -+ -+/* Special register offset constant to intercept a non-MMIO access -+ * to the flash cache register space. This is intentionally large -+ * not to overlap with an existing offset. -+ */ -+#define BRCMNAND_NON_MMIO_FC_ADDR 0xffffffff - - struct brcmnand_soc { - bool (*ctlrdy_ack)(struct brcmnand_soc *soc); - void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en); - void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare, - bool is_param); -+ const struct brcmnand_io_ops *ops; -+}; -+ -+struct brcmnand_io_ops { -+ u32 (*read_reg)(struct brcmnand_soc *soc, u32 offset); -+ void (*write_reg)(struct brcmnand_soc *soc, u32 val, u32 offset); - }; - - static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc, -@@ -58,6 +71,22 @@ static inline void brcmnand_writel(u32 v - writel_relaxed(val, addr); - } - -+static inline bool brcmnand_soc_has_ops(struct brcmnand_soc *soc) -+{ -+ return soc && soc->ops && soc->ops->read_reg && soc->ops->write_reg; -+} -+ -+static inline u32 brcmnand_soc_read(struct brcmnand_soc *soc, u32 offset) -+{ -+ return soc->ops->read_reg(soc, offset); -+} -+ -+static inline void brcmnand_soc_write(struct brcmnand_soc *soc, u32 val, -+ u32 offset) -+{ -+ soc->ops->write_reg(soc, val, offset); -+} -+ - int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc); - int brcmnand_remove(struct platform_device *pdev); - diff --git a/target/linux/bcm47xx/patches-5.10/102-v5.18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch b/target/linux/bcm47xx/patches-5.10/102-v5.18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch deleted file mode 100644 index d9324c2595..0000000000 --- a/target/linux/bcm47xx/patches-5.10/102-v5.18-mtd-rawnand-brcmnand-Avoid-pdev-in-brcmnand_init_cs.patch +++ /dev/null @@ -1,52 +0,0 @@ -From: Florian Fainelli -Subject: [PATCH v3 3/9] mtd: rawnand: brcmnand: Avoid pdev in brcmnand_init_cs() -Date: Fri, 07 Jan 2022 10:46:08 -0800 -Content-Type: text/plain; charset="utf-8" - -In preparation for encapsulating more of what the loop calling -brcmnand_init_cs() does, avoid using platform_device when it is the -device behind platform_device that we are using for printing errors. - -No functional changes introduced. - -Signed-off-by: Florian Fainelli ---- - drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -2722,7 +2722,7 @@ static const struct nand_controller_ops - static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn) - { - struct brcmnand_controller *ctrl = host->ctrl; -- struct platform_device *pdev = host->pdev; -+ struct device *dev = ctrl->dev; - struct mtd_info *mtd; - struct nand_chip *chip; - int ret; -@@ -2730,7 +2730,7 @@ static int brcmnand_init_cs(struct brcmn - - ret = of_property_read_u32(dn, "reg", &host->cs); - if (ret) { -- dev_err(&pdev->dev, "can't get chip-select\n"); -+ dev_err(dev, "can't get chip-select\n"); - return -ENXIO; - } - -@@ -2739,13 +2739,13 @@ static int brcmnand_init_cs(struct brcmn - - nand_set_flash_node(chip, dn); - nand_set_controller_data(chip, host); -- mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d", -+ mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d", - host->cs); - if (!mtd->name) - return -ENOMEM; - - mtd->owner = THIS_MODULE; -- mtd->dev.parent = &pdev->dev; -+ mtd->dev.parent = dev; - - chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl; - chip->legacy.cmdfunc = brcmnand_cmdfunc; diff --git a/target/linux/bcm47xx/patches-5.10/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch b/target/linux/bcm47xx/patches-5.10/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch deleted file mode 100644 index 34fd1b47ea..0000000000 --- a/target/linux/bcm47xx/patches-5.10/103-v5.18-mtd-rawnand-brcmnand-Move-OF-operations-out-of-brcmnand_init_cs.patch +++ /dev/null @@ -1,63 +0,0 @@ -From: Florian Fainelli -Subject: [PATCH v3 4/9] mtd: rawnand: brcmnand: Move OF operations out of brcmnand_init_cs() -Date: Fri, 07 Jan 2022 10:46:09 -0800 -Content-Type: text/plain; charset="utf-8" - -In order to initialize a given chip select object for use by the -brcmnand driver, move all of the Device Tree specific routines outside -of brcmnand_init_cs() in order to make it usable in a platform data -configuration which will be necessary for supporting BCMA chips. - -No functional changes introduced. - -Signed-off-by: Florian Fainelli ---- - drivers/mtd/nand/raw/brcmnand/brcmnand.c | 20 +++++++++++--------- - 1 file changed, 11 insertions(+), 9 deletions(-) - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -2719,7 +2719,7 @@ static const struct nand_controller_ops - .attach_chip = brcmnand_attach_chip, - }; - --static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn) -+static int brcmnand_init_cs(struct brcmnand_host *host) - { - struct brcmnand_controller *ctrl = host->ctrl; - struct device *dev = ctrl->dev; -@@ -2728,16 +2728,9 @@ static int brcmnand_init_cs(struct brcmn - int ret; - u16 cfg_offs; - -- ret = of_property_read_u32(dn, "reg", &host->cs); -- if (ret) { -- dev_err(dev, "can't get chip-select\n"); -- return -ENXIO; -- } -- - mtd = nand_to_mtd(&host->chip); - chip = &host->chip; - -- nand_set_flash_node(chip, dn); - nand_set_controller_data(chip, host); - mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d", - host->cs); -@@ -3144,7 +3137,16 @@ int brcmnand_probe(struct platform_devic - host->pdev = pdev; - host->ctrl = ctrl; - -- ret = brcmnand_init_cs(host, child); -+ ret = of_property_read_u32(child, "reg", &host->cs); -+ if (ret) { -+ dev_err(dev, "can't get chip-select\n"); -+ devm_kfree(dev, host); -+ continue; -+ } -+ -+ nand_set_flash_node(&host->chip, child); -+ -+ ret = brcmnand_init_cs(host); - if (ret) { - devm_kfree(dev, host); - continue; /* Try all chip-selects */ diff --git a/target/linux/bcm47xx/patches-5.10/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch b/target/linux/bcm47xx/patches-5.10/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch deleted file mode 100644 index 3a9d18fa21..0000000000 --- a/target/linux/bcm47xx/patches-5.10/104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch +++ /dev/null @@ -1,91 +0,0 @@ -From: Florian Fainelli -Subject: [PATCH v3 5/9] mtd: rawnand: brcmnand: Allow working without interrupts -Date: Fri, 07 Jan 2022 10:46:10 -0800 -Content-Type: text/plain; charset="utf-8" - -The BCMA devices include the brcmnand controller but they do not wire up -any interrupt line, allow the main interrupt to be optional and update -the completion path to also check for the lack of an interrupt line. - -Signed-off-by: Florian Fainelli ---- - drivers/mtd/nand/raw/brcmnand/brcmnand.c | 52 +++++++++++------------- - 1 file changed, 24 insertions(+), 28 deletions(-) - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -216,7 +216,7 @@ struct brcmnand_controller { - void __iomem *nand_base; - void __iomem *nand_fc; /* flash cache */ - void __iomem *flash_dma_base; -- unsigned int irq; -+ int irq; - unsigned int dma_irq; - int nand_version; - -@@ -1590,7 +1590,7 @@ static bool brcmstb_nand_wait_for_comple - bool err = false; - int sts; - -- if (mtd->oops_panic_write) { -+ if (mtd->oops_panic_write || ctrl->irq < 0) { - /* switch to interrupt polling and PIO mode */ - disable_ctrl_irqs(ctrl); - sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, -@@ -3095,33 +3095,29 @@ int brcmnand_probe(struct platform_devic - } - - /* IRQ */ -- ctrl->irq = platform_get_irq(pdev, 0); -- if ((int)ctrl->irq < 0) { -- dev_err(dev, "no IRQ defined\n"); -- ret = -ENODEV; -- goto err; -- } -- -- /* -- * Some SoCs integrate this controller (e.g., its interrupt bits) in -- * interesting ways -- */ -- if (soc) { -- ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, -- DRV_NAME, ctrl); -- -- /* Enable interrupt */ -- ctrl->soc->ctlrdy_ack(ctrl->soc); -- ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); -- } else { -- /* Use standard interrupt infrastructure */ -- ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, -- DRV_NAME, ctrl); -- } -- if (ret < 0) { -- dev_err(dev, "can't allocate IRQ %d: error %d\n", -- ctrl->irq, ret); -- goto err; -+ ctrl->irq = platform_get_irq_optional(pdev, 0); -+ if (ctrl->irq > 0) { -+ /* -+ * Some SoCs integrate this controller (e.g., its interrupt bits) in -+ * interesting ways -+ */ -+ if (soc) { -+ ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, -+ DRV_NAME, ctrl); -+ -+ /* Enable interrupt */ -+ ctrl->soc->ctlrdy_ack(ctrl->soc); -+ ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); -+ } else { -+ /* Use standard interrupt infrastructure */ -+ ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, -+ DRV_NAME, ctrl); -+ } -+ if (ret < 0) { -+ dev_err(dev, "can't allocate IRQ %d: error %d\n", -+ ctrl->irq, ret); -+ goto err; -+ } - } - - for_each_available_child_of_node(dn, child) { diff --git a/target/linux/bcm47xx/patches-5.10/105-v5.18-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch b/target/linux/bcm47xx/patches-5.10/105-v5.18-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch deleted file mode 100644 index 973a3e95ee..0000000000 --- a/target/linux/bcm47xx/patches-5.10/105-v5.18-mtd-rawnand-brcmnand-Add-platform-data-structure-for-BCMA.patch +++ /dev/null @@ -1,115 +0,0 @@ -From: Florian Fainelli -Subject: [PATCH v3 6/9] mtd: rawnand: brcmnand: Add platform data structure for BCMA -Date: Fri, 07 Jan 2022 10:46:11 -0800 -Content-Type: text/plain; charset="utf-8" - -Update the BCMA's chipcommon nand flash driver to detect which -chip-select is used and pass that information via platform data to the -brcmnand driver. Make sure that the brcmnand platform data structure is -always at the beginning of the platform data of the "nflash" device -created by BCMA to allow brcmnand to safely de-reference it. - -Signed-off-by: Florian Fainelli ---- - MAINTAINERS | 1 + - drivers/bcma/driver_chipcommon_nflash.c | 20 +++++++++++++++++++- - include/linux/bcma/bcma_driver_chipcommon.h | 5 +++++ - include/linux/platform_data/brcmnand.h | 12 ++++++++++++ - 4 files changed, 37 insertions(+), 1 deletion(-) - create mode 100644 include/linux/platform_data/brcmnand.h - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3712,6 +3712,7 @@ L: linux-mtd@lists.infradead.org - L: bcm-kernel-feedback-list@broadcom.com - S: Maintained - F: drivers/mtd/nand/raw/brcmnand/ -+F: include/linux/platform_data/brcmnand.h - - BROADCOM SYSTEMPORT ETHERNET DRIVER - M: Florian Fainelli ---- a/drivers/bcma/driver_chipcommon_nflash.c -+++ b/drivers/bcma/driver_chipcommon_nflash.c -@@ -7,18 +7,28 @@ - - #include "bcma_private.h" - -+#include - #include -+#include - #include - -+/* Alternate NAND controller driver name in order to allow both bcm47xxnflash -+ * and bcma_brcmnand to be built into the same kernel image. -+ */ -+static const char *bcma_nflash_alt_name = "bcma_brcmnand"; -+ - struct platform_device bcma_nflash_dev = { - .name = "bcma_nflash", - .num_resources = 0, - }; - -+static const char *probes[] = { "bcm47xxpart", NULL }; -+ - /* Initialize NAND flash access */ - int bcma_nflash_init(struct bcma_drv_cc *cc) - { - struct bcma_bus *bus = cc->core->bus; -+ u32 reg; - - if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 && - cc->core->id.rev != 38) { -@@ -33,8 +43,16 @@ int bcma_nflash_init(struct bcma_drv_cc - - cc->nflash.present = true; - if (cc->core->id.rev == 38 && -- (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) -+ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) { - cc->nflash.boot = true; -+ /* Determine the chip select that is being used */ -+ reg = bcma_cc_read32(cc, BCMA_CC_NAND_CS_NAND_SELECT) & 0xff; -+ cc->nflash.brcmnand_info.chip_select = ffs(reg) - 1; -+ cc->nflash.brcmnand_info.part_probe_types = probes; -+ cc->nflash.brcmnand_info.ecc_stepsize = 512; -+ cc->nflash.brcmnand_info.ecc_strength = 1; -+ bcma_nflash_dev.name = bcma_nflash_alt_name; -+ } - - /* Prepare platform device, but don't register it yet. It's too early, - * malloc (required by device_private_init) is not available yet. */ ---- a/include/linux/bcma/bcma_driver_chipcommon.h -+++ b/include/linux/bcma/bcma_driver_chipcommon.h -@@ -3,6 +3,7 @@ - #define LINUX_BCMA_DRIVER_CC_H_ - - #include -+#include - #include - - /** ChipCommon core registers. **/ -@@ -599,6 +600,10 @@ struct bcma_sflash { - - #ifdef CONFIG_BCMA_NFLASH - struct bcma_nflash { -+ /* Must be the fist member for the brcmnand driver to -+ * de-reference that structure. -+ */ -+ struct brcmnand_platform_data brcmnand_info; - bool present; - bool boot; /* This is the flash the SoC boots from */ - }; ---- /dev/null -+++ b/include/linux/platform_data/brcmnand.h -@@ -0,0 +1,12 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+#ifndef BRCMNAND_PLAT_DATA_H -+#define BRCMNAND_PLAT_DATA_H -+ -+struct brcmnand_platform_data { -+ int chip_select; -+ const char * const *part_probe_types; -+ unsigned int ecc_stepsize; -+ unsigned int ecc_strength; -+}; -+ -+#endif /* BRCMNAND_PLAT_DATA_H */ diff --git a/target/linux/bcm47xx/patches-5.10/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch b/target/linux/bcm47xx/patches-5.10/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch deleted file mode 100644 index fb9ee07d04..0000000000 --- a/target/linux/bcm47xx/patches-5.10/106-v5.18-mtd-rawnand-brcmnand-Allow-platform-data-instantation.patch +++ /dev/null @@ -1,124 +0,0 @@ -From: Florian Fainelli -Subject: [PATCH v3 7/9] mtd: rawnand: brcmnand: Allow platform data instantation -Date: Fri, 07 Jan 2022 10:46:12 -0800 -Content-Type: text/plain; charset="utf-8" - -Make use of the recently refactored code in brcmnand_init_cs() and -derive the chip-select from the platform data that is supplied. Update -the various code paths to avoid relying on possibly non-existent -resources, too. - -Signed-off-by: Florian Fainelli ---- - drivers/mtd/nand/raw/brcmnand/brcmnand.c | 45 ++++++++++++++++++------ - 1 file changed, 35 insertions(+), 10 deletions(-) - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -2719,7 +2720,8 @@ static const struct nand_controller_ops - .attach_chip = brcmnand_attach_chip, - }; - --static int brcmnand_init_cs(struct brcmnand_host *host) -+static int brcmnand_init_cs(struct brcmnand_host *host, -+ const char * const *part_probe_types) - { - struct brcmnand_controller *ctrl = host->ctrl; - struct device *dev = ctrl->dev; -@@ -2772,7 +2774,7 @@ static int brcmnand_init_cs(struct brcmn - if (ret) - return ret; - -- ret = mtd_device_register(mtd, NULL, 0); -+ ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0); - if (ret) - nand_cleanup(chip); - -@@ -2941,17 +2943,15 @@ static int brcmnand_edu_setup(struct pla - - int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) - { -+ struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev); - struct device *dev = &pdev->dev; - struct device_node *dn = dev->of_node, *child; - struct brcmnand_controller *ctrl; -+ struct brcmnand_host *host; - struct resource *res; - int ret; - -- /* We only support device-tree instantiation */ -- if (!dn) -- return -ENODEV; -- -- if (!of_match_node(brcmnand_of_match, dn)) -+ if (dn && !of_match_node(brcmnand_of_match, dn)) - return -ENODEV; - - ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); -@@ -2978,7 +2978,7 @@ int brcmnand_probe(struct platform_devic - /* NAND register range */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ctrl->nand_base = devm_ioremap_resource(dev, res); -- if (IS_ERR(ctrl->nand_base)) -+ if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc)) - return PTR_ERR(ctrl->nand_base); - - /* Enable clock before using NAND registers */ -@@ -3122,7 +3122,6 @@ int brcmnand_probe(struct platform_devic - - for_each_available_child_of_node(dn, child) { - if (of_device_is_compatible(child, "brcm,nandcs")) { -- struct brcmnand_host *host; - - host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); - if (!host) { -@@ -3142,7 +3141,7 @@ int brcmnand_probe(struct platform_devic - - nand_set_flash_node(&host->chip, child); - -- ret = brcmnand_init_cs(host); -+ ret = brcmnand_init_cs(host, NULL); - if (ret) { - devm_kfree(dev, host); - continue; /* Try all chip-selects */ -@@ -3152,6 +3151,32 @@ int brcmnand_probe(struct platform_devic - } - } - -+ if (!list_empty(&ctrl->host_list)) -+ return 0; -+ -+ if (!pd) { -+ ret = -ENODEV; -+ goto err; -+ } -+ -+ /* If we got there we must have been probing via platform data */ -+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); -+ if (!host) { -+ ret = -ENOMEM; -+ goto err; -+ } -+ host->pdev = pdev; -+ host->ctrl = ctrl; -+ host->cs = pd->chip_select; -+ host->chip.ecc.size = pd->ecc_stepsize; -+ host->chip.ecc.strength = pd->ecc_strength; -+ -+ ret = brcmnand_init_cs(host, pd->part_probe_types); -+ if (ret) -+ goto err; -+ -+ list_add_tail(&host->node, &ctrl->host_list); -+ - /* No chip-selects could initialize properly */ - if (list_empty(&ctrl->host_list)) { - ret = -ENODEV; diff --git a/target/linux/bcm47xx/patches-5.10/107-v5.18-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch b/target/linux/bcm47xx/patches-5.10/107-v5.18-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch deleted file mode 100644 index 39f34aab29..0000000000 --- a/target/linux/bcm47xx/patches-5.10/107-v5.18-mtd-rawnand-brcmnand-BCMA-controller-uses-command-shift-of-0.patch +++ /dev/null @@ -1,29 +0,0 @@ -From: Florian Fainelli -Subject: [PATCH v3 8/9] mtd: rawnand: brcmnand: BCMA controller uses command shift of 0 -Date: Fri, 07 Jan 2022 10:46:13 -0800 -Content-Type: text/plain; charset="utf-8" - -For some odd and unexplained reason the BCMA NAND controller, albeit -revision 3.4 uses a command shift of 0 instead of 24 as it should be, -quirk that. - -Signed-off-by: Florian Fainelli ---- - drivers/mtd/nand/raw/brcmnand/brcmnand.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -913,6 +913,12 @@ static void brcmnand_wr_corr_thresh(stru - - static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) - { -+ /* Kludge for the BCMA-based NAND controller which does not actually -+ * shift the command -+ */ -+ if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl)) -+ return 0; -+ - if (ctrl->nand_version < 0x0602) - return 24; - return 0; diff --git a/target/linux/bcm47xx/patches-5.10/108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch b/target/linux/bcm47xx/patches-5.10/108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch deleted file mode 100644 index eabb4c2475..0000000000 --- a/target/linux/bcm47xx/patches-5.10/108-v5.18-mtd-rawnand-brcmnand-Add-BCMA-shim.patch +++ /dev/null @@ -1,201 +0,0 @@ -From: Florian Fainelli -Subject: [PATCH v3 9/9] mtd: rawnand: brcmnand: Add BCMA shim -Date: Fri, 07 Jan 2022 10:46:14 -0800 -Content-Type: text/plain; charset="utf-8" - -Add a BCMA shim to allow us to register the brcmnand driver using the -BCMA bus which provides indirect memory mapped access to SoC registers. - -There are a number of registers that need to be byte swapped because -they are natively big endian, coming directly from the NAND chip, and -there is no bus interface unlike the iProc or STB platforms that -performs the byte swapping for us. - -Signed-off-by: Florian Fainelli ---- - drivers/mtd/nand/raw/Kconfig | 13 +++ - drivers/mtd/nand/raw/brcmnand/Makefile | 2 + - drivers/mtd/nand/raw/brcmnand/bcma_nand.c | 132 ++++++++++++++++++++++ - drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 + - 4 files changed, 151 insertions(+) - create mode 100644 drivers/mtd/nand/raw/brcmnand/bcma_nand.c - ---- a/drivers/mtd/nand/raw/Kconfig -+++ b/drivers/mtd/nand/raw/Kconfig -@@ -236,6 +236,19 @@ config MTD_NAND_BRCMNAND - originally designed for Set-Top Box but is used on various BCM7xxx, - BCM3xxx, BCM63xxx, iProc/Cygnus and more. - -+if MTD_NAND_BRCMNAND -+ -+config MTD_NAND_BRCMNAND_BCMA -+ tristate "Broadcom BCMA NAND controller" -+ depends on BCMA_NFLASH -+ depends on BCMA -+ help -+ Enables the BRCMNAND controller over BCMA on BCM47186/BCM5358 SoCs. -+ The glue driver will take care of performing the low-level I/O -+ operations to interface the BRCMNAND controller over the BCMA bus. -+ -+endif # MTD_NAND_BRCMNAND -+ - config MTD_NAND_BCM47XXNFLASH - tristate "BCM4706 BCMA NAND controller" - depends on BCMA_NFLASH ---- a/drivers/mtd/nand/raw/brcmnand/Makefile -+++ b/drivers/mtd/nand/raw/brcmnand/Makefile -@@ -6,3 +6,5 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm6 - obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm6368_nand.o - obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmstb_nand.o - obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o -+ -+obj-$(CONFIG_MTD_NAND_BRCMNAND_BCMA) += bcma_nand.o ---- /dev/null -+++ b/drivers/mtd/nand/raw/brcmnand/bcma_nand.c -@@ -0,0 +1,132 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright © 2021 Broadcom -+ */ -+#include -+#include -+#include -+#include -+#include -+ -+#include "brcmnand.h" -+ -+struct brcmnand_bcma_soc { -+ struct brcmnand_soc soc; -+ struct bcma_drv_cc *cc; -+}; -+ -+static inline bool brcmnand_bcma_needs_swapping(u32 offset) -+{ -+ switch (offset) { -+ case BCMA_CC_NAND_SPARE_RD0: -+ case BCMA_CC_NAND_SPARE_RD4: -+ case BCMA_CC_NAND_SPARE_RD8: -+ case BCMA_CC_NAND_SPARE_RD12: -+ case BCMA_CC_NAND_SPARE_WR0: -+ case BCMA_CC_NAND_SPARE_WR4: -+ case BCMA_CC_NAND_SPARE_WR8: -+ case BCMA_CC_NAND_SPARE_WR12: -+ case BCMA_CC_NAND_DEVID: -+ case BCMA_CC_NAND_DEVID_X: -+ case BCMA_CC_NAND_SPARE_RD16: -+ case BCMA_CC_NAND_SPARE_RD20: -+ case BCMA_CC_NAND_SPARE_RD24: -+ case BCMA_CC_NAND_SPARE_RD28: -+ return true; -+ } -+ -+ return false; -+} -+ -+static inline struct brcmnand_bcma_soc *to_bcma_soc(struct brcmnand_soc *soc) -+{ -+ return container_of(soc, struct brcmnand_bcma_soc, soc); -+} -+ -+static u32 brcmnand_bcma_read_reg(struct brcmnand_soc *soc, u32 offset) -+{ -+ struct brcmnand_bcma_soc *sc = to_bcma_soc(soc); -+ u32 val; -+ -+ /* Offset into the NAND block and deal with the flash cache separately */ -+ if (offset == BRCMNAND_NON_MMIO_FC_ADDR) -+ offset = BCMA_CC_NAND_CACHE_DATA; -+ else -+ offset += BCMA_CC_NAND_REVISION; -+ -+ val = bcma_cc_read32(sc->cc, offset); -+ -+ /* Swap if necessary */ -+ if (brcmnand_bcma_needs_swapping(offset)) -+ val = be32_to_cpu(val); -+ return val; -+} -+ -+static void brcmnand_bcma_write_reg(struct brcmnand_soc *soc, u32 val, -+ u32 offset) -+{ -+ struct brcmnand_bcma_soc *sc = to_bcma_soc(soc); -+ -+ /* Offset into the NAND block */ -+ if (offset == BRCMNAND_NON_MMIO_FC_ADDR) -+ offset = BCMA_CC_NAND_CACHE_DATA; -+ else -+ offset += BCMA_CC_NAND_REVISION; -+ -+ /* Swap if necessary */ -+ if (brcmnand_bcma_needs_swapping(offset)) -+ val = cpu_to_be32(val); -+ -+ bcma_cc_write32(sc->cc, offset, val); -+} -+ -+static struct brcmnand_io_ops brcmnand_bcma_io_ops = { -+ .read_reg = brcmnand_bcma_read_reg, -+ .write_reg = brcmnand_bcma_write_reg, -+}; -+ -+static void brcmnand_bcma_prepare_data_bus(struct brcmnand_soc *soc, bool prepare, -+ bool is_param) -+{ -+ struct brcmnand_bcma_soc *sc = to_bcma_soc(soc); -+ -+ /* Reset the cache address to ensure we are already accessing the -+ * beginning of a sub-page. -+ */ -+ bcma_cc_write32(sc->cc, BCMA_CC_NAND_CACHE_ADDR, 0); -+} -+ -+static int brcmnand_bcma_nand_probe(struct platform_device *pdev) -+{ -+ struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev); -+ struct brcmnand_bcma_soc *soc; -+ -+ soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL); -+ if (!soc) -+ return -ENOMEM; -+ -+ soc->cc = container_of(nflash, struct bcma_drv_cc, nflash); -+ soc->soc.prepare_data_bus = brcmnand_bcma_prepare_data_bus; -+ soc->soc.ops = &brcmnand_bcma_io_ops; -+ -+ if (soc->cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { -+ dev_err(&pdev->dev, "Use bcm47xxnflash for 4706!\n"); -+ return -ENODEV; -+ } -+ -+ return brcmnand_probe(pdev, &soc->soc); -+} -+ -+static struct platform_driver brcmnand_bcma_nand_driver = { -+ .probe = brcmnand_bcma_nand_probe, -+ .remove = brcmnand_remove, -+ .driver = { -+ .name = "bcma_brcmnand", -+ .pm = &brcmnand_pm_ops, -+ } -+}; -+module_platform_driver(brcmnand_bcma_nand_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Broadcom"); -+MODULE_DESCRIPTION("NAND controller driver glue for BCMA chips"); ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -595,7 +595,11 @@ enum { - - static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl) - { -+#if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA) - return static_branch_unlikely(&brcmnand_soc_has_ops_key); -+#else -+ return false; -+#endif - } - - static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) diff --git a/target/linux/bcm47xx/patches-5.10/130-MIPS-BCM47XX-Add-support-for-Huawei-B593u-12.patch b/target/linux/bcm47xx/patches-5.10/130-MIPS-BCM47XX-Add-support-for-Huawei-B593u-12.patch deleted file mode 100644 index 333c3d7b87..0000000000 --- a/target/linux/bcm47xx/patches-5.10/130-MIPS-BCM47XX-Add-support-for-Huawei-B593u-12.patch +++ /dev/null @@ -1,61 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 27 Feb 2023 07:44:38 +0100 -Subject: [PATCH] MIPS: BCM47XX: Add support for Huawei B593u-12 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's a BCM5358 based home router. One of very few bcm47xx devices with -cellular modems (here: LTE). - -Signed-off-by: Rafał Miłecki ---- - arch/mips/bcm47xx/board.c | 1 + - arch/mips/bcm47xx/leds.c | 8 ++++++++ - arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + - 3 files changed, 10 insertions(+) - ---- a/arch/mips/bcm47xx/board.c -+++ b/arch/mips/bcm47xx/board.c -@@ -193,6 +193,7 @@ struct bcm47xx_board_type_list1 bcm47xx_ - /* boardtype, boardnum, boardrev */ - static const - struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = { -+ {{BCM47XX_BOARD_HUAWEI_B593U_12, "Huawei B593u-12"}, "0x053d", "1234", "0x1301"}, - {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"}, - {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, - {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, ---- a/arch/mips/bcm47xx/leds.c -+++ b/arch/mips/bcm47xx/leds.c -@@ -223,6 +223,11 @@ bcm47xx_leds_dlink_dir330[] __initconst - /* Huawei */ - - static const struct gpio_led -+bcm47xx_leds_huawei_b593u_12[] __initconst = { -+ BCM47XX_GPIO_LED(5, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), -+}; -+ -+static const struct gpio_led - bcm47xx_leds_huawei_e970[] __initconst = { - BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), - }; -@@ -672,6 +677,9 @@ void __init bcm47xx_leds_register(void) - bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330); - break; - -+ case BCM47XX_BOARD_HUAWEI_B593U_12: -+ bcm47xx_set_pdata(bcm47xx_leds_huawei_b593u_12); -+ break; - case BCM47XX_BOARD_HUAWEI_E970: - bcm47xx_set_pdata(bcm47xx_leds_huawei_e970); - break; ---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h -@@ -53,6 +53,7 @@ enum bcm47xx_board { - BCM47XX_BOARD_DLINK_DIR130, - BCM47XX_BOARD_DLINK_DIR330, - -+ BCM47XX_BOARD_HUAWEI_B593U_12, - BCM47XX_BOARD_HUAWEI_E970, - - BCM47XX_BOARD_LINKSYS_E900V1, diff --git a/target/linux/bcm47xx/patches-5.10/159-cpu_fixes.patch b/target/linux/bcm47xx/patches-5.10/159-cpu_fixes.patch deleted file mode 100644 index eb4c0e6ac8..0000000000 --- a/target/linux/bcm47xx/patches-5.10/159-cpu_fixes.patch +++ /dev/null @@ -1,493 +0,0 @@ ---- a/arch/mips/include/asm/r4kcache.h -+++ b/arch/mips/include/asm/r4kcache.h -@@ -28,6 +28,38 @@ - extern void (*r4k_blast_dcache)(void); - extern void (*r4k_blast_icache)(void); - -+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2) -+#include -+#include -+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg() -+ -+static inline unsigned long bcm4710_dummy_rreg(void) -+{ -+ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE)); -+} -+ -+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr)) -+ -+static inline unsigned long bcm4710_fill_tlb(void *addr) -+{ -+ return *(unsigned long *)addr; -+} -+ -+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr)) -+ -+static inline void bcm4710_protected_fill_tlb(void *addr) -+{ -+ unsigned long x; -+ get_dbe(x, (unsigned long *)addr);; -+} -+ -+#else -+#define BCM4710_DUMMY_RREG() -+ -+#define BCM4710_FILL_TLB(addr) -+#define BCM4710_PROTECTED_FILL_TLB(addr) -+#endif -+ - /* - * This macro return a properly sign-extended address suitable as base address - * for indexed cache operations. Two issues here: -@@ -61,6 +93,7 @@ static inline void flush_icache_line_ind - - static inline void flush_dcache_line_indexed(unsigned long addr) - { -+ BCM4710_DUMMY_RREG(); - cache_op(Index_Writeback_Inv_D, addr); - } - -@@ -84,11 +117,13 @@ static inline void flush_icache_line(uns - - static inline void flush_dcache_line(unsigned long addr) - { -+ BCM4710_DUMMY_RREG(); - cache_op(Hit_Writeback_Inv_D, addr); - } - - static inline void invalidate_dcache_line(unsigned long addr) - { -+ BCM4710_DUMMY_RREG(); - cache_op(Hit_Invalidate_D, addr); - } - -@@ -161,6 +196,7 @@ static inline int protected_flush_icache - #ifdef CONFIG_EVA - return protected_cachee_op(Hit_Invalidate_I, addr); - #else -+ BCM4710_DUMMY_RREG(); - return protected_cache_op(Hit_Invalidate_I, addr); - #endif - } -@@ -174,6 +210,7 @@ static inline int protected_flush_icache - */ - static inline int protected_writeback_dcache_line(unsigned long addr) - { -+ BCM4710_DUMMY_RREG(); - #ifdef CONFIG_EVA - return protected_cachee_op(Hit_Writeback_Inv_D, addr); - #else -@@ -203,8 +240,51 @@ static inline void invalidate_tcache_pag - unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \ - } while (0) - -+static inline void blast_dcache(void) -+{ -+ unsigned long start = KSEG0; -+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways; -+ unsigned long end = (start + dcache_size); -+ -+ do { -+ BCM4710_DUMMY_RREG(); -+ cache_op(Index_Writeback_Inv_D, start); -+ start += current_cpu_data.dcache.linesz; -+ } while(start < end); -+} -+ -+static inline void blast_dcache_page(unsigned long page) -+{ -+ unsigned long start = page; -+ unsigned long end = start + PAGE_SIZE; -+ -+ BCM4710_FILL_TLB(start); -+ do { -+ BCM4710_DUMMY_RREG(); -+ cache_op(Hit_Writeback_Inv_D, start); -+ start += current_cpu_data.dcache.linesz; -+ } while(start < end); -+} -+ -+static inline void blast_dcache_page_indexed(unsigned long page) -+{ -+ unsigned long start = page; -+ unsigned long end = start + PAGE_SIZE; -+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; -+ unsigned long ws_end = current_cpu_data.dcache.ways << -+ current_cpu_data.dcache.waybit; -+ unsigned long ws, addr; -+ for (ws = 0; ws < ws_end; ws += ws_inc) { -+ start = page + ws; -+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) { -+ BCM4710_DUMMY_RREG(); -+ cache_op(Index_Writeback_Inv_D, addr); -+ } -+ } -+} -+ - /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ --#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \ -+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \ - static inline void extra##blast_##pfx##cache##lsize(void) \ - { \ - unsigned long start = INDEX_BASE; \ -@@ -214,6 +294,7 @@ static inline void extra##blast_##pfx##c - current_cpu_data.desc.waybit; \ - unsigned long ws, addr; \ - \ -+ war \ - for (ws = 0; ws < ws_end; ws += ws_inc) \ - for (addr = start; addr < end; addr += lsize * 32) \ - cache_unroll(32, kernel_cache, indexop, \ -@@ -225,6 +306,7 @@ static inline void extra##blast_##pfx##c - unsigned long start = page; \ - unsigned long end = page + PAGE_SIZE; \ - \ -+ war \ - do { \ - cache_unroll(32, kernel_cache, hitop, start, lsize); \ - start += lsize * 32; \ -@@ -241,32 +323,33 @@ static inline void extra##blast_##pfx##c - current_cpu_data.desc.waybit; \ - unsigned long ws, addr; \ - \ -+ war \ - for (ws = 0; ws < ws_end; ws += ws_inc) \ - for (addr = start; addr < end; addr += lsize * 32) \ - cache_unroll(32, kernel_cache, indexop, \ - addr | ws, lsize); \ - } - --__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) --__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, ) --__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, ) --__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) --__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, ) --__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_) --__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, ) --__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, ) --__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, ) --__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, ) --__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, ) --__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, ) --__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, ) -- --__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, ) --__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, ) --__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, ) --__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, ) --__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, ) --__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, ) -+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , ) -+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);) -+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , ) -+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , ) -+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);) -+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);) -+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , ) -+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , ) -+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);) -+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , ) -+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , ) -+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , ) -+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , ) -+ -+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , ) -+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , ) -+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , ) -+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , ) -+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , ) -+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , ) - - #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \ - static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ -@@ -291,58 +374,29 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde - __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) - - /* build blast_xxx_range, protected_blast_xxx_range */ --#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ -+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \ - static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ - unsigned long end) \ - { \ - unsigned long lsize = cpu_##desc##_line_size(); \ -- unsigned long lsize_2 = lsize * 2; \ -- unsigned long lsize_3 = lsize * 3; \ -- unsigned long lsize_4 = lsize * 4; \ -- unsigned long lsize_5 = lsize * 5; \ -- unsigned long lsize_6 = lsize * 6; \ -- unsigned long lsize_7 = lsize * 7; \ -- unsigned long lsize_8 = lsize * 8; \ - unsigned long addr = start & ~(lsize - 1); \ -- unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \ -- int lines = (aend - addr) / lsize; \ -- \ -- while (lines >= 8) { \ -- prot##cache_op(hitop, addr); \ -- prot##cache_op(hitop, addr + lsize); \ -- prot##cache_op(hitop, addr + lsize_2); \ -- prot##cache_op(hitop, addr + lsize_3); \ -- prot##cache_op(hitop, addr + lsize_4); \ -- prot##cache_op(hitop, addr + lsize_5); \ -- prot##cache_op(hitop, addr + lsize_6); \ -- prot##cache_op(hitop, addr + lsize_7); \ -- addr += lsize_8; \ -- lines -= 8; \ -- } \ -- \ -- if (lines & 0x4) { \ -- prot##cache_op(hitop, addr); \ -- prot##cache_op(hitop, addr + lsize); \ -- prot##cache_op(hitop, addr + lsize_2); \ -- prot##cache_op(hitop, addr + lsize_3); \ -- addr += lsize_4; \ -- } \ -+ unsigned long aend = (end - 1) & ~(lsize - 1); \ - \ -- if (lines & 0x2) { \ -- prot##cache_op(hitop, addr); \ -- prot##cache_op(hitop, addr + lsize); \ -- addr += lsize_2; \ -- } \ -+ war \ - \ -- if (lines & 0x1) { \ -+ while (1) { \ -+ war2 \ - prot##cache_op(hitop, addr); \ -+ if (addr == aend) \ -+ break; \ -+ addr += lsize; \ - } \ - } - - #ifndef CONFIG_EVA - --__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) --__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) -+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) -+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , ) - - #else - -@@ -376,15 +430,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache - __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I) - - #endif --__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, ) -+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , ) - __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ -- protected_, loongson2_) --__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) --__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , ) --__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , ) -+ protected_, loongson2_, , ) -+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) -+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , ) -+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , ) - /* blast_inv_dcache_range */ --__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) --__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , ) -+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();) -+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , ) - - /* Currently, this is very specific to Loongson-3 */ - #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \ ---- a/arch/mips/include/asm/stackframe.h -+++ b/arch/mips/include/asm/stackframe.h -@@ -429,6 +429,10 @@ - #else - .set push - .set arch=r4000 -+#ifdef CONFIG_BCM47XX -+ nop -+ nop -+#endif - eret - .set pop - #endif ---- a/arch/mips/kernel/genex.S -+++ b/arch/mips/kernel/genex.S -@@ -22,6 +22,19 @@ - #include - #include - -+#ifdef CONFIG_BCM47XX -+# ifdef eret -+# undef eret -+# endif -+# define eret \ -+ .set push; \ -+ .set noreorder; \ -+ nop; \ -+ nop; \ -+ eret; \ -+ .set pop; -+#endif -+ - __INIT - - /* -@@ -33,6 +46,9 @@ - NESTED(except_vec3_generic, 0, sp) - .set push - .set noat -+#ifdef CONFIG_BCM47XX -+ nop -+#endif - mfc0 k1, CP0_CAUSE - andi k1, k1, 0x7c - #ifdef CONFIG_64BIT -@@ -53,6 +69,9 @@ NESTED(except_vec3_r4000, 0, sp) - .set push - .set arch=r4000 - .set noat -+#ifdef CONFIG_BCM47XX -+ nop -+#endif - mfc0 k1, CP0_CAUSE - li k0, 31<<2 - andi k1, k1, 0x7c ---- a/arch/mips/mm/c-r4k.c -+++ b/arch/mips/mm/c-r4k.c -@@ -38,6 +38,9 @@ - #include - #include - -+/* For enabling BCM4710 cache workarounds */ -+static int bcm4710 = 0; -+ - /* - * Bits describing what cache ops an SMP callback function may perform. - * -@@ -190,6 +193,9 @@ static void r4k_blast_dcache_user_page_s - { - unsigned long dc_lsize = cpu_dcache_line_size(); - -+ if (bcm4710) -+ r4k_blast_dcache_page = blast_dcache_page; -+ else - if (dc_lsize == 0) - r4k_blast_dcache_user_page = (void *)cache_noop; - else if (dc_lsize == 16) -@@ -208,6 +214,9 @@ static void r4k_blast_dcache_page_indexe - { - unsigned long dc_lsize = cpu_dcache_line_size(); - -+ if (bcm4710) -+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed; -+ else - if (dc_lsize == 0) - r4k_blast_dcache_page_indexed = (void *)cache_noop; - else if (dc_lsize == 16) -@@ -227,6 +236,9 @@ static void r4k_blast_dcache_setup(void) - { - unsigned long dc_lsize = cpu_dcache_line_size(); - -+ if (bcm4710) -+ r4k_blast_dcache = blast_dcache; -+ else - if (dc_lsize == 0) - r4k_blast_dcache = (void *)cache_noop; - else if (dc_lsize == 16) -@@ -1827,6 +1839,17 @@ static void coherency_setup(void) - * silly idea of putting something else there ... - */ - switch (current_cpu_type()) { -+ case CPU_BMIPS3300: -+ { -+ u32 cm; -+ cm = read_c0_diag(); -+ /* Enable icache */ -+ cm |= (1 << 31); -+ /* Enable dcache */ -+ cm |= (1 << 30); -+ write_c0_diag(cm); -+ } -+ break; - case CPU_R4000PC: - case CPU_R4000SC: - case CPU_R4000MC: -@@ -1873,6 +1896,15 @@ void r4k_cache_init(void) - extern void build_copy_page(void); - struct cpuinfo_mips *c = ¤t_cpu_data; - -+ /* Check if special workarounds are required */ -+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2) -+ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) { -+ printk("Enabling BCM4710A0 cache workarounds.\n"); -+ bcm4710 = 1; -+ } else -+#endif -+ bcm4710 = 0; -+ - probe_pcache(); - probe_vcache(); - setup_scache(); -@@ -1949,7 +1981,15 @@ void r4k_cache_init(void) - */ - local_r4k___flush_cache_all(NULL); - -+#ifdef CONFIG_BCM47XX -+ { -+ static void (*_coherency_setup)(void); -+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup); -+ _coherency_setup(); -+ } -+#else - coherency_setup(); -+#endif - board_cache_error_setup = r4k_cache_error_setup; - - /* ---- a/arch/mips/mm/tlbex.c -+++ b/arch/mips/mm/tlbex.c -@@ -984,6 +984,9 @@ void build_get_pgde32(u32 **p, unsigned - uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); - uasm_i_addu(p, ptr, tmp, ptr); - #else -+#ifdef CONFIG_BCM47XX -+ uasm_i_nop(p); -+#endif - UASM_i_LA_mostly(p, ptr, pgdc); - #endif - uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ -@@ -1345,6 +1348,9 @@ static void build_r4000_tlb_refill_handl - #ifdef CONFIG_64BIT - build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ - #else -+# ifdef CONFIG_BCM47XX -+ uasm_i_nop(&p); -+# endif - build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ - #endif - -@@ -1356,6 +1362,9 @@ static void build_r4000_tlb_refill_handl - build_update_entries(&p, K0, K1); - build_tlb_write_entry(&p, &l, &r, tlb_random); - uasm_l_leave(&l, p); -+#ifdef CONFIG_BCM47XX -+ uasm_i_nop(&p); -+#endif - uasm_i_eret(&p); /* return from trap */ - } - #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT -@@ -2056,6 +2065,9 @@ build_r4000_tlbchange_handler_head(u32 * - #ifdef CONFIG_64BIT - build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ - #else -+# ifdef CONFIG_BCM47XX -+ uasm_i_nop(p); -+# endif - build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ - #endif - -@@ -2102,6 +2114,9 @@ build_r4000_tlbchange_handler_tail(u32 * - build_tlb_write_entry(p, l, r, tlb_indexed); - uasm_l_leave(l, *p); - build_restore_work_registers(p); -+#ifdef CONFIG_BCM47XX -+ uasm_i_nop(p); -+#endif - uasm_i_eret(p); /* return from trap */ - - #ifdef CONFIG_64BIT diff --git a/target/linux/bcm47xx/patches-5.10/160-kmap_coherent.patch b/target/linux/bcm47xx/patches-5.10/160-kmap_coherent.patch deleted file mode 100644 index c85fa0be4c..0000000000 --- a/target/linux/bcm47xx/patches-5.10/160-kmap_coherent.patch +++ /dev/null @@ -1,78 +0,0 @@ -From: Jeff Hansen -Subject: [PATCH] kmap_coherent - -On ASUS WL-500gP there are some "Data bus error"s when executing simple -commands liks "ps" or "cat /proc/1/cmdline". - -This fixes OpenWrt ticket #1485: https://dev.openwrt.org/ticket/1485 ---- ---- a/arch/mips/include/asm/cpu-features.h -+++ b/arch/mips/include/asm/cpu-features.h -@@ -242,6 +242,9 @@ - #ifndef cpu_has_pindexed_dcache - #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) - #endif -+#ifndef cpu_use_kmap_coherent -+#define cpu_use_kmap_coherent 1 -+#endif - - /* - * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors ---- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h -+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h -@@ -80,4 +80,6 @@ - #define cpu_scache_line_size() 0 - #define cpu_has_vz 0 - -+#define cpu_use_kmap_coherent 0 -+ - #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */ ---- a/arch/mips/mm/c-r4k.c -+++ b/arch/mips/mm/c-r4k.c -@@ -702,7 +702,7 @@ static inline void local_r4k_flush_cache - map_coherent = (cpu_has_dc_aliases && - page_mapcount(page) && - !Page_dcache_dirty(page)); -- if (map_coherent) -+ if (map_coherent && cpu_use_kmap_coherent) - vaddr = kmap_coherent(page, addr); - else - vaddr = kmap_atomic(page); -@@ -729,7 +729,7 @@ static inline void local_r4k_flush_cache - } - - if (vaddr) { -- if (map_coherent) -+ if (map_coherent && cpu_use_kmap_coherent) - kunmap_coherent(); - else - kunmap_atomic(vaddr); ---- a/arch/mips/mm/init.c -+++ b/arch/mips/mm/init.c -@@ -173,7 +173,7 @@ void copy_user_highpage(struct page *to, - void *vfrom, *vto; - - vto = kmap_atomic(to); -- if (cpu_has_dc_aliases && -+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && - page_mapcount(from) && !Page_dcache_dirty(from)) { - vfrom = kmap_coherent(from, vaddr); - copy_page(vto, vfrom); -@@ -195,7 +195,7 @@ void copy_to_user_page(struct vm_area_st - struct page *page, unsigned long vaddr, void *dst, const void *src, - unsigned long len) - { -- if (cpu_has_dc_aliases && -+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && - page_mapcount(page) && !Page_dcache_dirty(page)) { - void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); - memcpy(vto, src, len); -@@ -213,7 +213,7 @@ void copy_from_user_page(struct vm_area_ - struct page *page, unsigned long vaddr, void *dst, const void *src, - unsigned long len) - { -- if (cpu_has_dc_aliases && -+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent && - page_mapcount(page) && !Page_dcache_dirty(page)) { - void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK); - memcpy(dst, vfrom, len); diff --git a/target/linux/bcm47xx/patches-5.10/209-b44-register-adm-switch.patch b/target/linux/bcm47xx/patches-5.10/209-b44-register-adm-switch.patch deleted file mode 100644 index 7728ec1094..0000000000 --- a/target/linux/bcm47xx/patches-5.10/209-b44-register-adm-switch.patch +++ /dev/null @@ -1,121 +0,0 @@ -From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sat, 9 Nov 2013 17:03:59 +0100 -Subject: [PATCH 210/210] b44: register adm switch - ---- - drivers/net/ethernet/broadcom/b44.c | 57 +++++++++++++++++++++++++++++++++++ - drivers/net/ethernet/broadcom/b44.h | 3 ++ - 2 files changed, 60 insertions(+) - ---- a/drivers/net/ethernet/broadcom/b44.c -+++ b/drivers/net/ethernet/broadcom/b44.c -@@ -31,6 +31,8 @@ - #include - #include - #include -+#include -+#include - - #include - #include -@@ -2243,6 +2245,69 @@ static void b44_adjust_link(struct net_d - } - } - -+#ifdef CONFIG_BCM47XX -+static int b44_register_adm_switch(struct b44 *bp) -+{ -+ int gpio; -+ struct platform_device *pdev; -+ struct adm6996_gpio_platform_data adm_data = {0}; -+ struct platform_device_info info = {0}; -+ -+ adm_data.model = ADM6996L; -+ gpio = bcm47xx_nvram_gpio_pin("adm_eecs"); -+ if (gpio >= 0) -+ adm_data.eecs = gpio; -+ else -+ adm_data.eecs = 2; -+ -+ gpio = bcm47xx_nvram_gpio_pin("adm_eesk"); -+ if (gpio >= 0) -+ adm_data.eesk = gpio; -+ else -+ adm_data.eesk = 3; -+ -+ gpio = bcm47xx_nvram_gpio_pin("adm_eedi"); -+ if (gpio >= 0) -+ adm_data.eedi = gpio; -+ else -+ adm_data.eedi = 4; -+ -+ /* -+ * We ignore the "adm_rc" GPIO here. The driver does not use it, -+ * and it conflicts with the Reset button GPIO on the Linksys WRT54GSv1. -+ */ -+ -+ info.parent = bp->sdev->dev; -+ info.name = "adm6996_gpio"; -+ info.id = -1; -+ info.data = &adm_data; -+ info.size_data = sizeof(adm_data); -+ -+ if (!bp->adm_switch) { -+ pdev = platform_device_register_full(&info); -+ if (IS_ERR(pdev)) -+ return PTR_ERR(pdev); -+ -+ bp->adm_switch = pdev; -+ } -+ return 0; -+} -+static void b44_unregister_adm_switch(struct b44 *bp) -+{ -+ if (bp->adm_switch) -+ platform_device_unregister(bp->adm_switch); -+} -+#else -+static int b44_register_adm_switch(struct b44 *bp) -+{ -+ return 0; -+} -+static void b44_unregister_adm_switch(struct b44 *bp) -+{ -+ -+} -+#endif /* CONFIG_BCM47XX */ -+ - static int b44_register_phy_one(struct b44 *bp) - { - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; -@@ -2279,6 +2344,9 @@ static int b44_register_phy_one(struct b - if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) && - (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) { - -+ if (sprom->boardflags_lo & B44_BOARDFLAG_ADM) -+ b44_register_adm_switch(bp); -+ - dev_info(sdev->dev, - "could not find PHY at %i, use fixed one\n", - bp->phy_addr); -@@ -2473,6 +2541,7 @@ static void b44_remove_one(struct ssb_de - unregister_netdev(dev); - if (bp->flags & B44_FLAG_EXTERNAL_PHY) - b44_unregister_phy_one(bp); -+ b44_unregister_adm_switch(bp); - ssb_device_disable(sdev, 0); - ssb_bus_may_powerdown(sdev->bus); - netif_napi_del(&bp->napi); ---- a/drivers/net/ethernet/broadcom/b44.h -+++ b/drivers/net/ethernet/broadcom/b44.h -@@ -408,6 +408,9 @@ struct b44 { - struct mii_bus *mii_bus; - int old_link; - struct mii_if_info mii_if; -+ -+ /* platform device for associated switch */ -+ struct platform_device *adm_switch; - }; - - #endif /* _B44_H */ diff --git a/target/linux/bcm47xx/patches-5.10/210-b44_phy_fix.patch b/target/linux/bcm47xx/patches-5.10/210-b44_phy_fix.patch deleted file mode 100644 index bedebc415e..0000000000 --- a/target/linux/bcm47xx/patches-5.10/210-b44_phy_fix.patch +++ /dev/null @@ -1,54 +0,0 @@ ---- a/drivers/net/ethernet/broadcom/b44.c -+++ b/drivers/net/ethernet/broadcom/b44.c -@@ -429,10 +429,34 @@ static void b44_wap54g10_workaround(stru - error: - pr_warn("PHY: cannot reset MII transceiver isolate bit\n"); - } -+ -+static void b44_bcm47xx_workarounds(struct b44 *bp) -+{ -+ char buf[20]; -+ struct ssb_device *sdev = bp->sdev; -+ -+ /* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */ -+ if (sdev->bus->sprom.board_num == 100) { -+ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY; -+ } else { -+ /* WL-HDD */ -+ if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 && -+ !strncmp(buf, "WL300-", strlen("WL300-"))) { -+ if (sdev->bus->sprom.et0phyaddr == 0 && -+ sdev->bus->sprom.et1phyaddr == 1) -+ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY; -+ } -+ } -+ return; -+} - #else - static inline void b44_wap54g10_workaround(struct b44 *bp) - { - } -+ -+static inline void b44_bcm47xx_workarounds(struct b44 *bp) -+{ -+} - #endif - - static int b44_setup_phy(struct b44 *bp) -@@ -441,6 +465,7 @@ static int b44_setup_phy(struct b44 *bp) - int err; - - b44_wap54g10_workaround(bp); -+ b44_bcm47xx_workarounds(bp); - - if (bp->flags & B44_FLAG_EXTERNAL_PHY) - return 0; -@@ -2173,6 +2198,8 @@ static int b44_get_invariants(struct b44 - * valid PHY address. */ - bp->phy_addr &= 0x1F; - -+ b44_bcm47xx_workarounds(bp); -+ - memcpy(bp->dev->dev_addr, addr, ETH_ALEN); - - if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){ diff --git a/target/linux/bcm47xx/patches-5.10/280-activate_ssb_support_in_usb.patch b/target/linux/bcm47xx/patches-5.10/280-activate_ssb_support_in_usb.patch deleted file mode 100644 index f6e9e6d30a..0000000000 --- a/target/linux/bcm47xx/patches-5.10/280-activate_ssb_support_in_usb.patch +++ /dev/null @@ -1,25 +0,0 @@ -This prevents the options from being delete with make kernel_oldconfig. ---- - drivers/ssb/Kconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/bcma/Kconfig -+++ b/drivers/bcma/Kconfig -@@ -36,6 +36,7 @@ config BCMA_HOST_PCI - config BCMA_HOST_SOC - bool "Support for BCMA in a SoC" - depends on HAS_IOMEM -+ select USB_HCD_BCMA if USB_EHCI_HCD || USB_OHCI_HCD - help - Host interface for a Broadcom AIX bus directly mapped into - the memory. This only works with the Broadcom SoCs from the ---- a/drivers/ssb/Kconfig -+++ b/drivers/ssb/Kconfig -@@ -141,6 +141,7 @@ config SSB_SFLASH - config SSB_EMBEDDED - bool - depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE -+ select USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD - default y - - config SSB_DRIVER_EXTIF diff --git a/target/linux/bcm47xx/patches-5.10/300-fork_cacheflush.patch b/target/linux/bcm47xx/patches-5.10/300-fork_cacheflush.patch deleted file mode 100644 index daa2c1adf0..0000000000 --- a/target/linux/bcm47xx/patches-5.10/300-fork_cacheflush.patch +++ /dev/null @@ -1,21 +0,0 @@ -From: Wolfram Joost -Subject: [PATCH] fork_cacheflush - -On ASUS WL-500gP there are many unexpected "Segmentation fault"s that -seem to be caused by a kernel. They can be avoided by: -1) Disabling highpage -2) Using flush_cache_mm in flush_cache_dup_mm - -For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035 ---- ---- a/arch/mips/include/asm/cacheflush.h -+++ b/arch/mips/include/asm/cacheflush.h -@@ -46,7 +46,7 @@ - extern void (*flush_cache_all)(void); - extern void (*__flush_cache_all)(void); - extern void (*flush_cache_mm)(struct mm_struct *mm); --#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0) -+#define flush_cache_dup_mm(mm) flush_cache_mm(mm) - extern void (*flush_cache_range)(struct vm_area_struct *vma, - unsigned long start, unsigned long end); - extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); diff --git a/target/linux/bcm47xx/patches-5.10/310-no_highpage.patch b/target/linux/bcm47xx/patches-5.10/310-no_highpage.patch deleted file mode 100644 index b1dcdf9cb2..0000000000 --- a/target/linux/bcm47xx/patches-5.10/310-no_highpage.patch +++ /dev/null @@ -1,74 +0,0 @@ -From: Jeff Hansen -Subject: [PATCH] no highpage - -On ASUS WL-500gP there are many unexpected "Segmentation fault"s that -seem to be caused by a kernel. They can be avoided by: -1) Disabling highpage -2) Using flush_cache_mm in flush_cache_dup_mm - -For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035 ---- ---- a/arch/mips/include/asm/page.h -+++ b/arch/mips/include/asm/page.h -@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl - #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ - - #include -+#include - - extern void build_clear_page(void); - extern void build_copy_page(void); -@@ -110,11 +111,16 @@ static inline void clear_user_page(void - flush_data_cache_page((unsigned long)addr); - } - --struct vm_area_struct; --extern void copy_user_highpage(struct page *to, struct page *from, -- unsigned long vaddr, struct vm_area_struct *vma); -+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, -+ struct page *to) -+{ -+ extern void (*flush_data_cache_page)(unsigned long addr); - --#define __HAVE_ARCH_COPY_USER_HIGHPAGE -+ copy_page(vto, vfrom); -+ if (!cpu_has_ic_fills_f_dc || -+ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) -+ flush_data_cache_page((unsigned long)vto); -+} - - /* - * These are used to make use of C type-checking.. ---- a/arch/mips/mm/init.c -+++ b/arch/mips/mm/init.c -@@ -167,30 +167,6 @@ void kunmap_coherent(void) - preempt_enable(); - } - --void copy_user_highpage(struct page *to, struct page *from, -- unsigned long vaddr, struct vm_area_struct *vma) --{ -- void *vfrom, *vto; -- -- vto = kmap_atomic(to); -- if (cpu_has_dc_aliases && cpu_use_kmap_coherent && -- page_mapcount(from) && !Page_dcache_dirty(from)) { -- vfrom = kmap_coherent(from, vaddr); -- copy_page(vto, vfrom); -- kunmap_coherent(); -- } else { -- vfrom = kmap_atomic(from); -- copy_page(vto, vfrom); -- kunmap_atomic(vfrom); -- } -- if ((!cpu_has_ic_fills_f_dc) || -- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK)) -- flush_data_cache_page((unsigned long)vto); -- kunmap_atomic(vto); -- /* Make sure this page is cleared on other CPU's too before using it */ -- smp_wmb(); --} -- - void copy_to_user_page(struct vm_area_struct *vma, - struct page *page, unsigned long vaddr, void *dst, const void *src, - unsigned long len) diff --git a/target/linux/bcm47xx/patches-5.10/400-mtd-bcm47xxpart-get-nvram.patch b/target/linux/bcm47xx/patches-5.10/400-mtd-bcm47xxpart-get-nvram.patch deleted file mode 100644 index 17abe89d1d..0000000000 --- a/target/linux/bcm47xx/patches-5.10/400-mtd-bcm47xxpart-get-nvram.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/mtd/parsers/bcm47xxpart.c -+++ b/drivers/mtd/parsers/bcm47xxpart.c -@@ -98,6 +98,7 @@ static int bcm47xxpart_parse(struct mtd_ - int trx_num = 0; /* Number of found TRX partitions */ - int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, }; - int err; -+ bool found_nvram = false; - - /* - * Some really old flashes (like AT45DB*) had smaller erasesize-s, but -@@ -279,12 +280,23 @@ static int bcm47xxpart_parse(struct mtd_ - if (buf[0] == NVRAM_HEADER) { - bcm47xxpart_add_part(&parts[curr_part++], "nvram", - master->size - blocksize, 0); -+ found_nvram = true; - break; - } - } - - kfree(buf); - -+ if (!found_nvram) { -+ pr_err("can not find a nvram partition reserve last block\n"); -+ bcm47xxpart_add_part(&parts[curr_part++], "nvram_guess", -+ master->size - blocksize * 2, MTD_WRITEABLE); -+ for (i = 0; i < curr_part; i++) { -+ if (parts[i].size + parts[i].offset == master->size) -+ parts[i].offset -= blocksize * 2; -+ } -+ } -+ - /* - * Assume that partitions end at the beginning of the one they are - * followed by. diff --git a/target/linux/bcm47xx/patches-5.10/610-pci_ide_fix.patch b/target/linux/bcm47xx/patches-5.10/610-pci_ide_fix.patch deleted file mode 100644 index 520828e8e5..0000000000 --- a/target/linux/bcm47xx/patches-5.10/610-pci_ide_fix.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: b.sander -Subject: [PATCH] pci: IDE fix - -These are standard probing messages when using pdc202xx_old: -pdc202xx_old 0000:00:01.0: IDE controller (0x105a:0x0d30 rev 0x02) -PCI: Enabling device 0000:00:01.0 (0004 -> 0007) -PCI: Fixing up device 0000:00:01.0 -0000:00:01.0: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode. -0000:00:01.0: FORCING BURST BIT 0x00->0x01 ACTIVE -pdc202xx_old 0000:00:01.0: 100% native mode on irq 6 - -With the default MAX_HWIFS value after above we get: - ide2: BM-DMA at 0x0400-0x0407 - ide3: BM-DMA at 0x0408-0x040f -Probing IDE interface ide2... -hde: CF500, CFA DISK drive - -As you can see it's ide2 + ide3 and hde. - -With this patch applied we get: - ide0: BM-DMA at 0x0400-0x0407 - ide1: BM-DMA at 0x0408-0x040f -Probing IDE interface ide0... -hda: CF500, CFA DISK drive - -This fixes OpenWrt ticket #7061: https://dev.openwrt.org/ticket/7061 ---- ---- a/include/linux/ide.h -+++ b/include/linux/ide.h -@@ -236,7 +236,11 @@ static inline void ide_std_init_ports(st - hw->io_ports.ctl_addr = ctl_addr; - } - -+#if defined CONFIG_BCM47XX -+# define MAX_HWIFS 2 -+#else - #define MAX_HWIFS 10 -+#endif - - /* - * Now for the data we need to maintain per-drive: ide_drive_t diff --git a/target/linux/bcm47xx/patches-5.10/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch b/target/linux/bcm47xx/patches-5.10/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch deleted file mode 100644 index 2fcfbb7438..0000000000 --- a/target/linux/bcm47xx/patches-5.10/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch +++ /dev/null @@ -1,42 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sun, 7 Nov 2021 14:20:40 +0100 -Subject: [PATCH] net: bgmac: connect to PHY even if it is BGMAC_PHY_NOREGS -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Recent bgmac change was meant to just fix a race between "Generic PHY" -and "bcm53xx" drivers after -EPROBE_DEFER. It modified bgmac to use -phy_connect() only if there is a real PHY device connected. - -That change broke bgmac on bcm47xx. bcma_phy_connect() now registers a -fixed PHY with the bgmac_phy_connect_direct(). That fails as another -fixed PHY (also using address 0) is already registered - by bcm47xx arch -code bcm47xx_register_bus_complete(). - -This change brings origial behaviour. It connects Ethernet interface -with pseudo-PHY (switch device) and adjusts Ethernet interface link to -match connected switch. - -This fixes: -[ 2.548098] bgmac_bcma bcma0:1: Failed to register fixed PHY device -[ 2.554584] bgmac_bcma bcma0:1: Cannot connect to phy - -Fixes: b5375509184d ("net: bgmac: improve handling PHY") -Link: https://lore.kernel.org/netdev/3639116e-9292-03ca-b9d9-d741118a4541@gmail.com/T/#u -Signed-off-by: Rafał Miłecki ---- - drivers/net/ethernet/broadcom/bgmac-bcma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/broadcom/bgmac-bcma.c -+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c -@@ -94,7 +94,7 @@ static int bcma_phy_connect(struct bgmac - return 0; - - /* Connect to the PHY */ -- if (bgmac->mii_bus && bgmac->phyaddr != BGMAC_PHY_NOREGS) { -+ if (bgmac->mii_bus) { - snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id, - bgmac->phyaddr); - phy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link, diff --git a/target/linux/bcm47xx/patches-5.10/701-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch b/target/linux/bcm47xx/patches-5.10/701-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch deleted file mode 100644 index 2c2eb07b82..0000000000 --- a/target/linux/bcm47xx/patches-5.10/701-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch +++ /dev/null @@ -1,33 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 10 Jun 2022 13:10:47 +0200 -Subject: [PATCH] bgmac: reduce max frame size to support just MTU 1500 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -bgmac allocates new replacement buffer before handling each received -frame. Allocating & DMA-preparing 9724 B each time consumes a lot of CPU -time. Ideally bgmac should just respect currently set MTU but it isn't -the case right now. For now just revert back to the old limited frame -size. - -This change bumps NAT masquarade speed by ~95%. - -Ref: 8c7da63978f1 ("bgmac: configure MTU and add support for frames beyond 8192 byte size") -Signed-off-by: Rafał Miłecki ---- - drivers/net/ethernet/broadcom/bgmac.h | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bgmac.h -+++ b/drivers/net/ethernet/broadcom/bgmac.h -@@ -366,8 +366,7 @@ - #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ - #define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \ - BGMAC_RX_FRAME_OFFSET) --/* Jumbo frame size with FCS */ --#define BGMAC_RX_MAX_FRAME_SIZE 9724 -+#define BGMAC_RX_MAX_FRAME_SIZE 1536 - #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) - #define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \ - SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) diff --git a/target/linux/bcm47xx/patches-5.10/791-tg3-no-pci-sleep.patch b/target/linux/bcm47xx/patches-5.10/791-tg3-no-pci-sleep.patch deleted file mode 100644 index 50edfc3b41..0000000000 --- a/target/linux/bcm47xx/patches-5.10/791-tg3-no-pci-sleep.patch +++ /dev/null @@ -1,17 +0,0 @@ -When the Ethernet controller is powered down and someone wants to -access the mdio bus like the witch driver (b53) the system crashed if -PCI_D3hot was set before. This patch deactivates this power sawing mode -when a switch driver is in use. - ---- a/drivers/net/ethernet/broadcom/tg3.c -+++ b/drivers/net/ethernet/broadcom/tg3.c -@@ -4273,7 +4273,8 @@ static int tg3_power_down_prepare(struct - static void tg3_power_down(struct tg3 *tp) - { - pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); -- pci_set_power_state(tp->pdev, PCI_D3hot); -+ if (!tg3_flag(tp, ROBOSWITCH)) -+ pci_set_power_state(tp->pdev, PCI_D3hot); - } - - static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex) diff --git a/target/linux/bcm47xx/patches-5.10/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch b/target/linux/bcm47xx/patches-5.10/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch deleted file mode 100644 index 318dc55810..0000000000 --- a/target/linux/bcm47xx/patches-5.10/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 597715c61ae75a05ab3310a34ff3857a006f0f63 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 20 Nov 2014 21:32:42 +0100 -Subject: [PATCH] bcma: add table of serial flashes with smaller blocks -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki ---- - drivers/bcma/driver_chipcommon_sflash.c | 29 +++++++++++++++++++++++++++++ - 1 file changed, 29 insertions(+) - ---- a/drivers/bcma/driver_chipcommon_sflash.c -+++ b/drivers/bcma/driver_chipcommon_sflash.c -@@ -9,6 +9,7 @@ - - #include - #include -+#include - - static struct resource bcma_sflash_resource = { - .name = "bcma_sflash", -@@ -42,6 +43,13 @@ static const struct bcma_sflash_tbl_e bc - { NULL }, - }; - -+/* Some devices use smaller blocks (and have more of them) */ -+static const struct bcma_sflash_tbl_e bcma_sflash_st_shrink_tbl[] = { -+ { "M25P16", 0x14, 0x1000, 512, }, -+ { "M25P32", 0x15, 0x1000, 1024, }, -+ { NULL }, -+}; -+ - static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = { - { "SST25WF512", 1, 0x1000, 16, }, - { "SST25VF512", 0x48, 0x1000, 16, }, -@@ -85,6 +93,24 @@ static void bcma_sflash_cmd(struct bcma_ - bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n"); - } - -+const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id) -+{ -+ enum bcm47xx_board board = bcm47xx_board_get(); -+ const struct bcma_sflash_tbl_e *e; -+ -+ switch (board) { -+ case BCM47XX_BOARD_NETGEAR_WGR614_V10: -+ case BCM47XX_BOARD_NETGEAR_WNR1000_V3: -+ for (e = bcma_sflash_st_shrink_tbl; e->name; e++) { -+ if (e->id == id) -+ return e; -+ } -+ return NULL; -+ default: -+ return NULL; -+ } -+} -+ - /* Initialize serial flash access */ - int bcma_sflash_init(struct bcma_drv_cc *cc) - { -@@ -115,6 +141,10 @@ int bcma_sflash_init(struct bcma_drv_cc - case 0x13: - return -ENOTSUPP; - default: -+ e = bcma_sflash_shrink_flash(id); -+ if (e) -+ break; -+ - for (e = bcma_sflash_st_tbl; e->name; e++) { - if (e->id == id) - break; diff --git a/target/linux/bcm47xx/patches-5.10/820-wgt634u-nvram-fix.patch b/target/linux/bcm47xx/patches-5.10/820-wgt634u-nvram-fix.patch deleted file mode 100644 index bfcfae885f..0000000000 --- a/target/linux/bcm47xx/patches-5.10/820-wgt634u-nvram-fix.patch +++ /dev/null @@ -1,296 +0,0 @@ -The Netgear wgt634u uses a different format for storing the -configuration. This patch is needed to read out the correct -configuration. The cfe_env.c file uses a different method way to read -out the configuration than the in kernel cfe config reader. - ---- a/drivers/firmware/broadcom/Makefile -+++ b/drivers/firmware/broadcom/Makefile -@@ -1,4 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only --obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx_nvram.o -+obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx_nvram.o cfe_env.o - obj-$(CONFIG_BCM47XX_SPROM) += bcm47xx_sprom.o - obj-$(CONFIG_TEE_BNXT_FW) += tee_bnxt_fw.o ---- /dev/null -+++ b/drivers/firmware/broadcom/cfe_env.c -@@ -0,0 +1,228 @@ -+/* -+ * CFE environment variable access -+ * -+ * Copyright 2001-2003, Broadcom Corporation -+ * Copyright 2006, Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define NVRAM_SIZE (0x1ff0) -+static char _nvdata[NVRAM_SIZE]; -+static char _valuestr[256]; -+ -+/* -+ * TLV types. These codes are used in the "type-length-value" -+ * encoding of the items stored in the NVRAM device (flash or EEPROM) -+ * -+ * The layout of the flash/nvram is as follows: -+ * -+ * -+ * -+ * The type code of "ENV_TLV_TYPE_END" marks the end of the list. -+ * The "length" field marks the length of the data section, not -+ * including the type and length fields. -+ * -+ * Environment variables are stored as follows: -+ * -+ * = -+ * -+ * If bit 0 (low bit) is set, the length is an 8-bit value. -+ * If bit 0 (low bit) is clear, the length is a 16-bit value -+ * -+ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still -+ * indicates the size of the length field. -+ * -+ * Flags are from the constants below: -+ * -+ */ -+#define ENV_LENGTH_16BITS 0x00 /* for low bit */ -+#define ENV_LENGTH_8BITS 0x01 -+ -+#define ENV_TYPE_USER 0x80 -+ -+#define ENV_CODE_SYS(n,l) (((n)<<1)|(l)) -+#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER) -+ -+/* -+ * The actual TLV types we support -+ */ -+ -+#define ENV_TLV_TYPE_END 0x00 -+#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS) -+ -+/* -+ * Environment variable flags -+ */ -+ -+#define ENV_FLG_NORMAL 0x00 /* normal read/write */ -+#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */ -+#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */ -+ -+#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */ -+#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */ -+ -+ -+/* ********************************************************************* -+ * _nvram_read(buffer,offset,length) -+ * -+ * Read data from the NVRAM device -+ * -+ * Input parameters: -+ * buffer - destination buffer -+ * offset - offset of data to read -+ * length - number of bytes to read -+ * -+ * Return value: -+ * number of bytes read, or <0 if error occured -+ ********************************************************************* */ -+static int -+_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length) -+{ -+ int i; -+ if (offset > NVRAM_SIZE) -+ return -1; -+ -+ for ( i = 0; i < length; i++) { -+ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i]; -+ } -+ return length; -+} -+ -+ -+static char* -+_strnchr(const char *dest,int c,size_t cnt) -+{ -+ while (*dest && (cnt > 0)) { -+ if (*dest == c) return (char *) dest; -+ dest++; -+ cnt--; -+ } -+ return NULL; -+} -+ -+ -+ -+/* -+ * Core support API: Externally visible. -+ */ -+ -+/* -+ * Get the value of an NVRAM variable -+ * @param name name of variable to get -+ * @return value of variable or NULL if undefined -+ */ -+ -+char *cfe_env_get(unsigned char *nv_buf, const char *name) -+{ -+ int size; -+ unsigned char *buffer; -+ unsigned char *ptr; -+ unsigned char *envval; -+ unsigned int reclen; -+ unsigned int rectype; -+ int offset; -+ int flg; -+ -+ if (!strcmp(name, "nvram_type")) -+ return "cfe"; -+ -+ size = NVRAM_SIZE; -+ buffer = &_nvdata[0]; -+ -+ ptr = buffer; -+ offset = 0; -+ -+ /* Read the record type and length */ -+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) { -+ goto error; -+ } -+ -+ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) { -+ -+ /* Adjust pointer for TLV type */ -+ rectype = *(ptr); -+ offset++; -+ size--; -+ -+ /* -+ * Read the length. It can be either 1 or 2 bytes -+ * depending on the code -+ */ -+ if (rectype & ENV_LENGTH_8BITS) { -+ /* Read the record type and length - 8 bits */ -+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) { -+ goto error; -+ } -+ reclen = *(ptr); -+ size--; -+ offset++; -+ } -+ else { -+ /* Read the record type and length - 16 bits, MSB first */ -+ if (_nvram_read(nv_buf, ptr,offset,2) != 2) { -+ goto error; -+ } -+ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1); -+ size -= 2; -+ offset += 2; -+ } -+ -+ if (reclen > size) -+ break; /* should not happen, bad NVRAM */ -+ -+ switch (rectype) { -+ case ENV_TLV_TYPE_ENV: -+ /* Read the TLV data */ -+ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen) -+ goto error; -+ flg = *ptr++; -+ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1)); -+ if (envval) { -+ *envval++ = '\0'; -+ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr)); -+ _valuestr[(reclen-1)-(envval-ptr)] = '\0'; -+#if 0 -+ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr); -+#endif -+ if(!strcmp(ptr, name)){ -+ return _valuestr; -+ } -+ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name)) -+ return _valuestr; -+ } -+ break; -+ -+ default: -+ /* Unknown TLV type, skip it. */ -+ break; -+ } -+ -+ /* -+ * Advance to next TLV -+ */ -+ -+ size -= (int)reclen; -+ offset += reclen; -+ -+ /* Read the next record type */ -+ ptr = buffer; -+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) -+ goto error; -+ } -+ -+error: -+ return NULL; -+ -+} -+ ---- a/drivers/firmware/broadcom/bcm47xx_nvram.c -+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c -@@ -33,6 +33,8 @@ struct nvram_header { - static char nvram_buf[NVRAM_SPACE]; - static size_t nvram_len; - static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000}; -+static int cfe_env; -+extern char *cfe_env_get(char *nv_buf, const char *name); - - /** - * bcm47xx_nvram_is_valid - check for a valid NVRAM at specified memory -@@ -80,6 +82,26 @@ static int bcm47xx_nvram_find_and_copy(v - return -EEXIST; - } - -+ cfe_env = 0; -+ -+ /* XXX: hack for supporting the CFE environment stuff on WGT634U */ -+ if (res_size >= 8 * 1024 * 1024) { -+ u32 *src = (u32 *)(flash_start + 8 * 1024 * 1024 - 0x2000); -+ u32 *dst = (u32 *)nvram_buf; -+ -+ if ((*src & 0xff00ff) == 0x000001) { -+ printk("early_nvram_init: WGT634U NVRAM found.\n"); -+ -+ for (i = 0; i < 0x1ff0; i++) { -+ if (*src == 0xFFFFFFFF) -+ break; -+ *dst++ = *src++; -+ } -+ cfe_env = 1; -+ return 0; -+ } -+ } -+ - /* TODO: when nvram is on nand flash check for bad blocks first. */ - - /* Try every possible flash size and check for NVRAM at its end */ -@@ -172,6 +194,13 @@ int bcm47xx_nvram_getenv(const char *nam - if (!name) - return -EINVAL; - -+ if (cfe_env) { -+ value = cfe_env_get(nvram_buf, name); -+ if (!value) -+ return -ENOENT; -+ return snprintf(val, val_len, "%s", value); -+ } -+ - if (!nvram_len) { - err = nvram_init(); - if (err) diff --git a/target/linux/bcm47xx/patches-5.10/830-huawei_e970_support.patch b/target/linux/bcm47xx/patches-5.10/830-huawei_e970_support.patch deleted file mode 100644 index 1746fee592..0000000000 --- a/target/linux/bcm47xx/patches-5.10/830-huawei_e970_support.patch +++ /dev/null @@ -1,101 +0,0 @@ ---- a/arch/mips/bcm47xx/setup.c -+++ b/arch/mips/bcm47xx/setup.c -@@ -37,6 +37,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -254,6 +255,33 @@ static struct fixed_phy_status bcm47xx_f - .duplex = DUPLEX_FULL, - }; - -+static struct gpio_wdt_platform_data gpio_wdt_data; -+ -+static struct platform_device gpio_wdt_device = { -+ .name = "gpio-wdt", -+ .id = 0, -+ .dev = { -+ .platform_data = &gpio_wdt_data, -+ }, -+}; -+ -+static int __init bcm47xx_register_gpio_watchdog(void) -+{ -+ enum bcm47xx_board board = bcm47xx_board_get(); -+ -+ switch (board) { -+ case BCM47XX_BOARD_HUAWEI_E970: -+ pr_info("bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\n"); -+ gpio_wdt_data.gpio = 7; -+ gpio_wdt_data.interval = HZ; -+ gpio_wdt_data.first_interval = HZ / 5; -+ return platform_device_register(&gpio_wdt_device); -+ default: -+ /* Nothing to do */ -+ return 0; -+ } -+} -+ - static int __init bcm47xx_register_bus_complete(void) - { - switch (bcm47xx_bus_type) { -@@ -275,6 +303,7 @@ static int __init bcm47xx_register_bus_c - bcm47xx_workarounds(); - - fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status); -+ bcm47xx_register_gpio_watchdog(); - return 0; - } - device_initcall(bcm47xx_register_bus_complete); ---- a/arch/mips/configs/bcm47xx_defconfig -+++ b/arch/mips/configs/bcm47xx_defconfig -@@ -63,6 +63,7 @@ CONFIG_HW_RANDOM=y - CONFIG_GPIO_SYSFS=y - CONFIG_WATCHDOG=y - CONFIG_BCM47XX_WDT=y -+CONFIG_GPIO_WDT=y - CONFIG_SSB_DRIVER_GIGE=y - CONFIG_BCMA_DRIVER_GMAC_CMN=y - CONFIG_USB=y ---- a/drivers/ssb/embedded.c -+++ b/drivers/ssb/embedded.c -@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu - } - EXPORT_SYMBOL(ssb_watchdog_timer_set); - -+#ifdef CONFIG_BCM47XX -+#include -+ -+static bool ssb_watchdog_supported(void) -+{ -+ enum bcm47xx_board board = bcm47xx_board_get(); -+ -+ /* The Huawei E970 has a hardware watchdog using a GPIO */ -+ switch (board) { -+ case BCM47XX_BOARD_HUAWEI_E970: -+ return false; -+ default: -+ return true; -+ } -+} -+#else -+static bool ssb_watchdog_supported(void) -+{ -+ return true; -+} -+#endif -+ - int ssb_watchdog_register(struct ssb_bus *bus) - { - struct bcm47xx_wdt wdt = {}; - struct platform_device *pdev; - -+ if (!ssb_watchdog_supported()) -+ return 0; -+ - if (ssb_chipco_available(&bus->chipco)) { - wdt.driver_data = &bus->chipco; - wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt; diff --git a/target/linux/bcm47xx/patches-5.10/831-old_gpio_wdt.patch b/target/linux/bcm47xx/patches-5.10/831-old_gpio_wdt.patch deleted file mode 100644 index f6fb7f1855..0000000000 --- a/target/linux/bcm47xx/patches-5.10/831-old_gpio_wdt.patch +++ /dev/null @@ -1,360 +0,0 @@ -This generic GPIO watchdog is used on Huawei E970 (bcm47xx) - -Signed-off-by: Mathias Adam - ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -1698,6 +1698,15 @@ config WDT_MTX1 - Hardware driver for the MTX-1 boards. This is a watchdog timer that - will reboot the machine after a 100 seconds timer expired. - -+config GPIO_WDT -+ tristate "GPIO Hardware Watchdog" -+ help -+ Hardware driver for GPIO-controlled watchdogs. GPIO pin and -+ toggle interval settings are platform-specific. The driver -+ will stop toggling the GPIO (i.e. machine reboots) after a -+ 100 second timer expired and no process has written to -+ /dev/watchdog during that time. -+ - config PNX833X_WDT - tristate "PNX833x Hardware Watchdog" - depends on SOC_PNX8335 ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -161,6 +161,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt - obj-$(CONFIG_INDYDOG) += indydog.o - obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o - obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o -+obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o - obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o ---- /dev/null -+++ b/drivers/watchdog/old_gpio_wdt.c -@@ -0,0 +1,301 @@ -+/* -+ * Driver for GPIO-controlled Hardware Watchdogs. -+ * -+ * Copyright (C) 2013 Mathias Adam -+ * -+ * Replaces mtx1_wdt (driver for the MTX-1 Watchdog): -+ * -+ * (C) Copyright 2005 4G Systems , -+ * All Rights Reserved. -+ * http://www.4g-systems.biz -+ * -+ * (C) Copyright 2007 OpenWrt.org, Florian Fainelli -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ * Neither Michael Stickel nor 4G Systems admit liability nor provide -+ * warranty for any of this software. This material is provided -+ * "AS-IS" and at no charge. -+ * -+ * (c) Copyright 2005 4G Systems -+ * -+ * Release 0.01. -+ * Author: Michael Stickel michael.stickel@4g-systems.biz -+ * -+ * Release 0.02. -+ * Author: Florian Fainelli florian@openwrt.org -+ * use the Linux watchdog/timer APIs -+ * -+ * Release 0.03. -+ * Author: Mathias Adam -+ * make it a generic gpio watchdog driver -+ * -+ * The Watchdog is configured to reset the MTX-1 -+ * if it is not triggered for 100 seconds. -+ * It should not be triggered more often than 1.6 seconds. -+ * -+ * A timer triggers the watchdog every 5 seconds, until -+ * it is opened for the first time. After the first open -+ * it MUST be triggered every 2..95 seconds. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static int ticks = 100 * HZ; -+ -+static struct { -+ struct completion stop; -+ spinlock_t lock; -+ int running; -+ struct timer_list timer; -+ int queue; -+ int default_ticks; -+ unsigned long inuse; -+ unsigned gpio; -+ unsigned int gstate; -+ int interval; -+ int first_interval; -+} gpio_wdt_device; -+ -+static void gpio_wdt_trigger(struct timer_list *unused) -+{ -+ spin_lock(&gpio_wdt_device.lock); -+ if (gpio_wdt_device.running && ticks > 0) -+ ticks -= gpio_wdt_device.interval; -+ -+ /* toggle wdt gpio */ -+ gpio_wdt_device.gstate = !gpio_wdt_device.gstate; -+ gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate); -+ -+ if (gpio_wdt_device.queue && ticks > 0) -+ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval); -+ else -+ complete(&gpio_wdt_device.stop); -+ spin_unlock(&gpio_wdt_device.lock); -+} -+ -+static void gpio_wdt_reset(void) -+{ -+ ticks = gpio_wdt_device.default_ticks; -+} -+ -+ -+static void gpio_wdt_start(void) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&gpio_wdt_device.lock, flags); -+ if (!gpio_wdt_device.queue) { -+ gpio_wdt_device.queue = 1; -+ gpio_wdt_device.gstate = 1; -+ gpio_set_value(gpio_wdt_device.gpio, 1); -+ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval); -+ } -+ gpio_wdt_device.running++; -+ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); -+} -+ -+static int gpio_wdt_stop(void) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&gpio_wdt_device.lock, flags); -+ if (gpio_wdt_device.queue) { -+ gpio_wdt_device.queue = 0; -+ gpio_wdt_device.gstate = 0; -+ gpio_set_value(gpio_wdt_device.gpio, 0); -+ } -+ ticks = gpio_wdt_device.default_ticks; -+ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags); -+ return 0; -+} -+ -+/* Filesystem functions */ -+ -+static int gpio_wdt_open(struct inode *inode, struct file *file) -+{ -+ if (test_and_set_bit(0, &gpio_wdt_device.inuse)) -+ return -EBUSY; -+ return nonseekable_open(inode, file); -+} -+ -+ -+static int gpio_wdt_release(struct inode *inode, struct file *file) -+{ -+ clear_bit(0, &gpio_wdt_device.inuse); -+ return 0; -+} -+ -+static long gpio_wdt_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ void __user *argp = (void __user *)arg; -+ int __user *p = (int __user *)argp; -+ unsigned int value; -+ static const struct watchdog_info ident = { -+ .options = WDIOF_CARDRESET, -+ .identity = "GPIO WDT", -+ }; -+ -+ switch (cmd) { -+ case WDIOC_GETSUPPORT: -+ if (copy_to_user(argp, &ident, sizeof(ident))) -+ return -EFAULT; -+ break; -+ case WDIOC_GETSTATUS: -+ case WDIOC_GETBOOTSTATUS: -+ put_user(0, p); -+ break; -+ case WDIOC_SETOPTIONS: -+ if (get_user(value, p)) -+ return -EFAULT; -+ if (value & WDIOS_ENABLECARD) -+ gpio_wdt_start(); -+ else if (value & WDIOS_DISABLECARD) -+ gpio_wdt_stop(); -+ else -+ return -EINVAL; -+ return 0; -+ case WDIOC_KEEPALIVE: -+ gpio_wdt_reset(); -+ break; -+ default: -+ return -ENOTTY; -+ } -+ return 0; -+} -+ -+ -+static ssize_t gpio_wdt_write(struct file *file, const char *buf, -+ size_t count, loff_t *ppos) -+{ -+ if (!count) -+ return -EIO; -+ gpio_wdt_reset(); -+ return count; -+} -+ -+static const struct file_operations gpio_wdt_fops = { -+ .owner = THIS_MODULE, -+ .llseek = no_llseek, -+ .unlocked_ioctl = gpio_wdt_ioctl, -+ .open = gpio_wdt_open, -+ .write = gpio_wdt_write, -+ .release = gpio_wdt_release, -+}; -+ -+ -+static struct miscdevice gpio_wdt_misc = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &gpio_wdt_fops, -+}; -+ -+ -+static int gpio_wdt_probe(struct platform_device *pdev) -+{ -+ int ret; -+ struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data; -+ -+ gpio_wdt_device.gpio = gpio_wdt_data->gpio; -+ gpio_wdt_device.interval = gpio_wdt_data->interval; -+ gpio_wdt_device.first_interval = gpio_wdt_data->first_interval; -+ if (gpio_wdt_device.first_interval <= 0) { -+ gpio_wdt_device.first_interval = gpio_wdt_device.interval; -+ } -+ -+ ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt"); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "failed to request gpio"); -+ return ret; -+ } -+ -+ spin_lock_init(&gpio_wdt_device.lock); -+ init_completion(&gpio_wdt_device.stop); -+ gpio_wdt_device.queue = 0; -+ clear_bit(0, &gpio_wdt_device.inuse); -+ timer_setup(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L); -+ gpio_wdt_device.default_ticks = ticks; -+ -+ gpio_wdt_start(); -+ dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n", -+ gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval); -+ return 0; -+} -+ -+static int gpio_wdt_remove(struct platform_device *pdev) -+{ -+ /* FIXME: do we need to lock this test ? */ -+ if (gpio_wdt_device.queue) { -+ gpio_wdt_device.queue = 0; -+ wait_for_completion(&gpio_wdt_device.stop); -+ } -+ -+ gpio_free(gpio_wdt_device.gpio); -+ misc_deregister(&gpio_wdt_misc); -+ return 0; -+} -+ -+static struct platform_driver gpio_wdt_driver = { -+ .probe = gpio_wdt_probe, -+ .remove = gpio_wdt_remove, -+ .driver.name = "gpio-wdt", -+ .driver.owner = THIS_MODULE, -+}; -+ -+static int __init gpio_wdt_init(void) -+{ -+ return platform_driver_register(&gpio_wdt_driver); -+} -+arch_initcall(gpio_wdt_init); -+ -+/* -+ * We do wdt initialization in two steps: arch_initcall probes the wdt -+ * very early to start pinging the watchdog (misc devices are not yet -+ * available), and later module_init() just registers the misc device. -+ */ -+static int gpio_wdt_init_late(void) -+{ -+ int ret; -+ -+ ret = misc_register(&gpio_wdt_misc); -+ if (ret < 0) { -+ pr_err("GPIO_WDT: failed to register misc device\n"); -+ return ret; -+ } -+ return 0; -+} -+#ifndef MODULE -+module_init(gpio_wdt_init_late); -+#endif -+ -+static void __exit gpio_wdt_exit(void) -+{ -+ platform_driver_unregister(&gpio_wdt_driver); -+} -+module_exit(gpio_wdt_exit); -+ -+MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam"); -+MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -+MODULE_ALIAS("platform:gpio-wdt"); ---- /dev/null -+++ b/include/linux/old_gpio_wdt.h -@@ -0,0 +1,21 @@ -+/* -+ * Definitions for the GPIO watchdog driver -+ * -+ * Copyright (C) 2013 Mathias Adam -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef _GPIO_WDT_H_ -+#define _GPIO_WDT_H_ -+ -+struct gpio_wdt_platform_data { -+ int gpio; /* GPIO line number */ -+ int interval; /* watchdog reset interval in system ticks */ -+ int first_interval; /* first wd reset interval in system ticks */ -+}; -+ -+#endif /* _GPIO_WDT_H_ */ diff --git a/target/linux/bcm47xx/patches-5.10/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch b/target/linux/bcm47xx/patches-5.10/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch deleted file mode 100644 index 6b7ee06e50..0000000000 --- a/target/linux/bcm47xx/patches-5.10/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 5c81397a0147ea59c778d1de14ef54e2268221f6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 8 Apr 2015 06:58:11 +0200 -Subject: [PATCH] ssb: reject PCI writes setting CardBus bridge resources -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -If SoC has a CardBus we can set resources of device at slot 1 only. It's -impossigle to set bridge resources as it simply overwrites device 1 -configuration and usually results in Data bus error-s. - -Signed-off-by: Rafał Miłecki ---- - drivers/ssb/driver_pcicore.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/ssb/driver_pcicore.c -+++ b/drivers/ssb/driver_pcicore.c -@@ -164,6 +164,10 @@ static int ssb_extpci_write_config(struc - WARN_ON(!pc->hostmode); - if (unlikely(len != 1 && len != 2 && len != 4)) - goto out; -+ /* CardBus SoCs allow configuring dev 1 resources only */ -+ if (extpci_core->cardbusmode && dev != 1 && -+ off >= PCI_BASE_ADDRESS_0 && off <= PCI_BASE_ADDRESS_5) -+ goto out; - addr = get_cfgspace_addr(pc, bus, dev, func, off); - if (unlikely(!addr)) - goto out; diff --git a/target/linux/bcm47xx/patches-5.10/940-bcm47xx-yenta.patch b/target/linux/bcm47xx/patches-5.10/940-bcm47xx-yenta.patch deleted file mode 100644 index 8847b0c0c7..0000000000 --- a/target/linux/bcm47xx/patches-5.10/940-bcm47xx-yenta.patch +++ /dev/null @@ -1,46 +0,0 @@ ---- a/drivers/pcmcia/yenta_socket.c -+++ b/drivers/pcmcia/yenta_socket.c -@@ -932,6 +932,8 @@ static unsigned int yenta_probe_irq(stru - * Probe for usable interrupts using the force - * register to generate bogus card status events. - */ -+#ifndef CONFIG_BCM47XX -+ /* WRT54G3G does not like this */ - cb_writel(socket, CB_SOCKET_EVENT, -1); - cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK); - reg = exca_readb(socket, I365_CSCINT); -@@ -947,6 +949,7 @@ static unsigned int yenta_probe_irq(stru - } - cb_writel(socket, CB_SOCKET_MASK, 0); - exca_writeb(socket, I365_CSCINT, reg); -+#endif - - mask = probe_irq_mask(val) & 0xffff; - -@@ -1031,6 +1034,10 @@ static void yenta_get_socket_capabilitie - else - socket->socket.irq_mask = 0; - -+ /* irq mask probing is broken for the WRT54G3G */ -+ if (socket->socket.irq_mask == 0) -+ socket->socket.irq_mask = 0x6f8; -+ - dev_info(&socket->dev->dev, "ISA IRQ mask 0x%04x, PCI irq %d\n", - socket->socket.irq_mask, socket->cb_irq); - } -@@ -1262,6 +1269,15 @@ static int yenta_probe(struct pci_dev *d - dev_info(&dev->dev, "Socket status: %08x\n", - cb_readl(socket, CB_SOCKET_STATE)); - -+ /* Generate an interrupt on card insert/remove */ -+ config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK); -+ -+ /* Set up Multifunction Routing Status Register */ -+ config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */); -+ -+ /* Switch interrupts to parallelized */ -+ config_writeb(socket, 0x92, 0x64); -+ - yenta_fixup_parent_bridge(dev->subordinate); - - /* Register it with the pcmcia layer.. */ diff --git a/target/linux/bcm47xx/patches-5.10/976-ssb_increase_pci_delay.patch b/target/linux/bcm47xx/patches-5.10/976-ssb_increase_pci_delay.patch deleted file mode 100644 index 99aa188374..0000000000 --- a/target/linux/bcm47xx/patches-5.10/976-ssb_increase_pci_delay.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/ssb/driver_pcicore.c -+++ b/drivers/ssb/driver_pcicore.c -@@ -390,7 +390,7 @@ static void ssb_pcicore_init_hostmode(st - set_io_port_base(ssb_pcicore_controller.io_map_base); - /* Give some time to the PCI controller to configure itself with the new - * values. Not waiting at this point causes crashes of the machine. */ -- mdelay(10); -+ mdelay(300); - register_pci_controller(&ssb_pcicore_controller); - } - diff --git a/target/linux/bcm47xx/patches-5.10/999-wl_exports.patch b/target/linux/bcm47xx/patches-5.10/999-wl_exports.patch deleted file mode 100644 index 48c6a47871..0000000000 --- a/target/linux/bcm47xx/patches-5.10/999-wl_exports.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/firmware/broadcom/bcm47xx_nvram.c -+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c -@@ -30,7 +30,8 @@ struct nvram_header { - u32 config_ncdl; /* ncdl values for memc */ - }; - --static char nvram_buf[NVRAM_SPACE]; -+char nvram_buf[NVRAM_SPACE]; -+EXPORT_SYMBOL(nvram_buf); - static size_t nvram_len; - static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000}; - static int cfe_env; ---- a/arch/mips/mm/cache.c -+++ b/arch/mips/mm/cache.c -@@ -61,6 +61,9 @@ void (*_dma_cache_wback_inv)(unsigned lo - void (*_dma_cache_wback)(unsigned long start, unsigned long size); - void (*_dma_cache_inv)(unsigned long start, unsigned long size); - -+EXPORT_SYMBOL(_dma_cache_wback_inv); -+EXPORT_SYMBOL(_dma_cache_inv); -+ - #endif /* CONFIG_DMA_NONCOHERENT */ - - /* diff --git a/target/linux/bcm4908/config-5.10 b/target/linux/bcm4908/config-5.10 deleted file mode 100644 index 1564123ca7..0000000000 --- a/target/linux/bcm4908/config-5.10 +++ /dev/null @@ -1,234 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_BCM4908=y -CONFIG_ARCH_BCMBCA=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_PSCI_FW=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_B53=y -CONFIG_BCM4908_ENET=y -CONFIG_BCM7038_WDT=y -CONFIG_BCM7XXX_PHY=y -CONFIG_BCM_NET_PHYLIB=y -CONFIG_BCM_PMB=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_PM=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200" -CONFIG_CMDLINE_FORCE=y -CONFIG_COMMON_CLK=y -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_EDAC_SUPPORT=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_BRCMSTB=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_LEDS_BCM63138=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BCM_UNIMAC=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_BRCM_U_BOOT=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_BRCMNAND=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_OF_PARTS_BCM4908=y -# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPLIT_CFE_BOOTFS=y -# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_BCM_SF2=y -CONFIG_NET_DSA_TAG_BRCM=y -CONFIG_NET_DSA_TAG_BRCM_COMMON=y -CONFIG_NET_DSA_TAG_BRCM_LEGACY=y -CONFIG_NET_DSA_TAG_BRCM_PREPEND=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NO_IOPORT_MAP=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_NVMEM_U_BOOT_ENV=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PADATA=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_BRCM_USB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_BCM4908=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RELOCATABLE=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_BCM63XX=y -CONFIG_SERIAL_BCM63XX_CONSOLE=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB_SUPPORT=y -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/bcm4908/files-5.10/drivers/net/ethernet/broadcom/unimac.h b/target/linux/bcm4908/files-5.10/drivers/net/ethernet/broadcom/unimac.h deleted file mode 100644 index 585a852862..0000000000 --- a/target/linux/bcm4908/files-5.10/drivers/net/ethernet/broadcom/unimac.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __UNIMAC_H -#define __UNIMAC_H - -#define UMAC_HD_BKP_CTRL 0x004 -#define HD_FC_EN (1 << 0) -#define HD_FC_BKOFF_OK (1 << 1) -#define IPG_CONFIG_RX_SHIFT 2 -#define IPG_CONFIG_RX_MASK 0x1F -#define UMAC_CMD 0x008 -#define CMD_TX_EN (1 << 0) -#define CMD_RX_EN (1 << 1) -#define CMD_SPEED_10 0 -#define CMD_SPEED_100 1 -#define CMD_SPEED_1000 2 -#define CMD_SPEED_2500 3 -#define CMD_SPEED_SHIFT 2 -#define CMD_SPEED_MASK 3 -#define CMD_PROMISC (1 << 4) -#define CMD_PAD_EN (1 << 5) -#define CMD_CRC_FWD (1 << 6) -#define CMD_PAUSE_FWD (1 << 7) -#define CMD_RX_PAUSE_IGNORE (1 << 8) -#define CMD_TX_ADDR_INS (1 << 9) -#define CMD_HD_EN (1 << 10) -#define CMD_SW_RESET_OLD (1 << 11) -#define CMD_SW_RESET (1 << 13) -#define CMD_LCL_LOOP_EN (1 << 15) -#define CMD_AUTO_CONFIG (1 << 22) -#define CMD_CNTL_FRM_EN (1 << 23) -#define CMD_NO_LEN_CHK (1 << 24) -#define CMD_RMT_LOOP_EN (1 << 25) -#define CMD_RX_ERR_DISC (1 << 26) -#define CMD_PRBL_EN (1 << 27) -#define CMD_TX_PAUSE_IGNORE (1 << 28) -#define CMD_TX_RX_EN (1 << 29) -#define CMD_RUNT_FILTER_DIS (1 << 30) -#define UMAC_MAC0 0x00c -#define UMAC_MAC1 0x010 -#define UMAC_MAX_FRAME_LEN 0x014 -#define UMAC_PAUSE_QUANTA 0x018 -#define UMAC_MODE 0x044 -#define MODE_LINK_STATUS (1 << 5) -#define UMAC_FRM_TAG0 0x048 /* outer tag */ -#define UMAC_FRM_TAG1 0x04c /* inner tag */ -#define UMAC_TX_IPG_LEN 0x05c -#define UMAC_EEE_CTRL 0x064 -#define EN_LPI_RX_PAUSE (1 << 0) -#define EN_LPI_TX_PFC (1 << 1) -#define EN_LPI_TX_PAUSE (1 << 2) -#define EEE_EN (1 << 3) -#define RX_FIFO_CHECK (1 << 4) -#define EEE_TX_CLK_DIS (1 << 5) -#define DIS_EEE_10M (1 << 6) -#define LP_IDLE_PREDICTION_MODE (1 << 7) -#define UMAC_EEE_LPI_TIMER 0x068 -#define UMAC_EEE_WAKE_TIMER 0x06C -#define UMAC_EEE_REF_COUNT 0x070 -#define EEE_REFERENCE_COUNT_MASK 0xffff -#define UMAC_RX_IPG_INV 0x078 -#define UMAC_MACSEC_PROG_TX_CRC 0x310 -#define UMAC_MACSEC_CTRL 0x314 -#define UMAC_PAUSE_CTRL 0x330 -#define UMAC_TX_FLUSH 0x334 -#define UMAC_RX_FIFO_STATUS 0x338 -#define UMAC_TX_FIFO_STATUS 0x33c - -#endif diff --git a/target/linux/bcm4908/patches-5.10/030-v5.11-0001-dt-bindings-arm-bcm-document-BCM4908-bindings.patch b/target/linux/bcm4908/patches-5.10/030-v5.11-0001-dt-bindings-arm-bcm-document-BCM4908-bindings.patch deleted file mode 100644 index 66726cbf0b..0000000000 --- a/target/linux/bcm4908/patches-5.10/030-v5.11-0001-dt-bindings-arm-bcm-document-BCM4908-bindings.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 2f8913a7b17efd3a116825160a2d3a6610444587 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 12 Nov 2020 16:08:31 +0100 -Subject: [PATCH] dt-bindings: arm: bcm: document BCM4908 bindings -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 is a new family that includes BCM4906, BCM4908 and BCM49408. -It's mostly used in home routers and often replaces Northstar in vendors -portfolio. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../bindings/arm/bcm/brcm,bcm4908.yaml | 38 +++++++++++++++++++ - 1 file changed, 38 insertions(+) - create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml -@@ -0,0 +1,38 @@ -+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4908.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM4908 device tree bindings -+ -+description: -+ Broadcom BCM4906 / BCM4908 / BCM49408 Wi-Fi/network SoCs with Brahma CPUs. -+ -+maintainers: -+ - Rafał Miłecki -+ -+properties: -+ $nodename: -+ const: '/' -+ compatible: -+ oneOf: -+ - description: BCM4906 based boards -+ items: -+ - const: brcm,bcm4906 -+ - const: brcm,bcm4908 -+ -+ - description: BCM4908 based boards -+ items: -+ - enum: -+ - asus,gt-ac5300 -+ - const: brcm,bcm4908 -+ -+ - description: BCM49408 based boards -+ items: -+ - const: brcm,bcm49408 -+ - const: brcm,bcm4908 -+ -+additionalProperties: true -+ -+... diff --git a/target/linux/bcm4908/patches-5.10/030-v5.11-0002-arm64-dts-broadcom-add-BCM4908-and-Asus-GT-AC5300-ea.patch b/target/linux/bcm4908/patches-5.10/030-v5.11-0002-arm64-dts-broadcom-add-BCM4908-and-Asus-GT-AC5300-ea.patch deleted file mode 100644 index fd7d6a5f11..0000000000 --- a/target/linux/bcm4908/patches-5.10/030-v5.11-0002-arm64-dts-broadcom-add-BCM4908-and-Asus-GT-AC5300-ea.patch +++ /dev/null @@ -1,307 +0,0 @@ -From 2961f69f151c0a6771f55cef46398fe49ca20902 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 12 Nov 2020 16:08:32 +0100 -Subject: [PATCH] arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early - DTS files -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -They don't descibe hardware fully yet but it's enough to boot a system. - -Some missing blocks: -1. PMC (Power Management Controller?) -2. Ethernet -3. Crypto -4. Thermal - -Asus DTS is missing defining full NAND partitions layout and buttons. - -Further changes will fill those gaps as soon as required bindings will -be found / tested / added. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/Makefile | 1 + - arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 2 + - .../bcm4908/bcm4908-asus-gt-ac5300.dts | 66 +++++++ - .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 187 ++++++++++++++++++ - 4 files changed, 256 insertions(+) - create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile - create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts - create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi - ---- a/arch/arm64/boot/dts/broadcom/Makefile -+++ b/arch/arm64/boot/dts/broadcom/Makefile -@@ -5,5 +5,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp - bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb - -+subdir-y += bcm4908 - subdir-y += northstar2 - subdir-y += stingray ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -@@ -0,0 +1,66 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include -+#include -+ -+#include "bcm4908.dtsi" -+ -+/ { -+ compatible = "asus,gt-ac5300", "brcm,bcm4908"; -+ model = "Asus GT-AC5300"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00 0x00 0x00 0x40000000>; -+ }; -+ -+ gpio-keys-polled { -+ compatible = "gpio-keys-polled"; -+ poll-interval = <100>; -+ -+ wifi { -+ label = "WiFi"; -+ linux,code = ; -+ gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wps { -+ label = "WPS"; -+ linux,code = ; -+ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; -+ }; -+ -+ restart { -+ label = "Reset"; -+ linux,code = ; -+ gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; -+ }; -+ -+ brightness { -+ label = "LEDs"; -+ linux,code = ; -+ gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&nandcs { -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; -+ nand-on-flash-bbt; -+ brcm,nand-has-wp; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "cferom"; -+ reg = <0x0 0x100000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -0,0 +1,187 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include -+#include -+ -+/dts-v1/; -+ -+/ { -+ interrupt-parent = <&gic>; -+ -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "brcm,brahma-b53"; -+ reg = <0x0>; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "brcm,brahma-b53"; -+ reg = <0x1>; -+ enable-method = "spin-table"; -+ cpu-release-addr = <0x0 0xfff8>; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "brcm,brahma-b53"; -+ reg = <0x2>; -+ enable-method = "spin-table"; -+ cpu-release-addr = <0x0 0xfff8>; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "brcm,brahma-b53"; -+ reg = <0x3>; -+ enable-method = "spin-table"; -+ cpu-release-addr = <0x0 0xfff8>; -+ next-level-cache = <&l2>; -+ }; -+ -+ l2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ axi@81000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x00 0x00 0x81000000 0x4000>; -+ -+ gic: interrupt-controller@1000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ #address-cells = <0>; -+ interrupt-controller; -+ reg = <0x1000 0x1000>, -+ <0x2000 0x2000>; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -+ }; -+ -+ clocks { -+ periph_clk: periph_clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <50000000>; -+ clock-output-names = "periph"; -+ }; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x00 0x00 0x80000000 0x10000>; -+ -+ usb@c300 { -+ compatible = "generic-ehci"; -+ reg = <0xc300 0x100>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ usb@c400 { -+ compatible = "generic-ohci"; -+ reg = <0xc400 0x100>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ -+ usb@d000 { -+ compatible = "generic-xhci"; -+ reg = <0xd000 0x8c8>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ }; -+ -+ bus@ff800000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x00 0x00 0xff800000 0x3000>; -+ -+ timer: timer@400 { -+ compatible = "brcm,bcm6328-timer", "syscon"; -+ reg = <0x400 0x3c>; -+ }; -+ -+ gpio0: gpio-controller@500 { -+ compatible = "brcm,bcm6345-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0x500 0x28>, <0x528 0x28>; -+ -+ #gpio-cells = <2>; -+ gpio-controller; -+ }; -+ -+ uart0: serial@640 { -+ compatible = "brcm,bcm6345-uart"; -+ reg = <0x640 0x18>; -+ interrupts = ; -+ clocks = <&periph_clk>; -+ clock-names = "periph"; -+ status = "okay"; -+ }; -+ -+ nand@1800 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; -+ reg = <0x1800 0x600>, <0x2000 0x10>; -+ reg-names = "nand", "nand-int-base"; -+ interrupts = ; -+ interrupt-names = "nand"; -+ status = "okay"; -+ -+ nandcs: nandcs@0 { -+ compatible = "brcm,nandcs"; -+ reg = <0>; -+ }; -+ }; -+ -+ reboot { -+ compatible = "syscon-reboot"; -+ regmap = <&timer>; -+ offset = <0x34>; -+ mask = <1>; -+ }; -+ }; -+}; diff --git a/target/linux/bcm4908/patches-5.10/030-v5.11-0003-v5.11-arm64-add-config-for-Broadcom-BCM4908-SoCs.patch b/target/linux/bcm4908/patches-5.10/030-v5.11-0003-v5.11-arm64-add-config-for-Broadcom-BCM4908-SoCs.patch deleted file mode 100644 index 962517a57e..0000000000 --- a/target/linux/bcm4908/patches-5.10/030-v5.11-0003-v5.11-arm64-add-config-for-Broadcom-BCM4908-SoCs.patch +++ /dev/null @@ -1,44 +0,0 @@ -From dccb22d078ebd098115e4f66bde1ee2249c8640b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 12 Nov 2020 16:08:30 +0100 -Subject: [PATCH] arm64: add config for Broadcom BCM4908 SoCs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add ARCH_BCM4908 config that can be used for compiling DTS files. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/Kconfig.platforms | 8 ++++++++ - arch/arm64/configs/defconfig | 1 + - 2 files changed, 9 insertions(+) - ---- a/arch/arm64/Kconfig.platforms -+++ b/arch/arm64/Kconfig.platforms -@@ -43,6 +43,14 @@ config ARCH_BCM2835 - This enables support for the Broadcom BCM2837 and BCM2711 SoC. - These SoCs are used in the Raspberry Pi 3 and 4 devices. - -+config ARCH_BCM4908 -+ bool "Broadcom BCM4908 family" -+ select GPIOLIB -+ help -+ This enables support for the Broadcom BCM4906, BCM4908 and -+ BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be -+ found in home routers. -+ - config ARCH_BCM_IPROC - bool "Broadcom iProc SoC Family" - select COMMON_CLK_IPROC ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -32,6 +32,7 @@ CONFIG_ARCH_AGILEX=y - CONFIG_ARCH_SUNXI=y - CONFIG_ARCH_ALPINE=y - CONFIG_ARCH_BCM2835=y -+CONFIG_ARCH_BCM4908=y - CONFIG_ARCH_BCM_IPROC=y - CONFIG_ARCH_BERLIN=y - CONFIG_ARCH_BRCMSTB=y diff --git a/target/linux/bcm4908/patches-5.10/031-v5.12-0001-dt-bindings-arm-bcm-document-Netgear-R8000P-binding.patch b/target/linux/bcm4908/patches-5.10/031-v5.12-0001-dt-bindings-arm-bcm-document-Netgear-R8000P-binding.patch deleted file mode 100644 index 24a0749c77..0000000000 --- a/target/linux/bcm4908/patches-5.10/031-v5.12-0001-dt-bindings-arm-bcm-document-Netgear-R8000P-binding.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 3a5da4f54801ac42837a0b3151fa8285e01e8b0e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 8 Dec 2020 08:03:03 +0100 -Subject: [PATCH] dt-bindings: arm: bcm: document Netgear R8000P binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's a BCM4906 based device. - -Signed-off-by: Rafał Miłecki -Acked-by: Rob Herring -Signed-off-by: Florian Fainelli ---- - Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml -+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml -@@ -19,6 +19,8 @@ properties: - oneOf: - - description: BCM4906 based boards - items: -+ - enum: -+ - netgear,r8000p - - const: brcm,bcm4906 - - const: brcm,bcm4908 - diff --git a/target/linux/bcm4908/patches-5.10/031-v5.12-0002-arm64-dts-broadcom-bcm4908-add-BCM4906-Netgear-R8000.patch b/target/linux/bcm4908/patches-5.10/031-v5.12-0002-arm64-dts-broadcom-bcm4908-add-BCM4906-Netgear-R8000.patch deleted file mode 100644 index 93fa2150af..0000000000 --- a/target/linux/bcm4908/patches-5.10/031-v5.12-0002-arm64-dts-broadcom-bcm4908-add-BCM4906-Netgear-R8000.patch +++ /dev/null @@ -1,104 +0,0 @@ -From c8b404fb05dcfadff477e49b7ea6b500e015f101 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 8 Dec 2020 08:03:04 +0100 -Subject: [PATCH 2/4] arm64: dts: broadcom: bcm4908: add BCM4906 Netgear R8000P - DTS files -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Netgear R8000P is home router based on BCM4906 that is a cheaper variant -of BCM4908 (e.g. 2 cores instead of 4). - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 1 + - .../bcm4908/bcm4906-netgear-r8000p.dts | 52 +++++++++++++++++++ - .../boot/dts/broadcom/bcm4908/bcm4906.dtsi | 18 +++++++ - 3 files changed, 71 insertions(+) - create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts - create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 -+dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb - dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -@@ -0,0 +1,52 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include -+#include -+#include -+ -+#include "bcm4906.dtsi" -+ -+/ { -+ compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908"; -+ model = "Netgear R8000P"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00 0x00 0x00 0x20000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ wps { -+ function = LED_FUNCTION_WPS; -+ color = ; -+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&nandcs { -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; -+ nand-on-flash-bbt; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "cferom"; -+ reg = <0x0 0x100000>; -+ }; -+ -+ partition@100000 { -+ label = "firmware"; -+ reg = <0x100000 0x4400000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include "bcm4908.dtsi" -+ -+/ { -+ cpus { -+ /delete-node/ cpu@2; -+ -+ /delete-node/ cpu@3; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ ; -+ interrupt-affinity = <&cpu0>, <&cpu1>; -+ }; -+}; diff --git a/target/linux/bcm4908/patches-5.10/031-v5.12-0003-arm64-dts-broadcom-bcm4908-use-proper-NAND-binding.patch b/target/linux/bcm4908/patches-5.10/031-v5.12-0003-arm64-dts-broadcom-bcm4908-use-proper-NAND-binding.patch deleted file mode 100644 index ccd260fadf..0000000000 --- a/target/linux/bcm4908/patches-5.10/031-v5.12-0003-arm64-dts-broadcom-bcm4908-use-proper-NAND-binding.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 56098be85d19cd56b59d7b3854ea035cc8cb9e95 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 8 Dec 2020 11:49:50 +0100 -Subject: [PATCH 3/4] arm64: dts: broadcom: bcm4908: use proper NAND binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 has controller that needs different IRQ handling just like the -BCM63138. Describe it properly. - -On Linux this change fixes: -brcmstb_nand ff801800.nand: timeout waiting for command 0x9 -brcmstb_nand ff801800.nand: intfc status d0000000 - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -164,7 +164,7 @@ - nand@1800 { - #address-cells = <1>; - #size-cells = <0>; -- compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; -+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; - reg = <0x1800 0x600>, <0x2000 0x10>; - reg-names = "nand", "nand-int-base"; - interrupts = ; diff --git a/target/linux/bcm4908/patches-5.10/031-v5.12-0004-arm64-dts-broadcom-bcm4908-describe-PCIe-reset-contr.patch b/target/linux/bcm4908/patches-5.10/031-v5.12-0004-arm64-dts-broadcom-bcm4908-describe-PCIe-reset-contr.patch deleted file mode 100644 index 8ce4d69d8f..0000000000 --- a/target/linux/bcm4908/patches-5.10/031-v5.12-0004-arm64-dts-broadcom-bcm4908-describe-PCIe-reset-contr.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 1b88c6ed26a1aa1d68d1661404e6e939709ff530 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 10 Dec 2020 08:21:54 +0100 -Subject: [PATCH 4/4] arm64: dts: broadcom: bcm4908: describe PCIe reset - controller -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This reset controller is a single register in the Broadcom's MISC block. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -177,6 +177,21 @@ - }; - }; - -+ misc@2600 { -+ compatible = "brcm,misc", "simple-mfd"; -+ reg = <0x2600 0xe4>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x00 0x2600 0xe4>; -+ -+ reset-controller@2644 { -+ compatible = "brcm,bcm4908-misc-pcie-reset"; -+ reg = <0x44 0x04>; -+ #reset-cells = <1>; -+ }; -+ }; -+ - reboot { - compatible = "syscon-reboot"; - regmap = <&timer>; diff --git a/target/linux/bcm4908/patches-5.10/031-v5.12-0005-arm64-dts-broadcom-bcm4908-describe-internal-switch.patch b/target/linux/bcm4908/patches-5.10/031-v5.12-0005-arm64-dts-broadcom-bcm4908-describe-internal-switch.patch deleted file mode 100644 index f80dc239bc..0000000000 --- a/target/linux/bcm4908/patches-5.10/031-v5.12-0005-arm64-dts-broadcom-bcm4908-describe-internal-switch.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 527a3ac9bdf81da4b7160ce3cea57f28a0e5eb64 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 13 Jan 2021 12:14:06 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe internal switch -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 has internal switch with 5 GPHYs. Ports 0 - 3 are always -connected to the internal PHYs. Remaining ports depend on device setup. - -Asus GT-AC5300 has an extra switch with its PHYs accessible using the -internal MDIO. - -CPU port and Ethernet interface remain to be documented. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../bcm4908/bcm4908-asus-gt-ac5300.dts | 51 +++++++++++ - .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 85 ++++++++++++++++++- - 2 files changed, 135 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -@@ -44,6 +44,57 @@ - }; - }; - -+&ports { -+ port@0 { -+ label = "lan2"; -+ }; -+ -+ port@1 { -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ label = "lan6"; -+ }; -+ -+ port@3 { -+ label = "lan5"; -+ }; -+ -+ /* External BCM53134S switch */ -+ port@7 { -+ label = "sw"; -+ reg = <7>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+}; -+ -+&mdio { -+ /* lan8 */ -+ ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ /* lan7 */ -+ ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ /* lan4 */ -+ ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ /* lan3 */ -+ ethernet-phy@3 { -+ reg = <3>; -+ }; -+}; -+ - &nandcs { - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -108,7 +108,7 @@ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; -- ranges = <0x00 0x00 0x80000000 0x10000>; -+ ranges = <0x00 0x00 0x80000000 0xd0000>; - - usb@c300 { - compatible = "generic-ehci"; -@@ -130,6 +130,89 @@ - interrupts = ; - status = "disabled"; - }; -+ -+ ethernet-switch@80000 { -+ compatible = "simple-bus"; -+ #size-cells = <1>; -+ #address-cells = <1>; -+ ranges = <0 0x80000 0x50000>; -+ -+ ethernet-switch@0 { -+ compatible = "brcm,bcm4908-switch"; -+ reg = <0x0 0x40000>, -+ <0x40000 0x110>, -+ <0x40340 0x30>, -+ <0x40380 0x30>, -+ <0x40600 0x34>, -+ <0x40800 0x208>; -+ reg-names = "core", "reg", "intrl2_0", -+ "intrl2_1", "fcb", "acb"; -+ interrupts = , -+ ; -+ brcm,num-gphy = <5>; -+ brcm,num-rgmii-ports = <2>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ports: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ phy-mode = "internal"; -+ phy-handle = <&phy8>; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ phy-mode = "internal"; -+ phy-handle = <&phy9>; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ phy-mode = "internal"; -+ phy-handle = <&phy10>; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ phy-mode = "internal"; -+ phy-handle = <&phy11>; -+ }; -+ }; -+ }; -+ -+ mdio: mdio@405c0 { -+ compatible = "brcm,unimac-mdio"; -+ reg = <0x405c0 0x8>; -+ reg-names = "mdio"; -+ #size-cells = <0>; -+ #address-cells = <1>; -+ -+ phy8: ethernet-phy@8 { -+ reg = <8>; -+ }; -+ -+ phy9: ethernet-phy@9 { -+ reg = <9>; -+ }; -+ -+ phy10: ethernet-phy@a { -+ reg = <10>; -+ }; -+ -+ phy11: ethernet-phy@b { -+ reg = <11>; -+ }; -+ -+ phy12: ethernet-phy@c { -+ reg = <12>; -+ }; -+ }; -+ }; - }; - - bus@ff800000 { diff --git a/target/linux/bcm4908/patches-5.10/031-v5.12-0006-arm64-dts-broadcom-bcm4908-describe-PMB-block.patch b/target/linux/bcm4908/patches-5.10/031-v5.12-0006-arm64-dts-broadcom-bcm4908-describe-PMB-block.patch deleted file mode 100644 index c1a9c35837..0000000000 --- a/target/linux/bcm4908/patches-5.10/031-v5.12-0006-arm64-dts-broadcom-bcm4908-describe-PMB-block.patch +++ /dev/null @@ -1,50 +0,0 @@ -From edcf90801c8e58bd6306d85a4e714a6f09f452df Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 13 Jan 2021 12:15:47 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe PMB block -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -PMB (Power Management Bus) controls powering connected devices (e.g. -PCIe, USB, SATA). In BCM4908 it's a part of the PROCMON block. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -108,7 +108,7 @@ - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; -- ranges = <0x00 0x00 0x80000000 0xd0000>; -+ ranges = <0x00 0x00 0x80000000 0x281000>; - - usb@c300 { - compatible = "generic-ehci"; -@@ -213,6 +213,21 @@ - }; - }; - }; -+ -+ procmon: syscon@280000 { -+ compatible = "simple-bus"; -+ reg = <0x280000 0x1000>; -+ ranges; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ power-controller@2800c0 { -+ compatible = "brcm,bcm4908-pmb"; -+ reg = <0x2800c0 0x40>; -+ #power-domain-cells = <1>; -+ }; -+ }; - }; - - bus@ff800000 { diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0001-arm64-dts-broadcom-bcm4908-describe-USB-PHY.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0001-arm64-dts-broadcom-bcm4908-describe-USB-PHY.patch deleted file mode 100644 index edf2ca6a38..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0001-arm64-dts-broadcom-bcm4908-describe-USB-PHY.patch +++ /dev/null @@ -1,134 +0,0 @@ -From 3c321ba794ca6383a4aa68ea803e18cc6ad44412 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 19 Feb 2021 06:50:26 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe USB PHY -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 uses slightly modified STB family USB PHY. It handles OHCI/EHCI -and XHCI. It requires powering up using the PMB. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../bcm4908/bcm4906-netgear-r8000p.dts | 17 +++++++++++++ - .../bcm4908/bcm4908-asus-gt-ac5300.dts | 17 +++++++++++++ - .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 25 ++++++++++++++++--- - 3 files changed, 55 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -@@ -26,6 +26,23 @@ - }; - }; - -+&usb_phy { -+ brcm,ioc = <1>; -+ status = "okay"; -+}; -+ -+&ehci { -+ status = "okay"; -+}; -+ -+&ohci { -+ status = "okay"; -+}; -+ -+&xhci { -+ status = "okay"; -+}; -+ - &nandcs { - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -@@ -44,6 +44,23 @@ - }; - }; - -+&usb_phy { -+ brcm,ioc = <1>; -+ status = "okay"; -+}; -+ -+&ehci { -+ status = "okay"; -+}; -+ -+&ohci { -+ status = "okay"; -+}; -+ -+&xhci { -+ status = "okay"; -+}; -+ - &ports { - port@0 { - label = "lan2"; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -2,6 +2,8 @@ - - #include - #include -+#include -+#include - - /dts-v1/; - -@@ -110,24 +112,39 @@ - #size-cells = <1>; - ranges = <0x00 0x00 0x80000000 0x281000>; - -- usb@c300 { -+ usb_phy: usb-phy@c200 { -+ compatible = "brcm,bcm4908-usb-phy"; -+ reg = <0xc200 0x100>; -+ reg-names = "ctrl"; -+ power-domains = <&pmb BCM_PMB_HOST_USB>; -+ dr_mode = "host"; -+ brcm,has-xhci; -+ brcm,has-eohci; -+ #phy-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ ehci: usb@c300 { - compatible = "generic-ehci"; - reg = <0xc300 0x100>; - interrupts = ; -+ phys = <&usb_phy PHY_TYPE_USB2>; - status = "disabled"; - }; - -- usb@c400 { -+ ohci: usb@c400 { - compatible = "generic-ohci"; - reg = <0xc400 0x100>; - interrupts = ; -+ phys = <&usb_phy PHY_TYPE_USB2>; - status = "disabled"; - }; - -- usb@d000 { -+ xhci: usb@d000 { - compatible = "generic-xhci"; - reg = <0xd000 0x8c8>; - interrupts = ; -+ phys = <&usb_phy PHY_TYPE_USB3>; - status = "disabled"; - }; - -@@ -222,7 +239,7 @@ - #address-cells = <1>; - #size-cells = <1>; - -- power-controller@2800c0 { -+ pmb: power-controller@2800c0 { - compatible = "brcm,bcm4908-pmb"; - reg = <0x2800c0 0x40>; - #power-domain-cells = <1>; diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0002-arm64-dts-broadcom-bcm4908-describe-Ethernet-control.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0002-arm64-dts-broadcom-bcm4908-describe-Ethernet-control.patch deleted file mode 100644 index 6c41e3d797..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0002-arm64-dts-broadcom-bcm4908-describe-Ethernet-control.patch +++ /dev/null @@ -1,51 +0,0 @@ -From b1bbe48eec190b6a35f400c5a3ec6b0fc8fc3fe6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 19 Feb 2021 06:50:27 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe Ethernet controller -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 SoCs have an integrated Ethernet controller. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -112,6 +112,14 @@ - #size-cells = <1>; - ranges = <0x00 0x00 0x80000000 0x281000>; - -+ enet: ethernet@2000 { -+ compatible = "brcm,bcm4908-enet"; -+ reg = <0x2000 0x1000>; -+ -+ interrupts = ; -+ interrupt-names = "rx"; -+ }; -+ - usb_phy: usb-phy@c200 { - compatible = "brcm,bcm4908-usb-phy"; - reg = <0xc200 0x100>; -@@ -199,6 +207,17 @@ - phy-mode = "internal"; - phy-handle = <&phy11>; - }; -+ -+ port@8 { -+ reg = <8>; -+ phy-mode = "internal"; -+ ethernet = <&enet>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; - }; - }; - diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0003-arm64-dts-broadcom-bcm4908-describe-Netgear-R8000P-s.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0003-arm64-dts-broadcom-bcm4908-describe-Netgear-R8000P-s.patch deleted file mode 100644 index 9c7f9cee6c..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0003-arm64-dts-broadcom-bcm4908-describe-Netgear-R8000P-s.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 406e98afffe975982f63ea5d21bf9a47a81b56ee Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 19 Feb 2021 06:50:28 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe Netgear R8000P switch -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -R8000P model has 4 LAN ports and 1 WAN port. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../bcm4908/bcm4906-netgear-r8000p.dts | 25 +++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -@@ -43,6 +43,31 @@ - status = "okay"; - }; - -+&ports { -+ port@0 { -+ label = "lan4"; -+ }; -+ -+ port@1 { -+ label = "lan3"; -+ }; -+ -+ port@2 { -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ label = "lan1"; -+ }; -+ -+ port@7 { -+ reg = <7>; -+ phy-mode = "internal"; -+ phy-handle = <&phy12>; -+ label = "wan"; -+ }; -+}; -+ - &nandcs { - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0004-arm64-dts-broadcom-bcm4908-add-remaining-Netgear-R80.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0004-arm64-dts-broadcom-bcm4908-add-remaining-Netgear-R80.patch deleted file mode 100644 index 56249c82f8..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0004-arm64-dts-broadcom-bcm4908-add-remaining-Netgear-R80.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 6224415c0389ba6661825746312163a64ece8f3a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 19 Feb 2021 06:50:29 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining Netgear R8000P - LEDs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There are a few more GPIO connected LEDs there didn't get described -initially. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../bcm4908/bcm4906-netgear-r8000p.dts | 50 ++++++++++++++++++- - 1 file changed, 49 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -@@ -18,11 +18,59 @@ - leds { - compatible = "gpio-leds"; - -- wps { -+ led-power-white { -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-power-amber { -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-wps { - function = LED_FUNCTION_WPS; - color = ; - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - }; -+ -+ led-2ghz { -+ function = "2ghz"; -+ color = ; -+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-5ghz-1 { -+ function = "5ghz-1"; -+ color = ; -+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-5ghz-2 { -+ function = "5ghz-2"; -+ color = ; -+ gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-usb2 { -+ function = "usb2"; -+ color = ; -+ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-usb3 { -+ function = "usb3"; -+ color = ; -+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-wifi { -+ function = "wifi"; -+ color = ; -+ gpios = <&gpio0 56 GPIO_ACTIVE_LOW>; -+ }; - }; - }; - diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0005-arm64-dts-broadcom-bcm4908-describe-firmware-partiti.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0005-arm64-dts-broadcom-bcm4908-describe-firmware-partiti.patch deleted file mode 100644 index d03adc1743..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0005-arm64-dts-broadcom-bcm4908-describe-firmware-partiti.patch +++ /dev/null @@ -1,55 +0,0 @@ -From cbaca2c467dc25a163107e14a53b7925214eab17 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 19 Feb 2021 06:50:30 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe firmware partitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 bootloader supports multiple firmware partitions and has its own -bindings defined for them. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts | 1 + - .../dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 12 +++++++++++- - 2 files changed, 12 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -@@ -135,6 +135,7 @@ - }; - - partition@100000 { -+ compatible = "brcm,bcm4908-firmware"; - label = "firmware"; - reg = <0x100000 0x4400000>; - }; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -@@ -122,7 +122,7 @@ - #size-cells = <0>; - - partitions { -- compatible = "fixed-partitions"; -+ compatible = "brcm,bcm4908-partitions"; - #address-cells = <1>; - #size-cells = <1>; - -@@ -130,5 +130,15 @@ - label = "cferom"; - reg = <0x0 0x100000>; - }; -+ -+ partition@100000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x100000 0x5700000>; -+ }; -+ -+ partition@5800000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x5800000 0x5700000>; -+ }; - }; - }; diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0006-arm64-dts-broadcom-bcm4908-fix-switch-parent-node-na.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0006-arm64-dts-broadcom-bcm4908-fix-switch-parent-node-na.patch deleted file mode 100644 index 8b95fc2759..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0006-arm64-dts-broadcom-bcm4908-fix-switch-parent-node-na.patch +++ /dev/null @@ -1,30 +0,0 @@ -From a348ff97ffb840b9d74b0e64b3e0e6002187d224 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 9 Mar 2021 19:44:09 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: fix switch parent node name -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Ethernet switch and MDIO are grouped using "simple-bus". It's not -allowed to use "ethernet-switch" node name as it isn't a switch. Replace -it with "bus". - -Fixes: 527a3ac9bdf8 ("arm64: dts: broadcom: bcm4908: describe internal switch") -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -156,7 +156,7 @@ - status = "disabled"; - }; - -- ethernet-switch@80000 { -+ bus@80000 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0007-dt-bindings-arm-bcm-document-TP-Link-Archer-C2300-bi.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0007-dt-bindings-arm-bcm-document-TP-Link-Archer-C2300-bi.patch deleted file mode 100644 index 07d4121ef1..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0007-dt-bindings-arm-bcm-document-TP-Link-Archer-C2300-bi.patch +++ /dev/null @@ -1,27 +0,0 @@ -From b3de2a12d1a61d90a4d86c9840acc7d05066137f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 10 Mar 2021 08:46:02 +0100 -Subject: [PATCH] dt-bindings: arm: bcm: document TP-Link Archer C2300 binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -One more BCM4906 based device. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Rob Herring -Signed-off-by: Florian Fainelli ---- - Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml -+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml -@@ -21,6 +21,7 @@ properties: - items: - - enum: - - netgear,r8000p -+ - tplink,archer-c2300-v1 - - const: brcm,bcm4906 - - const: brcm,bcm4908 - diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0008-arm64-dts-broadcom-bcm4908-add-TP-Link-Archer-C2300-.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0008-arm64-dts-broadcom-bcm4908-add-TP-Link-Archer-C2300-.patch deleted file mode 100644 index 0dd7f2301f..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0008-arm64-dts-broadcom-bcm4908-add-TP-Link-Archer-C2300-.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 6a30934a5470a0ce7ea32b0c6b600accfae94b1a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 10 Mar 2021 08:46:03 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add TP-Link Archer C2300 V1 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Archer C2300 V1 is a home router based on the BCM4906 (2 CPU cores). It -has 512 MiB of RAM, NAND flash, USB 2.0 and USB 3.0 ports, 4 LAN ports, -1 WAN port. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 1 + - .../bcm4906-tplink-archer-c2300-v1.dts | 182 ++++++++++++++++++ - 2 files changed, 183 insertions(+) - create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb -+dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb - dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts -@@ -0,0 +1,182 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include -+#include -+#include -+ -+#include "bcm4906.dtsi" -+ -+/ { -+ compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908"; -+ model = "TP-Link Archer C2300 V1"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00 0x00 0x00 0x20000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-power { -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-2ghz { -+ function = "2ghz"; -+ color = ; -+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-5ghz { -+ function = "5ghz"; -+ color = ; -+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-wan-amber { -+ function = LED_FUNCTION_WAN; -+ color = ; -+ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-wan-blue { -+ function = LED_FUNCTION_WAN; -+ color = ; -+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-lan { -+ function = LED_FUNCTION_LAN; -+ color = ; -+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-wps { -+ function = LED_FUNCTION_WPS; -+ color = ; -+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-usb2 { -+ function = "usb2"; -+ color = ; -+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-usb3 { -+ function = "usbd3"; -+ color = ; -+ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-brightness { -+ function = LED_FUNCTION_BACKLIGHT; -+ color = ; -+ gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-keys-polled { -+ compatible = "gpio-keys-polled"; -+ poll-interval = <100>; -+ -+ brightness { -+ label = "LEDs"; -+ linux,code = ; -+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wps { -+ label = "WPS"; -+ linux,code = ; -+ gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wifi { -+ label = "WiFi"; -+ linux,code = ; -+ gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; -+ }; -+ -+ restart { -+ label = "Reset"; -+ linux,code = ; -+ gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&usb_phy { -+ brcm,ioc = <1>; -+ status = "okay"; -+}; -+ -+&ehci { -+ status = "okay"; -+}; -+ -+&ohci { -+ status = "okay"; -+}; -+ -+&xhci { -+ status = "okay"; -+}; -+ -+&ports { -+ port@0 { -+ label = "lan4"; -+ }; -+ -+ port@1 { -+ label = "lan3"; -+ }; -+ -+ port@2 { -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ label = "lan1"; -+ }; -+ -+ port@7 { -+ reg = <7>; -+ phy-mode = "internal"; -+ phy-handle = <&phy12>; -+ label = "wan"; -+ }; -+}; -+ -+&nandcs { -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; -+ nand-on-flash-bbt; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ partitions { -+ compatible = "brcm,bcm4908-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "cferom"; -+ reg = <0x0 0x100000>; -+ }; -+ -+ partition@100000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x100000 0x3900000>; -+ }; -+ -+ partition@5800000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x3a00000 0x3900000>; -+ }; -+ }; -+}; diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0009-arm64-dts-broadcom-bcm4908-set-Asus-GT-AC5300-port-7.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0009-arm64-dts-broadcom-bcm4908-set-Asus-GT-AC5300-port-7.patch deleted file mode 100644 index 30def36c39..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0009-arm64-dts-broadcom-bcm4908-set-Asus-GT-AC5300-port-7.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 5ccb9f9cf05bbd729430c6d6d30d40c96a15c56a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 12 Mar 2021 12:01:20 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: set Asus GT-AC5300 port 7 PHY - mode -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Port 7 is connected to the external BCM53134S switch using RGMII. - -Fixes: 527a3ac9bdf8 ("arm64: dts: broadcom: bcm4908: describe internal switch") -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -@@ -82,6 +82,7 @@ - port@7 { - label = "sw"; - reg = <7>; -+ phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0010-arm64-dts-broadcom-bcm4908-add-Ethernet-TX-irq.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0010-arm64-dts-broadcom-bcm4908-add-Ethernet-TX-irq.patch deleted file mode 100644 index 9ba30b3a14..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0010-arm64-dts-broadcom-bcm4908-add-Ethernet-TX-irq.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 5337af7918bedde9713cd223ce5df74b3d6c7d7a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 17 Mar 2021 09:16:31 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Ethernet TX irq -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This hardware supports two interrupts, one per DMA channel (RX and TX). - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -116,8 +116,9 @@ - compatible = "brcm,bcm4908-enet"; - reg = <0x2000 0x1000>; - -- interrupts = ; -- interrupt-names = "rx"; -+ interrupts = , -+ ; -+ interrupt-names = "rx", "tx"; - }; - - usb_phy: usb-phy@c200 { diff --git a/target/linux/bcm4908/patches-5.10/032-v5.13-0011-arm64-dts-broadcom-bcm4908-add-Ethernet-MAC-addr.patch b/target/linux/bcm4908/patches-5.10/032-v5.13-0011-arm64-dts-broadcom-bcm4908-add-Ethernet-MAC-addr.patch deleted file mode 100644 index 67f30c8213..0000000000 --- a/target/linux/bcm4908/patches-5.10/032-v5.13-0011-arm64-dts-broadcom-bcm4908-add-Ethernet-MAC-addr.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 9f01f5cdb548352418b34ce77db02a560fe2913b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 29 Mar 2021 17:45:14 +0200 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Ethernet MAC addr -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -On most BCM4908 devices MAC address can be read from the bootloader -binary section containing device settings. Use NVMEM to describe that. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../broadcom/bcm4908/bcm4906-netgear-r8000p.dts | 14 ++++++++++++++ - .../broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 14 ++++++++++++++ - 2 files changed, 28 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -@@ -74,6 +74,11 @@ - }; - }; - -+&enet { -+ nvmem-cells = <&base_mac_addr>; -+ nvmem-cell-names = "mac-address"; -+}; -+ - &usb_phy { - brcm,ioc = <1>; - status = "okay"; -@@ -130,8 +135,17 @@ - #size-cells = <1>; - - partition@0 { -+ compatible = "nvmem-cells"; - label = "cferom"; - reg = <0x0 0x100000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x0 0x100000>; -+ -+ base_mac_addr: mac@106a0 { -+ reg = <0x106a0 0x6>; -+ }; - }; - - partition@100000 { ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -@@ -44,6 +44,11 @@ - }; - }; - -+&enet { -+ nvmem-cells = <&base_mac_addr>; -+ nvmem-cell-names = "mac-address"; -+}; -+ - &usb_phy { - brcm,ioc = <1>; - status = "okay"; -@@ -128,8 +133,17 @@ - #size-cells = <1>; - - partition@0 { -+ compatible = "nvmem-cells"; - label = "cferom"; - reg = <0x0 0x100000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x0 0x100000>; -+ -+ base_mac_addr: mac@106a0 { -+ reg = <0x106a0 0x6>; -+ }; - }; - - partition@100000 { diff --git a/target/linux/bcm4908/patches-5.10/033-v5.14-0001-ARM-dts-BCM5301X-Fix-NAND-nodes-names.patch b/target/linux/bcm4908/patches-5.10/033-v5.14-0001-ARM-dts-BCM5301X-Fix-NAND-nodes-names.patch deleted file mode 100644 index 757b2c439d..0000000000 --- a/target/linux/bcm4908/patches-5.10/033-v5.14-0001-ARM-dts-BCM5301X-Fix-NAND-nodes-names.patch +++ /dev/null @@ -1,25 +0,0 @@ -From b660269cba748dfd07eb5551a88ff34d5ea0b86e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 16 Apr 2021 15:37:48 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Fix NAND nodes names -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This matches nand-controller.yaml requirements. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -306,7 +306,7 @@ - interrupt-names = "nand"; - status = "okay"; - -- nandcs: nandcs@0 { -+ nandcs: nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - }; diff --git a/target/linux/bcm4908/patches-5.10/034-v5.16-0001-arm64-dts-broadcom-bcm4908-Fix-NAND-node-name.patch b/target/linux/bcm4908/patches-5.10/034-v5.16-0001-arm64-dts-broadcom-bcm4908-Fix-NAND-node-name.patch deleted file mode 100644 index 80ce766751..0000000000 --- a/target/linux/bcm4908/patches-5.10/034-v5.16-0001-arm64-dts-broadcom-bcm4908-Fix-NAND-node-name.patch +++ /dev/null @@ -1,27 +0,0 @@ -From d0ae9c944b9472c5691a482297df7a57d7fd1199 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 19 Aug 2021 14:11:08 +0200 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix NAND node name -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This matches nand-controller.yaml requirements. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -296,7 +296,7 @@ - status = "okay"; - }; - -- nand@1800 { -+ nand-controller@1800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; diff --git a/target/linux/bcm4908/patches-5.10/034-v5.16-0002-arm64-dts-broadcom-bcm4908-Move-reboot-syscon-out-of.patch b/target/linux/bcm4908/patches-5.10/034-v5.16-0002-arm64-dts-broadcom-bcm4908-Move-reboot-syscon-out-of.patch deleted file mode 100644 index 6ac618a768..0000000000 --- a/target/linux/bcm4908/patches-5.10/034-v5.16-0002-arm64-dts-broadcom-bcm4908-Move-reboot-syscon-out-of.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 6cf9f70255b90b540b9cbde062f18fea29024a75 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 19 Aug 2021 14:26:06 +0200 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: Move reboot syscon out of bus -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes following error for every bcm4908 DTS file: -bus@ff800000: reboot: {'type': 'object'} is not allowed for {'compatible': ['syscon-reboot'], 'regmap': [[15]], 'offset': [[52]], 'mask': [[1]]} - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -326,12 +326,12 @@ - #reset-cells = <1>; - }; - }; -+ }; - -- reboot { -- compatible = "syscon-reboot"; -- regmap = <&timer>; -- offset = <0x34>; -- mask = <1>; -- }; -+ reboot { -+ compatible = "syscon-reboot"; -+ regmap = <&timer>; -+ offset = <0x34>; -+ mask = <1>; - }; - }; diff --git a/target/linux/bcm4908/patches-5.10/034-v5.16-0003-arm64-dts-broadcom-bcm4908-Fix-UART-clock-name.patch b/target/linux/bcm4908/patches-5.10/034-v5.16-0003-arm64-dts-broadcom-bcm4908-Fix-UART-clock-name.patch deleted file mode 100644 index af9441875c..0000000000 --- a/target/linux/bcm4908/patches-5.10/034-v5.16-0003-arm64-dts-broadcom-bcm4908-Fix-UART-clock-name.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 6c38c39ab2141f53786d73e706675e8819a3f2cb Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 19 Aug 2021 17:37:02 +0200 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix UART clock name -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -According to the binding the correct clock name is "refclk". - -Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files") -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -292,7 +292,7 @@ - reg = <0x640 0x18>; - interrupts = ; - clocks = <&periph_clk>; -- clock-names = "periph"; -+ clock-names = "refclk"; - status = "okay"; - }; - diff --git a/target/linux/bcm4908/patches-5.10/035-v5.17-0001-dt-bindings-arm-bcm-document-Netgear-RAXE500-binding.patch b/target/linux/bcm4908/patches-5.10/035-v5.17-0001-dt-bindings-arm-bcm-document-Netgear-RAXE500-binding.patch deleted file mode 100644 index 4d5ffcb9e3..0000000000 --- a/target/linux/bcm4908/patches-5.10/035-v5.17-0001-dt-bindings-arm-bcm-document-Netgear-RAXE500-binding.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 7b0c9ca7f18e8d2e2cf3c342d91f037d436777bf Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 5 Nov 2021 11:14:12 +0100 -Subject: [PATCH] dt-bindings: arm: bcm: document Netgear RAXE500 binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -One more BCM4908 based device. - -Signed-off-by: Rafał Miłecki -Acked-by: Rob Herring -Signed-off-by: Florian Fainelli ---- - Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml -+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml -@@ -29,6 +29,7 @@ properties: - items: - - enum: - - asus,gt-ac5300 -+ - netgear,raxe500 - - const: brcm,bcm4908 - - - description: BCM49408 based boards diff --git a/target/linux/bcm4908/patches-5.10/035-v5.17-0002-arm64-dts-broadcom-bcm4908-add-DT-for-Netgear-RAXE50.patch b/target/linux/bcm4908/patches-5.10/035-v5.17-0002-arm64-dts-broadcom-bcm4908-add-DT-for-Netgear-RAXE50.patch deleted file mode 100644 index 9e0236ad0f..0000000000 --- a/target/linux/bcm4908/patches-5.10/035-v5.17-0002-arm64-dts-broadcom-bcm4908-add-DT-for-Netgear-RAXE50.patch +++ /dev/null @@ -1,81 +0,0 @@ -From d0e68d354f345873e15876a7b35be1baaf5e3ec9 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 5 Nov 2021 11:14:13 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add DT for Netgear RAXE500 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's a home router based on BCM4908 SoC. It has: 1 GiB of RAM, 512 MiB -NAND flash, 6 Ethernet ports and 3 x BCM43684 (WiFi). One of Ethernet -ports is "2.5 G Multi-Gig port" that isn't described yet (it isn't known -how it's wired up). - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 1 + - .../bcm4908/bcm4908-netgear-raxe500.dts | 50 +++++++++++++++++++ - 2 files changed, 51 insertions(+) - create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile -@@ -2,3 +2,4 @@ - dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb - dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb - dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb -+dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-netgear-raxe500.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts -@@ -0,0 +1,50 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include "bcm4908.dtsi" -+ -+/ { -+ compatible = "netgear,raxe500", "brcm,bcm4908"; -+ model = "Netgear RAXE500"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00 0x00 0x00 0x40000000>; -+ }; -+}; -+ -+&ehci { -+ status = "okay"; -+}; -+ -+&ohci { -+ status = "okay"; -+}; -+ -+&xhci { -+ status = "okay"; -+}; -+ -+&ports { -+ port@0 { -+ label = "lan4"; -+ }; -+ -+ port@1 { -+ label = "lan3"; -+ }; -+ -+ port@2 { -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ label = "lan1"; -+ }; -+ -+ port@7 { -+ reg = <7>; -+ phy-mode = "internal"; -+ phy-handle = <&phy12>; -+ label = "wan"; -+ }; -+}; diff --git a/target/linux/bcm4908/patches-5.10/036-v5.18-0001-arm64-dts-broadcom-bcm4908-use-proper-TWD-binding.patch b/target/linux/bcm4908/patches-5.10/036-v5.18-0001-arm64-dts-broadcom-bcm4908-use-proper-TWD-binding.patch deleted file mode 100644 index 420f790fdd..0000000000 --- a/target/linux/bcm4908/patches-5.10/036-v5.18-0001-arm64-dts-broadcom-bcm4908-use-proper-TWD-binding.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 33826e9c6ba76b265d4e26cb95493fa27ed78974 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 29 Dec 2021 11:23:14 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: use proper TWD binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Block at is a TWD that contains timers, watchdog and -reset. Actual timers happen to be at block beginning but they only span -across the first 0x28 registers. It means the old block description was -incorrect (size 0x3c). - -Drop timers binding for now and use documented TWD binding. Timers -should be properly documented and defined as TWD subnode. - -Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files") -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -273,9 +273,9 @@ - #size-cells = <1>; - ranges = <0x00 0x00 0xff800000 0x3000>; - -- timer: timer@400 { -- compatible = "brcm,bcm6328-timer", "syscon"; -- reg = <0x400 0x3c>; -+ twd: timer-mfd@400 { -+ compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; -+ reg = <0x400 0x4c>; - }; - - gpio0: gpio-controller@500 { -@@ -330,7 +330,7 @@ - - reboot { - compatible = "syscon-reboot"; -- regmap = <&timer>; -+ regmap = <&twd>; - offset = <0x34>; - mask = <1>; - }; diff --git a/target/linux/bcm4908/patches-5.10/036-v5.18-0002-arm64-dts-broadcom-bcm4908-add-pinctrl-binding.patch b/target/linux/bcm4908/patches-5.10/036-v5.18-0002-arm64-dts-broadcom-bcm4908-add-pinctrl-binding.patch deleted file mode 100644 index 2f4baf80c6..0000000000 --- a/target/linux/bcm4908/patches-5.10/036-v5.18-0002-arm64-dts-broadcom-bcm4908-add-pinctrl-binding.patch +++ /dev/null @@ -1,160 +0,0 @@ -From 72b1c5da796ec5266f2012c36470e226cb4f09c9 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 30 Dec 2021 12:05:35 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add pinctrl binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Describe pinmux block with its maps. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 135 ++++++++++++++++++ - 1 file changed, 135 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -287,6 +287,141 @@ - gpio-controller; - }; - -+ pinctrl@560 { -+ compatible = "brcm,bcm4908-pinctrl"; -+ reg = <0x560 0x10>; -+ -+ pins_led_0_a: led_0-a-pins { -+ function = "led_0"; -+ groups = "led_0_grp_a"; -+ }; -+ -+ pins_led_1_a: led_1-a-pins { -+ function = "led_1"; -+ groups = "led_1_grp_a"; -+ }; -+ -+ pins_led_2_a: led_2-a-pins { -+ function = "led_2"; -+ groups = "led_2_grp_a"; -+ }; -+ -+ pins_led_3_a: led_3-a-pins { -+ function = "led_3"; -+ groups = "led_3_grp_a"; -+ }; -+ -+ pins_led_4_a: led_4-a-pins { -+ function = "led_4"; -+ groups = "led_4_grp_a"; -+ }; -+ -+ pins_led_5_a: led_5-a-pins { -+ function = "led_5"; -+ groups = "led_5_grp_a"; -+ }; -+ -+ pins_led_6_a: led_6-a-pins { -+ function = "led_6"; -+ groups = "led_6_grp_a"; -+ }; -+ -+ pins_led_7_a: led_7-a-pins { -+ function = "led_7"; -+ groups = "led_7_grp_a"; -+ }; -+ -+ pins_led_8_a: led_8-a-pins { -+ function = "led_8"; -+ groups = "led_8_grp_a"; -+ }; -+ -+ pins_led_9_a: led_9-a-pins { -+ function = "led_9"; -+ groups = "led_9_grp_a"; -+ }; -+ -+ pins_led_21_a: led_21-a-pins { -+ function = "led_21"; -+ groups = "led_21_grp_a"; -+ }; -+ -+ pins_led_22_a: led_22-a-pins { -+ function = "led_22"; -+ groups = "led_22_grp_a"; -+ }; -+ -+ pins_led_26_a: led_26-a-pins { -+ function = "led_26"; -+ groups = "led_26_grp_a"; -+ }; -+ -+ pins_led_27_a: led_27-a-pins { -+ function = "led_27"; -+ groups = "led_27_grp_a"; -+ }; -+ -+ pins_led_28_a: led_28-a-pins { -+ function = "led_28"; -+ groups = "led_28_grp_a"; -+ }; -+ -+ pins_led_29_a: led_29-a-pins { -+ function = "led_29"; -+ groups = "led_29_grp_a"; -+ }; -+ -+ pins_led_30_a: led_30-a-pins { -+ function = "led_30"; -+ groups = "led_30_grp_a"; -+ }; -+ -+ pins_hs_uart: hs_uart-pins { -+ function = "hs_uart"; -+ groups = "hs_uart_grp"; -+ }; -+ -+ pins_i2c_a: i2c-a-pins { -+ function = "i2c"; -+ groups = "i2c_grp_a"; -+ }; -+ -+ pins_i2c_b: i2c-b-pins { -+ function = "i2c"; -+ groups = "i2c_grp_b"; -+ }; -+ -+ pins_i2s: i2s-pins { -+ function = "i2s"; -+ groups = "i2s_grp"; -+ }; -+ -+ pins_nand_ctrl: nand_ctrl-pins { -+ function = "nand_ctrl"; -+ groups = "nand_ctrl_grp"; -+ }; -+ -+ pins_nand_data: nand_data-pins { -+ function = "nand_data"; -+ groups = "nand_data_grp"; -+ }; -+ -+ pins_emmc_ctrl: emmc_ctrl-pins { -+ function = "emmc_ctrl"; -+ groups = "emmc_ctrl_grp"; -+ }; -+ -+ pins_usb0_pwr: usb0_pwr-pins { -+ function = "usb0_pwr"; -+ groups = "usb0_pwr_grp"; -+ }; -+ -+ pins_usb1_pwr: usb1_pwr-pins { -+ function = "usb1_pwr"; -+ groups = "usb1_pwr_grp"; -+ }; -+ }; -+ - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x18>; diff --git a/target/linux/bcm4908/patches-5.10/036-v5.18-0003-arm64-dts-broadcom-bcm4908-add-watchdog-block.patch b/target/linux/bcm4908/patches-5.10/036-v5.18-0003-arm64-dts-broadcom-bcm4908-add-watchdog-block.patch deleted file mode 100644 index 3ca778dcd8..0000000000 --- a/target/linux/bcm4908/patches-5.10/036-v5.18-0003-arm64-dts-broadcom-bcm4908-add-watchdog-block.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 47513f6dd93b5b7d91143219c2c1fb883664ed13 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 9 Feb 2022 21:14:17 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add watchdog block -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 has the same watchdog as BCM63xx devices. Use "brcm,bcm6345-wdt" -binding which matches the first SoC with that block. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -276,6 +276,15 @@ - twd: timer-mfd@400 { - compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; - reg = <0x400 0x4c>; -+ ranges = <0x0 0x400 0x4c>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ watchdog@28 { -+ compatible = "brcm,bcm6345-wdt"; -+ reg = <0x28 0x8>; -+ }; - }; - - gpio0: gpio-controller@500 { diff --git a/target/linux/bcm4908/patches-5.10/036-v5.18-0004-arm64-dts-broadcom-bcm4908-add-I2C-block.patch b/target/linux/bcm4908/patches-5.10/036-v5.18-0004-arm64-dts-broadcom-bcm4908-add-I2C-block.patch deleted file mode 100644 index ab00f44b14..0000000000 --- a/target/linux/bcm4908/patches-5.10/036-v5.18-0004-arm64-dts-broadcom-bcm4908-add-I2C-block.patch +++ /dev/null @@ -1,34 +0,0 @@ -From ba5dfa2fd8d0aed4e4b6f650ba9e8ea7cdd6ead1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 15 Feb 2022 07:36:39 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add I2C block -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 uses the same I2C hw as BCM63xx / BCM67xx / BCM68xx SoCs. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -456,6 +456,15 @@ - }; - }; - -+ i2c@2100 { -+ compatible = "brcm,brcmper-i2c"; -+ reg = <0x2100 0x58>; -+ clock-frequency = <97500>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_i2c_a>; -+ status = "disabled"; -+ }; -+ - misc@2600 { - compatible = "brcm,misc", "simple-mfd"; - reg = <0x2600 0xe4>; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0001-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63158.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0001-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63158.patch deleted file mode 100644 index 2a1260f73b..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0001-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63158.patch +++ /dev/null @@ -1,199 +0,0 @@ -From 076dcedc6628c6bf92bd17bfcf8fb7b1af62bfb6 Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Wed, 1 Jun 2022 15:56:51 -0700 -Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63158 - -Add DTS for ARMv8 based broadband SoC BCM63158. bcm63158.dtsi is the -SoC description DTS header and bcm963158.dts is a simple DTS file for -Broadcom BCM963158 Reference board that only enable the UART port. - -Signed-off-by: William Zhang -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/Makefile | 1 + - arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 2 + - .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 128 ++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm963158.dts | 30 ++++ - 4 files changed, 161 insertions(+) - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/Makefile - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts - ---- a/arch/arm64/boot/dts/broadcom/Makefile -+++ b/arch/arm64/boot/dts/broadcom/Makefile -@@ -6,5 +6,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp - bcm2837-rpi-cm3-io3.dtb - - subdir-y += bcm4908 -+subdir-y += bcmbca - subdir-y += northstar2 - subdir-y += stingray ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi -@@ -0,0 +1,128 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+#include -+#include -+ -+/ { -+ compatible = "brcm,bcm63158", "brcm,bcmbca"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ interrupt-parent = <&gic>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ B53_0: cpu@0 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x0>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_1: cpu@1 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x1>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_2: cpu@2 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x2>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_3: cpu@3 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x3>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ L2_0: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu: pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-affinity = <&B53_0>, <&B53_1>, -+ <&B53_2>, <&B53_3>; -+ }; -+ -+ clocks: clocks { -+ periph_clk: periph-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; -+ uart_clk: uart-clk { -+ compatible = "fixed-factor-clock"; -+ #clock-cells = <0>; -+ clocks = <&periph_clk>; -+ clock-div = <4>; -+ clock-mult = <1>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-0.2"; -+ method = "smc"; -+ }; -+ -+ axi@81000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x81000000 0x8000>; -+ -+ gic: interrupt-controller@1000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ reg = <0x1000 0x1000>, -+ <0x2000 0x2000>, -+ <0x4000 0x2000>, -+ <0x6000 0x2000>; -+ }; -+ }; -+ -+ bus@ff800000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0xff800000 0x800000>; -+ -+ uart0: serial@12000 { -+ compatible = "arm,pl011", "arm,primecell"; -+ reg = <0x12000 0x1000>; -+ interrupts = ; -+ clocks = <&uart_clk>, <&uart_clk>; -+ clock-names = "uartclk", "apb_pclk"; -+ status = "disabled"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm63158.dtsi" -+ -+/ { -+ model = "Broadcom BCM963158 Reference Board"; -+ compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x0 0x0 0x08000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patch deleted file mode 100644 index 5cdb9d1df1..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patch +++ /dev/null @@ -1,191 +0,0 @@ -From 1ba56aeb391401c4cb2126c39f90b3cdbfabdb3f Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Wed, 1 Jun 2022 13:17:34 -0700 -Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM4912 - -Add DTS for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the -SoC description DTS header and bcm94912.dts is a simple DTS file for -Broadcom BCM94912 Reference board that only enable the UART port. - -Signed-off-by: William Zhang -Acked-by: Krzysztof Kozlowski -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- - .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 128 ++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm94912.dts | 30 ++++ - 3 files changed, 160 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb -+dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ -+ bcm963158.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi -@@ -0,0 +1,128 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+#include -+#include -+ -+/ { -+ compatible = "brcm,bcm4912", "brcm,bcmbca"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ interrupt-parent = <&gic>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ B53_0: cpu@0 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x0>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_1: cpu@1 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x1>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_2: cpu@2 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x2>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_3: cpu@3 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x3>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ L2_0: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu: pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-affinity = <&B53_0>, <&B53_1>, -+ <&B53_2>, <&B53_3>; -+ }; -+ -+ clocks: clocks { -+ periph_clk: periph-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; -+ uart_clk: uart-clk { -+ compatible = "fixed-factor-clock"; -+ #clock-cells = <0>; -+ clocks = <&periph_clk>; -+ clock-div = <4>; -+ clock-mult = <1>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-0.2"; -+ method = "smc"; -+ }; -+ -+ axi@81000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x81000000 0x8000>; -+ -+ gic: interrupt-controller@1000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ reg = <0x1000 0x1000>, -+ <0x2000 0x2000>, -+ <0x4000 0x2000>, -+ <0x6000 0x2000>; -+ }; -+ }; -+ -+ bus@ff800000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0xff800000 0x800000>; -+ -+ uart0: serial@12000 { -+ compatible = "arm,pl011", "arm,primecell"; -+ reg = <0x12000 0x1000>; -+ interrupts = ; -+ clocks = <&uart_clk>, <&uart_clk>; -+ clock-names = "uartclk", "apb_pclk"; -+ status = "disabled"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4912.dtsi" -+ -+/ { -+ model = "Broadcom BCM94912 Reference Board"; -+ compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x0 0x0 0x08000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0003-ARM64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6858.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0003-ARM64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6858.patch deleted file mode 100644 index f10a44f890..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0003-ARM64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6858.patch +++ /dev/null @@ -1,184 +0,0 @@ -From e663e06bd3f21e64bc2163910f626af68add6308 Mon Sep 17 00:00:00 2001 -From: Anand Gore -Date: Wed, 1 Jun 2022 13:19:56 -0700 -Subject: [PATCH] ARM64: dts: Add DTS files for bcmbca SoC BCM6858 - -Add DTS for ARMv8 based broadband SoC BCM6858. bcm6858.dtsi is the SoC -description DTS header and bcm96858.dts is a simple DTS file for -Broadcom BCM96858 Reference board that only enables the UART port. - -Signed-off-by: Anand Gore -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- - .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 121 ++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm96858.dts | 30 +++++ - 3 files changed, 153 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ -- bcm963158.dtb -+ bcm963158.dtb \ -+ bcm96858.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi -@@ -0,0 +1,121 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+#include -+#include -+ -+/ { -+ compatible = "brcm,bcm6858", "brcm,bcmbca"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ interrupt-parent = <&gic>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ B53_0: cpu@0 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x0>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_1: cpu@1 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x1>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_2: cpu@2 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x2>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_3: cpu@3 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x3>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ L2_0: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu: pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-affinity = <&B53_0>, <&B53_1>, -+ <&B53_2>, <&B53_3>; -+ }; -+ -+ clocks: clocks { -+ periph_clk:periph-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-0.2"; -+ method = "smc"; -+ }; -+ -+ axi@81000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x81000000 0x8000>; -+ -+ gic: interrupt-controller@1000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x1000 0x1000>, /* GICD */ -+ <0x2000 0x2000>, /* GICC */ -+ <0x4000 0x2000>, /* GICH */ -+ <0x6000 0x2000>; /* GICV */ -+ interrupts = ; -+ }; -+ }; -+ -+ bus@ff800000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0xff800000 0x62000>; -+ -+ uart0: serial@640 { -+ compatible = "brcm,bcm6345-uart"; -+ reg = <0x640 0x18>; -+ interrupts = ; -+ clocks = <&periph_clk>; -+ clock-names = "refclk"; -+ status = "disabled"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm6858.dtsi" -+ -+/ { -+ model = "Broadcom BCM96858 Reference Board"; -+ compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x0 0x0 0x08000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patch deleted file mode 100644 index 793c5af738..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Wed, 8 Jun 2022 11:00:59 -0700 -Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146 - -Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the -SoC description DTS header and bcm963146.dts is a simple DTS file for -Broadcom BCM963146 Reference board that only enable the UART port. - -Signed-off-by: William Zhang -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- - .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 110 ++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm963146.dts | 30 +++++ - 3 files changed, 142 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ - bcm963158.dtb \ -- bcm96858.dtb -+ bcm96858.dtb \ -+ bcm963146.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi -@@ -0,0 +1,110 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+#include -+#include -+ -+/ { -+ compatible = "brcm,bcm63146", "brcm,bcmbca"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ interrupt-parent = <&gic>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ B53_0: cpu@0 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x0>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_1: cpu@1 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x1>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ L2_0: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu: pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ ; -+ interrupt-affinity = <&B53_0>, <&B53_1>; -+ }; -+ -+ clocks: clocks { -+ periph_clk: periph-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; -+ uart_clk: uart-clk { -+ compatible = "fixed-factor-clock"; -+ #clock-cells = <0>; -+ clocks = <&periph_clk>; -+ clock-div = <4>; -+ clock-mult = <1>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-0.2"; -+ method = "smc"; -+ }; -+ -+ axi@81000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x81000000 0x8000>; -+ -+ gic: interrupt-controller@1000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x1000 0x1000>, -+ <0x2000 0x2000>, -+ <0x4000 0x2000>, -+ <0x6000 0x2000>; -+ interrupts = ; -+ }; -+ }; -+ -+ bus@ff800000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0xff800000 0x800000>; -+ -+ uart0: serial@12000 { -+ compatible = "arm,pl011", "arm,primecell"; -+ reg = <0x12000 0x1000>; -+ interrupts = ; -+ clocks = <&uart_clk>, <&uart_clk>; -+ clock-names = "uartclk", "apb_pclk"; -+ status = "disabled"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm63146.dtsi" -+ -+/ { -+ model = "Broadcom BCM963146 Reference Board"; -+ compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x0 0x0 0x08000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patch deleted file mode 100644 index 0fdafb7f17..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patch +++ /dev/null @@ -1,167 +0,0 @@ -From 64eca7ad058cff861b48cdead8dee40dfc284e9e Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Wed, 8 Jun 2022 11:04:36 -0700 -Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6856 - -Add DTS for ARMv8 based broadband SoC BCM6856. bcm6856.dtsi is the -SoC description DTS header and bcm96856.dts is a simple DTS file for -Broadcom BCM96956 Reference board that only enable the UART port. - -Signed-off-by: William Zhang -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- - .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 103 ++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm96856.dts | 30 +++++ - 3 files changed, 135 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -@@ -2,4 +2,5 @@ - dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ - bcm963158.dtb \ - bcm96858.dtb \ -- bcm963146.dtb -+ bcm963146.dtb \ -+ bcm96856.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi -@@ -0,0 +1,103 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+#include -+#include -+ -+/ { -+ compatible = "brcm,bcm6856", "brcm,bcmbca"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ interrupt-parent = <&gic>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ B53_0: cpu@0 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x0>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_1: cpu@1 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x1>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ L2_0: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu: pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ ; -+ interrupt-affinity = <&B53_0>, <&B53_1>; -+ }; -+ -+ clocks: clocks { -+ periph_clk:periph-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-0.2"; -+ method = "smc"; -+ }; -+ -+ axi@81000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x81000000 0x8000>; -+ -+ gic: interrupt-controller@1000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x1000 0x1000>, /* GICD */ -+ <0x2000 0x2000>, /* GICC */ -+ <0x4000 0x2000>, /* GICH */ -+ <0x6000 0x2000>; /* GICV */ -+ interrupts = ; -+ }; -+ }; -+ -+ bus@ff800000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0xff800000 0x800000>; -+ -+ uart0: serial@640 { -+ compatible = "brcm,bcm6345-uart"; -+ reg = <0x640 0x18>; -+ interrupts = ; -+ clocks = <&periph_clk>; -+ clock-names = "refclk"; -+ status = "disabled"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm6856.dtsi" -+ -+/ { -+ model = "Broadcom BCM96856 Reference Board"; -+ compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x0 0x0 0x08000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0006-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6813.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0006-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6813.patch deleted file mode 100644 index 58af85a68c..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0006-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6813.patch +++ /dev/null @@ -1,192 +0,0 @@ -From eab6bb0994b806525fc5e362e8b865f61c4a9e20 Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Thu, 9 Jun 2022 17:15:33 -0700 -Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6813 - -Add DTS for ARMv8 based broadband SoC BCM6813. bcm6813.dtsi is the -SoC description DTS header and bcm96813.dts is a simple DTS file for -Broadcom BCM96813 Reference board that only enable the UART port. - -Signed-off-by: William Zhang -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +- - .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 128 ++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm96813.dts | 30 ++++ - 3 files changed, 160 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dt - bcm963158.dtb \ - bcm96858.dtb \ - bcm963146.dtb \ -- bcm96856.dtb -+ bcm96856.dtb \ -+ bcm96813.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi -@@ -0,0 +1,128 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+#include -+#include -+ -+/ { -+ compatible = "brcm,bcm6813", "brcm,bcmbca"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ interrupt-parent = <&gic>; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ B53_0: cpu@0 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x0>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_1: cpu@1 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x1>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_2: cpu@2 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x2>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ B53_3: cpu@3 { -+ compatible = "brcm,brahma-b53"; -+ device_type = "cpu"; -+ reg = <0x0 0x3>; -+ next-level-cache = <&L2_0>; -+ enable-method = "psci"; -+ }; -+ -+ L2_0: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu: pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-affinity = <&B53_0>, <&B53_1>, -+ <&B53_2>, <&B53_3>; -+ }; -+ -+ clocks: clocks { -+ periph_clk: periph-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; -+ uart_clk: uart-clk { -+ compatible = "fixed-factor-clock"; -+ #clock-cells = <0>; -+ clocks = <&periph_clk>; -+ clock-div = <4>; -+ clock-mult = <1>; -+ }; -+ }; -+ -+ psci { -+ compatible = "arm,psci-0.2"; -+ method = "smc"; -+ }; -+ -+ axi@81000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x81000000 0x8000>; -+ -+ gic: interrupt-controller@1000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ interrupts = ; -+ reg = <0x1000 0x1000>, -+ <0x2000 0x2000>, -+ <0x4000 0x2000>, -+ <0x6000 0x2000>; -+ }; -+ }; -+ -+ bus@ff800000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0xff800000 0x800000>; -+ -+ uart0: serial@12000 { -+ compatible = "arm,pl011", "arm,primecell"; -+ reg = <0x12000 0x1000>; -+ interrupts = ; -+ clocks = <&uart_clk>, <&uart_clk>; -+ clock-names = "uartclk", "apb_pclk"; -+ status = "disabled"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm6813.dtsi" -+ -+/ { -+ model = "Broadcom BCM96813 Reference Board"; -+ compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x0 0x0 0x08000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0007-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0007-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patch deleted file mode 100644 index d0d6151957..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0007-arm64-dts-broadcom-align-gpio-key-node-names-with-dt.patch +++ /dev/null @@ -1,79 +0,0 @@ -From ea559c81b61603d4044df6f826f10a832c42c98c Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Wed, 15 Jun 2022 17:52:59 -0700 -Subject: [PATCH] arm64: dts: broadcom: align gpio-key node names with dtschema - -The node names should be generic and DT schema expects certain pattern -(e.g. with key/button/switch). - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220616005333.18491-6-krzysztof.kozlowski@linaro.org ---- - .../broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts | 8 ++++---- - .../boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 8 ++++---- - 2 files changed, 8 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts -@@ -83,25 +83,25 @@ - compatible = "gpio-keys-polled"; - poll-interval = <100>; - -- brightness { -+ key-brightness { - label = "LEDs"; - linux,code = ; - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - }; - -- wps { -+ key-wps { - label = "WPS"; - linux,code = ; - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - -- wifi { -+ key-wifi { - label = "WiFi"; - linux,code = ; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ key-restart { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -@@ -18,25 +18,25 @@ - compatible = "gpio-keys-polled"; - poll-interval = <100>; - -- wifi { -+ key-wifi { - label = "WiFi"; - linux,code = ; - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - }; - -- wps { -+ key-wps { - label = "WPS"; - linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ key-restart { - label = "Reset"; - linux,code = ; - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - }; - -- brightness { -+ key-brightness { - label = "LEDs"; - linux,code = ; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0008-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0008-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patch deleted file mode 100644 index c2b924a0fd..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0008-arm64-dts-broadcom-bcm4908-Fix-timer-node-for-BCM490.patch +++ /dev/null @@ -1,33 +0,0 @@ -From b4a544e415e9be33b37d9bfa9d9f9f4d13f553d6 Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Fri, 8 Jul 2022 11:25:06 -0700 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix timer node for BCM4906 SoC - -The cpu mask value in interrupt property inherits from bcm4908.dtsi -which sets to four cpus. Correct the value to two cpus for dual core -BCM4906 SoC. - -Fixes: c8b404fb05dc ("arm64: dts: broadcom: bcm4908: add BCM4906 Netgear R8000P DTS files") -Signed-off-by: William Zhang -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi -@@ -9,6 +9,14 @@ - /delete-node/ cpu@3; - }; - -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0009-arm64-dts-broadcom-bcm4908-Fix-cpu-node-for-smp-boot.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0009-arm64-dts-broadcom-bcm4908-Fix-cpu-node-for-smp-boot.patch deleted file mode 100644 index 482fd1cc98..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0009-arm64-dts-broadcom-bcm4908-Fix-cpu-node-for-smp-boot.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 8bd582ae9a71d7f14c4e0c735b2eacaf7516d626 Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Fri, 8 Jul 2022 11:25:07 -0700 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix cpu node for smp boot - -Add spin-table enable-method and cpu-release-addr properties for -cpu0 node. This is required by all ARMv8 SoC. Otherwise some -bootloader like u-boot can not update cpu-release-addr and linux -fails to start up secondary cpus. - -Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files") -Signed-off-by: William Zhang -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -29,6 +29,8 @@ - device_type = "cpu"; - compatible = "brcm,brahma-b53"; - reg = <0x0>; -+ enable-method = "spin-table"; -+ cpu-release-addr = <0x0 0xfff8>; - next-level-cache = <&l2>; - }; - diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0010-arm64-dts-Add-base-DTS-file-for-bcmbca-device-Asus-G.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0010-arm64-dts-Add-base-DTS-file-for-bcmbca-device-Asus-G.patch deleted file mode 100644 index 6f71c8b5fb..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0010-arm64-dts-Add-base-DTS-file-for-bcmbca-device-Asus-G.patch +++ /dev/null @@ -1,54 +0,0 @@ -From f3f575c4bef95384e68de552c7b29938fd0d9201 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 13 Jul 2022 22:03:51 +0200 -Subject: [PATCH] arm64: dts: Add base DTS file for bcmbca device Asus - GT-AX6000 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's a home router with 1 GiB of RAM, 6 Ethernet ports, 2 USB ports. - -Signed-off-by: Rafał Miłecki -Acked-by: William Zhang -Link: https://lore.kernel.org/r/20220713200351.28526-2-zajec5@gmail.com -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 4 +++- - .../bcmbca/bcm4912-asus-gt-ax6000.dts | 19 +++++++++++++++++++ - 2 files changed, 22 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -@@ -1,5 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \ -+dtb-$(CONFIG_ARCH_BCMBCA) += \ -+ bcm4912-asus-gt-ax6000.dtb \ -+ bcm94912.dtb \ - bcm963158.dtb \ - bcm96858.dtb \ - bcm963146.dtb \ ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912-asus-gt-ax6000.dts -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+/dts-v1/; -+ -+#include "bcm4912.dtsi" -+ -+/ { -+ compatible = "asus,gt-ax6000", "brcm,bcm4912", "brcm,bcmbca"; -+ model = "Asus GT-AX6000"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00 0x00 0x00 0x40000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm4908/patches-5.10/037-v5.20-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch b/target/linux/bcm4908/patches-5.10/037-v5.20-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch deleted file mode 100644 index 1b9a32e30a..0000000000 --- a/target/linux/bcm4908/patches-5.10/037-v5.20-0011-arm64-bcmbca-add-arch-bcmbca-machine-entry.patch +++ /dev/null @@ -1,31 +0,0 @@ -From fdcd652ce2b6b819f5c4dc3cead5215c84ee6933 Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Wed, 1 Jun 2022 15:56:50 -0700 -Subject: [PATCH] arm64: bcmbca: add arch bcmbca machine entry - -Add ARCH_BCMBCA config for Broadcom Broadband SoC chipsets - -Signed-off-by: William Zhang -Signed-off-by: Florian Fainelli ---- - arch/arm64/Kconfig.platforms | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/Kconfig.platforms -+++ b/arch/arm64/Kconfig.platforms -@@ -59,6 +59,15 @@ config ARCH_BCM_IPROC - help - This enables support for Broadcom iProc based SoCs - -+config ARCH_BCMBCA -+ bool "Broadcom Broadband SoC" -+ help -+ Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based -+ BCA chipset. -+ -+ This enables support for Broadcom BCA ARM-based broadband chipsets, -+ including the DSL, PON and Wireless family of chips. -+ - config ARCH_BERLIN - bool "Marvell Berlin SoC Family" - select DW_APB_ICTL diff --git a/target/linux/bcm4908/patches-5.10/038-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch b/target/linux/bcm4908/patches-5.10/038-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch deleted file mode 100644 index 437249f2cb..0000000000 --- a/target/linux/bcm4908/patches-5.10/038-v6.1-0001-arm64-dts-broadcom-bcm4908-add-remaining-LED-pins.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 456b6dd1baadd2da10e28ffd1717b06d1fa17a97 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 18 Jul 2022 15:20:58 +0200 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining LED pins -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Include all 32 pins. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20220718132100.13277-1-zajec5@gmail.com -Signed-off-by: Florian Fainelli ---- - .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 75 +++++++++++++++++++ - 1 file changed, 75 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -352,6 +352,61 @@ - groups = "led_9_grp_a"; - }; - -+ pins_led_10_a: led_10-a-pins { -+ function = "led_10"; -+ groups = "led_10_grp_a"; -+ }; -+ -+ pins_led_11_a: led_11-a-pins { -+ function = "led_11"; -+ groups = "led_11_grp_a"; -+ }; -+ -+ pins_led_12_a: led_12-a-pins { -+ function = "led_12"; -+ groups = "led_12_grp_a"; -+ }; -+ -+ pins_led_13_a: led_13-a-pins { -+ function = "led_13"; -+ groups = "led_13_grp_a"; -+ }; -+ -+ pins_led_14_a: led_14-a-pins { -+ function = "led_14"; -+ groups = "led_14_grp_a"; -+ }; -+ -+ pins_led_15_a: led_15-a-pins { -+ function = "led_15"; -+ groups = "led_15_grp_a"; -+ }; -+ -+ pins_led_16_a: led_16-a-pins { -+ function = "led_16"; -+ groups = "led_16_grp_a"; -+ }; -+ -+ pins_led_17_a: led_17-a-pins { -+ function = "led_17"; -+ groups = "led_17_grp_a"; -+ }; -+ -+ pins_led_18_a: led_18-a-pins { -+ function = "led_18"; -+ groups = "led_18_grp_a"; -+ }; -+ -+ pins_led_19_a: led_19-a-pins { -+ function = "led_19"; -+ groups = "led_19_grp_a"; -+ }; -+ -+ pins_led_20_a: led_20-a-pins { -+ function = "led_20"; -+ groups = "led_20_grp_a"; -+ }; -+ - pins_led_21_a: led_21-a-pins { - function = "led_21"; - groups = "led_21_grp_a"; -@@ -362,6 +417,21 @@ - groups = "led_22_grp_a"; - }; - -+ pins_led_23_a: led_23-a-pins { -+ function = "led_23"; -+ groups = "led_23_grp_a"; -+ }; -+ -+ pins_led_24_a: led_24-a-pins { -+ function = "led_24"; -+ groups = "led_24_grp_a"; -+ }; -+ -+ pins_led_25_a: led_25-a-pins { -+ function = "led_25"; -+ groups = "led_25_grp_a"; -+ }; -+ - pins_led_26_a: led_26-a-pins { - function = "led_26"; - groups = "led_26_grp_a"; -@@ -387,6 +457,11 @@ - groups = "led_30_grp_a"; - }; - -+ pins_led_31_a: led_31-a-pins { -+ function = "led_31"; -+ groups = "led_31_grp_a"; -+ }; -+ - pins_hs_uart: hs_uart-pins { - function = "hs_uart"; - groups = "hs_uart_grp"; diff --git a/target/linux/bcm4908/patches-5.10/038-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch b/target/linux/bcm4908/patches-5.10/038-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch deleted file mode 100644 index c890340893..0000000000 --- a/target/linux/bcm4908/patches-5.10/038-v6.1-0002-arm64-dts-broadcom-bcm4908-add-LEDs-controller-block.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 7de56b1dc1149c702d4cc1e89ccc251bfb2bc246 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 18 Jul 2022 15:20:59 +0200 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add LEDs controller block -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 includes LEDs controller that supports multiple brightness -levels & hardware blinking. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20220718132100.13277-2-zajec5@gmail.com -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -@@ -517,6 +517,14 @@ - status = "okay"; - }; - -+ leds: leds@800 { -+ compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds"; -+ reg = <0x800 0xdc>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ - nand-controller@1800 { - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/bcm4908/patches-5.10/038-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch b/target/linux/bcm4908/patches-5.10/038-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch deleted file mode 100644 index 3888efb66b..0000000000 --- a/target/linux/bcm4908/patches-5.10/038-v6.1-0003-arm64-dts-broadcom-bcm4908-add-Asus-GT-AC5300-LEDs.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 3bcae3396e986b4ab97a69e8de517e32f9691a4b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 18 Jul 2022 15:21:00 +0200 -Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There are 5 software-controllable LEDs on PCB. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20220718132100.13277-3-zajec5@gmail.com -Signed-off-by: Florian Fainelli ---- - .../bcm4908/bcm4908-asus-gt-ac5300.dts | 48 +++++++++++++++++++ - 1 file changed, 48 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -@@ -2,6 +2,7 @@ - - #include - #include -+#include - - #include "bcm4908.dtsi" - -@@ -118,6 +119,53 @@ - }; - }; - -+&leds { -+ led-power@11 { -+ reg = <0x11>; -+ function = LED_FUNCTION_POWER; -+ color = ; -+ default-state = "on"; -+ active-low; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_17_a>; -+ }; -+ -+ led-wan-red@12 { -+ reg = <0x12>; -+ function = LED_FUNCTION_WAN; -+ color = ; -+ active-low; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_18_a>; -+ }; -+ -+ led-wps@14 { -+ reg = <0x14>; -+ function = LED_FUNCTION_WPS; -+ color = ; -+ active-low; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_20_a>; -+ }; -+ -+ led-wan-white@15 { -+ reg = <0x15>; -+ function = LED_FUNCTION_WAN; -+ color = ; -+ active-low; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_21_a>; -+ }; -+ -+ led-lan@19 { -+ reg = <0x19>; -+ function = LED_FUNCTION_LAN; -+ color = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_25_a>; -+ }; -+}; -+ - &nandcs { - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; diff --git a/target/linux/bcm4908/patches-5.10/038-v6.1-0004-arm64-dts-bcmbca-update-BCM4908-board-dts-files.patch b/target/linux/bcm4908/patches-5.10/038-v6.1-0004-arm64-dts-bcmbca-update-BCM4908-board-dts-files.patch deleted file mode 100644 index d4b7a983de..0000000000 --- a/target/linux/bcm4908/patches-5.10/038-v6.1-0004-arm64-dts-bcmbca-update-BCM4908-board-dts-files.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 4fdcbde682291fba2c3f45a41decd656d92a314f Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Wed, 3 Aug 2022 10:54:49 -0700 -Subject: [PATCH] arm64: dts: bcmbca: update BCM4908 board dts files -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Append "brcm,bcmbca" to compatible strings based on the new bcmbca -binding rule for BCM4908 family based boards. - -Signed-off-by: William Zhang -Acked-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20220803175455.47638-4-william.zhang@broadcom.com -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts | 2 +- - .../dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts | 2 +- - arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 2 +- - .../arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts | 2 +- - 4 files changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -@@ -7,7 +7,7 @@ - #include "bcm4906.dtsi" - - / { -- compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908"; -+ compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca"; - model = "Netgear R8000P"; - - memory@0 { ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts -@@ -7,7 +7,7 @@ - #include "bcm4906.dtsi" - - / { -- compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908"; -+ compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca"; - model = "TP-Link Archer C2300 V1"; - - memory@0 { ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -@@ -7,7 +7,7 @@ - #include "bcm4908.dtsi" - - / { -- compatible = "asus,gt-ac5300", "brcm,bcm4908"; -+ compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca"; - model = "Asus GT-AC5300"; - - memory@0 { ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts -@@ -3,7 +3,7 @@ - #include "bcm4908.dtsi" - - / { -- compatible = "netgear,raxe500", "brcm,bcm4908"; -+ compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca"; - model = "Netgear RAXE500"; - - memory@0 { diff --git a/target/linux/bcm4908/patches-5.10/038-v6.1-0005-arm64-dts-Move-BCM4908-dts-to-bcmbca-folder.patch b/target/linux/bcm4908/patches-5.10/038-v6.1-0005-arm64-dts-Move-BCM4908-dts-to-bcmbca-folder.patch deleted file mode 100644 index 70484ab93f..0000000000 --- a/target/linux/bcm4908/patches-5.10/038-v6.1-0005-arm64-dts-Move-BCM4908-dts-to-bcmbca-folder.patch +++ /dev/null @@ -1,2491 +0,0 @@ -From ded8f22945899f4e87dd6d952bbc4abce6e64b7e Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Wed, 3 Aug 2022 10:54:50 -0700 -Subject: [PATCH] arm64: dts: Move BCM4908 dts to bcmbca folder - -As part of ARCH_BCM4908 to ARCH_BCMBCA migration, move the BCM4908 dts -files to bcmbca folder and use CONFIG_ARCH_BCMBCA to build all the -BCM4908 board dts. Delete bcm4908 folder and its makefile as well. - -Signed-off-by: William Zhang -Link: https://lore.kernel.org/r/20220803175455.47638-5-william.zhang@broadcom.com -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/Makefile | 1 - - arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 5 ----- - arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 4 ++++ - .../broadcom/{bcm4908 => bcmbca}/bcm4906-netgear-r8000p.dts | 0 - .../{bcm4908 => bcmbca}/bcm4906-tplink-archer-c2300-v1.dts | 0 - .../arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4906.dtsi | 0 - .../broadcom/{bcm4908 => bcmbca}/bcm4908-asus-gt-ac5300.dts | 0 - .../broadcom/{bcm4908 => bcmbca}/bcm4908-netgear-raxe500.dts | 0 - .../arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4908.dtsi | 0 - 9 files changed, 4 insertions(+), 6 deletions(-) - delete mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile - rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4906-netgear-r8000p.dts (100%) - rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4906-tplink-archer-c2300-v1.dts (100%) - rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4906.dtsi (100%) - rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4908-asus-gt-ac5300.dts (100%) - rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4908-netgear-raxe500.dts (100%) - rename arch/arm64/boot/dts/broadcom/{bcm4908 => bcmbca}/bcm4908.dtsi (100%) - ---- a/arch/arm64/boot/dts/broadcom/Makefile -+++ b/arch/arm64/boot/dts/broadcom/Makefile -@@ -5,7 +5,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp - bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb - --subdir-y += bcm4908 - subdir-y += bcmbca - subdir-y += northstar2 - subdir-y += stingray ---- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile -+++ /dev/null -@@ -1,5 +0,0 @@ --# SPDX-License-Identifier: GPL-2.0 --dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb --dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb --dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb --dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-netgear-raxe500.dtb ---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -@@ -1,5 +1,9 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_BCMBCA) += \ -+ bcm4906-netgear-r8000p.dtb \ -+ bcm4906-tplink-archer-c2300-v1.dtb \ -+ bcm4908-asus-gt-ac5300.dtb \ -+ bcm4908-netgear-raxe500.dtb \ - bcm4912-asus-gt-ax6000.dtb \ - bcm94912.dtb \ - bcm963158.dtb \ ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts -+++ /dev/null -@@ -1,157 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -- --#include --#include --#include -- --#include "bcm4906.dtsi" -- --/ { -- compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca"; -- model = "Netgear R8000P"; -- -- memory@0 { -- device_type = "memory"; -- reg = <0x00 0x00 0x00 0x20000000>; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- led-power-white { -- function = LED_FUNCTION_POWER; -- color = ; -- gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; -- }; -- -- led-power-amber { -- function = LED_FUNCTION_POWER; -- color = ; -- gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; -- }; -- -- led-wps { -- function = LED_FUNCTION_WPS; -- color = ; -- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; -- }; -- -- led-2ghz { -- function = "2ghz"; -- color = ; -- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; -- }; -- -- led-5ghz-1 { -- function = "5ghz-1"; -- color = ; -- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; -- }; -- -- led-5ghz-2 { -- function = "5ghz-2"; -- color = ; -- gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; -- }; -- -- led-usb2 { -- function = "usb2"; -- color = ; -- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; -- }; -- -- led-usb3 { -- function = "usb3"; -- color = ; -- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; -- }; -- -- led-wifi { -- function = "wifi"; -- color = ; -- gpios = <&gpio0 56 GPIO_ACTIVE_LOW>; -- }; -- }; --}; -- --&enet { -- nvmem-cells = <&base_mac_addr>; -- nvmem-cell-names = "mac-address"; --}; -- --&usb_phy { -- brcm,ioc = <1>; -- status = "okay"; --}; -- --&ehci { -- status = "okay"; --}; -- --&ohci { -- status = "okay"; --}; -- --&xhci { -- status = "okay"; --}; -- --&ports { -- port@0 { -- label = "lan4"; -- }; -- -- port@1 { -- label = "lan3"; -- }; -- -- port@2 { -- label = "lan2"; -- }; -- -- port@3 { -- label = "lan1"; -- }; -- -- port@7 { -- reg = <7>; -- phy-mode = "internal"; -- phy-handle = <&phy12>; -- label = "wan"; -- }; --}; -- --&nandcs { -- nand-ecc-strength = <4>; -- nand-ecc-step-size = <512>; -- nand-on-flash-bbt; -- -- #address-cells = <1>; -- #size-cells = <0>; -- -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- compatible = "nvmem-cells"; -- label = "cferom"; -- reg = <0x0 0x100000>; -- -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0 0x0 0x100000>; -- -- base_mac_addr: mac@106a0 { -- reg = <0x106a0 0x6>; -- }; -- }; -- -- partition@100000 { -- compatible = "brcm,bcm4908-firmware"; -- label = "firmware"; -- reg = <0x100000 0x4400000>; -- }; -- }; --}; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts -+++ /dev/null -@@ -1,182 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -- --#include --#include --#include -- --#include "bcm4906.dtsi" -- --/ { -- compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca"; -- model = "TP-Link Archer C2300 V1"; -- -- memory@0 { -- device_type = "memory"; -- reg = <0x00 0x00 0x00 0x20000000>; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- led-power { -- function = LED_FUNCTION_POWER; -- color = ; -- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; -- }; -- -- led-2ghz { -- function = "2ghz"; -- color = ; -- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; -- }; -- -- led-5ghz { -- function = "5ghz"; -- color = ; -- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; -- }; -- -- led-wan-amber { -- function = LED_FUNCTION_WAN; -- color = ; -- gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; -- }; -- -- led-wan-blue { -- function = LED_FUNCTION_WAN; -- color = ; -- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; -- }; -- -- led-lan { -- function = LED_FUNCTION_LAN; -- color = ; -- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; -- }; -- -- led-wps { -- function = LED_FUNCTION_WPS; -- color = ; -- gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; -- }; -- -- led-usb2 { -- function = "usb2"; -- color = ; -- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; -- }; -- -- led-usb3 { -- function = "usbd3"; -- color = ; -- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; -- }; -- -- led-brightness { -- function = LED_FUNCTION_BACKLIGHT; -- color = ; -- gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; -- }; -- }; -- -- gpio-keys-polled { -- compatible = "gpio-keys-polled"; -- poll-interval = <100>; -- -- key-brightness { -- label = "LEDs"; -- linux,code = ; -- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; -- }; -- -- key-wps { -- label = "WPS"; -- linux,code = ; -- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; -- }; -- -- key-wifi { -- label = "WiFi"; -- linux,code = ; -- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; -- }; -- -- key-restart { -- label = "Reset"; -- linux,code = ; -- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; -- }; -- }; --}; -- --&usb_phy { -- brcm,ioc = <1>; -- status = "okay"; --}; -- --&ehci { -- status = "okay"; --}; -- --&ohci { -- status = "okay"; --}; -- --&xhci { -- status = "okay"; --}; -- --&ports { -- port@0 { -- label = "lan4"; -- }; -- -- port@1 { -- label = "lan3"; -- }; -- -- port@2 { -- label = "lan2"; -- }; -- -- port@3 { -- label = "lan1"; -- }; -- -- port@7 { -- reg = <7>; -- phy-mode = "internal"; -- phy-handle = <&phy12>; -- label = "wan"; -- }; --}; -- --&nandcs { -- nand-ecc-strength = <4>; -- nand-ecc-step-size = <512>; -- nand-on-flash-bbt; -- -- #address-cells = <1>; -- #size-cells = <0>; -- -- partitions { -- compatible = "brcm,bcm4908-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "cferom"; -- reg = <0x0 0x100000>; -- }; -- -- partition@100000 { -- compatible = "brcm,bcm4908-firmware"; -- reg = <0x100000 0x3900000>; -- }; -- -- partition@5800000 { -- compatible = "brcm,bcm4908-firmware"; -- reg = <0x3a00000 0x3900000>; -- }; -- }; --}; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi -+++ /dev/null -@@ -1,26 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -- --#include "bcm4908.dtsi" -- --/ { -- cpus { -- /delete-node/ cpu@2; -- -- /delete-node/ cpu@3; -- }; -- -- timer { -- compatible = "arm,armv8-timer"; -- interrupts = , -- , -- , -- ; -- }; -- -- pmu { -- compatible = "arm,cortex-a53-pmu"; -- interrupts = , -- ; -- interrupt-affinity = <&cpu0>, <&cpu1>; -- }; --}; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts -+++ /dev/null -@@ -1,207 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -- --#include --#include --#include -- --#include "bcm4908.dtsi" -- --/ { -- compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca"; -- model = "Asus GT-AC5300"; -- -- memory@0 { -- device_type = "memory"; -- reg = <0x00 0x00 0x00 0x40000000>; -- }; -- -- gpio-keys-polled { -- compatible = "gpio-keys-polled"; -- poll-interval = <100>; -- -- key-wifi { -- label = "WiFi"; -- linux,code = ; -- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; -- }; -- -- key-wps { -- label = "WPS"; -- linux,code = ; -- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; -- }; -- -- key-restart { -- label = "Reset"; -- linux,code = ; -- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; -- }; -- -- key-brightness { -- label = "LEDs"; -- linux,code = ; -- gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; -- }; -- }; --}; -- --&enet { -- nvmem-cells = <&base_mac_addr>; -- nvmem-cell-names = "mac-address"; --}; -- --&usb_phy { -- brcm,ioc = <1>; -- status = "okay"; --}; -- --&ehci { -- status = "okay"; --}; -- --&ohci { -- status = "okay"; --}; -- --&xhci { -- status = "okay"; --}; -- --&ports { -- port@0 { -- label = "lan2"; -- }; -- -- port@1 { -- label = "lan1"; -- }; -- -- port@2 { -- label = "lan6"; -- }; -- -- port@3 { -- label = "lan5"; -- }; -- -- /* External BCM53134S switch */ -- port@7 { -- label = "sw"; -- reg = <7>; -- phy-mode = "rgmii"; -- -- fixed-link { -- speed = <1000>; -- full-duplex; -- }; -- }; --}; -- --&mdio { -- /* lan8 */ -- ethernet-phy@0 { -- reg = <0>; -- }; -- -- /* lan7 */ -- ethernet-phy@1 { -- reg = <1>; -- }; -- -- /* lan4 */ -- ethernet-phy@2 { -- reg = <2>; -- }; -- -- /* lan3 */ -- ethernet-phy@3 { -- reg = <3>; -- }; --}; -- --&leds { -- led-power@11 { -- reg = <0x11>; -- function = LED_FUNCTION_POWER; -- color = ; -- default-state = "on"; -- active-low; -- pinctrl-names = "default"; -- pinctrl-0 = <&pins_led_17_a>; -- }; -- -- led-wan-red@12 { -- reg = <0x12>; -- function = LED_FUNCTION_WAN; -- color = ; -- active-low; -- pinctrl-names = "default"; -- pinctrl-0 = <&pins_led_18_a>; -- }; -- -- led-wps@14 { -- reg = <0x14>; -- function = LED_FUNCTION_WPS; -- color = ; -- active-low; -- pinctrl-names = "default"; -- pinctrl-0 = <&pins_led_20_a>; -- }; -- -- led-wan-white@15 { -- reg = <0x15>; -- function = LED_FUNCTION_WAN; -- color = ; -- active-low; -- pinctrl-names = "default"; -- pinctrl-0 = <&pins_led_21_a>; -- }; -- -- led-lan@19 { -- reg = <0x19>; -- function = LED_FUNCTION_LAN; -- color = ; -- pinctrl-names = "default"; -- pinctrl-0 = <&pins_led_25_a>; -- }; --}; -- --&nandcs { -- nand-ecc-strength = <4>; -- nand-ecc-step-size = <512>; -- nand-on-flash-bbt; -- brcm,nand-has-wp; -- -- #address-cells = <1>; -- #size-cells = <0>; -- -- partitions { -- compatible = "brcm,bcm4908-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- compatible = "nvmem-cells"; -- label = "cferom"; -- reg = <0x0 0x100000>; -- -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0 0x0 0x100000>; -- -- base_mac_addr: mac@106a0 { -- reg = <0x106a0 0x6>; -- }; -- }; -- -- partition@100000 { -- compatible = "brcm,bcm4908-firmware"; -- reg = <0x100000 0x5700000>; -- }; -- -- partition@5800000 { -- compatible = "brcm,bcm4908-firmware"; -- reg = <0x5800000 0x5700000>; -- }; -- }; --}; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts -+++ /dev/null -@@ -1,50 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -- --#include "bcm4908.dtsi" -- --/ { -- compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca"; -- model = "Netgear RAXE500"; -- -- memory@0 { -- device_type = "memory"; -- reg = <0x00 0x00 0x00 0x40000000>; -- }; --}; -- --&ehci { -- status = "okay"; --}; -- --&ohci { -- status = "okay"; --}; -- --&xhci { -- status = "okay"; --}; -- --&ports { -- port@0 { -- label = "lan4"; -- }; -- -- port@1 { -- label = "lan3"; -- }; -- -- port@2 { -- label = "lan2"; -- }; -- -- port@3 { -- label = "lan1"; -- }; -- -- port@7 { -- reg = <7>; -- phy-mode = "internal"; -- phy-handle = <&phy12>; -- label = "wan"; -- }; --}; ---- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi -+++ /dev/null -@@ -1,575 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -- --#include --#include --#include --#include -- --/dts-v1/; -- --/ { -- interrupt-parent = <&gic>; -- -- #address-cells = <2>; -- #size-cells = <2>; -- -- aliases { -- serial0 = &uart0; -- }; -- -- chosen { -- stdout-path = "serial0:115200n8"; -- }; -- -- cpus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- cpu0: cpu@0 { -- device_type = "cpu"; -- compatible = "brcm,brahma-b53"; -- reg = <0x0>; -- enable-method = "spin-table"; -- cpu-release-addr = <0x0 0xfff8>; -- next-level-cache = <&l2>; -- }; -- -- cpu1: cpu@1 { -- device_type = "cpu"; -- compatible = "brcm,brahma-b53"; -- reg = <0x1>; -- enable-method = "spin-table"; -- cpu-release-addr = <0x0 0xfff8>; -- next-level-cache = <&l2>; -- }; -- -- cpu2: cpu@2 { -- device_type = "cpu"; -- compatible = "brcm,brahma-b53"; -- reg = <0x2>; -- enable-method = "spin-table"; -- cpu-release-addr = <0x0 0xfff8>; -- next-level-cache = <&l2>; -- }; -- -- cpu3: cpu@3 { -- device_type = "cpu"; -- compatible = "brcm,brahma-b53"; -- reg = <0x3>; -- enable-method = "spin-table"; -- cpu-release-addr = <0x0 0xfff8>; -- next-level-cache = <&l2>; -- }; -- -- l2: l2-cache0 { -- compatible = "cache"; -- }; -- }; -- -- axi@81000000 { -- compatible = "simple-bus"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0x00 0x00 0x81000000 0x4000>; -- -- gic: interrupt-controller@1000 { -- compatible = "arm,gic-400"; -- #interrupt-cells = <3>; -- #address-cells = <0>; -- interrupt-controller; -- reg = <0x1000 0x1000>, -- <0x2000 0x2000>; -- }; -- }; -- -- timer { -- compatible = "arm,armv8-timer"; -- interrupts = , -- , -- , -- ; -- }; -- -- pmu { -- compatible = "arm,cortex-a53-pmu"; -- interrupts = , -- , -- , -- ; -- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -- }; -- -- clocks { -- periph_clk: periph_clk { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-frequency = <50000000>; -- clock-output-names = "periph"; -- }; -- }; -- -- soc { -- compatible = "simple-bus"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0x00 0x00 0x80000000 0x281000>; -- -- enet: ethernet@2000 { -- compatible = "brcm,bcm4908-enet"; -- reg = <0x2000 0x1000>; -- -- interrupts = , -- ; -- interrupt-names = "rx", "tx"; -- }; -- -- usb_phy: usb-phy@c200 { -- compatible = "brcm,bcm4908-usb-phy"; -- reg = <0xc200 0x100>; -- reg-names = "ctrl"; -- power-domains = <&pmb BCM_PMB_HOST_USB>; -- dr_mode = "host"; -- brcm,has-xhci; -- brcm,has-eohci; -- #phy-cells = <1>; -- status = "disabled"; -- }; -- -- ehci: usb@c300 { -- compatible = "generic-ehci"; -- reg = <0xc300 0x100>; -- interrupts = ; -- phys = <&usb_phy PHY_TYPE_USB2>; -- status = "disabled"; -- }; -- -- ohci: usb@c400 { -- compatible = "generic-ohci"; -- reg = <0xc400 0x100>; -- interrupts = ; -- phys = <&usb_phy PHY_TYPE_USB2>; -- status = "disabled"; -- }; -- -- xhci: usb@d000 { -- compatible = "generic-xhci"; -- reg = <0xd000 0x8c8>; -- interrupts = ; -- phys = <&usb_phy PHY_TYPE_USB3>; -- status = "disabled"; -- }; -- -- bus@80000 { -- compatible = "simple-bus"; -- #size-cells = <1>; -- #address-cells = <1>; -- ranges = <0 0x80000 0x50000>; -- -- ethernet-switch@0 { -- compatible = "brcm,bcm4908-switch"; -- reg = <0x0 0x40000>, -- <0x40000 0x110>, -- <0x40340 0x30>, -- <0x40380 0x30>, -- <0x40600 0x34>, -- <0x40800 0x208>; -- reg-names = "core", "reg", "intrl2_0", -- "intrl2_1", "fcb", "acb"; -- interrupts = , -- ; -- brcm,num-gphy = <5>; -- brcm,num-rgmii-ports = <2>; -- -- #address-cells = <1>; -- #size-cells = <0>; -- -- ports: ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- phy-mode = "internal"; -- phy-handle = <&phy8>; -- }; -- -- port@1 { -- reg = <1>; -- phy-mode = "internal"; -- phy-handle = <&phy9>; -- }; -- -- port@2 { -- reg = <2>; -- phy-mode = "internal"; -- phy-handle = <&phy10>; -- }; -- -- port@3 { -- reg = <3>; -- phy-mode = "internal"; -- phy-handle = <&phy11>; -- }; -- -- port@8 { -- reg = <8>; -- phy-mode = "internal"; -- ethernet = <&enet>; -- -- fixed-link { -- speed = <1000>; -- full-duplex; -- }; -- }; -- }; -- }; -- -- mdio: mdio@405c0 { -- compatible = "brcm,unimac-mdio"; -- reg = <0x405c0 0x8>; -- reg-names = "mdio"; -- #size-cells = <0>; -- #address-cells = <1>; -- -- phy8: ethernet-phy@8 { -- reg = <8>; -- }; -- -- phy9: ethernet-phy@9 { -- reg = <9>; -- }; -- -- phy10: ethernet-phy@a { -- reg = <10>; -- }; -- -- phy11: ethernet-phy@b { -- reg = <11>; -- }; -- -- phy12: ethernet-phy@c { -- reg = <12>; -- }; -- }; -- }; -- -- procmon: syscon@280000 { -- compatible = "simple-bus"; -- reg = <0x280000 0x1000>; -- ranges; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- pmb: power-controller@2800c0 { -- compatible = "brcm,bcm4908-pmb"; -- reg = <0x2800c0 0x40>; -- #power-domain-cells = <1>; -- }; -- }; -- }; -- -- bus@ff800000 { -- compatible = "simple-bus"; -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0x00 0x00 0xff800000 0x3000>; -- -- twd: timer-mfd@400 { -- compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; -- reg = <0x400 0x4c>; -- ranges = <0x0 0x400 0x4c>; -- -- #address-cells = <1>; -- #size-cells = <1>; -- -- watchdog@28 { -- compatible = "brcm,bcm6345-wdt"; -- reg = <0x28 0x8>; -- }; -- }; -- -- gpio0: gpio-controller@500 { -- compatible = "brcm,bcm6345-gpio"; -- reg-names = "dirout", "dat"; -- reg = <0x500 0x28>, <0x528 0x28>; -- -- #gpio-cells = <2>; -- gpio-controller; -- }; -- -- pinctrl@560 { -- compatible = "brcm,bcm4908-pinctrl"; -- reg = <0x560 0x10>; -- -- pins_led_0_a: led_0-a-pins { -- function = "led_0"; -- groups = "led_0_grp_a"; -- }; -- -- pins_led_1_a: led_1-a-pins { -- function = "led_1"; -- groups = "led_1_grp_a"; -- }; -- -- pins_led_2_a: led_2-a-pins { -- function = "led_2"; -- groups = "led_2_grp_a"; -- }; -- -- pins_led_3_a: led_3-a-pins { -- function = "led_3"; -- groups = "led_3_grp_a"; -- }; -- -- pins_led_4_a: led_4-a-pins { -- function = "led_4"; -- groups = "led_4_grp_a"; -- }; -- -- pins_led_5_a: led_5-a-pins { -- function = "led_5"; -- groups = "led_5_grp_a"; -- }; -- -- pins_led_6_a: led_6-a-pins { -- function = "led_6"; -- groups = "led_6_grp_a"; -- }; -- -- pins_led_7_a: led_7-a-pins { -- function = "led_7"; -- groups = "led_7_grp_a"; -- }; -- -- pins_led_8_a: led_8-a-pins { -- function = "led_8"; -- groups = "led_8_grp_a"; -- }; -- -- pins_led_9_a: led_9-a-pins { -- function = "led_9"; -- groups = "led_9_grp_a"; -- }; -- -- pins_led_10_a: led_10-a-pins { -- function = "led_10"; -- groups = "led_10_grp_a"; -- }; -- -- pins_led_11_a: led_11-a-pins { -- function = "led_11"; -- groups = "led_11_grp_a"; -- }; -- -- pins_led_12_a: led_12-a-pins { -- function = "led_12"; -- groups = "led_12_grp_a"; -- }; -- -- pins_led_13_a: led_13-a-pins { -- function = "led_13"; -- groups = "led_13_grp_a"; -- }; -- -- pins_led_14_a: led_14-a-pins { -- function = "led_14"; -- groups = "led_14_grp_a"; -- }; -- -- pins_led_15_a: led_15-a-pins { -- function = "led_15"; -- groups = "led_15_grp_a"; -- }; -- -- pins_led_16_a: led_16-a-pins { -- function = "led_16"; -- groups = "led_16_grp_a"; -- }; -- -- pins_led_17_a: led_17-a-pins { -- function = "led_17"; -- groups = "led_17_grp_a"; -- }; -- -- pins_led_18_a: led_18-a-pins { -- function = "led_18"; -- groups = "led_18_grp_a"; -- }; -- -- pins_led_19_a: led_19-a-pins { -- function = "led_19"; -- groups = "led_19_grp_a"; -- }; -- -- pins_led_20_a: led_20-a-pins { -- function = "led_20"; -- groups = "led_20_grp_a"; -- }; -- -- pins_led_21_a: led_21-a-pins { -- function = "led_21"; -- groups = "led_21_grp_a"; -- }; -- -- pins_led_22_a: led_22-a-pins { -- function = "led_22"; -- groups = "led_22_grp_a"; -- }; -- -- pins_led_23_a: led_23-a-pins { -- function = "led_23"; -- groups = "led_23_grp_a"; -- }; -- -- pins_led_24_a: led_24-a-pins { -- function = "led_24"; -- groups = "led_24_grp_a"; -- }; -- -- pins_led_25_a: led_25-a-pins { -- function = "led_25"; -- groups = "led_25_grp_a"; -- }; -- -- pins_led_26_a: led_26-a-pins { -- function = "led_26"; -- groups = "led_26_grp_a"; -- }; -- -- pins_led_27_a: led_27-a-pins { -- function = "led_27"; -- groups = "led_27_grp_a"; -- }; -- -- pins_led_28_a: led_28-a-pins { -- function = "led_28"; -- groups = "led_28_grp_a"; -- }; -- -- pins_led_29_a: led_29-a-pins { -- function = "led_29"; -- groups = "led_29_grp_a"; -- }; -- -- pins_led_30_a: led_30-a-pins { -- function = "led_30"; -- groups = "led_30_grp_a"; -- }; -- -- pins_led_31_a: led_31-a-pins { -- function = "led_31"; -- groups = "led_31_grp_a"; -- }; -- -- pins_hs_uart: hs_uart-pins { -- function = "hs_uart"; -- groups = "hs_uart_grp"; -- }; -- -- pins_i2c_a: i2c-a-pins { -- function = "i2c"; -- groups = "i2c_grp_a"; -- }; -- -- pins_i2c_b: i2c-b-pins { -- function = "i2c"; -- groups = "i2c_grp_b"; -- }; -- -- pins_i2s: i2s-pins { -- function = "i2s"; -- groups = "i2s_grp"; -- }; -- -- pins_nand_ctrl: nand_ctrl-pins { -- function = "nand_ctrl"; -- groups = "nand_ctrl_grp"; -- }; -- -- pins_nand_data: nand_data-pins { -- function = "nand_data"; -- groups = "nand_data_grp"; -- }; -- -- pins_emmc_ctrl: emmc_ctrl-pins { -- function = "emmc_ctrl"; -- groups = "emmc_ctrl_grp"; -- }; -- -- pins_usb0_pwr: usb0_pwr-pins { -- function = "usb0_pwr"; -- groups = "usb0_pwr_grp"; -- }; -- -- pins_usb1_pwr: usb1_pwr-pins { -- function = "usb1_pwr"; -- groups = "usb1_pwr_grp"; -- }; -- }; -- -- uart0: serial@640 { -- compatible = "brcm,bcm6345-uart"; -- reg = <0x640 0x18>; -- interrupts = ; -- clocks = <&periph_clk>; -- clock-names = "refclk"; -- status = "okay"; -- }; -- -- leds: leds@800 { -- compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds"; -- reg = <0x800 0xdc>; -- -- #address-cells = <1>; -- #size-cells = <0>; -- }; -- -- nand-controller@1800 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; -- reg = <0x1800 0x600>, <0x2000 0x10>; -- reg-names = "nand", "nand-int-base"; -- interrupts = ; -- interrupt-names = "nand"; -- status = "okay"; -- -- nandcs: nand@0 { -- compatible = "brcm,nandcs"; -- reg = <0>; -- }; -- }; -- -- i2c@2100 { -- compatible = "brcm,brcmper-i2c"; -- reg = <0x2100 0x58>; -- clock-frequency = <97500>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pins_i2c_a>; -- status = "disabled"; -- }; -- -- misc@2600 { -- compatible = "brcm,misc", "simple-mfd"; -- reg = <0x2600 0xe4>; -- -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0x00 0x2600 0xe4>; -- -- reset-controller@2644 { -- compatible = "brcm,bcm4908-misc-pcie-reset"; -- reg = <0x44 0x04>; -- #reset-cells = <1>; -- }; -- }; -- }; -- -- reboot { -- compatible = "syscon-reboot"; -- regmap = <&twd>; -- offset = <0x34>; -- mask = <1>; -- }; --}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts -@@ -0,0 +1,157 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include -+#include -+#include -+ -+#include "bcm4906.dtsi" -+ -+/ { -+ compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca"; -+ model = "Netgear R8000P"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00 0x00 0x00 0x20000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-power-white { -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-power-amber { -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-wps { -+ function = LED_FUNCTION_WPS; -+ color = ; -+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-2ghz { -+ function = "2ghz"; -+ color = ; -+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-5ghz-1 { -+ function = "5ghz-1"; -+ color = ; -+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-5ghz-2 { -+ function = "5ghz-2"; -+ color = ; -+ gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-usb2 { -+ function = "usb2"; -+ color = ; -+ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-usb3 { -+ function = "usb3"; -+ color = ; -+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-wifi { -+ function = "wifi"; -+ color = ; -+ gpios = <&gpio0 56 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&enet { -+ nvmem-cells = <&base_mac_addr>; -+ nvmem-cell-names = "mac-address"; -+}; -+ -+&usb_phy { -+ brcm,ioc = <1>; -+ status = "okay"; -+}; -+ -+&ehci { -+ status = "okay"; -+}; -+ -+&ohci { -+ status = "okay"; -+}; -+ -+&xhci { -+ status = "okay"; -+}; -+ -+&ports { -+ port@0 { -+ label = "lan4"; -+ }; -+ -+ port@1 { -+ label = "lan3"; -+ }; -+ -+ port@2 { -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ label = "lan1"; -+ }; -+ -+ port@7 { -+ reg = <7>; -+ phy-mode = "internal"; -+ phy-handle = <&phy12>; -+ label = "wan"; -+ }; -+}; -+ -+&nandcs { -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; -+ nand-on-flash-bbt; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ compatible = "nvmem-cells"; -+ label = "cferom"; -+ reg = <0x0 0x100000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x0 0x100000>; -+ -+ base_mac_addr: mac@106a0 { -+ reg = <0x106a0 0x6>; -+ }; -+ }; -+ -+ partition@100000 { -+ compatible = "brcm,bcm4908-firmware"; -+ label = "firmware"; -+ reg = <0x100000 0x4400000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts -@@ -0,0 +1,182 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include -+#include -+#include -+ -+#include "bcm4906.dtsi" -+ -+/ { -+ compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca"; -+ model = "TP-Link Archer C2300 V1"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00 0x00 0x00 0x20000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-power { -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-2ghz { -+ function = "2ghz"; -+ color = ; -+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-5ghz { -+ function = "5ghz"; -+ color = ; -+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-wan-amber { -+ function = LED_FUNCTION_WAN; -+ color = ; -+ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-wan-blue { -+ function = LED_FUNCTION_WAN; -+ color = ; -+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-lan { -+ function = LED_FUNCTION_LAN; -+ color = ; -+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-wps { -+ function = LED_FUNCTION_WPS; -+ color = ; -+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-usb2 { -+ function = "usb2"; -+ color = ; -+ gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-usb3 { -+ function = "usbd3"; -+ color = ; -+ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-brightness { -+ function = LED_FUNCTION_BACKLIGHT; -+ color = ; -+ gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-keys-polled { -+ compatible = "gpio-keys-polled"; -+ poll-interval = <100>; -+ -+ key-brightness { -+ label = "LEDs"; -+ linux,code = ; -+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; -+ }; -+ -+ key-wps { -+ label = "WPS"; -+ linux,code = ; -+ gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; -+ }; -+ -+ key-wifi { -+ label = "WiFi"; -+ linux,code = ; -+ gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; -+ }; -+ -+ key-restart { -+ label = "Reset"; -+ linux,code = ; -+ gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&usb_phy { -+ brcm,ioc = <1>; -+ status = "okay"; -+}; -+ -+&ehci { -+ status = "okay"; -+}; -+ -+&ohci { -+ status = "okay"; -+}; -+ -+&xhci { -+ status = "okay"; -+}; -+ -+&ports { -+ port@0 { -+ label = "lan4"; -+ }; -+ -+ port@1 { -+ label = "lan3"; -+ }; -+ -+ port@2 { -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ label = "lan1"; -+ }; -+ -+ port@7 { -+ reg = <7>; -+ phy-mode = "internal"; -+ phy-handle = <&phy12>; -+ label = "wan"; -+ }; -+}; -+ -+&nandcs { -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; -+ nand-on-flash-bbt; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ partitions { -+ compatible = "brcm,bcm4908-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "cferom"; -+ reg = <0x0 0x100000>; -+ }; -+ -+ partition@100000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x100000 0x3900000>; -+ }; -+ -+ partition@5800000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x3a00000 0x3900000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include "bcm4908.dtsi" -+ -+/ { -+ cpus { -+ /delete-node/ cpu@2; -+ -+ /delete-node/ cpu@3; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ ; -+ interrupt-affinity = <&cpu0>, <&cpu1>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts -@@ -0,0 +1,207 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include -+#include -+#include -+ -+#include "bcm4908.dtsi" -+ -+/ { -+ compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca"; -+ model = "Asus GT-AC5300"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00 0x00 0x00 0x40000000>; -+ }; -+ -+ gpio-keys-polled { -+ compatible = "gpio-keys-polled"; -+ poll-interval = <100>; -+ -+ key-wifi { -+ label = "WiFi"; -+ linux,code = ; -+ gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; -+ }; -+ -+ key-wps { -+ label = "WPS"; -+ linux,code = ; -+ gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; -+ }; -+ -+ key-restart { -+ label = "Reset"; -+ linux,code = ; -+ gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; -+ }; -+ -+ key-brightness { -+ label = "LEDs"; -+ linux,code = ; -+ gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&enet { -+ nvmem-cells = <&base_mac_addr>; -+ nvmem-cell-names = "mac-address"; -+}; -+ -+&usb_phy { -+ brcm,ioc = <1>; -+ status = "okay"; -+}; -+ -+&ehci { -+ status = "okay"; -+}; -+ -+&ohci { -+ status = "okay"; -+}; -+ -+&xhci { -+ status = "okay"; -+}; -+ -+&ports { -+ port@0 { -+ label = "lan2"; -+ }; -+ -+ port@1 { -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ label = "lan6"; -+ }; -+ -+ port@3 { -+ label = "lan5"; -+ }; -+ -+ /* External BCM53134S switch */ -+ port@7 { -+ label = "sw"; -+ reg = <7>; -+ phy-mode = "rgmii"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+}; -+ -+&mdio { -+ /* lan8 */ -+ ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ /* lan7 */ -+ ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ /* lan4 */ -+ ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ /* lan3 */ -+ ethernet-phy@3 { -+ reg = <3>; -+ }; -+}; -+ -+&leds { -+ led-power@11 { -+ reg = <0x11>; -+ function = LED_FUNCTION_POWER; -+ color = ; -+ default-state = "on"; -+ active-low; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_17_a>; -+ }; -+ -+ led-wan-red@12 { -+ reg = <0x12>; -+ function = LED_FUNCTION_WAN; -+ color = ; -+ active-low; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_18_a>; -+ }; -+ -+ led-wps@14 { -+ reg = <0x14>; -+ function = LED_FUNCTION_WPS; -+ color = ; -+ active-low; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_20_a>; -+ }; -+ -+ led-wan-white@15 { -+ reg = <0x15>; -+ function = LED_FUNCTION_WAN; -+ color = ; -+ active-low; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_21_a>; -+ }; -+ -+ led-lan@19 { -+ reg = <0x19>; -+ function = LED_FUNCTION_LAN; -+ color = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_led_25_a>; -+ }; -+}; -+ -+&nandcs { -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; -+ nand-on-flash-bbt; -+ brcm,nand-has-wp; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ partitions { -+ compatible = "brcm,bcm4908-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ compatible = "nvmem-cells"; -+ label = "cferom"; -+ reg = <0x0 0x100000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x0 0x100000>; -+ -+ base_mac_addr: mac@106a0 { -+ reg = <0x106a0 0x6>; -+ }; -+ }; -+ -+ partition@100000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x100000 0x5700000>; -+ }; -+ -+ partition@5800000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x5800000 0x5700000>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts -@@ -0,0 +1,50 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include "bcm4908.dtsi" -+ -+/ { -+ compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca"; -+ model = "Netgear RAXE500"; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00 0x00 0x00 0x40000000>; -+ }; -+}; -+ -+&ehci { -+ status = "okay"; -+}; -+ -+&ohci { -+ status = "okay"; -+}; -+ -+&xhci { -+ status = "okay"; -+}; -+ -+&ports { -+ port@0 { -+ label = "lan4"; -+ }; -+ -+ port@1 { -+ label = "lan3"; -+ }; -+ -+ port@2 { -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ label = "lan1"; -+ }; -+ -+ port@7 { -+ reg = <7>; -+ phy-mode = "internal"; -+ phy-handle = <&phy12>; -+ label = "wan"; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -@@ -0,0 +1,575 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+ -+#include -+#include -+#include -+#include -+ -+/dts-v1/; -+ -+/ { -+ interrupt-parent = <&gic>; -+ -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "brcm,brahma-b53"; -+ reg = <0x0>; -+ enable-method = "spin-table"; -+ cpu-release-addr = <0x0 0xfff8>; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "brcm,brahma-b53"; -+ reg = <0x1>; -+ enable-method = "spin-table"; -+ cpu-release-addr = <0x0 0xfff8>; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "brcm,brahma-b53"; -+ reg = <0x2>; -+ enable-method = "spin-table"; -+ cpu-release-addr = <0x0 0xfff8>; -+ next-level-cache = <&l2>; -+ }; -+ -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "brcm,brahma-b53"; -+ reg = <0x3>; -+ enable-method = "spin-table"; -+ cpu-release-addr = <0x0 0xfff8>; -+ next-level-cache = <&l2>; -+ }; -+ -+ l2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ }; -+ -+ axi@81000000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x00 0x00 0x81000000 0x4000>; -+ -+ gic: interrupt-controller@1000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ #address-cells = <0>; -+ interrupt-controller; -+ reg = <0x1000 0x1000>, -+ <0x2000 0x2000>; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a53-pmu"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -+ }; -+ -+ clocks { -+ periph_clk: periph_clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <50000000>; -+ clock-output-names = "periph"; -+ }; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x00 0x00 0x80000000 0x281000>; -+ -+ enet: ethernet@2000 { -+ compatible = "brcm,bcm4908-enet"; -+ reg = <0x2000 0x1000>; -+ -+ interrupts = , -+ ; -+ interrupt-names = "rx", "tx"; -+ }; -+ -+ usb_phy: usb-phy@c200 { -+ compatible = "brcm,bcm4908-usb-phy"; -+ reg = <0xc200 0x100>; -+ reg-names = "ctrl"; -+ power-domains = <&pmb BCM_PMB_HOST_USB>; -+ dr_mode = "host"; -+ brcm,has-xhci; -+ brcm,has-eohci; -+ #phy-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ ehci: usb@c300 { -+ compatible = "generic-ehci"; -+ reg = <0xc300 0x100>; -+ interrupts = ; -+ phys = <&usb_phy PHY_TYPE_USB2>; -+ status = "disabled"; -+ }; -+ -+ ohci: usb@c400 { -+ compatible = "generic-ohci"; -+ reg = <0xc400 0x100>; -+ interrupts = ; -+ phys = <&usb_phy PHY_TYPE_USB2>; -+ status = "disabled"; -+ }; -+ -+ xhci: usb@d000 { -+ compatible = "generic-xhci"; -+ reg = <0xd000 0x8c8>; -+ interrupts = ; -+ phys = <&usb_phy PHY_TYPE_USB3>; -+ status = "disabled"; -+ }; -+ -+ bus@80000 { -+ compatible = "simple-bus"; -+ #size-cells = <1>; -+ #address-cells = <1>; -+ ranges = <0 0x80000 0x50000>; -+ -+ ethernet-switch@0 { -+ compatible = "brcm,bcm4908-switch"; -+ reg = <0x0 0x40000>, -+ <0x40000 0x110>, -+ <0x40340 0x30>, -+ <0x40380 0x30>, -+ <0x40600 0x34>, -+ <0x40800 0x208>; -+ reg-names = "core", "reg", "intrl2_0", -+ "intrl2_1", "fcb", "acb"; -+ interrupts = , -+ ; -+ brcm,num-gphy = <5>; -+ brcm,num-rgmii-ports = <2>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ports: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ phy-mode = "internal"; -+ phy-handle = <&phy8>; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ phy-mode = "internal"; -+ phy-handle = <&phy9>; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ phy-mode = "internal"; -+ phy-handle = <&phy10>; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ phy-mode = "internal"; -+ phy-handle = <&phy11>; -+ }; -+ -+ port@8 { -+ reg = <8>; -+ phy-mode = "internal"; -+ ethernet = <&enet>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+ }; -+ -+ mdio: mdio@405c0 { -+ compatible = "brcm,unimac-mdio"; -+ reg = <0x405c0 0x8>; -+ reg-names = "mdio"; -+ #size-cells = <0>; -+ #address-cells = <1>; -+ -+ phy8: ethernet-phy@8 { -+ reg = <8>; -+ }; -+ -+ phy9: ethernet-phy@9 { -+ reg = <9>; -+ }; -+ -+ phy10: ethernet-phy@a { -+ reg = <10>; -+ }; -+ -+ phy11: ethernet-phy@b { -+ reg = <11>; -+ }; -+ -+ phy12: ethernet-phy@c { -+ reg = <12>; -+ }; -+ }; -+ }; -+ -+ procmon: syscon@280000 { -+ compatible = "simple-bus"; -+ reg = <0x280000 0x1000>; -+ ranges; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ pmb: power-controller@2800c0 { -+ compatible = "brcm,bcm4908-pmb"; -+ reg = <0x2800c0 0x40>; -+ #power-domain-cells = <1>; -+ }; -+ }; -+ }; -+ -+ bus@ff800000 { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x00 0x00 0xff800000 0x3000>; -+ -+ twd: timer-mfd@400 { -+ compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; -+ reg = <0x400 0x4c>; -+ ranges = <0x0 0x400 0x4c>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ watchdog@28 { -+ compatible = "brcm,bcm6345-wdt"; -+ reg = <0x28 0x8>; -+ }; -+ }; -+ -+ gpio0: gpio-controller@500 { -+ compatible = "brcm,bcm6345-gpio"; -+ reg-names = "dirout", "dat"; -+ reg = <0x500 0x28>, <0x528 0x28>; -+ -+ #gpio-cells = <2>; -+ gpio-controller; -+ }; -+ -+ pinctrl@560 { -+ compatible = "brcm,bcm4908-pinctrl"; -+ reg = <0x560 0x10>; -+ -+ pins_led_0_a: led_0-a-pins { -+ function = "led_0"; -+ groups = "led_0_grp_a"; -+ }; -+ -+ pins_led_1_a: led_1-a-pins { -+ function = "led_1"; -+ groups = "led_1_grp_a"; -+ }; -+ -+ pins_led_2_a: led_2-a-pins { -+ function = "led_2"; -+ groups = "led_2_grp_a"; -+ }; -+ -+ pins_led_3_a: led_3-a-pins { -+ function = "led_3"; -+ groups = "led_3_grp_a"; -+ }; -+ -+ pins_led_4_a: led_4-a-pins { -+ function = "led_4"; -+ groups = "led_4_grp_a"; -+ }; -+ -+ pins_led_5_a: led_5-a-pins { -+ function = "led_5"; -+ groups = "led_5_grp_a"; -+ }; -+ -+ pins_led_6_a: led_6-a-pins { -+ function = "led_6"; -+ groups = "led_6_grp_a"; -+ }; -+ -+ pins_led_7_a: led_7-a-pins { -+ function = "led_7"; -+ groups = "led_7_grp_a"; -+ }; -+ -+ pins_led_8_a: led_8-a-pins { -+ function = "led_8"; -+ groups = "led_8_grp_a"; -+ }; -+ -+ pins_led_9_a: led_9-a-pins { -+ function = "led_9"; -+ groups = "led_9_grp_a"; -+ }; -+ -+ pins_led_10_a: led_10-a-pins { -+ function = "led_10"; -+ groups = "led_10_grp_a"; -+ }; -+ -+ pins_led_11_a: led_11-a-pins { -+ function = "led_11"; -+ groups = "led_11_grp_a"; -+ }; -+ -+ pins_led_12_a: led_12-a-pins { -+ function = "led_12"; -+ groups = "led_12_grp_a"; -+ }; -+ -+ pins_led_13_a: led_13-a-pins { -+ function = "led_13"; -+ groups = "led_13_grp_a"; -+ }; -+ -+ pins_led_14_a: led_14-a-pins { -+ function = "led_14"; -+ groups = "led_14_grp_a"; -+ }; -+ -+ pins_led_15_a: led_15-a-pins { -+ function = "led_15"; -+ groups = "led_15_grp_a"; -+ }; -+ -+ pins_led_16_a: led_16-a-pins { -+ function = "led_16"; -+ groups = "led_16_grp_a"; -+ }; -+ -+ pins_led_17_a: led_17-a-pins { -+ function = "led_17"; -+ groups = "led_17_grp_a"; -+ }; -+ -+ pins_led_18_a: led_18-a-pins { -+ function = "led_18"; -+ groups = "led_18_grp_a"; -+ }; -+ -+ pins_led_19_a: led_19-a-pins { -+ function = "led_19"; -+ groups = "led_19_grp_a"; -+ }; -+ -+ pins_led_20_a: led_20-a-pins { -+ function = "led_20"; -+ groups = "led_20_grp_a"; -+ }; -+ -+ pins_led_21_a: led_21-a-pins { -+ function = "led_21"; -+ groups = "led_21_grp_a"; -+ }; -+ -+ pins_led_22_a: led_22-a-pins { -+ function = "led_22"; -+ groups = "led_22_grp_a"; -+ }; -+ -+ pins_led_23_a: led_23-a-pins { -+ function = "led_23"; -+ groups = "led_23_grp_a"; -+ }; -+ -+ pins_led_24_a: led_24-a-pins { -+ function = "led_24"; -+ groups = "led_24_grp_a"; -+ }; -+ -+ pins_led_25_a: led_25-a-pins { -+ function = "led_25"; -+ groups = "led_25_grp_a"; -+ }; -+ -+ pins_led_26_a: led_26-a-pins { -+ function = "led_26"; -+ groups = "led_26_grp_a"; -+ }; -+ -+ pins_led_27_a: led_27-a-pins { -+ function = "led_27"; -+ groups = "led_27_grp_a"; -+ }; -+ -+ pins_led_28_a: led_28-a-pins { -+ function = "led_28"; -+ groups = "led_28_grp_a"; -+ }; -+ -+ pins_led_29_a: led_29-a-pins { -+ function = "led_29"; -+ groups = "led_29_grp_a"; -+ }; -+ -+ pins_led_30_a: led_30-a-pins { -+ function = "led_30"; -+ groups = "led_30_grp_a"; -+ }; -+ -+ pins_led_31_a: led_31-a-pins { -+ function = "led_31"; -+ groups = "led_31_grp_a"; -+ }; -+ -+ pins_hs_uart: hs_uart-pins { -+ function = "hs_uart"; -+ groups = "hs_uart_grp"; -+ }; -+ -+ pins_i2c_a: i2c-a-pins { -+ function = "i2c"; -+ groups = "i2c_grp_a"; -+ }; -+ -+ pins_i2c_b: i2c-b-pins { -+ function = "i2c"; -+ groups = "i2c_grp_b"; -+ }; -+ -+ pins_i2s: i2s-pins { -+ function = "i2s"; -+ groups = "i2s_grp"; -+ }; -+ -+ pins_nand_ctrl: nand_ctrl-pins { -+ function = "nand_ctrl"; -+ groups = "nand_ctrl_grp"; -+ }; -+ -+ pins_nand_data: nand_data-pins { -+ function = "nand_data"; -+ groups = "nand_data_grp"; -+ }; -+ -+ pins_emmc_ctrl: emmc_ctrl-pins { -+ function = "emmc_ctrl"; -+ groups = "emmc_ctrl_grp"; -+ }; -+ -+ pins_usb0_pwr: usb0_pwr-pins { -+ function = "usb0_pwr"; -+ groups = "usb0_pwr_grp"; -+ }; -+ -+ pins_usb1_pwr: usb1_pwr-pins { -+ function = "usb1_pwr"; -+ groups = "usb1_pwr_grp"; -+ }; -+ }; -+ -+ uart0: serial@640 { -+ compatible = "brcm,bcm6345-uart"; -+ reg = <0x640 0x18>; -+ interrupts = ; -+ clocks = <&periph_clk>; -+ clock-names = "refclk"; -+ status = "okay"; -+ }; -+ -+ leds: leds@800 { -+ compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds"; -+ reg = <0x800 0xdc>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ nand-controller@1800 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; -+ reg = <0x1800 0x600>, <0x2000 0x10>; -+ reg-names = "nand", "nand-int-base"; -+ interrupts = ; -+ interrupt-names = "nand"; -+ status = "okay"; -+ -+ nandcs: nand@0 { -+ compatible = "brcm,nandcs"; -+ reg = <0>; -+ }; -+ }; -+ -+ i2c@2100 { -+ compatible = "brcm,brcmper-i2c"; -+ reg = <0x2100 0x58>; -+ clock-frequency = <97500>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pins_i2c_a>; -+ status = "disabled"; -+ }; -+ -+ misc@2600 { -+ compatible = "brcm,misc", "simple-mfd"; -+ reg = <0x2600 0xe4>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x00 0x2600 0xe4>; -+ -+ reset-controller@2644 { -+ compatible = "brcm,bcm4908-misc-pcie-reset"; -+ reg = <0x44 0x04>; -+ #reset-cells = <1>; -+ }; -+ }; -+ }; -+ -+ reboot { -+ compatible = "syscon-reboot"; -+ regmap = <&twd>; -+ offset = <0x34>; -+ mask = <1>; -+ }; -+}; diff --git a/target/linux/bcm4908/patches-5.10/038-v6.1-0006-arm64-dts-Add-BCM4908-generic-board-dts.patch b/target/linux/bcm4908/patches-5.10/038-v6.1-0006-arm64-dts-Add-BCM4908-generic-board-dts.patch deleted file mode 100644 index b19c5d33b4..0000000000 --- a/target/linux/bcm4908/patches-5.10/038-v6.1-0006-arm64-dts-Add-BCM4908-generic-board-dts.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 72e0bdb6d7edb1785d58f2e8e7c80e1d2f93a319 Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Wed, 3 Aug 2022 10:54:51 -0700 -Subject: [PATCH] arm64: dts: Add BCM4908 generic board dts - -Add generic bare bone bcm94908.dts file to support any 4908 based -design. It supports cpu subsystem, memory and an uart console. This can -be useful for board bring-up and cpu subsystem and memory related kernel -test as well. - -Signed-off-by: William Zhang -Link: https://lore.kernel.org/r/20220803175455.47638-6-william.zhang@broadcom.com -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 1 + - .../boot/dts/broadcom/bcmbca/bcm94908.dts | 30 +++++++++++++++++++ - 2 files changed, 31 insertions(+) - create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile -@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \ - bcm4906-tplink-archer-c2300-v1.dtb \ - bcm4908-asus-gt-ac5300.dtb \ - bcm4908-netgear-raxe500.dtb \ -+ bcm94908.dtb \ - bcm4912-asus-gt-ax6000.dtb \ - bcm94912.dtb \ - bcm963158.dtb \ ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts -@@ -0,0 +1,30 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright 2022 Broadcom Ltd. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4908.dtsi" -+ -+/ { -+ model = "Broadcom BCM94908 Reference Board"; -+ compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca"; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x0 0x0 0x0 0x08000000>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm4908/patches-5.10/039-v6.2-0001-arm64-dts-broadcom-bcmbca-bcm4908-add-TWD-block-time.patch b/target/linux/bcm4908/patches-5.10/039-v6.2-0001-arm64-dts-broadcom-bcmbca-bcm4908-add-TWD-block-time.patch deleted file mode 100644 index a3f49ca440..0000000000 --- a/target/linux/bcm4908/patches-5.10/039-v6.2-0001-arm64-dts-broadcom-bcmbca-bcm4908-add-TWD-block-time.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 68064196cffea33f090bd2e8d81cd5e20107ecf1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 3 Nov 2022 11:53:16 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 TWD contains block with 4 timers. Add binding for it. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20221103105316.21294-1-zajec5@gmail.com -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -@@ -283,6 +283,11 @@ - #address-cells = <1>; - #size-cells = <1>; - -+ timer@0 { -+ compatible = "brcm,bcm63138-timer"; -+ reg = <0x0 0x28>; -+ }; -+ - watchdog@28 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x28 0x8>; diff --git a/target/linux/bcm4908/patches-5.10/039-v6.2-0002-arm64-dts-broadcom-bcmbca-bcm6858-add-TWD-block.patch b/target/linux/bcm4908/patches-5.10/039-v6.2-0002-arm64-dts-broadcom-bcmbca-bcm6858-add-TWD-block.patch deleted file mode 100644 index e8e81ae544..0000000000 --- a/target/linux/bcm4908/patches-5.10/039-v6.2-0002-arm64-dts-broadcom-bcmbca-bcm6858-add-TWD-block.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 4f9fb09175e87a233787a2dee1e5dabb14deb022 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 3 Nov 2022 12:00:15 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm6858: add TWD block -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM6858 contains TWD block with timers, watchdog, and reset subblocks. -Describe it. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20221103110015.21761-1-zajec5@gmail.com -Signed-off-by: Florian Fainelli ---- - .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi -@@ -109,6 +109,25 @@ - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x62000>; - -+ twd: timer-mfd@400 { -+ compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; -+ reg = <0x400 0x4c>; -+ ranges = <0x0 0x400 0x4c>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ timer@0 { -+ compatible = "brcm,bcm63138-timer"; -+ reg = <0x0 0x28>; -+ }; -+ -+ watchdog@28 { -+ compatible = "brcm,bcm6345-wdt"; -+ reg = <0x28 0x8>; -+ }; -+ }; -+ - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x18>; diff --git a/target/linux/bcm4908/patches-5.10/039-v6.2-0003-arm64-dts-Update-cache-properties-for-broadcom.patch b/target/linux/bcm4908/patches-5.10/039-v6.2-0003-arm64-dts-Update-cache-properties-for-broadcom.patch deleted file mode 100644 index a19ab8cf8f..0000000000 --- a/target/linux/bcm4908/patches-5.10/039-v6.2-0003-arm64-dts-Update-cache-properties-for-broadcom.patch +++ /dev/null @@ -1,134 +0,0 @@ -From e567e58d6819adc002c57b81e16b88da24d3b4aa Mon Sep 17 00:00:00 2001 -From: Pierre Gondois -Date: Tue, 22 Nov 2022 17:32:07 +0100 -Subject: [PATCH] arm64: dts: Update cache properties for broadcom - -The DeviceTree Specification v0.3 specifies that the cache node -'compatible' and 'cache-level' properties are 'required'. Cf. -s3.8 Multi-level and Shared Cache Nodes -The 'cache-unified' property should be present if one of the -properties for unified cache is present ('cache-size', ...). - -Update the Device Trees accordingly. - -Acked-by: William Zhang -Signed-off-by: Pierre Gondois -Link: https://lore.kernel.org/r/20221122163208.3810985-3-pierre.gondois@arm.com -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 + - arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 + - arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 + - arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 + - arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 + - arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 + - arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 + - arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 + - arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++ - 9 files changed, 12 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -@@ -63,6 +63,7 @@ - - l2: l2-cache0 { - compatible = "cache"; -+ cache-level = <2>; - }; - }; - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi -@@ -51,6 +51,7 @@ - - L2_0: l2-cache0 { - compatible = "cache"; -+ cache-level = <2>; - }; - }; - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi -@@ -35,6 +35,7 @@ - - L2_0: l2-cache0 { - compatible = "cache"; -+ cache-level = <2>; - }; - }; - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi -@@ -51,6 +51,7 @@ - - L2_0: l2-cache0 { - compatible = "cache"; -+ cache-level = <2>; - }; - }; - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi -@@ -51,6 +51,7 @@ - - L2_0: l2-cache0 { - compatible = "cache"; -+ cache-level = <2>; - }; - }; - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi -@@ -35,6 +35,7 @@ - - L2_0: l2-cache0 { - compatible = "cache"; -+ cache-level = <2>; - }; - }; - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi -@@ -50,6 +50,7 @@ - }; - L2_0: l2-cache0 { - compatible = "cache"; -+ cache-level = <2>; - }; - }; - ---- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi -+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi -@@ -79,6 +79,7 @@ - - CLUSTER0_L2: l2-cache@0 { - compatible = "cache"; -+ cache-level = <2>; - }; - }; - ---- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi -+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi -@@ -108,18 +108,22 @@ - - CLUSTER0_L2: l2-cache@0 { - compatible = "cache"; -+ cache-level = <2>; - }; - - CLUSTER1_L2: l2-cache@100 { - compatible = "cache"; -+ cache-level = <2>; - }; - - CLUSTER2_L2: l2-cache@200 { - compatible = "cache"; -+ cache-level = <2>; - }; - - CLUSTER3_L2: l2-cache@300 { - compatible = "cache"; -+ cache-level = <2>; - }; - }; - diff --git a/target/linux/bcm4908/patches-5.10/040-v6.1-mtd-parsers-add-Broadcom-s-U-Boot-parser.patch b/target/linux/bcm4908/patches-5.10/040-v6.1-mtd-parsers-add-Broadcom-s-U-Boot-parser.patch deleted file mode 100644 index 4d4059b17f..0000000000 --- a/target/linux/bcm4908/patches-5.10/040-v6.1-mtd-parsers-add-Broadcom-s-U-Boot-parser.patch +++ /dev/null @@ -1,137 +0,0 @@ -From 002181f5b150e60c77f21de7ad4dd10e4614cd91 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 11 Jul 2022 17:30:41 +0200 -Subject: [PATCH] mtd: parsers: add Broadcom's U-Boot parser -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Broadcom stores environment variables blocks inside U-Boot partition -itself. This driver finds & registers them. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220711153041.6036-2-zajec5@gmail.com ---- - drivers/mtd/parsers/Kconfig | 10 ++++ - drivers/mtd/parsers/Makefile | 1 + - drivers/mtd/parsers/brcm_u-boot.c | 84 +++++++++++++++++++++++++++++++ - 3 files changed, 95 insertions(+) - create mode 100644 drivers/mtd/parsers/brcm_u-boot.c - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -20,6 +20,16 @@ config MTD_BCM63XX_PARTS - This provides partition parsing for BCM63xx devices with CFE - bootloaders. - -+config MTD_BRCM_U_BOOT -+ tristate "Broadcom's U-Boot partition parser" -+ depends on ARCH_BCM4908 || COMPILE_TEST -+ help -+ Broadcom uses a custom way of storing U-Boot environment variables. -+ They are placed inside U-Boot partition itself at unspecified offset. -+ It's possible to locate them by looking for a custom header with a -+ magic value. This driver does that and creates subpartitions for -+ each found environment variables block. -+ - config MTD_CMDLINE_PARTS - tristate "Command line partition table parsing" - depends on MTD ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -2,6 +2,7 @@ - obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o - obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o - obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o -+obj-$(CONFIG_MTD_BRCM_U_BOOT) += brcm_u-boot.o - obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o - obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o - obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o ---- /dev/null -+++ b/drivers/mtd/parsers/brcm_u-boot.c -@@ -0,0 +1,84 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright © 2022 Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define BRCM_U_BOOT_MAX_OFFSET 0x200000 -+#define BRCM_U_BOOT_STEP 0x1000 -+ -+#define BRCM_U_BOOT_MAX_PARTS 2 -+ -+#define BRCM_U_BOOT_MAGIC 0x75456e76 /* uEnv */ -+ -+struct brcm_u_boot_header { -+ __le32 magic; -+ __le32 length; -+} __packed; -+ -+static const char *names[BRCM_U_BOOT_MAX_PARTS] = { -+ "u-boot-env", -+ "u-boot-env-backup", -+}; -+ -+static int brcm_u_boot_parse(struct mtd_info *mtd, -+ const struct mtd_partition **pparts, -+ struct mtd_part_parser_data *data) -+{ -+ struct brcm_u_boot_header header; -+ struct mtd_partition *parts; -+ size_t bytes_read; -+ size_t offset; -+ int err; -+ int i = 0; -+ -+ parts = kcalloc(BRCM_U_BOOT_MAX_PARTS, sizeof(*parts), GFP_KERNEL); -+ if (!parts) -+ return -ENOMEM; -+ -+ for (offset = 0; -+ offset < min_t(size_t, mtd->size, BRCM_U_BOOT_MAX_OFFSET); -+ offset += BRCM_U_BOOT_STEP) { -+ err = mtd_read(mtd, offset, sizeof(header), &bytes_read, (uint8_t *)&header); -+ if (err && !mtd_is_bitflip(err)) { -+ pr_err("Failed to read from %s at 0x%zx: %d\n", mtd->name, offset, err); -+ continue; -+ } -+ -+ if (le32_to_cpu(header.magic) != BRCM_U_BOOT_MAGIC) -+ continue; -+ -+ parts[i].name = names[i]; -+ parts[i].offset = offset; -+ parts[i].size = sizeof(header) + le32_to_cpu(header.length); -+ i++; -+ pr_info("offset:0x%zx magic:0x%08x BINGO\n", offset, header.magic); -+ -+ if (i == BRCM_U_BOOT_MAX_PARTS) -+ break; -+ } -+ -+ *pparts = parts; -+ -+ return i; -+}; -+ -+static const struct of_device_id brcm_u_boot_of_match_table[] = { -+ { .compatible = "brcm,u-boot" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, brcm_u_boot_of_match_table); -+ -+static struct mtd_part_parser brcm_u_boot_mtd_parser = { -+ .parse_fn = brcm_u_boot_parse, -+ .name = "brcm_u-boot", -+ .of_match_table = brcm_u_boot_of_match_table, -+}; -+module_mtd_part_parser(brcm_u_boot_mtd_parser); -+ -+MODULE_LICENSE("GPL"); diff --git a/target/linux/bcm4908/patches-5.10/040-v6.4-0001-arm64-dts-broadcom-bcmbca-Add-spi-controller-node.patch b/target/linux/bcm4908/patches-5.10/040-v6.4-0001-arm64-dts-broadcom-bcmbca-Add-spi-controller-node.patch deleted file mode 100644 index e8e1228179..0000000000 --- a/target/linux/bcm4908/patches-5.10/040-v6.4-0001-arm64-dts-broadcom-bcmbca-Add-spi-controller-node.patch +++ /dev/null @@ -1,367 +0,0 @@ -From f5d83b714e304d5f3229da434af2eeea033c4f5d Mon Sep 17 00:00:00 2001 -From: William Zhang -Date: Mon, 6 Feb 2023 22:58:15 -0800 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: Add spi controller node - -Add support for HSSPI controller in ARMv8 chip dts files. - -Signed-off-by: William Zhang -Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com -Signed-off-by: Florian Fainelli ---- - .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 18 +++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 20 +++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 19 ++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 19 ++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 20 +++++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 18 +++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 18 +++++++++++++++++ - .../boot/dts/broadcom/bcmbca/bcm94908.dts | 4 ++++ - .../boot/dts/broadcom/bcmbca/bcm94912.dts | 4 ++++ - .../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 ++++ - .../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 ++++ - .../boot/dts/broadcom/bcmbca/bcm96813.dts | 4 ++++ - .../boot/dts/broadcom/bcmbca/bcm96856.dts | 4 ++++ - .../boot/dts/broadcom/bcmbca/bcm96858.dts | 4 ++++ - 14 files changed, 160 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -@@ -107,6 +107,12 @@ - clock-frequency = <50000000>; - clock-output-names = "periph"; - }; -+ -+ hsspi_pll: hsspi-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ }; - }; - - soc { -@@ -531,6 +537,18 @@ - #size-cells = <0>; - }; - -+ hsspi: spi@1000{ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0"; -+ reg = <0x1000 0x600>; -+ interrupts = ; -+ clocks = <&hsspi_pll &hsspi_pll>; -+ clock-names = "hsspi", "pll"; -+ num-cs = <8>; -+ status = "disabled"; -+ }; -+ - nand-controller@1800 { - #address-cells = <1>; - #size-cells = <0>; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi -@@ -79,6 +79,7 @@ - #clock-cells = <0>; - clock-frequency = <200000000>; - }; -+ - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; -@@ -86,6 +87,12 @@ - clock-div = <4>; - clock-mult = <1>; - }; -+ -+ hsspi_pll: hsspi-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; - }; - - psci { -@@ -117,6 +124,19 @@ - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - -+ hsspi: spi@1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1"; -+ reg = <0x1000 0x600>, <0x2610 0x4>; -+ reg-names = "hsspi", "spim-ctrl"; -+ interrupts = ; -+ clocks = <&hsspi_pll &hsspi_pll>; -+ clock-names = "hsspi", "pll"; -+ num-cs = <8>; -+ status = "disabled"; -+ }; -+ - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi -@@ -60,6 +60,7 @@ - #clock-cells = <0>; - clock-frequency = <200000000>; - }; -+ - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; -@@ -67,6 +68,12 @@ - clock-div = <4>; - clock-mult = <1>; - }; -+ -+ hsspi_pll: hsspi-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; - }; - - psci { -@@ -99,6 +106,18 @@ - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - -+ hsspi: spi@1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0"; -+ reg = <0x1000 0x600>; -+ interrupts = ; -+ clocks = <&hsspi_pll &hsspi_pll>; -+ clock-names = "hsspi", "pll"; -+ num-cs = <8>; -+ status = "disabled"; -+ }; -+ - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi -@@ -79,6 +79,7 @@ - #clock-cells = <0>; - clock-frequency = <200000000>; - }; -+ - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; -@@ -86,6 +87,12 @@ - clock-div = <4>; - clock-mult = <1>; - }; -+ -+ hsspi_pll: hsspi-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ }; - }; - - psci { -@@ -117,6 +124,18 @@ - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - -+ hsspi: spi@1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0"; -+ reg = <0x1000 0x600>; -+ interrupts = ; -+ clocks = <&hsspi_pll &hsspi_pll>; -+ clock-names = "hsspi", "pll"; -+ num-cs = <8>; -+ status = "disabled"; -+ }; -+ - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi -@@ -79,6 +79,7 @@ - #clock-cells = <0>; - clock-frequency = <200000000>; - }; -+ - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; -@@ -86,6 +87,12 @@ - clock-div = <4>; - clock-mult = <1>; - }; -+ -+ hsspi_pll: hsspi-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <200000000>; -+ }; - }; - - psci { -@@ -117,6 +124,19 @@ - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - -+ hsspi: spi@1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1"; -+ reg = <0x1000 0x600>, <0x2610 0x4>; -+ reg-names = "hsspi", "spim-ctrl"; -+ interrupts = ; -+ clocks = <&hsspi_pll &hsspi_pll>; -+ clock-names = "hsspi", "pll"; -+ num-cs = <8>; -+ status = "disabled"; -+ }; -+ - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi -@@ -60,6 +60,12 @@ - #clock-cells = <0>; - clock-frequency = <200000000>; - }; -+ -+ hsspi_pll: hsspi-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ }; - }; - - psci { -@@ -100,5 +106,17 @@ - clock-names = "refclk"; - status = "disabled"; - }; -+ -+ hsspi: spi@1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0"; -+ reg = <0x1000 0x600>; -+ interrupts = ; -+ clocks = <&hsspi_pll &hsspi_pll>; -+ clock-names = "hsspi", "pll"; -+ num-cs = <8>; -+ status = "disabled"; -+ }; - }; - }; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi -@@ -78,6 +78,12 @@ - #clock-cells = <0>; - clock-frequency = <200000000>; - }; -+ -+ hsspi_pll: hsspi-pll { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <400000000>; -+ }; - }; - - psci { -@@ -137,5 +143,17 @@ - clock-names = "refclk"; - status = "disabled"; - }; -+ -+ hsspi: spi@1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0"; -+ reg = <0x1000 0x600>; -+ interrupts = ; -+ clocks = <&hsspi_pll &hsspi_pll>; -+ clock-names = "hsspi", "pll"; -+ num-cs = <8>; -+ status = "disabled"; -+ }; - }; - }; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts -@@ -28,3 +28,7 @@ - &uart0 { - status = "okay"; - }; -+ -+&hsspi { -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts -@@ -28,3 +28,7 @@ - &uart0 { - status = "okay"; - }; -+ -+&hsspi { -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts -@@ -28,3 +28,7 @@ - &uart0 { - status = "okay"; - }; -+ -+&hsspi { -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts -@@ -28,3 +28,7 @@ - &uart0 { - status = "okay"; - }; -+ -+&hsspi { -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts -@@ -28,3 +28,7 @@ - &uart0 { - status = "okay"; - }; -+ -+&hsspi { -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts -@@ -28,3 +28,7 @@ - &uart0 { - status = "okay"; - }; -+ -+&hsspi { -+ status = "okay"; -+}; ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts -@@ -28,3 +28,7 @@ - &uart0 { - status = "okay"; - }; -+ -+&hsspi { -+ status = "okay"; -+}; diff --git a/target/linux/bcm4908/patches-5.10/040-v6.4-0002-arm64-dts-broadcom-bcmbca-bcm4908-fix-NAND-interrupt.patch b/target/linux/bcm4908/patches-5.10/040-v6.4-0002-arm64-dts-broadcom-bcmbca-bcm4908-fix-NAND-interrupt.patch deleted file mode 100644 index b121200a25..0000000000 --- a/target/linux/bcm4908/patches-5.10/040-v6.4-0002-arm64-dts-broadcom-bcmbca-bcm4908-fix-NAND-interrupt.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 5cca02449490e767289bda38db1577e2c375c084 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 28 Feb 2023 15:43:58 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: fix NAND interrupt - name -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes: -arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dtb: nand-controller@1800: interrupt-names:0: 'nand_ctlrdy' was expected - From schema: Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml -arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dtb: nand-controller@1800: Unevaluated properties are not allowed ('interrupt-names' was unexpected) - From schema: Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/all/20230228144400.21689-1-zajec5@gmail.com/ -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -@@ -556,7 +556,7 @@ - reg = <0x1800 0x600>, <0x2000 0x10>; - reg-names = "nand", "nand-int-base"; - interrupts = ; -- interrupt-names = "nand"; -+ interrupt-names = "nand_ctlrdy"; - status = "okay"; - - nandcs: nand@0 { diff --git a/target/linux/bcm4908/patches-5.10/040-v6.4-0003-arm64-dts-broadcom-bcmbca-bcm4908-fix-LED-nodenames.patch b/target/linux/bcm4908/patches-5.10/040-v6.4-0003-arm64-dts-broadcom-bcmbca-bcm4908-fix-LED-nodenames.patch deleted file mode 100644 index 7ce17c1870..0000000000 --- a/target/linux/bcm4908/patches-5.10/040-v6.4-0003-arm64-dts-broadcom-bcmbca-bcm4908-fix-LED-nodenames.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 23be9f68f933adee8163b8efc9c6bff71410cc7c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 28 Feb 2023 15:43:59 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: fix LED nodenames -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes: -arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dtb: leds@800: 'led-lan@19', 'led-power@11', 'led-wan-red@12', 'led-wan-white@15', 'led-wps@14' do not match any of the regexes: '^led@[a-f0-9]+$', 'pinctrl-[0-9]+' - From schema: Documentation/devicetree/bindings/leds/leds-bcm63138.yaml - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/all/20230228144400.21689-2-zajec5@gmail.com/ -Signed-off-by: Florian Fainelli ---- - .../dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts -@@ -120,7 +120,7 @@ - }; - - &leds { -- led-power@11 { -+ led@11 { - reg = <0x11>; - function = LED_FUNCTION_POWER; - color = ; -@@ -130,7 +130,7 @@ - pinctrl-0 = <&pins_led_17_a>; - }; - -- led-wan-red@12 { -+ led@12 { - reg = <0x12>; - function = LED_FUNCTION_WAN; - color = ; -@@ -139,7 +139,7 @@ - pinctrl-0 = <&pins_led_18_a>; - }; - -- led-wps@14 { -+ led@14 { - reg = <0x14>; - function = LED_FUNCTION_WPS; - color = ; -@@ -148,7 +148,7 @@ - pinctrl-0 = <&pins_led_20_a>; - }; - -- led-wan-white@15 { -+ led@15 { - reg = <0x15>; - function = LED_FUNCTION_WAN; - color = ; -@@ -157,7 +157,7 @@ - pinctrl-0 = <&pins_led_21_a>; - }; - -- led-lan@19 { -+ led@19 { - reg = <0x19>; - function = LED_FUNCTION_LAN; - color = ; diff --git a/target/linux/bcm4908/patches-5.10/040-v6.4-0004-arm64-dts-broadcom-bcmbca-bcm4908-fix-procmon-nodena.patch b/target/linux/bcm4908/patches-5.10/040-v6.4-0004-arm64-dts-broadcom-bcmbca-bcm4908-fix-procmon-nodena.patch deleted file mode 100644 index a469a32a2c..0000000000 --- a/target/linux/bcm4908/patches-5.10/040-v6.4-0004-arm64-dts-broadcom-bcmbca-bcm4908-fix-procmon-nodena.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f16a8294dd7a02c7ad042cd2e3acc5ea06698dc1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 28 Feb 2023 15:44:00 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: fix procmon nodename -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes: -arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dtb: syscon@280000: $nodename:0: 'syscon@280000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' - From schema: schemas/simple-bus.yaml - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/all/20230228144400.21689-3-zajec5@gmail.com/ -Signed-off-by: Florian Fainelli ---- - arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -@@ -260,7 +260,7 @@ - }; - }; - -- procmon: syscon@280000 { -+ procmon: bus@280000 { - compatible = "simple-bus"; - reg = <0x280000 0x1000>; - ranges; diff --git a/target/linux/bcm4908/patches-5.10/040-v6.4-0005-arm64-dts-broadcom-bcmbca-bcm4908-add-on-SoC-USB-por.patch b/target/linux/bcm4908/patches-5.10/040-v6.4-0005-arm64-dts-broadcom-bcmbca-bcm4908-add-on-SoC-USB-por.patch deleted file mode 100644 index 47b2455ae6..0000000000 --- a/target/linux/bcm4908/patches-5.10/040-v6.4-0005-arm64-dts-broadcom-bcmbca-bcm4908-add-on-SoC-USB-por.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 477cad715de1dfc256a20da3ed83b62f3cb2944d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 28 Feb 2023 15:45:18 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add on-SoC USB ports -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 has 3 USB controllers each with 2 USB ports. Home routers often -have LEDs indicating state of selected USB ports. Describe those SoC USB -ports to allow using them as LED trigger sources. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/all/20230228144520.21816-1-zajec5@gmail.com/ -Signed-off-by: Florian Fainelli ---- - .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 39 +++++++++++++++++++ - 1 file changed, 39 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -@@ -148,6 +148,19 @@ - interrupts = ; - phys = <&usb_phy PHY_TYPE_USB2>; - status = "disabled"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ehci_port1: port@1 { -+ reg = <1>; -+ #trigger-source-cells = <0>; -+ }; -+ -+ ehci_port2: port@2 { -+ reg = <2>; -+ #trigger-source-cells = <0>; -+ }; - }; - - ohci: usb@c400 { -@@ -156,6 +169,19 @@ - interrupts = ; - phys = <&usb_phy PHY_TYPE_USB2>; - status = "disabled"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ohci_port1: port@1 { -+ reg = <1>; -+ #trigger-source-cells = <0>; -+ }; -+ -+ ohci_port2: port@2 { -+ reg = <2>; -+ #trigger-source-cells = <0>; -+ }; - }; - - xhci: usb@d000 { -@@ -164,6 +190,19 @@ - interrupts = ; - phys = <&usb_phy PHY_TYPE_USB3>; - status = "disabled"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ xhci_port1: port@1 { -+ reg = <1>; -+ #trigger-source-cells = <0>; -+ }; -+ -+ xhci_port2: port@2 { -+ reg = <2>; -+ #trigger-source-cells = <0>; -+ }; - }; - - bus@80000 { diff --git a/target/linux/bcm4908/patches-5.10/040-v6.4-0006-arm64-dts-broadcom-bcmbca-bcm4908-add-Netgear-R8000P.patch b/target/linux/bcm4908/patches-5.10/040-v6.4-0006-arm64-dts-broadcom-bcmbca-bcm4908-add-Netgear-R8000P.patch deleted file mode 100644 index 3e210d68e1..0000000000 --- a/target/linux/bcm4908/patches-5.10/040-v6.4-0006-arm64-dts-broadcom-bcmbca-bcm4908-add-Netgear-R8000P.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 889e53ccccc29ff4bf8d4c89cca34e8768845747 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 28 Feb 2023 15:45:19 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add Netgear R8000P USB - LED triggers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This device has 2 USB LEDs meant to be triggered by devices in relevant -USB ports. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/all/20230228144520.21816-2-zajec5@gmail.com/ -Signed-off-by: Florian Fainelli ---- - .../arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts -@@ -58,12 +58,16 @@ - function = "usb2"; - color = ; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; -+ trigger-sources = <&ohci_port1>, <&ehci_port1>; -+ linux,default-trigger = "usbport"; - }; - - led-usb3 { - function = "usb3"; - color = ; - gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; -+ trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>; -+ linux,default-trigger = "usbport"; - }; - - led-wifi { diff --git a/target/linux/bcm4908/patches-5.10/040-v6.4-0007-arm64-dts-broadcom-bcmbca-bcm4908-add-TP-Link-C2300-.patch b/target/linux/bcm4908/patches-5.10/040-v6.4-0007-arm64-dts-broadcom-bcmbca-bcm4908-add-TP-Link-C2300-.patch deleted file mode 100644 index 959ccd4fa3..0000000000 --- a/target/linux/bcm4908/patches-5.10/040-v6.4-0007-arm64-dts-broadcom-bcmbca-bcm4908-add-TP-Link-C2300-.patch +++ /dev/null @@ -1,41 +0,0 @@ -From e6d356b146b75f1f77621aab7950a1eb550859f9 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 28 Feb 2023 15:45:20 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TP-Link C2300 USB - LED triggers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This device has 2 USB LEDs meant to be triggered by devices in relevant -USB ports. - -While at it fix typo in USB LED name. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/all/20230228144520.21816-3-zajec5@gmail.com/ -Signed-off-by: Florian Fainelli ---- - .../dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts -@@ -64,12 +64,16 @@ - function = "usb2"; - color = ; - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; -+ trigger-sources = <&ohci_port1>, <&ehci_port1>; -+ linux,default-trigger = "usbport"; - }; - - led-usb3 { -- function = "usbd3"; -+ function = "usb3"; - color = ; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; -+ trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>; -+ linux,default-trigger = "usbport"; - }; - - led-brightness { diff --git a/target/linux/bcm4908/patches-5.10/071-v5.12-0001-net-dsa-bcm_sf2-support-BCM4908-s-integrated-switch.patch b/target/linux/bcm4908/patches-5.10/071-v5.12-0001-net-dsa-bcm_sf2-support-BCM4908-s-integrated-switch.patch deleted file mode 100644 index 344093c548..0000000000 --- a/target/linux/bcm4908/patches-5.10/071-v5.12-0001-net-dsa-bcm_sf2-support-BCM4908-s-integrated-switch.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 73b7a6047971aa6ce4a70fc4901964d14f077171 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 6 Jan 2021 22:32:02 +0100 -Subject: [PATCH] net: dsa: bcm_sf2: support BCM4908's integrated switch -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 family SoCs come with integrated Starfighter 2 switch. Its -registers layout it a mix of BCM7278 and BCM7445. It has 5 integrated -PHYs and 8 ports. It also supports RGMII and SerDes. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20210106213202.17459-3-zajec5@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/b53/b53_common.c | 14 +++++++++++++ - drivers/net/dsa/b53/b53_priv.h | 1 + - drivers/net/dsa/bcm_sf2.c | 36 +++++++++++++++++++++++++++++--- - drivers/net/dsa/bcm_sf2_regs.h | 1 + - 4 files changed, 49 insertions(+), 3 deletions(-) - ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -2493,6 +2493,22 @@ static const struct b53_chip_data b53_sw - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, - .jumbo_size_reg = B53_JUMBO_MAX_SIZE, - }, -+ /* Starfighter 2 */ -+ { -+ .chip_id = BCM4908_DEVICE_ID, -+ .dev_name = "BCM4908", -+ .vlans = 4096, -+ .enabled_ports = 0x1bf, -+#if 0 -+ .arl_bins = 4, -+ .arl_buckets = 256, -+#endif -+ .cpu_port = 8, /* TODO: ports 4, 5, 8 */ -+ .vta_regs = B53_VTA_REGS, -+ .duplex_reg = B53_DUPLEX_STAT_GE, -+ .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -+ .jumbo_size_reg = B53_JUMBO_MAX_SIZE, -+ }, - { - .chip_id = BCM7445_DEVICE_ID, - .dev_name = "BCM7445", ---- a/drivers/net/dsa/b53/b53_priv.h -+++ b/drivers/net/dsa/b53/b53_priv.h -@@ -64,6 +64,7 @@ struct b53_io_ops { - #define B53_INVALID_LANE 0xff - - enum { -+ BCM4908_DEVICE_ID = 0x4908, - BCM5325_DEVICE_ID = 0x25, - BCM5365_DEVICE_ID = 0x65, - BCM5389_DEVICE_ID = 0x89, ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -105,7 +105,8 @@ static void bcm_sf2_imp_setup(struct dsa - b53_brcm_hdr_setup(ds, port); - - if (port == 8) { -- if (priv->type == BCM7445_DEVICE_ID) -+ if (priv->type == BCM4908_DEVICE_ID || -+ priv->type == BCM7445_DEVICE_ID) - offset = CORE_STS_OVERRIDE_IMP; - else - offset = CORE_STS_OVERRIDE_IMP2; -@@ -714,7 +715,8 @@ static void bcm_sf2_sw_mac_link_down(str - return; - - if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { -- if (priv->type == BCM7445_DEVICE_ID) -+ if (priv->type == BCM4908_DEVICE_ID || -+ priv->type == BCM7445_DEVICE_ID) - offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); - else - offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); -@@ -741,7 +743,8 @@ static void bcm_sf2_sw_mac_link_up(struc - bcm_sf2_sw_mac_link_set(ds, port, interface, true); - - if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { -- if (priv->type == BCM7445_DEVICE_ID) -+ if (priv->type == BCM4908_DEVICE_ID || -+ priv->type == BCM7445_DEVICE_ID) - offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); - else - offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); -@@ -1139,6 +1142,30 @@ struct bcm_sf2_of_data { - unsigned int num_cfp_rules; - }; - -+static const u16 bcm_sf2_4908_reg_offsets[] = { -+ [REG_SWITCH_CNTRL] = 0x00, -+ [REG_SWITCH_STATUS] = 0x04, -+ [REG_DIR_DATA_WRITE] = 0x08, -+ [REG_DIR_DATA_READ] = 0x0c, -+ [REG_SWITCH_REVISION] = 0x10, -+ [REG_PHY_REVISION] = 0x14, -+ [REG_SPHY_CNTRL] = 0x24, -+ [REG_CROSSBAR] = 0xc8, -+ [REG_RGMII_0_CNTRL] = 0xe0, -+ [REG_RGMII_1_CNTRL] = 0xec, -+ [REG_RGMII_2_CNTRL] = 0xf8, -+ [REG_LED_0_CNTRL] = 0x40, -+ [REG_LED_1_CNTRL] = 0x4c, -+ [REG_LED_2_CNTRL] = 0x58, -+}; -+ -+static const struct bcm_sf2_of_data bcm_sf2_4908_data = { -+ .type = BCM4908_DEVICE_ID, -+ .core_reg_align = 0, -+ .reg_offsets = bcm_sf2_4908_reg_offsets, -+ .num_cfp_rules = 0, /* FIXME */ -+}; -+ - /* Register offsets for the SWITCH_REG_* block */ - static const u16 bcm_sf2_7445_reg_offsets[] = { - [REG_SWITCH_CNTRL] = 0x00, -@@ -1187,6 +1214,9 @@ static const struct bcm_sf2_of_data bcm_ - }; - - static const struct of_device_id bcm_sf2_of_match[] = { -+ { .compatible = "brcm,bcm4908-switch", -+ .data = &bcm_sf2_4908_data -+ }, - { .compatible = "brcm,bcm7445-switch-v4.0", - .data = &bcm_sf2_7445_data - }, ---- a/drivers/net/dsa/bcm_sf2_regs.h -+++ b/drivers/net/dsa/bcm_sf2_regs.h -@@ -17,6 +17,7 @@ enum bcm_sf2_reg_offs { - REG_SWITCH_REVISION, - REG_PHY_REVISION, - REG_SPHY_CNTRL, -+ REG_CROSSBAR, - REG_RGMII_0_CNTRL, - REG_RGMII_1_CNTRL, - REG_RGMII_2_CNTRL, diff --git a/target/linux/bcm4908/patches-5.10/071-v5.12-0002-net-dsa-bcm_sf2-use-2-Gbps-IMP-port-link-on-BCM4908.patch b/target/linux/bcm4908/patches-5.10/071-v5.12-0002-net-dsa-bcm_sf2-use-2-Gbps-IMP-port-link-on-BCM4908.patch deleted file mode 100644 index 7785e0c036..0000000000 --- a/target/linux/bcm4908/patches-5.10/071-v5.12-0002-net-dsa-bcm_sf2-use-2-Gbps-IMP-port-link-on-BCM4908.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8373a0fe9c7160a55482effa8a3f725efd3f8434 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 10 Mar 2021 13:51:59 +0100 -Subject: [PATCH] net: dsa: bcm_sf2: use 2 Gbps IMP port link on BCM4908 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 uses 2 Gbps link between switch and the Ethernet interface. -Without this BCM4908 devices were able to achieve only 2 x ~895 Mb/s. -This allows handling e.g. NAT traffic with 940 Mb/s. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/bcm_sf2.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -114,7 +114,10 @@ static void bcm_sf2_imp_setup(struct dsa - /* Force link status for IMP port */ - reg = core_readl(priv, offset); - reg |= (MII_SW_OR | LINK_STS); -- reg &= ~GMII_SPEED_UP_2G; -+ if (priv->type == BCM4908_DEVICE_ID) -+ reg |= GMII_SPEED_UP_2G; -+ else -+ reg &= ~GMII_SPEED_UP_2G; - core_writel(priv, reg, offset); - - /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ diff --git a/target/linux/bcm4908/patches-5.10/072-v5.12-0001-dt-bindings-net-document-BCM4908-Ethernet-controller.patch b/target/linux/bcm4908/patches-5.10/072-v5.12-0001-dt-bindings-net-document-BCM4908-Ethernet-controller.patch deleted file mode 100644 index 8c60b9706e..0000000000 --- a/target/linux/bcm4908/patches-5.10/072-v5.12-0001-dt-bindings-net-document-BCM4908-Ethernet-controller.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 387d1c1819790aa8398c7cffab587f9a050a0d1a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sun, 7 Feb 2021 23:26:31 +0100 -Subject: [PATCH] dt-bindings: net: document BCM4908 Ethernet controller -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 is a family of SoCs with integrated Ethernet controller. - -Signed-off-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - .../bindings/net/brcm,bcm4908enet.yaml | 45 +++++++++++++++++++ - 1 file changed, 45 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml -@@ -0,0 +1,45 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/brcm,bcm4908enet.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM4908 Ethernet controller -+ -+description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs -+ -+maintainers: -+ - Rafał Miłecki -+ -+properties: -+ compatible: -+ const: brcm,bcm4908enet -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ description: RX interrupt -+ -+ interrupt-names: -+ const: rx -+ -+required: -+ - reg -+ - interrupts -+ - interrupt-names -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ -+ ethernet@80002000 { -+ compatible = "brcm,bcm4908enet"; -+ reg = <0x80002000 0x1000>; -+ -+ interrupts = ; -+ interrupt-names = "rx"; -+ }; diff --git a/target/linux/bcm4908/patches-5.10/072-v5.12-0002-net-broadcom-bcm4908enet-add-BCM4908-controller-driv.patch b/target/linux/bcm4908/patches-5.10/072-v5.12-0002-net-broadcom-bcm4908enet-add-BCM4908-controller-driv.patch deleted file mode 100644 index 958ef85f9e..0000000000 --- a/target/linux/bcm4908/patches-5.10/072-v5.12-0002-net-broadcom-bcm4908enet-add-BCM4908-controller-driv.patch +++ /dev/null @@ -1,847 +0,0 @@ -From 4feffeadbcb2e5b11cbbf191a33c245b74a5837b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sun, 7 Feb 2021 23:26:32 +0100 -Subject: [PATCH] net: broadcom: bcm4908enet: add BCM4908 controller driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 SoCs family uses Ethernel controller that includes UniMAC but -uses different DMA engine (than other controllers) and requires -different programming. - -Signed-off-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - MAINTAINERS | 9 + - drivers/net/ethernet/broadcom/Kconfig | 8 + - drivers/net/ethernet/broadcom/Makefile | 1 + - drivers/net/ethernet/broadcom/bcm4908enet.c | 676 ++++++++++++++++++++ - drivers/net/ethernet/broadcom/bcm4908enet.h | 96 +++ - 5 files changed, 790 insertions(+) - create mode 100644 drivers/net/ethernet/broadcom/bcm4908enet.c - create mode 100644 drivers/net/ethernet/broadcom/bcm4908enet.h - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3427,6 +3427,15 @@ F: Documentation/devicetree/bindings/mip - F: arch/mips/bcm47xx/* - F: arch/mips/include/asm/mach-bcm47xx/* - -+BROADCOM BCM4908 ETHERNET DRIVER -+M: Rafał Miłecki -+M: bcm-kernel-feedback-list@broadcom.com -+L: netdev@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml -+F: drivers/net/ethernet/broadcom/bcm4908enet.* -+F: drivers/net/ethernet/broadcom/unimac.h -+ - BROADCOM BCM5301X ARM ARCHITECTURE - M: Hauke Mehrtens - M: Rafał Miłecki ---- a/drivers/net/ethernet/broadcom/Kconfig -+++ b/drivers/net/ethernet/broadcom/Kconfig -@@ -51,6 +51,14 @@ config B44_PCI - depends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT - default y - -+config BCM4908ENET -+ tristate "Broadcom BCM4908 internal mac support" -+ depends on ARCH_BCM4908 || COMPILE_TEST -+ default y -+ help -+ This driver supports Ethernet controller integrated into Broadcom -+ BCM4908 family SoCs. -+ - config BCM63XX_ENET - tristate "Broadcom 63xx internal mac support" - depends on BCM63XX ---- a/drivers/net/ethernet/broadcom/Makefile -+++ b/drivers/net/ethernet/broadcom/Makefile -@@ -4,6 +4,7 @@ - # - - obj-$(CONFIG_B44) += b44.o -+obj-$(CONFIG_BCM4908ENET) += bcm4908enet.o - obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o - obj-$(CONFIG_BCMGENET) += genet/ - obj-$(CONFIG_BNX2) += bnx2.o ---- /dev/null -+++ b/drivers/net/ethernet/broadcom/bcm4908enet.c -@@ -0,0 +1,676 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2021 Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "bcm4908enet.h" -+#include "unimac.h" -+ -+#define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG -+#define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG -+#define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM -+#define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM -+ -+#define ENET_TX_BDS_NUM 200 -+#define ENET_RX_BDS_NUM 200 -+#define ENET_RX_BDS_NUM_MAX 8192 -+ -+#define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \ -+ ENET_DMA_CH_CFG_INT_NO_DESC | \ -+ ENET_DMA_CH_CFG_INT_BUFF_DONE) -+#define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */ -+ -+#define ENET_MTU_MIN 60 -+#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */ -+#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */ -+ -+struct bcm4908enet_dma_ring_bd { -+ __le32 ctl; -+ __le32 addr; -+} __packed; -+ -+struct bcm4908enet_dma_ring_slot { -+ struct sk_buff *skb; -+ unsigned int len; -+ dma_addr_t dma_addr; -+}; -+ -+struct bcm4908enet_dma_ring { -+ int is_tx; -+ int read_idx; -+ int write_idx; -+ int length; -+ u16 cfg_block; -+ u16 st_ram_block; -+ -+ union { -+ void *cpu_addr; -+ struct bcm4908enet_dma_ring_bd *buf_desc; -+ }; -+ dma_addr_t dma_addr; -+ -+ struct bcm4908enet_dma_ring_slot *slots; -+}; -+ -+struct bcm4908enet { -+ struct device *dev; -+ struct net_device *netdev; -+ struct napi_struct napi; -+ void __iomem *base; -+ -+ struct bcm4908enet_dma_ring tx_ring; -+ struct bcm4908enet_dma_ring rx_ring; -+}; -+ -+/*** -+ * R/W ops -+ */ -+ -+static inline u32 enet_read(struct bcm4908enet *enet, u16 offset) -+{ -+ return readl(enet->base + offset); -+} -+ -+static inline void enet_write(struct bcm4908enet *enet, u16 offset, u32 value) -+{ -+ writel(value, enet->base + offset); -+} -+ -+static inline void enet_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set) -+{ -+ u32 val; -+ -+ WARN_ON(set & ~mask); -+ -+ val = enet_read(enet, offset); -+ val = (val & ~mask) | (set & mask); -+ enet_write(enet, offset, val); -+} -+ -+static inline void enet_set(struct bcm4908enet *enet, u16 offset, u32 set) -+{ -+ enet_maskset(enet, offset, set, set); -+} -+ -+static inline u32 enet_umac_read(struct bcm4908enet *enet, u16 offset) -+{ -+ return enet_read(enet, ENET_UNIMAC + offset); -+} -+ -+static inline void enet_umac_write(struct bcm4908enet *enet, u16 offset, u32 value) -+{ -+ enet_write(enet, ENET_UNIMAC + offset, value); -+} -+ -+static inline void enet_umac_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set) -+{ -+ enet_maskset(enet, ENET_UNIMAC + offset, mask, set); -+} -+ -+static inline void enet_umac_set(struct bcm4908enet *enet, u16 offset, u32 set) -+{ -+ enet_set(enet, ENET_UNIMAC + offset, set); -+} -+ -+/*** -+ * Helpers -+ */ -+ -+static void bcm4908enet_intrs_on(struct bcm4908enet *enet) -+{ -+ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS); -+} -+ -+static void bcm4908enet_intrs_off(struct bcm4908enet *enet) -+{ -+ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0); -+} -+ -+static void bcm4908enet_intrs_ack(struct bcm4908enet *enet) -+{ -+ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS); -+} -+ -+/*** -+ * DMA -+ */ -+ -+static int bcm4908_dma_alloc_buf_descs(struct bcm4908enet *enet, struct bcm4908enet_dma_ring *ring) -+{ -+ int size = ring->length * sizeof(struct bcm4908enet_dma_ring_bd); -+ struct device *dev = enet->dev; -+ -+ ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL); -+ if (!ring->cpu_addr) -+ return -ENOMEM; -+ -+ if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) { -+ dev_err(dev, "Invalid DMA ring alignment\n"); -+ goto err_free_buf_descs; -+ } -+ -+ ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL); -+ if (!ring->slots) -+ goto err_free_buf_descs; -+ -+ memset(ring->cpu_addr, 0, size); -+ -+ ring->read_idx = 0; -+ ring->write_idx = 0; -+ -+ return 0; -+ -+err_free_buf_descs: -+ dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr); -+ return -ENOMEM; -+} -+ -+static void bcm4908enet_dma_free(struct bcm4908enet *enet) -+{ -+ struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring; -+ struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring; -+ struct device *dev = enet->dev; -+ int size; -+ -+ size = rx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd); -+ if (rx_ring->cpu_addr) -+ dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr); -+ kfree(rx_ring->slots); -+ -+ size = tx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd); -+ if (tx_ring->cpu_addr) -+ dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr); -+ kfree(tx_ring->slots); -+} -+ -+static int bcm4908enet_dma_alloc(struct bcm4908enet *enet) -+{ -+ struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring; -+ struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring; -+ struct device *dev = enet->dev; -+ int err; -+ -+ tx_ring->length = ENET_TX_BDS_NUM; -+ tx_ring->is_tx = 1; -+ tx_ring->cfg_block = ENET_DMA_CH_TX_CFG; -+ tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM; -+ err = bcm4908_dma_alloc_buf_descs(enet, tx_ring); -+ if (err) { -+ dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err); -+ return err; -+ } -+ -+ rx_ring->length = ENET_RX_BDS_NUM; -+ rx_ring->is_tx = 0; -+ rx_ring->cfg_block = ENET_DMA_CH_RX_CFG; -+ rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM; -+ err = bcm4908_dma_alloc_buf_descs(enet, rx_ring); -+ if (err) { -+ dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err); -+ bcm4908enet_dma_free(enet); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static void bcm4908enet_dma_reset(struct bcm4908enet *enet) -+{ -+ struct bcm4908enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring }; -+ int i; -+ -+ /* Disable the DMA controller and channel */ -+ for (i = 0; i < ARRAY_SIZE(rings); i++) -+ enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0); -+ enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0); -+ -+ /* Reset channels state */ -+ for (i = 0; i < ARRAY_SIZE(rings); i++) { -+ struct bcm4908enet_dma_ring *ring = rings[i]; -+ -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0); -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0); -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0); -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0); -+ } -+} -+ -+static int bcm4908enet_dma_alloc_rx_buf(struct bcm4908enet *enet, unsigned int idx) -+{ -+ struct bcm4908enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx]; -+ struct bcm4908enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx]; -+ struct device *dev = enet->dev; -+ u32 tmp; -+ int err; -+ -+ slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE; -+ -+ slot->skb = netdev_alloc_skb(enet->netdev, slot->len); -+ if (!slot->skb) -+ return -ENOMEM; -+ -+ slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE); -+ err = dma_mapping_error(dev, slot->dma_addr); -+ if (err) { -+ dev_err(dev, "Failed to map DMA buffer: %d\n", err); -+ kfree_skb(slot->skb); -+ slot->skb = NULL; -+ return err; -+ } -+ -+ tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -+ tmp |= DMA_CTL_STATUS_OWN; -+ if (idx == enet->rx_ring.length - 1) -+ tmp |= DMA_CTL_STATUS_WRAP; -+ buf_desc->ctl = cpu_to_le32(tmp); -+ buf_desc->addr = cpu_to_le32(slot->dma_addr); -+ -+ return 0; -+} -+ -+static void bcm4908enet_dma_ring_init(struct bcm4908enet *enet, -+ struct bcm4908enet_dma_ring *ring) -+{ -+ int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */ -+ int reset_subch = ring->is_tx ? 1 : 0; -+ -+ /* Reset the DMA channel */ -+ enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch)); -+ enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0); -+ -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN); -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0); -+ -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, -+ (uint32_t)ring->dma_addr); -+} -+ -+static void bcm4908enet_dma_uninit(struct bcm4908enet *enet) -+{ -+ struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring; -+ struct bcm4908enet_dma_ring_slot *slot; -+ struct device *dev = enet->dev; -+ int i; -+ -+ for (i = rx_ring->length - 1; i >= 0; i--) { -+ slot = &rx_ring->slots[i]; -+ if (!slot->skb) -+ continue; -+ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE); -+ kfree_skb(slot->skb); -+ slot->skb = NULL; -+ } -+} -+ -+static int bcm4908enet_dma_init(struct bcm4908enet *enet) -+{ -+ struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring; -+ struct device *dev = enet->dev; -+ int err; -+ int i; -+ -+ for (i = 0; i < rx_ring->length; i++) { -+ err = bcm4908enet_dma_alloc_rx_buf(enet, i); -+ if (err) { -+ dev_err(dev, "Failed to alloc RX buffer: %d\n", err); -+ bcm4908enet_dma_uninit(enet); -+ return err; -+ } -+ } -+ -+ bcm4908enet_dma_ring_init(enet, &enet->tx_ring); -+ bcm4908enet_dma_ring_init(enet, &enet->rx_ring); -+ -+ return 0; -+} -+ -+static void bcm4908enet_dma_tx_ring_ensable(struct bcm4908enet *enet, -+ struct bcm4908enet_dma_ring *ring) -+{ -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); -+} -+ -+static void bcm4908enet_dma_tx_ring_disable(struct bcm4908enet *enet, -+ struct bcm4908enet_dma_ring *ring) -+{ -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); -+} -+ -+static void bcm4908enet_dma_rx_ring_enable(struct bcm4908enet *enet, -+ struct bcm4908enet_dma_ring *ring) -+{ -+ enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); -+} -+ -+static void bcm4908enet_dma_rx_ring_disable(struct bcm4908enet *enet, -+ struct bcm4908enet_dma_ring *ring) -+{ -+ unsigned long deadline; -+ u32 tmp; -+ -+ enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); -+ -+ deadline = jiffies + usecs_to_jiffies(2000); -+ do { -+ tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG); -+ if (!(tmp & ENET_DMA_CH_CFG_ENABLE)) -+ return; -+ enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); -+ usleep_range(10, 30); -+ } while (!time_after_eq(jiffies, deadline)); -+ -+ dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n"); -+} -+ -+/*** -+ * Ethernet driver -+ */ -+ -+static void bcm4908enet_gmac_init(struct bcm4908enet *enet) -+{ -+ u32 cmd; -+ -+ cmd = enet_umac_read(enet, UMAC_CMD); -+ enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET); -+ enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET); -+ -+ enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH); -+ enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0); -+ -+ enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB); -+ enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0); -+ -+ cmd = enet_umac_read(enet, UMAC_CMD); -+ cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT); -+ cmd &= ~CMD_TX_EN; -+ cmd &= ~CMD_RX_EN; -+ cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT; -+ enet_umac_write(enet, UMAC_CMD, cmd); -+ -+ enet_maskset(enet, ENET_GMAC_STATUS, -+ ENET_GMAC_STATUS_ETH_SPEED_MASK | -+ ENET_GMAC_STATUS_HD | -+ ENET_GMAC_STATUS_AUTO_CFG_EN | -+ ENET_GMAC_STATUS_LINK_UP, -+ ENET_GMAC_STATUS_ETH_SPEED_1000 | -+ ENET_GMAC_STATUS_AUTO_CFG_EN | -+ ENET_GMAC_STATUS_LINK_UP); -+} -+ -+static irqreturn_t bcm4908enet_irq_handler(int irq, void *dev_id) -+{ -+ struct bcm4908enet *enet = dev_id; -+ -+ bcm4908enet_intrs_off(enet); -+ bcm4908enet_intrs_ack(enet); -+ -+ napi_schedule(&enet->napi); -+ -+ return IRQ_HANDLED; -+} -+ -+static int bcm4908enet_open(struct net_device *netdev) -+{ -+ struct bcm4908enet *enet = netdev_priv(netdev); -+ struct device *dev = enet->dev; -+ int err; -+ -+ err = request_irq(netdev->irq, bcm4908enet_irq_handler, 0, "enet", enet); -+ if (err) { -+ dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err); -+ return err; -+ } -+ -+ bcm4908enet_gmac_init(enet); -+ bcm4908enet_dma_reset(enet); -+ bcm4908enet_dma_init(enet); -+ -+ enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN); -+ -+ enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN); -+ enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0); -+ bcm4908enet_dma_rx_ring_enable(enet, &enet->rx_ring); -+ -+ napi_enable(&enet->napi); -+ netif_carrier_on(netdev); -+ netif_start_queue(netdev); -+ -+ bcm4908enet_intrs_ack(enet); -+ bcm4908enet_intrs_on(enet); -+ -+ return 0; -+} -+ -+static int bcm4908enet_stop(struct net_device *netdev) -+{ -+ struct bcm4908enet *enet = netdev_priv(netdev); -+ -+ netif_stop_queue(netdev); -+ netif_carrier_off(netdev); -+ napi_disable(&enet->napi); -+ -+ bcm4908enet_dma_rx_ring_disable(enet, &enet->rx_ring); -+ bcm4908enet_dma_tx_ring_disable(enet, &enet->tx_ring); -+ -+ bcm4908enet_dma_uninit(enet); -+ -+ free_irq(enet->netdev->irq, enet); -+ -+ return 0; -+} -+ -+static int bcm4908enet_start_xmit(struct sk_buff *skb, struct net_device *netdev) -+{ -+ struct bcm4908enet *enet = netdev_priv(netdev); -+ struct bcm4908enet_dma_ring *ring = &enet->tx_ring; -+ struct bcm4908enet_dma_ring_slot *slot; -+ struct device *dev = enet->dev; -+ struct bcm4908enet_dma_ring_bd *buf_desc; -+ int free_buf_descs; -+ u32 tmp; -+ -+ /* Free transmitted skbs */ -+ while (ring->read_idx != ring->write_idx) { -+ buf_desc = &ring->buf_desc[ring->read_idx]; -+ if (buf_desc->ctl & DMA_CTL_STATUS_OWN) -+ break; -+ slot = &ring->slots[ring->read_idx]; -+ -+ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); -+ dev_kfree_skb(slot->skb); -+ if (++ring->read_idx == ring->length) -+ ring->read_idx = 0; -+ } -+ -+ /* Don't use the last empty buf descriptor */ -+ if (ring->read_idx <= ring->write_idx) -+ free_buf_descs = ring->read_idx - ring->write_idx + ring->length; -+ else -+ free_buf_descs = ring->read_idx - ring->write_idx; -+ if (free_buf_descs < 2) -+ return NETDEV_TX_BUSY; -+ -+ /* Hardware removes OWN bit after sending data */ -+ buf_desc = &ring->buf_desc[ring->write_idx]; -+ if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) { -+ netif_stop_queue(netdev); -+ return NETDEV_TX_BUSY; -+ } -+ -+ slot = &ring->slots[ring->write_idx]; -+ slot->skb = skb; -+ slot->len = skb->len; -+ slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); -+ if (unlikely(dma_mapping_error(dev, slot->dma_addr))) -+ return NETDEV_TX_BUSY; -+ -+ tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -+ tmp |= DMA_CTL_STATUS_OWN; -+ tmp |= DMA_CTL_STATUS_SOP; -+ tmp |= DMA_CTL_STATUS_EOP; -+ tmp |= DMA_CTL_STATUS_APPEND_CRC; -+ if (ring->write_idx + 1 == ring->length - 1) -+ tmp |= DMA_CTL_STATUS_WRAP; -+ -+ buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr); -+ buf_desc->ctl = cpu_to_le32(tmp); -+ -+ bcm4908enet_dma_tx_ring_ensable(enet, &enet->tx_ring); -+ -+ if (++ring->write_idx == ring->length - 1) -+ ring->write_idx = 0; -+ enet->netdev->stats.tx_bytes += skb->len; -+ enet->netdev->stats.tx_packets++; -+ -+ return NETDEV_TX_OK; -+} -+ -+static int bcm4908enet_poll(struct napi_struct *napi, int weight) -+{ -+ struct bcm4908enet *enet = container_of(napi, struct bcm4908enet, napi); -+ struct device *dev = enet->dev; -+ int handled = 0; -+ -+ while (handled < weight) { -+ struct bcm4908enet_dma_ring_bd *buf_desc; -+ struct bcm4908enet_dma_ring_slot slot; -+ u32 ctl; -+ int len; -+ int err; -+ -+ buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx]; -+ ctl = le32_to_cpu(buf_desc->ctl); -+ if (ctl & DMA_CTL_STATUS_OWN) -+ break; -+ -+ slot = enet->rx_ring.slots[enet->rx_ring.read_idx]; -+ -+ /* Provide new buffer before unpinning the old one */ -+ err = bcm4908enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx); -+ if (err) -+ break; -+ -+ if (++enet->rx_ring.read_idx == enet->rx_ring.length) -+ enet->rx_ring.read_idx = 0; -+ -+ len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -+ -+ if (len < ENET_MTU_MIN || -+ (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) { -+ enet->netdev->stats.rx_dropped++; -+ break; -+ } -+ -+ dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE); -+ -+ skb_put(slot.skb, len - 4 + 2); -+ slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev); -+ netif_receive_skb(slot.skb); -+ -+ enet->netdev->stats.rx_packets++; -+ enet->netdev->stats.rx_bytes += len; -+ } -+ -+ if (handled < weight) { -+ napi_complete_done(napi, handled); -+ bcm4908enet_intrs_on(enet); -+ } -+ -+ return handled; -+} -+ -+static const struct net_device_ops bcm96xx_netdev_ops = { -+ .ndo_open = bcm4908enet_open, -+ .ndo_stop = bcm4908enet_stop, -+ .ndo_start_xmit = bcm4908enet_start_xmit, -+ .ndo_set_mac_address = eth_mac_addr, -+}; -+ -+static int bcm4908enet_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct net_device *netdev; -+ struct bcm4908enet *enet; -+ int err; -+ -+ netdev = devm_alloc_etherdev(dev, sizeof(*enet)); -+ if (!netdev) -+ return -ENOMEM; -+ -+ enet = netdev_priv(netdev); -+ enet->dev = dev; -+ enet->netdev = netdev; -+ -+ enet->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(enet->base)) { -+ dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base)); -+ return PTR_ERR(enet->base); -+ } -+ -+ netdev->irq = platform_get_irq_byname(pdev, "rx"); -+ if (netdev->irq < 0) -+ return netdev->irq; -+ -+ dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); -+ -+ err = bcm4908enet_dma_alloc(enet); -+ if (err) -+ return err; -+ -+ SET_NETDEV_DEV(netdev, &pdev->dev); -+ eth_hw_addr_random(netdev); -+ netdev->netdev_ops = &bcm96xx_netdev_ops; -+ netdev->min_mtu = ETH_ZLEN; -+ netdev->mtu = ENET_MTU_MAX; -+ netdev->max_mtu = ENET_MTU_MAX; -+ netif_napi_add(netdev, &enet->napi, bcm4908enet_poll, 64); -+ -+ err = register_netdev(netdev); -+ if (err) { -+ bcm4908enet_dma_free(enet); -+ return err; -+ } -+ -+ platform_set_drvdata(pdev, enet); -+ -+ return 0; -+} -+ -+static int bcm4908enet_remove(struct platform_device *pdev) -+{ -+ struct bcm4908enet *enet = platform_get_drvdata(pdev); -+ -+ unregister_netdev(enet->netdev); -+ netif_napi_del(&enet->napi); -+ bcm4908enet_dma_free(enet); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm4908enet_of_match[] = { -+ { .compatible = "brcm,bcm4908enet"}, -+ {}, -+}; -+ -+static struct platform_driver bcm4908enet_driver = { -+ .driver = { -+ .name = "bcm4908enet", -+ .of_match_table = bcm4908enet_of_match, -+ }, -+ .probe = bcm4908enet_probe, -+ .remove = bcm4908enet_remove, -+}; -+module_platform_driver(bcm4908enet_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_DEVICE_TABLE(of, bcm4908enet_of_match); ---- /dev/null -+++ b/drivers/net/ethernet/broadcom/bcm4908enet.h -@@ -0,0 +1,96 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+#ifndef __BCM4908ENET_H -+#define __BCM4908ENET_H -+ -+#define ENET_CONTROL 0x000 -+#define ENET_MIB_CTRL 0x004 -+#define ENET_MIB_CTRL_CLR_MIB 0x00000001 -+#define ENET_RX_ERR_MASK 0x008 -+#define ENET_MIB_MAX_PKT_SIZE 0x00C -+#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff -+#define ENET_DIAG_OUT 0x01c -+#define ENET_ENABLE_DROP_PKT 0x020 -+#define ENET_IRQ_ENABLE 0x024 -+#define ENET_IRQ_ENABLE_OVFL 0x00000001 -+#define ENET_GMAC_STATUS 0x028 -+#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003 -+#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000 -+#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001 -+#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002 -+#define ENET_GMAC_STATUS_HD 0x00000004 -+#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008 -+#define ENET_GMAC_STATUS_LINK_UP 0x00000010 -+#define ENET_IRQ_STATUS 0x02c -+#define ENET_IRQ_STATUS_OVFL 0x00000001 -+#define ENET_OVERFLOW_COUNTER 0x030 -+#define ENET_FLUSH 0x034 -+#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001 -+#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002 -+#define ENET_RSV_SELECT 0x038 -+#define ENET_BP_FORCE 0x03c -+#define ENET_BP_FORCE_FORCE 0x00000001 -+#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040 -+#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f -+#define ENET_TX_CRC_CTRL 0x044 -+#define ENET_MIB 0x200 -+#define ENET_UNIMAC 0x400 -+#define ENET_DMA 0x800 -+#define ENET_DMA_CONTROLLER_CFG 0x800 -+#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001 -+#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002 -+#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004 -+#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804 -+#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808 -+#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c -+#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000 -+#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810 -+#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814 -+#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818 -+#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C -+#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820 -+#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824 -+#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828 -+#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C -+#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830 -+#define ENET_DMA_CTRL_CHANNEL_RESET 0x834 -+#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838 -+#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840 -+#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844 -+#define ENET_DMA_CH0_CFG 0xa00 /* RX */ -+#define ENET_DMA_CH1_CFG 0xa10 /* TX */ -+#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */ -+#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */ -+ -+#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */ -+#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */ -+#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ -+#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */ -+#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */ -+#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */ -+#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */ -+#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */ -+#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */ -+#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */ -+#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */ -+#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ -+#define ENET_DMA_CH_CFG_SIZE 0x10 -+ -+#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */ -+#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */ -+#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */ -+#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */ -+#define ENET_DMA_CH_STATE_RAM_SIZE 0x10 -+ -+#define DMA_CTL_STATUS_APPEND_CRC 0x00000100 -+#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200 -+#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */ -+#define DMA_CTL_STATUS_WRAP 0x00001000 /* */ -+#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */ -+#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */ -+#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */ -+#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000 -+#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16 -+#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000 -+#define DMA_CTL_LEN_DESC_USEFPM 0x80000000 -+ -+#endif diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0001-dt-bindings-net-rename-BCM4908-Ethernet-binding.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0001-dt-bindings-net-rename-BCM4908-Ethernet-binding.patch deleted file mode 100644 index dd297bcf9b..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0001-dt-bindings-net-rename-BCM4908-Ethernet-binding.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 6710c5b0674f8811f7d8fbfc526684e7ed77f765 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 13:12:32 +0100 -Subject: [PATCH] dt-bindings: net: rename BCM4908 Ethernet binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Rob pointed out that a normal convention is "brcm,bcm4908-enet" so -update whole binding to match it. - -Suggested-by: Rob Herring -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - .../net/{brcm,bcm4908enet.yaml => brcm,bcm4908-enet.yaml} | 6 +++--- - MAINTAINERS | 2 +- - 2 files changed, 4 insertions(+), 4 deletions(-) - rename Documentation/devicetree/bindings/net/{brcm,bcm4908enet.yaml => brcm,bcm4908-enet.yaml} (85%) - ---- a/Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml -+++ /dev/null -@@ -1,45 +0,0 @@ --# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause --%YAML 1.2 ----- --$id: http://devicetree.org/schemas/net/brcm,bcm4908enet.yaml# --$schema: http://devicetree.org/meta-schemas/core.yaml# -- --title: Broadcom BCM4908 Ethernet controller -- --description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs -- --maintainers: -- - Rafał Miłecki -- --properties: -- compatible: -- const: brcm,bcm4908enet -- -- reg: -- maxItems: 1 -- -- interrupts: -- description: RX interrupt -- -- interrupt-names: -- const: rx -- --required: -- - reg -- - interrupts -- - interrupt-names -- --additionalProperties: false -- --examples: -- - | -- #include -- #include -- -- ethernet@80002000 { -- compatible = "brcm,bcm4908enet"; -- reg = <0x80002000 0x1000>; -- -- interrupts = ; -- interrupt-names = "rx"; -- }; ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml -@@ -0,0 +1,45 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/brcm,bcm4908-enet.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM4908 Ethernet controller -+ -+description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs -+ -+maintainers: -+ - Rafał Miłecki -+ -+properties: -+ compatible: -+ const: brcm,bcm4908-enet -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ description: RX interrupt -+ -+ interrupt-names: -+ const: rx -+ -+required: -+ - reg -+ - interrupts -+ - interrupt-names -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ -+ ethernet@80002000 { -+ compatible = "brcm,bcm4908-enet"; -+ reg = <0x80002000 0x1000>; -+ -+ interrupts = ; -+ interrupt-names = "rx"; -+ }; ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3432,7 +3432,7 @@ M: Rafał Miłecki - M: bcm-kernel-feedback-list@broadcom.com - L: netdev@vger.kernel.org - S: Maintained --F: Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml -+F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml - F: drivers/net/ethernet/broadcom/bcm4908enet.* - F: drivers/net/ethernet/broadcom/unimac.h - diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0002-dt-bindings-net-bcm4908-enet-include-ethernet-contro.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0002-dt-bindings-net-bcm4908-enet-include-ethernet-contro.patch deleted file mode 100644 index a4409a818a..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0002-dt-bindings-net-bcm4908-enet-include-ethernet-contro.patch +++ /dev/null @@ -1,32 +0,0 @@ -From f08b5cf1eb1f2aefc6fe4a89c8c757ba94721d0b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 13:12:33 +0100 -Subject: [PATCH] dt-bindings: net: bcm4908-enet: include - ethernet-controller.yaml -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It should be /included/ by every Ethernet controller binding. It adds -support for various generic properties. - -Suggested-by: Rob Herring -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml -+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml -@@ -11,6 +11,9 @@ description: Broadcom's Ethernet control - maintainers: - - Rafał Miłecki - -+allOf: -+ - $ref: ethernet-controller.yaml# -+ - properties: - compatible: - const: brcm,bcm4908-enet diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0003-net-broadcom-rename-BCM4908-driver-update-DT-binding.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0003-net-broadcom-rename-BCM4908-driver-update-DT-binding.patch deleted file mode 100644 index 3d22d0e042..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0003-net-broadcom-rename-BCM4908-driver-update-DT-binding.patch +++ /dev/null @@ -1,1614 +0,0 @@ -From 9d61d138ab30bbfe4a8609853c81e881c4054a0b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 13:12:34 +0100 -Subject: [PATCH] net: broadcom: rename BCM4908 driver & update DT binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -compatible string was updated to match normal naming convention so -update driver as well - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - MAINTAINERS | 2 +- - drivers/net/ethernet/broadcom/Kconfig | 2 +- - drivers/net/ethernet/broadcom/Makefile | 2 +- - .../{bcm4908enet.c => bcm4908_enet.c} | 215 +++++++++--------- - .../{bcm4908enet.h => bcm4908_enet.h} | 4 +- - 5 files changed, 113 insertions(+), 112 deletions(-) - rename drivers/net/ethernet/broadcom/{bcm4908enet.c => bcm4908_enet.c} (68%) - rename drivers/net/ethernet/broadcom/{bcm4908enet.h => bcm4908_enet.h} (98%) - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3433,7 +3433,7 @@ M: bcm-kernel-feedback-list@broadcom.com - L: netdev@vger.kernel.org - S: Maintained - F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml --F: drivers/net/ethernet/broadcom/bcm4908enet.* -+F: drivers/net/ethernet/broadcom/bcm4908_enet.* - F: drivers/net/ethernet/broadcom/unimac.h - - BROADCOM BCM5301X ARM ARCHITECTURE ---- a/drivers/net/ethernet/broadcom/Kconfig -+++ b/drivers/net/ethernet/broadcom/Kconfig -@@ -51,7 +51,7 @@ config B44_PCI - depends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT - default y - --config BCM4908ENET -+config BCM4908_ENET - tristate "Broadcom BCM4908 internal mac support" - depends on ARCH_BCM4908 || COMPILE_TEST - default y ---- a/drivers/net/ethernet/broadcom/Makefile -+++ b/drivers/net/ethernet/broadcom/Makefile -@@ -4,7 +4,7 @@ - # - - obj-$(CONFIG_B44) += b44.o --obj-$(CONFIG_BCM4908ENET) += bcm4908enet.o -+obj-$(CONFIG_BCM4908_ENET) += bcm4908_enet.o - obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o - obj-$(CONFIG_BCMGENET) += genet/ - obj-$(CONFIG_BNX2) += bnx2.o ---- a/drivers/net/ethernet/broadcom/bcm4908enet.c -+++ /dev/null -@@ -1,676 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-only --/* -- * Copyright (C) 2021 Rafał Miłecki -- */ -- --#include --#include --#include --#include --#include --#include --#include --#include -- --#include "bcm4908enet.h" --#include "unimac.h" -- --#define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG --#define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG --#define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM --#define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM -- --#define ENET_TX_BDS_NUM 200 --#define ENET_RX_BDS_NUM 200 --#define ENET_RX_BDS_NUM_MAX 8192 -- --#define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \ -- ENET_DMA_CH_CFG_INT_NO_DESC | \ -- ENET_DMA_CH_CFG_INT_BUFF_DONE) --#define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */ -- --#define ENET_MTU_MIN 60 --#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */ --#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */ -- --struct bcm4908enet_dma_ring_bd { -- __le32 ctl; -- __le32 addr; --} __packed; -- --struct bcm4908enet_dma_ring_slot { -- struct sk_buff *skb; -- unsigned int len; -- dma_addr_t dma_addr; --}; -- --struct bcm4908enet_dma_ring { -- int is_tx; -- int read_idx; -- int write_idx; -- int length; -- u16 cfg_block; -- u16 st_ram_block; -- -- union { -- void *cpu_addr; -- struct bcm4908enet_dma_ring_bd *buf_desc; -- }; -- dma_addr_t dma_addr; -- -- struct bcm4908enet_dma_ring_slot *slots; --}; -- --struct bcm4908enet { -- struct device *dev; -- struct net_device *netdev; -- struct napi_struct napi; -- void __iomem *base; -- -- struct bcm4908enet_dma_ring tx_ring; -- struct bcm4908enet_dma_ring rx_ring; --}; -- --/*** -- * R/W ops -- */ -- --static inline u32 enet_read(struct bcm4908enet *enet, u16 offset) --{ -- return readl(enet->base + offset); --} -- --static inline void enet_write(struct bcm4908enet *enet, u16 offset, u32 value) --{ -- writel(value, enet->base + offset); --} -- --static inline void enet_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set) --{ -- u32 val; -- -- WARN_ON(set & ~mask); -- -- val = enet_read(enet, offset); -- val = (val & ~mask) | (set & mask); -- enet_write(enet, offset, val); --} -- --static inline void enet_set(struct bcm4908enet *enet, u16 offset, u32 set) --{ -- enet_maskset(enet, offset, set, set); --} -- --static inline u32 enet_umac_read(struct bcm4908enet *enet, u16 offset) --{ -- return enet_read(enet, ENET_UNIMAC + offset); --} -- --static inline void enet_umac_write(struct bcm4908enet *enet, u16 offset, u32 value) --{ -- enet_write(enet, ENET_UNIMAC + offset, value); --} -- --static inline void enet_umac_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set) --{ -- enet_maskset(enet, ENET_UNIMAC + offset, mask, set); --} -- --static inline void enet_umac_set(struct bcm4908enet *enet, u16 offset, u32 set) --{ -- enet_set(enet, ENET_UNIMAC + offset, set); --} -- --/*** -- * Helpers -- */ -- --static void bcm4908enet_intrs_on(struct bcm4908enet *enet) --{ -- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS); --} -- --static void bcm4908enet_intrs_off(struct bcm4908enet *enet) --{ -- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0); --} -- --static void bcm4908enet_intrs_ack(struct bcm4908enet *enet) --{ -- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS); --} -- --/*** -- * DMA -- */ -- --static int bcm4908_dma_alloc_buf_descs(struct bcm4908enet *enet, struct bcm4908enet_dma_ring *ring) --{ -- int size = ring->length * sizeof(struct bcm4908enet_dma_ring_bd); -- struct device *dev = enet->dev; -- -- ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL); -- if (!ring->cpu_addr) -- return -ENOMEM; -- -- if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) { -- dev_err(dev, "Invalid DMA ring alignment\n"); -- goto err_free_buf_descs; -- } -- -- ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL); -- if (!ring->slots) -- goto err_free_buf_descs; -- -- memset(ring->cpu_addr, 0, size); -- -- ring->read_idx = 0; -- ring->write_idx = 0; -- -- return 0; -- --err_free_buf_descs: -- dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr); -- return -ENOMEM; --} -- --static void bcm4908enet_dma_free(struct bcm4908enet *enet) --{ -- struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring; -- struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring; -- struct device *dev = enet->dev; -- int size; -- -- size = rx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd); -- if (rx_ring->cpu_addr) -- dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr); -- kfree(rx_ring->slots); -- -- size = tx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd); -- if (tx_ring->cpu_addr) -- dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr); -- kfree(tx_ring->slots); --} -- --static int bcm4908enet_dma_alloc(struct bcm4908enet *enet) --{ -- struct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring; -- struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring; -- struct device *dev = enet->dev; -- int err; -- -- tx_ring->length = ENET_TX_BDS_NUM; -- tx_ring->is_tx = 1; -- tx_ring->cfg_block = ENET_DMA_CH_TX_CFG; -- tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM; -- err = bcm4908_dma_alloc_buf_descs(enet, tx_ring); -- if (err) { -- dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err); -- return err; -- } -- -- rx_ring->length = ENET_RX_BDS_NUM; -- rx_ring->is_tx = 0; -- rx_ring->cfg_block = ENET_DMA_CH_RX_CFG; -- rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM; -- err = bcm4908_dma_alloc_buf_descs(enet, rx_ring); -- if (err) { -- dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err); -- bcm4908enet_dma_free(enet); -- return err; -- } -- -- return 0; --} -- --static void bcm4908enet_dma_reset(struct bcm4908enet *enet) --{ -- struct bcm4908enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring }; -- int i; -- -- /* Disable the DMA controller and channel */ -- for (i = 0; i < ARRAY_SIZE(rings); i++) -- enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0); -- enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0); -- -- /* Reset channels state */ -- for (i = 0; i < ARRAY_SIZE(rings); i++) { -- struct bcm4908enet_dma_ring *ring = rings[i]; -- -- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0); -- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0); -- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0); -- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0); -- } --} -- --static int bcm4908enet_dma_alloc_rx_buf(struct bcm4908enet *enet, unsigned int idx) --{ -- struct bcm4908enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx]; -- struct bcm4908enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx]; -- struct device *dev = enet->dev; -- u32 tmp; -- int err; -- -- slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE; -- -- slot->skb = netdev_alloc_skb(enet->netdev, slot->len); -- if (!slot->skb) -- return -ENOMEM; -- -- slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE); -- err = dma_mapping_error(dev, slot->dma_addr); -- if (err) { -- dev_err(dev, "Failed to map DMA buffer: %d\n", err); -- kfree_skb(slot->skb); -- slot->skb = NULL; -- return err; -- } -- -- tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -- tmp |= DMA_CTL_STATUS_OWN; -- if (idx == enet->rx_ring.length - 1) -- tmp |= DMA_CTL_STATUS_WRAP; -- buf_desc->ctl = cpu_to_le32(tmp); -- buf_desc->addr = cpu_to_le32(slot->dma_addr); -- -- return 0; --} -- --static void bcm4908enet_dma_ring_init(struct bcm4908enet *enet, -- struct bcm4908enet_dma_ring *ring) --{ -- int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */ -- int reset_subch = ring->is_tx ? 1 : 0; -- -- /* Reset the DMA channel */ -- enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch)); -- enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0); -- -- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); -- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN); -- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0); -- -- enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, -- (uint32_t)ring->dma_addr); --} -- --static void bcm4908enet_dma_uninit(struct bcm4908enet *enet) --{ -- struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring; -- struct bcm4908enet_dma_ring_slot *slot; -- struct device *dev = enet->dev; -- int i; -- -- for (i = rx_ring->length - 1; i >= 0; i--) { -- slot = &rx_ring->slots[i]; -- if (!slot->skb) -- continue; -- dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE); -- kfree_skb(slot->skb); -- slot->skb = NULL; -- } --} -- --static int bcm4908enet_dma_init(struct bcm4908enet *enet) --{ -- struct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring; -- struct device *dev = enet->dev; -- int err; -- int i; -- -- for (i = 0; i < rx_ring->length; i++) { -- err = bcm4908enet_dma_alloc_rx_buf(enet, i); -- if (err) { -- dev_err(dev, "Failed to alloc RX buffer: %d\n", err); -- bcm4908enet_dma_uninit(enet); -- return err; -- } -- } -- -- bcm4908enet_dma_ring_init(enet, &enet->tx_ring); -- bcm4908enet_dma_ring_init(enet, &enet->rx_ring); -- -- return 0; --} -- --static void bcm4908enet_dma_tx_ring_ensable(struct bcm4908enet *enet, -- struct bcm4908enet_dma_ring *ring) --{ -- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); --} -- --static void bcm4908enet_dma_tx_ring_disable(struct bcm4908enet *enet, -- struct bcm4908enet_dma_ring *ring) --{ -- enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); --} -- --static void bcm4908enet_dma_rx_ring_enable(struct bcm4908enet *enet, -- struct bcm4908enet_dma_ring *ring) --{ -- enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); --} -- --static void bcm4908enet_dma_rx_ring_disable(struct bcm4908enet *enet, -- struct bcm4908enet_dma_ring *ring) --{ -- unsigned long deadline; -- u32 tmp; -- -- enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); -- -- deadline = jiffies + usecs_to_jiffies(2000); -- do { -- tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG); -- if (!(tmp & ENET_DMA_CH_CFG_ENABLE)) -- return; -- enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); -- usleep_range(10, 30); -- } while (!time_after_eq(jiffies, deadline)); -- -- dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n"); --} -- --/*** -- * Ethernet driver -- */ -- --static void bcm4908enet_gmac_init(struct bcm4908enet *enet) --{ -- u32 cmd; -- -- cmd = enet_umac_read(enet, UMAC_CMD); -- enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET); -- enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET); -- -- enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH); -- enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0); -- -- enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB); -- enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0); -- -- cmd = enet_umac_read(enet, UMAC_CMD); -- cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT); -- cmd &= ~CMD_TX_EN; -- cmd &= ~CMD_RX_EN; -- cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT; -- enet_umac_write(enet, UMAC_CMD, cmd); -- -- enet_maskset(enet, ENET_GMAC_STATUS, -- ENET_GMAC_STATUS_ETH_SPEED_MASK | -- ENET_GMAC_STATUS_HD | -- ENET_GMAC_STATUS_AUTO_CFG_EN | -- ENET_GMAC_STATUS_LINK_UP, -- ENET_GMAC_STATUS_ETH_SPEED_1000 | -- ENET_GMAC_STATUS_AUTO_CFG_EN | -- ENET_GMAC_STATUS_LINK_UP); --} -- --static irqreturn_t bcm4908enet_irq_handler(int irq, void *dev_id) --{ -- struct bcm4908enet *enet = dev_id; -- -- bcm4908enet_intrs_off(enet); -- bcm4908enet_intrs_ack(enet); -- -- napi_schedule(&enet->napi); -- -- return IRQ_HANDLED; --} -- --static int bcm4908enet_open(struct net_device *netdev) --{ -- struct bcm4908enet *enet = netdev_priv(netdev); -- struct device *dev = enet->dev; -- int err; -- -- err = request_irq(netdev->irq, bcm4908enet_irq_handler, 0, "enet", enet); -- if (err) { -- dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err); -- return err; -- } -- -- bcm4908enet_gmac_init(enet); -- bcm4908enet_dma_reset(enet); -- bcm4908enet_dma_init(enet); -- -- enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN); -- -- enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN); -- enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0); -- bcm4908enet_dma_rx_ring_enable(enet, &enet->rx_ring); -- -- napi_enable(&enet->napi); -- netif_carrier_on(netdev); -- netif_start_queue(netdev); -- -- bcm4908enet_intrs_ack(enet); -- bcm4908enet_intrs_on(enet); -- -- return 0; --} -- --static int bcm4908enet_stop(struct net_device *netdev) --{ -- struct bcm4908enet *enet = netdev_priv(netdev); -- -- netif_stop_queue(netdev); -- netif_carrier_off(netdev); -- napi_disable(&enet->napi); -- -- bcm4908enet_dma_rx_ring_disable(enet, &enet->rx_ring); -- bcm4908enet_dma_tx_ring_disable(enet, &enet->tx_ring); -- -- bcm4908enet_dma_uninit(enet); -- -- free_irq(enet->netdev->irq, enet); -- -- return 0; --} -- --static int bcm4908enet_start_xmit(struct sk_buff *skb, struct net_device *netdev) --{ -- struct bcm4908enet *enet = netdev_priv(netdev); -- struct bcm4908enet_dma_ring *ring = &enet->tx_ring; -- struct bcm4908enet_dma_ring_slot *slot; -- struct device *dev = enet->dev; -- struct bcm4908enet_dma_ring_bd *buf_desc; -- int free_buf_descs; -- u32 tmp; -- -- /* Free transmitted skbs */ -- while (ring->read_idx != ring->write_idx) { -- buf_desc = &ring->buf_desc[ring->read_idx]; -- if (buf_desc->ctl & DMA_CTL_STATUS_OWN) -- break; -- slot = &ring->slots[ring->read_idx]; -- -- dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); -- dev_kfree_skb(slot->skb); -- if (++ring->read_idx == ring->length) -- ring->read_idx = 0; -- } -- -- /* Don't use the last empty buf descriptor */ -- if (ring->read_idx <= ring->write_idx) -- free_buf_descs = ring->read_idx - ring->write_idx + ring->length; -- else -- free_buf_descs = ring->read_idx - ring->write_idx; -- if (free_buf_descs < 2) -- return NETDEV_TX_BUSY; -- -- /* Hardware removes OWN bit after sending data */ -- buf_desc = &ring->buf_desc[ring->write_idx]; -- if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) { -- netif_stop_queue(netdev); -- return NETDEV_TX_BUSY; -- } -- -- slot = &ring->slots[ring->write_idx]; -- slot->skb = skb; -- slot->len = skb->len; -- slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); -- if (unlikely(dma_mapping_error(dev, slot->dma_addr))) -- return NETDEV_TX_BUSY; -- -- tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -- tmp |= DMA_CTL_STATUS_OWN; -- tmp |= DMA_CTL_STATUS_SOP; -- tmp |= DMA_CTL_STATUS_EOP; -- tmp |= DMA_CTL_STATUS_APPEND_CRC; -- if (ring->write_idx + 1 == ring->length - 1) -- tmp |= DMA_CTL_STATUS_WRAP; -- -- buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr); -- buf_desc->ctl = cpu_to_le32(tmp); -- -- bcm4908enet_dma_tx_ring_ensable(enet, &enet->tx_ring); -- -- if (++ring->write_idx == ring->length - 1) -- ring->write_idx = 0; -- enet->netdev->stats.tx_bytes += skb->len; -- enet->netdev->stats.tx_packets++; -- -- return NETDEV_TX_OK; --} -- --static int bcm4908enet_poll(struct napi_struct *napi, int weight) --{ -- struct bcm4908enet *enet = container_of(napi, struct bcm4908enet, napi); -- struct device *dev = enet->dev; -- int handled = 0; -- -- while (handled < weight) { -- struct bcm4908enet_dma_ring_bd *buf_desc; -- struct bcm4908enet_dma_ring_slot slot; -- u32 ctl; -- int len; -- int err; -- -- buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx]; -- ctl = le32_to_cpu(buf_desc->ctl); -- if (ctl & DMA_CTL_STATUS_OWN) -- break; -- -- slot = enet->rx_ring.slots[enet->rx_ring.read_idx]; -- -- /* Provide new buffer before unpinning the old one */ -- err = bcm4908enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx); -- if (err) -- break; -- -- if (++enet->rx_ring.read_idx == enet->rx_ring.length) -- enet->rx_ring.read_idx = 0; -- -- len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -- -- if (len < ENET_MTU_MIN || -- (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) { -- enet->netdev->stats.rx_dropped++; -- break; -- } -- -- dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE); -- -- skb_put(slot.skb, len - 4 + 2); -- slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev); -- netif_receive_skb(slot.skb); -- -- enet->netdev->stats.rx_packets++; -- enet->netdev->stats.rx_bytes += len; -- } -- -- if (handled < weight) { -- napi_complete_done(napi, handled); -- bcm4908enet_intrs_on(enet); -- } -- -- return handled; --} -- --static const struct net_device_ops bcm96xx_netdev_ops = { -- .ndo_open = bcm4908enet_open, -- .ndo_stop = bcm4908enet_stop, -- .ndo_start_xmit = bcm4908enet_start_xmit, -- .ndo_set_mac_address = eth_mac_addr, --}; -- --static int bcm4908enet_probe(struct platform_device *pdev) --{ -- struct device *dev = &pdev->dev; -- struct net_device *netdev; -- struct bcm4908enet *enet; -- int err; -- -- netdev = devm_alloc_etherdev(dev, sizeof(*enet)); -- if (!netdev) -- return -ENOMEM; -- -- enet = netdev_priv(netdev); -- enet->dev = dev; -- enet->netdev = netdev; -- -- enet->base = devm_platform_ioremap_resource(pdev, 0); -- if (IS_ERR(enet->base)) { -- dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base)); -- return PTR_ERR(enet->base); -- } -- -- netdev->irq = platform_get_irq_byname(pdev, "rx"); -- if (netdev->irq < 0) -- return netdev->irq; -- -- dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); -- -- err = bcm4908enet_dma_alloc(enet); -- if (err) -- return err; -- -- SET_NETDEV_DEV(netdev, &pdev->dev); -- eth_hw_addr_random(netdev); -- netdev->netdev_ops = &bcm96xx_netdev_ops; -- netdev->min_mtu = ETH_ZLEN; -- netdev->mtu = ENET_MTU_MAX; -- netdev->max_mtu = ENET_MTU_MAX; -- netif_napi_add(netdev, &enet->napi, bcm4908enet_poll, 64); -- -- err = register_netdev(netdev); -- if (err) { -- bcm4908enet_dma_free(enet); -- return err; -- } -- -- platform_set_drvdata(pdev, enet); -- -- return 0; --} -- --static int bcm4908enet_remove(struct platform_device *pdev) --{ -- struct bcm4908enet *enet = platform_get_drvdata(pdev); -- -- unregister_netdev(enet->netdev); -- netif_napi_del(&enet->napi); -- bcm4908enet_dma_free(enet); -- -- return 0; --} -- --static const struct of_device_id bcm4908enet_of_match[] = { -- { .compatible = "brcm,bcm4908enet"}, -- {}, --}; -- --static struct platform_driver bcm4908enet_driver = { -- .driver = { -- .name = "bcm4908enet", -- .of_match_table = bcm4908enet_of_match, -- }, -- .probe = bcm4908enet_probe, -- .remove = bcm4908enet_remove, --}; --module_platform_driver(bcm4908enet_driver); -- --MODULE_LICENSE("GPL v2"); --MODULE_DEVICE_TABLE(of, bcm4908enet_of_match); ---- /dev/null -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -0,0 +1,677 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2021 Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "bcm4908_enet.h" -+#include "unimac.h" -+ -+#define ENET_DMA_CH_RX_CFG ENET_DMA_CH0_CFG -+#define ENET_DMA_CH_TX_CFG ENET_DMA_CH1_CFG -+#define ENET_DMA_CH_RX_STATE_RAM ENET_DMA_CH0_STATE_RAM -+#define ENET_DMA_CH_TX_STATE_RAM ENET_DMA_CH1_STATE_RAM -+ -+#define ENET_TX_BDS_NUM 200 -+#define ENET_RX_BDS_NUM 200 -+#define ENET_RX_BDS_NUM_MAX 8192 -+ -+#define ENET_DMA_INT_DEFAULTS (ENET_DMA_CH_CFG_INT_DONE | \ -+ ENET_DMA_CH_CFG_INT_NO_DESC | \ -+ ENET_DMA_CH_CFG_INT_BUFF_DONE) -+#define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */ -+ -+#define ENET_MTU_MIN 60 -+#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */ -+#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */ -+ -+struct bcm4908_enet_dma_ring_bd { -+ __le32 ctl; -+ __le32 addr; -+} __packed; -+ -+struct bcm4908_enet_dma_ring_slot { -+ struct sk_buff *skb; -+ unsigned int len; -+ dma_addr_t dma_addr; -+}; -+ -+struct bcm4908_enet_dma_ring { -+ int is_tx; -+ int read_idx; -+ int write_idx; -+ int length; -+ u16 cfg_block; -+ u16 st_ram_block; -+ -+ union { -+ void *cpu_addr; -+ struct bcm4908_enet_dma_ring_bd *buf_desc; -+ }; -+ dma_addr_t dma_addr; -+ -+ struct bcm4908_enet_dma_ring_slot *slots; -+}; -+ -+struct bcm4908_enet { -+ struct device *dev; -+ struct net_device *netdev; -+ struct napi_struct napi; -+ void __iomem *base; -+ -+ struct bcm4908_enet_dma_ring tx_ring; -+ struct bcm4908_enet_dma_ring rx_ring; -+}; -+ -+/*** -+ * R/W ops -+ */ -+ -+static inline u32 enet_read(struct bcm4908_enet *enet, u16 offset) -+{ -+ return readl(enet->base + offset); -+} -+ -+static inline void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value) -+{ -+ writel(value, enet->base + offset); -+} -+ -+static inline void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set) -+{ -+ u32 val; -+ -+ WARN_ON(set & ~mask); -+ -+ val = enet_read(enet, offset); -+ val = (val & ~mask) | (set & mask); -+ enet_write(enet, offset, val); -+} -+ -+static inline void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set) -+{ -+ enet_maskset(enet, offset, set, set); -+} -+ -+static inline u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset) -+{ -+ return enet_read(enet, ENET_UNIMAC + offset); -+} -+ -+static inline void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value) -+{ -+ enet_write(enet, ENET_UNIMAC + offset, value); -+} -+ -+static inline void enet_umac_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set) -+{ -+ enet_maskset(enet, ENET_UNIMAC + offset, mask, set); -+} -+ -+static inline void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set) -+{ -+ enet_set(enet, ENET_UNIMAC + offset, set); -+} -+ -+/*** -+ * Helpers -+ */ -+ -+static void bcm4908_enet_intrs_on(struct bcm4908_enet *enet) -+{ -+ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS); -+} -+ -+static void bcm4908_enet_intrs_off(struct bcm4908_enet *enet) -+{ -+ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0); -+} -+ -+static void bcm4908_enet_intrs_ack(struct bcm4908_enet *enet) -+{ -+ enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS); -+} -+ -+/*** -+ * DMA -+ */ -+ -+static int bcm4908_dma_alloc_buf_descs(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) -+{ -+ int size = ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); -+ struct device *dev = enet->dev; -+ -+ ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL); -+ if (!ring->cpu_addr) -+ return -ENOMEM; -+ -+ if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) { -+ dev_err(dev, "Invalid DMA ring alignment\n"); -+ goto err_free_buf_descs; -+ } -+ -+ ring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL); -+ if (!ring->slots) -+ goto err_free_buf_descs; -+ -+ memset(ring->cpu_addr, 0, size); -+ -+ ring->read_idx = 0; -+ ring->write_idx = 0; -+ -+ return 0; -+ -+err_free_buf_descs: -+ dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr); -+ return -ENOMEM; -+} -+ -+static void bcm4908_enet_dma_free(struct bcm4908_enet *enet) -+{ -+ struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; -+ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; -+ struct device *dev = enet->dev; -+ int size; -+ -+ size = rx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); -+ if (rx_ring->cpu_addr) -+ dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr); -+ kfree(rx_ring->slots); -+ -+ size = tx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd); -+ if (tx_ring->cpu_addr) -+ dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr); -+ kfree(tx_ring->slots); -+} -+ -+static int bcm4908_enet_dma_alloc(struct bcm4908_enet *enet) -+{ -+ struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; -+ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; -+ struct device *dev = enet->dev; -+ int err; -+ -+ tx_ring->length = ENET_TX_BDS_NUM; -+ tx_ring->is_tx = 1; -+ tx_ring->cfg_block = ENET_DMA_CH_TX_CFG; -+ tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM; -+ err = bcm4908_dma_alloc_buf_descs(enet, tx_ring); -+ if (err) { -+ dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err); -+ return err; -+ } -+ -+ rx_ring->length = ENET_RX_BDS_NUM; -+ rx_ring->is_tx = 0; -+ rx_ring->cfg_block = ENET_DMA_CH_RX_CFG; -+ rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM; -+ err = bcm4908_dma_alloc_buf_descs(enet, rx_ring); -+ if (err) { -+ dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err); -+ bcm4908_enet_dma_free(enet); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static void bcm4908_enet_dma_reset(struct bcm4908_enet *enet) -+{ -+ struct bcm4908_enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring }; -+ int i; -+ -+ /* Disable the DMA controller and channel */ -+ for (i = 0; i < ARRAY_SIZE(rings); i++) -+ enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0); -+ enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0); -+ -+ /* Reset channels state */ -+ for (i = 0; i < ARRAY_SIZE(rings); i++) { -+ struct bcm4908_enet_dma_ring *ring = rings[i]; -+ -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0); -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0); -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0); -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0); -+ } -+} -+ -+static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx) -+{ -+ struct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx]; -+ struct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx]; -+ struct device *dev = enet->dev; -+ u32 tmp; -+ int err; -+ -+ slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE; -+ -+ slot->skb = netdev_alloc_skb(enet->netdev, slot->len); -+ if (!slot->skb) -+ return -ENOMEM; -+ -+ slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE); -+ err = dma_mapping_error(dev, slot->dma_addr); -+ if (err) { -+ dev_err(dev, "Failed to map DMA buffer: %d\n", err); -+ kfree_skb(slot->skb); -+ slot->skb = NULL; -+ return err; -+ } -+ -+ tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -+ tmp |= DMA_CTL_STATUS_OWN; -+ if (idx == enet->rx_ring.length - 1) -+ tmp |= DMA_CTL_STATUS_WRAP; -+ buf_desc->ctl = cpu_to_le32(tmp); -+ buf_desc->addr = cpu_to_le32(slot->dma_addr); -+ -+ return 0; -+} -+ -+static void bcm4908_enet_dma_ring_init(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) -+{ -+ int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */ -+ int reset_subch = ring->is_tx ? 1 : 0; -+ -+ /* Reset the DMA channel */ -+ enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch)); -+ enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0); -+ -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN); -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0); -+ -+ enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, -+ (uint32_t)ring->dma_addr); -+} -+ -+static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet) -+{ -+ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; -+ struct bcm4908_enet_dma_ring_slot *slot; -+ struct device *dev = enet->dev; -+ int i; -+ -+ for (i = rx_ring->length - 1; i >= 0; i--) { -+ slot = &rx_ring->slots[i]; -+ if (!slot->skb) -+ continue; -+ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE); -+ kfree_skb(slot->skb); -+ slot->skb = NULL; -+ } -+} -+ -+static int bcm4908_enet_dma_init(struct bcm4908_enet *enet) -+{ -+ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; -+ struct device *dev = enet->dev; -+ int err; -+ int i; -+ -+ for (i = 0; i < rx_ring->length; i++) { -+ err = bcm4908_enet_dma_alloc_rx_buf(enet, i); -+ if (err) { -+ dev_err(dev, "Failed to alloc RX buffer: %d\n", err); -+ bcm4908_enet_dma_uninit(enet); -+ return err; -+ } -+ } -+ -+ bcm4908_enet_dma_ring_init(enet, &enet->tx_ring); -+ bcm4908_enet_dma_ring_init(enet, &enet->rx_ring); -+ -+ return 0; -+} -+ -+static void bcm4908_enet_dma_tx_ring_ensable(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) -+{ -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); -+} -+ -+static void bcm4908_enet_dma_tx_ring_disable(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) -+{ -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0); -+} -+ -+static void bcm4908_enet_dma_rx_ring_enable(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) -+{ -+ enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); -+} -+ -+static void bcm4908_enet_dma_rx_ring_disable(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) -+{ -+ unsigned long deadline; -+ u32 tmp; -+ -+ enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); -+ -+ deadline = jiffies + usecs_to_jiffies(2000); -+ do { -+ tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG); -+ if (!(tmp & ENET_DMA_CH_CFG_ENABLE)) -+ return; -+ enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0); -+ usleep_range(10, 30); -+ } while (!time_after_eq(jiffies, deadline)); -+ -+ dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n"); -+} -+ -+/*** -+ * Ethernet driver -+ */ -+ -+static void bcm4908_enet_gmac_init(struct bcm4908_enet *enet) -+{ -+ u32 cmd; -+ -+ cmd = enet_umac_read(enet, UMAC_CMD); -+ enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET); -+ enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET); -+ -+ enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH); -+ enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0); -+ -+ enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB); -+ enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0); -+ -+ cmd = enet_umac_read(enet, UMAC_CMD); -+ cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT); -+ cmd &= ~CMD_TX_EN; -+ cmd &= ~CMD_RX_EN; -+ cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT; -+ enet_umac_write(enet, UMAC_CMD, cmd); -+ -+ enet_maskset(enet, ENET_GMAC_STATUS, -+ ENET_GMAC_STATUS_ETH_SPEED_MASK | -+ ENET_GMAC_STATUS_HD | -+ ENET_GMAC_STATUS_AUTO_CFG_EN | -+ ENET_GMAC_STATUS_LINK_UP, -+ ENET_GMAC_STATUS_ETH_SPEED_1000 | -+ ENET_GMAC_STATUS_AUTO_CFG_EN | -+ ENET_GMAC_STATUS_LINK_UP); -+} -+ -+static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id) -+{ -+ struct bcm4908_enet *enet = dev_id; -+ -+ bcm4908_enet_intrs_off(enet); -+ bcm4908_enet_intrs_ack(enet); -+ -+ napi_schedule(&enet->napi); -+ -+ return IRQ_HANDLED; -+} -+ -+static int bcm4908_enet_open(struct net_device *netdev) -+{ -+ struct bcm4908_enet *enet = netdev_priv(netdev); -+ struct device *dev = enet->dev; -+ int err; -+ -+ err = request_irq(netdev->irq, bcm4908_enet_irq_handler, 0, "enet", enet); -+ if (err) { -+ dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err); -+ return err; -+ } -+ -+ bcm4908_enet_gmac_init(enet); -+ bcm4908_enet_dma_reset(enet); -+ bcm4908_enet_dma_init(enet); -+ -+ enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN); -+ -+ enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN); -+ enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0); -+ bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring); -+ -+ napi_enable(&enet->napi); -+ netif_carrier_on(netdev); -+ netif_start_queue(netdev); -+ -+ bcm4908_enet_intrs_ack(enet); -+ bcm4908_enet_intrs_on(enet); -+ -+ return 0; -+} -+ -+static int bcm4908_enet_stop(struct net_device *netdev) -+{ -+ struct bcm4908_enet *enet = netdev_priv(netdev); -+ -+ netif_stop_queue(netdev); -+ netif_carrier_off(netdev); -+ napi_disable(&enet->napi); -+ -+ bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring); -+ bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring); -+ -+ bcm4908_enet_dma_uninit(enet); -+ -+ free_irq(enet->netdev->irq, enet); -+ -+ return 0; -+} -+ -+static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev) -+{ -+ struct bcm4908_enet *enet = netdev_priv(netdev); -+ struct bcm4908_enet_dma_ring *ring = &enet->tx_ring; -+ struct bcm4908_enet_dma_ring_slot *slot; -+ struct device *dev = enet->dev; -+ struct bcm4908_enet_dma_ring_bd *buf_desc; -+ int free_buf_descs; -+ u32 tmp; -+ -+ /* Free transmitted skbs */ -+ while (ring->read_idx != ring->write_idx) { -+ buf_desc = &ring->buf_desc[ring->read_idx]; -+ if (buf_desc->ctl & DMA_CTL_STATUS_OWN) -+ break; -+ slot = &ring->slots[ring->read_idx]; -+ -+ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); -+ dev_kfree_skb(slot->skb); -+ if (++ring->read_idx == ring->length) -+ ring->read_idx = 0; -+ } -+ -+ /* Don't use the last empty buf descriptor */ -+ if (ring->read_idx <= ring->write_idx) -+ free_buf_descs = ring->read_idx - ring->write_idx + ring->length; -+ else -+ free_buf_descs = ring->read_idx - ring->write_idx; -+ if (free_buf_descs < 2) -+ return NETDEV_TX_BUSY; -+ -+ /* Hardware removes OWN bit after sending data */ -+ buf_desc = &ring->buf_desc[ring->write_idx]; -+ if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) { -+ netif_stop_queue(netdev); -+ return NETDEV_TX_BUSY; -+ } -+ -+ slot = &ring->slots[ring->write_idx]; -+ slot->skb = skb; -+ slot->len = skb->len; -+ slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); -+ if (unlikely(dma_mapping_error(dev, slot->dma_addr))) -+ return NETDEV_TX_BUSY; -+ -+ tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -+ tmp |= DMA_CTL_STATUS_OWN; -+ tmp |= DMA_CTL_STATUS_SOP; -+ tmp |= DMA_CTL_STATUS_EOP; -+ tmp |= DMA_CTL_STATUS_APPEND_CRC; -+ if (ring->write_idx + 1 == ring->length - 1) -+ tmp |= DMA_CTL_STATUS_WRAP; -+ -+ buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr); -+ buf_desc->ctl = cpu_to_le32(tmp); -+ -+ bcm4908_enet_dma_tx_ring_ensable(enet, &enet->tx_ring); -+ -+ if (++ring->write_idx == ring->length - 1) -+ ring->write_idx = 0; -+ enet->netdev->stats.tx_bytes += skb->len; -+ enet->netdev->stats.tx_packets++; -+ -+ return NETDEV_TX_OK; -+} -+ -+static int bcm4908_enet_poll(struct napi_struct *napi, int weight) -+{ -+ struct bcm4908_enet *enet = container_of(napi, struct bcm4908_enet, napi); -+ struct device *dev = enet->dev; -+ int handled = 0; -+ -+ while (handled < weight) { -+ struct bcm4908_enet_dma_ring_bd *buf_desc; -+ struct bcm4908_enet_dma_ring_slot slot; -+ u32 ctl; -+ int len; -+ int err; -+ -+ buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx]; -+ ctl = le32_to_cpu(buf_desc->ctl); -+ if (ctl & DMA_CTL_STATUS_OWN) -+ break; -+ -+ slot = enet->rx_ring.slots[enet->rx_ring.read_idx]; -+ -+ /* Provide new buffer before unpinning the old one */ -+ err = bcm4908_enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx); -+ if (err) -+ break; -+ -+ if (++enet->rx_ring.read_idx == enet->rx_ring.length) -+ enet->rx_ring.read_idx = 0; -+ -+ len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -+ -+ if (len < ENET_MTU_MIN || -+ (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) { -+ enet->netdev->stats.rx_dropped++; -+ break; -+ } -+ -+ dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE); -+ -+ skb_put(slot.skb, len - 4 + 2); -+ slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev); -+ netif_receive_skb(slot.skb); -+ -+ enet->netdev->stats.rx_packets++; -+ enet->netdev->stats.rx_bytes += len; -+ } -+ -+ if (handled < weight) { -+ napi_complete_done(napi, handled); -+ bcm4908_enet_intrs_on(enet); -+ } -+ -+ return handled; -+} -+ -+static const struct net_device_ops bcm96xx_netdev_ops = { -+ .ndo_open = bcm4908_enet_open, -+ .ndo_stop = bcm4908_enet_stop, -+ .ndo_start_xmit = bcm4908_enet_start_xmit, -+ .ndo_set_mac_address = eth_mac_addr, -+}; -+ -+static int bcm4908_enet_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct net_device *netdev; -+ struct bcm4908_enet *enet; -+ int err; -+ -+ netdev = devm_alloc_etherdev(dev, sizeof(*enet)); -+ if (!netdev) -+ return -ENOMEM; -+ -+ enet = netdev_priv(netdev); -+ enet->dev = dev; -+ enet->netdev = netdev; -+ -+ enet->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(enet->base)) { -+ dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base)); -+ return PTR_ERR(enet->base); -+ } -+ -+ netdev->irq = platform_get_irq_byname(pdev, "rx"); -+ if (netdev->irq < 0) -+ return netdev->irq; -+ -+ dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); -+ -+ err = bcm4908_enet_dma_alloc(enet); -+ if (err) -+ return err; -+ -+ SET_NETDEV_DEV(netdev, &pdev->dev); -+ eth_hw_addr_random(netdev); -+ netdev->netdev_ops = &bcm96xx_netdev_ops; -+ netdev->min_mtu = ETH_ZLEN; -+ netdev->mtu = ENET_MTU_MAX; -+ netdev->max_mtu = ENET_MTU_MAX; -+ netif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64); -+ -+ err = register_netdev(netdev); -+ if (err) { -+ bcm4908_enet_dma_free(enet); -+ return err; -+ } -+ -+ platform_set_drvdata(pdev, enet); -+ -+ return 0; -+} -+ -+static int bcm4908_enet_remove(struct platform_device *pdev) -+{ -+ struct bcm4908_enet *enet = platform_get_drvdata(pdev); -+ -+ unregister_netdev(enet->netdev); -+ netif_napi_del(&enet->napi); -+ bcm4908_enet_dma_free(enet); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm4908_enet_of_match[] = { -+ { .compatible = "brcm,bcm4908-enet"}, -+ {}, -+}; -+ -+static struct platform_driver bcm4908_enet_driver = { -+ .driver = { -+ .name = "bcm4908_enet", -+ .of_match_table = bcm4908_enet_of_match, -+ }, -+ .probe = bcm4908_enet_probe, -+ .remove = bcm4908_enet_remove, -+}; -+module_platform_driver(bcm4908_enet_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_DEVICE_TABLE(of, bcm4908_enet_of_match); ---- a/drivers/net/ethernet/broadcom/bcm4908enet.h -+++ /dev/null -@@ -1,96 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ --#ifndef __BCM4908ENET_H --#define __BCM4908ENET_H -- --#define ENET_CONTROL 0x000 --#define ENET_MIB_CTRL 0x004 --#define ENET_MIB_CTRL_CLR_MIB 0x00000001 --#define ENET_RX_ERR_MASK 0x008 --#define ENET_MIB_MAX_PKT_SIZE 0x00C --#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff --#define ENET_DIAG_OUT 0x01c --#define ENET_ENABLE_DROP_PKT 0x020 --#define ENET_IRQ_ENABLE 0x024 --#define ENET_IRQ_ENABLE_OVFL 0x00000001 --#define ENET_GMAC_STATUS 0x028 --#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003 --#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000 --#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001 --#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002 --#define ENET_GMAC_STATUS_HD 0x00000004 --#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008 --#define ENET_GMAC_STATUS_LINK_UP 0x00000010 --#define ENET_IRQ_STATUS 0x02c --#define ENET_IRQ_STATUS_OVFL 0x00000001 --#define ENET_OVERFLOW_COUNTER 0x030 --#define ENET_FLUSH 0x034 --#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001 --#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002 --#define ENET_RSV_SELECT 0x038 --#define ENET_BP_FORCE 0x03c --#define ENET_BP_FORCE_FORCE 0x00000001 --#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040 --#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f --#define ENET_TX_CRC_CTRL 0x044 --#define ENET_MIB 0x200 --#define ENET_UNIMAC 0x400 --#define ENET_DMA 0x800 --#define ENET_DMA_CONTROLLER_CFG 0x800 --#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001 --#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002 --#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004 --#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804 --#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808 --#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c --#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000 --#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810 --#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814 --#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818 --#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C --#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820 --#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824 --#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828 --#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C --#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830 --#define ENET_DMA_CTRL_CHANNEL_RESET 0x834 --#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838 --#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840 --#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844 --#define ENET_DMA_CH0_CFG 0xa00 /* RX */ --#define ENET_DMA_CH1_CFG 0xa10 /* TX */ --#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */ --#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */ -- --#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */ --#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */ --#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ --#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */ --#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */ --#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */ --#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */ --#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */ --#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */ --#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */ --#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */ --#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ --#define ENET_DMA_CH_CFG_SIZE 0x10 -- --#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */ --#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */ --#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */ --#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */ --#define ENET_DMA_CH_STATE_RAM_SIZE 0x10 -- --#define DMA_CTL_STATUS_APPEND_CRC 0x00000100 --#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200 --#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */ --#define DMA_CTL_STATUS_WRAP 0x00001000 /* */ --#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */ --#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */ --#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */ --#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000 --#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16 --#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000 --#define DMA_CTL_LEN_DESC_USEFPM 0x80000000 -- --#endif ---- /dev/null -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.h -@@ -0,0 +1,96 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+#ifndef __BCM4908_ENET_H -+#define __BCM4908_ENET_H -+ -+#define ENET_CONTROL 0x000 -+#define ENET_MIB_CTRL 0x004 -+#define ENET_MIB_CTRL_CLR_MIB 0x00000001 -+#define ENET_RX_ERR_MASK 0x008 -+#define ENET_MIB_MAX_PKT_SIZE 0x00C -+#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff -+#define ENET_DIAG_OUT 0x01c -+#define ENET_ENABLE_DROP_PKT 0x020 -+#define ENET_IRQ_ENABLE 0x024 -+#define ENET_IRQ_ENABLE_OVFL 0x00000001 -+#define ENET_GMAC_STATUS 0x028 -+#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003 -+#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000 -+#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001 -+#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002 -+#define ENET_GMAC_STATUS_HD 0x00000004 -+#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008 -+#define ENET_GMAC_STATUS_LINK_UP 0x00000010 -+#define ENET_IRQ_STATUS 0x02c -+#define ENET_IRQ_STATUS_OVFL 0x00000001 -+#define ENET_OVERFLOW_COUNTER 0x030 -+#define ENET_FLUSH 0x034 -+#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001 -+#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002 -+#define ENET_RSV_SELECT 0x038 -+#define ENET_BP_FORCE 0x03c -+#define ENET_BP_FORCE_FORCE 0x00000001 -+#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040 -+#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f -+#define ENET_TX_CRC_CTRL 0x044 -+#define ENET_MIB 0x200 -+#define ENET_UNIMAC 0x400 -+#define ENET_DMA 0x800 -+#define ENET_DMA_CONTROLLER_CFG 0x800 -+#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001 -+#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002 -+#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004 -+#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804 -+#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808 -+#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c -+#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000 -+#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810 -+#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814 -+#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818 -+#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C -+#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820 -+#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824 -+#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828 -+#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C -+#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830 -+#define ENET_DMA_CTRL_CHANNEL_RESET 0x834 -+#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838 -+#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840 -+#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844 -+#define ENET_DMA_CH0_CFG 0xa00 /* RX */ -+#define ENET_DMA_CH1_CFG 0xa10 /* TX */ -+#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */ -+#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */ -+ -+#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */ -+#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */ -+#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */ -+#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */ -+#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */ -+#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */ -+#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */ -+#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */ -+#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */ -+#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */ -+#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */ -+#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */ -+#define ENET_DMA_CH_CFG_SIZE 0x10 -+ -+#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */ -+#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */ -+#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */ -+#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */ -+#define ENET_DMA_CH_STATE_RAM_SIZE 0x10 -+ -+#define DMA_CTL_STATUS_APPEND_CRC 0x00000100 -+#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200 -+#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */ -+#define DMA_CTL_STATUS_WRAP 0x00001000 /* */ -+#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */ -+#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */ -+#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */ -+#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000 -+#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16 -+#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000 -+#define DMA_CTL_LEN_DESC_USEFPM 0x80000000 -+ -+#endif diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0004-net-broadcom-bcm4908_enet-drop-unneeded-memset.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0004-net-broadcom-bcm4908_enet-drop-unneeded-memset.patch deleted file mode 100644 index 561f045b75..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0004-net-broadcom-bcm4908_enet-drop-unneeded-memset.patch +++ /dev/null @@ -1,30 +0,0 @@ -From af263af64683f018be9ce3c309edfa9903f5109a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 13:12:35 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: drop unneeded memset() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -dma_alloc_coherent takes care of zeroing allocated memory - -Suggested-by: Andrew Lunn -Signed-off-by: Rafał Miłecki -Reviewed-by: Andrew Lunn -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -163,8 +163,6 @@ static int bcm4908_dma_alloc_buf_descs(s - if (!ring->slots) - goto err_free_buf_descs; - -- memset(ring->cpu_addr, 0, size); -- - ring->read_idx = 0; - ring->write_idx = 0; - diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0005-net-broadcom-bcm4908_enet-drop-inline-from-C-functio.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0005-net-broadcom-bcm4908_enet-drop-inline-from-C-functio.patch deleted file mode 100644 index a8c188f30d..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0005-net-broadcom-bcm4908_enet-drop-inline-from-C-functio.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 7b778ae4eb9cd6e1518e4e47902a104b13ae8929 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 13:12:36 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: drop "inline" from C functions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It seems preferred to let compiler optimize code if applicable. -While at it drop unused enet_umac_maskset(). - -Suggested-by: Andrew Lunn -Signed-off-by: Rafał Miłecki -Reviewed-by: Andrew Lunn -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 19 +++++++------------ - 1 file changed, 7 insertions(+), 12 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -75,17 +75,17 @@ struct bcm4908_enet { - * R/W ops - */ - --static inline u32 enet_read(struct bcm4908_enet *enet, u16 offset) -+static u32 enet_read(struct bcm4908_enet *enet, u16 offset) - { - return readl(enet->base + offset); - } - --static inline void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value) -+static void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value) - { - writel(value, enet->base + offset); - } - --static inline void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set) -+static void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set) - { - u32 val; - -@@ -96,27 +96,22 @@ static inline void enet_maskset(struct b - enet_write(enet, offset, val); - } - --static inline void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set) -+static void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set) - { - enet_maskset(enet, offset, set, set); - } - --static inline u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset) -+static u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset) - { - return enet_read(enet, ENET_UNIMAC + offset); - } - --static inline void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value) -+static void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value) - { - enet_write(enet, ENET_UNIMAC + offset, value); - } - --static inline void enet_umac_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set) --{ -- enet_maskset(enet, ENET_UNIMAC + offset, mask, set); --} -- --static inline void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set) -+static void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set) - { - enet_set(enet, ENET_UNIMAC + offset, set); - } diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0006-net-broadcom-bcm4908_enet-fix-minor-typos.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0006-net-broadcom-bcm4908_enet-fix-minor-typos.patch deleted file mode 100644 index 1aacb1c8cf..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0006-net-broadcom-bcm4908_enet-fix-minor-typos.patch +++ /dev/null @@ -1,60 +0,0 @@ -From e3948811720341f99cd5cb4a8a650473400ec4f8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 13:12:37 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: fix minor typos -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. Fix "ensable" typo noticed by Andrew -2. Fix chipset name in the struct net_device_ops variable - -Suggested-by: Andrew Lunn -Signed-off-by: Rafał Miłecki -Reviewed-by: Andrew Lunn -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -328,8 +328,8 @@ static int bcm4908_enet_dma_init(struct - return 0; - } - --static void bcm4908_enet_dma_tx_ring_ensable(struct bcm4908_enet *enet, -- struct bcm4908_enet_dma_ring *ring) -+static void bcm4908_enet_dma_tx_ring_enable(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) - { - enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE); - } -@@ -519,7 +519,7 @@ static int bcm4908_enet_start_xmit(struc - buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr); - buf_desc->ctl = cpu_to_le32(tmp); - -- bcm4908_enet_dma_tx_ring_ensable(enet, &enet->tx_ring); -+ bcm4908_enet_dma_tx_ring_enable(enet, &enet->tx_ring); - - if (++ring->write_idx == ring->length - 1) - ring->write_idx = 0; -@@ -583,7 +583,7 @@ static int bcm4908_enet_poll(struct napi - return handled; - } - --static const struct net_device_ops bcm96xx_netdev_ops = { -+static const struct net_device_ops bcm4908_enet_netdev_ops = { - .ndo_open = bcm4908_enet_open, - .ndo_stop = bcm4908_enet_stop, - .ndo_start_xmit = bcm4908_enet_start_xmit, -@@ -623,7 +623,7 @@ static int bcm4908_enet_probe(struct pla - - SET_NETDEV_DEV(netdev, &pdev->dev); - eth_hw_addr_random(netdev); -- netdev->netdev_ops = &bcm96xx_netdev_ops; -+ netdev->netdev_ops = &bcm4908_enet_netdev_ops; - netdev->min_mtu = ETH_ZLEN; - netdev->mtu = ENET_MTU_MAX; - netdev->max_mtu = ENET_MTU_MAX; diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0007-net-broadcom-bcm4908_enet-fix-received-skb-length.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0007-net-broadcom-bcm4908_enet-fix-received-skb-length.patch deleted file mode 100644 index 1b51979d71..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0007-net-broadcom-bcm4908_enet-fix-received-skb-length.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 195e2d9febfbeef1d09701c387925e5c2f5cb038 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 13:12:38 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: fix received skb length -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Use ETH_FCS_LEN instead of magic value and drop incorrect + 2 - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -567,7 +567,7 @@ static int bcm4908_enet_poll(struct napi - - dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE); - -- skb_put(slot.skb, len - 4 + 2); -+ skb_put(slot.skb, len - ETH_FCS_LEN); - slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev); - netif_receive_skb(slot.skb); - diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0008-net-broadcom-bcm4908_enet-fix-endianness-in-xmit-cod.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0008-net-broadcom-bcm4908_enet-fix-endianness-in-xmit-cod.patch deleted file mode 100644 index eda0bf482e..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0008-net-broadcom-bcm4908_enet-fix-endianness-in-xmit-cod.patch +++ /dev/null @@ -1,28 +0,0 @@ -From bdd70b997799099597fc0952fb0ec1bd80505bc4 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 13:12:39 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: fix endianness in xmit code -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Use le32_to_cpu() for reading __le32 struct field filled by hw. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -476,7 +476,7 @@ static int bcm4908_enet_start_xmit(struc - /* Free transmitted skbs */ - while (ring->read_idx != ring->write_idx) { - buf_desc = &ring->buf_desc[ring->read_idx]; -- if (buf_desc->ctl & DMA_CTL_STATUS_OWN) -+ if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN) - break; - slot = &ring->slots[ring->read_idx]; - diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0009-net-broadcom-bcm4908_enet-set-MTU-on-open-on-request.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0009-net-broadcom-bcm4908_enet-set-MTU-on-open-on-request.patch deleted file mode 100644 index 0201bfeda3..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0009-net-broadcom-bcm4908_enet-set-MTU-on-open-on-request.patch +++ /dev/null @@ -1,119 +0,0 @@ -From 14b3b46a67f78ade99eafcbf320105615e948569 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 12 Feb 2021 16:21:35 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: set MTU on open & on request -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Hardware comes up with default max frame size set to 1518. When using it -with switch it results in actual Ethernet MTU 1492: -1518 - 14 (Ethernet header) - 4 (Broadcom's tag) - 4 (802.1q) - 4 (FCS) - -Above means hardware in its default state can't handle standard Ethernet -traffic (MTU 1500). - -Define maximum possible Ethernet overhead and always set MAC max frame -length accordingly. This change fixes handling Ethernet frames of length -1506 - 1514. - -Signed-off-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 31 ++++++++++++++++---- - 1 file changed, 25 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -29,9 +30,10 @@ - ENET_DMA_CH_CFG_INT_BUFF_DONE) - #define ENET_DMA_MAX_BURST_LEN 8 /* in 64 bit words */ - --#define ENET_MTU_MIN 60 --#define ENET_MTU_MAX 1500 /* Is it possible to support 2044? */ --#define ENET_MTU_MAX_EXTRA_SIZE 32 /* L2 */ -+#define ENET_MTU_MAX ETH_DATA_LEN /* Is it possible to support 2044? */ -+#define BRCM_MAX_TAG_LEN 6 -+#define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \ -+ ETH_FCS_LEN + 4) /* 32 */ - - struct bcm4908_enet_dma_ring_bd { - __le32 ctl; -@@ -135,6 +137,11 @@ static void bcm4908_enet_intrs_ack(struc - enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS); - } - -+static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu) -+{ -+ enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD); -+} -+ - /*** - * DMA - */ -@@ -246,7 +253,7 @@ static int bcm4908_enet_dma_alloc_rx_buf - u32 tmp; - int err; - -- slot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE; -+ slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD; - - slot->skb = netdev_alloc_skb(enet->netdev, slot->len); - if (!slot->skb) -@@ -374,6 +381,8 @@ static void bcm4908_enet_gmac_init(struc - { - u32 cmd; - -+ bcm4908_enet_set_mtu(enet, enet->netdev->mtu); -+ - cmd = enet_umac_read(enet, UMAC_CMD); - enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET); - enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET); -@@ -559,7 +568,7 @@ static int bcm4908_enet_poll(struct napi - - len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; - -- if (len < ENET_MTU_MIN || -+ if (len < ETH_ZLEN || - (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) { - enet->netdev->stats.rx_dropped++; - break; -@@ -583,11 +592,21 @@ static int bcm4908_enet_poll(struct napi - return handled; - } - -+static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu) -+{ -+ struct bcm4908_enet *enet = netdev_priv(netdev); -+ -+ bcm4908_enet_set_mtu(enet, new_mtu); -+ -+ return 0; -+} -+ - static const struct net_device_ops bcm4908_enet_netdev_ops = { - .ndo_open = bcm4908_enet_open, - .ndo_stop = bcm4908_enet_stop, - .ndo_start_xmit = bcm4908_enet_start_xmit, - .ndo_set_mac_address = eth_mac_addr, -+ .ndo_change_mtu = bcm4908_enet_change_mtu, - }; - - static int bcm4908_enet_probe(struct platform_device *pdev) -@@ -625,7 +644,7 @@ static int bcm4908_enet_probe(struct pla - eth_hw_addr_random(netdev); - netdev->netdev_ops = &bcm4908_enet_netdev_ops; - netdev->min_mtu = ETH_ZLEN; -- netdev->mtu = ENET_MTU_MAX; -+ netdev->mtu = ETH_DATA_LEN; - netdev->max_mtu = ENET_MTU_MAX; - netif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64); - diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0010-net-broadcom-bcm4908_enet-fix-RX-path-possible-mem-l.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0010-net-broadcom-bcm4908_enet-fix-RX-path-possible-mem-l.patch deleted file mode 100644 index 8a24324122..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0010-net-broadcom-bcm4908_enet-fix-RX-path-possible-mem-l.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 4dc7f09b8becfa35a55430a49d95acf19f996e6b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 24 Feb 2021 16:18:41 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: fix RX path possible mem leak -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -After filling RX ring slot with new skb it's required to free old skb. -Immediately on error or later in the net subsystem. - -Fixes: 4feffeadbcb2 ("net: broadcom: bcm4908enet: add BCM4908 controller driver") -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20210224151842.2419-1-zajec5@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -570,6 +570,7 @@ static int bcm4908_enet_poll(struct napi - - if (len < ETH_ZLEN || - (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) { -+ kfree_skb(slot.skb); - enet->netdev->stats.rx_dropped++; - break; - } diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0011-net-broadcom-bcm4908_enet-fix-NAPI-poll-returned-val.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0011-net-broadcom-bcm4908_enet-fix-NAPI-poll-returned-val.patch deleted file mode 100644 index d4cf84e4b6..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0011-net-broadcom-bcm4908_enet-fix-NAPI-poll-returned-val.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 4d9274cee40b6a20dd6148c6c81c6733c2678cbc Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 24 Feb 2021 16:18:42 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: fix NAPI poll returned value -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Missing increment was resulting in poll function always returning 0 -instead of amount of processed packets. - -Fixes: 4feffeadbcb2 ("net: broadcom: bcm4908enet: add BCM4908 controller driver") -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20210224151842.2419-2-zajec5@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -583,6 +583,8 @@ static int bcm4908_enet_poll(struct napi - - enet->netdev->stats.rx_packets++; - enet->netdev->stats.rx_bytes += len; -+ -+ handled++; - } - - if (handled < weight) { diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0012-net-broadcom-bcm4908_enet-enable-RX-after-processing.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0012-net-broadcom-bcm4908_enet-enable-RX-after-processing.patch deleted file mode 100644 index ad1bebf3ec..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0012-net-broadcom-bcm4908_enet-enable-RX-after-processing.patch +++ /dev/null @@ -1,34 +0,0 @@ -From d313d16bbaea0f11a2e98f04a6c678b43c208915 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 26 Feb 2021 14:20:38 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: enable RX after processing - packets -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -When receiving a lot of packets hardware may run out of free -descriptiors and stop RX ring. Enable it every time after handling -received packets. - -Fixes: 4feffeadbcb2 ("net: broadcom: bcm4908enet: add BCM4908 controller driver") -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20210226132038.29849-1-zajec5@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -592,6 +592,9 @@ static int bcm4908_enet_poll(struct napi - bcm4908_enet_intrs_on(enet); - } - -+ /* Hardware could disable ring if it run out of descriptors */ -+ bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring); -+ - return handled; - } - diff --git a/target/linux/bcm4908/patches-5.10/073-v5.12-0013-net-broadcom-BCM4908_ENET-should-not-default-to-y-un.patch b/target/linux/bcm4908/patches-5.10/073-v5.12-0013-net-broadcom-BCM4908_ENET-should-not-default-to-y-un.patch deleted file mode 100644 index 43e5ee01bf..0000000000 --- a/target/linux/bcm4908/patches-5.10/073-v5.12-0013-net-broadcom-BCM4908_ENET-should-not-default-to-y-un.patch +++ /dev/null @@ -1,33 +0,0 @@ -From a3bc483216650a7232559bf0a1debfbabff3e12c Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Tue, 16 Mar 2021 15:03:41 +0100 -Subject: [PATCH] net: broadcom: BCM4908_ENET should not default to y, - unconditionally -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Merely enabling compile-testing should not enable additional code. -To fix this, restrict the automatic enabling of BCM4908_ENET to -ARCH_BCM4908. - -Fixes: 4feffeadbcb2e5b1 ("net: broadcom: bcm4908enet: add BCM4908 controller driver") -Signed-off-by: Geert Uytterhoeven -Acked-by: Florian Fainelli -Acked-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/broadcom/Kconfig -+++ b/drivers/net/ethernet/broadcom/Kconfig -@@ -54,7 +54,7 @@ config B44_PCI - config BCM4908_ENET - tristate "Broadcom BCM4908 internal mac support" - depends on ARCH_BCM4908 || COMPILE_TEST -- default y -+ default y if ARCH_BCM4908 - help - This driver supports Ethernet controller integrated into Broadcom - BCM4908 family SoCs. diff --git a/target/linux/bcm4908/patches-5.10/074-v5.13-0001-net-broadcom-bcm4908_enet-read-MAC-from-OF.patch b/target/linux/bcm4908/patches-5.10/074-v5.13-0001-net-broadcom-bcm4908_enet-read-MAC-from-OF.patch deleted file mode 100644 index c4f336e671..0000000000 --- a/target/linux/bcm4908/patches-5.10/074-v5.13-0001-net-broadcom-bcm4908_enet-read-MAC-from-OF.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 3559c1ea4336636c886002996d50805365d3055c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 10 Mar 2021 09:48:13 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: read MAC from OF -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 devices have MAC address accessible using NVMEM so it's needed -to use OF helper for reading it. - -Signed-off-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -647,7 +648,9 @@ static int bcm4908_enet_probe(struct pla - return err; - - SET_NETDEV_DEV(netdev, &pdev->dev); -- eth_hw_addr_random(netdev); -+ of_get_mac_address(dev->of_node, netdev->dev_addr); -+ if (!is_valid_ether_addr(netdev->dev_addr)) -+ eth_hw_addr_random(netdev); - netdev->netdev_ops = &bcm4908_enet_netdev_ops; - netdev->min_mtu = ETH_ZLEN; - netdev->mtu = ETH_DATA_LEN; diff --git a/target/linux/bcm4908/patches-5.10/074-v5.13-0002-dt-bindings-net-bcm4908-enet-add-optional-TX-interru.patch b/target/linux/bcm4908/patches-5.10/074-v5.13-0002-dt-bindings-net-bcm4908-enet-add-optional-TX-interru.patch deleted file mode 100644 index b61437a2de..0000000000 --- a/target/linux/bcm4908/patches-5.10/074-v5.13-0002-dt-bindings-net-bcm4908-enet-add-optional-TX-interru.patch +++ /dev/null @@ -1,50 +0,0 @@ -From ab4dda7a8cb7e55ea3d92fd5e249cf6f5396028c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Mar 2021 13:35:20 +0100 -Subject: [PATCH] dt-bindings: net: bcm4908-enet: add optional TX interrupt -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -I discovered that hardware actually supports two interrupts, one per DMA -channel (RX and TX). - -Signed-off-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - .../bindings/net/brcm,bcm4908-enet.yaml | 17 +++++++++++++---- - 1 file changed, 13 insertions(+), 4 deletions(-) - ---- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml -+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml -@@ -22,10 +22,18 @@ properties: - maxItems: 1 - - interrupts: -- description: RX interrupt -+ minItems: 1 -+ maxItems: 2 -+ items: -+ - description: RX interrupt -+ - description: TX interrupt - - interrupt-names: -- const: rx -+ minItems: 1 -+ maxItems: 2 -+ items: -+ - const: rx -+ - const: tx - - required: - - reg -@@ -43,6 +51,7 @@ examples: - compatible = "brcm,bcm4908-enet"; - reg = <0x80002000 0x1000>; - -- interrupts = ; -- interrupt-names = "rx"; -+ interrupts = , -+ ; -+ interrupt-names = "rx", "tx"; - }; diff --git a/target/linux/bcm4908/patches-5.10/074-v5.13-0003-net-broadcom-bcm4908_enet-support-TX-interrupt.patch b/target/linux/bcm4908/patches-5.10/074-v5.13-0003-net-broadcom-bcm4908_enet-support-TX-interrupt.patch deleted file mode 100644 index 03ac4b07bf..0000000000 --- a/target/linux/bcm4908/patches-5.10/074-v5.13-0003-net-broadcom-bcm4908_enet-support-TX-interrupt.patch +++ /dev/null @@ -1,300 +0,0 @@ -From 12bb508bfe5a564c36864b12253db23cac83bfa1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Mar 2021 13:35:21 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: support TX interrupt -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It appears that each DMA channel has its own interrupt and both rings -can be configured (the same way) to handle interrupts. - -1. Make ring interrupts code generic (make it operate on given ring) -2. Move napi to ring (so each has its own) -3. Make IRQ handler generic (match ring against received IRQ number) -4. Add (optional) support for TX interrupt - -Signed-off-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 138 ++++++++++++++----- - 1 file changed, 103 insertions(+), 35 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -54,6 +54,7 @@ struct bcm4908_enet_dma_ring { - int length; - u16 cfg_block; - u16 st_ram_block; -+ struct napi_struct napi; - - union { - void *cpu_addr; -@@ -67,8 +68,8 @@ struct bcm4908_enet_dma_ring { - struct bcm4908_enet { - struct device *dev; - struct net_device *netdev; -- struct napi_struct napi; - void __iomem *base; -+ int irq_tx; - - struct bcm4908_enet_dma_ring tx_ring; - struct bcm4908_enet_dma_ring rx_ring; -@@ -123,24 +124,31 @@ static void enet_umac_set(struct bcm4908 - * Helpers - */ - --static void bcm4908_enet_intrs_on(struct bcm4908_enet *enet) -+static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu) - { -- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS); -+ enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD); - } - --static void bcm4908_enet_intrs_off(struct bcm4908_enet *enet) -+/*** -+ * DMA ring ops -+ */ -+ -+static void bcm4908_enet_dma_ring_intrs_on(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) - { -- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0); -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS); - } - --static void bcm4908_enet_intrs_ack(struct bcm4908_enet *enet) -+static void bcm4908_enet_dma_ring_intrs_off(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) - { -- enet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS); -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0); - } - --static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu) -+static void bcm4908_enet_dma_ring_intrs_ack(struct bcm4908_enet *enet, -+ struct bcm4908_enet_dma_ring *ring) - { -- enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD); -+ enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS); - } - - /*** -@@ -414,11 +422,14 @@ static void bcm4908_enet_gmac_init(struc - static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id) - { - struct bcm4908_enet *enet = dev_id; -+ struct bcm4908_enet_dma_ring *ring; - -- bcm4908_enet_intrs_off(enet); -- bcm4908_enet_intrs_ack(enet); -+ ring = (irq == enet->irq_tx) ? &enet->tx_ring : &enet->rx_ring; - -- napi_schedule(&enet->napi); -+ bcm4908_enet_dma_ring_intrs_off(enet, ring); -+ bcm4908_enet_dma_ring_intrs_ack(enet, ring); -+ -+ napi_schedule(&ring->napi); - - return IRQ_HANDLED; - } -@@ -426,6 +437,8 @@ static irqreturn_t bcm4908_enet_irq_hand - static int bcm4908_enet_open(struct net_device *netdev) - { - struct bcm4908_enet *enet = netdev_priv(netdev); -+ struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; -+ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; - struct device *dev = enet->dev; - int err; - -@@ -435,6 +448,17 @@ static int bcm4908_enet_open(struct net_ - return err; - } - -+ if (enet->irq_tx > 0) { -+ err = request_irq(enet->irq_tx, bcm4908_enet_irq_handler, 0, -+ "tx", enet); -+ if (err) { -+ dev_err(dev, "Failed to request IRQ %d: %d\n", -+ enet->irq_tx, err); -+ free_irq(netdev->irq, enet); -+ return err; -+ } -+ } -+ - bcm4908_enet_gmac_init(enet); - bcm4908_enet_dma_reset(enet); - bcm4908_enet_dma_init(enet); -@@ -443,14 +467,19 @@ static int bcm4908_enet_open(struct net_ - - enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN); - enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0); -- bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring); - -- napi_enable(&enet->napi); -+ if (enet->irq_tx > 0) { -+ napi_enable(&tx_ring->napi); -+ bcm4908_enet_dma_ring_intrs_ack(enet, tx_ring); -+ bcm4908_enet_dma_ring_intrs_on(enet, tx_ring); -+ } -+ -+ bcm4908_enet_dma_rx_ring_enable(enet, rx_ring); -+ napi_enable(&rx_ring->napi); - netif_carrier_on(netdev); - netif_start_queue(netdev); -- -- bcm4908_enet_intrs_ack(enet); -- bcm4908_enet_intrs_on(enet); -+ bcm4908_enet_dma_ring_intrs_ack(enet, rx_ring); -+ bcm4908_enet_dma_ring_intrs_on(enet, rx_ring); - - return 0; - } -@@ -458,16 +487,20 @@ static int bcm4908_enet_open(struct net_ - static int bcm4908_enet_stop(struct net_device *netdev) - { - struct bcm4908_enet *enet = netdev_priv(netdev); -+ struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring; -+ struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring; - - netif_stop_queue(netdev); - netif_carrier_off(netdev); -- napi_disable(&enet->napi); -+ napi_disable(&rx_ring->napi); -+ napi_disable(&tx_ring->napi); - - bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring); - bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring); - - bcm4908_enet_dma_uninit(enet); - -+ free_irq(enet->irq_tx, enet); - free_irq(enet->netdev->irq, enet); - - return 0; -@@ -484,25 +517,19 @@ static int bcm4908_enet_start_xmit(struc - u32 tmp; - - /* Free transmitted skbs */ -- while (ring->read_idx != ring->write_idx) { -- buf_desc = &ring->buf_desc[ring->read_idx]; -- if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN) -- break; -- slot = &ring->slots[ring->read_idx]; -- -- dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); -- dev_kfree_skb(slot->skb); -- if (++ring->read_idx == ring->length) -- ring->read_idx = 0; -- } -+ if (enet->irq_tx < 0 && -+ !(le32_to_cpu(ring->buf_desc[ring->read_idx].ctl) & DMA_CTL_STATUS_OWN)) -+ napi_schedule(&enet->tx_ring.napi); - - /* Don't use the last empty buf descriptor */ - if (ring->read_idx <= ring->write_idx) - free_buf_descs = ring->read_idx - ring->write_idx + ring->length; - else - free_buf_descs = ring->read_idx - ring->write_idx; -- if (free_buf_descs < 2) -+ if (free_buf_descs < 2) { -+ netif_stop_queue(netdev); - return NETDEV_TX_BUSY; -+ } - - /* Hardware removes OWN bit after sending data */ - buf_desc = &ring->buf_desc[ring->write_idx]; -@@ -539,9 +566,10 @@ static int bcm4908_enet_start_xmit(struc - return NETDEV_TX_OK; - } - --static int bcm4908_enet_poll(struct napi_struct *napi, int weight) -+static int bcm4908_enet_poll_rx(struct napi_struct *napi, int weight) - { -- struct bcm4908_enet *enet = container_of(napi, struct bcm4908_enet, napi); -+ struct bcm4908_enet_dma_ring *rx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi); -+ struct bcm4908_enet *enet = container_of(rx_ring, struct bcm4908_enet, rx_ring); - struct device *dev = enet->dev; - int handled = 0; - -@@ -590,7 +618,7 @@ static int bcm4908_enet_poll(struct napi - - if (handled < weight) { - napi_complete_done(napi, handled); -- bcm4908_enet_intrs_on(enet); -+ bcm4908_enet_dma_ring_intrs_on(enet, rx_ring); - } - - /* Hardware could disable ring if it run out of descriptors */ -@@ -599,6 +627,42 @@ static int bcm4908_enet_poll(struct napi - return handled; - } - -+static int bcm4908_enet_poll_tx(struct napi_struct *napi, int weight) -+{ -+ struct bcm4908_enet_dma_ring *tx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi); -+ struct bcm4908_enet *enet = container_of(tx_ring, struct bcm4908_enet, tx_ring); -+ struct bcm4908_enet_dma_ring_bd *buf_desc; -+ struct bcm4908_enet_dma_ring_slot *slot; -+ struct device *dev = enet->dev; -+ unsigned int bytes = 0; -+ int handled = 0; -+ -+ while (handled < weight && tx_ring->read_idx != tx_ring->write_idx) { -+ buf_desc = &tx_ring->buf_desc[tx_ring->read_idx]; -+ if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN) -+ break; -+ slot = &tx_ring->slots[tx_ring->read_idx]; -+ -+ dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); -+ dev_kfree_skb(slot->skb); -+ bytes += slot->len; -+ if (++tx_ring->read_idx == tx_ring->length) -+ tx_ring->read_idx = 0; -+ -+ handled++; -+ } -+ -+ if (handled < weight) { -+ napi_complete_done(napi, handled); -+ bcm4908_enet_dma_ring_intrs_on(enet, tx_ring); -+ } -+ -+ if (netif_queue_stopped(enet->netdev)) -+ netif_wake_queue(enet->netdev); -+ -+ return handled; -+} -+ - static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu) - { - struct bcm4908_enet *enet = netdev_priv(netdev); -@@ -641,6 +705,8 @@ static int bcm4908_enet_probe(struct pla - if (netdev->irq < 0) - return netdev->irq; - -+ enet->irq_tx = platform_get_irq_byname(pdev, "tx"); -+ - dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); - - err = bcm4908_enet_dma_alloc(enet); -@@ -655,7 +721,8 @@ static int bcm4908_enet_probe(struct pla - netdev->min_mtu = ETH_ZLEN; - netdev->mtu = ETH_DATA_LEN; - netdev->max_mtu = ENET_MTU_MAX; -- netif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64); -+ netif_tx_napi_add(netdev, &enet->tx_ring.napi, bcm4908_enet_poll_tx, NAPI_POLL_WEIGHT); -+ netif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT); - - err = register_netdev(netdev); - if (err) { -@@ -673,7 +740,8 @@ static int bcm4908_enet_remove(struct pl - struct bcm4908_enet *enet = platform_get_drvdata(pdev); - - unregister_netdev(enet->netdev); -- netif_napi_del(&enet->napi); -+ netif_napi_del(&enet->rx_ring.napi); -+ netif_napi_del(&enet->tx_ring.napi); - bcm4908_enet_dma_free(enet); - - return 0; diff --git a/target/linux/bcm4908/patches-5.10/075-v5.13-0001-net-dsa-bcm_sf2-store-PHY-interface-mode-in-port-str.patch b/target/linux/bcm4908/patches-5.10/075-v5.13-0001-net-dsa-bcm_sf2-store-PHY-interface-mode-in-port-str.patch deleted file mode 100644 index 9b3a831773..0000000000 --- a/target/linux/bcm4908/patches-5.10/075-v5.13-0001-net-dsa-bcm_sf2-store-PHY-interface-mode-in-port-str.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 01488a0ccd9abe15565bed50a45afcddbb0fe199 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 12 Mar 2021 11:41:07 +0100 -Subject: [PATCH] net: dsa: bcm_sf2: store PHY interface/mode in port structure -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's needed later for proper switch / crossbar setup. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/bcm_sf2.c | 16 ++++++++++++---- - drivers/net/dsa/bcm_sf2.h | 1 + - 2 files changed, 13 insertions(+), 4 deletions(-) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -446,10 +446,11 @@ static void bcm_sf2_intr_disable(struct - static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, - struct device_node *dn) - { -+ struct device *dev = priv->dev->ds->dev; -+ struct bcm_sf2_port_status *port_st; - struct device_node *port; - unsigned int port_num; - struct property *prop; -- phy_interface_t mode; - int err; - - priv->moca_port = -1; -@@ -458,19 +459,26 @@ static void bcm_sf2_identify_ports(struc - if (of_property_read_u32(port, "reg", &port_num)) - continue; - -+ if (port_num >= DSA_MAX_PORTS) { -+ dev_err(dev, "Invalid port number %d\n", port_num); -+ continue; -+ } -+ -+ port_st = &priv->port_sts[port_num]; -+ - /* Internal PHYs get assigned a specific 'phy-mode' property - * value: "internal" to help flag them before MDIO probing - * has completed, since they might be turned off at that - * time - */ -- err = of_get_phy_mode(port, &mode); -+ err = of_get_phy_mode(port, &port_st->mode); - if (err) - continue; - -- if (mode == PHY_INTERFACE_MODE_INTERNAL) -+ if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL) - priv->int_phy_mask |= 1 << port_num; - -- if (mode == PHY_INTERFACE_MODE_MOCA) -+ if (port_st->mode == PHY_INTERFACE_MODE_MOCA) - priv->moca_port = port_num; - - if (of_property_read_bool(port, "brcm,use-bcm-hdr")) ---- a/drivers/net/dsa/bcm_sf2.h -+++ b/drivers/net/dsa/bcm_sf2.h -@@ -44,6 +44,7 @@ struct bcm_sf2_hw_params { - #define BCM_SF2_REGS_NUM 6 - - struct bcm_sf2_port_status { -+ phy_interface_t mode; - unsigned int link; - bool enabled; - }; diff --git a/target/linux/bcm4908/patches-5.10/075-v5.13-0002-net-dsa-bcm_sf2-setup-BCM4908-internal-crossbar.patch b/target/linux/bcm4908/patches-5.10/075-v5.13-0002-net-dsa-bcm_sf2-setup-BCM4908-internal-crossbar.patch deleted file mode 100644 index 8230648301..0000000000 --- a/target/linux/bcm4908/patches-5.10/075-v5.13-0002-net-dsa-bcm_sf2-setup-BCM4908-internal-crossbar.patch +++ /dev/null @@ -1,152 +0,0 @@ -From a9349f08ec6c1251d41ef167d27a15cc39bc5b97 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 12 Mar 2021 11:41:08 +0100 -Subject: [PATCH] net: dsa: bcm_sf2: setup BCM4908 internal crossbar -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -On some SoCs (e.g. BCM4908, BCM631[345]8) SF2 has an integrated -crossbar. It allows connecting its selected external ports to internal -ports. It's used by vendors to handle custom Ethernet setups. - -BCM4908 has following 3x2 crossbar. On Asus GT-AC5300 rgmii is used for -connecting external BCM53134S switch. GPHY4 is usually used for WAN -port. More fancy devices use SerDes for 2.5 Gbps Ethernet. - - ┌──────────┐ -SerDes ─── 0 ─┤ │ - │ 3x2 ├─ 0 ─── switch port 7 - GPHY4 ─── 1 ─┤ │ - │ crossbar ├─ 1 ─── runner (accelerator) - rgmii ─── 2 ─┤ │ - └──────────┘ - -Use setup data based on DT info to configure BCM4908's switch port 7. -Right now only GPHY and rgmii variants are supported. Handling SerDes -can be implemented later. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/bcm_sf2.c | 45 ++++++++++++++++++++++++++++++++++ - drivers/net/dsa/bcm_sf2.h | 1 + - drivers/net/dsa/bcm_sf2_regs.h | 7 ++++++ - 3 files changed, 53 insertions(+) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -435,6 +435,44 @@ static int bcm_sf2_sw_rst(struct bcm_sf2 - return 0; - } - -+static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv) -+{ -+ struct device *dev = priv->dev->ds->dev; -+ int shift; -+ u32 mask; -+ u32 reg; -+ int i; -+ -+ mask = BIT(priv->num_crossbar_int_ports) - 1; -+ -+ reg = reg_readl(priv, REG_CROSSBAR); -+ switch (priv->type) { -+ case BCM4908_DEVICE_ID: -+ shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports; -+ reg &= ~(mask << shift); -+ if (0) /* FIXME */ -+ reg |= CROSSBAR_BCM4908_EXT_SERDES << shift; -+ else if (priv->int_phy_mask & BIT(7)) -+ reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift; -+ else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode)) -+ reg |= CROSSBAR_BCM4908_EXT_RGMII << shift; -+ else if (WARN(1, "Invalid port mode\n")) -+ return; -+ break; -+ default: -+ return; -+ } -+ reg_writel(priv, reg, REG_CROSSBAR); -+ -+ reg = reg_readl(priv, REG_CROSSBAR); -+ for (i = 0; i < priv->num_crossbar_int_ports; i++) { -+ shift = i * priv->num_crossbar_int_ports; -+ -+ dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i, -+ (reg >> shift) & mask); -+ } -+} -+ - static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) - { - intrl2_0_mask_set(priv, 0xffffffff); -@@ -880,6 +918,8 @@ static int bcm_sf2_sw_resume(struct dsa_ - return ret; - } - -+ bcm_sf2_crossbar_setup(priv); -+ - ret = bcm_sf2_cfp_resume(ds); - if (ret) - return ret; -@@ -1151,6 +1191,7 @@ struct bcm_sf2_of_data { - const u16 *reg_offsets; - unsigned int core_reg_align; - unsigned int num_cfp_rules; -+ unsigned int num_crossbar_int_ports; - }; - - static const u16 bcm_sf2_4908_reg_offsets[] = { -@@ -1175,6 +1216,7 @@ static const struct bcm_sf2_of_data bcm_ - .core_reg_align = 0, - .reg_offsets = bcm_sf2_4908_reg_offsets, - .num_cfp_rules = 0, /* FIXME */ -+ .num_crossbar_int_ports = 2, - }; - - /* Register offsets for the SWITCH_REG_* block */ -@@ -1285,6 +1327,7 @@ static int bcm_sf2_sw_probe(struct platf - priv->reg_offsets = data->reg_offsets; - priv->core_reg_align = data->core_reg_align; - priv->num_cfp_rules = data->num_cfp_rules; -+ priv->num_crossbar_int_ports = data->num_crossbar_int_ports; - - priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev, - "switch"); -@@ -1358,6 +1401,8 @@ static int bcm_sf2_sw_probe(struct platf - goto out_clk_mdiv; - } - -+ bcm_sf2_crossbar_setup(priv); -+ - bcm_sf2_gphy_enable_set(priv->dev->ds, true); - - ret = bcm_sf2_mdio_register(ds); ---- a/drivers/net/dsa/bcm_sf2.h -+++ b/drivers/net/dsa/bcm_sf2.h -@@ -74,6 +74,7 @@ struct bcm_sf2_priv { - const u16 *reg_offsets; - unsigned int core_reg_align; - unsigned int num_cfp_rules; -+ unsigned int num_crossbar_int_ports; - - /* spinlock protecting access to the indirect registers */ - spinlock_t indir_lock; ---- a/drivers/net/dsa/bcm_sf2_regs.h -+++ b/drivers/net/dsa/bcm_sf2_regs.h -@@ -48,6 +48,13 @@ enum bcm_sf2_reg_offs { - #define PHY_PHYAD_SHIFT 8 - #define PHY_PHYAD_MASK 0x1F - -+/* Relative to REG_CROSSBAR */ -+#define CROSSBAR_BCM4908_INT_P7 0 -+#define CROSSBAR_BCM4908_INT_RUNNER 1 -+#define CROSSBAR_BCM4908_EXT_SERDES 0 -+#define CROSSBAR_BCM4908_EXT_GPHY4 1 -+#define CROSSBAR_BCM4908_EXT_RGMII 2 -+ - #define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x)) - - /* Relative to REG_RGMII_CNTRL */ diff --git a/target/linux/bcm4908/patches-5.10/075-v5.13-0003-net-dsa-bcm_sf2-Fill-in-BCM4908-CFP-entries.patch b/target/linux/bcm4908/patches-5.10/075-v5.13-0003-net-dsa-bcm_sf2-Fill-in-BCM4908-CFP-entries.patch deleted file mode 100644 index dc8479b479..0000000000 --- a/target/linux/bcm4908/patches-5.10/075-v5.13-0003-net-dsa-bcm_sf2-Fill-in-BCM4908-CFP-entries.patch +++ /dev/null @@ -1,25 +0,0 @@ -From f4e6d7cdbfae502788bc468295b232dec76ee57e Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Fri, 12 Mar 2021 13:11:01 -0800 -Subject: [PATCH] net: dsa: bcm_sf2: Fill in BCM4908 CFP entries - -The BCM4908 switch has 256 CFP entrie, update that setting so CFP can be -used. - -Signed-off-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/bcm_sf2.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -1215,7 +1215,7 @@ static const struct bcm_sf2_of_data bcm_ - .type = BCM4908_DEVICE_ID, - .core_reg_align = 0, - .reg_offsets = bcm_sf2_4908_reg_offsets, -- .num_cfp_rules = 0, /* FIXME */ -+ .num_cfp_rules = 256, - .num_crossbar_int_ports = 2, - }; - diff --git a/target/linux/bcm4908/patches-5.10/075-v5.13-0004-net-dsa-bcm_sf2-add-function-finding-RGMII-register.patch b/target/linux/bcm4908/patches-5.10/075-v5.13-0004-net-dsa-bcm_sf2-add-function-finding-RGMII-register.patch deleted file mode 100644 index 281a8bbcda..0000000000 --- a/target/linux/bcm4908/patches-5.10/075-v5.13-0004-net-dsa-bcm_sf2-add-function-finding-RGMII-register.patch +++ /dev/null @@ -1,161 +0,0 @@ -From 55cfeb396965c3906a84d09a9c487d065e37773b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 18 Mar 2021 09:01:42 +0100 -Subject: [PATCH 1/2] net: dsa: bcm_sf2: add function finding RGMII register -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Simple macro like REG_RGMII_CNTRL_P() is insufficient as: -1. It doesn't validate port argument -2. It doesn't support chipsets with non-lineral RGMII regs layout - -Missing port validation could result in getting register offset from out -of array. Random memory -> random offset -> random reads/writes. It -affected e.g. BCM4908 for REG_RGMII_CNTRL_P(7). - -Fixes: a78e86ed586d ("net: dsa: bcm_sf2: Prepare for different register layouts") -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/bcm_sf2.c | 49 +++++++++++++++++++++++++++++----- - drivers/net/dsa/bcm_sf2_regs.h | 2 -- - 2 files changed, 42 insertions(+), 9 deletions(-) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -75,6 +75,31 @@ static void bcm_sf2_recalc_clock(struct - clk_set_rate(priv->clk_mdiv, new_rate); - } - -+static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port) -+{ -+ switch (priv->type) { -+ case BCM4908_DEVICE_ID: -+ /* TODO */ -+ break; -+ default: -+ switch (port) { -+ case 0: -+ return REG_RGMII_0_CNTRL; -+ case 1: -+ return REG_RGMII_1_CNTRL; -+ case 2: -+ return REG_RGMII_2_CNTRL; -+ default: -+ break; -+ } -+ } -+ -+ WARN_ONCE(1, "Unsupported port %d\n", port); -+ -+ /* RO fallback reg */ -+ return REG_SWITCH_STATUS; -+} -+ - static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) - { - struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); -@@ -696,6 +721,7 @@ static void bcm_sf2_sw_mac_config(struct - { - struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); - u32 id_mode_dis = 0, port_mode; -+ u32 reg_rgmii_ctrl; - u32 reg; - - if (port == core_readl(priv, CORE_IMP0_PRT_ID)) -@@ -719,10 +745,12 @@ static void bcm_sf2_sw_mac_config(struct - return; - } - -+ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); -+ - /* Clear id_mode_dis bit, and the existing port mode, let - * RGMII_MODE_EN bet set by mac_link_{up,down} - */ -- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); -+ reg = reg_readl(priv, reg_rgmii_ctrl); - reg &= ~ID_MODE_DIS; - reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); - -@@ -730,13 +758,14 @@ static void bcm_sf2_sw_mac_config(struct - if (id_mode_dis) - reg |= ID_MODE_DIS; - -- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); -+ reg_writel(priv, reg, reg_rgmii_ctrl); - } - - static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port, - phy_interface_t interface, bool link) - { - struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); -+ u32 reg_rgmii_ctrl; - u32 reg; - - if (!phy_interface_mode_is_rgmii(interface) && -@@ -744,13 +773,15 @@ static void bcm_sf2_sw_mac_link_set(stru - interface != PHY_INTERFACE_MODE_REVMII) - return; - -+ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); -+ - /* If the link is down, just disable the interface to conserve power */ -- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); -+ reg = reg_readl(priv, reg_rgmii_ctrl); - if (link) - reg |= RGMII_MODE_EN; - else - reg &= ~RGMII_MODE_EN; -- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); -+ reg_writel(priv, reg, reg_rgmii_ctrl); - } - - static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port, -@@ -787,11 +818,15 @@ static void bcm_sf2_sw_mac_link_up(struc - { - struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); - struct ethtool_eee *p = &priv->dev->ports[port].eee; -- u32 reg, offset; - - bcm_sf2_sw_mac_link_set(ds, port, interface, true); - - if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { -+ u32 reg_rgmii_ctrl; -+ u32 reg, offset; -+ -+ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); -+ - if (priv->type == BCM4908_DEVICE_ID || - priv->type == BCM7445_DEVICE_ID) - offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); -@@ -802,7 +837,7 @@ static void bcm_sf2_sw_mac_link_up(struc - interface == PHY_INTERFACE_MODE_RGMII_TXID || - interface == PHY_INTERFACE_MODE_MII || - interface == PHY_INTERFACE_MODE_REVMII) { -- reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); -+ reg = reg_readl(priv, reg_rgmii_ctrl); - reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); - - if (tx_pause) -@@ -810,7 +845,7 @@ static void bcm_sf2_sw_mac_link_up(struc - if (rx_pause) - reg |= RX_PAUSE_EN; - -- reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); -+ reg_writel(priv, reg, reg_rgmii_ctrl); - } - - reg = SW_OVERRIDE | LINK_STS; ---- a/drivers/net/dsa/bcm_sf2_regs.h -+++ b/drivers/net/dsa/bcm_sf2_regs.h -@@ -55,8 +55,6 @@ enum bcm_sf2_reg_offs { - #define CROSSBAR_BCM4908_EXT_GPHY4 1 - #define CROSSBAR_BCM4908_EXT_RGMII 2 - --#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x)) -- - /* Relative to REG_RGMII_CNTRL */ - #define RGMII_MODE_EN (1 << 0) - #define ID_MODE_DIS (1 << 1) diff --git a/target/linux/bcm4908/patches-5.10/075-v5.13-0005-net-dsa-bcm_sf2-fix-BCM4908-RGMII-reg-s.patch b/target/linux/bcm4908/patches-5.10/075-v5.13-0005-net-dsa-bcm_sf2-fix-BCM4908-RGMII-reg-s.patch deleted file mode 100644 index cf1c36c527..0000000000 --- a/target/linux/bcm4908/patches-5.10/075-v5.13-0005-net-dsa-bcm_sf2-fix-BCM4908-RGMII-reg-s.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 6859d91549341c2ad769d482de58129f080c0f04 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 18 Mar 2021 09:01:43 +0100 -Subject: [PATCH 2/2] net: dsa: bcm_sf2: fix BCM4908 RGMII reg(s) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 has only 1 RGMII reg for controlling port 7. - -Fixes: 73b7a6047971 ("net: dsa: bcm_sf2: support BCM4908's integrated switch") -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/bcm_sf2.c | 11 +++++++---- - drivers/net/dsa/bcm_sf2_regs.h | 1 + - 2 files changed, 8 insertions(+), 4 deletions(-) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -79,7 +79,12 @@ static u16 bcm_sf2_reg_rgmii_cntrl(struc - { - switch (priv->type) { - case BCM4908_DEVICE_ID: -- /* TODO */ -+ switch (port) { -+ case 7: -+ return REG_RGMII_11_CNTRL; -+ default: -+ break; -+ } - break; - default: - switch (port) { -@@ -1238,9 +1243,7 @@ static const u16 bcm_sf2_4908_reg_offset - [REG_PHY_REVISION] = 0x14, - [REG_SPHY_CNTRL] = 0x24, - [REG_CROSSBAR] = 0xc8, -- [REG_RGMII_0_CNTRL] = 0xe0, -- [REG_RGMII_1_CNTRL] = 0xec, -- [REG_RGMII_2_CNTRL] = 0xf8, -+ [REG_RGMII_11_CNTRL] = 0x014c, - [REG_LED_0_CNTRL] = 0x40, - [REG_LED_1_CNTRL] = 0x4c, - [REG_LED_2_CNTRL] = 0x58, ---- a/drivers/net/dsa/bcm_sf2_regs.h -+++ b/drivers/net/dsa/bcm_sf2_regs.h -@@ -21,6 +21,7 @@ enum bcm_sf2_reg_offs { - REG_RGMII_0_CNTRL, - REG_RGMII_1_CNTRL, - REG_RGMII_2_CNTRL, -+ REG_RGMII_11_CNTRL, - REG_LED_0_CNTRL, - REG_LED_1_CNTRL, - REG_LED_2_CNTRL, diff --git a/target/linux/bcm4908/patches-5.10/075-v5.13-0006-net-dsa-bcm_sf2-Fix-bcm_sf2_reg_rgmii_cntrl-call-for.patch b/target/linux/bcm4908/patches-5.10/075-v5.13-0006-net-dsa-bcm_sf2-Fix-bcm_sf2_reg_rgmii_cntrl-call-for.patch deleted file mode 100644 index f7e9bcb5a2..0000000000 --- a/target/linux/bcm4908/patches-5.10/075-v5.13-0006-net-dsa-bcm_sf2-Fix-bcm_sf2_reg_rgmii_cntrl-call-for.patch +++ /dev/null @@ -1,46 +0,0 @@ -From fc516d3a6aa2c6ffe27d0da8818d13839e023e7e Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Fri, 21 May 2021 10:46:14 -0700 -Subject: [PATCH] net: dsa: bcm_sf2: Fix bcm_sf2_reg_rgmii_cntrl() call for - non-RGMII port -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -We cannot call bcm_sf2_reg_rgmii_cntrl() for a port that is not RGMII, -yet we do that in bcm_sf2_sw_mac_link_up() irrespective of the port's -interface. Move that read until we have properly qualified the PHY -interface mode. This avoids triggering a warning on 7278 platforms that -have GMII ports. - -Fixes: 55cfeb396965 ("net: dsa: bcm_sf2: add function finding RGMII register") -Signed-off-by: Florian Fainelli -Acked-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - drivers/net/dsa/bcm_sf2.c | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -827,11 +827,9 @@ static void bcm_sf2_sw_mac_link_up(struc - bcm_sf2_sw_mac_link_set(ds, port, interface, true); - - if (port != core_readl(priv, CORE_IMP0_PRT_ID)) { -- u32 reg_rgmii_ctrl; -+ u32 reg_rgmii_ctrl = 0; - u32 reg, offset; - -- reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); -- - if (priv->type == BCM4908_DEVICE_ID || - priv->type == BCM7445_DEVICE_ID) - offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); -@@ -842,6 +840,7 @@ static void bcm_sf2_sw_mac_link_up(struc - interface == PHY_INTERFACE_MODE_RGMII_TXID || - interface == PHY_INTERFACE_MODE_MII || - interface == PHY_INTERFACE_MODE_REVMII) { -+ reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port); - reg = reg_readl(priv, reg_rgmii_ctrl); - reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); - diff --git a/target/linux/bcm4908/patches-5.10/076-v5.17-net-dsa-bcm_sf2-refactor-LED-regs-access.patch b/target/linux/bcm4908/patches-5.10/076-v5.17-net-dsa-bcm_sf2-refactor-LED-regs-access.patch deleted file mode 100644 index df8dcd8a2c..0000000000 --- a/target/linux/bcm4908/patches-5.10/076-v5.17-net-dsa-bcm_sf2-refactor-LED-regs-access.patch +++ /dev/null @@ -1,209 +0,0 @@ -From af30f8eaa8fe4ff1987280f716309711997bd979 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 29 Dec 2021 18:16:42 +0100 -Subject: [PATCH] net: dsa: bcm_sf2: refactor LED regs access -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. Define more regs. Some switches (e.g. BCM4908) have up to 6 regs. -2. Add helper for handling non-lineral port <-> reg mappings. -3. Add support for 12 B LED reg blocks on BCM4908 (different layout) - -Complete support for LEDs setup will be implemented once Linux receives -a proper design & implementation for "hardware" LEDs. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20211229171642.22942-1-zajec5@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/bcm_sf2.c | 54 ++++++++++++++++++++++++---- - drivers/net/dsa/bcm_sf2.h | 10 ++++++ - drivers/net/dsa/bcm_sf2_regs.h | 65 +++++++++++++++++++++++++++++++--- - 3 files changed, 119 insertions(+), 10 deletions(-) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -32,6 +32,38 @@ - #include "b53/b53_priv.h" - #include "b53/b53_regs.h" - -+static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port) -+{ -+ switch (port) { -+ case 0: -+ return REG_LED_0_CNTRL; -+ case 1: -+ return REG_LED_1_CNTRL; -+ case 2: -+ return REG_LED_2_CNTRL; -+ } -+ -+ switch (priv->type) { -+ case BCM4908_DEVICE_ID: -+ switch (port) { -+ case 3: -+ return REG_LED_3_CNTRL; -+ case 7: -+ return REG_LED_4_CNTRL; -+ default: -+ break; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ WARN_ONCE(1, "Unsupported port %d\n", port); -+ -+ /* RO fallback reg */ -+ return REG_SWITCH_STATUS; -+} -+ - /* Return the number of active ports, not counting the IMP (CPU) port */ - static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds) - { -@@ -187,9 +219,14 @@ static void bcm_sf2_gphy_enable_set(stru - - /* Use PHY-driven LED signaling */ - if (!enable) { -- reg = reg_readl(priv, REG_LED_CNTRL(0)); -- reg |= SPDLNK_SRC_SEL; -- reg_writel(priv, reg, REG_LED_CNTRL(0)); -+ u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0); -+ -+ if (priv->type == BCM7278_DEVICE_ID || -+ priv->type == BCM7445_DEVICE_ID) { -+ reg = reg_led_readl(priv, led_ctrl, 0); -+ reg |= LED_CNTRL_SPDLNK_SRC_SEL; -+ reg_led_writel(priv, reg, led_ctrl, 0); -+ } - } - } - -@@ -1243,9 +1280,14 @@ static const u16 bcm_sf2_4908_reg_offset - [REG_SPHY_CNTRL] = 0x24, - [REG_CROSSBAR] = 0xc8, - [REG_RGMII_11_CNTRL] = 0x014c, -- [REG_LED_0_CNTRL] = 0x40, -- [REG_LED_1_CNTRL] = 0x4c, -- [REG_LED_2_CNTRL] = 0x58, -+ [REG_LED_0_CNTRL] = 0x40, -+ [REG_LED_1_CNTRL] = 0x4c, -+ [REG_LED_2_CNTRL] = 0x58, -+ [REG_LED_3_CNTRL] = 0x64, -+ [REG_LED_4_CNTRL] = 0x88, -+ [REG_LED_5_CNTRL] = 0xa0, -+ [REG_LED_AGGREGATE_CTRL] = 0xb8, -+ - }; - - static const struct bcm_sf2_of_data bcm_sf2_4908_data = { ---- a/drivers/net/dsa/bcm_sf2.h -+++ b/drivers/net/dsa/bcm_sf2.h -@@ -210,6 +210,16 @@ SF2_IO_MACRO(acb); - SWITCH_INTR_L2(0); - SWITCH_INTR_L2(1); - -+static inline u32 reg_led_readl(struct bcm_sf2_priv *priv, u16 off, u16 reg) -+{ -+ return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg); -+} -+ -+static inline void reg_led_writel(struct bcm_sf2_priv *priv, u32 val, u16 off, u16 reg) -+{ -+ writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg); -+} -+ - /* RXNFC */ - int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port, - struct ethtool_rxnfc *nfc, u32 *rule_locs); ---- a/drivers/net/dsa/bcm_sf2_regs.h -+++ b/drivers/net/dsa/bcm_sf2_regs.h -@@ -25,6 +25,10 @@ enum bcm_sf2_reg_offs { - REG_LED_0_CNTRL, - REG_LED_1_CNTRL, - REG_LED_2_CNTRL, -+ REG_LED_3_CNTRL, -+ REG_LED_4_CNTRL, -+ REG_LED_5_CNTRL, -+ REG_LED_AGGREGATE_CTRL, - REG_SWITCH_REG_MAX, - }; - -@@ -56,6 +60,63 @@ enum bcm_sf2_reg_offs { - #define CROSSBAR_BCM4908_EXT_GPHY4 1 - #define CROSSBAR_BCM4908_EXT_RGMII 2 - -+/* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */ -+#define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0 -+#define LED_CNTRL_M10_ENCODE_SHIFT 2 -+#define LED_CNTRL_M100_ENCODE_SHIFT 4 -+#define LED_CNTRL_M1000_ENCODE_SHIFT 6 -+#define LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT 8 -+#define LED_CNTRL_SEL_10M_ENCODE_SHIFT 10 -+#define LED_CNTRL_SEL_100M_ENCODE_SHIFT 12 -+#define LED_CNTRL_SEL_1000M_ENCODE_SHIFT 14 -+#define LED_CNTRL_RX_DV_EN (1 << 16) -+#define LED_CNTRL_TX_EN_EN (1 << 17) -+#define LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT 18 -+#define LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT 20 -+#define LED_CNTRL_ACT_LED_ACT_SEL_SHIFT 22 -+#define LED_CNTRL_SPDLNK_SRC_SEL (1 << 24) -+#define LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL (1 << 25) -+#define LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL (1 << 26) -+#define LED_CNTRL_ACT_LED_POL_SEL (1 << 27) -+#define LED_CNTRL_MASK 0x3 -+ -+/* Register relative to REG_LED_*_CNTRL (BCM4908) */ -+#define REG_LED_CTRL 0x0 -+#define LED_CTRL_RX_ACT_EN 0x00000001 -+#define LED_CTRL_TX_ACT_EN 0x00000002 -+#define LED_CTRL_SPDLNK_LED0_ACT_SEL 0x00000004 -+#define LED_CTRL_SPDLNK_LED1_ACT_SEL 0x00000008 -+#define LED_CTRL_SPDLNK_LED2_ACT_SEL 0x00000010 -+#define LED_CTRL_ACT_LED_ACT_SEL 0x00000020 -+#define LED_CTRL_SPDLNK_LED0_ACT_POL_SEL 0x00000040 -+#define LED_CTRL_SPDLNK_LED1_ACT_POL_SEL 0x00000080 -+#define LED_CTRL_SPDLNK_LED2_ACT_POL_SEL 0x00000100 -+#define LED_CTRL_ACT_LED_POL_SEL 0x00000200 -+#define LED_CTRL_LED_SPD_OVRD 0x00001c00 -+#define LED_CTRL_LNK_STATUS_OVRD 0x00002000 -+#define LED_CTRL_SPD_OVRD_EN 0x00004000 -+#define LED_CTRL_LNK_OVRD_EN 0x00008000 -+ -+/* Register relative to REG_LED_*_CNTRL (BCM4908) */ -+#define REG_LED_LINK_SPEED_ENC_SEL 0x4 -+#define LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT 0 -+#define LED_LINK_SPEED_ENC_SEL_10M_SHIFT 3 -+#define LED_LINK_SPEED_ENC_SEL_100M_SHIFT 6 -+#define LED_LINK_SPEED_ENC_SEL_1000M_SHIFT 9 -+#define LED_LINK_SPEED_ENC_SEL_2500M_SHIFT 12 -+#define LED_LINK_SPEED_ENC_SEL_10G_SHIFT 15 -+#define LED_LINK_SPEED_ENC_SEL_MASK 0x7 -+ -+/* Register relative to REG_LED_*_CNTRL (BCM4908) */ -+#define REG_LED_LINK_SPEED_ENC 0x8 -+#define LED_LINK_SPEED_ENC_NO_LINK_SHIFT 0 -+#define LED_LINK_SPEED_ENC_M10_SHIFT 3 -+#define LED_LINK_SPEED_ENC_M100_SHIFT 6 -+#define LED_LINK_SPEED_ENC_M1000_SHIFT 9 -+#define LED_LINK_SPEED_ENC_M2500_SHIFT 12 -+#define LED_LINK_SPEED_ENC_M10G_SHIFT 15 -+#define LED_LINK_SPEED_ENC_MASK 0x7 -+ - /* Relative to REG_RGMII_CNTRL */ - #define RGMII_MODE_EN (1 << 0) - #define ID_MODE_DIS (1 << 1) -@@ -73,10 +134,6 @@ enum bcm_sf2_reg_offs { - #define LPI_COUNT_SHIFT 9 - #define LPI_COUNT_MASK 0x3F - --#define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x)) -- --#define SPDLNK_SRC_SEL (1 << 24) -- - /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */ - #define INTRL2_CPU_STATUS 0x00 - #define INTRL2_CPU_SET 0x04 diff --git a/target/linux/bcm4908/patches-5.10/077-v5.14-net-broadcom-bcm4908_enet-reset-DMA-rings-sw-indexes.patch b/target/linux/bcm4908/patches-5.10/077-v5.14-net-broadcom-bcm4908_enet-reset-DMA-rings-sw-indexes.patch deleted file mode 100644 index 02290c8e64..0000000000 --- a/target/linux/bcm4908/patches-5.10/077-v5.14-net-broadcom-bcm4908_enet-reset-DMA-rings-sw-indexes.patch +++ /dev/null @@ -1,45 +0,0 @@ -From ddeacc4f6494e07cbb6f033627926623f3e7a9d0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 22 Jun 2021 07:24:15 +0200 -Subject: [PATCH] net: broadcom: bcm4908_enet: reset DMA rings sw indexes - properly -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Resetting software indexes in bcm4908_dma_alloc_buf_descs() is not -enough as it's called during device probe only. Driver resets DMA on -every .ndo_open callback and it's required to reset indexes then. - -This fixes inconsistent rings state and stalled traffic after interface -down & up sequence. - -Fixes: 4feffeadbcb2 ("net: broadcom: bcm4908enet: add BCM4908 controller driver") -Signed-off-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -174,9 +174,6 @@ static int bcm4908_dma_alloc_buf_descs(s - if (!ring->slots) - goto err_free_buf_descs; - -- ring->read_idx = 0; -- ring->write_idx = 0; -- - return 0; - - err_free_buf_descs: -@@ -303,6 +300,9 @@ static void bcm4908_enet_dma_ring_init(s - - enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, - (uint32_t)ring->dma_addr); -+ -+ ring->read_idx = 0; -+ ring->write_idx = 0; - } - - static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet) diff --git a/target/linux/bcm4908/patches-5.10/077-v5.17-net-broadcom-bcm4908enet-remove-redundant-variable-b.patch b/target/linux/bcm4908/patches-5.10/077-v5.17-net-broadcom-bcm4908enet-remove-redundant-variable-b.patch deleted file mode 100644 index 03e546cb5f..0000000000 --- a/target/linux/bcm4908/patches-5.10/077-v5.17-net-broadcom-bcm4908enet-remove-redundant-variable-b.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 62a3106697f3c6f9af64a2cd0f9ff58552010dc8 Mon Sep 17 00:00:00 2001 -From: Colin Ian King -Date: Wed, 22 Dec 2021 00:39:37 +0000 -Subject: [PATCH] net: broadcom: bcm4908enet: remove redundant variable bytes - -The variable bytes is being used to summate slot lengths, -however the value is never used afterwards. The summation -is redundant so remove variable bytes. - -Signed-off-by: Colin Ian King -Link: https://lore.kernel.org/r/20211222003937.727325-1-colin.i.king@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -634,7 +634,6 @@ static int bcm4908_enet_poll_tx(struct n - struct bcm4908_enet_dma_ring_bd *buf_desc; - struct bcm4908_enet_dma_ring_slot *slot; - struct device *dev = enet->dev; -- unsigned int bytes = 0; - int handled = 0; - - while (handled < weight && tx_ring->read_idx != tx_ring->write_idx) { -@@ -645,7 +644,6 @@ static int bcm4908_enet_poll_tx(struct n - - dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); - dev_kfree_skb(slot->skb); -- bytes += slot->len; - if (++tx_ring->read_idx == tx_ring->length) - tx_ring->read_idx = 0; - diff --git a/target/linux/bcm4908/patches-5.10/078-v6.1-0001-net-broadcom-bcm4908_enet-handle-EPROBE_DEFER-when-g.patch b/target/linux/bcm4908/patches-5.10/078-v6.1-0001-net-broadcom-bcm4908_enet-handle-EPROBE_DEFER-when-g.patch deleted file mode 100644 index a6eba111f9..0000000000 --- a/target/linux/bcm4908/patches-5.10/078-v6.1-0001-net-broadcom-bcm4908_enet-handle-EPROBE_DEFER-when-g.patch +++ /dev/null @@ -1,55 +0,0 @@ -From e93a766da57fff3273bcb618edf5dfca1fb86b89 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 15 Sep 2022 15:30:13 +0200 -Subject: [PATCH] net: broadcom: bcm4908_enet: handle -EPROBE_DEFER when - getting MAC -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Reading MAC from OF may return -EPROBE_DEFER if underlaying NVMEM device -isn't ready yet. In such case pass that error code up and "wait" to be -probed later. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20220915133013.2243-1-zajec5@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -712,7 +712,9 @@ static int bcm4908_enet_probe(struct pla - return err; - - SET_NETDEV_DEV(netdev, &pdev->dev); -- of_get_mac_address(dev->of_node, netdev->dev_addr); -+ err = of_get_mac_address(dev->of_node, netdev->dev_addr); -+ if (err == -EPROBE_DEFER) -+ goto err_dma_free; - if (!is_valid_ether_addr(netdev->dev_addr)) - eth_hw_addr_random(netdev); - netdev->netdev_ops = &bcm4908_enet_netdev_ops; -@@ -723,14 +725,17 @@ static int bcm4908_enet_probe(struct pla - netif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT); - - err = register_netdev(netdev); -- if (err) { -- bcm4908_enet_dma_free(enet); -- return err; -- } -+ if (err) -+ goto err_dma_free; - - platform_set_drvdata(pdev, enet); - - return 0; -+ -+err_dma_free: -+ bcm4908_enet_dma_free(enet); -+ -+ return err; - } - - static int bcm4908_enet_remove(struct platform_device *pdev) diff --git a/target/linux/bcm4908/patches-5.10/078-v6.1-0002-net-broadcom-bcm4908_enet-update-TX-stats-after-actu.patch b/target/linux/bcm4908/patches-5.10/078-v6.1-0002-net-broadcom-bcm4908_enet-update-TX-stats-after-actu.patch deleted file mode 100644 index 29cf3742f4..0000000000 --- a/target/linux/bcm4908/patches-5.10/078-v6.1-0002-net-broadcom-bcm4908_enet-update-TX-stats-after-actu.patch +++ /dev/null @@ -1,65 +0,0 @@ -From ef3556ee16c68735ec69bd08df41d1cd83b14ad3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 27 Oct 2022 13:24:30 +0200 -Subject: [PATCH] net: broadcom: bcm4908_enet: update TX stats after actual - transmission -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Queueing packets doesn't guarantee their transmission. Update TX stats -after hardware confirms consuming submitted data. - -This also fixes a possible race and NULL dereference. -bcm4908_enet_start_xmit() could try to access skb after freeing it in -the bcm4908_enet_poll_tx(). - -Reported-by: Florian Fainelli -Fixes: 4feffeadbcb2e ("net: broadcom: bcm4908enet: add BCM4908 controller driver") -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Link: https://lore.kernel.org/r/20221027112430.8696-1-zajec5@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -560,8 +560,6 @@ static int bcm4908_enet_start_xmit(struc - - if (++ring->write_idx == ring->length - 1) - ring->write_idx = 0; -- enet->netdev->stats.tx_bytes += skb->len; -- enet->netdev->stats.tx_packets++; - - return NETDEV_TX_OK; - } -@@ -634,6 +632,7 @@ static int bcm4908_enet_poll_tx(struct n - struct bcm4908_enet_dma_ring_bd *buf_desc; - struct bcm4908_enet_dma_ring_slot *slot; - struct device *dev = enet->dev; -+ unsigned int bytes = 0; - int handled = 0; - - while (handled < weight && tx_ring->read_idx != tx_ring->write_idx) { -@@ -644,12 +643,17 @@ static int bcm4908_enet_poll_tx(struct n - - dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE); - dev_kfree_skb(slot->skb); -- if (++tx_ring->read_idx == tx_ring->length) -- tx_ring->read_idx = 0; - - handled++; -+ bytes += slot->len; -+ -+ if (++tx_ring->read_idx == tx_ring->length) -+ tx_ring->read_idx = 0; - } - -+ enet->netdev->stats.tx_packets += handled; -+ enet->netdev->stats.tx_bytes += bytes; -+ - if (handled < weight) { - napi_complete_done(napi, handled); - bcm4908_enet_dma_ring_intrs_on(enet, tx_ring); diff --git a/target/linux/bcm4908/patches-5.10/079-v6.2-0001-net-broadcom-bcm4908_enet-use-build_skb.patch b/target/linux/bcm4908/patches-5.10/079-v6.2-0001-net-broadcom-bcm4908_enet-use-build_skb.patch deleted file mode 100644 index 834973f5c7..0000000000 --- a/target/linux/bcm4908/patches-5.10/079-v6.2-0001-net-broadcom-bcm4908_enet-use-build_skb.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 3a1cc23a75abcd9cea585eb84846507363d58397 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 25 Oct 2022 15:22:45 +0200 -Subject: [PATCH] net: broadcom: bcm4908_enet: use build_skb() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -RX code can be more efficient with the build_skb(). Allocating actual -SKB around eth packet buffer - right before passing it up - results in -a better cache usage. - -Without RPS (echo 0 > rps_cpus) BCM4908 NAT masq performance "jumps" -between two speeds: ~900 Mbps and 940 Mbps (it's a 4 CPUs SoC). This -change bumps the lower speed from 905 Mb/s to 918 Mb/s (tested using -single stream iperf 2.0.5 traffic). - -There are more optimizations to consider. One obvious to try is GRO -however as BCM4908 doesn't do hw csum is may actually lower performance. -Sometimes. Some early testing: - -┌─────────────────────────────────┬─────────────────────┬────────────────────┐ -│ │ netif_receive_skb() │ napi_gro_receive() │ -├─────────────────────────────────┼─────────────────────┼────────────────────┤ -│ netdev_alloc_skb() │ 905 Mb/s │ 892 Mb/s │ -│ napi_alloc_frag() + build_skb() │ 918 Mb/s │ 917 Mb/s │ -└─────────────────────────────────┴─────────────────────┴────────────────────┘ - -Another ideas: -1. napi_build_skb() -2. skb_copy_from_linear_data() for small packets - -Those need proper testing first though. That can be done later. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20221025132245.22871-1-zajec5@gmail.com -Signed-off-by: Paolo Abeni ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 53 +++++++++++++------- - 1 file changed, 36 insertions(+), 17 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -36,13 +36,24 @@ - #define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \ - ETH_FCS_LEN + 4) /* 32 */ - -+#define ENET_RX_SKB_BUF_SIZE (NET_SKB_PAD + NET_IP_ALIGN + \ -+ ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \ -+ ENET_MTU_MAX + ETH_FCS_LEN + 4) -+#define ENET_RX_SKB_BUF_ALLOC_SIZE (SKB_DATA_ALIGN(ENET_RX_SKB_BUF_SIZE) + \ -+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) -+#define ENET_RX_BUF_DMA_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) -+#define ENET_RX_BUF_DMA_SIZE (ENET_RX_SKB_BUF_SIZE - ENET_RX_BUF_DMA_OFFSET) -+ - struct bcm4908_enet_dma_ring_bd { - __le32 ctl; - __le32 addr; - } __packed; - - struct bcm4908_enet_dma_ring_slot { -- struct sk_buff *skb; -+ union { -+ void *buf; /* RX */ -+ struct sk_buff *skb; /* TX */ -+ }; - unsigned int len; - dma_addr_t dma_addr; - }; -@@ -259,22 +270,21 @@ static int bcm4908_enet_dma_alloc_rx_buf - u32 tmp; - int err; - -- slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD; -- -- slot->skb = netdev_alloc_skb(enet->netdev, slot->len); -- if (!slot->skb) -+ slot->buf = napi_alloc_frag(ENET_RX_SKB_BUF_ALLOC_SIZE); -+ if (!slot->buf) - return -ENOMEM; - -- slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE); -+ slot->dma_addr = dma_map_single(dev, slot->buf + ENET_RX_BUF_DMA_OFFSET, -+ ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE); - err = dma_mapping_error(dev, slot->dma_addr); - if (err) { - dev_err(dev, "Failed to map DMA buffer: %d\n", err); -- kfree_skb(slot->skb); -- slot->skb = NULL; -+ skb_free_frag(slot->buf); -+ slot->buf = NULL; - return err; - } - -- tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; -+ tmp = ENET_RX_BUF_DMA_SIZE << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT; - tmp |= DMA_CTL_STATUS_OWN; - if (idx == enet->rx_ring.length - 1) - tmp |= DMA_CTL_STATUS_WRAP; -@@ -314,11 +324,11 @@ static void bcm4908_enet_dma_uninit(stru - - for (i = rx_ring->length - 1; i >= 0; i--) { - slot = &rx_ring->slots[i]; -- if (!slot->skb) -+ if (!slot->buf) - continue; - dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE); -- kfree_skb(slot->skb); -- slot->skb = NULL; -+ skb_free_frag(slot->buf); -+ slot->buf = NULL; - } - } - -@@ -574,6 +584,7 @@ static int bcm4908_enet_poll_rx(struct n - while (handled < weight) { - struct bcm4908_enet_dma_ring_bd *buf_desc; - struct bcm4908_enet_dma_ring_slot slot; -+ struct sk_buff *skb; - u32 ctl; - int len; - int err; -@@ -597,16 +608,24 @@ static int bcm4908_enet_poll_rx(struct n - - if (len < ETH_ZLEN || - (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) { -- kfree_skb(slot.skb); -+ skb_free_frag(slot.buf); - enet->netdev->stats.rx_dropped++; - break; - } - -- dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE); -+ dma_unmap_single(dev, slot.dma_addr, ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE); -+ -+ skb = build_skb(slot.buf, ENET_RX_SKB_BUF_ALLOC_SIZE); -+ if (unlikely(!skb)) { -+ skb_free_frag(slot.buf); -+ enet->netdev->stats.rx_dropped++; -+ break; -+ } -+ skb_reserve(skb, ENET_RX_BUF_DMA_OFFSET); -+ skb_put(skb, len - ETH_FCS_LEN); -+ skb->protocol = eth_type_trans(skb, enet->netdev); - -- skb_put(slot.skb, len - ETH_FCS_LEN); -- slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev); -- netif_receive_skb(slot.skb); -+ netif_receive_skb(skb); - - enet->netdev->stats.rx_packets++; - enet->netdev->stats.rx_bytes += len; diff --git a/target/linux/bcm4908/patches-5.10/079-v6.2-0002-net-broadcom-bcm4908_enet-report-queued-and-transmit.patch b/target/linux/bcm4908/patches-5.10/079-v6.2-0002-net-broadcom-bcm4908_enet-report-queued-and-transmit.patch deleted file mode 100644 index 9f85a77b76..0000000000 --- a/target/linux/bcm4908/patches-5.10/079-v6.2-0002-net-broadcom-bcm4908_enet-report-queued-and-transmit.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 471ef777ec79baadc5cd9773d08f95f49cf5e2b1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 31 Oct 2022 11:48:56 +0100 -Subject: [PATCH] net: broadcom: bcm4908_enet: report queued and transmitted - bytes -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This allows BQL to operate avoiding buffer bloat and reducing latency. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20221031104856.32388-1-zajec5@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c -+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c -@@ -504,6 +504,7 @@ static int bcm4908_enet_stop(struct net_ - netif_carrier_off(netdev); - napi_disable(&rx_ring->napi); - napi_disable(&tx_ring->napi); -+ netdev_reset_queue(netdev); - - bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring); - bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring); -@@ -563,6 +564,8 @@ static int bcm4908_enet_start_xmit(struc - if (ring->write_idx + 1 == ring->length - 1) - tmp |= DMA_CTL_STATUS_WRAP; - -+ netdev_sent_queue(enet->netdev, skb->len); -+ - buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr); - buf_desc->ctl = cpu_to_le32(tmp); - -@@ -670,6 +673,7 @@ static int bcm4908_enet_poll_tx(struct n - tx_ring->read_idx = 0; - } - -+ netdev_completed_queue(enet->netdev, handled, bytes); - enet->netdev->stats.tx_packets += handled; - enet->netdev->stats.tx_bytes += bytes; - diff --git a/target/linux/bcm4908/patches-5.10/080-v5.11-tty-serial-bcm63xx-lower-driver-dependencies.patch b/target/linux/bcm4908/patches-5.10/080-v5.11-tty-serial-bcm63xx-lower-driver-dependencies.patch deleted file mode 100644 index 38e3d056b9..0000000000 --- a/target/linux/bcm4908/patches-5.10/080-v5.11-tty-serial-bcm63xx-lower-driver-dependencies.patch +++ /dev/null @@ -1,31 +0,0 @@ -From f35a07f92616700733636c06dd6e5b6cdc807fe4 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 25 Nov 2020 10:06:08 +0100 -Subject: [PATCH] tty: serial: bcm63xx: lower driver dependencies -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Hardware supported by bcm63xx is also used by BCM4908 SoCs family that -is ARM64. In future more architectures may need it as well. There is -nothing arch specific breaking compilation so just stick to requiring -COMMON_CLK. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20201125090608.28442-1-zajec5@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/tty/serial/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/tty/serial/Kconfig -+++ b/drivers/tty/serial/Kconfig -@@ -1133,7 +1133,7 @@ config SERIAL_TIMBERDALE - config SERIAL_BCM63XX - tristate "Broadcom BCM63xx/BCM33xx UART support" - select SERIAL_CORE -- depends on MIPS || ARM || COMPILE_TEST -+ depends on COMMON_CLK - help - This enables the driver for the onchip UART core found on - the following chipsets: diff --git a/target/linux/bcm4908/patches-5.10/081-v5.12-reset-simple-add-BCM4908-MISC-PCIe-reset-controller-.patch b/target/linux/bcm4908/patches-5.10/081-v5.12-reset-simple-add-BCM4908-MISC-PCIe-reset-controller-.patch deleted file mode 100644 index 28702c9d0e..0000000000 --- a/target/linux/bcm4908/patches-5.10/081-v5.12-reset-simple-add-BCM4908-MISC-PCIe-reset-controller-.patch +++ /dev/null @@ -1,40 +0,0 @@ -From def26913b66fd94e431afecf28e09c08e8c02a35 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 27 Nov 2020 12:14:42 +0100 -Subject: [PATCH] reset: simple: add BCM4908 MISC PCIe reset controller support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's a trivial reset controller. One register with bit per PCIe core. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Signed-off-by: Philipp Zabel ---- - drivers/reset/Kconfig | 2 +- - drivers/reset/reset-simple.c | 2 ++ - 2 files changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -167,7 +167,7 @@ config RESET_SCMI - - config RESET_SIMPLE - bool "Simple Reset Controller Driver" if COMPILE_TEST -- default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC -+ default ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC - help - This enables a simple reset controller driver for reset lines that - that can be asserted and deasserted by toggling bits in a contiguous, ---- a/drivers/reset/reset-simple.c -+++ b/drivers/reset/reset-simple.c -@@ -146,6 +146,8 @@ static const struct of_device_id reset_s - { .compatible = "aspeed,ast2500-lpc-reset" }, - { .compatible = "bitmain,bm1880-reset", - .data = &reset_simple_active_low }, -+ { .compatible = "brcm,bcm4908-misc-pcie-reset", -+ .data = &reset_simple_active_low }, - { .compatible = "snps,dw-high-reset" }, - { .compatible = "snps,dw-low-reset", - .data = &reset_simple_active_low }, diff --git a/target/linux/bcm4908/patches-5.10/082-v5.12-0001-dt-bindings-power-document-Broadcom-s-PMB-binding.patch b/target/linux/bcm4908/patches-5.10/082-v5.12-0001-dt-bindings-power-document-Broadcom-s-PMB-binding.patch deleted file mode 100644 index c5c1a5dc7e..0000000000 --- a/target/linux/bcm4908/patches-5.10/082-v5.12-0001-dt-bindings-power-document-Broadcom-s-PMB-binding.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 82853543057f78d8a331272b70bc3f1e8cb0cbf4 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 14 Dec 2020 19:07:42 +0100 -Subject: [PATCH] dt-bindings: power: document Broadcom's PMB binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Broadcom's PMB is power controller used for disabling and enabling SoC -devices. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Rob Herring -Acked-by: Florian Fainelli -Acked-by: Ulf Hansson -Signed-off-by: Florian Fainelli ---- - .../bindings/power/brcm,bcm-pmb.yaml | 50 +++++++++++++++++++ - include/dt-bindings/soc/bcm-pmb.h | 11 ++++ - 2 files changed, 61 insertions(+) - create mode 100644 Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml - create mode 100644 include/dt-bindings/soc/bcm-pmb.h - ---- /dev/null -+++ b/Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml -@@ -0,0 +1,50 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/power/brcm,bcm-pmb.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom PMB (Power Management Bus) controller -+ -+description: This document describes Broadcom's PMB controller. It supports -+ powering various types of connected devices (e.g. PCIe, USB, SATA). -+ -+maintainers: -+ - Rafał Miłecki -+ -+properties: -+ compatible: -+ enum: -+ - brcm,bcm4908-pmb -+ -+ reg: -+ description: register space of one or more buses -+ maxItems: 1 -+ -+ big-endian: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: Flag to use for block working in big endian mode. -+ -+ "#power-domain-cells": -+ description: cell specifies device ID (see bcm-pmb.h) -+ const: 1 -+ -+required: -+ - reg -+ - "#power-domain-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ -+ pmb: power-controller@802800e0 { -+ compatible = "brcm,bcm4908-pmb"; -+ reg = <0x802800e0 0x40>; -+ #power-domain-cells = <1>; -+ }; -+ -+ foo { -+ power-domains = <&pmb BCM_PMB_PCIE0>; -+ }; ---- /dev/null -+++ b/include/dt-bindings/soc/bcm-pmb.h -@@ -0,0 +1,11 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ -+ -+#ifndef __DT_BINDINGS_SOC_BCM_PMB_H -+#define __DT_BINDINGS_SOC_BCM_PMB_H -+ -+#define BCM_PMB_PCIE0 0x01 -+#define BCM_PMB_PCIE1 0x02 -+#define BCM_PMB_PCIE2 0x03 -+#define BCM_PMB_HOST_USB 0x04 -+ -+#endif diff --git a/target/linux/bcm4908/patches-5.10/082-v5.12-0002-soc-bcm-add-PM-driver-for-Broadcom-s-PMB.patch b/target/linux/bcm4908/patches-5.10/082-v5.12-0002-soc-bcm-add-PM-driver-for-Broadcom-s-PMB.patch deleted file mode 100644 index 8cbf33f5a9..0000000000 --- a/target/linux/bcm4908/patches-5.10/082-v5.12-0002-soc-bcm-add-PM-driver-for-Broadcom-s-PMB.patch +++ /dev/null @@ -1,409 +0,0 @@ -From 8bcac4011ebe0dbdd46fd55b036ee855c95702d3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 14 Dec 2020 19:07:43 +0100 -Subject: [PATCH] soc: bcm: add PM driver for Broadcom's PMB -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -PMB originally comes from BCM63138 but can be also found on many other -chipsets (e.g. BCM4908). It's needed to power on and off SoC blocks like -PCIe, SATA, USB. - -Signed-off-by: Rafał Miłecki -Acked-by: Ulf Hansson -Signed-off-by: Florian Fainelli ---- - MAINTAINERS | 10 + - drivers/soc/bcm/Makefile | 2 +- - drivers/soc/bcm/bcm63xx/Kconfig | 9 + - drivers/soc/bcm/bcm63xx/Makefile | 1 + - drivers/soc/bcm/bcm63xx/bcm-pmb.c | 333 ++++++++++++++++++++++++++++++ - 5 files changed, 354 insertions(+), 1 deletion(-) - create mode 100644 drivers/soc/bcm/bcm63xx/bcm-pmb.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3674,6 +3674,16 @@ L: linux-mips@vger.kernel.org - S: Maintained - F: drivers/firmware/broadcom/* - -+BROADCOM PMB (POWER MANAGEMENT BUS) DRIVER -+M: Rafał Miłecki -+M: Florian Fainelli -+M: bcm-kernel-feedback-list@broadcom.com -+L: linux-pm@vger.kernel.org -+S: Maintained -+T: git git://github.com/broadcom/stblinux.git -+F: drivers/soc/bcm/bcm-pmb.c -+F: include/dt-bindings/soc/bcm-pmb.h -+ - BROADCOM SPECIFIC AMBA DRIVER (BCMA) - M: Rafał Miłecki - L: linux-wireless@vger.kernel.org ---- a/drivers/soc/bcm/Makefile -+++ b/drivers/soc/bcm/Makefile -@@ -1,5 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_BCM2835_POWER) += bcm2835-power.o - obj-$(CONFIG_RASPBERRYPI_POWER) += raspberrypi-power.o --obj-$(CONFIG_SOC_BCM63XX) += bcm63xx/ -+obj-y += bcm63xx/ - obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/ ---- a/drivers/soc/bcm/bcm63xx/Kconfig -+++ b/drivers/soc/bcm/bcm63xx/Kconfig -@@ -10,3 +10,12 @@ config BCM63XX_POWER - BCM6318, BCM6328, BCM6362 and BCM63268 SoCs. - - endif # SOC_BCM63XX -+ -+config BCM_PMB -+ bool "Broadcom PMB (Power Management Bus) driver" -+ depends on ARCH_BCM4908 || (COMPILE_TEST && OF) -+ default ARCH_BCM4908 -+ select PM_GENERIC_DOMAINS if PM -+ help -+ This enables support for the Broadcom's PMB (Power Management Bus) that -+ is used for disabling and enabling SoC devices. ---- a/drivers/soc/bcm/bcm63xx/Makefile -+++ b/drivers/soc/bcm/bcm63xx/Makefile -@@ -1,2 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_BCM63XX_POWER) += bcm63xx-power.o -+obj-$(CONFIG_BCM_PMB) += bcm-pmb.o ---- /dev/null -+++ b/drivers/soc/bcm/bcm63xx/bcm-pmb.c -@@ -0,0 +1,333 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright (c) 2013 Broadcom -+ * Copyright (C) 2020 Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BPCM_ID_REG 0x00 -+#define BPCM_CAPABILITIES 0x04 -+#define BPCM_CAP_NUM_ZONES 0x000000ff -+#define BPCM_CAP_SR_REG_BITS 0x0000ff00 -+#define BPCM_CAP_PLLTYPE 0x00030000 -+#define BPCM_CAP_UBUS 0x00080000 -+#define BPCM_CONTROL 0x08 -+#define BPCM_STATUS 0x0c -+#define BPCM_ROSC_CONTROL 0x10 -+#define BPCM_ROSC_THRESH_H 0x14 -+#define BPCM_ROSC_THRESHOLD_BCM6838 0x14 -+#define BPCM_ROSC_THRESH_S 0x18 -+#define BPCM_ROSC_COUNT_BCM6838 0x18 -+#define BPCM_ROSC_COUNT 0x1c -+#define BPCM_PWD_CONTROL_BCM6838 0x1c -+#define BPCM_PWD_CONTROL 0x20 -+#define BPCM_SR_CONTROL_BCM6838 0x20 -+#define BPCM_PWD_ACCUM_CONTROL 0x24 -+#define BPCM_SR_CONTROL 0x28 -+#define BPCM_GLOBAL_CONTROL 0x2c -+#define BPCM_MISC_CONTROL 0x30 -+#define BPCM_MISC_CONTROL2 0x34 -+#define BPCM_SGPHY_CNTL 0x38 -+#define BPCM_SGPHY_STATUS 0x3c -+#define BPCM_ZONE0 0x40 -+#define BPCM_ZONE_CONTROL 0x00 -+#define BPCM_ZONE_CONTROL_MANUAL_CLK_EN 0x00000001 -+#define BPCM_ZONE_CONTROL_MANUAL_RESET_CTL 0x00000002 -+#define BPCM_ZONE_CONTROL_FREQ_SCALE_USED 0x00000004 /* R/O */ -+#define BPCM_ZONE_CONTROL_DPG_CAPABLE 0x00000008 /* R/O */ -+#define BPCM_ZONE_CONTROL_MANUAL_MEM_PWR 0x00000030 -+#define BPCM_ZONE_CONTROL_MANUAL_ISO_CTL 0x00000040 -+#define BPCM_ZONE_CONTROL_MANUAL_CTL 0x00000080 -+#define BPCM_ZONE_CONTROL_DPG_CTL_EN 0x00000100 -+#define BPCM_ZONE_CONTROL_PWR_DN_REQ 0x00000200 -+#define BPCM_ZONE_CONTROL_PWR_UP_REQ 0x00000400 -+#define BPCM_ZONE_CONTROL_MEM_PWR_CTL_EN 0x00000800 -+#define BPCM_ZONE_CONTROL_BLK_RESET_ASSERT 0x00001000 -+#define BPCM_ZONE_CONTROL_MEM_STBY 0x00002000 -+#define BPCM_ZONE_CONTROL_RESERVED 0x0007c000 -+#define BPCM_ZONE_CONTROL_PWR_CNTL_STATE 0x00f80000 -+#define BPCM_ZONE_CONTROL_FREQ_SCALAR_DYN_SEL 0x01000000 /* R/O */ -+#define BPCM_ZONE_CONTROL_PWR_OFF_STATE 0x02000000 /* R/O */ -+#define BPCM_ZONE_CONTROL_PWR_ON_STATE 0x04000000 /* R/O */ -+#define BPCM_ZONE_CONTROL_PWR_GOOD 0x08000000 /* R/O */ -+#define BPCM_ZONE_CONTROL_DPG_PWR_STATE 0x10000000 /* R/O */ -+#define BPCM_ZONE_CONTROL_MEM_PWR_STATE 0x20000000 /* R/O */ -+#define BPCM_ZONE_CONTROL_ISO_STATE 0x40000000 /* R/O */ -+#define BPCM_ZONE_CONTROL_RESET_STATE 0x80000000 /* R/O */ -+#define BPCM_ZONE_CONFIG1 0x04 -+#define BPCM_ZONE_CONFIG2 0x08 -+#define BPCM_ZONE_FREQ_SCALAR_CONTROL 0x0c -+#define BPCM_ZONE_SIZE 0x10 -+ -+struct bcm_pmb { -+ struct device *dev; -+ void __iomem *base; -+ spinlock_t lock; -+ bool little_endian; -+ struct genpd_onecell_data genpd_onecell_data; -+}; -+ -+struct bcm_pmb_pd_data { -+ const char * const name; -+ int id; -+ u8 bus; -+ u8 device; -+}; -+ -+struct bcm_pmb_pm_domain { -+ struct bcm_pmb *pmb; -+ const struct bcm_pmb_pd_data *data; -+ struct generic_pm_domain genpd; -+}; -+ -+static int bcm_pmb_bpcm_read(struct bcm_pmb *pmb, int bus, u8 device, -+ int offset, u32 *val) -+{ -+ void __iomem *base = pmb->base + bus * 0x20; -+ unsigned long flags; -+ int err; -+ -+ spin_lock_irqsave(&pmb->lock, flags); -+ err = bpcm_rd(base, device, offset, val); -+ spin_unlock_irqrestore(&pmb->lock, flags); -+ -+ if (!err) -+ *val = pmb->little_endian ? le32_to_cpu(*val) : be32_to_cpu(*val); -+ -+ return err; -+} -+ -+static int bcm_pmb_bpcm_write(struct bcm_pmb *pmb, int bus, u8 device, -+ int offset, u32 val) -+{ -+ void __iomem *base = pmb->base + bus * 0x20; -+ unsigned long flags; -+ int err; -+ -+ val = pmb->little_endian ? cpu_to_le32(val) : cpu_to_be32(val); -+ -+ spin_lock_irqsave(&pmb->lock, flags); -+ err = bpcm_wr(base, device, offset, val); -+ spin_unlock_irqrestore(&pmb->lock, flags); -+ -+ return err; -+} -+ -+static int bcm_pmb_power_off_zone(struct bcm_pmb *pmb, int bus, u8 device, -+ int zone) -+{ -+ int offset; -+ u32 val; -+ int err; -+ -+ offset = BPCM_ZONE0 + zone * BPCM_ZONE_SIZE + BPCM_ZONE_CONTROL; -+ -+ err = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val); -+ if (err) -+ return err; -+ -+ val |= BPCM_ZONE_CONTROL_PWR_DN_REQ; -+ val &= ~BPCM_ZONE_CONTROL_PWR_UP_REQ; -+ -+ err = bcm_pmb_bpcm_write(pmb, bus, device, offset, val); -+ -+ return err; -+} -+ -+static int bcm_pmb_power_on_zone(struct bcm_pmb *pmb, int bus, u8 device, -+ int zone) -+{ -+ int offset; -+ u32 val; -+ int err; -+ -+ offset = BPCM_ZONE0 + zone * BPCM_ZONE_SIZE + BPCM_ZONE_CONTROL; -+ -+ err = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val); -+ if (err) -+ return err; -+ -+ if (!(val & BPCM_ZONE_CONTROL_PWR_ON_STATE)) { -+ val &= ~BPCM_ZONE_CONTROL_PWR_DN_REQ; -+ val |= BPCM_ZONE_CONTROL_DPG_CTL_EN; -+ val |= BPCM_ZONE_CONTROL_PWR_UP_REQ; -+ val |= BPCM_ZONE_CONTROL_MEM_PWR_CTL_EN; -+ val |= BPCM_ZONE_CONTROL_BLK_RESET_ASSERT; -+ -+ err = bcm_pmb_bpcm_write(pmb, bus, device, offset, val); -+ } -+ -+ return err; -+} -+ -+static int bcm_pmb_power_off_device(struct bcm_pmb *pmb, int bus, u8 device) -+{ -+ int offset; -+ u32 val; -+ int err; -+ -+ /* Entire device can be powered off by powering off the 0th zone */ -+ offset = BPCM_ZONE0 + BPCM_ZONE_CONTROL; -+ -+ err = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val); -+ if (err) -+ return err; -+ -+ if (!(val & BPCM_ZONE_CONTROL_PWR_OFF_STATE)) { -+ val = BPCM_ZONE_CONTROL_PWR_DN_REQ; -+ -+ err = bcm_pmb_bpcm_write(pmb, bus, device, offset, val); -+ } -+ -+ return err; -+} -+ -+static int bcm_pmb_power_on_device(struct bcm_pmb *pmb, int bus, u8 device) -+{ -+ u32 val; -+ int err; -+ int i; -+ -+ err = bcm_pmb_bpcm_read(pmb, bus, device, BPCM_CAPABILITIES, &val); -+ if (err) -+ return err; -+ -+ for (i = 0; i < (val & BPCM_CAP_NUM_ZONES); i++) { -+ err = bcm_pmb_power_on_zone(pmb, bus, device, i); -+ if (err) -+ return err; -+ } -+ -+ return err; -+} -+ -+static int bcm_pmb_power_on(struct generic_pm_domain *genpd) -+{ -+ struct bcm_pmb_pm_domain *pd = container_of(genpd, struct bcm_pmb_pm_domain, genpd); -+ const struct bcm_pmb_pd_data *data = pd->data; -+ struct bcm_pmb *pmb = pd->pmb; -+ -+ switch (data->id) { -+ case BCM_PMB_PCIE0: -+ case BCM_PMB_PCIE1: -+ case BCM_PMB_PCIE2: -+ return bcm_pmb_power_on_zone(pmb, data->bus, data->device, 0); -+ case BCM_PMB_HOST_USB: -+ return bcm_pmb_power_on_device(pmb, data->bus, data->device); -+ default: -+ dev_err(pmb->dev, "unsupported device id: %d\n", data->id); -+ return -EINVAL; -+ } -+} -+ -+static int bcm_pmb_power_off(struct generic_pm_domain *genpd) -+{ -+ struct bcm_pmb_pm_domain *pd = container_of(genpd, struct bcm_pmb_pm_domain, genpd); -+ const struct bcm_pmb_pd_data *data = pd->data; -+ struct bcm_pmb *pmb = pd->pmb; -+ -+ switch (data->id) { -+ case BCM_PMB_PCIE0: -+ case BCM_PMB_PCIE1: -+ case BCM_PMB_PCIE2: -+ return bcm_pmb_power_off_zone(pmb, data->bus, data->device, 0); -+ case BCM_PMB_HOST_USB: -+ return bcm_pmb_power_off_device(pmb, data->bus, data->device); -+ default: -+ dev_err(pmb->dev, "unsupported device id: %d\n", data->id); -+ return -EINVAL; -+ } -+} -+ -+static int bcm_pmb_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ const struct bcm_pmb_pd_data *table; -+ const struct bcm_pmb_pd_data *e; -+ struct resource *res; -+ struct bcm_pmb *pmb; -+ int max_id; -+ int err; -+ -+ pmb = devm_kzalloc(dev, sizeof(*pmb), GFP_KERNEL); -+ if (!pmb) -+ return -ENOMEM; -+ -+ pmb->dev = dev; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ pmb->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(pmb->base)) -+ return PTR_ERR(pmb->base); -+ -+ spin_lock_init(&pmb->lock); -+ -+ pmb->little_endian = !of_device_is_big_endian(dev->of_node); -+ -+ table = of_device_get_match_data(dev); -+ if (!table) -+ return -EINVAL; -+ -+ max_id = 0; -+ for (e = table; e->name; e++) -+ max_id = max(max_id, e->id); -+ -+ pmb->genpd_onecell_data.num_domains = max_id + 1; -+ pmb->genpd_onecell_data.domains = -+ devm_kcalloc(dev, pmb->genpd_onecell_data.num_domains, -+ sizeof(struct generic_pm_domain *), GFP_KERNEL); -+ if (!pmb->genpd_onecell_data.domains) -+ return -ENOMEM; -+ -+ for (e = table; e->name; e++) { -+ struct bcm_pmb_pm_domain *pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); -+ -+ pd->pmb = pmb; -+ pd->data = e; -+ pd->genpd.name = e->name; -+ pd->genpd.power_on = bcm_pmb_power_on; -+ pd->genpd.power_off = bcm_pmb_power_off; -+ -+ pm_genpd_init(&pd->genpd, NULL, true); -+ pmb->genpd_onecell_data.domains[e->id] = &pd->genpd; -+ } -+ -+ err = of_genpd_add_provider_onecell(dev->of_node, &pmb->genpd_onecell_data); -+ if (err) { -+ dev_err(dev, "failed to add genpd provider: %d\n", err); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static const struct bcm_pmb_pd_data bcm_pmb_bcm4908_data[] = { -+ { .name = "pcie2", .id = BCM_PMB_PCIE2, .bus = 0, .device = 2, }, -+ { .name = "pcie0", .id = BCM_PMB_PCIE0, .bus = 1, .device = 14, }, -+ { .name = "pcie1", .id = BCM_PMB_PCIE1, .bus = 1, .device = 15, }, -+ { .name = "usb", .id = BCM_PMB_HOST_USB, .bus = 1, .device = 17, }, -+ { }, -+}; -+ -+static const struct of_device_id bcm_pmb_of_match[] = { -+ { .compatible = "brcm,bcm4908-pmb", .data = &bcm_pmb_bcm4908_data, }, -+ { }, -+}; -+ -+static struct platform_driver bcm_pmb_driver = { -+ .driver = { -+ .name = "bcm-pmb", -+ .of_match_table = bcm_pmb_of_match, -+ }, -+ .probe = bcm_pmb_probe, -+}; -+ -+builtin_platform_driver(bcm_pmb_driver); diff --git a/target/linux/bcm4908/patches-5.10/082-v5.12-0003-soc-bcm-brcmstb-add-stubs-for-getting-platform-IDs.patch b/target/linux/bcm4908/patches-5.10/082-v5.12-0003-soc-bcm-brcmstb-add-stubs-for-getting-platform-IDs.patch deleted file mode 100644 index aab65925b4..0000000000 --- a/target/linux/bcm4908/patches-5.10/082-v5.12-0003-soc-bcm-brcmstb-add-stubs-for-getting-platform-IDs.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 149ae80b1d50e7db5ac7df1cdf0820017b70e716 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 14 Jan 2021 11:53:18 +0100 -Subject: [PATCH] soc: bcm: brcmstb: add stubs for getting platform IDs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Some brcmstb drivers may be shared with other SoC families. E.g. the -same USB PHY block is shared by brcmstb and BCM4908. - -To avoid building brcmstb common code on non-brcmstb platforms we need -stubs for: -1. brcmstb_get_family_id() -2. brcmstb_get_product_id() -(to avoid "undefined reference to" errors). - -With this change PHY_BRCM_USB will not have to unconditionally select -SOC_BRCMSTB anymore. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - include/linux/soc/brcmstb/brcmstb.h | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/include/linux/soc/brcmstb/brcmstb.h -+++ b/include/linux/soc/brcmstb/brcmstb.h -@@ -2,6 +2,8 @@ - #ifndef __BRCMSTB_SOC_H - #define __BRCMSTB_SOC_H - -+#include -+ - static inline u32 BRCM_ID(u32 reg) - { - return reg >> 28 ? reg >> 16 : reg >> 8; -@@ -12,6 +14,8 @@ static inline u32 BRCM_REV(u32 reg) - return reg & 0xff; - } - -+#if IS_ENABLED(CONFIG_SOC_BRCMSTB) -+ - /* - * Helper functions for getting family or product id from the - * SoC driver. -@@ -19,4 +23,16 @@ static inline u32 BRCM_REV(u32 reg) - u32 brcmstb_get_family_id(void); - u32 brcmstb_get_product_id(void); - -+#else -+static inline u32 brcmstb_get_family_id(void) -+{ -+ return 0; -+} -+ -+static inline u32 brcmstb_get_product_id(void) -+{ -+ return 0; -+} -+#endif -+ - #endif /* __BRCMSTB_SOC_H */ diff --git a/target/linux/bcm4908/patches-5.10/085-v5.18-0001-dt-bindings-pinctrl-Add-binding-for-BCM4908-pinctrl.patch b/target/linux/bcm4908/patches-5.10/085-v5.18-0001-dt-bindings-pinctrl-Add-binding-for-BCM4908-pinctrl.patch deleted file mode 100644 index 0dcc112edb..0000000000 --- a/target/linux/bcm4908/patches-5.10/085-v5.18-0001-dt-bindings-pinctrl-Add-binding-for-BCM4908-pinctrl.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 7b5730f0ff24b0d7d1cb660a482384a807618a46 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 24 Jan 2022 11:22:42 +0100 -Subject: [PATCH] dt-bindings: pinctrl: Add binding for BCM4908 pinctrl -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's hardware block that is part of every SoC from BCM4908 family. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/20220124102243.14912-1-zajec5@gmail.com -Signed-off-by: Linus Walleij ---- - .../pinctrl/brcm,bcm4908-pinctrl.yaml | 72 +++++++++++++++++++ - MAINTAINERS | 7 ++ - 2 files changed, 79 insertions(+) - create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml -@@ -0,0 +1,72 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM4908 pin controller -+ -+maintainers: -+ - Rafał Miłecki -+ -+description: -+ Binding for pin controller present on BCM4908 family SoCs. -+ -+properties: -+ compatible: -+ const: brcm,bcm4908-pinctrl -+ -+ reg: -+ maxItems: 1 -+ -+patternProperties: -+ '-pins$': -+ type: object -+ $ref: pinmux-node.yaml# -+ -+ properties: -+ function: -+ enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8, -+ led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16, -+ led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24, -+ led_25, led_26, led_27, led_28, led_29, led_30, led_31, -+ hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr, -+ usb1_pwr ] -+ -+ groups: -+ minItems: 1 -+ maxItems: 2 -+ items: -+ enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a, -+ led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a, -+ led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b, -+ led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b, -+ led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a, -+ led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a, -+ led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a, -+ led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a, -+ led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a, -+ led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp, -+ nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp, -+ usb1_pwr_grp ] -+ -+allOf: -+ - $ref: pinctrl.yaml# -+ -+required: -+ - compatible -+ - reg -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ pinctrl@ff800560 { -+ compatible = "brcm,bcm4908-pinctrl"; -+ reg = <0xff800560 0x10>; -+ -+ led_0-a-pins { -+ function = "led_0"; -+ groups = "led_0_grp_a"; -+ }; -+ }; ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3436,6 +3436,13 @@ F: Documentation/devicetree/bindings/net - F: drivers/net/ethernet/broadcom/bcm4908_enet.* - F: drivers/net/ethernet/broadcom/unimac.h - -+BROADCOM BCM4908 PINMUX DRIVER -+M: Rafał Miłecki -+M: bcm-kernel-feedback-list@broadcom.com -+L: linux-gpio@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml -+ - BROADCOM BCM5301X ARM ARCHITECTURE - M: Hauke Mehrtens - M: Rafał Miłecki diff --git a/target/linux/bcm4908/patches-5.10/085-v5.18-0002-pinctrl-bcm-add-driver-for-BCM4908-pinmux.patch b/target/linux/bcm4908/patches-5.10/085-v5.18-0002-pinctrl-bcm-add-driver-for-BCM4908-pinmux.patch deleted file mode 100644 index bb2ae459e9..0000000000 --- a/target/linux/bcm4908/patches-5.10/085-v5.18-0002-pinctrl-bcm-add-driver-for-BCM4908-pinmux.patch +++ /dev/null @@ -1,629 +0,0 @@ -From f7e322d99f1180270fb4a3e1ae992b3116cfcf34 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 24 Jan 2022 11:22:43 +0100 -Subject: [PATCH] pinctrl: bcm: add driver for BCM4908 pinmux -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 has its own pins layout so it needs a custom binding and a Linux -driver. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20220124102243.14912-2-zajec5@gmail.com -Signed-off-by: Linus Walleij ---- - MAINTAINERS | 1 + - drivers/pinctrl/bcm/Kconfig | 14 + - drivers/pinctrl/bcm/Makefile | 1 + - drivers/pinctrl/bcm/pinctrl-bcm4908.c | 563 ++++++++++++++++++++++++++ - 4 files changed, 579 insertions(+) - create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm4908.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3442,6 +3442,7 @@ M: bcm-kernel-feedback-list@broadcom.com - L: linux-gpio@vger.kernel.org - S: Maintained - F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml -+F: drivers/pinctrl/bcm/pinctrl-bcm4908.c - - BROADCOM BCM5301X ARM ARCHITECTURE - M: Hauke Mehrtens ---- a/drivers/pinctrl/bcm/Kconfig -+++ b/drivers/pinctrl/bcm/Kconfig -@@ -29,6 +29,20 @@ config PINCTRL_BCM2835 - help - Say Y here to enable the Broadcom BCM2835 GPIO driver. - -+config PINCTRL_BCM4908 -+ tristate "Broadcom BCM4908 pinmux driver" -+ depends on OF && (ARCH_BCM4908 || COMPILE_TEST) -+ select PINMUX -+ select PINCONF -+ select GENERIC_PINCONF -+ select GENERIC_PINCTRL_GROUPS -+ select GENERIC_PINMUX_FUNCTIONS -+ default ARCH_BCM4908 -+ help -+ Driver for BCM4908 family SoCs with integrated pin controller. -+ -+ If compiled as module it will be called pinctrl-bcm4908. -+ - config PINCTRL_IPROC_GPIO - bool "Broadcom iProc GPIO (with PINCONF) driver" - depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) ---- a/drivers/pinctrl/bcm/Makefile -+++ b/drivers/pinctrl/bcm/Makefile -@@ -3,6 +3,7 @@ - - obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o - obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o -+obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o - obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o - obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o - obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o ---- /dev/null -+++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c -@@ -0,0 +1,560 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright (C) 2021 Rafał Miłecki */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../core.h" -+#include "../pinmux.h" -+ -+#define BCM4908_NUM_PINS 86 -+ -+#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00 -+#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04 -+#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08 -+#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12 -+#define BCM4908_TEST_PORT_COMMAND 0x0c -+#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021 -+ -+struct bcm4908_pinctrl { -+ struct device *dev; -+ void __iomem *base; -+ struct mutex mutex; -+ struct pinctrl_dev *pctldev; -+ struct pinctrl_desc pctldesc; -+}; -+ -+/* -+ * Groups -+ */ -+ -+struct bcm4908_pinctrl_pin_setup { -+ unsigned int number; -+ unsigned int function; -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = { -+ { 0, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = { -+ { 1, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = { -+ { 2, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = { -+ { 3, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = { -+ { 4, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = { -+ { 5, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = { -+ { 6, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = { -+ { 7, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = { -+ { 8, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = { -+ { 9, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = { -+ { 10, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = { -+ { 11, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = { -+ { 12, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = { -+ { 13, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = { -+ { 14, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = { -+ { 15, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = { -+ { 16, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = { -+ { 17, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = { -+ { 18, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = { -+ { 19, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = { -+ { 20, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = { -+ { 21, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = { -+ { 22, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = { -+ { 23, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = { -+ { 24, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = { -+ { 25, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = { -+ { 26, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = { -+ { 27, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = { -+ { 28, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = { -+ { 29, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = { -+ { 30, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = { -+ { 31, 3 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = { -+ { 8, 2 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = { -+ { 9, 2 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = { -+ { 0, 2 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = { -+ { 1, 2 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = { -+ { 30, 2 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = { -+ { 10, 0 }, /* CTS */ -+ { 11, 0 }, /* RTS */ -+ { 12, 0 }, /* RXD */ -+ { 13, 0 }, /* TXD */ -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = { -+ { 18, 0 }, /* SDA */ -+ { 19, 0 }, /* SCL */ -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = { -+ { 22, 0 }, /* SDA */ -+ { 23, 0 }, /* SCL */ -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = { -+ { 27, 0 }, /* MCLK */ -+ { 28, 0 }, /* LRCK */ -+ { 29, 0 }, /* SDATA */ -+ { 30, 0 }, /* SCLK */ -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = { -+ { 32, 0 }, -+ { 33, 0 }, -+ { 34, 0 }, -+ { 43, 0 }, -+ { 44, 0 }, -+ { 45, 0 }, -+ { 56, 1 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = { -+ { 35, 0 }, -+ { 36, 0 }, -+ { 37, 0 }, -+ { 38, 0 }, -+ { 39, 0 }, -+ { 40, 0 }, -+ { 41, 0 }, -+ { 42, 0 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = { -+ { 46, 0 }, -+ { 47, 0 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = { -+ { 63, 0 }, -+ { 64, 0 }, -+}; -+ -+static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = { -+ { 66, 0 }, -+ { 67, 0 }, -+}; -+ -+struct bcm4908_pinctrl_grp { -+ const char *name; -+ const struct bcm4908_pinctrl_pin_setup *pins; -+ const unsigned int num_pins; -+}; -+ -+static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = { -+ { "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) }, -+ { "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) }, -+ { "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) }, -+ { "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) }, -+ { "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) }, -+ { "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) }, -+ { "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) }, -+ { "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) }, -+ { "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) }, -+ { "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) }, -+ { "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) }, -+ { "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) }, -+ { "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) }, -+ { "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) }, -+ { "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) }, -+ { "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) }, -+ { "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) }, -+ { "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) }, -+ { "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) }, -+ { "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) }, -+ { "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) }, -+ { "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) }, -+ { "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) }, -+ { "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) }, -+ { "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) }, -+ { "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) }, -+ { "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) }, -+ { "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) }, -+ { "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) }, -+ { "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) }, -+ { "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) }, -+ { "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) }, -+ { "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) }, -+ { "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) }, -+ { "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) }, -+ { "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) }, -+ { "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) }, -+ { "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) }, -+ { "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) }, -+ { "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) }, -+ { "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) }, -+ { "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) }, -+ { "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) }, -+ { "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) }, -+ { "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) }, -+ { "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) }, -+}; -+ -+/* -+ * Functions -+ */ -+ -+struct bcm4908_pinctrl_function { -+ const char *name; -+ const char * const *groups; -+ const unsigned int num_groups; -+}; -+ -+static const char * const led_0_groups[] = { "led_0_grp_a" }; -+static const char * const led_1_groups[] = { "led_1_grp_a" }; -+static const char * const led_2_groups[] = { "led_2_grp_a" }; -+static const char * const led_3_groups[] = { "led_3_grp_a" }; -+static const char * const led_4_groups[] = { "led_4_grp_a" }; -+static const char * const led_5_groups[] = { "led_5_grp_a" }; -+static const char * const led_6_groups[] = { "led_6_grp_a" }; -+static const char * const led_7_groups[] = { "led_7_grp_a" }; -+static const char * const led_8_groups[] = { "led_8_grp_a" }; -+static const char * const led_9_groups[] = { "led_9_grp_a" }; -+static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" }; -+static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" }; -+static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" }; -+static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" }; -+static const char * const led_14_groups[] = { "led_14_grp_a" }; -+static const char * const led_15_groups[] = { "led_15_grp_a" }; -+static const char * const led_16_groups[] = { "led_16_grp_a" }; -+static const char * const led_17_groups[] = { "led_17_grp_a" }; -+static const char * const led_18_groups[] = { "led_18_grp_a" }; -+static const char * const led_19_groups[] = { "led_19_grp_a" }; -+static const char * const led_20_groups[] = { "led_20_grp_a" }; -+static const char * const led_21_groups[] = { "led_21_grp_a" }; -+static const char * const led_22_groups[] = { "led_22_grp_a" }; -+static const char * const led_23_groups[] = { "led_23_grp_a" }; -+static const char * const led_24_groups[] = { "led_24_grp_a" }; -+static const char * const led_25_groups[] = { "led_25_grp_a" }; -+static const char * const led_26_groups[] = { "led_26_grp_a" }; -+static const char * const led_27_groups[] = { "led_27_grp_a" }; -+static const char * const led_28_groups[] = { "led_28_grp_a" }; -+static const char * const led_29_groups[] = { "led_29_grp_a" }; -+static const char * const led_30_groups[] = { "led_30_grp_a" }; -+static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" }; -+static const char * const hs_uart_groups[] = { "hs_uart_grp" }; -+static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" }; -+static const char * const i2s_groups[] = { "i2s_grp" }; -+static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" }; -+static const char * const nand_data_groups[] = { "nand_data_grp" }; -+static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" }; -+static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" }; -+static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" }; -+ -+static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = { -+ { "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) }, -+ { "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) }, -+ { "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) }, -+ { "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) }, -+ { "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) }, -+ { "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) }, -+ { "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) }, -+ { "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) }, -+ { "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) }, -+ { "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) }, -+ { "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) }, -+ { "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) }, -+ { "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) }, -+ { "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) }, -+ { "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) }, -+ { "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) }, -+ { "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) }, -+ { "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) }, -+ { "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) }, -+ { "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) }, -+ { "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) }, -+ { "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) }, -+ { "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) }, -+ { "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) }, -+ { "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) }, -+ { "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) }, -+ { "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) }, -+ { "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) }, -+ { "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) }, -+ { "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) }, -+ { "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) }, -+ { "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) }, -+ { "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) }, -+ { "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) }, -+ { "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) }, -+ { "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) }, -+ { "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) }, -+ { "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) }, -+ { "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) }, -+ { "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) }, -+}; -+ -+/* -+ * Groups code -+ */ -+ -+static const struct pinctrl_ops bcm4908_pinctrl_ops = { -+ .get_groups_count = pinctrl_generic_get_group_count, -+ .get_group_name = pinctrl_generic_get_group_name, -+ .get_group_pins = pinctrl_generic_get_group_pins, -+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group, -+ .dt_free_map = pinconf_generic_dt_free_map, -+}; -+ -+/* -+ * Functions code -+ */ -+ -+static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, -+ unsigned int func_selector, -+ unsigned int group_selector) -+{ -+ struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); -+ const struct bcm4908_pinctrl_grp *group; -+ struct group_desc *group_desc; -+ int i; -+ -+ group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector); -+ if (!group_desc) -+ return -EINVAL; -+ group = group_desc->data; -+ -+ mutex_lock(&bcm4908_pinctrl->mutex); -+ for (i = 0; i < group->num_pins; i++) { -+ u32 lsb = 0; -+ -+ lsb |= group->pins[i].number; -+ lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT; -+ -+ writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB); -+ writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB); -+ writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG, -+ bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND); -+ } -+ mutex_unlock(&bcm4908_pinctrl->mutex); -+ -+ return 0; -+} -+ -+static const struct pinmux_ops bcm4908_pinctrl_pmxops = { -+ .get_functions_count = pinmux_generic_get_function_count, -+ .get_function_name = pinmux_generic_get_function_name, -+ .get_function_groups = pinmux_generic_get_function_groups, -+ .set_mux = bcm4908_pinctrl_set_mux, -+}; -+ -+/* -+ * Controller code -+ */ -+ -+static struct pinctrl_desc bcm4908_pinctrl_desc = { -+ .name = "bcm4908-pinctrl", -+ .pctlops = &bcm4908_pinctrl_ops, -+ .pmxops = &bcm4908_pinctrl_pmxops, -+}; -+ -+static const struct of_device_id bcm4908_pinctrl_of_match_table[] = { -+ { .compatible = "brcm,bcm4908-pinctrl", }, -+ { } -+}; -+ -+static int bcm4908_pinctrl_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct bcm4908_pinctrl *bcm4908_pinctrl; -+ struct pinctrl_desc *pctldesc; -+ struct pinctrl_pin_desc *pins; -+ int i; -+ -+ bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL); -+ if (!bcm4908_pinctrl) -+ return -ENOMEM; -+ pctldesc = &bcm4908_pinctrl->pctldesc; -+ platform_set_drvdata(pdev, bcm4908_pinctrl); -+ -+ /* Set basic properties */ -+ -+ bcm4908_pinctrl->dev = dev; -+ -+ bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(bcm4908_pinctrl->base)) -+ return PTR_ERR(bcm4908_pinctrl->base); -+ -+ mutex_init(&bcm4908_pinctrl->mutex); -+ -+ memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc)); -+ -+ /* Set pinctrl properties */ -+ -+ pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL); -+ if (!pins) -+ return -ENOMEM; -+ for (i = 0; i < BCM4908_NUM_PINS; i++) { -+ pins[i].number = i; -+ pins[i].name = devm_kasprintf(dev, GFP_KERNEL, "pin-%d", i); -+ if (!pins[i].name) -+ return -ENOMEM; -+ } -+ pctldesc->pins = pins; -+ pctldesc->npins = BCM4908_NUM_PINS; -+ -+ /* Register */ -+ -+ bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl); -+ if (IS_ERR(bcm4908_pinctrl->pctldev)) -+ return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev), -+ "Failed to register pinctrl\n"); -+ -+ /* Groups */ -+ -+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) { -+ const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i]; -+ int *pins; -+ int j; -+ -+ pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL); -+ if (!pins) -+ return -ENOMEM; -+ for (j = 0; j < group->num_pins; j++) -+ pins[j] = group->pins[j].number; -+ -+ pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name, -+ pins, group->num_pins, (void *)group); -+ } -+ -+ /* Functions */ -+ -+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) { -+ const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i]; -+ -+ pinmux_generic_add_function(bcm4908_pinctrl->pctldev, -+ function->name, -+ function->groups, -+ function->num_groups, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver bcm4908_pinctrl_driver = { -+ .probe = bcm4908_pinctrl_probe, -+ .driver = { -+ .name = "bcm4908-pinctrl", -+ .of_match_table = bcm4908_pinctrl_of_match_table, -+ }, -+}; -+ -+module_platform_driver(bcm4908_pinctrl_driver); -+ -+MODULE_AUTHOR("Rafał Miłecki"); -+MODULE_LICENSE("GPL v2"); -+MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table); diff --git a/target/linux/bcm4908/patches-5.10/086-v5.12-0001-phy-phy-brcm-usb-improve-getting-OF-matching-data.patch b/target/linux/bcm4908/patches-5.10/086-v5.12-0001-phy-phy-brcm-usb-improve-getting-OF-matching-data.patch deleted file mode 100644 index ec9b1fea3d..0000000000 --- a/target/linux/bcm4908/patches-5.10/086-v5.12-0001-phy-phy-brcm-usb-improve-getting-OF-matching-data.patch +++ /dev/null @@ -1,49 +0,0 @@ -From d14f4cce9340a6586512a0eb6bc680dedeaaef14 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 16 Dec 2020 15:33:04 +0100 -Subject: [PATCH] phy: phy-brcm-usb: improve getting OF matching data -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. Use of_device_get_match_data() helper to simplify the code -2. Check for NULL as a good practice - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20201216143305.12179-1-zajec5@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/broadcom/phy-brcm-usb.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - ---- a/drivers/phy/broadcom/phy-brcm-usb.c -+++ b/drivers/phy/broadcom/phy-brcm-usb.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -457,7 +458,6 @@ static int brcm_usb_phy_probe(struct pla - struct device_node *dn = pdev->dev.of_node; - int err; - const char *mode; -- const struct of_device_id *match; - void (*dvr_init)(struct brcm_usb_init_params *params); - const struct match_chip_info *info; - struct regmap *rmap; -@@ -471,8 +471,9 @@ static int brcm_usb_phy_probe(struct pla - priv->ini.family_id = brcmstb_get_family_id(); - priv->ini.product_id = brcmstb_get_product_id(); - -- match = of_match_node(brcm_usb_dt_ids, dev->of_node); -- info = match->data; -+ info = of_device_get_match_data(&pdev->dev); -+ if (!info) -+ return -ENOENT; - dvr_init = info->init_func; - (*dvr_init)(&priv->ini); - diff --git a/target/linux/bcm4908/patches-5.10/086-v5.12-0002-phy-phy-brcm-usb-specify-init-function-format-at-str.patch b/target/linux/bcm4908/patches-5.10/086-v5.12-0002-phy-phy-brcm-usb-specify-init-function-format-at-str.patch deleted file mode 100644 index ffb064f95f..0000000000 --- a/target/linux/bcm4908/patches-5.10/086-v5.12-0002-phy-phy-brcm-usb-specify-init-function-format-at-str.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 915f1d230e5292bc2156a9997bcb19d9e632f10b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 16 Dec 2020 15:33:05 +0100 -Subject: [PATCH] phy: phy-brcm-usb: specify init function format at struct - level -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This is slightly cleaner solution that assures noone assings a wrong -function to the pointer. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20201216143305.12179-2-zajec5@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/broadcom/phy-brcm-usb.c | 7 +++---- - 1 file changed, 3 insertions(+), 4 deletions(-) - ---- a/drivers/phy/broadcom/phy-brcm-usb.c -+++ b/drivers/phy/broadcom/phy-brcm-usb.c -@@ -36,7 +36,7 @@ struct value_to_name_map { - }; - - struct match_chip_info { -- void *init_func; -+ void (*init_func)(struct brcm_usb_init_params *params); - u8 required_regs[BRCM_REGS_MAX + 1]; - u8 optional_reg; - }; -@@ -458,7 +458,6 @@ static int brcm_usb_phy_probe(struct pla - struct device_node *dn = pdev->dev.of_node; - int err; - const char *mode; -- void (*dvr_init)(struct brcm_usb_init_params *params); - const struct match_chip_info *info; - struct regmap *rmap; - int x; -@@ -474,8 +473,8 @@ static int brcm_usb_phy_probe(struct pla - info = of_device_get_match_data(&pdev->dev); - if (!info) - return -ENOENT; -- dvr_init = info->init_func; -- (*dvr_init)(&priv->ini); -+ -+ info->init_func(&priv->ini); - - dev_dbg(dev, "Best mapping table is for %s\n", - priv->ini.family_name); diff --git a/target/linux/bcm4908/patches-5.10/086-v5.12-0003-dt-bindings-phy-brcm-brcmstb-usb-phy-convert-to-the-.patch b/target/linux/bcm4908/patches-5.10/086-v5.12-0003-dt-bindings-phy-brcm-brcmstb-usb-phy-convert-to-the-.patch deleted file mode 100644 index 1edd63ea5d..0000000000 --- a/target/linux/bcm4908/patches-5.10/086-v5.12-0003-dt-bindings-phy-brcm-brcmstb-usb-phy-convert-to-the-.patch +++ /dev/null @@ -1,315 +0,0 @@ -From b39069a482ade0c5e18c407c3218ba1aeed371b6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 6 Jan 2021 21:58:36 +0100 -Subject: [PATCH] dt-bindings: phy: brcm, brcmstb-usb-phy: convert to the - json-schema -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Changes that require mentioning: -1. interrupt-names - Name "wakeup" was changed to the "wake". It matches example and what - Linux driver looks for in the first place -2. brcm,ipp and brcm,ioc - Both were described as booleans with 0 / 1 values. In examples they - were integers and Linux checks for int as well. Both got uint32. -3. Added minimal description - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/20210106205838.10964-1-zajec5@gmail.com -Signed-off-by: Vinod Koul ---- - .../bindings/phy/brcm,brcmstb-usb-phy.txt | 86 -------- - .../bindings/phy/brcm,brcmstb-usb-phy.yaml | 193 ++++++++++++++++++ - 2 files changed, 193 insertions(+), 86 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt - create mode 100644 Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml - ---- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt -+++ /dev/null -@@ -1,86 +0,0 @@ --Broadcom STB USB PHY -- --Required properties: --- compatible: should be one of -- "brcm,brcmstb-usb-phy" -- "brcm,bcm7216-usb-phy" -- "brcm,bcm7211-usb-phy" -- --- reg and reg-names properties requirements are specific to the -- compatible string. -- "brcm,brcmstb-usb-phy": -- - reg: 1 or 2 offset and length pairs. One for the base CTRL registers -- and an optional pair for systems with USB 3.x support -- - reg-names: not specified -- "brcm,bcm7216-usb-phy": -- - reg: 3 offset and length pairs for CTRL, XHCI_EC and XHCI_GBL -- registers -- - reg-names: "ctrl", "xhci_ec", "xhci_gbl" -- "brcm,bcm7211-usb-phy": -- - reg: 5 offset and length pairs for CTRL, XHCI_EC, XHCI_GBL, -- USB_PHY and USB_MDIO registers and an optional pair -- for the BDC registers -- - reg-names: "ctrl", "xhci_ec", "xhci_gbl", "usb_phy", "usb_mdio", "bdc_ec" -- --- #phy-cells: Shall be 1 as it expects one argument for setting -- the type of the PHY. Possible values are: -- - PHY_TYPE_USB2 for USB1.1/2.0 PHY -- - PHY_TYPE_USB3 for USB3.x PHY -- --Optional Properties: --- clocks : clock phandles. --- clock-names: String, clock name. --- interrupts: wakeup interrupt --- interrupt-names: "wakeup" --- brcm,ipp: Boolean, Invert Port Power. -- Possible values are: 0 (Don't invert), 1 (Invert) --- brcm,ioc: Boolean, Invert Over Current detection. -- Possible values are: 0 (Don't invert), 1 (Invert) --- dr_mode: String, PHY Device mode. -- Possible values are: "host", "peripheral ", "drd" or "typec-pd" -- If this property is not defined, the phy will default to "host" mode. --- brcm,syscon-piarbctl: phandle to syscon for handling config registers --NOTE: one or both of the following two properties must be set --- brcm,has-xhci: Boolean indicating the phy has an XHCI phy. --- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy. -- -- --Example: -- --usbphy_0: usb-phy@f0470200 { -- reg = <0xf0470200 0xb8>, -- <0xf0471940 0x6c0>; -- compatible = "brcm,brcmstb-usb-phy"; -- #phy-cells = <1>; -- dr_mode = "host" -- brcm,ioc = <1>; -- brcm,ipp = <1>; -- brcm,has-xhci; -- brcm,has-eohci; -- clocks = <&usb20>, <&usb30>; -- clock-names = "sw_usb", "sw_usb3"; --}; -- --usb-phy@29f0200 { -- reg = <0x29f0200 0x200>, -- <0x29c0880 0x30>, -- <0x29cc100 0x534>, -- <0x2808000 0x24>, -- <0x2980080 0x8>; -- reg-names = "ctrl", -- "xhci_ec", -- "xhci_gbl", -- "usb_phy", -- "usb_mdio"; -- brcm,ioc = <0x0>; -- brcm,ipp = <0x0>; -- compatible = "brcm,bcm7211-usb-phy"; -- interrupts = <0x30>; -- interrupt-parent = <&vpu_intr1_nosec_intc>; -- interrupt-names = "wake"; -- #phy-cells = <0x1>; -- brcm,has-xhci; -- syscon-piarbctl = <&syscon_piarbctl>; -- clocks = <&scmi_clk 256>; -- clock-names = "sw_usb"; --}; ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml -@@ -0,0 +1,193 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/phy/brcm,brcmstb-usb-phy.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom STB USB PHY -+ -+description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI -+ -+maintainers: -+ - Al Cooper -+ - Rafał Miłecki -+ -+properties: -+ compatible: -+ enum: -+ - brcm,bcm7211-usb-phy -+ - brcm,bcm7216-usb-phy -+ - brcm,brcmstb-usb-phy -+ -+ reg: -+ minItems: 1 -+ maxItems: 6 -+ items: -+ - description: the base CTRL register -+ - description: XHCI EC register -+ - description: XHCI GBL register -+ - description: USB PHY register -+ - description: USB MDIO register -+ - description: BDC register -+ -+ reg-names: -+ minItems: 1 -+ maxItems: 6 -+ items: -+ - const: ctrl -+ - const: xhci_ec -+ - const: xhci_gbl -+ - const: usb_phy -+ - const: usb_mdio -+ - const: bdc_ec -+ -+ clocks: -+ minItems: 1 -+ maxItems: 2 -+ -+ clock-names: -+ minItems: 1 -+ maxItems: 2 -+ items: -+ - const: sw_usb -+ - const: sw_usb3 -+ -+ interrupts: -+ description: wakeup interrupt -+ -+ interrupt-names: -+ const: wake -+ -+ brcm,ipp: -+ $ref: /schemas/types.yaml#/definitions/uint32 -+ description: Invert Port Power -+ minimum: 0 -+ maximum: 1 -+ -+ brcm,ioc: -+ $ref: /schemas/types.yaml#/definitions/uint32 -+ description: Invert Over Current detection -+ minimum: 0 -+ maximum: 1 -+ -+ dr_mode: -+ description: PHY Device mode. If this property is not defined, the PHY will -+ default to "host" mode. -+ enum: -+ - host -+ - peripheral -+ - drd -+ - typec-pd -+ -+ brcm,syscon-piarbctl: -+ description: phandle to syscon for handling config registers -+ $ref: /schemas/types.yaml#/definitions/phandle -+ -+ brcm,has-xhci: -+ description: Indicates the PHY has an XHCI PHY. -+ type: boolean -+ -+ brcm,has-eohci: -+ description: Indicates the PHY has an EHCI/OHCI PHY. -+ type: boolean -+ -+ "#phy-cells": -+ description: | -+ Cell allows setting the type of the PHY. Possible values are: -+ - PHY_TYPE_USB2 for USB1.1/2.0 PHY -+ - PHY_TYPE_USB3 for USB3.x PHY -+ const: 1 -+ -+required: -+ - reg -+ - "#phy-cells" -+ -+anyOf: -+ - required: -+ - brcm,has-xhci -+ - required: -+ - brcm,has-eohci -+ -+allOf: -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: brcm,brcmstb-usb-phy -+ then: -+ properties: -+ reg: -+ minItems: 1 -+ maxItems: 2 -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: brcm,bcm7211-usb-phy -+ then: -+ properties: -+ reg: -+ minItems: 5 -+ maxItems: 6 -+ reg-names: -+ minItems: 5 -+ maxItems: 6 -+ - if: -+ properties: -+ compatible: -+ contains: -+ const: brcm,bcm7216-usb-phy -+ then: -+ properties: -+ reg: -+ minItems: 3 -+ maxItems: 3 -+ reg-names: -+ minItems: 3 -+ maxItems: 3 -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ -+ usb-phy@f0470200 { -+ compatible = "brcm,brcmstb-usb-phy"; -+ reg = <0xf0470200 0xb8>, -+ <0xf0471940 0x6c0>; -+ #phy-cells = <1>; -+ dr_mode = "host"; -+ brcm,ioc = <1>; -+ brcm,ipp = <1>; -+ brcm,has-xhci; -+ brcm,has-eohci; -+ clocks = <&usb20>, <&usb30>; -+ clock-names = "sw_usb", "sw_usb3"; -+ }; -+ - | -+ #include -+ -+ usb-phy@29f0200 { -+ compatible = "brcm,bcm7211-usb-phy"; -+ reg = <0x29f0200 0x200>, -+ <0x29c0880 0x30>, -+ <0x29cc100 0x534>, -+ <0x2808000 0x24>, -+ <0x2980080 0x8>; -+ reg-names = "ctrl", -+ "xhci_ec", -+ "xhci_gbl", -+ "usb_phy", -+ "usb_mdio"; -+ brcm,ioc = <0x0>; -+ brcm,ipp = <0x0>; -+ interrupts = <0x30>; -+ interrupt-parent = <&vpu_intr1_nosec_intc>; -+ interrupt-names = "wake"; -+ #phy-cells = <0x1>; -+ brcm,has-xhci; -+ brcm,syscon-piarbctl = <&syscon_piarbctl>; -+ clocks = <&scmi_clk 256>; -+ clock-names = "sw_usb"; -+ }; diff --git a/target/linux/bcm4908/patches-5.10/086-v5.12-0004-dt-bindings-phy-brcm-brcmstb-usb-phy-add-BCM4908-bin.patch b/target/linux/bcm4908/patches-5.10/086-v5.12-0004-dt-bindings-phy-brcm-brcmstb-usb-phy-add-BCM4908-bin.patch deleted file mode 100644 index 6127800a43..0000000000 --- a/target/linux/bcm4908/patches-5.10/086-v5.12-0004-dt-bindings-phy-brcm-brcmstb-usb-phy-add-BCM4908-bin.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 46b616c1574def7a1629bdeded3d44e76382f950 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 6 Jan 2021 21:58:37 +0100 -Subject: [PATCH] dt-bindings: phy: brcm, brcmstb-usb-phy: add BCM4908 binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 uses the same PHY and may require just a slightly different -programming. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20210106205838.10964-2-zajec5@gmail.com -Signed-off-by: Vinod Koul ---- - .../devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml -+++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml -@@ -15,6 +15,7 @@ maintainers: - properties: - compatible: - enum: -+ - brcm,bcm4908-usb-phy - - brcm,bcm7211-usb-phy - - brcm,bcm7216-usb-phy - - brcm,brcmstb-usb-phy -@@ -113,7 +114,9 @@ allOf: - properties: - compatible: - contains: -- const: brcm,brcmstb-usb-phy -+ enum: -+ - const: brcm,bcm4908-usb-phy -+ - const: brcm,brcmstb-usb-phy - then: - properties: - reg: diff --git a/target/linux/bcm4908/patches-5.10/086-v5.12-0005-phy-phy-brcm-usb-support-PHY-on-the-BCM4908.patch b/target/linux/bcm4908/patches-5.10/086-v5.12-0005-phy-phy-brcm-usb-support-PHY-on-the-BCM4908.patch deleted file mode 100644 index 362738c802..0000000000 --- a/target/linux/bcm4908/patches-5.10/086-v5.12-0005-phy-phy-brcm-usb-support-PHY-on-the-BCM4908.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 4b402fa8e0b7817f3e3738d7828038f114e6899e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 6 Jan 2021 21:58:38 +0100 -Subject: [PATCH] phy: phy-brcm-usb: support PHY on the BCM4908 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 seems to have slightly different registers but works when -programmed just like the STB one. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20210106205838.10964-3-zajec5@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/broadcom/Kconfig | 3 ++- - drivers/phy/broadcom/phy-brcm-usb.c | 4 ++++ - 2 files changed, 6 insertions(+), 1 deletion(-) - ---- a/drivers/phy/broadcom/Kconfig -+++ b/drivers/phy/broadcom/Kconfig -@@ -91,10 +91,11 @@ config PHY_BRCM_SATA - - config PHY_BRCM_USB - tristate "Broadcom STB USB PHY driver" -- depends on ARCH_BRCMSTB || COMPILE_TEST -+ depends on ARCH_BCM4908 || ARCH_BRCMSTB || COMPILE_TEST - depends on OF - select GENERIC_PHY - select SOC_BRCMSTB -+ default ARCH_BCM4908 - default ARCH_BRCMSTB - help - Enable this to support the Broadcom STB USB PHY. ---- a/drivers/phy/broadcom/phy-brcm-usb.c -+++ b/drivers/phy/broadcom/phy-brcm-usb.c -@@ -317,6 +317,10 @@ static const struct match_chip_info chip - - static const struct of_device_id brcm_usb_dt_ids[] = { - { -+ .compatible = "brcm,bcm4908-usb-phy", -+ .data = &chip_info_7445, -+ }, -+ { - .compatible = "brcm,bcm7216-usb-phy", - .data = &chip_info_7216, - }, diff --git a/target/linux/bcm4908/patches-5.10/086-v5.13-0001-phy-phy-brcm-usb-select-SOC_BRCMSTB-on-brcmstb-only.patch b/target/linux/bcm4908/patches-5.10/086-v5.13-0001-phy-phy-brcm-usb-select-SOC_BRCMSTB-on-brcmstb-only.patch deleted file mode 100644 index 89ee4df78c..0000000000 --- a/target/linux/bcm4908/patches-5.10/086-v5.13-0001-phy-phy-brcm-usb-select-SOC_BRCMSTB-on-brcmstb-only.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 261ab1fd5c5d2d7ff7d5bab3f5db3c69c4bcea58 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 5 Mar 2021 16:24:06 +0100 -Subject: [PATCH] phy: phy-brcm-usb: select SOC_BRCMSTB on brcmstb only -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -phy-brcm-usb has some conditional init code required on selected brcmstb -devices. Execution of that code depends on family / product detected by -brcmstb soc code. - -For ARCH_BCM4908 brcmstb soc code always return 0 values as ids. Don't -bother selecting & compiling that redundant driver. - -Depends-on: 149ae80b1d50 ("soc: bcm: brcmstb: add stubs for getting platform IDs") -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20210305152406.2588-1-zajec5@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/broadcom/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/phy/broadcom/Kconfig -+++ b/drivers/phy/broadcom/Kconfig -@@ -94,7 +94,7 @@ config PHY_BRCM_USB - depends on ARCH_BCM4908 || ARCH_BRCMSTB || COMPILE_TEST - depends on OF - select GENERIC_PHY -- select SOC_BRCMSTB -+ select SOC_BRCMSTB if ARCH_BRCMSTB - default ARCH_BCM4908 - default ARCH_BRCMSTB - help diff --git a/target/linux/bcm4908/patches-5.10/086-v5.13-0002-dt-bindings-phy-brcm-brcmstb-usb-phy-add-power-domai.patch b/target/linux/bcm4908/patches-5.10/086-v5.13-0002-dt-bindings-phy-brcm-brcmstb-usb-phy-add-power-domai.patch deleted file mode 100644 index 4db442c0ae..0000000000 --- a/target/linux/bcm4908/patches-5.10/086-v5.13-0002-dt-bindings-phy-brcm-brcmstb-usb-phy-add-power-domai.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d9de0cbd5b1f6b51c92a40937945f26a35d848ff Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 9 Mar 2021 19:26:16 +0100 -Subject: [PATCH] dt-bindings: phy: brcm,brcmstb-usb-phy: add power-domains -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -On BCM4908 USB PHY is managed using power controller so it needs -describing properly using the power-domains. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Link: https://lore.kernel.org/r/20210309182616.25783-1-zajec5@gmail.com -Signed-off-by: Vinod Koul ---- - .../devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml -+++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml -@@ -42,6 +42,9 @@ properties: - - const: usb_mdio - - const: bdc_ec - -+ power-domains: -+ maxItems: 1 -+ - clocks: - minItems: 1 - maxItems: 2 diff --git a/target/linux/bcm4908/patches-5.10/087-v5.18-0001-i2c-brcmstb-allow-compiling-on-BCM4908.patch b/target/linux/bcm4908/patches-5.10/087-v5.18-0001-i2c-brcmstb-allow-compiling-on-BCM4908.patch deleted file mode 100644 index 246f249413..0000000000 --- a/target/linux/bcm4908/patches-5.10/087-v5.18-0001-i2c-brcmstb-allow-compiling-on-BCM4908.patch +++ /dev/null @@ -1,30 +0,0 @@ -From d0aee048d648ec2d9aa7af43b127ebf847d497d5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 11 Feb 2022 11:58:06 +0100 -Subject: [PATCH] i2c: brcmstb: allow compiling on BCM4908 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 SoCs use the same I2C hardware block as STB and BCM63xx devices. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/Kconfig | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -477,8 +477,8 @@ config I2C_BCM_KONA - - config I2C_BRCMSTB - tristate "BRCM Settop/DSL I2C controller" -- depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || \ -- ARCH_BCM_63XX || COMPILE_TEST -+ depends on ARCH_BCM2835 || ARCH_BCM4908 || ARCH_BCM_63XX || \ -+ ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST - default y - help - If you say yes to this option, support will be included for the diff --git a/target/linux/bcm4908/patches-5.10/088-v5.18-phy-phy-brcm-usb-fixup-BCM4908-support.patch b/target/linux/bcm4908/patches-5.10/088-v5.18-phy-phy-brcm-usb-fixup-BCM4908-support.patch deleted file mode 100644 index 4d39f646e1..0000000000 --- a/target/linux/bcm4908/patches-5.10/088-v5.18-phy-phy-brcm-usb-fixup-BCM4908-support.patch +++ /dev/null @@ -1,147 +0,0 @@ -From 32942d33d63d27714ed16a4176e5a99547adb6e0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 18 Feb 2022 18:24:59 +0100 -Subject: [PATCH] phy: phy-brcm-usb: fixup BCM4908 support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Just like every other family BCM4908 should get its own enum value. That -is required to properly handle it in chipset conditional code. - -The real change is excluding BCM4908 from the PLL reprogramming code -(see brcmusb_usb3_pll_54mhz()). I'm not sure what's the BCM4908 -reference clock frequency but: -1. BCM4908 custom driver from Broadcom's SDK doesn't reprogram PLL -2. Doing that in Linux driver stopped PHY handling some USB 3.0 devices - -This change makes USB 3.0 PHY recognize e.g.: -1. 04e8:6860 - Samsung Electronics Co., Ltd Galaxy series, misc. (MTP mode) -2. 1058:259f - Western Digital My Passport 259F - -Broadcom's STB SoCs come with a set of SUN_TOP_CTRL_* registers that -allow reading chip family and product ids. Such a block & register is -missing on BCM4908 so this commit introduces "compatible" string -specific binding. - -Fixes: 4b402fa8e0b7 ("phy: phy-brcm-usb: support PHY on the BCM4908") -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Link: https://lore.kernel.org/r/20220218172459.10431-1-zajec5@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/broadcom/phy-brcm-usb-init.c | 36 ++++++++++++++++++++++++ - drivers/phy/broadcom/phy-brcm-usb-init.h | 1 + - drivers/phy/broadcom/phy-brcm-usb.c | 11 +++++++- - 3 files changed, 47 insertions(+), 1 deletion(-) - ---- a/drivers/phy/broadcom/phy-brcm-usb-init.c -+++ b/drivers/phy/broadcom/phy-brcm-usb-init.c -@@ -79,6 +79,7 @@ - - enum brcm_family_type { - BRCM_FAMILY_3390A0, -+ BRCM_FAMILY_4908, - BRCM_FAMILY_7250B0, - BRCM_FAMILY_7271A0, - BRCM_FAMILY_7364A0, -@@ -96,6 +97,7 @@ enum brcm_family_type { - - static const char *family_names[BRCM_FAMILY_COUNT] = { - USB_BRCM_FAMILY(3390A0), -+ USB_BRCM_FAMILY(4908), - USB_BRCM_FAMILY(7250B0), - USB_BRCM_FAMILY(7271A0), - USB_BRCM_FAMILY(7364A0), -@@ -203,6 +205,27 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT - USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK, - ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */ - }, -+ /* 4908 */ -+ [BRCM_FAMILY_4908] = { -+ 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */ -+ 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */ -+ 0, /* USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */ -+ 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */ -+ 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */ -+ 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */ -+ 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */ -+ USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK, -+ USB_CTRL_USB_PM_USB_PWRDN_MASK, -+ 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */ -+ 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */ -+ 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */ -+ 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */ -+ 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */ -+ 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */ -+ 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */ -+ 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK */ -+ 0, /* USB_CTRL_SETUP ENDIAN bits */ -+ }, - /* 7250b0 */ - [BRCM_FAMILY_7250B0] = { - USB_CTRL_SETUP_SCB1_EN_MASK, -@@ -559,6 +582,7 @@ static void brcmusb_usb3_pll_54mhz(struc - */ - switch (params->selected_family) { - case BRCM_FAMILY_3390A0: -+ case BRCM_FAMILY_4908: - case BRCM_FAMILY_7250B0: - case BRCM_FAMILY_7366C0: - case BRCM_FAMILY_74371A0: -@@ -1004,6 +1028,18 @@ static const struct brcm_usb_init_ops bc - .set_dual_select = usb_set_dual_select, - }; - -+void brcm_usb_dvr_init_4908(struct brcm_usb_init_params *params) -+{ -+ int fam; -+ -+ fam = BRCM_FAMILY_4908; -+ params->selected_family = fam; -+ params->usb_reg_bits_map = -+ &usb_reg_bits_map_table[fam][0]; -+ params->family_name = family_names[fam]; -+ params->ops = &bcm7445_ops; -+} -+ - void brcm_usb_dvr_init_7445(struct brcm_usb_init_params *params) - { - int fam; ---- a/drivers/phy/broadcom/phy-brcm-usb-init.h -+++ b/drivers/phy/broadcom/phy-brcm-usb-init.h -@@ -64,6 +64,7 @@ struct brcm_usb_init_params { - bool suspend_with_clocks; - }; - -+void brcm_usb_dvr_init_4908(struct brcm_usb_init_params *params); - void brcm_usb_dvr_init_7445(struct brcm_usb_init_params *params); - void brcm_usb_dvr_init_7216(struct brcm_usb_init_params *params); - void brcm_usb_dvr_init_7211b0(struct brcm_usb_init_params *params); ---- a/drivers/phy/broadcom/phy-brcm-usb.c -+++ b/drivers/phy/broadcom/phy-brcm-usb.c -@@ -283,6 +283,15 @@ static const struct attribute_group brcm - .attrs = brcm_usb_phy_attrs, - }; - -+static const struct match_chip_info chip_info_4908 = { -+ .init_func = &brcm_usb_dvr_init_4908, -+ .required_regs = { -+ BRCM_REGS_CTRL, -+ BRCM_REGS_XHCI_EC, -+ -1, -+ }, -+}; -+ - static const struct match_chip_info chip_info_7216 = { - .init_func = &brcm_usb_dvr_init_7216, - .required_regs = { -@@ -318,7 +327,7 @@ static const struct match_chip_info chip - static const struct of_device_id brcm_usb_dt_ids[] = { - { - .compatible = "brcm,bcm4908-usb-phy", -- .data = &chip_info_7445, -+ .data = &chip_info_4908, - }, - { - .compatible = "brcm,bcm7216-usb-phy", diff --git a/target/linux/bcm4908/patches-5.10/089-v5.18-watchdog-allow-building-BCM7038_WDT-for-BCM4908.patch b/target/linux/bcm4908/patches-5.10/089-v5.18-watchdog-allow-building-BCM7038_WDT-for-BCM4908.patch deleted file mode 100644 index ea75181a6e..0000000000 --- a/target/linux/bcm4908/patches-5.10/089-v5.18-watchdog-allow-building-BCM7038_WDT-for-BCM4908.patch +++ /dev/null @@ -1,32 +0,0 @@ -From cd91fb2776967b2b2dea27307a3f23ba3d9bbb32 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 9 Feb 2022 21:32:02 +0100 -Subject: [PATCH] watchdog: allow building BCM7038_WDT for BCM4908 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 is a SoCs family that shares a lot of hardware with BCM63xx -including the watchdog block. Allow building this driver for it. - -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20220209203202.26395-1-zajec5@gmail.com -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -1800,7 +1800,7 @@ config BCM7038_WDT - tristate "BCM7038 Watchdog" - select WATCHDOG_CORE - depends on HAS_IOMEM -- depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST -+ depends on ARCH_BCM4908 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST - help - Watchdog driver for the built-in hardware in Broadcom 7038 and - later SoCs used in set-top boxes. BCM7038 was made public diff --git a/target/linux/bcm4908/patches-5.10/090-v5.20-watchdog-bcm7038_wdt-Support-BCM6345-compatible-stri.patch b/target/linux/bcm4908/patches-5.10/090-v5.20-watchdog-bcm7038_wdt-Support-BCM6345-compatible-stri.patch deleted file mode 100644 index d6d2fd9ab6..0000000000 --- a/target/linux/bcm4908/patches-5.10/090-v5.20-watchdog-bcm7038_wdt-Support-BCM6345-compatible-stri.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 2dd441f16d6ad6104d85c4e5dfeb6dde4df26869 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 16 Feb 2022 07:34:08 +0100 -Subject: [PATCH] watchdog: bcm7038_wdt: Support BCM6345 compatible string -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -A new "compatible" value has been added in the commit 17fffe91ba36 -("dt-bindings: watchdog: Add BCM6345 compatible to BCM7038 binding"). -It's meant to be used for BCM63xx SoCs family but hardware block can be -programmed just like the 7038 one. - -Cc: Florian Fainelli -Signed-off-by: Rafał Miłecki -Acked-by: Florian Fainelli -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20220216063408.23168-1-zajec5@gmail.com -Signed-off-by: Guenter Roeck -Signed-off-by: Wim Van Sebroeck ---- - drivers/watchdog/bcm7038_wdt.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/watchdog/bcm7038_wdt.c -+++ b/drivers/watchdog/bcm7038_wdt.c -@@ -193,6 +193,7 @@ static SIMPLE_DEV_PM_OPS(bcm7038_wdt_pm_ - bcm7038_wdt_resume); - - static const struct of_device_id bcm7038_wdt_match[] = { -+ { .compatible = "brcm,bcm6345-wdt" }, - { .compatible = "brcm,bcm7038-wdt" }, - {}, - }; diff --git a/target/linux/bcm4908/patches-5.10/300-arm64-dts-broadcom-bcmbca-bcm4908-limit-amount-of-GP.patch b/target/linux/bcm4908/patches-5.10/300-arm64-dts-broadcom-bcmbca-bcm4908-limit-amount-of-GP.patch deleted file mode 100644 index a7c6d0102f..0000000000 --- a/target/linux/bcm4908/patches-5.10/300-arm64-dts-broadcom-bcmbca-bcm4908-limit-amount-of-GP.patch +++ /dev/null @@ -1,23 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 15 Feb 2021 22:01:03 +0100 -Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: limit amount of GPIOs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Linux driver can't handle more than 64 GPIOs - -Signed-off-by: Rafał Miłecki ---- - ---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi -@@ -343,7 +343,7 @@ - gpio0: gpio-controller@500 { - compatible = "brcm,bcm6345-gpio"; - reg-names = "dirout", "dat"; -- reg = <0x500 0x28>, <0x528 0x28>; -+ reg = <0x500 0x8>, <0x528 0x8>; - - #gpio-cells = <2>; - gpio-controller; diff --git a/target/linux/bcm4908/patches-5.10/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch b/target/linux/bcm4908/patches-5.10/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch deleted file mode 100644 index 74dddb7f48..0000000000 --- a/target/linux/bcm4908/patches-5.10/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 21 Jan 2021 10:44:53 +0100 -Subject: [PATCH] mtd: rawnand: brcmnand: disable WP on BCM4908 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 contains NAND controller version 0x0701 (v7.1). It means that -NAND_WP should be available. - -For some reason setting #WP on doesn't result in clearing NAND_STATUS_WP -status bit: -[ 1.077857] bcm63138_nand ff801800.nand: timeout on status poll (expected c0000040 got c00000c0) -[ 1.086832] bcm63138_nand ff801800.nand: nand #WP expected on - -For now try working without touching #WP. - -Signed-off-by: Rafał Miłecki ---- - ---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c -@@ -37,7 +37,11 @@ - * 1: NAND_WP is set by default, cleared for erase/write operations - * 2: NAND_WP is always cleared - */ -+#if IS_ENABLED(CONFIG_ARCH_BCM4908) -+static int wp_on = 0; -+#else - static int wp_on = 1; -+#endif - module_param(wp_on, int, 0444); - - /*********************************************************************** diff --git a/target/linux/bcm4908/patches-5.10/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch b/target/linux/bcm4908/patches-5.10/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch deleted file mode 100644 index 5cdaa222c2..0000000000 --- a/target/linux/bcm4908/patches-5.10/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch +++ /dev/null @@ -1,46 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 15 Feb 2021 23:59:26 +0100 -Subject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -GPHY needs to be enabled to succesfully probe & setup switch port -connected to it. Otherwise hardcoding PHY OUI would be required. - -Before: -brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL) -brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL) -brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL) -brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL) -brcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7 - -After: -brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL) -brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL) -brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL) -brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL) -brcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL) - -Signed-off-by: Rafał Miłecki ---- - drivers/net/dsa/bcm_sf2.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -1540,10 +1540,14 @@ static int bcm_sf2_sw_probe(struct platf - rev = reg_readl(priv, REG_PHY_REVISION); - priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; - -+ bcm_sf2_gphy_enable_set(priv->dev->ds, true); -+ - ret = b53_switch_register(dev); - if (ret) - goto out_mdio; - -+ bcm_sf2_gphy_enable_set(priv->dev->ds, false); -+ - dev_info(&pdev->dev, - "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n", - priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, diff --git a/target/linux/bcm4908/patches-5.10/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch b/target/linux/bcm4908/patches-5.10/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch deleted file mode 100644 index 7659aa266b..0000000000 --- a/target/linux/bcm4908/patches-5.10/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 16 Feb 2021 00:06:35 +0100 -Subject: [PATCH] net: dsa: bcm_sf2: keep GPHY enabled on the BCM4908 - -Trying to access disabled PHY results in MDIO_READ_FAIL and: -[ 11.962886] brcm-sf2 80080000.switch wan: configuring for phy/internal link mode -[ 11.972500] 8021q: adding VLAN 0 to HW filter on device wan -[ 11.980205] ------------[ cut here ]------------ -[ 11.984885] WARNING: CPU: 0 PID: 7 at phy_error+0x10/0x58 - -Signed-off-by: Rafał Miłecki ---- - drivers/net/dsa/bcm_sf2.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/net/dsa/bcm_sf2.c -+++ b/drivers/net/dsa/bcm_sf2.c -@@ -1554,6 +1554,12 @@ static int bcm_sf2_sw_probe(struct platf - priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, - priv->irq0, priv->irq1); - -+ /* BCM4908 has 5 GPHYs which means bcm_sf2_port_setup() will not enable -+ * GPHY when needed. Leave it enabled here. -+ */ -+ if (priv->type == BCM4908_DEVICE_ID) -+ bcm_sf2_gphy_enable_set(priv->dev->ds, true); -+ - return 0; - - out_mdio: diff --git a/target/linux/bcm53xx/config-5.10 b/target/linux/bcm53xx/config-5.10 deleted file mode 100644 index 04b972131a..0000000000 --- a/target/linux/bcm53xx/config-5.10 +++ /dev/null @@ -1,308 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_BCM=y -CONFIG_ARCH_BCM_5301X=y -CONFIG_ARCH_BCM_53573=y -# CONFIG_ARCH_BCM_HR2 is not set -CONFIG_ARCH_BCM_IPROC=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GLOBAL_TIMER=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_B53=y -CONFIG_B53_MDIO_DRIVER=y -CONFIG_B53_SRAB_DRIVER=y -CONFIG_BCM47XX_NVRAM=y -CONFIG_BCM47XX_SPROM=y -CONFIG_BCM47XX_WDT=y -CONFIG_BCMA=y -CONFIG_BCMA_BLOCKIO=y -CONFIG_BCMA_DEBUG=y -CONFIG_BCMA_DRIVER_GMAC_CMN=y -CONFIG_BCMA_DRIVER_GPIO=y -CONFIG_BCMA_DRIVER_PCI=y -CONFIG_BCMA_HOST_PCI=y -CONFIG_BCMA_HOST_PCI_POSSIBLE=y -CONFIG_BCMA_HOST_SOC=y -CONFIG_BCMA_SFLASH=y -# CONFIG_BCM_CYGNUS_PHY is not set -CONFIG_BCM_NET_PHYLIB=y -CONFIG_BCM_NS_THERMAL=y -CONFIG_BCM_SR_THERMAL=y -CONFIG_BGMAC=y -CONFIG_BGMAC_BCMA=y -# CONFIG_BGMAC_PLATFORM is not set -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOUNCE=y -CONFIG_BROADCOM_PHY=y -CONFIG_CACHE_L2X0=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y -CONFIG_CLKSRC_MMIO=y -# CONFIG_CLK_BCM_NS2 is not set -CONFIG_CLK_BCM_NSP=y -# CONFIG_CLK_BCM_SR is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_IPROC=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BCM_5301X=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=0 -CONFIG_DEBUG_UART_PHYS=0x18000300 -CONFIG_DEBUG_UART_VIRT=0xf1000300 -CONFIG_DEBUG_UNCOMPRESS=y -CONFIG_DEBUG_USER=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EXTCON=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FW_LOADER_PAGED_BUF=y -# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_74X164=y -CONFIG_GPIO_BCM_XGS_IPROC=y -CONFIG_GPIO_GENERIC=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_BCM2835=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_LEDS_BCM63138 is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BCM_IPROC=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_BUS_MUX=y -# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_BCM47XXSFLASH=y -CONFIG_MTD_BCM47XX_PARTS=y -CONFIG_MTD_NAND_BRCMNAND=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_OF_PARTS_LINKSYS_NS=y -CONFIG_MTD_PARSER_TPLINK_SAFELOADER=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_TAG_BRCM=y -CONFIG_NET_DSA_TAG_BRCM_COMMON=y -CONFIG_NET_DSA_TAG_BRCM_LEGACY=y -CONFIG_NET_DSA_TAG_BRCM_PREPEND=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_BRCM_NVRAM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIE_IPROC=y -CONFIG_PCIE_IPROC_BCMA=y -# CONFIG_PCIE_IPROC_PLATFORM is not set -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_BCM_NS_USB2 is not set -# CONFIG_PHY_BCM_NS_USB3 is not set -# CONFIG_PHY_BCM_SR_PCIE is not set -CONFIG_PHY_BCM_SR_USB=y -# CONFIG_PHY_BRCM_SATA is not set -# CONFIG_PHY_NS2_USB_DRD is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_IPROC_GPIO is not set -CONFIG_PINCTRL_NS=y -# CONFIG_PINCTRL_NS2_MUX is not set -CONFIG_PWM=y -CONFIG_PWM_BCM_IPROC=y -CONFIG_PWM_SYSFS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BCM_QSPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0001-ARM-dts-BCM5301X-Linksys-EA9500-add-port-5-and-port-.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0001-ARM-dts-BCM5301X-Linksys-EA9500-add-port-5-and-port-.patch deleted file mode 100644 index f0cfbf8e63..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0001-ARM-dts-BCM5301X-Linksys-EA9500-add-port-5-and-port-.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 1ca5f2430c4f9d85b98b8d6e5d93f8d4802faf8e Mon Sep 17 00:00:00 2001 -From: Vivek Unune -Date: Wed, 14 Oct 2020 15:27:27 -0400 -Subject: [PATCH] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7 - -Add ports 5 and 7 which are connected to gmac cores 1 & 2. -These will be disabled for now. - -Signed-off-by: Vivek Unune -Signed-off-by: Florian Fainelli ---- - .../boot/dts/bcm47094-linksys-panamera.dts | 24 +++++++++++++++++++ - 1 file changed, 24 insertions(+) - ---- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -@@ -242,6 +242,30 @@ - label = "wan"; - }; - -+ port@5 { -+ reg = <5>; -+ ethernet = <&gmac0>; -+ label = "cpu"; -+ status = "disabled"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@7 { -+ reg = <7>; -+ ethernet = <&gmac1>; -+ label = "cpu"; -+ status = "disabled"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ - port@8 { - reg = <8>; - ethernet = <&gmac2>; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0002-ARM-dts-BCM5301X-Harmonize-EHCI-OHCI-DT-nodes-name.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0002-ARM-dts-BCM5301X-Harmonize-EHCI-OHCI-DT-nodes-name.patch deleted file mode 100644 index d6e5fca967..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0002-ARM-dts-BCM5301X-Harmonize-EHCI-OHCI-DT-nodes-name.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 74abbfe99f43eb7466d26d9e48fbeb46b8f3d804 Mon Sep 17 00:00:00 2001 -From: Serge Semin -Date: Tue, 20 Oct 2020 14:59:37 +0300 -Subject: [PATCH] ARM: dts: BCM5301X: Harmonize EHCI/OHCI DT nodes name - -In accordance with the Generic EHCI/OHCI bindings the corresponding node -name is suppose to comply with the Generic USB HCD DT schema, which -requires the USB nodes to have the name acceptable by the regexp: -"^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible -nodes are correctly named. - -Signed-off-by: Serge Semin -Acked-by: Florian Fainelli -Acked-by: Krzysztof Kozlowski -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 4 ++-- - arch/arm/boot/dts/bcm53573.dtsi | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -267,7 +267,7 @@ - - interrupt-parent = <&gic>; - -- ehci: ehci@21000 { -+ ehci: usb@21000 { - #usb-cells = <0>; - - compatible = "generic-ehci"; -@@ -289,7 +289,7 @@ - }; - }; - -- ohci: ohci@22000 { -+ ohci: usb@22000 { - #usb-cells = <0>; - - compatible = "generic-ohci"; ---- a/arch/arm/boot/dts/bcm53573.dtsi -+++ b/arch/arm/boot/dts/bcm53573.dtsi -@@ -135,7 +135,7 @@ - #address-cells = <1>; - #size-cells = <1>; - -- ehci: ehci@4000 { -+ ehci: usb@4000 { - compatible = "generic-ehci"; - reg = <0x4000 0x1000>; - interrupt-parent = <&gic>; -@@ -155,7 +155,7 @@ - }; - }; - -- ohci: ohci@d000 { -+ ohci: usb@d000 { - #usb-cells = <0>; - - compatible = "generic-ohci"; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0003-ARM-dts-BCM5310X-Harmonize-xHCI-DT-nodes-name.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0003-ARM-dts-BCM5310X-Harmonize-xHCI-DT-nodes-name.patch deleted file mode 100644 index 2f9c8ce8c0..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0003-ARM-dts-BCM5310X-Harmonize-xHCI-DT-nodes-name.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 4b650a20bdb5f9558007dd3055a17a1644a91c3e Mon Sep 17 00:00:00 2001 -From: Serge Semin -Date: Tue, 20 Oct 2020 14:59:46 +0300 -Subject: [PATCH] ARM: dts: BCM5310X: Harmonize xHCI DT nodes name - -In accordance with the Generic xHCI bindings the corresponding node -name is suppose to comply with the Generic USB HCD DT schema, which -requires the USB nodes to have the name acceptable by the regexp: -"^usb(@.*)?" . Make sure the "generic-xhci"-compatible nodes are -correctly named. - -Signed-off-by: Serge Semin -Acked-by: Krzysztof Kozlowski -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -320,7 +320,7 @@ - - interrupt-parent = <&gic>; - -- xhci: xhci@23000 { -+ xhci: usb@23000 { - #usb-cells = <0>; - - compatible = "generic-xhci"; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0004-ARM-dts-BCM5301X-Linksys-EA9500-add-fixed-partitions.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0004-ARM-dts-BCM5301X-Linksys-EA9500-add-fixed-partitions.patch deleted file mode 100644 index c3fdd163d9..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0004-ARM-dts-BCM5301X-Linksys-EA9500-add-fixed-partitions.patch +++ /dev/null @@ -1,71 +0,0 @@ -From bd9a01e28e5d1632528e531480b42d6e2c861d88 Mon Sep 17 00:00:00 2001 -From: Vivek Unune -Date: Sun, 1 Nov 2020 15:08:03 -0500 -Subject: [PATCH] ARM: dts: BCM5301X: Linksys EA9500 add fixed partitions - -This router has dual paritions to store trx firmware image and -dual partitions for nvram. The second one in each of these cases acts -as a backup store. - -When tested with OpenWrt, the default partition parser causes two issues: - -1. It labels both nvram partitions as nvram. In factory, second one is -labeled devinfo. -2. It parses second trx image and tries to create second 'linux' partition -and fails with - cannot create duplicate 'linux' partition - -The following patch works around both of these issues. - -Signed-off-by: Vivek Unune -Signed-off-by: Florian Fainelli ---- - .../boot/dts/bcm47094-linksys-panamera.dts | 41 +++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -@@ -292,3 +292,44 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&nandcs { -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "boot"; -+ reg = <0x0000000 0x0080000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "nvram"; -+ reg = <0x080000 0x0100000>; -+ }; -+ -+ partition@180000{ -+ label = "devinfo"; -+ reg = <0x0180000 0x080000>; -+ }; -+ -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x0200000 0x01D00000>; -+ compatible = "brcm,trx"; -+ }; -+ -+ partition@1F00000 { -+ label = "failsafe"; -+ reg = <0x01F00000 0x01D00000>; -+ read-only; -+ }; -+ -+ partition@5200000 { -+ label = "system"; -+ reg = <0x05200000 0x02E00000>; -+ }; -+ }; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0005-ARM-dts-BCM5301X-Use-corretc-pinctrl-compatible-for-.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0005-ARM-dts-BCM5301X-Use-corretc-pinctrl-compatible-for-.patch deleted file mode 100644 index ddebdc4343..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0005-ARM-dts-BCM5301X-Use-corretc-pinctrl-compatible-for-.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 2f34ae32f5e74096540cd7ce95bfd467cb74b21a Mon Sep 17 00:00:00 2001 -From: Vivek Unune -Date: Wed, 4 Nov 2020 15:29:51 -0500 -Subject: [PATCH] ARM: dts: BCM5301X: Use corretc pinctrl compatible for 4709x -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM47094 version of pinmux uses different compatible and supports MDIO -pinmux pins. Hence, use the correct compatible string and defines the -MDIO pins group. - -Signed-off-by: Vivek Unune -Acked-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094.dtsi | 9 +++++++++ - arch/arm/boot/dts/bcm5301x.dtsi | 2 +- - 2 files changed, 10 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm47094.dtsi -+++ b/arch/arm/boot/dts/bcm47094.dtsi -@@ -8,6 +8,15 @@ - / { - }; - -+&pinctrl { -+ compatible = "brcm,bcm4709-pinmux"; -+ -+ pinmux_mdio: mdio { -+ groups = "mdio_grp"; -+ function = "mdio"; -+ }; -+}; -+ - &usb3_phy { - compatible = "brcm,ns-bx-usb3-phy"; - }; ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -430,7 +430,7 @@ - #address-cells = <1>; - #size-cells = <1>; - -- pin-controller@1c0 { -+ pinctrl: pin-controller@1c0 { - compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; - reg-names = "cru_gpio_control"; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0006-ARM-dts-BCM5301X-Linksys-EA9500-make-use-of-pinctrl.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0006-ARM-dts-BCM5301X-Linksys-EA9500-make-use-of-pinctrl.patch deleted file mode 100644 index 785271546b..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0006-ARM-dts-BCM5301X-Linksys-EA9500-make-use-of-pinctrl.patch +++ /dev/null @@ -1,61 +0,0 @@ -From c862059875cffc013ee27bf9759ac288224e7a14 Mon Sep 17 00:00:00 2001 -From: Vivek Unune -Date: Wed, 4 Nov 2020 15:29:52 -0500 -Subject: [PATCH] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl - -Now that we have a pin controller, use that instead of manuplating the -mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux - -Signed-off-by: Vivek Unune -Signed-off-by: Florian Fainelli ---- - .../boot/dts/bcm47094-linksys-panamera.dts | 26 +++---------------- - 1 file changed, 4 insertions(+), 22 deletions(-) - ---- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -@@ -123,33 +123,13 @@ - }; - }; - -- mdio-bus-mux { -- #address-cells = <1>; -- #size-cells = <0>; -+ mdio-bus-mux@18003000 { - - /* BIT(9) = 1 => external mdio */ -- mdio_ext: mdio@200 { -+ mdio@200 { - reg = <0x200>; - #address-cells = <1>; - #size-cells = <0>; -- }; -- }; -- -- mdio-mii-mux { -- compatible = "mdio-mux-mmioreg"; -- mdio-parent-bus = <&mdio_ext>; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x1800c1c0 0x4>; -- -- /* BIT(6) = mdc, BIT(7) = mdio */ -- mux-mask = <0xc0>; -- -- mdio-mii@0 { -- /* Enable MII function */ -- reg = <0x0>; -- #address-cells = <1>; -- #size-cells = <0>; - - switch@0 { - compatible = "brcm,bcm53125"; -@@ -159,6 +139,8 @@ - reset-names = "robo_reset"; - reg = <0>; - dsa,member = <1 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinmux_mdio>; - - ports { - #address-cells = <1>; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0007-ARM-dts-BCM5301X-Move-CRU-devices-to-the-CRU-node.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0007-ARM-dts-BCM5301X-Move-CRU-devices-to-the-CRU-node.patch deleted file mode 100644 index 3c3db540d0..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0007-ARM-dts-BCM5301X-Move-CRU-devices-to-the-CRU-node.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 776461b1795b4dc4084894cf53399044aafa1d21 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 11 Nov 2020 15:55:38 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: Move CRU devices to the CRU node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Clocks and thermal blocks are part of the CRU ("Clock and Reset Unit" or -"Central Resource Unit"). - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 51 +++++++++++++++++---------------- - 1 file changed, 26 insertions(+), 25 deletions(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -430,6 +430,26 @@ - #address-cells = <1>; - #size-cells = <1>; - -+ lcpll0: lcpll0@100 { -+ #clock-cells = <1>; -+ compatible = "brcm,nsp-lcpll0"; -+ reg = <0x100 0x14>; -+ clocks = <&osc>; -+ clock-output-names = "lcpll0", "pcie_phy", -+ "sdio", "ddr_phy"; -+ }; -+ -+ genpll: genpll@140 { -+ #clock-cells = <1>; -+ compatible = "brcm,nsp-genpll"; -+ reg = <0x140 0x24>; -+ clocks = <&osc>; -+ clock-output-names = "genpll", "phy", -+ "ethernetclk", -+ "usbclk", "iprocfast", -+ "sata1", "sata2"; -+ }; -+ - pinctrl: pin-controller@1c0 { - compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; -@@ -456,32 +476,13 @@ - function = "uart1"; - }; - }; -- }; -- }; - -- lcpll0: lcpll0@1800c100 { -- #clock-cells = <1>; -- compatible = "brcm,nsp-lcpll0"; -- reg = <0x1800c100 0x14>; -- clocks = <&osc>; -- clock-output-names = "lcpll0", "pcie_phy", "sdio", -- "ddr_phy"; -- }; -- -- genpll: genpll@1800c140 { -- #clock-cells = <1>; -- compatible = "brcm,nsp-genpll"; -- reg = <0x1800c140 0x24>; -- clocks = <&osc>; -- clock-output-names = "genpll", "phy", "ethernetclk", -- "usbclk", "iprocfast", "sata1", -- "sata2"; -- }; -- -- thermal: thermal@1800c2c0 { -- compatible = "brcm,ns-thermal"; -- reg = <0x1800c2c0 0x10>; -- #thermal-sensor-cells = <0>; -+ thermal: thermal@2c0 { -+ compatible = "brcm,ns-thermal"; -+ reg = <0x2c0 0x10>; -+ #thermal-sensor-cells = <0>; -+ }; -+ }; - }; - - srab: srab@18007000 { diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0008-ARM-dts-BCM5301X-Disable-USB-3-PHY-on-devices-withou.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0008-ARM-dts-BCM5301X-Disable-USB-3-PHY-on-devices-withou.patch deleted file mode 100644 index 64415c14db..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0008-ARM-dts-BCM5301X-Disable-USB-3-PHY-on-devices-withou.patch +++ /dev/null @@ -1,94 +0,0 @@ -From 632ddf978565378e7efb9ea77c0ba239ea66bfdc Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 13 Nov 2020 11:09:19 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: Disable USB 3 PHY on devices without USB - 3 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It seems pointless to have it enabled. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 4 ---- - arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 4 ---- - arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 4 ---- - arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 4 ---- - arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 4 ---- - arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts | 4 ---- - 6 files changed, 24 deletions(-) - ---- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts -+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts -@@ -57,10 +57,6 @@ - status = "okay"; - }; - --&usb3_phy { -- status = "okay"; --}; -- - &srab { - status = "okay"; - ---- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -@@ -64,10 +64,6 @@ - status = "okay"; - }; - --&usb3_phy { -- status = "okay"; --}; -- - &srab { - status = "okay"; - ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -@@ -117,7 +117,3 @@ - }; - }; - }; -- --&usb3_phy { -- status = "okay"; --}; ---- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts -+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts -@@ -57,10 +57,6 @@ - status = "okay"; - }; - --&usb3_phy { -- status = "okay"; --}; -- - &srab { - status = "okay"; - ---- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts -+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts -@@ -105,10 +105,6 @@ - status = "okay"; - }; - --&usb3_phy { -- status = "okay"; --}; -- - &srab { - status = "okay"; - ---- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts -+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts -@@ -126,7 +126,3 @@ - &usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - }; -- --&usb3_phy { -- status = "okay"; --}; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0009-ARM-dts-BCM5301X-Enable-USB-3-PHY-on-Luxul-XWR-3150.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0009-ARM-dts-BCM5301X-Enable-USB-3-PHY-on-Luxul-XWR-3150.patch deleted file mode 100644 index 5834e300f5..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0009-ARM-dts-BCM5301X-Enable-USB-3-PHY-on-Luxul-XWR-3150.patch +++ /dev/null @@ -1,30 +0,0 @@ -From b2ab5e8697ef6591aeeda23be49e096705dbbda3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 13 Nov 2020 10:50:12 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: Enable USB 3 PHY on Luxul XWR-3150 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This device has a functional USB 3 port so PHY is required. - -Signed-off-by: Rafał Miłecki -Reported-by: kernel test robot -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -@@ -71,6 +71,10 @@ - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; - }; - -+&usb3_phy { -+ status = "okay"; -+}; -+ - &spi_nor { - status = "okay"; - }; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0010-ARM-dts-BCM5301X-Update-Ethernet-switch-node-name.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0010-ARM-dts-BCM5301X-Update-Ethernet-switch-node-name.patch deleted file mode 100644 index b3a774e340..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0010-ARM-dts-BCM5301X-Update-Ethernet-switch-node-name.patch +++ /dev/null @@ -1,32 +0,0 @@ -From f527cb6f3345f7faa8e61dd9f3c437437327428c Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 9 Nov 2020 11:41:01 -0800 -Subject: [PATCH] ARM: dts: BCM5301X: Update Ethernet switch node name - -Update the switch unit name from srab to ethernet-switch, allowing us to -fix warnings such as: - - CHECK arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml -arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml: -srab@18007000: $nodename:0: 'srab@18007000' does not match -'^(ethernet-)?switch(@.*)?$' - From schema: -Documentation/devicetree/bindings/net/dsa/b53.yaml - -Reviewed-by: Vladimir Oltean -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -485,7 +485,7 @@ - }; - }; - -- srab: srab@18007000 { -+ srab: ethernet-switch@18007000 { - compatible = "brcm,bcm5301x-srab"; - reg = <0x18007000 0x1000>; - diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0011-ARM-dts-BCM5301X-Add-a-default-compatible-for-switch.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0011-ARM-dts-BCM5301X-Add-a-default-compatible-for-switch.patch deleted file mode 100644 index 677e94f271..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0011-ARM-dts-BCM5301X-Add-a-default-compatible-for-switch.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 953efcb0c0234f8c488ebd4090378e949d6ba78b Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 9 Nov 2020 16:42:09 -0800 -Subject: [PATCH] ARM: dts: BCM5301X: Add a default compatible for switch node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Provide a default compatible string which is based on the 53011 SRAB -compatible by default. The 4709 and 47094 default to the 53012 SRAB -compatible. - -This allows us to have sane defaults and silences the following -warnings: - -arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: -ethernet-switch@18007000: compatible: 'oneOf' conditional failed, one -must be fixed: - ['brcm,bcm5301x-srab'] is too short - 'brcm,bcm5325' was expected - 'brcm,bcm53115' was expected - 'brcm,bcm53125' was expected - 'brcm,bcm53128' was expected - 'brcm,bcm5365' was expected - 'brcm,bcm5395' was expected - 'brcm,bcm5389' was expected - 'brcm,bcm5397' was expected - 'brcm,bcm5398' was expected - 'brcm,bcm11360-srab' was expected - 'brcm,bcm5301x-srab' is not one of ['brcm,bcm53010-srab', -'brcm,bcm53011-srab', 'brcm,bcm53012-srab', 'brcm,bcm53018-srab', -'brcm,bcm53019-srab'] - 'brcm,bcm5301x-srab' is not one of ['brcm,bcm11404-srab', -'brcm,bcm11407-srab', 'brcm,bcm11409-srab', 'brcm,bcm58310-srab', -'brcm,bcm58311-srab', 'brcm,bcm58313-srab'] - 'brcm,bcm5301x-srab' is not one of ['brcm,bcm58522-srab', -'brcm,bcm58523-srab', 'brcm,bcm58525-srab', 'brcm,bcm58622-srab', -'brcm,bcm58623-srab', 'brcm,bcm58625-srab', 'brcm,bcm88312-srab'] - 'brcm,bcm5301x-srab' is not one of ['brcm,bcm3384-switch', -'brcm,bcm6328-switch', 'brcm,bcm6368-switch'] - From schema: -Documentation/devicetree/bindings/net/dsa/b53.yaml - -Acked-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm4709.dtsi | 4 ++++ - arch/arm/boot/dts/bcm47094.dtsi | 4 ++++ - arch/arm/boot/dts/bcm5301x.dtsi | 2 +- - 3 files changed, 9 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm4709.dtsi -+++ b/arch/arm/boot/dts/bcm4709.dtsi -@@ -9,3 +9,7 @@ - clock-frequency = <125000000>; - status = "okay"; - }; -+ -+&srab { -+ compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; -+}; ---- a/arch/arm/boot/dts/bcm47094.dtsi -+++ b/arch/arm/boot/dts/bcm47094.dtsi -@@ -25,3 +25,7 @@ - clock-frequency = <125000000>; - status = "okay"; - }; -+ -+&srab { -+ compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; -+}; ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -486,7 +486,7 @@ - }; - - srab: ethernet-switch@18007000 { -- compatible = "brcm,bcm5301x-srab"; -+ compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; - reg = <0x18007000 0x1000>; - - status = "disabled"; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0012-ARM-dts-BCM5301X-Provide-defaults-ports-container-no.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0012-ARM-dts-BCM5301X-Provide-defaults-ports-container-no.patch deleted file mode 100644 index 6e4f5f7bb8..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0012-ARM-dts-BCM5301X-Provide-defaults-ports-container-no.patch +++ /dev/null @@ -1,180 +0,0 @@ -From fd577b41421bc24e2d04cab96d387301b649eb14 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 9 Nov 2020 17:20:17 -0800 -Subject: [PATCH] ARM: dts: BCM5301X: Provide defaults ports container node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Provide an empty 'ports' container node with the correct #address-cells -and #size-cells properties. This silences the following warning: - -arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: -ethernet-switch@18007000: 'oneOf' conditional failed, one must be fixed: - 'ports' is a required property - 'ethernet-ports' is a required property - From schema: -Documentation/devicetree/bindings/net/dsa/b53.yaml - -Acked-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 3 --- - arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 3 --- - arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 3 --- - arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 3 --- - arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 3 --- - arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 3 --- - arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 3 --- - arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 3 --- - arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 3 --- - arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 3 --- - arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ - arch/arm/boot/dts/bcm953012er.dts | 3 --- - 12 files changed, 4 insertions(+), 33 deletions(-) - ---- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts -+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts -@@ -61,9 +61,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - reg = <0>; - label = "poe"; ---- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -@@ -68,9 +68,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@4 { - reg = <4>; - label = "lan"; ---- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts -+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts -@@ -122,9 +122,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - reg = <0>; - label = "lan4"; ---- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts -+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts -@@ -61,9 +61,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@4 { - reg = <4>; - label = "poe"; ---- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts -+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts -@@ -109,9 +109,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - reg = <0>; - label = "lan4"; ---- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -@@ -201,9 +201,6 @@ - dsa,member = <0 0>; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@1 { - reg = <1>; - label = "lan7"; ---- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts -@@ -59,9 +59,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - reg = <0>; - label = "poe"; ---- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts -@@ -57,9 +57,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - reg = <0>; - label = "lan"; ---- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts -@@ -108,9 +108,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - reg = <0>; - label = "lan4"; ---- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -@@ -83,9 +83,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - reg = <0>; - label = "lan4"; ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -492,6 +492,10 @@ - status = "disabled"; - - /* ports are defined in board DTS */ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; - }; - - rng: rng@18004000 { ---- a/arch/arm/boot/dts/bcm953012er.dts -+++ b/arch/arm/boot/dts/bcm953012er.dts -@@ -69,9 +69,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - reg = <0>; - label = "port0"; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0013-ARM-dts-NSP-Update-ethernet-switch-node-name.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0013-ARM-dts-NSP-Update-ethernet-switch-node-name.patch deleted file mode 100644 index 6a7641648d..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0013-ARM-dts-NSP-Update-ethernet-switch-node-name.patch +++ /dev/null @@ -1,32 +0,0 @@ -From fd66cd0d79cb836badecb91fdd19afd32afbb443 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 9 Nov 2020 12:02:08 -0800 -Subject: [PATCH 13/16] ARM: dts: NSP: Update ethernet switch node name - -Update the switch unit name from srab to ethernet-switch, allowing us -to fix warnings such as: - - CHECK arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml - arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml: - srab@18007000: $nodename:0: 'srab@18007000' does not match - '^(ethernet-)?switch(@.*)?$' - From schema: - Documentation/devicetree/bindings/net/dsa/b53.yaml - -Reviewed-by: Vladimir Oltean -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -385,7 +385,7 @@ - clock-names = "apb_pclk"; - }; - -- srab: srab@36000 { -+ srab: ethernet-switch@36000 { - compatible = "brcm,nsp-srab"; - reg = <0x36000 0x1000>, - <0x3f308 0x8>, diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0014-ARM-dts-NSP-Fix-Ethernet-switch-SGMII-register-name.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0014-ARM-dts-NSP-Fix-Ethernet-switch-SGMII-register-name.patch deleted file mode 100644 index 033dc0c031..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0014-ARM-dts-NSP-Fix-Ethernet-switch-SGMII-register-name.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 8b0235d1deace8f1bd8cdd149d698fee3974fdf4 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 9 Nov 2020 12:06:15 -0800 -Subject: [PATCH 14/16] ARM: dts: NSP: Fix Ethernet switch SGMII register name - -The register name should be "sgmii_config", not "sgmii", this is not a -functional change since no code is currently looking for that register -by name (or at all). - -Reviewed-by: Vladimir Oltean -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -390,7 +390,7 @@ - reg = <0x36000 0x1000>, - <0x3f308 0x8>, - <0x3f410 0xc>; -- reg-names = "srab", "mux_config", "sgmii"; -+ reg-names = "srab", "mux_config", "sgmii_config"; - interrupts = , - , - , diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0015-ARM-dts-NSP-Add-a-SRAB-compatible-string-for-each-bo.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0015-ARM-dts-NSP-Add-a-SRAB-compatible-string-for-each-bo.patch deleted file mode 100644 index 890b913b0c..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0015-ARM-dts-NSP-Add-a-SRAB-compatible-string-for-each-bo.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 42791b317db4cda36751f57bada27857849811d3 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 9 Nov 2020 17:41:32 -0800 -Subject: [PATCH 15/16] ARM: dts: NSP: Add a SRAB compatible string for each - board - -Provide a valid compatible string for the Ethernet switch node based on -the board including the switch. This allows us to have sane defaults and -silences the following warnings: - - arch/arm/boot/dts/bcm958522er.dt.yaml: - ethernet-switch@36000: compatible: 'oneOf' conditional failed, -one - must be fixed: - ['brcm,bcm5301x-srab'] is too short - 'brcm,bcm5325' was expected - 'brcm,bcm53115' was expected - 'brcm,bcm53125' was expected - 'brcm,bcm53128' was expected - 'brcm,bcm5365' was expected - 'brcm,bcm5395' was expected - 'brcm,bcm5389' was expected - 'brcm,bcm5397' was expected - 'brcm,bcm5398' was expected - 'brcm,bcm11360-srab' was expected - 'brcm,bcm5301x-srab' is not one of ['brcm,bcm53010-srab', - 'brcm,bcm53011-srab', 'brcm,bcm53012-srab', 'brcm,bcm53018-srab', - 'brcm,bcm53019-srab'] - 'brcm,bcm5301x-srab' is not one of ['brcm,bcm11404-srab', - 'brcm,bcm11407-srab', 'brcm,bcm11409-srab', 'brcm,bcm58310-srab', - 'brcm,bcm58311-srab', 'brcm,bcm58313-srab'] - 'brcm,bcm5301x-srab' is not one of ['brcm,bcm58522-srab', - 'brcm,bcm58523-srab', 'brcm,bcm58525-srab', 'brcm,bcm58622-srab', - 'brcm,bcm58623-srab', 'brcm,bcm58625-srab', 'brcm,bcm88312-srab'] - 'brcm,bcm5301x-srab' is not one of ['brcm,bcm3384-switch', - 'brcm,bcm6328-switch', 'brcm,bcm6368-switch'] - From schema: - Documentation/devicetree/bindings/net/dsa/b53.yaml - -Reviewed-by: Vladimir Oltean -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm958522er.dts | 4 ++++ - arch/arm/boot/dts/bcm958525er.dts | 4 ++++ - arch/arm/boot/dts/bcm958525xmc.dts | 4 ++++ - 3 files changed, 12 insertions(+) - ---- a/arch/arm/boot/dts/bcm958522er.dts -+++ b/arch/arm/boot/dts/bcm958522er.dts -@@ -178,3 +178,7 @@ - &xhci { - status = "okay"; - }; -+ -+&srab { -+ compatible = "brcm,bcm58522-srab", "brcm,nsp-srab"; -+}; ---- a/arch/arm/boot/dts/bcm958525er.dts -+++ b/arch/arm/boot/dts/bcm958525er.dts -@@ -190,3 +190,7 @@ - &xhci { - status = "okay"; - }; -+ -+&srab { -+ compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; -+}; ---- a/arch/arm/boot/dts/bcm958525xmc.dts -+++ b/arch/arm/boot/dts/bcm958525xmc.dts -@@ -210,3 +210,7 @@ - &xhci { - status = "okay"; - }; -+ -+&srab { -+ compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0016-ARM-dts-NSP-Provide-defaults-ports-container-node.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0016-ARM-dts-NSP-Provide-defaults-ports-container-node.patch deleted file mode 100644 index 7ca01b5b7d..0000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0016-ARM-dts-NSP-Provide-defaults-ports-container-node.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 51e40c25aa18d926a8eb1c07289d01611b21123a Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 9 Nov 2020 17:44:33 -0800 -Subject: [PATCH 16/16] ARM: dts: NSP: Provide defaults ports container node - -Provide an empty 'ports' container node with the correct #address-cells -and #size-cells properties. This silences the following warning: - -arch/arm/boot/dts/bcm958522er.dt.yaml: -ethernet-switch@36000: 'oneOf' conditional failed, one must be fixed: - 'ports' is a required property - 'ethernet-ports' is a required property - From schema: -Documentation/devicetree/bindings/net/dsa/b53.yaml - -Reviewed-by: Vladimir Oltean -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 4 ++++ - arch/arm/boot/dts/bcm958622hr.dts | 3 --- - arch/arm/boot/dts/bcm958623hr.dts | 3 --- - arch/arm/boot/dts/bcm958625hr.dts | 3 --- - arch/arm/boot/dts/bcm958625k.dts | 3 --- - arch/arm/boot/dts/bcm988312hr.dts | 3 --- - 6 files changed, 4 insertions(+), 15 deletions(-) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -420,6 +420,10 @@ - status = "disabled"; - - /* ports are defined in board DTS */ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; - }; - - i2c0: i2c@38000 { ---- a/arch/arm/boot/dts/bcm958622hr.dts -+++ b/arch/arm/boot/dts/bcm958622hr.dts -@@ -176,9 +176,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - label = "port0"; - reg = <0>; ---- a/arch/arm/boot/dts/bcm958623hr.dts -+++ b/arch/arm/boot/dts/bcm958623hr.dts -@@ -180,9 +180,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - label = "port0"; - reg = <0>; ---- a/arch/arm/boot/dts/bcm958625hr.dts -+++ b/arch/arm/boot/dts/bcm958625hr.dts -@@ -195,9 +195,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - label = "port0"; - reg = <0>; ---- a/arch/arm/boot/dts/bcm958625k.dts -+++ b/arch/arm/boot/dts/bcm958625k.dts -@@ -216,9 +216,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - label = "port0"; - reg = <0>; ---- a/arch/arm/boot/dts/bcm988312hr.dts -+++ b/arch/arm/boot/dts/bcm988312hr.dts -@@ -184,9 +184,6 @@ - status = "okay"; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - label = "port0"; - reg = <0>; diff --git a/target/linux/bcm53xx/patches-5.10/031-v5.13-0002-ARM-dts-BCM5301X-Describe-NVMEM-NVRAM-on-Linksys-Lux.patch b/target/linux/bcm53xx/patches-5.10/031-v5.13-0002-ARM-dts-BCM5301X-Describe-NVMEM-NVRAM-on-Linksys-Lux.patch deleted file mode 100644 index 136d221a97..0000000000 --- a/target/linux/bcm53xx/patches-5.10/031-v5.13-0002-ARM-dts-BCM5301X-Describe-NVMEM-NVRAM-on-Linksys-Lux.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 428ac8df021dd1cbcc693eb76636873d42327e5d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 10 Mar 2021 22:04:46 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: Describe NVMEM NVRAM on Linksys & Luxul - routers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Provide access to NVRAM which contains device environment variables. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts | 5 +++++ - arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 5 +++++ - arch/arm/boot/dts/bcm4709-linksys-ea9200.dts | 5 +++++ - arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 5 +++++ - arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 5 +++++ - arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 5 +++++ - arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 5 +++++ - arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 5 +++++ - 8 files changed, 40 insertions(+) - ---- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts -+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts -@@ -21,6 +21,11 @@ - reg = <0x00000000 0x08000000>; - }; - -+ nvram@1c080000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1c080000 0x180000>; -+ }; -+ - gpio-keys { - compatible = "gpio-keys"; - ---- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts -+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts -@@ -21,6 +21,11 @@ - reg = <0x00000000 0x08000000>; - }; - -+ nvram@1eff0000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1eff0000 0x10000>; -+ }; -+ - leds { - compatible = "gpio-leds"; - ---- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts -+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts -@@ -22,6 +22,11 @@ - <0x88000000 0x08000000>; - }; - -+ nvram@1c080000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1c080000 0x180000>; -+ }; -+ - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -@@ -22,6 +22,11 @@ - <0x88000000 0x08000000>; - }; - -+ nvram@1c080000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1c080000 0x100000>; -+ }; -+ - gpio-keys { - compatible = "gpio-keys"; - ---- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts -@@ -22,6 +22,11 @@ - <0x88000000 0x18000000>; - }; - -+ nvram@1eff0000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1eff0000 0x10000>; -+ }; -+ - leds { - compatible = "gpio-leds"; - ---- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts -@@ -22,6 +22,11 @@ - <0x88000000 0x18000000>; - }; - -+ nvram@1eff0000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1eff0000 0x10000>; -+ }; -+ - leds { - compatible = "gpio-leds"; - ---- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts -@@ -22,6 +22,11 @@ - <0x88000000 0x08000000>; - }; - -+ nvram@1eff0000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1eff0000 0x10000>; -+ }; -+ - leds { - compatible = "gpio-leds"; - ---- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -@@ -22,6 +22,11 @@ - <0x88000000 0x18000000>; - }; - -+ nvram@1eff0000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1eff0000 0x10000>; -+ }; -+ - leds { - compatible = "gpio-leds"; - diff --git a/target/linux/bcm53xx/patches-5.10/031-v5.13-0003-ARM-dts-BCM5301X-Fix-Linksys-EA9500-partitions.patch b/target/linux/bcm53xx/patches-5.10/031-v5.13-0003-ARM-dts-BCM5301X-Fix-Linksys-EA9500-partitions.patch deleted file mode 100644 index d52f46f979..0000000000 --- a/target/linux/bcm53xx/patches-5.10/031-v5.13-0003-ARM-dts-BCM5301X-Fix-Linksys-EA9500-partitions.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 1d3352aeed164ef73f05cf80ca001f11d2f3312d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 29 Mar 2021 07:54:30 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Fix Linksys EA9500 partitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Partitions are basically fixed indeed but firmware ones don't have -hardcoded function ("firmware" vs "failsafe"). Actual function depends -on bootloader configuration. Use a proper binding for that. - -While at it fix numbers formatting to avoid: -arch/arm/boot/dts/bcm47094-linksys-panamera.dt.yaml: partitions: 'partition@1F00000' does not match any of the regexes: '^partition@[0-9a-f]+$', 'pinctrl-[0-9]+' - From schema: Documentation/devicetree/bindings/mtd/partitions/linksys,ns-partitions.yaml - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 16 +++++++--------- - 1 file changed, 7 insertions(+), 9 deletions(-) - ---- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -@@ -279,7 +279,7 @@ - - &nandcs { - partitions { -- compatible = "fixed-partitions"; -+ compatible = "linksys,ns-partitions"; - #address-cells = <1>; - #size-cells = <1>; - -@@ -300,20 +300,18 @@ - }; - - partition@200000 { -- label = "firmware"; -- reg = <0x0200000 0x01D00000>; -- compatible = "brcm,trx"; -+ reg = <0x0200000 0x01d00000>; -+ compatible = "linksys,ns-firmware", "brcm,trx"; - }; - -- partition@1F00000 { -- label = "failsafe"; -- reg = <0x01F00000 0x01D00000>; -- read-only; -+ partition@1f00000 { -+ reg = <0x01f00000 0x01d00000>; -+ compatible = "linksys,ns-firmware", "brcm,trx"; - }; - - partition@5200000 { - label = "system"; -- reg = <0x05200000 0x02E00000>; -+ reg = <0x05200000 0x02e00000>; - }; - }; - }; diff --git a/target/linux/bcm53xx/patches-5.10/031-v5.13-0004-ARM-dts-BCM5301X-Set-Linksys-EA9500-power-LED.patch b/target/linux/bcm53xx/patches-5.10/031-v5.13-0004-ARM-dts-BCM5301X-Set-Linksys-EA9500-power-LED.patch deleted file mode 100644 index 76cb296422..0000000000 --- a/target/linux/bcm53xx/patches-5.10/031-v5.13-0004-ARM-dts-BCM5301X-Set-Linksys-EA9500-power-LED.patch +++ /dev/null @@ -1,27 +0,0 @@ -From dcb56d61d5a8acca0a357cc603397bc0272ce4cb Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 29 Mar 2021 10:04:09 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Set Linksys EA9500 power LED -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Set Linux default trigger to default on, just like it's normally done -for power LEDs. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -@@ -75,6 +75,7 @@ - power { - label = "bcm53xx:white:power"; - gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-on"; - }; - - wifi-disabled { diff --git a/target/linux/bcm53xx/patches-5.10/032-v5.14-0001-ARM-dts-BCM5301X-Fix-NAND-nodes-names.patch b/target/linux/bcm53xx/patches-5.10/032-v5.14-0001-ARM-dts-BCM5301X-Fix-NAND-nodes-names.patch deleted file mode 100644 index 48cceee743..0000000000 --- a/target/linux/bcm53xx/patches-5.10/032-v5.14-0001-ARM-dts-BCM5301X-Fix-NAND-nodes-names.patch +++ /dev/null @@ -1,77 +0,0 @@ -From b660269cba748dfd07eb5551a88ff34d5ea0b86e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 16 Apr 2021 15:37:48 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Fix NAND nodes names -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This matches nand-controller.yaml requirements. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - ---- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -@@ -24,8 +24,8 @@ - reg = <0x00000000 0x08000000>; - }; - -- nand: nand@18028000 { -- nandcs@0 { -+ nand_controller: nand-controller@18028000 { -+ nand@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -@@ -25,8 +25,8 @@ - <0x88000000 0x08000000>; - }; - -- nand: nand@18028000 { -- nandcs@0 { -+ nand_controller: nand-controller@18028000 { -+ nand@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi -+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi -@@ -6,8 +6,8 @@ - */ - - / { -- nand@18028000 { -- nandcs: nandcs@0 { -+ nand-controller@18028000 { -+ nandcs: nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -503,7 +503,7 @@ - reg = <0x18004000 0x14>; - }; - -- nand: nand@18028000 { -+ nand_controller: nand-controller@18028000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; - reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; ---- a/arch/arm/boot/dts/bcm953012k.dts -+++ b/arch/arm/boot/dts/bcm953012k.dts -@@ -49,8 +49,8 @@ - }; - }; - --&nand { -- nandcs@0 { -+&nand_controller { -+ nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-on-flash-bbt; diff --git a/target/linux/bcm53xx/patches-5.10/032-v5.14-0002-ARM-dts-BCM5301X-Fix-pinmux-subnodes-names.patch b/target/linux/bcm53xx/patches-5.10/032-v5.14-0002-ARM-dts-BCM5301X-Fix-pinmux-subnodes-names.patch deleted file mode 100644 index d8a4f87c38..0000000000 --- a/target/linux/bcm53xx/patches-5.10/032-v5.14-0002-ARM-dts-BCM5301X-Fix-pinmux-subnodes-names.patch +++ /dev/null @@ -1,52 +0,0 @@ -From bb95d7d440fefd104c593d9cb20da6d34a474e97 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 21 Apr 2021 11:00:06 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Fix pinmux subnodes names -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This matches pinmux-node.yaml requirements. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094.dtsi | 2 +- - arch/arm/boot/dts/bcm5301x.dtsi | 6 +++--- - 2 files changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/bcm47094.dtsi -+++ b/arch/arm/boot/dts/bcm47094.dtsi -@@ -11,7 +11,7 @@ - &pinctrl { - compatible = "brcm,bcm4709-pinmux"; - -- pinmux_mdio: mdio { -+ pinmux_mdio: mdio-pins { - groups = "mdio_grp"; - function = "mdio"; - }; ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -460,18 +460,18 @@ - function = "spi"; - }; - -- pinmux_i2c: i2c { -+ pinmux_i2c: i2c-pins { - groups = "i2c_grp"; - function = "i2c"; - }; - -- pinmux_pwm: pwm { -+ pinmux_pwm: pwm-pins { - groups = "pwm0_grp", "pwm1_grp", - "pwm2_grp", "pwm3_grp"; - function = "pwm"; - }; - -- pinmux_uart1: uart1 { -+ pinmux_uart1: uart1-pins { - groups = "uart1_grp"; - function = "uart1"; - }; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0001-ARM-dts-NSP-add-device-names-to-compatible.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0001-ARM-dts-NSP-add-device-names-to-compatible.patch deleted file mode 100644 index c994953d4d..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0001-ARM-dts-NSP-add-device-names-to-compatible.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 465078bfdf5271601f098450ae2fc974865c59fd Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Thu, 10 Jun 2021 21:35:10 +0100 -Subject: [PATCH] ARM: dts: NSP: add device names to compatible - -Currently only the SoC type and platform are specified for all NSP -devices. This patch adds the device names. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm958522er.dts | 2 +- - arch/arm/boot/dts/bcm958525er.dts | 2 +- - arch/arm/boot/dts/bcm958525xmc.dts | 2 +- - arch/arm/boot/dts/bcm958622hr.dts | 2 +- - arch/arm/boot/dts/bcm958625hr.dts | 2 +- - arch/arm/boot/dts/bcm958625k.dts | 2 +- - arch/arm/boot/dts/bcm988312hr.dts | 2 +- - 7 files changed, 7 insertions(+), 7 deletions(-) - ---- a/arch/arm/boot/dts/bcm958522er.dts -+++ b/arch/arm/boot/dts/bcm958522er.dts -@@ -37,7 +37,7 @@ - - / { - model = "NorthStar Plus SVK (BCM958522ER)"; -- compatible = "brcm,bcm58522", "brcm,nsp"; -+ compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; ---- a/arch/arm/boot/dts/bcm958525er.dts -+++ b/arch/arm/boot/dts/bcm958525er.dts -@@ -37,7 +37,7 @@ - - / { - model = "NorthStar Plus SVK (BCM958525ER)"; -- compatible = "brcm,bcm58525", "brcm,nsp"; -+ compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; ---- a/arch/arm/boot/dts/bcm958525xmc.dts -+++ b/arch/arm/boot/dts/bcm958525xmc.dts -@@ -37,7 +37,7 @@ - - / { - model = "NorthStar Plus XMC (BCM958525xmc)"; -- compatible = "brcm,bcm58525", "brcm,nsp"; -+ compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; ---- a/arch/arm/boot/dts/bcm958622hr.dts -+++ b/arch/arm/boot/dts/bcm958622hr.dts -@@ -37,7 +37,7 @@ - - / { - model = "NorthStar Plus SVK (BCM958622HR)"; -- compatible = "brcm,bcm58622", "brcm,nsp"; -+ compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; ---- a/arch/arm/boot/dts/bcm958625hr.dts -+++ b/arch/arm/boot/dts/bcm958625hr.dts -@@ -37,7 +37,7 @@ - - / { - model = "NorthStar Plus SVK (BCM958625HR)"; -- compatible = "brcm,bcm58625", "brcm,nsp"; -+ compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; ---- a/arch/arm/boot/dts/bcm958625k.dts -+++ b/arch/arm/boot/dts/bcm958625k.dts -@@ -36,7 +36,7 @@ - - / { - model = "NorthStar Plus SVK (BCM958625K)"; -- compatible = "brcm,bcm58625", "brcm,nsp"; -+ compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; ---- a/arch/arm/boot/dts/bcm988312hr.dts -+++ b/arch/arm/boot/dts/bcm988312hr.dts -@@ -37,7 +37,7 @@ - - / { - model = "NorthStar Plus SVK (BCM988312HR)"; -- compatible = "brcm,bcm88312", "brcm,nsp"; -+ compatible = "brcm,bcm988312hr", "brcm,bcm88312", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0002-ARM-dts-NSP-enable-DMA-on-bcm988312hr.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0002-ARM-dts-NSP-enable-DMA-on-bcm988312hr.patch deleted file mode 100644 index d84124d2dd..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0002-ARM-dts-NSP-enable-DMA-on-bcm988312hr.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 1b90dde4278a7b459979706b572785bc3a10bbb5 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Thu, 10 Jun 2021 21:35:12 +0100 -Subject: [PATCH] ARM: dts: NSP: enable DMA on bcm988312hr - -The previous patch "ARM: dts: NSP: Disable PL330 by default, add -dma-coherent property" set the DMAC to disabled by default, requiring it -to be manually enabled on each device. The bcm988312hr was mistakenly -omitted. This patch adds it back. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm988312hr.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/boot/dts/bcm988312hr.dts -+++ b/arch/arm/boot/dts/bcm988312hr.dts -@@ -58,6 +58,10 @@ - - /* USB 3 support needed to be complete */ - -+&dma { -+ status = "okay"; -+}; -+ - &amac0 { - status = "okay"; - }; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0003-ARM-dts-NSP-disable-qspi-node-by-default.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0003-ARM-dts-NSP-disable-qspi-node-by-default.patch deleted file mode 100644 index e540245b0f..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0003-ARM-dts-NSP-disable-qspi-node-by-default.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 091a12b1814142eac16a115dab206f735b5476a9 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Sun, 13 Jun 2021 10:46:34 +0100 -Subject: [PATCH] ARM: dts: NSP: disable qspi node by default - -The QSPI bus is enabled by default, however this may not used on all -devices. This patch disables by default, requiring it to be explicitly -enabled where required. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 1 + - arch/arm/boot/dts/bcm958522er.dts | 1 + - arch/arm/boot/dts/bcm958525er.dts | 1 + - arch/arm/boot/dts/bcm958525xmc.dts | 1 + - arch/arm/boot/dts/bcm958622hr.dts | 1 + - arch/arm/boot/dts/bcm958623hr.dts | 1 + - arch/arm/boot/dts/bcm958625hr.dts | 1 + - arch/arm/boot/dts/bcm958625k.dts | 1 + - arch/arm/boot/dts/bcm988312hr.dts | 1 + - 9 files changed, 9 insertions(+) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -310,6 +310,7 @@ - num-cs = <2>; - #address-cells = <1>; - #size-cells = <0>; -+ status = "disabled"; - }; - - xhci: usb@29000 { ---- a/arch/arm/boot/dts/bcm958522er.dts -+++ b/arch/arm/boot/dts/bcm958522er.dts -@@ -134,6 +134,7 @@ - }; - - &qspi { -+ status = "okay"; - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm958525er.dts -+++ b/arch/arm/boot/dts/bcm958525er.dts -@@ -134,6 +134,7 @@ - }; - - &qspi { -+ status = "okay"; - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm958525xmc.dts -+++ b/arch/arm/boot/dts/bcm958525xmc.dts -@@ -150,6 +150,7 @@ - }; - - &qspi { -+ status = "okay"; - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm958622hr.dts -+++ b/arch/arm/boot/dts/bcm958622hr.dts -@@ -138,6 +138,7 @@ - }; - - &qspi { -+ status = "okay"; - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm958623hr.dts -+++ b/arch/arm/boot/dts/bcm958623hr.dts -@@ -142,6 +142,7 @@ - }; - - &qspi { -+ status = "okay"; - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm958625hr.dts -+++ b/arch/arm/boot/dts/bcm958625hr.dts -@@ -149,6 +149,7 @@ - }; - - &qspi { -+ status = "okay"; - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm958625k.dts -+++ b/arch/arm/boot/dts/bcm958625k.dts -@@ -153,6 +153,7 @@ - }; - - &qspi { -+ status = "okay"; - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm988312hr.dts -+++ b/arch/arm/boot/dts/bcm988312hr.dts -@@ -138,6 +138,7 @@ - }; - - &qspi { -+ status = "okay"; - bspi-sel = <0>; - flash: m25p80@0 { - #address-cells = <1>; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0004-ARM-dts-NSP-add-MDIO-bus-controller-node.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0004-ARM-dts-NSP-add-MDIO-bus-controller-node.patch deleted file mode 100644 index 6164a22c76..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0004-ARM-dts-NSP-add-MDIO-bus-controller-node.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 236b31b1d84eb0e4f10c5f113a2675529456f919 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Sun, 13 Jun 2021 10:46:36 +0100 -Subject: [PATCH] ARM: dts: NSP: add MDIO bus controller node - -This patch adds the node for the MDIO bus controller, present on the NSP -SoC. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -363,6 +363,13 @@ - status = "disabled"; - }; - -+ mdio: mdio@32000 { -+ compatible = "brcm,iproc-mdio"; -+ reg = <0x32000 0x8>; -+ #size-cells = <0>; -+ #address-cells = <1>; -+ }; -+ - rng: rng@33000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x33000 0x14>; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0005-ARM-dts-NSP-Move-USB3-PHY-to-internal-MDIO-bus.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0005-ARM-dts-NSP-Move-USB3-PHY-to-internal-MDIO-bus.patch deleted file mode 100644 index b760e0fcf2..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0005-ARM-dts-NSP-Move-USB3-PHY-to-internal-MDIO-bus.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 1c615401bddb1be21e1d375aaa071680f40f1ae2 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Sun, 13 Jun 2021 10:46:37 +0100 -Subject: [PATCH] ARM: dts: NSP: Move USB3 PHY to internal MDIO bus - -This patch largely replicates Vivek Unune's patch "ARM: dts: -BCM5301X:Make usb3 phy use mdio phy driver"[1] for the NSP platform, -whereby we need to create an mdio-mux to facilitate switches -configured via external MDIO, in this case on the Meraki MX65. - -However in doing so, we are creating an overlap with usb3_phy's -ccb-mii range. To resolve this, usb3_phy should be moved to a child -node of the internal MDIO bus. The result is heavily based upon Vivek's -patch. This has also been cross-referenced with Yendapally Reddy's -earlier work which utilised the subsequently dropped brcm,nsp-usb3-phy -driver: "[PATCH v2 4/4] arm: dts: nsp: Add USB nodes to device tree" -[2]. Finally, this change provides conformance to the bcm-ns-usb3-phy -documentation, utilising the required usb3-dmp-syscon property. Note -that support for the deprecated ccb-mii bindings has been dropped as of -"phy: phy-bcm-ns-usb3: drop support for deprecated DT binding"[3]. - -[1] https://lore.kernel.org/patchwork/patch/933971/ -[2] https://www.spinics.net/lists/arm-kernel/msg555132.html -[3] https://lore.kernel.org/linux-devicetree/20201113113423.9466-1-zajec5@gmail.com/ - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 38 +++++++++++++++++++++++++++------- - 1 file changed, 31 insertions(+), 7 deletions(-) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -370,6 +370,35 @@ - #address-cells = <1>; - }; - -+ mdio-mux@32000 { -+ compatible = "mdio-mux-mmioreg"; -+ reg = <0x32000 0x4>; -+ mux-mask = <0x200>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ mdio-parent-bus = <&mdio>; -+ -+ mdio_int: mdio@0 { -+ reg = <0x0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usb3_phy: usb3-phy@10 { -+ compatible = "brcm,ns-bx-usb3-phy"; -+ reg = <0x10>; -+ usb3-dmp-syscon = <&usb3_dmp>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ mdio_ext: mdio@200 { -+ reg = <0x200>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ - rng: rng@33000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x33000 0x14>; -@@ -528,13 +557,8 @@ - }; - }; - -- usb3_phy: usb3-phy@104000 { -- compatible = "brcm,ns-bx-usb3-phy"; -- reg = <0x104000 0x1000>, -- <0x032000 0x1000>; -- reg-names = "dmp", "ccb-mii"; -- #phy-cells = <0>; -- status = "disabled"; -+ usb3_dmp: syscon@104000 { -+ reg = <0x104000 0x1000>; - }; - }; - diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0006-ARM-dts-NSP-Add-common-bindings-for-MX64-MX65.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0006-ARM-dts-NSP-Add-common-bindings-for-MX64-MX65.patch deleted file mode 100644 index aebf62af9b..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0006-ARM-dts-NSP-Add-common-bindings-for-MX64-MX65.patch +++ /dev/null @@ -1,148 +0,0 @@ -From f111016a8293b968f05450fec83020c94d0f88c2 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Fri, 6 Aug 2021 21:44:32 +0100 -Subject: [PATCH] ARM: dts: NSP: Add common bindings for MX64/MX65 - -These bindings are required for all Meraki MX64/MX65 devices. These -common bindings include memory (2GB), PWM LEDs, AMAC, I2C (AT24), NAND -partitions, EHCI, OHCI and pinctrl. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - .../dts/bcm958625-meraki-mx6x-common.dtsi | 129 ++++++++++++++++++ - 1 file changed, 129 insertions(+) - create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -@@ -0,0 +1,129 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices. -+ * -+ * Copyright (C) 2020-2021 Matthew Hagan -+ */ -+ -+#include "bcm-nsp.dtsi" -+#include -+#include -+#include -+ -+/ { -+ pwm-leds { -+ compatible = "pwm-leds"; -+ -+ led-1 { -+ function = LED_FUNCTION_INDICATOR; -+ color = ; -+ pwms = <&pwm 1 50000>; -+ max-brightness = <255>; -+ }; -+ -+ led-2 { -+ function = LED_FUNCTION_INDICATOR; -+ color = ; -+ pwms = <&pwm 2 50000>; -+ max-brightness = <255>; -+ }; -+ -+ led-3 { -+ function = LED_FUNCTION_INDICATOR; -+ color = ; -+ pwms = <&pwm 3 50000>; -+ max-brightness = <255>; -+ }; -+ }; -+}; -+ -+&amac2 { -+ status = "okay"; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ at24@50 { -+ compatible = "atmel,24c64"; -+ reg = <0x50>; -+ pagesize = <32>; -+ read-only; -+ }; -+}; -+ -+&nand_controller { -+ nand@0 { -+ compatible = "brcm,nandcs"; -+ reg = <0>; -+ nand-on-flash-bbt; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ nand-ecc-strength = <24>; -+ nand-ecc-step-size = <1024>; -+ -+ brcm,nand-oob-sector-size = <27>; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "shmoo"; -+ reg = <0x80000 0x80000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "bootkernel1"; -+ reg = <0x100000 0x300000>; -+ }; -+ -+ partition@400000 { -+ label = "nvram"; -+ reg = <0x400000 0x100000>; -+ }; -+ -+ partition@500000 { -+ label = "bootkernel2"; -+ reg = <0x500000 0x300000>; -+ }; -+ -+ partition@800000 { -+ label = "ubi"; -+ reg = <0x800000 0x3f700000>; -+ }; -+ }; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&pinctrl { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_leds>; -+ -+ pwm_leds: pwm_leds { -+ function = "pwm"; -+ groups = "pwm1_grp", "pwm2_grp", "pwm3_grp"; -+ }; -+}; -+ -+&pwm { -+ status = "okay"; -+ #pwm-cells = <2>; -+}; -+ -+&uart0 { -+ clock-frequency = <62500000>; -+ status = "okay"; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch deleted file mode 100644 index 39a69bd9a8..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 2addf9266a1d0f4ba59c9868b3effcd50de441a4 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Fri, 6 Aug 2021 21:44:33 +0100 -Subject: [PATCH] ARM: dts: NSP: Add Ax stepping modifications - -While uncommon, some Ax NSP SoCs exist in the wild. This stepping -requires a modified secondary CPU boot-reg and removal of DMA coherency -properties. Without these modifications, the secondary CPU will be -inactive and many peripherals will exhibit undefined behaviour. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 +++++++++++++++++++++++++++++++ - 1 file changed, 70 insertions(+) - create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi - ---- /dev/null -+++ b/arch/arm/boot/dts/bcm-nsp-ax.dtsi -@@ -0,0 +1,70 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Broadcom Northstar Plus Ax stepping-specific bindings. -+ * Notable differences from B0+ are the secondary-boot-reg and -+ * lack of DMA coherency. -+ */ -+ -+&cpu1 { -+ secondary-boot-reg = <0xffff042c>; -+}; -+ -+&dma { -+ /delete-property/ dma-coherent; -+}; -+ -+&sdio { -+ /delete-property/ dma-coherent; -+}; -+ -+&amac0 { -+ /delete-property/ dma-coherent; -+}; -+ -+&amac1 { -+ /delete-property/ dma-coherent; -+}; -+ -+&amac2 { -+ /delete-property/ dma-coherent; -+}; -+ -+&ehci0 { -+ /delete-property/ dma-coherent; -+}; -+ -+&mailbox { -+ /delete-property/ dma-coherent; -+}; -+ -+&xhci { -+ /delete-property/ dma-coherent; -+}; -+ -+&ehci0 { -+ /delete-property/ dma-coherent; -+}; -+ -+&ohci0 { -+ /delete-property/ dma-coherent; -+}; -+ -+&i2c0 { -+ /delete-property/ dma-coherent; -+}; -+ -+&sata { -+ /delete-property/ dma-coherent; -+}; -+ -+&pcie0 { -+ /delete-property/ dma-coherent; -+}; -+ -+&pcie1 { -+ /delete-property/ dma-coherent; -+}; -+ -+&pcie2 { -+ /delete-property/ dma-coherent; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0008-ARM-dts-NSP-Add-DT-files-for-Meraki-MX64-series.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0008-ARM-dts-NSP-Add-DT-files-for-Meraki-MX64-series.patch deleted file mode 100644 index 8fec1ca29f..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0008-ARM-dts-NSP-Add-DT-files-for-Meraki-MX64-series.patch +++ /dev/null @@ -1,340 +0,0 @@ -From 3f902645280baf0d7dab57c227cc14f43edb45ef Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Fri, 6 Aug 2021 21:44:34 +0100 -Subject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX64 series - -MX64 & MX64W Hardware info: - - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - - Storage: 1 GB (Micron MT29F8G08ABACA) - - Networking: BCM58625 internal switch (5x 1GbE ports) - - USB: 1x USB2.0 - - Serial: Internal header - - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus - -This patch adds the Meraki MX64 series-specific bindings. Since some -devices make use of the older A0 SoC, changes need to be made to -accommodate this case, including removal of coherency options and -modification to the secondary-boot-reg. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/Makefile | 4 + - .../boot/dts/bcm958625-meraki-kingpin.dtsi | 163 ++++++++++++++++++ - .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts | 25 +++ - arch/arm/boot/dts/bcm958625-meraki-mx64.dts | 24 +++ - .../boot/dts/bcm958625-meraki-mx64w-a0.dts | 33 ++++ - arch/arm/boot/dts/bcm958625-meraki-mx64w.dts | 32 ++++ - 6 files changed, 281 insertions(+) - create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi - create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts - create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts - create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts - create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -159,6 +159,10 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ - bcm958525xmc.dtb \ - bcm958622hr.dtb \ - bcm958623hr.dtb \ -+ bcm958625-meraki-mx64.dtb \ -+ bcm958625-meraki-mx64-a0.dtb \ -+ bcm958625-meraki-mx64w.dtb \ -+ bcm958625-meraki-mx64w-a0.dtb \ - bcm958625hr.dtb \ - bcm988312hr.dtb \ - bcm958625k.dtb ---- /dev/null -+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi -@@ -0,0 +1,163 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin). -+ * -+ * Copyright (C) 2020-2021 Matthew Hagan -+ */ -+ -+#include "bcm958625-meraki-mx6x-common.dtsi" -+ -+/ { -+ -+ keys { -+ compatible = "gpio-keys-polled"; -+ autorepeat; -+ poll-interval = <20>; -+ -+ reset { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-0 { -+ /* green:lan1-left */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <0>; -+ color = ; -+ gpios = <&gpioa 19 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-1 { -+ /* green:lan1-right */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <1>; -+ color = ; -+ gpios = <&gpioa 18 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-2 { -+ /* green:lan2-left */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <2>; -+ color = ; -+ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-3 { -+ /* green:lan2-right */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <3>; -+ color = ; -+ gpios = <&gpioa 20 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-4 { -+ /* green:lan3-left */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <4>; -+ color = ; -+ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-5 { -+ /* green:lan3-right */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <5>; -+ color = ; -+ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-6 { -+ /* green:lan4-left */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <6>; -+ color = ; -+ gpios = <&gpioa 28 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-7 { -+ /* green:lan4-right */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <7>; -+ color = ; -+ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-8 { -+ /* green:wan-left */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <8>; -+ color = ; -+ gpios = <&gpioa 30 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-9 { -+ /* green:wan-right */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <9>; -+ color = ; -+ gpios = <&gpioa 29 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-a { -+ /* amber:power */ -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ }; -+ -+ led-b { -+ /* white:status */ -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; -+ -+&srab { -+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ label = "lan1"; -+ reg = <0>; -+ }; -+ -+ port@1 { -+ label = "lan2"; -+ reg = <1>; -+ }; -+ -+ port@2 { -+ label = "lan3"; -+ reg = <2>; -+ }; -+ -+ port@3 { -+ label = "lan4"; -+ reg = <3>; -+ }; -+ -+ port@4 { -+ label = "wan"; -+ reg = <4>; -+ }; -+ -+ port@8 { -+ ethernet = <&amac2>; -+ reg = <8>; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts -@@ -0,0 +1,25 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC. -+ * -+ * Copyright (C) 2020-2021 Matthew Hagan -+ */ -+ -+/dts-v1/; -+ -+#include "bcm958625-meraki-kingpin.dtsi" -+#include "bcm-nsp-ax.dtsi" -+ -+/ { -+ model = "Cisco Meraki MX64(A0)"; -+ compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@60000000 { -+ device_type = "memory"; -+ reg = <0x60000000 0x80000000>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC. -+ * -+ * Copyright (C) 2020-2021 Matthew Hagan -+ */ -+ -+/dts-v1/; -+ -+#include "bcm958625-meraki-kingpin.dtsi" -+ -+/ { -+ model = "Cisco Meraki MX64"; -+ compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@60000000 { -+ device_type = "memory"; -+ reg = <0x60000000 0x80000000>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts -@@ -0,0 +1,33 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC. -+ * -+ * Copyright (C) 2020-2021 Matthew Hagan -+ */ -+ -+/dts-v1/; -+ -+#include "bcm958625-meraki-kingpin.dtsi" -+#include "bcm-nsp-ax.dtsi" -+ -+/ { -+ model = "Cisco Meraki MX64W(A0)"; -+ compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@60000000 { -+ device_type = "memory"; -+ reg = <0x60000000 0x80000000>; -+ }; -+}; -+ -+&pcie0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts -@@ -0,0 +1,32 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC. -+ * -+ * Copyright (C) 2020-2021 Matthew Hagan -+ */ -+ -+/dts-v1/; -+ -+#include "bcm958625-meraki-kingpin.dtsi" -+ -+/ { -+ model = "Cisco Meraki MX64W"; -+ compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@60000000 { -+ device_type = "memory"; -+ reg = <0x60000000 0x80000000>; -+ }; -+}; -+ -+&pcie0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0009-ARM-dts-NSP-Add-DT-files-for-Meraki-MX65-series.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0009-ARM-dts-NSP-Add-DT-files-for-Meraki-MX65-series.patch deleted file mode 100644 index 6b473911ab..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0009-ARM-dts-NSP-Add-DT-files-for-Meraki-MX65-series.patch +++ /dev/null @@ -1,386 +0,0 @@ -From 702a8f4744ed5b480f2b2411858184afdb10f9fd Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Fri, 6 Aug 2021 21:44:35 +0100 -Subject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX65 series - -MX65 & MX65W Hardware info: - - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - - Storage: 1 GB (Micron MT29F8G08ABACA) - - Networking: BCM58625 switch (2x 1GbE ports) - 2x Qualcomm QCA8337 switches (10x 1GbE ports total) - - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12 - - USB: 1x USB2.0 - - Serial: Internal header - - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus. - -Note that a driver and firmware image for the BCM59111 PSE has been -released under GPL, but this is not present in the kernel. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/Makefile | 2 + - arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++ - arch/arm/boot/dts/bcm958625-meraki-mx65.dts | 24 ++ - arch/arm/boot/dts/bcm958625-meraki-mx65w.dts | 32 ++ - 4 files changed, 337 insertions(+) - create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi - create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts - create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -163,6 +163,8 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ - bcm958625-meraki-mx64-a0.dtb \ - bcm958625-meraki-mx64w.dtb \ - bcm958625-meraki-mx64w-a0.dtb \ -+ bcm958625-meraki-mx65.dtb \ -+ bcm958625-meraki-mx65w.dtb \ - bcm958625hr.dtb \ - bcm988312hr.dtb \ - bcm958625k.dtb ---- /dev/null -+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -@@ -0,0 +1,279 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindings for Cisco Meraki MX65 series (Alamo). -+ * -+ * Copyright (C) 2020-2021 Matthew Hagan -+ */ -+ -+#include "bcm958625-meraki-mx6x-common.dtsi" -+ -+/ { -+ keys { -+ compatible = "gpio-keys-polled"; -+ autorepeat; -+ poll-interval = <20>; -+ -+ reset { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-0 { -+ /* green:wan1-left */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <0>; -+ color = ; -+ gpios = <&gpioa 25 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-1 { -+ /* green:wan1-right */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <1>; -+ color = ; -+ gpios = <&gpioa 24 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-2 { -+ /* green:wan2-left */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <2>; -+ color = ; -+ gpios = <&gpioa 27 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-3 { -+ /* green:wan2-right */ -+ function = LED_FUNCTION_ACTIVITY; -+ function-enumerator = <3>; -+ color = ; -+ gpios = <&gpioa 26 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led-4 { -+ /* amber:power */ -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ led-5 { -+ /* white:status */ -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ mdio-mii-mux { -+ compatible = "mdio-mux-mmioreg"; -+ reg = <0x1803f1c0 0x4>; -+ mux-mask = <0x2000>; -+ mdio-parent-bus = <&mdio_ext>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mdio@0 { -+ reg = <0x0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ phy_port6: phy@0 { -+ reg = <0>; -+ }; -+ -+ phy_port7: phy@1 { -+ reg = <1>; -+ }; -+ -+ phy_port8: phy@2 { -+ reg = <2>; -+ }; -+ -+ phy_port9: phy@3 { -+ reg = <3>; -+ }; -+ -+ phy_port10: phy@4 { -+ reg = <4>; -+ }; -+ -+ switch@10 { -+ compatible = "qca,qca8337"; -+ reg = <0x10>; -+ dsa,member = <1 0>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ port@0 { -+ reg = <0>; -+ ethernet = <&sgmii1>; -+ phy-mode = "sgmii"; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan8"; -+ phy-handle = <&phy_port6>; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan9"; -+ phy-handle = <&phy_port7>; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan10"; -+ phy-handle = <&phy_port8>; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan11"; -+ phy-handle = <&phy_port9>; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "lan12"; -+ phy-handle = <&phy_port10>; -+ }; -+ }; -+ }; -+ }; -+ -+ mdio-mii@2000 { -+ reg = <0x2000>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ phy_port1: phy@0 { -+ reg = <0>; -+ }; -+ -+ phy_port2: phy@1 { -+ reg = <1>; -+ }; -+ -+ phy_port3: phy@2 { -+ reg = <2>; -+ }; -+ -+ phy_port4: phy@3 { -+ reg = <3>; -+ }; -+ -+ phy_port5: phy@4 { -+ reg = <4>; -+ }; -+ -+ switch@10 { -+ compatible = "qca,qca8337"; -+ reg = <0x10>; -+ dsa,member = <2 0>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ port@0 { -+ reg = <0>; -+ ethernet = <&sgmii0>; -+ phy-mode = "sgmii"; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan3"; -+ phy-handle = <&phy_port1>; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan4"; -+ phy-handle = <&phy_port2>; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan5"; -+ phy-handle = <&phy_port3>; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan6"; -+ phy-handle = <&phy_port4>; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "lan7"; -+ phy-handle = <&phy_port5>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&srab { -+ compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; -+ status = "okay"; -+ dsa,member = <0 0>; -+ -+ ports { -+ port@0 { -+ label = "wan1"; -+ reg = <0>; -+ }; -+ -+ port@1 { -+ label = "wan2"; -+ reg = <1>; -+ }; -+ -+ sgmii0: port@4 { -+ label = "sw0"; -+ reg = <4>; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ sgmii1: port@5 { -+ label = "sw1"; -+ reg = <5>; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@8 { -+ ethernet = <&amac2>; -+ reg = <8>; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindings for Cisco Meraki MX65. -+ * -+ * Copyright (C) 2020-2021 Matthew Hagan -+ */ -+ -+/dts-v1/; -+ -+#include "bcm958625-meraki-alamo.dtsi" -+ -+/ { -+ model = "Cisco Meraki MX65"; -+ compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@60000000 { -+ device_type = "memory"; -+ reg = <0x60000000 0x80000000>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts -@@ -0,0 +1,32 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindings for Cisco Meraki MX65W. -+ * -+ * Copyright (C) 2020-2021 Matthew Hagan -+ */ -+ -+/dts-v1/; -+ -+#include "bcm958625-meraki-alamo.dtsi" -+ -+/ { -+ model = "Cisco Meraki MX65W"; -+ compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory@60000000 { -+ device_type = "memory"; -+ reg = <0x60000000 0x80000000>; -+ }; -+}; -+ -+&pcie0 { -+ status = "okay"; -+}; -+ -+&pcie1 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0010-ARM-dts-BCM5301X-Fix-nodes-names.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0010-ARM-dts-BCM5301X-Fix-nodes-names.patch deleted file mode 100644 index e779d45645..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0010-ARM-dts-BCM5301X-Fix-nodes-names.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 0e89c0d8e8edece7f8e4607841ca6651885d23b1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 19 Aug 2021 08:57:00 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Fix nodes names -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes following errors for all BCM5301X dts files: -chipcommonA@18000000: $nodename:0: 'chipcommonA@18000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' -mpcore@19000000: $nodename:0: 'mpcore@19000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' -mdio-bus-mux@18003000: $nodename:0: 'mdio-bus-mux@18003000' does not match '^mdio-mux[\\-@]?' -dmu@1800c000: $nodename:0: 'dmu@1800c000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 2 +- - arch/arm/boot/dts/bcm5301x.dtsi | 8 ++++---- - 2 files changed, 5 insertions(+), 5 deletions(-) - ---- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -@@ -129,7 +129,7 @@ - }; - }; - -- mdio-bus-mux@18003000 { -+ mdio-mux@18003000 { - - /* BIT(9) = 1 => external mdio */ - mdio@200 { ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -19,7 +19,7 @@ - #size-cells = <1>; - interrupt-parent = <&gic>; - -- chipcommonA@18000000 { -+ chipcommon-a-bus@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x00001000>; - #address-cells = <1>; -@@ -44,7 +44,7 @@ - }; - }; - -- mpcore@19000000 { -+ mpcore-bus@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; -@@ -371,7 +371,7 @@ - #address-cells = <1>; - }; - -- mdio-bus-mux@18003000 { -+ mdio-mux@18003000 { - compatible = "mdio-mux-mmioreg"; - mdio-parent-bus = <&mdio>; - #address-cells = <1>; -@@ -417,7 +417,7 @@ - status = "disabled"; - }; - -- dmu@1800c000 { -+ dmu-bus@1800c000 { - compatible = "simple-bus"; - ranges = <0 0x1800c000 0x1000>; - #address-cells = <1>; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.15-0011-ARM-dts-BCM5301X-Fix-MDIO-mux-binding.patch b/target/linux/bcm53xx/patches-5.10/033-v5.15-0011-ARM-dts-BCM5301X-Fix-MDIO-mux-binding.patch deleted file mode 100644 index dc20720dbd..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.15-0011-ARM-dts-BCM5301X-Fix-MDIO-mux-binding.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 75a5646c26895c4cfadc8d54aa53ac5455947895 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 19 Aug 2021 08:57:01 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Fix MDIO mux binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes following error for all BCM5301X dts files: -mdio-bus-mux@18003000: compatible: ['mdio-mux-mmioreg'] is too short - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -372,7 +372,7 @@ - }; - - mdio-mux@18003000 { -- compatible = "mdio-mux-mmioreg"; -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; - mdio-parent-bus = <&mdio>; - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0013-ARM-dts-NSP-Add-bcm958623hr-board-name-to-dts.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0013-ARM-dts-NSP-Add-bcm958623hr-board-name-to-dts.patch deleted file mode 100644 index c5f28474e3..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0013-ARM-dts-NSP-Add-bcm958623hr-board-name-to-dts.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 695717eb4c61173d05a277e37132b5e2c6531bf1 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Sun, 29 Aug 2021 22:37:47 +0000 -Subject: [PATCH] ARM: dts: NSP: Add bcm958623hr board name to dts - -This board was previously added to -Documentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml -however the dts file was not updated to reflect this change. This patch -corrects bcm958623hr.dts by adding the board name to the compatible. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm958623hr.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm958623hr.dts -+++ b/arch/arm/boot/dts/bcm958623hr.dts -@@ -37,7 +37,7 @@ - - / { - model = "NorthStar Plus SVK (BCM958623HR)"; -- compatible = "brcm,bcm58623", "brcm,nsp"; -+ compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp"; - - chosen { - stdout-path = "serial0:115200n8"; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0015-ARM-dts-NSP-Fix-MDIO-mux-node-names.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0015-ARM-dts-NSP-Fix-MDIO-mux-node-names.patch deleted file mode 100644 index a7c0f16719..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0015-ARM-dts-NSP-Fix-MDIO-mux-node-names.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 38f8111369f318a538e9d4d89d8e48030c22fb40 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Sun, 29 Aug 2021 22:37:49 +0000 -Subject: [PATCH] ARM: dts: NSP: Fix MDIO mux node names - -While functional, the mdio-mux-mmioreg binding does not conform to -Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml in that an -mdio-mux compatible is also required. Without this the following output -is observed when running dtbs_check: - -mdio-mux@32000: compatible: ['mdio-mux-mmioreg'] is too short - -This change brings conformance to this requirement and corresponds -likewise to Rafal Milecki's change to the BCM5301x platform[1]. - -[1] https://lore.kernel.org/linux-arm-kernel/20210822191256.3715003-1-f.fainelli@gmail.com/T/ - -Signed-off-by: Matthew Hagan -Reviewed-by: Andrew Lunn -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- - arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -371,7 +371,7 @@ - }; - - mdio-mux@32000 { -- compatible = "mdio-mux-mmioreg"; -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; - reg = <0x32000 0x4>; - mux-mask = <0x200>; - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -@@ -72,7 +72,7 @@ - }; - - mdio-mii-mux { -- compatible = "mdio-mux-mmioreg"; -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; - reg = <0x1803f1c0 0x4>; - mux-mask = <0x2000>; - mdio-parent-bus = <&mdio_ext>; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0016-ARM-dts-NSP-Fix-MX64-MX65-eeprom-node-name.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0016-ARM-dts-NSP-Fix-MX64-MX65-eeprom-node-name.patch deleted file mode 100644 index 4cffad1f4e..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0016-ARM-dts-NSP-Fix-MX64-MX65-eeprom-node-name.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 56e4e548427240d85fd220460d0ab5987e1dec00 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Sun, 29 Aug 2021 22:37:50 +0000 -Subject: [PATCH] ARM: dts: NSP: Fix MX64/MX65 eeprom node name - -Running dtbs_check yields the following message when checking the -MX64/MX65 devicetree: -at24@50: $nodename:0: 'at24@50' does not match '^eeprom@[0-9a-f]{1,2}$' - -This patch fixes the issue by renaming the at24 node appropriately. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -@@ -48,7 +48,7 @@ - &i2c0 { - status = "okay"; - -- at24@50 { -+ eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0017-ARM-dts-NSP-Fix-MX65-MDIO-mux-warnings.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0017-ARM-dts-NSP-Fix-MX65-MDIO-mux-warnings.patch deleted file mode 100644 index cad7388685..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0017-ARM-dts-NSP-Fix-MX65-MDIO-mux-warnings.patch +++ /dev/null @@ -1,52 +0,0 @@ -From f5fc9044e5d45a4d97b5240c8723f4677f647c9f Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Sun, 29 Aug 2021 22:37:51 +0000 -Subject: [PATCH] ARM: dts: NSP: Fix MX65 MDIO mux warnings - -The naming of this node is based upon that of the initial EA9500 dts[1]. -However this does not conform with the mdio-mux format, yielding the -following message when running dtbs_check: -mdio-mii-mux: $nodename:0: 'mdio-mii-mux' does not match '^mdio-mux[\\-@]?' - -Secondly, this node should be moved to within the axi node and given the -appropriate unit address. This also requires exposing the axi node via a -label in bcm-nsp.dtsi. This fixes the following warning: -Warning (unit_address_vs_reg): /mdio-mii-mux: node has a reg or ranges property, but no unit name - -[1]https://patchwork.ozlabs.org/project/linux-imx/patch/20180618174159.86150-1-npcomplete13@gmail.com/#1941353 - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- - arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 6 ++++-- - 2 files changed, 5 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -166,7 +166,7 @@ - }; - }; - -- axi@18000000 { -+ axi: axi@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x0011c40c>; - #address-cells = <1>; ---- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -@@ -70,10 +70,12 @@ - gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>; - }; - }; -+}; - -- mdio-mii-mux { -+&axi { -+ mdio-mux@3f1c0 { - compatible = "mdio-mux-mmioreg", "mdio-mux"; -- reg = <0x1803f1c0 0x4>; -+ reg = <0x3f1c0 0x4>; - mux-mask = <0x2000>; - mdio-parent-bus = <&mdio_ext>; - #address-cells = <1>; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0018-ARM-dts-BCM5301X-Specify-switch-ports-for-more-devic.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0018-ARM-dts-BCM5301X-Specify-switch-ports-for-more-devic.patch deleted file mode 100644 index b309771369..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0018-ARM-dts-BCM5301X-Specify-switch-ports-for-more-devic.patch +++ /dev/null @@ -1,290 +0,0 @@ -From 225ffaf3d0e00daa2d0c7b68e8fd731ebbde3c03 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 7 Sep 2021 08:00:48 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Specify switch ports for more devices -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Those are remaining models I have that didn't have ports yet. All -tested. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 37 ++++++++++++++++ - .../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 37 ++++++++++++++++ - arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 42 +++++++++++++++++++ - arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 42 +++++++++++++++++++ - arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 37 ++++++++++++++++ - arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 37 ++++++++++++++++ - 6 files changed, 232 insertions(+) - ---- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -@@ -94,3 +94,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan4"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan3"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan1"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -@@ -117,3 +117,40 @@ - }; - }; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -@@ -187,3 +187,45 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@8 { -+ reg = <8>; -+ label = "cpu"; -+ ethernet = <&gmac2>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -@@ -118,3 +118,45 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan4"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan3"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan1"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@8 { -+ reg = <8>; -+ label = "cpu"; -+ ethernet = <&gmac2>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts -@@ -68,3 +68,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan4"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan2"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan1"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts -@@ -68,3 +68,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan4"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan2"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan1"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0019-ARM-dts-BCM53573-Describe-on-SoC-BCM53125-rev-4-swit.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0019-ARM-dts-BCM53573-Describe-on-SoC-BCM53125-rev-4-swit.patch deleted file mode 100644 index 3a5438c228..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0019-ARM-dts-BCM53573-Describe-on-SoC-BCM53125-rev-4-swit.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 9fb90ae6cae7f8fe4fbf626945f32cd9da2c3892 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 20 Sep 2021 16:10:23 +0200 -Subject: [PATCH] ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM53573 family SoC have Ethernet switch connected to the first Ethernet -controller (accessible over MDIO). - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm53573.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm/boot/dts/bcm53573.dtsi -+++ b/arch/arm/boot/dts/bcm53573.dtsi -@@ -180,6 +180,24 @@ - - gmac0: ethernet@5000 { - reg = <0x5000 0x1000>; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ switch: switch@1e { -+ compatible = "brcm,bcm53125"; -+ reg = <0x1e>; -+ -+ status = "disabled"; -+ -+ /* ports are defined in board DTS */ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; - }; - - gmac1: ethernet@b000 { diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0020-ARM-dts-BCM53573-Add-Tenda-AC9-switch-ports.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0020-ARM-dts-BCM53573-Add-Tenda-AC9-switch-ports.patch deleted file mode 100644 index c6d995723c..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0020-ARM-dts-BCM53573-Add-Tenda-AC9-switch-ports.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 64612828628cca6e3992e421f45c242dc6625647 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 20 Sep 2021 16:10:24 +0200 -Subject: [PATCH] ARM: dts: BCM53573: Add Tenda AC9 switch ports -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This router has 1 WAN and 4 LAN ports. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 37 ++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - ---- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts -+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts -@@ -105,3 +105,40 @@ - }; - }; - }; -+ -+&switch { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan4"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0021-ARM-BCM53016-Specify-switch-ports-for-Meraki-MR32.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0021-ARM-BCM53016-Specify-switch-ports-for-Meraki-MR32.patch deleted file mode 100644 index 35f697c66f..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0021-ARM-BCM53016-Specify-switch-ports-for-Meraki-MR32.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 6abc4ca5a28070945e0d68cb4160b309bfbf4b8b Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sat, 18 Sep 2021 19:29:30 +0200 -Subject: [PATCH] ARM: BCM53016: Specify switch ports for Meraki MR32 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -the switch identifies itself as a BCM53012 (rev 5)... -This patch has been tested & verified on OpenWrt's -snapshot with Linux 5.10 (didn't test any older kernels). -The MR32 is able to "talk to the network" as before with -OpenWrt's SWITCHDEV b53 driver. - -| b53-srab-switch 18007000.ethernet-switch: found switch: BCM53012, rev 5 -| libphy: dsa slave smi: probed -| b53-srab-switch 18007000.ethernet-switch poe (uninitialized): -| PHY [dsa-0.0:00] driver [Generic PHY] (irq=POLL) -| b53-srab-switch 18007000.ethernet-switch: Using legacy PHYLIB callbacks. -| Please migrate to PHYLINK! -| DSA: tree 0 setup - -Reported-by: Rafał Miłecki -Signed-off-by: Christian Lamparter -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -@@ -217,3 +217,25 @@ - }; - }; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "poe"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ -+ fixed-link { -+ speed = <1000>; -+ duplex-full; -+ }; -+ }; -+ }; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0022-ARM-BCM53016-MR32-get-mac-address-from-nvmem.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0022-ARM-BCM53016-MR32-get-mac-address-from-nvmem.patch deleted file mode 100644 index 70a18822a9..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0022-ARM-BCM53016-MR32-get-mac-address-from-nvmem.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 477ffdbdf389cc91294d66e251cc6f856da5820c Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sat, 18 Sep 2021 19:29:31 +0200 -Subject: [PATCH] ARM: BCM53016: MR32: get mac-address from nvmem - -The MAC-Address of the MR32's sole ethernet port is -located in offset 0x66 of the attached AT24C64 eeprom. - -Signed-off-by: Christian Lamparter -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -@@ -110,6 +110,12 @@ - reg = <0x50>; - pagesize = <32>; - read-only; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ mac_address: mac-address@66 { -+ reg = <0x66 0x6>; -+ }; - }; - }; - }; -@@ -133,6 +139,11 @@ - */ - }; - -+&gmac0 { -+ nvmem-cell-names = "mac-address"; -+ nvmem-cells = <&mac_address>; -+}; -+ - &gmac1 { - status = "disabled"; - }; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0023-ARM-dts-BCM5301X-Add-DT-for-Asus-RT-AC88U.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0023-ARM-dts-BCM5301X-Add-DT-for-Asus-RT-AC88U.patch deleted file mode 100644 index 70955269f6..0000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0023-ARM-dts-BCM5301X-Add-DT-for-Asus-RT-AC88U.patch +++ /dev/null @@ -1,242 +0,0 @@ -From beff77b93452cd2057c859694709dd34a181488f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Tue, 21 Sep 2021 20:19:01 +0800 -Subject: [PATCH] ARM: dts: BCM5301X: Add DT for Asus RT-AC88U -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Hardware Info -------------- - -Processor - Broadcom BCM4709C0KFEBG dual-core @ 1.4 GHz -Switch - BCM53012 in BCM4709C0KFEBG & external RTL8365MB -DDR3 RAM - 512 MB -Flash - 128 MB (ESMT F59L1G81LA-25T) -2.4GHz - BCM4366 4×4 2.4/5G single chip 802.11ac SoC -5GHz - BCM4366 4×4 2.4/5G single chip 802.11ac SoC -Ports - 8 Ports, 1 WAN Ports - -Tested on OpenWrt on kernel 5.10 built with DSA driver. - -Signed-off-by: Arınç ÜNAL -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 200 +++++++++++++++++++ - 2 files changed, 201 insertions(+) - create mode 100644 arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -118,6 +118,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm4709-netgear-r7000.dtb \ - bcm4709-netgear-r8000.dtb \ - bcm4709-tplink-archer-c9-v1.dtb \ -+ bcm47094-asus-rt-ac88u.dtb \ - bcm47094-dlink-dir-885l.dtb \ - bcm47094-linksys-panamera.dtb \ - bcm47094-luxul-abr-4500.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -0,0 +1,200 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (C) 2021 Arınç ÜNAL -+ */ -+ -+/dts-v1/; -+ -+#include "bcm47094.dtsi" -+#include "bcm5301x-nand-cs0-bch8.dtsi" -+ -+/ { -+ compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708"; -+ model = "Asus RT-AC88U"; -+ -+ chosen { -+ bootargs = "earlycon"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00000000 0x08000000>, -+ <0x88000000 0x18000000>; -+ }; -+ -+ nvram@1c080000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1c080000 0x00180000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ power { -+ label = "white:power"; -+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ wan-red { -+ label = "red:wan"; -+ gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ lan { -+ label = "white:lan"; -+ gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; -+ }; -+ -+ usb2 { -+ label = "white:usb2"; -+ gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; -+ trigger-sources = <&ehci_port2>; -+ linux,default-trigger = "usbport"; -+ }; -+ -+ usb3 { -+ label = "white:usb3"; -+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; -+ trigger-sources = <&ehci_port1>, <&xhci_port1>; -+ linux,default-trigger = "usbport"; -+ }; -+ -+ wps { -+ label = "white:wps"; -+ gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ wps { -+ label = "WPS"; -+ linux,code = ; -+ gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; -+ }; -+ -+ reset { -+ label = "Reset"; -+ linux,code = ; -+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wifi { -+ label = "Wi-Fi"; -+ linux,code = ; -+ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; -+ }; -+ -+ led { -+ label = "Backlight"; -+ linux,code = ; -+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&srab { -+ compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; -+ status = "okay"; -+ dsa,member = <0 0>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ label = "lan4"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan3"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan1"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ sw0_p5: port@5 { -+ reg = <5>; -+ label = "extsw"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@7 { -+ reg = <7>; -+ ethernet = <&gmac1>; -+ label = "cpu"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@8 { -+ reg = <8>; -+ ethernet = <&gmac2>; -+ label = "cpu"; -+ status = "disabled"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+}; -+ -+&usb2 { -+ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -+}; -+ -+&usb3_phy { -+ status = "okay"; -+}; -+ -+&nandcs { -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "boot"; -+ reg = <0x00000000 0x00080000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "nvram"; -+ reg = <0x00080000 0x00180000>; -+ }; -+ -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x00200000 0x07e00000>; -+ compatible = "brcm,trx"; -+ }; -+ }; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0001-ARM-dts-NSP-MX65-add-qca8k-falling-edge-PLL-properti.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0001-ARM-dts-NSP-MX65-add-qca8k-falling-edge-PLL-properti.patch deleted file mode 100644 index a0be1eda4d..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0001-ARM-dts-NSP-MX65-add-qca8k-falling-edge-PLL-properti.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 58d3d07985c1adab31a3ed76360d016bb1c5b358 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Fri, 15 Oct 2021 23:50:22 +0100 -Subject: [PATCH] ARM: dts: NSP: MX65: add qca8k falling-edge, PLL properties - -This patch enables two properties for the QCA8337 switches on the MX65. - -Set the SGMII transmit clock to falling edge -"qca,sgmii-txclk-falling-edge" to conform to the OEM configuration [1]. - -The new explicit PLL enable option "qca,sgmii-enable-pll" is required -[2]. - -[1] https://git.kernel.org/netdev/net-next/c/6c43809bf1be -[2] https://git.kernel.org/netdev/net-next/c/bbc4799e8bb6 - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -@@ -118,6 +118,8 @@ - reg = <0>; - ethernet = <&sgmii1>; - phy-mode = "sgmii"; -+ qca,sgmii-enable-pll; -+ qca,sgmii-txclk-falling-edge; - fixed-link { - speed = <1000>; - full-duplex; -@@ -194,6 +196,8 @@ - reg = <0>; - ethernet = <&sgmii0>; - phy-mode = "sgmii"; -+ qca,sgmii-enable-pll; -+ qca,sgmii-txclk-falling-edge; - fixed-link { - speed = <1000>; - full-duplex; diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0002-ARM-dts-BCM5301X-remove-unnecessary-address-size-cel.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0002-ARM-dts-BCM5301X-remove-unnecessary-address-size-cel.patch deleted file mode 100644 index 3c3725adec..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0002-ARM-dts-BCM5301X-remove-unnecessary-address-size-cel.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 835992e7eca4b29a87c204cefff2f7863fd087f3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Wed, 27 Oct 2021 00:57:03 +0800 -Subject: [PATCH] ARM: dts: BCM5301X: remove unnecessary address & size cells - from Asus RT-AC88U -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Remove the unnecessary #address-cells & #size-cells in the gpio-keys node -from the device tree of Asus RT-AC88U. - -Signed-off-by: Arınç ÜNAL -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 2 -- - 1 file changed, 2 deletions(-) - ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -68,8 +68,6 @@ - - gpio-keys { - compatible = "gpio-keys"; -- #address-cells = <1>; -- #size-cells = <0>; - - wps { - label = "WPS"; diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0003-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0003-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch deleted file mode 100644 index 562d5a22c7..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0003-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch +++ /dev/null @@ -1,104 +0,0 @@ -From b6c99228c8edc5e67d8229ba1c5f76cce210ddfc Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Wed, 27 Oct 2021 00:57:06 +0800 -Subject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Define the Realtek RTL8365MB switch without interrupt support on the device -tree of Asus RT-AC88U. - -Signed-off-by: Arınç ÜNAL -Acked-by: Alvin Å ipraga -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++ - 1 file changed, 77 insertions(+) - ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -93,6 +93,83 @@ - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - }; -+ -+ switch { -+ compatible = "realtek,rtl8365mb"; -+ /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ -+ mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; -+ mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; -+ realtek,disable-leds; -+ dsa,member = <1 0>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ port@0 { -+ reg = <0>; -+ label = "lan5"; -+ phy-handle = <ðphy0>; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan6"; -+ phy-handle = <ðphy1>; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan7"; -+ phy-handle = <ðphy2>; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan8"; -+ phy-handle = <ðphy3>; -+ }; -+ -+ port@6 { -+ reg = <6>; -+ label = "cpu"; -+ ethernet = <&sw0_p5>; -+ phy-mode = "rgmii"; -+ tx-internal-delay-ps = <2000>; -+ rx-internal-delay-ps = <2000>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ }; -+ -+ mdio { -+ compatible = "realtek,smi-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ ethphy2: ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ ethphy3: ethernet-phy@3 { -+ reg = <3>; -+ }; -+ }; -+ }; - }; - - &srab { diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0004-ARM-BCM53016-MR32-convert-to-Broadcom-iProc-I2C-Driv.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0004-ARM-BCM53016-MR32-convert-to-Broadcom-iProc-I2C-Driv.patch deleted file mode 100644 index 6118e98cc5..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0004-ARM-BCM53016-MR32-convert-to-Broadcom-iProc-I2C-Driv.patch +++ /dev/null @@ -1,104 +0,0 @@ -From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Thu, 28 Oct 2021 09:03:44 +0200 -Subject: [PATCH] ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -replaces the bit-banged i2c-gpio provided i2c functionality -with the hardware in the SoC. - -During review of the MR32, Florian Fainelli pointed out that the -SoC has a real I2C-controller. Furthermore, the connected pins -(SDA and SCL) would line up perfectly for use. Back then I couldn't -get it working though and I left it with i2c-gpio (which worked). - -Now we know the reason: the interrupt was incorrectly specified. -(Hence, this patch depends on Florian Fainelli's -"ARM: dts: BCM5301X: Fix I2C controller interrupt" patch). - -Cc: Florian Fainelli -Cc: Rafał Miłecki -Cc: Matthew Hagan -Signed-off-by: Christian Lamparter -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++------------ - 1 file changed, 28 insertions(+), 34 deletions(-) - ---- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -@@ -84,40 +84,6 @@ - max-brightness = <255>; - }; - }; -- -- i2c { -- /* -- * The platform provided I2C does not budge. -- * This is a replacement until I can figure -- * out what are the missing bits... -- */ -- -- compatible = "i2c-gpio"; -- sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; -- scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; -- i2c-gpio,delay-us = <10>; /* close to 100 kHz */ -- #address-cells = <1>; -- #size-cells = <0>; -- -- current_sense: ina219@45 { -- compatible = "ti,ina219"; -- reg = <0x45>; -- shunt-resistor = <60000>; /* = 60 mOhms */ -- }; -- -- eeprom: eeprom@50 { -- compatible = "atmel,24c64"; -- reg = <0x50>; -- pagesize = <32>; -- read-only; -- #address-cells = <1>; -- #size-cells = <1>; -- -- mac_address: mac-address@66 { -- reg = <0x66 0x6>; -- }; -- }; -- }; - }; - - &uart0 { -@@ -250,3 +216,31 @@ - }; - }; - }; -+ -+&i2c0 { -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinmux_i2c>; -+ -+ clock-frequency = <100000>; -+ -+ current_sense: ina219@45 { -+ compatible = "ti,ina219"; -+ reg = <0x45>; -+ shunt-resistor = <60000>; /* = 60 mOhms */ -+ }; -+ -+ eeprom: eeprom@50 { -+ compatible = "atmel,24c64"; -+ reg = <0x50>; -+ pagesize = <32>; -+ read-only; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ mac_address: mac-address@66 { -+ reg = <0x66 0x6>; -+ }; -+ }; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0005-ARM-dts-BCM5301X-update-CRU-block-description.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0005-ARM-dts-BCM5301X-update-CRU-block-description.patch deleted file mode 100644 index 0a817e8fd1..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0005-ARM-dts-BCM5301X-update-CRU-block-description.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 29 Oct 2021 18:05:23 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: update CRU block description -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This describes CRU in a way matching documentation and fixes: - -arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' - From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -423,14 +423,14 @@ - #address-cells = <1>; - #size-cells = <1>; - -- cru@100 { -- compatible = "simple-bus"; -+ cru-bus@100 { -+ compatible = "brcm,ns-cru", "simple-mfd"; - reg = <0x100 0x1a4>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - -- lcpll0: lcpll0@100 { -+ lcpll0: clock-controller@100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x100 0x14>; -@@ -439,7 +439,7 @@ - "sdio", "ddr_phy"; - }; - -- genpll: genpll@140 { -+ genpll: clock-controller@140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x140 0x24>; -@@ -450,6 +450,11 @@ - "sata1", "sata2"; - }; - -+ syscon@180 { -+ compatible = "brcm,cru-clkset", "syscon"; -+ reg = <0x180 0x4>; -+ }; -+ - pinctrl: pin-controller@1c0 { - compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0006-ARM-dts-BCM5301X-use-non-deprecated-USB-2.0-PHY-bind.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0006-ARM-dts-BCM5301X-use-non-deprecated-USB-2.0-PHY-bind.patch deleted file mode 100644 index e01927bedf..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0006-ARM-dts-BCM5301X-use-non-deprecated-USB-2.0-PHY-bind.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 1a46061a2a4130a08841941ce6dcaa32be2ce312 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 23 Nov 2021 10:03:33 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY binding -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The new binding covers a single reg and uses syscon to reference shared -register. - -References: 55b9b741712d ("dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block") -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -148,15 +148,6 @@ - }; - }; - -- usb2_phy: usb2-phy@1800c000 { -- compatible = "brcm,ns-usb2-phy"; -- reg = <0x1800c000 0x1000>; -- reg-names = "dmu"; -- #phy-cells = <0>; -- clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; -- clock-names = "phy-ref-clk"; -- }; -- - axi@18000000 { - compatible = "brcm,bus-axi"; - reg = <0x18000000 0x1000>; -@@ -450,7 +441,16 @@ - "sata1", "sata2"; - }; - -- syscon@180 { -+ usb2_phy: phy@164 { -+ compatible = "brcm,ns-usb2-phy"; -+ reg = <0x164 0x4>; -+ brcm,syscon-clkset = <&cru_clkset>; -+ clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; -+ clock-names = "phy-ref-clk"; -+ #phy-cells = <0>; -+ }; -+ -+ cru_clkset: syscon@180 { - compatible = "brcm,cru-clkset", "syscon"; - reg = <0x180 0x4>; - }; diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0007-ARM-dts-NSP-Fixed-iProc-PCIe-MSI-sub-node.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0007-ARM-dts-NSP-Fixed-iProc-PCIe-MSI-sub-node.patch deleted file mode 100644 index 730b989808..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0007-ARM-dts-NSP-Fixed-iProc-PCIe-MSI-sub-node.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 69c4e53bdd055ecc27761f6971a50c631ff9072e Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Thu, 2 Dec 2021 15:16:27 -0800 -Subject: [PATCH] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node - -Rename the msi controller unit name to 'msi' to avoid collisions with -the 'msi-controller' boolean property. - -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -587,7 +587,7 @@ - status = "disabled"; - - msi-parent = <&msi0>; -- msi0: msi-controller { -+ msi0: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; -@@ -624,7 +624,7 @@ - status = "disabled"; - - msi-parent = <&msi1>; -- msi1: msi-controller { -+ msi1: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; -@@ -661,7 +661,7 @@ - status = "disabled"; - - msi-parent = <&msi2>; -- msi2: msi-controller { -+ msi2: msi { - compatible = "brcm,iproc-msi"; - msi-controller; - interrupt-parent = <&gic>; diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0008-ARM-dts-NSP-Rename-SATA-unit-name.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0008-ARM-dts-NSP-Rename-SATA-unit-name.patch deleted file mode 100644 index fd90fbf1f6..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0008-ARM-dts-NSP-Rename-SATA-unit-name.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 9a68c53f875e88edd3403c001ad85f4ac0ed3486 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Tue, 7 Dec 2021 10:19:09 -0800 -Subject: [PATCH] ARM: dts: NSP: Rename SATA unit name - -Rename the SATA controller unit name from ahci to sata in preparation -for adding the Broadcom SATA3 controller YAML binding which will bring -validation. - -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm-nsp.dtsi -+++ b/arch/arm/boot/dts/bcm-nsp.dtsi -@@ -534,7 +534,7 @@ - }; - }; - -- sata: ahci@41000 { -+ sata: sata@41000 { - compatible = "brcm,bcm-nsp-ahci"; - reg-names = "ahci", "top-ctrl"; - reg = <0x41000 0x1000>, <0x40020 0x1c>; diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0009-ARM-dts-BCM5301X-correct-RX-delay-and-enable-flow-co.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0009-ARM-dts-BCM5301X-correct-RX-delay-and-enable-flow-co.patch deleted file mode 100644 index e81ec169b9..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0009-ARM-dts-BCM5301X-correct-RX-delay-and-enable-flow-co.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Fri, 17 Dec 2021 00:03:19 +0800 -Subject: [PATCH] ARM: dts: BCM5301X: correct RX delay and enable flow control - on Asus RT-AC88U -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The current 'rx-internal-delay-ps' property value on the Realtek switch -node, 2000, will be divided by 300, resulting in 6.66, which will be -rounded to the closest step value, 7. Change it to 2100 to be accurate. -See ef136837aaf6 ("net: dsa: rtl8365mb: set RGMII RX delay in steps of -0.3 ns") for reference. - -Flow control needs to be enabled on both sides of the internal and -external switch. It is already enabled on the CPU port of the Realtek -switch so we also enable it on the external switch port of the Broadcom -switch as well. - -Signed-off-by: Arınç ÜNAL -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -138,7 +138,7 @@ - ethernet = <&sw0_p5>; - phy-mode = "rgmii"; - tx-internal-delay-ps = <2000>; -- rx-internal-delay-ps = <2000>; -+ rx-internal-delay-ps = <2100>; - - fixed-link { - speed = <1000>; -@@ -213,6 +213,7 @@ - fixed-link { - speed = <1000>; - full-duplex; -+ pause; - }; - }; - diff --git a/target/linux/bcm53xx/patches-5.10/034-v5.17-0010-Revert-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-A.patch b/target/linux/bcm53xx/patches-5.10/034-v5.17-0010-Revert-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-A.patch deleted file mode 100644 index 3d814b1252..0000000000 --- a/target/linux/bcm53xx/patches-5.10/034-v5.17-0010-Revert-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-A.patch +++ /dev/null @@ -1,109 +0,0 @@ -From 8b0c59c622dc4dab970ec63264fb5b152944ac80 Mon Sep 17 00:00:00 2001 -From: Arnd Bergmann -Date: Thu, 23 Dec 2021 00:17:17 +0100 -Subject: [PATCH] Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus - RT-AC88U" - -This reverts commit 3d2d52a0d1835b56f6bd67d268f6c39df0e41692, it caused -a build regression: - -arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:109.4-14: Warning (reg_format): /switch/ports:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) -arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' -arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' -arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' -arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' -arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #address-cells value -arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #size-cells value - -Reported-by: Stephen Rothwell -Signed-off-by: Arnd Bergmann ---- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 -------------------- - 1 file changed, 77 deletions(-) - ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -93,83 +93,6 @@ - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - }; -- -- switch { -- compatible = "realtek,rtl8365mb"; -- /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ -- mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; -- mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; -- reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; -- realtek,disable-leds; -- dsa,member = <1 0>; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0>; -- -- port@0 { -- reg = <0>; -- label = "lan5"; -- phy-handle = <ðphy0>; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan6"; -- phy-handle = <ðphy1>; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan7"; -- phy-handle = <ðphy2>; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan8"; -- phy-handle = <ðphy3>; -- }; -- -- port@6 { -- reg = <6>; -- label = "cpu"; -- ethernet = <&sw0_p5>; -- phy-mode = "rgmii"; -- tx-internal-delay-ps = <2000>; -- rx-internal-delay-ps = <2100>; -- -- fixed-link { -- speed = <1000>; -- full-duplex; -- pause; -- }; -- }; -- }; -- -- mdio { -- compatible = "realtek,smi-mdio"; -- #address-cells = <1>; -- #size-cells = <0>; -- -- ethphy0: ethernet-phy@0 { -- reg = <0>; -- }; -- -- ethphy1: ethernet-phy@1 { -- reg = <1>; -- }; -- -- ethphy2: ethernet-phy@2 { -- reg = <2>; -- }; -- -- ethphy3: ethernet-phy@3 { -- reg = <3>; -- }; -- }; -- }; - }; - - &srab { diff --git a/target/linux/bcm53xx/patches-5.10/035-v5.18-0001-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch b/target/linux/bcm53xx/patches-5.10/035-v5.18-0001-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch deleted file mode 100644 index 77d3420ff8..0000000000 --- a/target/linux/bcm53xx/patches-5.10/035-v5.18-0001-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 441d531ec9b766f49e01c107a3043235daa4493f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Sun, 2 Jan 2022 23:33:04 +0300 -Subject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Define the Realtek RTL8365MB switch without interrupt support on the device -tree of Asus RT-AC88U. - -Signed-off-by: Arınç ÜNAL -Acked-by: Alvin Å ipraga -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 76 ++++++++++++++++++++ - 1 file changed, 76 insertions(+) - ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -93,6 +93,82 @@ - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - }; -+ -+ switch { -+ compatible = "realtek,rtl8365mb"; -+ /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ -+ mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; -+ mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; -+ reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; -+ realtek,disable-leds; -+ dsa,member = <1 0>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ label = "lan5"; -+ phy-handle = <ðphy0>; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan6"; -+ phy-handle = <ðphy1>; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan7"; -+ phy-handle = <ðphy2>; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan8"; -+ phy-handle = <ðphy3>; -+ }; -+ -+ port@6 { -+ reg = <6>; -+ label = "cpu"; -+ ethernet = <&sw0_p5>; -+ phy-mode = "rgmii"; -+ tx-internal-delay-ps = <2000>; -+ rx-internal-delay-ps = <2100>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ }; -+ -+ mdio { -+ compatible = "realtek,smi-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethphy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ ethphy1: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ ethphy2: ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ ethphy3: ethernet-phy@3 { -+ reg = <3>; -+ }; -+ }; -+ }; - }; - - &srab { diff --git a/target/linux/bcm53xx/patches-5.10/035-v5.18-0002-ARM-dts-NSP-MX6X-get-mac-address-from-eeprom.patch b/target/linux/bcm53xx/patches-5.10/035-v5.18-0002-ARM-dts-NSP-MX6X-get-mac-address-from-eeprom.patch deleted file mode 100644 index 19cf1fe952..0000000000 --- a/target/linux/bcm53xx/patches-5.10/035-v5.18-0002-ARM-dts-NSP-MX6X-get-mac-address-from-eeprom.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 66848aff05f669e95795b5f3a163f4762781333e Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Wed, 23 Feb 2022 23:50:39 +0000 -Subject: [PATCH] ARM: dts: NSP: MX6X: get mac-address from eeprom - -The MAC address on the MX64/MX65 series is located on the AT24 EEPROM. -This is the same as other Meraki devices such as the MR32 [1]. - -[1] https://lore.kernel.org/linux-arm-kernel/fa8271d02ef74a687f365cebe5c55ec846963ab7.1631986106.git.chunkeey@gmail.com/ - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -@@ -39,6 +39,8 @@ - - &amac2 { - status = "okay"; -+ nvmem-cells = <&mac_address>; -+ nvmem-cell-names = "mac-address"; - }; - - &ehci0 { -@@ -53,6 +55,12 @@ - reg = <0x50>; - pagesize = <32>; - read-only; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ mac_address: mac-address@66 { -+ reg = <0x66 0x6>; -+ }; - }; - }; - diff --git a/target/linux/bcm53xx/patches-5.10/035-v5.18-0003-ARM-dts-NSP-MX6X-correct-LED-function-types.patch b/target/linux/bcm53xx/patches-5.10/035-v5.18-0003-ARM-dts-NSP-MX6X-correct-LED-function-types.patch deleted file mode 100644 index 2da45ff9da..0000000000 --- a/target/linux/bcm53xx/patches-5.10/035-v5.18-0003-ARM-dts-NSP-MX6X-correct-LED-function-types.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 482c85c7fc95c572d368b2214b9e9d2c4a2e5789 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Wed, 23 Feb 2022 23:50:40 +0000 -Subject: [PATCH] ARM: dts: NSP: MX6X: correct LED function types - -Currently, the amber LED will remain always on. This is due to a -misinterpretation of the LED sub-node properties, where-by "default-state" -was used to indicate the initial state when powering on the device. When in -use, however, this resulted in the amber LED always being on. Instead change -this to only indicate a fault state. - -Assign LED_FUNCTION_POWER to the green PWM LED. - -These changes bring the MX64/65 in line with the MR32's devicetree. - -Signed-off-by: Matthew Hagan -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 3 +-- - arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi | 3 +-- - arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 2 +- - 3 files changed, 3 insertions(+), 5 deletions(-) - ---- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -@@ -57,10 +57,9 @@ - - led-4 { - /* amber:power */ -- function = LED_FUNCTION_POWER; -+ function = LED_FUNCTION_FAULT; - color = ; - gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; -- default-state = "on"; - }; - - led-5 { ---- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi -@@ -106,10 +106,9 @@ - - led-a { - /* amber:power */ -- function = LED_FUNCTION_POWER; -+ function = LED_FUNCTION_FAULT; - color = ; - gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; -- default-state = "on"; - }; - - led-b { ---- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi -@@ -22,7 +22,7 @@ - }; - - led-2 { -- function = LED_FUNCTION_INDICATOR; -+ function = LED_FUNCTION_POWER; - color = ; - pwms = <&pwm 2 50000>; - max-brightness = <255>; diff --git a/target/linux/bcm53xx/patches-5.10/035-v5.18-0004-ARM-dts-BCM5301X-Add-Ethernet-MAC-address-to-Luxul-X.patch b/target/linux/bcm53xx/patches-5.10/035-v5.18-0004-ARM-dts-BCM5301X-Add-Ethernet-MAC-address-to-Luxul-X.patch deleted file mode 100644 index c70fbc398b..0000000000 --- a/target/linux/bcm53xx/patches-5.10/035-v5.18-0004-ARM-dts-BCM5301X-Add-Ethernet-MAC-address-to-Luxul-X.patch +++ /dev/null @@ -1,42 +0,0 @@ -From c8442f0fb09ca3d842b9b23d1d0650f649fd10f8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 28 Feb 2022 10:52:07 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: Add Ethernet MAC address to Luxul - XWR-3150 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Luxul XWR-3150 stores MAC as NVRAM variable. Add NVMEM cell for it and -reference it in the Ethernet interface node. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -@@ -25,6 +25,9 @@ - nvram@1eff0000 { - compatible = "brcm,nvram"; - reg = <0x1eff0000 0x10000>; -+ -+ et0macaddr: et0macaddr { -+ }; - }; - - leds { -@@ -72,6 +75,11 @@ - }; - }; - -+&gmac0 { -+ nvmem-cells = <&et0macaddr>; -+ nvmem-cell-names = "mac-address"; -+}; -+ - &usb3 { - vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; - }; diff --git a/target/linux/bcm53xx/patches-5.10/036-v5.19-0001-ARM-dts-BCM5301X-Update-pin-controller-node-name.patch b/target/linux/bcm53xx/patches-5.10/036-v5.19-0001-ARM-dts-BCM5301X-Update-pin-controller-node-name.patch deleted file mode 100644 index 690abb9270..0000000000 --- a/target/linux/bcm53xx/patches-5.10/036-v5.19-0001-ARM-dts-BCM5301X-Update-pin-controller-node-name.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 130b5e32ba9d2d2313e39cf3f6d0729bff02b76a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 30 Mar 2022 14:05:27 +0200 -Subject: [PATCH] ARM: dts: BCM5301X: Update pin controller node name -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes: -arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: cru-bus@100: 'pin-controller@1c0' does not match any of the regexes: '^clock-controller@[a-f0-9]+$', '^phy@[a-f0-9]+$', '^pinctrl@[a-f0-9]+$', '^syscon@[a-f0-9]+$', '^thermal@[a-f0-9]+$' - From schema: Documentation/devicetree/bindings/mfd/brcm,cru.yaml -arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pin-controller@1c0: $nodename:0: 'pin-controller@1c0' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$' - From schema: Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml - -Ref: e7391b021e3f ("dt-bindings: mfd: brcm,cru: Rename pinctrl node") -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -455,7 +455,7 @@ - reg = <0x180 0x4>; - }; - -- pinctrl: pin-controller@1c0 { -+ pinctrl: pinctrl@1c0 { - compatible = "brcm,bcm4708-pinmux"; - reg = <0x1c0 0x24>; - reg-names = "cru_gpio_control"; diff --git a/target/linux/bcm53xx/patches-5.10/036-v5.19-0002-ARM-dts-BCM5301X-Fix-DTC-warning-for-NAND-node.patch b/target/linux/bcm53xx/patches-5.10/036-v5.19-0002-ARM-dts-BCM5301X-Fix-DTC-warning-for-NAND-node.patch deleted file mode 100644 index e61fef8aab..0000000000 --- a/target/linux/bcm53xx/patches-5.10/036-v5.19-0002-ARM-dts-BCM5301X-Fix-DTC-warning-for-NAND-node.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 90103611d573c5c238350f9b1d7cb682c62f5681 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Fri, 1 Apr 2022 13:19:58 +0300 -Subject: [PATCH] ARM: dts: BCM5301X: Fix DTC warning for NAND node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Remove the unnecessary #address-cells and #size-cells properties on the -nand@0 node to fix the warning below. - -Warning (avoid_unnecessary_addr_size): /nand-controller@18028000/nand@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property - -Signed-off-by: Arınç ÜNAL -Acked-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi | 2 -- - 1 file changed, 2 deletions(-) - ---- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi -+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi -@@ -10,8 +10,6 @@ - nandcs: nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; -- #address-cells = <1>; -- #size-cells = <1>; - - partitions { - compatible = "brcm,bcm947xx-cfe-partitions"; diff --git a/target/linux/bcm53xx/patches-5.10/036-v5.19-0003-ARM-dts-BCM5301X-Remove-cell-properties-from-srab-po.patch b/target/linux/bcm53xx/patches-5.10/036-v5.19-0003-ARM-dts-BCM5301X-Remove-cell-properties-from-srab-po.patch deleted file mode 100644 index 6ef8720b1d..0000000000 --- a/target/linux/bcm53xx/patches-5.10/036-v5.19-0003-ARM-dts-BCM5301X-Remove-cell-properties-from-srab-po.patch +++ /dev/null @@ -1,40 +0,0 @@ -From e5ff0a7aab3ef5dd8ec7636b936c95179aa5ddfa Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Fri, 1 Apr 2022 13:19:59 +0300 -Subject: [PATCH] ARM: dts: BCM5301X: Remove cell properties from srab ports on - Asus RT-AC88U -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Remove #address-cells and #size-cells properties from the ports node of -&srab. They are already defined on bcm5301x.dtsi, there's no need to define -them again. - -Signed-off-by: Arınç ÜNAL -Acked-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0-or-later OR MIT - /* -- * Copyright (C) 2021 Arınç ÜNAL -+ * Copyright (C) 2021-2022 Arınç ÜNAL - */ - - /dts-v1/; -@@ -177,9 +177,6 @@ - dsa,member = <0 0>; - - ports { -- #address-cells = <1>; -- #size-cells = <0>; -- - port@0 { - reg = <0>; - label = "lan4"; diff --git a/target/linux/bcm53xx/patches-5.10/036-v5.19-0004-ARM-dts-BCM5301X-Add-rgmii-to-port-5-of-Broadcom-swi.patch b/target/linux/bcm53xx/patches-5.10/036-v5.19-0004-ARM-dts-BCM5301X-Add-rgmii-to-port-5-of-Broadcom-swi.patch deleted file mode 100644 index aa192b3a11..0000000000 --- a/target/linux/bcm53xx/patches-5.10/036-v5.19-0004-ARM-dts-BCM5301X-Add-rgmii-to-port-5-of-Broadcom-swi.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 4b7a67420a34ebd8fbf0111221a8bfd8001d418d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Fri, 1 Apr 2022 13:20:00 +0300 -Subject: [PATCH] ARM: dts: BCM5301X: Add rgmii to port@5 of Broadcom switch on - Asus RT-AC88U -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Define phy-mode of the Broadcom switch's port@5 as rgmii. This doesn't seem -to matter but let's explicitly define it since phy-mode as rgmii is defined -on the other side which is port@6 of the Realtek switch. - -Signed-off-by: Arınç ÜNAL -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -205,6 +205,7 @@ - sw0_p5: port@5 { - reg = <5>; - label = "extsw"; -+ phy-mode = "rgmii"; - - fixed-link { - speed = <1000>; diff --git a/target/linux/bcm53xx/patches-5.10/036-v5.19-0005-ARM-dts-BCM5301X-Retrieve-gmac1-MAC-address-from-NVR.patch b/target/linux/bcm53xx/patches-5.10/036-v5.19-0005-ARM-dts-BCM5301X-Retrieve-gmac1-MAC-address-from-NVR.patch deleted file mode 100644 index 4c0858be0a..0000000000 --- a/target/linux/bcm53xx/patches-5.10/036-v5.19-0005-ARM-dts-BCM5301X-Retrieve-gmac1-MAC-address-from-NVR.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 7f7f8c7b9f3cbae1355fb3b0ce4ea9d6f1552521 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Fri, 1 Apr 2022 13:20:01 +0300 -Subject: [PATCH] ARM: dts: BCM5301X: Retrieve gmac1 MAC address from NVRAM on - Asus RT-AC88U -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The et1macaddr NVRAM variable contains a MAC address for gmac1 on Asus -RT-AC88U. Add NVMEM cell for it and reference it in the gmac1 node. - -Signed-off-by: Arınç ÜNAL -Acked-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -25,6 +25,9 @@ - nvram@1c080000 { - compatible = "brcm,nvram"; - reg = <0x1c080000 0x00180000>; -+ -+ et1macaddr: et1macaddr { -+ }; - }; - - leds { -@@ -239,6 +242,11 @@ - }; - }; - -+&gmac1 { -+ nvmem-cells = <&et1macaddr>; -+ nvmem-cell-names = "mac-address"; -+}; -+ - &usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; - }; diff --git a/target/linux/bcm53xx/patches-5.10/036-v5.19-0006-ARM-dts-BCM5301X-Fix-compatible-strings-for-BCM53012.patch b/target/linux/bcm53xx/patches-5.10/036-v5.19-0006-ARM-dts-BCM5301X-Fix-compatible-strings-for-BCM53012.patch deleted file mode 100644 index 59e99dae62..0000000000 --- a/target/linux/bcm53xx/patches-5.10/036-v5.19-0006-ARM-dts-BCM5301X-Fix-compatible-strings-for-BCM53012.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 69bb5c6f3f41fe6baa86a775c8a3e69dd27f85d6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Sat, 2 Apr 2022 23:46:21 +0300 -Subject: [PATCH] ARM: dts: BCM5301X: Fix compatible strings for BCM53012 and - BCM53016 SoC -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Fix compatible strings for devicetrees using the BCM53012 and BCM53016 SoC. - -Signed-off-by: Arınç ÜNAL -Acked-by: Krzysztof Kozlowski -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 +- - arch/arm/boot/dts/bcm953012er.dts | 2 +- - arch/arm/boot/dts/bcm953012hr.dts | 2 +- - arch/arm/boot/dts/bcm953012k.dts | 2 +- - 4 files changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -@@ -13,7 +13,7 @@ - #include - - / { -- compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708"; -+ compatible = "meraki,mr32", "brcm,bcm53016", "brcm,bcm4708"; - model = "Meraki MR32"; - - chosen { ---- a/arch/arm/boot/dts/bcm953012er.dts -+++ b/arch/arm/boot/dts/bcm953012er.dts -@@ -37,7 +37,7 @@ - - / { - model = "NorthStar Enterprise Router (BCM953012ER)"; -- compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708"; -+ compatible = "brcm,bcm953012er", "brcm,bcm53012", "brcm,bcm4708"; - - memory@0 { - device_type = "memory"; ---- a/arch/arm/boot/dts/bcm953012hr.dts -+++ b/arch/arm/boot/dts/bcm953012hr.dts -@@ -37,7 +37,7 @@ - - / { - model = "NorthStar HR (BCM953012HR)"; -- compatible = "brcm,bcm953012hr", "brcm,brcm53012", "brcm,bcm4708"; -+ compatible = "brcm,bcm953012hr", "brcm,bcm53012", "brcm,bcm4708"; - - aliases { - ethernet0 = &gmac0; ---- a/arch/arm/boot/dts/bcm953012k.dts -+++ b/arch/arm/boot/dts/bcm953012k.dts -@@ -36,7 +36,7 @@ - - / { - model = "NorthStar SVK (BCM953012K)"; -- compatible = "brcm,bcm953012k", "brcm,brcm53012", "brcm,bcm4708"; -+ compatible = "brcm,bcm953012k", "brcm,bcm53012", "brcm,bcm4708"; - - aliases { - serial0 = &uart0; diff --git a/target/linux/bcm53xx/patches-5.10/036-v5.19-0007-ARM-dts-BCM5301X-Disable-gmac0-and-enable-port-8-on-.patch b/target/linux/bcm53xx/patches-5.10/036-v5.19-0007-ARM-dts-BCM5301X-Disable-gmac0-and-enable-port-8-on-.patch deleted file mode 100644 index f75a53777f..0000000000 --- a/target/linux/bcm53xx/patches-5.10/036-v5.19-0007-ARM-dts-BCM5301X-Disable-gmac0-and-enable-port-8-on-.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b9cff8783439ff1803709128af3a0e04c5f5f047 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Sun, 10 Apr 2022 12:44:55 +0300 -Subject: [PATCH] ARM: dts: BCM5301X: Disable gmac0 and enable port@8 on Asus - RT-AC88U -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Disable gmac0 which is not connected to any switch MAC. Enable port@8 of -the Broadcom switch which is connected to gmac2. - -Signed-off-by: Arınç ÜNAL -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -232,7 +232,6 @@ - reg = <8>; - ethernet = <&gmac2>; - label = "cpu"; -- status = "disabled"; - - fixed-link { - speed = <1000>; -@@ -242,6 +241,10 @@ - }; - }; - -+&gmac0 { -+ status = "disabled"; -+}; -+ - &gmac1 { - nvmem-cells = <&et1macaddr>; - nvmem-cell-names = "mac-address"; diff --git a/target/linux/bcm53xx/patches-5.10/036-v5.19-0008-ARM-dts-BCM5301X-Add-DT-for-WZR-1166DHP-DHP2.patch b/target/linux/bcm53xx/patches-5.10/036-v5.19-0008-ARM-dts-BCM5301X-Add-DT-for-WZR-1166DHP-DHP2.patch deleted file mode 100644 index bce497bba7..0000000000 --- a/target/linux/bcm53xx/patches-5.10/036-v5.19-0008-ARM-dts-BCM5301X-Add-DT-for-WZR-1166DHP-DHP2.patch +++ /dev/null @@ -1,300 +0,0 @@ -From 417aea4436bb658d8c5c4dcd0e3c255931d0ee96 Mon Sep 17 00:00:00 2001 -From: SHIMAMOTO Takayoshi -Date: Fri, 22 Apr 2022 00:10:54 +0900 -Subject: [PATCH] ARM: dts: BCM5301X: Add DT for WZR-1166DHP,DHP2 - -Buffalo WZR-1166DHP/WZR-1166DHP2 wireless router with - - - BCM4708A0 - - 128MiB NAND flash - - 2T2R 11ac/a/b/g/n Wi-Fi - - 4x 10/100/1000M ethernet switch - - 1x USB 3.0 port - - WZR-1166DHP and WZR-1166DHP2 have different memory capacity. - - WZR-1166DHP - - 512 MiB DDR2 SDRAM - - WZR-1166DHP2 - - 256 MiB DDR2 SDRAM - - These hardware components are very similar to the WZR-1750DHP - except for the number of antennas. - -Signed-off-by: SHIMAMOTO Takayoshi -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/Makefile | 2 + - .../bcm4708-buffalo-wzr-1166dhp-common.dtsi | 192 ++++++++++++++++++ - .../boot/dts/bcm4708-buffalo-wzr-1166dhp.dts | 26 +++ - .../boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts | 26 +++ - 4 files changed, 246 insertions(+) - create mode 100644 arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi - create mode 100644 arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts - create mode 100644 arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -99,6 +99,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm4708-asus-rt-ac56u.dtb \ - bcm4708-asus-rt-ac68u.dtb \ - bcm4708-buffalo-wzr-1750dhp.dtb \ -+ bcm4708-buffalo-wzr-1166dhp.dtb \ -+ bcm4708-buffalo-wzr-1166dhp2.dtb \ - bcm4708-linksys-ea6300-v1.dtb \ - bcm4708-linksys-ea6500-v2.dtb \ - bcm4708-luxul-xap-1510.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi -@@ -0,0 +1,192 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Broadcom BCM470X / BCM5301X ARM platform code. -+ * DTS for Buffalo WZR-1166DHP and WZR-1166DHP2 -+ * -+ * Copyright (C) 2014 Rafał Miłecki -+ * Copyright (C) 2022 SHIMAMOTO Takayoshi -+ */ -+ -+ -+#include "bcm4708.dtsi" -+#include "bcm5301x-nand-cs0-bch8.dtsi" -+#include -+ -+/ { -+ spi { -+ compatible = "spi-gpio"; -+ num-chipselects = <1>; -+ gpio-sck = <&chipcommon 7 0>; -+ gpio-mosi = <&chipcommon 4 0>; -+ cs-gpios = <&chipcommon 6 0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hc595: gpio_spi@0 { -+ compatible = "fairchild,74hc595"; -+ reg = <0>; -+ registers-number = <1>; -+ spi-max-frequency = <100000>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ usb { -+ /* label = "bcm53xx:blue:usb"; */ -+ function = LED_FUNCTION_USB; -+ color = ; -+ gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; -+ trigger-sources = <&ohci_port1>, <&ehci_port1>, -+ <&xhci_port1>, <&ohci_port2>, -+ <&ehci_port2>; -+ linux,default-trigger = "usbport"; -+ }; -+ -+ power0 { -+ /* label = "bcm53xx:red:power"; */ -+ function = LED_FUNCTION_FAULT; -+ color = ; -+ gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ power1 { -+ /* label = "bcm53xx:white:power"; */ -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ router0 { -+ /* label = "bcm53xx:blue:router"; */ -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ router1 { -+ /* label = "bcm53xx:amber:router"; */ -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ wan { -+ /* label = "bcm53xx:blue:wan"; */ -+ function = LED_FUNCTION_WAN; -+ color = ; -+ gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ wireless0 { -+ /* label = "bcm53xx:blue:wireless"; */ -+ function = LED_FUNCTION_WLAN; -+ color = ; -+ gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ wireless1 { -+ /* label = "bcm53xx:amber:wireless"; */ -+ function = LED_FUNCTION_WLAN; -+ color = ; -+ gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ restart { -+ label = "Reset"; -+ linux,code = ; -+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; -+ }; -+ -+ aoss { -+ label = "AOSS"; -+ linux,code = ; -+ gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; -+ }; -+ -+ /* Commit mode set by switch? */ -+ mode { -+ label = "Mode"; -+ linux,code = ; -+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; -+ }; -+ -+ /* Switch: AP mode */ -+ sw_ap { -+ label = "AP"; -+ linux,code = ; -+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; -+ }; -+ -+ eject { -+ label = "USB eject"; -+ linux,code = ; -+ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&usb2 { -+ vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -+}; -+ -+&usb3 { -+ vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; -+}; -+ -+&spi_nor { -+ status = "okay"; -+}; -+ -+&usb3_phy { -+ status = "okay"; -+}; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindigs for Buffalo WZR-1166DHP -+ * -+ * Copyright (C) 2022 SHIMAMOTO Takayoshi -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" -+ -+/ { -+ compatible = "buffalo,wzr-1166dhp", "brcm,bcm4708"; -+ model = "Buffalo WZR-1166DHP"; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00000000 0x08000000>, -+ <0x88000000 0x18000000>; -+ }; -+ -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device Tree Bindigs for Buffalo WZR-1166DHP2 -+ * -+ * Copyright (C) 2022 SHIMAMOTO Takayoshi -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi" -+ -+/ { -+ compatible = "buffalo,wzr-1166dhp2", "brcm,bcm4708"; -+ model = "Buffalo WZR-1166DHP2"; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00000000 0x08000000>, -+ <0x88000000 0x08000000>; -+ }; -+ -+}; diff --git a/target/linux/bcm53xx/patches-5.10/036-v5.19-0009-Revert-ARM-dts-BCM5301X-Fix-DTC-warning-for-NAND-nod.patch b/target/linux/bcm53xx/patches-5.10/036-v5.19-0009-Revert-ARM-dts-BCM5301X-Fix-DTC-warning-for-NAND-nod.patch deleted file mode 100644 index cc7e9741a7..0000000000 --- a/target/linux/bcm53xx/patches-5.10/036-v5.19-0009-Revert-ARM-dts-BCM5301X-Fix-DTC-warning-for-NAND-nod.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 18176b9d82eebaf4408dc0440f54d57a8cbced83 Mon Sep 17 00:00:00 2001 -From: Arnd Bergmann -Date: Fri, 13 May 2022 11:11:07 +0200 -Subject: [PATCH] Revert "ARM: dts: BCM5301X: Fix DTC warning for NAND node" - -This reverts commit 90103611d573, which caused a new DTC warning - -arch/arm/boot/dts/bcm953012hr.dts:57.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@0:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) -arch/arm/boot/dts/bcm953012hr.dts:62.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@200000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) -arch/arm/boot/dts/bcm953012hr.dts:66.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@600000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) -arch/arm/boot/dts/bcm953012hr.dts:70.3-33: Warning (reg_format): /nand-controller@18028000/nand@0/partition@1000000:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) -arch/arm/boot/dts/bcm953012hr.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format' -arch/arm/boot/dts/bcm953012hr.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format' -arch/arm/boot/dts/bcm953012hr.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format' -arch/arm/boot/dts/bcm953012hr.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format' - -Signed-off-by: Arnd Bergmann ---- - arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi -+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi -@@ -10,6 +10,8 @@ - nandcs: nand@0 { - compatible = "brcm,nandcs"; - reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; - - partitions { - compatible = "brcm,bcm947xx-cfe-partitions"; diff --git a/target/linux/bcm53xx/patches-5.10/037-v6.0-0001-ARM-dts-broadcom-align-gpio-key-node-names-with-dtsc.patch b/target/linux/bcm53xx/patches-5.10/037-v6.0-0001-ARM-dts-broadcom-align-gpio-key-node-names-with-dtsc.patch deleted file mode 100644 index 33d675297e..0000000000 --- a/target/linux/bcm53xx/patches-5.10/037-v6.0-0001-ARM-dts-broadcom-align-gpio-key-node-names-with-dtsc.patch +++ /dev/null @@ -1,912 +0,0 @@ -From c5aec5611aec8fb1ca68f68e41acaefccfc93c16 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Thu, 9 Jun 2022 13:39:30 +0200 -Subject: [PATCH] ARM: dts: broadcom: align gpio-key node names with dtschema - -The node names should be generic and DT schema expects certain pattern -(e.g. with key/button/switch). - -Signed-off-by: Krzysztof Kozlowski -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts | 6 +++--- - arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts | 8 ++++---- - .../boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi | 10 +++++----- - arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 10 +++++----- - arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts | 4 ++-- - arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts | 4 ++-- - arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 2 +- - arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 2 +- - arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 6 +++--- - arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 6 +++--- - arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 6 +++--- - arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts | 4 ++-- - arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 8 ++++---- - arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 2 +- - arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 2 +- - arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 2 +- - arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts | 4 ++-- - arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 4 ++-- - arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 12 ++++++------ - arch/arm/boot/dts/bcm4709-linksys-ea9200.dts | 4 ++-- - arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 6 +++--- - arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 8 ++++---- - arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 4 ++-- - arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 8 ++++---- - arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 6 +++--- - arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 6 +++--- - arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 2 +- - arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 2 +- - arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 2 +- - arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 2 +- - arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 2 +- - arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 2 +- - arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 8 ++++---- - arch/arm/boot/dts/bcm47094-phicomm-k3.dts | 2 +- - arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts | 2 +- - arch/arm/boot/dts/bcm47189-luxul-xap-810.dts | 2 +- - arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 6 +++--- - arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 +- - arch/arm/boot/dts/bcm911360_entphn.dts | 4 ++-- - arch/arm/boot/dts/bcm947189acdbmr.dts | 4 ++-- - arch/arm/boot/dts/bcm953012er.dts | 4 ++-- - arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 2 +- - arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi | 2 +- - 43 files changed, 97 insertions(+), 97 deletions(-) - ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -@@ -70,19 +70,19 @@ - gpio-keys { - compatible = "gpio-keys"; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -@@ -54,25 +54,25 @@ - gpio-keys { - compatible = "gpio-keys"; - -- brightness { -+ button-brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi -@@ -104,33 +104,33 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - -- aoss { -+ button-aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ -- mode { -+ button-mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ -- sw_ap { -+ button-sw-ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - -- eject { -+ button-eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -@@ -100,33 +100,33 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - -- aoss { -+ button-aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ -- mode { -+ button-mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ -- sw_ap { -+ button-sw-ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - -- eject { -+ button-eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts -+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts -@@ -29,13 +29,13 @@ - gpio-keys { - compatible = "gpio-keys"; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts -+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts -@@ -25,13 +25,13 @@ - gpio-keys { - compatible = "gpio-keys"; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts -+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts -@@ -45,7 +45,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts -@@ -52,7 +52,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts -@@ -63,19 +63,19 @@ - gpio-keys { - compatible = "gpio-keys"; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts -@@ -59,19 +59,19 @@ - gpio-keys { - compatible = "gpio-keys"; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts -+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts -@@ -94,19 +94,19 @@ - gpio-keys { - compatible = "gpio-keys"; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -@@ -60,13 +60,13 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts -@@ -91,26 +91,26 @@ - gpio-keys { - compatible = "gpio-keys"; - -- aoss { -+ button-aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - /* Switch device mode? */ -- mode { -+ button-mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - -- eject { -+ button-eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -@@ -96,7 +96,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts -+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts -@@ -45,7 +45,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts -+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts -@@ -94,7 +94,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts -+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts -@@ -77,13 +77,13 @@ - gpio-keys { - compatible = "gpio-keys"; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -@@ -50,13 +50,13 @@ - #address-cells = <1>; - #size-cells = <0>; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -@@ -80,39 +80,39 @@ - #address-cells = <1>; - #size-cells = <0>; - -- power { -+ button-power { - label = "Power"; - linux,code = ; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; - }; - -- aoss { -+ button-aoss { - label = "AOSS"; - linux,code = ; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - }; - - /* Commit mode set by switch? */ -- mode { -+ button-mode { - label = "Mode"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - }; - - /* Switch: AP mode */ -- sw_ap { -+ button-sw-ap { - label = "AP"; - linux,code = ; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - -- eject { -+ button-eject { - label = "USB eject"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts -+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts -@@ -32,13 +32,13 @@ - #address-cells = <1>; - #size-cells = <0>; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -@@ -75,19 +75,19 @@ - #address-cells = <1>; - #size-cells = <0>; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -@@ -102,25 +102,25 @@ - #address-cells = <1>; - #size-cells = <0>; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - -- brightness { -+ button-brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts -+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts -@@ -80,13 +80,13 @@ - #address-cells = <1>; - #size-cells = <0>; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts -@@ -72,25 +72,25 @@ - gpio-keys { - compatible = "gpio-keys"; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - }; - -- reset { -+ button-reset { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - -- wifi { -+ button-wifi { - label = "Wi-Fi"; - linux,code = ; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - -- led { -+ button-led { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -@@ -86,20 +86,20 @@ - gpio-keys { - compatible = "gpio-keys"; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - - /* Switch: router / extender */ -- extender { -+ button-extender { - label = "Extender"; - linux,code = ; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts -@@ -30,19 +30,19 @@ - gpio-keys { - compatible = "gpio-keys"; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - }; - -- reset { -+ button-reset { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts -@@ -49,7 +49,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts -@@ -43,7 +43,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts -@@ -49,7 +49,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts -@@ -37,7 +37,7 @@ - #address-cells = <1>; - #size-cells = <0>; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts -@@ -89,7 +89,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts -@@ -67,7 +67,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts -+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts -@@ -65,25 +65,25 @@ - gpio-keys { - compatible = "gpio-keys"; - -- brightness { -+ button-brightness { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - }; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; - }; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts -+++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts -@@ -22,7 +22,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts -+++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts -@@ -39,7 +39,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts -+++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts -@@ -49,7 +49,7 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts -+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts -@@ -59,19 +59,19 @@ - gpio-keys { - compatible = "gpio-keys"; - -- rfkill { -+ button-rfkill { - label = "WiFi"; - linux,code = ; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; - }; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -@@ -50,7 +50,7 @@ - #address-cells = <1>; - #size-cells = <0>; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm911360_entphn.dts -+++ b/arch/arm/boot/dts/bcm911360_entphn.dts -@@ -47,10 +47,10 @@ - stdout-path = "serial0:115200n8"; - }; - -- gpio_keys { -+ gpio-keys { - compatible = "gpio-keys"; - -- hook { -+ button-hook { - label = "HOOK"; - linux,code = ; - gpios = <&gpio_asiu 48 0>; ---- a/arch/arm/boot/dts/bcm947189acdbmr.dts -+++ b/arch/arm/boot/dts/bcm947189acdbmr.dts -@@ -44,13 +44,13 @@ - gpio-keys { - compatible = "gpio-keys"; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; - }; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm953012er.dts -+++ b/arch/arm/boot/dts/bcm953012er.dts -@@ -47,13 +47,13 @@ - gpio-keys { - compatible = "gpio-keys"; - -- wps { -+ button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; - }; - -- restart { -+ button-restart { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi -@@ -13,7 +13,7 @@ - autorepeat; - poll-interval = <20>; - -- reset { -+ button-reset { - label = "reset"; - linux,code = ; - gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; ---- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi -+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi -@@ -14,7 +14,7 @@ - autorepeat; - poll-interval = <20>; - -- reset { -+ button-reset { - label = "reset"; - linux,code = ; - gpios = <&gpioa 6 GPIO_ACTIVE_LOW>; diff --git a/target/linux/bcm53xx/patches-5.10/037-v6.0-0002-ARM-dts-broadcom-correct-gpio-keys-properties.patch b/target/linux/bcm53xx/patches-5.10/037-v6.0-0002-ARM-dts-broadcom-correct-gpio-keys-properties.patch deleted file mode 100644 index 7bded431b0..0000000000 --- a/target/linux/bcm53xx/patches-5.10/037-v6.0-0002-ARM-dts-broadcom-correct-gpio-keys-properties.patch +++ /dev/null @@ -1,108 +0,0 @@ -From d634a6969c03803a945fdc2bccbe7d813420e569 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Thu, 9 Jun 2022 13:39:31 +0200 -Subject: [PATCH] ARM: dts: broadcom: correct gpio-keys properties - -gpio-keys children do not use unit addresses. - -Signed-off-by: Krzysztof Kozlowski -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 2 -- - arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 2 -- - arch/arm/boot/dts/bcm4709-linksys-ea9200.dts | 2 -- - arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 2 -- - arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 2 -- - arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts | 2 -- - arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 2 -- - arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 -- - 8 files changed, 16 deletions(-) - ---- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -@@ -47,8 +47,6 @@ - - gpio-keys { - compatible = "gpio-keys"; -- #address-cells = <1>; -- #size-cells = <0>; - - button-wps { - label = "WPS"; ---- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -@@ -77,8 +77,6 @@ - - gpio-keys { - compatible = "gpio-keys"; -- #address-cells = <1>; -- #size-cells = <0>; - - button-power { - label = "Power"; ---- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts -+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts -@@ -29,8 +29,6 @@ - - gpio-keys { - compatible = "gpio-keys"; -- #address-cells = <1>; -- #size-cells = <0>; - - button-wps { - label = "WPS"; ---- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -@@ -72,8 +72,6 @@ - - gpio-keys { - compatible = "gpio-keys"; -- #address-cells = <1>; -- #size-cells = <0>; - - button-wps { - label = "WPS"; ---- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts -@@ -99,8 +99,6 @@ - - gpio-keys { - compatible = "gpio-keys"; -- #address-cells = <1>; -- #size-cells = <0>; - - button-rfkill { - label = "WiFi"; ---- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts -+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts -@@ -77,8 +77,6 @@ - - gpio-keys { - compatible = "gpio-keys"; -- #address-cells = <1>; -- #size-cells = <0>; - - button-wps { - label = "WPS"; ---- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts -+++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts -@@ -34,8 +34,6 @@ - - gpio-keys { - compatible = "gpio-keys"; -- #address-cells = <1>; -- #size-cells = <0>; - - button-restart { - label = "Reset"; ---- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts -@@ -47,8 +47,6 @@ - - keys { - compatible = "gpio-keys"; -- #address-cells = <1>; -- #size-cells = <0>; - - button-restart { - label = "Reset"; diff --git a/target/linux/bcm53xx/patches-5.10/038-v6.1-0001-ARM-dts-BCM5301X-Correct-description-of-TP-Link-part.patch b/target/linux/bcm53xx/patches-5.10/038-v6.1-0001-ARM-dts-BCM5301X-Correct-description-of-TP-Link-part.patch deleted file mode 100644 index 4c4ed036b9..0000000000 --- a/target/linux/bcm53xx/patches-5.10/038-v6.1-0001-ARM-dts-BCM5301X-Correct-description-of-TP-Link-part.patch +++ /dev/null @@ -1,99 +0,0 @@ -From c8ee9f119bfb4244f76c9971c341ec06b49332cd Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 8 Nov 2022 12:07:08 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: Correct description of TP-Link partitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -TP-Link routers have flash space partitioned according to the partitions -table. It may look like fixed partitioning but those partitions can be -actually reorganized. New can be added (or some removed), offsets and -sizes may change. - -Fix DT to use binding for the TP-Link SafeLoader partitioning method. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20221108110708.13693-1-zajec5@gmail.com -Signed-off-by: Florian Fainelli ---- - .../boot/dts/bcm47081-tplink-archer-c5-v2.dts | 25 ++++--------------- - .../boot/dts/bcm4709-tplink-archer-c9-v1.dts | 25 ++++--------------- - 2 files changed, 10 insertions(+), 40 deletions(-) - ---- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts -+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts -@@ -95,30 +95,15 @@ - status = "okay"; - - partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -+ compatible = "tplink,safeloader-partitions"; -+ partitions-table-offset = <0xe50000>; - -- boot@0 { -- label = "boot"; -- reg = <0x000000 0x040000>; -- read-only; -- }; -- -- os-image@100000 { -- label = "os-image"; -- reg = <0x040000 0x200000>; -+ partition-os-image { - compatible = "brcm,trx"; - }; - -- rootfs@240000 { -- label = "rootfs"; -- reg = <0x240000 0xc00000>; -- }; -- -- nvram@ff0000 { -- label = "nvram"; -- reg = <0xff0000 0x010000>; -+ partition-file-system { -+ linux,rootfs; - }; - }; - }; ---- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts -+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts -@@ -104,30 +104,15 @@ - status = "okay"; - - partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -+ compatible = "tplink,safeloader-partitions"; -+ partitions-table-offset = <0xe50000>; - -- boot@0 { -- label = "boot"; -- reg = <0x000000 0x040000>; -- read-only; -- }; -- -- os-image@100000 { -- label = "os-image"; -- reg = <0x040000 0x200000>; -+ partition-os-image { - compatible = "brcm,trx"; - }; - -- rootfs@240000 { -- label = "rootfs"; -- reg = <0x240000 0xc00000>; -- }; -- -- nvram@ff0000 { -- label = "nvram"; -- reg = <0xff0000 0x010000>; -+ partition-file-system { -+ linux,rootfs; - }; - }; - }; diff --git a/target/linux/bcm53xx/patches-5.10/038-v6.1-0001-ARM-dts-bcm47094-Add-devicetree-for-D-Link-DIR-890L.patch b/target/linux/bcm53xx/patches-5.10/038-v6.1-0001-ARM-dts-bcm47094-Add-devicetree-for-D-Link-DIR-890L.patch deleted file mode 100644 index e921e55461..0000000000 --- a/target/linux/bcm53xx/patches-5.10/038-v6.1-0001-ARM-dts-bcm47094-Add-devicetree-for-D-Link-DIR-890L.patch +++ /dev/null @@ -1,242 +0,0 @@ -From b1ba87897ceda8e49a47aa92832dd7bff8583e21 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Mon, 7 Nov 2022 14:41:04 +0100 -Subject: [PATCH] ARM: dts: bcm47094: Add devicetree for D-Link DIR-890L - -This adds a device tree for the D-Link DIR-890L. This device -is very similar to D-Link DIR-885L, the differences are detailed -as a comment in the DTS file. - -Signed-off-by: Linus Walleij -Link: https://lore.kernel.org/r/20221107134104.1422169-2-linus.walleij@linaro.org -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts | 211 ++++++++++++++++++ - 2 files changed, 212 insertions(+) - create mode 100644 arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -122,6 +122,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm4709-tplink-archer-c9-v1.dtb \ - bcm47094-asus-rt-ac88u.dtb \ - bcm47094-dlink-dir-885l.dtb \ -+ bcm47094-dlink-dir-890l.dtb \ - bcm47094-linksys-panamera.dtb \ - bcm47094-luxul-abr-4500.dtb \ - bcm47094-luxul-xap-1610.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts -@@ -0,0 +1,211 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Device tree for D-Link DIR-890L -+ * D-Link calls this board "WRGAC36" -+ * this router has the same looks and form factor as D-Link DIR-885L. -+ * -+ * Some differences from DIR-885L include a separate USB2 port, separate LEDs -+ * for USB2 and USB3, a separate VCC supply for the USB2 slot and no -+ * router/extender switch is mounted (there is an empty mount point on the -+ * PCB) so this device is a pure router. Also the LAN ports are in the right -+ * order. -+ * -+ * Based on the device tree for DIR-885L -+ * Copyright (C) 2016 Rafał Miłecki -+ * Copyright (C) 2022 Linus Walleij -+ */ -+ -+/dts-v1/; -+ -+#include "bcm47094.dtsi" -+#include "bcm5301x-nand-cs0-bch1.dtsi" -+ -+/ { -+ compatible = "dlink,dir-890l", "brcm,bcm47094", "brcm,bcm4708"; -+ model = "D-Link DIR-890L"; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200 earlycon"; -+ }; -+ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0x00000000 0x08000000>, -+ <0x88000000 0x08000000>; -+ }; -+ -+ leds { -+ /* -+ * LED information is derived from the boot log which -+ * conveniently lists all the LEDs. -+ */ -+ compatible = "gpio-leds"; -+ -+ power-white { -+ label = "bcm53xx:white:power"; -+ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ wan-white { -+ label = "bcm53xx:white:wan"; -+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; -+ }; -+ -+ power-amber { -+ label = "bcm53xx:amber:power"; -+ gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wan-amber { -+ label = "bcm53xx:amber:wan"; -+ gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; -+ }; -+ -+ usb3-white { -+ label = "bcm53xx:white:usb3"; -+ gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; -+ trigger-sources = <&xhci_port1>; -+ linux,default-trigger = "usbport"; -+ }; -+ -+ usb2-white { -+ label = "bcm53xx:white:usb2"; -+ gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; -+ trigger-sources = <&ohci_port1>, <&ehci_port1>; -+ linux,default-trigger = "usbport"; -+ }; -+ -+ 2ghz { -+ label = "bcm53xx:white:2ghz"; -+ gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; -+ }; -+ -+ 5ghz { -+ label = "bcm53xx:white:5ghz"; -+ gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ button-wps { -+ label = "WPS"; -+ linux,code = ; -+ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; -+ }; -+ -+ /* Called "factory reset" in the vendor dmesg */ -+ button-restart { -+ label = "Reset"; -+ linux,code = ; -+ gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ /* -+ * The flash memory is memory mapped at 0x1e000000-0x1fffffff -+ * 64KB blocks; total size 2MB, same that can be -+ * found attached to the spi_nor SPI controller. -+ */ -+ nvram@1e1f0000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1e1f0000 0x00010000>; -+ -+ et0macaddr: et0macaddr { -+ }; -+ }; -+}; -+ -+&gmac2 { -+ /* -+ * The NVRAM curiously does not contain a MAC address -+ * for et2 so since that is the only ethernet interface -+ * actually in use on the platform, we use this et0 MAC -+ * address for et2. -+ */ -+ nvmem-cells = <&et0macaddr>; -+ nvmem-cell-names = "mac-address"; -+}; -+ -+&spi_nor { -+ status = "okay"; -+}; -+ -+&nandcs { -+ /* Spansion S34ML01G2, 128MB with 128KB erase blocks */ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ /* -+ * This is called "nflash" in the vendor kernel with -+ * "upgrade" and "rootfs" (probably using OpenWrt -+ * splitpart). We call it "firmware" like standard tools -+ * assume. The CFE loader contains incorrect information -+ * about TRX partitions, ignore this, there are no TRX -+ * partitions: this device uses SEAMA. -+ */ -+ firmware@0 { -+ label = "firmware"; -+ reg = <0x00000000 0x08000000>; -+ }; -+ }; -+}; -+ -+&usb2 { -+ vcc-gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; -+}; -+ -+&usb3 { -+ vcc-gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; -+}; -+ -+&usb3_phy { -+ status = "okay"; -+}; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@8 { -+ reg = <8>; -+ label = "cpu"; -+ ethernet = <&gmac2>; -+ phy-mode = "rgmii"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/038-v6.1-0001-ARM-dts-bcm53016-Add-devicetree-for-D-Link-DWL-8610A.patch b/target/linux/bcm53xx/patches-5.10/038-v6.1-0001-ARM-dts-bcm53016-Add-devicetree-for-D-Link-DWL-8610A.patch deleted file mode 100644 index c02c80065b..0000000000 --- a/target/linux/bcm53xx/patches-5.10/038-v6.1-0001-ARM-dts-bcm53016-Add-devicetree-for-D-Link-DWL-8610A.patch +++ /dev/null @@ -1,165 +0,0 @@ -From 9f66e1dd82e3186aee95282657512ca2aef1afe0 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Wed, 19 Oct 2022 21:34:49 +0200 -Subject: [PATCH] ARM: dts: bcm53016: Add devicetree for D-Link DWL-8610AP - -This adds a device tree for the BCM53016-based D-Link DWL-8610AP -access point wireless router. - -The TRX-format partitions had to be named "firmware" due to -an OpenWrt patch that only accepts parting such nodes if they -are named "firmware". - -Signed-off-by: Linus Walleij -Link: https://lore.kernel.org/r/20221019193449.3036010-2-linus.walleij@linaro.org -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/Makefile | 1 + - .../boot/dts/bcm53016-dlink-dwl-8610ap.dts | 131 ++++++++++++++++++ - 2 files changed, 132 insertions(+) - create mode 100644 arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -133,6 +133,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm47094-netgear-r8500.dtb \ - bcm47094-phicomm-k3.dtb \ - bcm53015-meraki-mr26.dtb \ -+ bcm53016-dlink-dwl-8610ap.dtb \ - bcm53016-meraki-mr32.dtb \ - bcm94708.dtb \ - bcm94709.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts -@@ -0,0 +1,131 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/dts-v1/; -+ -+#include "bcm4709.dtsi" -+#include "bcm5301x-nand-cs0-bch8.dtsi" -+#include -+#include -+ -+/ { -+ model = "D-Link DWL-8610AP"; -+ compatible = "dlink,dwl-8610ap", "brcm,bcm53016", "brcm,bcm4708"; -+ -+ memory@0 { -+ device_type = "memory"; -+ /* 512 MB RAM in 2 x Macronix D9PSH chips */ -+ reg = <0x00000000 0x08000000>, -+ <0x88000000 0x08000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ power { -+ function = LED_FUNCTION_POWER; -+ color = ; -+ gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ }; -+ -+ diag { -+ /* Actually "diag" unclear what this means */ -+ function = LED_FUNCTION_INDICATOR; -+ color = ; -+ gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ wlan-2g { -+ function = LED_FUNCTION_WLAN; -+ color = ; -+ gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wlan-5g { -+ function = LED_FUNCTION_WLAN; -+ color = ; -+ gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ gpio_keys { -+ compatible = "gpio-keys"; -+ -+ button-reset { -+ debounce-interval = <100>; -+ wakeup-source; -+ linux,code = ; -+ label = "reset"; -+ /* This GPIO is actually stored in NVRAM, but it's not gonna change */ -+ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ /* -+ * Flash memory at 0x1e000000-0x1fffffff -+ * Macronix 32 64KB blocks; total size 2MB, same that can be -+ * found attached to the spi_nor SPI controller. -+ */ -+ nvram@1e080000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1e080000 0x00020000>; -+ -+ et0macaddr: et0macaddr { -+ }; -+ -+ et1macaddr: et1macaddr { -+ }; -+ }; -+}; -+ -+&gmac0 { -+ nvmem-cells = <&et0macaddr>; -+ nvmem-cell-names = "mac-address"; -+}; -+ -+&gmac1 { -+ nvmem-cells = <&et1macaddr>; -+ nvmem-cell-names = "mac-address"; -+}; -+ -+&spi_nor { -+ /* Serial SPI NOR Flash MX 25L1606E */ -+ status = "okay"; -+}; -+ -+&nandcs { -+ /* -+ * Spansion S34ML01G100TFI00 128 MB NAND Flash memory -+ * -+ * This ECC is a bit unorthodox but it is what the stock firmware -+ * is using, so to be able to mount the original partitions -+ * this is necessary. -+ */ -+ nand-ecc-strength = <5>; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ /* This is named nflash1.trx in CFE */ -+ trx@0 { -+ label = "firmware"; -+ reg = <0x00000000 0x02800000>; -+ compatible = "brcm,trx"; -+ }; -+ -+ /* This is named nflash1.trx2 in CFE */ -+ trx2@2800000 { -+ label = "firmware2"; -+ reg = <0x02800000 0x02800000>; -+ compatible = "brcm,trx"; -+ }; -+ -+ /* This is named nflash1.rwfs in CFE */ -+ free@5000000 { -+ label = "free"; -+ reg = <0x05000000 0x03000000>; -+ }; -+ }; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/039-v6.2-bcma-support-SPROM-rev-11.patch b/target/linux/bcm53xx/patches-5.10/039-v6.2-bcma-support-SPROM-rev-11.patch deleted file mode 100644 index 5ebc78ca20..0000000000 --- a/target/linux/bcm53xx/patches-5.10/039-v6.2-bcma-support-SPROM-rev-11.patch +++ /dev/null @@ -1,28 +0,0 @@ -From b9457a04eb89645049fdf427c13e6a18d5501895 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Tue, 11 Oct 2022 14:24:40 +0200 -Subject: [PATCH] bcma: support SPROM rev 11 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Rev 11 works fine for me to set the MAC address of gmac0 and -gmac1 in the D-Link DWL-8610AP. - -Cc: Rafał Miłecki -Signed-off-by: Linus Walleij ---- - drivers/bcma/sprom.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/bcma/sprom.c -+++ b/drivers/bcma/sprom.c -@@ -170,7 +170,7 @@ static int bcma_sprom_valid(struct bcma_ - return err; - - revision = sprom[words - 1] & SSB_SPROM_REVISION_REV; -- if (revision != 8 && revision != 9 && revision != 10) { -+ if (revision < 8 || revision > 11) { - pr_err("Unsupported SPROM revision: %d\n", revision); - return -ENOENT; - } diff --git a/target/linux/bcm53xx/patches-5.10/070-v5.17-phy-bcm-ns-usb2-support-updated-DT-binding-with-PHY-.patch b/target/linux/bcm53xx/patches-5.10/070-v5.17-phy-bcm-ns-usb2-support-updated-DT-binding-with-PHY-.patch deleted file mode 100644 index 464849bc69..0000000000 --- a/target/linux/bcm53xx/patches-5.10/070-v5.17-phy-bcm-ns-usb2-support-updated-DT-binding-with-PHY-.patch +++ /dev/null @@ -1,131 +0,0 @@ -From d3bc6269e21fc474763708e79c7a118740befb94 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 26 Oct 2021 11:37:16 +0200 -Subject: [PATCH] phy: bcm-ns-usb2: support updated DT binding with PHY reg - space -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Updated DT binding maps just a PHY's register space instead of the whole -DMU block. Accessing a common CRU reg is handled using syscon & -regmap. - -The old binding has been deprecated and remains supported as a fallback -method. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20211026093716.5567-1-zajec5@gmail.com -Signed-off-by: Vinod Koul ---- - drivers/phy/broadcom/phy-bcm-ns-usb2.c | 52 +++++++++++++++++++++----- - 1 file changed, 43 insertions(+), 9 deletions(-) - ---- a/drivers/phy/broadcom/phy-bcm-ns-usb2.c -+++ b/drivers/phy/broadcom/phy-bcm-ns-usb2.c -@@ -9,17 +9,23 @@ - #include - #include - #include -+#include - #include - #include - #include - #include - #include -+#include - #include - - struct bcm_ns_usb2 { - struct device *dev; - struct clk *ref_clk; - struct phy *phy; -+ struct regmap *clkset; -+ void __iomem *base; -+ -+ /* Deprecated binding */ - void __iomem *dmu; - }; - -@@ -27,7 +33,6 @@ static int bcm_ns_usb2_phy_init(struct p - { - struct bcm_ns_usb2 *usb2 = phy_get_drvdata(phy); - struct device *dev = usb2->dev; -- void __iomem *dmu = usb2->dmu; - u32 ref_clk_rate, usb2ctl, usb_pll_ndiv, usb_pll_pdiv; - int err = 0; - -@@ -44,7 +49,10 @@ static int bcm_ns_usb2_phy_init(struct p - goto err_clk_off; - } - -- usb2ctl = readl(dmu + BCMA_DMU_CRU_USB2_CONTROL); -+ if (usb2->base) -+ usb2ctl = readl(usb2->base); -+ else -+ usb2ctl = readl(usb2->dmu + BCMA_DMU_CRU_USB2_CONTROL); - - if (usb2ctl & BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK) { - usb_pll_pdiv = usb2ctl; -@@ -58,15 +66,24 @@ static int bcm_ns_usb2_phy_init(struct p - usb_pll_ndiv = (1920000000 * usb_pll_pdiv) / ref_clk_rate; - - /* Unlock DMU PLL settings with some magic value */ -- writel(0x0000ea68, dmu + BCMA_DMU_CRU_CLKSET_KEY); -+ if (usb2->clkset) -+ regmap_write(usb2->clkset, 0, 0x0000ea68); -+ else -+ writel(0x0000ea68, usb2->dmu + BCMA_DMU_CRU_CLKSET_KEY); - - /* Write USB 2.0 PLL control setting */ - usb2ctl &= ~BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK; - usb2ctl |= usb_pll_ndiv << BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT; -- writel(usb2ctl, dmu + BCMA_DMU_CRU_USB2_CONTROL); -+ if (usb2->base) -+ writel(usb2ctl, usb2->base); -+ else -+ writel(usb2ctl, usb2->dmu + BCMA_DMU_CRU_USB2_CONTROL); - - /* Lock DMU PLL settings */ -- writel(0x00000000, dmu + BCMA_DMU_CRU_CLKSET_KEY); -+ if (usb2->clkset) -+ regmap_write(usb2->clkset, 0, 0x00000000); -+ else -+ writel(0x00000000, usb2->dmu + BCMA_DMU_CRU_CLKSET_KEY); - - err_clk_off: - clk_disable_unprepare(usb2->ref_clk); -@@ -91,11 +108,28 @@ static int bcm_ns_usb2_probe(struct plat - return -ENOMEM; - usb2->dev = dev; - -- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmu"); -- usb2->dmu = devm_ioremap_resource(dev, res); -- if (IS_ERR(usb2->dmu)) { -- dev_err(dev, "Failed to map DMU regs\n"); -- return PTR_ERR(usb2->dmu); -+ if (of_find_property(dev->of_node, "brcm,syscon-clkset", NULL)) { -+ usb2->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(usb2->base)) { -+ dev_err(dev, "Failed to map control reg\n"); -+ return PTR_ERR(usb2->base); -+ } -+ -+ usb2->clkset = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "brcm,syscon-clkset"); -+ if (IS_ERR(usb2->clkset)) { -+ dev_err(dev, "Failed to lookup clkset regmap\n"); -+ return PTR_ERR(usb2->clkset); -+ } -+ } else { -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmu"); -+ usb2->dmu = devm_ioremap_resource(dev, res); -+ if (IS_ERR(usb2->dmu)) { -+ dev_err(dev, "Failed to map DMU regs\n"); -+ return PTR_ERR(usb2->dmu); -+ } -+ -+ dev_warn(dev, "using deprecated DT binding\n"); - } - - usb2->ref_clk = devm_clk_get(dev, "phy-ref-clk"); diff --git a/target/linux/bcm53xx/patches-5.10/080-v5.13-0001-dt-bindings-nvmem-add-Broadcom-s-NVRAM.patch b/target/linux/bcm53xx/patches-5.10/080-v5.13-0001-dt-bindings-nvmem-add-Broadcom-s-NVRAM.patch deleted file mode 100644 index 01e29aaad6..0000000000 --- a/target/linux/bcm53xx/patches-5.10/080-v5.13-0001-dt-bindings-nvmem-add-Broadcom-s-NVRAM.patch +++ /dev/null @@ -1,56 +0,0 @@ -From c39edb9f9dcb6c8a0ba0ebf5df9e0ac93ab94b82 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 5 Mar 2021 19:32:35 +0100 -Subject: [PATCH] dt-bindings: nvmem: add Broadcom's NVRAM -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Broadcom's NVRAM structure contains device data and can be accessed -using I/O mapping. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Rob Herring -Signed-off-by: Srinivas Kandagatla ---- - .../devicetree/bindings/nvmem/brcm,nvram.yaml | 34 +++++++++++++++++++ - 1 file changed, 34 insertions(+) - create mode 100644 Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml -@@ -0,0 +1,34 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/nvmem/brcm,nvram.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom's NVRAM -+ -+description: | -+ Broadcom's NVRAM is a structure containing device specific environment -+ variables. It is used for storing device configuration, booting parameters -+ and calibration data. -+ -+ NVRAM can be accessed on Broadcom BCM47xx MIPS and Northstar ARM Cortex-A9 -+ devices usiong I/O mapped memory. -+ -+maintainers: -+ - Rafał Miłecki -+ -+allOf: -+ - $ref: "nvmem.yaml#" -+ -+properties: -+ compatible: -+ const: brcm,nvram -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ nvram@1eff0000 { -+ compatible = "brcm,nvram"; -+ reg = <0x1eff0000 0x10000>; -+ }; diff --git a/target/linux/bcm53xx/patches-5.10/140-mtd-parsers-trx-parse-firmware-MTD-partitions-only.patch b/target/linux/bcm53xx/patches-5.10/140-mtd-parsers-trx-parse-firmware-MTD-partitions-only.patch deleted file mode 100644 index e1933e75c7..0000000000 --- a/target/linux/bcm53xx/patches-5.10/140-mtd-parsers-trx-parse-firmware-MTD-partitions-only.patch +++ /dev/null @@ -1,43 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 13 Apr 2021 18:25:20 +0200 -Subject: [PATCH] mtd: parsers: trx: parse "firmware" MTD partitions only -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Parsing every partition with "compatible" set to "brcm,trx" results in -parsing both: firmware partition and failsafe partition on devices that -implement failsafe booting. This affects e.g. Linksys EA9500 which has: - -partition@200000 { - reg = <0x0200000 0x01d00000>; - compatible = "linksys,ns-firmware", "brcm,trx"; -}; - -partition@1f00000 { - reg = <0x01f00000 0x01d00000>; - compatible = "linksys,ns-firmware", "brcm,trx"; -}; - -Check for MTD partition name "firmware" before parsing. Recently added -ofpart_linksys_ns.c creates "firmware" and "failsafe" depending on -bootloader setup. - -Signed-off-by: Rafał Miłecki ---- - drivers/mtd/parsers/parser_trx.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/parsers/parser_trx.c -+++ b/drivers/mtd/parsers/parser_trx.c -@@ -92,6 +92,10 @@ static int parser_trx_parse(struct mtd_i - if (err != 0 && err != -EINVAL) - pr_err("failed to parse \"brcm,trx-magic\" DT attribute, using default: %d\n", err); - -+ /* Don't parse any failsafe / backup partitions */ -+ if (strcmp(mtd->name, "firmware")) -+ return -EINVAL; -+ - parts = kcalloc(TRX_PARSER_MAX_PARTS, sizeof(struct mtd_partition), - GFP_KERNEL); - if (!parts) diff --git a/target/linux/bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch b/target/linux/bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch deleted file mode 100644 index 5254b3fbbe..0000000000 --- a/target/linux/bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch +++ /dev/null @@ -1,137 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sat, 1 Oct 2016 22:54:48 +0200 -Subject: [PATCH] usb: xhci: add support for performing fake doorbell - -Broadcom's Northstar XHCI controllers seem to need a special start -procedure to work correctly. There isn't any official documentation of -this, the problem is that controller doesn't detect any connected -devices with default setup. Moreover connecting USB device to controller -that doesn't run properly can cause SoC's watchdog issues. - -A workaround that was successfully tested on multiple devices is to -perform a fake doorbell. This patch adds code for doing this and enables -it on BCM4708 family. ---- - drivers/usb/host/xhci-plat.c | 6 +++++ - drivers/usb/host/xhci.c | 63 +++++++++++++++++++++++++++++++++++++++++--- - drivers/usb/host/xhci.h | 1 + - 3 files changed, 67 insertions(+), 3 deletions(-) - ---- a/drivers/usb/host/xhci-plat.c -+++ b/drivers/usb/host/xhci-plat.c -@@ -77,6 +77,8 @@ static int xhci_priv_resume_quirk(struct - static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) - { - struct xhci_plat_priv *priv = xhci_to_priv(xhci); -+ struct platform_device*pdev = to_platform_device(dev); -+ struct device_node *node = pdev->dev.of_node; - - /* - * As of now platform drivers don't provide MSI support so we ensure -@@ -84,6 +86,9 @@ static void xhci_plat_quirks(struct devi - * dev struct in order to setup MSI - */ - xhci->quirks |= XHCI_PLAT | priv->quirks; -+ -+ if (node && of_machine_is_compatible("brcm,bcm4708")) -+ xhci->quirks |= XHCI_FAKE_DOORBELL; - } - - /* called during probe() after chip reset completes */ ---- a/drivers/usb/host/xhci.c -+++ b/drivers/usb/host/xhci.c -@@ -159,6 +159,49 @@ int xhci_start(struct xhci_hcd *xhci) - return ret; - } - -+/** -+ * xhci_fake_doorbell - Perform a fake doorbell on a specified slot -+ * -+ * Some controllers require a fake doorbell to start correctly. Without that -+ * they simply don't detect any devices. -+ */ -+static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id) -+{ -+ u32 temp; -+ -+ /* Alloc a virt device for that slot */ -+ if (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) { -+ xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); -+ return -ENOMEM; -+ } -+ -+ /* Ring fake doorbell for slot_id ep 0 */ -+ xhci_ring_ep_doorbell(xhci, slot_id, 0, 0); -+ usleep_range(1000, 1500); -+ -+ /* Read the status to check if HSE is set or not */ -+ temp = readl(&xhci->op_regs->status); -+ -+ /* Clear HSE if set */ -+ if (temp & STS_FATAL) { -+ xhci_dbg(xhci, "HSE problem detected, status: 0x%08x\n", temp); -+ temp &= ~0x1fff; -+ temp |= STS_FATAL; -+ writel(temp, &xhci->op_regs->status); -+ usleep_range(1000, 1500); -+ readl(&xhci->op_regs->status); -+ } -+ -+ /* Free virt device */ -+ xhci_free_virt_device(xhci, slot_id); -+ -+ /* We're done if controller is already running */ -+ if (readl(&xhci->op_regs->command) & CMD_RUN) -+ return 0; -+ -+ return xhci_start(xhci); -+} -+ - /* - * Reset a halted HC. - * -@@ -612,10 +655,20 @@ static int xhci_init(struct usb_hcd *hcd - - static int xhci_run_finished(struct xhci_hcd *xhci) - { -- if (xhci_start(xhci)) { -- xhci_halt(xhci); -- return -ENODEV; -+ int err; -+ -+ err = xhci_start(xhci); -+ if (err) { -+ err = -ENODEV; -+ goto err_halt; - } -+ -+ if (xhci->quirks & XHCI_FAKE_DOORBELL) { -+ err = xhci_fake_doorbell(xhci, 1); -+ if (err) -+ goto err_halt; -+ } -+ - xhci->shared_hcd->state = HC_STATE_RUNNING; - xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; - -@@ -625,6 +678,10 @@ static int xhci_run_finished(struct xhci - xhci_dbg_trace(xhci, trace_xhci_dbg_init, - "Finished xhci_run for USB3 roothub"); - return 0; -+ -+err_halt: -+ xhci_halt(xhci); -+ return err; - } - - /* ---- a/drivers/usb/host/xhci.h -+++ b/drivers/usb/host/xhci.h -@@ -1895,6 +1895,7 @@ struct xhci_hcd { - #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) - #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) - #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) -+#define XHCI_FAKE_DOORBELL BIT_ULL(45) - - unsigned int num_active_eps; - unsigned int limit_active_eps; diff --git a/target/linux/bcm53xx/patches-5.10/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch b/target/linux/bcm53xx/patches-5.10/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch deleted file mode 100644 index 034d5b52fc..0000000000 --- a/target/linux/bcm53xx/patches-5.10/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch +++ /dev/null @@ -1,101 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 24 Sep 2014 22:14:07 +0200 -Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache during decompression -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Broadcom devices have broken CFE (bootloader) that leaves hardware in an -invalid state. It causes problems with booting Linux. On Northstar -devices kernel was randomly hanging in ~25% of tries during early init. -Hangs used to happen at random places in the start_kernel. On BCM53573 -kernel doesn't even seem to start booting. - -To workaround this problem we need to do following very early: -1) Clear 2 following bits in the SCTLR register: -#define CR_M (1 << 0) /* MMU enable */ -#define CR_C (1 << 2) /* Dcache enable */ -2) Flush the whole D-cache -3) Disable L2 cache - -Unfortunately this patch is not upstreamable as it does above things -unconditionally. We can't check if we are running on Broadcom platform -in any safe way and doing such hacks with ARCH_MULTI_V7 is unacceptable -as it could break other devices support. - -Signed-off-by: Rafał Miłecki ---- - ---- a/arch/arm/boot/compressed/Makefile -+++ b/arch/arm/boot/compressed/Makefile -@@ -35,6 +35,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y) - OBJS += ll_char_wr.o font.o - endif - -+ifeq ($(CONFIG_ARCH_BCM_5301X),y) -+OBJS += head-bcm_5301x-mpcore.o -+OBJS += cache-v7-min.o -+endif -+ - ifeq ($(CONFIG_ARCH_SA1100),y) - OBJS += head-sa1100.o - endif ---- /dev/null -+++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S -@@ -0,0 +1,37 @@ -+/* -+ * -+ * Platform specific tweaks. This is merged into head.S by the linker. -+ * -+ */ -+ -+#include -+#include -+#include -+ -+ .section ".start", "ax" -+ -+/* -+ * This code section is spliced into the head code by the linker -+ */ -+ -+__plat_uncompress_start: -+ -+ @ Preserve r8/r7 i.e. kernel entry values -+ mov r12, r8 -+ -+ @ Clear MMU enable and Dcache enable bits -+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR -+ bic r0, #CR_C|CR_M -+ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR -+ nop -+ -+ @ Call the cache invalidation routine -+ bl v7_flush_dcache_all -+ nop -+ mov r0,#0 -+ ldr r3, =0x19022000 @ L2 cache controller, control reg -+ str r0, [r3, #0x100] @ Disable L2 cache -+ nop -+ -+ @ Restore -+ mov r8, r12 ---- a/arch/arm/boot/compressed/cache-v7-min.S -+++ b/arch/arm/boot/compressed/cache-v7-min.S -@@ -12,6 +12,7 @@ - - #include - #include -+#include - - __INIT - -@@ -63,7 +64,7 @@ loop2: - ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 - THUMB( lsl r6, r9, r2 ) - THUMB( orr r11, r11, r6 ) @ factor index number into r11 -- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way -+ mcr p15, 0, r11, c7, c6, 2 @ clean & invalidate by set/way - subs r9, r9, #1 @ decrement the index - bge loop2 - subs r4, r4, #1 @ decrement the way diff --git a/target/linux/bcm53xx/patches-5.10/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch b/target/linux/bcm53xx/patches-5.10/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch deleted file mode 100644 index 0fb29e99d3..0000000000 --- a/target/linux/bcm53xx/patches-5.10/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch +++ /dev/null @@ -1,711 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Subject: [PATCH] ARM: dts: BCM5301X: Specify switch ports for remaining - devices -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki ---- - ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts -@@ -93,3 +93,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts -@@ -83,3 +83,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan4"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts -@@ -149,3 +149,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts -+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts -@@ -46,3 +46,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts -+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts -@@ -42,3 +42,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts -+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts -@@ -86,3 +86,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts -@@ -77,3 +77,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan4"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts -@@ -66,6 +66,38 @@ - status = "okay"; - }; - -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ }; -+ -+ port@7 { -+ reg = <7>; -+ label = "cpu"; -+ ethernet = <&gmac1>; -+ }; -+ }; -+}; -+ - &nandcs { - partitions { - compatible = "fixed-partitions"; ---- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts -@@ -130,3 +130,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts -+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts -@@ -47,3 +47,45 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@8 { -+ reg = <8>; -+ label = "cpu"; -+ ethernet = <&gmac2>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts -@@ -104,3 +104,40 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan4"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts -+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts -@@ -94,3 +94,45 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan4"; -+ }; -+ -+ port@8 { -+ reg = <8>; -+ label = "cpu"; -+ ethernet = <&gmac2>; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts -+++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts -@@ -38,6 +38,38 @@ - status = "okay"; - }; - -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; -+ - &nandcs { - partitions { - compatible = "fixed-partitions"; ---- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts -+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts -@@ -91,6 +91,43 @@ - }; - }; - -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan4"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; -+ - &spi_nor { - status = "okay"; - ---- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts -+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts -@@ -100,6 +100,43 @@ - vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>; - }; - -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan4"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; -+ - &spi_nor { - status = "okay"; - ---- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts -@@ -107,3 +107,41 @@ - &usb3_phy { - status = "okay"; - }; -+ -+&srab { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ reg = <0>; -+ label = "lan1"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan2"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan3"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan4"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "wan"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ }; -+ }; -+}; -+ diff --git a/target/linux/bcm53xx/patches-5.10/310-ARM-BCM5301X-Add-DT-for-Netgear-R7900.patch b/target/linux/bcm53xx/patches-5.10/310-ARM-BCM5301X-Add-DT-for-Netgear-R7900.patch deleted file mode 100644 index 923b4a0f37..0000000000 --- a/target/linux/bcm53xx/patches-5.10/310-ARM-BCM5301X-Add-DT-for-Netgear-R7900.patch +++ /dev/null @@ -1,64 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Subject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7900 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki ---- - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -118,6 +118,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ - bcm4709-buffalo-wxr-1900dhp.dtb \ - bcm4709-linksys-ea9200.dtb \ - bcm4709-netgear-r7000.dtb \ -+ bcm4709-netgear-r7900.dtb \ - bcm4709-netgear-r8000.dtb \ - bcm4709-tplink-archer-c9-v1.dtb \ - bcm47094-asus-rt-ac88u.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/bcm4709-netgear-r7900.dts -@@ -0,0 +1,42 @@ -+/* -+ * Broadcom BCM470X / BCM5301X ARM platform code. -+ * DTS for Netgear R7900 -+ * -+ * Copyright (C) 2016 Rafał Miłecki -+ * -+ * Licensed under the GNU/GPL. See COPYING for details. -+ */ -+ -+/dts-v1/; -+ -+#include "bcm4709.dtsi" -+#include "bcm5301x-nand-cs0-bch8.dtsi" -+ -+/ { -+ compatible = "netgear,r7900", "brcm,bcm4709", "brcm,bcm4708"; -+ model = "Netgear R7900"; -+ -+ chosen { -+ bootargs = "console=ttyS0,115200"; -+ }; -+ -+ memory { -+ reg = <0x00000000 0x08000000 -+ 0x88000000 0x08000000>; -+ }; -+ -+ axi@18000000 { -+ usb3@23000 { -+ reg = <0x00023000 0x1000>; -+ -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; diff --git a/target/linux/bcm53xx/patches-5.10/315-ARM-dts-BCM5301X-Extend-RAM-to-full-256MB-for-Linksy.patch b/target/linux/bcm53xx/patches-5.10/315-ARM-dts-BCM5301X-Extend-RAM-to-full-256MB-for-Linksy.patch deleted file mode 100644 index 068d676962..0000000000 --- a/target/linux/bcm53xx/patches-5.10/315-ARM-dts-BCM5301X-Extend-RAM-to-full-256MB-for-Linksy.patch +++ /dev/null @@ -1,27 +0,0 @@ -From e492f69e4da879db7b3e9a2290e5b6620f1335b5 Mon Sep 17 00:00:00 2001 -From: Aleksey Nasibulin -Date: Thu, 13 Oct 2022 08:16:51 +0000 -Subject: [PATCH] ARM: dts: BCM5301X: Extend RAM to full 256MB for Linksys - EA6500 V2 - -Linksys ea6500-v2 have 256MB of ram. Currently we only use 128MB. -Expand the definition to use all the available RAM. - -Fixes: 03e96644d7a8 ("ARM: dts: BCM5301X: Add basic DT for Linksys EA6500 V2") -Signed-off-by: Aleksey Nasibulin ---- - arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts -+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts -@@ -19,7 +19,8 @@ - - memory@0 { - device_type = "memory"; -- reg = <0x00000000 0x08000000>; -+ reg = <0x00000000 0x08000000>, -+ <0x88000000 0x08000000>; - }; - - gpio-keys { diff --git a/target/linux/bcm53xx/patches-5.10/321-ARM-dts-BCM5301X-Describe-partition-formats.patch b/target/linux/bcm53xx/patches-5.10/321-ARM-dts-BCM5301X-Describe-partition-formats.patch deleted file mode 100644 index f2861177dd..0000000000 --- a/target/linux/bcm53xx/patches-5.10/321-ARM-dts-BCM5301X-Describe-partition-formats.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 7166207bd1d8c46d09d640d46afc685df9bb9083 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 22 Nov 2018 09:21:49 +0100 -Subject: [PATCH] ARM: dts: BCM5301X: Describe partition formats -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's needed by OpenWrt for custom partitioning. - -Signed-off-by: Rafał Miłecki ---- - arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts -@@ -35,6 +35,7 @@ - partition@0 { - label = "firmware"; - reg = <0x00000000 0x08000000>; -+ compatible = "seama"; - }; - }; - }; diff --git a/target/linux/bcm53xx/patches-5.10/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch b/target/linux/bcm53xx/patches-5.10/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch deleted file mode 100644 index ff9d6b0005..0000000000 --- a/target/linux/bcm53xx/patches-5.10/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 16 Oct 2014 20:52:16 +0200 -Subject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki ---- - drivers/mtd/ubi/attach.c | 5 +++++ - drivers/mtd/ubi/io.c | 4 ++++ - drivers/mtd/ubi/ubi.h | 1 + - 3 files changed, 10 insertions(+) - ---- a/drivers/mtd/ubi/attach.c -+++ b/drivers/mtd/ubi/attach.c -@@ -82,6 +82,9 @@ static int self_check_ai(struct ubi_devi - #define AV_ADD BIT(1) - #define AV_FIND_OR_ADD (AV_FIND | AV_ADD) - -+/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */ -+bool erase_all_next; -+ - /** - * find_or_add_av - internal function to find a volume, add a volume or do - * both (find and add if missing). -@@ -1580,6 +1583,8 @@ int ubi_attach(struct ubi_device *ubi, i - if (!ai) - return -ENOMEM; - -+ erase_all_next = false; -+ - #ifdef CONFIG_MTD_UBI_FASTMAP - /* On small flash devices we disable fastmap in any case. */ - if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) { ---- a/drivers/mtd/ubi/io.c -+++ b/drivers/mtd/ubi/io.c -@@ -710,6 +710,10 @@ int ubi_io_read_ec_hdr(struct ubi_device - } - - magic = be32_to_cpu(ec_hdr->magic); -+ if (magic == 0xdeadc0de) -+ erase_all_next = true; -+ if (erase_all_next) -+ return read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF; - if (magic != UBI_EC_HDR_MAGIC) { - if (mtd_is_eccerr(read_err)) - return UBI_IO_BAD_HDR_EBADMSG; ---- a/drivers/mtd/ubi/ubi.h -+++ b/drivers/mtd/ubi/ubi.h -@@ -822,6 +822,7 @@ extern struct mutex ubi_devices_mutex; - extern struct blocking_notifier_head ubi_notifiers; - - /* attach.c */ -+extern bool erase_all_next; - struct ubi_ainf_peb *ubi_alloc_aeb(struct ubi_attach_info *ai, int pnum, - int ec); - void ubi_free_aeb(struct ubi_attach_info *ai, struct ubi_ainf_peb *aeb); diff --git a/target/linux/bcm53xx/patches-5.10/600-net-disable-GRO-by-default.patch b/target/linux/bcm53xx/patches-5.10/600-net-disable-GRO-by-default.patch deleted file mode 100644 index d001852f38..0000000000 --- a/target/linux/bcm53xx/patches-5.10/600-net-disable-GRO-by-default.patch +++ /dev/null @@ -1,36 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 20 Jun 2022 10:01:18 +0200 -Subject: [PATCH] net: disable GRO by default -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -In many cases GRO improves network performance however it comes at a -cost of chacksums calculations. In case of slow CPU and missing hardware -csum calculation support GRO can actually decrease network speed. - -On BCM4708 *disabling* GRO results in following NAT masquarade speed -changes: -1. 364 Mb/s → 396 Mb/s (packet steering disabled) -2. 341 Mb/s → 566 Mb/s (packet steering enabled) - -Signed-off-by: Rafał Miłecki ---- - include/linux/netdev_features.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/include/linux/netdev_features.h -+++ b/include/linux/netdev_features.h -@@ -231,10 +231,10 @@ static inline int find_next_netdev_featu - #define NETIF_F_UPPER_DISABLES NETIF_F_LRO - - /* changeable features with no special hardware requirements */ --#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO) -+#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO) - - /* Changeable features with no special hardware requirements that defaults to off. */ --#define NETIF_F_SOFT_FEATURES_OFF NETIF_F_GRO_FRAGLIST -+#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO) - - #define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \ - NETIF_F_HW_VLAN_CTAG_RX | \ diff --git a/target/linux/bcm53xx/patches-5.10/700-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch b/target/linux/bcm53xx/patches-5.10/700-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch deleted file mode 100644 index 2c2eb07b82..0000000000 --- a/target/linux/bcm53xx/patches-5.10/700-bgmac-reduce-max-frame-size-to-support-just-MTU-1500.patch +++ /dev/null @@ -1,33 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 10 Jun 2022 13:10:47 +0200 -Subject: [PATCH] bgmac: reduce max frame size to support just MTU 1500 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -bgmac allocates new replacement buffer before handling each received -frame. Allocating & DMA-preparing 9724 B each time consumes a lot of CPU -time. Ideally bgmac should just respect currently set MTU but it isn't -the case right now. For now just revert back to the old limited frame -size. - -This change bumps NAT masquarade speed by ~95%. - -Ref: 8c7da63978f1 ("bgmac: configure MTU and add support for frames beyond 8192 byte size") -Signed-off-by: Rafał Miłecki ---- - drivers/net/ethernet/broadcom/bgmac.h | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bgmac.h -+++ b/drivers/net/ethernet/broadcom/bgmac.h -@@ -366,8 +366,7 @@ - #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */ - #define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \ - BGMAC_RX_FRAME_OFFSET) --/* Jumbo frame size with FCS */ --#define BGMAC_RX_MAX_FRAME_SIZE 9724 -+#define BGMAC_RX_MAX_FRAME_SIZE 1536 - #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE) - #define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \ - SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) diff --git a/target/linux/bcm53xx/patches-5.10/800-0001-firmware-bcm47xx_nvram-support-init-from-IO-memory.patch b/target/linux/bcm53xx/patches-5.10/800-0001-firmware-bcm47xx_nvram-support-init-from-IO-memory.patch deleted file mode 100644 index 86792d6ebf..0000000000 --- a/target/linux/bcm53xx/patches-5.10/800-0001-firmware-bcm47xx_nvram-support-init-from-IO-memory.patch +++ /dev/null @@ -1,61 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Mar 2021 08:24:44 +0100 -Subject: [PATCH] firmware: bcm47xx_nvram: support init from IO memory -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki ---- - drivers/firmware/broadcom/bcm47xx_nvram.c | 17 +++++++++++++++++ - include/linux/bcm47xx_nvram.h | 6 ++++++ - 2 files changed, 23 insertions(+) - ---- a/drivers/firmware/broadcom/bcm47xx_nvram.c -+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c -@@ -110,6 +110,23 @@ found: - return 0; - } - -+int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size) -+{ -+ if (nvram_len) { -+ pr_warn("nvram already initialized\n"); -+ return -EEXIST; -+ } -+ -+ if (!bcm47xx_nvram_is_valid(nvram_start)) { -+ pr_err("No valid NVRAM found\n"); -+ return -ENOENT; -+ } -+ -+ bcm47xx_nvram_copy(nvram_start, res_size); -+ -+ return 0; -+} -+ - /* - * On bcm47xx we need access to the NVRAM very early, so we can't use mtd - * subsystem to access flash. We can't even use platform device / driver to ---- a/include/linux/bcm47xx_nvram.h -+++ b/include/linux/bcm47xx_nvram.h -@@ -11,6 +11,7 @@ - #include - - #ifdef CONFIG_BCM47XX_NVRAM -+int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size); - int bcm47xx_nvram_init_from_mem(u32 base, u32 lim); - int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len); - int bcm47xx_nvram_gpio_pin(const char *name); -@@ -20,6 +21,11 @@ static inline void bcm47xx_nvram_release - vfree(nvram); - }; - #else -+static inline int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, -+ size_t res_size) -+{ -+ return -ENOTSUPP; -+} - static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim) - { - return -ENOTSUPP; diff --git a/target/linux/bcm53xx/patches-5.10/800-0002-nvmem-brcm_nvram-provide-NVMEM-content-to-the-NVRAM-.patch b/target/linux/bcm53xx/patches-5.10/800-0002-nvmem-brcm_nvram-provide-NVMEM-content-to-the-NVRAM-.patch deleted file mode 100644 index 6648874bcf..0000000000 --- a/target/linux/bcm53xx/patches-5.10/800-0002-nvmem-brcm_nvram-provide-NVMEM-content-to-the-NVRAM-.patch +++ /dev/null @@ -1,31 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Mar 2021 08:26:14 +0100 -Subject: [PATCH] nvmem: brcm_nvram: provide NVMEM content to the NVRAM driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki ---- - drivers/nvmem/brcm_nvram.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/nvmem/brcm_nvram.c -+++ b/drivers/nvmem/brcm_nvram.c -@@ -3,6 +3,7 @@ - * Copyright (C) 2021 Rafał Miłecki - */ - -+#include - #include - #include - #include -@@ -139,6 +140,8 @@ static int brcm_nvram_probe(struct platf - if (err) - return err; - -+ bcm47xx_nvram_init_from_iomem(priv->base, resource_size(res)); -+ - config.dev = dev; - config.cells = priv->cells; - config.ncells = priv->ncells; diff --git a/target/linux/bcm53xx/patches-5.10/905-BCM53573-minor-hacks.patch b/target/linux/bcm53xx/patches-5.10/905-BCM53573-minor-hacks.patch deleted file mode 100644 index 9aaa72595d..0000000000 --- a/target/linux/bcm53xx/patches-5.10/905-BCM53573-minor-hacks.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 6f1c62440eb6846cb8045d7a5480ec7bbe47c96f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 15 Aug 2016 10:30:41 +0200 -Subject: [PATCH] BCM53573 minor hacks -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Rafał Miłecki ---- - ---- a/arch/arm/boot/dts/bcm53573.dtsi -+++ b/arch/arm/boot/dts/bcm53573.dtsi -@@ -54,6 +54,7 @@ - , - , - ; -+ clocks = <&ilp>; - }; - - clocks { ---- a/drivers/bcma/main.c -+++ b/drivers/bcma/main.c -@@ -328,14 +328,6 @@ static int bcma_register_devices(struct - } - #endif - --#ifdef CONFIG_BCMA_SFLASH -- if (bus->drv_cc.sflash.present) { -- err = platform_device_register(&bcma_sflash_dev); -- if (err) -- bcma_err(bus, "Error registering serial flash\n"); -- } --#endif -- - #ifdef CONFIG_BCMA_NFLASH - if (bus->drv_cc.nflash.present) { - err = platform_device_register(&bcma_nflash_dev); -@@ -413,6 +405,14 @@ int bcma_bus_register(struct bcma_bus *b - bcma_register_core(bus, core); - } - -+#ifdef CONFIG_BCMA_SFLASH -+ if (bus->drv_cc.sflash.present) { -+ err = platform_device_register(&bcma_sflash_dev); -+ if (err) -+ bcma_err(bus, "Error registering serial flash\n"); -+ } -+#endif -+ - /* Try to get SPROM */ - err = bcma_sprom_get(bus); - if (err == -ENOENT) { ---- a/drivers/clocksource/arm_arch_timer.c -+++ b/drivers/clocksource/arm_arch_timer.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -934,6 +935,16 @@ static void arch_timer_of_configure_rate - if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) - arch_timer_rate = rate; - -+ /* Get clk rate through clk driver if present */ -+ if (!arch_timer_rate) { -+ struct clk *clk = of_clk_get(np, 0); -+ -+ if (!IS_ERR(clk)) { -+ if (!clk_prepare_enable(clk)) -+ arch_timer_rate = clk_get_rate(clk); -+ } -+ } -+ - /* Check the timer frequency. */ - if (validate_timer_rate()) - pr_warn("frequency not available\n"); diff --git a/target/linux/gemini/config-5.10 b/target/linux/gemini/config-5.10 deleted file mode 100644 index 19dc2692f2..0000000000 --- a/target/linux/gemini/config-5.10 +++ /dev/null @@ -1,416 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_AMBA_PL08X=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_GEMINI=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -# CONFIG_ARCH_MOXART is not set -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V4=y -# CONFIG_ARCH_MULTI_V4T is not set -CONFIG_ARCH_MULTI_V4_V5=y -# CONFIG_ARCH_MULTI_V5 is not set -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_APPENDED_DTB=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=5 -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_UNWIND=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_ATA_FORCE=y -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_PERCENTAGE=10 -# CONFIG_CMA_SIZE_SEL_MAX is not set -# CONFIG_CMA_SIZE_SEL_MBYTES is not set -# CONFIG_CMA_SIZE_SEL_MIN is not set -CONFIG_CMA_SIZE_SEL_PERCENTAGE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_GEMINI=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPU_32v4=y -CONFIG_CPU_ABRT_EV4=y -CONFIG_CPU_CACHE_FA=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_FA=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set -CONFIG_CPU_FA526=y -CONFIG_CPU_NO_EFFICIENT_FFS=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_TLB_FA=y -CONFIG_CPU_USE_DOMAINS=y -CONFIG_CRASH_CORE=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA256=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_CMA=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_KMS_CMA_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ILITEK_IL9322=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_TVE200=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_93CX6=y -CONFIG_ELF_CORE=y -# CONFIG_EMBEDDED is not set -# CONFIG_EXPERT is not set -CONFIG_EXT4_FS=y -CONFIG_FARADAY_FTINTC010=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FTTMR010_TIMER=y -CONFIG_FTWDT010_WATCHDOG=y -CONFIG_FW_LOADER_PAGED_BUF=y -# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set -CONFIG_GEMINI_ETHERNET=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_FTGPIO010=y -CONFIG_GPIO_GENERIC=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HDMI=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_KEYBOARD=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IPC_NS=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_ISDN is not set -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KERNEL_LZMA=y -# CONFIG_KERNEL_XZ is not set -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -CONFIG_KEYBOARD_DLINK_DIR685=y -# CONFIG_LDM_DEBUG is not set -CONFIG_LDM_PARTITION=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MANDATORY_FILE_LOCKING=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MODULE_UNLOAD is not set -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_GEMINI=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_WRGG_FW=y -CONFIG_NAMESPACES=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_KUSER_HELPERS=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_REALTEK_SMI=y -CONFIG_NET_DSA_TAG_RTL4_A=y -CONFIG_NET_NS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_PATA_FTIDE010=y -CONFIG_PCI=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_FTPCI100=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PID_NS=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_GEMINI=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GEMINI_POWEROFF=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_RATIONAL=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RD_LZ4=y -CONFIG_RD_LZMA=y -CONFIG_RD_LZO=y -CONFIG_RD_XZ=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RELAY=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RSEQ=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_FTRTC010=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RTC_NVMEM=y -CONFIG_SATA_GEMINI=y -CONFIG_SATA_HOST=y -CONFIG_SATA_PMP=y -CONFIG_SCSI=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SENSORS_DRIVETEMP=y -CONFIG_SENSORS_GPIO_FAN=y -CONFIG_SENSORS_LM75=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SLUB_DEBUG=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_GPIO=y -CONFIG_SPI_MASTER=y -CONFIG_SPLIT_PTLOCK_CPUS=999999 -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SWPHY=y -CONFIG_SYNC_FILE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNWINDER_ARM=y -CONFIG_USB_SUPPORT=y -CONFIG_USER_NS=y -CONFIG_USE_OF=y -CONFIG_UTS_NS=y -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -CONFIG_VITESSE_PHY=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_X86=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/gemini/patches-5.10/0001-usb-host-fotg2-add-Gemini-specific-handling.patch b/target/linux/gemini/patches-5.10/0001-usb-host-fotg2-add-Gemini-specific-handling.patch deleted file mode 100644 index 937c9824f4..0000000000 --- a/target/linux/gemini/patches-5.10/0001-usb-host-fotg2-add-Gemini-specific-handling.patch +++ /dev/null @@ -1,131 +0,0 @@ -From ff887de2f7af17d6264eb946f6b336e6e1521222 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Fri, 21 Apr 2017 22:19:00 +0200 -Subject: [PATCH 1/2] usb: host: fotg2: add Gemini-specific handling - -The Cortina Systems Gemini has bolted on a PHY inside the -silicon that can be handled by six bits in a MISC register in -the system controller. - -If we are running on Gemini, look up a syscon regmap through -a phandle and enable VBUS and optionally the Mini-B connector. - -If the device is flagged as "wakeup-source" using the standard -DT bindings, we also enable this in the global controller for -respective port. - -Signed-off-by: Linus Walleij ---- - drivers/usb/host/Kconfig | 1 + - drivers/usb/host/fotg210-hcd.c | 76 ++++++++++++++++++++++++++++++++++ - 2 files changed, 77 insertions(+) - ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -392,6 +392,7 @@ config USB_ISP1362_HCD - config USB_FOTG210_HCD - tristate "FOTG210 HCD support" - depends on USB && HAS_DMA && HAS_IOMEM -+ select MFD_SYSCON - help - Faraday FOTG210 is an OTG controller which can be configured as - an USB2.0 host. It is designed to meet USB2.0 EHCI specification ---- a/drivers/usb/host/fotg210-hcd.c -+++ b/drivers/usb/host/fotg210-hcd.c -@@ -34,6 +34,10 @@ - #include - #include - #include -+#include -+/* For Cortina Gemini */ -+#include -+#include - - #include - #include -@@ -5553,6 +5557,72 @@ static void fotg210_init(struct fotg210_ - } - - /* -+ * Gemini-specific initialization function, only executed on the -+ * Gemini SoC using the global misc control register. -+ */ -+#define GEMINI_GLOBAL_MISC_CTRL 0x30 -+#define GEMINI_MISC_USB0_WAKEUP BIT(14) -+#define GEMINI_MISC_USB1_WAKEUP BIT(15) -+#define GEMINI_MISC_USB0_VBUS_ON BIT(22) -+#define GEMINI_MISC_USB1_VBUS_ON BIT(23) -+#define GEMINI_MISC_USB0_MINI_B BIT(29) -+#define GEMINI_MISC_USB1_MINI_B BIT(30) -+ -+static int fotg210_gemini_init(struct device *dev, struct usb_hcd *hcd) -+{ -+ struct device_node *np = dev->of_node; -+ struct regmap *map; -+ bool mini_b; -+ bool wakeup; -+ u32 mask, val; -+ int ret; -+ -+ map = syscon_regmap_lookup_by_phandle(np, "syscon"); -+ if (IS_ERR(map)) { -+ dev_err(dev, "no syscon\n"); -+ return PTR_ERR(map); -+ } -+ mini_b = of_property_read_bool(np, "cortina,gemini-mini-b"); -+ wakeup = of_property_read_bool(np, "wakeup-source"); -+ -+ /* -+ * Figure out if this is USB0 or USB1 by simply checking the -+ * physical base address. -+ */ -+ mask = 0; -+ if (hcd->rsrc_start == 0x69000000) { -+ val = GEMINI_MISC_USB1_VBUS_ON; -+ if (mini_b) -+ val |= GEMINI_MISC_USB1_MINI_B; -+ else -+ mask |= GEMINI_MISC_USB1_MINI_B; -+ if (wakeup) -+ val |= GEMINI_MISC_USB1_WAKEUP; -+ else -+ mask |= GEMINI_MISC_USB1_WAKEUP; -+ } else { -+ val = GEMINI_MISC_USB0_VBUS_ON; -+ if (mini_b) -+ val |= GEMINI_MISC_USB0_MINI_B; -+ else -+ mask |= GEMINI_MISC_USB0_MINI_B; -+ if (wakeup) -+ val |= GEMINI_MISC_USB0_WAKEUP; -+ else -+ mask |= GEMINI_MISC_USB0_WAKEUP; -+ } -+ -+ ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val); -+ if (ret) { -+ dev_err(dev, "failed to initialize Gemini PHY\n"); -+ return ret; -+ } -+ -+ dev_info(dev, "initialized Gemini PHY\n"); -+ return 0; -+} -+ -+/** - * fotg210_hcd_probe - initialize faraday FOTG210 HCDs - * - * Allocates basic resources for this USB host controller, and -@@ -5629,6 +5699,12 @@ static int fotg210_hcd_probe(struct plat - - fotg210_init(fotg210); - -+ if (of_device_is_compatible(dev->of_node, "cortina,gemini-usb")) { -+ retval = fotg210_gemini_init(dev, hcd); -+ if (retval) -+ goto failed_dis_clk; -+ } -+ - retval = usb_add_hcd(hcd, irq, IRQF_SHARED); - if (retval) { - dev_err(dev, "failed to add hcd with err %d\n", retval); diff --git a/target/linux/gemini/patches-5.10/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch b/target/linux/gemini/patches-5.10/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch deleted file mode 100644 index 78a163afd8..0000000000 --- a/target/linux/gemini/patches-5.10/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 36ee838bf83c01cff7cb47c7b07be278d2950ac0 Mon Sep 17 00:00:00 2001 -From: Linus Walleij -Date: Mon, 11 Mar 2019 15:44:29 +0100 -Subject: [PATCH 2/2] ARM: dts: Augment DIR-685 partition table for OpenWrt - -Rename the firmware partition so that the firmware MTD -splitter will do its job, drop the rootfs arguments as -the MTD splitter will set this up automatically. - -Signed-off-by: Linus Walleij ---- - arch/arm/boot/dts/gemini-dlink-dir-685.dts | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts -+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts -@@ -20,7 +20,7 @@ - }; - - chosen { -- bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300"; -+ bootargs = "console=ttyS0,19200n8 consoleblank=300"; - stdout-path = "uart0:19200n8"; - }; - -@@ -317,9 +317,9 @@ - * this is called "upgrade" on the vendor system. - */ - partition@40000 { -- label = "upgrade"; -+ compatible = "wrg"; -+ label = "firmware"; - reg = <0x00040000 0x01f40000>; -- read-only; - }; - /* RGDB, Residental Gateway Database? */ - partition@1f80000 { diff --git a/target/linux/generic/backport-5.10/005-v5.17-01-Kbuild-use-Wdeclaration-after-statement.patch b/target/linux/generic/backport-5.10/005-v5.17-01-Kbuild-use-Wdeclaration-after-statement.patch deleted file mode 100644 index 6eb1dd7ced..0000000000 --- a/target/linux/generic/backport-5.10/005-v5.17-01-Kbuild-use-Wdeclaration-after-statement.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 2fd7e7f9317d3048a14026816d081b08ba98ea8e Mon Sep 17 00:00:00 2001 -From: Mark Rutland -Date: Tue, 8 Mar 2022 22:56:13 +0100 -Subject: [PATCH 1/3] Kbuild: use -Wdeclaration-after-statement - -The kernel is moving from using `-std=gnu89` to `-std=gnu11`, permitting -the use of additional C11 features such as for-loop initial declarations. - -One contentious aspect of C99 is that it permits mixed declarations and -code, and for now at least, it seems preferable to enforce that -declarations must come first. - -These warnings were already enabled in the kernel itself, but not -for KBUILD_USERCFLAGS or the compat VDSO on arch/arm64, which uses -a separate set of CFLAGS. - -This patch fixes an existing violation in modpost.c, which is not -reported because of the missing flag in KBUILD_USERCFLAGS: - -| scripts/mod/modpost.c: In function ‘match’: -| scripts/mod/modpost.c:837:3: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] -| 837 | const char *endp = p + strlen(p) - 1; -| | ^~~~~ - -Signed-off-by: Mark Rutland -[arnd: don't add a duplicate flag to the default set, update changelog] -Signed-off-by: Arnd Bergmann -Reviewed-by: Nathan Chancellor -Reviewed-by: Nick Desaulniers -Tested-by: Sedat Dilek # LLVM/Clang v13.0.0 (x86-64) -Signed-off-by: Masahiro Yamada ---- - Makefile | 3 ++- - arch/arm64/kernel/vdso32/Makefile | 1 + - scripts/mod/modpost.c | 4 +++- - 3 files changed, 6 insertions(+), 2 deletions(-) - ---- a/Makefile -+++ b/Makefile -@@ -423,7 +423,8 @@ HOSTCXX = g++ - endif - - export KBUILD_USERCFLAGS := -Wall -Wmissing-prototypes -Wstrict-prototypes \ -- -O2 -fomit-frame-pointer -std=gnu89 -+ -O2 -fomit-frame-pointer -std=gnu89 \ -+ -Wdeclaration-after-statement - export KBUILD_USERLDFLAGS := - - KBUILD_HOSTCFLAGS := $(KBUILD_USERCFLAGS) $(HOST_LFS_CFLAGS) $(HOSTCFLAGS) ---- a/arch/arm64/kernel/vdso32/Makefile -+++ b/arch/arm64/kernel/vdso32/Makefile -@@ -76,6 +76,7 @@ VDSO_CFLAGS += -Wall -Wundef -Wstrict-pr - -fno-strict-aliasing -fno-common \ - -Werror-implicit-function-declaration \ - -Wno-format-security \ -+ -Wdeclaration-after-statement \ - -std=gnu89 - VDSO_CFLAGS += -O2 - # Some useful compiler-dependent flags from top-level Makefile ---- a/scripts/mod/modpost.c -+++ b/scripts/mod/modpost.c -@@ -844,8 +844,10 @@ static int match(const char *sym, const - { - const char *p; - while (*pat) { -+ const char *endp; -+ - p = *pat++; -- const char *endp = p + strlen(p) - 1; -+ endp = p + strlen(p) - 1; - - /* "*foo*" */ - if (*p == '*' && *endp == '*') { diff --git a/target/linux/generic/backport-5.10/005-v5.17-02-Kbuild-move-to-std-gnu11.patch b/target/linux/generic/backport-5.10/005-v5.17-02-Kbuild-move-to-std-gnu11.patch deleted file mode 100644 index 89de9e8df9..0000000000 --- a/target/linux/generic/backport-5.10/005-v5.17-02-Kbuild-move-to-std-gnu11.patch +++ /dev/null @@ -1,60 +0,0 @@ -From b810c8e719ea082e47c7a8f7cf878bc84fa2455d Mon Sep 17 00:00:00 2001 -From: Arnd Bergmann -Date: Tue, 8 Mar 2022 22:56:14 +0100 -Subject: [PATCH 2/3] Kbuild: move to -std=gnu11 - -During a patch discussion, Linus brought up the option of changing -the C standard version from gnu89 to gnu99, which allows using variable -declaration inside of a for() loop. While the C99, C11 and later standards -introduce many other features, most of these are already available in -gnu89 as GNU extensions as well. - -An earlier attempt to do this when gcc-5 started defaulting to --std=gnu11 failed because at the time that caused warnings about -designated initializers with older compilers. Now that gcc-5.1 is -the minimum compiler version used for building kernels, that is no -longer a concern. Similarly, the behavior of 'inline' functions changes -between gnu89 using gnu_inline behavior and gnu11 using standard c99+ -behavior, but this was taken care of by defining 'inline' to include -__attribute__((gnu_inline)) in order to allow building with clang a -while ago. - -Nathan Chancellor reported a new -Wdeclaration-after-statement -warning that appears in a system header on arm, this still needs a -workaround. - -The differences between gnu99, gnu11, gnu1x and gnu17 are fairly -minimal and mainly impact warnings at the -Wpedantic level that the -kernel never enables. Between these, gnu11 is the newest version -that is supported by all supported compiler versions, though it is -only the default on gcc-5, while all other supported versions of -gcc or clang default to gnu1x/gnu17. - -Link: https://lore.kernel.org/lkml/CAHk-=wiyCH7xeHcmiFJ-YgXUy2Jaj7pnkdKpcovt8fYbVFW3TA@mail.gmail.com/ -Link: https://github.com/ClangBuiltLinux/linux/issues/1603 -Suggested-by: Linus Torvalds -Acked-by: Marco Elver -Acked-by: Jani Nikula -Acked-by: David Sterba -Tested-by: Sedat Dilek -Reviewed-by: Alex Shi -Reviewed-by: Nick Desaulniers -Reviewed-by: Miguel Ojeda -Signed-off-by: Arnd Bergmann -Reviewed-by: Nathan Chancellor -Signed-off-by: Masahiro Yamada ---- - Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/Makefile -+++ b/Makefile -@@ -507,7 +507,7 @@ KBUILD_CFLAGS := -Wall -Wundef -Werror - -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE \ - -Werror=implicit-function-declaration -Werror=implicit-int \ - -Werror=return-type -Wno-format-security \ -- -std=gnu89 -+ -std=gnu11 - KBUILD_CPPFLAGS := -D__KERNEL__ - KBUILD_AFLAGS_KERNEL := - KBUILD_CFLAGS_KERNEL := diff --git a/target/linux/generic/backport-5.10/005-v5.17-03-Kbuild-use-std-gnu11-for-KBUILD_USERCFLAGS.patch b/target/linux/generic/backport-5.10/005-v5.17-03-Kbuild-use-std-gnu11-for-KBUILD_USERCFLAGS.patch deleted file mode 100644 index 22c4d590b9..0000000000 --- a/target/linux/generic/backport-5.10/005-v5.17-03-Kbuild-use-std-gnu11-for-KBUILD_USERCFLAGS.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 40337d6f3d677aee7ad3052ae662d3f53dd4d5cb Mon Sep 17 00:00:00 2001 -From: Arnd Bergmann -Date: Tue, 8 Mar 2022 22:56:15 +0100 -Subject: [PATCH 3/3] Kbuild: use -std=gnu11 for KBUILD_USERCFLAGS - -As we change the C language standard for the kernel from gnu89 to -gnu11, it makes sense to also update the version for user space -compilation. - -Some users have older native compilers than what they use for -kernel builds, so I considered using gnu99 as the default version -for wider compatibility with gcc-4.6 and earlier. - -However, testing with older compilers showed that we already require -HOSTCC version 5.1 as well because a lot of host tools include -linux/compiler.h that uses __has_attribute(): - - CC tools/objtool/exec-cmd.o -In file included from tools/include/linux/compiler_types.h:36:0, - from tools/include/linux/compiler.h:5, - from exec-cmd.c:2: -tools/include/linux/compiler-gcc.h:19:5: error: "__has_attribute" is not defined [-Werror=undef] - -Signed-off-by: Arnd Bergmann -Reviewed-by: Nathan Chancellor -Reviewed-by: Nick Desaulniers -Tested-by: Sedat Dilek -Signed-off-by: Masahiro Yamada ---- - Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/Makefile -+++ b/Makefile -@@ -423,7 +423,7 @@ HOSTCXX = g++ - endif - - export KBUILD_USERCFLAGS := -Wall -Wmissing-prototypes -Wstrict-prototypes \ -- -O2 -fomit-frame-pointer -std=gnu89 \ -+ -O2 -fomit-frame-pointer -std=gnu11 \ - -Wdeclaration-after-statement - export KBUILD_USERLDFLAGS := - diff --git a/target/linux/generic/backport-5.10/010-Kbuild-don-t-hardcode-path-to-awk-in-scripts-ld-vers.patch b/target/linux/generic/backport-5.10/010-Kbuild-don-t-hardcode-path-to-awk-in-scripts-ld-vers.patch deleted file mode 100644 index 7ac4f9d240..0000000000 --- a/target/linux/generic/backport-5.10/010-Kbuild-don-t-hardcode-path-to-awk-in-scripts-ld-vers.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 13b1ecc3401653a355798eb1dee10cc1608202f4 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Mon, 18 Jan 2016 12:27:49 +0100 -Subject: [PATCH 33/34] Kbuild: don't hardcode path to awk in - scripts/ld-version.sh - -On some systems /usr/bin/awk does not exist, or is broken. Find it via -$PATH instead. - -Signed-off-by: Felix Fietkau ---- - scripts/ld-version.sh | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/scripts/ld-version.sh -+++ b/scripts/ld-version.sh -@@ -1,6 +1,7 @@ --#!/usr/bin/awk -f -+#!/bin/sh - # SPDX-License-Identifier: GPL-2.0 - # extract linker version number from stdin and turn into single number -+exec awk ' - { - gsub(".*\\)", ""); - gsub(".*version ", ""); -@@ -9,3 +10,4 @@ - print a[1]*100000000 + a[2]*1000000 + a[3]*10000; - exit - } -+' diff --git a/target/linux/generic/backport-5.10/011-kbuild-export-SUBARCH.patch b/target/linux/generic/backport-5.10/011-kbuild-export-SUBARCH.patch deleted file mode 100644 index aeb59c7e35..0000000000 --- a/target/linux/generic/backport-5.10/011-kbuild-export-SUBARCH.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 173019b66dcc9d68ad9333aa744dad1e369b5aa8 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sun, 9 Jul 2017 00:26:53 +0200 -Subject: [PATCH 34/34] kernel: add compile fix for linux 4.9 on x86 - -Signed-off-by: Felix Fietkau ---- - Makefile | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/Makefile -+++ b/Makefile -@@ -517,7 +517,7 @@ KBUILD_LDFLAGS_MODULE := - KBUILD_LDFLAGS := - CLANG_FLAGS := - --export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC -+export ARCH SRCARCH SUBARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC - export CPP AR NM STRIP OBJCOPY OBJDUMP READELF PAHOLE RESOLVE_BTFIDS LEX YACC AWK INSTALLKERNEL - export PERL PYTHON PYTHON3 CHECK CHECKFLAGS MAKE UTS_MACHINE HOSTCXX - export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ ZSTD diff --git a/target/linux/generic/backport-5.10/026-power-reset-linkstation-poweroff-add-missing-put_dev.patch b/target/linux/generic/backport-5.10/026-power-reset-linkstation-poweroff-add-missing-put_dev.patch deleted file mode 100644 index 66e75bf514..0000000000 --- a/target/linux/generic/backport-5.10/026-power-reset-linkstation-poweroff-add-missing-put_dev.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 1027a42c25cbf8cfc4ade6503c5110aae04866af Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= -Date: Fri, 16 Oct 2020 20:22:37 +0200 -Subject: [PATCH] power: reset: linkstation-poweroff: add missing put_device() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The of_mdio_find_bus() takes a reference to the underlying device -structure, we should release that reference using a put_device() call. - -Signed-off-by: Daniel González Cabanelas -Signed-off-by: Sebastian Reichel ---- - drivers/power/reset/linkstation-poweroff.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/power/reset/linkstation-poweroff.c -+++ b/drivers/power/reset/linkstation-poweroff.c -@@ -113,6 +113,7 @@ static int __init linkstation_poweroff_i - return -EPROBE_DEFER; - - phydev = phy_find_first(bus); -+ put_device(&bus->dev); - if (!phydev) - return -EPROBE_DEFER; - diff --git a/target/linux/generic/backport-5.10/050-v5.16-00-MIPS-uasm-Enable-muhu-opcode-for-MIPS-R6.patch b/target/linux/generic/backport-5.10/050-v5.16-00-MIPS-uasm-Enable-muhu-opcode-for-MIPS-R6.patch deleted file mode 100644 index 82feb7421d..0000000000 --- a/target/linux/generic/backport-5.10/050-v5.16-00-MIPS-uasm-Enable-muhu-opcode-for-MIPS-R6.patch +++ /dev/null @@ -1,65 +0,0 @@ -From: Johan Almbladh -Date: Tue, 5 Oct 2021 18:54:02 +0200 -Subject: [PATCH] MIPS: uasm: Enable muhu opcode for MIPS R6 - -Enable the 'muhu' instruction, complementing the existing 'mulu', needed -to implement a MIPS32 BPF JIT. - -Also fix a typo in the existing definition of 'dmulu'. - -Signed-off-by: Tony Ambardar - -This patch is a dependency for my 32-bit MIPS eBPF JIT. - -Signed-off-by: Johan Almbladh ---- - ---- a/arch/mips/include/asm/uasm.h -+++ b/arch/mips/include/asm/uasm.h -@@ -145,6 +145,7 @@ Ip_u1(_mtlo); - Ip_u3u1u2(_mul); - Ip_u1u2(_multu); - Ip_u3u1u2(_mulu); -+Ip_u3u1u2(_muhu); - Ip_u3u1u2(_nor); - Ip_u3u1u2(_or); - Ip_u2u1u3(_ori); ---- a/arch/mips/mm/uasm-mips.c -+++ b/arch/mips/mm/uasm-mips.c -@@ -90,7 +90,7 @@ static const struct insn insn_table[insn - RS | RT | RD}, - [insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, - [insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT}, -- [insn_dmulu] = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op), -+ [insn_dmulu] = {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op), - RS | RT | RD}, - [insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE}, - [insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE}, -@@ -150,6 +150,8 @@ static const struct insn insn_table[insn - [insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS}, - [insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op), - RS | RT | RD}, -+ [insn_muhu] = {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op), -+ RS | RT | RD}, - #ifndef CONFIG_CPU_MIPSR6 - [insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, - #else ---- a/arch/mips/mm/uasm.c -+++ b/arch/mips/mm/uasm.c -@@ -59,7 +59,7 @@ enum opcode { - insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld, - insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, - insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0, -- insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor, -+ insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor, - insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc, - insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll, - insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, -@@ -344,6 +344,7 @@ I_u1(_mtlo) - I_u3u1u2(_mul) - I_u1u2(_multu) - I_u3u1u2(_mulu) -+I_u3u1u2(_muhu) - I_u3u1u2(_nor) - I_u3u1u2(_or) - I_u2u1u3(_ori) diff --git a/target/linux/generic/backport-5.10/050-v5.16-01-mips-uasm-Add-workaround-for-Loongson-2F-nop-CPU-err.patch b/target/linux/generic/backport-5.10/050-v5.16-01-mips-uasm-Add-workaround-for-Loongson-2F-nop-CPU-err.patch deleted file mode 100644 index 3a4d573f80..0000000000 --- a/target/linux/generic/backport-5.10/050-v5.16-01-mips-uasm-Add-workaround-for-Loongson-2F-nop-CPU-err.patch +++ /dev/null @@ -1,31 +0,0 @@ -From: Johan Almbladh -Date: Tue, 5 Oct 2021 18:54:03 +0200 -Subject: [PATCH] mips: uasm: Add workaround for Loongson-2F nop CPU errata - -This patch implements a workaround for the Loongson-2F nop in generated, -code, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before, -the binutils option -mfix-loongson2f-nop was enabled, but no workaround -was done when emitting MIPS code. Now, the nop pseudo instruction is -emitted as "or ax,ax,zero" instead of the default "sll zero,zero,0". This -is consistent with the workaround implemented by binutils. - -Link: https://sourceware.org/legacy-ml/binutils/2009-11/msg00387.html - -Signed-off-by: Johan Almbladh -Reviewed-by: Jiaxun Yang ---- - ---- a/arch/mips/include/asm/uasm.h -+++ b/arch/mips/include/asm/uasm.h -@@ -249,7 +249,11 @@ static inline void uasm_l##lb(struct uas - #define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off) - #define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3) - #define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b) -+#ifdef CONFIG_CPU_NOP_WORKAROUNDS -+#define uasm_i_nop(buf) uasm_i_or(buf, 1, 1, 0) -+#else - #define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0) -+#endif - #define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1) - - static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1, diff --git a/target/linux/generic/backport-5.10/050-v5.16-02-mips-bpf-Add-eBPF-JIT-for-32-bit-MIPS.patch b/target/linux/generic/backport-5.10/050-v5.16-02-mips-bpf-Add-eBPF-JIT-for-32-bit-MIPS.patch deleted file mode 100644 index 7980659961..0000000000 --- a/target/linux/generic/backport-5.10/050-v5.16-02-mips-bpf-Add-eBPF-JIT-for-32-bit-MIPS.patch +++ /dev/null @@ -1,3078 +0,0 @@ -From: Johan Almbladh -Date: Tue, 5 Oct 2021 18:54:04 +0200 -Subject: [PATCH] mips: bpf: Add eBPF JIT for 32-bit MIPS - -This is an implementation of an eBPF JIT for 32-bit MIPS I-V and MIPS32. -The implementation supports all 32-bit and 64-bit ALU and JMP operations, -including the recently-added atomics. 64-bit div/mod and 64-bit atomics -are implemented using function calls to math64 and atomic64 functions, -respectively. All 32-bit operations are implemented natively by the JIT, -except if the CPU lacks ll/sc instructions. - -Register mapping -================ -All 64-bit eBPF registers are mapped to native 32-bit MIPS register pairs, -and does not use any stack scratch space for register swapping. This means -that all eBPF register data is kept in CPU registers all the time, and -this simplifies the register management a lot. It also reduces the JIT's -pressure on temporary registers since we do not have to move data around. - -Native register pairs are ordered according to CPU endiannes, following -the O32 calling convention for passing 64-bit arguments and return values. -The eBPF return value, arguments and callee-saved registers are mapped to -their native MIPS equivalents. - -Since the 32 highest bits in the eBPF FP (frame pointer) register are -always zero, only one general-purpose register is actually needed for the -mapping. The MIPS fp register is used for this purpose. The high bits are -mapped to MIPS register r0. This saves us one CPU register, which is much -needed for temporaries, while still allowing us to treat the R10 (FP) -register just like any other eBPF register in the JIT. - -The MIPS gp (global pointer) and at (assembler temporary) registers are -used as internal temporary registers for constant blinding. CPU registers -t6-t9 are used internally by the JIT when constructing more complex 64-bit -operations. This is precisely what is needed - two registers to store an -operand value, and two more as scratch registers when performing the -operation. - -The register mapping is shown below. - - R0 - $v1, $v0 return value - R1 - $a1, $a0 argument 1, passed in registers - R2 - $a3, $a2 argument 2, passed in registers - R3 - $t1, $t0 argument 3, passed on stack - R4 - $t3, $t2 argument 4, passed on stack - R5 - $t4, $t3 argument 5, passed on stack - R6 - $s1, $s0 callee-saved - R7 - $s3, $s2 callee-saved - R8 - $s5, $s4 callee-saved - R9 - $s7, $s6 callee-saved - FP - $r0, $fp 32-bit frame pointer - AX - $gp, $at constant-blinding - $t6 - $t9 unallocated, JIT temporaries - -Jump offsets -============ -The JIT tries to map all conditional JMP operations to MIPS conditional -PC-relative branches. The MIPS branch offset field is 18 bits, in bytes, -which is equivalent to the eBPF 16-bit instruction offset. However, since -the JIT may emit more than one CPU instruction per eBPF instruction, the -field width may overflow. If that happens, the JIT converts the long -conditional jump to a short PC-relative branch with the condition -inverted, jumping over a long unconditional absolute jmp (j). - -This conversion will change the instruction offset mapping used for jumps, -and may in turn result in more branch offset overflows. The JIT therefore -dry-runs the translation until no more branches are converted and the -offsets do not change anymore. There is an upper bound on this of course, -and if the JIT hits that limit, the last two iterations are run with all -branches being converted. - -Tail call count -=============== -The current tail call count is stored in the 16-byte area of the caller's -stack frame that is reserved for the callee in the o32 ABI. The value is -initialized in the prologue, and propagated to the tail-callee by skipping -the initialization instructions when emitting the tail call. - -Signed-off-by: Johan Almbladh ---- - create mode 100644 arch/mips/net/bpf_jit_comp.c - create mode 100644 arch/mips/net/bpf_jit_comp.h - create mode 100644 arch/mips/net/bpf_jit_comp32.c - ---- a/arch/mips/net/Makefile -+++ b/arch/mips/net/Makefile -@@ -2,4 +2,9 @@ - # MIPS networking code - - obj-$(CONFIG_MIPS_CBPF_JIT) += bpf_jit.o bpf_jit_asm.o --obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o -+ -+ifeq ($(CONFIG_32BIT),y) -+ obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp.o bpf_jit_comp32.o -+else -+ obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o -+endif ---- /dev/null -+++ b/arch/mips/net/bpf_jit_comp.c -@@ -0,0 +1,1020 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Just-In-Time compiler for eBPF bytecode on MIPS. -+ * Implementation of JIT functions common to 32-bit and 64-bit CPUs. -+ * -+ * Copyright (c) 2021 Anyfi Networks AB. -+ * Author: Johan Almbladh -+ * -+ * Based on code and ideas from -+ * Copyright (c) 2017 Cavium, Inc. -+ * Copyright (c) 2017 Shubham Bansal -+ * Copyright (c) 2011 Mircea Gherzan -+ */ -+ -+/* -+ * Code overview -+ * ============= -+ * -+ * - bpf_jit_comp.h -+ * Common definitions and utilities. -+ * -+ * - bpf_jit_comp.c -+ * Implementation of JIT top-level logic and exported JIT API functions. -+ * Implementation of internal operations shared by 32-bit and 64-bit code. -+ * JMP and ALU JIT control code, register control code, shared ALU and -+ * JMP/JMP32 JIT operations. -+ * -+ * - bpf_jit_comp32.c -+ * Implementation of functions to JIT prologue, epilogue and a single eBPF -+ * instruction for 32-bit MIPS CPUs. The functions use shared operations -+ * where possible, and implement the rest for 32-bit MIPS such as ALU64 -+ * operations. -+ * -+ * - bpf_jit_comp64.c -+ * Ditto, for 64-bit MIPS CPUs. -+ * -+ * Zero and sign extension -+ * ======================== -+ * 32-bit MIPS instructions on 64-bit MIPS registers use sign extension, -+ * but the eBPF instruction set mandates zero extension. We let the verifier -+ * insert explicit zero-extensions after 32-bit ALU operations, both for -+ * 32-bit and 64-bit MIPS JITs. Conditional JMP32 operations on 64-bit MIPs -+ * are JITed with sign extensions inserted when so expected. -+ * -+ * ALU operations -+ * ============== -+ * ALU operations on 32/64-bit MIPS and ALU64 operations on 64-bit MIPS are -+ * JITed in the following steps. ALU64 operations on 32-bit MIPS are more -+ * complicated and therefore only processed by special implementations in -+ * step (3). -+ * -+ * 1) valid_alu_i: -+ * Determine if an immediate operation can be emitted as such, or if -+ * we must fall back to the register version. -+ * -+ * 2) rewrite_alu_i: -+ * Convert BPF operation and immediate value to a canonical form for -+ * JITing. In some degenerate cases this form may be a no-op. -+ * -+ * 3) emit_alu_{i,i64,r,64}: -+ * Emit instructions for an ALU or ALU64 immediate or register operation. -+ * -+ * JMP operations -+ * ============== -+ * JMP and JMP32 operations require an JIT instruction offset table for -+ * translating the jump offset. This table is computed by dry-running the -+ * JIT without actually emitting anything. However, the computed PC-relative -+ * offset may overflow the 18-bit offset field width of the native MIPS -+ * branch instruction. In such cases, the long jump is converted into the -+ * following sequence. -+ * -+ * ! +2 Inverted PC-relative branch -+ * nop Delay slot -+ * j Unconditional absolute long jump -+ * nop Delay slot -+ * -+ * Since this converted sequence alters the offset table, all offsets must -+ * be re-calculated. This may in turn trigger new branch conversions, so -+ * the process is repeated until no further changes are made. Normally it -+ * completes in 1-2 iterations. If JIT_MAX_ITERATIONS should reached, we -+ * fall back to converting every remaining jump operation. The branch -+ * conversion is independent of how the JMP or JMP32 condition is JITed. -+ * -+ * JMP32 and JMP operations are JITed as follows. -+ * -+ * 1) setup_jmp_{i,r}: -+ * Convert jump conditional and offset into a form that can be JITed. -+ * This form may be a no-op, a canonical form, or an inverted PC-relative -+ * jump if branch conversion is necessary. -+ * -+ * 2) valid_jmp_i: -+ * Determine if an immediate operations can be emitted as such, or if -+ * we must fall back to the register version. Applies to JMP32 for 32-bit -+ * MIPS, and both JMP and JMP32 for 64-bit MIPS. -+ * -+ * 3) emit_jmp_{i,i64,r,r64}: -+ * Emit instructions for an JMP or JMP32 immediate or register operation. -+ * -+ * 4) finish_jmp_{i,r}: -+ * Emit any instructions needed to finish the jump. This includes a nop -+ * for the delay slot if a branch was emitted, and a long absolute jump -+ * if the branch was converted. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "bpf_jit_comp.h" -+ -+/* Convenience macros for descriptor access */ -+#define CONVERTED(desc) ((desc) & JIT_DESC_CONVERT) -+#define INDEX(desc) ((desc) & ~JIT_DESC_CONVERT) -+ -+/* -+ * Push registers on the stack, starting at a given depth from the stack -+ * pointer and increasing. The next depth to be written is returned. -+ */ -+int push_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth) -+{ -+ int reg; -+ -+ for (reg = 0; reg < BITS_PER_BYTE * sizeof(mask); reg++) -+ if (mask & BIT(reg)) { -+ if ((excl & BIT(reg)) == 0) { -+ if (sizeof(long) == 4) -+ emit(ctx, sw, reg, depth, MIPS_R_SP); -+ else /* sizeof(long) == 8 */ -+ emit(ctx, sd, reg, depth, MIPS_R_SP); -+ } -+ depth += sizeof(long); -+ } -+ -+ ctx->stack_used = max((int)ctx->stack_used, depth); -+ return depth; -+} -+ -+/* -+ * Pop registers from the stack, starting at a given depth from the stack -+ * pointer and increasing. The next depth to be read is returned. -+ */ -+int pop_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth) -+{ -+ int reg; -+ -+ for (reg = 0; reg < BITS_PER_BYTE * sizeof(mask); reg++) -+ if (mask & BIT(reg)) { -+ if ((excl & BIT(reg)) == 0) { -+ if (sizeof(long) == 4) -+ emit(ctx, lw, reg, depth, MIPS_R_SP); -+ else /* sizeof(long) == 8 */ -+ emit(ctx, ld, reg, depth, MIPS_R_SP); -+ } -+ depth += sizeof(long); -+ } -+ -+ return depth; -+} -+ -+/* Compute the 28-bit jump target address from a BPF program location */ -+int get_target(struct jit_context *ctx, u32 loc) -+{ -+ u32 index = INDEX(ctx->descriptors[loc]); -+ unsigned long pc = (unsigned long)&ctx->target[ctx->jit_index]; -+ unsigned long addr = (unsigned long)&ctx->target[index]; -+ -+ if (!ctx->target) -+ return 0; -+ -+ if ((addr ^ pc) & ~MIPS_JMP_MASK) -+ return -1; -+ -+ return addr & MIPS_JMP_MASK; -+} -+ -+/* Compute the PC-relative offset to relative BPF program offset */ -+int get_offset(const struct jit_context *ctx, int off) -+{ -+ return (INDEX(ctx->descriptors[ctx->bpf_index + off]) - -+ ctx->jit_index - 1) * sizeof(u32); -+} -+ -+/* dst = imm (register width) */ -+void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm) -+{ -+ if (imm >= -0x8000 && imm <= 0x7fff) { -+ emit(ctx, addiu, dst, MIPS_R_ZERO, imm); -+ } else { -+ emit(ctx, lui, dst, (s16)((u32)imm >> 16)); -+ emit(ctx, ori, dst, dst, (u16)(imm & 0xffff)); -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* dst = src (register width) */ -+void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src) -+{ -+ emit(ctx, ori, dst, src, 0); -+ clobber_reg(ctx, dst); -+} -+ -+/* Validate ALU immediate range */ -+bool valid_alu_i(u8 op, s32 imm) -+{ -+ switch (BPF_OP(op)) { -+ case BPF_NEG: -+ case BPF_LSH: -+ case BPF_RSH: -+ case BPF_ARSH: -+ /* All legal eBPF values are valid */ -+ return true; -+ case BPF_ADD: -+ /* imm must be 16 bits */ -+ return imm >= -0x8000 && imm <= 0x7fff; -+ case BPF_SUB: -+ /* -imm must be 16 bits */ -+ return imm >= -0x7fff && imm <= 0x8000; -+ case BPF_AND: -+ case BPF_OR: -+ case BPF_XOR: -+ /* imm must be 16 bits unsigned */ -+ return imm >= 0 && imm <= 0xffff; -+ case BPF_MUL: -+ /* imm must be zero or a positive power of two */ -+ return imm == 0 || (imm > 0 && is_power_of_2(imm)); -+ case BPF_DIV: -+ case BPF_MOD: -+ /* imm must be an 17-bit power of two */ -+ return (u32)imm <= 0x10000 && is_power_of_2((u32)imm); -+ } -+ return false; -+} -+ -+/* Rewrite ALU immediate operation */ -+bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val) -+{ -+ bool act = true; -+ -+ switch (BPF_OP(op)) { -+ case BPF_LSH: -+ case BPF_RSH: -+ case BPF_ARSH: -+ case BPF_ADD: -+ case BPF_SUB: -+ case BPF_OR: -+ case BPF_XOR: -+ /* imm == 0 is a no-op */ -+ act = imm != 0; -+ break; -+ case BPF_MUL: -+ if (imm == 1) { -+ /* dst * 1 is a no-op */ -+ act = false; -+ } else if (imm == 0) { -+ /* dst * 0 is dst & 0 */ -+ op = BPF_AND; -+ } else { -+ /* dst * (1 << n) is dst << n */ -+ op = BPF_LSH; -+ imm = ilog2(abs(imm)); -+ } -+ break; -+ case BPF_DIV: -+ if (imm == 1) { -+ /* dst / 1 is a no-op */ -+ act = false; -+ } else { -+ /* dst / (1 << n) is dst >> n */ -+ op = BPF_RSH; -+ imm = ilog2(imm); -+ } -+ break; -+ case BPF_MOD: -+ /* dst % (1 << n) is dst & ((1 << n) - 1) */ -+ op = BPF_AND; -+ imm--; -+ break; -+ } -+ -+ *alu = op; -+ *val = imm; -+ return act; -+} -+ -+/* ALU immediate operation (32-bit) */ -+void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op) -+{ -+ switch (BPF_OP(op)) { -+ /* dst = -dst */ -+ case BPF_NEG: -+ emit(ctx, subu, dst, MIPS_R_ZERO, dst); -+ break; -+ /* dst = dst & imm */ -+ case BPF_AND: -+ emit(ctx, andi, dst, dst, (u16)imm); -+ break; -+ /* dst = dst | imm */ -+ case BPF_OR: -+ emit(ctx, ori, dst, dst, (u16)imm); -+ break; -+ /* dst = dst ^ imm */ -+ case BPF_XOR: -+ emit(ctx, xori, dst, dst, (u16)imm); -+ break; -+ /* dst = dst << imm */ -+ case BPF_LSH: -+ emit(ctx, sll, dst, dst, imm); -+ break; -+ /* dst = dst >> imm */ -+ case BPF_RSH: -+ emit(ctx, srl, dst, dst, imm); -+ break; -+ /* dst = dst >> imm (arithmetic) */ -+ case BPF_ARSH: -+ emit(ctx, sra, dst, dst, imm); -+ break; -+ /* dst = dst + imm */ -+ case BPF_ADD: -+ emit(ctx, addiu, dst, dst, imm); -+ break; -+ /* dst = dst - imm */ -+ case BPF_SUB: -+ emit(ctx, addiu, dst, dst, -imm); -+ break; -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* ALU register operation (32-bit) */ -+void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op) -+{ -+ switch (BPF_OP(op)) { -+ /* dst = dst & src */ -+ case BPF_AND: -+ emit(ctx, and, dst, dst, src); -+ break; -+ /* dst = dst | src */ -+ case BPF_OR: -+ emit(ctx, or, dst, dst, src); -+ break; -+ /* dst = dst ^ src */ -+ case BPF_XOR: -+ emit(ctx, xor, dst, dst, src); -+ break; -+ /* dst = dst << src */ -+ case BPF_LSH: -+ emit(ctx, sllv, dst, dst, src); -+ break; -+ /* dst = dst >> src */ -+ case BPF_RSH: -+ emit(ctx, srlv, dst, dst, src); -+ break; -+ /* dst = dst >> src (arithmetic) */ -+ case BPF_ARSH: -+ emit(ctx, srav, dst, dst, src); -+ break; -+ /* dst = dst + src */ -+ case BPF_ADD: -+ emit(ctx, addu, dst, dst, src); -+ break; -+ /* dst = dst - src */ -+ case BPF_SUB: -+ emit(ctx, subu, dst, dst, src); -+ break; -+ /* dst = dst * src */ -+ case BPF_MUL: -+ if (cpu_has_mips32r1 || cpu_has_mips32r6) { -+ emit(ctx, mul, dst, dst, src); -+ } else { -+ emit(ctx, multu, dst, src); -+ emit(ctx, mflo, dst); -+ } -+ break; -+ /* dst = dst / src */ -+ case BPF_DIV: -+ if (cpu_has_mips32r6) { -+ emit(ctx, divu_r6, dst, dst, src); -+ } else { -+ emit(ctx, divu, dst, src); -+ emit(ctx, mflo, dst); -+ } -+ break; -+ /* dst = dst % src */ -+ case BPF_MOD: -+ if (cpu_has_mips32r6) { -+ emit(ctx, modu, dst, dst, src); -+ } else { -+ emit(ctx, divu, dst, src); -+ emit(ctx, mfhi, dst); -+ } -+ break; -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* Atomic read-modify-write (32-bit) */ -+void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code) -+{ -+ emit(ctx, ll, MIPS_R_T9, off, dst); -+ switch (code) { -+ case BPF_ADD: -+ emit(ctx, addu, MIPS_R_T8, MIPS_R_T9, src); -+ break; -+ case BPF_AND: -+ emit(ctx, and, MIPS_R_T8, MIPS_R_T9, src); -+ break; -+ case BPF_OR: -+ emit(ctx, or, MIPS_R_T8, MIPS_R_T9, src); -+ break; -+ case BPF_XOR: -+ emit(ctx, xor, MIPS_R_T8, MIPS_R_T9, src); -+ break; -+ } -+ emit(ctx, sc, MIPS_R_T8, off, dst); -+ emit(ctx, beqz, MIPS_R_T8, -16); -+ emit(ctx, nop); /* Delay slot */ -+} -+ -+/* Atomic compare-and-exchange (32-bit) */ -+void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off) -+{ -+ emit(ctx, ll, MIPS_R_T9, off, dst); -+ emit(ctx, bne, MIPS_R_T9, res, 12); -+ emit(ctx, move, MIPS_R_T8, src); /* Delay slot */ -+ emit(ctx, sc, MIPS_R_T8, off, dst); -+ emit(ctx, beqz, MIPS_R_T8, -20); -+ emit(ctx, move, res, MIPS_R_T9); /* Delay slot */ -+ clobber_reg(ctx, res); -+} -+ -+/* Swap bytes and truncate a register word or half word */ -+void emit_bswap_r(struct jit_context *ctx, u8 dst, u32 width) -+{ -+ u8 tmp = MIPS_R_T8; -+ u8 msk = MIPS_R_T9; -+ -+ switch (width) { -+ /* Swap bytes in a word */ -+ case 32: -+ if (cpu_has_mips32r2 || cpu_has_mips32r6) { -+ emit(ctx, wsbh, dst, dst); -+ emit(ctx, rotr, dst, dst, 16); -+ } else { -+ emit(ctx, sll, tmp, dst, 16); /* tmp = dst << 16 */ -+ emit(ctx, srl, dst, dst, 16); /* dst = dst >> 16 */ -+ emit(ctx, or, dst, dst, tmp); /* dst = dst | tmp */ -+ -+ emit(ctx, lui, msk, 0xff); /* msk = 0x00ff0000 */ -+ emit(ctx, ori, msk, msk, 0xff); /* msk = msk | 0xff */ -+ -+ emit(ctx, and, tmp, dst, msk); /* tmp = dst & msk */ -+ emit(ctx, sll, tmp, tmp, 8); /* tmp = tmp << 8 */ -+ emit(ctx, srl, dst, dst, 8); /* dst = dst >> 8 */ -+ emit(ctx, and, dst, dst, msk); /* dst = dst & msk */ -+ emit(ctx, or, dst, dst, tmp); /* reg = dst | tmp */ -+ } -+ break; -+ /* Swap bytes in a half word */ -+ case 16: -+ if (cpu_has_mips32r2 || cpu_has_mips32r6) { -+ emit(ctx, wsbh, dst, dst); -+ emit(ctx, andi, dst, dst, 0xffff); -+ } else { -+ emit(ctx, andi, tmp, dst, 0xff00); /* t = d & 0xff00 */ -+ emit(ctx, srl, tmp, tmp, 8); /* t = t >> 8 */ -+ emit(ctx, andi, dst, dst, 0x00ff); /* d = d & 0x00ff */ -+ emit(ctx, sll, dst, dst, 8); /* d = d << 8 */ -+ emit(ctx, or, dst, dst, tmp); /* d = d | t */ -+ } -+ break; -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* Validate jump immediate range */ -+bool valid_jmp_i(u8 op, s32 imm) -+{ -+ switch (op) { -+ case JIT_JNOP: -+ /* Immediate value not used */ -+ return true; -+ case BPF_JEQ: -+ case BPF_JNE: -+ /* No immediate operation */ -+ return false; -+ case BPF_JSET: -+ case JIT_JNSET: -+ /* imm must be 16 bits unsigned */ -+ return imm >= 0 && imm <= 0xffff; -+ case BPF_JGE: -+ case BPF_JLT: -+ case BPF_JSGE: -+ case BPF_JSLT: -+ /* imm must be 16 bits */ -+ return imm >= -0x8000 && imm <= 0x7fff; -+ case BPF_JGT: -+ case BPF_JLE: -+ case BPF_JSGT: -+ case BPF_JSLE: -+ /* imm + 1 must be 16 bits */ -+ return imm >= -0x8001 && imm <= 0x7ffe; -+ } -+ return false; -+} -+ -+/* Invert a conditional jump operation */ -+static u8 invert_jmp(u8 op) -+{ -+ switch (op) { -+ case BPF_JA: return JIT_JNOP; -+ case BPF_JEQ: return BPF_JNE; -+ case BPF_JNE: return BPF_JEQ; -+ case BPF_JSET: return JIT_JNSET; -+ case BPF_JGT: return BPF_JLE; -+ case BPF_JGE: return BPF_JLT; -+ case BPF_JLT: return BPF_JGE; -+ case BPF_JLE: return BPF_JGT; -+ case BPF_JSGT: return BPF_JSLE; -+ case BPF_JSGE: return BPF_JSLT; -+ case BPF_JSLT: return BPF_JSGE; -+ case BPF_JSLE: return BPF_JSGT; -+ } -+ return 0; -+} -+ -+/* Prepare a PC-relative jump operation */ -+static void setup_jmp(struct jit_context *ctx, u8 bpf_op, -+ s16 bpf_off, u8 *jit_op, s32 *jit_off) -+{ -+ u32 *descp = &ctx->descriptors[ctx->bpf_index]; -+ int op = bpf_op; -+ int offset = 0; -+ -+ /* Do not compute offsets on the first pass */ -+ if (INDEX(*descp) == 0) -+ goto done; -+ -+ /* Skip jumps never taken */ -+ if (bpf_op == JIT_JNOP) -+ goto done; -+ -+ /* Convert jumps always taken */ -+ if (bpf_op == BPF_JA) -+ *descp |= JIT_DESC_CONVERT; -+ -+ /* -+ * Current ctx->jit_index points to the start of the branch preamble. -+ * Since the preamble differs among different branch conditionals, -+ * the current index cannot be used to compute the branch offset. -+ * Instead, we use the offset table value for the next instruction, -+ * which gives the index immediately after the branch delay slot. -+ */ -+ if (!CONVERTED(*descp)) { -+ int target = ctx->bpf_index + bpf_off + 1; -+ int origin = ctx->bpf_index + 1; -+ -+ offset = (INDEX(ctx->descriptors[target]) - -+ INDEX(ctx->descriptors[origin]) + 1) * sizeof(u32); -+ } -+ -+ /* -+ * The PC-relative branch offset field on MIPS is 18 bits signed, -+ * so if the computed offset is larger than this we generate a an -+ * absolute jump that we skip with an inverted conditional branch. -+ */ -+ if (CONVERTED(*descp) || offset < -0x20000 || offset > 0x1ffff) { -+ offset = 3 * sizeof(u32); -+ op = invert_jmp(bpf_op); -+ ctx->changes += !CONVERTED(*descp); -+ *descp |= JIT_DESC_CONVERT; -+ } -+ -+done: -+ *jit_off = offset; -+ *jit_op = op; -+} -+ -+/* Prepare a PC-relative jump operation with immediate conditional */ -+void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width, -+ u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off) -+{ -+ bool always = false; -+ bool never = false; -+ -+ switch (bpf_op) { -+ case BPF_JEQ: -+ case BPF_JNE: -+ break; -+ case BPF_JSET: -+ case BPF_JLT: -+ never = imm == 0; -+ break; -+ case BPF_JGE: -+ always = imm == 0; -+ break; -+ case BPF_JGT: -+ never = (u32)imm == U32_MAX; -+ break; -+ case BPF_JLE: -+ always = (u32)imm == U32_MAX; -+ break; -+ case BPF_JSGT: -+ never = imm == S32_MAX && width == 32; -+ break; -+ case BPF_JSGE: -+ always = imm == S32_MIN && width == 32; -+ break; -+ case BPF_JSLT: -+ never = imm == S32_MIN && width == 32; -+ break; -+ case BPF_JSLE: -+ always = imm == S32_MAX && width == 32; -+ break; -+ } -+ -+ if (never) -+ bpf_op = JIT_JNOP; -+ if (always) -+ bpf_op = BPF_JA; -+ setup_jmp(ctx, bpf_op, bpf_off, jit_op, jit_off); -+} -+ -+/* Prepare a PC-relative jump operation with register conditional */ -+void setup_jmp_r(struct jit_context *ctx, bool same_reg, -+ u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off) -+{ -+ switch (bpf_op) { -+ case BPF_JSET: -+ break; -+ case BPF_JEQ: -+ case BPF_JGE: -+ case BPF_JLE: -+ case BPF_JSGE: -+ case BPF_JSLE: -+ if (same_reg) -+ bpf_op = BPF_JA; -+ break; -+ case BPF_JNE: -+ case BPF_JLT: -+ case BPF_JGT: -+ case BPF_JSGT: -+ case BPF_JSLT: -+ if (same_reg) -+ bpf_op = JIT_JNOP; -+ break; -+ } -+ setup_jmp(ctx, bpf_op, bpf_off, jit_op, jit_off); -+} -+ -+/* Finish a PC-relative jump operation */ -+int finish_jmp(struct jit_context *ctx, u8 jit_op, s16 bpf_off) -+{ -+ /* Emit conditional branch delay slot */ -+ if (jit_op != JIT_JNOP) -+ emit(ctx, nop); -+ /* -+ * Emit an absolute long jump with delay slot, -+ * if the PC-relative branch was converted. -+ */ -+ if (CONVERTED(ctx->descriptors[ctx->bpf_index])) { -+ int target = get_target(ctx, ctx->bpf_index + bpf_off + 1); -+ -+ if (target < 0) -+ return -1; -+ emit(ctx, j, target); -+ emit(ctx, nop); -+ } -+ return 0; -+} -+ -+/* Jump immediate (32-bit) */ -+void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op) -+{ -+ switch (op) { -+ /* No-op, used internally for branch optimization */ -+ case JIT_JNOP: -+ break; -+ /* PC += off if dst & imm */ -+ case BPF_JSET: -+ emit(ctx, andi, MIPS_R_T9, dst, (u16)imm); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ /* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */ -+ case JIT_JNSET: -+ emit(ctx, andi, MIPS_R_T9, dst, (u16)imm); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst > imm */ -+ case BPF_JGT: -+ emit(ctx, sltiu, MIPS_R_T9, dst, imm + 1); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst >= imm */ -+ case BPF_JGE: -+ emit(ctx, sltiu, MIPS_R_T9, dst, imm); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst < imm */ -+ case BPF_JLT: -+ emit(ctx, sltiu, MIPS_R_T9, dst, imm); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst <= imm */ -+ case BPF_JLE: -+ emit(ctx, sltiu, MIPS_R_T9, dst, imm + 1); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst > imm (signed) */ -+ case BPF_JSGT: -+ emit(ctx, slti, MIPS_R_T9, dst, imm + 1); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst >= imm (signed) */ -+ case BPF_JSGE: -+ emit(ctx, slti, MIPS_R_T9, dst, imm); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst < imm (signed) */ -+ case BPF_JSLT: -+ emit(ctx, slti, MIPS_R_T9, dst, imm); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst <= imm (signed) */ -+ case BPF_JSLE: -+ emit(ctx, slti, MIPS_R_T9, dst, imm + 1); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ } -+} -+ -+/* Jump register (32-bit) */ -+void emit_jmp_r(struct jit_context *ctx, u8 dst, u8 src, s32 off, u8 op) -+{ -+ switch (op) { -+ /* No-op, used internally for branch optimization */ -+ case JIT_JNOP: -+ break; -+ /* PC += off if dst == src */ -+ case BPF_JEQ: -+ emit(ctx, beq, dst, src, off); -+ break; -+ /* PC += off if dst != src */ -+ case BPF_JNE: -+ emit(ctx, bne, dst, src, off); -+ break; -+ /* PC += off if dst & src */ -+ case BPF_JSET: -+ emit(ctx, and, MIPS_R_T9, dst, src); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ /* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */ -+ case JIT_JNSET: -+ emit(ctx, and, MIPS_R_T9, dst, src); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst > src */ -+ case BPF_JGT: -+ emit(ctx, sltu, MIPS_R_T9, src, dst); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst >= src */ -+ case BPF_JGE: -+ emit(ctx, sltu, MIPS_R_T9, dst, src); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst < src */ -+ case BPF_JLT: -+ emit(ctx, sltu, MIPS_R_T9, dst, src); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst <= src */ -+ case BPF_JLE: -+ emit(ctx, sltu, MIPS_R_T9, src, dst); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst > src (signed) */ -+ case BPF_JSGT: -+ emit(ctx, slt, MIPS_R_T9, src, dst); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst >= src (signed) */ -+ case BPF_JSGE: -+ emit(ctx, slt, MIPS_R_T9, dst, src); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst < src (signed) */ -+ case BPF_JSLT: -+ emit(ctx, slt, MIPS_R_T9, dst, src); -+ emit(ctx, bnez, MIPS_R_T9, off); -+ break; -+ /* PC += off if dst <= src (signed) */ -+ case BPF_JSLE: -+ emit(ctx, slt, MIPS_R_T9, src, dst); -+ emit(ctx, beqz, MIPS_R_T9, off); -+ break; -+ } -+} -+ -+/* Jump always */ -+int emit_ja(struct jit_context *ctx, s16 off) -+{ -+ int target = get_target(ctx, ctx->bpf_index + off + 1); -+ -+ if (target < 0) -+ return -1; -+ emit(ctx, j, target); -+ emit(ctx, nop); -+ return 0; -+} -+ -+/* Jump to epilogue */ -+int emit_exit(struct jit_context *ctx) -+{ -+ int target = get_target(ctx, ctx->program->len); -+ -+ if (target < 0) -+ return -1; -+ emit(ctx, j, target); -+ emit(ctx, nop); -+ return 0; -+} -+ -+/* Build the program body from eBPF bytecode */ -+static int build_body(struct jit_context *ctx) -+{ -+ const struct bpf_prog *prog = ctx->program; -+ unsigned int i; -+ -+ ctx->stack_used = 0; -+ for (i = 0; i < prog->len; i++) { -+ const struct bpf_insn *insn = &prog->insnsi[i]; -+ u32 *descp = &ctx->descriptors[i]; -+ int ret; -+ -+ access_reg(ctx, insn->src_reg); -+ access_reg(ctx, insn->dst_reg); -+ -+ ctx->bpf_index = i; -+ if (ctx->target == NULL) { -+ ctx->changes += INDEX(*descp) != ctx->jit_index; -+ *descp &= JIT_DESC_CONVERT; -+ *descp |= ctx->jit_index; -+ } -+ -+ ret = build_insn(insn, ctx); -+ if (ret < 0) -+ return ret; -+ -+ if (ret > 0) { -+ i++; -+ if (ctx->target == NULL) -+ descp[1] = ctx->jit_index; -+ } -+ } -+ -+ /* Store the end offset, where the epilogue begins */ -+ ctx->descriptors[prog->len] = ctx->jit_index; -+ return 0; -+} -+ -+/* Set the branch conversion flag on all instructions */ -+static void set_convert_flag(struct jit_context *ctx, bool enable) -+{ -+ const struct bpf_prog *prog = ctx->program; -+ u32 flag = enable ? JIT_DESC_CONVERT : 0; -+ unsigned int i; -+ -+ for (i = 0; i <= prog->len; i++) -+ ctx->descriptors[i] = INDEX(ctx->descriptors[i]) | flag; -+} -+ -+static void jit_fill_hole(void *area, unsigned int size) -+{ -+ u32 *p; -+ -+ /* We are guaranteed to have aligned memory. */ -+ for (p = area; size >= sizeof(u32); size -= sizeof(u32)) -+ uasm_i_break(&p, BRK_BUG); /* Increments p */ -+} -+ -+bool bpf_jit_needs_zext(void) -+{ -+ return true; -+} -+ -+struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) -+{ -+ struct bpf_prog *tmp, *orig_prog = prog; -+ struct bpf_binary_header *header = NULL; -+ struct jit_context ctx; -+ bool tmp_blinded = false; -+ unsigned int tmp_idx; -+ unsigned int image_size; -+ u8 *image_ptr; -+ int tries; -+ -+ /* -+ * If BPF JIT was not enabled then we must fall back to -+ * the interpreter. -+ */ -+ if (!prog->jit_requested) -+ return orig_prog; -+ /* -+ * If constant blinding was enabled and we failed during blinding -+ * then we must fall back to the interpreter. Otherwise, we save -+ * the new JITed code. -+ */ -+ tmp = bpf_jit_blind_constants(prog); -+ if (IS_ERR(tmp)) -+ return orig_prog; -+ if (tmp != prog) { -+ tmp_blinded = true; -+ prog = tmp; -+ } -+ -+ memset(&ctx, 0, sizeof(ctx)); -+ ctx.program = prog; -+ -+ /* -+ * Not able to allocate memory for descriptors[], then -+ * we must fall back to the interpreter -+ */ -+ ctx.descriptors = kcalloc(prog->len + 1, sizeof(*ctx.descriptors), -+ GFP_KERNEL); -+ if (ctx.descriptors == NULL) -+ goto out_err; -+ -+ /* First pass discovers used resources */ -+ if (build_body(&ctx) < 0) -+ goto out_err; -+ /* -+ * Second pass computes instruction offsets. -+ * If any PC-relative branches are out of range, a sequence of -+ * a PC-relative branch + a jump is generated, and we have to -+ * try again from the beginning to generate the new offsets. -+ * This is done until no additional conversions are necessary. -+ * The last two iterations are done with all branches being -+ * converted, to guarantee offset table convergence within a -+ * fixed number of iterations. -+ */ -+ ctx.jit_index = 0; -+ build_prologue(&ctx); -+ tmp_idx = ctx.jit_index; -+ -+ tries = JIT_MAX_ITERATIONS; -+ do { -+ ctx.jit_index = tmp_idx; -+ ctx.changes = 0; -+ if (tries == 2) -+ set_convert_flag(&ctx, true); -+ if (build_body(&ctx) < 0) -+ goto out_err; -+ } while (ctx.changes > 0 && --tries > 0); -+ -+ if (WARN_ONCE(ctx.changes > 0, "JIT offsets failed to converge")) -+ goto out_err; -+ -+ build_epilogue(&ctx, MIPS_R_RA); -+ -+ /* Now we know the size of the structure to make */ -+ image_size = sizeof(u32) * ctx.jit_index; -+ header = bpf_jit_binary_alloc(image_size, &image_ptr, -+ sizeof(u32), jit_fill_hole); -+ /* -+ * Not able to allocate memory for the structure then -+ * we must fall back to the interpretation -+ */ -+ if (header == NULL) -+ goto out_err; -+ -+ /* Actual pass to generate final JIT code */ -+ ctx.target = (u32 *)image_ptr; -+ ctx.jit_index = 0; -+ -+ /* -+ * If building the JITed code fails somehow, -+ * we fall back to the interpretation. -+ */ -+ build_prologue(&ctx); -+ if (build_body(&ctx) < 0) -+ goto out_err; -+ build_epilogue(&ctx, MIPS_R_RA); -+ -+ /* Populate line info meta data */ -+ set_convert_flag(&ctx, false); -+ bpf_prog_fill_jited_linfo(prog, &ctx.descriptors[1]); -+ -+ /* Set as read-only exec and flush instruction cache */ -+ bpf_jit_binary_lock_ro(header); -+ flush_icache_range((unsigned long)header, -+ (unsigned long)&ctx.target[ctx.jit_index]); -+ -+ if (bpf_jit_enable > 1) -+ bpf_jit_dump(prog->len, image_size, 2, ctx.target); -+ -+ prog->bpf_func = (void *)ctx.target; -+ prog->jited = 1; -+ prog->jited_len = image_size; -+ -+out: -+ if (tmp_blinded) -+ bpf_jit_prog_release_other(prog, prog == orig_prog ? -+ tmp : orig_prog); -+ kfree(ctx.descriptors); -+ return prog; -+ -+out_err: -+ prog = orig_prog; -+ if (header) -+ bpf_jit_binary_free(header); -+ goto out; -+} ---- /dev/null -+++ b/arch/mips/net/bpf_jit_comp.h -@@ -0,0 +1,211 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Just-In-Time compiler for eBPF bytecode on 32-bit and 64-bit MIPS. -+ * -+ * Copyright (c) 2021 Anyfi Networks AB. -+ * Author: Johan Almbladh -+ * -+ * Based on code and ideas from -+ * Copyright (c) 2017 Cavium, Inc. -+ * Copyright (c) 2017 Shubham Bansal -+ * Copyright (c) 2011 Mircea Gherzan -+ */ -+ -+#ifndef _BPF_JIT_COMP_H -+#define _BPF_JIT_COMP_H -+ -+/* MIPS registers */ -+#define MIPS_R_ZERO 0 /* Const zero */ -+#define MIPS_R_AT 1 /* Asm temp */ -+#define MIPS_R_V0 2 /* Result */ -+#define MIPS_R_V1 3 /* Result */ -+#define MIPS_R_A0 4 /* Argument */ -+#define MIPS_R_A1 5 /* Argument */ -+#define MIPS_R_A2 6 /* Argument */ -+#define MIPS_R_A3 7 /* Argument */ -+#define MIPS_R_A4 8 /* Arg (n64) */ -+#define MIPS_R_A5 9 /* Arg (n64) */ -+#define MIPS_R_A6 10 /* Arg (n64) */ -+#define MIPS_R_A7 11 /* Arg (n64) */ -+#define MIPS_R_T0 8 /* Temp (o32) */ -+#define MIPS_R_T1 9 /* Temp (o32) */ -+#define MIPS_R_T2 10 /* Temp (o32) */ -+#define MIPS_R_T3 11 /* Temp (o32) */ -+#define MIPS_R_T4 12 /* Temporary */ -+#define MIPS_R_T5 13 /* Temporary */ -+#define MIPS_R_T6 14 /* Temporary */ -+#define MIPS_R_T7 15 /* Temporary */ -+#define MIPS_R_S0 16 /* Saved */ -+#define MIPS_R_S1 17 /* Saved */ -+#define MIPS_R_S2 18 /* Saved */ -+#define MIPS_R_S3 19 /* Saved */ -+#define MIPS_R_S4 20 /* Saved */ -+#define MIPS_R_S5 21 /* Saved */ -+#define MIPS_R_S6 22 /* Saved */ -+#define MIPS_R_S7 23 /* Saved */ -+#define MIPS_R_T8 24 /* Temporary */ -+#define MIPS_R_T9 25 /* Temporary */ -+/* MIPS_R_K0 26 Reserved */ -+/* MIPS_R_K1 27 Reserved */ -+#define MIPS_R_GP 28 /* Global ptr */ -+#define MIPS_R_SP 29 /* Stack ptr */ -+#define MIPS_R_FP 30 /* Frame ptr */ -+#define MIPS_R_RA 31 /* Return */ -+ -+/* -+ * Jump address mask for immediate jumps. The four most significant bits -+ * must be equal to PC. -+ */ -+#define MIPS_JMP_MASK 0x0fffffffUL -+ -+/* Maximum number of iterations in offset table computation */ -+#define JIT_MAX_ITERATIONS 8 -+ -+/* -+ * Jump pseudo-instructions used internally -+ * for branch conversion and branch optimization. -+ */ -+#define JIT_JNSET 0xe0 -+#define JIT_JNOP 0xf0 -+ -+/* Descriptor flag for PC-relative branch conversion */ -+#define JIT_DESC_CONVERT BIT(31) -+ -+/* JIT context for an eBPF program */ -+struct jit_context { -+ struct bpf_prog *program; /* The eBPF program being JITed */ -+ u32 *descriptors; /* eBPF to JITed CPU insn descriptors */ -+ u32 *target; /* JITed code buffer */ -+ u32 bpf_index; /* Index of current BPF program insn */ -+ u32 jit_index; /* Index of current JIT target insn */ -+ u32 changes; /* Number of PC-relative branch conv */ -+ u32 accessed; /* Bit mask of read eBPF registers */ -+ u32 clobbered; /* Bit mask of modified CPU registers */ -+ u32 stack_size; /* Total allocated stack size in bytes */ -+ u32 saved_size; /* Size of callee-saved registers */ -+ u32 stack_used; /* Stack size used for function calls */ -+}; -+ -+/* Emit the instruction if the JIT memory space has been allocated */ -+#define emit(ctx, func, ...) \ -+do { \ -+ if ((ctx)->target != NULL) { \ -+ u32 *p = &(ctx)->target[ctx->jit_index]; \ -+ uasm_i_##func(&p, ##__VA_ARGS__); \ -+ } \ -+ (ctx)->jit_index++; \ -+} while (0) -+ -+/* -+ * Mark a BPF register as accessed, it needs to be -+ * initialized by the program if expected, e.g. FP. -+ */ -+static inline void access_reg(struct jit_context *ctx, u8 reg) -+{ -+ ctx->accessed |= BIT(reg); -+} -+ -+/* -+ * Mark a CPU register as clobbered, it needs to be -+ * saved/restored by the program if callee-saved. -+ */ -+static inline void clobber_reg(struct jit_context *ctx, u8 reg) -+{ -+ ctx->clobbered |= BIT(reg); -+} -+ -+/* -+ * Push registers on the stack, starting at a given depth from the stack -+ * pointer and increasing. The next depth to be written is returned. -+ */ -+int push_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth); -+ -+/* -+ * Pop registers from the stack, starting at a given depth from the stack -+ * pointer and increasing. The next depth to be read is returned. -+ */ -+int pop_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth); -+ -+/* Compute the 28-bit jump target address from a BPF program location */ -+int get_target(struct jit_context *ctx, u32 loc); -+ -+/* Compute the PC-relative offset to relative BPF program offset */ -+int get_offset(const struct jit_context *ctx, int off); -+ -+/* dst = imm (32-bit) */ -+void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm); -+ -+/* dst = src (32-bit) */ -+void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src); -+ -+/* Validate ALU/ALU64 immediate range */ -+bool valid_alu_i(u8 op, s32 imm); -+ -+/* Rewrite ALU/ALU64 immediate operation */ -+bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val); -+ -+/* ALU immediate operation (32-bit) */ -+void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op); -+ -+/* ALU register operation (32-bit) */ -+void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op); -+ -+/* Atomic read-modify-write (32-bit) */ -+void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code); -+ -+/* Atomic compare-and-exchange (32-bit) */ -+void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off); -+ -+/* Swap bytes and truncate a register word or half word */ -+void emit_bswap_r(struct jit_context *ctx, u8 dst, u32 width); -+ -+/* Validate JMP/JMP32 immediate range */ -+bool valid_jmp_i(u8 op, s32 imm); -+ -+/* Prepare a PC-relative jump operation with immediate conditional */ -+void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width, -+ u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off); -+ -+/* Prepare a PC-relative jump operation with register conditional */ -+void setup_jmp_r(struct jit_context *ctx, bool same_reg, -+ u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off); -+ -+/* Finish a PC-relative jump operation */ -+int finish_jmp(struct jit_context *ctx, u8 jit_op, s16 bpf_off); -+ -+/* Conditional JMP/JMP32 immediate */ -+void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op); -+ -+/* Conditional JMP/JMP32 register */ -+void emit_jmp_r(struct jit_context *ctx, u8 dst, u8 src, s32 off, u8 op); -+ -+/* Jump always */ -+int emit_ja(struct jit_context *ctx, s16 off); -+ -+/* Jump to epilogue */ -+int emit_exit(struct jit_context *ctx); -+ -+/* -+ * Build program prologue to set up the stack and registers. -+ * This function is implemented separately for 32-bit and 64-bit JITs. -+ */ -+void build_prologue(struct jit_context *ctx); -+ -+/* -+ * Build the program epilogue to restore the stack and registers. -+ * This function is implemented separately for 32-bit and 64-bit JITs. -+ */ -+void build_epilogue(struct jit_context *ctx, int dest_reg); -+ -+/* -+ * Convert an eBPF instruction to native instruction, i.e -+ * JITs an eBPF instruction. -+ * Returns : -+ * 0 - Successfully JITed an 8-byte eBPF instruction -+ * >0 - Successfully JITed a 16-byte eBPF instruction -+ * <0 - Failed to JIT. -+ * This function is implemented separately for 32-bit and 64-bit JITs. -+ */ -+int build_insn(const struct bpf_insn *insn, struct jit_context *ctx); -+ -+#endif /* _BPF_JIT_COMP_H */ ---- /dev/null -+++ b/arch/mips/net/bpf_jit_comp32.c -@@ -0,0 +1,1741 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Just-In-Time compiler for eBPF bytecode on MIPS. -+ * Implementation of JIT functions for 32-bit CPUs. -+ * -+ * Copyright (c) 2021 Anyfi Networks AB. -+ * Author: Johan Almbladh -+ * -+ * Based on code and ideas from -+ * Copyright (c) 2017 Cavium, Inc. -+ * Copyright (c) 2017 Shubham Bansal -+ * Copyright (c) 2011 Mircea Gherzan -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "bpf_jit_comp.h" -+ -+/* MIPS a4-a7 are not available in the o32 ABI */ -+#undef MIPS_R_A4 -+#undef MIPS_R_A5 -+#undef MIPS_R_A6 -+#undef MIPS_R_A7 -+ -+/* Stack is 8-byte aligned in o32 ABI */ -+#define MIPS_STACK_ALIGNMENT 8 -+ -+/* -+ * The top 16 bytes of a stack frame is reserved for the callee in O32 ABI. -+ * This corresponds to stack space for register arguments a0-a3. -+ */ -+#define JIT_RESERVED_STACK 16 -+ -+/* Temporary 64-bit register used by JIT */ -+#define JIT_REG_TMP MAX_BPF_JIT_REG -+ -+/* -+ * Number of prologue bytes to skip when doing a tail call. -+ * Tail call count (TCC) initialization (8 bytes) always, plus -+ * R0-to-v0 assignment (4 bytes) if big endian. -+ */ -+#ifdef __BIG_ENDIAN -+#define JIT_TCALL_SKIP 12 -+#else -+#define JIT_TCALL_SKIP 8 -+#endif -+ -+/* CPU registers holding the callee return value */ -+#define JIT_RETURN_REGS \ -+ (BIT(MIPS_R_V0) | \ -+ BIT(MIPS_R_V1)) -+ -+/* CPU registers arguments passed to callee directly */ -+#define JIT_ARG_REGS \ -+ (BIT(MIPS_R_A0) | \ -+ BIT(MIPS_R_A1) | \ -+ BIT(MIPS_R_A2) | \ -+ BIT(MIPS_R_A3)) -+ -+/* CPU register arguments passed to callee on stack */ -+#define JIT_STACK_REGS \ -+ (BIT(MIPS_R_T0) | \ -+ BIT(MIPS_R_T1) | \ -+ BIT(MIPS_R_T2) | \ -+ BIT(MIPS_R_T3) | \ -+ BIT(MIPS_R_T4) | \ -+ BIT(MIPS_R_T5)) -+ -+/* Caller-saved CPU registers */ -+#define JIT_CALLER_REGS \ -+ (JIT_RETURN_REGS | \ -+ JIT_ARG_REGS | \ -+ JIT_STACK_REGS) -+ -+/* Callee-saved CPU registers */ -+#define JIT_CALLEE_REGS \ -+ (BIT(MIPS_R_S0) | \ -+ BIT(MIPS_R_S1) | \ -+ BIT(MIPS_R_S2) | \ -+ BIT(MIPS_R_S3) | \ -+ BIT(MIPS_R_S4) | \ -+ BIT(MIPS_R_S5) | \ -+ BIT(MIPS_R_S6) | \ -+ BIT(MIPS_R_S7) | \ -+ BIT(MIPS_R_GP) | \ -+ BIT(MIPS_R_FP) | \ -+ BIT(MIPS_R_RA)) -+ -+/* -+ * Mapping of 64-bit eBPF registers to 32-bit native MIPS registers. -+ * -+ * 1) Native register pairs are ordered according to CPU endiannes, following -+ * the MIPS convention for passing 64-bit arguments and return values. -+ * 2) The eBPF return value, arguments and callee-saved registers are mapped -+ * to their native MIPS equivalents. -+ * 3) Since the 32 highest bits in the eBPF FP register are always zero, -+ * only one general-purpose register is actually needed for the mapping. -+ * We use the fp register for this purpose, and map the highest bits to -+ * the MIPS register r0 (zero). -+ * 4) We use the MIPS gp and at registers as internal temporary registers -+ * for constant blinding. The gp register is callee-saved. -+ * 5) One 64-bit temporary register is mapped for use when sign-extending -+ * immediate operands. MIPS registers t6-t9 are available to the JIT -+ * for as temporaries when implementing complex 64-bit operations. -+ * -+ * With this scheme all eBPF registers are being mapped to native MIPS -+ * registers without having to use any stack scratch space. The direct -+ * register mapping (2) simplifies the handling of function calls. -+ */ -+static const u8 bpf2mips32[][2] = { -+ /* Return value from in-kernel function, and exit value from eBPF */ -+ [BPF_REG_0] = {MIPS_R_V1, MIPS_R_V0}, -+ /* Arguments from eBPF program to in-kernel function */ -+ [BPF_REG_1] = {MIPS_R_A1, MIPS_R_A0}, -+ [BPF_REG_2] = {MIPS_R_A3, MIPS_R_A2}, -+ /* Remaining arguments, to be passed on the stack per O32 ABI */ -+ [BPF_REG_3] = {MIPS_R_T1, MIPS_R_T0}, -+ [BPF_REG_4] = {MIPS_R_T3, MIPS_R_T2}, -+ [BPF_REG_5] = {MIPS_R_T5, MIPS_R_T4}, -+ /* Callee-saved registers that in-kernel function will preserve */ -+ [BPF_REG_6] = {MIPS_R_S1, MIPS_R_S0}, -+ [BPF_REG_7] = {MIPS_R_S3, MIPS_R_S2}, -+ [BPF_REG_8] = {MIPS_R_S5, MIPS_R_S4}, -+ [BPF_REG_9] = {MIPS_R_S7, MIPS_R_S6}, -+ /* Read-only frame pointer to access the eBPF stack */ -+#ifdef __BIG_ENDIAN -+ [BPF_REG_FP] = {MIPS_R_FP, MIPS_R_ZERO}, -+#else -+ [BPF_REG_FP] = {MIPS_R_ZERO, MIPS_R_FP}, -+#endif -+ /* Temporary register for blinding constants */ -+ [BPF_REG_AX] = {MIPS_R_GP, MIPS_R_AT}, -+ /* Temporary register for internal JIT use */ -+ [JIT_REG_TMP] = {MIPS_R_T7, MIPS_R_T6}, -+}; -+ -+/* Get low CPU register for a 64-bit eBPF register mapping */ -+static inline u8 lo(const u8 reg[]) -+{ -+#ifdef __BIG_ENDIAN -+ return reg[0]; -+#else -+ return reg[1]; -+#endif -+} -+ -+/* Get high CPU register for a 64-bit eBPF register mapping */ -+static inline u8 hi(const u8 reg[]) -+{ -+#ifdef __BIG_ENDIAN -+ return reg[1]; -+#else -+ return reg[0]; -+#endif -+} -+ -+/* -+ * Mark a 64-bit CPU register pair as clobbered, it needs to be -+ * saved/restored by the program if callee-saved. -+ */ -+static void clobber_reg64(struct jit_context *ctx, const u8 reg[]) -+{ -+ clobber_reg(ctx, reg[0]); -+ clobber_reg(ctx, reg[1]); -+} -+ -+/* dst = imm (sign-extended) */ -+static void emit_mov_se_i64(struct jit_context *ctx, const u8 dst[], s32 imm) -+{ -+ emit_mov_i(ctx, lo(dst), imm); -+ if (imm < 0) -+ emit(ctx, addiu, hi(dst), MIPS_R_ZERO, -1); -+ else -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ clobber_reg64(ctx, dst); -+} -+ -+/* Zero extension, if verifier does not do it for us */ -+static void emit_zext_ver(struct jit_context *ctx, const u8 dst[]) -+{ -+ if (!ctx->program->aux->verifier_zext) { -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ clobber_reg(ctx, hi(dst)); -+ } -+} -+ -+/* Load delay slot, if ISA mandates it */ -+static void emit_load_delay(struct jit_context *ctx) -+{ -+ if (!cpu_has_mips_2_3_4_5_r) -+ emit(ctx, nop); -+} -+ -+/* ALU immediate operation (64-bit) */ -+static void emit_alu_i64(struct jit_context *ctx, -+ const u8 dst[], s32 imm, u8 op) -+{ -+ u8 src = MIPS_R_T6; -+ -+ /* -+ * ADD/SUB with all but the max negative imm can be handled by -+ * inverting the operation and the imm value, saving one insn. -+ */ -+ if (imm > S32_MIN && imm < 0) -+ switch (op) { -+ case BPF_ADD: -+ op = BPF_SUB; -+ imm = -imm; -+ break; -+ case BPF_SUB: -+ op = BPF_ADD; -+ imm = -imm; -+ break; -+ } -+ -+ /* Move immediate to temporary register */ -+ emit_mov_i(ctx, src, imm); -+ -+ switch (op) { -+ /* dst = dst + imm */ -+ case BPF_ADD: -+ emit(ctx, addu, lo(dst), lo(dst), src); -+ emit(ctx, sltu, MIPS_R_T9, lo(dst), src); -+ emit(ctx, addu, hi(dst), hi(dst), MIPS_R_T9); -+ if (imm < 0) -+ emit(ctx, addiu, hi(dst), hi(dst), -1); -+ break; -+ /* dst = dst - imm */ -+ case BPF_SUB: -+ emit(ctx, sltu, MIPS_R_T9, lo(dst), src); -+ emit(ctx, subu, lo(dst), lo(dst), src); -+ emit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9); -+ if (imm < 0) -+ emit(ctx, addiu, hi(dst), hi(dst), 1); -+ break; -+ /* dst = dst | imm */ -+ case BPF_OR: -+ emit(ctx, or, lo(dst), lo(dst), src); -+ if (imm < 0) -+ emit(ctx, addiu, hi(dst), MIPS_R_ZERO, -1); -+ break; -+ /* dst = dst & imm */ -+ case BPF_AND: -+ emit(ctx, and, lo(dst), lo(dst), src); -+ if (imm >= 0) -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ break; -+ /* dst = dst ^ imm */ -+ case BPF_XOR: -+ emit(ctx, xor, lo(dst), lo(dst), src); -+ if (imm < 0) { -+ emit(ctx, subu, hi(dst), MIPS_R_ZERO, hi(dst)); -+ emit(ctx, addiu, hi(dst), hi(dst), -1); -+ } -+ break; -+ } -+ clobber_reg64(ctx, dst); -+} -+ -+/* ALU register operation (64-bit) */ -+static void emit_alu_r64(struct jit_context *ctx, -+ const u8 dst[], const u8 src[], u8 op) -+{ -+ switch (BPF_OP(op)) { -+ /* dst = dst + src */ -+ case BPF_ADD: -+ if (src == dst) { -+ emit(ctx, srl, MIPS_R_T9, lo(dst), 31); -+ emit(ctx, addu, lo(dst), lo(dst), lo(dst)); -+ } else { -+ emit(ctx, addu, lo(dst), lo(dst), lo(src)); -+ emit(ctx, sltu, MIPS_R_T9, lo(dst), lo(src)); -+ } -+ emit(ctx, addu, hi(dst), hi(dst), hi(src)); -+ emit(ctx, addu, hi(dst), hi(dst), MIPS_R_T9); -+ break; -+ /* dst = dst - src */ -+ case BPF_SUB: -+ emit(ctx, sltu, MIPS_R_T9, lo(dst), lo(src)); -+ emit(ctx, subu, lo(dst), lo(dst), lo(src)); -+ emit(ctx, subu, hi(dst), hi(dst), hi(src)); -+ emit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9); -+ break; -+ /* dst = dst | src */ -+ case BPF_OR: -+ emit(ctx, or, lo(dst), lo(dst), lo(src)); -+ emit(ctx, or, hi(dst), hi(dst), hi(src)); -+ break; -+ /* dst = dst & src */ -+ case BPF_AND: -+ emit(ctx, and, lo(dst), lo(dst), lo(src)); -+ emit(ctx, and, hi(dst), hi(dst), hi(src)); -+ break; -+ /* dst = dst ^ src */ -+ case BPF_XOR: -+ emit(ctx, xor, lo(dst), lo(dst), lo(src)); -+ emit(ctx, xor, hi(dst), hi(dst), hi(src)); -+ break; -+ } -+ clobber_reg64(ctx, dst); -+} -+ -+/* ALU invert (64-bit) */ -+static void emit_neg_i64(struct jit_context *ctx, const u8 dst[]) -+{ -+ emit(ctx, sltu, MIPS_R_T9, MIPS_R_ZERO, lo(dst)); -+ emit(ctx, subu, lo(dst), MIPS_R_ZERO, lo(dst)); -+ emit(ctx, subu, hi(dst), MIPS_R_ZERO, hi(dst)); -+ emit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9); -+ -+ clobber_reg64(ctx, dst); -+} -+ -+/* ALU shift immediate (64-bit) */ -+static void emit_shift_i64(struct jit_context *ctx, -+ const u8 dst[], u32 imm, u8 op) -+{ -+ switch (BPF_OP(op)) { -+ /* dst = dst << imm */ -+ case BPF_LSH: -+ if (imm < 32) { -+ emit(ctx, srl, MIPS_R_T9, lo(dst), 32 - imm); -+ emit(ctx, sll, lo(dst), lo(dst), imm); -+ emit(ctx, sll, hi(dst), hi(dst), imm); -+ emit(ctx, or, hi(dst), hi(dst), MIPS_R_T9); -+ } else { -+ emit(ctx, sll, hi(dst), lo(dst), imm - 32); -+ emit(ctx, move, lo(dst), MIPS_R_ZERO); -+ } -+ break; -+ /* dst = dst >> imm */ -+ case BPF_RSH: -+ if (imm < 32) { -+ emit(ctx, sll, MIPS_R_T9, hi(dst), 32 - imm); -+ emit(ctx, srl, lo(dst), lo(dst), imm); -+ emit(ctx, srl, hi(dst), hi(dst), imm); -+ emit(ctx, or, lo(dst), lo(dst), MIPS_R_T9); -+ } else { -+ emit(ctx, srl, lo(dst), hi(dst), imm - 32); -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ } -+ break; -+ /* dst = dst >> imm (arithmetic) */ -+ case BPF_ARSH: -+ if (imm < 32) { -+ emit(ctx, sll, MIPS_R_T9, hi(dst), 32 - imm); -+ emit(ctx, srl, lo(dst), lo(dst), imm); -+ emit(ctx, sra, hi(dst), hi(dst), imm); -+ emit(ctx, or, lo(dst), lo(dst), MIPS_R_T9); -+ } else { -+ emit(ctx, sra, lo(dst), hi(dst), imm - 32); -+ emit(ctx, sra, hi(dst), hi(dst), 31); -+ } -+ break; -+ } -+ clobber_reg64(ctx, dst); -+} -+ -+/* ALU shift register (64-bit) */ -+static void emit_shift_r64(struct jit_context *ctx, -+ const u8 dst[], u8 src, u8 op) -+{ -+ u8 t1 = MIPS_R_T8; -+ u8 t2 = MIPS_R_T9; -+ -+ emit(ctx, andi, t1, src, 32); /* t1 = src & 32 */ -+ emit(ctx, beqz, t1, 16); /* PC += 16 if t1 == 0 */ -+ emit(ctx, nor, t2, src, MIPS_R_ZERO); /* t2 = ~src (delay slot) */ -+ -+ switch (BPF_OP(op)) { -+ /* dst = dst << src */ -+ case BPF_LSH: -+ /* Next: shift >= 32 */ -+ emit(ctx, sllv, hi(dst), lo(dst), src); /* dh = dl << src */ -+ emit(ctx, move, lo(dst), MIPS_R_ZERO); /* dl = 0 */ -+ emit(ctx, b, 20); /* PC += 20 */ -+ /* +16: shift < 32 */ -+ emit(ctx, srl, t1, lo(dst), 1); /* t1 = dl >> 1 */ -+ emit(ctx, srlv, t1, t1, t2); /* t1 = t1 >> t2 */ -+ emit(ctx, sllv, lo(dst), lo(dst), src); /* dl = dl << src */ -+ emit(ctx, sllv, hi(dst), hi(dst), src); /* dh = dh << src */ -+ emit(ctx, or, hi(dst), hi(dst), t1); /* dh = dh | t1 */ -+ break; -+ /* dst = dst >> src */ -+ case BPF_RSH: -+ /* Next: shift >= 32 */ -+ emit(ctx, srlv, lo(dst), hi(dst), src); /* dl = dh >> src */ -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); /* dh = 0 */ -+ emit(ctx, b, 20); /* PC += 20 */ -+ /* +16: shift < 32 */ -+ emit(ctx, sll, t1, hi(dst), 1); /* t1 = dl << 1 */ -+ emit(ctx, sllv, t1, t1, t2); /* t1 = t1 << t2 */ -+ emit(ctx, srlv, lo(dst), lo(dst), src); /* dl = dl >> src */ -+ emit(ctx, srlv, hi(dst), hi(dst), src); /* dh = dh >> src */ -+ emit(ctx, or, lo(dst), lo(dst), t1); /* dl = dl | t1 */ -+ break; -+ /* dst = dst >> src (arithmetic) */ -+ case BPF_ARSH: -+ /* Next: shift >= 32 */ -+ emit(ctx, srav, lo(dst), hi(dst), src); /* dl = dh >>a src */ -+ emit(ctx, sra, hi(dst), hi(dst), 31); /* dh = dh >>a 31 */ -+ emit(ctx, b, 20); /* PC += 20 */ -+ /* +16: shift < 32 */ -+ emit(ctx, sll, t1, hi(dst), 1); /* t1 = dl << 1 */ -+ emit(ctx, sllv, t1, t1, t2); /* t1 = t1 << t2 */ -+ emit(ctx, srlv, lo(dst), lo(dst), src); /* dl = dl >>a src */ -+ emit(ctx, srav, hi(dst), hi(dst), src); /* dh = dh >> src */ -+ emit(ctx, or, lo(dst), lo(dst), t1); /* dl = dl | t1 */ -+ break; -+ } -+ -+ /* +20: Done */ -+ clobber_reg64(ctx, dst); -+} -+ -+/* ALU mul immediate (64x32-bit) */ -+static void emit_mul_i64(struct jit_context *ctx, const u8 dst[], s32 imm) -+{ -+ u8 src = MIPS_R_T6; -+ u8 tmp = MIPS_R_T9; -+ -+ switch (imm) { -+ /* dst = dst * 1 is a no-op */ -+ case 1: -+ break; -+ /* dst = dst * -1 */ -+ case -1: -+ emit_neg_i64(ctx, dst); -+ break; -+ case 0: -+ emit_mov_r(ctx, lo(dst), MIPS_R_ZERO); -+ emit_mov_r(ctx, hi(dst), MIPS_R_ZERO); -+ break; -+ /* Full 64x32 multiply */ -+ default: -+ /* hi(dst) = hi(dst) * src(imm) */ -+ emit_mov_i(ctx, src, imm); -+ if (cpu_has_mips32r1 || cpu_has_mips32r6) { -+ emit(ctx, mul, hi(dst), hi(dst), src); -+ } else { -+ emit(ctx, multu, hi(dst), src); -+ emit(ctx, mflo, hi(dst)); -+ } -+ -+ /* hi(dst) = hi(dst) - lo(dst) */ -+ if (imm < 0) -+ emit(ctx, subu, hi(dst), hi(dst), lo(dst)); -+ -+ /* tmp = lo(dst) * src(imm) >> 32 */ -+ /* lo(dst) = lo(dst) * src(imm) */ -+ if (cpu_has_mips32r6) { -+ emit(ctx, muhu, tmp, lo(dst), src); -+ emit(ctx, mulu, lo(dst), lo(dst), src); -+ } else { -+ emit(ctx, multu, lo(dst), src); -+ emit(ctx, mflo, lo(dst)); -+ emit(ctx, mfhi, tmp); -+ } -+ -+ /* hi(dst) += tmp */ -+ emit(ctx, addu, hi(dst), hi(dst), tmp); -+ clobber_reg64(ctx, dst); -+ break; -+ } -+} -+ -+/* ALU mul register (64x64-bit) */ -+static void emit_mul_r64(struct jit_context *ctx, -+ const u8 dst[], const u8 src[]) -+{ -+ u8 acc = MIPS_R_T8; -+ u8 tmp = MIPS_R_T9; -+ -+ /* acc = hi(dst) * lo(src) */ -+ if (cpu_has_mips32r1 || cpu_has_mips32r6) { -+ emit(ctx, mul, acc, hi(dst), lo(src)); -+ } else { -+ emit(ctx, multu, hi(dst), lo(src)); -+ emit(ctx, mflo, acc); -+ } -+ -+ /* tmp = lo(dst) * hi(src) */ -+ if (cpu_has_mips32r1 || cpu_has_mips32r6) { -+ emit(ctx, mul, tmp, lo(dst), hi(src)); -+ } else { -+ emit(ctx, multu, lo(dst), hi(src)); -+ emit(ctx, mflo, tmp); -+ } -+ -+ /* acc += tmp */ -+ emit(ctx, addu, acc, acc, tmp); -+ -+ /* tmp = lo(dst) * lo(src) >> 32 */ -+ /* lo(dst) = lo(dst) * lo(src) */ -+ if (cpu_has_mips32r6) { -+ emit(ctx, muhu, tmp, lo(dst), lo(src)); -+ emit(ctx, mulu, lo(dst), lo(dst), lo(src)); -+ } else { -+ emit(ctx, multu, lo(dst), lo(src)); -+ emit(ctx, mflo, lo(dst)); -+ emit(ctx, mfhi, tmp); -+ } -+ -+ /* hi(dst) = acc + tmp */ -+ emit(ctx, addu, hi(dst), acc, tmp); -+ clobber_reg64(ctx, dst); -+} -+ -+/* Helper function for 64-bit modulo */ -+static u64 jit_mod64(u64 a, u64 b) -+{ -+ u64 rem; -+ -+ div64_u64_rem(a, b, &rem); -+ return rem; -+} -+ -+/* ALU div/mod register (64-bit) */ -+static void emit_divmod_r64(struct jit_context *ctx, -+ const u8 dst[], const u8 src[], u8 op) -+{ -+ const u8 *r0 = bpf2mips32[BPF_REG_0]; /* Mapped to v0-v1 */ -+ const u8 *r1 = bpf2mips32[BPF_REG_1]; /* Mapped to a0-a1 */ -+ const u8 *r2 = bpf2mips32[BPF_REG_2]; /* Mapped to a2-a3 */ -+ int exclude, k; -+ u32 addr = 0; -+ -+ /* Push caller-saved registers on stack */ -+ push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, -+ 0, JIT_RESERVED_STACK); -+ -+ /* Put 64-bit arguments 1 and 2 in registers a0-a3 */ -+ for (k = 0; k < 2; k++) { -+ emit(ctx, move, MIPS_R_T9, src[k]); -+ emit(ctx, move, r1[k], dst[k]); -+ emit(ctx, move, r2[k], MIPS_R_T9); -+ } -+ -+ /* Emit function call */ -+ switch (BPF_OP(op)) { -+ /* dst = dst / src */ -+ case BPF_DIV: -+ addr = (u32)&div64_u64; -+ break; -+ /* dst = dst % src */ -+ case BPF_MOD: -+ addr = (u32)&jit_mod64; -+ break; -+ } -+ emit_mov_i(ctx, MIPS_R_T9, addr); -+ emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); -+ emit(ctx, nop); /* Delay slot */ -+ -+ /* Store the 64-bit result in dst */ -+ emit(ctx, move, dst[0], r0[0]); -+ emit(ctx, move, dst[1], r0[1]); -+ -+ /* Restore caller-saved registers, excluding the computed result */ -+ exclude = BIT(lo(dst)) | BIT(hi(dst)); -+ pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, -+ exclude, JIT_RESERVED_STACK); -+ emit_load_delay(ctx); -+ -+ clobber_reg64(ctx, dst); -+ clobber_reg(ctx, MIPS_R_V0); -+ clobber_reg(ctx, MIPS_R_V1); -+ clobber_reg(ctx, MIPS_R_RA); -+} -+ -+/* Swap bytes in a register word */ -+static void emit_swap8_r(struct jit_context *ctx, u8 dst, u8 src, u8 mask) -+{ -+ u8 tmp = MIPS_R_T9; -+ -+ emit(ctx, and, tmp, src, mask); /* tmp = src & 0x00ff00ff */ -+ emit(ctx, sll, tmp, tmp, 8); /* tmp = tmp << 8 */ -+ emit(ctx, srl, dst, src, 8); /* dst = src >> 8 */ -+ emit(ctx, and, dst, dst, mask); /* dst = dst & 0x00ff00ff */ -+ emit(ctx, or, dst, dst, tmp); /* dst = dst | tmp */ -+} -+ -+/* Swap half words in a register word */ -+static void emit_swap16_r(struct jit_context *ctx, u8 dst, u8 src) -+{ -+ u8 tmp = MIPS_R_T9; -+ -+ emit(ctx, sll, tmp, src, 16); /* tmp = src << 16 */ -+ emit(ctx, srl, dst, src, 16); /* dst = src >> 16 */ -+ emit(ctx, or, dst, dst, tmp); /* dst = dst | tmp */ -+} -+ -+/* Swap bytes and truncate a register double word, word or half word */ -+static void emit_bswap_r64(struct jit_context *ctx, const u8 dst[], u32 width) -+{ -+ u8 tmp = MIPS_R_T8; -+ -+ switch (width) { -+ /* Swap bytes in a double word */ -+ case 64: -+ if (cpu_has_mips32r2 || cpu_has_mips32r6) { -+ emit(ctx, rotr, tmp, hi(dst), 16); -+ emit(ctx, rotr, hi(dst), lo(dst), 16); -+ emit(ctx, wsbh, lo(dst), tmp); -+ emit(ctx, wsbh, hi(dst), hi(dst)); -+ } else { -+ emit_swap16_r(ctx, tmp, lo(dst)); -+ emit_swap16_r(ctx, lo(dst), hi(dst)); -+ emit(ctx, move, hi(dst), tmp); -+ -+ emit(ctx, lui, tmp, 0xff); /* tmp = 0x00ff0000 */ -+ emit(ctx, ori, tmp, tmp, 0xff); /* tmp = 0x00ff00ff */ -+ emit_swap8_r(ctx, lo(dst), lo(dst), tmp); -+ emit_swap8_r(ctx, hi(dst), hi(dst), tmp); -+ } -+ break; -+ /* Swap bytes in a word */ -+ /* Swap bytes in a half word */ -+ case 32: -+ case 16: -+ emit_bswap_r(ctx, lo(dst), width); -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ break; -+ } -+ clobber_reg64(ctx, dst); -+} -+ -+/* Truncate a register double word, word or half word */ -+static void emit_trunc_r64(struct jit_context *ctx, const u8 dst[], u32 width) -+{ -+ switch (width) { -+ case 64: -+ break; -+ /* Zero-extend a word */ -+ case 32: -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ clobber_reg(ctx, hi(dst)); -+ break; -+ /* Zero-extend a half word */ -+ case 16: -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ emit(ctx, andi, lo(dst), lo(dst), 0xffff); -+ clobber_reg64(ctx, dst); -+ break; -+ } -+} -+ -+/* Load operation: dst = *(size*)(src + off) */ -+static void emit_ldx(struct jit_context *ctx, -+ const u8 dst[], u8 src, s16 off, u8 size) -+{ -+ switch (size) { -+ /* Load a byte */ -+ case BPF_B: -+ emit(ctx, lbu, lo(dst), off, src); -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ break; -+ /* Load a half word */ -+ case BPF_H: -+ emit(ctx, lhu, lo(dst), off, src); -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ break; -+ /* Load a word */ -+ case BPF_W: -+ emit(ctx, lw, lo(dst), off, src); -+ emit(ctx, move, hi(dst), MIPS_R_ZERO); -+ break; -+ /* Load a double word */ -+ case BPF_DW: -+ if (dst[1] == src) { -+ emit(ctx, lw, dst[0], off + 4, src); -+ emit(ctx, lw, dst[1], off, src); -+ } else { -+ emit(ctx, lw, dst[1], off, src); -+ emit(ctx, lw, dst[0], off + 4, src); -+ } -+ emit_load_delay(ctx); -+ break; -+ } -+ clobber_reg64(ctx, dst); -+} -+ -+/* Store operation: *(size *)(dst + off) = src */ -+static void emit_stx(struct jit_context *ctx, -+ const u8 dst, const u8 src[], s16 off, u8 size) -+{ -+ switch (size) { -+ /* Store a byte */ -+ case BPF_B: -+ emit(ctx, sb, lo(src), off, dst); -+ break; -+ /* Store a half word */ -+ case BPF_H: -+ emit(ctx, sh, lo(src), off, dst); -+ break; -+ /* Store a word */ -+ case BPF_W: -+ emit(ctx, sw, lo(src), off, dst); -+ break; -+ /* Store a double word */ -+ case BPF_DW: -+ emit(ctx, sw, src[1], off, dst); -+ emit(ctx, sw, src[0], off + 4, dst); -+ break; -+ } -+} -+ -+/* Atomic read-modify-write (32-bit, non-ll/sc fallback) */ -+static void emit_atomic_r32(struct jit_context *ctx, -+ u8 dst, u8 src, s16 off, u8 code) -+{ -+ u32 exclude = 0; -+ u32 addr = 0; -+ -+ /* Push caller-saved registers on stack */ -+ push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, -+ 0, JIT_RESERVED_STACK); -+ /* -+ * Argument 1: dst+off if xchg, otherwise src, passed in register a0 -+ * Argument 2: src if xchg, othersize dst+off, passed in register a1 -+ */ -+ emit(ctx, move, MIPS_R_T9, dst); -+ emit(ctx, move, MIPS_R_A0, src); -+ emit(ctx, addiu, MIPS_R_A1, MIPS_R_T9, off); -+ -+ /* Emit function call */ -+ switch (code) { -+ case BPF_ADD: -+ addr = (u32)&atomic_add; -+ break; -+ case BPF_SUB: -+ addr = (u32)&atomic_sub; -+ break; -+ case BPF_OR: -+ addr = (u32)&atomic_or; -+ break; -+ case BPF_AND: -+ addr = (u32)&atomic_and; -+ break; -+ case BPF_XOR: -+ addr = (u32)&atomic_xor; -+ break; -+ } -+ emit_mov_i(ctx, MIPS_R_T9, addr); -+ emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); -+ emit(ctx, nop); /* Delay slot */ -+ -+ /* Restore caller-saved registers, except any fetched value */ -+ pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, -+ exclude, JIT_RESERVED_STACK); -+ emit_load_delay(ctx); -+ clobber_reg(ctx, MIPS_R_RA); -+} -+ -+/* Atomic read-modify-write (64-bit) */ -+static void emit_atomic_r64(struct jit_context *ctx, -+ u8 dst, const u8 src[], s16 off, u8 code) -+{ -+ const u8 *r1 = bpf2mips32[BPF_REG_1]; /* Mapped to a0-a1 */ -+ u32 exclude = 0; -+ u32 addr = 0; -+ -+ /* Push caller-saved registers on stack */ -+ push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, -+ 0, JIT_RESERVED_STACK); -+ /* -+ * Argument 1: 64-bit src, passed in registers a0-a1 -+ * Argument 2: 32-bit dst+off, passed in register a2 -+ */ -+ emit(ctx, move, MIPS_R_T9, dst); -+ emit(ctx, move, r1[0], src[0]); -+ emit(ctx, move, r1[1], src[1]); -+ emit(ctx, addiu, MIPS_R_A2, MIPS_R_T9, off); -+ -+ /* Emit function call */ -+ switch (code) { -+ case BPF_ADD: -+ addr = (u32)&atomic64_add; -+ break; -+ case BPF_SUB: -+ addr = (u32)&atomic64_sub; -+ break; -+ case BPF_OR: -+ addr = (u32)&atomic64_or; -+ break; -+ case BPF_AND: -+ addr = (u32)&atomic64_and; -+ break; -+ case BPF_XOR: -+ addr = (u32)&atomic64_xor; -+ break; -+ } -+ emit_mov_i(ctx, MIPS_R_T9, addr); -+ emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); -+ emit(ctx, nop); /* Delay slot */ -+ -+ /* Restore caller-saved registers, except any fetched value */ -+ pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, -+ exclude, JIT_RESERVED_STACK); -+ emit_load_delay(ctx); -+ clobber_reg(ctx, MIPS_R_RA); -+} -+ -+/* -+ * Conditional movz or an emulated equivalent. -+ * Note that the rs register may be modified. -+ */ -+static void emit_movz_r(struct jit_context *ctx, u8 rd, u8 rs, u8 rt) -+{ -+ if (cpu_has_mips_2) { -+ emit(ctx, movz, rd, rs, rt); /* rd = rt ? rd : rs */ -+ } else if (cpu_has_mips32r6) { -+ if (rs != MIPS_R_ZERO) -+ emit(ctx, seleqz, rs, rs, rt); /* rs = 0 if rt == 0 */ -+ emit(ctx, selnez, rd, rd, rt); /* rd = 0 if rt != 0 */ -+ if (rs != MIPS_R_ZERO) -+ emit(ctx, or, rd, rd, rs); /* rd = rd | rs */ -+ } else { -+ emit(ctx, bnez, rt, 8); /* PC += 8 if rd != 0 */ -+ emit(ctx, nop); /* +0: delay slot */ -+ emit(ctx, or, rd, rs, MIPS_R_ZERO); /* +4: rd = rs */ -+ } -+ clobber_reg(ctx, rd); -+ clobber_reg(ctx, rs); -+} -+ -+/* -+ * Conditional movn or an emulated equivalent. -+ * Note that the rs register may be modified. -+ */ -+static void emit_movn_r(struct jit_context *ctx, u8 rd, u8 rs, u8 rt) -+{ -+ if (cpu_has_mips_2) { -+ emit(ctx, movn, rd, rs, rt); /* rd = rt ? rs : rd */ -+ } else if (cpu_has_mips32r6) { -+ if (rs != MIPS_R_ZERO) -+ emit(ctx, selnez, rs, rs, rt); /* rs = 0 if rt == 0 */ -+ emit(ctx, seleqz, rd, rd, rt); /* rd = 0 if rt != 0 */ -+ if (rs != MIPS_R_ZERO) -+ emit(ctx, or, rd, rd, rs); /* rd = rd | rs */ -+ } else { -+ emit(ctx, beqz, rt, 8); /* PC += 8 if rd == 0 */ -+ emit(ctx, nop); /* +0: delay slot */ -+ emit(ctx, or, rd, rs, MIPS_R_ZERO); /* +4: rd = rs */ -+ } -+ clobber_reg(ctx, rd); -+ clobber_reg(ctx, rs); -+} -+ -+/* Emulation of 64-bit sltiu rd, rs, imm, where imm may be S32_MAX + 1 */ -+static void emit_sltiu_r64(struct jit_context *ctx, u8 rd, -+ const u8 rs[], s64 imm) -+{ -+ u8 tmp = MIPS_R_T9; -+ -+ if (imm < 0) { -+ emit_mov_i(ctx, rd, imm); /* rd = imm */ -+ emit(ctx, sltu, rd, lo(rs), rd); /* rd = rsl < rd */ -+ emit(ctx, sltiu, tmp, hi(rs), -1); /* tmp = rsh < ~0U */ -+ emit(ctx, or, rd, rd, tmp); /* rd = rd | tmp */ -+ } else { /* imm >= 0 */ -+ if (imm > 0x7fff) { -+ emit_mov_i(ctx, rd, (s32)imm); /* rd = imm */ -+ emit(ctx, sltu, rd, lo(rs), rd); /* rd = rsl < rd */ -+ } else { -+ emit(ctx, sltiu, rd, lo(rs), imm); /* rd = rsl < imm */ -+ } -+ emit_movn_r(ctx, rd, MIPS_R_ZERO, hi(rs)); /* rd = 0 if rsh */ -+ } -+} -+ -+/* Emulation of 64-bit sltu rd, rs, rt */ -+static void emit_sltu_r64(struct jit_context *ctx, u8 rd, -+ const u8 rs[], const u8 rt[]) -+{ -+ u8 tmp = MIPS_R_T9; -+ -+ emit(ctx, sltu, rd, lo(rs), lo(rt)); /* rd = rsl < rtl */ -+ emit(ctx, subu, tmp, hi(rs), hi(rt)); /* tmp = rsh - rth */ -+ emit_movn_r(ctx, rd, MIPS_R_ZERO, tmp); /* rd = 0 if tmp != 0 */ -+ emit(ctx, sltu, tmp, hi(rs), hi(rt)); /* tmp = rsh < rth */ -+ emit(ctx, or, rd, rd, tmp); /* rd = rd | tmp */ -+} -+ -+/* Emulation of 64-bit slti rd, rs, imm, where imm may be S32_MAX + 1 */ -+static void emit_slti_r64(struct jit_context *ctx, u8 rd, -+ const u8 rs[], s64 imm) -+{ -+ u8 t1 = MIPS_R_T8; -+ u8 t2 = MIPS_R_T9; -+ u8 cmp; -+ -+ /* -+ * if ((rs < 0) ^ (imm < 0)) t1 = imm >u rsl -+ * else t1 = rsl > 31 */ -+ if (imm < 0) -+ emit_movz_r(ctx, t1, t2, rd); /* t1 = rd ? t1 : t2 */ -+ else -+ emit_movn_r(ctx, t1, t2, rd); /* t1 = rd ? t2 : t1 */ -+ /* -+ * if ((imm < 0 && rsh != 0xffffffff) || -+ * (imm >= 0 && rsh != 0)) -+ * t1 = 0 -+ */ -+ if (imm < 0) { -+ emit(ctx, addiu, rd, hi(rs), 1); /* rd = rsh + 1 */ -+ cmp = rd; -+ } else { /* imm >= 0 */ -+ cmp = hi(rs); -+ } -+ emit_movn_r(ctx, t1, MIPS_R_ZERO, cmp); /* t1 = 0 if cmp != 0 */ -+ -+ /* -+ * if (imm < 0) rd = rsh < -1 -+ * else rd = rsh != 0 -+ * rd = rd | t1 -+ */ -+ emit(ctx, slti, rd, hi(rs), imm < 0 ? -1 : 0); /* rd = rsh < hi(imm) */ -+ emit(ctx, or, rd, rd, t1); /* rd = rd | t1 */ -+} -+ -+/* Emulation of 64-bit(slt rd, rs, rt) */ -+static void emit_slt_r64(struct jit_context *ctx, u8 rd, -+ const u8 rs[], const u8 rt[]) -+{ -+ u8 t1 = MIPS_R_T7; -+ u8 t2 = MIPS_R_T8; -+ u8 t3 = MIPS_R_T9; -+ -+ /* -+ * if ((rs < 0) ^ (rt < 0)) t1 = rtl > 31 */ -+ emit_movn_r(ctx, t1, t2, rd); /* t1 = rd ? t2 : t1 */ -+ emit_movn_r(ctx, t1, MIPS_R_ZERO, t3); /* t1 = 0 if t3 != 0 */ -+ -+ /* rd = (rsh < rth) | t1 */ -+ emit(ctx, slt, rd, hi(rs), hi(rt)); /* rd = rsh = -0x7fff && imm <= 0x8000) { -+ emit(ctx, addiu, tmp, lo(dst), -imm); -+ } else if ((u32)imm <= 0xffff) { -+ emit(ctx, xori, tmp, lo(dst), imm); -+ } else { /* Register fallback */ -+ emit_mov_i(ctx, tmp, imm); -+ emit(ctx, xor, tmp, lo(dst), tmp); -+ } -+ if (imm < 0) { /* Compare sign extension */ -+ emit(ctx, addu, MIPS_R_T9, hi(dst), 1); -+ emit(ctx, or, tmp, tmp, MIPS_R_T9); -+ } else { /* Compare zero extension */ -+ emit(ctx, or, tmp, tmp, hi(dst)); -+ } -+ if (op == BPF_JEQ) -+ emit(ctx, beqz, tmp, off); -+ else /* BPF_JNE */ -+ emit(ctx, bnez, tmp, off); -+ break; -+ /* PC += off if dst & imm */ -+ /* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */ -+ case BPF_JSET: -+ case JIT_JNSET: -+ if ((u32)imm <= 0xffff) { -+ emit(ctx, andi, tmp, lo(dst), imm); -+ } else { /* Register fallback */ -+ emit_mov_i(ctx, tmp, imm); -+ emit(ctx, and, tmp, lo(dst), tmp); -+ } -+ if (imm < 0) /* Sign-extension pulls in high word */ -+ emit(ctx, or, tmp, tmp, hi(dst)); -+ if (op == BPF_JSET) -+ emit(ctx, bnez, tmp, off); -+ else /* JIT_JNSET */ -+ emit(ctx, beqz, tmp, off); -+ break; -+ /* PC += off if dst > imm */ -+ case BPF_JGT: -+ emit_sltiu_r64(ctx, tmp, dst, (s64)imm + 1); -+ emit(ctx, beqz, tmp, off); -+ break; -+ /* PC += off if dst >= imm */ -+ case BPF_JGE: -+ emit_sltiu_r64(ctx, tmp, dst, imm); -+ emit(ctx, beqz, tmp, off); -+ break; -+ /* PC += off if dst < imm */ -+ case BPF_JLT: -+ emit_sltiu_r64(ctx, tmp, dst, imm); -+ emit(ctx, bnez, tmp, off); -+ break; -+ /* PC += off if dst <= imm */ -+ case BPF_JLE: -+ emit_sltiu_r64(ctx, tmp, dst, (s64)imm + 1); -+ emit(ctx, bnez, tmp, off); -+ break; -+ /* PC += off if dst > imm (signed) */ -+ case BPF_JSGT: -+ emit_slti_r64(ctx, tmp, dst, (s64)imm + 1); -+ emit(ctx, beqz, tmp, off); -+ break; -+ /* PC += off if dst >= imm (signed) */ -+ case BPF_JSGE: -+ emit_slti_r64(ctx, tmp, dst, imm); -+ emit(ctx, beqz, tmp, off); -+ break; -+ /* PC += off if dst < imm (signed) */ -+ case BPF_JSLT: -+ emit_slti_r64(ctx, tmp, dst, imm); -+ emit(ctx, bnez, tmp, off); -+ break; -+ /* PC += off if dst <= imm (signed) */ -+ case BPF_JSLE: -+ emit_slti_r64(ctx, tmp, dst, (s64)imm + 1); -+ emit(ctx, bnez, tmp, off); -+ break; -+ } -+} -+ -+/* Jump register (64-bit) */ -+static void emit_jmp_r64(struct jit_context *ctx, -+ const u8 dst[], const u8 src[], s32 off, u8 op) -+{ -+ u8 t1 = MIPS_R_T6; -+ u8 t2 = MIPS_R_T7; -+ -+ switch (op) { -+ /* No-op, used internally for branch optimization */ -+ case JIT_JNOP: -+ break; -+ /* PC += off if dst == src */ -+ /* PC += off if dst != src */ -+ case BPF_JEQ: -+ case BPF_JNE: -+ emit(ctx, subu, t1, lo(dst), lo(src)); -+ emit(ctx, subu, t2, hi(dst), hi(src)); -+ emit(ctx, or, t1, t1, t2); -+ if (op == BPF_JEQ) -+ emit(ctx, beqz, t1, off); -+ else /* BPF_JNE */ -+ emit(ctx, bnez, t1, off); -+ break; -+ /* PC += off if dst & src */ -+ /* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */ -+ case BPF_JSET: -+ case JIT_JNSET: -+ emit(ctx, and, t1, lo(dst), lo(src)); -+ emit(ctx, and, t2, hi(dst), hi(src)); -+ emit(ctx, or, t1, t1, t2); -+ if (op == BPF_JSET) -+ emit(ctx, bnez, t1, off); -+ else /* JIT_JNSET */ -+ emit(ctx, beqz, t1, off); -+ break; -+ /* PC += off if dst > src */ -+ case BPF_JGT: -+ emit_sltu_r64(ctx, t1, src, dst); -+ emit(ctx, bnez, t1, off); -+ break; -+ /* PC += off if dst >= src */ -+ case BPF_JGE: -+ emit_sltu_r64(ctx, t1, dst, src); -+ emit(ctx, beqz, t1, off); -+ break; -+ /* PC += off if dst < src */ -+ case BPF_JLT: -+ emit_sltu_r64(ctx, t1, dst, src); -+ emit(ctx, bnez, t1, off); -+ break; -+ /* PC += off if dst <= src */ -+ case BPF_JLE: -+ emit_sltu_r64(ctx, t1, src, dst); -+ emit(ctx, beqz, t1, off); -+ break; -+ /* PC += off if dst > src (signed) */ -+ case BPF_JSGT: -+ emit_slt_r64(ctx, t1, src, dst); -+ emit(ctx, bnez, t1, off); -+ break; -+ /* PC += off if dst >= src (signed) */ -+ case BPF_JSGE: -+ emit_slt_r64(ctx, t1, dst, src); -+ emit(ctx, beqz, t1, off); -+ break; -+ /* PC += off if dst < src (signed) */ -+ case BPF_JSLT: -+ emit_slt_r64(ctx, t1, dst, src); -+ emit(ctx, bnez, t1, off); -+ break; -+ /* PC += off if dst <= src (signed) */ -+ case BPF_JSLE: -+ emit_slt_r64(ctx, t1, src, dst); -+ emit(ctx, beqz, t1, off); -+ break; -+ } -+} -+ -+/* Function call */ -+static int emit_call(struct jit_context *ctx, const struct bpf_insn *insn) -+{ -+ bool fixed; -+ u64 addr; -+ -+ /* Decode the call address */ -+ if (bpf_jit_get_func_addr(ctx->program, insn, false, -+ &addr, &fixed) < 0) -+ return -1; -+ if (!fixed) -+ return -1; -+ -+ /* Push stack arguments */ -+ push_regs(ctx, JIT_STACK_REGS, 0, JIT_RESERVED_STACK); -+ -+ /* Emit function call */ -+ emit_mov_i(ctx, MIPS_R_T9, addr); -+ emit(ctx, jalr, MIPS_R_RA, MIPS_R_T9); -+ emit(ctx, nop); /* Delay slot */ -+ -+ clobber_reg(ctx, MIPS_R_RA); -+ clobber_reg(ctx, MIPS_R_V0); -+ clobber_reg(ctx, MIPS_R_V1); -+ return 0; -+} -+ -+/* Function tail call */ -+static int emit_tail_call(struct jit_context *ctx) -+{ -+ u8 ary = lo(bpf2mips32[BPF_REG_2]); -+ u8 ind = lo(bpf2mips32[BPF_REG_3]); -+ u8 t1 = MIPS_R_T8; -+ u8 t2 = MIPS_R_T9; -+ int off; -+ -+ /* -+ * Tail call: -+ * eBPF R1 - function argument (context ptr), passed in a0-a1 -+ * eBPF R2 - ptr to object with array of function entry points -+ * eBPF R3 - array index of function to be called -+ * stack[sz] - remaining tail call count, initialized in prologue -+ */ -+ -+ /* if (ind >= ary->map.max_entries) goto out */ -+ off = offsetof(struct bpf_array, map.max_entries); -+ if (off > 0x7fff) -+ return -1; -+ emit(ctx, lw, t1, off, ary); /* t1 = ary->map.max_entries*/ -+ emit_load_delay(ctx); /* Load delay slot */ -+ emit(ctx, sltu, t1, ind, t1); /* t1 = ind < t1 */ -+ emit(ctx, beqz, t1, get_offset(ctx, 1)); /* PC += off(1) if t1 == 0 */ -+ /* (next insn delay slot) */ -+ /* if (TCC-- <= 0) goto out */ -+ emit(ctx, lw, t2, ctx->stack_size, MIPS_R_SP); /* t2 = *(SP + size) */ -+ emit_load_delay(ctx); /* Load delay slot */ -+ emit(ctx, blez, t2, get_offset(ctx, 1)); /* PC += off(1) if t2 < 0 */ -+ emit(ctx, addiu, t2, t2, -1); /* t2-- (delay slot) */ -+ emit(ctx, sw, t2, ctx->stack_size, MIPS_R_SP); /* *(SP + size) = t2 */ -+ -+ /* prog = ary->ptrs[ind] */ -+ off = offsetof(struct bpf_array, ptrs); -+ if (off > 0x7fff) -+ return -1; -+ emit(ctx, sll, t1, ind, 2); /* t1 = ind << 2 */ -+ emit(ctx, addu, t1, t1, ary); /* t1 += ary */ -+ emit(ctx, lw, t2, off, t1); /* t2 = *(t1 + off) */ -+ emit_load_delay(ctx); /* Load delay slot */ -+ -+ /* if (prog == 0) goto out */ -+ emit(ctx, beqz, t2, get_offset(ctx, 1)); /* PC += off(1) if t2 == 0 */ -+ emit(ctx, nop); /* Delay slot */ -+ -+ /* func = prog->bpf_func + 8 (prologue skip offset) */ -+ off = offsetof(struct bpf_prog, bpf_func); -+ if (off > 0x7fff) -+ return -1; -+ emit(ctx, lw, t1, off, t2); /* t1 = *(t2 + off) */ -+ emit_load_delay(ctx); /* Load delay slot */ -+ emit(ctx, addiu, t1, t1, JIT_TCALL_SKIP); /* t1 += skip (8 or 12) */ -+ -+ /* goto func */ -+ build_epilogue(ctx, t1); -+ return 0; -+} -+ -+/* -+ * Stack frame layout for a JITed program (stack grows down). -+ * -+ * Higher address : Caller's stack frame : -+ * :----------------------------: -+ * : 64-bit eBPF args r3-r5 : -+ * :----------------------------: -+ * : Reserved / tail call count : -+ * +============================+ <--- MIPS sp before call -+ * | Callee-saved registers, | -+ * | including RA and FP | -+ * +----------------------------+ <--- eBPF FP (MIPS zero,fp) -+ * | Local eBPF variables | -+ * | allocated by program | -+ * +----------------------------+ -+ * | Reserved for caller-saved | -+ * | registers | -+ * +----------------------------+ -+ * | Reserved for 64-bit eBPF | -+ * | args r3-r5 & args passed | -+ * | on stack in kernel calls | -+ * Lower address +============================+ <--- MIPS sp -+ */ -+ -+/* Build program prologue to set up the stack and registers */ -+void build_prologue(struct jit_context *ctx) -+{ -+ const u8 *r1 = bpf2mips32[BPF_REG_1]; -+ const u8 *fp = bpf2mips32[BPF_REG_FP]; -+ int stack, saved, locals, reserved; -+ -+ /* -+ * The first two instructions initialize TCC in the reserved (for us) -+ * 16-byte area in the parent's stack frame. On a tail call, the -+ * calling function jumps into the prologue after these instructions. -+ */ -+ emit(ctx, ori, MIPS_R_T9, MIPS_R_ZERO, -+ min(MAX_TAIL_CALL_CNT + 1, 0xffff)); -+ emit(ctx, sw, MIPS_R_T9, 0, MIPS_R_SP); -+ -+ /* -+ * Register eBPF R1 contains the 32-bit context pointer argument. -+ * A 32-bit argument is always passed in MIPS register a0, regardless -+ * of CPU endianness. Initialize R1 accordingly and zero-extend. -+ */ -+#ifdef __BIG_ENDIAN -+ emit(ctx, move, lo(r1), MIPS_R_A0); -+#endif -+ -+ /* === Entry-point for tail calls === */ -+ -+ /* Zero-extend the 32-bit argument */ -+ emit(ctx, move, hi(r1), MIPS_R_ZERO); -+ -+ /* If the eBPF frame pointer was accessed it must be saved */ -+ if (ctx->accessed & BIT(BPF_REG_FP)) -+ clobber_reg64(ctx, fp); -+ -+ /* Compute the stack space needed for callee-saved registers */ -+ saved = hweight32(ctx->clobbered & JIT_CALLEE_REGS) * sizeof(u32); -+ saved = ALIGN(saved, MIPS_STACK_ALIGNMENT); -+ -+ /* Stack space used by eBPF program local data */ -+ locals = ALIGN(ctx->program->aux->stack_depth, MIPS_STACK_ALIGNMENT); -+ -+ /* -+ * If we are emitting function calls, reserve extra stack space for -+ * caller-saved registers and function arguments passed on the stack. -+ * The required space is computed automatically during resource -+ * usage discovery (pass 1). -+ */ -+ reserved = ctx->stack_used; -+ -+ /* Allocate the stack frame */ -+ stack = ALIGN(saved + locals + reserved, MIPS_STACK_ALIGNMENT); -+ emit(ctx, addiu, MIPS_R_SP, MIPS_R_SP, -stack); -+ -+ /* Store callee-saved registers on stack */ -+ push_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, stack - saved); -+ -+ /* Initialize the eBPF frame pointer if accessed */ -+ if (ctx->accessed & BIT(BPF_REG_FP)) -+ emit(ctx, addiu, lo(fp), MIPS_R_SP, stack - saved); -+ -+ ctx->saved_size = saved; -+ ctx->stack_size = stack; -+} -+ -+/* Build the program epilogue to restore the stack and registers */ -+void build_epilogue(struct jit_context *ctx, int dest_reg) -+{ -+ /* Restore callee-saved registers from stack */ -+ pop_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, -+ ctx->stack_size - ctx->saved_size); -+ /* -+ * A 32-bit return value is always passed in MIPS register v0, -+ * but on big-endian targets the low part of R0 is mapped to v1. -+ */ -+#ifdef __BIG_ENDIAN -+ emit(ctx, move, MIPS_R_V0, MIPS_R_V1); -+#endif -+ -+ /* Jump to the return address and adjust the stack pointer */ -+ emit(ctx, jr, dest_reg); -+ emit(ctx, addiu, MIPS_R_SP, MIPS_R_SP, ctx->stack_size); -+} -+ -+/* Build one eBPF instruction */ -+int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) -+{ -+ const u8 *dst = bpf2mips32[insn->dst_reg]; -+ const u8 *src = bpf2mips32[insn->src_reg]; -+ const u8 *tmp = bpf2mips32[JIT_REG_TMP]; -+ u8 code = insn->code; -+ s16 off = insn->off; -+ s32 imm = insn->imm; -+ s32 val, rel; -+ u8 alu, jmp; -+ -+ switch (code) { -+ /* ALU operations */ -+ /* dst = imm */ -+ case BPF_ALU | BPF_MOV | BPF_K: -+ emit_mov_i(ctx, lo(dst), imm); -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = src */ -+ case BPF_ALU | BPF_MOV | BPF_X: -+ if (imm == 1) { -+ /* Special mov32 for zext */ -+ emit_mov_i(ctx, hi(dst), 0); -+ } else { -+ emit_mov_r(ctx, lo(dst), lo(src)); -+ emit_zext_ver(ctx, dst); -+ } -+ break; -+ /* dst = -dst */ -+ case BPF_ALU | BPF_NEG: -+ emit_alu_i(ctx, lo(dst), 0, BPF_NEG); -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = dst & imm */ -+ /* dst = dst | imm */ -+ /* dst = dst ^ imm */ -+ /* dst = dst << imm */ -+ /* dst = dst >> imm */ -+ /* dst = dst >> imm (arithmetic) */ -+ /* dst = dst + imm */ -+ /* dst = dst - imm */ -+ /* dst = dst * imm */ -+ /* dst = dst / imm */ -+ /* dst = dst % imm */ -+ case BPF_ALU | BPF_OR | BPF_K: -+ case BPF_ALU | BPF_AND | BPF_K: -+ case BPF_ALU | BPF_XOR | BPF_K: -+ case BPF_ALU | BPF_LSH | BPF_K: -+ case BPF_ALU | BPF_RSH | BPF_K: -+ case BPF_ALU | BPF_ARSH | BPF_K: -+ case BPF_ALU | BPF_ADD | BPF_K: -+ case BPF_ALU | BPF_SUB | BPF_K: -+ case BPF_ALU | BPF_MUL | BPF_K: -+ case BPF_ALU | BPF_DIV | BPF_K: -+ case BPF_ALU | BPF_MOD | BPF_K: -+ if (!valid_alu_i(BPF_OP(code), imm)) { -+ emit_mov_i(ctx, MIPS_R_T6, imm); -+ emit_alu_r(ctx, lo(dst), MIPS_R_T6, BPF_OP(code)); -+ } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { -+ emit_alu_i(ctx, lo(dst), val, alu); -+ } -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = dst & src */ -+ /* dst = dst | src */ -+ /* dst = dst ^ src */ -+ /* dst = dst << src */ -+ /* dst = dst >> src */ -+ /* dst = dst >> src (arithmetic) */ -+ /* dst = dst + src */ -+ /* dst = dst - src */ -+ /* dst = dst * src */ -+ /* dst = dst / src */ -+ /* dst = dst % src */ -+ case BPF_ALU | BPF_AND | BPF_X: -+ case BPF_ALU | BPF_OR | BPF_X: -+ case BPF_ALU | BPF_XOR | BPF_X: -+ case BPF_ALU | BPF_LSH | BPF_X: -+ case BPF_ALU | BPF_RSH | BPF_X: -+ case BPF_ALU | BPF_ARSH | BPF_X: -+ case BPF_ALU | BPF_ADD | BPF_X: -+ case BPF_ALU | BPF_SUB | BPF_X: -+ case BPF_ALU | BPF_MUL | BPF_X: -+ case BPF_ALU | BPF_DIV | BPF_X: -+ case BPF_ALU | BPF_MOD | BPF_X: -+ emit_alu_r(ctx, lo(dst), lo(src), BPF_OP(code)); -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = imm (64-bit) */ -+ case BPF_ALU64 | BPF_MOV | BPF_K: -+ emit_mov_se_i64(ctx, dst, imm); -+ break; -+ /* dst = src (64-bit) */ -+ case BPF_ALU64 | BPF_MOV | BPF_X: -+ emit_mov_r(ctx, lo(dst), lo(src)); -+ emit_mov_r(ctx, hi(dst), hi(src)); -+ break; -+ /* dst = -dst (64-bit) */ -+ case BPF_ALU64 | BPF_NEG: -+ emit_neg_i64(ctx, dst); -+ break; -+ /* dst = dst & imm (64-bit) */ -+ case BPF_ALU64 | BPF_AND | BPF_K: -+ emit_alu_i64(ctx, dst, imm, BPF_OP(code)); -+ break; -+ /* dst = dst | imm (64-bit) */ -+ /* dst = dst ^ imm (64-bit) */ -+ /* dst = dst + imm (64-bit) */ -+ /* dst = dst - imm (64-bit) */ -+ case BPF_ALU64 | BPF_OR | BPF_K: -+ case BPF_ALU64 | BPF_XOR | BPF_K: -+ case BPF_ALU64 | BPF_ADD | BPF_K: -+ case BPF_ALU64 | BPF_SUB | BPF_K: -+ if (imm) -+ emit_alu_i64(ctx, dst, imm, BPF_OP(code)); -+ break; -+ /* dst = dst << imm (64-bit) */ -+ /* dst = dst >> imm (64-bit) */ -+ /* dst = dst >> imm (64-bit, arithmetic) */ -+ case BPF_ALU64 | BPF_LSH | BPF_K: -+ case BPF_ALU64 | BPF_RSH | BPF_K: -+ case BPF_ALU64 | BPF_ARSH | BPF_K: -+ if (imm) -+ emit_shift_i64(ctx, dst, imm, BPF_OP(code)); -+ break; -+ /* dst = dst * imm (64-bit) */ -+ case BPF_ALU64 | BPF_MUL | BPF_K: -+ emit_mul_i64(ctx, dst, imm); -+ break; -+ /* dst = dst / imm (64-bit) */ -+ /* dst = dst % imm (64-bit) */ -+ case BPF_ALU64 | BPF_DIV | BPF_K: -+ case BPF_ALU64 | BPF_MOD | BPF_K: -+ /* -+ * Sign-extend the immediate value into a temporary register, -+ * and then do the operation on this register. -+ */ -+ emit_mov_se_i64(ctx, tmp, imm); -+ emit_divmod_r64(ctx, dst, tmp, BPF_OP(code)); -+ break; -+ /* dst = dst & src (64-bit) */ -+ /* dst = dst | src (64-bit) */ -+ /* dst = dst ^ src (64-bit) */ -+ /* dst = dst + src (64-bit) */ -+ /* dst = dst - src (64-bit) */ -+ case BPF_ALU64 | BPF_AND | BPF_X: -+ case BPF_ALU64 | BPF_OR | BPF_X: -+ case BPF_ALU64 | BPF_XOR | BPF_X: -+ case BPF_ALU64 | BPF_ADD | BPF_X: -+ case BPF_ALU64 | BPF_SUB | BPF_X: -+ emit_alu_r64(ctx, dst, src, BPF_OP(code)); -+ break; -+ /* dst = dst << src (64-bit) */ -+ /* dst = dst >> src (64-bit) */ -+ /* dst = dst >> src (64-bit, arithmetic) */ -+ case BPF_ALU64 | BPF_LSH | BPF_X: -+ case BPF_ALU64 | BPF_RSH | BPF_X: -+ case BPF_ALU64 | BPF_ARSH | BPF_X: -+ emit_shift_r64(ctx, dst, lo(src), BPF_OP(code)); -+ break; -+ /* dst = dst * src (64-bit) */ -+ case BPF_ALU64 | BPF_MUL | BPF_X: -+ emit_mul_r64(ctx, dst, src); -+ break; -+ /* dst = dst / src (64-bit) */ -+ /* dst = dst % src (64-bit) */ -+ case BPF_ALU64 | BPF_DIV | BPF_X: -+ case BPF_ALU64 | BPF_MOD | BPF_X: -+ emit_divmod_r64(ctx, dst, src, BPF_OP(code)); -+ break; -+ /* dst = htole(dst) */ -+ /* dst = htobe(dst) */ -+ case BPF_ALU | BPF_END | BPF_FROM_LE: -+ case BPF_ALU | BPF_END | BPF_FROM_BE: -+ if (BPF_SRC(code) == -+#ifdef __BIG_ENDIAN -+ BPF_FROM_LE -+#else -+ BPF_FROM_BE -+#endif -+ ) -+ emit_bswap_r64(ctx, dst, imm); -+ else -+ emit_trunc_r64(ctx, dst, imm); -+ break; -+ /* dst = imm64 */ -+ case BPF_LD | BPF_IMM | BPF_DW: -+ emit_mov_i(ctx, lo(dst), imm); -+ emit_mov_i(ctx, hi(dst), insn[1].imm); -+ return 1; -+ /* LDX: dst = *(size *)(src + off) */ -+ case BPF_LDX | BPF_MEM | BPF_W: -+ case BPF_LDX | BPF_MEM | BPF_H: -+ case BPF_LDX | BPF_MEM | BPF_B: -+ case BPF_LDX | BPF_MEM | BPF_DW: -+ emit_ldx(ctx, dst, lo(src), off, BPF_SIZE(code)); -+ break; -+ /* ST: *(size *)(dst + off) = imm */ -+ case BPF_ST | BPF_MEM | BPF_W: -+ case BPF_ST | BPF_MEM | BPF_H: -+ case BPF_ST | BPF_MEM | BPF_B: -+ case BPF_ST | BPF_MEM | BPF_DW: -+ switch (BPF_SIZE(code)) { -+ case BPF_DW: -+ /* Sign-extend immediate value into temporary reg */ -+ emit_mov_se_i64(ctx, tmp, imm); -+ break; -+ case BPF_W: -+ case BPF_H: -+ case BPF_B: -+ emit_mov_i(ctx, lo(tmp), imm); -+ break; -+ } -+ emit_stx(ctx, lo(dst), tmp, off, BPF_SIZE(code)); -+ break; -+ /* STX: *(size *)(dst + off) = src */ -+ case BPF_STX | BPF_MEM | BPF_W: -+ case BPF_STX | BPF_MEM | BPF_H: -+ case BPF_STX | BPF_MEM | BPF_B: -+ case BPF_STX | BPF_MEM | BPF_DW: -+ emit_stx(ctx, lo(dst), src, off, BPF_SIZE(code)); -+ break; -+ /* Speculation barrier */ -+ case BPF_ST | BPF_NOSPEC: -+ break; -+ /* Atomics */ -+ case BPF_STX | BPF_XADD | BPF_W: -+ switch (imm) { -+ case BPF_ADD: -+ case BPF_AND: -+ case BPF_OR: -+ case BPF_XOR: -+ if (cpu_has_llsc) -+ emit_atomic_r(ctx, lo(dst), lo(src), off, imm); -+ else /* Non-ll/sc fallback */ -+ emit_atomic_r32(ctx, lo(dst), lo(src), -+ off, imm); -+ break; -+ default: -+ goto notyet; -+ } -+ break; -+ /* Atomics (64-bit) */ -+ case BPF_STX | BPF_XADD | BPF_DW: -+ switch (imm) { -+ case BPF_ADD: -+ case BPF_AND: -+ case BPF_OR: -+ case BPF_XOR: -+ emit_atomic_r64(ctx, lo(dst), src, off, imm); -+ break; -+ default: -+ goto notyet; -+ } -+ break; -+ /* PC += off if dst == src */ -+ /* PC += off if dst != src */ -+ /* PC += off if dst & src */ -+ /* PC += off if dst > src */ -+ /* PC += off if dst >= src */ -+ /* PC += off if dst < src */ -+ /* PC += off if dst <= src */ -+ /* PC += off if dst > src (signed) */ -+ /* PC += off if dst >= src (signed) */ -+ /* PC += off if dst < src (signed) */ -+ /* PC += off if dst <= src (signed) */ -+ case BPF_JMP32 | BPF_JEQ | BPF_X: -+ case BPF_JMP32 | BPF_JNE | BPF_X: -+ case BPF_JMP32 | BPF_JSET | BPF_X: -+ case BPF_JMP32 | BPF_JGT | BPF_X: -+ case BPF_JMP32 | BPF_JGE | BPF_X: -+ case BPF_JMP32 | BPF_JLT | BPF_X: -+ case BPF_JMP32 | BPF_JLE | BPF_X: -+ case BPF_JMP32 | BPF_JSGT | BPF_X: -+ case BPF_JMP32 | BPF_JSGE | BPF_X: -+ case BPF_JMP32 | BPF_JSLT | BPF_X: -+ case BPF_JMP32 | BPF_JSLE | BPF_X: -+ if (off == 0) -+ break; -+ setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); -+ emit_jmp_r(ctx, lo(dst), lo(src), rel, jmp); -+ if (finish_jmp(ctx, jmp, off) < 0) -+ goto toofar; -+ break; -+ /* PC += off if dst == imm */ -+ /* PC += off if dst != imm */ -+ /* PC += off if dst & imm */ -+ /* PC += off if dst > imm */ -+ /* PC += off if dst >= imm */ -+ /* PC += off if dst < imm */ -+ /* PC += off if dst <= imm */ -+ /* PC += off if dst > imm (signed) */ -+ /* PC += off if dst >= imm (signed) */ -+ /* PC += off if dst < imm (signed) */ -+ /* PC += off if dst <= imm (signed) */ -+ case BPF_JMP32 | BPF_JEQ | BPF_K: -+ case BPF_JMP32 | BPF_JNE | BPF_K: -+ case BPF_JMP32 | BPF_JSET | BPF_K: -+ case BPF_JMP32 | BPF_JGT | BPF_K: -+ case BPF_JMP32 | BPF_JGE | BPF_K: -+ case BPF_JMP32 | BPF_JLT | BPF_K: -+ case BPF_JMP32 | BPF_JLE | BPF_K: -+ case BPF_JMP32 | BPF_JSGT | BPF_K: -+ case BPF_JMP32 | BPF_JSGE | BPF_K: -+ case BPF_JMP32 | BPF_JSLT | BPF_K: -+ case BPF_JMP32 | BPF_JSLE | BPF_K: -+ if (off == 0) -+ break; -+ setup_jmp_i(ctx, imm, 32, BPF_OP(code), off, &jmp, &rel); -+ if (valid_jmp_i(jmp, imm)) { -+ emit_jmp_i(ctx, lo(dst), imm, rel, jmp); -+ } else { -+ /* Move large immediate to register */ -+ emit_mov_i(ctx, MIPS_R_T6, imm); -+ emit_jmp_r(ctx, lo(dst), MIPS_R_T6, rel, jmp); -+ } -+ if (finish_jmp(ctx, jmp, off) < 0) -+ goto toofar; -+ break; -+ /* PC += off if dst == src */ -+ /* PC += off if dst != src */ -+ /* PC += off if dst & src */ -+ /* PC += off if dst > src */ -+ /* PC += off if dst >= src */ -+ /* PC += off if dst < src */ -+ /* PC += off if dst <= src */ -+ /* PC += off if dst > src (signed) */ -+ /* PC += off if dst >= src (signed) */ -+ /* PC += off if dst < src (signed) */ -+ /* PC += off if dst <= src (signed) */ -+ case BPF_JMP | BPF_JEQ | BPF_X: -+ case BPF_JMP | BPF_JNE | BPF_X: -+ case BPF_JMP | BPF_JSET | BPF_X: -+ case BPF_JMP | BPF_JGT | BPF_X: -+ case BPF_JMP | BPF_JGE | BPF_X: -+ case BPF_JMP | BPF_JLT | BPF_X: -+ case BPF_JMP | BPF_JLE | BPF_X: -+ case BPF_JMP | BPF_JSGT | BPF_X: -+ case BPF_JMP | BPF_JSGE | BPF_X: -+ case BPF_JMP | BPF_JSLT | BPF_X: -+ case BPF_JMP | BPF_JSLE | BPF_X: -+ if (off == 0) -+ break; -+ setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); -+ emit_jmp_r64(ctx, dst, src, rel, jmp); -+ if (finish_jmp(ctx, jmp, off) < 0) -+ goto toofar; -+ break; -+ /* PC += off if dst == imm */ -+ /* PC += off if dst != imm */ -+ /* PC += off if dst & imm */ -+ /* PC += off if dst > imm */ -+ /* PC += off if dst >= imm */ -+ /* PC += off if dst < imm */ -+ /* PC += off if dst <= imm */ -+ /* PC += off if dst > imm (signed) */ -+ /* PC += off if dst >= imm (signed) */ -+ /* PC += off if dst < imm (signed) */ -+ /* PC += off if dst <= imm (signed) */ -+ case BPF_JMP | BPF_JEQ | BPF_K: -+ case BPF_JMP | BPF_JNE | BPF_K: -+ case BPF_JMP | BPF_JSET | BPF_K: -+ case BPF_JMP | BPF_JGT | BPF_K: -+ case BPF_JMP | BPF_JGE | BPF_K: -+ case BPF_JMP | BPF_JLT | BPF_K: -+ case BPF_JMP | BPF_JLE | BPF_K: -+ case BPF_JMP | BPF_JSGT | BPF_K: -+ case BPF_JMP | BPF_JSGE | BPF_K: -+ case BPF_JMP | BPF_JSLT | BPF_K: -+ case BPF_JMP | BPF_JSLE | BPF_K: -+ if (off == 0) -+ break; -+ setup_jmp_i(ctx, imm, 64, BPF_OP(code), off, &jmp, &rel); -+ emit_jmp_i64(ctx, dst, imm, rel, jmp); -+ if (finish_jmp(ctx, jmp, off) < 0) -+ goto toofar; -+ break; -+ /* PC += off */ -+ case BPF_JMP | BPF_JA: -+ if (off == 0) -+ break; -+ if (emit_ja(ctx, off) < 0) -+ goto toofar; -+ break; -+ /* Tail call */ -+ case BPF_JMP | BPF_TAIL_CALL: -+ if (emit_tail_call(ctx) < 0) -+ goto invalid; -+ break; -+ /* Function call */ -+ case BPF_JMP | BPF_CALL: -+ if (emit_call(ctx, insn) < 0) -+ goto invalid; -+ break; -+ /* Function return */ -+ case BPF_JMP | BPF_EXIT: -+ /* -+ * Optimization: when last instruction is EXIT -+ * simply continue to epilogue. -+ */ -+ if (ctx->bpf_index == ctx->program->len - 1) -+ break; -+ if (emit_exit(ctx) < 0) -+ goto toofar; -+ break; -+ -+ default: -+invalid: -+ pr_err_once("unknown opcode %02x\n", code); -+ return -EINVAL; -+notyet: -+ pr_info_once("*** NOT YET: opcode %02x ***\n", code); -+ return -EFAULT; -+toofar: -+ pr_info_once("*** TOO FAR: jump at %u opcode %02x ***\n", -+ ctx->bpf_index, code); -+ return -E2BIG; -+ } -+ return 0; -+} diff --git a/target/linux/generic/backport-5.10/050-v5.16-03-mips-bpf-Add-new-eBPF-JIT-for-64-bit-MIPS.patch b/target/linux/generic/backport-5.10/050-v5.16-03-mips-bpf-Add-new-eBPF-JIT-for-64-bit-MIPS.patch deleted file mode 100644 index 38b46c0b76..0000000000 --- a/target/linux/generic/backport-5.10/050-v5.16-03-mips-bpf-Add-new-eBPF-JIT-for-64-bit-MIPS.patch +++ /dev/null @@ -1,1005 +0,0 @@ -From: Johan Almbladh -Date: Tue, 5 Oct 2021 18:54:05 +0200 -Subject: [PATCH] mips: bpf: Add new eBPF JIT for 64-bit MIPS - -This is an implementation on of an eBPF JIT for 64-bit MIPS III-V and -MIPS64r1-r6. It uses the same framework introduced by the 32-bit JIT. - -Signed-off-by: Johan Almbladh ---- - create mode 100644 arch/mips/net/bpf_jit_comp64.c - ---- /dev/null -+++ b/arch/mips/net/bpf_jit_comp64.c -@@ -0,0 +1,991 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Just-In-Time compiler for eBPF bytecode on MIPS. -+ * Implementation of JIT functions for 64-bit CPUs. -+ * -+ * Copyright (c) 2021 Anyfi Networks AB. -+ * Author: Johan Almbladh -+ * -+ * Based on code and ideas from -+ * Copyright (c) 2017 Cavium, Inc. -+ * Copyright (c) 2017 Shubham Bansal -+ * Copyright (c) 2011 Mircea Gherzan -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "bpf_jit_comp.h" -+ -+/* MIPS t0-t3 are not available in the n64 ABI */ -+#undef MIPS_R_T0 -+#undef MIPS_R_T1 -+#undef MIPS_R_T2 -+#undef MIPS_R_T3 -+ -+/* Stack is 16-byte aligned in n64 ABI */ -+#define MIPS_STACK_ALIGNMENT 16 -+ -+/* Extra 64-bit eBPF registers used by JIT */ -+#define JIT_REG_TC (MAX_BPF_JIT_REG + 0) -+#define JIT_REG_ZX (MAX_BPF_JIT_REG + 1) -+ -+/* Number of prologue bytes to skip when doing a tail call */ -+#define JIT_TCALL_SKIP 4 -+ -+/* Callee-saved CPU registers that the JIT must preserve */ -+#define JIT_CALLEE_REGS \ -+ (BIT(MIPS_R_S0) | \ -+ BIT(MIPS_R_S1) | \ -+ BIT(MIPS_R_S2) | \ -+ BIT(MIPS_R_S3) | \ -+ BIT(MIPS_R_S4) | \ -+ BIT(MIPS_R_S5) | \ -+ BIT(MIPS_R_S6) | \ -+ BIT(MIPS_R_S7) | \ -+ BIT(MIPS_R_GP) | \ -+ BIT(MIPS_R_FP) | \ -+ BIT(MIPS_R_RA)) -+ -+/* Caller-saved CPU registers available for JIT use */ -+#define JIT_CALLER_REGS \ -+ (BIT(MIPS_R_A5) | \ -+ BIT(MIPS_R_A6) | \ -+ BIT(MIPS_R_A7)) -+/* -+ * Mapping of 64-bit eBPF registers to 64-bit native MIPS registers. -+ * MIPS registers t4 - t7 may be used by the JIT as temporary registers. -+ * MIPS registers t8 - t9 are reserved for single-register common functions. -+ */ -+static const u8 bpf2mips64[] = { -+ /* Return value from in-kernel function, and exit value from eBPF */ -+ [BPF_REG_0] = MIPS_R_V0, -+ /* Arguments from eBPF program to in-kernel function */ -+ [BPF_REG_1] = MIPS_R_A0, -+ [BPF_REG_2] = MIPS_R_A1, -+ [BPF_REG_3] = MIPS_R_A2, -+ [BPF_REG_4] = MIPS_R_A3, -+ [BPF_REG_5] = MIPS_R_A4, -+ /* Callee-saved registers that in-kernel function will preserve */ -+ [BPF_REG_6] = MIPS_R_S0, -+ [BPF_REG_7] = MIPS_R_S1, -+ [BPF_REG_8] = MIPS_R_S2, -+ [BPF_REG_9] = MIPS_R_S3, -+ /* Read-only frame pointer to access the eBPF stack */ -+ [BPF_REG_FP] = MIPS_R_FP, -+ /* Temporary register for blinding constants */ -+ [BPF_REG_AX] = MIPS_R_AT, -+ /* Tail call count register, caller-saved */ -+ [JIT_REG_TC] = MIPS_R_A5, -+ /* Constant for register zero-extension */ -+ [JIT_REG_ZX] = MIPS_R_V1, -+}; -+ -+/* -+ * MIPS 32-bit operations on 64-bit registers generate a sign-extended -+ * result. However, the eBPF ISA mandates zero-extension, so we rely on the -+ * verifier to add that for us (emit_zext_ver). In addition, ALU arithmetic -+ * operations, right shift and byte swap require properly sign-extended -+ * operands or the result is unpredictable. We emit explicit sign-extensions -+ * in those cases. -+ */ -+ -+/* Sign extension */ -+static void emit_sext(struct jit_context *ctx, u8 dst, u8 src) -+{ -+ emit(ctx, sll, dst, src, 0); -+ clobber_reg(ctx, dst); -+} -+ -+/* Zero extension */ -+static void emit_zext(struct jit_context *ctx, u8 dst) -+{ -+ if (cpu_has_mips64r2 || cpu_has_mips64r6) { -+ emit(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32); -+ } else { -+ emit(ctx, and, dst, dst, bpf2mips64[JIT_REG_ZX]); -+ access_reg(ctx, JIT_REG_ZX); /* We need the ZX register */ -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* Zero extension, if verifier does not do it for us */ -+static void emit_zext_ver(struct jit_context *ctx, u8 dst) -+{ -+ if (!ctx->program->aux->verifier_zext) -+ emit_zext(ctx, dst); -+} -+ -+/* dst = imm (64-bit) */ -+static void emit_mov_i64(struct jit_context *ctx, u8 dst, u64 imm64) -+{ -+ if (imm64 >= 0xffffffffffff8000ULL || imm64 < 0x8000ULL) { -+ emit(ctx, daddiu, dst, MIPS_R_ZERO, (s16)imm64); -+ } else if (imm64 >= 0xffffffff80000000ULL || -+ (imm64 < 0x80000000 && imm64 > 0xffff)) { -+ emit(ctx, lui, dst, (s16)(imm64 >> 16)); -+ emit(ctx, ori, dst, dst, (u16)imm64 & 0xffff); -+ } else { -+ u8 acc = MIPS_R_ZERO; -+ int k; -+ -+ for (k = 0; k < 4; k++) { -+ u16 half = imm64 >> (48 - 16 * k); -+ -+ if (acc == dst) -+ emit(ctx, dsll, dst, dst, 16); -+ -+ if (half) { -+ emit(ctx, ori, dst, acc, half); -+ acc = dst; -+ } -+ } -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* ALU immediate operation (64-bit) */ -+static void emit_alu_i64(struct jit_context *ctx, u8 dst, s32 imm, u8 op) -+{ -+ switch (BPF_OP(op)) { -+ /* dst = dst | imm */ -+ case BPF_OR: -+ emit(ctx, ori, dst, dst, (u16)imm); -+ break; -+ /* dst = dst ^ imm */ -+ case BPF_XOR: -+ emit(ctx, xori, dst, dst, (u16)imm); -+ break; -+ /* dst = -dst */ -+ case BPF_NEG: -+ emit(ctx, dsubu, dst, MIPS_R_ZERO, dst); -+ break; -+ /* dst = dst << imm */ -+ case BPF_LSH: -+ emit(ctx, dsll_safe, dst, dst, imm); -+ break; -+ /* dst = dst >> imm */ -+ case BPF_RSH: -+ emit(ctx, dsrl_safe, dst, dst, imm); -+ break; -+ /* dst = dst >> imm (arithmetic) */ -+ case BPF_ARSH: -+ emit(ctx, dsra_safe, dst, dst, imm); -+ break; -+ /* dst = dst + imm */ -+ case BPF_ADD: -+ emit(ctx, daddiu, dst, dst, imm); -+ break; -+ /* dst = dst - imm */ -+ case BPF_SUB: -+ emit(ctx, daddiu, dst, dst, -imm); -+ break; -+ default: -+ /* Width-generic operations */ -+ emit_alu_i(ctx, dst, imm, op); -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* ALU register operation (64-bit) */ -+static void emit_alu_r64(struct jit_context *ctx, u8 dst, u8 src, u8 op) -+{ -+ switch (BPF_OP(op)) { -+ /* dst = dst << src */ -+ case BPF_LSH: -+ emit(ctx, dsllv, dst, dst, src); -+ break; -+ /* dst = dst >> src */ -+ case BPF_RSH: -+ emit(ctx, dsrlv, dst, dst, src); -+ break; -+ /* dst = dst >> src (arithmetic) */ -+ case BPF_ARSH: -+ emit(ctx, dsrav, dst, dst, src); -+ break; -+ /* dst = dst + src */ -+ case BPF_ADD: -+ emit(ctx, daddu, dst, dst, src); -+ break; -+ /* dst = dst - src */ -+ case BPF_SUB: -+ emit(ctx, dsubu, dst, dst, src); -+ break; -+ /* dst = dst * src */ -+ case BPF_MUL: -+ if (cpu_has_mips64r6) { -+ emit(ctx, dmulu, dst, dst, src); -+ } else { -+ emit(ctx, dmultu, dst, src); -+ emit(ctx, mflo, dst); -+ } -+ break; -+ /* dst = dst / src */ -+ case BPF_DIV: -+ if (cpu_has_mips64r6) { -+ emit(ctx, ddivu_r6, dst, dst, src); -+ } else { -+ emit(ctx, ddivu, dst, src); -+ emit(ctx, mflo, dst); -+ } -+ break; -+ /* dst = dst % src */ -+ case BPF_MOD: -+ if (cpu_has_mips64r6) { -+ emit(ctx, dmodu, dst, dst, src); -+ } else { -+ emit(ctx, ddivu, dst, src); -+ emit(ctx, mfhi, dst); -+ } -+ break; -+ default: -+ /* Width-generic operations */ -+ emit_alu_r(ctx, dst, src, op); -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* Swap sub words in a register double word */ -+static void emit_swap_r64(struct jit_context *ctx, u8 dst, u8 mask, u32 bits) -+{ -+ u8 tmp = MIPS_R_T9; -+ -+ emit(ctx, and, tmp, dst, mask); /* tmp = dst & mask */ -+ emit(ctx, dsll, tmp, tmp, bits); /* tmp = tmp << bits */ -+ emit(ctx, dsrl, dst, dst, bits); /* dst = dst >> bits */ -+ emit(ctx, and, dst, dst, mask); /* dst = dst & mask */ -+ emit(ctx, or, dst, dst, tmp); /* dst = dst | tmp */ -+} -+ -+/* Swap bytes and truncate a register double word, word or half word */ -+static void emit_bswap_r64(struct jit_context *ctx, u8 dst, u32 width) -+{ -+ switch (width) { -+ /* Swap bytes in a double word */ -+ case 64: -+ if (cpu_has_mips64r2 || cpu_has_mips64r6) { -+ emit(ctx, dsbh, dst, dst); -+ emit(ctx, dshd, dst, dst); -+ } else { -+ u8 t1 = MIPS_R_T6; -+ u8 t2 = MIPS_R_T7; -+ -+ emit(ctx, dsll32, t2, dst, 0); /* t2 = dst << 32 */ -+ emit(ctx, dsrl32, dst, dst, 0); /* dst = dst >> 32 */ -+ emit(ctx, or, dst, dst, t2); /* dst = dst | t2 */ -+ -+ emit(ctx, ori, t2, MIPS_R_ZERO, 0xffff); -+ emit(ctx, dsll32, t1, t2, 0); /* t1 = t2 << 32 */ -+ emit(ctx, or, t1, t1, t2); /* t1 = t1 | t2 */ -+ emit_swap_r64(ctx, dst, t1, 16);/* dst = swap16(dst) */ -+ -+ emit(ctx, lui, t2, 0xff); /* t2 = 0x00ff0000 */ -+ emit(ctx, ori, t2, t2, 0xff); /* t2 = t2 | 0x00ff */ -+ emit(ctx, dsll32, t1, t2, 0); /* t1 = t2 << 32 */ -+ emit(ctx, or, t1, t1, t2); /* t1 = t1 | t2 */ -+ emit_swap_r64(ctx, dst, t1, 8); /* dst = swap8(dst) */ -+ } -+ break; -+ /* Swap bytes in a half word */ -+ /* Swap bytes in a word */ -+ case 32: -+ case 16: -+ emit_sext(ctx, dst, dst); -+ emit_bswap_r(ctx, dst, width); -+ if (cpu_has_mips64r2 || cpu_has_mips64r6) -+ emit_zext(ctx, dst); -+ break; -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* Truncate a register double word, word or half word */ -+static void emit_trunc_r64(struct jit_context *ctx, u8 dst, u32 width) -+{ -+ switch (width) { -+ case 64: -+ break; -+ /* Zero-extend a word */ -+ case 32: -+ emit_zext(ctx, dst); -+ break; -+ /* Zero-extend a half word */ -+ case 16: -+ emit(ctx, andi, dst, dst, 0xffff); -+ break; -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* Load operation: dst = *(size*)(src + off) */ -+static void emit_ldx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size) -+{ -+ switch (size) { -+ /* Load a byte */ -+ case BPF_B: -+ emit(ctx, lbu, dst, off, src); -+ break; -+ /* Load a half word */ -+ case BPF_H: -+ emit(ctx, lhu, dst, off, src); -+ break; -+ /* Load a word */ -+ case BPF_W: -+ emit(ctx, lwu, dst, off, src); -+ break; -+ /* Load a double word */ -+ case BPF_DW: -+ emit(ctx, ld, dst, off, src); -+ break; -+ } -+ clobber_reg(ctx, dst); -+} -+ -+/* Store operation: *(size *)(dst + off) = src */ -+static void emit_stx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size) -+{ -+ switch (size) { -+ /* Store a byte */ -+ case BPF_B: -+ emit(ctx, sb, src, off, dst); -+ break; -+ /* Store a half word */ -+ case BPF_H: -+ emit(ctx, sh, src, off, dst); -+ break; -+ /* Store a word */ -+ case BPF_W: -+ emit(ctx, sw, src, off, dst); -+ break; -+ /* Store a double word */ -+ case BPF_DW: -+ emit(ctx, sd, src, off, dst); -+ break; -+ } -+} -+ -+/* Atomic read-modify-write */ -+static void emit_atomic_r64(struct jit_context *ctx, -+ u8 dst, u8 src, s16 off, u8 code) -+{ -+ u8 t1 = MIPS_R_T6; -+ u8 t2 = MIPS_R_T7; -+ -+ emit(ctx, lld, t1, off, dst); -+ switch (code) { -+ case BPF_ADD: -+ emit(ctx, daddu, t2, t1, src); -+ break; -+ case BPF_AND: -+ emit(ctx, and, t2, t1, src); -+ break; -+ case BPF_OR: -+ emit(ctx, or, t2, t1, src); -+ break; -+ case BPF_XOR: -+ emit(ctx, xor, t2, t1, src); -+ break; -+ } -+ emit(ctx, scd, t2, off, dst); -+ emit(ctx, beqz, t2, -16); -+ emit(ctx, nop); /* Delay slot */ -+} -+ -+/* Function call */ -+static int emit_call(struct jit_context *ctx, const struct bpf_insn *insn) -+{ -+ u8 zx = bpf2mips64[JIT_REG_ZX]; -+ u8 tmp = MIPS_R_T6; -+ bool fixed; -+ u64 addr; -+ -+ /* Decode the call address */ -+ if (bpf_jit_get_func_addr(ctx->program, insn, false, -+ &addr, &fixed) < 0) -+ return -1; -+ if (!fixed) -+ return -1; -+ -+ /* Push caller-saved registers on stack */ -+ push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0); -+ -+ /* Emit function call */ -+ emit_mov_i64(ctx, tmp, addr); -+ emit(ctx, jalr, MIPS_R_RA, tmp); -+ emit(ctx, nop); /* Delay slot */ -+ -+ /* Restore caller-saved registers */ -+ pop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0); -+ -+ /* Re-initialize the JIT zero-extension register if accessed */ -+ if (ctx->accessed & BIT(JIT_REG_ZX)) { -+ emit(ctx, daddiu, zx, MIPS_R_ZERO, -1); -+ emit(ctx, dsrl32, zx, zx, 0); -+ } -+ -+ clobber_reg(ctx, MIPS_R_RA); -+ clobber_reg(ctx, MIPS_R_V0); -+ clobber_reg(ctx, MIPS_R_V1); -+ return 0; -+} -+ -+/* Function tail call */ -+static int emit_tail_call(struct jit_context *ctx) -+{ -+ u8 ary = bpf2mips64[BPF_REG_2]; -+ u8 ind = bpf2mips64[BPF_REG_3]; -+ u8 tcc = bpf2mips64[JIT_REG_TC]; -+ u8 tmp = MIPS_R_T6; -+ int off; -+ -+ /* -+ * Tail call: -+ * eBPF R1 - function argument (context ptr), passed in a0-a1 -+ * eBPF R2 - ptr to object with array of function entry points -+ * eBPF R3 - array index of function to be called -+ */ -+ -+ /* if (ind >= ary->map.max_entries) goto out */ -+ off = offsetof(struct bpf_array, map.max_entries); -+ if (off > 0x7fff) -+ return -1; -+ emit(ctx, lwu, tmp, off, ary); /* tmp = ary->map.max_entrs*/ -+ emit(ctx, sltu, tmp, ind, tmp); /* tmp = ind < t1 */ -+ emit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/ -+ -+ /* if (--TCC < 0) goto out */ -+ emit(ctx, daddiu, tcc, tcc, -1); /* tcc-- (delay slot) */ -+ emit(ctx, bltz, tcc, get_offset(ctx, 1)); /* PC += off(1) if tcc < 0 */ -+ /* (next insn delay slot) */ -+ /* prog = ary->ptrs[ind] */ -+ off = offsetof(struct bpf_array, ptrs); -+ if (off > 0x7fff) -+ return -1; -+ emit(ctx, dsll, tmp, ind, 3); /* tmp = ind << 3 */ -+ emit(ctx, daddu, tmp, tmp, ary); /* tmp += ary */ -+ emit(ctx, ld, tmp, off, tmp); /* tmp = *(tmp + off) */ -+ -+ /* if (prog == 0) goto out */ -+ emit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/ -+ emit(ctx, nop); /* Delay slot */ -+ -+ /* func = prog->bpf_func + 8 (prologue skip offset) */ -+ off = offsetof(struct bpf_prog, bpf_func); -+ if (off > 0x7fff) -+ return -1; -+ emit(ctx, ld, tmp, off, tmp); /* tmp = *(tmp + off) */ -+ emit(ctx, daddiu, tmp, tmp, JIT_TCALL_SKIP); /* tmp += skip (4) */ -+ -+ /* goto func */ -+ build_epilogue(ctx, tmp); -+ access_reg(ctx, JIT_REG_TC); -+ return 0; -+} -+ -+/* -+ * Stack frame layout for a JITed program (stack grows down). -+ * -+ * Higher address : Previous stack frame : -+ * +===========================+ <--- MIPS sp before call -+ * | Callee-saved registers, | -+ * | including RA and FP | -+ * +---------------------------+ <--- eBPF FP (MIPS fp) -+ * | Local eBPF variables | -+ * | allocated by program | -+ * +---------------------------+ -+ * | Reserved for caller-saved | -+ * | registers | -+ * Lower address +===========================+ <--- MIPS sp -+ */ -+ -+/* Build program prologue to set up the stack and registers */ -+void build_prologue(struct jit_context *ctx) -+{ -+ u8 fp = bpf2mips64[BPF_REG_FP]; -+ u8 tc = bpf2mips64[JIT_REG_TC]; -+ u8 zx = bpf2mips64[JIT_REG_ZX]; -+ int stack, saved, locals, reserved; -+ -+ /* -+ * The first instruction initializes the tail call count register. -+ * On a tail call, the calling function jumps into the prologue -+ * after this instruction. -+ */ -+ emit(ctx, addiu, tc, MIPS_R_ZERO, min(MAX_TAIL_CALL_CNT + 1, 0xffff)); -+ -+ /* === Entry-point for tail calls === */ -+ -+ /* -+ * If the eBPF frame pointer and tail call count registers were -+ * accessed they must be preserved. Mark them as clobbered here -+ * to save and restore them on the stack as needed. -+ */ -+ if (ctx->accessed & BIT(BPF_REG_FP)) -+ clobber_reg(ctx, fp); -+ if (ctx->accessed & BIT(JIT_REG_TC)) -+ clobber_reg(ctx, tc); -+ if (ctx->accessed & BIT(JIT_REG_ZX)) -+ clobber_reg(ctx, zx); -+ -+ /* Compute the stack space needed for callee-saved registers */ -+ saved = hweight32(ctx->clobbered & JIT_CALLEE_REGS) * sizeof(u64); -+ saved = ALIGN(saved, MIPS_STACK_ALIGNMENT); -+ -+ /* Stack space used by eBPF program local data */ -+ locals = ALIGN(ctx->program->aux->stack_depth, MIPS_STACK_ALIGNMENT); -+ -+ /* -+ * If we are emitting function calls, reserve extra stack space for -+ * caller-saved registers needed by the JIT. The required space is -+ * computed automatically during resource usage discovery (pass 1). -+ */ -+ reserved = ctx->stack_used; -+ -+ /* Allocate the stack frame */ -+ stack = ALIGN(saved + locals + reserved, MIPS_STACK_ALIGNMENT); -+ if (stack) -+ emit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, -stack); -+ -+ /* Store callee-saved registers on stack */ -+ push_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, stack - saved); -+ -+ /* Initialize the eBPF frame pointer if accessed */ -+ if (ctx->accessed & BIT(BPF_REG_FP)) -+ emit(ctx, daddiu, fp, MIPS_R_SP, stack - saved); -+ -+ /* Initialize the ePF JIT zero-extension register if accessed */ -+ if (ctx->accessed & BIT(JIT_REG_ZX)) { -+ emit(ctx, daddiu, zx, MIPS_R_ZERO, -1); -+ emit(ctx, dsrl32, zx, zx, 0); -+ } -+ -+ ctx->saved_size = saved; -+ ctx->stack_size = stack; -+} -+ -+/* Build the program epilogue to restore the stack and registers */ -+void build_epilogue(struct jit_context *ctx, int dest_reg) -+{ -+ /* Restore callee-saved registers from stack */ -+ pop_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, -+ ctx->stack_size - ctx->saved_size); -+ -+ /* Release the stack frame */ -+ if (ctx->stack_size) -+ emit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, ctx->stack_size); -+ -+ /* Jump to return address and sign-extend the 32-bit return value */ -+ emit(ctx, jr, dest_reg); -+ emit(ctx, sll, MIPS_R_V0, MIPS_R_V0, 0); /* Delay slot */ -+} -+ -+/* Build one eBPF instruction */ -+int build_insn(const struct bpf_insn *insn, struct jit_context *ctx) -+{ -+ u8 dst = bpf2mips64[insn->dst_reg]; -+ u8 src = bpf2mips64[insn->src_reg]; -+ u8 code = insn->code; -+ s16 off = insn->off; -+ s32 imm = insn->imm; -+ s32 val, rel; -+ u8 alu, jmp; -+ -+ switch (code) { -+ /* ALU operations */ -+ /* dst = imm */ -+ case BPF_ALU | BPF_MOV | BPF_K: -+ emit_mov_i(ctx, dst, imm); -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = src */ -+ case BPF_ALU | BPF_MOV | BPF_X: -+ if (imm == 1) { -+ /* Special mov32 for zext */ -+ emit_zext(ctx, dst); -+ } else { -+ emit_mov_r(ctx, dst, src); -+ emit_zext_ver(ctx, dst); -+ } -+ break; -+ /* dst = -dst */ -+ case BPF_ALU | BPF_NEG: -+ emit_sext(ctx, dst, dst); -+ emit_alu_i(ctx, dst, 0, BPF_NEG); -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = dst & imm */ -+ /* dst = dst | imm */ -+ /* dst = dst ^ imm */ -+ /* dst = dst << imm */ -+ case BPF_ALU | BPF_OR | BPF_K: -+ case BPF_ALU | BPF_AND | BPF_K: -+ case BPF_ALU | BPF_XOR | BPF_K: -+ case BPF_ALU | BPF_LSH | BPF_K: -+ if (!valid_alu_i(BPF_OP(code), imm)) { -+ emit_mov_i(ctx, MIPS_R_T4, imm); -+ emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); -+ } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { -+ emit_alu_i(ctx, dst, val, alu); -+ } -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = dst >> imm */ -+ /* dst = dst >> imm (arithmetic) */ -+ /* dst = dst + imm */ -+ /* dst = dst - imm */ -+ /* dst = dst * imm */ -+ /* dst = dst / imm */ -+ /* dst = dst % imm */ -+ case BPF_ALU | BPF_RSH | BPF_K: -+ case BPF_ALU | BPF_ARSH | BPF_K: -+ case BPF_ALU | BPF_ADD | BPF_K: -+ case BPF_ALU | BPF_SUB | BPF_K: -+ case BPF_ALU | BPF_MUL | BPF_K: -+ case BPF_ALU | BPF_DIV | BPF_K: -+ case BPF_ALU | BPF_MOD | BPF_K: -+ if (!valid_alu_i(BPF_OP(code), imm)) { -+ emit_sext(ctx, dst, dst); -+ emit_mov_i(ctx, MIPS_R_T4, imm); -+ emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); -+ } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { -+ emit_sext(ctx, dst, dst); -+ emit_alu_i(ctx, dst, val, alu); -+ } -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = dst & src */ -+ /* dst = dst | src */ -+ /* dst = dst ^ src */ -+ /* dst = dst << src */ -+ case BPF_ALU | BPF_AND | BPF_X: -+ case BPF_ALU | BPF_OR | BPF_X: -+ case BPF_ALU | BPF_XOR | BPF_X: -+ case BPF_ALU | BPF_LSH | BPF_X: -+ emit_alu_r(ctx, dst, src, BPF_OP(code)); -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = dst >> src */ -+ /* dst = dst >> src (arithmetic) */ -+ /* dst = dst + src */ -+ /* dst = dst - src */ -+ /* dst = dst * src */ -+ /* dst = dst / src */ -+ /* dst = dst % src */ -+ case BPF_ALU | BPF_RSH | BPF_X: -+ case BPF_ALU | BPF_ARSH | BPF_X: -+ case BPF_ALU | BPF_ADD | BPF_X: -+ case BPF_ALU | BPF_SUB | BPF_X: -+ case BPF_ALU | BPF_MUL | BPF_X: -+ case BPF_ALU | BPF_DIV | BPF_X: -+ case BPF_ALU | BPF_MOD | BPF_X: -+ emit_sext(ctx, dst, dst); -+ emit_sext(ctx, MIPS_R_T4, src); -+ emit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code)); -+ emit_zext_ver(ctx, dst); -+ break; -+ /* dst = imm (64-bit) */ -+ case BPF_ALU64 | BPF_MOV | BPF_K: -+ emit_mov_i(ctx, dst, imm); -+ break; -+ /* dst = src (64-bit) */ -+ case BPF_ALU64 | BPF_MOV | BPF_X: -+ emit_mov_r(ctx, dst, src); -+ break; -+ /* dst = -dst (64-bit) */ -+ case BPF_ALU64 | BPF_NEG: -+ emit_alu_i64(ctx, dst, 0, BPF_NEG); -+ break; -+ /* dst = dst & imm (64-bit) */ -+ /* dst = dst | imm (64-bit) */ -+ /* dst = dst ^ imm (64-bit) */ -+ /* dst = dst << imm (64-bit) */ -+ /* dst = dst >> imm (64-bit) */ -+ /* dst = dst >> imm ((64-bit, arithmetic) */ -+ /* dst = dst + imm (64-bit) */ -+ /* dst = dst - imm (64-bit) */ -+ /* dst = dst * imm (64-bit) */ -+ /* dst = dst / imm (64-bit) */ -+ /* dst = dst % imm (64-bit) */ -+ case BPF_ALU64 | BPF_AND | BPF_K: -+ case BPF_ALU64 | BPF_OR | BPF_K: -+ case BPF_ALU64 | BPF_XOR | BPF_K: -+ case BPF_ALU64 | BPF_LSH | BPF_K: -+ case BPF_ALU64 | BPF_RSH | BPF_K: -+ case BPF_ALU64 | BPF_ARSH | BPF_K: -+ case BPF_ALU64 | BPF_ADD | BPF_K: -+ case BPF_ALU64 | BPF_SUB | BPF_K: -+ case BPF_ALU64 | BPF_MUL | BPF_K: -+ case BPF_ALU64 | BPF_DIV | BPF_K: -+ case BPF_ALU64 | BPF_MOD | BPF_K: -+ if (!valid_alu_i(BPF_OP(code), imm)) { -+ emit_mov_i(ctx, MIPS_R_T4, imm); -+ emit_alu_r64(ctx, dst, MIPS_R_T4, BPF_OP(code)); -+ } else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) { -+ emit_alu_i64(ctx, dst, val, alu); -+ } -+ break; -+ /* dst = dst & src (64-bit) */ -+ /* dst = dst | src (64-bit) */ -+ /* dst = dst ^ src (64-bit) */ -+ /* dst = dst << src (64-bit) */ -+ /* dst = dst >> src (64-bit) */ -+ /* dst = dst >> src (64-bit, arithmetic) */ -+ /* dst = dst + src (64-bit) */ -+ /* dst = dst - src (64-bit) */ -+ /* dst = dst * src (64-bit) */ -+ /* dst = dst / src (64-bit) */ -+ /* dst = dst % src (64-bit) */ -+ case BPF_ALU64 | BPF_AND | BPF_X: -+ case BPF_ALU64 | BPF_OR | BPF_X: -+ case BPF_ALU64 | BPF_XOR | BPF_X: -+ case BPF_ALU64 | BPF_LSH | BPF_X: -+ case BPF_ALU64 | BPF_RSH | BPF_X: -+ case BPF_ALU64 | BPF_ARSH | BPF_X: -+ case BPF_ALU64 | BPF_ADD | BPF_X: -+ case BPF_ALU64 | BPF_SUB | BPF_X: -+ case BPF_ALU64 | BPF_MUL | BPF_X: -+ case BPF_ALU64 | BPF_DIV | BPF_X: -+ case BPF_ALU64 | BPF_MOD | BPF_X: -+ emit_alu_r64(ctx, dst, src, BPF_OP(code)); -+ break; -+ /* dst = htole(dst) */ -+ /* dst = htobe(dst) */ -+ case BPF_ALU | BPF_END | BPF_FROM_LE: -+ case BPF_ALU | BPF_END | BPF_FROM_BE: -+ if (BPF_SRC(code) == -+#ifdef __BIG_ENDIAN -+ BPF_FROM_LE -+#else -+ BPF_FROM_BE -+#endif -+ ) -+ emit_bswap_r64(ctx, dst, imm); -+ else -+ emit_trunc_r64(ctx, dst, imm); -+ break; -+ /* dst = imm64 */ -+ case BPF_LD | BPF_IMM | BPF_DW: -+ emit_mov_i64(ctx, dst, (u32)imm | ((u64)insn[1].imm << 32)); -+ return 1; -+ /* LDX: dst = *(size *)(src + off) */ -+ case BPF_LDX | BPF_MEM | BPF_W: -+ case BPF_LDX | BPF_MEM | BPF_H: -+ case BPF_LDX | BPF_MEM | BPF_B: -+ case BPF_LDX | BPF_MEM | BPF_DW: -+ emit_ldx(ctx, dst, src, off, BPF_SIZE(code)); -+ break; -+ /* ST: *(size *)(dst + off) = imm */ -+ case BPF_ST | BPF_MEM | BPF_W: -+ case BPF_ST | BPF_MEM | BPF_H: -+ case BPF_ST | BPF_MEM | BPF_B: -+ case BPF_ST | BPF_MEM | BPF_DW: -+ emit_mov_i(ctx, MIPS_R_T4, imm); -+ emit_stx(ctx, dst, MIPS_R_T4, off, BPF_SIZE(code)); -+ break; -+ /* STX: *(size *)(dst + off) = src */ -+ case BPF_STX | BPF_MEM | BPF_W: -+ case BPF_STX | BPF_MEM | BPF_H: -+ case BPF_STX | BPF_MEM | BPF_B: -+ case BPF_STX | BPF_MEM | BPF_DW: -+ emit_stx(ctx, dst, src, off, BPF_SIZE(code)); -+ break; -+ /* Speculation barrier */ -+ case BPF_ST | BPF_NOSPEC: -+ break; -+ /* Atomics */ -+ case BPF_STX | BPF_XADD | BPF_W: -+ case BPF_STX | BPF_XADD | BPF_DW: -+ switch (imm) { -+ case BPF_ADD: -+ case BPF_AND: -+ case BPF_OR: -+ case BPF_XOR: -+ if (BPF_SIZE(code) == BPF_DW) { -+ emit_atomic_r64(ctx, dst, src, off, imm); -+ } else { /* 32-bit, no fetch */ -+ emit_sext(ctx, MIPS_R_T4, src); -+ emit_atomic_r(ctx, dst, MIPS_R_T4, off, imm); -+ } -+ break; -+ default: -+ goto notyet; -+ } -+ break; -+ /* PC += off if dst == src */ -+ /* PC += off if dst != src */ -+ /* PC += off if dst & src */ -+ /* PC += off if dst > src */ -+ /* PC += off if dst >= src */ -+ /* PC += off if dst < src */ -+ /* PC += off if dst <= src */ -+ /* PC += off if dst > src (signed) */ -+ /* PC += off if dst >= src (signed) */ -+ /* PC += off if dst < src (signed) */ -+ /* PC += off if dst <= src (signed) */ -+ case BPF_JMP32 | BPF_JEQ | BPF_X: -+ case BPF_JMP32 | BPF_JNE | BPF_X: -+ case BPF_JMP32 | BPF_JSET | BPF_X: -+ case BPF_JMP32 | BPF_JGT | BPF_X: -+ case BPF_JMP32 | BPF_JGE | BPF_X: -+ case BPF_JMP32 | BPF_JLT | BPF_X: -+ case BPF_JMP32 | BPF_JLE | BPF_X: -+ case BPF_JMP32 | BPF_JSGT | BPF_X: -+ case BPF_JMP32 | BPF_JSGE | BPF_X: -+ case BPF_JMP32 | BPF_JSLT | BPF_X: -+ case BPF_JMP32 | BPF_JSLE | BPF_X: -+ if (off == 0) -+ break; -+ setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); -+ emit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */ -+ emit_sext(ctx, MIPS_R_T5, src); /* Sign-extended src */ -+ emit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp); -+ if (finish_jmp(ctx, jmp, off) < 0) -+ goto toofar; -+ break; -+ /* PC += off if dst == imm */ -+ /* PC += off if dst != imm */ -+ /* PC += off if dst & imm */ -+ /* PC += off if dst > imm */ -+ /* PC += off if dst >= imm */ -+ /* PC += off if dst < imm */ -+ /* PC += off if dst <= imm */ -+ /* PC += off if dst > imm (signed) */ -+ /* PC += off if dst >= imm (signed) */ -+ /* PC += off if dst < imm (signed) */ -+ /* PC += off if dst <= imm (signed) */ -+ case BPF_JMP32 | BPF_JEQ | BPF_K: -+ case BPF_JMP32 | BPF_JNE | BPF_K: -+ case BPF_JMP32 | BPF_JSET | BPF_K: -+ case BPF_JMP32 | BPF_JGT | BPF_K: -+ case BPF_JMP32 | BPF_JGE | BPF_K: -+ case BPF_JMP32 | BPF_JLT | BPF_K: -+ case BPF_JMP32 | BPF_JLE | BPF_K: -+ case BPF_JMP32 | BPF_JSGT | BPF_K: -+ case BPF_JMP32 | BPF_JSGE | BPF_K: -+ case BPF_JMP32 | BPF_JSLT | BPF_K: -+ case BPF_JMP32 | BPF_JSLE | BPF_K: -+ if (off == 0) -+ break; -+ setup_jmp_i(ctx, imm, 32, BPF_OP(code), off, &jmp, &rel); -+ emit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */ -+ if (valid_jmp_i(jmp, imm)) { -+ emit_jmp_i(ctx, MIPS_R_T4, imm, rel, jmp); -+ } else { -+ /* Move large immediate to register, sign-extended */ -+ emit_mov_i(ctx, MIPS_R_T5, imm); -+ emit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp); -+ } -+ if (finish_jmp(ctx, jmp, off) < 0) -+ goto toofar; -+ break; -+ /* PC += off if dst == src */ -+ /* PC += off if dst != src */ -+ /* PC += off if dst & src */ -+ /* PC += off if dst > src */ -+ /* PC += off if dst >= src */ -+ /* PC += off if dst < src */ -+ /* PC += off if dst <= src */ -+ /* PC += off if dst > src (signed) */ -+ /* PC += off if dst >= src (signed) */ -+ /* PC += off if dst < src (signed) */ -+ /* PC += off if dst <= src (signed) */ -+ case BPF_JMP | BPF_JEQ | BPF_X: -+ case BPF_JMP | BPF_JNE | BPF_X: -+ case BPF_JMP | BPF_JSET | BPF_X: -+ case BPF_JMP | BPF_JGT | BPF_X: -+ case BPF_JMP | BPF_JGE | BPF_X: -+ case BPF_JMP | BPF_JLT | BPF_X: -+ case BPF_JMP | BPF_JLE | BPF_X: -+ case BPF_JMP | BPF_JSGT | BPF_X: -+ case BPF_JMP | BPF_JSGE | BPF_X: -+ case BPF_JMP | BPF_JSLT | BPF_X: -+ case BPF_JMP | BPF_JSLE | BPF_X: -+ if (off == 0) -+ break; -+ setup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel); -+ emit_jmp_r(ctx, dst, src, rel, jmp); -+ if (finish_jmp(ctx, jmp, off) < 0) -+ goto toofar; -+ break; -+ /* PC += off if dst == imm */ -+ /* PC += off if dst != imm */ -+ /* PC += off if dst & imm */ -+ /* PC += off if dst > imm */ -+ /* PC += off if dst >= imm */ -+ /* PC += off if dst < imm */ -+ /* PC += off if dst <= imm */ -+ /* PC += off if dst > imm (signed) */ -+ /* PC += off if dst >= imm (signed) */ -+ /* PC += off if dst < imm (signed) */ -+ /* PC += off if dst <= imm (signed) */ -+ case BPF_JMP | BPF_JEQ | BPF_K: -+ case BPF_JMP | BPF_JNE | BPF_K: -+ case BPF_JMP | BPF_JSET | BPF_K: -+ case BPF_JMP | BPF_JGT | BPF_K: -+ case BPF_JMP | BPF_JGE | BPF_K: -+ case BPF_JMP | BPF_JLT | BPF_K: -+ case BPF_JMP | BPF_JLE | BPF_K: -+ case BPF_JMP | BPF_JSGT | BPF_K: -+ case BPF_JMP | BPF_JSGE | BPF_K: -+ case BPF_JMP | BPF_JSLT | BPF_K: -+ case BPF_JMP | BPF_JSLE | BPF_K: -+ if (off == 0) -+ break; -+ setup_jmp_i(ctx, imm, 64, BPF_OP(code), off, &jmp, &rel); -+ if (valid_jmp_i(jmp, imm)) { -+ emit_jmp_i(ctx, dst, imm, rel, jmp); -+ } else { -+ /* Move large immediate to register */ -+ emit_mov_i(ctx, MIPS_R_T4, imm); -+ emit_jmp_r(ctx, dst, MIPS_R_T4, rel, jmp); -+ } -+ if (finish_jmp(ctx, jmp, off) < 0) -+ goto toofar; -+ break; -+ /* PC += off */ -+ case BPF_JMP | BPF_JA: -+ if (off == 0) -+ break; -+ if (emit_ja(ctx, off) < 0) -+ goto toofar; -+ break; -+ /* Tail call */ -+ case BPF_JMP | BPF_TAIL_CALL: -+ if (emit_tail_call(ctx) < 0) -+ goto invalid; -+ break; -+ /* Function call */ -+ case BPF_JMP | BPF_CALL: -+ if (emit_call(ctx, insn) < 0) -+ goto invalid; -+ break; -+ /* Function return */ -+ case BPF_JMP | BPF_EXIT: -+ /* -+ * Optimization: when last instruction is EXIT -+ * simply continue to epilogue. -+ */ -+ if (ctx->bpf_index == ctx->program->len - 1) -+ break; -+ if (emit_exit(ctx) < 0) -+ goto toofar; -+ break; -+ -+ default: -+invalid: -+ pr_err_once("unknown opcode %02x\n", code); -+ return -EINVAL; -+notyet: -+ pr_info_once("*** NOT YET: opcode %02x ***\n", code); -+ return -EFAULT; -+toofar: -+ pr_info_once("*** TOO FAR: jump at %u opcode %02x ***\n", -+ ctx->bpf_index, code); -+ return -E2BIG; -+ } -+ return 0; -+} diff --git a/target/linux/generic/backport-5.10/050-v5.16-04-mips-bpf-Add-JIT-workarounds-for-CPU-errata.patch b/target/linux/generic/backport-5.10/050-v5.16-04-mips-bpf-Add-JIT-workarounds-for-CPU-errata.patch deleted file mode 100644 index 63553ebe58..0000000000 --- a/target/linux/generic/backport-5.10/050-v5.16-04-mips-bpf-Add-JIT-workarounds-for-CPU-errata.patch +++ /dev/null @@ -1,120 +0,0 @@ -From: Johan Almbladh -Date: Tue, 5 Oct 2021 18:54:06 +0200 -Subject: [PATCH] mips: bpf: Add JIT workarounds for CPU errata - -This patch adds workarounds for the following CPU errata to the MIPS -eBPF JIT, if enabled in the kernel configuration. - - - R10000 ll/sc weak ordering - - Loongson-3 ll/sc weak ordering - - Loongson-2F jump hang - -The Loongson-2F nop errata is implemented in uasm, which the JIT uses, -so no additional mitigations are needed for that. - -Signed-off-by: Johan Almbladh -Reviewed-by: Jiaxun Yang ---- - ---- a/arch/mips/net/bpf_jit_comp.c -+++ b/arch/mips/net/bpf_jit_comp.c -@@ -404,6 +404,7 @@ void emit_alu_r(struct jit_context *ctx, - /* Atomic read-modify-write (32-bit) */ - void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code) - { -+ LLSC_sync(ctx); - emit(ctx, ll, MIPS_R_T9, off, dst); - switch (code) { - case BPF_ADD: -@@ -420,18 +421,19 @@ void emit_atomic_r(struct jit_context *c - break; - } - emit(ctx, sc, MIPS_R_T8, off, dst); -- emit(ctx, beqz, MIPS_R_T8, -16); -+ emit(ctx, LLSC_beqz, MIPS_R_T8, -16 - LLSC_offset); - emit(ctx, nop); /* Delay slot */ - } - - /* Atomic compare-and-exchange (32-bit) */ - void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off) - { -+ LLSC_sync(ctx); - emit(ctx, ll, MIPS_R_T9, off, dst); - emit(ctx, bne, MIPS_R_T9, res, 12); - emit(ctx, move, MIPS_R_T8, src); /* Delay slot */ - emit(ctx, sc, MIPS_R_T8, off, dst); -- emit(ctx, beqz, MIPS_R_T8, -20); -+ emit(ctx, LLSC_beqz, MIPS_R_T8, -20 - LLSC_offset); - emit(ctx, move, res, MIPS_R_T9); /* Delay slot */ - clobber_reg(ctx, res); - } ---- a/arch/mips/net/bpf_jit_comp.h -+++ b/arch/mips/net/bpf_jit_comp.h -@@ -87,7 +87,7 @@ struct jit_context { - }; - - /* Emit the instruction if the JIT memory space has been allocated */ --#define emit(ctx, func, ...) \ -+#define __emit(ctx, func, ...) \ - do { \ - if ((ctx)->target != NULL) { \ - u32 *p = &(ctx)->target[ctx->jit_index]; \ -@@ -95,6 +95,30 @@ do { \ - } \ - (ctx)->jit_index++; \ - } while (0) -+#define emit(...) __emit(__VA_ARGS__) -+ -+/* Workaround for R10000 ll/sc errata */ -+#ifdef CONFIG_WAR_R10000 -+#define LLSC_beqz beqzl -+#else -+#define LLSC_beqz beqz -+#endif -+ -+/* Workaround for Loongson-3 ll/sc errata */ -+#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS -+#define LLSC_sync(ctx) emit(ctx, sync, 0) -+#define LLSC_offset 4 -+#else -+#define LLSC_sync(ctx) -+#define LLSC_offset 0 -+#endif -+ -+/* Workaround for Loongson-2F jump errata */ -+#ifdef CONFIG_CPU_JUMP_WORKAROUNDS -+#define JALR_MASK 0xffffffffcfffffffULL -+#else -+#define JALR_MASK (~0ULL) -+#endif - - /* - * Mark a BPF register as accessed, it needs to be ---- a/arch/mips/net/bpf_jit_comp64.c -+++ b/arch/mips/net/bpf_jit_comp64.c -@@ -375,6 +375,7 @@ static void emit_atomic_r64(struct jit_c - u8 t1 = MIPS_R_T6; - u8 t2 = MIPS_R_T7; - -+ LLSC_sync(ctx); - emit(ctx, lld, t1, off, dst); - switch (code) { - case BPF_ADD: -@@ -391,7 +392,7 @@ static void emit_atomic_r64(struct jit_c - break; - } - emit(ctx, scd, t2, off, dst); -- emit(ctx, beqz, t2, -16); -+ emit(ctx, LLSC_beqz, t2, -16 - LLSC_offset); - emit(ctx, nop); /* Delay slot */ - } - -@@ -414,7 +415,7 @@ static int emit_call(struct jit_context - push_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0); - - /* Emit function call */ -- emit_mov_i64(ctx, tmp, addr); -+ emit_mov_i64(ctx, tmp, addr & JALR_MASK); - emit(ctx, jalr, MIPS_R_RA, tmp); - emit(ctx, nop); /* Delay slot */ - diff --git a/target/linux/generic/backport-5.10/050-v5.16-05-mips-bpf-Enable-eBPF-JITs.patch b/target/linux/generic/backport-5.10/050-v5.16-05-mips-bpf-Enable-eBPF-JITs.patch deleted file mode 100644 index 10685c5f3c..0000000000 --- a/target/linux/generic/backport-5.10/050-v5.16-05-mips-bpf-Enable-eBPF-JITs.patch +++ /dev/null @@ -1,61 +0,0 @@ -From: Johan Almbladh -Date: Tue, 5 Oct 2021 18:54:07 +0200 -Subject: [PATCH] mips: bpf: Enable eBPF JITs - -This patch enables the new eBPF JITs for 32-bit and 64-bit MIPS. It also -disables the old cBPF JIT to so cBPF programs are converted to use the -new JIT. - -Workarounds for R4000 CPU errata are not implemented by the JIT, so the -JIT is disabled if any of those workarounds are configured. - -Signed-off-by: Johan Almbladh ---- - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -3294,6 +3294,7 @@ S: Supported - F: arch/arm64/net/ - - BPF JIT for MIPS (32-BIT AND 64-BIT) -+M: Johan Almbladh - M: Paul Burton - L: netdev@vger.kernel.org - L: bpf@vger.kernel.org ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -49,7 +49,6 @@ config MIPS - select HAVE_ARCH_TRACEHOOK - select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES - select HAVE_ASM_MODVERSIONS -- select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS - select HAVE_CONTEXT_TRACKING - select HAVE_TIF_NOHZ - select HAVE_C_RECORDMCOUNT -@@ -57,7 +56,10 @@ config MIPS - select HAVE_DEBUG_STACKOVERFLOW - select HAVE_DMA_CONTIGUOUS - select HAVE_DYNAMIC_FTRACE -- select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2 -+ select HAVE_EBPF_JIT if !CPU_MICROMIPS && \ -+ !CPU_DADDI_WORKAROUNDS && \ -+ !CPU_R4000_WORKAROUNDS && \ -+ !CPU_R4400_WORKAROUNDS - select HAVE_EXIT_THREAD - select HAVE_FAST_GUP - select HAVE_FTRACE_MCOUNT_RECORD ---- a/arch/mips/net/Makefile -+++ b/arch/mips/net/Makefile -@@ -2,9 +2,10 @@ - # MIPS networking code - - obj-$(CONFIG_MIPS_CBPF_JIT) += bpf_jit.o bpf_jit_asm.o -+obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp.o - - ifeq ($(CONFIG_32BIT),y) -- obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp.o bpf_jit_comp32.o -+ obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp32.o - else -- obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o -+ obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp64.o - endif diff --git a/target/linux/generic/backport-5.10/050-v5.16-06-mips-bpf-Remove-old-BPF-JIT-implementations.patch b/target/linux/generic/backport-5.10/050-v5.16-06-mips-bpf-Remove-old-BPF-JIT-implementations.patch deleted file mode 100644 index e25c336831..0000000000 --- a/target/linux/generic/backport-5.10/050-v5.16-06-mips-bpf-Remove-old-BPF-JIT-implementations.patch +++ /dev/null @@ -1,387 +0,0 @@ -From: Johan Almbladh -Date: Tue, 5 Oct 2021 18:54:08 +0200 -Subject: [PATCH] mips: bpf: Remove old BPF JIT implementations - -This patch removes the old 32-bit cBPF and 64-bit eBPF JIT implementations. -They are replaced by a new eBPF implementation that supports both 32-bit -and 64-bit MIPS CPUs. - -Signed-off-by: Johan Almbladh ---- - delete mode 100644 arch/mips/net/bpf_jit.c - delete mode 100644 arch/mips/net/bpf_jit.h - delete mode 100644 arch/mips/net/bpf_jit_asm.S - delete mode 100644 arch/mips/net/ebpf_jit.c - ---- a/arch/mips/net/bpf_jit.h -+++ /dev/null -@@ -1,81 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ --/* -- * Just-In-Time compiler for BPF filters on MIPS -- * -- * Copyright (c) 2014 Imagination Technologies Ltd. -- * Author: Markos Chandras -- */ -- --#ifndef BPF_JIT_MIPS_OP_H --#define BPF_JIT_MIPS_OP_H -- --/* Registers used by JIT */ --#define MIPS_R_ZERO 0 --#define MIPS_R_V0 2 --#define MIPS_R_A0 4 --#define MIPS_R_A1 5 --#define MIPS_R_T4 12 --#define MIPS_R_T5 13 --#define MIPS_R_T6 14 --#define MIPS_R_T7 15 --#define MIPS_R_S0 16 --#define MIPS_R_S1 17 --#define MIPS_R_S2 18 --#define MIPS_R_S3 19 --#define MIPS_R_S4 20 --#define MIPS_R_S5 21 --#define MIPS_R_S6 22 --#define MIPS_R_S7 23 --#define MIPS_R_SP 29 --#define MIPS_R_RA 31 -- --/* Conditional codes */ --#define MIPS_COND_EQ 0x1 --#define MIPS_COND_GE (0x1 << 1) --#define MIPS_COND_GT (0x1 << 2) --#define MIPS_COND_NE (0x1 << 3) --#define MIPS_COND_ALL (0x1 << 4) --/* Conditionals on X register or K immediate */ --#define MIPS_COND_X (0x1 << 5) --#define MIPS_COND_K (0x1 << 6) -- --#define r_ret MIPS_R_V0 -- --/* -- * Use 2 scratch registers to avoid pipeline interlocks. -- * There is no overhead during epilogue and prologue since -- * any of the $s0-$s6 registers will only be preserved if -- * they are going to actually be used. -- */ --#define r_skb_hl MIPS_R_S0 /* skb header length */ --#define r_skb_data MIPS_R_S1 /* skb actual data */ --#define r_off MIPS_R_S2 --#define r_A MIPS_R_S3 --#define r_X MIPS_R_S4 --#define r_skb MIPS_R_S5 --#define r_M MIPS_R_S6 --#define r_skb_len MIPS_R_S7 --#define r_s0 MIPS_R_T4 /* scratch reg 1 */ --#define r_s1 MIPS_R_T5 /* scratch reg 2 */ --#define r_tmp_imm MIPS_R_T6 /* No need to preserve this */ --#define r_tmp MIPS_R_T7 /* No need to preserve this */ --#define r_zero MIPS_R_ZERO --#define r_sp MIPS_R_SP --#define r_ra MIPS_R_RA -- --#ifndef __ASSEMBLY__ -- --/* Declare ASM helpers */ -- --#define DECLARE_LOAD_FUNC(func) \ -- extern u8 func(unsigned long *skb, int offset); \ -- extern u8 func##_negative(unsigned long *skb, int offset); \ -- extern u8 func##_positive(unsigned long *skb, int offset) -- --DECLARE_LOAD_FUNC(sk_load_word); --DECLARE_LOAD_FUNC(sk_load_half); --DECLARE_LOAD_FUNC(sk_load_byte); -- --#endif -- --#endif /* BPF_JIT_MIPS_OP_H */ ---- a/arch/mips/net/bpf_jit_asm.S -+++ /dev/null -@@ -1,285 +0,0 @@ --/* -- * bpf_jib_asm.S: Packet/header access helper functions for MIPS/MIPS64 BPF -- * compiler. -- * -- * Copyright (C) 2015 Imagination Technologies Ltd. -- * Author: Markos Chandras -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License as published by the -- * Free Software Foundation; version 2 of the License. -- */ -- --#include --#include --#include --#include "bpf_jit.h" -- --/* ABI -- * -- * r_skb_hl skb header length -- * r_skb_data skb data -- * r_off(a1) offset register -- * r_A BPF register A -- * r_X PF register X -- * r_skb(a0) *skb -- * r_M *scratch memory -- * r_skb_le skb length -- * r_s0 Scratch register 0 -- * r_s1 Scratch register 1 -- * -- * On entry: -- * a0: *skb -- * a1: offset (imm or imm + X) -- * -- * All non-BPF-ABI registers are free for use. On return, we only -- * care about r_ret. The BPF-ABI registers are assumed to remain -- * unmodified during the entire filter operation. -- */ -- --#define skb a0 --#define offset a1 --#define SKF_LL_OFF (-0x200000) /* Can't include linux/filter.h in assembly */ -- -- /* We know better :) so prevent assembler reordering etc */ -- .set noreorder -- --#define is_offset_negative(TYPE) \ -- /* If offset is negative we have more work to do */ \ -- slti t0, offset, 0; \ -- bgtz t0, bpf_slow_path_##TYPE##_neg; \ -- /* Be careful what follows in DS. */ -- --#define is_offset_in_header(SIZE, TYPE) \ -- /* Reading from header? */ \ -- addiu $r_s0, $r_skb_hl, -SIZE; \ -- slt t0, $r_s0, offset; \ -- bgtz t0, bpf_slow_path_##TYPE; \ -- --LEAF(sk_load_word) -- is_offset_negative(word) --FEXPORT(sk_load_word_positive) -- is_offset_in_header(4, word) -- /* Offset within header boundaries */ -- PTR_ADDU t1, $r_skb_data, offset -- .set reorder -- lw $r_A, 0(t1) -- .set noreorder --#ifdef CONFIG_CPU_LITTLE_ENDIAN --# if MIPS_ISA_REV >= 2 -- wsbh t0, $r_A -- rotr $r_A, t0, 16 --# else -- sll t0, $r_A, 24 -- srl t1, $r_A, 24 -- srl t2, $r_A, 8 -- or t0, t0, t1 -- andi t2, t2, 0xff00 -- andi t1, $r_A, 0xff00 -- or t0, t0, t2 -- sll t1, t1, 8 -- or $r_A, t0, t1 --# endif --#endif -- jr $r_ra -- move $r_ret, zero -- END(sk_load_word) -- --LEAF(sk_load_half) -- is_offset_negative(half) --FEXPORT(sk_load_half_positive) -- is_offset_in_header(2, half) -- /* Offset within header boundaries */ -- PTR_ADDU t1, $r_skb_data, offset -- lhu $r_A, 0(t1) --#ifdef CONFIG_CPU_LITTLE_ENDIAN --# if MIPS_ISA_REV >= 2 -- wsbh $r_A, $r_A --# else -- sll t0, $r_A, 8 -- srl t1, $r_A, 8 -- andi t0, t0, 0xff00 -- or $r_A, t0, t1 --# endif --#endif -- jr $r_ra -- move $r_ret, zero -- END(sk_load_half) -- --LEAF(sk_load_byte) -- is_offset_negative(byte) --FEXPORT(sk_load_byte_positive) -- is_offset_in_header(1, byte) -- /* Offset within header boundaries */ -- PTR_ADDU t1, $r_skb_data, offset -- lbu $r_A, 0(t1) -- jr $r_ra -- move $r_ret, zero -- END(sk_load_byte) -- --/* -- * call skb_copy_bits: -- * (prototype in linux/skbuff.h) -- * -- * int skb_copy_bits(sk_buff *skb, int offset, void *to, int len) -- * -- * o32 mandates we leave 4 spaces for argument registers in case -- * the callee needs to use them. Even though we don't care about -- * the argument registers ourselves, we need to allocate that space -- * to remain ABI compliant since the callee may want to use that space. -- * We also allocate 2 more spaces for $r_ra and our return register (*to). -- * -- * n64 is a bit different. The *caller* will allocate the space to preserve -- * the arguments. So in 64-bit kernels, we allocate the 4-arg space for no -- * good reason but it does not matter that much really. -- * -- * (void *to) is returned in r_s0 -- * -- */ --#ifdef CONFIG_CPU_LITTLE_ENDIAN --#define DS_OFFSET(SIZE) (4 * SZREG) --#else --#define DS_OFFSET(SIZE) ((4 * SZREG) + (4 - SIZE)) --#endif --#define bpf_slow_path_common(SIZE) \ -- /* Quick check. Are we within reasonable boundaries? */ \ -- LONG_ADDIU $r_s1, $r_skb_len, -SIZE; \ -- sltu $r_s0, offset, $r_s1; \ -- beqz $r_s0, fault; \ -- /* Load 4th argument in DS */ \ -- LONG_ADDIU a3, zero, SIZE; \ -- PTR_ADDIU $r_sp, $r_sp, -(6 * SZREG); \ -- PTR_LA t0, skb_copy_bits; \ -- PTR_S $r_ra, (5 * SZREG)($r_sp); \ -- /* Assign low slot to a2 */ \ -- PTR_ADDIU a2, $r_sp, DS_OFFSET(SIZE); \ -- jalr t0; \ -- /* Reset our destination slot (DS but it's ok) */ \ -- INT_S zero, (4 * SZREG)($r_sp); \ -- /* \ -- * skb_copy_bits returns 0 on success and -EFAULT \ -- * on error. Our data live in a2. Do not bother with \ -- * our data if an error has been returned. \ -- */ \ -- /* Restore our frame */ \ -- PTR_L $r_ra, (5 * SZREG)($r_sp); \ -- INT_L $r_s0, (4 * SZREG)($r_sp); \ -- bltz v0, fault; \ -- PTR_ADDIU $r_sp, $r_sp, 6 * SZREG; \ -- move $r_ret, zero; \ -- --NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp) -- bpf_slow_path_common(4) --#ifdef CONFIG_CPU_LITTLE_ENDIAN --# if MIPS_ISA_REV >= 2 -- wsbh t0, $r_s0 -- jr $r_ra -- rotr $r_A, t0, 16 --# else -- sll t0, $r_s0, 24 -- srl t1, $r_s0, 24 -- srl t2, $r_s0, 8 -- or t0, t0, t1 -- andi t2, t2, 0xff00 -- andi t1, $r_s0, 0xff00 -- or t0, t0, t2 -- sll t1, t1, 8 -- jr $r_ra -- or $r_A, t0, t1 --# endif --#else -- jr $r_ra -- move $r_A, $r_s0 --#endif -- -- END(bpf_slow_path_word) -- --NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp) -- bpf_slow_path_common(2) --#ifdef CONFIG_CPU_LITTLE_ENDIAN --# if MIPS_ISA_REV >= 2 -- jr $r_ra -- wsbh $r_A, $r_s0 --# else -- sll t0, $r_s0, 8 -- andi t1, $r_s0, 0xff00 -- andi t0, t0, 0xff00 -- srl t1, t1, 8 -- jr $r_ra -- or $r_A, t0, t1 --# endif --#else -- jr $r_ra -- move $r_A, $r_s0 --#endif -- -- END(bpf_slow_path_half) -- --NESTED(bpf_slow_path_byte, (6 * SZREG), $r_sp) -- bpf_slow_path_common(1) -- jr $r_ra -- move $r_A, $r_s0 -- -- END(bpf_slow_path_byte) -- --/* -- * Negative entry points -- */ -- .macro bpf_is_end_of_data -- li t0, SKF_LL_OFF -- /* Reading link layer data? */ -- slt t1, offset, t0 -- bgtz t1, fault -- /* Be careful what follows in DS. */ -- .endm --/* -- * call skb_copy_bits: -- * (prototype in linux/filter.h) -- * -- * void *bpf_internal_load_pointer_neg_helper(const struct sk_buff *skb, -- * int k, unsigned int size) -- * -- * see above (bpf_slow_path_common) for ABI restrictions -- */ --#define bpf_negative_common(SIZE) \ -- PTR_ADDIU $r_sp, $r_sp, -(6 * SZREG); \ -- PTR_LA t0, bpf_internal_load_pointer_neg_helper; \ -- PTR_S $r_ra, (5 * SZREG)($r_sp); \ -- jalr t0; \ -- li a2, SIZE; \ -- PTR_L $r_ra, (5 * SZREG)($r_sp); \ -- /* Check return pointer */ \ -- beqz v0, fault; \ -- PTR_ADDIU $r_sp, $r_sp, 6 * SZREG; \ -- /* Preserve our pointer */ \ -- move $r_s0, v0; \ -- /* Set return value */ \ -- move $r_ret, zero; \ -- --bpf_slow_path_word_neg: -- bpf_is_end_of_data --NESTED(sk_load_word_negative, (6 * SZREG), $r_sp) -- bpf_negative_common(4) -- jr $r_ra -- lw $r_A, 0($r_s0) -- END(sk_load_word_negative) -- --bpf_slow_path_half_neg: -- bpf_is_end_of_data --NESTED(sk_load_half_negative, (6 * SZREG), $r_sp) -- bpf_negative_common(2) -- jr $r_ra -- lhu $r_A, 0($r_s0) -- END(sk_load_half_negative) -- --bpf_slow_path_byte_neg: -- bpf_is_end_of_data --NESTED(sk_load_byte_negative, (6 * SZREG), $r_sp) -- bpf_negative_common(1) -- jr $r_ra -- lbu $r_A, 0($r_s0) -- END(sk_load_byte_negative) -- --fault: -- jr $r_ra -- addiu $r_ret, zero, 1 diff --git a/target/linux/generic/backport-5.10/071-crypto-arm-chacha-neon-optimize-for-non-block-size-m.patch b/target/linux/generic/backport-5.10/071-crypto-arm-chacha-neon-optimize-for-non-block-size-m.patch deleted file mode 100644 index b1f46e9af8..0000000000 --- a/target/linux/generic/backport-5.10/071-crypto-arm-chacha-neon-optimize-for-non-block-size-m.patch +++ /dev/null @@ -1,272 +0,0 @@ -From 03662fcd41f4b764857f17b95f9a2a63c24bddd4 Mon Sep 17 00:00:00 2001 -From: Ard Biesheuvel -Date: Tue, 3 Nov 2020 17:28:09 +0100 -Subject: [PATCH 1/2] crypto: arm/chacha-neon - optimize for non-block size - multiples - -commit 86cd97ec4b943af35562a74688bc4e909b32c3d1 upstream. - -The current NEON based ChaCha implementation for ARM is optimized for -multiples of 4x the ChaCha block size (64 bytes). This makes sense for -block encryption, but given that ChaCha is also often used in the -context of networking, it makes sense to consider arbitrary length -inputs as well. - -For example, WireGuard typically uses 1420 byte packets, and performing -ChaCha encryption involves 5 invocations of chacha_4block_xor_neon() -and 3 invocations of chacha_block_xor_neon(), where the last one also -involves a memcpy() using a buffer on the stack to process the final -chunk of 1420 % 64 == 12 bytes. - -Let's optimize for this case as well, by letting chacha_4block_xor_neon() -deal with any input size between 64 and 256 bytes, using NEON permutation -instructions and overlapping loads and stores. This way, the 140 byte -tail of a 1420 byte input buffer can simply be processed in one go. - -This results in the following performance improvements for 1420 byte -blocks, without significant impact on power-of-2 input sizes. (Note -that Raspberry Pi is widely used in combination with a 32-bit kernel, -even though the core is 64-bit capable) - - Cortex-A8 (BeagleBone) : 7% - Cortex-A15 (Calxeda Midway) : 21% - Cortex-A53 (Raspberry Pi 3) : 3% - Cortex-A72 (Raspberry Pi 4) : 19% - -Cc: Eric Biggers -Cc: "Jason A . Donenfeld" -Signed-off-by: Ard Biesheuvel -Signed-off-by: Herbert Xu -Signed-off-by: Jason A. Donenfeld ---- - arch/arm/crypto/chacha-glue.c | 34 +++++------ - arch/arm/crypto/chacha-neon-core.S | 97 +++++++++++++++++++++++++++--- - 2 files changed, 107 insertions(+), 24 deletions(-) - ---- a/arch/arm/crypto/chacha-glue.c -+++ b/arch/arm/crypto/chacha-glue.c -@@ -23,7 +23,7 @@ - asmlinkage void chacha_block_xor_neon(const u32 *state, u8 *dst, const u8 *src, - int nrounds); - asmlinkage void chacha_4block_xor_neon(const u32 *state, u8 *dst, const u8 *src, -- int nrounds); -+ int nrounds, unsigned int nbytes); - asmlinkage void hchacha_block_arm(const u32 *state, u32 *out, int nrounds); - asmlinkage void hchacha_block_neon(const u32 *state, u32 *out, int nrounds); - -@@ -42,24 +42,24 @@ static void chacha_doneon(u32 *state, u8 - { - u8 buf[CHACHA_BLOCK_SIZE]; - -- while (bytes >= CHACHA_BLOCK_SIZE * 4) { -- chacha_4block_xor_neon(state, dst, src, nrounds); -- bytes -= CHACHA_BLOCK_SIZE * 4; -- src += CHACHA_BLOCK_SIZE * 4; -- dst += CHACHA_BLOCK_SIZE * 4; -- state[12] += 4; -- } -- while (bytes >= CHACHA_BLOCK_SIZE) { -- chacha_block_xor_neon(state, dst, src, nrounds); -- bytes -= CHACHA_BLOCK_SIZE; -- src += CHACHA_BLOCK_SIZE; -- dst += CHACHA_BLOCK_SIZE; -- state[12]++; -+ while (bytes > CHACHA_BLOCK_SIZE) { -+ unsigned int l = min(bytes, CHACHA_BLOCK_SIZE * 4U); -+ -+ chacha_4block_xor_neon(state, dst, src, nrounds, l); -+ bytes -= l; -+ src += l; -+ dst += l; -+ state[12] += DIV_ROUND_UP(l, CHACHA_BLOCK_SIZE); - } - if (bytes) { -- memcpy(buf, src, bytes); -- chacha_block_xor_neon(state, buf, buf, nrounds); -- memcpy(dst, buf, bytes); -+ const u8 *s = src; -+ u8 *d = dst; -+ -+ if (bytes != CHACHA_BLOCK_SIZE) -+ s = d = memcpy(buf, src, bytes); -+ chacha_block_xor_neon(state, d, s, nrounds); -+ if (d != dst) -+ memcpy(dst, buf, bytes); - } - } - ---- a/arch/arm/crypto/chacha-neon-core.S -+++ b/arch/arm/crypto/chacha-neon-core.S -@@ -47,6 +47,7 @@ - */ - - #include -+#include - - .text - .fpu neon -@@ -205,7 +206,7 @@ ENDPROC(hchacha_block_neon) - - .align 5 - ENTRY(chacha_4block_xor_neon) -- push {r4-r5} -+ push {r4, lr} - mov r4, sp // preserve the stack pointer - sub ip, sp, #0x20 // allocate a 32 byte buffer - bic ip, ip, #0x1f // aligned to 32 bytes -@@ -229,10 +230,10 @@ ENTRY(chacha_4block_xor_neon) - vld1.32 {q0-q1}, [r0] - vld1.32 {q2-q3}, [ip] - -- adr r5, .Lctrinc -+ adr lr, .Lctrinc - vdup.32 q15, d7[1] - vdup.32 q14, d7[0] -- vld1.32 {q4}, [r5, :128] -+ vld1.32 {q4}, [lr, :128] - vdup.32 q13, d6[1] - vdup.32 q12, d6[0] - vdup.32 q11, d5[1] -@@ -455,7 +456,7 @@ ENTRY(chacha_4block_xor_neon) - - // Re-interleave the words in the first two rows of each block (x0..7). - // Also add the counter values 0-3 to x12[0-3]. -- vld1.32 {q8}, [r5, :128] // load counter values 0-3 -+ vld1.32 {q8}, [lr, :128] // load counter values 0-3 - vzip.32 q0, q1 // => (0 1 0 1) (0 1 0 1) - vzip.32 q2, q3 // => (2 3 2 3) (2 3 2 3) - vzip.32 q4, q5 // => (4 5 4 5) (4 5 4 5) -@@ -493,6 +494,8 @@ ENTRY(chacha_4block_xor_neon) - - // Re-interleave the words in the last two rows of each block (x8..15). - vld1.32 {q8-q9}, [sp, :256] -+ mov sp, r4 // restore original stack pointer -+ ldr r4, [r4, #8] // load number of bytes - vzip.32 q12, q13 // => (12 13 12 13) (12 13 12 13) - vzip.32 q14, q15 // => (14 15 14 15) (14 15 14 15) - vzip.32 q8, q9 // => (8 9 8 9) (8 9 8 9) -@@ -520,41 +523,121 @@ ENTRY(chacha_4block_xor_neon) - // XOR the rest of the data with the keystream - - vld1.8 {q0-q1}, [r2]! -+ subs r4, r4, #96 - veor q0, q0, q8 - veor q1, q1, q12 -+ ble .Lle96 - vst1.8 {q0-q1}, [r1]! - - vld1.8 {q0-q1}, [r2]! -+ subs r4, r4, #32 - veor q0, q0, q2 - veor q1, q1, q6 -+ ble .Lle128 - vst1.8 {q0-q1}, [r1]! - - vld1.8 {q0-q1}, [r2]! -+ subs r4, r4, #32 - veor q0, q0, q10 - veor q1, q1, q14 -+ ble .Lle160 - vst1.8 {q0-q1}, [r1]! - - vld1.8 {q0-q1}, [r2]! -+ subs r4, r4, #32 - veor q0, q0, q4 - veor q1, q1, q5 -+ ble .Lle192 - vst1.8 {q0-q1}, [r1]! - - vld1.8 {q0-q1}, [r2]! -+ subs r4, r4, #32 - veor q0, q0, q9 - veor q1, q1, q13 -+ ble .Lle224 - vst1.8 {q0-q1}, [r1]! - - vld1.8 {q0-q1}, [r2]! -+ subs r4, r4, #32 - veor q0, q0, q3 - veor q1, q1, q7 -+ blt .Llt256 -+.Lout: - vst1.8 {q0-q1}, [r1]! - - vld1.8 {q0-q1}, [r2] -- mov sp, r4 // restore original stack pointer - veor q0, q0, q11 - veor q1, q1, q15 - vst1.8 {q0-q1}, [r1] - -- pop {r4-r5} -- bx lr -+ pop {r4, pc} -+ -+.Lle192: -+ vmov q4, q9 -+ vmov q5, q13 -+ -+.Lle160: -+ // nothing to do -+ -+.Lfinalblock: -+ // Process the final block if processing less than 4 full blocks. -+ // Entered with 32 bytes of ChaCha cipher stream in q4-q5, and the -+ // previous 32 byte output block that still needs to be written at -+ // [r1] in q0-q1. -+ beq .Lfullblock -+ -+.Lpartialblock: -+ adr lr, .Lpermute + 32 -+ add r2, r2, r4 -+ add lr, lr, r4 -+ add r4, r4, r1 -+ -+ vld1.8 {q2-q3}, [lr] -+ vld1.8 {q6-q7}, [r2] -+ -+ add r4, r4, #32 -+ -+ vtbl.8 d4, {q4-q5}, d4 -+ vtbl.8 d5, {q4-q5}, d5 -+ vtbl.8 d6, {q4-q5}, d6 -+ vtbl.8 d7, {q4-q5}, d7 -+ -+ veor q6, q6, q2 -+ veor q7, q7, q3 -+ -+ vst1.8 {q6-q7}, [r4] // overlapping stores -+ vst1.8 {q0-q1}, [r1] -+ pop {r4, pc} -+ -+.Lfullblock: -+ vmov q11, q4 -+ vmov q15, q5 -+ b .Lout -+.Lle96: -+ vmov q4, q2 -+ vmov q5, q6 -+ b .Lfinalblock -+.Lle128: -+ vmov q4, q10 -+ vmov q5, q14 -+ b .Lfinalblock -+.Lle224: -+ vmov q4, q3 -+ vmov q5, q7 -+ b .Lfinalblock -+.Llt256: -+ vmov q4, q11 -+ vmov q5, q15 -+ b .Lpartialblock - ENDPROC(chacha_4block_xor_neon) -+ -+ .align L1_CACHE_SHIFT -+.Lpermute: -+ .byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 -+ .byte 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f -+ .byte 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 -+ .byte 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f -+ .byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 -+ .byte 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f -+ .byte 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17 -+ .byte 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f diff --git a/target/linux/generic/backport-5.10/072-crypto-arm-chacha-neon-add-missing-counter-increment.patch b/target/linux/generic/backport-5.10/072-crypto-arm-chacha-neon-add-missing-counter-increment.patch deleted file mode 100644 index 1e4d2041e5..0000000000 --- a/target/linux/generic/backport-5.10/072-crypto-arm-chacha-neon-add-missing-counter-increment.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 7f63462faf9eab69132bea9abd48c2c05a93145b Mon Sep 17 00:00:00 2001 -From: Ard Biesheuvel -Date: Sun, 13 Dec 2020 15:39:29 +0100 -Subject: [PATCH 2/2] crypto: arm/chacha-neon - add missing counter increment - -commit fd16931a2f518a32753920ff20895e5cf04c8ff1 upstream. - -Commit 86cd97ec4b943af3 ("crypto: arm/chacha-neon - optimize for non-block -size multiples") refactored the chacha block handling in the glue code in -a way that may result in the counter increment to be omitted when calling -chacha_block_xor_neon() to process a full block. This violates the skcipher -API, which requires that the output IV is suitable for handling more input -as long as the preceding input has been presented in round multiples of the -block size. Also, the same code is exposed via the chacha library interface -whose callers may actually rely on this increment to occur even for final -blocks that are smaller than the chacha block size. - -So increment the counter after calling chacha_block_xor_neon(). - -Fixes: 86cd97ec4b943af3 ("crypto: arm/chacha-neon - optimize for non-block size multiples") -Reported-by: Eric Biggers -Signed-off-by: Ard Biesheuvel -Signed-off-by: Herbert Xu -Signed-off-by: Jason A. Donenfeld ---- - arch/arm/crypto/chacha-glue.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/crypto/chacha-glue.c -+++ b/arch/arm/crypto/chacha-glue.c -@@ -60,6 +60,7 @@ static void chacha_doneon(u32 *state, u8 - chacha_block_xor_neon(state, d, s, nrounds); - if (d != dst) - memcpy(dst, buf, bytes); -+ state[12]++; - } - } - diff --git a/target/linux/generic/backport-5.10/080-wireguard-peer-put-frequently-used-members-above-cac.patch b/target/linux/generic/backport-5.10/080-wireguard-peer-put-frequently-used-members-above-cac.patch deleted file mode 100644 index 444fd677b4..0000000000 --- a/target/linux/generic/backport-5.10/080-wireguard-peer-put-frequently-used-members-above-cac.patch +++ /dev/null @@ -1,42 +0,0 @@ -From a13827e9091c07e25cdeec9a402d74a27e2a1111 Mon Sep 17 00:00:00 2001 -From: "Jason A. Donenfeld" -Date: Mon, 22 Feb 2021 17:25:46 +0100 -Subject: [PATCH] wireguard: peer: put frequently used members above cache - lines - -commit 5a0598695634a6bb4126818902dd9140cd9df8b6 upstream. - -The is_dead boolean is checked for every single packet, while the -internal_id member is used basically only for pr_debug messages. So it -makes sense to hoist up is_dead into some space formerly unused by a -struct hole, while demoting internal_api to below the lowest struct -cache line. - -Signed-off-by: Jason A. Donenfeld -Signed-off-by: Jakub Kicinski -Signed-off-by: Jason A. Donenfeld ---- - drivers/net/wireguard/peer.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/wireguard/peer.h -+++ b/drivers/net/wireguard/peer.h -@@ -39,6 +39,7 @@ struct wg_peer { - struct prev_queue tx_queue, rx_queue; - struct sk_buff_head staged_packet_queue; - int serial_work_cpu; -+ bool is_dead; - struct noise_keypairs keypairs; - struct endpoint endpoint; - struct dst_cache endpoint_cache; -@@ -61,9 +62,8 @@ struct wg_peer { - struct rcu_head rcu; - struct list_head peer_list; - struct list_head allowedips_list; -- u64 internal_id; - struct napi_struct napi; -- bool is_dead; -+ u64 internal_id; - }; - - struct wg_peer *wg_peer_create(struct wg_device *wg, diff --git a/target/linux/generic/backport-5.10/081-net-next-regmap-allow-to-define-reg_update_bits-for-no-bus.patch b/target/linux/generic/backport-5.10/081-net-next-regmap-allow-to-define-reg_update_bits-for-no-bus.patch deleted file mode 100644 index 6e274acb1f..0000000000 --- a/target/linux/generic/backport-5.10/081-net-next-regmap-allow-to-define-reg_update_bits-for-no-bus.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 02d6fdecb9c38de19065f6bed8d5214556fd061d Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 4 Nov 2021 16:00:40 +0100 -Subject: regmap: allow to define reg_update_bits for no bus configuration - -Some device requires a special handling for reg_update_bits and can't use -the normal regmap read write logic. An example is when locking is -handled by the device and rmw operations requires to do atomic operations. -Allow to declare a dedicated function in regmap_config for -reg_update_bits in no bus configuration. - -Signed-off-by: Ansuel Smith -Link: https://lore.kernel.org/r/20211104150040.1260-1-ansuelsmth@gmail.com -Signed-off-by: Mark Brown ---- - drivers/base/regmap/regmap.c | 1 + - include/linux/regmap.h | 7 +++++++ - 2 files changed, 8 insertions(+) - ---- a/drivers/base/regmap/regmap.c -+++ b/drivers/base/regmap/regmap.c -@@ -842,6 +842,7 @@ struct regmap *__regmap_init(struct devi - if (!bus) { - map->reg_read = config->reg_read; - map->reg_write = config->reg_write; -+ map->reg_update_bits = config->reg_update_bits; - - map->defer_caching = false; - goto skip_format_initialization; ---- a/include/linux/regmap.h -+++ b/include/linux/regmap.h -@@ -289,6 +289,11 @@ typedef void (*regmap_unlock)(void *); - * read operation on a bus such as SPI, I2C, etc. Most of the - * devices do not need this. - * @reg_write: Same as above for writing. -+ * @reg_update_bits: Optional callback that if filled will be used to perform -+ * all the update_bits(rmw) operation. Should only be provided -+ * if the function require special handling with lock and reg -+ * handling and the operation cannot be represented as a simple -+ * update_bits operation on a bus such as SPI, I2C, etc. - * @fast_io: Register IO is fast. Use a spinlock instead of a mutex - * to perform locking. This field is ignored if custom lock/unlock - * functions are used (see fields lock/unlock of struct regmap_config). -@@ -366,6 +371,8 @@ struct regmap_config { - - int (*reg_read)(void *context, unsigned int reg, unsigned int *val); - int (*reg_write)(void *context, unsigned int reg, unsigned int val); -+ int (*reg_update_bits)(void *context, unsigned int reg, -+ unsigned int mask, unsigned int val); - - bool fast_io; - diff --git a/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch b/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch deleted file mode 100644 index fafe530ac5..0000000000 --- a/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 6523061868212473f63812a0c477a161742bed42 Mon Sep 17 00:00:00 2001 -From: "Jason A. Donenfeld" -Date: Sat, 27 Feb 2021 13:20:24 +0100 -Subject: [PATCH] MIPS: select CPU_MIPS64 for remaining MIPS64 CPUs - -The CPU_MIPS64 and CPU_MIPS32 variables are supposed to be able to -distinguish broadly between 64-bit and 32-bit MIPS CPUs. However, they -weren't selected by the specialty CPUs, Octeon and Loongson, which meant -it was possible to hit a weird state of: - - MIPS=y, CONFIG_64BIT=y, CPU_MIPS64=n - -This commit rectifies the issue by having CPU_MIPS64 be selected when -the missing Octeon or Loongson models are selected. - -Cc: Thomas Bogendoerfer -Cc: Ralf Baechle -Cc: George Cherian -Cc: Huacai Chen -Cc: Jiaxun Yang -Signed-off-by: Jason A. Donenfeld ---- - arch/mips/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -2088,7 +2088,7 @@ config CPU_MIPS32 - config CPU_MIPS64 - bool - default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \ -- CPU_MIPS64_R6 -+ CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON - - # - # These indicate the revision of the architecture diff --git a/target/linux/generic/backport-5.10/200-v5.18-tools-resolve_btfids-Build-with-host-flags.patch b/target/linux/generic/backport-5.10/200-v5.18-tools-resolve_btfids-Build-with-host-flags.patch deleted file mode 100644 index caec8db5d6..0000000000 --- a/target/linux/generic/backport-5.10/200-v5.18-tools-resolve_btfids-Build-with-host-flags.patch +++ /dev/null @@ -1,49 +0,0 @@ -From cdbc4e3399ed8cdcf234a85f7a2482b622379e82 Mon Sep 17 00:00:00 2001 -From: Connor O'Brien -Date: Wed, 12 Jan 2022 00:25:03 +0000 -Subject: [PATCH] tools/resolve_btfids: Build with host flags - -resolve_btfids is built using $(HOSTCC) and $(HOSTLD) but does not -pick up the corresponding flags. As a result, host-specific settings -(such as a sysroot specified via HOSTCFLAGS=--sysroot=..., or a linker -specified via HOSTLDFLAGS=-fuse-ld=...) will not be respected. - -Fix this by setting CFLAGS to KBUILD_HOSTCFLAGS and LDFLAGS to -KBUILD_HOSTLDFLAGS. - -Also pass the cflags through to libbpf via EXTRA_CFLAGS to ensure that -the host libbpf is built with flags consistent with resolve_btfids. - -Signed-off-by: Connor O'Brien -Signed-off-by: Andrii Nakryiko -Acked-by: Song Liu -Link: https://lore.kernel.org/bpf/20220112002503.115968-1-connoro@google.com -(cherry picked from commit 0e3a1c902ffb56e9fe4416f0cd382c97b09ecbf6) -Signed-off-by: Stijn Tintel ---- - tools/bpf/resolve_btfids/Makefile | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/tools/bpf/resolve_btfids/Makefile -+++ b/tools/bpf/resolve_btfids/Makefile -@@ -23,6 +23,8 @@ CC = $(HOSTCC) - LD = $(HOSTLD) - ARCH = $(HOSTARCH) - RM ?= rm -+CFLAGS := $(KBUILD_HOSTCFLAGS) -+LDFLAGS := $(KBUILD_HOSTLDFLAGS) - - OUTPUT ?= $(srctree)/tools/bpf/resolve_btfids/ - -@@ -45,9 +47,9 @@ $(SUBCMDOBJ): fixdep FORCE | $(OUTPUT)/l - $(Q)$(MAKE) -C $(SUBCMD_SRC) OUTPUT=$(abspath $(dir $@))/ $(abspath $@) - - $(BPFOBJ): $(wildcard $(LIBBPF_SRC)/*.[ch] $(LIBBPF_SRC)/Makefile) | $(OUTPUT)/libbpf -- $(Q)$(MAKE) $(submake_extras) -C $(LIBBPF_SRC) OUTPUT=$(abspath $(dir $@))/ $(abspath $@) -+ $(Q)$(MAKE) $(submake_extras) -C $(LIBBPF_SRC) OUTPUT=$(abspath $(dir $@))/ EXTRA_CFLAGS="$(CFLAGS)" $(abspath $@) - --CFLAGS := -g \ -+CFLAGS += -g \ - -I$(srctree)/tools/include \ - -I$(srctree)/tools/include/uapi \ - -I$(LIBBPF_SRC) \ diff --git a/target/linux/generic/backport-5.10/311-v5.11-MIPS-zboot-put-appended-dtb-into-a-section.patch b/target/linux/generic/backport-5.10/311-v5.11-MIPS-zboot-put-appended-dtb-into-a-section.patch deleted file mode 100644 index 3f8808f702..0000000000 --- a/target/linux/generic/backport-5.10/311-v5.11-MIPS-zboot-put-appended-dtb-into-a-section.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 7d1531c81c0fb4c93bea8dc316043ad0e4d0c270 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 25 Oct 2020 23:19:40 +0800 -Subject: [PATCH] MIPS: zboot: put appended dtb into a section - -This will make a separated section for dtb appear in ELF, and we can -then use objcopy to patch a dtb into vmlinuz when RAW_APPENDED_DTB -is set in kernel config. - -command to patch a dtb: -objcopy --set-section-flags=.appended_dtb=alloc,contents \ - --update-section=.appended_dtb=.dtb vmlinuz vmlinuz-dtb - -Signed-off-by: Chuanhong Guo ---- - arch/mips/boot/compressed/ld.script | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/arch/mips/boot/compressed/ld.script -+++ b/arch/mips/boot/compressed/ld.script -@@ -31,9 +31,12 @@ SECTIONS - CONSTRUCTORS - . = ALIGN(16); - } -- __appended_dtb = .; -- /* leave space for appended DTB */ -- . += 0x100000; -+ -+ .appended_dtb : { -+ __appended_dtb = .; -+ /* leave space for appended DTB */ -+ . += 0x100000; -+ } - - _edata = .; - /* End of data section */ diff --git a/target/linux/generic/backport-5.10/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/backport-5.10/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch deleted file mode 100644 index d300af3342..0000000000 --- a/target/linux/generic/backport-5.10/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch +++ /dev/null @@ -1,106 +0,0 @@ -From: Pablo Neira Ayuso -Date: Thu, 25 Jan 2018 12:58:55 +0100 -Subject: [PATCH] netfilter: nft_flow_offload: handle netdevice events from - nf_flow_table - -Move the code that deals with device events to the core. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -576,13 +576,41 @@ void nf_flow_table_free(struct nf_flowta - } - EXPORT_SYMBOL_GPL(nf_flow_table_free); - -+static int nf_flow_table_netdev_event(struct notifier_block *this, -+ unsigned long event, void *ptr) -+{ -+ struct net_device *dev = netdev_notifier_info_to_dev(ptr); -+ -+ if (event != NETDEV_DOWN) -+ return NOTIFY_DONE; -+ -+ nf_flow_table_cleanup(dev); -+ -+ return NOTIFY_DONE; -+} -+ -+static struct notifier_block flow_offload_netdev_notifier = { -+ .notifier_call = nf_flow_table_netdev_event, -+}; -+ - static int __init nf_flow_table_module_init(void) - { -- return nf_flow_table_offload_init(); -+ int ret; -+ -+ ret = nf_flow_table_offload_init(); -+ if (ret) -+ return ret; -+ -+ ret = register_netdevice_notifier(&flow_offload_netdev_notifier); -+ if (ret) -+ nf_flow_table_offload_exit(); -+ -+ return ret; - } - - static void __exit nf_flow_table_module_exit(void) - { -+ unregister_netdevice_notifier(&flow_offload_netdev_notifier); - nf_flow_table_offload_exit(); - } - ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -237,47 +237,14 @@ static struct nft_expr_type nft_flow_off - .owner = THIS_MODULE, - }; - --static int flow_offload_netdev_event(struct notifier_block *this, -- unsigned long event, void *ptr) --{ -- struct net_device *dev = netdev_notifier_info_to_dev(ptr); -- -- if (event != NETDEV_DOWN) -- return NOTIFY_DONE; -- -- nf_flow_table_cleanup(dev); -- -- return NOTIFY_DONE; --} -- --static struct notifier_block flow_offload_netdev_notifier = { -- .notifier_call = flow_offload_netdev_event, --}; -- - static int __init nft_flow_offload_module_init(void) - { -- int err; -- -- err = register_netdevice_notifier(&flow_offload_netdev_notifier); -- if (err) -- goto err; -- -- err = nft_register_expr(&nft_flow_offload_type); -- if (err < 0) -- goto register_expr; -- -- return 0; -- --register_expr: -- unregister_netdevice_notifier(&flow_offload_netdev_notifier); --err: -- return err; -+ return nft_register_expr(&nft_flow_offload_type); - } - - static void __exit nft_flow_offload_module_exit(void) - { - nft_unregister_expr(&nft_flow_offload_type); -- unregister_netdevice_notifier(&flow_offload_netdev_notifier); - } - - module_init(nft_flow_offload_module_init); diff --git a/target/linux/generic/backport-5.10/401-v5.11-dt-bindings-mtd-convert-fixed-partitions-to-the-json.patch b/target/linux/generic/backport-5.10/401-v5.11-dt-bindings-mtd-convert-fixed-partitions-to-the-json.patch deleted file mode 100644 index 8aded43526..0000000000 --- a/target/linux/generic/backport-5.10/401-v5.11-dt-bindings-mtd-convert-fixed-partitions-to-the-json.patch +++ /dev/null @@ -1,324 +0,0 @@ -From 04e9ab75267489224364fa510a88ada83e11c325 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 10 Dec 2020 18:23:52 +0100 -Subject: [PATCH] dt-bindings: mtd: convert "fixed-partitions" to the - json-schema -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This standardizes its documentation, allows validating with Makefile -checks and helps writing DTS files. - -Noticeable changes: -1. Dropped "Partitions can be represented by sub-nodes of a flash - device." as we also support subpartitions (don't have to be part of - flash device node) -2. Dropped "to Linux" as bindings are meant to be os agnostic. - -Signed-off-by: Rafał Miłecki -Link: https://lore.kernel.org/r/20201210172352.31632-1-zajec5@gmail.com -Signed-off-by: Rob Herring ---- - .../devicetree/bindings/mtd/partition.txt | 131 +-------------- - .../mtd/partitions/fixed-partitions.yaml | 152 ++++++++++++++++++ - 2 files changed, 154 insertions(+), 129 deletions(-) - create mode 100644 Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml - ---- a/Documentation/devicetree/bindings/mtd/partition.txt -+++ b/Documentation/devicetree/bindings/mtd/partition.txt -@@ -24,137 +24,10 @@ another partitioning method. - Available bindings are listed in the "partitions" subdirectory. - - --Fixed Partitions --================ -- --Partitions can be represented by sub-nodes of a flash device. This can be used --on platforms which have strong conventions about which portions of a flash are --used for what purposes, but which don't use an on-flash partition table such --as RedBoot. -- --The partition table should be a subnode of the flash node and should be named --'partitions'. This node should have the following property: --- compatible : (required) must be "fixed-partitions" --Partitions are then defined in subnodes of the partitions node. -+Deprecated: partitions defined in flash node -+============================================ - - For backwards compatibility partitions as direct subnodes of the flash device are - supported. This use is discouraged. - NOTE: also for backwards compatibility, direct subnodes that have a compatible - string are not considered partitions, as they may be used for other bindings. -- --#address-cells & #size-cells must both be present in the partitions subnode of the --flash device. There are two valid values for both: --<1>: for partitions that require a single 32-bit cell to represent their -- size/address (aka the value is below 4 GiB) --<2>: for partitions that require two 32-bit cells to represent their -- size/address (aka the value is 4 GiB or greater). -- --Required properties: --- reg : The partition's offset and size within the flash -- --Optional properties: --- label : The label / name for this partition. If omitted, the label is taken -- from the node name (excluding the unit address). --- read-only : This parameter, if present, is a hint to Linux that this -- partition should only be mounted read-only. This is usually used for flash -- partitions containing early-boot firmware images or data which should not be -- clobbered. --- lock : Do not unlock the partition at initialization time (not supported on -- all devices) --- slc-mode: This parameter, if present, allows one to emulate SLC mode on a -- partition attached to an MLC NAND thus making this partition immune to -- paired-pages corruptions -- --Examples: -- -- --flash@0 { -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "u-boot"; -- reg = <0x0000000 0x100000>; -- read-only; -- }; -- -- uimage@100000 { -- reg = <0x0100000 0x200000>; -- }; -- }; --}; -- --flash@1 { -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <2>; -- -- /* a 4 GiB partition */ -- partition@0 { -- label = "filesystem"; -- reg = <0x00000000 0x1 0x00000000>; -- }; -- }; --}; -- --flash@2 { -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <2>; -- #size-cells = <2>; -- -- /* an 8 GiB partition */ -- partition@0 { -- label = "filesystem #1"; -- reg = <0x0 0x00000000 0x2 0x00000000>; -- }; -- -- /* a 4 GiB partition */ -- partition@200000000 { -- label = "filesystem #2"; -- reg = <0x2 0x00000000 0x1 0x00000000>; -- }; -- }; --}; -- --flash@3 { -- partitions { -- compatible = "fixed-partitions"; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "bootloader"; -- reg = <0x000000 0x100000>; -- read-only; -- }; -- -- firmware@100000 { -- label = "firmware"; -- reg = <0x100000 0xe00000>; -- compatible = "brcm,trx"; -- }; -- -- calibration@f00000 { -- label = "calibration"; -- reg = <0xf00000 0x100000>; -- compatible = "fixed-partitions"; -- ranges = <0 0xf00000 0x100000>; -- #address-cells = <1>; -- #size-cells = <1>; -- -- partition@0 { -- label = "wifi0"; -- reg = <0x000000 0x080000>; -- }; -- -- partition@80000 { -- label = "wifi1"; -- reg = <0x080000 0x080000>; -- }; -- }; -- }; --}; ---- /dev/null -+++ b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml -@@ -0,0 +1,152 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mtd/partitions/fixed-partitions.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Fixed partitions -+ -+description: | -+ This binding can be used on platforms which have strong conventions about -+ which portions of a flash are used for what purposes, but which don't use an -+ on-flash partition table such as RedBoot. -+ -+ The partition table should be a node named "partitions". Partitions are then -+ defined as subnodes. -+ -+maintainers: -+ - Rafał Miłecki -+ -+properties: -+ compatible: -+ const: fixed-partitions -+ -+ "#address-cells": true -+ -+ "#size-cells": true -+ -+patternProperties: -+ "@[0-9a-f]+$": -+ description: node describing a single flash partition -+ type: object -+ -+ properties: -+ reg: -+ description: partition's offset and size within the flash -+ maxItems: 1 -+ -+ label: -+ description: The label / name for this partition. If omitted, the label -+ is taken from the node name (excluding the unit address). -+ -+ read-only: -+ description: This parameter, if present, is a hint that this partition -+ should only be mounted read-only. This is usually used for flash -+ partitions containing early-boot firmware images or data which should -+ not be clobbered. -+ type: boolean -+ -+ lock: -+ description: Do not unlock the partition at initialization time (not -+ supported on all devices) -+ type: boolean -+ -+ slc-mode: -+ description: This parameter, if present, allows one to emulate SLC mode -+ on a partition attached to an MLC NAND thus making this partition -+ immune to paired-pages corruptions -+ type: boolean -+ -+ required: -+ - reg -+ -+required: -+ - "#address-cells" -+ - "#size-cells" -+ -+additionalProperties: true -+ -+examples: -+ - | -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x0000000 0x100000>; -+ read-only; -+ }; -+ -+ uimage@100000 { -+ reg = <0x0100000 0x200000>; -+ }; -+ }; -+ - | -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <2>; -+ -+ /* a 4 GiB partition */ -+ partition@0 { -+ label = "filesystem"; -+ reg = <0x00000000 0x1 0x00000000>; -+ }; -+ }; -+ - | -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ /* an 8 GiB partition */ -+ partition@0 { -+ label = "filesystem #1"; -+ reg = <0x0 0x00000000 0x2 0x00000000>; -+ }; -+ -+ /* a 4 GiB partition */ -+ partition@200000000 { -+ label = "filesystem #2"; -+ reg = <0x2 0x00000000 0x1 0x00000000>; -+ }; -+ }; -+ - | -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bootloader"; -+ reg = <0x000000 0x100000>; -+ read-only; -+ }; -+ -+ firmware@100000 { -+ compatible = "brcm,trx"; -+ label = "firmware"; -+ reg = <0x100000 0xe00000>; -+ }; -+ -+ calibration@f00000 { -+ compatible = "fixed-partitions"; -+ label = "calibration"; -+ reg = <0xf00000 0x100000>; -+ ranges = <0 0xf00000 0x100000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "wifi0"; -+ reg = <0x000000 0x080000>; -+ }; -+ -+ partition@80000 { -+ label = "wifi1"; -+ reg = <0x080000 0x080000>; -+ }; -+ }; -+ }; diff --git a/target/linux/generic/backport-5.10/402-v5.12-0001-dt-bindings-mtd-move-partition-binding-to-its-own-fi.patch b/target/linux/generic/backport-5.10/402-v5.12-0001-dt-bindings-mtd-move-partition-binding-to-its-own-fi.patch deleted file mode 100644 index f3b1179ecd..0000000000 --- a/target/linux/generic/backport-5.10/402-v5.12-0001-dt-bindings-mtd-move-partition-binding-to-its-own-fi.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 6418522022c706fd867b00b2571edba48b8fa8c7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 23:04:25 +0100 -Subject: [PATCH] dt-bindings: mtd: move partition binding to its own file -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Single partition binding is quite common and may be: -1. Used by multiple parsers -2. Extended for more specific cases - -Move it to separated file to avoid code duplication. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Rob Herring -Signed-off-by: Richard Weinberger ---- - .../mtd/partitions/fixed-partitions.yaml | 33 +------------ - .../bindings/mtd/partitions/partition.yaml | 47 +++++++++++++++++++ - 2 files changed, 48 insertions(+), 32 deletions(-) - create mode 100644 Documentation/devicetree/bindings/mtd/partitions/partition.yaml - ---- a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml -+++ b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml -@@ -27,38 +27,7 @@ properties: - - patternProperties: - "@[0-9a-f]+$": -- description: node describing a single flash partition -- type: object -- -- properties: -- reg: -- description: partition's offset and size within the flash -- maxItems: 1 -- -- label: -- description: The label / name for this partition. If omitted, the label -- is taken from the node name (excluding the unit address). -- -- read-only: -- description: This parameter, if present, is a hint that this partition -- should only be mounted read-only. This is usually used for flash -- partitions containing early-boot firmware images or data which should -- not be clobbered. -- type: boolean -- -- lock: -- description: Do not unlock the partition at initialization time (not -- supported on all devices) -- type: boolean -- -- slc-mode: -- description: This parameter, if present, allows one to emulate SLC mode -- on a partition attached to an MLC NAND thus making this partition -- immune to paired-pages corruptions -- type: boolean -- -- required: -- - reg -+ $ref: "partition.yaml#" - - required: - - "#address-cells" ---- /dev/null -+++ b/Documentation/devicetree/bindings/mtd/partitions/partition.yaml -@@ -0,0 +1,47 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mtd/partitions/partition.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Partition -+ -+description: | -+ This binding describes a single flash partition. Each partition must have its -+ relative offset and size specified. Depending on partition function extra -+ properties can be used. -+ -+maintainers: -+ - Rafał Miłecki -+ -+properties: -+ reg: -+ description: partition's offset and size within the flash -+ maxItems: 1 -+ -+ label: -+ description: The label / name for this partition. If omitted, the label -+ is taken from the node name (excluding the unit address). -+ -+ read-only: -+ description: This parameter, if present, is a hint that this partition -+ should only be mounted read-only. This is usually used for flash -+ partitions containing early-boot firmware images or data which should -+ not be clobbered. -+ type: boolean -+ -+ lock: -+ description: Do not unlock the partition at initialization time (not -+ supported on all devices) -+ type: boolean -+ -+ slc-mode: -+ description: This parameter, if present, allows one to emulate SLC mode -+ on a partition attached to an MLC NAND thus making this partition -+ immune to paired-pages corruptions -+ type: boolean -+ -+required: -+ - reg -+ -+additionalProperties: true diff --git a/target/linux/generic/backport-5.10/402-v5.12-0002-dt-bindings-mtd-add-binding-for-BCM4908-partitions.patch b/target/linux/generic/backport-5.10/402-v5.12-0002-dt-bindings-mtd-add-binding-for-BCM4908-partitions.patch deleted file mode 100644 index 8576c7d78d..0000000000 --- a/target/linux/generic/backport-5.10/402-v5.12-0002-dt-bindings-mtd-add-binding-for-BCM4908-partitions.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 6e9dff6fe3fbc452f16566e4a7e293b0decefdba Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 23:04:26 +0100 -Subject: [PATCH] dt-bindings: mtd: add binding for BCM4908 partitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM4908 uses fixed partitions layout but function of some partitions may -vary. Some devices use multiple firmware partitions and those partitions -should be marked to let system discover their purpose. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Richard Weinberger ---- - .../partitions/brcm,bcm4908-partitions.yaml | 70 +++++++++++++++++++ - 1 file changed, 70 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml -@@ -0,0 +1,70 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mtd/partitions/brcm,bcm4908-partitions.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom BCM4908 partitioning -+ -+description: | -+ Broadcom BCM4908 CFE bootloader supports two firmware partitions. One is used -+ for regular booting, the other is treated as fallback. -+ -+ This binding allows defining all fixed partitions and marking those containing -+ firmware. System can use that information e.g. for booting or flashing -+ purposes. -+ -+maintainers: -+ - Rafał Miłecki -+ -+properties: -+ compatible: -+ const: brcm,bcm4908-partitions -+ -+ "#address-cells": -+ enum: [ 1, 2 ] -+ -+ "#size-cells": -+ enum: [ 1, 2 ] -+ -+patternProperties: -+ "^partition@[0-9a-f]+$": -+ $ref: "partition.yaml#" -+ properties: -+ compatible: -+ const: brcm,bcm4908-firmware -+ unevaluatedProperties: false -+ -+required: -+ - "#address-cells" -+ - "#size-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ partitions { -+ compatible = "brcm,bcm4908-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "cferom"; -+ reg = <0x0 0x100000>; -+ }; -+ -+ partition@100000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x100000 0xf00000>; -+ }; -+ -+ partition@1000000 { -+ compatible = "brcm,bcm4908-firmware"; -+ reg = <0x1000000 0xf00000>; -+ }; -+ -+ partition@1f00000 { -+ label = "calibration"; -+ reg = <0x1f00000 0x100000>; -+ }; -+ }; diff --git a/target/linux/generic/backport-5.10/403-v5.13-mtd-parsers-ofpart-support-BCM4908-fixed-partitions.patch b/target/linux/generic/backport-5.10/403-v5.13-mtd-parsers-ofpart-support-BCM4908-fixed-partitions.patch deleted file mode 100644 index d3891228e2..0000000000 --- a/target/linux/generic/backport-5.10/403-v5.13-mtd-parsers-ofpart-support-BCM4908-fixed-partitions.patch +++ /dev/null @@ -1,654 +0,0 @@ -From afbef8efb591792579c633a7c545f914c6165f82 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 11 Feb 2021 23:04:27 +0100 -Subject: [PATCH] mtd: parsers: ofpart: support BCM4908 fixed partitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Some devices use fixed partitioning with some partitions requiring some -extra logic. E.g. BCM4908 may have multiple firmware partitions but -detecting currently used one requires checking bootloader parameters. - -To support such cases without duplicating a lot of code (without copying -most of the ofpart.c code) support for post-parsing callback was added. - -BCM4908 support in ofpart can be enabled using config option and results -in compiling & executing a specific callback. It simply reads offset of -currently used firmware partition from the DT. Bootloader specifies it -using the "brcm_blparms" property. - -Signed-off-by: Rafał Miłecki ---- - drivers/mtd/parsers/Kconfig | 9 +++ - drivers/mtd/parsers/Makefile | 2 + - drivers/mtd/parsers/ofpart_bcm4908.c | 64 +++++++++++++++++++ - drivers/mtd/parsers/ofpart_bcm4908.h | 15 +++++ - .../mtd/parsers/{ofpart.c => ofpart_core.c} | 28 +++++++- - 5 files changed, 116 insertions(+), 2 deletions(-) - create mode 100644 drivers/mtd/parsers/ofpart_bcm4908.c - create mode 100644 drivers/mtd/parsers/ofpart_bcm4908.h - rename drivers/mtd/parsers/{ofpart.c => ofpart_core.c} (88%) - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -67,6 +67,15 @@ config MTD_OF_PARTS - flash memory node, as described in - Documentation/devicetree/bindings/mtd/partition.txt. - -+config MTD_OF_PARTS_BCM4908 -+ bool "BCM4908 partitioning support" -+ depends on MTD_OF_PARTS && (ARCH_BCM4908 || COMPILE_TEST) -+ default ARCH_BCM4908 -+ help -+ This provides partitions parser for BCM4908 family devices -+ that can have multiple "firmware" partitions. It takes care of -+ finding currently used one and backup ones. -+ - config MTD_PARSER_IMAGETAG - tristate "Parser for BCM963XX Image Tag format partitions" - depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -4,6 +4,8 @@ obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm4 - obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o - obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o - obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o -+ofpart-y += ofpart_core.o -+ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908) += ofpart_bcm4908.o - obj-$(CONFIG_MTD_PARSER_IMAGETAG) += parser_imagetag.o - obj-$(CONFIG_MTD_AFS_PARTS) += afs.o - obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o ---- /dev/null -+++ b/drivers/mtd/parsers/ofpart_bcm4908.c -@@ -0,0 +1,64 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2021 Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ofpart_bcm4908.h" -+ -+#define BLPARAMS_FW_OFFSET "NAND_RFS_OFS" -+ -+static long long bcm4908_partitions_fw_offset(void) -+{ -+ struct device_node *root; -+ struct property *prop; -+ const char *s; -+ -+ root = of_find_node_by_path("/"); -+ if (!root) -+ return -ENOENT; -+ -+ of_property_for_each_string(root, "brcm_blparms", prop, s) { -+ size_t len = strlen(BLPARAMS_FW_OFFSET); -+ unsigned long offset; -+ int err; -+ -+ if (strncmp(s, BLPARAMS_FW_OFFSET, len) || s[len] != '=') -+ continue; -+ -+ err = kstrtoul(s + len + 1, 0, &offset); -+ if (err) { -+ pr_err("failed to parse %s\n", s + len + 1); -+ return err; -+ } -+ -+ return offset << 10; -+ } -+ -+ return -ENOENT; -+} -+ -+int bcm4908_partitions_post_parse(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts) -+{ -+ long long fw_offset; -+ int i; -+ -+ fw_offset = bcm4908_partitions_fw_offset(); -+ -+ for (i = 0; i < nr_parts; i++) { -+ if (of_device_is_compatible(parts[i].of_node, "brcm,bcm4908-firmware")) { -+ if (fw_offset < 0 || parts[i].offset == fw_offset) -+ parts[i].name = "firmware"; -+ else -+ parts[i].name = "backup"; -+ } -+ } -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/mtd/parsers/ofpart_bcm4908.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+#ifndef __BCM4908_PARTITIONS_H -+#define __BCM4908_PARTITIONS_H -+ -+#ifdef CONFIG_MTD_OF_PARTS_BCM4908 -+int bcm4908_partitions_post_parse(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts); -+#else -+static inline int bcm4908_partitions_post_parse(struct mtd_info *mtd, struct mtd_partition *parts, -+ int nr_parts) -+{ -+ return -EOPNOTSUPP; -+} -+#endif -+ -+#endif ---- a/drivers/mtd/parsers/ofpart.c -+++ /dev/null -@@ -1,239 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0-or-later --/* -- * Flash partitions described by the OF (or flattened) device tree -- * -- * Copyright © 2006 MontaVista Software Inc. -- * Author: Vitaly Wool -- * -- * Revised to handle newer style flash binding by: -- * Copyright © 2007 David Gibson, IBM Corporation. -- */ -- --#include --#include --#include --#include --#include --#include -- --static bool node_has_compatible(struct device_node *pp) --{ -- return of_get_property(pp, "compatible", NULL); --} -- --static int parse_fixed_partitions(struct mtd_info *master, -- const struct mtd_partition **pparts, -- struct mtd_part_parser_data *data) --{ -- struct mtd_partition *parts; -- struct device_node *mtd_node; -- struct device_node *ofpart_node; -- const char *partname; -- struct device_node *pp; -- int nr_parts, i, ret = 0; -- bool dedicated = true; -- -- -- /* Pull of_node from the master device node */ -- mtd_node = mtd_get_of_node(master); -- if (!mtd_node) -- return 0; -- -- ofpart_node = of_get_child_by_name(mtd_node, "partitions"); -- if (!ofpart_node) { -- /* -- * We might get here even when ofpart isn't used at all (e.g., -- * when using another parser), so don't be louder than -- * KERN_DEBUG -- */ -- pr_debug("%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\n", -- master->name, mtd_node); -- ofpart_node = mtd_node; -- dedicated = false; -- } else if (!of_device_is_compatible(ofpart_node, "fixed-partitions")) { -- /* The 'partitions' subnode might be used by another parser */ -- return 0; -- } -- -- /* First count the subnodes */ -- nr_parts = 0; -- for_each_child_of_node(ofpart_node, pp) { -- if (!dedicated && node_has_compatible(pp)) -- continue; -- -- nr_parts++; -- } -- -- if (nr_parts == 0) -- return 0; -- -- parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); -- if (!parts) -- return -ENOMEM; -- -- i = 0; -- for_each_child_of_node(ofpart_node, pp) { -- const __be32 *reg; -- int len; -- int a_cells, s_cells; -- -- if (!dedicated && node_has_compatible(pp)) -- continue; -- -- reg = of_get_property(pp, "reg", &len); -- if (!reg) { -- if (dedicated) { -- pr_debug("%s: ofpart partition %pOF (%pOF) missing reg property.\n", -- master->name, pp, -- mtd_node); -- goto ofpart_fail; -- } else { -- nr_parts--; -- continue; -- } -- } -- -- a_cells = of_n_addr_cells(pp); -- s_cells = of_n_size_cells(pp); -- if (len / 4 != a_cells + s_cells) { -- pr_debug("%s: ofpart partition %pOF (%pOF) error parsing reg property.\n", -- master->name, pp, -- mtd_node); -- goto ofpart_fail; -- } -- -- parts[i].offset = of_read_number(reg, a_cells); -- parts[i].size = of_read_number(reg + a_cells, s_cells); -- parts[i].of_node = pp; -- -- partname = of_get_property(pp, "label", &len); -- if (!partname) -- partname = of_get_property(pp, "name", &len); -- parts[i].name = partname; -- -- if (of_get_property(pp, "read-only", &len)) -- parts[i].mask_flags |= MTD_WRITEABLE; -- -- if (of_get_property(pp, "lock", &len)) -- parts[i].mask_flags |= MTD_POWERUP_LOCK; -- -- if (of_property_read_bool(pp, "slc-mode")) -- parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION; -- -- i++; -- } -- -- if (!nr_parts) -- goto ofpart_none; -- -- *pparts = parts; -- return nr_parts; -- --ofpart_fail: -- pr_err("%s: error parsing ofpart partition %pOF (%pOF)\n", -- master->name, pp, mtd_node); -- ret = -EINVAL; --ofpart_none: -- of_node_put(pp); -- kfree(parts); -- return ret; --} -- --static const struct of_device_id parse_ofpart_match_table[] = { -- { .compatible = "fixed-partitions" }, -- {}, --}; --MODULE_DEVICE_TABLE(of, parse_ofpart_match_table); -- --static struct mtd_part_parser ofpart_parser = { -- .parse_fn = parse_fixed_partitions, -- .name = "fixed-partitions", -- .of_match_table = parse_ofpart_match_table, --}; -- --static int parse_ofoldpart_partitions(struct mtd_info *master, -- const struct mtd_partition **pparts, -- struct mtd_part_parser_data *data) --{ -- struct mtd_partition *parts; -- struct device_node *dp; -- int i, plen, nr_parts; -- const struct { -- __be32 offset, len; -- } *part; -- const char *names; -- -- /* Pull of_node from the master device node */ -- dp = mtd_get_of_node(master); -- if (!dp) -- return 0; -- -- part = of_get_property(dp, "partitions", &plen); -- if (!part) -- return 0; /* No partitions found */ -- -- pr_warn("Device tree uses obsolete partition map binding: %pOF\n", dp); -- -- nr_parts = plen / sizeof(part[0]); -- -- parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); -- if (!parts) -- return -ENOMEM; -- -- names = of_get_property(dp, "partition-names", &plen); -- -- for (i = 0; i < nr_parts; i++) { -- parts[i].offset = be32_to_cpu(part->offset); -- parts[i].size = be32_to_cpu(part->len) & ~1; -- /* bit 0 set signifies read only partition */ -- if (be32_to_cpu(part->len) & 1) -- parts[i].mask_flags = MTD_WRITEABLE; -- -- if (names && (plen > 0)) { -- int len = strlen(names) + 1; -- -- parts[i].name = names; -- plen -= len; -- names += len; -- } else { -- parts[i].name = "unnamed"; -- } -- -- part++; -- } -- -- *pparts = parts; -- return nr_parts; --} -- --static struct mtd_part_parser ofoldpart_parser = { -- .parse_fn = parse_ofoldpart_partitions, -- .name = "ofoldpart", --}; -- --static int __init ofpart_parser_init(void) --{ -- register_mtd_parser(&ofpart_parser); -- register_mtd_parser(&ofoldpart_parser); -- return 0; --} -- --static void __exit ofpart_parser_exit(void) --{ -- deregister_mtd_parser(&ofpart_parser); -- deregister_mtd_parser(&ofoldpart_parser); --} -- --module_init(ofpart_parser_init); --module_exit(ofpart_parser_exit); -- --MODULE_LICENSE("GPL"); --MODULE_DESCRIPTION("Parser for MTD partitioning information in device tree"); --MODULE_AUTHOR("Vitaly Wool, David Gibson"); --/* -- * When MTD core cannot find the requested parser, it tries to load the module -- * with the same name. Since we provide the ofoldpart parser, we should have -- * the corresponding alias. -- */ --MODULE_ALIAS("fixed-partitions"); --MODULE_ALIAS("ofoldpart"); ---- /dev/null -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -0,0 +1,263 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Flash partitions described by the OF (or flattened) device tree -+ * -+ * Copyright © 2006 MontaVista Software Inc. -+ * Author: Vitaly Wool -+ * -+ * Revised to handle newer style flash binding by: -+ * Copyright © 2007 David Gibson, IBM Corporation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ofpart_bcm4908.h" -+ -+struct fixed_partitions_quirks { -+ int (*post_parse)(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts); -+}; -+ -+struct fixed_partitions_quirks bcm4908_partitions_quirks = { -+ .post_parse = bcm4908_partitions_post_parse, -+}; -+ -+static const struct of_device_id parse_ofpart_match_table[]; -+ -+static bool node_has_compatible(struct device_node *pp) -+{ -+ return of_get_property(pp, "compatible", NULL); -+} -+ -+static int parse_fixed_partitions(struct mtd_info *master, -+ const struct mtd_partition **pparts, -+ struct mtd_part_parser_data *data) -+{ -+ const struct fixed_partitions_quirks *quirks; -+ const struct of_device_id *of_id; -+ struct mtd_partition *parts; -+ struct device_node *mtd_node; -+ struct device_node *ofpart_node; -+ const char *partname; -+ struct device_node *pp; -+ int nr_parts, i, ret = 0; -+ bool dedicated = true; -+ -+ /* Pull of_node from the master device node */ -+ mtd_node = mtd_get_of_node(master); -+ if (!mtd_node) -+ return 0; -+ -+ ofpart_node = of_get_child_by_name(mtd_node, "partitions"); -+ if (!ofpart_node) { -+ /* -+ * We might get here even when ofpart isn't used at all (e.g., -+ * when using another parser), so don't be louder than -+ * KERN_DEBUG -+ */ -+ pr_debug("%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\n", -+ master->name, mtd_node); -+ ofpart_node = mtd_node; -+ dedicated = false; -+ } -+ -+ of_id = of_match_node(parse_ofpart_match_table, ofpart_node); -+ if (dedicated && !of_id) { -+ /* The 'partitions' subnode might be used by another parser */ -+ return 0; -+ } -+ -+ quirks = of_id ? of_id->data : NULL; -+ -+ /* First count the subnodes */ -+ nr_parts = 0; -+ for_each_child_of_node(ofpart_node, pp) { -+ if (!dedicated && node_has_compatible(pp)) -+ continue; -+ -+ nr_parts++; -+ } -+ -+ if (nr_parts == 0) -+ return 0; -+ -+ parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); -+ if (!parts) -+ return -ENOMEM; -+ -+ i = 0; -+ for_each_child_of_node(ofpart_node, pp) { -+ const __be32 *reg; -+ int len; -+ int a_cells, s_cells; -+ -+ if (!dedicated && node_has_compatible(pp)) -+ continue; -+ -+ reg = of_get_property(pp, "reg", &len); -+ if (!reg) { -+ if (dedicated) { -+ pr_debug("%s: ofpart partition %pOF (%pOF) missing reg property.\n", -+ master->name, pp, -+ mtd_node); -+ goto ofpart_fail; -+ } else { -+ nr_parts--; -+ continue; -+ } -+ } -+ -+ a_cells = of_n_addr_cells(pp); -+ s_cells = of_n_size_cells(pp); -+ if (len / 4 != a_cells + s_cells) { -+ pr_debug("%s: ofpart partition %pOF (%pOF) error parsing reg property.\n", -+ master->name, pp, -+ mtd_node); -+ goto ofpart_fail; -+ } -+ -+ parts[i].offset = of_read_number(reg, a_cells); -+ parts[i].size = of_read_number(reg + a_cells, s_cells); -+ parts[i].of_node = pp; -+ -+ partname = of_get_property(pp, "label", &len); -+ if (!partname) -+ partname = of_get_property(pp, "name", &len); -+ parts[i].name = partname; -+ -+ if (of_get_property(pp, "read-only", &len)) -+ parts[i].mask_flags |= MTD_WRITEABLE; -+ -+ if (of_get_property(pp, "lock", &len)) -+ parts[i].mask_flags |= MTD_POWERUP_LOCK; -+ -+ if (of_property_read_bool(pp, "slc-mode")) -+ parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION; -+ -+ i++; -+ } -+ -+ if (!nr_parts) -+ goto ofpart_none; -+ -+ if (quirks && quirks->post_parse) -+ quirks->post_parse(master, parts, nr_parts); -+ -+ *pparts = parts; -+ return nr_parts; -+ -+ofpart_fail: -+ pr_err("%s: error parsing ofpart partition %pOF (%pOF)\n", -+ master->name, pp, mtd_node); -+ ret = -EINVAL; -+ofpart_none: -+ of_node_put(pp); -+ kfree(parts); -+ return ret; -+} -+ -+static const struct of_device_id parse_ofpart_match_table[] = { -+ /* Generic */ -+ { .compatible = "fixed-partitions" }, -+ /* Customized */ -+ { .compatible = "brcm,bcm4908-partitions", .data = &bcm4908_partitions_quirks, }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, parse_ofpart_match_table); -+ -+static struct mtd_part_parser ofpart_parser = { -+ .parse_fn = parse_fixed_partitions, -+ .name = "fixed-partitions", -+ .of_match_table = parse_ofpart_match_table, -+}; -+ -+static int parse_ofoldpart_partitions(struct mtd_info *master, -+ const struct mtd_partition **pparts, -+ struct mtd_part_parser_data *data) -+{ -+ struct mtd_partition *parts; -+ struct device_node *dp; -+ int i, plen, nr_parts; -+ const struct { -+ __be32 offset, len; -+ } *part; -+ const char *names; -+ -+ /* Pull of_node from the master device node */ -+ dp = mtd_get_of_node(master); -+ if (!dp) -+ return 0; -+ -+ part = of_get_property(dp, "partitions", &plen); -+ if (!part) -+ return 0; /* No partitions found */ -+ -+ pr_warn("Device tree uses obsolete partition map binding: %pOF\n", dp); -+ -+ nr_parts = plen / sizeof(part[0]); -+ -+ parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); -+ if (!parts) -+ return -ENOMEM; -+ -+ names = of_get_property(dp, "partition-names", &plen); -+ -+ for (i = 0; i < nr_parts; i++) { -+ parts[i].offset = be32_to_cpu(part->offset); -+ parts[i].size = be32_to_cpu(part->len) & ~1; -+ /* bit 0 set signifies read only partition */ -+ if (be32_to_cpu(part->len) & 1) -+ parts[i].mask_flags = MTD_WRITEABLE; -+ -+ if (names && (plen > 0)) { -+ int len = strlen(names) + 1; -+ -+ parts[i].name = names; -+ plen -= len; -+ names += len; -+ } else { -+ parts[i].name = "unnamed"; -+ } -+ -+ part++; -+ } -+ -+ *pparts = parts; -+ return nr_parts; -+} -+ -+static struct mtd_part_parser ofoldpart_parser = { -+ .parse_fn = parse_ofoldpart_partitions, -+ .name = "ofoldpart", -+}; -+ -+static int __init ofpart_parser_init(void) -+{ -+ register_mtd_parser(&ofpart_parser); -+ register_mtd_parser(&ofoldpart_parser); -+ return 0; -+} -+ -+static void __exit ofpart_parser_exit(void) -+{ -+ deregister_mtd_parser(&ofpart_parser); -+ deregister_mtd_parser(&ofoldpart_parser); -+} -+ -+module_init(ofpart_parser_init); -+module_exit(ofpart_parser_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Parser for MTD partitioning information in device tree"); -+MODULE_AUTHOR("Vitaly Wool, David Gibson"); -+/* -+ * When MTD core cannot find the requested parser, it tries to load the module -+ * with the same name. Since we provide the ofoldpart parser, we should have -+ * the corresponding alias. -+ */ -+MODULE_ALIAS("fixed-partitions"); -+MODULE_ALIAS("ofoldpart"); diff --git a/target/linux/generic/backport-5.10/404-v5.13-mtd-parsers-ofpart-limit-parsing-of-deprecated-DT-sy.patch b/target/linux/generic/backport-5.10/404-v5.13-mtd-parsers-ofpart-limit-parsing-of-deprecated-DT-sy.patch deleted file mode 100644 index 55a91d7680..0000000000 --- a/target/linux/generic/backport-5.10/404-v5.13-mtd-parsers-ofpart-limit-parsing-of-deprecated-DT-sy.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 2d751203aacf86a1b301a188d8551c7da91043ab Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 2 Mar 2021 20:00:12 +0100 -Subject: [PATCH] mtd: parsers: ofpart: limit parsing of deprecated DT syntax -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -For backward compatibility ofpart still supports the old syntax like: -spi-flash@0 { - compatible = "jedec,spi-nor"; - reg = <0x0>; - - partition@0 { - label = "bootloader"; - reg = <0x0 0x100000>; - }; -}; -(without "partitions" subnode). - -There is no reason however to support nested partitions without a clear -"compatible" string like: -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x0 0x100000>; - - partition@0 { - label = "config"; - reg = <0x80000 0x80000>; - }; - }; -}; -(we never officially supported or documented that). - -Make sure ofpart doesn't attempt to parse above. - -Cc: Ansuel Smith -Signed-off-by: Rafał Miłecki -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210302190012.1255-1-zajec5@gmail.com ---- - drivers/mtd/parsers/ofpart_core.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/parsers/ofpart_core.c -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -53,7 +53,7 @@ static int parse_fixed_partitions(struct - return 0; - - ofpart_node = of_get_child_by_name(mtd_node, "partitions"); -- if (!ofpart_node) { -+ if (!ofpart_node && !master->parent) { - /* - * We might get here even when ofpart isn't used at all (e.g., - * when using another parser), so don't be louder than -@@ -64,6 +64,8 @@ static int parse_fixed_partitions(struct - ofpart_node = mtd_node; - dedicated = false; - } -+ if (!ofpart_node) -+ return 0; - - of_id = of_match_node(parse_ofpart_match_table, ofpart_node); - if (dedicated && !of_id) { diff --git a/target/linux/generic/backport-5.10/405-v5.13-mtd-parsers-ofpart-make-symbol-bcm4908_partitions_qu.patch b/target/linux/generic/backport-5.10/405-v5.13-mtd-parsers-ofpart-make-symbol-bcm4908_partitions_qu.patch deleted file mode 100644 index f1b778a6e1..0000000000 --- a/target/linux/generic/backport-5.10/405-v5.13-mtd-parsers-ofpart-make-symbol-bcm4908_partitions_qu.patch +++ /dev/null @@ -1,34 +0,0 @@ -From b87b6d2d6f540e29c3f98e1572d64e560d73d6c1 Mon Sep 17 00:00:00 2001 -From: Wei Yongjun -Date: Thu, 4 Mar 2021 06:46:00 +0000 -Subject: [PATCH] mtd: parsers: ofpart: make symbol 'bcm4908_partitions_quirks' - static - -The sparse tool complains as follows: - -drivers/mtd/parsers/ofpart_core.c:25:32: warning: - symbol 'bcm4908_partitions_quirks' was not declared. Should it be static? - -This symbol is not used outside of ofpart_core.c, so this -commit marks it static. - -Fixes: 457da931b608 ("mtd: parsers: ofpart: support BCM4908 fixed partitions") -Reported-by: Hulk Robot -Signed-off-by: Wei Yongjun -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210304064600.3279138-1-weiyongjun1@huawei.com ---- - drivers/mtd/parsers/ofpart_core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/parsers/ofpart_core.c -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -22,7 +22,7 @@ struct fixed_partitions_quirks { - int (*post_parse)(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts); - }; - --struct fixed_partitions_quirks bcm4908_partitions_quirks = { -+static struct fixed_partitions_quirks bcm4908_partitions_quirks = { - .post_parse = bcm4908_partitions_post_parse, - }; - diff --git a/target/linux/generic/backport-5.10/406-v5.13-0001-mtd-core-add-nvmem-cells-compatible-to-parse-mtd-as-.patch b/target/linux/generic/backport-5.10/406-v5.13-0001-mtd-core-add-nvmem-cells-compatible-to-parse-mtd-as-.patch deleted file mode 100644 index 28335cb71f..0000000000 --- a/target/linux/generic/backport-5.10/406-v5.13-0001-mtd-core-add-nvmem-cells-compatible-to-parse-mtd-as-.patch +++ /dev/null @@ -1,38 +0,0 @@ -From a5d83d6e2bc747b13f347962d4b335d70b23559b Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 12 Mar 2021 07:28:19 +0100 -Subject: [PATCH] mtd: core: add nvmem-cells compatible to parse mtd as nvmem - cells -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Partitions that contains the nvmem-cells compatible will register -their direct subonodes as nvmem cells and the node will be treated as a -nvmem provider. - -Signed-off-by: Ansuel Smith -Tested-by: Rafał Miłecki ---- - drivers/mtd/mtdcore.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -531,6 +531,7 @@ static int mtd_nvmem_reg_read(void *priv - - static int mtd_nvmem_add(struct mtd_info *mtd) - { -+ struct device_node *node = mtd_get_of_node(mtd); - struct nvmem_config config = {}; - - config.id = -1; -@@ -543,7 +544,7 @@ static int mtd_nvmem_add(struct mtd_info - config.stride = 1; - config.read_only = true; - config.root_only = true; -- config.no_of_node = true; -+ config.no_of_node = !of_device_is_compatible(node, "nvmem-cells"); - config.priv = mtd; - - mtd->nvmem = nvmem_register(&config); diff --git a/target/linux/generic/backport-5.10/406-v5.13-0002-dt-bindings-nvmem-drop-nodename-restriction.patch b/target/linux/generic/backport-5.10/406-v5.13-0002-dt-bindings-nvmem-drop-nodename-restriction.patch deleted file mode 100644 index 14ea3f6b8c..0000000000 --- a/target/linux/generic/backport-5.10/406-v5.13-0002-dt-bindings-nvmem-drop-nodename-restriction.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 42645976c3289b03a12f1bd2bc131fd98fc27170 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 12 Mar 2021 07:28:20 +0100 -Subject: [PATCH] devicetree: nvmem: nvmem: drop $nodename restriction - -Drop $nodename restriction as now mtd partition can also be used as -nvmem provider. - -Signed-off-by: Ansuel Smith ---- - Documentation/devicetree/bindings/nvmem/nvmem.yaml | 3 --- - 1 file changed, 3 deletions(-) - ---- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml -+++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml -@@ -20,9 +20,6 @@ description: | - storage device. - - properties: -- $nodename: -- pattern: "^(eeprom|efuse|nvram)(@.*|-[0-9a-f])*$" -- - "#address-cells": - const: 1 - diff --git a/target/linux/generic/backport-5.10/406-v5.13-0003-dt-bindings-mtd-Document-use-of-nvmem-cells-compatib.patch b/target/linux/generic/backport-5.10/406-v5.13-0003-dt-bindings-mtd-Document-use-of-nvmem-cells-compatib.patch deleted file mode 100644 index 0eb4c637cf..0000000000 --- a/target/linux/generic/backport-5.10/406-v5.13-0003-dt-bindings-mtd-Document-use-of-nvmem-cells-compatib.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 377aa0135dc8489312edd3184d143ce3a89ff7ee Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 12 Mar 2021 07:28:21 +0100 -Subject: [PATCH] dt-bindings: mtd: Document use of nvmem-cells compatible - -Document nvmem-cells compatible used to treat mtd partitions as a -nvmem provider. - -Signed-off-by: Ansuel Smith -Reviewed-by: Rob Herring ---- - .../bindings/mtd/partitions/nvmem-cells.yaml | 99 +++++++++++++++++++ - 1 file changed, 99 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mtd/partitions/nvmem-cells.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mtd/partitions/nvmem-cells.yaml -@@ -0,0 +1,99 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mtd/partitions/nvmem-cells.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Nvmem cells -+ -+description: | -+ Any partition containing the compatible "nvmem-cells" will register as a -+ nvmem provider. -+ Each direct subnodes represents a nvmem cell following the nvmem binding. -+ Nvmem binding to declare nvmem-cells can be found in: -+ Documentation/devicetree/bindings/nvmem/nvmem.yaml -+ -+maintainers: -+ - Ansuel Smith -+ -+allOf: -+ - $ref: /schemas/nvmem/nvmem.yaml# -+ -+properties: -+ compatible: -+ const: nvmem-cells -+ -+required: -+ - compatible -+ -+additionalProperties: true -+ -+examples: -+ - | -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ /* ... */ -+ -+ }; -+ art: art@1200000 { -+ compatible = "nvmem-cells"; -+ reg = <0x1200000 0x0140000>; -+ label = "art"; -+ read-only; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_gmac1: macaddr_gmac1@0 { -+ reg = <0x0 0x6>; -+ }; -+ -+ macaddr_gmac2: macaddr_gmac2@6 { -+ reg = <0x6 0x6>; -+ }; -+ -+ pre_cal_24g: pre_cal_24g@1000 { -+ reg = <0x1000 0x2f20>; -+ }; -+ -+ pre_cal_5g: pre_cal_5g@5000{ -+ reg = <0x5000 0x2f20>; -+ }; -+ }; -+ - | -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bootloader"; -+ reg = <0x000000 0x100000>; -+ read-only; -+ }; -+ -+ firmware@100000 { -+ compatible = "brcm,trx"; -+ label = "firmware"; -+ reg = <0x100000 0xe00000>; -+ }; -+ -+ calibration@f00000 { -+ compatible = "nvmem-cells"; -+ label = "calibration"; -+ reg = <0xf00000 0x100000>; -+ ranges = <0 0xf00000 0x100000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ wifi0@0 { -+ reg = <0x000000 0x080000>; -+ }; -+ -+ wifi1@80000 { -+ reg = <0x080000 0x080000>; -+ }; -+ }; -+ }; diff --git a/target/linux/generic/backport-5.10/407-v5.13-0001-dt-bindings-mtd-add-binding-for-Linksys-Northstar-pa.patch b/target/linux/generic/backport-5.10/407-v5.13-0001-dt-bindings-mtd-add-binding-for-Linksys-Northstar-pa.patch deleted file mode 100644 index 35a4afd67b..0000000000 --- a/target/linux/generic/backport-5.10/407-v5.13-0001-dt-bindings-mtd-add-binding-for-Linksys-Northstar-pa.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 2fa7294175c76e1ec568aa75c1891fd908728c8d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 12 Mar 2021 14:49:18 +0100 -Subject: [PATCH] dt-bindings: mtd: add binding for Linksys Northstar - partitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Linksys on Broadcom Northstar devices uses fixed flash layout with -multiple firmware partitions. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Rob Herring -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210312134919.7767-1-zajec5@gmail.com ---- - .../mtd/partitions/linksys,ns-partitions.yaml | 74 +++++++++++++++++++ - 1 file changed, 74 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mtd/partitions/linksys,ns-partitions.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mtd/partitions/linksys,ns-partitions.yaml -@@ -0,0 +1,74 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mtd/partitions/linksys,ns-partitions.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Linksys Northstar partitioning -+ -+description: | -+ Linksys devices based on Broadcom Northstar architecture often use two -+ firmware partitions. One is used for regular booting, the other is treated as -+ fallback. -+ -+ This binding allows defining all fixed partitions and marking those containing -+ firmware. System can use that information e.g. for booting or flashing -+ purposes. -+ -+maintainers: -+ - Rafał Miłecki -+ -+properties: -+ compatible: -+ const: linksys,ns-partitions -+ -+ "#address-cells": -+ enum: [ 1, 2 ] -+ -+ "#size-cells": -+ enum: [ 1, 2 ] -+ -+patternProperties: -+ "^partition@[0-9a-f]+$": -+ $ref: "partition.yaml#" -+ properties: -+ compatible: -+ items: -+ - const: linksys,ns-firmware -+ - const: brcm,trx -+ unevaluatedProperties: false -+ -+required: -+ - "#address-cells" -+ - "#size-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ partitions { -+ compatible = "linksys,ns-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "boot"; -+ reg = <0x0 0x100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "nvram"; -+ reg = <0x100000 0x100000>; -+ }; -+ -+ partition@200000 { -+ compatible = "linksys,ns-firmware", "brcm,trx"; -+ reg = <0x200000 0xf00000>; -+ }; -+ -+ partition@1100000 { -+ compatible = "linksys,ns-firmware", "brcm,trx"; -+ reg = <0x1100000 0xf00000>; -+ }; -+ }; diff --git a/target/linux/generic/backport-5.10/407-v5.13-0002-mtd-parsers-ofpart-support-Linksys-Northstar-partiti.patch b/target/linux/generic/backport-5.10/407-v5.13-0002-mtd-parsers-ofpart-support-Linksys-Northstar-partiti.patch deleted file mode 100644 index f317889785..0000000000 --- a/target/linux/generic/backport-5.10/407-v5.13-0002-mtd-parsers-ofpart-support-Linksys-Northstar-partiti.patch +++ /dev/null @@ -1,156 +0,0 @@ -From 7134a2d026d942210b4d26d6059c9d979ca7866e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 12 Mar 2021 14:49:19 +0100 -Subject: [PATCH] mtd: parsers: ofpart: support Linksys Northstar partitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This allows extending ofpart parser with support for Linksys Northstar -devices. That support uses recently added quirks mechanism. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210312134919.7767-2-zajec5@gmail.com ---- - drivers/mtd/parsers/Kconfig | 10 +++++ - drivers/mtd/parsers/Makefile | 1 + - drivers/mtd/parsers/ofpart_core.c | 6 +++ - drivers/mtd/parsers/ofpart_linksys_ns.c | 50 +++++++++++++++++++++++++ - drivers/mtd/parsers/ofpart_linksys_ns.h | 18 +++++++++ - 5 files changed, 85 insertions(+) - create mode 100644 drivers/mtd/parsers/ofpart_linksys_ns.c - create mode 100644 drivers/mtd/parsers/ofpart_linksys_ns.h - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -76,6 +76,16 @@ config MTD_OF_PARTS_BCM4908 - that can have multiple "firmware" partitions. It takes care of - finding currently used one and backup ones. - -+config MTD_OF_PARTS_LINKSYS_NS -+ bool "Linksys Northstar partitioning support" -+ depends on MTD_OF_PARTS && (ARCH_BCM_5301X || ARCH_BCM4908 || COMPILE_TEST) -+ default ARCH_BCM_5301X -+ help -+ This provides partitions parser for Linksys devices based on Broadcom -+ Northstar architecture. Linksys commonly uses fixed flash layout with -+ two "firmware" partitions. Currently used firmware has to be detected -+ using CFE environment variable. -+ - config MTD_PARSER_IMAGETAG - tristate "Parser for BCM963XX Image Tag format partitions" - depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -6,6 +6,7 @@ obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdl - obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o - ofpart-y += ofpart_core.o - ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908) += ofpart_bcm4908.o -+ofpart-$(CONFIG_MTD_OF_PARTS_LINKSYS_NS)+= ofpart_linksys_ns.o - obj-$(CONFIG_MTD_PARSER_IMAGETAG) += parser_imagetag.o - obj-$(CONFIG_MTD_AFS_PARTS) += afs.o - obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o ---- a/drivers/mtd/parsers/ofpart_core.c -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -17,6 +17,7 @@ - #include - - #include "ofpart_bcm4908.h" -+#include "ofpart_linksys_ns.h" - - struct fixed_partitions_quirks { - int (*post_parse)(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts); -@@ -26,6 +27,10 @@ static struct fixed_partitions_quirks bc - .post_parse = bcm4908_partitions_post_parse, - }; - -+static struct fixed_partitions_quirks linksys_ns_partitions_quirks = { -+ .post_parse = linksys_ns_partitions_post_parse, -+}; -+ - static const struct of_device_id parse_ofpart_match_table[]; - - static bool node_has_compatible(struct device_node *pp) -@@ -167,6 +172,7 @@ static const struct of_device_id parse_o - { .compatible = "fixed-partitions" }, - /* Customized */ - { .compatible = "brcm,bcm4908-partitions", .data = &bcm4908_partitions_quirks, }, -+ { .compatible = "linksys,ns-partitions", .data = &linksys_ns_partitions_quirks, }, - {}, - }; - MODULE_DEVICE_TABLE(of, parse_ofpart_match_table); ---- /dev/null -+++ b/drivers/mtd/parsers/ofpart_linksys_ns.c -@@ -0,0 +1,50 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2021 Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+ -+#include "ofpart_linksys_ns.h" -+ -+#define NVRAM_BOOT_PART "bootpartition" -+ -+static int ofpart_linksys_ns_bootpartition(void) -+{ -+ char buf[4]; -+ int bootpartition; -+ -+ /* Check CFE environment variable */ -+ if (bcm47xx_nvram_getenv(NVRAM_BOOT_PART, buf, sizeof(buf)) > 0) { -+ if (!kstrtoint(buf, 0, &bootpartition)) -+ return bootpartition; -+ pr_warn("Failed to parse %s value \"%s\"\n", NVRAM_BOOT_PART, -+ buf); -+ } else { -+ pr_warn("Failed to get NVRAM \"%s\"\n", NVRAM_BOOT_PART); -+ } -+ -+ return 0; -+} -+ -+int linksys_ns_partitions_post_parse(struct mtd_info *mtd, -+ struct mtd_partition *parts, -+ int nr_parts) -+{ -+ int bootpartition = ofpart_linksys_ns_bootpartition(); -+ int trx_idx = 0; -+ int i; -+ -+ for (i = 0; i < nr_parts; i++) { -+ if (of_device_is_compatible(parts[i].of_node, "linksys,ns-firmware")) { -+ if (trx_idx++ == bootpartition) -+ parts[i].name = "firmware"; -+ else -+ parts[i].name = "backup"; -+ } -+ } -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/mtd/parsers/ofpart_linksys_ns.h -@@ -0,0 +1,18 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+#ifndef __OFPART_LINKSYS_NS_H -+#define __OFPART_LINKSYS_NS_H -+ -+#ifdef CONFIG_MTD_OF_PARTS_LINKSYS_NS -+int linksys_ns_partitions_post_parse(struct mtd_info *mtd, -+ struct mtd_partition *parts, -+ int nr_parts); -+#else -+static inline int linksys_ns_partitions_post_parse(struct mtd_info *mtd, -+ struct mtd_partition *parts, -+ int nr_parts) -+{ -+ return -EOPNOTSUPP; -+} -+#endif -+ -+#endif diff --git a/target/linux/generic/backport-5.10/408-v5.13-mtd-cfi_cmdset_0002-Disable-buffered-writes-for-AMD.patch b/target/linux/generic/backport-5.10/408-v5.13-mtd-cfi_cmdset_0002-Disable-buffered-writes-for-AMD.patch deleted file mode 100644 index 8aba0cab22..0000000000 --- a/target/linux/generic/backport-5.10/408-v5.13-mtd-cfi_cmdset_0002-Disable-buffered-writes-for-AMD.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 7e4404113686868858a34210c28ae122e967aa64 Mon Sep 17 00:00:00 2001 -From: Mauri Sandberg -Date: Tue, 9 Mar 2021 19:48:59 +0200 -Subject: [PATCH] mtd: cfi_cmdset_0002: Disable buffered writes for AMD chip - 0x2201 - -Buffer writes do not work with AMD chip 0x2201. The chip in question -is a AMD/Spansion/Cypress Semiconductor S29GL256N and datasheet [1] -talks about writing buffers being possible. While waiting for a neater -solution resort to writing word-sized chunks only. - -Without the patch kernel logs will be flooded with entries like below: - -jffs2_scan_eraseblock(): End of filesystem marker found at 0x0 -jffs2_build_filesystem(): unlocking the mtd device... -done. -jffs2_build_filesystem(): erasing all blocks after the end marker... -MTD do_write_buffer_wait(): software timeout, address:0x01ec000a. -jffs2: Write clean marker to block at 0x01920000 failed: -5 -MTD do_write_buffer_wait(): software timeout, address:0x01e2000a. -jffs2: Write clean marker to block at 0x01880000 failed: -5 -MTD do_write_buffer_wait(): software timeout, address:0x01e0000a. -jffs2: Write clean marker to block at 0x01860000 failed: -5 -MTD do_write_buffer_wait(): software timeout, address:0x01dc000a. -jffs2: Write clean marker to block at 0x01820000 failed: -5 -MTD do_write_buffer_wait(): software timeout, address:0x01da000a. -jffs2: Write clean marker to block at 0x01800000 failed: -5 -... - -Tested on a Buffalo wzr-hp-g300nh running kernel 5.10.16. - -[1] https://www.cypress.com/file/219941/download -or https://datasheetspdf.com/pdf-file/565708/SPANSION/S29GL256N/1 - -Signed-off-by: Mauri Sandberg -Signed-off-by: Vignesh Raghavendra -Link: https://lore.kernel.org/r/20210309174859.362060-1-sandberg@mailfence.com ---- - drivers/mtd/chips/cfi_cmdset_0002.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -276,6 +276,10 @@ static void fixup_use_write_buffers(stru - { - struct map_info *map = mtd->priv; - struct cfi_private *cfi = map->fldrv_priv; -+ -+ if (cfi->mfr == CFI_MFR_AMD && cfi->id == 0x2201) -+ return; -+ - if (cfi->cfiq->BufWriteTimeoutTyp) { - pr_debug("Using buffer write method\n"); - mtd->_write = cfi_amdstd_write_buffers; diff --git a/target/linux/generic/backport-5.10/409-v5.14-0001-dt-bindings-mtd-brcm-trx-Add-brcm-trx-magic.patch b/target/linux/generic/backport-5.10/409-v5.14-0001-dt-bindings-mtd-brcm-trx-Add-brcm-trx-magic.patch deleted file mode 100644 index 1f34652141..0000000000 --- a/target/linux/generic/backport-5.10/409-v5.14-0001-dt-bindings-mtd-brcm-trx-Add-brcm-trx-magic.patch +++ /dev/null @@ -1,32 +0,0 @@ -From a4d82940ff85a7e307953dfa715f65d5ab487e10 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sun, 18 Apr 2021 23:46:14 +0200 -Subject: dt-bindings: mtd: brcm,trx: Add brcm,trx-magic - -This adds the description of an additional property which allows to -specify a custom partition parser magic to detect a trx partition. -Buffalo has multiple device which are using the trx format, but with -different magic values. - -Signed-off-by: Hauke Mehrtens -Acked-by: Rob Herring -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210418214616.239574-2-hauke@hauke-m.de ---- - .../devicetree/bindings/mtd/partitions/brcm,trx.txt | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt -+++ b/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt -@@ -28,6 +28,11 @@ detected by a software parsing TRX heade - Required properties: - - compatible : (required) must be "brcm,trx" - -+Optional properties: -+ -+- brcm,trx-magic: TRX magic, if it is different from the default magic -+ 0x30524448 as a u32. -+ - Example: - - flash@0 { diff --git a/target/linux/generic/backport-5.10/409-v5.14-0002-mtd-parsers-trx-Allow-to-specify-brcm-trx-magic-in-D.patch b/target/linux/generic/backport-5.10/409-v5.14-0002-mtd-parsers-trx-Allow-to-specify-brcm-trx-magic-in-D.patch deleted file mode 100644 index de2d914852..0000000000 --- a/target/linux/generic/backport-5.10/409-v5.14-0002-mtd-parsers-trx-Allow-to-specify-brcm-trx-magic-in-D.patch +++ /dev/null @@ -1,50 +0,0 @@ -From d7f7e04f8b67571a4bf5a0dcd4f9da4214f5262c Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sun, 18 Apr 2021 23:46:15 +0200 -Subject: mtd: parsers: trx: Allow to specify brcm, trx-magic in DT - -Buffalo uses a different TRX magic for every device, to be able to use -this trx parser, make it possible to specify the TRX magic in device -tree. If no TRX magic is specified in device tree, the standard value -will be used. This value should only be specified if a vendor chooses to -use a non standard TRX magic. - -Signed-off-by: Hauke Mehrtens -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210418214616.239574-3-hauke@hauke-m.de ---- - drivers/mtd/parsers/parser_trx.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/parsers/parser_trx.c -+++ b/drivers/mtd/parsers/parser_trx.c -@@ -51,13 +51,20 @@ static int parser_trx_parse(struct mtd_i - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) - { -+ struct device_node *np = mtd_get_of_node(mtd); - struct mtd_partition *parts; - struct mtd_partition *part; - struct trx_header trx; - size_t bytes_read; - uint8_t curr_part = 0, i = 0; -+ uint32_t trx_magic = TRX_MAGIC; - int err; - -+ /* Get different magic from device tree if specified */ -+ err = of_property_read_u32(np, "brcm,trx-magic", &trx_magic); -+ if (err != 0 && err != -EINVAL) -+ pr_err("failed to parse \"brcm,trx-magic\" DT attribute, using default: %d\n", err); -+ - parts = kcalloc(TRX_PARSER_MAX_PARTS, sizeof(struct mtd_partition), - GFP_KERNEL); - if (!parts) -@@ -70,7 +77,7 @@ static int parser_trx_parse(struct mtd_i - return err; - } - -- if (trx.magic != TRX_MAGIC) { -+ if (trx.magic != trx_magic) { - kfree(parts); - return -ENOENT; - } diff --git a/target/linux/generic/backport-5.10/409-v5.14-0003-mtd-parsers-trx-Allow-to-use-TRX-parser-on-Mediatek-.patch b/target/linux/generic/backport-5.10/409-v5.14-0003-mtd-parsers-trx-Allow-to-use-TRX-parser-on-Mediatek-.patch deleted file mode 100644 index faac535270..0000000000 --- a/target/linux/generic/backport-5.10/409-v5.14-0003-mtd-parsers-trx-Allow-to-use-TRX-parser-on-Mediatek-.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 81bb218c829246962a6327c64eec18ddcc049936 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sun, 18 Apr 2021 23:46:16 +0200 -Subject: mtd: parsers: trx: Allow to use TRX parser on Mediatek SoCs - -Buffalo uses the TRX partition format also on Mediatek MT7622 SoCs. - -Signed-off-by: Hauke Mehrtens -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210418214616.239574-4-hauke@hauke-m.de ---- - drivers/mtd/parsers/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -115,7 +115,7 @@ config MTD_AFS_PARTS - - config MTD_PARSER_TRX - tristate "Parser for TRX format partitions" -- depends on MTD && (BCM47XX || ARCH_BCM_5301X || COMPILE_TEST) -+ depends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || COMPILE_TEST) - help - TRX is a firmware format used by Broadcom on their devices. It - may contain up to 3/4 partitions (depending on the version). diff --git a/target/linux/generic/backport-5.10/410-mtd-next-mtd-parsers-trx-allow-to-use-on-MediaTek-MIPS-SoCs.patch b/target/linux/generic/backport-5.10/410-mtd-next-mtd-parsers-trx-allow-to-use-on-MediaTek-MIPS-SoCs.patch deleted file mode 100644 index 5c49841760..0000000000 --- a/target/linux/generic/backport-5.10/410-mtd-next-mtd-parsers-trx-allow-to-use-on-MediaTek-MIPS-SoCs.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 2365f91c861cbfeef7141c69842848c7b2d3c2db Mon Sep 17 00:00:00 2001 -From: INAGAKI Hiroshi -Date: Sun, 13 Feb 2022 15:40:44 +0900 -Subject: [PATCH] mtd: parsers: trx: allow to use on MediaTek MIPS SoCs - -Buffalo sells some router devices which have trx-formatted firmware, -based on MediaTek MIPS SoCs. To use parser_trx on those devices, add -"RALINK" to dependency and allow to compile for MediaTek MIPS SoCs. - -examples: - -- WCR-1166DS (MT7628) -- WSR-1166DHP (MT7621) -- WSR-2533DHP (MT7621) - -Signed-off-by: INAGAKI Hiroshi -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220213064045.1781-1-musashino.open@gmail.com ---- - drivers/mtd/parsers/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -115,7 +115,7 @@ config MTD_AFS_PARTS - - config MTD_PARSER_TRX - tristate "Parser for TRX format partitions" -- depends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || COMPILE_TEST) -+ depends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || RALINK || COMPILE_TEST) - help - TRX is a firmware format used by Broadcom on their devices. It - may contain up to 3/4 partitions (depending on the version). diff --git a/target/linux/generic/backport-5.10/411-v6.0-mtd-parsers-add-support-for-Sercomm-partitions.patch b/target/linux/generic/backport-5.10/411-v6.0-mtd-parsers-add-support-for-Sercomm-partitions.patch deleted file mode 100644 index 5ed6fd1b3b..0000000000 --- a/target/linux/generic/backport-5.10/411-v6.0-mtd-parsers-add-support-for-Sercomm-partitions.patch +++ /dev/null @@ -1,301 +0,0 @@ -From 9b78ef0c7997052e9eaa0f7a4513d546fa17358c Mon Sep 17 00:00:00 2001 -From: Mikhail Zhilkin -Date: Sun, 29 May 2022 11:07:14 +0000 -Subject: [PATCH] mtd: parsers: add support for Sercomm partitions - -This adds an MTD partition parser for the Sercomm partition table that -is used in some Beeline, Netgear and Sercomm routers. - -The Sercomm partition map table contains real partition offsets, which -may differ from device to device depending on the number and location of -bad blocks on NAND. - -Original patch (proposed by NOGUCHI Hiroshi): -Link: https://github.com/openwrt/openwrt/pull/1318#issuecomment-420607394 - -Signed-off-by: NOGUCHI Hiroshi -Signed-off-by: Mikhail Zhilkin -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220529110714.189732-1-csharper2005@gmail.com ---- - drivers/mtd/parsers/Kconfig | 9 ++ - drivers/mtd/parsers/Makefile | 1 + - drivers/mtd/parsers/scpart.c | 248 +++++++++++++++++++++++++++++++++++ - 3 files changed, 258 insertions(+) - create mode 100644 drivers/mtd/parsers/scpart.c - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -179,3 +179,12 @@ config MTD_REDBOOT_PARTS_READONLY - 'FIS directory' images, enable this option. - - endif # MTD_REDBOOT_PARTS -+ -+config MTD_SERCOMM_PARTS -+ tristate "Sercomm partition table parser" -+ depends on MTD && RALINK -+ help -+ This provides partitions table parser for devices with Sercomm -+ partition map. This partition table contains real partition -+ offsets, which may differ from device to device depending on the -+ number and location of bad blocks on NAND. ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -10,5 +10,6 @@ ofpart-$(CONFIG_MTD_OF_PARTS_LINKSYS_NS) - obj-$(CONFIG_MTD_PARSER_IMAGETAG) += parser_imagetag.o - obj-$(CONFIG_MTD_AFS_PARTS) += afs.o - obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o -+obj-$(CONFIG_MTD_SERCOMM_PARTS) += scpart.o - obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o - obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o ---- /dev/null -+++ b/drivers/mtd/parsers/scpart.c -@@ -0,0 +1,248 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * drivers/mtd/scpart.c: Sercomm Partition Parser -+ * -+ * Copyright (C) 2018 NOGUCHI Hiroshi -+ * Copyright (C) 2022 Mikhail Zhilkin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define MOD_NAME "scpart" -+ -+#ifdef pr_fmt -+#undef pr_fmt -+#endif -+ -+#define pr_fmt(fmt) MOD_NAME ": " fmt -+ -+#define ID_ALREADY_FOUND 0xffffffffUL -+ -+#define MAP_OFFS_IN_BLK 0x800 -+#define MAP_MIRROR_NUM 2 -+ -+static const char sc_part_magic[] = { -+ 'S', 'C', 'F', 'L', 'M', 'A', 'P', 'O', 'K', '\0', -+}; -+#define PART_MAGIC_LEN sizeof(sc_part_magic) -+ -+/* assumes that all fields are set by CPU native endian */ -+struct sc_part_desc { -+ uint32_t part_id; -+ uint32_t part_offs; -+ uint32_t part_bytes; -+}; -+ -+static uint32_t scpart_desc_is_valid(struct sc_part_desc *pdesc) -+{ -+ return ((pdesc->part_id != 0xffffffffUL) && -+ (pdesc->part_offs != 0xffffffffUL) && -+ (pdesc->part_bytes != 0xffffffffUL)); -+} -+ -+static int scpart_scan_partmap(struct mtd_info *master, loff_t partmap_offs, -+ struct sc_part_desc **ppdesc) -+{ -+ int cnt = 0; -+ int res = 0; -+ int res2; -+ loff_t offs; -+ size_t retlen; -+ struct sc_part_desc *pdesc = NULL; -+ struct sc_part_desc *tmpdesc; -+ uint8_t *buf; -+ -+ buf = kzalloc(master->erasesize, GFP_KERNEL); -+ if (!buf) { -+ res = -ENOMEM; -+ goto out; -+ } -+ -+ res2 = mtd_read(master, partmap_offs, master->erasesize, &retlen, buf); -+ if (res2 || retlen != master->erasesize) { -+ res = -EIO; -+ goto free; -+ } -+ -+ for (offs = MAP_OFFS_IN_BLK; -+ offs < master->erasesize - sizeof(*tmpdesc); -+ offs += sizeof(*tmpdesc)) { -+ tmpdesc = (struct sc_part_desc *)&buf[offs]; -+ if (!scpart_desc_is_valid(tmpdesc)) -+ break; -+ cnt++; -+ } -+ -+ if (cnt > 0) { -+ int bytes = cnt * sizeof(*pdesc); -+ -+ pdesc = kcalloc(cnt, sizeof(*pdesc), GFP_KERNEL); -+ if (!pdesc) { -+ res = -ENOMEM; -+ goto free; -+ } -+ memcpy(pdesc, &(buf[MAP_OFFS_IN_BLK]), bytes); -+ -+ *ppdesc = pdesc; -+ res = cnt; -+ } -+ -+free: -+ kfree(buf); -+ -+out: -+ return res; -+} -+ -+static int scpart_find_partmap(struct mtd_info *master, -+ struct sc_part_desc **ppdesc) -+{ -+ int magic_found = 0; -+ int res = 0; -+ int res2; -+ loff_t offs = 0; -+ size_t retlen; -+ uint8_t rdbuf[PART_MAGIC_LEN]; -+ -+ while ((magic_found < MAP_MIRROR_NUM) && -+ (offs < master->size) && -+ !mtd_block_isbad(master, offs)) { -+ res2 = mtd_read(master, offs, PART_MAGIC_LEN, &retlen, rdbuf); -+ if (res2 || retlen != PART_MAGIC_LEN) { -+ res = -EIO; -+ goto out; -+ } -+ if (!memcmp(rdbuf, sc_part_magic, PART_MAGIC_LEN)) { -+ pr_debug("Signature found at 0x%llx\n", offs); -+ magic_found++; -+ res = scpart_scan_partmap(master, offs, ppdesc); -+ if (res > 0) -+ goto out; -+ } -+ offs += master->erasesize; -+ } -+ -+out: -+ if (res > 0) -+ pr_info("Valid 'SC PART MAP' (%d partitions) found at 0x%llx\n", res, offs); -+ else -+ pr_info("No valid 'SC PART MAP' was found\n"); -+ -+ return res; -+} -+ -+static int scpart_parse(struct mtd_info *master, -+ const struct mtd_partition **pparts, -+ struct mtd_part_parser_data *data) -+{ -+ const char *partname; -+ int n; -+ int nr_scparts; -+ int nr_parts = 0; -+ int res = 0; -+ struct sc_part_desc *scpart_map = NULL; -+ struct mtd_partition *parts = NULL; -+ struct device_node *mtd_node; -+ struct device_node *ofpart_node; -+ struct device_node *pp; -+ -+ mtd_node = mtd_get_of_node(master); -+ if (!mtd_node) { -+ res = -ENOENT; -+ goto out; -+ } -+ -+ ofpart_node = of_get_child_by_name(mtd_node, "partitions"); -+ if (!ofpart_node) { -+ pr_info("%s: 'partitions' subnode not found on %pOF.\n", -+ master->name, mtd_node); -+ res = -ENOENT; -+ goto out; -+ } -+ -+ nr_scparts = scpart_find_partmap(master, &scpart_map); -+ if (nr_scparts <= 0) { -+ pr_info("No any partitions was found in 'SC PART MAP'.\n"); -+ res = -ENOENT; -+ goto free; -+ } -+ -+ parts = kcalloc(of_get_child_count(ofpart_node), sizeof(*parts), -+ GFP_KERNEL); -+ if (!parts) { -+ res = -ENOMEM; -+ goto free; -+ } -+ -+ for_each_child_of_node(ofpart_node, pp) { -+ u32 scpart_id; -+ -+ if (of_property_read_u32(pp, "sercomm,scpart-id", &scpart_id)) -+ continue; -+ -+ for (n = 0 ; n < nr_scparts ; n++) -+ if ((scpart_map[n].part_id != ID_ALREADY_FOUND) && -+ (scpart_id == scpart_map[n].part_id)) -+ break; -+ if (n >= nr_scparts) -+ /* not match */ -+ continue; -+ -+ /* add the partition found in OF into MTD partition array */ -+ parts[nr_parts].offset = scpart_map[n].part_offs; -+ parts[nr_parts].size = scpart_map[n].part_bytes; -+ parts[nr_parts].of_node = pp; -+ -+ if (!of_property_read_string(pp, "label", &partname)) -+ parts[nr_parts].name = partname; -+ if (of_property_read_bool(pp, "read-only")) -+ parts[nr_parts].mask_flags |= MTD_WRITEABLE; -+ if (of_property_read_bool(pp, "lock")) -+ parts[nr_parts].mask_flags |= MTD_POWERUP_LOCK; -+ -+ /* mark as 'done' */ -+ scpart_map[n].part_id = ID_ALREADY_FOUND; -+ -+ nr_parts++; -+ } -+ -+ if (nr_parts > 0) { -+ *pparts = parts; -+ res = nr_parts; -+ } else -+ pr_info("No partition in OF matches partition ID with 'SC PART MAP'.\n"); -+ -+ of_node_put(pp); -+ -+free: -+ kfree(scpart_map); -+ if (res <= 0) -+ kfree(parts); -+ -+out: -+ return res; -+} -+ -+static const struct of_device_id scpart_parser_of_match_table[] = { -+ { .compatible = "sercomm,sc-partitions" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, scpart_parser_of_match_table); -+ -+static struct mtd_part_parser scpart_parser = { -+ .parse_fn = scpart_parse, -+ .name = "scpart", -+ .of_match_table = scpart_parser_of_match_table, -+}; -+module_mtd_part_parser(scpart_parser); -+ -+/* mtd parsers will request the module by parser name */ -+MODULE_ALIAS("scpart"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("NOGUCHI Hiroshi "); -+MODULE_AUTHOR("Mikhail Zhilkin "); -+MODULE_DESCRIPTION("Sercomm partition parser"); diff --git a/target/linux/generic/backport-5.10/412-v5.19-mtd-call-of_platform_populate-for-MTD-partitions.patch b/target/linux/generic/backport-5.10/412-v5.19-mtd-call-of_platform_populate-for-MTD-partitions.patch deleted file mode 100644 index aaeb087c89..0000000000 --- a/target/linux/generic/backport-5.10/412-v5.19-mtd-call-of_platform_populate-for-MTD-partitions.patch +++ /dev/null @@ -1,72 +0,0 @@ -From bcdf0315a61a29eb753a607d3a85a4032de72d94 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 10 May 2022 15:12:59 +0200 -Subject: [PATCH] mtd: call of_platform_populate() for MTD partitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Until this change MTD subsystem supported handling partitions only with -MTD partitions parsers. That's a specific / limited API designed around -partitions. - -Some MTD partitions may however require different handling. They may -contain specific data that needs to be parsed and somehow extracted. For -that purpose MTD subsystem should allow binding of standard platform -drivers. - -An example can be U-Boot (sub)partition with environment variables. -There exist a "u-boot,env" DT binding for MTD (sub)partition that -requires an NVMEM driver. - -Ref: 5db1c2dbc04c ("dt-bindings: nvmem: add U-Boot environment variables binding") -Signed-off-by: Rafał Miłecki -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220510131259.555-1-zajec5@gmail.com ---- - drivers/mtd/mtdpart.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/mtd/mtdpart.c -+++ b/drivers/mtd/mtdpart.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - - #include "mtdcore.h" - -@@ -578,10 +579,16 @@ static int mtd_part_of_parse(struct mtd_ - struct mtd_part_parser *parser; - struct device_node *np; - struct property *prop; -+ struct device *dev; - const char *compat; - const char *fixed = "fixed-partitions"; - int ret, err = 0; - -+ dev = &master->dev; -+ /* Use parent device (controller) if the top level MTD is not registered */ -+ if (!IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) && !mtd_is_partition(master)) -+ dev = master->dev.parent; -+ - np = mtd_get_of_node(master); - if (mtd_is_partition(master)) - of_node_get(np); -@@ -594,6 +601,7 @@ static int mtd_part_of_parse(struct mtd_ - continue; - ret = mtd_part_do_parse(parser, master, pparts, NULL); - if (ret > 0) { -+ of_platform_populate(np, NULL, NULL, dev); - of_node_put(np); - return ret; - } -@@ -601,6 +609,7 @@ static int mtd_part_of_parse(struct mtd_ - if (ret < 0 && !err) - err = ret; - } -+ of_platform_populate(np, NULL, NULL, dev); - of_node_put(np); - - /* diff --git a/target/linux/generic/backport-5.10/413-v6.0-mtd-next-mtd-core-introduce-of-support-for-dynamic-partitions.patch b/target/linux/generic/backport-5.10/413-v6.0-mtd-next-mtd-core-introduce-of-support-for-dynamic-partitions.patch deleted file mode 100644 index e71098d563..0000000000 --- a/target/linux/generic/backport-5.10/413-v6.0-mtd-next-mtd-core-introduce-of-support-for-dynamic-partitions.patch +++ /dev/null @@ -1,106 +0,0 @@ -From ad9b10d1eaada169bd764abcab58f08538877e26 Mon Sep 17 00:00:00 2001 -From: Christian Marangi -Date: Wed, 22 Jun 2022 03:06:28 +0200 -Subject: mtd: core: introduce of support for dynamic partitions - -We have many parser that register mtd partitions at runtime. One example -is the cmdlinepart or the smem-part parser where the compatible is defined -in the dts and the partitions gets detected and registered by the -parser. This is problematic for the NVMEM subsystem that requires an OF -node to detect NVMEM cells. - -To fix this problem, introduce an additional logic that will try to -assign an OF node to the MTD if declared. - -On MTD addition, it will be checked if the MTD has an OF node and if -not declared will check if a partition with the same label / node name is -declared in DTS. If an exact match is found, the partition dynamically -allocated by the parser will have a connected OF node. - -The NVMEM subsystem will detect the OF node and register any NVMEM cells -declared statically in the DTS. - -Signed-off-by: Christian Marangi -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220622010628.30414-4-ansuelsmth@gmail.com ---- - drivers/mtd/mtdcore.c | 61 +++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 61 insertions(+) - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -561,6 +561,66 @@ static int mtd_nvmem_add(struct mtd_info - return 0; - } - -+static void mtd_check_of_node(struct mtd_info *mtd) -+{ -+ struct device_node *partitions, *parent_dn, *mtd_dn = NULL; -+ const char *pname, *prefix = "partition-"; -+ int plen, mtd_name_len, offset, prefix_len; -+ struct mtd_info *parent; -+ bool found = false; -+ -+ /* Check if MTD already has a device node */ -+ if (dev_of_node(&mtd->dev)) -+ return; -+ -+ /* Check if a partitions node exist */ -+ parent = mtd->parent; -+ parent_dn = dev_of_node(&parent->dev); -+ if (!parent_dn) -+ return; -+ -+ partitions = of_get_child_by_name(parent_dn, "partitions"); -+ if (!partitions) -+ goto exit_parent; -+ -+ prefix_len = strlen(prefix); -+ mtd_name_len = strlen(mtd->name); -+ -+ /* Search if a partition is defined with the same name */ -+ for_each_child_of_node(partitions, mtd_dn) { -+ offset = 0; -+ -+ /* Skip partition with no/wrong prefix */ -+ if (!of_node_name_prefix(mtd_dn, "partition-")) -+ continue; -+ -+ /* Label have priority. Check that first */ -+ if (of_property_read_string(mtd_dn, "label", &pname)) { -+ of_property_read_string(mtd_dn, "name", &pname); -+ offset = prefix_len; -+ } -+ -+ plen = strlen(pname) - offset; -+ if (plen == mtd_name_len && -+ !strncmp(mtd->name, pname + offset, plen)) { -+ found = true; -+ break; -+ } -+ } -+ -+ if (!found) -+ goto exit_partitions; -+ -+ /* Set of_node only for nvmem */ -+ if (of_device_is_compatible(mtd_dn, "nvmem-cells")) -+ mtd_set_of_node(mtd, mtd_dn); -+ -+exit_partitions: -+ of_node_put(partitions); -+exit_parent: -+ of_node_put(parent_dn); -+} -+ - /** - * add_mtd_device - register an MTD device - * @mtd: pointer to new MTD device info structure -@@ -666,6 +726,7 @@ int add_mtd_device(struct mtd_info *mtd) - mtd->dev.devt = MTD_DEVT(i); - dev_set_name(&mtd->dev, "mtd%d", i); - dev_set_drvdata(&mtd->dev, mtd); -+ mtd_check_of_node(mtd); - of_node_get(mtd_get_of_node(mtd)); - error = device_register(&mtd->dev); - if (error) { diff --git a/target/linux/generic/backport-5.10/414-v6.1-mtd-allow-getting-MTD-device-associated-with-a-speci.patch b/target/linux/generic/backport-5.10/414-v6.1-mtd-allow-getting-MTD-device-associated-with-a-speci.patch deleted file mode 100644 index 968279185e..0000000000 --- a/target/linux/generic/backport-5.10/414-v6.1-mtd-allow-getting-MTD-device-associated-with-a-speci.patch +++ /dev/null @@ -1,72 +0,0 @@ -From b0321721be50b80c03a51866a94fde4f94690e18 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 15 Jun 2022 21:42:59 +0200 -Subject: [PATCH] mtd: allow getting MTD device associated with a specific DT - node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MTD subsystem API allows interacting with MTD devices (e.g. reading, -writing, handling bad blocks). So far a random driver could get MTD -device only by its name (get_mtd_device_nm()). This change allows -getting them also by a DT node. - -This API is required for drivers handling DT defined MTD partitions in a -specific way (e.g. U-Boot (sub)partition with environment variables). - -Signed-off-by: Rafał Miłecki -Acked-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla ---- - drivers/mtd/mtdcore.c | 28 ++++++++++++++++++++++++++++ - include/linux/mtd/mtd.h | 1 + - 2 files changed, 29 insertions(+) - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -1072,6 +1072,34 @@ int __get_mtd_device(struct mtd_info *mt - EXPORT_SYMBOL_GPL(__get_mtd_device); - - /** -+ * of_get_mtd_device_by_node - obtain an MTD device associated with a given node -+ * -+ * @np: device tree node -+ */ -+struct mtd_info *of_get_mtd_device_by_node(struct device_node *np) -+{ -+ struct mtd_info *mtd = NULL; -+ struct mtd_info *tmp; -+ int err; -+ -+ mutex_lock(&mtd_table_mutex); -+ -+ err = -EPROBE_DEFER; -+ mtd_for_each_device(tmp) { -+ if (mtd_get_of_node(tmp) == np) { -+ mtd = tmp; -+ err = __get_mtd_device(mtd); -+ break; -+ } -+ } -+ -+ mutex_unlock(&mtd_table_mutex); -+ -+ return err ? ERR_PTR(err) : mtd; -+} -+EXPORT_SYMBOL_GPL(of_get_mtd_device_by_node); -+ -+/** - * get_mtd_device_nm - obtain a validated handle for an MTD device by - * device name - * @name: MTD device name to open ---- a/include/linux/mtd/mtd.h -+++ b/include/linux/mtd/mtd.h -@@ -675,6 +675,7 @@ extern int mtd_device_unregister(struct - extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); - extern int __get_mtd_device(struct mtd_info *mtd); - extern void __put_mtd_device(struct mtd_info *mtd); -+extern struct mtd_info *of_get_mtd_device_by_node(struct device_node *np); - extern struct mtd_info *get_mtd_device_nm(const char *name); - extern void put_mtd_device(struct mtd_info *mtd); - diff --git a/target/linux/generic/backport-5.10/415-v6.0-mtd-core-check-partition-before-dereference.patch b/target/linux/generic/backport-5.10/415-v6.0-mtd-core-check-partition-before-dereference.patch deleted file mode 100644 index 65789ddf2d..0000000000 --- a/target/linux/generic/backport-5.10/415-v6.0-mtd-core-check-partition-before-dereference.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 7ec4cdb321738d44ae5d405e7b6ac73dfbf99caa Mon Sep 17 00:00:00 2001 -From: Tetsuo Handa -Date: Mon, 25 Jul 2022 22:49:25 +0900 -Subject: [PATCH] mtd: core: check partition before dereference - -syzbot is reporting NULL pointer dereference at mtd_check_of_node() [1], -for mtdram test device (CONFIG_MTD_MTDRAM) is not partition. - -Link: https://syzkaller.appspot.com/bug?extid=fe013f55a2814a9e8cfd [1] -Reported-by: syzbot -Reported-by: kernel test robot -Fixes: ad9b10d1eaada169 ("mtd: core: introduce of support for dynamic partitions") -Signed-off-by: Tetsuo Handa -CC: stable@vger.kernel.org -Signed-off-by: Richard Weinberger ---- - drivers/mtd/mtdcore.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -574,6 +574,8 @@ static void mtd_check_of_node(struct mtd - return; - - /* Check if a partitions node exist */ -+ if (!mtd_is_partition(mtd)) -+ return; - parent = mtd->parent; - parent_dn = dev_of_node(&parent->dev); - if (!parent_dn) diff --git a/target/linux/generic/backport-5.10/416-v6.1-mtd-core-add-missing-of_node_get-in-dynamic-partitio.patch b/target/linux/generic/backport-5.10/416-v6.1-mtd-core-add-missing-of_node_get-in-dynamic-partitio.patch deleted file mode 100644 index 0c359c65f8..0000000000 --- a/target/linux/generic/backport-5.10/416-v6.1-mtd-core-add-missing-of_node_get-in-dynamic-partitio.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 12b58961de0bd88b3c7dfa5d21f6d67f4678b780 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 18 Oct 2022 07:18:22 +0200 -Subject: [PATCH] mtd: core: add missing of_node_get() in dynamic partitions - code -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes unbalanced of_node_put(): -[ 1.078910] 6 cmdlinepart partitions found on MTD device gpmi-nand -[ 1.085116] Creating 6 MTD partitions on "gpmi-nand": -[ 1.090181] 0x000000000000-0x000008000000 : "nandboot" -[ 1.096952] 0x000008000000-0x000009000000 : "nandfit" -[ 1.103547] 0x000009000000-0x00000b000000 : "nandkernel" -[ 1.110317] 0x00000b000000-0x00000c000000 : "nanddtb" -[ 1.115525] ------------[ cut here ]------------ -[ 1.120141] refcount_t: addition on 0; use-after-free. -[ 1.125328] WARNING: CPU: 0 PID: 1 at lib/refcount.c:25 refcount_warn_saturate+0xdc/0x148 -[ 1.133528] Modules linked in: -[ 1.136589] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.0.0-rc7-next-20220930-04543-g8cf3f7 -[ 1.146342] Hardware name: Freescale i.MX8DXL DDR3L EVK (DT) -[ 1.151999] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) -[ 1.158965] pc : refcount_warn_saturate+0xdc/0x148 -[ 1.163760] lr : refcount_warn_saturate+0xdc/0x148 -[ 1.168556] sp : ffff800009ddb080 -[ 1.171866] x29: ffff800009ddb080 x28: ffff800009ddb35a x27: 0000000000000002 -[ 1.179015] x26: ffff8000098b06ad x25: ffffffffffffffff x24: ffff0a00ffffff05 -[ 1.186165] x23: ffff00001fdf6470 x22: ffff800009ddb367 x21: 0000000000000000 -[ 1.193314] x20: ffff00001fdfebe8 x19: ffff00001fdfec50 x18: ffffffffffffffff -[ 1.200464] x17: 0000000000000000 x16: 0000000000000118 x15: 0000000000000004 -[ 1.207614] x14: 0000000000000fff x13: ffff800009bca248 x12: 0000000000000003 -[ 1.214764] x11: 00000000ffffefff x10: c0000000ffffefff x9 : 4762cb2ccb52de00 -[ 1.221914] x8 : 4762cb2ccb52de00 x7 : 205d313431303231 x6 : 312e31202020205b -[ 1.229063] x5 : ffff800009d55c1f x4 : 0000000000000001 x3 : 0000000000000000 -[ 1.236213] x2 : 0000000000000000 x1 : ffff800009954be6 x0 : 000000000000002a -[ 1.243365] Call trace: -[ 1.245806] refcount_warn_saturate+0xdc/0x148 -[ 1.250253] kobject_get+0x98/0x9c -[ 1.253658] of_node_get+0x20/0x34 -[ 1.257072] of_fwnode_get+0x3c/0x54 -[ 1.260652] fwnode_get_nth_parent+0xd8/0xf4 -[ 1.264926] fwnode_full_name_string+0x3c/0xb4 -[ 1.269373] device_node_string+0x498/0x5b4 -[ 1.273561] pointer+0x41c/0x5d0 -[ 1.276793] vsnprintf+0x4d8/0x694 -[ 1.280198] vprintk_store+0x164/0x528 -[ 1.283951] vprintk_emit+0x98/0x164 -[ 1.287530] vprintk_default+0x44/0x6c -[ 1.291284] vprintk+0xf0/0x134 -[ 1.294428] _printk+0x54/0x7c -[ 1.297486] of_node_release+0xe8/0x128 -[ 1.301326] kobject_put+0x98/0xfc -[ 1.304732] of_node_put+0x1c/0x28 -[ 1.308137] add_mtd_device+0x484/0x6d4 -[ 1.311977] add_mtd_partitions+0xf0/0x1d0 -[ 1.316078] parse_mtd_partitions+0x45c/0x518 -[ 1.320439] mtd_device_parse_register+0xb0/0x274 -[ 1.325147] gpmi_nand_probe+0x51c/0x650 -[ 1.329074] platform_probe+0xa8/0xd0 -[ 1.332740] really_probe+0x130/0x334 -[ 1.336406] __driver_probe_device+0xb4/0xe0 -[ 1.340681] driver_probe_device+0x3c/0x1f8 -[ 1.344869] __driver_attach+0xdc/0x1a4 -[ 1.348708] bus_for_each_dev+0x80/0xcc -[ 1.352548] driver_attach+0x24/0x30 -[ 1.356127] bus_add_driver+0x108/0x1f4 -[ 1.359967] driver_register+0x78/0x114 -[ 1.363807] __platform_driver_register+0x24/0x30 -[ 1.368515] gpmi_nand_driver_init+0x1c/0x28 -[ 1.372798] do_one_initcall+0xbc/0x238 -[ 1.376638] do_initcall_level+0x94/0xb4 -[ 1.380565] do_initcalls+0x54/0x94 -[ 1.384058] do_basic_setup+0x1c/0x28 -[ 1.387724] kernel_init_freeable+0x110/0x188 -[ 1.392084] kernel_init+0x20/0x1a0 -[ 1.395578] ret_from_fork+0x10/0x20 -[ 1.399157] ---[ end trace 0000000000000000 ]--- -[ 1.403782] ------------[ cut here ]------------ - -Reported-by: Han Xu -Fixes: ad9b10d1eaada169 ("mtd: core: introduce of support for dynamic partitions") -Signed-off-by: Rafał Miłecki -Tested-by: Han Xu -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20221018051822.28685-1-zajec5@gmail.com ---- - drivers/mtd/mtdcore.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -577,7 +577,7 @@ static void mtd_check_of_node(struct mtd - if (!mtd_is_partition(mtd)) - return; - parent = mtd->parent; -- parent_dn = dev_of_node(&parent->dev); -+ parent_dn = of_node_get(dev_of_node(&parent->dev)); - if (!parent_dn) - return; - diff --git a/target/linux/generic/backport-5.10/417-v6.2-0001-mtd-core-simplify-a-bit-code-find-partition-matching.patch b/target/linux/generic/backport-5.10/417-v6.2-0001-mtd-core-simplify-a-bit-code-find-partition-matching.patch deleted file mode 100644 index e47def580c..0000000000 --- a/target/linux/generic/backport-5.10/417-v6.2-0001-mtd-core-simplify-a-bit-code-find-partition-matching.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 63db0cb35e1cb3b3c134906d1062f65513fdda2d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 4 Oct 2022 10:37:09 +0200 -Subject: [PATCH] mtd: core: simplify (a bit) code find partition-matching - dynamic OF node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. Don't hardcode "partition-" string twice -2. Use simpler logic & use ->name to avoid of_property_read_string() -3. Use mtd_get_of_node() helper - -Cc: Christian Marangi -Signed-off-by: Rafał Miłecki -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20221004083710.27704-1-zajec5@gmail.com ---- - drivers/mtd/mtdcore.c | 16 +++++++--------- - 1 file changed, 7 insertions(+), 9 deletions(-) - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -566,18 +566,16 @@ static void mtd_check_of_node(struct mtd - struct device_node *partitions, *parent_dn, *mtd_dn = NULL; - const char *pname, *prefix = "partition-"; - int plen, mtd_name_len, offset, prefix_len; -- struct mtd_info *parent; - bool found = false; - - /* Check if MTD already has a device node */ -- if (dev_of_node(&mtd->dev)) -+ if (mtd_get_of_node(mtd)) - return; - - /* Check if a partitions node exist */ - if (!mtd_is_partition(mtd)) - return; -- parent = mtd->parent; -- parent_dn = of_node_get(dev_of_node(&parent->dev)); -+ parent_dn = of_node_get(mtd_get_of_node(mtd->parent)); - if (!parent_dn) - return; - -@@ -590,15 +588,15 @@ static void mtd_check_of_node(struct mtd - - /* Search if a partition is defined with the same name */ - for_each_child_of_node(partitions, mtd_dn) { -- offset = 0; -- - /* Skip partition with no/wrong prefix */ -- if (!of_node_name_prefix(mtd_dn, "partition-")) -+ if (!of_node_name_prefix(mtd_dn, prefix)) - continue; - - /* Label have priority. Check that first */ -- if (of_property_read_string(mtd_dn, "label", &pname)) { -- of_property_read_string(mtd_dn, "name", &pname); -+ if (!of_property_read_string(mtd_dn, "label", &pname)) { -+ offset = 0; -+ } else { -+ pname = mtd_dn->name; - offset = prefix_len; - } - diff --git a/target/linux/generic/backport-5.10/417-v6.2-0002-mtd-core-try-to-find-OF-node-for-every-MTD-partition.patch b/target/linux/generic/backport-5.10/417-v6.2-0002-mtd-core-try-to-find-OF-node-for-every-MTD-partition.patch deleted file mode 100644 index 438e25b7f9..0000000000 --- a/target/linux/generic/backport-5.10/417-v6.2-0002-mtd-core-try-to-find-OF-node-for-every-MTD-partition.patch +++ /dev/null @@ -1,84 +0,0 @@ -From ddb8cefb7af288950447ca6eeeafb09977dab56f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 4 Oct 2022 10:37:10 +0200 -Subject: [PATCH] mtd: core: try to find OF node for every MTD partition -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -So far this feature was limited to the top-level "nvmem-cells" node. -There are multiple parsers creating partitions and subpartitions -dynamically. Extend that code to handle them too. - -This allows finding partition-* node for every MTD (sub)partition. - -Random example: - -partitions { - compatible = "brcm,bcm947xx-cfe-partitions"; - - partition-firmware { - compatible = "brcm,trx"; - - partition-loader { - }; - }; -}; - -Cc: Christian Marangi -Signed-off-by: Rafał Miłecki -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20221004083710.27704-2-zajec5@gmail.com ---- - drivers/mtd/mtdcore.c | 18 ++++++------------ - 1 file changed, 6 insertions(+), 12 deletions(-) - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -566,20 +566,22 @@ static void mtd_check_of_node(struct mtd - struct device_node *partitions, *parent_dn, *mtd_dn = NULL; - const char *pname, *prefix = "partition-"; - int plen, mtd_name_len, offset, prefix_len; -- bool found = false; - - /* Check if MTD already has a device node */ - if (mtd_get_of_node(mtd)) - return; - -- /* Check if a partitions node exist */ - if (!mtd_is_partition(mtd)) - return; -+ - parent_dn = of_node_get(mtd_get_of_node(mtd->parent)); - if (!parent_dn) - return; - -- partitions = of_get_child_by_name(parent_dn, "partitions"); -+ if (mtd_is_partition(mtd->parent)) -+ partitions = of_node_get(parent_dn); -+ else -+ partitions = of_get_child_by_name(parent_dn, "partitions"); - if (!partitions) - goto exit_parent; - -@@ -603,19 +605,11 @@ static void mtd_check_of_node(struct mtd - plen = strlen(pname) - offset; - if (plen == mtd_name_len && - !strncmp(mtd->name, pname + offset, plen)) { -- found = true; -+ mtd_set_of_node(mtd, mtd_dn); - break; - } - } - -- if (!found) -- goto exit_partitions; -- -- /* Set of_node only for nvmem */ -- if (of_device_is_compatible(mtd_dn, "nvmem-cells")) -- mtd_set_of_node(mtd, mtd_dn); -- --exit_partitions: - of_node_put(partitions); - exit_parent: - of_node_put(parent_dn); diff --git a/target/linux/generic/backport-5.10/418-v6.2-mtd-core-set-ROOT_DEV-for-partitions-marked-as-rootf.patch b/target/linux/generic/backport-5.10/418-v6.2-mtd-core-set-ROOT_DEV-for-partitions-marked-as-rootf.patch deleted file mode 100644 index 2a132bd8a3..0000000000 --- a/target/linux/generic/backport-5.10/418-v6.2-mtd-core-set-ROOT_DEV-for-partitions-marked-as-rootf.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 26422ac78e9d8767bd4aabfbae616b15edbf6a1b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sat, 22 Oct 2022 23:13:18 +0200 -Subject: [PATCH] mtd: core: set ROOT_DEV for partitions marked as rootfs in DT -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This adds support for "linux,rootfs" binding that is used to mark flash -partition containing rootfs. It's useful for devices using device tree -that don't have bootloader passing root info in cmdline. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20221022211318.32009-2-zajec5@gmail.com ---- - drivers/mtd/mtdcore.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -28,6 +28,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -745,6 +746,17 @@ int add_mtd_device(struct mtd_info *mtd) - not->add(mtd); - - mutex_unlock(&mtd_table_mutex); -+ -+ if (of_find_property(mtd_get_of_node(mtd), "linux,rootfs", NULL)) { -+ if (IS_BUILTIN(CONFIG_MTD)) { -+ pr_info("mtd: setting mtd%d (%s) as root device\n", mtd->index, mtd->name); -+ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, mtd->index); -+ } else { -+ pr_warn("mtd: can't set mtd%d (%s) as root device - mtd must be builtin\n", -+ mtd->index, mtd->name); -+ } -+ } -+ - /* We _know_ we aren't being removed, because - our caller is still holding us here. So none - of this try_ nonsense, and no bitching about it diff --git a/target/linux/generic/backport-5.10/419-v5.14-mtd-spinand-gigadevice-Support-GD5F1GQ5UExxG.patch b/target/linux/generic/backport-5.10/419-v5.14-mtd-spinand-gigadevice-Support-GD5F1GQ5UExxG.patch deleted file mode 100644 index 00c43879f6..0000000000 --- a/target/linux/generic/backport-5.10/419-v5.14-mtd-spinand-gigadevice-Support-GD5F1GQ5UExxG.patch +++ /dev/null @@ -1,172 +0,0 @@ -From bd568cc04c675b7fa97214d278a54794c2ecc2ad Mon Sep 17 00:00:00 2001 -From: Reto Schneider -Date: Thu, 11 Feb 2021 12:36:19 +0100 -Subject: [PATCH] mtd: spinand: gigadevice: Support GD5F1GQ5UExxG - -The relevant changes to the already existing GD5F1GQ4UExxG support has -been determined by consulting the GigaDevice product change notice -AN-0392-10, version 1.0 from November 30, 2020. - -As the overlaps are huge, variable names have been generalized -accordingly. - -Apart from the lowered ECC strength (4 instead of 8 bits per 512 bytes), -the new device ID, and the extra quad IO dummy byte, no changes had to -be taken into account. - -New hardware features are not supported, namely: - - Power on reset - - Unique ID - - Double transfer rate (DTR) - - Parameter page - - Random data quad IO - -The inverted semantic of the "driver strength" register bits, defaulting -to 100% instead of 50% for the Q5 devices, got ignored as the driver has -never touched them anyway. - -The no longer supported "read from cache during block erase" -functionality is not reflected as the current SPI NAND core does not -support it anyway. - -Implementation has been tested on MediaTek MT7688 based GARDENA smart -Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG. - -Signed-off-by: Reto Schneider -Reviewed-by: Frieder Schrempf -Reviewed-by: Stefan Roese -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210211113619.3502-1-code@reto-schneider.ch -(cherry picked from commit 469b992489852b500d39048aa0013639dfe9f2e6) ---- - drivers/mtd/nand/spi/gigadevice.c | 69 +++++++++++++++++++++++++++---- - 1 file changed, 60 insertions(+), 9 deletions(-) - ---- a/drivers/mtd/nand/spi/gigadevice.c -+++ b/drivers/mtd/nand/spi/gigadevice.c -@@ -13,7 +13,10 @@ - #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4) - #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4) - --#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0 -+#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4) -+#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4) -+ -+#define GD5FXGQXXEXXG_REG_STATUS2 0xf0 - - #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4) - #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4) -@@ -102,7 +105,7 @@ static int gd5fxgq4xa_ecc_get_status(str - return -EINVAL; - } - --static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, -+static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) - { - if (section) -@@ -114,7 +117,7 @@ static int gd5fxgq4_variant2_ooblayout_e - return 0; - } - --static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section, -+static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) - { - if (section) -@@ -127,9 +130,10 @@ static int gd5fxgq4_variant2_ooblayout_f - return 0; - } - --static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = { -- .ecc = gd5fxgq4_variant2_ooblayout_ecc, -- .free = gd5fxgq4_variant2_ooblayout_free, -+/* Valid for Q4/Q5 and Q6 (untested) devices */ -+static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = { -+ .ecc = gd5fxgqx_variant2_ooblayout_ecc, -+ .free = gd5fxgqx_variant2_ooblayout_free, - }; - - static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section, -@@ -165,7 +169,7 @@ static int gd5fxgq4uexxg_ecc_get_status( - u8 status) - { - u8 status2; -- struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2, -+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, - &status2); - int ret; - -@@ -203,6 +207,43 @@ static int gd5fxgq4uexxg_ecc_get_status( - return -EINVAL; - } - -+static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand, -+ u8 status) -+{ -+ u8 status2; -+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2, -+ &status2); -+ int ret; -+ -+ switch (status & STATUS_ECC_MASK) { -+ case STATUS_ECC_NO_BITFLIPS: -+ return 0; -+ -+ case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS: -+ /* -+ * Read status2 register to determine a more fine grained -+ * bit error status -+ */ -+ ret = spi_mem_exec_op(spinand->spimem, &op); -+ if (ret) -+ return ret; -+ -+ /* -+ * 1 ... 4 bits are flipped (and corrected) -+ */ -+ /* bits sorted this way (1...0): ECCSE1, ECCSE0 */ -+ return ((status2 & STATUS_ECC_MASK) >> 4) + 1; -+ -+ case STATUS_ECC_UNCOR_ERROR: -+ return -EBADMSG; -+ -+ default: -+ break; -+ } -+ -+ return -EINVAL; -+} -+ - static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand, - u8 status) - { -@@ -282,7 +323,7 @@ static const struct spinand_info gigadev - &write_cache_variants, - &update_cache_variants), - SPINAND_HAS_QE_BIT, -- SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, - gd5fxgq4uexxg_ecc_get_status)), - SPINAND_INFO("GD5F1GQ4UFxxG", - SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), -@@ -292,8 +333,18 @@ static const struct spinand_info gigadev - &write_cache_variants, - &update_cache_variants), - SPINAND_HAS_QE_BIT, -- SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, - gd5fxgq4ufxxg_ecc_get_status)), -+ SPINAND_INFO("GD5F1GQ5UExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq5xexxg_ecc_get_status)), - }; - - static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { diff --git a/target/linux/generic/backport-5.10/420-v5.19-01-mtd-spinand-gigadevice-fix-Quad-IO-for-GD5F1GQ5UExxG.patch b/target/linux/generic/backport-5.10/420-v5.19-01-mtd-spinand-gigadevice-fix-Quad-IO-for-GD5F1GQ5UExxG.patch deleted file mode 100644 index 1b0b57c2b0..0000000000 --- a/target/linux/generic/backport-5.10/420-v5.19-01-mtd-spinand-gigadevice-fix-Quad-IO-for-GD5F1GQ5UExxG.patch +++ /dev/null @@ -1,44 +0,0 @@ -From a4f9dd55c5e1bb951db6f1dee20e62e0103f3438 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 20 Mar 2022 17:59:57 +0800 -Subject: [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG - -Read From Cache Quad IO (EBH) uses 2 dummy bytes on this chip according -to page 23 of the datasheet[0]. - -[0]: https://www.gigadevice.com/datasheet/gd5f1gq5xexxg/ - -Fixes: 469b99248985 ("mtd: spinand: gigadevice: Support GD5F1GQ5UExxG") -Signed-off-by: Chuanhong Guo -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-2-gch981213@gmail.com ---- - drivers/mtd/nand/spi/gigadevice.c | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/spi/gigadevice.c -+++ b/drivers/mtd/nand/spi/gigadevice.c -@@ -39,6 +39,14 @@ static SPINAND_OP_VARIANTS(read_cache_va - SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); - -+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5, -+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -+ - static SPINAND_OP_VARIANTS(write_cache_variants, - SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), - SPINAND_PROG_LOAD(true, 0, NULL, 0)); -@@ -339,7 +347,7 @@ static const struct spinand_info gigadev - SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51), - NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), - NAND_ECCREQ(4, 512), -- SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, - &write_cache_variants, - &update_cache_variants), - SPINAND_HAS_QE_BIT, diff --git a/target/linux/generic/backport-5.10/420-v5.19-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch b/target/linux/generic/backport-5.10/420-v5.19-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch deleted file mode 100644 index 181c912fbf..0000000000 --- a/target/linux/generic/backport-5.10/420-v5.19-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 573eec222bc82fb5e724586267fbbb1aed9ffd03 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 20 Mar 2022 17:59:58 +0800 -Subject: [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG - -Add support for: - GD5F1GQ4RExxG - GD5F2GQ4{U,R}ExxG - -These chips differ from GD5F1GQ4UExxG only in chip ID, voltage -and capacity. - -Signed-off-by: Chuanhong Guo -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-3-gch981213@gmail.com ---- - drivers/mtd/nand/spi/gigadevice.c | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/drivers/mtd/nand/spi/gigadevice.c -+++ b/drivers/mtd/nand/spi/gigadevice.c -@@ -333,6 +333,36 @@ static const struct spinand_info gigadev - SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, - gd5fxgq4uexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F1GQ4RExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F2GQ4UExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F2GQ4RExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), - SPINAND_INFO("GD5F1GQ4UFxxG", - SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48), - NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), diff --git a/target/linux/generic/backport-5.10/420-v5.19-03-mtd-spinand-gigadevice-add-support-for-GD5F1GQ5RExxG.patch b/target/linux/generic/backport-5.10/420-v5.19-03-mtd-spinand-gigadevice-add-support-for-GD5F1GQ5RExxG.patch deleted file mode 100644 index 3a1cc9efcf..0000000000 --- a/target/linux/generic/backport-5.10/420-v5.19-03-mtd-spinand-gigadevice-add-support-for-GD5F1GQ5RExxG.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 620a988813403318023296b61228ee8f3fcdb8e0 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 20 Mar 2022 17:59:59 +0800 -Subject: [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG - -This chip is the 1.8v version of GD5F1GQ5UExxG. - -Signed-off-by: Chuanhong Guo -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-4-gch981213@gmail.com ---- - drivers/mtd/nand/spi/gigadevice.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/mtd/nand/spi/gigadevice.c -+++ b/drivers/mtd/nand/spi/gigadevice.c -@@ -383,6 +383,16 @@ static const struct spinand_info gigadev - SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, - gd5fxgq5xexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F1GQ5RExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq5xexxg_ecc_get_status)), - }; - - static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { diff --git a/target/linux/generic/backport-5.10/420-v5.19-04-mtd-spinand-gigadevice-add-support-for-GD5F-2-4-GQ5x.patch b/target/linux/generic/backport-5.10/420-v5.19-04-mtd-spinand-gigadevice-add-support-for-GD5F-2-4-GQ5x.patch deleted file mode 100644 index cee9d9db3e..0000000000 --- a/target/linux/generic/backport-5.10/420-v5.19-04-mtd-spinand-gigadevice-add-support-for-GD5F-2-4-GQ5x.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 194ec04b3a9e7fa97d1fbef296410631bc3cf1c8 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 20 Mar 2022 18:00:00 +0800 -Subject: [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2, - 4}GQ5xExxG - -Add support for: - GD5F2GQ5{U,R}ExxG - GD5F4GQ6{U,R}ExxG - -These chips uses 4 dummy bytes for quad io and 2 dummy bytes for dual io. -Besides that and memory layout, they are identical to their 1G variant. - -Signed-off-by: Chuanhong Guo -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-5-gch981213@gmail.com ---- - drivers/mtd/nand/spi/gigadevice.c | 48 +++++++++++++++++++++++++++++++ - 1 file changed, 48 insertions(+) - ---- a/drivers/mtd/nand/spi/gigadevice.c -+++ b/drivers/mtd/nand/spi/gigadevice.c -@@ -47,6 +47,14 @@ static SPINAND_OP_VARIANTS(read_cache_va - SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); - -+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5, -+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -+ - static SPINAND_OP_VARIANTS(write_cache_variants, - SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), - SPINAND_PROG_LOAD(true, 0, NULL, 0)); -@@ -391,6 +399,46 @@ static const struct spinand_info gigadev - &write_cache_variants, - &update_cache_variants), - SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq5xexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F2GQ5UExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq5xexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F2GQ5RExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq5xexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F4GQ6UExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq5xexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F4GQ6RExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, - gd5fxgq5xexxg_ecc_get_status)), - }; diff --git a/target/linux/generic/backport-5.10/420-v5.19-05-mtd-spinand-gigadevice-add-support-for-GD5FxGM7xExxG.patch b/target/linux/generic/backport-5.10/420-v5.19-05-mtd-spinand-gigadevice-add-support-for-GD5FxGM7xExxG.patch deleted file mode 100644 index d63113e1a6..0000000000 --- a/target/linux/generic/backport-5.10/420-v5.19-05-mtd-spinand-gigadevice-add-support-for-GD5FxGM7xExxG.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 54647cd003c08b714474a5b599a147ec6a160486 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Sun, 20 Mar 2022 18:00:01 +0800 -Subject: [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG - -Add support for: - GD5F{1,2}GM7{U,R}ExxG - GD5F4GM8{U,R}ExxG - -These are new 27nm counterparts for the GD5FxGQ4 chips from GigaDevice -with 8b/512b on-die ECC capability. -These chips (and currently supported GD5FxGQ5 chips) have QIO DTR -instruction for reading page cache. It isn't added in this patch because -I don't have a DTR spi controller for testing. - -Signed-off-by: Chuanhong Guo -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-6-gch981213@gmail.com ---- - drivers/mtd/nand/spi/gigadevice.c | 60 +++++++++++++++++++++++++++++++ - 1 file changed, 60 insertions(+) - ---- a/drivers/mtd/nand/spi/gigadevice.c -+++ b/drivers/mtd/nand/spi/gigadevice.c -@@ -441,6 +441,66 @@ static const struct spinand_info gigadev - SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, - gd5fxgq5xexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F1GM7UExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F1GM7RExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81), -+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F2GM7UExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F2GM7RExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82), -+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F4GM8UExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95), -+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), -+ SPINAND_INFO("GD5F4GM8RExxG", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85), -+ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, -+ gd5fxgq4uexxg_ecc_get_status)), - }; - - static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { diff --git a/target/linux/generic/backport-5.10/421-v6.2-mtd-parsers-add-TP-Link-SafeLoader-partitions-table-.patch b/target/linux/generic/backport-5.10/421-v6.2-mtd-parsers-add-TP-Link-SafeLoader-partitions-table-.patch deleted file mode 100644 index 9f543365a5..0000000000 --- a/target/linux/generic/backport-5.10/421-v6.2-mtd-parsers-add-TP-Link-SafeLoader-partitions-table-.patch +++ /dev/null @@ -1,229 +0,0 @@ -From aec4d5f5ffd0f0092bd9dc21ea90e0bc237d4b74 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sat, 15 Oct 2022 11:29:50 +0200 -Subject: [PATCH] mtd: parsers: add TP-Link SafeLoader partitions table parser -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This parser deals with most TP-Link home routers. It reads info about -partitions and registers them in the MTD subsystem. - -Example from TP-Link Archer C5 V2: - -spi-nor spi0.0: s25fl128s1 (16384 Kbytes) -15 tplink-safeloader partitions found on MTD device spi0.0 -Creating 15 MTD partitions on "spi0.0": -0x000000000000-0x000000040000 : "fs-uboot" -0x000000040000-0x000000440000 : "os-image" -0x000000440000-0x000000e40000 : "rootfs" -0x000000e40000-0x000000e40200 : "default-mac" -0x000000e40200-0x000000e40400 : "pin" -0x000000e40400-0x000000e40600 : "product-info" -0x000000e50000-0x000000e60000 : "partition-table" -0x000000e60000-0x000000e60200 : "soft-version" -0x000000e61000-0x000000e70000 : "support-list" -0x000000e70000-0x000000e80000 : "profile" -0x000000e80000-0x000000e90000 : "default-config" -0x000000e90000-0x000000ee0000 : "user-config" -0x000000ee0000-0x000000fe0000 : "log" -0x000000fe0000-0x000000ff0000 : "radio_bk" -0x000000ff0000-0x000001000000 : "radio" - -Signed-off-by: Rafał Miłecki -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20221015092950.27467-2-zajec5@gmail.com ---- - drivers/mtd/parsers/Kconfig | 15 +++ - drivers/mtd/parsers/Makefile | 1 + - drivers/mtd/parsers/tplink_safeloader.c | 150 ++++++++++++++++++++++++ - 3 files changed, 166 insertions(+) - create mode 100644 drivers/mtd/parsers/tplink_safeloader.c - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -113,6 +113,21 @@ config MTD_AFS_PARTS - for your particular device. It won't happen automatically. The - 'physmap' map driver (CONFIG_MTD_PHYSMAP) does this, for example. - -+config MTD_PARSER_TPLINK_SAFELOADER -+ tristate "TP-Link Safeloader partitions parser" -+ depends on MTD && (ARCH_BCM_5301X || ATH79 || SOC_MT7620 || SOC_MT7621 || COMPILE_TEST) -+ help -+ TP-Link home routers use flash partitions to store various data. Info -+ about flash space layout is stored in a partitions table using a -+ custom ASCII-based format. -+ -+ That format was first found in devices with SafeLoader bootloader and -+ was named after it. Later it was adapted to CFE and U-Boot -+ bootloaders. -+ -+ This driver reads partitions table, parses it and creates MTD -+ partitions. -+ - config MTD_PARSER_TRX - tristate "Parser for TRX format partitions" - depends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || RALINK || COMPILE_TEST) ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -9,6 +9,7 @@ ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908) += - ofpart-$(CONFIG_MTD_OF_PARTS_LINKSYS_NS)+= ofpart_linksys_ns.o - obj-$(CONFIG_MTD_PARSER_IMAGETAG) += parser_imagetag.o - obj-$(CONFIG_MTD_AFS_PARTS) += afs.o -+obj-$(CONFIG_MTD_PARSER_TPLINK_SAFELOADER) += tplink_safeloader.o - obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o - obj-$(CONFIG_MTD_SERCOMM_PARTS) += scpart.o - obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o ---- /dev/null -+++ b/drivers/mtd/parsers/tplink_safeloader.c -@@ -0,0 +1,150 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright © 2022 Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TPLINK_SAFELOADER_DATA_OFFSET 4 -+#define TPLINK_SAFELOADER_MAX_PARTS 32 -+ -+struct safeloader_cmn_header { -+ __be32 size; -+ uint32_t unused; -+} __packed; -+ -+static void *mtd_parser_tplink_safeloader_read_table(struct mtd_info *mtd) -+{ -+ struct safeloader_cmn_header hdr; -+ struct device_node *np; -+ size_t bytes_read; -+ size_t offset; -+ size_t size; -+ char *buf; -+ int err; -+ -+ np = mtd_get_of_node(mtd); -+ if (mtd_is_partition(mtd)) -+ of_node_get(np); -+ else -+ np = of_get_child_by_name(np, "partitions"); -+ -+ if (of_property_read_u32(np, "partitions-table-offset", (u32 *)&offset)) { -+ pr_err("Failed to get partitions table offset\n"); -+ goto err_put; -+ } -+ -+ err = mtd_read(mtd, offset, sizeof(hdr), &bytes_read, (uint8_t *)&hdr); -+ if (err && !mtd_is_bitflip(err)) { -+ pr_err("Failed to read from %s at 0x%zx\n", mtd->name, offset); -+ goto err_put; -+ } -+ -+ size = be32_to_cpu(hdr.size); -+ -+ buf = kmalloc(size + 1, GFP_KERNEL); -+ if (!buf) -+ goto err_put; -+ -+ err = mtd_read(mtd, offset + sizeof(hdr), size, &bytes_read, buf); -+ if (err && !mtd_is_bitflip(err)) { -+ pr_err("Failed to read from %s at 0x%zx\n", mtd->name, offset + sizeof(hdr)); -+ goto err_kfree; -+ } -+ -+ buf[size] = '\0'; -+ -+ of_node_put(np); -+ -+ return buf; -+ -+err_kfree: -+ kfree(buf); -+err_put: -+ of_node_put(np); -+ return NULL; -+} -+ -+static int mtd_parser_tplink_safeloader_parse(struct mtd_info *mtd, -+ const struct mtd_partition **pparts, -+ struct mtd_part_parser_data *data) -+{ -+ struct mtd_partition *parts; -+ char name[65]; -+ size_t offset; -+ size_t bytes; -+ char *buf; -+ int idx; -+ int err; -+ -+ parts = kcalloc(TPLINK_SAFELOADER_MAX_PARTS, sizeof(*parts), GFP_KERNEL); -+ if (!parts) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ buf = mtd_parser_tplink_safeloader_read_table(mtd); -+ if (!buf) { -+ err = -ENOENT; -+ goto err_out; -+ } -+ -+ for (idx = 0, offset = TPLINK_SAFELOADER_DATA_OFFSET; -+ idx < TPLINK_SAFELOADER_MAX_PARTS && -+ sscanf(buf + offset, "partition %64s base 0x%llx size 0x%llx%zn\n", -+ name, &parts[idx].offset, &parts[idx].size, &bytes) == 3; -+ idx++, offset += bytes + 1) { -+ parts[idx].name = kstrdup(name, GFP_KERNEL); -+ if (!parts[idx].name) { -+ err = -ENOMEM; -+ goto err_free; -+ } -+ } -+ -+ if (idx == TPLINK_SAFELOADER_MAX_PARTS) -+ pr_warn("Reached maximum number of partitions!\n"); -+ -+ kfree(buf); -+ -+ *pparts = parts; -+ -+ return idx; -+ -+err_free: -+ for (idx -= 1; idx >= 0; idx--) -+ kfree(parts[idx].name); -+err_out: -+ return err; -+}; -+ -+static void mtd_parser_tplink_safeloader_cleanup(const struct mtd_partition *pparts, -+ int nr_parts) -+{ -+ int i; -+ -+ for (i = 0; i < nr_parts; i++) -+ kfree(pparts[i].name); -+ -+ kfree(pparts); -+} -+ -+static const struct of_device_id mtd_parser_tplink_safeloader_of_match_table[] = { -+ { .compatible = "tplink,safeloader-partitions" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, mtd_parser_tplink_safeloader_of_match_table); -+ -+static struct mtd_part_parser mtd_parser_tplink_safeloader = { -+ .parse_fn = mtd_parser_tplink_safeloader_parse, -+ .cleanup = mtd_parser_tplink_safeloader_cleanup, -+ .name = "tplink-safeloader", -+ .of_match_table = mtd_parser_tplink_safeloader_of_match_table, -+}; -+module_mtd_part_parser(mtd_parser_tplink_safeloader); -+ -+MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/backport-5.10/422-v5.19-mtd-spi-nor-support-eon-en25qh256a.patch b/target/linux/generic/backport-5.10/422-v5.19-mtd-spi-nor-support-eon-en25qh256a.patch deleted file mode 100644 index 2358352e93..0000000000 --- a/target/linux/generic/backport-5.10/422-v5.19-mtd-spi-nor-support-eon-en25qh256a.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 6abef37d16d0c570ef5a149e63762fba2a30804b Mon Sep 17 00:00:00 2001 -From: "Leon M. George" -Date: Wed, 30 Mar 2022 16:16:56 +0200 -Subject: [PATCH] mtd: spi-nor: support eon en25qh256a variant - -The EN25QH256A variant of the EN25QH256 doesn't initialize correctly from SFDP -alone and only accesses memory below 8m (addr_width is 4 but read_opcode takes -only 3 bytes). - -Set SNOR_F_4B_OPCODES if the flash chip variant was detected using hwcaps. - -The fix submitted upstream uses the PARSE_SFDP initializer that is not -available in the kernel used with Openwrt. - -Signed-off-by: Leon M. George ---- - drivers/mtd/spi-nor/eon.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/drivers/mtd/spi-nor/eon.c -+++ b/drivers/mtd/spi-nor/eon.c -@@ -8,6 +8,16 @@ - - #include "core.h" - -+static void en25qh256_post_sfdp_fixups(struct spi_nor *nor) -+{ -+ if (nor->params->hwcaps.mask & SNOR_HWCAPS_READ_1_1_4) -+ nor->flags |= SNOR_F_4B_OPCODES; -+} -+ -+static const struct spi_nor_fixups en25qh256_fixups = { -+ .post_sfdp = en25qh256_post_sfdp_fixups, -+}; -+ - static const struct flash_info eon_parts[] = { - /* EON -- en25xxx */ - { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, -@@ -23,7 +33,9 @@ static const struct flash_info eon_parts - { "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128, - SECT_4K | SPI_NOR_DUAL_READ) }, - { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, -- { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, -+ { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, -+ SPI_NOR_DUAL_READ) -+ .fixups = &en25qh256_fixups }, - { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, - }; - diff --git a/target/linux/generic/backport-5.10/500-v5.13-ubifs-default-to-zstd-compression.patch b/target/linux/generic/backport-5.10/500-v5.13-ubifs-default-to-zstd-compression.patch deleted file mode 100644 index dd50c19c27..0000000000 --- a/target/linux/generic/backport-5.10/500-v5.13-ubifs-default-to-zstd-compression.patch +++ /dev/null @@ -1,25 +0,0 @@ -From dcdf415b740923530dc71d89fecc8361078473f5 Mon Sep 17 00:00:00 2001 -From: Rui Salvaterra -Date: Mon, 5 Apr 2021 16:11:55 +0100 -Subject: [PATCH] ubifs: default to zstd compression - -Compared to lzo and zlib, zstd is the best all-around performer, both in terms -of speed and compression ratio. Set it as the default, if available. - -Signed-off-by: Rui Salvaterra ---- - fs/ubifs/sb.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/fs/ubifs/sb.c -+++ b/fs/ubifs/sb.c -@@ -53,6 +53,9 @@ - - static int get_default_compressor(struct ubifs_info *c) - { -+ if (ubifs_compr_present(c, UBIFS_COMPR_ZSTD)) -+ return UBIFS_COMPR_ZSTD; -+ - if (ubifs_compr_present(c, UBIFS_COMPR_LZO)) - return UBIFS_COMPR_LZO; - diff --git a/target/linux/generic/backport-5.10/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch b/target/linux/generic/backport-5.10/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch deleted file mode 100644 index 7d73293532..0000000000 --- a/target/linux/generic/backport-5.10/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch +++ /dev/null @@ -1,88 +0,0 @@ -From: Felix Fietkau -Date: Mon, 8 Feb 2021 11:34:08 -0800 -Subject: [PATCH] net: extract napi poll functionality to __napi_poll() - -This commit introduces a new function __napi_poll() which does the main -logic of the existing napi_poll() function, and will be called by other -functions in later commits. -This idea and implementation is done by Felix Fietkau and -is proposed as part of the patch to move napi work to work_queue -context. -This commit by itself is a code restructure. - -Signed-off-by: Felix Fietkau -Signed-off-by: Wei Wang -Reviewed-by: Alexander Duyck -Signed-off-by: David S. Miller ---- - ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -6813,15 +6813,10 @@ void __netif_napi_del(struct napi_struct - } - EXPORT_SYMBOL(__netif_napi_del); - --static int napi_poll(struct napi_struct *n, struct list_head *repoll) -+static int __napi_poll(struct napi_struct *n, bool *repoll) - { -- void *have; - int work, weight; - -- list_del_init(&n->poll_list); -- -- have = netpoll_poll_lock(n); -- - weight = n->weight; - - /* This NAPI_STATE_SCHED test is for avoiding a race -@@ -6841,7 +6836,7 @@ static int napi_poll(struct napi_struct - n->poll, work, weight); - - if (likely(work < weight)) -- goto out_unlock; -+ return work; - - /* Drivers must not modify the NAPI state if they - * consume the entire weight. In such cases this code -@@ -6850,7 +6845,7 @@ static int napi_poll(struct napi_struct - */ - if (unlikely(napi_disable_pending(n))) { - napi_complete(n); -- goto out_unlock; -+ return work; - } - - if (n->gro_bitmask) { -@@ -6868,12 +6863,29 @@ static int napi_poll(struct napi_struct - if (unlikely(!list_empty(&n->poll_list))) { - pr_warn_once("%s: Budget exhausted after napi rescheduled\n", - n->dev ? n->dev->name : "backlog"); -- goto out_unlock; -+ return work; - } - -- list_add_tail(&n->poll_list, repoll); -+ *repoll = true; -+ -+ return work; -+} -+ -+static int napi_poll(struct napi_struct *n, struct list_head *repoll) -+{ -+ bool do_repoll = false; -+ void *have; -+ int work; -+ -+ list_del_init(&n->poll_list); -+ -+ have = netpoll_poll_lock(n); -+ -+ work = __napi_poll(n, &do_repoll); -+ -+ if (do_repoll) -+ list_add_tail(&n->poll_list, repoll); - --out_unlock: - netpoll_poll_unlock(have); - - return work; diff --git a/target/linux/generic/backport-5.10/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch b/target/linux/generic/backport-5.10/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch deleted file mode 100644 index 9d5fb6e20c..0000000000 --- a/target/linux/generic/backport-5.10/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch +++ /dev/null @@ -1,261 +0,0 @@ -From: Wei Wang -Date: Mon, 8 Feb 2021 11:34:09 -0800 -Subject: [PATCH] net: implement threaded-able napi poll loop support - -This patch allows running each napi poll loop inside its own -kernel thread. -The kthread is created during netif_napi_add() if dev->threaded -is set. And threaded mode is enabled in napi_enable(). We will -provide a way to set dev->threaded and enable threaded mode -without a device up/down in the following patch. - -Once that threaded mode is enabled and the kthread is -started, napi_schedule() will wake-up such thread instead -of scheduling the softirq. - -The threaded poll loop behaves quite likely the net_rx_action, -but it does not have to manipulate local irqs and uses -an explicit scheduling point based on netdev_budget. - -Co-developed-by: Paolo Abeni -Signed-off-by: Paolo Abeni -Co-developed-by: Hannes Frederic Sowa -Signed-off-by: Hannes Frederic Sowa -Co-developed-by: Jakub Kicinski -Signed-off-by: Jakub Kicinski -Signed-off-by: Wei Wang -Reviewed-by: Alexander Duyck -Signed-off-by: David S. Miller ---- - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -356,6 +356,7 @@ struct napi_struct { - struct list_head dev_list; - struct hlist_node napi_hash_node; - unsigned int napi_id; -+ struct task_struct *thread; - }; - - enum { -@@ -366,6 +367,7 @@ enum { - NAPI_STATE_LISTED, /* NAPI added to system lists */ - NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */ - NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */ -+ NAPI_STATE_THREADED, /* The poll is performed inside its own thread*/ - }; - - enum { -@@ -376,6 +378,7 @@ enum { - NAPIF_STATE_LISTED = BIT(NAPI_STATE_LISTED), - NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL), - NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL), -+ NAPIF_STATE_THREADED = BIT(NAPI_STATE_THREADED), - }; - - enum gro_result { -@@ -506,20 +509,7 @@ static inline bool napi_complete(struct - */ - void napi_disable(struct napi_struct *n); - --/** -- * napi_enable - enable NAPI scheduling -- * @n: NAPI context -- * -- * Resume NAPI from being scheduled on this context. -- * Must be paired with napi_disable. -- */ --static inline void napi_enable(struct napi_struct *n) --{ -- BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state)); -- smp_mb__before_atomic(); -- clear_bit(NAPI_STATE_SCHED, &n->state); -- clear_bit(NAPI_STATE_NPSVC, &n->state); --} -+void napi_enable(struct napi_struct *n); - - /** - * napi_synchronize - wait until NAPI is not running -@@ -1865,6 +1855,8 @@ enum netdev_ml_priv_type { - * - * @wol_enabled: Wake-on-LAN is enabled - * -+ * @threaded: napi threaded mode is enabled -+ * - * @net_notifier_list: List of per-net netdev notifier block - * that follow this device when it is moved - * to another network namespace. -@@ -2184,6 +2176,7 @@ struct net_device { - struct lock_class_key *qdisc_running_key; - bool proto_down; - unsigned wol_enabled:1; -+ unsigned threaded:1; - - struct list_head net_notifier_list; - ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -91,6 +91,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -1500,6 +1501,27 @@ void netdev_notify_peers(struct net_devi - } - EXPORT_SYMBOL(netdev_notify_peers); - -+static int napi_threaded_poll(void *data); -+ -+static int napi_kthread_create(struct napi_struct *n) -+{ -+ int err = 0; -+ -+ /* Create and wake up the kthread once to put it in -+ * TASK_INTERRUPTIBLE mode to avoid the blocked task -+ * warning and work with loadavg. -+ */ -+ n->thread = kthread_run(napi_threaded_poll, n, "napi/%s-%d", -+ n->dev->name, n->napi_id); -+ if (IS_ERR(n->thread)) { -+ err = PTR_ERR(n->thread); -+ pr_err("kthread_run failed with err %d\n", err); -+ n->thread = NULL; -+ } -+ -+ return err; -+} -+ - static int __dev_open(struct net_device *dev, struct netlink_ext_ack *extack) - { - const struct net_device_ops *ops = dev->netdev_ops; -@@ -4274,6 +4296,21 @@ int gro_normal_batch __read_mostly = 8; - static inline void ____napi_schedule(struct softnet_data *sd, - struct napi_struct *napi) - { -+ struct task_struct *thread; -+ -+ if (test_bit(NAPI_STATE_THREADED, &napi->state)) { -+ /* Paired with smp_mb__before_atomic() in -+ * napi_enable(). Use READ_ONCE() to guarantee -+ * a complete read on napi->thread. Only call -+ * wake_up_process() when it's not NULL. -+ */ -+ thread = READ_ONCE(napi->thread); -+ if (thread) { -+ wake_up_process(thread); -+ return; -+ } -+ } -+ - list_add_tail(&napi->poll_list, &sd->poll_list); - __raise_softirq_irqoff(NET_RX_SOFTIRQ); - } -@@ -6766,6 +6803,12 @@ void netif_napi_add(struct net_device *d - set_bit(NAPI_STATE_NPSVC, &napi->state); - list_add_rcu(&napi->dev_list, &dev->napi_list); - napi_hash_add(napi); -+ /* Create kthread for this napi if dev->threaded is set. -+ * Clear dev->threaded if kthread creation failed so that -+ * threaded mode will not be enabled in napi_enable(). -+ */ -+ if (dev->threaded && napi_kthread_create(napi)) -+ dev->threaded = 0; - } - EXPORT_SYMBOL(netif_napi_add); - -@@ -6782,9 +6825,28 @@ void napi_disable(struct napi_struct *n) - hrtimer_cancel(&n->timer); - - clear_bit(NAPI_STATE_DISABLE, &n->state); -+ clear_bit(NAPI_STATE_THREADED, &n->state); - } - EXPORT_SYMBOL(napi_disable); - -+/** -+ * napi_enable - enable NAPI scheduling -+ * @n: NAPI context -+ * -+ * Resume NAPI from being scheduled on this context. -+ * Must be paired with napi_disable. -+ */ -+void napi_enable(struct napi_struct *n) -+{ -+ BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state)); -+ smp_mb__before_atomic(); -+ clear_bit(NAPI_STATE_SCHED, &n->state); -+ clear_bit(NAPI_STATE_NPSVC, &n->state); -+ if (n->dev->threaded && n->thread) -+ set_bit(NAPI_STATE_THREADED, &n->state); -+} -+EXPORT_SYMBOL(napi_enable); -+ - static void flush_gro_hash(struct napi_struct *napi) - { - int i; -@@ -6810,6 +6872,11 @@ void __netif_napi_del(struct napi_struct - - flush_gro_hash(napi); - napi->gro_bitmask = 0; -+ -+ if (napi->thread) { -+ kthread_stop(napi->thread); -+ napi->thread = NULL; -+ } - } - EXPORT_SYMBOL(__netif_napi_del); - -@@ -6891,6 +6958,51 @@ static int napi_poll(struct napi_struct - return work; - } - -+static int napi_thread_wait(struct napi_struct *napi) -+{ -+ set_current_state(TASK_INTERRUPTIBLE); -+ -+ while (!kthread_should_stop() && !napi_disable_pending(napi)) { -+ if (test_bit(NAPI_STATE_SCHED, &napi->state)) { -+ WARN_ON(!list_empty(&napi->poll_list)); -+ __set_current_state(TASK_RUNNING); -+ return 0; -+ } -+ -+ schedule(); -+ set_current_state(TASK_INTERRUPTIBLE); -+ } -+ __set_current_state(TASK_RUNNING); -+ return -1; -+} -+ -+static int napi_threaded_poll(void *data) -+{ -+ struct napi_struct *napi = data; -+ void *have; -+ -+ while (!napi_thread_wait(napi)) { -+ for (;;) { -+ bool repoll = false; -+ -+ local_bh_disable(); -+ -+ have = netpoll_poll_lock(napi); -+ __napi_poll(napi, &repoll); -+ netpoll_poll_unlock(have); -+ -+ __kfree_skb_flush(); -+ local_bh_enable(); -+ -+ if (!repoll) -+ break; -+ -+ cond_resched(); -+ } -+ } -+ return 0; -+} -+ - static __latent_entropy void net_rx_action(struct softirq_action *h) - { - struct softnet_data *sd = this_cpu_ptr(&softnet_data); diff --git a/target/linux/generic/backport-5.10/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch b/target/linux/generic/backport-5.10/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch deleted file mode 100644 index 05d5f59f80..0000000000 --- a/target/linux/generic/backport-5.10/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch +++ /dev/null @@ -1,177 +0,0 @@ -From: Wei Wang -Date: Mon, 8 Feb 2021 11:34:10 -0800 -Subject: [PATCH] net: add sysfs attribute to control napi threaded mode - -This patch adds a new sysfs attribute to the network device class. -Said attribute provides a per-device control to enable/disable the -threaded mode for all the napi instances of the given network device, -without the need for a device up/down. -User sets it to 1 or 0 to enable or disable threaded mode. -Note: when switching between threaded and the current softirq based mode -for a napi instance, it will not immediately take effect if the napi is -currently being polled. The mode switch will happen for the next time -napi_schedule() is called. - -Co-developed-by: Paolo Abeni -Signed-off-by: Paolo Abeni -Co-developed-by: Hannes Frederic Sowa -Signed-off-by: Hannes Frederic Sowa -Co-developed-by: Felix Fietkau -Signed-off-by: Felix Fietkau -Signed-off-by: Wei Wang -Reviewed-by: Alexander Duyck -Signed-off-by: David S. Miller ---- - ---- a/Documentation/ABI/testing/sysfs-class-net -+++ b/Documentation/ABI/testing/sysfs-class-net -@@ -337,3 +337,18 @@ Contact: netdev@vger.kernel.org - Description: - 32-bit unsigned integer counting the number of times the link has - been down -+ -+What: /sys/class/net//threaded -+Date: Jan 2021 -+KernelVersion: 5.12 -+Contact: netdev@vger.kernel.org -+Description: -+ Boolean value to control the threaded mode per device. User could -+ set this value to enable/disable threaded mode for all napi -+ belonging to this device, without the need to do device up/down. -+ -+ Possible values: -+ == ================================== -+ 0 threaded mode disabled for this dev -+ 1 threaded mode enabled for this dev -+ == ================================== ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -500,6 +500,8 @@ static inline bool napi_complete(struct - return napi_complete_done(n, 0); - } - -+int dev_set_threaded(struct net_device *dev, bool threaded); -+ - /** - * napi_disable - prevent NAPI from scheduling - * @n: NAPI context ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -4300,8 +4300,9 @@ static inline void ____napi_schedule(str - - if (test_bit(NAPI_STATE_THREADED, &napi->state)) { - /* Paired with smp_mb__before_atomic() in -- * napi_enable(). Use READ_ONCE() to guarantee -- * a complete read on napi->thread. Only call -+ * napi_enable()/dev_set_threaded(). -+ * Use READ_ONCE() to guarantee a complete -+ * read on napi->thread. Only call - * wake_up_process() when it's not NULL. - */ - thread = READ_ONCE(napi->thread); -@@ -6776,6 +6777,49 @@ static void init_gro_hash(struct napi_st - napi->gro_bitmask = 0; - } - -+int dev_set_threaded(struct net_device *dev, bool threaded) -+{ -+ struct napi_struct *napi; -+ int err = 0; -+ -+ if (dev->threaded == threaded) -+ return 0; -+ -+ if (threaded) { -+ list_for_each_entry(napi, &dev->napi_list, dev_list) { -+ if (!napi->thread) { -+ err = napi_kthread_create(napi); -+ if (err) { -+ threaded = false; -+ break; -+ } -+ } -+ } -+ } -+ -+ dev->threaded = threaded; -+ -+ /* Make sure kthread is created before THREADED bit -+ * is set. -+ */ -+ smp_mb__before_atomic(); -+ -+ /* Setting/unsetting threaded mode on a napi might not immediately -+ * take effect, if the current napi instance is actively being -+ * polled. In this case, the switch between threaded mode and -+ * softirq mode will happen in the next round of napi_schedule(). -+ * This should not cause hiccups/stalls to the live traffic. -+ */ -+ list_for_each_entry(napi, &dev->napi_list, dev_list) { -+ if (threaded) -+ set_bit(NAPI_STATE_THREADED, &napi->state); -+ else -+ clear_bit(NAPI_STATE_THREADED, &napi->state); -+ } -+ -+ return err; -+} -+ - void netif_napi_add(struct net_device *dev, struct napi_struct *napi, - int (*poll)(struct napi_struct *, int), int weight) - { ---- a/net/core/net-sysfs.c -+++ b/net/core/net-sysfs.c -@@ -587,6 +587,45 @@ static ssize_t phys_switch_id_show(struc - } - static DEVICE_ATTR_RO(phys_switch_id); - -+static ssize_t threaded_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct net_device *netdev = to_net_dev(dev); -+ ssize_t ret = -EINVAL; -+ -+ if (!rtnl_trylock()) -+ return restart_syscall(); -+ -+ if (dev_isalive(netdev)) -+ ret = sprintf(buf, fmt_dec, netdev->threaded); -+ -+ rtnl_unlock(); -+ return ret; -+} -+ -+static int modify_napi_threaded(struct net_device *dev, unsigned long val) -+{ -+ int ret; -+ -+ if (list_empty(&dev->napi_list)) -+ return -EOPNOTSUPP; -+ -+ if (val != 0 && val != 1) -+ return -EOPNOTSUPP; -+ -+ ret = dev_set_threaded(dev, val); -+ -+ return ret; -+} -+ -+static ssize_t threaded_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t len) -+{ -+ return netdev_store(dev, attr, buf, len, modify_napi_threaded); -+} -+static DEVICE_ATTR_RW(threaded); -+ - static struct attribute *net_class_attrs[] __ro_after_init = { - &dev_attr_netdev_group.attr, - &dev_attr_type.attr, -@@ -619,6 +658,7 @@ static struct attribute *net_class_attrs - &dev_attr_proto_down.attr, - &dev_attr_carrier_up_count.attr, - &dev_attr_carrier_down_count.attr, -+ &dev_attr_threaded.attr, - NULL, - }; - ATTRIBUTE_GROUPS(net_class); diff --git a/target/linux/generic/backport-5.10/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch b/target/linux/generic/backport-5.10/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch deleted file mode 100644 index b83078d51c..0000000000 --- a/target/linux/generic/backport-5.10/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch +++ /dev/null @@ -1,93 +0,0 @@ -From: Wei Wang -Date: Mon, 1 Mar 2021 17:21:13 -0800 -Subject: [PATCH] net: fix race between napi kthread mode and busy poll - -Currently, napi_thread_wait() checks for NAPI_STATE_SCHED bit to -determine if the kthread owns this napi and could call napi->poll() on -it. However, if socket busy poll is enabled, it is possible that the -busy poll thread grabs this SCHED bit (after the previous napi->poll() -invokes napi_complete_done() and clears SCHED bit) and tries to poll -on the same napi. napi_disable() could grab the SCHED bit as well. -This patch tries to fix this race by adding a new bit -NAPI_STATE_SCHED_THREADED in napi->state. This bit gets set in -____napi_schedule() if the threaded mode is enabled, and gets cleared -in napi_complete_done(), and we only poll the napi in kthread if this -bit is set. This helps distinguish the ownership of the napi between -kthread and other scenarios and fixes the race issue. - -Fixes: 29863d41bb6e ("net: implement threaded-able napi poll loop support") -Reported-by: Martin Zaharinov -Suggested-by: Jakub Kicinski -Signed-off-by: Wei Wang -Cc: Alexander Duyck -Cc: Eric Dumazet -Cc: Paolo Abeni -Cc: Hannes Frederic Sowa ---- - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -368,6 +368,7 @@ enum { - NAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */ - NAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */ - NAPI_STATE_THREADED, /* The poll is performed inside its own thread*/ -+ NAPI_STATE_SCHED_THREADED, /* Napi is currently scheduled in threaded mode */ - }; - - enum { -@@ -379,6 +380,7 @@ enum { - NAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL), - NAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL), - NAPIF_STATE_THREADED = BIT(NAPI_STATE_THREADED), -+ NAPIF_STATE_SCHED_THREADED = BIT(NAPI_STATE_SCHED_THREADED), - }; - - enum gro_result { ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -4307,6 +4307,8 @@ static inline void ____napi_schedule(str - */ - thread = READ_ONCE(napi->thread); - if (thread) { -+ if (thread->state != TASK_INTERRUPTIBLE) -+ set_bit(NAPI_STATE_SCHED_THREADED, &napi->state); - wake_up_process(thread); - return; - } -@@ -6568,7 +6570,8 @@ bool napi_complete_done(struct napi_stru - - WARN_ON_ONCE(!(val & NAPIF_STATE_SCHED)); - -- new = val & ~(NAPIF_STATE_MISSED | NAPIF_STATE_SCHED); -+ new = val & ~(NAPIF_STATE_MISSED | NAPIF_STATE_SCHED | -+ NAPIF_STATE_SCHED_THREADED); - - /* If STATE_MISSED was set, leave STATE_SCHED set, - * because we will call napi->poll() one more time. -@@ -7004,16 +7007,25 @@ static int napi_poll(struct napi_struct - - static int napi_thread_wait(struct napi_struct *napi) - { -+ bool woken = false; -+ - set_current_state(TASK_INTERRUPTIBLE); - - while (!kthread_should_stop() && !napi_disable_pending(napi)) { -- if (test_bit(NAPI_STATE_SCHED, &napi->state)) { -+ /* Testing SCHED_THREADED bit here to make sure the current -+ * kthread owns this napi and could poll on this napi. -+ * Testing SCHED bit is not enough because SCHED bit might be -+ * set by some other busy poll thread or by napi_disable(). -+ */ -+ if (test_bit(NAPI_STATE_SCHED_THREADED, &napi->state) || woken) { - WARN_ON(!list_empty(&napi->poll_list)); - __set_current_state(TASK_RUNNING); - return 0; - } - - schedule(); -+ /* woken being true indicates this thread owns this napi. */ -+ woken = true; - set_current_state(TASK_INTERRUPTIBLE); - } - __set_current_state(TASK_RUNNING); diff --git a/target/linux/generic/backport-5.10/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch b/target/linux/generic/backport-5.10/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch deleted file mode 100644 index bf6fd25ac1..0000000000 --- a/target/linux/generic/backport-5.10/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch +++ /dev/null @@ -1,53 +0,0 @@ -From: Paolo Abeni -Date: Fri, 9 Apr 2021 17:24:17 +0200 -Subject: [PATCH] net: fix hangup on napi_disable for threaded napi - -napi_disable() is subject to an hangup, when the threaded -mode is enabled and the napi is under heavy traffic. - -If the relevant napi has been scheduled and the napi_disable() -kicks in before the next napi_threaded_wait() completes - so -that the latter quits due to the napi_disable_pending() condition, -the existing code leaves the NAPI_STATE_SCHED bit set and the -napi_disable() loop waiting for such bit will hang. - -This patch addresses the issue by dropping the NAPI_STATE_DISABLE -bit test in napi_thread_wait(). The later napi_threaded_poll() -iteration will take care of clearing the NAPI_STATE_SCHED. - -This also addresses a related problem reported by Jakub: -before this patch a napi_disable()/napi_enable() pair killed -the napi thread, effectively disabling the threaded mode. -On the patched kernel napi_disable() simply stops scheduling -the relevant thread. - -v1 -> v2: - - let the main napi_thread_poll() loop clear the SCHED bit - -Reported-by: Jakub Kicinski -Fixes: 29863d41bb6e ("net: implement threaded-able napi poll loop support") -Signed-off-by: Paolo Abeni -Reviewed-by: Eric Dumazet -Link: https://lore.kernel.org/r/883923fa22745a9589e8610962b7dc59df09fb1f.1617981844.git.pabeni@redhat.com -Signed-off-by: Jakub Kicinski ---- - ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -7011,7 +7011,7 @@ static int napi_thread_wait(struct napi_ - - set_current_state(TASK_INTERRUPTIBLE); - -- while (!kthread_should_stop() && !napi_disable_pending(napi)) { -+ while (!kthread_should_stop()) { - /* Testing SCHED_THREADED bit here to make sure the current - * kthread owns this napi and could poll on this napi. - * Testing SCHED bit is not enough because SCHED bit might be -@@ -7029,6 +7029,7 @@ static int napi_thread_wait(struct napi_ - set_current_state(TASK_INTERRUPTIBLE); - } - __set_current_state(TASK_RUNNING); -+ - return -1; - } - diff --git a/target/linux/generic/backport-5.10/605-v5.12-net-export-dev_set_threaded-symbol.patch b/target/linux/generic/backport-5.10/605-v5.12-net-export-dev_set_threaded-symbol.patch deleted file mode 100644 index 2d9c1875ce..0000000000 --- a/target/linux/generic/backport-5.10/605-v5.12-net-export-dev_set_threaded-symbol.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: Lorenzo Bianconi -Date: Sun, 14 Mar 2021 15:49:19 +0100 -Subject: [PATCH] net: export dev_set_threaded symbol - -For wireless devices (e.g. mt76 driver) multiple net_devices belongs to -the same wireless phy and the napi object is registered in a dummy -netdevice related to the wireless phy. -Export dev_set_threaded in order to be reused in device drivers enabling -threaded NAPI. - -Signed-off-by: Lorenzo Bianconi -Signed-off-by: David S. Miller ---- - ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -6822,6 +6822,7 @@ int dev_set_threaded(struct net_device * - - return err; - } -+EXPORT_SYMBOL(dev_set_threaded); - - void netif_napi_add(struct net_device *dev, struct napi_struct *napi, - int (*poll)(struct napi_struct *, int), int weight) diff --git a/target/linux/generic/backport-5.10/610-v5.13-00-netfilter-flowtable-add-hash-offset-field-to-tuple.patch b/target/linux/generic/backport-5.10/610-v5.13-00-netfilter-flowtable-add-hash-offset-field-to-tuple.patch deleted file mode 100644 index c881ccfcb0..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-00-netfilter-flowtable-add-hash-offset-field-to-tuple.patch +++ /dev/null @@ -1,52 +0,0 @@ -From: Pablo Neira Ayuso -Date: Fri, 20 Nov 2020 13:49:13 +0100 -Subject: [PATCH] netfilter: flowtable: add hash offset field to tuple - -Add a placeholder field to calculate hash tuple offset. Similar to -2c407aca6497 ("netfilter: conntrack: avoid gcc-10 zero-length-bounds -warning"). - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -107,6 +107,10 @@ struct flow_offload_tuple { - - u8 l3proto; - u8 l4proto; -+ -+ /* All members above are keys for lookups, see flow_offload_hash(). */ -+ struct { } __hash; -+ - u8 dir; - - u16 mtu; ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -191,14 +191,14 @@ static u32 flow_offload_hash(const void - { - const struct flow_offload_tuple *tuple = data; - -- return jhash(tuple, offsetof(struct flow_offload_tuple, dir), seed); -+ return jhash(tuple, offsetof(struct flow_offload_tuple, __hash), seed); - } - - static u32 flow_offload_hash_obj(const void *data, u32 len, u32 seed) - { - const struct flow_offload_tuple_rhash *tuplehash = data; - -- return jhash(&tuplehash->tuple, offsetof(struct flow_offload_tuple, dir), seed); -+ return jhash(&tuplehash->tuple, offsetof(struct flow_offload_tuple, __hash), seed); - } - - static int flow_offload_hash_cmp(struct rhashtable_compare_arg *arg, -@@ -207,7 +207,7 @@ static int flow_offload_hash_cmp(struct - const struct flow_offload_tuple *tuple = arg->key; - const struct flow_offload_tuple_rhash *x = ptr; - -- if (memcmp(&x->tuple, tuple, offsetof(struct flow_offload_tuple, dir))) -+ if (memcmp(&x->tuple, tuple, offsetof(struct flow_offload_tuple, __hash))) - return 1; - - return 0; diff --git a/target/linux/generic/backport-5.10/610-v5.13-01-netfilter-flowtable-separate-replace-destroy-and-sta.patch b/target/linux/generic/backport-5.10/610-v5.13-01-netfilter-flowtable-separate-replace-destroy-and-sta.patch deleted file mode 100644 index 478a2e0ec2..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-01-netfilter-flowtable-separate-replace-destroy-and-sta.patch +++ /dev/null @@ -1,98 +0,0 @@ -From: Oz Shlomo -Date: Tue, 23 Mar 2021 00:56:19 +0100 -Subject: [PATCH] netfilter: flowtable: separate replace, destroy and - stats to different workqueues - -Currently the flow table offload replace, destroy and stats work items are -executed on a single workqueue. As such, DESTROY and STATS commands may -be backloged after a burst of REPLACE work items. This scenario can bloat -up memory and may cause active connections to age. - -Instatiate add, del and stats workqueues to avoid backlogs of non-dependent -actions. Provide sysfs control over the workqueue attributes, allowing -userspace applications to control the workqueue cpumask. - -Signed-off-by: Oz Shlomo -Reviewed-by: Paul Blakey -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_offload.c -+++ b/net/netfilter/nf_flow_table_offload.c -@@ -13,7 +13,9 @@ - #include - #include - --static struct workqueue_struct *nf_flow_offload_wq; -+static struct workqueue_struct *nf_flow_offload_add_wq; -+static struct workqueue_struct *nf_flow_offload_del_wq; -+static struct workqueue_struct *nf_flow_offload_stats_wq; - - struct flow_offload_work { - struct list_head list; -@@ -827,7 +829,12 @@ static void flow_offload_work_handler(st - - static void flow_offload_queue_work(struct flow_offload_work *offload) - { -- queue_work(nf_flow_offload_wq, &offload->work); -+ if (offload->cmd == FLOW_CLS_REPLACE) -+ queue_work(nf_flow_offload_add_wq, &offload->work); -+ else if (offload->cmd == FLOW_CLS_DESTROY) -+ queue_work(nf_flow_offload_del_wq, &offload->work); -+ else -+ queue_work(nf_flow_offload_stats_wq, &offload->work); - } - - static struct flow_offload_work * -@@ -899,8 +906,11 @@ void nf_flow_offload_stats(struct nf_flo - - void nf_flow_table_offload_flush(struct nf_flowtable *flowtable) - { -- if (nf_flowtable_hw_offload(flowtable)) -- flush_workqueue(nf_flow_offload_wq); -+ if (nf_flowtable_hw_offload(flowtable)) { -+ flush_workqueue(nf_flow_offload_add_wq); -+ flush_workqueue(nf_flow_offload_del_wq); -+ flush_workqueue(nf_flow_offload_stats_wq); -+ } - } - - static int nf_flow_table_block_setup(struct nf_flowtable *flowtable, -@@ -1017,15 +1027,33 @@ EXPORT_SYMBOL_GPL(nf_flow_table_offload_ - - int nf_flow_table_offload_init(void) - { -- nf_flow_offload_wq = alloc_workqueue("nf_flow_table_offload", -- WQ_UNBOUND, 0); -- if (!nf_flow_offload_wq) -+ nf_flow_offload_add_wq = alloc_workqueue("nf_ft_offload_add", -+ WQ_UNBOUND | WQ_SYSFS, 0); -+ if (!nf_flow_offload_add_wq) - return -ENOMEM; - -+ nf_flow_offload_del_wq = alloc_workqueue("nf_ft_offload_del", -+ WQ_UNBOUND | WQ_SYSFS, 0); -+ if (!nf_flow_offload_del_wq) -+ goto err_del_wq; -+ -+ nf_flow_offload_stats_wq = alloc_workqueue("nf_ft_offload_stats", -+ WQ_UNBOUND | WQ_SYSFS, 0); -+ if (!nf_flow_offload_stats_wq) -+ goto err_stats_wq; -+ - return 0; -+ -+err_stats_wq: -+ destroy_workqueue(nf_flow_offload_del_wq); -+err_del_wq: -+ destroy_workqueue(nf_flow_offload_add_wq); -+ return -ENOMEM; - } - - void nf_flow_table_offload_exit(void) - { -- destroy_workqueue(nf_flow_offload_wq); -+ destroy_workqueue(nf_flow_offload_add_wq); -+ destroy_workqueue(nf_flow_offload_del_wq); -+ destroy_workqueue(nf_flow_offload_stats_wq); - } diff --git a/target/linux/generic/backport-5.10/610-v5.13-03-netfilter-conntrack-Remove-unused-variable-declarati.patch b/target/linux/generic/backport-5.10/610-v5.13-03-netfilter-conntrack-Remove-unused-variable-declarati.patch deleted file mode 100644 index 37e80d989d..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-03-netfilter-conntrack-Remove-unused-variable-declarati.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: YueHaibing -Date: Tue, 23 Mar 2021 00:56:21 +0100 -Subject: [PATCH] netfilter: conntrack: Remove unused variable - declaration - -commit e97c3e278e95 ("tproxy: split off ipv6 defragmentation to a separate -module") left behind this. - -Signed-off-by: YueHaibing -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/ipv6/nf_conntrack_ipv6.h -+++ b/include/net/netfilter/ipv6/nf_conntrack_ipv6.h -@@ -4,7 +4,4 @@ - - extern const struct nf_conntrack_l4proto nf_conntrack_l4proto_icmpv6; - --#include --extern struct ctl_table nf_ct_ipv6_sysctl_table[]; -- - #endif /* _NF_CONNTRACK_IPV6_H*/ diff --git a/target/linux/generic/backport-5.10/610-v5.13-04-netfilter-flowtable-consolidate-skb_try_make_writabl.patch b/target/linux/generic/backport-5.10/610-v5.13-04-netfilter-flowtable-consolidate-skb_try_make_writabl.patch deleted file mode 100644 index 9fd01b465e..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-04-netfilter-flowtable-consolidate-skb_try_make_writabl.patch +++ /dev/null @@ -1,291 +0,0 @@ -From: Pablo Neira Ayuso -Date: Tue, 23 Mar 2021 00:56:22 +0100 -Subject: [PATCH] netfilter: flowtable: consolidate - skb_try_make_writable() call - -Fetch the layer 4 header size to be mangled by NAT when building the -tuple, then use it to make writable the network and the transport -headers. After this update, the NAT routines now assumes that the skbuff -area is writable. Do the pointer refetch only after the single -skb_try_make_writable() call. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -394,9 +394,6 @@ static int nf_flow_nat_port_tcp(struct s - { - struct tcphdr *tcph; - -- if (skb_try_make_writable(skb, thoff + sizeof(*tcph))) -- return -1; -- - tcph = (void *)(skb_network_header(skb) + thoff); - inet_proto_csum_replace2(&tcph->check, skb, port, new_port, false); - -@@ -408,9 +405,6 @@ static int nf_flow_nat_port_udp(struct s - { - struct udphdr *udph; - -- if (skb_try_make_writable(skb, thoff + sizeof(*udph))) -- return -1; -- - udph = (void *)(skb_network_header(skb) + thoff); - if (udph->check || skb->ip_summed == CHECKSUM_PARTIAL) { - inet_proto_csum_replace2(&udph->check, skb, port, -@@ -446,9 +440,6 @@ int nf_flow_snat_port(const struct flow_ - struct flow_ports *hdr; - __be16 port, new_port; - -- if (skb_try_make_writable(skb, thoff + sizeof(*hdr))) -- return -1; -- - hdr = (void *)(skb_network_header(skb) + thoff); - - switch (dir) { -@@ -477,9 +468,6 @@ int nf_flow_dnat_port(const struct flow_ - struct flow_ports *hdr; - __be16 port, new_port; - -- if (skb_try_make_writable(skb, thoff + sizeof(*hdr))) -- return -1; -- - hdr = (void *)(skb_network_header(skb) + thoff); - - switch (dir) { ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -39,9 +39,6 @@ static int nf_flow_nat_ip_tcp(struct sk_ - { - struct tcphdr *tcph; - -- if (skb_try_make_writable(skb, thoff + sizeof(*tcph))) -- return -1; -- - tcph = (void *)(skb_network_header(skb) + thoff); - inet_proto_csum_replace4(&tcph->check, skb, addr, new_addr, true); - -@@ -53,9 +50,6 @@ static int nf_flow_nat_ip_udp(struct sk_ - { - struct udphdr *udph; - -- if (skb_try_make_writable(skb, thoff + sizeof(*udph))) -- return -1; -- - udph = (void *)(skb_network_header(skb) + thoff); - if (udph->check || skb->ip_summed == CHECKSUM_PARTIAL) { - inet_proto_csum_replace4(&udph->check, skb, addr, -@@ -136,19 +130,17 @@ static int nf_flow_dnat_ip(const struct - } - - static int nf_flow_nat_ip(const struct flow_offload *flow, struct sk_buff *skb, -- unsigned int thoff, enum flow_offload_tuple_dir dir) -+ unsigned int thoff, enum flow_offload_tuple_dir dir, -+ struct iphdr *iph) - { -- struct iphdr *iph = ip_hdr(skb); -- - if (test_bit(NF_FLOW_SNAT, &flow->flags) && - (nf_flow_snat_port(flow, skb, thoff, iph->protocol, dir) < 0 || -- nf_flow_snat_ip(flow, skb, ip_hdr(skb), thoff, dir) < 0)) -+ nf_flow_snat_ip(flow, skb, iph, thoff, dir) < 0)) - return -1; - -- iph = ip_hdr(skb); - if (test_bit(NF_FLOW_DNAT, &flow->flags) && - (nf_flow_dnat_port(flow, skb, thoff, iph->protocol, dir) < 0 || -- nf_flow_dnat_ip(flow, skb, ip_hdr(skb), thoff, dir) < 0)) -+ nf_flow_dnat_ip(flow, skb, iph, thoff, dir) < 0)) - return -1; - - return 0; -@@ -160,10 +152,10 @@ static bool ip_has_options(unsigned int - } - - static int nf_flow_tuple_ip(struct sk_buff *skb, const struct net_device *dev, -- struct flow_offload_tuple *tuple) -+ struct flow_offload_tuple *tuple, u32 *hdrsize) - { -- unsigned int thoff, hdrsize; - struct flow_ports *ports; -+ unsigned int thoff; - struct iphdr *iph; - - if (!pskb_may_pull(skb, sizeof(*iph))) -@@ -178,10 +170,10 @@ static int nf_flow_tuple_ip(struct sk_bu - - switch (iph->protocol) { - case IPPROTO_TCP: -- hdrsize = sizeof(struct tcphdr); -+ *hdrsize = sizeof(struct tcphdr); - break; - case IPPROTO_UDP: -- hdrsize = sizeof(struct udphdr); -+ *hdrsize = sizeof(struct udphdr); - break; - default: - return -1; -@@ -191,7 +183,7 @@ static int nf_flow_tuple_ip(struct sk_bu - return -1; - - thoff = iph->ihl * 4; -- if (!pskb_may_pull(skb, thoff + hdrsize)) -+ if (!pskb_may_pull(skb, thoff + *hdrsize)) - return -1; - - iph = ip_hdr(skb); -@@ -252,11 +244,12 @@ nf_flow_offload_ip_hook(void *priv, stru - unsigned int thoff; - struct iphdr *iph; - __be32 nexthop; -+ u32 hdrsize; - - if (skb->protocol != htons(ETH_P_IP)) - return NF_ACCEPT; - -- if (nf_flow_tuple_ip(skb, state->in, &tuple) < 0) -+ if (nf_flow_tuple_ip(skb, state->in, &tuple, &hdrsize) < 0) - return NF_ACCEPT; - - tuplehash = flow_offload_lookup(flow_table, &tuple); -@@ -271,11 +264,13 @@ nf_flow_offload_ip_hook(void *priv, stru - if (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu))) - return NF_ACCEPT; - -- if (skb_try_make_writable(skb, sizeof(*iph))) -+ iph = ip_hdr(skb); -+ thoff = iph->ihl * 4; -+ if (skb_try_make_writable(skb, thoff + hdrsize)) - return NF_DROP; - -- thoff = ip_hdr(skb)->ihl * 4; -- if (nf_flow_state_check(flow, ip_hdr(skb)->protocol, skb, thoff)) -+ iph = ip_hdr(skb); -+ if (nf_flow_state_check(flow, iph->protocol, skb, thoff)) - return NF_ACCEPT; - - flow_offload_refresh(flow_table, flow); -@@ -285,10 +280,9 @@ nf_flow_offload_ip_hook(void *priv, stru - return NF_ACCEPT; - } - -- if (nf_flow_nat_ip(flow, skb, thoff, dir) < 0) -+ if (nf_flow_nat_ip(flow, skb, thoff, dir, iph) < 0) - return NF_DROP; - -- iph = ip_hdr(skb); - ip_decrease_ttl(iph); - skb->tstamp = 0; - -@@ -317,9 +311,6 @@ static int nf_flow_nat_ipv6_tcp(struct s - { - struct tcphdr *tcph; - -- if (skb_try_make_writable(skb, thoff + sizeof(*tcph))) -- return -1; -- - tcph = (void *)(skb_network_header(skb) + thoff); - inet_proto_csum_replace16(&tcph->check, skb, addr->s6_addr32, - new_addr->s6_addr32, true); -@@ -333,9 +324,6 @@ static int nf_flow_nat_ipv6_udp(struct s - { - struct udphdr *udph; - -- if (skb_try_make_writable(skb, thoff + sizeof(*udph))) -- return -1; -- - udph = (void *)(skb_network_header(skb) + thoff); - if (udph->check || skb->ip_summed == CHECKSUM_PARTIAL) { - inet_proto_csum_replace16(&udph->check, skb, addr->s6_addr32, -@@ -417,31 +405,30 @@ static int nf_flow_dnat_ipv6(const struc - - static int nf_flow_nat_ipv6(const struct flow_offload *flow, - struct sk_buff *skb, -- enum flow_offload_tuple_dir dir) -+ enum flow_offload_tuple_dir dir, -+ struct ipv6hdr *ip6h) - { -- struct ipv6hdr *ip6h = ipv6_hdr(skb); - unsigned int thoff = sizeof(*ip6h); - - if (test_bit(NF_FLOW_SNAT, &flow->flags) && - (nf_flow_snat_port(flow, skb, thoff, ip6h->nexthdr, dir) < 0 || -- nf_flow_snat_ipv6(flow, skb, ipv6_hdr(skb), thoff, dir) < 0)) -+ nf_flow_snat_ipv6(flow, skb, ip6h, thoff, dir) < 0)) - return -1; - -- ip6h = ipv6_hdr(skb); - if (test_bit(NF_FLOW_DNAT, &flow->flags) && - (nf_flow_dnat_port(flow, skb, thoff, ip6h->nexthdr, dir) < 0 || -- nf_flow_dnat_ipv6(flow, skb, ipv6_hdr(skb), thoff, dir) < 0)) -+ nf_flow_dnat_ipv6(flow, skb, ip6h, thoff, dir) < 0)) - return -1; - - return 0; - } - - static int nf_flow_tuple_ipv6(struct sk_buff *skb, const struct net_device *dev, -- struct flow_offload_tuple *tuple) -+ struct flow_offload_tuple *tuple, u32 *hdrsize) - { -- unsigned int thoff, hdrsize; - struct flow_ports *ports; - struct ipv6hdr *ip6h; -+ unsigned int thoff; - - if (!pskb_may_pull(skb, sizeof(*ip6h))) - return -1; -@@ -450,10 +437,10 @@ static int nf_flow_tuple_ipv6(struct sk_ - - switch (ip6h->nexthdr) { - case IPPROTO_TCP: -- hdrsize = sizeof(struct tcphdr); -+ *hdrsize = sizeof(struct tcphdr); - break; - case IPPROTO_UDP: -- hdrsize = sizeof(struct udphdr); -+ *hdrsize = sizeof(struct udphdr); - break; - default: - return -1; -@@ -463,7 +450,7 @@ static int nf_flow_tuple_ipv6(struct sk_ - return -1; - - thoff = sizeof(*ip6h); -- if (!pskb_may_pull(skb, thoff + hdrsize)) -+ if (!pskb_may_pull(skb, thoff + *hdrsize)) - return -1; - - ip6h = ipv6_hdr(skb); -@@ -493,11 +480,12 @@ nf_flow_offload_ipv6_hook(void *priv, st - struct net_device *outdev; - struct ipv6hdr *ip6h; - struct rt6_info *rt; -+ u32 hdrsize; - - if (skb->protocol != htons(ETH_P_IPV6)) - return NF_ACCEPT; - -- if (nf_flow_tuple_ipv6(skb, state->in, &tuple) < 0) -+ if (nf_flow_tuple_ipv6(skb, state->in, &tuple, &hdrsize) < 0) - return NF_ACCEPT; - - tuplehash = flow_offload_lookup(flow_table, &tuple); -@@ -523,13 +511,13 @@ nf_flow_offload_ipv6_hook(void *priv, st - return NF_ACCEPT; - } - -- if (skb_try_make_writable(skb, sizeof(*ip6h))) -+ if (skb_try_make_writable(skb, sizeof(*ip6h) + hdrsize)) - return NF_DROP; - -- if (nf_flow_nat_ipv6(flow, skb, dir) < 0) -+ ip6h = ipv6_hdr(skb); -+ if (nf_flow_nat_ipv6(flow, skb, dir, ip6h) < 0) - return NF_DROP; - -- ip6h = ipv6_hdr(skb); - ip6h->hop_limit--; - skb->tstamp = 0; - diff --git a/target/linux/generic/backport-5.10/610-v5.13-05-netfilter-flowtable-move-skb_try_make_writable-befor.patch b/target/linux/generic/backport-5.10/610-v5.13-05-netfilter-flowtable-move-skb_try_make_writable-befor.patch deleted file mode 100644 index 84e294de7a..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-05-netfilter-flowtable-move-skb_try_make_writable-befor.patch +++ /dev/null @@ -1,35 +0,0 @@ -From: Pablo Neira Ayuso -Date: Tue, 23 Mar 2021 00:56:23 +0100 -Subject: [PATCH] netfilter: flowtable: move skb_try_make_writable() - before NAT in IPv4 - -For consistency with the IPv6 flowtable datapath and to make sure the -skbuff is writable right before the NAT header updates. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -266,10 +266,6 @@ nf_flow_offload_ip_hook(void *priv, stru - - iph = ip_hdr(skb); - thoff = iph->ihl * 4; -- if (skb_try_make_writable(skb, thoff + hdrsize)) -- return NF_DROP; -- -- iph = ip_hdr(skb); - if (nf_flow_state_check(flow, iph->protocol, skb, thoff)) - return NF_ACCEPT; - -@@ -280,6 +276,10 @@ nf_flow_offload_ip_hook(void *priv, stru - return NF_ACCEPT; - } - -+ if (skb_try_make_writable(skb, thoff + hdrsize)) -+ return NF_DROP; -+ -+ iph = ip_hdr(skb); - if (nf_flow_nat_ip(flow, skb, thoff, dir, iph) < 0) - return NF_DROP; - diff --git a/target/linux/generic/backport-5.10/610-v5.13-06-netfilter-flowtable-move-FLOW_OFFLOAD_DIR_MAX-away-f.patch b/target/linux/generic/backport-5.10/610-v5.13-06-netfilter-flowtable-move-FLOW_OFFLOAD_DIR_MAX-away-f.patch deleted file mode 100644 index 64a0e42079..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-06-netfilter-flowtable-move-FLOW_OFFLOAD_DIR_MAX-away-f.patch +++ /dev/null @@ -1,82 +0,0 @@ -From: Pablo Neira Ayuso -Date: Tue, 23 Mar 2021 00:56:24 +0100 -Subject: [PATCH] netfilter: flowtable: move FLOW_OFFLOAD_DIR_MAX away - from enumeration - -This allows to remove the default case which should not ever happen and -that was added to avoid gcc warnings on unhandled FLOW_OFFLOAD_DIR_MAX -enumeration case. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -86,8 +86,8 @@ static inline bool nf_flowtable_hw_offlo - enum flow_offload_tuple_dir { - FLOW_OFFLOAD_DIR_ORIGINAL = IP_CT_DIR_ORIGINAL, - FLOW_OFFLOAD_DIR_REPLY = IP_CT_DIR_REPLY, -- FLOW_OFFLOAD_DIR_MAX = IP_CT_DIR_MAX - }; -+#define FLOW_OFFLOAD_DIR_MAX IP_CT_DIR_MAX - - struct flow_offload_tuple { - union { ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -453,8 +453,6 @@ int nf_flow_snat_port(const struct flow_ - new_port = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.src_port; - hdr->dest = new_port; - break; -- default: -- return -1; - } - - return nf_flow_nat_port(skb, thoff, protocol, port, new_port); -@@ -481,8 +479,6 @@ int nf_flow_dnat_port(const struct flow_ - new_port = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.dst_port; - hdr->source = new_port; - break; -- default: -- return -1; - } - - return nf_flow_nat_port(skb, thoff, protocol, port, new_port); ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -96,8 +96,6 @@ static int nf_flow_snat_ip(const struct - new_addr = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.src_v4.s_addr; - iph->daddr = new_addr; - break; -- default: -- return -1; - } - csum_replace4(&iph->check, addr, new_addr); - -@@ -121,8 +119,6 @@ static int nf_flow_dnat_ip(const struct - new_addr = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.dst_v4.s_addr; - iph->saddr = new_addr; - break; -- default: -- return -1; - } - csum_replace4(&iph->check, addr, new_addr); - -@@ -371,8 +367,6 @@ static int nf_flow_snat_ipv6(const struc - new_addr = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.src_v6; - ip6h->daddr = new_addr; - break; -- default: -- return -1; - } - - return nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr); -@@ -396,8 +390,6 @@ static int nf_flow_dnat_ipv6(const struc - new_addr = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.dst_v6; - ip6h->saddr = new_addr; - break; -- default: -- return -1; - } - - return nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr); diff --git a/target/linux/generic/backport-5.10/610-v5.13-07-netfilter-flowtable-fast-NAT-functions-never-fail.patch b/target/linux/generic/backport-5.10/610-v5.13-07-netfilter-flowtable-fast-NAT-functions-never-fail.patch deleted file mode 100644 index 2224e095c9..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-07-netfilter-flowtable-fast-NAT-functions-never-fail.patch +++ /dev/null @@ -1,394 +0,0 @@ -From: Pablo Neira Ayuso -Date: Tue, 23 Mar 2021 00:56:25 +0100 -Subject: [PATCH] netfilter: flowtable: fast NAT functions never fail - -Simplify existing fast NAT routines by returning void. After the -skb_try_make_writable() call consolidation, these routines cannot ever -fail. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -228,12 +228,12 @@ void nf_flow_table_free(struct nf_flowta - - void flow_offload_teardown(struct flow_offload *flow); - --int nf_flow_snat_port(const struct flow_offload *flow, -- struct sk_buff *skb, unsigned int thoff, -- u8 protocol, enum flow_offload_tuple_dir dir); --int nf_flow_dnat_port(const struct flow_offload *flow, -- struct sk_buff *skb, unsigned int thoff, -- u8 protocol, enum flow_offload_tuple_dir dir); -+void nf_flow_snat_port(const struct flow_offload *flow, -+ struct sk_buff *skb, unsigned int thoff, -+ u8 protocol, enum flow_offload_tuple_dir dir); -+void nf_flow_dnat_port(const struct flow_offload *flow, -+ struct sk_buff *skb, unsigned int thoff, -+ u8 protocol, enum flow_offload_tuple_dir dir); - - struct flow_ports { - __be16 source, dest; ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -388,20 +388,17 @@ static void nf_flow_offload_work_gc(stru - queue_delayed_work(system_power_efficient_wq, &flow_table->gc_work, HZ); - } - -- --static int nf_flow_nat_port_tcp(struct sk_buff *skb, unsigned int thoff, -- __be16 port, __be16 new_port) -+static void nf_flow_nat_port_tcp(struct sk_buff *skb, unsigned int thoff, -+ __be16 port, __be16 new_port) - { - struct tcphdr *tcph; - - tcph = (void *)(skb_network_header(skb) + thoff); - inet_proto_csum_replace2(&tcph->check, skb, port, new_port, false); -- -- return 0; - } - --static int nf_flow_nat_port_udp(struct sk_buff *skb, unsigned int thoff, -- __be16 port, __be16 new_port) -+static void nf_flow_nat_port_udp(struct sk_buff *skb, unsigned int thoff, -+ __be16 port, __be16 new_port) - { - struct udphdr *udph; - -@@ -412,30 +409,24 @@ static int nf_flow_nat_port_udp(struct s - if (!udph->check) - udph->check = CSUM_MANGLED_0; - } -- -- return 0; - } - --static int nf_flow_nat_port(struct sk_buff *skb, unsigned int thoff, -- u8 protocol, __be16 port, __be16 new_port) -+static void nf_flow_nat_port(struct sk_buff *skb, unsigned int thoff, -+ u8 protocol, __be16 port, __be16 new_port) - { - switch (protocol) { - case IPPROTO_TCP: -- if (nf_flow_nat_port_tcp(skb, thoff, port, new_port) < 0) -- return NF_DROP; -+ nf_flow_nat_port_tcp(skb, thoff, port, new_port); - break; - case IPPROTO_UDP: -- if (nf_flow_nat_port_udp(skb, thoff, port, new_port) < 0) -- return NF_DROP; -+ nf_flow_nat_port_udp(skb, thoff, port, new_port); - break; - } -- -- return 0; - } - --int nf_flow_snat_port(const struct flow_offload *flow, -- struct sk_buff *skb, unsigned int thoff, -- u8 protocol, enum flow_offload_tuple_dir dir) -+void nf_flow_snat_port(const struct flow_offload *flow, -+ struct sk_buff *skb, unsigned int thoff, -+ u8 protocol, enum flow_offload_tuple_dir dir) - { - struct flow_ports *hdr; - __be16 port, new_port; -@@ -455,13 +446,13 @@ int nf_flow_snat_port(const struct flow_ - break; - } - -- return nf_flow_nat_port(skb, thoff, protocol, port, new_port); -+ nf_flow_nat_port(skb, thoff, protocol, port, new_port); - } - EXPORT_SYMBOL_GPL(nf_flow_snat_port); - --int nf_flow_dnat_port(const struct flow_offload *flow, -- struct sk_buff *skb, unsigned int thoff, -- u8 protocol, enum flow_offload_tuple_dir dir) -+void nf_flow_dnat_port(const struct flow_offload *flow, struct sk_buff *skb, -+ unsigned int thoff, u8 protocol, -+ enum flow_offload_tuple_dir dir) - { - struct flow_ports *hdr; - __be16 port, new_port; -@@ -481,7 +472,7 @@ int nf_flow_dnat_port(const struct flow_ - break; - } - -- return nf_flow_nat_port(skb, thoff, protocol, port, new_port); -+ nf_flow_nat_port(skb, thoff, protocol, port, new_port); - } - EXPORT_SYMBOL_GPL(nf_flow_dnat_port); - ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -34,19 +34,17 @@ static int nf_flow_state_check(struct fl - return 0; - } - --static int nf_flow_nat_ip_tcp(struct sk_buff *skb, unsigned int thoff, -- __be32 addr, __be32 new_addr) -+static void nf_flow_nat_ip_tcp(struct sk_buff *skb, unsigned int thoff, -+ __be32 addr, __be32 new_addr) - { - struct tcphdr *tcph; - - tcph = (void *)(skb_network_header(skb) + thoff); - inet_proto_csum_replace4(&tcph->check, skb, addr, new_addr, true); -- -- return 0; - } - --static int nf_flow_nat_ip_udp(struct sk_buff *skb, unsigned int thoff, -- __be32 addr, __be32 new_addr) -+static void nf_flow_nat_ip_udp(struct sk_buff *skb, unsigned int thoff, -+ __be32 addr, __be32 new_addr) - { - struct udphdr *udph; - -@@ -57,31 +55,25 @@ static int nf_flow_nat_ip_udp(struct sk_ - if (!udph->check) - udph->check = CSUM_MANGLED_0; - } -- -- return 0; - } - --static int nf_flow_nat_ip_l4proto(struct sk_buff *skb, struct iphdr *iph, -- unsigned int thoff, __be32 addr, -- __be32 new_addr) -+static void nf_flow_nat_ip_l4proto(struct sk_buff *skb, struct iphdr *iph, -+ unsigned int thoff, __be32 addr, -+ __be32 new_addr) - { - switch (iph->protocol) { - case IPPROTO_TCP: -- if (nf_flow_nat_ip_tcp(skb, thoff, addr, new_addr) < 0) -- return NF_DROP; -+ nf_flow_nat_ip_tcp(skb, thoff, addr, new_addr); - break; - case IPPROTO_UDP: -- if (nf_flow_nat_ip_udp(skb, thoff, addr, new_addr) < 0) -- return NF_DROP; -+ nf_flow_nat_ip_udp(skb, thoff, addr, new_addr); - break; - } -- -- return 0; - } - --static int nf_flow_snat_ip(const struct flow_offload *flow, struct sk_buff *skb, -- struct iphdr *iph, unsigned int thoff, -- enum flow_offload_tuple_dir dir) -+static void nf_flow_snat_ip(const struct flow_offload *flow, -+ struct sk_buff *skb, struct iphdr *iph, -+ unsigned int thoff, enum flow_offload_tuple_dir dir) - { - __be32 addr, new_addr; - -@@ -99,12 +91,12 @@ static int nf_flow_snat_ip(const struct - } - csum_replace4(&iph->check, addr, new_addr); - -- return nf_flow_nat_ip_l4proto(skb, iph, thoff, addr, new_addr); -+ nf_flow_nat_ip_l4proto(skb, iph, thoff, addr, new_addr); - } - --static int nf_flow_dnat_ip(const struct flow_offload *flow, struct sk_buff *skb, -- struct iphdr *iph, unsigned int thoff, -- enum flow_offload_tuple_dir dir) -+static void nf_flow_dnat_ip(const struct flow_offload *flow, -+ struct sk_buff *skb, struct iphdr *iph, -+ unsigned int thoff, enum flow_offload_tuple_dir dir) - { - __be32 addr, new_addr; - -@@ -122,24 +114,21 @@ static int nf_flow_dnat_ip(const struct - } - csum_replace4(&iph->check, addr, new_addr); - -- return nf_flow_nat_ip_l4proto(skb, iph, thoff, addr, new_addr); -+ nf_flow_nat_ip_l4proto(skb, iph, thoff, addr, new_addr); - } - --static int nf_flow_nat_ip(const struct flow_offload *flow, struct sk_buff *skb, -+static void nf_flow_nat_ip(const struct flow_offload *flow, struct sk_buff *skb, - unsigned int thoff, enum flow_offload_tuple_dir dir, - struct iphdr *iph) - { -- if (test_bit(NF_FLOW_SNAT, &flow->flags) && -- (nf_flow_snat_port(flow, skb, thoff, iph->protocol, dir) < 0 || -- nf_flow_snat_ip(flow, skb, iph, thoff, dir) < 0)) -- return -1; -- -- if (test_bit(NF_FLOW_DNAT, &flow->flags) && -- (nf_flow_dnat_port(flow, skb, thoff, iph->protocol, dir) < 0 || -- nf_flow_dnat_ip(flow, skb, iph, thoff, dir) < 0)) -- return -1; -- -- return 0; -+ if (test_bit(NF_FLOW_SNAT, &flow->flags)) { -+ nf_flow_snat_port(flow, skb, thoff, iph->protocol, dir); -+ nf_flow_snat_ip(flow, skb, iph, thoff, dir); -+ } -+ if (test_bit(NF_FLOW_DNAT, &flow->flags)) { -+ nf_flow_dnat_port(flow, skb, thoff, iph->protocol, dir); -+ nf_flow_dnat_ip(flow, skb, iph, thoff, dir); -+ } - } - - static bool ip_has_options(unsigned int thoff) -@@ -276,8 +265,7 @@ nf_flow_offload_ip_hook(void *priv, stru - return NF_DROP; - - iph = ip_hdr(skb); -- if (nf_flow_nat_ip(flow, skb, thoff, dir, iph) < 0) -- return NF_DROP; -+ nf_flow_nat_ip(flow, skb, thoff, dir, iph); - - ip_decrease_ttl(iph); - skb->tstamp = 0; -@@ -301,22 +289,21 @@ nf_flow_offload_ip_hook(void *priv, stru - } - EXPORT_SYMBOL_GPL(nf_flow_offload_ip_hook); - --static int nf_flow_nat_ipv6_tcp(struct sk_buff *skb, unsigned int thoff, -- struct in6_addr *addr, -- struct in6_addr *new_addr) -+static void nf_flow_nat_ipv6_tcp(struct sk_buff *skb, unsigned int thoff, -+ struct in6_addr *addr, -+ struct in6_addr *new_addr, -+ struct ipv6hdr *ip6h) - { - struct tcphdr *tcph; - - tcph = (void *)(skb_network_header(skb) + thoff); - inet_proto_csum_replace16(&tcph->check, skb, addr->s6_addr32, - new_addr->s6_addr32, true); -- -- return 0; - } - --static int nf_flow_nat_ipv6_udp(struct sk_buff *skb, unsigned int thoff, -- struct in6_addr *addr, -- struct in6_addr *new_addr) -+static void nf_flow_nat_ipv6_udp(struct sk_buff *skb, unsigned int thoff, -+ struct in6_addr *addr, -+ struct in6_addr *new_addr) - { - struct udphdr *udph; - -@@ -327,32 +314,26 @@ static int nf_flow_nat_ipv6_udp(struct s - if (!udph->check) - udph->check = CSUM_MANGLED_0; - } -- -- return 0; - } - --static int nf_flow_nat_ipv6_l4proto(struct sk_buff *skb, struct ipv6hdr *ip6h, -- unsigned int thoff, struct in6_addr *addr, -- struct in6_addr *new_addr) -+static void nf_flow_nat_ipv6_l4proto(struct sk_buff *skb, struct ipv6hdr *ip6h, -+ unsigned int thoff, struct in6_addr *addr, -+ struct in6_addr *new_addr) - { - switch (ip6h->nexthdr) { - case IPPROTO_TCP: -- if (nf_flow_nat_ipv6_tcp(skb, thoff, addr, new_addr) < 0) -- return NF_DROP; -+ nf_flow_nat_ipv6_tcp(skb, thoff, addr, new_addr, ip6h); - break; - case IPPROTO_UDP: -- if (nf_flow_nat_ipv6_udp(skb, thoff, addr, new_addr) < 0) -- return NF_DROP; -+ nf_flow_nat_ipv6_udp(skb, thoff, addr, new_addr); - break; - } -- -- return 0; - } - --static int nf_flow_snat_ipv6(const struct flow_offload *flow, -- struct sk_buff *skb, struct ipv6hdr *ip6h, -- unsigned int thoff, -- enum flow_offload_tuple_dir dir) -+static void nf_flow_snat_ipv6(const struct flow_offload *flow, -+ struct sk_buff *skb, struct ipv6hdr *ip6h, -+ unsigned int thoff, -+ enum flow_offload_tuple_dir dir) - { - struct in6_addr addr, new_addr; - -@@ -369,13 +350,13 @@ static int nf_flow_snat_ipv6(const struc - break; - } - -- return nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr); -+ nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr); - } - --static int nf_flow_dnat_ipv6(const struct flow_offload *flow, -- struct sk_buff *skb, struct ipv6hdr *ip6h, -- unsigned int thoff, -- enum flow_offload_tuple_dir dir) -+static void nf_flow_dnat_ipv6(const struct flow_offload *flow, -+ struct sk_buff *skb, struct ipv6hdr *ip6h, -+ unsigned int thoff, -+ enum flow_offload_tuple_dir dir) - { - struct in6_addr addr, new_addr; - -@@ -392,27 +373,24 @@ static int nf_flow_dnat_ipv6(const struc - break; - } - -- return nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr); -+ nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr); - } - --static int nf_flow_nat_ipv6(const struct flow_offload *flow, -- struct sk_buff *skb, -- enum flow_offload_tuple_dir dir, -- struct ipv6hdr *ip6h) -+static void nf_flow_nat_ipv6(const struct flow_offload *flow, -+ struct sk_buff *skb, -+ enum flow_offload_tuple_dir dir, -+ struct ipv6hdr *ip6h) - { - unsigned int thoff = sizeof(*ip6h); - -- if (test_bit(NF_FLOW_SNAT, &flow->flags) && -- (nf_flow_snat_port(flow, skb, thoff, ip6h->nexthdr, dir) < 0 || -- nf_flow_snat_ipv6(flow, skb, ip6h, thoff, dir) < 0)) -- return -1; -- -- if (test_bit(NF_FLOW_DNAT, &flow->flags) && -- (nf_flow_dnat_port(flow, skb, thoff, ip6h->nexthdr, dir) < 0 || -- nf_flow_dnat_ipv6(flow, skb, ip6h, thoff, dir) < 0)) -- return -1; -- -- return 0; -+ if (test_bit(NF_FLOW_SNAT, &flow->flags)) { -+ nf_flow_snat_port(flow, skb, thoff, ip6h->nexthdr, dir); -+ nf_flow_snat_ipv6(flow, skb, ip6h, thoff, dir); -+ } -+ if (test_bit(NF_FLOW_DNAT, &flow->flags)) { -+ nf_flow_dnat_port(flow, skb, thoff, ip6h->nexthdr, dir); -+ nf_flow_dnat_ipv6(flow, skb, ip6h, thoff, dir); -+ } - } - - static int nf_flow_tuple_ipv6(struct sk_buff *skb, const struct net_device *dev, -@@ -507,8 +485,7 @@ nf_flow_offload_ipv6_hook(void *priv, st - return NF_DROP; - - ip6h = ipv6_hdr(skb); -- if (nf_flow_nat_ipv6(flow, skb, dir, ip6h) < 0) -- return NF_DROP; -+ nf_flow_nat_ipv6(flow, skb, dir, ip6h); - - ip6h->hop_limit--; - skb->tstamp = 0; diff --git a/target/linux/generic/backport-5.10/610-v5.13-08-netfilter-flowtable-call-dst_check-to-fall-back-to-c.patch b/target/linux/generic/backport-5.10/610-v5.13-08-netfilter-flowtable-call-dst_check-to-fall-back-to-c.patch deleted file mode 100644 index 276785030d..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-08-netfilter-flowtable-call-dst_check-to-fall-back-to-c.patch +++ /dev/null @@ -1,46 +0,0 @@ -From: Pablo Neira Ayuso -Date: Tue, 23 Mar 2021 00:56:26 +0100 -Subject: [PATCH] netfilter: flowtable: call dst_check() to fall back to - classic forwarding - -In case the route is stale, pass up the packet to the classic forwarding -path for re-evaluation and schedule this flow entry for removal. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -197,14 +197,6 @@ static bool nf_flow_exceeds_mtu(const st - return true; - } - --static int nf_flow_offload_dst_check(struct dst_entry *dst) --{ -- if (unlikely(dst_xfrm(dst))) -- return dst_check(dst, 0) ? 0 : -1; -- -- return 0; --} -- - static unsigned int nf_flow_xmit_xfrm(struct sk_buff *skb, - const struct nf_hook_state *state, - struct dst_entry *dst) -@@ -256,7 +248,7 @@ nf_flow_offload_ip_hook(void *priv, stru - - flow_offload_refresh(flow_table, flow); - -- if (nf_flow_offload_dst_check(&rt->dst)) { -+ if (!dst_check(&rt->dst, 0)) { - flow_offload_teardown(flow); - return NF_ACCEPT; - } -@@ -476,7 +468,7 @@ nf_flow_offload_ipv6_hook(void *priv, st - - flow_offload_refresh(flow_table, flow); - -- if (nf_flow_offload_dst_check(&rt->dst)) { -+ if (!dst_check(&rt->dst, 0)) { - flow_offload_teardown(flow); - return NF_ACCEPT; - } diff --git a/target/linux/generic/backport-5.10/610-v5.13-09-netfilter-flowtable-refresh-timeout-after-dst-and-wr.patch b/target/linux/generic/backport-5.10/610-v5.13-09-netfilter-flowtable-refresh-timeout-after-dst-and-wr.patch deleted file mode 100644 index 14ac2ee295..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-09-netfilter-flowtable-refresh-timeout-after-dst-and-wr.patch +++ /dev/null @@ -1,49 +0,0 @@ -From: Pablo Neira Ayuso -Date: Tue, 23 Mar 2021 00:56:27 +0100 -Subject: [PATCH] netfilter: flowtable: refresh timeout after dst and - writable checks - -Refresh the timeout (and retry hardware offload) once the skbuff dst -is confirmed to be current and after the skbuff is made writable. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -246,8 +246,6 @@ nf_flow_offload_ip_hook(void *priv, stru - if (nf_flow_state_check(flow, iph->protocol, skb, thoff)) - return NF_ACCEPT; - -- flow_offload_refresh(flow_table, flow); -- - if (!dst_check(&rt->dst, 0)) { - flow_offload_teardown(flow); - return NF_ACCEPT; -@@ -256,6 +254,8 @@ nf_flow_offload_ip_hook(void *priv, stru - if (skb_try_make_writable(skb, thoff + hdrsize)) - return NF_DROP; - -+ flow_offload_refresh(flow_table, flow); -+ - iph = ip_hdr(skb); - nf_flow_nat_ip(flow, skb, thoff, dir, iph); - -@@ -466,8 +466,6 @@ nf_flow_offload_ipv6_hook(void *priv, st - sizeof(*ip6h))) - return NF_ACCEPT; - -- flow_offload_refresh(flow_table, flow); -- - if (!dst_check(&rt->dst, 0)) { - flow_offload_teardown(flow); - return NF_ACCEPT; -@@ -476,6 +474,8 @@ nf_flow_offload_ipv6_hook(void *priv, st - if (skb_try_make_writable(skb, sizeof(*ip6h) + hdrsize)) - return NF_DROP; - -+ flow_offload_refresh(flow_table, flow); -+ - ip6h = ipv6_hdr(skb); - nf_flow_nat_ipv6(flow, skb, dir, ip6h); - diff --git a/target/linux/generic/backport-5.10/610-v5.13-10-netfilter-nftables-update-table-flags-from-the-commi.patch b/target/linux/generic/backport-5.10/610-v5.13-10-netfilter-nftables-update-table-flags-from-the-commi.patch deleted file mode 100644 index 964a94a58a..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-10-netfilter-nftables-update-table-flags-from-the-commi.patch +++ /dev/null @@ -1,103 +0,0 @@ -From: Pablo Neira Ayuso -Date: Tue, 23 Mar 2021 00:56:28 +0100 -Subject: [PATCH] netfilter: nftables: update table flags from the commit - phase - -Do not update table flags from the preparation phase. Store the flags -update into the transaction, then update the flags from the commit -phase. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_tables.h -+++ b/include/net/netfilter/nf_tables.h -@@ -1474,13 +1474,16 @@ struct nft_trans_chain { - - struct nft_trans_table { - bool update; -- bool enable; -+ u8 state; -+ u32 flags; - }; - - #define nft_trans_table_update(trans) \ - (((struct nft_trans_table *)trans->data)->update) --#define nft_trans_table_enable(trans) \ -- (((struct nft_trans_table *)trans->data)->enable) -+#define nft_trans_table_state(trans) \ -+ (((struct nft_trans_table *)trans->data)->state) -+#define nft_trans_table_flags(trans) \ -+ (((struct nft_trans_table *)trans->data)->flags) - - struct nft_trans_elem { - struct nft_set *set; ---- a/net/netfilter/nf_tables_api.c -+++ b/net/netfilter/nf_tables_api.c -@@ -917,6 +917,12 @@ static void nf_tables_table_disable(stru - nft_table_disable(net, table, 0); - } - -+enum { -+ NFT_TABLE_STATE_UNCHANGED = 0, -+ NFT_TABLE_STATE_DORMANT, -+ NFT_TABLE_STATE_WAKEUP -+}; -+ - static int nf_tables_updtable(struct nft_ctx *ctx) - { - struct nft_trans *trans; -@@ -940,19 +946,17 @@ static int nf_tables_updtable(struct nft - - if ((flags & NFT_TABLE_F_DORMANT) && - !(ctx->table->flags & NFT_TABLE_F_DORMANT)) { -- nft_trans_table_enable(trans) = false; -+ nft_trans_table_state(trans) = NFT_TABLE_STATE_DORMANT; - } else if (!(flags & NFT_TABLE_F_DORMANT) && - ctx->table->flags & NFT_TABLE_F_DORMANT) { -- ctx->table->flags &= ~NFT_TABLE_F_DORMANT; - ret = nf_tables_table_enable(ctx->net, ctx->table); - if (ret >= 0) -- nft_trans_table_enable(trans) = true; -- else -- ctx->table->flags |= NFT_TABLE_F_DORMANT; -+ nft_trans_table_state(trans) = NFT_TABLE_STATE_WAKEUP; - } - if (ret < 0) - goto err; - -+ nft_trans_table_flags(trans) = flags; - nft_trans_table_update(trans) = true; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); - return 0; -@@ -7918,11 +7922,10 @@ static int nf_tables_commit(struct net * - switch (trans->msg_type) { - case NFT_MSG_NEWTABLE: - if (nft_trans_table_update(trans)) { -- if (!nft_trans_table_enable(trans)) { -- nf_tables_table_disable(net, -- trans->ctx.table); -- trans->ctx.table->flags |= NFT_TABLE_F_DORMANT; -- } -+ if (nft_trans_table_state(trans) == NFT_TABLE_STATE_DORMANT) -+ nf_tables_table_disable(net, trans->ctx.table); -+ -+ trans->ctx.table->flags = nft_trans_table_flags(trans); - } else { - nft_clear(net, trans->ctx.table); - } -@@ -8139,11 +8142,9 @@ static int __nf_tables_abort(struct net - switch (trans->msg_type) { - case NFT_MSG_NEWTABLE: - if (nft_trans_table_update(trans)) { -- if (nft_trans_table_enable(trans)) { -- nf_tables_table_disable(net, -- trans->ctx.table); -- trans->ctx.table->flags |= NFT_TABLE_F_DORMANT; -- } -+ if (nft_trans_table_state(trans) == NFT_TABLE_STATE_WAKEUP) -+ nf_tables_table_disable(net, trans->ctx.table); -+ - nft_trans_destroy(trans); - } else { - list_del_rcu(&trans->ctx.table->list); diff --git a/target/linux/generic/backport-5.10/610-v5.13-11-net-resolve-forwarding-path-from-virtual-netdevice-a.patch b/target/linux/generic/backport-5.10/610-v5.13-11-net-resolve-forwarding-path-from-virtual-netdevice-a.patch deleted file mode 100644 index b3c0c2e927..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-11-net-resolve-forwarding-path-from-virtual-netdevice-a.patch +++ /dev/null @@ -1,170 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:32 +0100 -Subject: [PATCH] net: resolve forwarding path from virtual netdevice and - HW destination address - -This patch adds dev_fill_forward_path() which resolves the path to reach -the real netdevice from the IP forwarding side. This function takes as -input the netdevice and the destination hardware address and it walks -down the devices calling .ndo_fill_forward_path() for each device until -the real device is found. - -For instance, assuming the following topology: - - IP forwarding - / \ - br0 eth0 - / \ - eth1 eth2 - . - . - . - ethX - ab:cd:ef:ab:cd:ef - -where eth1 and eth2 are bridge ports and eth0 provides WAN connectivity. -ethX is the interface in another box which is connected to the eth1 -bridge port. - -For packets going through IP forwarding to br0 whose destination MAC -address is ab:cd:ef:ab:cd:ef, dev_fill_forward_path() provides the -following path: - - br0 -> eth1 - -.ndo_fill_forward_path for br0 looks up at the FDB for the bridge port -from the destination MAC address to get the bridge port eth1. - -This information allows to create a fast path that bypasses the classic -bridge and IP forwarding paths, so packets go directly from the bridge -port eth1 to eth0 (wan interface) and vice versa. - - fast path - .------------------------. - / \ - | IP forwarding | - | / \ \/ - | br0 eth0 - . / \ - -> eth1 eth2 - . - . - . - ethX - ab:cd:ef:ab:cd:ef - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -850,6 +850,27 @@ typedef u16 (*select_queue_fallback_t)(s - struct sk_buff *skb, - struct net_device *sb_dev); - -+enum net_device_path_type { -+ DEV_PATH_ETHERNET = 0, -+}; -+ -+struct net_device_path { -+ enum net_device_path_type type; -+ const struct net_device *dev; -+}; -+ -+#define NET_DEVICE_PATH_STACK_MAX 5 -+ -+struct net_device_path_stack { -+ int num_paths; -+ struct net_device_path path[NET_DEVICE_PATH_STACK_MAX]; -+}; -+ -+struct net_device_path_ctx { -+ const struct net_device *dev; -+ const u8 *daddr; -+}; -+ - enum tc_setup_type { - TC_SETUP_QDISC_MQPRIO, - TC_SETUP_CLSU32, -@@ -1296,6 +1317,8 @@ struct netdev_net_notifier { - * struct net_device *(*ndo_get_peer_dev)(struct net_device *dev); - * If a device is paired with a peer device, return the peer instance. - * The caller must be under RCU read context. -+ * int (*ndo_fill_forward_path)(struct net_device_path_ctx *ctx, struct net_device_path *path); -+ * Get the forwarding path to reach the real device from the HW destination address - */ - struct net_device_ops { - int (*ndo_init)(struct net_device *dev); -@@ -1504,6 +1527,8 @@ struct net_device_ops { - int (*ndo_tunnel_ctl)(struct net_device *dev, - struct ip_tunnel_parm *p, int cmd); - struct net_device * (*ndo_get_peer_dev)(struct net_device *dev); -+ int (*ndo_fill_forward_path)(struct net_device_path_ctx *ctx, -+ struct net_device_path *path); - }; - - /** -@@ -2851,6 +2876,8 @@ void dev_remove_offload(struct packet_of - - int dev_get_iflink(const struct net_device *dev); - int dev_fill_metadata_dst(struct net_device *dev, struct sk_buff *skb); -+int dev_fill_forward_path(const struct net_device *dev, const u8 *daddr, -+ struct net_device_path_stack *stack); - struct net_device *__dev_get_by_flags(struct net *net, unsigned short flags, - unsigned short mask); - struct net_device *dev_get_by_name(struct net *net, const char *name); ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -847,6 +847,52 @@ int dev_fill_metadata_dst(struct net_dev - } - EXPORT_SYMBOL_GPL(dev_fill_metadata_dst); - -+static struct net_device_path *dev_fwd_path(struct net_device_path_stack *stack) -+{ -+ int k = stack->num_paths++; -+ -+ if (WARN_ON_ONCE(k >= NET_DEVICE_PATH_STACK_MAX)) -+ return NULL; -+ -+ return &stack->path[k]; -+} -+ -+int dev_fill_forward_path(const struct net_device *dev, const u8 *daddr, -+ struct net_device_path_stack *stack) -+{ -+ const struct net_device *last_dev; -+ struct net_device_path_ctx ctx = { -+ .dev = dev, -+ .daddr = daddr, -+ }; -+ struct net_device_path *path; -+ int ret = 0; -+ -+ stack->num_paths = 0; -+ while (ctx.dev && ctx.dev->netdev_ops->ndo_fill_forward_path) { -+ last_dev = ctx.dev; -+ path = dev_fwd_path(stack); -+ if (!path) -+ return -1; -+ -+ memset(path, 0, sizeof(struct net_device_path)); -+ ret = ctx.dev->netdev_ops->ndo_fill_forward_path(&ctx, path); -+ if (ret < 0) -+ return -1; -+ -+ if (WARN_ON_ONCE(last_dev == ctx.dev)) -+ return -1; -+ } -+ path = dev_fwd_path(stack); -+ if (!path) -+ return -1; -+ path->type = DEV_PATH_ETHERNET; -+ path->dev = ctx.dev; -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(dev_fill_forward_path); -+ - /** - * __dev_get_by_name - find a device by its name - * @net: the applicable net namespace diff --git a/target/linux/generic/backport-5.10/610-v5.13-12-net-8021q-resolve-forwarding-path-for-vlan-devices.patch b/target/linux/generic/backport-5.10/610-v5.13-12-net-8021q-resolve-forwarding-path-for-vlan-devices.patch deleted file mode 100644 index a906dc06ce..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-12-net-8021q-resolve-forwarding-path-for-vlan-devices.patch +++ /dev/null @@ -1,80 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:33 +0100 -Subject: [PATCH] net: 8021q: resolve forwarding path for vlan devices - -Add .ndo_fill_forward_path for vlan devices. - -For instance, assuming the following topology: - - IP forwarding - / \ - eth0.100 eth0 - | - eth0 - . - . - . - ethX - ab:cd:ef:ab:cd:ef - -For packets going through IP forwarding to eth0.100 whose destination -MAC address is ab:cd:ef:ab:cd:ef, dev_fill_forward_path() provides the -following path: - - eth0.100 -> eth0 - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -852,11 +852,18 @@ typedef u16 (*select_queue_fallback_t)(s - - enum net_device_path_type { - DEV_PATH_ETHERNET = 0, -+ DEV_PATH_VLAN, - }; - - struct net_device_path { - enum net_device_path_type type; - const struct net_device *dev; -+ union { -+ struct { -+ u16 id; -+ __be16 proto; -+ } encap; -+ }; - }; - - #define NET_DEVICE_PATH_STACK_MAX 5 ---- a/net/8021q/vlan_dev.c -+++ b/net/8021q/vlan_dev.c -@@ -770,6 +770,20 @@ static int vlan_dev_get_iflink(const str - return real_dev->ifindex; - } - -+static int vlan_dev_fill_forward_path(struct net_device_path_ctx *ctx, -+ struct net_device_path *path) -+{ -+ struct vlan_dev_priv *vlan = vlan_dev_priv(ctx->dev); -+ -+ path->type = DEV_PATH_VLAN; -+ path->encap.id = vlan->vlan_id; -+ path->encap.proto = vlan->vlan_proto; -+ path->dev = ctx->dev; -+ ctx->dev = vlan->real_dev; -+ -+ return 0; -+} -+ - static const struct ethtool_ops vlan_ethtool_ops = { - .get_link_ksettings = vlan_ethtool_get_link_ksettings, - .get_drvinfo = vlan_ethtool_get_drvinfo, -@@ -808,6 +822,7 @@ static const struct net_device_ops vlan_ - #endif - .ndo_fix_features = vlan_dev_fix_features, - .ndo_get_iflink = vlan_dev_get_iflink, -+ .ndo_fill_forward_path = vlan_dev_fill_forward_path, - }; - - static void vlan_dev_free(struct net_device *dev) diff --git a/target/linux/generic/backport-5.10/610-v5.13-13-net-bridge-resolve-forwarding-path-for-bridge-device.patch b/target/linux/generic/backport-5.10/610-v5.13-13-net-bridge-resolve-forwarding-path-for-bridge-device.patch deleted file mode 100644 index f5a6dd6ebc..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-13-net-bridge-resolve-forwarding-path-for-bridge-device.patch +++ /dev/null @@ -1,62 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:34 +0100 -Subject: [PATCH] net: bridge: resolve forwarding path for bridge devices - -Add .ndo_fill_forward_path for bridge devices. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -853,6 +853,7 @@ typedef u16 (*select_queue_fallback_t)(s - enum net_device_path_type { - DEV_PATH_ETHERNET = 0, - DEV_PATH_VLAN, -+ DEV_PATH_BRIDGE, - }; - - struct net_device_path { ---- a/net/bridge/br_device.c -+++ b/net/bridge/br_device.c -@@ -398,6 +398,32 @@ static int br_del_slave(struct net_devic - return br_del_if(br, slave_dev); - } - -+static int br_fill_forward_path(struct net_device_path_ctx *ctx, -+ struct net_device_path *path) -+{ -+ struct net_bridge_fdb_entry *f; -+ struct net_bridge_port *dst; -+ struct net_bridge *br; -+ -+ if (netif_is_bridge_port(ctx->dev)) -+ return -1; -+ -+ br = netdev_priv(ctx->dev); -+ f = br_fdb_find_rcu(br, ctx->daddr, 0); -+ if (!f || !f->dst) -+ return -1; -+ -+ dst = READ_ONCE(f->dst); -+ if (!dst) -+ return -1; -+ -+ path->type = DEV_PATH_BRIDGE; -+ path->dev = dst->br->dev; -+ ctx->dev = dst->dev; -+ -+ return 0; -+} -+ - static const struct ethtool_ops br_ethtool_ops = { - .get_drvinfo = br_getinfo, - .get_link = ethtool_op_get_link, -@@ -432,6 +458,7 @@ static const struct net_device_ops br_ne - .ndo_bridge_setlink = br_setlink, - .ndo_bridge_dellink = br_dellink, - .ndo_features_check = passthru_features_check, -+ .ndo_fill_forward_path = br_fill_forward_path, - }; - - static struct device_type br_type = { diff --git a/target/linux/generic/backport-5.10/610-v5.13-14-net-bridge-resolve-forwarding-path-for-VLAN-tag-acti.patch b/target/linux/generic/backport-5.10/610-v5.13-14-net-bridge-resolve-forwarding-path-for-VLAN-tag-acti.patch deleted file mode 100644 index 9e62546a6c..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-14-net-bridge-resolve-forwarding-path-for-VLAN-tag-acti.patch +++ /dev/null @@ -1,207 +0,0 @@ -From: Felix Fietkau -Date: Wed, 24 Mar 2021 02:30:35 +0100 -Subject: [PATCH] net: bridge: resolve forwarding path for VLAN tag - actions in bridge devices - -Depending on the VLAN settings of the bridge and the port, the bridge can -either add or remove a tag. When vlan filtering is enabled, the fdb lookup -also needs to know the VLAN tag/proto for the destination address -To provide this, keep track of the stack of VLAN tags for the path in the -lookup context - -Signed-off-by: Felix Fietkau -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -864,10 +864,20 @@ struct net_device_path { - u16 id; - __be16 proto; - } encap; -+ struct { -+ enum { -+ DEV_PATH_BR_VLAN_KEEP, -+ DEV_PATH_BR_VLAN_TAG, -+ DEV_PATH_BR_VLAN_UNTAG, -+ } vlan_mode; -+ u16 vlan_id; -+ __be16 vlan_proto; -+ } bridge; - }; - }; - - #define NET_DEVICE_PATH_STACK_MAX 5 -+#define NET_DEVICE_PATH_VLAN_MAX 2 - - struct net_device_path_stack { - int num_paths; -@@ -877,6 +887,12 @@ struct net_device_path_stack { - struct net_device_path_ctx { - const struct net_device *dev; - const u8 *daddr; -+ -+ int num_vlans; -+ struct { -+ u16 id; -+ __be16 proto; -+ } vlan[NET_DEVICE_PATH_VLAN_MAX]; - }; - - enum tc_setup_type { ---- a/net/8021q/vlan_dev.c -+++ b/net/8021q/vlan_dev.c -@@ -780,6 +780,12 @@ static int vlan_dev_fill_forward_path(st - path->encap.proto = vlan->vlan_proto; - path->dev = ctx->dev; - ctx->dev = vlan->real_dev; -+ if (ctx->num_vlans >= ARRAY_SIZE(ctx->vlan)) -+ return -ENOSPC; -+ -+ ctx->vlan[ctx->num_vlans].id = vlan->vlan_id; -+ ctx->vlan[ctx->num_vlans].proto = vlan->vlan_proto; -+ ctx->num_vlans++; - - return 0; - } ---- a/net/bridge/br_device.c -+++ b/net/bridge/br_device.c -@@ -409,7 +409,10 @@ static int br_fill_forward_path(struct n - return -1; - - br = netdev_priv(ctx->dev); -- f = br_fdb_find_rcu(br, ctx->daddr, 0); -+ -+ br_vlan_fill_forward_path_pvid(br, ctx, path); -+ -+ f = br_fdb_find_rcu(br, ctx->daddr, path->bridge.vlan_id); - if (!f || !f->dst) - return -1; - -@@ -417,10 +420,28 @@ static int br_fill_forward_path(struct n - if (!dst) - return -1; - -+ if (br_vlan_fill_forward_path_mode(br, dst, path)) -+ return -1; -+ - path->type = DEV_PATH_BRIDGE; - path->dev = dst->br->dev; - ctx->dev = dst->dev; - -+ switch (path->bridge.vlan_mode) { -+ case DEV_PATH_BR_VLAN_TAG: -+ if (ctx->num_vlans >= ARRAY_SIZE(ctx->vlan)) -+ return -ENOSPC; -+ ctx->vlan[ctx->num_vlans].id = path->bridge.vlan_id; -+ ctx->vlan[ctx->num_vlans].proto = path->bridge.vlan_proto; -+ ctx->num_vlans++; -+ break; -+ case DEV_PATH_BR_VLAN_UNTAG: -+ ctx->num_vlans--; -+ break; -+ case DEV_PATH_BR_VLAN_KEEP: -+ break; -+ } -+ - return 0; - } - ---- a/net/bridge/br_private.h -+++ b/net/bridge/br_private.h -@@ -1093,6 +1093,13 @@ void br_vlan_notify(const struct net_bri - bool br_vlan_can_enter_range(const struct net_bridge_vlan *v_curr, - const struct net_bridge_vlan *range_end); - -+void br_vlan_fill_forward_path_pvid(struct net_bridge *br, -+ struct net_device_path_ctx *ctx, -+ struct net_device_path *path); -+int br_vlan_fill_forward_path_mode(struct net_bridge *br, -+ struct net_bridge_port *dst, -+ struct net_device_path *path); -+ - static inline struct net_bridge_vlan_group *br_vlan_group( - const struct net_bridge *br) - { -@@ -1250,6 +1257,19 @@ static inline int nbp_get_num_vlan_infos - { - return 0; - } -+ -+static inline void br_vlan_fill_forward_path_pvid(struct net_bridge *br, -+ struct net_device_path_ctx *ctx, -+ struct net_device_path *path) -+{ -+} -+ -+static inline int br_vlan_fill_forward_path_mode(struct net_bridge *br, -+ struct net_bridge_port *dst, -+ struct net_device_path *path) -+{ -+ return 0; -+} - - static inline struct net_bridge_vlan_group *br_vlan_group( - const struct net_bridge *br) ---- a/net/bridge/br_vlan.c -+++ b/net/bridge/br_vlan.c -@@ -1350,6 +1350,59 @@ int br_vlan_get_pvid_rcu(const struct ne - } - EXPORT_SYMBOL_GPL(br_vlan_get_pvid_rcu); - -+void br_vlan_fill_forward_path_pvid(struct net_bridge *br, -+ struct net_device_path_ctx *ctx, -+ struct net_device_path *path) -+{ -+ struct net_bridge_vlan_group *vg; -+ int idx = ctx->num_vlans - 1; -+ u16 vid; -+ -+ path->bridge.vlan_mode = DEV_PATH_BR_VLAN_KEEP; -+ -+ if (!br_opt_get(br, BROPT_VLAN_ENABLED)) -+ return; -+ -+ vg = br_vlan_group(br); -+ -+ if (idx >= 0 && -+ ctx->vlan[idx].proto == br->vlan_proto) { -+ vid = ctx->vlan[idx].id; -+ } else { -+ path->bridge.vlan_mode = DEV_PATH_BR_VLAN_TAG; -+ vid = br_get_pvid(vg); -+ } -+ -+ path->bridge.vlan_id = vid; -+ path->bridge.vlan_proto = br->vlan_proto; -+} -+ -+int br_vlan_fill_forward_path_mode(struct net_bridge *br, -+ struct net_bridge_port *dst, -+ struct net_device_path *path) -+{ -+ struct net_bridge_vlan_group *vg; -+ struct net_bridge_vlan *v; -+ -+ if (!br_opt_get(br, BROPT_VLAN_ENABLED)) -+ return 0; -+ -+ vg = nbp_vlan_group_rcu(dst); -+ v = br_vlan_find(vg, path->bridge.vlan_id); -+ if (!v || !br_vlan_should_use(v)) -+ return -EINVAL; -+ -+ if (!(v->flags & BRIDGE_VLAN_INFO_UNTAGGED)) -+ return 0; -+ -+ if (path->bridge.vlan_mode == DEV_PATH_BR_VLAN_TAG) -+ path->bridge.vlan_mode = DEV_PATH_BR_VLAN_KEEP; -+ else -+ path->bridge.vlan_mode = DEV_PATH_BR_VLAN_UNTAG; -+ -+ return 0; -+} -+ - int br_vlan_get_info(const struct net_device *dev, u16 vid, - struct bridge_vlan_info *p_vinfo) - { diff --git a/target/linux/generic/backport-5.10/610-v5.13-15-net-ppp-resolve-forwarding-path-for-bridge-pppoe-dev.patch b/target/linux/generic/backport-5.10/610-v5.13-15-net-ppp-resolve-forwarding-path-for-bridge-pppoe-dev.patch deleted file mode 100644 index c714ff0584..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-15-net-ppp-resolve-forwarding-path-for-bridge-pppoe-dev.patch +++ /dev/null @@ -1,113 +0,0 @@ -From: Felix Fietkau -Date: Wed, 24 Mar 2021 02:30:36 +0100 -Subject: [PATCH] net: ppp: resolve forwarding path for bridge pppoe - devices - -Pass on the PPPoE session ID, destination hardware address and the real -device. - -Signed-off-by: Felix Fietkau -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/drivers/net/ppp/ppp_generic.c -+++ b/drivers/net/ppp/ppp_generic.c -@@ -1466,12 +1466,34 @@ static void ppp_dev_priv_destructor(stru - ppp_destroy_interface(ppp); - } - -+static int ppp_fill_forward_path(struct net_device_path_ctx *ctx, -+ struct net_device_path *path) -+{ -+ struct ppp *ppp = netdev_priv(ctx->dev); -+ struct ppp_channel *chan; -+ struct channel *pch; -+ -+ if (ppp->flags & SC_MULTILINK) -+ return -EOPNOTSUPP; -+ -+ if (list_empty(&ppp->channels)) -+ return -ENODEV; -+ -+ pch = list_first_entry(&ppp->channels, struct channel, clist); -+ chan = pch->chan; -+ if (!chan->ops->fill_forward_path) -+ return -EOPNOTSUPP; -+ -+ return chan->ops->fill_forward_path(ctx, path, chan); -+} -+ - static const struct net_device_ops ppp_netdev_ops = { - .ndo_init = ppp_dev_init, - .ndo_uninit = ppp_dev_uninit, - .ndo_start_xmit = ppp_start_xmit, - .ndo_do_ioctl = ppp_net_ioctl, - .ndo_get_stats64 = ppp_get_stats64, -+ .ndo_fill_forward_path = ppp_fill_forward_path, - }; - - static struct device_type ppp_type = { ---- a/drivers/net/ppp/pppoe.c -+++ b/drivers/net/ppp/pppoe.c -@@ -972,8 +972,31 @@ static int pppoe_xmit(struct ppp_channel - return __pppoe_xmit(sk, skb); - } - -+static int pppoe_fill_forward_path(struct net_device_path_ctx *ctx, -+ struct net_device_path *path, -+ const struct ppp_channel *chan) -+{ -+ struct sock *sk = (struct sock *)chan->private; -+ struct pppox_sock *po = pppox_sk(sk); -+ struct net_device *dev = po->pppoe_dev; -+ -+ if (sock_flag(sk, SOCK_DEAD) || -+ !(sk->sk_state & PPPOX_CONNECTED) || !dev) -+ return -1; -+ -+ path->type = DEV_PATH_PPPOE; -+ path->encap.proto = htons(ETH_P_PPP_SES); -+ path->encap.id = be16_to_cpu(po->num); -+ memcpy(path->encap.h_dest, po->pppoe_pa.remote, ETH_ALEN); -+ path->dev = ctx->dev; -+ ctx->dev = dev; -+ -+ return 0; -+} -+ - static const struct ppp_channel_ops pppoe_chan_ops = { - .start_xmit = pppoe_xmit, -+ .fill_forward_path = pppoe_fill_forward_path, - }; - - static int pppoe_recvmsg(struct socket *sock, struct msghdr *m, ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -854,6 +854,7 @@ enum net_device_path_type { - DEV_PATH_ETHERNET = 0, - DEV_PATH_VLAN, - DEV_PATH_BRIDGE, -+ DEV_PATH_PPPOE, - }; - - struct net_device_path { -@@ -863,6 +864,7 @@ struct net_device_path { - struct { - u16 id; - __be16 proto; -+ u8 h_dest[ETH_ALEN]; - } encap; - struct { - enum { ---- a/include/linux/ppp_channel.h -+++ b/include/linux/ppp_channel.h -@@ -28,6 +28,9 @@ struct ppp_channel_ops { - int (*start_xmit)(struct ppp_channel *, struct sk_buff *); - /* Handle an ioctl call that has come in via /dev/ppp. */ - int (*ioctl)(struct ppp_channel *, unsigned int, unsigned long); -+ int (*fill_forward_path)(struct net_device_path_ctx *, -+ struct net_device_path *, -+ const struct ppp_channel *); - }; - - struct ppp_channel { diff --git a/target/linux/generic/backport-5.10/610-v5.13-16-net-dsa-resolve-forwarding-path-for-dsa-slave-ports.patch b/target/linux/generic/backport-5.10/610-v5.13-16-net-dsa-resolve-forwarding-path-for-dsa-slave-ports.patch deleted file mode 100644 index a277f0ccf0..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-16-net-dsa-resolve-forwarding-path-for-dsa-slave-ports.patch +++ /dev/null @@ -1,63 +0,0 @@ -From: Felix Fietkau -Date: Wed, 24 Mar 2021 02:30:37 +0100 -Subject: [PATCH] net: dsa: resolve forwarding path for dsa slave ports - -Add .ndo_fill_forward_path for dsa slave port devices - -Signed-off-by: Felix Fietkau -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -855,6 +855,7 @@ enum net_device_path_type { - DEV_PATH_VLAN, - DEV_PATH_BRIDGE, - DEV_PATH_PPPOE, -+ DEV_PATH_DSA, - }; - - struct net_device_path { -@@ -875,6 +876,10 @@ struct net_device_path { - u16 vlan_id; - __be16 vlan_proto; - } bridge; -+ struct { -+ int port; -+ u16 proto; -+ } dsa; - }; - }; - ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -1619,6 +1619,21 @@ static struct devlink_port *dsa_slave_ge - return dp->ds->devlink ? &dp->devlink_port : NULL; - } - -+static int dsa_slave_fill_forward_path(struct net_device_path_ctx *ctx, -+ struct net_device_path *path) -+{ -+ struct dsa_port *dp = dsa_slave_to_port(ctx->dev); -+ struct dsa_port *cpu_dp = dp->cpu_dp; -+ -+ path->dev = ctx->dev; -+ path->type = DEV_PATH_DSA; -+ path->dsa.proto = cpu_dp->tag_ops->proto; -+ path->dsa.port = dp->index; -+ ctx->dev = cpu_dp->master; -+ -+ return 0; -+} -+ - static const struct net_device_ops dsa_slave_netdev_ops = { - .ndo_open = dsa_slave_open, - .ndo_stop = dsa_slave_close, -@@ -1644,6 +1659,7 @@ static const struct net_device_ops dsa_s - .ndo_vlan_rx_kill_vid = dsa_slave_vlan_rx_kill_vid, - .ndo_get_devlink_port = dsa_slave_get_devlink_port, - .ndo_change_mtu = dsa_slave_change_mtu, -+ .ndo_fill_forward_path = dsa_slave_fill_forward_path, - }; - - static struct device_type dsa_type = { diff --git a/target/linux/generic/backport-5.10/610-v5.13-17-netfilter-flowtable-add-xmit-path-types.patch b/target/linux/generic/backport-5.10/610-v5.13-17-netfilter-flowtable-add-xmit-path-types.patch deleted file mode 100644 index 6052f67faa..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-17-netfilter-flowtable-add-xmit-path-types.patch +++ /dev/null @@ -1,147 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:38 +0100 -Subject: [PATCH] netfilter: flowtable: add xmit path types - -Add the xmit_type field that defines the two supported xmit paths in the -flowtable data plane, which are the neighbour and the xfrm xmit paths. -This patch prepares for new flowtable xmit path types to come. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -89,6 +89,11 @@ enum flow_offload_tuple_dir { - }; - #define FLOW_OFFLOAD_DIR_MAX IP_CT_DIR_MAX - -+enum flow_offload_xmit_type { -+ FLOW_OFFLOAD_XMIT_NEIGH = 0, -+ FLOW_OFFLOAD_XMIT_XFRM, -+}; -+ - struct flow_offload_tuple { - union { - struct in_addr src_v4; -@@ -111,7 +116,8 @@ struct flow_offload_tuple { - /* All members above are keys for lookups, see flow_offload_hash(). */ - struct { } __hash; - -- u8 dir; -+ u8 dir:6, -+ xmit_type:2; - - u16 mtu; - -@@ -157,7 +163,8 @@ static inline __s32 nf_flow_timeout_delt - - struct nf_flow_route { - struct { -- struct dst_entry *dst; -+ struct dst_entry *dst; -+ enum flow_offload_xmit_type xmit_type; - } tuple[FLOW_OFFLOAD_DIR_MAX]; - }; - ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -95,6 +95,7 @@ static int flow_offload_fill_route(struc - } - - flow_tuple->iifidx = other_dst->dev->ifindex; -+ flow_tuple->xmit_type = route->tuple[dir].xmit_type; - flow_tuple->dst_cache = dst; - - return 0; ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -235,8 +235,6 @@ nf_flow_offload_ip_hook(void *priv, stru - - dir = tuplehash->tuple.dir; - flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]); -- rt = (struct rtable *)flow->tuplehash[dir].tuple.dst_cache; -- outdev = rt->dst.dev; - - if (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu))) - return NF_ACCEPT; -@@ -265,13 +263,16 @@ nf_flow_offload_ip_hook(void *priv, stru - if (flow_table->flags & NF_FLOWTABLE_COUNTER) - nf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len); - -- if (unlikely(dst_xfrm(&rt->dst))) { -+ rt = (struct rtable *)tuplehash->tuple.dst_cache; -+ -+ if (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) { - memset(skb->cb, 0, sizeof(struct inet_skb_parm)); - IPCB(skb)->iif = skb->dev->ifindex; - IPCB(skb)->flags = IPSKB_FORWARDED; - return nf_flow_xmit_xfrm(skb, state, &rt->dst); - } - -+ outdev = rt->dst.dev; - skb->dev = outdev; - nexthop = rt_nexthop(rt, flow->tuplehash[!dir].tuple.src_v4.s_addr); - skb_dst_set_noref(skb, &rt->dst); -@@ -456,8 +457,6 @@ nf_flow_offload_ipv6_hook(void *priv, st - - dir = tuplehash->tuple.dir; - flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]); -- rt = (struct rt6_info *)flow->tuplehash[dir].tuple.dst_cache; -- outdev = rt->dst.dev; - - if (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu))) - return NF_ACCEPT; -@@ -485,13 +484,16 @@ nf_flow_offload_ipv6_hook(void *priv, st - if (flow_table->flags & NF_FLOWTABLE_COUNTER) - nf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len); - -- if (unlikely(dst_xfrm(&rt->dst))) { -+ rt = (struct rt6_info *)tuplehash->tuple.dst_cache; -+ -+ if (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) { - memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); - IP6CB(skb)->iif = skb->dev->ifindex; - IP6CB(skb)->flags = IP6SKB_FORWARDED; - return nf_flow_xmit_xfrm(skb, state, &rt->dst); - } - -+ outdev = rt->dst.dev; - skb->dev = outdev; - nexthop = rt6_nexthop(rt, &flow->tuplehash[!dir].tuple.src_v6); - skb_dst_set_noref(skb, &rt->dst); ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -19,6 +19,22 @@ struct nft_flow_offload { - struct nft_flowtable *flowtable; - }; - -+static enum flow_offload_xmit_type nft_xmit_type(struct dst_entry *dst) -+{ -+ if (dst_xfrm(dst)) -+ return FLOW_OFFLOAD_XMIT_XFRM; -+ -+ return FLOW_OFFLOAD_XMIT_NEIGH; -+} -+ -+static void nft_default_forward_path(struct nf_flow_route *route, -+ struct dst_entry *dst_cache, -+ enum ip_conntrack_dir dir) -+{ -+ route->tuple[dir].dst = dst_cache; -+ route->tuple[dir].xmit_type = nft_xmit_type(dst_cache); -+} -+ - static int nft_flow_route(const struct nft_pktinfo *pkt, - const struct nf_conn *ct, - struct nf_flow_route *route, -@@ -44,8 +60,8 @@ static int nft_flow_route(const struct n - if (!other_dst) - return -ENOENT; - -- route->tuple[dir].dst = this_dst; -- route->tuple[!dir].dst = other_dst; -+ nft_default_forward_path(route, this_dst, dir); -+ nft_default_forward_path(route, other_dst, !dir); - - return 0; - } diff --git a/target/linux/generic/backport-5.10/610-v5.13-18-netfilter-flowtable-use-dev_fill_forward_path-to-obt.patch b/target/linux/generic/backport-5.10/610-v5.13-18-netfilter-flowtable-use-dev_fill_forward_path-to-obt.patch deleted file mode 100644 index 9541ce8867..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-18-netfilter-flowtable-use-dev_fill_forward_path-to-obt.patch +++ /dev/null @@ -1,191 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:39 +0100 -Subject: [PATCH] netfilter: flowtable: use dev_fill_forward_path() to - obtain ingress device - -Obtain the ingress device in the tuple from the route in the reply -direction. Use dev_fill_forward_path() instead to get the real ingress -device for this flow. - -Fall back to use the ingress device that the IP forwarding route -provides if: - -- dev_fill_forward_path() finds no real ingress device. -- the ingress device that is obtained is not part of the flowtable - devices. -- this route has a xfrm policy. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -164,6 +164,9 @@ static inline __s32 nf_flow_timeout_delt - struct nf_flow_route { - struct { - struct dst_entry *dst; -+ struct { -+ u32 ifindex; -+ } in; - enum flow_offload_xmit_type xmit_type; - } tuple[FLOW_OFFLOAD_DIR_MAX]; - }; ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -79,7 +79,6 @@ static int flow_offload_fill_route(struc - enum flow_offload_tuple_dir dir) - { - struct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple; -- struct dst_entry *other_dst = route->tuple[!dir].dst; - struct dst_entry *dst = route->tuple[dir].dst; - - if (!dst_hold_safe(route->tuple[dir].dst)) -@@ -94,7 +93,7 @@ static int flow_offload_fill_route(struc - break; - } - -- flow_tuple->iifidx = other_dst->dev->ifindex; -+ flow_tuple->iifidx = route->tuple[dir].in.ifindex; - flow_tuple->xmit_type = route->tuple[dir].xmit_type; - flow_tuple->dst_cache = dst; - ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -31,14 +31,104 @@ static void nft_default_forward_path(str - struct dst_entry *dst_cache, - enum ip_conntrack_dir dir) - { -+ route->tuple[!dir].in.ifindex = dst_cache->dev->ifindex; - route->tuple[dir].dst = dst_cache; - route->tuple[dir].xmit_type = nft_xmit_type(dst_cache); - } - -+static int nft_dev_fill_forward_path(const struct nf_flow_route *route, -+ const struct dst_entry *dst_cache, -+ const struct nf_conn *ct, -+ enum ip_conntrack_dir dir, -+ struct net_device_path_stack *stack) -+{ -+ const void *daddr = &ct->tuplehash[!dir].tuple.src.u3; -+ struct net_device *dev = dst_cache->dev; -+ unsigned char ha[ETH_ALEN]; -+ struct neighbour *n; -+ u8 nud_state; -+ -+ n = dst_neigh_lookup(dst_cache, daddr); -+ if (!n) -+ return -1; -+ -+ read_lock_bh(&n->lock); -+ nud_state = n->nud_state; -+ ether_addr_copy(ha, n->ha); -+ read_unlock_bh(&n->lock); -+ neigh_release(n); -+ -+ if (!(nud_state & NUD_VALID)) -+ return -1; -+ -+ return dev_fill_forward_path(dev, ha, stack); -+} -+ -+struct nft_forward_info { -+ const struct net_device *indev; -+}; -+ -+static void nft_dev_path_info(const struct net_device_path_stack *stack, -+ struct nft_forward_info *info) -+{ -+ const struct net_device_path *path; -+ int i; -+ -+ for (i = 0; i < stack->num_paths; i++) { -+ path = &stack->path[i]; -+ switch (path->type) { -+ case DEV_PATH_ETHERNET: -+ info->indev = path->dev; -+ break; -+ case DEV_PATH_VLAN: -+ case DEV_PATH_BRIDGE: -+ default: -+ info->indev = NULL; -+ break; -+ } -+ } -+} -+ -+static bool nft_flowtable_find_dev(const struct net_device *dev, -+ struct nft_flowtable *ft) -+{ -+ struct nft_hook *hook; -+ bool found = false; -+ -+ list_for_each_entry_rcu(hook, &ft->hook_list, list) { -+ if (hook->ops.dev != dev) -+ continue; -+ -+ found = true; -+ break; -+ } -+ -+ return found; -+} -+ -+static void nft_dev_forward_path(struct nf_flow_route *route, -+ const struct nf_conn *ct, -+ enum ip_conntrack_dir dir, -+ struct nft_flowtable *ft) -+{ -+ const struct dst_entry *dst = route->tuple[dir].dst; -+ struct net_device_path_stack stack; -+ struct nft_forward_info info = {}; -+ -+ if (nft_dev_fill_forward_path(route, dst, ct, dir, &stack) >= 0) -+ nft_dev_path_info(&stack, &info); -+ -+ if (!info.indev || !nft_flowtable_find_dev(info.indev, ft)) -+ return; -+ -+ route->tuple[!dir].in.ifindex = info.indev->ifindex; -+} -+ - static int nft_flow_route(const struct nft_pktinfo *pkt, - const struct nf_conn *ct, - struct nf_flow_route *route, -- enum ip_conntrack_dir dir) -+ enum ip_conntrack_dir dir, -+ struct nft_flowtable *ft) - { - struct dst_entry *this_dst = skb_dst(pkt->skb); - struct dst_entry *other_dst = NULL; -@@ -63,6 +153,12 @@ static int nft_flow_route(const struct n - nft_default_forward_path(route, this_dst, dir); - nft_default_forward_path(route, other_dst, !dir); - -+ if (route->tuple[dir].xmit_type == FLOW_OFFLOAD_XMIT_NEIGH && -+ route->tuple[!dir].xmit_type == FLOW_OFFLOAD_XMIT_NEIGH) { -+ nft_dev_forward_path(route, ct, dir, ft); -+ nft_dev_forward_path(route, ct, !dir, ft); -+ } -+ - return 0; - } - -@@ -90,8 +186,8 @@ static void nft_flow_offload_eval(const - struct nft_flow_offload *priv = nft_expr_priv(expr); - struct nf_flowtable *flowtable = &priv->flowtable->data; - struct tcphdr _tcph, *tcph = NULL; -+ struct nf_flow_route route = {}; - enum ip_conntrack_info ctinfo; -- struct nf_flow_route route; - struct flow_offload *flow; - enum ip_conntrack_dir dir; - struct nf_conn *ct; -@@ -128,7 +224,7 @@ static void nft_flow_offload_eval(const - goto out; - - dir = CTINFO2DIR(ctinfo); -- if (nft_flow_route(pkt, ct, &route, dir) < 0) -+ if (nft_flow_route(pkt, ct, &route, dir, priv->flowtable) < 0) - goto err_flow_route; - - flow = flow_offload_alloc(ct); diff --git a/target/linux/generic/backport-5.10/610-v5.13-19-netfilter-flowtable-use-dev_fill_forward_path-to-obt.patch b/target/linux/generic/backport-5.10/610-v5.13-19-netfilter-flowtable-use-dev_fill_forward_path-to-obt.patch deleted file mode 100644 index 457e218d9b..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-19-netfilter-flowtable-use-dev_fill_forward_path-to-obt.patch +++ /dev/null @@ -1,374 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:40 +0100 -Subject: [PATCH] netfilter: flowtable: use dev_fill_forward_path() to - obtain egress device - -The egress device in the tuple is obtained from route. Use -dev_fill_forward_path() instead to provide the real egress device for -this flow whenever this is available. - -The new FLOW_OFFLOAD_XMIT_DIRECT type uses dev_queue_xmit() to transmit -ethernet frames. Cache the source and destination hardware address to -use dev_queue_xmit() to transfer packets. - -The FLOW_OFFLOAD_XMIT_DIRECT replaces FLOW_OFFLOAD_XMIT_NEIGH if -dev_fill_forward_path() finds a direct transmit path. - -In case of topology updates, if peer is moved to different bridge port, -the connection will time out, reconnect will result in a new entry with -the correct path. Snooping fdb updates would allow for cleaning up stale -flowtable entries. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -92,6 +92,7 @@ enum flow_offload_tuple_dir { - enum flow_offload_xmit_type { - FLOW_OFFLOAD_XMIT_NEIGH = 0, - FLOW_OFFLOAD_XMIT_XFRM, -+ FLOW_OFFLOAD_XMIT_DIRECT, - }; - - struct flow_offload_tuple { -@@ -120,8 +121,14 @@ struct flow_offload_tuple { - xmit_type:2; - - u16 mtu; -- -- struct dst_entry *dst_cache; -+ union { -+ struct dst_entry *dst_cache; -+ struct { -+ u32 ifidx; -+ u8 h_source[ETH_ALEN]; -+ u8 h_dest[ETH_ALEN]; -+ } out; -+ }; - }; - - struct flow_offload_tuple_rhash { -@@ -167,6 +174,11 @@ struct nf_flow_route { - struct { - u32 ifindex; - } in; -+ struct { -+ u32 ifindex; -+ u8 h_source[ETH_ALEN]; -+ u8 h_dest[ETH_ALEN]; -+ } out; - enum flow_offload_xmit_type xmit_type; - } tuple[FLOW_OFFLOAD_DIR_MAX]; - }; ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -81,9 +81,6 @@ static int flow_offload_fill_route(struc - struct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple; - struct dst_entry *dst = route->tuple[dir].dst; - -- if (!dst_hold_safe(route->tuple[dir].dst)) -- return -1; -- - switch (flow_tuple->l3proto) { - case NFPROTO_IPV4: - flow_tuple->mtu = ip_dst_mtu_maybe_forward(dst, true); -@@ -94,12 +91,36 @@ static int flow_offload_fill_route(struc - } - - flow_tuple->iifidx = route->tuple[dir].in.ifindex; -+ -+ switch (route->tuple[dir].xmit_type) { -+ case FLOW_OFFLOAD_XMIT_DIRECT: -+ memcpy(flow_tuple->out.h_dest, route->tuple[dir].out.h_dest, -+ ETH_ALEN); -+ memcpy(flow_tuple->out.h_source, route->tuple[dir].out.h_source, -+ ETH_ALEN); -+ flow_tuple->out.ifidx = route->tuple[dir].out.ifindex; -+ break; -+ case FLOW_OFFLOAD_XMIT_XFRM: -+ case FLOW_OFFLOAD_XMIT_NEIGH: -+ if (!dst_hold_safe(route->tuple[dir].dst)) -+ return -1; -+ -+ flow_tuple->dst_cache = dst; -+ break; -+ } - flow_tuple->xmit_type = route->tuple[dir].xmit_type; -- flow_tuple->dst_cache = dst; - - return 0; - } - -+static void nft_flow_dst_release(struct flow_offload *flow, -+ enum flow_offload_tuple_dir dir) -+{ -+ if (flow->tuplehash[dir].tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH || -+ flow->tuplehash[dir].tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM) -+ dst_release(flow->tuplehash[dir].tuple.dst_cache); -+} -+ - int flow_offload_route_init(struct flow_offload *flow, - const struct nf_flow_route *route) - { -@@ -118,7 +139,7 @@ int flow_offload_route_init(struct flow_ - return 0; - - err_route_reply: -- dst_release(route->tuple[FLOW_OFFLOAD_DIR_ORIGINAL].dst); -+ nft_flow_dst_release(flow, FLOW_OFFLOAD_DIR_ORIGINAL); - - return err; - } -@@ -169,8 +190,8 @@ static void flow_offload_fixup_ct(struct - - static void flow_offload_route_release(struct flow_offload *flow) - { -- dst_release(flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.dst_cache); -- dst_release(flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple.dst_cache); -+ nft_flow_dst_release(flow, FLOW_OFFLOAD_DIR_ORIGINAL); -+ nft_flow_dst_release(flow, FLOW_OFFLOAD_DIR_REPLY); - } - - void flow_offload_free(struct flow_offload *flow) ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -207,6 +207,24 @@ static unsigned int nf_flow_xmit_xfrm(st - return NF_STOLEN; - } - -+static unsigned int nf_flow_queue_xmit(struct net *net, struct sk_buff *skb, -+ const struct flow_offload_tuple_rhash *tuplehash, -+ unsigned short type) -+{ -+ struct net_device *outdev; -+ -+ outdev = dev_get_by_index_rcu(net, tuplehash->tuple.out.ifidx); -+ if (!outdev) -+ return NF_DROP; -+ -+ skb->dev = outdev; -+ dev_hard_header(skb, skb->dev, type, tuplehash->tuple.out.h_dest, -+ tuplehash->tuple.out.h_source, skb->len); -+ dev_queue_xmit(skb); -+ -+ return NF_STOLEN; -+} -+ - unsigned int - nf_flow_offload_ip_hook(void *priv, struct sk_buff *skb, - const struct nf_hook_state *state) -@@ -222,6 +240,7 @@ nf_flow_offload_ip_hook(void *priv, stru - struct iphdr *iph; - __be32 nexthop; - u32 hdrsize; -+ int ret; - - if (skb->protocol != htons(ETH_P_IP)) - return NF_ACCEPT; -@@ -244,9 +263,13 @@ nf_flow_offload_ip_hook(void *priv, stru - if (nf_flow_state_check(flow, iph->protocol, skb, thoff)) - return NF_ACCEPT; - -- if (!dst_check(&rt->dst, 0)) { -- flow_offload_teardown(flow); -- return NF_ACCEPT; -+ if (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH || -+ tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM) { -+ rt = (struct rtable *)tuplehash->tuple.dst_cache; -+ if (!dst_check(&rt->dst, 0)) { -+ flow_offload_teardown(flow); -+ return NF_ACCEPT; -+ } - } - - if (skb_try_make_writable(skb, thoff + hdrsize)) -@@ -263,8 +286,6 @@ nf_flow_offload_ip_hook(void *priv, stru - if (flow_table->flags & NF_FLOWTABLE_COUNTER) - nf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len); - -- rt = (struct rtable *)tuplehash->tuple.dst_cache; -- - if (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) { - memset(skb->cb, 0, sizeof(struct inet_skb_parm)); - IPCB(skb)->iif = skb->dev->ifindex; -@@ -272,13 +293,23 @@ nf_flow_offload_ip_hook(void *priv, stru - return nf_flow_xmit_xfrm(skb, state, &rt->dst); - } - -- outdev = rt->dst.dev; -- skb->dev = outdev; -- nexthop = rt_nexthop(rt, flow->tuplehash[!dir].tuple.src_v4.s_addr); -- skb_dst_set_noref(skb, &rt->dst); -- neigh_xmit(NEIGH_ARP_TABLE, outdev, &nexthop, skb); -+ switch (tuplehash->tuple.xmit_type) { -+ case FLOW_OFFLOAD_XMIT_NEIGH: -+ outdev = rt->dst.dev; -+ skb->dev = outdev; -+ nexthop = rt_nexthop(rt, flow->tuplehash[!dir].tuple.src_v4.s_addr); -+ skb_dst_set_noref(skb, &rt->dst); -+ neigh_xmit(NEIGH_ARP_TABLE, outdev, &nexthop, skb); -+ ret = NF_STOLEN; -+ break; -+ case FLOW_OFFLOAD_XMIT_DIRECT: -+ ret = nf_flow_queue_xmit(state->net, skb, tuplehash, ETH_P_IP); -+ if (ret == NF_DROP) -+ flow_offload_teardown(flow); -+ break; -+ } - -- return NF_STOLEN; -+ return ret; - } - EXPORT_SYMBOL_GPL(nf_flow_offload_ip_hook); - -@@ -444,6 +475,7 @@ nf_flow_offload_ipv6_hook(void *priv, st - struct ipv6hdr *ip6h; - struct rt6_info *rt; - u32 hdrsize; -+ int ret; - - if (skb->protocol != htons(ETH_P_IPV6)) - return NF_ACCEPT; -@@ -465,9 +497,13 @@ nf_flow_offload_ipv6_hook(void *priv, st - sizeof(*ip6h))) - return NF_ACCEPT; - -- if (!dst_check(&rt->dst, 0)) { -- flow_offload_teardown(flow); -- return NF_ACCEPT; -+ if (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH || -+ tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM) { -+ rt = (struct rt6_info *)tuplehash->tuple.dst_cache; -+ if (!dst_check(&rt->dst, 0)) { -+ flow_offload_teardown(flow); -+ return NF_ACCEPT; -+ } - } - - if (skb_try_make_writable(skb, sizeof(*ip6h) + hdrsize)) -@@ -484,8 +520,6 @@ nf_flow_offload_ipv6_hook(void *priv, st - if (flow_table->flags & NF_FLOWTABLE_COUNTER) - nf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len); - -- rt = (struct rt6_info *)tuplehash->tuple.dst_cache; -- - if (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) { - memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); - IP6CB(skb)->iif = skb->dev->ifindex; -@@ -493,12 +527,22 @@ nf_flow_offload_ipv6_hook(void *priv, st - return nf_flow_xmit_xfrm(skb, state, &rt->dst); - } - -- outdev = rt->dst.dev; -- skb->dev = outdev; -- nexthop = rt6_nexthop(rt, &flow->tuplehash[!dir].tuple.src_v6); -- skb_dst_set_noref(skb, &rt->dst); -- neigh_xmit(NEIGH_ND_TABLE, outdev, nexthop, skb); -+ switch (tuplehash->tuple.xmit_type) { -+ case FLOW_OFFLOAD_XMIT_NEIGH: -+ outdev = rt->dst.dev; -+ skb->dev = outdev; -+ nexthop = rt6_nexthop(rt, &flow->tuplehash[!dir].tuple.src_v6); -+ skb_dst_set_noref(skb, &rt->dst); -+ neigh_xmit(NEIGH_ND_TABLE, outdev, nexthop, skb); -+ ret = NF_STOLEN; -+ break; -+ case FLOW_OFFLOAD_XMIT_DIRECT: -+ ret = nf_flow_queue_xmit(state->net, skb, tuplehash, ETH_P_IPV6); -+ if (ret == NF_DROP) -+ flow_offload_teardown(flow); -+ break; -+ } - -- return NF_STOLEN; -+ return ret; - } - EXPORT_SYMBOL_GPL(nf_flow_offload_ipv6_hook); ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -39,12 +39,11 @@ static void nft_default_forward_path(str - static int nft_dev_fill_forward_path(const struct nf_flow_route *route, - const struct dst_entry *dst_cache, - const struct nf_conn *ct, -- enum ip_conntrack_dir dir, -+ enum ip_conntrack_dir dir, u8 *ha, - struct net_device_path_stack *stack) - { - const void *daddr = &ct->tuplehash[!dir].tuple.src.u3; - struct net_device *dev = dst_cache->dev; -- unsigned char ha[ETH_ALEN]; - struct neighbour *n; - u8 nud_state; - -@@ -66,27 +65,43 @@ static int nft_dev_fill_forward_path(con - - struct nft_forward_info { - const struct net_device *indev; -+ const struct net_device *outdev; -+ u8 h_source[ETH_ALEN]; -+ u8 h_dest[ETH_ALEN]; -+ enum flow_offload_xmit_type xmit_type; - }; - - static void nft_dev_path_info(const struct net_device_path_stack *stack, -- struct nft_forward_info *info) -+ struct nft_forward_info *info, -+ unsigned char *ha) - { - const struct net_device_path *path; - int i; - -+ memcpy(info->h_dest, ha, ETH_ALEN); -+ - for (i = 0; i < stack->num_paths; i++) { - path = &stack->path[i]; - switch (path->type) { - case DEV_PATH_ETHERNET: - info->indev = path->dev; -+ if (is_zero_ether_addr(info->h_source)) -+ memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN); - break; -- case DEV_PATH_VLAN: - case DEV_PATH_BRIDGE: -+ if (is_zero_ether_addr(info->h_source)) -+ memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN); -+ -+ info->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT; -+ break; -+ case DEV_PATH_VLAN: - default: - info->indev = NULL; - break; - } - } -+ if (!info->outdev) -+ info->outdev = info->indev; - } - - static bool nft_flowtable_find_dev(const struct net_device *dev, -@@ -114,14 +129,22 @@ static void nft_dev_forward_path(struct - const struct dst_entry *dst = route->tuple[dir].dst; - struct net_device_path_stack stack; - struct nft_forward_info info = {}; -+ unsigned char ha[ETH_ALEN]; - -- if (nft_dev_fill_forward_path(route, dst, ct, dir, &stack) >= 0) -- nft_dev_path_info(&stack, &info); -+ if (nft_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0) -+ nft_dev_path_info(&stack, &info, ha); - - if (!info.indev || !nft_flowtable_find_dev(info.indev, ft)) - return; - - route->tuple[!dir].in.ifindex = info.indev->ifindex; -+ -+ if (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) { -+ memcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN); -+ memcpy(route->tuple[dir].out.h_dest, info.h_dest, ETH_ALEN); -+ route->tuple[dir].out.ifindex = info.outdev->ifindex; -+ route->tuple[dir].xmit_type = info.xmit_type; -+ } - } - - static int nft_flow_route(const struct nft_pktinfo *pkt, diff --git a/target/linux/generic/backport-5.10/610-v5.13-20-netfilter-flowtable-add-vlan-support.patch b/target/linux/generic/backport-5.10/610-v5.13-20-netfilter-flowtable-add-vlan-support.patch deleted file mode 100644 index 86a1129880..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-20-netfilter-flowtable-add-vlan-support.patch +++ /dev/null @@ -1,410 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:41 +0100 -Subject: [PATCH] netfilter: flowtable: add vlan support - -Add the vlan id and protocol to the flow tuple to uniquely identify -flows from the receive path. For the transmit path, dev_hard_header() on -the vlan device push the headers. This patch includes support for two -vlan headers (QinQ) from the ingress path. - -Add a generic encap field to the flowtable entry which stores the -protocol and the tag id. This allows to reuse these fields in the PPPoE -support coming in a later patch. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -95,6 +95,8 @@ enum flow_offload_xmit_type { - FLOW_OFFLOAD_XMIT_DIRECT, - }; - -+#define NF_FLOW_TABLE_ENCAP_MAX 2 -+ - struct flow_offload_tuple { - union { - struct in_addr src_v4; -@@ -113,13 +115,17 @@ struct flow_offload_tuple { - - u8 l3proto; - u8 l4proto; -+ struct { -+ u16 id; -+ __be16 proto; -+ } encap[NF_FLOW_TABLE_ENCAP_MAX]; - - /* All members above are keys for lookups, see flow_offload_hash(). */ - struct { } __hash; - -- u8 dir:6, -- xmit_type:2; -- -+ u8 dir:4, -+ xmit_type:2, -+ encap_num:2; - u16 mtu; - union { - struct dst_entry *dst_cache; -@@ -173,6 +179,11 @@ struct nf_flow_route { - struct dst_entry *dst; - struct { - u32 ifindex; -+ struct { -+ u16 id; -+ __be16 proto; -+ } encap[NF_FLOW_TABLE_ENCAP_MAX]; -+ u8 num_encaps; - } in; - struct { - u32 ifindex; ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -80,6 +80,7 @@ static int flow_offload_fill_route(struc - { - struct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple; - struct dst_entry *dst = route->tuple[dir].dst; -+ int i, j = 0; - - switch (flow_tuple->l3proto) { - case NFPROTO_IPV4: -@@ -91,6 +92,12 @@ static int flow_offload_fill_route(struc - } - - flow_tuple->iifidx = route->tuple[dir].in.ifindex; -+ for (i = route->tuple[dir].in.num_encaps - 1; i >= 0; i--) { -+ flow_tuple->encap[j].id = route->tuple[dir].in.encap[i].id; -+ flow_tuple->encap[j].proto = route->tuple[dir].in.encap[i].proto; -+ j++; -+ } -+ flow_tuple->encap_num = route->tuple[dir].in.num_encaps; - - switch (route->tuple[dir].xmit_type) { - case FLOW_OFFLOAD_XMIT_DIRECT: ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -136,23 +136,44 @@ static bool ip_has_options(unsigned int - return thoff != sizeof(struct iphdr); - } - -+static void nf_flow_tuple_encap(struct sk_buff *skb, -+ struct flow_offload_tuple *tuple) -+{ -+ int i = 0; -+ -+ if (skb_vlan_tag_present(skb)) { -+ tuple->encap[i].id = skb_vlan_tag_get(skb); -+ tuple->encap[i].proto = skb->vlan_proto; -+ i++; -+ } -+ if (skb->protocol == htons(ETH_P_8021Q)) { -+ struct vlan_ethhdr *veth = (struct vlan_ethhdr *)skb_mac_header(skb); -+ -+ tuple->encap[i].id = ntohs(veth->h_vlan_TCI); -+ tuple->encap[i].proto = skb->protocol; -+ } -+} -+ - static int nf_flow_tuple_ip(struct sk_buff *skb, const struct net_device *dev, -- struct flow_offload_tuple *tuple, u32 *hdrsize) -+ struct flow_offload_tuple *tuple, u32 *hdrsize, -+ u32 offset) - { - struct flow_ports *ports; - unsigned int thoff; - struct iphdr *iph; - -- if (!pskb_may_pull(skb, sizeof(*iph))) -+ if (!pskb_may_pull(skb, sizeof(*iph) + offset)) - return -1; - -- iph = ip_hdr(skb); -- thoff = iph->ihl * 4; -+ iph = (struct iphdr *)(skb_network_header(skb) + offset); -+ thoff = (iph->ihl * 4); - - if (ip_is_fragment(iph) || - unlikely(ip_has_options(thoff))) - return -1; - -+ thoff += offset; -+ - switch (iph->protocol) { - case IPPROTO_TCP: - *hdrsize = sizeof(struct tcphdr); -@@ -167,11 +188,10 @@ static int nf_flow_tuple_ip(struct sk_bu - if (iph->ttl <= 1) - return -1; - -- thoff = iph->ihl * 4; - if (!pskb_may_pull(skb, thoff + *hdrsize)) - return -1; - -- iph = ip_hdr(skb); -+ iph = (struct iphdr *)(skb_network_header(skb) + offset); - ports = (struct flow_ports *)(skb_network_header(skb) + thoff); - - tuple->src_v4.s_addr = iph->saddr; -@@ -181,6 +201,7 @@ static int nf_flow_tuple_ip(struct sk_bu - tuple->l3proto = AF_INET; - tuple->l4proto = iph->protocol; - tuple->iifidx = dev->ifindex; -+ nf_flow_tuple_encap(skb, tuple); - - return 0; - } -@@ -207,6 +228,43 @@ static unsigned int nf_flow_xmit_xfrm(st - return NF_STOLEN; - } - -+static bool nf_flow_skb_encap_protocol(const struct sk_buff *skb, __be16 proto, -+ u32 *offset) -+{ -+ if (skb->protocol == htons(ETH_P_8021Q)) { -+ struct vlan_ethhdr *veth; -+ -+ veth = (struct vlan_ethhdr *)skb_mac_header(skb); -+ if (veth->h_vlan_encapsulated_proto == proto) { -+ *offset += VLAN_HLEN; -+ return true; -+ } -+ } -+ -+ return false; -+} -+ -+static void nf_flow_encap_pop(struct sk_buff *skb, -+ struct flow_offload_tuple_rhash *tuplehash) -+{ -+ struct vlan_hdr *vlan_hdr; -+ int i; -+ -+ for (i = 0; i < tuplehash->tuple.encap_num; i++) { -+ if (skb_vlan_tag_present(skb)) { -+ __vlan_hwaccel_clear_tag(skb); -+ continue; -+ } -+ if (skb->protocol == htons(ETH_P_8021Q)) { -+ vlan_hdr = (struct vlan_hdr *)skb->data; -+ __skb_pull(skb, VLAN_HLEN); -+ vlan_set_encap_proto(skb, vlan_hdr); -+ skb_reset_network_header(skb); -+ break; -+ } -+ } -+} -+ - static unsigned int nf_flow_queue_xmit(struct net *net, struct sk_buff *skb, - const struct flow_offload_tuple_rhash *tuplehash, - unsigned short type) -@@ -235,17 +293,18 @@ nf_flow_offload_ip_hook(void *priv, stru - enum flow_offload_tuple_dir dir; - struct flow_offload *flow; - struct net_device *outdev; -+ u32 hdrsize, offset = 0; -+ unsigned int thoff, mtu; - struct rtable *rt; -- unsigned int thoff; - struct iphdr *iph; - __be32 nexthop; -- u32 hdrsize; - int ret; - -- if (skb->protocol != htons(ETH_P_IP)) -+ if (skb->protocol != htons(ETH_P_IP) && -+ !nf_flow_skb_encap_protocol(skb, htons(ETH_P_IP), &offset)) - return NF_ACCEPT; - -- if (nf_flow_tuple_ip(skb, state->in, &tuple, &hdrsize) < 0) -+ if (nf_flow_tuple_ip(skb, state->in, &tuple, &hdrsize, offset) < 0) - return NF_ACCEPT; - - tuplehash = flow_offload_lookup(flow_table, &tuple); -@@ -255,11 +314,12 @@ nf_flow_offload_ip_hook(void *priv, stru - dir = tuplehash->tuple.dir; - flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]); - -- if (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu))) -+ mtu = flow->tuplehash[dir].tuple.mtu + offset; -+ if (unlikely(nf_flow_exceeds_mtu(skb, mtu))) - return NF_ACCEPT; - -- iph = ip_hdr(skb); -- thoff = iph->ihl * 4; -+ iph = (struct iphdr *)(skb_network_header(skb) + offset); -+ thoff = (iph->ihl * 4) + offset; - if (nf_flow_state_check(flow, iph->protocol, skb, thoff)) - return NF_ACCEPT; - -@@ -277,6 +337,9 @@ nf_flow_offload_ip_hook(void *priv, stru - - flow_offload_refresh(flow_table, flow); - -+ nf_flow_encap_pop(skb, tuplehash); -+ thoff -= offset; -+ - iph = ip_hdr(skb); - nf_flow_nat_ip(flow, skb, thoff, dir, iph); - -@@ -418,16 +481,18 @@ static void nf_flow_nat_ipv6(const struc - } - - static int nf_flow_tuple_ipv6(struct sk_buff *skb, const struct net_device *dev, -- struct flow_offload_tuple *tuple, u32 *hdrsize) -+ struct flow_offload_tuple *tuple, u32 *hdrsize, -+ u32 offset) - { - struct flow_ports *ports; - struct ipv6hdr *ip6h; - unsigned int thoff; - -- if (!pskb_may_pull(skb, sizeof(*ip6h))) -+ thoff = sizeof(*ip6h) + offset; -+ if (!pskb_may_pull(skb, thoff)) - return -1; - -- ip6h = ipv6_hdr(skb); -+ ip6h = (struct ipv6hdr *)(skb_network_header(skb) + offset); - - switch (ip6h->nexthdr) { - case IPPROTO_TCP: -@@ -443,11 +508,10 @@ static int nf_flow_tuple_ipv6(struct sk_ - if (ip6h->hop_limit <= 1) - return -1; - -- thoff = sizeof(*ip6h); - if (!pskb_may_pull(skb, thoff + *hdrsize)) - return -1; - -- ip6h = ipv6_hdr(skb); -+ ip6h = (struct ipv6hdr *)(skb_network_header(skb) + offset); - ports = (struct flow_ports *)(skb_network_header(skb) + thoff); - - tuple->src_v6 = ip6h->saddr; -@@ -457,6 +521,7 @@ static int nf_flow_tuple_ipv6(struct sk_ - tuple->l3proto = AF_INET6; - tuple->l4proto = ip6h->nexthdr; - tuple->iifidx = dev->ifindex; -+ nf_flow_tuple_encap(skb, tuple); - - return 0; - } -@@ -472,15 +537,17 @@ nf_flow_offload_ipv6_hook(void *priv, st - const struct in6_addr *nexthop; - struct flow_offload *flow; - struct net_device *outdev; -+ unsigned int thoff, mtu; -+ u32 hdrsize, offset = 0; - struct ipv6hdr *ip6h; - struct rt6_info *rt; -- u32 hdrsize; - int ret; - -- if (skb->protocol != htons(ETH_P_IPV6)) -+ if (skb->protocol != htons(ETH_P_IPV6) && -+ !nf_flow_skb_encap_protocol(skb, htons(ETH_P_IPV6), &offset)) - return NF_ACCEPT; - -- if (nf_flow_tuple_ipv6(skb, state->in, &tuple, &hdrsize) < 0) -+ if (nf_flow_tuple_ipv6(skb, state->in, &tuple, &hdrsize, offset) < 0) - return NF_ACCEPT; - - tuplehash = flow_offload_lookup(flow_table, &tuple); -@@ -490,11 +557,13 @@ nf_flow_offload_ipv6_hook(void *priv, st - dir = tuplehash->tuple.dir; - flow = container_of(tuplehash, struct flow_offload, tuplehash[dir]); - -- if (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu))) -+ mtu = flow->tuplehash[dir].tuple.mtu + offset; -+ if (unlikely(nf_flow_exceeds_mtu(skb, mtu))) - return NF_ACCEPT; - -- if (nf_flow_state_check(flow, ipv6_hdr(skb)->nexthdr, skb, -- sizeof(*ip6h))) -+ ip6h = (struct ipv6hdr *)(skb_network_header(skb) + offset); -+ thoff = sizeof(*ip6h) + offset; -+ if (nf_flow_state_check(flow, ip6h->nexthdr, skb, thoff)) - return NF_ACCEPT; - - if (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH || -@@ -506,11 +575,13 @@ nf_flow_offload_ipv6_hook(void *priv, st - } - } - -- if (skb_try_make_writable(skb, sizeof(*ip6h) + hdrsize)) -+ if (skb_try_make_writable(skb, thoff + hdrsize)) - return NF_DROP; - - flow_offload_refresh(flow_table, flow); - -+ nf_flow_encap_pop(skb, tuplehash); -+ - ip6h = ipv6_hdr(skb); - nf_flow_nat_ipv6(flow, skb, dir, ip6h); - ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -66,6 +66,11 @@ static int nft_dev_fill_forward_path(con - struct nft_forward_info { - const struct net_device *indev; - const struct net_device *outdev; -+ struct id { -+ __u16 id; -+ __be16 proto; -+ } encap[NF_FLOW_TABLE_ENCAP_MAX]; -+ u8 num_encaps; - u8 h_source[ETH_ALEN]; - u8 h_dest[ETH_ALEN]; - enum flow_offload_xmit_type xmit_type; -@@ -84,9 +89,23 @@ static void nft_dev_path_info(const stru - path = &stack->path[i]; - switch (path->type) { - case DEV_PATH_ETHERNET: -+ case DEV_PATH_VLAN: - info->indev = path->dev; - if (is_zero_ether_addr(info->h_source)) - memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN); -+ -+ if (path->type == DEV_PATH_ETHERNET) -+ break; -+ -+ /* DEV_PATH_VLAN */ -+ if (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) { -+ info->indev = NULL; -+ break; -+ } -+ info->outdev = path->dev; -+ info->encap[info->num_encaps].id = path->encap.id; -+ info->encap[info->num_encaps].proto = path->encap.proto; -+ info->num_encaps++; - break; - case DEV_PATH_BRIDGE: - if (is_zero_ether_addr(info->h_source)) -@@ -94,7 +113,6 @@ static void nft_dev_path_info(const stru - - info->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT; - break; -- case DEV_PATH_VLAN: - default: - info->indev = NULL; - break; -@@ -130,6 +148,7 @@ static void nft_dev_forward_path(struct - struct net_device_path_stack stack; - struct nft_forward_info info = {}; - unsigned char ha[ETH_ALEN]; -+ int i; - - if (nft_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0) - nft_dev_path_info(&stack, &info, ha); -@@ -138,6 +157,11 @@ static void nft_dev_forward_path(struct - return; - - route->tuple[!dir].in.ifindex = info.indev->ifindex; -+ for (i = 0; i < info.num_encaps; i++) { -+ route->tuple[!dir].in.encap[i].id = info.encap[i].id; -+ route->tuple[!dir].in.encap[i].proto = info.encap[i].proto; -+ } -+ route->tuple[!dir].in.num_encaps = info.num_encaps; - - if (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) { - memcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN); diff --git a/target/linux/generic/backport-5.10/610-v5.13-21-netfilter-flowtable-add-bridge-vlan-filtering-suppor.patch b/target/linux/generic/backport-5.10/610-v5.13-21-netfilter-flowtable-add-bridge-vlan-filtering-suppor.patch deleted file mode 100644 index cb3ef99029..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-21-netfilter-flowtable-add-bridge-vlan-filtering-suppor.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:42 +0100 -Subject: [PATCH] netfilter: flowtable: add bridge vlan filtering support - -Add the vlan tag based when PVID is set on. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -111,6 +111,18 @@ static void nft_dev_path_info(const stru - if (is_zero_ether_addr(info->h_source)) - memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN); - -+ switch (path->bridge.vlan_mode) { -+ case DEV_PATH_BR_VLAN_TAG: -+ info->encap[info->num_encaps].id = path->bridge.vlan_id; -+ info->encap[info->num_encaps].proto = path->bridge.vlan_proto; -+ info->num_encaps++; -+ break; -+ case DEV_PATH_BR_VLAN_UNTAG: -+ info->num_encaps--; -+ break; -+ case DEV_PATH_BR_VLAN_KEEP: -+ break; -+ } - info->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT; - break; - default: diff --git a/target/linux/generic/backport-5.10/610-v5.13-22-netfilter-flowtable-add-pppoe-support.patch b/target/linux/generic/backport-5.10/610-v5.13-22-netfilter-flowtable-add-pppoe-support.patch deleted file mode 100644 index d5789cbad2..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-22-netfilter-flowtable-add-pppoe-support.patch +++ /dev/null @@ -1,145 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:43 +0100 -Subject: [PATCH] netfilter: flowtable: add pppoe support - -Add the PPPoE protocol and session id to the flow tuple using the encap -fields to uniquely identify flows from the receive path. For the -transmit path, dev_hard_header() on the vlan device push the headers. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -7,6 +7,9 @@ - #include - #include - #include -+#include -+#include -+#include - #include - #include - #include -@@ -139,6 +142,8 @@ static bool ip_has_options(unsigned int - static void nf_flow_tuple_encap(struct sk_buff *skb, - struct flow_offload_tuple *tuple) - { -+ struct vlan_ethhdr *veth; -+ struct pppoe_hdr *phdr; - int i = 0; - - if (skb_vlan_tag_present(skb)) { -@@ -146,11 +151,17 @@ static void nf_flow_tuple_encap(struct s - tuple->encap[i].proto = skb->vlan_proto; - i++; - } -- if (skb->protocol == htons(ETH_P_8021Q)) { -- struct vlan_ethhdr *veth = (struct vlan_ethhdr *)skb_mac_header(skb); -- -+ switch (skb->protocol) { -+ case htons(ETH_P_8021Q): -+ veth = (struct vlan_ethhdr *)skb_mac_header(skb); - tuple->encap[i].id = ntohs(veth->h_vlan_TCI); - tuple->encap[i].proto = skb->protocol; -+ break; -+ case htons(ETH_P_PPP_SES): -+ phdr = (struct pppoe_hdr *)skb_mac_header(skb); -+ tuple->encap[i].id = ntohs(phdr->sid); -+ tuple->encap[i].proto = skb->protocol; -+ break; - } - } - -@@ -228,17 +239,41 @@ static unsigned int nf_flow_xmit_xfrm(st - return NF_STOLEN; - } - -+static inline __be16 nf_flow_pppoe_proto(const struct sk_buff *skb) -+{ -+ __be16 proto; -+ -+ proto = *((__be16 *)(skb_mac_header(skb) + ETH_HLEN + -+ sizeof(struct pppoe_hdr))); -+ switch (proto) { -+ case htons(PPP_IP): -+ return htons(ETH_P_IP); -+ case htons(PPP_IPV6): -+ return htons(ETH_P_IPV6); -+ } -+ -+ return 0; -+} -+ - static bool nf_flow_skb_encap_protocol(const struct sk_buff *skb, __be16 proto, - u32 *offset) - { -- if (skb->protocol == htons(ETH_P_8021Q)) { -- struct vlan_ethhdr *veth; -+ struct vlan_ethhdr *veth; - -+ switch (skb->protocol) { -+ case htons(ETH_P_8021Q): - veth = (struct vlan_ethhdr *)skb_mac_header(skb); - if (veth->h_vlan_encapsulated_proto == proto) { - *offset += VLAN_HLEN; - return true; - } -+ break; -+ case htons(ETH_P_PPP_SES): -+ if (nf_flow_pppoe_proto(skb) == proto) { -+ *offset += PPPOE_SES_HLEN; -+ return true; -+ } -+ break; - } - - return false; -@@ -255,12 +290,18 @@ static void nf_flow_encap_pop(struct sk_ - __vlan_hwaccel_clear_tag(skb); - continue; - } -- if (skb->protocol == htons(ETH_P_8021Q)) { -+ switch (skb->protocol) { -+ case htons(ETH_P_8021Q): - vlan_hdr = (struct vlan_hdr *)skb->data; - __skb_pull(skb, VLAN_HLEN); - vlan_set_encap_proto(skb, vlan_hdr); - skb_reset_network_header(skb); - break; -+ case htons(ETH_P_PPP_SES): -+ skb->protocol = nf_flow_pppoe_proto(skb); -+ skb_pull(skb, PPPOE_SES_HLEN); -+ skb_reset_network_header(skb); -+ break; - } - } - } ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -90,6 +90,7 @@ static void nft_dev_path_info(const stru - switch (path->type) { - case DEV_PATH_ETHERNET: - case DEV_PATH_VLAN: -+ case DEV_PATH_PPPOE: - info->indev = path->dev; - if (is_zero_ether_addr(info->h_source)) - memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN); -@@ -97,7 +98,7 @@ static void nft_dev_path_info(const stru - if (path->type == DEV_PATH_ETHERNET) - break; - -- /* DEV_PATH_VLAN */ -+ /* DEV_PATH_VLAN and DEV_PATH_PPPOE */ - if (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) { - info->indev = NULL; - break; -@@ -106,6 +107,8 @@ static void nft_dev_path_info(const stru - info->encap[info->num_encaps].id = path->encap.id; - info->encap[info->num_encaps].proto = path->encap.proto; - info->num_encaps++; -+ if (path->type == DEV_PATH_PPPOE) -+ memcpy(info->h_dest, path->encap.h_dest, ETH_ALEN); - break; - case DEV_PATH_BRIDGE: - if (is_zero_ether_addr(info->h_source)) diff --git a/target/linux/generic/backport-5.10/610-v5.13-23-netfilter-flowtable-add-dsa-support.patch b/target/linux/generic/backport-5.10/610-v5.13-23-netfilter-flowtable-add-dsa-support.patch deleted file mode 100644 index b4931830d3..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-23-netfilter-flowtable-add-dsa-support.patch +++ /dev/null @@ -1,32 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:44 +0100 -Subject: [PATCH] netfilter: flowtable: add dsa support - -Replace the master ethernet device by the dsa slave port. Packets coming -in from the software ingress path use the dsa slave port as input -device. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -89,6 +89,7 @@ static void nft_dev_path_info(const stru - path = &stack->path[i]; - switch (path->type) { - case DEV_PATH_ETHERNET: -+ case DEV_PATH_DSA: - case DEV_PATH_VLAN: - case DEV_PATH_PPPOE: - info->indev = path->dev; -@@ -97,6 +98,10 @@ static void nft_dev_path_info(const stru - - if (path->type == DEV_PATH_ETHERNET) - break; -+ if (path->type == DEV_PATH_DSA) { -+ i = stack->num_paths; -+ break; -+ } - - /* DEV_PATH_VLAN and DEV_PATH_PPPOE */ - if (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) { diff --git a/target/linux/generic/backport-5.10/610-v5.13-24-selftests-netfilter-flowtable-bridge-and-vlan-suppor.patch b/target/linux/generic/backport-5.10/610-v5.13-24-selftests-netfilter-flowtable-bridge-and-vlan-suppor.patch deleted file mode 100644 index 3f332c70d3..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-24-selftests-netfilter-flowtable-bridge-and-vlan-suppor.patch +++ /dev/null @@ -1,107 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:45 +0100 -Subject: [PATCH] selftests: netfilter: flowtable bridge and vlan support - -This patch adds two new tests to cover bridge and vlan support: - -- Add a bridge device to the Router1 (nsr1) container and attach the - veth0 device to the bridge. Set the IP address to the bridge device - to exercise the bridge forwarding path. - -- Add vlan encapsulation between to the bridge device in the Router1 and - one of the sender containers (ns1). - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/tools/testing/selftests/netfilter/nft_flowtable.sh -+++ b/tools/testing/selftests/netfilter/nft_flowtable.sh -@@ -370,6 +370,88 @@ else - ip netns exec nsr1 nft list ruleset - fi - -+# Another test: -+# Add bridge interface br0 to Router1, with NAT enabled. -+ip -net nsr1 link add name br0 type bridge -+ip -net nsr1 addr flush dev veth0 -+ip -net nsr1 link set up dev veth0 -+ip -net nsr1 link set veth0 master br0 -+ip -net nsr1 addr add 10.0.1.1/24 dev br0 -+ip -net nsr1 addr add dead:1::1/64 dev br0 -+ip -net nsr1 link set up dev br0 -+ -+ip netns exec nsr1 sysctl net.ipv4.conf.br0.forwarding=1 > /dev/null -+ -+# br0 with NAT enabled. -+ip netns exec nsr1 nft -f - <&2 -+ ip netns exec nsr1 nft list ruleset -+ ret=1 -+fi -+ -+# Another test: -+# Add bridge interface br0 to Router1, with NAT and VLAN. -+ip -net nsr1 link set veth0 nomaster -+ip -net nsr1 link set down dev veth0 -+ip -net nsr1 link add link veth0 name veth0.10 type vlan id 10 -+ip -net nsr1 link set up dev veth0 -+ip -net nsr1 link set up dev veth0.10 -+ip -net nsr1 link set veth0.10 master br0 -+ -+ip -net ns1 addr flush dev eth0 -+ip -net ns1 link add link eth0 name eth0.10 type vlan id 10 -+ip -net ns1 link set eth0 up -+ip -net ns1 link set eth0.10 up -+ip -net ns1 addr add 10.0.1.99/24 dev eth0.10 -+ip -net ns1 route add default via 10.0.1.1 -+ip -net ns1 addr add dead:1::99/64 dev eth0.10 -+ -+if test_tcp_forwarding_nat ns1 ns2; then -+ echo "PASS: flow offloaded for ns1/ns2 with bridge NAT and VLAN" -+else -+ echo "FAIL: flow offload for ns1/ns2 with bridge NAT and VLAN" 1>&2 -+ ip netns exec nsr1 nft list ruleset -+ ret=1 -+fi -+ -+# restore test topology (remove bridge and VLAN) -+ip -net nsr1 link set veth0 nomaster -+ip -net nsr1 link set veth0 down -+ip -net nsr1 link set veth0.10 down -+ip -net nsr1 link delete veth0.10 type vlan -+ip -net nsr1 link delete br0 type bridge -+ip -net ns1 addr flush dev eth0.10 -+ip -net ns1 link set eth0.10 down -+ip -net ns1 link set eth0 down -+ip -net ns1 link delete eth0.10 type vlan -+ -+# restore address in ns1 and nsr1 -+ip -net ns1 link set eth0 up -+ip -net ns1 addr add 10.0.1.99/24 dev eth0 -+ip -net ns1 route add default via 10.0.1.1 -+ip -net ns1 addr add dead:1::99/64 dev eth0 -+ip -net ns1 route add default via dead:1::1 -+ip -net nsr1 addr add 10.0.1.1/24 dev veth0 -+ip -net nsr1 addr add dead:1::1/64 dev veth0 -+ip -net nsr1 link set up dev veth0 -+ - KEY_SHA="0x"$(ps -xaf | sha1sum | cut -d " " -f 1) - KEY_AES="0x"$(ps -xaf | md5sum | cut -d " " -f 1) - SPI1=$RANDOM diff --git a/target/linux/generic/backport-5.10/610-v5.13-25-netfilter-flowtable-add-offload-support-for-xmit-pat.patch b/target/linux/generic/backport-5.10/610-v5.13-25-netfilter-flowtable-add-offload-support-for-xmit-pat.patch deleted file mode 100644 index 7b6ec68d55..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-25-netfilter-flowtable-add-offload-support-for-xmit-pat.patch +++ /dev/null @@ -1,310 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:46 +0100 -Subject: [PATCH] netfilter: flowtable: add offload support for xmit path - types - -When the flow tuple xmit_type is set to FLOW_OFFLOAD_XMIT_DIRECT, the -dst_cache pointer is not valid, and the h_source/h_dest/ifidx out fields -need to be used. - -This patch also adds the FLOW_ACTION_VLAN_PUSH action to pass the VLAN -tag to the driver. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_offload.c -+++ b/net/netfilter/nf_flow_table_offload.c -@@ -177,28 +177,45 @@ static int flow_offload_eth_src(struct n - enum flow_offload_tuple_dir dir, - struct nf_flow_rule *flow_rule) - { -- const struct flow_offload_tuple *tuple = &flow->tuplehash[!dir].tuple; - struct flow_action_entry *entry0 = flow_action_entry_next(flow_rule); - struct flow_action_entry *entry1 = flow_action_entry_next(flow_rule); -- struct net_device *dev; -+ const struct flow_offload_tuple *other_tuple, *this_tuple; -+ struct net_device *dev = NULL; -+ const unsigned char *addr; - u32 mask, val; - u16 val16; - -- dev = dev_get_by_index(net, tuple->iifidx); -- if (!dev) -- return -ENOENT; -+ this_tuple = &flow->tuplehash[dir].tuple; -+ -+ switch (this_tuple->xmit_type) { -+ case FLOW_OFFLOAD_XMIT_DIRECT: -+ addr = this_tuple->out.h_source; -+ break; -+ case FLOW_OFFLOAD_XMIT_NEIGH: -+ other_tuple = &flow->tuplehash[!dir].tuple; -+ dev = dev_get_by_index(net, other_tuple->iifidx); -+ if (!dev) -+ return -ENOENT; -+ -+ addr = dev->dev_addr; -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } - - mask = ~0xffff0000; -- memcpy(&val16, dev->dev_addr, 2); -+ memcpy(&val16, addr, 2); - val = val16 << 16; - flow_offload_mangle(entry0, FLOW_ACT_MANGLE_HDR_TYPE_ETH, 4, - &val, &mask); - - mask = ~0xffffffff; -- memcpy(&val, dev->dev_addr + 2, 4); -+ memcpy(&val, addr + 2, 4); - flow_offload_mangle(entry1, FLOW_ACT_MANGLE_HDR_TYPE_ETH, 8, - &val, &mask); -- dev_put(dev); -+ -+ if (dev) -+ dev_put(dev); - - return 0; - } -@@ -210,27 +227,40 @@ static int flow_offload_eth_dst(struct n - { - struct flow_action_entry *entry0 = flow_action_entry_next(flow_rule); - struct flow_action_entry *entry1 = flow_action_entry_next(flow_rule); -- const void *daddr = &flow->tuplehash[!dir].tuple.src_v4; -+ const struct flow_offload_tuple *other_tuple, *this_tuple; - const struct dst_entry *dst_cache; - unsigned char ha[ETH_ALEN]; - struct neighbour *n; -+ const void *daddr; - u32 mask, val; - u8 nud_state; - u16 val16; - -- dst_cache = flow->tuplehash[dir].tuple.dst_cache; -- n = dst_neigh_lookup(dst_cache, daddr); -- if (!n) -- return -ENOENT; -- -- read_lock_bh(&n->lock); -- nud_state = n->nud_state; -- ether_addr_copy(ha, n->ha); -- read_unlock_bh(&n->lock); -+ this_tuple = &flow->tuplehash[dir].tuple; - -- if (!(nud_state & NUD_VALID)) { -+ switch (this_tuple->xmit_type) { -+ case FLOW_OFFLOAD_XMIT_DIRECT: -+ ether_addr_copy(ha, this_tuple->out.h_dest); -+ break; -+ case FLOW_OFFLOAD_XMIT_NEIGH: -+ other_tuple = &flow->tuplehash[!dir].tuple; -+ daddr = &other_tuple->src_v4; -+ dst_cache = this_tuple->dst_cache; -+ n = dst_neigh_lookup(dst_cache, daddr); -+ if (!n) -+ return -ENOENT; -+ -+ read_lock_bh(&n->lock); -+ nud_state = n->nud_state; -+ ether_addr_copy(ha, n->ha); -+ read_unlock_bh(&n->lock); - neigh_release(n); -- return -ENOENT; -+ -+ if (!(nud_state & NUD_VALID)) -+ return -ENOENT; -+ break; -+ default: -+ return -EOPNOTSUPP; - } - - mask = ~0xffffffff; -@@ -243,7 +273,6 @@ static int flow_offload_eth_dst(struct n - val = val16; - flow_offload_mangle(entry1, FLOW_ACT_MANGLE_HDR_TYPE_ETH, 4, - &val, &mask); -- neigh_release(n); - - return 0; - } -@@ -465,27 +494,52 @@ static void flow_offload_ipv4_checksum(s - } - } - --static void flow_offload_redirect(const struct flow_offload *flow, -+static void flow_offload_redirect(struct net *net, -+ const struct flow_offload *flow, - enum flow_offload_tuple_dir dir, - struct nf_flow_rule *flow_rule) - { -- struct flow_action_entry *entry = flow_action_entry_next(flow_rule); -- struct rtable *rt; -+ const struct flow_offload_tuple *this_tuple, *other_tuple; -+ struct flow_action_entry *entry; -+ struct net_device *dev; -+ int ifindex; -+ -+ this_tuple = &flow->tuplehash[dir].tuple; -+ switch (this_tuple->xmit_type) { -+ case FLOW_OFFLOAD_XMIT_DIRECT: -+ this_tuple = &flow->tuplehash[dir].tuple; -+ ifindex = this_tuple->out.ifidx; -+ break; -+ case FLOW_OFFLOAD_XMIT_NEIGH: -+ other_tuple = &flow->tuplehash[!dir].tuple; -+ ifindex = other_tuple->iifidx; -+ break; -+ default: -+ return; -+ } - -- rt = (struct rtable *)flow->tuplehash[dir].tuple.dst_cache; -+ dev = dev_get_by_index(net, ifindex); -+ if (!dev) -+ return; -+ -+ entry = flow_action_entry_next(flow_rule); - entry->id = FLOW_ACTION_REDIRECT; -- entry->dev = rt->dst.dev; -- dev_hold(rt->dst.dev); -+ entry->dev = dev; - } - - static void flow_offload_encap_tunnel(const struct flow_offload *flow, - enum flow_offload_tuple_dir dir, - struct nf_flow_rule *flow_rule) - { -+ const struct flow_offload_tuple *this_tuple; - struct flow_action_entry *entry; - struct dst_entry *dst; - -- dst = flow->tuplehash[dir].tuple.dst_cache; -+ this_tuple = &flow->tuplehash[dir].tuple; -+ if (this_tuple->xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) -+ return; -+ -+ dst = this_tuple->dst_cache; - if (dst && dst->lwtstate) { - struct ip_tunnel_info *tun_info; - -@@ -502,10 +556,15 @@ static void flow_offload_decap_tunnel(co - enum flow_offload_tuple_dir dir, - struct nf_flow_rule *flow_rule) - { -+ const struct flow_offload_tuple *other_tuple; - struct flow_action_entry *entry; - struct dst_entry *dst; - -- dst = flow->tuplehash[!dir].tuple.dst_cache; -+ other_tuple = &flow->tuplehash[!dir].tuple; -+ if (other_tuple->xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) -+ return; -+ -+ dst = other_tuple->dst_cache; - if (dst && dst->lwtstate) { - struct ip_tunnel_info *tun_info; - -@@ -517,10 +576,14 @@ static void flow_offload_decap_tunnel(co - } - } - --int nf_flow_rule_route_ipv4(struct net *net, const struct flow_offload *flow, -- enum flow_offload_tuple_dir dir, -- struct nf_flow_rule *flow_rule) -+static int -+nf_flow_rule_route_common(struct net *net, const struct flow_offload *flow, -+ enum flow_offload_tuple_dir dir, -+ struct nf_flow_rule *flow_rule) - { -+ const struct flow_offload_tuple *other_tuple; -+ int i; -+ - flow_offload_decap_tunnel(flow, dir, flow_rule); - flow_offload_encap_tunnel(flow, dir, flow_rule); - -@@ -528,6 +591,26 @@ int nf_flow_rule_route_ipv4(struct net * - flow_offload_eth_dst(net, flow, dir, flow_rule) < 0) - return -1; - -+ other_tuple = &flow->tuplehash[!dir].tuple; -+ -+ for (i = 0; i < other_tuple->encap_num; i++) { -+ struct flow_action_entry *entry = flow_action_entry_next(flow_rule); -+ -+ entry->id = FLOW_ACTION_VLAN_PUSH; -+ entry->vlan.vid = other_tuple->encap[i].id; -+ entry->vlan.proto = other_tuple->encap[i].proto; -+ } -+ -+ return 0; -+} -+ -+int nf_flow_rule_route_ipv4(struct net *net, const struct flow_offload *flow, -+ enum flow_offload_tuple_dir dir, -+ struct nf_flow_rule *flow_rule) -+{ -+ if (nf_flow_rule_route_common(net, flow, dir, flow_rule) < 0) -+ return -1; -+ - if (test_bit(NF_FLOW_SNAT, &flow->flags)) { - flow_offload_ipv4_snat(net, flow, dir, flow_rule); - flow_offload_port_snat(net, flow, dir, flow_rule); -@@ -540,7 +623,7 @@ int nf_flow_rule_route_ipv4(struct net * - test_bit(NF_FLOW_DNAT, &flow->flags)) - flow_offload_ipv4_checksum(net, flow, flow_rule); - -- flow_offload_redirect(flow, dir, flow_rule); -+ flow_offload_redirect(net, flow, dir, flow_rule); - - return 0; - } -@@ -550,11 +633,7 @@ int nf_flow_rule_route_ipv6(struct net * - enum flow_offload_tuple_dir dir, - struct nf_flow_rule *flow_rule) - { -- flow_offload_decap_tunnel(flow, dir, flow_rule); -- flow_offload_encap_tunnel(flow, dir, flow_rule); -- -- if (flow_offload_eth_src(net, flow, dir, flow_rule) < 0 || -- flow_offload_eth_dst(net, flow, dir, flow_rule) < 0) -+ if (nf_flow_rule_route_common(net, flow, dir, flow_rule) < 0) - return -1; - - if (test_bit(NF_FLOW_SNAT, &flow->flags)) { -@@ -566,7 +645,7 @@ int nf_flow_rule_route_ipv6(struct net * - flow_offload_port_dnat(net, flow, dir, flow_rule); - } - -- flow_offload_redirect(flow, dir, flow_rule); -+ flow_offload_redirect(net, flow, dir, flow_rule); - - return 0; - } -@@ -580,10 +659,10 @@ nf_flow_offload_rule_alloc(struct net *n - enum flow_offload_tuple_dir dir) - { - const struct nf_flowtable *flowtable = offload->flowtable; -+ const struct flow_offload_tuple *tuple, *other_tuple; - const struct flow_offload *flow = offload->flow; -- const struct flow_offload_tuple *tuple; -+ struct dst_entry *other_dst = NULL; - struct nf_flow_rule *flow_rule; -- struct dst_entry *other_dst; - int err = -ENOMEM; - - flow_rule = kzalloc(sizeof(*flow_rule), GFP_KERNEL); -@@ -599,7 +678,10 @@ nf_flow_offload_rule_alloc(struct net *n - flow_rule->rule->match.key = &flow_rule->match.key; - - tuple = &flow->tuplehash[dir].tuple; -- other_dst = flow->tuplehash[!dir].tuple.dst_cache; -+ other_tuple = &flow->tuplehash[!dir].tuple; -+ if (other_tuple->xmit_type == FLOW_OFFLOAD_XMIT_NEIGH) -+ other_dst = other_tuple->dst_cache; -+ - err = nf_flow_rule_match(&flow_rule->match, tuple, other_dst); - if (err < 0) - goto err_flow_match; diff --git a/target/linux/generic/backport-5.10/610-v5.13-26-netfilter-nft_flow_offload-use-direct-xmit-if-hardwa.patch b/target/linux/generic/backport-5.10/610-v5.13-26-netfilter-nft_flow_offload-use-direct-xmit-if-hardwa.patch deleted file mode 100644 index 56bb9fd56b..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-26-netfilter-nft_flow_offload-use-direct-xmit-if-hardwa.patch +++ /dev/null @@ -1,114 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:47 +0100 -Subject: [PATCH] netfilter: nft_flow_offload: use direct xmit if - hardware offload is enabled - -If there is a forward path to reach an ethernet device and hardware -offload is enabled, then use the direct xmit path. - -Moreover, store the real device in the direct xmit path info since -software datapath uses dev_hard_header() to push the layer encapsulation -headers while hardware offload refers to the real device. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -131,6 +131,7 @@ struct flow_offload_tuple { - struct dst_entry *dst_cache; - struct { - u32 ifidx; -+ u32 hw_ifidx; - u8 h_source[ETH_ALEN]; - u8 h_dest[ETH_ALEN]; - } out; -@@ -187,6 +188,7 @@ struct nf_flow_route { - } in; - struct { - u32 ifindex; -+ u32 hw_ifindex; - u8 h_source[ETH_ALEN]; - u8 h_dest[ETH_ALEN]; - } out; ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -106,6 +106,7 @@ static int flow_offload_fill_route(struc - memcpy(flow_tuple->out.h_source, route->tuple[dir].out.h_source, - ETH_ALEN); - flow_tuple->out.ifidx = route->tuple[dir].out.ifindex; -+ flow_tuple->out.hw_ifidx = route->tuple[dir].out.hw_ifindex; - break; - case FLOW_OFFLOAD_XMIT_XFRM: - case FLOW_OFFLOAD_XMIT_NEIGH: ---- a/net/netfilter/nf_flow_table_offload.c -+++ b/net/netfilter/nf_flow_table_offload.c -@@ -508,7 +508,7 @@ static void flow_offload_redirect(struct - switch (this_tuple->xmit_type) { - case FLOW_OFFLOAD_XMIT_DIRECT: - this_tuple = &flow->tuplehash[dir].tuple; -- ifindex = this_tuple->out.ifidx; -+ ifindex = this_tuple->out.hw_ifidx; - break; - case FLOW_OFFLOAD_XMIT_NEIGH: - other_tuple = &flow->tuplehash[!dir].tuple; ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -66,6 +66,7 @@ static int nft_dev_fill_forward_path(con - struct nft_forward_info { - const struct net_device *indev; - const struct net_device *outdev; -+ const struct net_device *hw_outdev; - struct id { - __u16 id; - __be16 proto; -@@ -76,9 +77,18 @@ struct nft_forward_info { - enum flow_offload_xmit_type xmit_type; - }; - -+static bool nft_is_valid_ether_device(const struct net_device *dev) -+{ -+ if (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER || -+ dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr)) -+ return false; -+ -+ return true; -+} -+ - static void nft_dev_path_info(const struct net_device_path_stack *stack, - struct nft_forward_info *info, -- unsigned char *ha) -+ unsigned char *ha, struct nf_flowtable *flowtable) - { - const struct net_device_path *path; - int i; -@@ -140,6 +150,12 @@ static void nft_dev_path_info(const stru - } - if (!info->outdev) - info->outdev = info->indev; -+ -+ info->hw_outdev = info->indev; -+ -+ if (nf_flowtable_hw_offload(flowtable) && -+ nft_is_valid_ether_device(info->indev)) -+ info->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT; - } - - static bool nft_flowtable_find_dev(const struct net_device *dev, -@@ -171,7 +187,7 @@ static void nft_dev_forward_path(struct - int i; - - if (nft_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0) -- nft_dev_path_info(&stack, &info, ha); -+ nft_dev_path_info(&stack, &info, ha, &ft->data); - - if (!info.indev || !nft_flowtable_find_dev(info.indev, ft)) - return; -@@ -187,6 +203,7 @@ static void nft_dev_forward_path(struct - memcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN); - memcpy(route->tuple[dir].out.h_dest, info.h_dest, ETH_ALEN); - route->tuple[dir].out.ifindex = info.outdev->ifindex; -+ route->tuple[dir].out.hw_ifindex = info.hw_outdev->ifindex; - route->tuple[dir].xmit_type = info.xmit_type; - } - } diff --git a/target/linux/generic/backport-5.10/610-v5.13-27-netfilter-flowtable-bridge-vlan-hardware-offload-and.patch b/target/linux/generic/backport-5.10/610-v5.13-27-netfilter-flowtable-bridge-vlan-hardware-offload-and.patch deleted file mode 100644 index 08c92d731a..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-27-netfilter-flowtable-bridge-vlan-hardware-offload-and.patch +++ /dev/null @@ -1,123 +0,0 @@ -From: Felix Fietkau -Date: Wed, 24 Mar 2021 02:30:48 +0100 -Subject: [PATCH] netfilter: flowtable: bridge vlan hardware offload and - switchdev - -The switch might have already added the VLAN tag through PVID hardware -offload. Keep this extra VLAN in the flowtable but skip it on egress. - -Signed-off-by: Felix Fietkau -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -872,6 +872,7 @@ struct net_device_path { - DEV_PATH_BR_VLAN_KEEP, - DEV_PATH_BR_VLAN_TAG, - DEV_PATH_BR_VLAN_UNTAG, -+ DEV_PATH_BR_VLAN_UNTAG_HW, - } vlan_mode; - u16 vlan_id; - __be16 vlan_proto; ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -123,9 +123,10 @@ struct flow_offload_tuple { - /* All members above are keys for lookups, see flow_offload_hash(). */ - struct { } __hash; - -- u8 dir:4, -+ u8 dir:2, - xmit_type:2, -- encap_num:2; -+ encap_num:2, -+ in_vlan_ingress:2; - u16 mtu; - union { - struct dst_entry *dst_cache; -@@ -184,7 +185,8 @@ struct nf_flow_route { - u16 id; - __be16 proto; - } encap[NF_FLOW_TABLE_ENCAP_MAX]; -- u8 num_encaps; -+ u8 num_encaps:2, -+ ingress_vlans:2; - } in; - struct { - u32 ifindex; ---- a/net/bridge/br_device.c -+++ b/net/bridge/br_device.c -@@ -435,6 +435,7 @@ static int br_fill_forward_path(struct n - ctx->vlan[ctx->num_vlans].proto = path->bridge.vlan_proto; - ctx->num_vlans++; - break; -+ case DEV_PATH_BR_VLAN_UNTAG_HW: - case DEV_PATH_BR_VLAN_UNTAG: - ctx->num_vlans--; - break; ---- a/net/bridge/br_vlan.c -+++ b/net/bridge/br_vlan.c -@@ -1397,6 +1397,8 @@ int br_vlan_fill_forward_path_mode(struc - - if (path->bridge.vlan_mode == DEV_PATH_BR_VLAN_TAG) - path->bridge.vlan_mode = DEV_PATH_BR_VLAN_KEEP; -+ else if (v->priv_flags & BR_VLFLAG_ADDED_BY_SWITCHDEV) -+ path->bridge.vlan_mode = DEV_PATH_BR_VLAN_UNTAG_HW; - else - path->bridge.vlan_mode = DEV_PATH_BR_VLAN_UNTAG; - ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -95,6 +95,8 @@ static int flow_offload_fill_route(struc - for (i = route->tuple[dir].in.num_encaps - 1; i >= 0; i--) { - flow_tuple->encap[j].id = route->tuple[dir].in.encap[i].id; - flow_tuple->encap[j].proto = route->tuple[dir].in.encap[i].proto; -+ if (route->tuple[dir].in.ingress_vlans & BIT(i)) -+ flow_tuple->in_vlan_ingress |= BIT(j); - j++; - } - flow_tuple->encap_num = route->tuple[dir].in.num_encaps; ---- a/net/netfilter/nf_flow_table_offload.c -+++ b/net/netfilter/nf_flow_table_offload.c -@@ -594,8 +594,12 @@ nf_flow_rule_route_common(struct net *ne - other_tuple = &flow->tuplehash[!dir].tuple; - - for (i = 0; i < other_tuple->encap_num; i++) { -- struct flow_action_entry *entry = flow_action_entry_next(flow_rule); -+ struct flow_action_entry *entry; - -+ if (other_tuple->in_vlan_ingress & BIT(i)) -+ continue; -+ -+ entry = flow_action_entry_next(flow_rule); - entry->id = FLOW_ACTION_VLAN_PUSH; - entry->vlan.vid = other_tuple->encap[i].id; - entry->vlan.proto = other_tuple->encap[i].proto; ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -72,6 +72,7 @@ struct nft_forward_info { - __be16 proto; - } encap[NF_FLOW_TABLE_ENCAP_MAX]; - u8 num_encaps; -+ u8 ingress_vlans; - u8 h_source[ETH_ALEN]; - u8 h_dest[ETH_ALEN]; - enum flow_offload_xmit_type xmit_type; -@@ -130,6 +131,9 @@ static void nft_dev_path_info(const stru - memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN); - - switch (path->bridge.vlan_mode) { -+ case DEV_PATH_BR_VLAN_UNTAG_HW: -+ info->ingress_vlans |= BIT(info->num_encaps - 1); -+ break; - case DEV_PATH_BR_VLAN_TAG: - info->encap[info->num_encaps].id = path->bridge.vlan_id; - info->encap[info->num_encaps].proto = path->bridge.vlan_proto; -@@ -198,6 +202,7 @@ static void nft_dev_forward_path(struct - route->tuple[!dir].in.encap[i].proto = info.encap[i].proto; - } - route->tuple[!dir].in.num_encaps = info.num_encaps; -+ route->tuple[!dir].in.ingress_vlans = info.ingress_vlans; - - if (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) { - memcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN); diff --git a/target/linux/generic/backport-5.10/610-v5.13-28-net-flow_offload-add-FLOW_ACTION_PPPOE_PUSH.patch b/target/linux/generic/backport-5.10/610-v5.13-28-net-flow_offload-add-FLOW_ACTION_PPPOE_PUSH.patch deleted file mode 100644 index 64eae6871f..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-28-net-flow_offload-add-FLOW_ACTION_PPPOE_PUSH.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:49 +0100 -Subject: [PATCH] net: flow_offload: add FLOW_ACTION_PPPOE_PUSH - -Add an action to represent the PPPoE hardware offload support that -includes the session ID. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/flow_offload.h -+++ b/include/net/flow_offload.h -@@ -147,6 +147,7 @@ enum flow_action_id { - FLOW_ACTION_MPLS_POP, - FLOW_ACTION_MPLS_MANGLE, - FLOW_ACTION_GATE, -+ FLOW_ACTION_PPPOE_PUSH, - NUM_FLOW_ACTIONS, - }; - -@@ -271,6 +272,9 @@ struct flow_action_entry { - u32 num_entries; - struct action_gate_entry *entries; - } gate; -+ struct { /* FLOW_ACTION_PPPOE_PUSH */ -+ u16 sid; -+ } pppoe; - }; - struct flow_action_cookie *cookie; /* user defined action cookie */ - }; diff --git a/target/linux/generic/backport-5.10/610-v5.13-29-netfilter-flowtable-support-for-FLOW_ACTION_PPPOE_PU.patch b/target/linux/generic/backport-5.10/610-v5.13-29-netfilter-flowtable-support-for-FLOW_ACTION_PPPOE_PU.patch deleted file mode 100644 index ed7346a61a..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-29-netfilter-flowtable-support-for-FLOW_ACTION_PPPOE_PU.patch +++ /dev/null @@ -1,35 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:50 +0100 -Subject: [PATCH] netfilter: flowtable: support for - FLOW_ACTION_PPPOE_PUSH - -Add a PPPoE push action if layer 2 protocol is ETH_P_PPP_SES to add -PPPoE flowtable hardware offload support. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_offload.c -+++ b/net/netfilter/nf_flow_table_offload.c -@@ -600,9 +600,18 @@ nf_flow_rule_route_common(struct net *ne - continue; - - entry = flow_action_entry_next(flow_rule); -- entry->id = FLOW_ACTION_VLAN_PUSH; -- entry->vlan.vid = other_tuple->encap[i].id; -- entry->vlan.proto = other_tuple->encap[i].proto; -+ -+ switch (other_tuple->encap[i].proto) { -+ case htons(ETH_P_PPP_SES): -+ entry->id = FLOW_ACTION_PPPOE_PUSH; -+ entry->pppoe.sid = other_tuple->encap[i].id; -+ break; -+ case htons(ETH_P_8021Q): -+ entry->id = FLOW_ACTION_VLAN_PUSH; -+ entry->vlan.vid = other_tuple->encap[i].id; -+ entry->vlan.proto = other_tuple->encap[i].proto; -+ break; -+ } - } - - return 0; diff --git a/target/linux/generic/backport-5.10/610-v5.13-30-dsa-slave-add-support-for-TC_SETUP_FT.patch b/target/linux/generic/backport-5.10/610-v5.13-30-dsa-slave-add-support-for-TC_SETUP_FT.patch deleted file mode 100644 index 72675dc294..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-30-dsa-slave-add-support-for-TC_SETUP_FT.patch +++ /dev/null @@ -1,53 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:51 +0100 -Subject: [PATCH] dsa: slave: add support for TC_SETUP_FT - -The dsa infrastructure provides a well-defined hierarchy of devices, -pass up the call to set up the flow block to the master device. From the -software dataplane, the netfilter infrastructure uses the dsa slave -devices to refer to the input and output device for the given skbuff. -Similarly, the flowtable definition in the ruleset refers to the dsa -slave port devices. - -This patch adds the glue code to call ndo_setup_tc with TC_SETUP_FT -with the master device via the dsa slave devices. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -1239,14 +1239,32 @@ static int dsa_slave_setup_tc_block(stru - } - } - -+static int dsa_slave_setup_ft_block(struct dsa_switch *ds, int port, -+ void *type_data) -+{ -+ struct dsa_port *cpu_dp = dsa_to_port(ds, port)->cpu_dp; -+ struct net_device *master = cpu_dp->master; -+ -+ if (!master->netdev_ops->ndo_setup_tc) -+ return -EOPNOTSUPP; -+ -+ return master->netdev_ops->ndo_setup_tc(master, TC_SETUP_FT, type_data); -+} -+ - static int dsa_slave_setup_tc(struct net_device *dev, enum tc_setup_type type, - void *type_data) - { - struct dsa_port *dp = dsa_slave_to_port(dev); - struct dsa_switch *ds = dp->ds; - -- if (type == TC_SETUP_BLOCK) -+ switch (type) { -+ case TC_SETUP_BLOCK: - return dsa_slave_setup_tc_block(dev, type_data); -+ case TC_SETUP_FT: -+ return dsa_slave_setup_ft_block(ds, dp->index, type_data); -+ default: -+ break; -+ } - - if (!ds->ops->port_setup_tc) - return -EOPNOTSUPP; diff --git a/target/linux/generic/backport-5.10/610-v5.13-31-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch b/target/linux/generic/backport-5.10/610-v5.13-31-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch deleted file mode 100644 index 3be60aee1d..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-31-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch +++ /dev/null @@ -1,68 +0,0 @@ -From: Felix Fietkau -Date: Wed, 24 Mar 2021 02:30:52 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: fix parsing packets in GDM - -When using DSA, set the special tag in GDM ingress control to allow the MAC -to parse packets properly earlier. This affects rx DMA source port reporting. - -Signed-off-by: Felix Fietkau -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - #include "mtk_eth_soc.h" - -@@ -1297,13 +1298,12 @@ static int mtk_poll_rx(struct napi_struc - break; - - /* find out which mac the packet come from. values start at 1 */ -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) || -+ (trxd.rxd4 & RX_DMA_SPECIAL_TAG)) - mac = 0; -- } else { -- mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & -- RX_DMA_FPORT_MASK; -- mac--; -- } -+ else -+ mac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & -+ RX_DMA_FPORT_MASK) - 1; - - if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || - !eth->netdev[mac])) -@@ -2275,6 +2275,9 @@ static void mtk_gdm_config(struct mtk_et - - val |= config; - -+ if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) -+ val |= MTK_GDMA_SPECIAL_TAG; -+ - mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); - } - /* Reset and enable PSE */ ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -81,6 +81,7 @@ - - /* GDM Exgress Control Register */ - #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) -+#define MTK_GDMA_SPECIAL_TAG BIT(24) - #define MTK_GDMA_ICS_EN BIT(22) - #define MTK_GDMA_TCS_EN BIT(21) - #define MTK_GDMA_UCS_EN BIT(20) -@@ -318,6 +319,7 @@ - #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ - #define RX_DMA_FPORT_SHIFT 19 - #define RX_DMA_FPORT_MASK 0x7 -+#define RX_DMA_SPECIAL_TAG BIT(22) - - /* PHY Indirect Access Control registers */ - #define MTK_PHY_IAC 0x10004 diff --git a/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch b/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch deleted file mode 100644 index 9378c3d422..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch +++ /dev/null @@ -1,1312 +0,0 @@ -From: Felix Fietkau -Date: Wed, 24 Mar 2021 02:30:53 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for - initializing the PPE - -The PPE (packet processing engine) is used to offload NAT/routed or even -bridged flows. This patch brings up the PPE and uses it to get a packet -hash. It also contains some functionality that will be used to bring up -flow offloading. - -Signed-off-by: Felix Fietkau -Signed-off-by: Pablo Neira Ayuso ---- - create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.c - create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.h - create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c - create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_regs.h - ---- a/drivers/net/ethernet/mediatek/Makefile -+++ b/drivers/net/ethernet/mediatek/Makefile -@@ -4,5 +4,5 @@ - # - - obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o --mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o -+mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o - obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2300,7 +2300,10 @@ static int mtk_open(struct net_device *d - - /* we run 2 netdevs on the same dma ring so we only bring it up once */ - if (!refcount_read(ð->dma_refcnt)) { -- int err = mtk_start_dma(eth); -+ u32 gdm_config = MTK_GDMA_TO_PDMA; -+ int err; -+ -+ err = mtk_start_dma(eth); - - if (err) - if (err) { -@@ -2308,7 +2311,10 @@ static int mtk_open(struct net_device *d - return err; - } - -- mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); -+ if (eth->soc->offload_version && mtk_ppe_start(ð->ppe) == 0) -+ gdm_config = MTK_GDMA_TO_PPE; -+ -+ mtk_gdm_config(eth, gdm_config); - - napi_enable(ð->tx_napi); - napi_enable(ð->rx_napi); -@@ -2375,6 +2381,9 @@ static int mtk_stop(struct net_device *d - - mtk_dma_free(eth); - -+ if (eth->soc->offload_version) -+ mtk_ppe_stop(ð->ppe); -+ - return 0; - } - -@@ -3103,6 +3112,13 @@ static int mtk_probe(struct platform_dev - goto err_free_dev; - } - -+ if (eth->soc->offload_version) { -+ err = mtk_ppe_init(ð->ppe, eth->dev, -+ eth->base + MTK_ETH_PPE_BASE, 2); -+ if (err) -+ goto err_free_dev; -+ } -+ - for (i = 0; i < MTK_MAX_DEVS; i++) { - if (!eth->netdev[i]) - continue; -@@ -3177,6 +3193,7 @@ static const struct mtk_soc_data mt7621_ - .hw_features = MTK_HW_FEATURES, - .required_clks = MT7621_CLKS_BITMAP, - .required_pctl = false, -+ .offload_version = 2, - }; - - static const struct mtk_soc_data mt7622_data = { -@@ -3185,6 +3202,7 @@ static const struct mtk_soc_data mt7622_ - .hw_features = MTK_HW_FEATURES, - .required_clks = MT7622_CLKS_BITMAP, - .required_pctl = false, -+ .offload_version = 2, - }; - - static const struct mtk_soc_data mt7623_data = { ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include "mtk_ppe.h" - - #define MTK_QDMA_PAGE_SIZE 2048 - #define MTK_MAX_RX_LENGTH 1536 -@@ -86,6 +87,7 @@ - #define MTK_GDMA_TCS_EN BIT(21) - #define MTK_GDMA_UCS_EN BIT(20) - #define MTK_GDMA_TO_PDMA 0x0 -+#define MTK_GDMA_TO_PPE 0x4444 - #define MTK_GDMA_DROP_ALL 0x7777 - - /* Unicast Filter MAC Address Register - Low */ -@@ -315,6 +317,12 @@ - #define RX_DMA_VID(_x) ((_x) & 0xfff) - - /* QDMA descriptor rxd4 */ -+#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0) -+#define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14) -+#define MTK_RXD4_SRC_PORT GENMASK(21, 19) -+#define MTK_RXD4_ALG GENMASK(31, 22) -+ -+/* QDMA descriptor rxd4 */ - #define RX_DMA_L4_VALID BIT(24) - #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */ - #define RX_DMA_FPORT_SHIFT 19 -@@ -820,6 +828,7 @@ struct mtk_soc_data { - u32 caps; - u32 required_clks; - bool required_pctl; -+ u8 offload_version; - netdev_features_t hw_features; - }; - -@@ -919,6 +928,8 @@ struct mtk_eth { - u32 tx_int_status_reg; - u32 rx_dma_l4_valid; - int ip_align; -+ -+ struct mtk_ppe ppe; - }; - - /* struct mtk_mac - the structure that holds the info about the MACs of the ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -0,0 +1,511 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (C) 2020 Felix Fietkau */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mtk_ppe.h" -+#include "mtk_ppe_regs.h" -+ -+static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val) -+{ -+ writel(val, ppe->base + reg); -+} -+ -+static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg) -+{ -+ return readl(ppe->base + reg); -+} -+ -+static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set) -+{ -+ u32 val; -+ -+ val = ppe_r32(ppe, reg); -+ val &= ~mask; -+ val |= set; -+ ppe_w32(ppe, reg, val); -+ -+ return val; -+} -+ -+static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val) -+{ -+ return ppe_m32(ppe, reg, 0, val); -+} -+ -+static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val) -+{ -+ return ppe_m32(ppe, reg, val, 0); -+} -+ -+static int mtk_ppe_wait_busy(struct mtk_ppe *ppe) -+{ -+ unsigned long timeout = jiffies + HZ; -+ -+ while (time_is_before_jiffies(timeout)) { -+ if (!(ppe_r32(ppe, MTK_PPE_GLO_CFG) & MTK_PPE_GLO_CFG_BUSY)) -+ return 0; -+ -+ usleep_range(10, 20); -+ } -+ -+ dev_err(ppe->dev, "PPE table busy"); -+ -+ return -ETIMEDOUT; -+} -+ -+static void mtk_ppe_cache_clear(struct mtk_ppe *ppe) -+{ -+ ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR); -+ ppe_clear(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR); -+} -+ -+static void mtk_ppe_cache_enable(struct mtk_ppe *ppe, bool enable) -+{ -+ mtk_ppe_cache_clear(ppe); -+ -+ ppe_m32(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_EN, -+ enable * MTK_PPE_CACHE_CTL_EN); -+} -+ -+static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e) -+{ -+ u32 hv1, hv2, hv3; -+ u32 hash; -+ -+ switch (FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, e->ib1)) { -+ case MTK_PPE_PKT_TYPE_BRIDGE: -+ hv1 = e->bridge.src_mac_lo; -+ hv1 ^= ((e->bridge.src_mac_hi & 0xffff) << 16); -+ hv2 = e->bridge.src_mac_hi >> 16; -+ hv2 ^= e->bridge.dest_mac_lo; -+ hv3 = e->bridge.dest_mac_hi; -+ break; -+ case MTK_PPE_PKT_TYPE_IPV4_ROUTE: -+ case MTK_PPE_PKT_TYPE_IPV4_HNAPT: -+ hv1 = e->ipv4.orig.ports; -+ hv2 = e->ipv4.orig.dest_ip; -+ hv3 = e->ipv4.orig.src_ip; -+ break; -+ case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T: -+ case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T: -+ hv1 = e->ipv6.src_ip[3] ^ e->ipv6.dest_ip[3]; -+ hv1 ^= e->ipv6.ports; -+ -+ hv2 = e->ipv6.src_ip[2] ^ e->ipv6.dest_ip[2]; -+ hv2 ^= e->ipv6.dest_ip[0]; -+ -+ hv3 = e->ipv6.src_ip[1] ^ e->ipv6.dest_ip[1]; -+ hv3 ^= e->ipv6.src_ip[0]; -+ break; -+ case MTK_PPE_PKT_TYPE_IPV4_DSLITE: -+ case MTK_PPE_PKT_TYPE_IPV6_6RD: -+ default: -+ WARN_ON_ONCE(1); -+ return MTK_PPE_HASH_MASK; -+ } -+ -+ hash = (hv1 & hv2) | ((~hv1) & hv3); -+ hash = (hash >> 24) | ((hash & 0xffffff) << 8); -+ hash ^= hv1 ^ hv2 ^ hv3; -+ hash ^= hash >> 16; -+ hash <<= 1; -+ hash &= MTK_PPE_ENTRIES - 1; -+ -+ return hash; -+} -+ -+static inline struct mtk_foe_mac_info * -+mtk_foe_entry_l2(struct mtk_foe_entry *entry) -+{ -+ int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); -+ -+ if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) -+ return &entry->ipv6.l2; -+ -+ return &entry->ipv4.l2; -+} -+ -+static inline u32 * -+mtk_foe_entry_ib2(struct mtk_foe_entry *entry) -+{ -+ int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); -+ -+ if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) -+ return &entry->ipv6.ib2; -+ -+ return &entry->ipv4.ib2; -+} -+ -+int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto, -+ u8 pse_port, u8 *src_mac, u8 *dest_mac) -+{ -+ struct mtk_foe_mac_info *l2; -+ u32 ports_pad, val; -+ -+ memset(entry, 0, sizeof(*entry)); -+ -+ val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) | -+ FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE, type) | -+ FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) | -+ MTK_FOE_IB1_BIND_TTL | -+ MTK_FOE_IB1_BIND_CACHE; -+ entry->ib1 = val; -+ -+ val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) | -+ FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0x1f) | -+ FIELD_PREP(MTK_FOE_IB2_DEST_PORT, pse_port); -+ -+ if (is_multicast_ether_addr(dest_mac)) -+ val |= MTK_FOE_IB2_MULTICAST; -+ -+ ports_pad = 0xa5a5a500 | (l4proto & 0xff); -+ if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE) -+ entry->ipv4.orig.ports = ports_pad; -+ if (type == MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T) -+ entry->ipv6.ports = ports_pad; -+ -+ if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) { -+ entry->ipv6.ib2 = val; -+ l2 = &entry->ipv6.l2; -+ } else { -+ entry->ipv4.ib2 = val; -+ l2 = &entry->ipv4.l2; -+ } -+ -+ l2->dest_mac_hi = get_unaligned_be32(dest_mac); -+ l2->dest_mac_lo = get_unaligned_be16(dest_mac + 4); -+ l2->src_mac_hi = get_unaligned_be32(src_mac); -+ l2->src_mac_lo = get_unaligned_be16(src_mac + 4); -+ -+ if (type >= MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T) -+ l2->etype = ETH_P_IPV6; -+ else -+ l2->etype = ETH_P_IP; -+ -+ return 0; -+} -+ -+int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port) -+{ -+ u32 *ib2 = mtk_foe_entry_ib2(entry); -+ u32 val; -+ -+ val = *ib2; -+ val &= ~MTK_FOE_IB2_DEST_PORT; -+ val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT, port); -+ *ib2 = val; -+ -+ return 0; -+} -+ -+int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool egress, -+ __be32 src_addr, __be16 src_port, -+ __be32 dest_addr, __be16 dest_port) -+{ -+ int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); -+ struct mtk_ipv4_tuple *t; -+ -+ switch (type) { -+ case MTK_PPE_PKT_TYPE_IPV4_HNAPT: -+ if (egress) { -+ t = &entry->ipv4.new; -+ break; -+ } -+ fallthrough; -+ case MTK_PPE_PKT_TYPE_IPV4_DSLITE: -+ case MTK_PPE_PKT_TYPE_IPV4_ROUTE: -+ t = &entry->ipv4.orig; -+ break; -+ case MTK_PPE_PKT_TYPE_IPV6_6RD: -+ entry->ipv6_6rd.tunnel_src_ip = be32_to_cpu(src_addr); -+ entry->ipv6_6rd.tunnel_dest_ip = be32_to_cpu(dest_addr); -+ return 0; -+ default: -+ WARN_ON_ONCE(1); -+ return -EINVAL; -+ } -+ -+ t->src_ip = be32_to_cpu(src_addr); -+ t->dest_ip = be32_to_cpu(dest_addr); -+ -+ if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE) -+ return 0; -+ -+ t->src_port = be16_to_cpu(src_port); -+ t->dest_port = be16_to_cpu(dest_port); -+ -+ return 0; -+} -+ -+int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry, -+ __be32 *src_addr, __be16 src_port, -+ __be32 *dest_addr, __be16 dest_port) -+{ -+ int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); -+ u32 *src, *dest; -+ int i; -+ -+ switch (type) { -+ case MTK_PPE_PKT_TYPE_IPV4_DSLITE: -+ src = entry->dslite.tunnel_src_ip; -+ dest = entry->dslite.tunnel_dest_ip; -+ break; -+ case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T: -+ case MTK_PPE_PKT_TYPE_IPV6_6RD: -+ entry->ipv6.src_port = be16_to_cpu(src_port); -+ entry->ipv6.dest_port = be16_to_cpu(dest_port); -+ fallthrough; -+ case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T: -+ src = entry->ipv6.src_ip; -+ dest = entry->ipv6.dest_ip; -+ break; -+ default: -+ WARN_ON_ONCE(1); -+ return -EINVAL; -+ }; -+ -+ for (i = 0; i < 4; i++) -+ src[i] = be32_to_cpu(src_addr[i]); -+ for (i = 0; i < 4; i++) -+ dest[i] = be32_to_cpu(dest_addr[i]); -+ -+ return 0; -+} -+ -+int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port) -+{ -+ struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry); -+ -+ l2->etype = BIT(port); -+ -+ if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER)) -+ entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1); -+ else -+ l2->etype |= BIT(8); -+ -+ entry->ib1 &= ~MTK_FOE_IB1_BIND_VLAN_TAG; -+ -+ return 0; -+} -+ -+int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid) -+{ -+ struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry); -+ -+ switch (FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, entry->ib1)) { -+ case 0: -+ entry->ib1 |= MTK_FOE_IB1_BIND_VLAN_TAG | -+ FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1); -+ l2->vlan1 = vid; -+ return 0; -+ case 1: -+ if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG)) { -+ l2->vlan1 = vid; -+ l2->etype |= BIT(8); -+ } else { -+ l2->vlan2 = vid; -+ entry->ib1 += FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1); -+ } -+ return 0; -+ default: -+ return -ENOSPC; -+ } -+} -+ -+int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid) -+{ -+ struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry); -+ -+ if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER) || -+ (entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG)) -+ l2->etype = ETH_P_PPP_SES; -+ -+ entry->ib1 |= MTK_FOE_IB1_BIND_PPPOE; -+ l2->pppoe_id = sid; -+ -+ return 0; -+} -+ -+static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry) -+{ -+ return !(entry->ib1 & MTK_FOE_IB1_STATIC) && -+ FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1) != MTK_FOE_STATE_BIND; -+} -+ -+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry, -+ u16 timestamp) -+{ -+ struct mtk_foe_entry *hwe; -+ u32 hash; -+ -+ timestamp &= MTK_FOE_IB1_BIND_TIMESTAMP; -+ entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP; -+ entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP, timestamp); -+ -+ hash = mtk_ppe_hash_entry(entry); -+ hwe = &ppe->foe_table[hash]; -+ if (!mtk_foe_entry_usable(hwe)) { -+ hwe++; -+ hash++; -+ -+ if (!mtk_foe_entry_usable(hwe)) -+ return -ENOSPC; -+ } -+ -+ memcpy(&hwe->data, &entry->data, sizeof(hwe->data)); -+ wmb(); -+ hwe->ib1 = entry->ib1; -+ -+ dma_wmb(); -+ -+ mtk_ppe_cache_clear(ppe); -+ -+ return hash; -+} -+ -+int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base, -+ int version) -+{ -+ struct mtk_foe_entry *foe; -+ -+ /* need to allocate a separate device, since it PPE DMA access is -+ * not coherent. -+ */ -+ ppe->base = base; -+ ppe->dev = dev; -+ ppe->version = version; -+ -+ foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe), -+ &ppe->foe_phys, GFP_KERNEL); -+ if (!foe) -+ return -ENOMEM; -+ -+ ppe->foe_table = foe; -+ -+ mtk_ppe_debugfs_init(ppe); -+ -+ return 0; -+} -+ -+static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe) -+{ -+ static const u8 skip[] = { 12, 25, 38, 51, 76, 89, 102 }; -+ int i, k; -+ -+ memset(ppe->foe_table, 0, MTK_PPE_ENTRIES * sizeof(ppe->foe_table)); -+ -+ if (!IS_ENABLED(CONFIG_SOC_MT7621)) -+ return; -+ -+ /* skip all entries that cross the 1024 byte boundary */ -+ for (i = 0; i < MTK_PPE_ENTRIES; i += 128) -+ for (k = 0; k < ARRAY_SIZE(skip); k++) -+ ppe->foe_table[i + skip[k]].ib1 |= MTK_FOE_IB1_STATIC; -+} -+ -+int mtk_ppe_start(struct mtk_ppe *ppe) -+{ -+ u32 val; -+ -+ mtk_ppe_init_foe_table(ppe); -+ ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys); -+ -+ val = MTK_PPE_TB_CFG_ENTRY_80B | -+ MTK_PPE_TB_CFG_AGE_NON_L4 | -+ MTK_PPE_TB_CFG_AGE_UNBIND | -+ MTK_PPE_TB_CFG_AGE_TCP | -+ MTK_PPE_TB_CFG_AGE_UDP | -+ MTK_PPE_TB_CFG_AGE_TCP_FIN | -+ FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS, -+ MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD) | -+ FIELD_PREP(MTK_PPE_TB_CFG_KEEPALIVE, -+ MTK_PPE_KEEPALIVE_DISABLE) | -+ FIELD_PREP(MTK_PPE_TB_CFG_HASH_MODE, 1) | -+ FIELD_PREP(MTK_PPE_TB_CFG_SCAN_MODE, -+ MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) | -+ FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM, -+ MTK_PPE_ENTRIES_SHIFT); -+ ppe_w32(ppe, MTK_PPE_TB_CFG, val); -+ -+ ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK, -+ MTK_PPE_IP_PROTO_CHK_IPV4 | MTK_PPE_IP_PROTO_CHK_IPV6); -+ -+ mtk_ppe_cache_enable(ppe, true); -+ -+ val = MTK_PPE_FLOW_CFG_IP4_TCP_FRAG | -+ MTK_PPE_FLOW_CFG_IP4_UDP_FRAG | -+ MTK_PPE_FLOW_CFG_IP6_3T_ROUTE | -+ MTK_PPE_FLOW_CFG_IP6_5T_ROUTE | -+ MTK_PPE_FLOW_CFG_IP6_6RD | -+ MTK_PPE_FLOW_CFG_IP4_NAT | -+ MTK_PPE_FLOW_CFG_IP4_NAPT | -+ MTK_PPE_FLOW_CFG_IP4_DSLITE | -+ MTK_PPE_FLOW_CFG_L2_BRIDGE | -+ MTK_PPE_FLOW_CFG_IP4_NAT_FRAG; -+ ppe_w32(ppe, MTK_PPE_FLOW_CFG, val); -+ -+ val = FIELD_PREP(MTK_PPE_UNBIND_AGE_MIN_PACKETS, 1000) | -+ FIELD_PREP(MTK_PPE_UNBIND_AGE_DELTA, 3); -+ ppe_w32(ppe, MTK_PPE_UNBIND_AGE, val); -+ -+ val = FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_UDP, 12) | -+ FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_NON_L4, 1); -+ ppe_w32(ppe, MTK_PPE_BIND_AGE0, val); -+ -+ val = FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP_FIN, 1) | -+ FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP, 7); -+ ppe_w32(ppe, MTK_PPE_BIND_AGE1, val); -+ -+ val = MTK_PPE_BIND_LIMIT0_QUARTER | MTK_PPE_BIND_LIMIT0_HALF; -+ ppe_w32(ppe, MTK_PPE_BIND_LIMIT0, val); -+ -+ val = MTK_PPE_BIND_LIMIT1_FULL | -+ FIELD_PREP(MTK_PPE_BIND_LIMIT1_NON_L4, 1); -+ ppe_w32(ppe, MTK_PPE_BIND_LIMIT1, val); -+ -+ val = FIELD_PREP(MTK_PPE_BIND_RATE_BIND, 30) | -+ FIELD_PREP(MTK_PPE_BIND_RATE_PREBIND, 1); -+ ppe_w32(ppe, MTK_PPE_BIND_RATE, val); -+ -+ /* enable PPE */ -+ val = MTK_PPE_GLO_CFG_EN | -+ MTK_PPE_GLO_CFG_IP4_L4_CS_DROP | -+ MTK_PPE_GLO_CFG_IP4_CS_DROP | -+ MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE; -+ ppe_w32(ppe, MTK_PPE_GLO_CFG, val); -+ -+ ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0); -+ -+ return 0; -+} -+ -+int mtk_ppe_stop(struct mtk_ppe *ppe) -+{ -+ u32 val; -+ int i; -+ -+ for (i = 0; i < MTK_PPE_ENTRIES; i++) -+ ppe->foe_table[i].ib1 = FIELD_PREP(MTK_FOE_IB1_STATE, -+ MTK_FOE_STATE_INVALID); -+ -+ mtk_ppe_cache_enable(ppe, false); -+ -+ /* disable offload engine */ -+ ppe_clear(ppe, MTK_PPE_GLO_CFG, MTK_PPE_GLO_CFG_EN); -+ ppe_w32(ppe, MTK_PPE_FLOW_CFG, 0); -+ -+ /* disable aging */ -+ val = MTK_PPE_TB_CFG_AGE_NON_L4 | -+ MTK_PPE_TB_CFG_AGE_UNBIND | -+ MTK_PPE_TB_CFG_AGE_TCP | -+ MTK_PPE_TB_CFG_AGE_UDP | -+ MTK_PPE_TB_CFG_AGE_TCP_FIN; -+ ppe_clear(ppe, MTK_PPE_TB_CFG, val); -+ -+ return mtk_ppe_wait_busy(ppe); -+} ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -0,0 +1,287 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (C) 2020 Felix Fietkau */ -+ -+#ifndef __MTK_PPE_H -+#define __MTK_PPE_H -+ -+#include -+#include -+ -+#define MTK_ETH_PPE_BASE 0xc00 -+ -+#define MTK_PPE_ENTRIES_SHIFT 3 -+#define MTK_PPE_ENTRIES (1024 << MTK_PPE_ENTRIES_SHIFT) -+#define MTK_PPE_HASH_MASK (MTK_PPE_ENTRIES - 1) -+ -+#define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) -+#define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) -+#define MTK_FOE_IB1_UNBIND_PREBIND BIT(24) -+ -+#define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) -+#define MTK_FOE_IB1_BIND_KEEPALIVE BIT(15) -+#define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(18, 16) -+#define MTK_FOE_IB1_BIND_PPPOE BIT(19) -+#define MTK_FOE_IB1_BIND_VLAN_TAG BIT(20) -+#define MTK_FOE_IB1_BIND_PKT_SAMPLE BIT(21) -+#define MTK_FOE_IB1_BIND_CACHE BIT(22) -+#define MTK_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) -+#define MTK_FOE_IB1_BIND_TTL BIT(24) -+ -+#define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 25) -+#define MTK_FOE_IB1_STATE GENMASK(29, 28) -+#define MTK_FOE_IB1_UDP BIT(30) -+#define MTK_FOE_IB1_STATIC BIT(31) -+ -+enum { -+ MTK_PPE_PKT_TYPE_IPV4_HNAPT = 0, -+ MTK_PPE_PKT_TYPE_IPV4_ROUTE = 1, -+ MTK_PPE_PKT_TYPE_BRIDGE = 2, -+ MTK_PPE_PKT_TYPE_IPV4_DSLITE = 3, -+ MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T = 4, -+ MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T = 5, -+ MTK_PPE_PKT_TYPE_IPV6_6RD = 7, -+}; -+ -+#define MTK_FOE_IB2_QID GENMASK(3, 0) -+#define MTK_FOE_IB2_PSE_QOS BIT(4) -+#define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5) -+#define MTK_FOE_IB2_MULTICAST BIT(8) -+ -+#define MTK_FOE_IB2_WHNAT_QID2 GENMASK(13, 12) -+#define MTK_FOE_IB2_WHNAT_DEVIDX BIT(16) -+#define MTK_FOE_IB2_WHNAT_NAT BIT(17) -+ -+#define MTK_FOE_IB2_PORT_MG GENMASK(17, 12) -+ -+#define MTK_FOE_IB2_PORT_AG GENMASK(23, 18) -+ -+#define MTK_FOE_IB2_DSCP GENMASK(31, 24) -+ -+#define MTK_FOE_VLAN2_WHNAT_BSS GEMMASK(5, 0) -+#define MTK_FOE_VLAN2_WHNAT_WCID GENMASK(13, 6) -+#define MTK_FOE_VLAN2_WHNAT_RING GENMASK(15, 14) -+ -+enum { -+ MTK_FOE_STATE_INVALID, -+ MTK_FOE_STATE_UNBIND, -+ MTK_FOE_STATE_BIND, -+ MTK_FOE_STATE_FIN -+}; -+ -+struct mtk_foe_mac_info { -+ u16 vlan1; -+ u16 etype; -+ -+ u32 dest_mac_hi; -+ -+ u16 vlan2; -+ u16 dest_mac_lo; -+ -+ u32 src_mac_hi; -+ -+ u16 pppoe_id; -+ u16 src_mac_lo; -+}; -+ -+struct mtk_foe_bridge { -+ u32 dest_mac_hi; -+ -+ u16 src_mac_lo; -+ u16 dest_mac_lo; -+ -+ u32 src_mac_hi; -+ -+ u32 ib2; -+ -+ u32 _rsv[5]; -+ -+ u32 udf_tsid; -+ struct mtk_foe_mac_info l2; -+}; -+ -+struct mtk_ipv4_tuple { -+ u32 src_ip; -+ u32 dest_ip; -+ union { -+ struct { -+ u16 dest_port; -+ u16 src_port; -+ }; -+ struct { -+ u8 protocol; -+ u8 _pad[3]; /* fill with 0xa5a5a5 */ -+ }; -+ u32 ports; -+ }; -+}; -+ -+struct mtk_foe_ipv4 { -+ struct mtk_ipv4_tuple orig; -+ -+ u32 ib2; -+ -+ struct mtk_ipv4_tuple new; -+ -+ u16 timestamp; -+ u16 _rsv0[3]; -+ -+ u32 udf_tsid; -+ -+ struct mtk_foe_mac_info l2; -+}; -+ -+struct mtk_foe_ipv4_dslite { -+ struct mtk_ipv4_tuple ip4; -+ -+ u32 tunnel_src_ip[4]; -+ u32 tunnel_dest_ip[4]; -+ -+ u8 flow_label[3]; -+ u8 priority; -+ -+ u32 udf_tsid; -+ -+ u32 ib2; -+ -+ struct mtk_foe_mac_info l2; -+}; -+ -+struct mtk_foe_ipv6 { -+ u32 src_ip[4]; -+ u32 dest_ip[4]; -+ -+ union { -+ struct { -+ u8 protocol; -+ u8 _pad[3]; /* fill with 0xa5a5a5 */ -+ }; /* 3-tuple */ -+ struct { -+ u16 dest_port; -+ u16 src_port; -+ }; /* 5-tuple */ -+ u32 ports; -+ }; -+ -+ u32 _rsv[3]; -+ -+ u32 udf; -+ -+ u32 ib2; -+ struct mtk_foe_mac_info l2; -+}; -+ -+struct mtk_foe_ipv6_6rd { -+ u32 src_ip[4]; -+ u32 dest_ip[4]; -+ u16 dest_port; -+ u16 src_port; -+ -+ u32 tunnel_src_ip; -+ u32 tunnel_dest_ip; -+ -+ u16 hdr_csum; -+ u8 dscp; -+ u8 ttl; -+ -+ u8 flag; -+ u8 pad; -+ u8 per_flow_6rd_id; -+ u8 pad2; -+ -+ u32 ib2; -+ struct mtk_foe_mac_info l2; -+}; -+ -+struct mtk_foe_entry { -+ u32 ib1; -+ -+ union { -+ struct mtk_foe_bridge bridge; -+ struct mtk_foe_ipv4 ipv4; -+ struct mtk_foe_ipv4_dslite dslite; -+ struct mtk_foe_ipv6 ipv6; -+ struct mtk_foe_ipv6_6rd ipv6_6rd; -+ u32 data[19]; -+ }; -+}; -+ -+enum { -+ MTK_PPE_CPU_REASON_TTL_EXCEEDED = 0x02, -+ MTK_PPE_CPU_REASON_OPTION_HEADER = 0x03, -+ MTK_PPE_CPU_REASON_NO_FLOW = 0x07, -+ MTK_PPE_CPU_REASON_IPV4_FRAG = 0x08, -+ MTK_PPE_CPU_REASON_IPV4_DSLITE_FRAG = 0x09, -+ MTK_PPE_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a, -+ MTK_PPE_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b, -+ MTK_PPE_CPU_REASON_TCP_FIN_SYN_RST = 0x0c, -+ MTK_PPE_CPU_REASON_UN_HIT = 0x0d, -+ MTK_PPE_CPU_REASON_HIT_UNBIND = 0x0e, -+ MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f, -+ MTK_PPE_CPU_REASON_HIT_BIND_TCP_FIN = 0x10, -+ MTK_PPE_CPU_REASON_HIT_TTL_1 = 0x11, -+ MTK_PPE_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12, -+ MTK_PPE_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13, -+ MTK_PPE_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14, -+ MTK_PPE_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15, -+ MTK_PPE_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16, -+ MTK_PPE_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17, -+ MTK_PPE_CPU_REASON_MULTICAST_TO_CPU = 0x18, -+ MTK_PPE_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19, -+ MTK_PPE_CPU_REASON_HIT_PRE_BIND = 0x1a, -+ MTK_PPE_CPU_REASON_PACKET_SAMPLING = 0x1b, -+ MTK_PPE_CPU_REASON_EXCEED_MTU = 0x1c, -+ MTK_PPE_CPU_REASON_PPE_BYPASS = 0x1e, -+ MTK_PPE_CPU_REASON_INVALID = 0x1f, -+}; -+ -+struct mtk_ppe { -+ struct device *dev; -+ void __iomem *base; -+ int version; -+ -+ struct mtk_foe_entry *foe_table; -+ dma_addr_t foe_phys; -+ -+ void *acct_table; -+}; -+ -+int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base, -+ int version); -+int mtk_ppe_start(struct mtk_ppe *ppe); -+int mtk_ppe_stop(struct mtk_ppe *ppe); -+ -+static inline void -+mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash) -+{ -+ ppe->foe_table[hash].ib1 = 0; -+ dma_wmb(); -+} -+ -+static inline int -+mtk_foe_entry_timestamp(struct mtk_ppe *ppe, u16 hash) -+{ -+ u32 ib1 = READ_ONCE(ppe->foe_table[hash].ib1); -+ -+ if (FIELD_GET(MTK_FOE_IB1_STATE, ib1) != MTK_FOE_STATE_BIND) -+ return -1; -+ -+ return FIELD_GET(MTK_FOE_IB1_BIND_TIMESTAMP, ib1); -+} -+ -+int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto, -+ u8 pse_port, u8 *src_mac, u8 *dest_mac); -+int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port); -+int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool orig, -+ __be32 src_addr, __be16 src_port, -+ __be32 dest_addr, __be16 dest_port); -+int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry, -+ __be32 *src_addr, __be16 src_port, -+ __be32 *dest_addr, __be16 dest_port); -+int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port); -+int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid); -+int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid); -+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry, -+ u16 timestamp); -+int mtk_ppe_debugfs_init(struct mtk_ppe *ppe); -+ -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c -@@ -0,0 +1,217 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (C) 2020 Felix Fietkau */ -+ -+#include -+#include -+#include "mtk_eth_soc.h" -+ -+struct mtk_flow_addr_info -+{ -+ void *src, *dest; -+ u16 *src_port, *dest_port; -+ bool ipv6; -+}; -+ -+static const char *mtk_foe_entry_state_str(int state) -+{ -+ static const char * const state_str[] = { -+ [MTK_FOE_STATE_INVALID] = "INV", -+ [MTK_FOE_STATE_UNBIND] = "UNB", -+ [MTK_FOE_STATE_BIND] = "BND", -+ [MTK_FOE_STATE_FIN] = "FIN", -+ }; -+ -+ if (state >= ARRAY_SIZE(state_str) || !state_str[state]) -+ return "UNK"; -+ -+ return state_str[state]; -+} -+ -+static const char *mtk_foe_pkt_type_str(int type) -+{ -+ static const char * const type_str[] = { -+ [MTK_PPE_PKT_TYPE_IPV4_HNAPT] = "IPv4 5T", -+ [MTK_PPE_PKT_TYPE_IPV4_ROUTE] = "IPv4 3T", -+ [MTK_PPE_PKT_TYPE_BRIDGE] = "L2", -+ [MTK_PPE_PKT_TYPE_IPV4_DSLITE] = "DS-LITE", -+ [MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T] = "IPv6 3T", -+ [MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T] = "IPv6 5T", -+ [MTK_PPE_PKT_TYPE_IPV6_6RD] = "6RD", -+ }; -+ -+ if (type >= ARRAY_SIZE(type_str) || !type_str[type]) -+ return "UNKNOWN"; -+ -+ return type_str[type]; -+} -+ -+static void -+mtk_print_addr(struct seq_file *m, u32 *addr, bool ipv6) -+{ -+ u32 n_addr[4]; -+ int i; -+ -+ if (!ipv6) { -+ seq_printf(m, "%pI4h", addr); -+ return; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(n_addr); i++) -+ n_addr[i] = htonl(addr[i]); -+ seq_printf(m, "%pI6", n_addr); -+} -+ -+static void -+mtk_print_addr_info(struct seq_file *m, struct mtk_flow_addr_info *ai) -+{ -+ mtk_print_addr(m, ai->src, ai->ipv6); -+ if (ai->src_port) -+ seq_printf(m, ":%d", *ai->src_port); -+ seq_printf(m, "->"); -+ mtk_print_addr(m, ai->dest, ai->ipv6); -+ if (ai->dest_port) -+ seq_printf(m, ":%d", *ai->dest_port); -+} -+ -+static int -+mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private, bool bind) -+{ -+ struct mtk_ppe *ppe = m->private; -+ int i, count; -+ -+ for (i = 0, count = 0; i < MTK_PPE_ENTRIES; i++) { -+ struct mtk_foe_entry *entry = &ppe->foe_table[i]; -+ struct mtk_foe_mac_info *l2; -+ struct mtk_flow_addr_info ai = {}; -+ unsigned char h_source[ETH_ALEN]; -+ unsigned char h_dest[ETH_ALEN]; -+ int type, state; -+ u32 ib2; -+ -+ -+ state = FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1); -+ if (!state) -+ continue; -+ -+ if (bind && state != MTK_FOE_STATE_BIND) -+ continue; -+ -+ type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); -+ seq_printf(m, "%05x %s %7s", i, -+ mtk_foe_entry_state_str(state), -+ mtk_foe_pkt_type_str(type)); -+ -+ switch (type) { -+ case MTK_PPE_PKT_TYPE_IPV4_HNAPT: -+ case MTK_PPE_PKT_TYPE_IPV4_DSLITE: -+ ai.src_port = &entry->ipv4.orig.src_port; -+ ai.dest_port = &entry->ipv4.orig.dest_port; -+ fallthrough; -+ case MTK_PPE_PKT_TYPE_IPV4_ROUTE: -+ ai.src = &entry->ipv4.orig.src_ip; -+ ai.dest = &entry->ipv4.orig.dest_ip; -+ break; -+ case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T: -+ ai.src_port = &entry->ipv6.src_port; -+ ai.dest_port = &entry->ipv6.dest_port; -+ fallthrough; -+ case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T: -+ case MTK_PPE_PKT_TYPE_IPV6_6RD: -+ ai.src = &entry->ipv6.src_ip; -+ ai.dest = &entry->ipv6.dest_ip; -+ ai.ipv6 = true; -+ break; -+ } -+ -+ seq_printf(m, " orig="); -+ mtk_print_addr_info(m, &ai); -+ -+ switch (type) { -+ case MTK_PPE_PKT_TYPE_IPV4_HNAPT: -+ case MTK_PPE_PKT_TYPE_IPV4_DSLITE: -+ ai.src_port = &entry->ipv4.new.src_port; -+ ai.dest_port = &entry->ipv4.new.dest_port; -+ fallthrough; -+ case MTK_PPE_PKT_TYPE_IPV4_ROUTE: -+ ai.src = &entry->ipv4.new.src_ip; -+ ai.dest = &entry->ipv4.new.dest_ip; -+ seq_printf(m, " new="); -+ mtk_print_addr_info(m, &ai); -+ break; -+ } -+ -+ if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) { -+ l2 = &entry->ipv6.l2; -+ ib2 = entry->ipv6.ib2; -+ } else { -+ l2 = &entry->ipv4.l2; -+ ib2 = entry->ipv4.ib2; -+ } -+ -+ *((__be32 *)h_source) = htonl(l2->src_mac_hi); -+ *((__be16 *)&h_source[4]) = htons(l2->src_mac_lo); -+ *((__be32 *)h_dest) = htonl(l2->dest_mac_hi); -+ *((__be16 *)&h_dest[4]) = htons(l2->dest_mac_lo); -+ -+ seq_printf(m, " eth=%pM->%pM etype=%04x" -+ " vlan=%d,%d ib1=%08x ib2=%08x\n", -+ h_source, h_dest, ntohs(l2->etype), -+ l2->vlan1, l2->vlan2, entry->ib1, ib2); -+ } -+ -+ return 0; -+} -+ -+static int -+mtk_ppe_debugfs_foe_show_all(struct seq_file *m, void *private) -+{ -+ return mtk_ppe_debugfs_foe_show(m, private, false); -+} -+ -+static int -+mtk_ppe_debugfs_foe_show_bind(struct seq_file *m, void *private) -+{ -+ return mtk_ppe_debugfs_foe_show(m, private, true); -+} -+ -+static int -+mtk_ppe_debugfs_foe_open_all(struct inode *inode, struct file *file) -+{ -+ return single_open(file, mtk_ppe_debugfs_foe_show_all, -+ inode->i_private); -+} -+ -+static int -+mtk_ppe_debugfs_foe_open_bind(struct inode *inode, struct file *file) -+{ -+ return single_open(file, mtk_ppe_debugfs_foe_show_bind, -+ inode->i_private); -+} -+ -+int mtk_ppe_debugfs_init(struct mtk_ppe *ppe) -+{ -+ static const struct file_operations fops_all = { -+ .open = mtk_ppe_debugfs_foe_open_all, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+ }; -+ -+ static const struct file_operations fops_bind = { -+ .open = mtk_ppe_debugfs_foe_open_bind, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+ }; -+ -+ struct dentry *root; -+ -+ root = debugfs_create_dir("mtk_ppe", NULL); -+ if (!root) -+ return -ENOMEM; -+ -+ debugfs_create_file("entries", S_IRUGO, root, ppe, &fops_all); -+ debugfs_create_file("bind", S_IRUGO, root, ppe, &fops_bind); -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h -@@ -0,0 +1,144 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (C) 2020 Felix Fietkau */ -+ -+#ifndef __MTK_PPE_REGS_H -+#define __MTK_PPE_REGS_H -+ -+#define MTK_PPE_GLO_CFG 0x200 -+#define MTK_PPE_GLO_CFG_EN BIT(0) -+#define MTK_PPE_GLO_CFG_TSID_EN BIT(1) -+#define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2) -+#define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3) -+#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4) -+#define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5) -+#define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6) -+#define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7) -+#define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8) -+#define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE BIT(9) -+#define MTK_PPE_GLO_CFG_UDP_LITE_EN BIT(10) -+#define MTK_PPE_GLO_CFG_UDP_LEN_DROP BIT(11) -+#define MTK_PPE_GLO_CFG_MCAST_ENTRIES GNEMASK(13, 12) -+#define MTK_PPE_GLO_CFG_BUSY BIT(31) -+ -+#define MTK_PPE_FLOW_CFG 0x204 -+#define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG BIT(6) -+#define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG BIT(7) -+#define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE BIT(8) -+#define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE BIT(9) -+#define MTK_PPE_FLOW_CFG_IP6_6RD BIT(10) -+#define MTK_PPE_FLOW_CFG_IP4_NAT BIT(12) -+#define MTK_PPE_FLOW_CFG_IP4_NAPT BIT(13) -+#define MTK_PPE_FLOW_CFG_IP4_DSLITE BIT(14) -+#define MTK_PPE_FLOW_CFG_L2_BRIDGE BIT(15) -+#define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST BIT(16) -+#define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG BIT(17) -+#define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL BIT(18) -+#define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY BIT(19) -+#define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY BIT(20) -+ -+#define MTK_PPE_IP_PROTO_CHK 0x208 -+#define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0) -+#define MTK_PPE_IP_PROTO_CHK_IPV6 GENMASK(31, 16) -+ -+#define MTK_PPE_TB_CFG 0x21c -+#define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0) -+#define MTK_PPE_TB_CFG_ENTRY_80B BIT(3) -+#define MTK_PPE_TB_CFG_SEARCH_MISS GENMASK(5, 4) -+#define MTK_PPE_TB_CFG_AGE_PREBIND BIT(6) -+#define MTK_PPE_TB_CFG_AGE_NON_L4 BIT(7) -+#define MTK_PPE_TB_CFG_AGE_UNBIND BIT(8) -+#define MTK_PPE_TB_CFG_AGE_TCP BIT(9) -+#define MTK_PPE_TB_CFG_AGE_UDP BIT(10) -+#define MTK_PPE_TB_CFG_AGE_TCP_FIN BIT(11) -+#define MTK_PPE_TB_CFG_KEEPALIVE GENMASK(13, 12) -+#define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14) -+#define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16) -+#define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18) -+ -+enum { -+ MTK_PPE_SCAN_MODE_DISABLED, -+ MTK_PPE_SCAN_MODE_CHECK_AGE, -+ MTK_PPE_SCAN_MODE_KEEPALIVE_AGE, -+}; -+ -+enum { -+ MTK_PPE_KEEPALIVE_DISABLE, -+ MTK_PPE_KEEPALIVE_UNICAST_CPU, -+ MTK_PPE_KEEPALIVE_DUP_CPU = 3, -+}; -+ -+enum { -+ MTK_PPE_SEARCH_MISS_ACTION_DROP, -+ MTK_PPE_SEARCH_MISS_ACTION_FORWARD = 2, -+ MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD = 3, -+}; -+ -+#define MTK_PPE_TB_BASE 0x220 -+ -+#define MTK_PPE_TB_USED 0x224 -+#define MTK_PPE_TB_USED_NUM GENMASK(13, 0) -+ -+#define MTK_PPE_BIND_RATE 0x228 -+#define MTK_PPE_BIND_RATE_BIND GENMASK(15, 0) -+#define MTK_PPE_BIND_RATE_PREBIND GENMASK(31, 16) -+ -+#define MTK_PPE_BIND_LIMIT0 0x22c -+#define MTK_PPE_BIND_LIMIT0_QUARTER GENMASK(13, 0) -+#define MTK_PPE_BIND_LIMIT0_HALF GENMASK(29, 16) -+ -+#define MTK_PPE_BIND_LIMIT1 0x230 -+#define MTK_PPE_BIND_LIMIT1_FULL GENMASK(13, 0) -+#define MTK_PPE_BIND_LIMIT1_NON_L4 GENMASK(23, 16) -+ -+#define MTK_PPE_KEEPALIVE 0x234 -+#define MTK_PPE_KEEPALIVE_TIME GENMASK(15, 0) -+#define MTK_PPE_KEEPALIVE_TIME_TCP GENMASK(23, 16) -+#define MTK_PPE_KEEPALIVE_TIME_UDP GENMASK(31, 24) -+ -+#define MTK_PPE_UNBIND_AGE 0x238 -+#define MTK_PPE_UNBIND_AGE_MIN_PACKETS GENMASK(31, 16) -+#define MTK_PPE_UNBIND_AGE_DELTA GENMASK(7, 0) -+ -+#define MTK_PPE_BIND_AGE0 0x23c -+#define MTK_PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16) -+#define MTK_PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0) -+ -+#define MTK_PPE_BIND_AGE1 0x240 -+#define MTK_PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16) -+#define MTK_PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0) -+ -+#define MTK_PPE_HASH_SEED 0x244 -+ -+#define MTK_PPE_DEFAULT_CPU_PORT 0x248 -+#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4)) -+ -+#define MTK_PPE_MTU_DROP 0x308 -+ -+#define MTK_PPE_VLAN_MTU0 0x30c -+#define MTK_PPE_VLAN_MTU0_NONE GENMASK(13, 0) -+#define MTK_PPE_VLAN_MTU0_1TAG GENMASK(29, 16) -+ -+#define MTK_PPE_VLAN_MTU1 0x310 -+#define MTK_PPE_VLAN_MTU1_2TAG GENMASK(13, 0) -+#define MTK_PPE_VLAN_MTU1_3TAG GENMASK(29, 16) -+ -+#define MTK_PPE_VPM_TPID 0x318 -+ -+#define MTK_PPE_CACHE_CTL 0x320 -+#define MTK_PPE_CACHE_CTL_EN BIT(0) -+#define MTK_PPE_CACHE_CTL_LOCK_CLR BIT(4) -+#define MTK_PPE_CACHE_CTL_REQ BIT(8) -+#define MTK_PPE_CACHE_CTL_CLEAR BIT(9) -+#define MTK_PPE_CACHE_CTL_CMD GENMASK(13, 12) -+ -+#define MTK_PPE_MIB_CFG 0x334 -+#define MTK_PPE_MIB_CFG_EN BIT(0) -+#define MTK_PPE_MIB_CFG_RD_CLR BIT(1) -+ -+#define MTK_PPE_MIB_TB_BASE 0x338 -+ -+#define MTK_PPE_MIB_CACHE_CTL 0x350 -+#define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) -+#define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2) -+ -+#endif diff --git a/target/linux/generic/backport-5.10/610-v5.13-33-net-ethernet-mtk_eth_soc-add-flow-offloading-support.patch b/target/linux/generic/backport-5.10/610-v5.13-33-net-ethernet-mtk_eth_soc-add-flow-offloading-support.patch deleted file mode 100644 index b43417db46..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-33-net-ethernet-mtk_eth_soc-add-flow-offloading-support.patch +++ /dev/null @@ -1,568 +0,0 @@ -From: Felix Fietkau -Date: Wed, 24 Mar 2021 02:30:54 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: add flow offloading support - -This adds support for offloading IPv4 routed flows, including SNAT/DNAT, -one VLAN, PPPoE and DSA. - -Signed-off-by: Felix Fietkau -Signed-off-by: Pablo Neira Ayuso ---- - create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_offload.c - ---- a/drivers/net/ethernet/mediatek/Makefile -+++ b/drivers/net/ethernet/mediatek/Makefile -@@ -4,5 +4,5 @@ - # - - obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o --mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o -+mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o - obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2859,6 +2859,7 @@ static const struct net_device_ops mtk_n - #ifdef CONFIG_NET_POLL_CONTROLLER - .ndo_poll_controller = mtk_poll_controller, - #endif -+ .ndo_setup_tc = mtk_eth_setup_tc, - }; - - static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) -@@ -3117,6 +3118,10 @@ static int mtk_probe(struct platform_dev - eth->base + MTK_ETH_PPE_BASE, 2); - if (err) - goto err_free_dev; -+ -+ err = mtk_eth_offload_init(eth); -+ if (err) -+ goto err_free_dev; - } - - for (i = 0; i < MTK_MAX_DEVS; i++) { ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include "mtk_ppe.h" - - #define MTK_QDMA_PAGE_SIZE 2048 -@@ -40,7 +41,8 @@ - NETIF_F_HW_VLAN_CTAG_RX | \ - NETIF_F_SG | NETIF_F_TSO | \ - NETIF_F_TSO6 | \ -- NETIF_F_IPV6_CSUM) -+ NETIF_F_IPV6_CSUM |\ -+ NETIF_F_HW_TC) - #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM) - #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1)) - -@@ -930,6 +932,7 @@ struct mtk_eth { - int ip_align; - - struct mtk_ppe ppe; -+ struct rhashtable flow_table; - }; - - /* struct mtk_mac - the structure that holds the info about the MACs of the -@@ -974,4 +977,9 @@ int mtk_gmac_sgmii_path_setup(struct mtk - int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); - int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); - -+int mtk_eth_offload_init(struct mtk_eth *eth); -+int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, -+ void *type_data); -+ -+ - #endif /* MTK_ETH_H */ ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -0,0 +1,485 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2020 Felix Fietkau -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mtk_eth_soc.h" -+ -+struct mtk_flow_data { -+ struct ethhdr eth; -+ -+ union { -+ struct { -+ __be32 src_addr; -+ __be32 dst_addr; -+ } v4; -+ }; -+ -+ __be16 src_port; -+ __be16 dst_port; -+ -+ struct { -+ u16 id; -+ __be16 proto; -+ u8 num; -+ } vlan; -+ struct { -+ u16 sid; -+ u8 num; -+ } pppoe; -+}; -+ -+struct mtk_flow_entry { -+ struct rhash_head node; -+ unsigned long cookie; -+ u16 hash; -+}; -+ -+static const struct rhashtable_params mtk_flow_ht_params = { -+ .head_offset = offsetof(struct mtk_flow_entry, node), -+ .head_offset = offsetof(struct mtk_flow_entry, cookie), -+ .key_len = sizeof(unsigned long), -+ .automatic_shrinking = true, -+}; -+ -+static u32 -+mtk_eth_timestamp(struct mtk_eth *eth) -+{ -+ return mtk_r32(eth, 0x0010) & MTK_FOE_IB1_BIND_TIMESTAMP; -+} -+ -+static int -+mtk_flow_set_ipv4_addr(struct mtk_foe_entry *foe, struct mtk_flow_data *data, -+ bool egress) -+{ -+ return mtk_foe_entry_set_ipv4_tuple(foe, egress, -+ data->v4.src_addr, data->src_port, -+ data->v4.dst_addr, data->dst_port); -+} -+ -+static void -+mtk_flow_offload_mangle_eth(const struct flow_action_entry *act, void *eth) -+{ -+ void *dest = eth + act->mangle.offset; -+ const void *src = &act->mangle.val; -+ -+ if (act->mangle.offset > 8) -+ return; -+ -+ if (act->mangle.mask == 0xffff) { -+ src += 2; -+ dest += 2; -+ } -+ -+ memcpy(dest, src, act->mangle.mask ? 2 : 4); -+} -+ -+ -+static int -+mtk_flow_mangle_ports(const struct flow_action_entry *act, -+ struct mtk_flow_data *data) -+{ -+ u32 val = ntohl(act->mangle.val); -+ -+ switch (act->mangle.offset) { -+ case 0: -+ if (act->mangle.mask == ~htonl(0xffff)) -+ data->dst_port = cpu_to_be16(val); -+ else -+ data->src_port = cpu_to_be16(val >> 16); -+ break; -+ case 2: -+ data->dst_port = cpu_to_be16(val); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int -+mtk_flow_mangle_ipv4(const struct flow_action_entry *act, -+ struct mtk_flow_data *data) -+{ -+ __be32 *dest; -+ -+ switch (act->mangle.offset) { -+ case offsetof(struct iphdr, saddr): -+ dest = &data->v4.src_addr; -+ break; -+ case offsetof(struct iphdr, daddr): -+ dest = &data->v4.dst_addr; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ memcpy(dest, &act->mangle.val, sizeof(u32)); -+ -+ return 0; -+} -+ -+static int -+mtk_flow_get_dsa_port(struct net_device **dev) -+{ -+#if IS_ENABLED(CONFIG_NET_DSA) -+ struct dsa_port *dp; -+ -+ dp = dsa_port_from_netdev(*dev); -+ if (IS_ERR(dp)) -+ return -ENODEV; -+ -+ if (dp->cpu_dp->tag_ops->proto != DSA_TAG_PROTO_MTK) -+ return -ENODEV; -+ -+ *dev = dp->cpu_dp->master; -+ -+ return dp->index; -+#else -+ return -ENODEV; -+#endif -+} -+ -+static int -+mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, -+ struct net_device *dev) -+{ -+ int pse_port, dsa_port; -+ -+ dsa_port = mtk_flow_get_dsa_port(&dev); -+ if (dsa_port >= 0) -+ mtk_foe_entry_set_dsa(foe, dsa_port); -+ -+ if (dev == eth->netdev[0]) -+ pse_port = 1; -+ else if (dev == eth->netdev[1]) -+ pse_port = 2; -+ else -+ return -EOPNOTSUPP; -+ -+ mtk_foe_entry_set_pse_port(foe, pse_port); -+ -+ return 0; -+} -+ -+static int -+mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f) -+{ -+ struct flow_rule *rule = flow_cls_offload_flow_rule(f); -+ struct flow_action_entry *act; -+ struct mtk_flow_data data = {}; -+ struct mtk_foe_entry foe; -+ struct net_device *odev = NULL; -+ struct mtk_flow_entry *entry; -+ int offload_type = 0; -+ u16 addr_type = 0; -+ u32 timestamp; -+ u8 l4proto = 0; -+ int err = 0; -+ int hash; -+ int i; -+ -+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META)) { -+ struct flow_match_meta match; -+ -+ flow_rule_match_meta(rule, &match); -+ } else { -+ return -EOPNOTSUPP; -+ } -+ -+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) { -+ struct flow_match_control match; -+ -+ flow_rule_match_control(rule, &match); -+ addr_type = match.key->addr_type; -+ } else { -+ return -EOPNOTSUPP; -+ } -+ -+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { -+ struct flow_match_basic match; -+ -+ flow_rule_match_basic(rule, &match); -+ l4proto = match.key->ip_proto; -+ } else { -+ return -EOPNOTSUPP; -+ } -+ -+ flow_action_for_each(i, act, &rule->action) { -+ switch (act->id) { -+ case FLOW_ACTION_MANGLE: -+ if (act->mangle.htype == FLOW_ACT_MANGLE_HDR_TYPE_ETH) -+ mtk_flow_offload_mangle_eth(act, &data.eth); -+ break; -+ case FLOW_ACTION_REDIRECT: -+ odev = act->dev; -+ break; -+ case FLOW_ACTION_CSUM: -+ break; -+ case FLOW_ACTION_VLAN_PUSH: -+ if (data.vlan.num == 1 || -+ act->vlan.proto != htons(ETH_P_8021Q)) -+ return -EOPNOTSUPP; -+ -+ data.vlan.id = act->vlan.vid; -+ data.vlan.proto = act->vlan.proto; -+ data.vlan.num++; -+ break; -+ case FLOW_ACTION_PPPOE_PUSH: -+ if (data.pppoe.num == 1) -+ return -EOPNOTSUPP; -+ -+ data.pppoe.sid = act->pppoe.sid; -+ data.pppoe.num++; -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ } -+ -+ switch (addr_type) { -+ case FLOW_DISSECTOR_KEY_IPV4_ADDRS: -+ offload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT; -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ if (!is_valid_ether_addr(data.eth.h_source) || -+ !is_valid_ether_addr(data.eth.h_dest)) -+ return -EINVAL; -+ -+ err = mtk_foe_entry_prepare(&foe, offload_type, l4proto, 0, -+ data.eth.h_source, -+ data.eth.h_dest); -+ if (err) -+ return err; -+ -+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { -+ struct flow_match_ports ports; -+ -+ flow_rule_match_ports(rule, &ports); -+ data.src_port = ports.key->src; -+ data.dst_port = ports.key->dst; -+ } else { -+ return -EOPNOTSUPP; -+ } -+ -+ if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { -+ struct flow_match_ipv4_addrs addrs; -+ -+ flow_rule_match_ipv4_addrs(rule, &addrs); -+ -+ data.v4.src_addr = addrs.key->src; -+ data.v4.dst_addr = addrs.key->dst; -+ -+ mtk_flow_set_ipv4_addr(&foe, &data, false); -+ } -+ -+ flow_action_for_each(i, act, &rule->action) { -+ if (act->id != FLOW_ACTION_MANGLE) -+ continue; -+ -+ switch (act->mangle.htype) { -+ case FLOW_ACT_MANGLE_HDR_TYPE_TCP: -+ case FLOW_ACT_MANGLE_HDR_TYPE_UDP: -+ err = mtk_flow_mangle_ports(act, &data); -+ break; -+ case FLOW_ACT_MANGLE_HDR_TYPE_IP4: -+ err = mtk_flow_mangle_ipv4(act, &data); -+ break; -+ case FLOW_ACT_MANGLE_HDR_TYPE_ETH: -+ /* handled earlier */ -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ if (err) -+ return err; -+ } -+ -+ if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { -+ err = mtk_flow_set_ipv4_addr(&foe, &data, true); -+ if (err) -+ return err; -+ } -+ -+ if (data.vlan.num == 1) { -+ if (data.vlan.proto != htons(ETH_P_8021Q)) -+ return -EOPNOTSUPP; -+ -+ mtk_foe_entry_set_vlan(&foe, data.vlan.id); -+ } -+ if (data.pppoe.num == 1) -+ mtk_foe_entry_set_pppoe(&foe, data.pppoe.sid); -+ -+ err = mtk_flow_set_output_device(eth, &foe, odev); -+ if (err) -+ return err; -+ -+ entry = kzalloc(sizeof(*entry), GFP_KERNEL); -+ if (!entry) -+ return -ENOMEM; -+ -+ entry->cookie = f->cookie; -+ timestamp = mtk_eth_timestamp(eth); -+ hash = mtk_foe_entry_commit(ð->ppe, &foe, timestamp); -+ if (hash < 0) { -+ err = hash; -+ goto free; -+ } -+ -+ entry->hash = hash; -+ err = rhashtable_insert_fast(ð->flow_table, &entry->node, -+ mtk_flow_ht_params); -+ if (err < 0) -+ goto clear_flow; -+ -+ return 0; -+clear_flow: -+ mtk_foe_entry_clear(ð->ppe, hash); -+free: -+ kfree(entry); -+ return err; -+} -+ -+static int -+mtk_flow_offload_destroy(struct mtk_eth *eth, struct flow_cls_offload *f) -+{ -+ struct mtk_flow_entry *entry; -+ -+ entry = rhashtable_lookup(ð->flow_table, &f->cookie, -+ mtk_flow_ht_params); -+ if (!entry) -+ return -ENOENT; -+ -+ mtk_foe_entry_clear(ð->ppe, entry->hash); -+ rhashtable_remove_fast(ð->flow_table, &entry->node, -+ mtk_flow_ht_params); -+ kfree(entry); -+ -+ return 0; -+} -+ -+static int -+mtk_flow_offload_stats(struct mtk_eth *eth, struct flow_cls_offload *f) -+{ -+ struct mtk_flow_entry *entry; -+ int timestamp; -+ u32 idle; -+ -+ entry = rhashtable_lookup(ð->flow_table, &f->cookie, -+ mtk_flow_ht_params); -+ if (!entry) -+ return -ENOENT; -+ -+ timestamp = mtk_foe_entry_timestamp(ð->ppe, entry->hash); -+ if (timestamp < 0) -+ return -ETIMEDOUT; -+ -+ idle = mtk_eth_timestamp(eth) - timestamp; -+ f->stats.lastused = jiffies - idle * HZ; -+ -+ return 0; -+} -+ -+static int -+mtk_eth_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv) -+{ -+ struct flow_cls_offload *cls = type_data; -+ struct net_device *dev = cb_priv; -+ struct mtk_mac *mac = netdev_priv(dev); -+ struct mtk_eth *eth = mac->hw; -+ -+ if (!tc_can_offload(dev)) -+ return -EOPNOTSUPP; -+ -+ if (type != TC_SETUP_CLSFLOWER) -+ return -EOPNOTSUPP; -+ -+ switch (cls->command) { -+ case FLOW_CLS_REPLACE: -+ return mtk_flow_offload_replace(eth, cls); -+ case FLOW_CLS_DESTROY: -+ return mtk_flow_offload_destroy(eth, cls); -+ case FLOW_CLS_STATS: -+ return mtk_flow_offload_stats(eth, cls); -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return 0; -+} -+ -+static int -+mtk_eth_setup_tc_block(struct net_device *dev, struct flow_block_offload *f) -+{ -+ struct mtk_mac *mac = netdev_priv(dev); -+ struct mtk_eth *eth = mac->hw; -+ static LIST_HEAD(block_cb_list); -+ struct flow_block_cb *block_cb; -+ flow_setup_cb_t *cb; -+ -+ if (!eth->ppe.foe_table) -+ return -EOPNOTSUPP; -+ -+ if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) -+ return -EOPNOTSUPP; -+ -+ cb = mtk_eth_setup_tc_block_cb; -+ f->driver_block_list = &block_cb_list; -+ -+ switch (f->command) { -+ case FLOW_BLOCK_BIND: -+ block_cb = flow_block_cb_lookup(f->block, cb, dev); -+ if (block_cb) { -+ flow_block_cb_incref(block_cb); -+ return 0; -+ } -+ block_cb = flow_block_cb_alloc(cb, dev, dev, NULL); -+ if (IS_ERR(block_cb)) -+ return PTR_ERR(block_cb); -+ -+ flow_block_cb_add(block_cb, f); -+ list_add_tail(&block_cb->driver_list, &block_cb_list); -+ return 0; -+ case FLOW_BLOCK_UNBIND: -+ block_cb = flow_block_cb_lookup(f->block, cb, dev); -+ if (!block_cb) -+ return -ENOENT; -+ -+ if (flow_block_cb_decref(block_cb)) { -+ flow_block_cb_remove(block_cb, f); -+ list_del(&block_cb->driver_list); -+ } -+ return 0; -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, -+ void *type_data) -+{ -+ if (type == TC_SETUP_FT) -+ return mtk_eth_setup_tc_block(dev, type_data); -+ -+ return -EOPNOTSUPP; -+} -+ -+int mtk_eth_offload_init(struct mtk_eth *eth) -+{ -+ if (!eth->ppe.foe_table) -+ return 0; -+ -+ return rhashtable_init(ð->flow_table, &mtk_flow_ht_params); -+} diff --git a/target/linux/generic/backport-5.10/610-v5.13-34-docs-nf_flowtable-update-documentation-with-enhancem.patch b/target/linux/generic/backport-5.10/610-v5.13-34-docs-nf_flowtable-update-documentation-with-enhancem.patch deleted file mode 100644 index 2cea1ebe24..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-34-docs-nf_flowtable-update-documentation-with-enhancem.patch +++ /dev/null @@ -1,236 +0,0 @@ -From: Pablo Neira Ayuso -Date: Wed, 24 Mar 2021 02:30:55 +0100 -Subject: [PATCH] docs: nf_flowtable: update documentation with - enhancements - -This patch updates the flowtable documentation to describe recent -enhancements: - -- Offload action is available after the first packets go through the - classic forwarding path. -- IPv4 and IPv6 are supported. Only TCP and UDP layer 4 are supported at - this stage. -- Tuple has been augmented to track VLAN id and PPPoE session id. -- Bridge and IP forwarding integration, including bridge VLAN filtering - support. -- Hardware offload support. -- Describe the [OFFLOAD] and [HW_OFFLOAD] tags in the conntrack table - listing. -- Replace 'flow offload' by 'flow add' in example rulesets (preferred - syntax). -- Describe existing cache limitations. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/Documentation/networking/nf_flowtable.rst -+++ b/Documentation/networking/nf_flowtable.rst -@@ -4,35 +4,38 @@ - Netfilter's flowtable infrastructure - ==================================== - --This documentation describes the software flowtable infrastructure available in --Netfilter since Linux kernel 4.16. -+This documentation describes the Netfilter flowtable infrastructure which allows -+you to define a fastpath through the flowtable datapath. This infrastructure -+also provides hardware offload support. The flowtable supports for the layer 3 -+IPv4 and IPv6 and the layer 4 TCP and UDP protocols. - - Overview - -------- - --Initial packets follow the classic forwarding path, once the flow enters the --established state according to the conntrack semantics (ie. we have seen traffic --in both directions), then you can decide to offload the flow to the flowtable --from the forward chain via the 'flow offload' action available in nftables. -- --Packets that find an entry in the flowtable (ie. flowtable hit) are sent to the --output netdevice via neigh_xmit(), hence, they bypass the classic forwarding --path (the visible effect is that you do not see these packets from any of the --netfilter hooks coming after the ingress). In case of flowtable miss, the packet --follows the classic forward path. -- --The flowtable uses a resizable hashtable, lookups are based on the following --7-tuple selectors: source, destination, layer 3 and layer 4 protocols, source --and destination ports and the input interface (useful in case there are several --conntrack zones in place). -- --Flowtables are populated via the 'flow offload' nftables action, so the user can --selectively specify what flows are placed into the flow table. Hence, packets --follow the classic forwarding path unless the user explicitly instruct packets --to use this new alternative forwarding path via nftables policy. -+Once the first packet of the flow successfully goes through the IP forwarding -+path, from the second packet on, you might decide to offload the flow to the -+flowtable through your ruleset. The flowtable infrastructure provides a rule -+action that allows you to specify when to add a flow to the flowtable. -+ -+A packet that finds a matching entry in the flowtable (ie. flowtable hit) is -+transmitted to the output netdevice via neigh_xmit(), hence, packets bypass the -+classic IP forwarding path (the visible effect is that you do not see these -+packets from any of the Netfilter hooks coming after ingress). In case that -+there is no matching entry in the flowtable (ie. flowtable miss), the packet -+follows the classic IP forwarding path. -+ -+The flowtable uses a resizable hashtable. Lookups are based on the following -+n-tuple selectors: layer 2 protocol encapsulation (VLAN and PPPoE), layer 3 -+source and destination, layer 4 source and destination ports and the input -+interface (useful in case there are several conntrack zones in place). -+ -+The 'flow add' action allows you to populate the flowtable, the user selectively -+specifies what flows are placed into the flowtable. Hence, packets follow the -+classic IP forwarding path unless the user explicitly instruct flows to use this -+new alternative forwarding path via policy. - --This is represented in Fig.1, which describes the classic forwarding path --including the Netfilter hooks and the flowtable fastpath bypass. -+The flowtable datapath is represented in Fig.1, which describes the classic IP -+forwarding path including the Netfilter hooks and the flowtable fastpath bypass. - - :: - -@@ -67,11 +70,13 @@ including the Netfilter hooks and the fl - Fig.1 Netfilter hooks and flowtable interactions - - The flowtable entry also stores the NAT configuration, so all packets are --mangled according to the NAT policy that matches the initial packets that went --through the classic forwarding path. The TTL is decremented before calling --neigh_xmit(). Fragmented traffic is passed up to follow the classic forwarding --path given that the transport selectors are missing, therefore flowtable lookup --is not possible. -+mangled according to the NAT policy that is specified from the classic IP -+forwarding path. The TTL is decremented before calling neigh_xmit(). Fragmented -+traffic is passed up to follow the classic IP forwarding path given that the -+transport header is missing, in this case, flowtable lookups are not possible. -+TCP RST and FIN packets are also passed up to the classic IP forwarding path to -+release the flow gracefully. Packets that exceed the MTU are also passed up to -+the classic forwarding path to report packet-too-big ICMP errors to the sender. - - Example configuration - --------------------- -@@ -85,7 +90,7 @@ flowtable and add one rule to your forwa - } - chain y { - type filter hook forward priority 0; policy accept; -- ip protocol tcp flow offload @f -+ ip protocol tcp flow add @f - counter packets 0 bytes 0 - } - } -@@ -103,6 +108,117 @@ flow is offloaded, you will observe that - does not get updated for the packets that are being forwarded through the - forwarding bypass. - -+You can identify offloaded flows through the [OFFLOAD] tag when listing your -+connection tracking table. -+ -+:: -+ # conntrack -L -+ tcp 6 src=10.141.10.2 dst=192.168.10.2 sport=52728 dport=5201 src=192.168.10.2 dst=192.168.10.1 sport=5201 dport=52728 [OFFLOAD] mark=0 use=2 -+ -+ -+Layer 2 encapsulation -+--------------------- -+ -+Since Linux kernel 5.13, the flowtable infrastructure discovers the real -+netdevice behind VLAN and PPPoE netdevices. The flowtable software datapath -+parses the VLAN and PPPoE layer 2 headers to extract the ethertype and the -+VLAN ID / PPPoE session ID which are used for the flowtable lookups. The -+flowtable datapath also deals with layer 2 decapsulation. -+ -+You do not need to add the PPPoE and the VLAN devices to your flowtable, -+instead the real device is sufficient for the flowtable to track your flows. -+ -+Bridge and IP forwarding -+------------------------ -+ -+Since Linux kernel 5.13, you can add bridge ports to the flowtable. The -+flowtable infrastructure discovers the topology behind the bridge device. This -+allows the flowtable to define a fastpath bypass between the bridge ports -+(represented as eth1 and eth2 in the example figure below) and the gateway -+device (represented as eth0) in your switch/router. -+ -+:: -+ fastpath bypass -+ .-------------------------. -+ / \ -+ | IP forwarding | -+ | / \ \/ -+ | br0 eth0 ..... eth0 -+ . / \ *host B* -+ -> eth1 eth2 -+ . *switch/router* -+ . -+ . -+ eth0 -+ *host A* -+ -+The flowtable infrastructure also supports for bridge VLAN filtering actions -+such as PVID and untagged. You can also stack a classic VLAN device on top of -+your bridge port. -+ -+If you would like that your flowtable defines a fastpath between your bridge -+ports and your IP forwarding path, you have to add your bridge ports (as -+represented by the real netdevice) to your flowtable definition. -+ -+Counters -+-------- -+ -+The flowtable can synchronize packet and byte counters with the existing -+connection tracking entry by specifying the counter statement in your flowtable -+definition, e.g. -+ -+:: -+ table inet x { -+ flowtable f { -+ hook ingress priority 0; devices = { eth0, eth1 }; -+ counter -+ } -+ ... -+ } -+ -+Counter support is available since Linux kernel 5.7. -+ -+Hardware offload -+---------------- -+ -+If your network device provides hardware offload support, you can turn it on by -+means of the 'offload' flag in your flowtable definition, e.g. -+ -+:: -+ table inet x { -+ flowtable f { -+ hook ingress priority 0; devices = { eth0, eth1 }; -+ flags offload; -+ } -+ ... -+ } -+ -+There is a workqueue that adds the flows to the hardware. Note that a few -+packets might still run over the flowtable software path until the workqueue has -+a chance to offload the flow to the network device. -+ -+You can identify hardware offloaded flows through the [HW_OFFLOAD] tag when -+listing your connection tracking table. Please, note that the [OFFLOAD] tag -+refers to the software offload mode, so there is a distinction between [OFFLOAD] -+which refers to the software flowtable fastpath and [HW_OFFLOAD] which refers -+to the hardware offload datapath being used by the flow. -+ -+The flowtable hardware offload infrastructure also supports for the DSA -+(Distributed Switch Architecture). -+ -+Limitations -+----------- -+ -+The flowtable behaves like a cache. The flowtable entries might get stale if -+either the destination MAC address or the egress netdevice that is used for -+transmission changes. -+ -+This might be a problem if: -+ -+- You run the flowtable in software mode and you combine bridge and IP -+ forwarding in your setup. -+- Hardware offload is enabled. -+ - More reading - ------------ - diff --git a/target/linux/generic/backport-5.10/610-v5.13-35-net-ethernet-mediatek-ppe-fix-busy-wait-loop.patch b/target/linux/generic/backport-5.10/610-v5.13-35-net-ethernet-mediatek-ppe-fix-busy-wait-loop.patch deleted file mode 100644 index 66cd053cd1..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-35-net-ethernet-mediatek-ppe-fix-busy-wait-loop.patch +++ /dev/null @@ -1,72 +0,0 @@ -From c5d66587b8900201e1530b7c18d41e87bd5812f4 Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Thu, 15 Apr 2021 17:37:48 -0700 -Subject: [PATCH] net: ethernet: mediatek: ppe: fix busy wait loop - -The intention is for the loop to timeout if the body does not succeed. -The current logic calls time_is_before_jiffies(timeout) which is false -until after the timeout, so the loop body never executes. - -Fix by using readl_poll_timeout as a more standard and less error-prone -solution. - -Fixes: ba37b7caf1ed ("net: ethernet: mtk_eth_soc: add support for initializing the PPE") -Signed-off-by: Ilya Lipnitskiy -Cc: Felix Fietkau -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_ppe.c | 20 +++++++++----------- - drivers/net/ethernet/mediatek/mtk_ppe.h | 1 + - 2 files changed, 10 insertions(+), 11 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_ppe.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -2,9 +2,8 @@ - /* Copyright (C) 2020 Felix Fietkau */ - - #include --#include --#include - #include -+#include - #include - #include - #include "mtk_ppe.h" -@@ -44,18 +43,17 @@ static u32 ppe_clear(struct mtk_ppe *ppe - - static int mtk_ppe_wait_busy(struct mtk_ppe *ppe) - { -- unsigned long timeout = jiffies + HZ; -- -- while (time_is_before_jiffies(timeout)) { -- if (!(ppe_r32(ppe, MTK_PPE_GLO_CFG) & MTK_PPE_GLO_CFG_BUSY)) -- return 0; -+ int ret; -+ u32 val; - -- usleep_range(10, 20); -- } -+ ret = readl_poll_timeout(ppe->base + MTK_PPE_GLO_CFG, val, -+ !(val & MTK_PPE_GLO_CFG_BUSY), -+ 20, MTK_PPE_WAIT_TIMEOUT_US); - -- dev_err(ppe->dev, "PPE table busy"); -+ if (ret) -+ dev_err(ppe->dev, "PPE table busy"); - -- return -ETIMEDOUT; -+ return ret; - } - - static void mtk_ppe_cache_clear(struct mtk_ppe *ppe) ---- a/drivers/net/ethernet/mediatek/mtk_ppe.h -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -12,6 +12,7 @@ - #define MTK_PPE_ENTRIES_SHIFT 3 - #define MTK_PPE_ENTRIES (1024 << MTK_PPE_ENTRIES_SHIFT) - #define MTK_PPE_HASH_MASK (MTK_PPE_ENTRIES - 1) -+#define MTK_PPE_WAIT_TIMEOUT_US 1000000 - - #define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) - #define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) diff --git a/target/linux/generic/backport-5.10/610-v5.13-36-net-ethernet-mediatek-fix-a-typo-bug-in-flow-offload.patch b/target/linux/generic/backport-5.10/610-v5.13-36-net-ethernet-mediatek-fix-a-typo-bug-in-flow-offload.patch deleted file mode 100644 index de376bf78d..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-36-net-ethernet-mediatek-fix-a-typo-bug-in-flow-offload.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 6ecaf81d4ac6365f9284f9d68d74f7c209e74f98 Mon Sep 17 00:00:00 2001 -From: DENG Qingfang -Date: Sat, 17 Apr 2021 15:29:04 +0800 -Subject: [PATCH] net: ethernet: mediatek: fix a typo bug in flow offloading - -Issue was traffic problems after a while with increased ping times if -flow offload is active. It turns out that key_offset with cookie is -needed in rhashtable_params but was re-assigned to head_offset. -Fix the assignment. - -Fixes: 502e84e2382d ("net: ethernet: mtk_eth_soc: add flow offloading support") -Signed-off-by: DENG Qingfang -Tested-by: Frank Wunderlich -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_ppe_offload.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -44,7 +44,7 @@ struct mtk_flow_entry { - - static const struct rhashtable_params mtk_flow_ht_params = { - .head_offset = offsetof(struct mtk_flow_entry, node), -- .head_offset = offsetof(struct mtk_flow_entry, cookie), -+ .key_offset = offsetof(struct mtk_flow_entry, cookie), - .key_len = sizeof(unsigned long), - .automatic_shrinking = true, - }; diff --git a/target/linux/generic/backport-5.10/610-v5.13-38-net-ethernet-mtk_eth_soc-unmap-RX-data-before-callin.patch b/target/linux/generic/backport-5.10/610-v5.13-38-net-ethernet-mtk_eth_soc-unmap-RX-data-before-callin.patch deleted file mode 100644 index 908ec7998b..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-38-net-ethernet-mtk_eth_soc-unmap-RX-data-before-callin.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 5196c417854942e218a59ec87bf7d414b3bd581e Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:20:55 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: unmap RX data before calling - build_skb - -Since build_skb accesses the data area (for initializing shinfo), dma unmap -needs to happen before that call - -Signed-off-by: Felix Fietkau -[Ilya: split build_skb cleanup fix into a separate commit] -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1334,6 +1334,9 @@ static int mtk_poll_rx(struct napi_struc - goto release_desc; - } - -+ dma_unmap_single(eth->dev, trxd.rxd1, -+ ring->buf_size, DMA_FROM_DEVICE); -+ - /* receive data */ - skb = build_skb(data, ring->frag_size); - if (unlikely(!skb)) { -@@ -1343,8 +1346,6 @@ static int mtk_poll_rx(struct napi_struc - } - skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); - -- dma_unmap_single(eth->dev, trxd.rxd1, -- ring->buf_size, DMA_FROM_DEVICE); - pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); - skb->dev = netdev; - skb_put(skb, pktlen); diff --git a/target/linux/generic/backport-5.10/610-v5.13-39-net-ethernet-mtk_eth_soc-fix-build_skb-cleanup.patch b/target/linux/generic/backport-5.10/610-v5.13-39-net-ethernet-mtk_eth_soc-fix-build_skb-cleanup.patch deleted file mode 100644 index 4284e951ce..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-39-net-ethernet-mtk_eth_soc-fix-build_skb-cleanup.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 787082ab9f7be4711e52f67c388535eda74a1269 Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Thu, 22 Apr 2021 22:20:56 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: fix build_skb cleanup - -In case build_skb fails, call skb_free_frag on the correct pointer. Also -update the DMA structures with the new mapping before exiting, because -the mapping was successful - -Suggested-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1340,9 +1340,9 @@ static int mtk_poll_rx(struct napi_struc - /* receive data */ - skb = build_skb(data, ring->frag_size); - if (unlikely(!skb)) { -- skb_free_frag(new_data); -+ skb_free_frag(data); - netdev->stats.rx_dropped++; -- goto release_desc; -+ goto skip_rx; - } - skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); - -@@ -1362,6 +1362,7 @@ static int mtk_poll_rx(struct napi_struc - skb_record_rx_queue(skb, 0); - napi_gro_receive(napi, skb); - -+skip_rx: - ring->data[idx] = new_data; - rxd->rxd1 = (unsigned int)dma_addr; - diff --git a/target/linux/generic/backport-5.10/610-v5.13-40-net-ethernet-mtk_eth_soc-use-napi_consume_skb.patch b/target/linux/generic/backport-5.10/610-v5.13-40-net-ethernet-mtk_eth_soc-use-napi_consume_skb.patch deleted file mode 100644 index a69f8830c5..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-40-net-ethernet-mtk_eth_soc-use-napi_consume_skb.patch +++ /dev/null @@ -1,77 +0,0 @@ -From c30c4a82739090a2de4a4e3f245355ea4fb3ec14 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:20:57 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: use napi_consume_skb - -Should improve performance, since it can use bulk free - -Signed-off-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 19 ++++++++++++------- - 1 file changed, 12 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -891,7 +891,8 @@ static int txd_to_idx(struct mtk_tx_ring - return ((void *)dma - (void *)ring->dma) / sizeof(*dma); - } - --static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) -+static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, -+ bool napi) - { - if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { - if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { -@@ -923,8 +924,12 @@ static void mtk_tx_unmap(struct mtk_eth - - tx_buf->flags = 0; - if (tx_buf->skb && -- (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) -- dev_kfree_skb_any(tx_buf->skb); -+ (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) { -+ if (napi) -+ napi_consume_skb(tx_buf->skb, napi); -+ else -+ dev_kfree_skb_any(tx_buf->skb); -+ } - tx_buf->skb = NULL; - } - -@@ -1102,7 +1107,7 @@ err_dma: - tx_buf = mtk_desc_to_tx_buf(ring, itxd); - - /* unmap dma */ -- mtk_tx_unmap(eth, tx_buf); -+ mtk_tx_unmap(eth, tx_buf, false); - - itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) -@@ -1424,7 +1429,7 @@ static int mtk_poll_tx_qdma(struct mtk_e - done[mac]++; - budget--; - } -- mtk_tx_unmap(eth, tx_buf); -+ mtk_tx_unmap(eth, tx_buf, true); - - ring->last_free = desc; - atomic_inc(&ring->free_count); -@@ -1461,7 +1466,7 @@ static int mtk_poll_tx_pdma(struct mtk_e - budget--; - } - -- mtk_tx_unmap(eth, tx_buf); -+ mtk_tx_unmap(eth, tx_buf, true); - - desc = &ring->dma[cpu]; - ring->last_free = desc; -@@ -1663,7 +1668,7 @@ static void mtk_tx_clean(struct mtk_eth - - if (ring->buf) { - for (i = 0; i < MTK_DMA_SIZE; i++) -- mtk_tx_unmap(eth, &ring->buf[i]); -+ mtk_tx_unmap(eth, &ring->buf[i], false); - kfree(ring->buf); - ring->buf = NULL; - } diff --git a/target/linux/generic/backport-5.10/610-v5.13-41-net-ethernet-mtk_eth_soc-reduce-MDIO-bus-access-late.patch b/target/linux/generic/backport-5.10/610-v5.13-41-net-ethernet-mtk_eth_soc-reduce-MDIO-bus-access-late.patch deleted file mode 100644 index 7ebc3fa903..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-41-net-ethernet-mtk_eth_soc-reduce-MDIO-bus-access-late.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 3630d519d7c3eab92567658690e44ffe0517d109 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:20:58 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: reduce MDIO bus access latency - -usleep_range often ends up sleeping much longer than the 10-20us provided -as a range here. This causes significant latency in mdio bus acceses, -which easily adds multiple seconds to the boot time on MT7621 when polling -DSA slave ports. -Use cond_resched instead of usleep_range, since the MDIO access does not -take much time - -Signed-off-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -86,7 +86,7 @@ static int mtk_mdio_busy_wait(struct mtk - return 0; - if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) - break; -- usleep_range(10, 20); -+ cond_resched(); - } - - dev_err(eth->dev, "mdio: MDIO timeout\n"); diff --git a/target/linux/generic/backport-5.10/610-v5.13-42-net-ethernet-mtk_eth_soc-remove-unnecessary-TX-queue.patch b/target/linux/generic/backport-5.10/610-v5.13-42-net-ethernet-mtk_eth_soc-remove-unnecessary-TX-queue.patch deleted file mode 100644 index f08efc1b77..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-42-net-ethernet-mtk_eth_soc-remove-unnecessary-TX-queue.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 16ef670789b252b221700adc413497ed2f941d8a Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:20:59 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: remove unnecessary TX queue stops - -When running short on descriptors, only stop the queue for the netdev that -tx was attempted for. By the time something tries to send on the other -netdev, the ring might have some more room already. - -Signed-off-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 15 ++------------- - 1 file changed, 2 insertions(+), 13 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1164,17 +1164,6 @@ static void mtk_wake_queue(struct mtk_et - } - } - --static void mtk_stop_queue(struct mtk_eth *eth) --{ -- int i; -- -- for (i = 0; i < MTK_MAC_COUNT; i++) { -- if (!eth->netdev[i]) -- continue; -- netif_stop_queue(eth->netdev[i]); -- } --} -- - static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) - { - struct mtk_mac *mac = netdev_priv(dev); -@@ -1195,7 +1184,7 @@ static netdev_tx_t mtk_start_xmit(struct - - tx_num = mtk_cal_txd_req(skb); - if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { -- mtk_stop_queue(eth); -+ netif_stop_queue(dev); - netif_err(eth, tx_queued, dev, - "Tx Ring full when queue awake!\n"); - spin_unlock(ð->page_lock); -@@ -1221,7 +1210,7 @@ static netdev_tx_t mtk_start_xmit(struct - goto drop; - - if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) -- mtk_stop_queue(eth); -+ netif_stop_queue(dev); - - spin_unlock(ð->page_lock); - diff --git a/target/linux/generic/backport-5.10/610-v5.13-43-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-Q.patch b/target/linux/generic/backport-5.10/610-v5.13-43-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-Q.patch deleted file mode 100644 index a8be3f4667..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-43-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-Q.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 59555a8d0dd39bf60b7ca1ba5e7393d293f7398d Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:21:00 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: use larger burst size for QDMA TX - -Improves tx performance - -Signed-off-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2235,7 +2235,7 @@ static int mtk_start_dma(struct mtk_eth - if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { - mtk_w32(eth, - MTK_TX_WB_DDONE | MTK_TX_DMA_EN | -- MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | -+ MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | - MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | - MTK_RX_BT_32DWORDS, - MTK_QDMA_GLO_CFG); ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -202,7 +202,7 @@ - #define MTK_RX_BT_32DWORDS (3 << 11) - #define MTK_NDP_CO_PRO BIT(10) - #define MTK_TX_WB_DDONE BIT(6) --#define MTK_DMA_SIZE_16DWORDS (2 << 4) -+#define MTK_TX_BT_32DWORDS (3 << 4) - #define MTK_RX_DMA_BUSY BIT(3) - #define MTK_TX_DMA_BUSY BIT(1) - #define MTK_RX_DMA_EN BIT(2) diff --git a/target/linux/generic/backport-5.10/610-v5.13-44-net-ethernet-mtk_eth_soc-increase-DMA-ring-sizes.patch b/target/linux/generic/backport-5.10/610-v5.13-44-net-ethernet-mtk_eth_soc-increase-DMA-ring-sizes.patch deleted file mode 100644 index d695f0fb8a..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-44-net-ethernet-mtk_eth_soc-increase-DMA-ring-sizes.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 6b4423b258b91032c50a5efca15d3d9bb194ea1d Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:21:01 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: increase DMA ring sizes - -256 descriptors is not enough for multi-gigabit traffic under load on -MT7622. Bump it to 512 to improve performance. - -Signed-off-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -21,7 +21,7 @@ - #define MTK_QDMA_PAGE_SIZE 2048 - #define MTK_MAX_RX_LENGTH 1536 - #define MTK_TX_DMA_BUF_LEN 0x3fff --#define MTK_DMA_SIZE 256 -+#define MTK_DMA_SIZE 512 - #define MTK_NAPI_WEIGHT 64 - #define MTK_MAC_COUNT 2 - #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) diff --git a/target/linux/generic/backport-5.10/610-v5.13-45-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch b/target/linux/generic/backport-5.10/610-v5.13-45-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch deleted file mode 100644 index e7898bbaff..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-45-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch +++ /dev/null @@ -1,313 +0,0 @@ -From e9229ffd550b2d8c4997c67a501dbc3919fd4e26 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:21:02 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: implement dynamic interrupt - moderation - -Reduces the number of interrupts under load - -Signed-off-by: Felix Fietkau -[Ilya: add documentation for new struct fields] -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/Kconfig | 1 + - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 96 +++++++++++++++++++-- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 41 +++++++-- - 3 files changed, 124 insertions(+), 14 deletions(-) - ---- a/drivers/net/ethernet/mediatek/Kconfig -+++ b/drivers/net/ethernet/mediatek/Kconfig -@@ -10,6 +10,7 @@ if NET_VENDOR_MEDIATEK - config NET_MEDIATEK_SOC - tristate "MediaTek SoC Gigabit Ethernet support" - select PHYLINK -+ select DIMLIB - help - This driver supports the gigabit ethernet MACs in the - MediaTek SoC family. ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1266,12 +1266,13 @@ static void mtk_update_rx_cpu_idx(struct - static int mtk_poll_rx(struct napi_struct *napi, int budget, - struct mtk_eth *eth) - { -+ struct dim_sample dim_sample = {}; - struct mtk_rx_ring *ring; - int idx; - struct sk_buff *skb; - u8 *data, *new_data; - struct mtk_rx_dma *rxd, trxd; -- int done = 0; -+ int done = 0, bytes = 0; - - while (done < budget) { - struct net_device *netdev; -@@ -1348,6 +1349,7 @@ static int mtk_poll_rx(struct napi_struc - else - skb_checksum_none_assert(skb); - skb->protocol = eth_type_trans(skb, netdev); -+ bytes += pktlen; - - if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && - (trxd.rxd2 & RX_DMA_VTAG)) -@@ -1380,6 +1382,12 @@ rx_done: - mtk_update_rx_cpu_idx(eth); - } - -+ eth->rx_packets += done; -+ eth->rx_bytes += bytes; -+ dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, -+ &dim_sample); -+ net_dim(ð->rx_dim, dim_sample); -+ - return done; - } - -@@ -1472,6 +1480,7 @@ static int mtk_poll_tx_pdma(struct mtk_e - static int mtk_poll_tx(struct mtk_eth *eth, int budget) - { - struct mtk_tx_ring *ring = ð->tx_ring; -+ struct dim_sample dim_sample = {}; - unsigned int done[MTK_MAX_DEVS]; - unsigned int bytes[MTK_MAX_DEVS]; - int total = 0, i; -@@ -1489,8 +1498,14 @@ static int mtk_poll_tx(struct mtk_eth *e - continue; - netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); - total += done[i]; -+ eth->tx_packets += done[i]; -+ eth->tx_bytes += bytes[i]; - } - -+ dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, -+ &dim_sample); -+ net_dim(ð->tx_dim, dim_sample); -+ - if (mtk_queue_stopped(eth) && - (atomic_read(&ring->free_count) > ring->thresh)) - mtk_wake_queue(eth); -@@ -2171,6 +2186,7 @@ static irqreturn_t mtk_handle_irq_rx(int - { - struct mtk_eth *eth = _eth; - -+ eth->rx_events++; - if (likely(napi_schedule_prep(ð->rx_napi))) { - __napi_schedule(ð->rx_napi); - mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); -@@ -2183,6 +2199,7 @@ static irqreturn_t mtk_handle_irq_tx(int - { - struct mtk_eth *eth = _eth; - -+ eth->tx_events++; - if (likely(napi_schedule_prep(ð->tx_napi))) { - __napi_schedule(ð->tx_napi); - mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); -@@ -2371,6 +2388,9 @@ static int mtk_stop(struct net_device *d - napi_disable(ð->tx_napi); - napi_disable(ð->rx_napi); - -+ cancel_work_sync(ð->rx_dim.work); -+ cancel_work_sync(ð->tx_dim.work); -+ - if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) - mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); - mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); -@@ -2423,6 +2443,64 @@ err_disable_clks: - return ret; - } - -+static void mtk_dim_rx(struct work_struct *work) -+{ -+ struct dim *dim = container_of(work, struct dim, work); -+ struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); -+ struct dim_cq_moder cur_profile; -+ u32 val, cur; -+ -+ cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, -+ dim->profile_ix); -+ spin_lock_bh(ð->dim_lock); -+ -+ val = mtk_r32(eth, MTK_PDMA_DELAY_INT); -+ val &= MTK_PDMA_DELAY_TX_MASK; -+ val |= MTK_PDMA_DELAY_RX_EN; -+ -+ cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); -+ val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; -+ -+ cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); -+ val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; -+ -+ mtk_w32(eth, val, MTK_PDMA_DELAY_INT); -+ mtk_w32(eth, val, MTK_QDMA_DELAY_INT); -+ -+ spin_unlock_bh(ð->dim_lock); -+ -+ dim->state = DIM_START_MEASURE; -+} -+ -+static void mtk_dim_tx(struct work_struct *work) -+{ -+ struct dim *dim = container_of(work, struct dim, work); -+ struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); -+ struct dim_cq_moder cur_profile; -+ u32 val, cur; -+ -+ cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, -+ dim->profile_ix); -+ spin_lock_bh(ð->dim_lock); -+ -+ val = mtk_r32(eth, MTK_PDMA_DELAY_INT); -+ val &= MTK_PDMA_DELAY_RX_MASK; -+ val |= MTK_PDMA_DELAY_TX_EN; -+ -+ cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); -+ val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; -+ -+ cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); -+ val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; -+ -+ mtk_w32(eth, val, MTK_PDMA_DELAY_INT); -+ mtk_w32(eth, val, MTK_QDMA_DELAY_INT); -+ -+ spin_unlock_bh(ð->dim_lock); -+ -+ dim->state = DIM_START_MEASURE; -+} -+ - static int mtk_hw_init(struct mtk_eth *eth) - { - int i, val, ret; -@@ -2444,9 +2522,6 @@ static int mtk_hw_init(struct mtk_eth *e - goto err_disable_pm; - } - -- /* enable interrupt delay for RX */ -- mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); -- - /* disable delay and normal interrupt */ - mtk_tx_irq_disable(eth, ~0); - mtk_rx_irq_disable(eth, ~0); -@@ -2485,11 +2560,11 @@ static int mtk_hw_init(struct mtk_eth *e - /* Enable RX VLan Offloading */ - mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); - -- /* enable interrupt delay for RX */ -- mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); -+ /* set interrupt delays based on current Net DIM sample */ -+ mtk_dim_rx(ð->rx_dim.work); -+ mtk_dim_tx(ð->tx_dim.work); - - /* disable delay and normal interrupt */ -- mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); - mtk_tx_irq_disable(eth, ~0); - mtk_rx_irq_disable(eth, ~0); - -@@ -2994,6 +3069,13 @@ static int mtk_probe(struct platform_dev - spin_lock_init(ð->page_lock); - spin_lock_init(ð->tx_irq_lock); - spin_lock_init(ð->rx_irq_lock); -+ spin_lock_init(ð->dim_lock); -+ -+ eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; -+ INIT_WORK(ð->rx_dim.work, mtk_dim_rx); -+ -+ eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; -+ INIT_WORK(ð->tx_dim.work, mtk_dim_tx); - - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { - eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include "mtk_ppe.h" - - #define MTK_QDMA_PAGE_SIZE 2048 -@@ -136,13 +137,18 @@ - - /* PDMA Delay Interrupt Register */ - #define MTK_PDMA_DELAY_INT 0xa0c -+#define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0) - #define MTK_PDMA_DELAY_RX_EN BIT(15) --#define MTK_PDMA_DELAY_RX_PINT 4 - #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8 --#define MTK_PDMA_DELAY_RX_PTIME 4 --#define MTK_PDMA_DELAY_RX_DELAY \ -- (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \ -- (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT)) -+#define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0 -+ -+#define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16) -+#define MTK_PDMA_DELAY_TX_EN BIT(31) -+#define MTK_PDMA_DELAY_TX_PINT_SHIFT 24 -+#define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16 -+ -+#define MTK_PDMA_DELAY_PINT_MASK 0x7f -+#define MTK_PDMA_DELAY_PTIME_MASK 0xff - - /* PDMA Interrupt Status Register */ - #define MTK_PDMA_INT_STATUS 0xa20 -@@ -224,6 +230,7 @@ - /* QDMA Interrupt Status Register */ - #define MTK_QDMA_INT_STATUS 0x1A18 - #define MTK_RX_DONE_DLY BIT(30) -+#define MTK_TX_DONE_DLY BIT(28) - #define MTK_RX_DONE_INT3 BIT(19) - #define MTK_RX_DONE_INT2 BIT(18) - #define MTK_RX_DONE_INT1 BIT(17) -@@ -233,8 +240,7 @@ - #define MTK_TX_DONE_INT1 BIT(1) - #define MTK_TX_DONE_INT0 BIT(0) - #define MTK_RX_DONE_INT MTK_RX_DONE_DLY --#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ -- MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) -+#define MTK_TX_DONE_INT MTK_TX_DONE_DLY - - /* QDMA Interrupt grouping registers */ - #define MTK_QDMA_INT_GRP1 0x1a20 -@@ -864,6 +870,7 @@ struct mtk_sgmii { - * @page_lock: Make sure that register operations are atomic - * @tx_irq__lock: Make sure that IRQ register operations are atomic - * @rx_irq__lock: Make sure that IRQ register operations are atomic -+ * @dim_lock: Make sure that Net DIM operations are atomic - * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a - * dummy for NAPI to work - * @netdev: The netdev instances -@@ -882,6 +889,14 @@ struct mtk_sgmii { - * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring - * @tx_napi: The TX NAPI struct - * @rx_napi: The RX NAPI struct -+ * @rx_events: Net DIM RX event counter -+ * @rx_packets: Net DIM RX packet counter -+ * @rx_bytes: Net DIM RX byte counter -+ * @rx_dim: Net DIM RX context -+ * @tx_events: Net DIM TX event counter -+ * @tx_packets: Net DIM TX packet counter -+ * @tx_bytes: Net DIM TX byte counter -+ * @tx_dim: Net DIM TX context - * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring - * @phy_scratch_ring: physical address of scratch_ring - * @scratch_head: The scratch memory that scratch_ring points to. -@@ -926,6 +941,18 @@ struct mtk_eth { - - const struct mtk_soc_data *soc; - -+ spinlock_t dim_lock; -+ -+ u32 rx_events; -+ u32 rx_packets; -+ u32 rx_bytes; -+ struct dim rx_dim; -+ -+ u32 tx_events; -+ u32 tx_packets; -+ u32 tx_bytes; -+ struct dim tx_dim; -+ - u32 tx_int_mask_reg; - u32 tx_int_status_reg; - u32 rx_dma_l4_valid; diff --git a/target/linux/generic/backport-5.10/610-v5.13-46-net-ethernet-mtk_eth_soc-cache-HW-pointer-of-last-fr.patch b/target/linux/generic/backport-5.10/610-v5.13-46-net-ethernet-mtk_eth_soc-cache-HW-pointer-of-last-fr.patch deleted file mode 100644 index 69f8536f0a..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-46-net-ethernet-mtk_eth_soc-cache-HW-pointer-of-last-fr.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 4e6bf609569c59b6bd6acf4a607c096cbd820d79 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:21:03 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: cache HW pointer of last freed TX - descriptor - -The value is only updated by the CPU, so it is cheaper to access from the -ring data structure than from a hardware register. - -Signed-off-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 ++++---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 ++ - 2 files changed, 6 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1400,7 +1400,7 @@ static int mtk_poll_tx_qdma(struct mtk_e - struct mtk_tx_buf *tx_buf; - u32 cpu, dma; - -- cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); -+ cpu = ring->last_free_ptr; - dma = mtk_r32(eth, MTK_QTX_DRX_PTR); - - desc = mtk_qdma_phys_to_virt(ring, cpu); -@@ -1434,6 +1434,7 @@ static int mtk_poll_tx_qdma(struct mtk_e - cpu = next_cpu; - } - -+ ring->last_free_ptr = cpu; - mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); - - return budget; -@@ -1634,6 +1635,7 @@ static int mtk_tx_alloc(struct mtk_eth * - atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); - ring->next_free = &ring->dma[0]; - ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; -+ ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); - ring->thresh = MAX_SKB_FRAGS; - - /* make sure that all changes to the dma ring are flushed before we -@@ -1647,9 +1649,7 @@ static int mtk_tx_alloc(struct mtk_eth * - mtk_w32(eth, - ring->phys + ((MTK_DMA_SIZE - 1) * sz), - MTK_QTX_CRX_PTR); -- mtk_w32(eth, -- ring->phys + ((MTK_DMA_SIZE - 1) * sz), -- MTK_QTX_DRX_PTR); -+ mtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR); - mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, - MTK_QTX_CFG(0)); - } else { ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -657,6 +657,7 @@ struct mtk_tx_buf { - * @phys: The physical addr of tx_buf - * @next_free: Pointer to the next free descriptor - * @last_free: Pointer to the last free descriptor -+ * @last_free_ptr: Hardware pointer value of the last free descriptor - * @thresh: The threshold of minimum amount of free descriptors - * @free_count: QDMA uses a linked list. Track how many free descriptors - * are present -@@ -667,6 +668,7 @@ struct mtk_tx_ring { - dma_addr_t phys; - struct mtk_tx_dma *next_free; - struct mtk_tx_dma *last_free; -+ u32 last_free_ptr; - u16 thresh; - atomic_t free_count; - int dma_size; diff --git a/target/linux/generic/backport-5.10/610-v5.13-47-net-ethernet-mtk_eth_soc-only-read-the-full-RX-descr.patch b/target/linux/generic/backport-5.10/610-v5.13-47-net-ethernet-mtk_eth_soc-only-read-the-full-RX-descr.patch deleted file mode 100644 index 6484361ee5..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-47-net-ethernet-mtk_eth_soc-only-read-the-full-RX-descr.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 816ac3e6e67bdd78d86226c6eb53619780750e92 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:21:04 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: only read the full RX descriptor - if DMA is done - -Uncached memory access is expensive, and there is no need to access all -descriptor words if we can't process them anyway - -Signed-off-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -799,13 +799,18 @@ static inline int mtk_max_buf_size(int f - return buf_size; - } - --static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, -+static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd, - struct mtk_rx_dma *dma_rxd) - { -- rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); - rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); -+ if (!(rxd->rxd2 & RX_DMA_DONE)) -+ return false; -+ -+ rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); - rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); - rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); -+ -+ return true; - } - - static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) -@@ -1288,8 +1293,7 @@ static int mtk_poll_rx(struct napi_struc - rxd = &ring->dma[idx]; - data = ring->data[idx]; - -- mtk_rx_get_desc(&trxd, rxd); -- if (!(trxd.rxd2 & RX_DMA_DONE)) -+ if (!mtk_rx_get_desc(&trxd, rxd)) - break; - - /* find out which mac the packet come from. values start at 1 */ diff --git a/target/linux/generic/backport-5.10/610-v5.13-48-net-ethernet-mtk_eth_soc-reduce-unnecessary-interrup.patch b/target/linux/generic/backport-5.10/610-v5.13-48-net-ethernet-mtk_eth_soc-reduce-unnecessary-interrup.patch deleted file mode 100644 index 27c04ae3c4..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-48-net-ethernet-mtk_eth_soc-reduce-unnecessary-interrup.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 16769a8923fad5a5377253bcd76b0e0d64976c73 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:21:05 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: reduce unnecessary interrupts - -Avoid rearming interrupt if napi_complete returns false - -Signed-off-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 +++++---- - 1 file changed, 5 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1555,8 +1555,8 @@ static int mtk_napi_tx(struct napi_struc - if (status & MTK_TX_DONE_INT) - return budget; - -- napi_complete(napi); -- mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); -+ if (napi_complete(napi)) -+ mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); - - return tx_done; - } -@@ -1589,8 +1589,9 @@ poll_again: - remain_budget -= rx_done; - goto poll_again; - } -- napi_complete(napi); -- mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); -+ -+ if (napi_complete(napi)) -+ mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); - - return rx_done + budget - remain_budget; - } diff --git a/target/linux/generic/backport-5.10/610-v5.13-49-net-ethernet-mtk_eth_soc-rework-NAPI-callbacks.patch b/target/linux/generic/backport-5.10/610-v5.13-49-net-ethernet-mtk_eth_soc-rework-NAPI-callbacks.patch deleted file mode 100644 index 21a3e9bef0..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-49-net-ethernet-mtk_eth_soc-rework-NAPI-callbacks.patch +++ /dev/null @@ -1,110 +0,0 @@ -From db2c7b353db3b3f71b55f9ff4627d8a786446fbe Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Thu, 22 Apr 2021 22:21:06 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: rework NAPI callbacks - -Use napi_complete_done to communicate total TX and RX work done to NAPI. -Count total RX work up instead of remaining work down for clarity. -Remove unneeded local variables for clarity. Use do {} while instead of -goto for clarity. - -Suggested-by: Jakub Kicinski -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 54 +++++++++------------ - 1 file changed, 24 insertions(+), 30 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -1532,7 +1532,6 @@ static void mtk_handle_status_irq(struct - static int mtk_napi_tx(struct napi_struct *napi, int budget) - { - struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); -- u32 status, mask; - int tx_done = 0; - - if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) -@@ -1541,21 +1540,19 @@ static int mtk_napi_tx(struct napi_struc - tx_done = mtk_poll_tx(eth, budget); - - if (unlikely(netif_msg_intr(eth))) { -- status = mtk_r32(eth, eth->tx_int_status_reg); -- mask = mtk_r32(eth, eth->tx_int_mask_reg); - dev_info(eth->dev, -- "done tx %d, intr 0x%08x/0x%x\n", -- tx_done, status, mask); -+ "done tx %d, intr 0x%08x/0x%x\n", tx_done, -+ mtk_r32(eth, eth->tx_int_status_reg), -+ mtk_r32(eth, eth->tx_int_mask_reg)); - } - - if (tx_done == budget) - return budget; - -- status = mtk_r32(eth, eth->tx_int_status_reg); -- if (status & MTK_TX_DONE_INT) -+ if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) - return budget; - -- if (napi_complete(napi)) -+ if (napi_complete_done(napi, tx_done)) - mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); - - return tx_done; -@@ -1564,36 +1561,33 @@ static int mtk_napi_tx(struct napi_struc - static int mtk_napi_rx(struct napi_struct *napi, int budget) - { - struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); -- u32 status, mask; -- int rx_done = 0; -- int remain_budget = budget; -+ int rx_done_total = 0; - - mtk_handle_status_irq(eth); - --poll_again: -- mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); -- rx_done = mtk_poll_rx(napi, remain_budget, eth); -+ do { -+ int rx_done; - -- if (unlikely(netif_msg_intr(eth))) { -- status = mtk_r32(eth, MTK_PDMA_INT_STATUS); -- mask = mtk_r32(eth, MTK_PDMA_INT_MASK); -- dev_info(eth->dev, -- "done rx %d, intr 0x%08x/0x%x\n", -- rx_done, status, mask); -- } -- if (rx_done == remain_budget) -- return budget; -+ mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); -+ rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); -+ rx_done_total += rx_done; -+ -+ if (unlikely(netif_msg_intr(eth))) { -+ dev_info(eth->dev, -+ "done rx %d, intr 0x%08x/0x%x\n", rx_done, -+ mtk_r32(eth, MTK_PDMA_INT_STATUS), -+ mtk_r32(eth, MTK_PDMA_INT_MASK)); -+ } - -- status = mtk_r32(eth, MTK_PDMA_INT_STATUS); -- if (status & MTK_RX_DONE_INT) { -- remain_budget -= rx_done; -- goto poll_again; -- } -+ if (rx_done_total == budget) -+ return budget; -+ -+ } while (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT); - -- if (napi_complete(napi)) -+ if (napi_complete_done(napi, rx_done_total)) - mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); - -- return rx_done + budget - remain_budget; -+ return rx_done_total; - } - - static int mtk_tx_alloc(struct mtk_eth *eth) diff --git a/target/linux/generic/backport-5.10/610-v5.13-50-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch b/target/linux/generic/backport-5.10/610-v5.13-50-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch deleted file mode 100644 index aad129b897..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-50-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch +++ /dev/null @@ -1,47 +0,0 @@ -From fa817272c37ef78e25dc14e4760ac78a7043a18a Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 22 Apr 2021 22:21:07 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: set PPE flow hash as skb hash if - present - -This improves GRO performance - -Signed-off-by: Felix Fietkau -[Ilya: Use MTK_RXD4_FOE_ENTRY instead of GENMASK(13, 0)] -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - #include - - #include "mtk_eth_soc.h" -@@ -1283,6 +1284,7 @@ static int mtk_poll_rx(struct napi_struc - struct net_device *netdev; - unsigned int pktlen; - dma_addr_t dma_addr; -+ u32 hash; - int mac; - - ring = mtk_get_rx_ring(eth); -@@ -1355,6 +1357,12 @@ static int mtk_poll_rx(struct napi_struc - skb->protocol = eth_type_trans(skb, netdev); - bytes += pktlen; - -+ hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; -+ if (hash != MTK_RXD4_FOE_ENTRY) { -+ hash = jhash_1word(hash, 0); -+ skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); -+ } -+ - if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && - (trxd.rxd2 & RX_DMA_VTAG)) - __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), diff --git a/target/linux/generic/backport-5.10/610-v5.13-51-net-ethernet-mtk_eth_soc-use-iopoll.h-macro-for-DMA-.patch b/target/linux/generic/backport-5.10/610-v5.13-51-net-ethernet-mtk_eth_soc-use-iopoll.h-macro-for-DMA-.patch deleted file mode 100644 index 493883f4f1..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-51-net-ethernet-mtk_eth_soc-use-iopoll.h-macro-for-DMA-.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 3bc8e0aff23be0526af0dbc7973a8866a08d73f1 Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Thu, 22 Apr 2021 22:21:08 -0700 -Subject: [PATCH] net: ethernet: mtk_eth_soc: use iopoll.h macro for DMA init - -Replace a tight busy-wait loop without a pause with a standard -readx_poll_timeout_atomic routine with a 5 us poll period. - -Tested by booting a MT7621 device to ensure the driver initializes -properly. - -Signed-off-by: Ilya Lipnitskiy -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 29 +++++++++------------ - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +- - 2 files changed, 14 insertions(+), 17 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2075,25 +2075,22 @@ static int mtk_set_features(struct net_d - /* wait for DMA to finish whatever it is doing before we start using it again */ - static int mtk_dma_busy_wait(struct mtk_eth *eth) - { -- unsigned long t_start = jiffies; -+ unsigned int reg; -+ int ret; -+ u32 val; - -- while (1) { -- if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { -- if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & -- (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) -- return 0; -- } else { -- if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) & -- (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) -- return 0; -- } -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) -+ reg = MTK_QDMA_GLO_CFG; -+ else -+ reg = MTK_PDMA_GLO_CFG; - -- if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) -- break; -- } -+ ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, -+ !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), -+ 5, MTK_DMA_BUSY_TIMEOUT_US); -+ if (ret) -+ dev_err(eth->dev, "DMA init timeout\n"); - -- dev_err(eth->dev, "DMA init timeout\n"); -- return -1; -+ return ret; - } - - static int mtk_dma_init(struct mtk_eth *eth) ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -213,7 +213,7 @@ - #define MTK_TX_DMA_BUSY BIT(1) - #define MTK_RX_DMA_EN BIT(2) - #define MTK_TX_DMA_EN BIT(0) --#define MTK_DMA_BUSY_TIMEOUT HZ -+#define MTK_DMA_BUSY_TIMEOUT_US 1000000 - - /* QDMA Reset Index Register */ - #define MTK_QDMA_RST_IDX 0x1A08 diff --git a/target/linux/generic/backport-5.10/610-v5.13-52-net-ethernet-mtk_eth_soc-missing-mutex.patch b/target/linux/generic/backport-5.10/610-v5.13-52-net-ethernet-mtk_eth_soc-missing-mutex.patch deleted file mode 100644 index a846ce43e2..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-52-net-ethernet-mtk_eth_soc-missing-mutex.patch +++ /dev/null @@ -1,63 +0,0 @@ -From: Pablo Neira Ayuso -Date: Sun, 18 Apr 2021 23:11:44 +0200 -Subject: [PATCH] net: ethernet: mtk_eth_soc: missing mutex - -Patch 2ed37183abb7 ("netfilter: flowtable: separate replace, destroy and -stats to different workqueues") splits the workqueue per event type. Add -a mutex to serialize updates. - -Fixes: 502e84e2382d ("net: ethernet: mtk_eth_soc: add flow offloading support") -Reported-by: Frank Wunderlich -Signed-off-by: Pablo Neira Ayuso -Signed-off-by: David S. Miller ---- - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -392,6 +392,8 @@ mtk_flow_offload_stats(struct mtk_eth *e - return 0; - } - -+static DEFINE_MUTEX(mtk_flow_offload_mutex); -+ - static int - mtk_eth_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv) - { -@@ -399,6 +401,7 @@ mtk_eth_setup_tc_block_cb(enum tc_setup_ - struct net_device *dev = cb_priv; - struct mtk_mac *mac = netdev_priv(dev); - struct mtk_eth *eth = mac->hw; -+ int err; - - if (!tc_can_offload(dev)) - return -EOPNOTSUPP; -@@ -406,18 +409,24 @@ mtk_eth_setup_tc_block_cb(enum tc_setup_ - if (type != TC_SETUP_CLSFLOWER) - return -EOPNOTSUPP; - -+ mutex_lock(&mtk_flow_offload_mutex); - switch (cls->command) { - case FLOW_CLS_REPLACE: -- return mtk_flow_offload_replace(eth, cls); -+ err = mtk_flow_offload_replace(eth, cls); -+ break; - case FLOW_CLS_DESTROY: -- return mtk_flow_offload_destroy(eth, cls); -+ err = mtk_flow_offload_destroy(eth, cls); -+ break; - case FLOW_CLS_STATS: -- return mtk_flow_offload_stats(eth, cls); -+ err = mtk_flow_offload_stats(eth, cls); -+ break; - default: -- return -EOPNOTSUPP; -+ err = -EOPNOTSUPP; -+ break; - } -+ mutex_unlock(&mtk_flow_offload_mutex); - -- return 0; -+ return err; - } - - static int diff --git a/target/linux/generic/backport-5.10/610-v5.13-53-net-ethernet-mtk_eth_soc-handle-VLAN-pop-action.patch b/target/linux/generic/backport-5.10/610-v5.13-53-net-ethernet-mtk_eth_soc-handle-VLAN-pop-action.patch deleted file mode 100644 index 806fd0dcdf..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-53-net-ethernet-mtk_eth_soc-handle-VLAN-pop-action.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Pablo Neira Ayuso -Date: Sun, 18 Apr 2021 23:11:45 +0200 -Subject: [PATCH] net: ethernet: mtk_eth_soc: handle VLAN pop action - -Do not hit EOPNOTSUPP when flowtable offload provides a VLAN pop action. - -Fixes: efce49dfe6a8 ("netfilter: flowtable: add vlan pop action offload support") -Signed-off-by: Pablo Neira Ayuso -Signed-off-by: David S. Miller ---- - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -233,6 +233,8 @@ mtk_flow_offload_replace(struct mtk_eth - data.vlan.proto = act->vlan.proto; - data.vlan.num++; - break; -+ case FLOW_ACTION_VLAN_POP: -+ break; - case FLOW_ACTION_PPPOE_PUSH: - if (data.pppoe.num == 1) - return -EOPNOTSUPP; diff --git a/target/linux/generic/backport-5.10/610-v5.13-54-netfilter-flowtable-dst_check-from-garbage-collector.patch b/target/linux/generic/backport-5.10/610-v5.13-54-netfilter-flowtable-dst_check-from-garbage-collector.patch deleted file mode 100644 index 42b55f021a..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-54-netfilter-flowtable-dst_check-from-garbage-collector.patch +++ /dev/null @@ -1,159 +0,0 @@ -From: Pablo Neira Ayuso -Date: Sun, 28 Mar 2021 23:08:55 +0200 -Subject: [PATCH] netfilter: flowtable: dst_check() from garbage collector path - -Move dst_check() to the garbage collector path. Stale routes trigger the -flow entry teardown state which makes affected flows go back to the -classic forwarding path to re-evaluate flow offloading. - -IPv6 requires the dst cookie to work, store it in the flow_tuple, -otherwise dst_check() always fails. - -Fixes: e5075c0badaa ("netfilter: flowtable: call dst_check() to fall back to classic forwarding") -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -129,7 +129,10 @@ struct flow_offload_tuple { - in_vlan_ingress:2; - u16 mtu; - union { -- struct dst_entry *dst_cache; -+ struct { -+ struct dst_entry *dst_cache; -+ u32 dst_cookie; -+ }; - struct { - u32 ifidx; - u32 hw_ifidx; ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -74,6 +74,18 @@ err_ct_refcnt: - } - EXPORT_SYMBOL_GPL(flow_offload_alloc); - -+static u32 flow_offload_dst_cookie(struct flow_offload_tuple *flow_tuple) -+{ -+ const struct rt6_info *rt; -+ -+ if (flow_tuple->l3proto == NFPROTO_IPV6) { -+ rt = (const struct rt6_info *)flow_tuple->dst_cache; -+ return rt6_get_cookie(rt); -+ } -+ -+ return 0; -+} -+ - static int flow_offload_fill_route(struct flow_offload *flow, - const struct nf_flow_route *route, - enum flow_offload_tuple_dir dir) -@@ -116,6 +128,7 @@ static int flow_offload_fill_route(struc - return -1; - - flow_tuple->dst_cache = dst; -+ flow_tuple->dst_cookie = flow_offload_dst_cookie(flow_tuple); - break; - } - flow_tuple->xmit_type = route->tuple[dir].xmit_type; -@@ -389,11 +402,33 @@ nf_flow_table_iterate(struct nf_flowtabl - return err; - } - -+static bool flow_offload_stale_dst(struct flow_offload_tuple *tuple) -+{ -+ struct dst_entry *dst; -+ -+ if (tuple->xmit_type == FLOW_OFFLOAD_XMIT_NEIGH || -+ tuple->xmit_type == FLOW_OFFLOAD_XMIT_XFRM) { -+ dst = tuple->dst_cache; -+ if (!dst_check(dst, tuple->dst_cookie)) -+ return true; -+ } -+ -+ return false; -+} -+ -+static bool nf_flow_has_stale_dst(struct flow_offload *flow) -+{ -+ return flow_offload_stale_dst(&flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple) || -+ flow_offload_stale_dst(&flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple); -+} -+ - static void nf_flow_offload_gc_step(struct flow_offload *flow, void *data) - { - struct nf_flowtable *flow_table = data; - -- if (nf_flow_has_expired(flow) || nf_ct_is_dying(flow->ct)) -+ if (nf_flow_has_expired(flow) || -+ nf_ct_is_dying(flow->ct) || -+ nf_flow_has_stale_dst(flow)) - set_bit(NF_FLOW_TEARDOWN, &flow->flags); - - if (test_bit(NF_FLOW_TEARDOWN, &flow->flags)) { ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -364,15 +364,6 @@ nf_flow_offload_ip_hook(void *priv, stru - if (nf_flow_state_check(flow, iph->protocol, skb, thoff)) - return NF_ACCEPT; - -- if (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH || -- tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM) { -- rt = (struct rtable *)tuplehash->tuple.dst_cache; -- if (!dst_check(&rt->dst, 0)) { -- flow_offload_teardown(flow); -- return NF_ACCEPT; -- } -- } -- - if (skb_try_make_writable(skb, thoff + hdrsize)) - return NF_DROP; - -@@ -391,6 +382,7 @@ nf_flow_offload_ip_hook(void *priv, stru - nf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len); - - if (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) { -+ rt = (struct rtable *)tuplehash->tuple.dst_cache; - memset(skb->cb, 0, sizeof(struct inet_skb_parm)); - IPCB(skb)->iif = skb->dev->ifindex; - IPCB(skb)->flags = IPSKB_FORWARDED; -@@ -399,6 +391,7 @@ nf_flow_offload_ip_hook(void *priv, stru - - switch (tuplehash->tuple.xmit_type) { - case FLOW_OFFLOAD_XMIT_NEIGH: -+ rt = (struct rtable *)tuplehash->tuple.dst_cache; - outdev = rt->dst.dev; - skb->dev = outdev; - nexthop = rt_nexthop(rt, flow->tuplehash[!dir].tuple.src_v4.s_addr); -@@ -607,15 +600,6 @@ nf_flow_offload_ipv6_hook(void *priv, st - if (nf_flow_state_check(flow, ip6h->nexthdr, skb, thoff)) - return NF_ACCEPT; - -- if (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH || -- tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM) { -- rt = (struct rt6_info *)tuplehash->tuple.dst_cache; -- if (!dst_check(&rt->dst, 0)) { -- flow_offload_teardown(flow); -- return NF_ACCEPT; -- } -- } -- - if (skb_try_make_writable(skb, thoff + hdrsize)) - return NF_DROP; - -@@ -633,6 +617,7 @@ nf_flow_offload_ipv6_hook(void *priv, st - nf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len); - - if (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) { -+ rt = (struct rt6_info *)tuplehash->tuple.dst_cache; - memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); - IP6CB(skb)->iif = skb->dev->ifindex; - IP6CB(skb)->flags = IP6SKB_FORWARDED; -@@ -641,6 +626,7 @@ nf_flow_offload_ipv6_hook(void *priv, st - - switch (tuplehash->tuple.xmit_type) { - case FLOW_OFFLOAD_XMIT_NEIGH: -+ rt = (struct rt6_info *)tuplehash->tuple.dst_cache; - outdev = rt->dst.dev; - skb->dev = outdev; - nexthop = rt6_nexthop(rt, &flow->tuplehash[!dir].tuple.src_v6); diff --git a/target/linux/generic/backport-5.10/610-v5.13-55-netfilter-conntrack-Introduce-tcp-offload-timeout-co.patch b/target/linux/generic/backport-5.10/610-v5.13-55-netfilter-conntrack-Introduce-tcp-offload-timeout-co.patch deleted file mode 100644 index 0d30b0c593..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-55-netfilter-conntrack-Introduce-tcp-offload-timeout-co.patch +++ /dev/null @@ -1,94 +0,0 @@ -From: Oz Shlomo -Date: Thu, 3 Jun 2021 15:12:33 +0300 -Subject: [PATCH] netfilter: conntrack: Introduce tcp offload timeout - configuration - -TCP connections may be offloaded from nf conntrack to nf flow table. -Offloaded connections are aged after 30 seconds of inactivity. -Once aged, ownership is returned to conntrack with a hard coded pickup -time of 120 seconds, after which the connection may be deleted. -eted. The current aging intervals may be too aggressive for some users. - -Provide users with the ability to control the nf flow table offload -aging and pickup time intervals via sysctl parameter as a pre-step for -configuring the nf flow table GC timeout intervals. - -Signed-off-by: Oz Shlomo -Reviewed-by: Paul Blakey -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netns/conntrack.h -+++ b/include/net/netns/conntrack.h -@@ -27,6 +27,10 @@ struct nf_tcp_net { - int tcp_loose; - int tcp_be_liberal; - int tcp_max_retrans; -+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE) -+ unsigned int offload_timeout; -+ unsigned int offload_pickup; -+#endif - }; - - enum udp_conntrack { ---- a/net/netfilter/nf_conntrack_proto_tcp.c -+++ b/net/netfilter/nf_conntrack_proto_tcp.c -@@ -1457,6 +1457,11 @@ void nf_conntrack_tcp_init_net(struct ne - tn->tcp_loose = nf_ct_tcp_loose; - tn->tcp_be_liberal = nf_ct_tcp_be_liberal; - tn->tcp_max_retrans = nf_ct_tcp_max_retrans; -+ -+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE) -+ tn->offload_timeout = 30 * HZ; -+ tn->offload_pickup = 120 * HZ; -+#endif - } - - const struct nf_conntrack_l4proto nf_conntrack_l4proto_tcp = ---- a/net/netfilter/nf_conntrack_standalone.c -+++ b/net/netfilter/nf_conntrack_standalone.c -@@ -567,6 +567,10 @@ enum nf_ct_sysctl_index { - NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_CLOSE, - NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_RETRANS, - NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_UNACK, -+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE) -+ NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD, -+ NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD_PICKUP, -+#endif - NF_SYSCTL_CT_PROTO_TCP_LOOSE, - NF_SYSCTL_CT_PROTO_TCP_LIBERAL, - NF_SYSCTL_CT_PROTO_TCP_MAX_RETRANS, -@@ -757,6 +761,20 @@ static struct ctl_table nf_ct_sysctl_tab - .mode = 0644, - .proc_handler = proc_dointvec_jiffies, - }, -+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE) -+ [NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD] = { -+ .procname = "nf_flowtable_tcp_timeout", -+ .maxlen = sizeof(unsigned int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_jiffies, -+ }, -+ [NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD_PICKUP] = { -+ .procname = "nf_flowtable_tcp_pickup", -+ .maxlen = sizeof(unsigned int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_jiffies, -+ }, -+#endif - [NF_SYSCTL_CT_PROTO_TCP_LOOSE] = { - .procname = "nf_conntrack_tcp_loose", - .maxlen = sizeof(int), -@@ -960,6 +978,12 @@ static void nf_conntrack_standalone_init - XASSIGN(LIBERAL, &tn->tcp_be_liberal); - XASSIGN(MAX_RETRANS, &tn->tcp_max_retrans); - #undef XASSIGN -+ -+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE) -+ table[NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD].data = &tn->offload_timeout; -+ table[NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD_PICKUP].data = &tn->offload_pickup; -+#endif -+ - } - - static void nf_conntrack_standalone_init_sctp_sysctl(struct net *net, diff --git a/target/linux/generic/backport-5.10/610-v5.13-56-netfilter-conntrack-Introduce-udp-offload-timeout-co.patch b/target/linux/generic/backport-5.10/610-v5.13-56-netfilter-conntrack-Introduce-udp-offload-timeout-co.patch deleted file mode 100644 index 93ff24a941..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-56-netfilter-conntrack-Introduce-udp-offload-timeout-co.patch +++ /dev/null @@ -1,92 +0,0 @@ -From: Oz Shlomo -Date: Thu, 3 Jun 2021 15:12:34 +0300 -Subject: [PATCH] netfilter: conntrack: Introduce udp offload timeout - configuration - -UDP connections may be offloaded from nf conntrack to nf flow table. -Offloaded connections are aged after 30 seconds of inactivity. -Once aged, ownership is returned to conntrack with a hard coded pickup -time of 30 seconds, after which the connection may be deleted. -eted. The current aging intervals may be too aggressive for some users. - -Provide users with the ability to control the nf flow table offload -aging and pickup time intervals via sysctl parameter as a pre-step for -configuring the nf flow table GC timeout intervals. - -Signed-off-by: Oz Shlomo -Reviewed-by: Paul Blakey -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netns/conntrack.h -+++ b/include/net/netns/conntrack.h -@@ -41,6 +41,10 @@ enum udp_conntrack { - - struct nf_udp_net { - unsigned int timeouts[UDP_CT_MAX]; -+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE) -+ unsigned int offload_timeout; -+ unsigned int offload_pickup; -+#endif - }; - - struct nf_icmp_net { ---- a/net/netfilter/nf_conntrack_proto_udp.c -+++ b/net/netfilter/nf_conntrack_proto_udp.c -@@ -273,6 +273,11 @@ void nf_conntrack_udp_init_net(struct ne - - for (i = 0; i < UDP_CT_MAX; i++) - un->timeouts[i] = udp_timeouts[i]; -+ -+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE) -+ un->offload_timeout = 30 * HZ; -+ un->offload_pickup = 30 * HZ; -+#endif - } - - const struct nf_conntrack_l4proto nf_conntrack_l4proto_udp = ---- a/net/netfilter/nf_conntrack_standalone.c -+++ b/net/netfilter/nf_conntrack_standalone.c -@@ -576,6 +576,10 @@ enum nf_ct_sysctl_index { - NF_SYSCTL_CT_PROTO_TCP_MAX_RETRANS, - NF_SYSCTL_CT_PROTO_TIMEOUT_UDP, - NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_STREAM, -+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE) -+ NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD, -+ NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD_PICKUP, -+#endif - NF_SYSCTL_CT_PROTO_TIMEOUT_ICMP, - NF_SYSCTL_CT_PROTO_TIMEOUT_ICMPV6, - #ifdef CONFIG_NF_CT_PROTO_SCTP -@@ -809,6 +813,20 @@ static struct ctl_table nf_ct_sysctl_tab - .mode = 0644, - .proc_handler = proc_dointvec_jiffies, - }, -+#if IS_ENABLED(CONFIG_NFT_FLOW_OFFLOAD) -+ [NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD] = { -+ .procname = "nf_flowtable_udp_timeout", -+ .maxlen = sizeof(unsigned int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_jiffies, -+ }, -+ [NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD_PICKUP] = { -+ .procname = "nf_flowtable_udp_pickup", -+ .maxlen = sizeof(unsigned int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_jiffies, -+ }, -+#endif - [NF_SYSCTL_CT_PROTO_TIMEOUT_ICMP] = { - .procname = "nf_conntrack_icmp_timeout", - .maxlen = sizeof(unsigned int), -@@ -1070,6 +1088,10 @@ static int nf_conntrack_standalone_init_ - table[NF_SYSCTL_CT_PROTO_TIMEOUT_ICMPV6].data = &nf_icmpv6_pernet(net)->timeout; - table[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP].data = &un->timeouts[UDP_CT_UNREPLIED]; - table[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_STREAM].data = &un->timeouts[UDP_CT_REPLIED]; -+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE) -+ table[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD].data = &un->offload_timeout; -+ table[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD_PICKUP].data = &un->offload_pickup; -+#endif - - nf_conntrack_standalone_init_tcp_sysctl(net, table); - nf_conntrack_standalone_init_sctp_sysctl(net, table); diff --git a/target/linux/generic/backport-5.10/610-v5.13-57-netfilter-flowtable-Set-offload-timeouts-according-t.patch b/target/linux/generic/backport-5.10/610-v5.13-57-netfilter-flowtable-Set-offload-timeouts-according-t.patch deleted file mode 100644 index 1e82308eaa..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-57-netfilter-flowtable-Set-offload-timeouts-according-t.patch +++ /dev/null @@ -1,134 +0,0 @@ -From: Oz Shlomo -Date: Thu, 3 Jun 2021 15:12:35 +0300 -Subject: [PATCH] netfilter: flowtable: Set offload timeouts according to proto - values - -Currently the aging period for tcp/udp connections is hard coded to -30 seconds. Aged tcp/udp connections configure a hard coded 120/30 -seconds pickup timeout for conntrack. -This configuration may be too aggressive or permissive for some users. - -Dynamically configure the nf flow table GC timeout intervals according -to the user defined values. - -Signed-off-by: Oz Shlomo -Reviewed-by: Paul Blakey -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -174,6 +174,8 @@ struct flow_offload { - #define NF_FLOW_TIMEOUT (30 * HZ) - #define nf_flowtable_time_stamp (u32)jiffies - -+unsigned long flow_offload_get_timeout(struct flow_offload *flow); -+ - static inline __s32 nf_flow_timeout_delta(unsigned int timeout) - { - return (__s32)(timeout - nf_flowtable_time_stamp); ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -175,12 +175,10 @@ static void flow_offload_fixup_tcp(struc - tcp->seen[1].td_maxwin = 0; - } - --#define NF_FLOWTABLE_TCP_PICKUP_TIMEOUT (120 * HZ) --#define NF_FLOWTABLE_UDP_PICKUP_TIMEOUT (30 * HZ) -- - static void flow_offload_fixup_ct_timeout(struct nf_conn *ct) - { - const struct nf_conntrack_l4proto *l4proto; -+ struct net *net = nf_ct_net(ct); - int l4num = nf_ct_protonum(ct); - unsigned int timeout; - -@@ -188,12 +186,17 @@ static void flow_offload_fixup_ct_timeou - if (!l4proto) - return; - -- if (l4num == IPPROTO_TCP) -- timeout = NF_FLOWTABLE_TCP_PICKUP_TIMEOUT; -- else if (l4num == IPPROTO_UDP) -- timeout = NF_FLOWTABLE_UDP_PICKUP_TIMEOUT; -- else -+ if (l4num == IPPROTO_TCP) { -+ struct nf_tcp_net *tn = nf_tcp_pernet(net); -+ -+ timeout = tn->offload_pickup; -+ } else if (l4num == IPPROTO_UDP) { -+ struct nf_udp_net *tn = nf_udp_pernet(net); -+ -+ timeout = tn->offload_pickup; -+ } else { - return; -+ } - - if (nf_flow_timeout_delta(READ_ONCE(ct->timeout)) > (__s32)timeout) - WRITE_ONCE(ct->timeout, nfct_time_stamp + timeout); -@@ -265,11 +268,35 @@ static const struct rhashtable_params nf - .automatic_shrinking = true, - }; - -+unsigned long flow_offload_get_timeout(struct flow_offload *flow) -+{ -+ const struct nf_conntrack_l4proto *l4proto; -+ unsigned long timeout = NF_FLOW_TIMEOUT; -+ struct net *net = nf_ct_net(flow->ct); -+ int l4num = nf_ct_protonum(flow->ct); -+ -+ l4proto = nf_ct_l4proto_find(l4num); -+ if (!l4proto) -+ return timeout; -+ -+ if (l4num == IPPROTO_TCP) { -+ struct nf_tcp_net *tn = nf_tcp_pernet(net); -+ -+ timeout = tn->offload_timeout; -+ } else if (l4num == IPPROTO_UDP) { -+ struct nf_udp_net *tn = nf_udp_pernet(net); -+ -+ timeout = tn->offload_timeout; -+ } -+ -+ return timeout; -+} -+ - int flow_offload_add(struct nf_flowtable *flow_table, struct flow_offload *flow) - { - int err; - -- flow->timeout = nf_flowtable_time_stamp + NF_FLOW_TIMEOUT; -+ flow->timeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow); - - err = rhashtable_insert_fast(&flow_table->rhashtable, - &flow->tuplehash[0].node, -@@ -301,7 +328,7 @@ EXPORT_SYMBOL_GPL(flow_offload_add); - void flow_offload_refresh(struct nf_flowtable *flow_table, - struct flow_offload *flow) - { -- flow->timeout = nf_flowtable_time_stamp + NF_FLOW_TIMEOUT; -+ flow->timeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow); - - if (likely(!nf_flowtable_hw_offload(flow_table))) - return; ---- a/net/netfilter/nf_flow_table_offload.c -+++ b/net/netfilter/nf_flow_table_offload.c -@@ -885,7 +885,7 @@ static void flow_offload_work_stats(stru - - lastused = max_t(u64, stats[0].lastused, stats[1].lastused); - offload->flow->timeout = max_t(u64, offload->flow->timeout, -- lastused + NF_FLOW_TIMEOUT); -+ lastused + flow_offload_get_timeout(offload->flow)); - - if (offload->flowtable->flags & NF_FLOWTABLE_COUNTER) { - if (stats[0].pkts) -@@ -989,7 +989,7 @@ void nf_flow_offload_stats(struct nf_flo - __s32 delta; - - delta = nf_flow_timeout_delta(flow->timeout); -- if ((delta >= (9 * NF_FLOW_TIMEOUT) / 10)) -+ if ((delta >= (9 * flow_offload_get_timeout(flow)) / 10)) - return; - - offload = nf_flow_offload_work_alloc(flowtable, flow, FLOW_CLS_STATS); diff --git a/target/linux/generic/backport-5.10/610-v5.13-58-netfilter-flowtable-Add-FLOW_OFFLOAD_XMIT_UNSPEC-xmi.patch b/target/linux/generic/backport-5.10/610-v5.13-58-netfilter-flowtable-Add-FLOW_OFFLOAD_XMIT_UNSPEC-xmi.patch deleted file mode 100644 index 62edb2c811..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-58-netfilter-flowtable-Add-FLOW_OFFLOAD_XMIT_UNSPEC-xmi.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 78ed0a9bc6db76f8e5f5f4cb0d2b2f0d1bb21b24 Mon Sep 17 00:00:00 2001 -From: Roi Dayan -Date: Tue, 13 Apr 2021 11:06:05 +0300 -Subject: [PATCH] netfilter: flowtable: Add FLOW_OFFLOAD_XMIT_UNSPEC xmit type - -It could be xmit type was not set and would default to FLOW_OFFLOAD_XMIT_NEIGH -and in this type the gc expect to have a route info. -Fix that by adding FLOW_OFFLOAD_XMIT_UNSPEC which defaults to 0. - -Fixes: 8b9229d15877 ("netfilter: flowtable: dst_check() from garbage collector path") -Signed-off-by: Roi Dayan -Signed-off-by: Pablo Neira Ayuso ---- - include/net/netfilter/nf_flow_table.h | 3 ++- - net/netfilter/nf_flow_table_core.c | 3 +++ - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -90,7 +90,8 @@ enum flow_offload_tuple_dir { - #define FLOW_OFFLOAD_DIR_MAX IP_CT_DIR_MAX - - enum flow_offload_xmit_type { -- FLOW_OFFLOAD_XMIT_NEIGH = 0, -+ FLOW_OFFLOAD_XMIT_UNSPEC = 0, -+ FLOW_OFFLOAD_XMIT_NEIGH, - FLOW_OFFLOAD_XMIT_XFRM, - FLOW_OFFLOAD_XMIT_DIRECT, - }; ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -130,6 +130,9 @@ static int flow_offload_fill_route(struc - flow_tuple->dst_cache = dst; - flow_tuple->dst_cookie = flow_offload_dst_cookie(flow_tuple); - break; -+ default: -+ WARN_ON_ONCE(1); -+ break; - } - flow_tuple->xmit_type = route->tuple[dir].xmit_type; - diff --git a/target/linux/generic/backport-5.10/610-v5.15-58-netfilter-flowtable-avoid-possible-false-sharing.patch b/target/linux/generic/backport-5.10/610-v5.15-58-netfilter-flowtable-avoid-possible-false-sharing.patch deleted file mode 100644 index a3d0a35923..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.15-58-netfilter-flowtable-avoid-possible-false-sharing.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Pablo Neira Ayuso -Date: Sat, 17 Jul 2021 10:10:29 +0200 -Subject: [PATCH] netfilter: flowtable: avoid possible false sharing - -The flowtable follows the same timeout approach as conntrack, use the -same idiom as in cc16921351d8 ("netfilter: conntrack: avoid same-timeout -update") but also include the fix provided by e37542ba111f ("netfilter: -conntrack: avoid possible false sharing"). - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -331,7 +331,11 @@ EXPORT_SYMBOL_GPL(flow_offload_add); - void flow_offload_refresh(struct nf_flowtable *flow_table, - struct flow_offload *flow) - { -- flow->timeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow); -+ u32 timeout; -+ -+ timeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow); -+ if (READ_ONCE(flow->timeout) != timeout) -+ WRITE_ONCE(flow->timeout, timeout); - - if (likely(!nf_flowtable_hw_offload(flow_table))) - return; diff --git a/target/linux/generic/backport-5.10/610-v5.18-netfilter-flowtable-move-dst_check-to-packet-path.patch b/target/linux/generic/backport-5.10/610-v5.18-netfilter-flowtable-move-dst_check-to-packet-path.patch deleted file mode 100644 index 53118939a3..0000000000 --- a/target/linux/generic/backport-5.10/610-v5.18-netfilter-flowtable-move-dst_check-to-packet-path.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 2738d9d963bd1f06d5114c2b4fa5771a95703991 Mon Sep 17 00:00:00 2001 -From: Ritaro Takenaka -Date: Tue, 17 May 2022 12:55:30 +0200 -Subject: [PATCH] netfilter: flowtable: move dst_check to packet path - -Fixes sporadic IPv6 packet loss when flow offloading is enabled. - -IPv6 route GC and flowtable GC are not synchronized. -When dst_cache becomes stale and a packet passes through the flow before -the flowtable GC teardowns it, the packet can be dropped. -So, it is necessary to check dst every time in packet path. - -Fixes: 227e1e4d0d6c ("netfilter: nf_flowtable: skip device lookup from interface index") -Signed-off-by: Ritaro Takenaka -Signed-off-by: Pablo Neira Ayuso ---- - net/netfilter/nf_flow_table_core.c | 23 +---------------------- - net/netfilter/nf_flow_table_ip.c | 19 +++++++++++++++++++ - 2 files changed, 20 insertions(+), 22 deletions(-) - ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -436,33 +436,12 @@ nf_flow_table_iterate(struct nf_flowtabl - return err; - } - --static bool flow_offload_stale_dst(struct flow_offload_tuple *tuple) --{ -- struct dst_entry *dst; -- -- if (tuple->xmit_type == FLOW_OFFLOAD_XMIT_NEIGH || -- tuple->xmit_type == FLOW_OFFLOAD_XMIT_XFRM) { -- dst = tuple->dst_cache; -- if (!dst_check(dst, tuple->dst_cookie)) -- return true; -- } -- -- return false; --} -- --static bool nf_flow_has_stale_dst(struct flow_offload *flow) --{ -- return flow_offload_stale_dst(&flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple) || -- flow_offload_stale_dst(&flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple); --} -- - static void nf_flow_offload_gc_step(struct flow_offload *flow, void *data) - { - struct nf_flowtable *flow_table = data; - - if (nf_flow_has_expired(flow) || -- nf_ct_is_dying(flow->ct) || -- nf_flow_has_stale_dst(flow)) -+ nf_ct_is_dying(flow->ct)) - set_bit(NF_FLOW_TEARDOWN, &flow->flags); - - if (test_bit(NF_FLOW_TEARDOWN, &flow->flags)) { ---- a/net/netfilter/nf_flow_table_ip.c -+++ b/net/netfilter/nf_flow_table_ip.c -@@ -229,6 +229,15 @@ static bool nf_flow_exceeds_mtu(const st - return true; - } - -+static inline bool nf_flow_dst_check(struct flow_offload_tuple *tuple) -+{ -+ if (tuple->xmit_type != FLOW_OFFLOAD_XMIT_NEIGH && -+ tuple->xmit_type != FLOW_OFFLOAD_XMIT_XFRM) -+ return true; -+ -+ return dst_check(tuple->dst_cache, tuple->dst_cookie); -+} -+ - static unsigned int nf_flow_xmit_xfrm(struct sk_buff *skb, - const struct nf_hook_state *state, - struct dst_entry *dst) -@@ -364,6 +373,11 @@ nf_flow_offload_ip_hook(void *priv, stru - if (nf_flow_state_check(flow, iph->protocol, skb, thoff)) - return NF_ACCEPT; - -+ if (!nf_flow_dst_check(&tuplehash->tuple)) { -+ flow_offload_teardown(flow); -+ return NF_ACCEPT; -+ } -+ - if (skb_try_make_writable(skb, thoff + hdrsize)) - return NF_DROP; - -@@ -600,6 +614,11 @@ nf_flow_offload_ipv6_hook(void *priv, st - if (nf_flow_state_check(flow, ip6h->nexthdr, skb, thoff)) - return NF_ACCEPT; - -+ if (!nf_flow_dst_check(&tuplehash->tuple)) { -+ flow_offload_teardown(flow); -+ return NF_ACCEPT; -+ } -+ - if (skb_try_make_writable(skb, thoff + hdrsize)) - return NF_DROP; - diff --git a/target/linux/generic/backport-5.10/611-v5.12-net-ethernet-mediatek-support-setting-MTU.patch b/target/linux/generic/backport-5.10/611-v5.12-net-ethernet-mediatek-support-setting-MTU.patch deleted file mode 100644 index a2c407f7c8..0000000000 --- a/target/linux/generic/backport-5.10/611-v5.12-net-ethernet-mediatek-support-setting-MTU.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 4fd59792097a6b2fb949d41264386a7ecade469e Mon Sep 17 00:00:00 2001 -From: DENG Qingfang -Date: Mon, 25 Jan 2021 12:20:46 +0800 -Subject: [PATCH] net: ethernet: mediatek: support setting MTU - -MT762x HW, except for MT7628, supports frame length up to 2048 -(maximum length on GDM), so allow setting MTU up to 2030. - -Also set the default frame length to the hardware default 1518. - -Signed-off-by: DENG Qingfang -Reviewed-by: Andrew Lunn -Link: https://lore.kernel.org/r/20210125042046.5599-1-dqfext@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 43 ++++++++++++++++++--- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++++-- - 2 files changed, 47 insertions(+), 8 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -355,7 +355,7 @@ static void mtk_mac_config(struct phylin - /* Setup gmac */ - mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); - mcr_new = mcr_cur; -- mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | -+ mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | - MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK | - MAC_MCR_RX_FIFO_CLR_DIS; - -@@ -783,8 +783,8 @@ static void mtk_get_stats64(struct net_d - static inline int mtk_max_frag_size(int mtu) - { - /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ -- if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) -- mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; -+ if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) -+ mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; - - return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); -@@ -795,7 +795,7 @@ static inline int mtk_max_buf_size(int f - int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - - SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); - -- WARN_ON(buf_size < MTK_MAX_RX_LENGTH); -+ WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); - - return buf_size; - } -@@ -2631,6 +2631,35 @@ static void mtk_uninit(struct net_device - mtk_rx_irq_disable(eth, ~0); - } - -+static int mtk_change_mtu(struct net_device *dev, int new_mtu) -+{ -+ int length = new_mtu + MTK_RX_ETH_HLEN; -+ struct mtk_mac *mac = netdev_priv(dev); -+ struct mtk_eth *eth = mac->hw; -+ u32 mcr_cur, mcr_new; -+ -+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { -+ mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); -+ mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; -+ -+ if (length <= 1518) -+ mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); -+ else if (length <= 1536) -+ mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); -+ else if (length <= 1552) -+ mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); -+ else -+ mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); -+ -+ if (mcr_new != mcr_cur) -+ mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); -+ } -+ -+ dev->mtu = new_mtu; -+ -+ return 0; -+} -+ - static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) - { - struct mtk_mac *mac = netdev_priv(dev); -@@ -2927,6 +2956,7 @@ static const struct net_device_ops mtk_n - .ndo_set_mac_address = mtk_set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_do_ioctl = mtk_do_ioctl, -+ .ndo_change_mtu = mtk_change_mtu, - .ndo_tx_timeout = mtk_tx_timeout, - .ndo_get_stats64 = mtk_get_stats64, - .ndo_fix_features = mtk_fix_features, -@@ -3029,7 +3059,10 @@ static int mtk_add_mac(struct mtk_eth *e - eth->netdev[id]->irq = eth->irq[0]; - eth->netdev[id]->dev.of_node = np; - -- eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; -+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) -+ eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; -+ else -+ eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; - - return 0; - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -20,12 +20,13 @@ - #include "mtk_ppe.h" - - #define MTK_QDMA_PAGE_SIZE 2048 --#define MTK_MAX_RX_LENGTH 1536 -+#define MTK_MAX_RX_LENGTH 1536 -+#define MTK_MAX_RX_LENGTH_2K 2048 - #define MTK_TX_DMA_BUF_LEN 0x3fff - #define MTK_DMA_SIZE 512 - #define MTK_NAPI_WEIGHT 64 - #define MTK_MAC_COUNT 2 --#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) -+#define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) - #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) - #define MTK_DMA_DUMMY_DESC 0xffffffff - #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ -@@ -352,7 +353,12 @@ - - /* Mac control registers */ - #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) --#define MAC_MCR_MAX_RX_1536 BIT(24) -+#define MAC_MCR_MAX_RX_MASK GENMASK(25, 24) -+#define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24)) -+#define MAC_MCR_MAX_RX_1518 0x0 -+#define MAC_MCR_MAX_RX_1536 0x1 -+#define MAC_MCR_MAX_RX_1552 0x2 -+#define MAC_MCR_MAX_RX_2048 0x3 - #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) - #define MAC_MCR_FORCE_MODE BIT(15) - #define MAC_MCR_TX_EN BIT(14) diff --git a/target/linux/generic/backport-5.10/612-v5.15-netfilter-conntrack-sanitize-table-size-default-sett.patch b/target/linux/generic/backport-5.10/612-v5.15-netfilter-conntrack-sanitize-table-size-default-sett.patch deleted file mode 100644 index 55bf0f612b..0000000000 --- a/target/linux/generic/backport-5.10/612-v5.15-netfilter-conntrack-sanitize-table-size-default-sett.patch +++ /dev/null @@ -1,100 +0,0 @@ -From d532bcd0b2699d84d71a0c71d37157ac6eb3be25 Mon Sep 17 00:00:00 2001 -Message-Id: -From: Florian Westphal -Date: Thu, 26 Aug 2021 15:54:19 +0200 -Subject: [PATCH] netfilter: conntrack: sanitize table size default settings - -conntrack has two distinct table size settings: -nf_conntrack_max and nf_conntrack_buckets. - -The former limits how many conntrack objects are allowed to exist -in each namespace. - -The second sets the size of the hashtable. - -As all entries are inserted twice (once for original direction, once for -reply), there should be at least twice as many buckets in the table than -the maximum number of conntrack objects that can exist at the same time. - -Change the default multiplier to 1 and increase the chosen bucket sizes. -This results in the same nf_conntrack_max settings as before but reduces -the average bucket list length. - -Signed-off-by: Florian Westphal -Signed-off-by: Pablo Neira Ayuso ---- - .../networking/nf_conntrack-sysctl.rst | 13 ++++---- - net/netfilter/nf_conntrack_core.c | 30 +++++++++---------- - 2 files changed, 22 insertions(+), 21 deletions(-) - ---- a/Documentation/networking/nf_conntrack-sysctl.rst -+++ b/Documentation/networking/nf_conntrack-sysctl.rst -@@ -17,9 +17,8 @@ nf_conntrack_acct - BOOLEAN - nf_conntrack_buckets - INTEGER - Size of hash table. If not specified as parameter during module - loading, the default size is calculated by dividing total memory -- by 16384 to determine the number of buckets but the hash table will -- never have fewer than 32 and limited to 16384 buckets. For systems -- with more than 4GB of memory it will be 65536 buckets. -+ by 16384 to determine the number of buckets. The hash table will -+ never have fewer than 1024 and never more than 262144 buckets. - This sysctl is only writeable in the initial net namespace. - - nf_conntrack_checksum - BOOLEAN -@@ -100,8 +99,12 @@ nf_conntrack_log_invalid - INTEGER - Log invalid packets of a type specified by value. - - nf_conntrack_max - INTEGER -- Size of connection tracking table. Default value is -- nf_conntrack_buckets value * 4. -+ Maximum number of allowed connection tracking entries. This value is set -+ to nf_conntrack_buckets by default. -+ Note that connection tracking entries are added to the table twice -- once -+ for the original direction and once for the reply direction (i.e., with -+ the reversed address). This means that with default settings a maxed-out -+ table will have a average hash chain length of 2, not 1. - - nf_conntrack_tcp_be_liberal - BOOLEAN - - 0 - disabled (default) ---- a/net/netfilter/nf_conntrack_core.c -+++ b/net/netfilter/nf_conntrack_core.c -@@ -2575,26 +2575,24 @@ int nf_conntrack_init_start(void) - spin_lock_init(&nf_conntrack_locks[i]); - - if (!nf_conntrack_htable_size) { -- /* Idea from tcp.c: use 1/16384 of memory. -- * On i386: 32MB machine has 512 buckets. -- * >= 1GB machines have 16384 buckets. -- * >= 4GB machines have 65536 buckets. -- */ - nf_conntrack_htable_size - = (((nr_pages << PAGE_SHIFT) / 16384) - / sizeof(struct hlist_head)); -- if (nr_pages > (4 * (1024 * 1024 * 1024 / PAGE_SIZE))) -- nf_conntrack_htable_size = 65536; -+ if (BITS_PER_LONG >= 64 && -+ nr_pages > (4 * (1024 * 1024 * 1024 / PAGE_SIZE))) -+ nf_conntrack_htable_size = 262144; - else if (nr_pages > (1024 * 1024 * 1024 / PAGE_SIZE)) -- nf_conntrack_htable_size = 16384; -- if (nf_conntrack_htable_size < 32) -- nf_conntrack_htable_size = 32; -+ nf_conntrack_htable_size = 65536; - -- /* Use a max. factor of four by default to get the same max as -- * with the old struct list_heads. When a table size is given -- * we use the old value of 8 to avoid reducing the max. -- * entries. */ -- max_factor = 4; -+ if (nf_conntrack_htable_size < 1024) -+ nf_conntrack_htable_size = 1024; -+ /* Use a max. factor of one by default to keep the average -+ * hash chain length at 2 entries. Each entry has to be added -+ * twice (once for original direction, once for reply). -+ * When a table size is given we use the old value of 8 to -+ * avoid implicit reduction of the max entries setting. -+ */ -+ max_factor = 1; - } - - nf_conntrack_hash = nf_ct_alloc_hashtable(&nf_conntrack_htable_size, 1); diff --git a/target/linux/generic/backport-5.10/613-v5.15-01-netfilter-flowtable-remove-nf_ct_l4proto_find-call.patch b/target/linux/generic/backport-5.10/613-v5.15-01-netfilter-flowtable-remove-nf_ct_l4proto_find-call.patch deleted file mode 100644 index 72accec50c..0000000000 --- a/target/linux/generic/backport-5.10/613-v5.15-01-netfilter-flowtable-remove-nf_ct_l4proto_find-call.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 92fb15513edc6ae1eb51f717e70d4d3d538c2d09 Mon Sep 17 00:00:00 2001 -From: Pablo Neira Ayuso -Date: Mon, 19 Jul 2021 18:04:01 +0200 -Subject: [PATCH] netfilter: flowtable: remove nf_ct_l4proto_find() call - -TCP and UDP are built-in conntrack protocol trackers and the flowtable -only supports for TCP and UDP, remove this call. - -Signed-off-by: Pablo Neira Ayuso ---- - net/netfilter/nf_flow_table_core.c | 10 ---------- - 1 file changed, 10 deletions(-) - ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -180,15 +180,10 @@ static void flow_offload_fixup_tcp(struc - - static void flow_offload_fixup_ct_timeout(struct nf_conn *ct) - { -- const struct nf_conntrack_l4proto *l4proto; - struct net *net = nf_ct_net(ct); - int l4num = nf_ct_protonum(ct); - unsigned int timeout; - -- l4proto = nf_ct_l4proto_find(l4num); -- if (!l4proto) -- return; -- - if (l4num == IPPROTO_TCP) { - struct nf_tcp_net *tn = nf_tcp_pernet(net); - -@@ -273,15 +268,10 @@ static const struct rhashtable_params nf - - unsigned long flow_offload_get_timeout(struct flow_offload *flow) - { -- const struct nf_conntrack_l4proto *l4proto; - unsigned long timeout = NF_FLOW_TIMEOUT; - struct net *net = nf_ct_net(flow->ct); - int l4num = nf_ct_protonum(flow->ct); - -- l4proto = nf_ct_l4proto_find(l4num); -- if (!l4proto) -- return timeout; -- - if (l4num == IPPROTO_TCP) { - struct nf_tcp_net *tn = nf_tcp_pernet(net); - diff --git a/target/linux/generic/backport-5.10/613-v5.15-02-netfilter-conntrack-remove-offload_pickup-sysctl-aga.patch b/target/linux/generic/backport-5.10/613-v5.15-02-netfilter-conntrack-remove-offload_pickup-sysctl-aga.patch deleted file mode 100644 index 71266c8a70..0000000000 --- a/target/linux/generic/backport-5.10/613-v5.15-02-netfilter-conntrack-remove-offload_pickup-sysctl-aga.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 4592ee7f525c4683ec9e290381601fdee50ae110 Mon Sep 17 00:00:00 2001 -From: Florian Westphal -Date: Wed, 4 Aug 2021 15:02:15 +0200 -Subject: [PATCH] netfilter: conntrack: remove offload_pickup sysctl again - -These two sysctls were added because the hardcoded defaults (2 minutes, -tcp, 30 seconds, udp) turned out to be too low for some setups. - -They appeared in 5.14-rc1 so it should be fine to remove it again. - -Marcelo convinced me that there should be no difference between a flow -that was offloaded vs. a flow that was not wrt. timeout handling. -Thus the default is changed to those for TCP established and UDP stream, -5 days and 120 seconds, respectively. - -Marcelo also suggested to account for the timeout value used for the -offloading, this avoids increase beyond the value in the conntrack-sysctl -and will also instantly expire the conntrack entry with altered sysctls. - -Example: - nf_conntrack_udp_timeout_stream=60 - nf_flowtable_udp_timeout=60 - -This will remove offloaded udp flows after one minute, rather than two. - -An earlier version of this patch also cleared the ASSURED bit to -allow nf_conntrack to evict the entry via early_drop (i.e., table full). -However, it looks like we can safely assume that connection timed out -via HW is still in established state, so this isn't needed. - -Quoting Oz: - [..] the hardware sends all packets with a set FIN flags to sw. - [..] Connections that are aged in hardware are expected to be in the - established state. - -In case it turns out that back-to-sw-path transition can occur for -'dodgy' connections too (e.g., one side disappeared while software-path -would have been in RETRANS timeout), we can adjust this later. - -Cc: Oz Shlomo -Cc: Paul Blakey -Suggested-by: Marcelo Ricardo Leitner -Signed-off-by: Florian Westphal -Reviewed-by: Marcelo Ricardo Leitner -Reviewed-by: Oz Shlomo -Signed-off-by: Pablo Neira Ayuso ---- - Documentation/networking/nf_conntrack-sysctl.rst | 10 ---------- - include/net/netns/conntrack.h | 2 -- - net/netfilter/nf_conntrack_proto_tcp.c | 1 - - net/netfilter/nf_conntrack_proto_udp.c | 1 - - net/netfilter/nf_conntrack_standalone.c | 16 ---------------- - net/netfilter/nf_flow_table_core.c | 11 ++++++++--- - 6 files changed, 8 insertions(+), 33 deletions(-) - ---- a/include/net/netns/conntrack.h -+++ b/include/net/netns/conntrack.h -@@ -29,7 +29,6 @@ struct nf_tcp_net { - int tcp_max_retrans; - #if IS_ENABLED(CONFIG_NF_FLOW_TABLE) - unsigned int offload_timeout; -- unsigned int offload_pickup; - #endif - }; - -@@ -43,7 +42,6 @@ struct nf_udp_net { - unsigned int timeouts[UDP_CT_MAX]; - #if IS_ENABLED(CONFIG_NF_FLOW_TABLE) - unsigned int offload_timeout; -- unsigned int offload_pickup; - #endif - }; - ---- a/net/netfilter/nf_conntrack_proto_tcp.c -+++ b/net/netfilter/nf_conntrack_proto_tcp.c -@@ -1460,7 +1460,6 @@ void nf_conntrack_tcp_init_net(struct ne - - #if IS_ENABLED(CONFIG_NF_FLOW_TABLE) - tn->offload_timeout = 30 * HZ; -- tn->offload_pickup = 120 * HZ; - #endif - } - ---- a/net/netfilter/nf_conntrack_proto_udp.c -+++ b/net/netfilter/nf_conntrack_proto_udp.c -@@ -276,7 +276,6 @@ void nf_conntrack_udp_init_net(struct ne - - #if IS_ENABLED(CONFIG_NF_FLOW_TABLE) - un->offload_timeout = 30 * HZ; -- un->offload_pickup = 30 * HZ; - #endif - } - ---- a/net/netfilter/nf_conntrack_standalone.c -+++ b/net/netfilter/nf_conntrack_standalone.c -@@ -569,7 +569,6 @@ enum nf_ct_sysctl_index { - NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_UNACK, - #if IS_ENABLED(CONFIG_NF_FLOW_TABLE) - NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD, -- NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD_PICKUP, - #endif - NF_SYSCTL_CT_PROTO_TCP_LOOSE, - NF_SYSCTL_CT_PROTO_TCP_LIBERAL, -@@ -578,7 +577,6 @@ enum nf_ct_sysctl_index { - NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_STREAM, - #if IS_ENABLED(CONFIG_NF_FLOW_TABLE) - NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD, -- NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD_PICKUP, - #endif - NF_SYSCTL_CT_PROTO_TIMEOUT_ICMP, - NF_SYSCTL_CT_PROTO_TIMEOUT_ICMPV6, -@@ -772,12 +770,6 @@ static struct ctl_table nf_ct_sysctl_tab - .mode = 0644, - .proc_handler = proc_dointvec_jiffies, - }, -- [NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD_PICKUP] = { -- .procname = "nf_flowtable_tcp_pickup", -- .maxlen = sizeof(unsigned int), -- .mode = 0644, -- .proc_handler = proc_dointvec_jiffies, -- }, - #endif - [NF_SYSCTL_CT_PROTO_TCP_LOOSE] = { - .procname = "nf_conntrack_tcp_loose", -@@ -820,12 +812,6 @@ static struct ctl_table nf_ct_sysctl_tab - .mode = 0644, - .proc_handler = proc_dointvec_jiffies, - }, -- [NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD_PICKUP] = { -- .procname = "nf_flowtable_udp_pickup", -- .maxlen = sizeof(unsigned int), -- .mode = 0644, -- .proc_handler = proc_dointvec_jiffies, -- }, - #endif - [NF_SYSCTL_CT_PROTO_TIMEOUT_ICMP] = { - .procname = "nf_conntrack_icmp_timeout", -@@ -999,7 +985,6 @@ static void nf_conntrack_standalone_init - - #if IS_ENABLED(CONFIG_NF_FLOW_TABLE) - table[NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD].data = &tn->offload_timeout; -- table[NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD_PICKUP].data = &tn->offload_pickup; - #endif - - } -@@ -1090,7 +1075,6 @@ static int nf_conntrack_standalone_init_ - table[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_STREAM].data = &un->timeouts[UDP_CT_REPLIED]; - #if IS_ENABLED(CONFIG_NF_FLOW_TABLE) - table[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD].data = &un->offload_timeout; -- table[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD_PICKUP].data = &un->offload_pickup; - #endif - - nf_conntrack_standalone_init_tcp_sysctl(net, table); ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -182,20 +182,25 @@ static void flow_offload_fixup_ct_timeou - { - struct net *net = nf_ct_net(ct); - int l4num = nf_ct_protonum(ct); -- unsigned int timeout; -+ s32 timeout; - - if (l4num == IPPROTO_TCP) { - struct nf_tcp_net *tn = nf_tcp_pernet(net); - -- timeout = tn->offload_pickup; -+ timeout = tn->timeouts[TCP_CONNTRACK_ESTABLISHED]; -+ timeout -= tn->offload_timeout; - } else if (l4num == IPPROTO_UDP) { - struct nf_udp_net *tn = nf_udp_pernet(net); - -- timeout = tn->offload_pickup; -+ timeout = tn->timeouts[UDP_CT_REPLIED]; -+ timeout -= tn->offload_timeout; - } else { - return; - } - -+ if (timeout < 0) -+ timeout = 0; -+ - if (nf_flow_timeout_delta(READ_ONCE(ct->timeout)) > (__s32)timeout) - WRITE_ONCE(ct->timeout, nfct_time_stamp + timeout); - } diff --git a/target/linux/generic/backport-5.10/614-v5.18-netfilter-flowtable-fix-TCP-flow-teardown.patch b/target/linux/generic/backport-5.10/614-v5.18-netfilter-flowtable-fix-TCP-flow-teardown.patch deleted file mode 100644 index 1b422ca4af..0000000000 --- a/target/linux/generic/backport-5.10/614-v5.18-netfilter-flowtable-fix-TCP-flow-teardown.patch +++ /dev/null @@ -1,166 +0,0 @@ -From b8835ba8c029b5c9ada5666754526c2b00f7ea80 Mon Sep 17 00:00:00 2001 -From: Pablo Neira Ayuso -Date: Tue, 17 May 2022 10:44:14 +0200 -Subject: netfilter: flowtable: fix TCP flow teardown - -[ Upstream commit e5eaac2beb54f0a16ff851125082d9faeb475572 ] - -This patch addresses three possible problems: - -1. ct gc may race to undo the timeout adjustment of the packet path, leaving - the conntrack entry in place with the internal offload timeout (one day). - -2. ct gc removes the ct because the IPS_OFFLOAD_BIT is not set and the CLOSE - timeout is reached before the flow offload del. - -3. tcp ct is always set to ESTABLISHED with a very long timeout - in flow offload teardown/delete even though the state might be already - CLOSED. Also as a remark we cannot assume that the FIN or RST packet - is hitting flow table teardown as the packet might get bumped to the - slow path in nftables. - -This patch resets IPS_OFFLOAD_BIT from flow_offload_teardown(), so -conntrack handles the tcp rst/fin packet which triggers the CLOSE/FIN -state transition. - -Moreover, teturn the connection's ownership to conntrack upon teardown -by clearing the offload flag and fixing the established timeout value. -The flow table GC thread will asynchonrnously free the flow table and -hardware offload entries. - -Before this patch, the IPS_OFFLOAD_BIT remained set for expired flows on -which is also misleading since the flow is back to classic conntrack -path. - -If nf_ct_delete() removes the entry from the conntrack table, then it -calls nf_ct_put() which decrements the refcnt. This is not a problem -because the flowtable holds a reference to the conntrack object from -flow_offload_alloc() path which is released via flow_offload_free(). - -This patch also updates nft_flow_offload to skip packets in SYN_RECV -state. Since we might miss or bump packets to slow path, we do not know -what will happen there while we are still in SYN_RECV, this patch -postpones offload up to the next packet which also aligns to the -existing behaviour in tc-ct. - -flow_offload_teardown() does not reset the existing tcp state from -flow_offload_fixup_tcp() to ESTABLISHED anymore, packets bump to slow -path might have already update the state to CLOSE/FIN. - -Joint work with Oz and Sven. - -Fixes: 1e5b2471bcc4 ("netfilter: nf_flow_table: teardown flow timeout race") -Signed-off-by: Oz Shlomo -Signed-off-by: Sven Auhagen -Signed-off-by: Pablo Neira Ayuso -Signed-off-by: Sasha Levin ---- - net/netfilter/nf_flow_table_core.c | 33 +++++++----------------------- - net/netfilter/nft_flow_offload.c | 3 ++- - 2 files changed, 9 insertions(+), 27 deletions(-) - ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -173,12 +173,11 @@ EXPORT_SYMBOL_GPL(flow_offload_route_ini - - static void flow_offload_fixup_tcp(struct ip_ct_tcp *tcp) - { -- tcp->state = TCP_CONNTRACK_ESTABLISHED; - tcp->seen[0].td_maxwin = 0; - tcp->seen[1].td_maxwin = 0; - } - --static void flow_offload_fixup_ct_timeout(struct nf_conn *ct) -+static void flow_offload_fixup_ct(struct nf_conn *ct) - { - struct net *net = nf_ct_net(ct); - int l4num = nf_ct_protonum(ct); -@@ -187,7 +186,9 @@ static void flow_offload_fixup_ct_timeou - if (l4num == IPPROTO_TCP) { - struct nf_tcp_net *tn = nf_tcp_pernet(net); - -- timeout = tn->timeouts[TCP_CONNTRACK_ESTABLISHED]; -+ flow_offload_fixup_tcp(&ct->proto.tcp); -+ -+ timeout = tn->timeouts[ct->proto.tcp.state]; - timeout -= tn->offload_timeout; - } else if (l4num == IPPROTO_UDP) { - struct nf_udp_net *tn = nf_udp_pernet(net); -@@ -205,18 +206,6 @@ static void flow_offload_fixup_ct_timeou - WRITE_ONCE(ct->timeout, nfct_time_stamp + timeout); - } - --static void flow_offload_fixup_ct_state(struct nf_conn *ct) --{ -- if (nf_ct_protonum(ct) == IPPROTO_TCP) -- flow_offload_fixup_tcp(&ct->proto.tcp); --} -- --static void flow_offload_fixup_ct(struct nf_conn *ct) --{ -- flow_offload_fixup_ct_state(ct); -- flow_offload_fixup_ct_timeout(ct); --} -- - static void flow_offload_route_release(struct flow_offload *flow) - { - nft_flow_dst_release(flow, FLOW_OFFLOAD_DIR_ORIGINAL); -@@ -353,22 +342,14 @@ static void flow_offload_del(struct nf_f - rhashtable_remove_fast(&flow_table->rhashtable, - &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].node, - nf_flow_offload_rhash_params); -- -- clear_bit(IPS_OFFLOAD_BIT, &flow->ct->status); -- -- if (nf_flow_has_expired(flow)) -- flow_offload_fixup_ct(flow->ct); -- else -- flow_offload_fixup_ct_timeout(flow->ct); -- - flow_offload_free(flow); - } - - void flow_offload_teardown(struct flow_offload *flow) - { -+ clear_bit(IPS_OFFLOAD_BIT, &flow->ct->status); - set_bit(NF_FLOW_TEARDOWN, &flow->flags); -- -- flow_offload_fixup_ct_state(flow->ct); -+ flow_offload_fixup_ct(flow->ct); - } - EXPORT_SYMBOL_GPL(flow_offload_teardown); - -@@ -437,7 +418,7 @@ static void nf_flow_offload_gc_step(stru - - if (nf_flow_has_expired(flow) || - nf_ct_is_dying(flow->ct)) -- set_bit(NF_FLOW_TEARDOWN, &flow->flags); -+ flow_offload_teardown(flow); - - if (test_bit(NF_FLOW_TEARDOWN, &flow->flags)) { - if (test_bit(NF_FLOW_HW, &flow->flags)) { ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -268,6 +268,12 @@ static bool nft_flow_offload_skip(struct - return false; - } - -+static bool nf_conntrack_tcp_established(const struct nf_conn *ct) -+{ -+ return ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED && -+ test_bit(IPS_ASSURED_BIT, &ct->status); -+} -+ - static void nft_flow_offload_eval(const struct nft_expr *expr, - struct nft_regs *regs, - const struct nft_pktinfo *pkt) -@@ -293,7 +299,8 @@ static void nft_flow_offload_eval(const - case IPPROTO_TCP: - tcph = skb_header_pointer(pkt->skb, pkt->xt.thoff, - sizeof(_tcph), &_tcph); -- if (unlikely(!tcph || tcph->fin || tcph->rst)) -+ if (unlikely(!tcph || tcph->fin || tcph->rst || -+ !nf_conntrack_tcp_established(ct))) - goto out; - break; - case IPPROTO_UDP: diff --git a/target/linux/generic/backport-5.10/615-v5.14-ip-Treat-IPv4-segment-s-lowest-address-as-unicast.patch b/target/linux/generic/backport-5.10/615-v5.14-ip-Treat-IPv4-segment-s-lowest-address-as-unicast.patch deleted file mode 100644 index 76e50d15eb..0000000000 --- a/target/linux/generic/backport-5.10/615-v5.14-ip-Treat-IPv4-segment-s-lowest-address-as-unicast.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 94c821c74bf5fe0c25e09df5334a16f98608db90 Mon Sep 17 00:00:00 2001 -From: Seth David Schoen -Date: Wed, 12 May 2021 21:37:49 -0700 -Subject: [PATCH] ip: Treat IPv4 segment's lowest address as unicast - -Treat only the highest, not the lowest, IPv4 address within a local -subnet as a broadcast address. - -Signed-off-by: Seth David Schoen -Suggested-by: John Gilmore -Acked-by: Dave Taht -Reviewed-by: David Ahern -Signed-off-by: David S. Miller -Link: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=94c821c74bf5 ---- - net/ipv4/fib_frontend.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/net/ipv4/fib_frontend.c -+++ b/net/ipv4/fib_frontend.c -@@ -1132,10 +1132,8 @@ void fib_add_ifaddr(struct in_ifaddr *if - prefix, ifa->ifa_prefixlen, prim, - ifa->ifa_rt_priority); - -- /* Add network specific broadcasts, when it takes a sense */ -+ /* Add the network broadcast address, when it makes sense */ - if (ifa->ifa_prefixlen < 31) { -- fib_magic(RTM_NEWROUTE, RTN_BROADCAST, prefix, 32, -- prim, 0); - fib_magic(RTM_NEWROUTE, RTN_BROADCAST, prefix | ~mask, - 32, prim, 0); - arp_invalidate(dev, prefix | ~mask, false); diff --git a/target/linux/generic/backport-5.10/630-v5.15-page_pool_frag_support.patch b/target/linux/generic/backport-5.10/630-v5.15-page_pool_frag_support.patch deleted file mode 100644 index dad4803848..0000000000 --- a/target/linux/generic/backport-5.10/630-v5.15-page_pool_frag_support.patch +++ /dev/null @@ -1,798 +0,0 @@ ---- a/include/net/page_pool.h -+++ b/include/net/page_pool.h -@@ -45,7 +45,10 @@ - * Please note DMA-sync-for-CPU is still - * device driver responsibility - */ --#define PP_FLAG_ALL (PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV) -+#define PP_FLAG_PAGE_FRAG BIT(2) /* for page frag feature */ -+#define PP_FLAG_ALL (PP_FLAG_DMA_MAP |\ -+ PP_FLAG_DMA_SYNC_DEV |\ -+ PP_FLAG_PAGE_FRAG) - - /* - * Fast allocation side cache array/stack -@@ -65,7 +68,7 @@ - #define PP_ALLOC_CACHE_REFILL 64 - struct pp_alloc_cache { - u32 count; -- void *cache[PP_ALLOC_CACHE_SIZE]; -+ struct page *cache[PP_ALLOC_CACHE_SIZE]; - }; - - struct page_pool_params { -@@ -79,6 +82,22 @@ struct page_pool_params { - unsigned int offset; /* DMA addr offset */ - }; - -+ -+static inline int page_pool_ethtool_stats_get_count(void) -+{ -+ return 0; -+} -+ -+static inline u8 *page_pool_ethtool_stats_get_strings(u8 *data) -+{ -+ return data; -+} -+ -+static inline u64 *page_pool_ethtool_stats_get(u64 *data, void *stats) -+{ -+ return data; -+} -+ - struct page_pool { - struct page_pool_params p; - -@@ -88,6 +107,9 @@ struct page_pool { - unsigned long defer_warn; - - u32 pages_state_hold_cnt; -+ unsigned int frag_offset; -+ struct page *frag_page; -+ long frag_users; - - /* - * Data structure for allocation side -@@ -137,6 +159,18 @@ static inline struct page *page_pool_dev - return page_pool_alloc_pages(pool, gfp); - } - -+struct page *page_pool_alloc_frag(struct page_pool *pool, unsigned int *offset, -+ unsigned int size, gfp_t gfp); -+ -+static inline struct page *page_pool_dev_alloc_frag(struct page_pool *pool, -+ unsigned int *offset, -+ unsigned int size) -+{ -+ gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); -+ -+ return page_pool_alloc_frag(pool, offset, size, gfp); -+} -+ - /* get the stored dma direction. A driver might decide to treat this locally and - * avoid the extra cache line from page_pool to determine the direction - */ -@@ -146,6 +180,8 @@ inline enum dma_data_direction page_pool - return pool->p.dma_dir; - } - -+bool page_pool_return_skb_page(struct page *page); -+ - struct page_pool *page_pool_create(const struct page_pool_params *params); - - #ifdef CONFIG_PAGE_POOL -@@ -165,6 +201,7 @@ static inline void page_pool_release_pag - struct page *page) - { - } -+ - #endif - - void page_pool_put_page(struct page_pool *pool, struct page *page, -@@ -189,19 +226,48 @@ static inline void page_pool_recycle_dir - page_pool_put_full_page(pool, page, true); - } - -+#define PAGE_POOL_DMA_USE_PP_FRAG_COUNT \ -+ (sizeof(dma_addr_t) > sizeof(unsigned long)) -+ - static inline dma_addr_t page_pool_get_dma_addr(struct page *page) - { -- dma_addr_t ret = page->dma_addr[0]; -- if (sizeof(dma_addr_t) > sizeof(unsigned long)) -- ret |= (dma_addr_t)page->dma_addr[1] << 16 << 16; -+ dma_addr_t ret = page->dma_addr; -+ -+ if (PAGE_POOL_DMA_USE_PP_FRAG_COUNT) -+ ret |= (dma_addr_t)page->dma_addr_upper << 16 << 16; -+ - return ret; - } - - static inline void page_pool_set_dma_addr(struct page *page, dma_addr_t addr) - { -- page->dma_addr[0] = addr; -- if (sizeof(dma_addr_t) > sizeof(unsigned long)) -- page->dma_addr[1] = upper_32_bits(addr); -+ page->dma_addr = addr; -+ if (PAGE_POOL_DMA_USE_PP_FRAG_COUNT) -+ page->dma_addr_upper = upper_32_bits(addr); -+} -+ -+static inline void page_pool_set_frag_count(struct page *page, long nr) -+{ -+ atomic_long_set(&page->pp_frag_count, nr); -+} -+ -+static inline long page_pool_atomic_sub_frag_count_return(struct page *page, -+ long nr) -+{ -+ long ret; -+ -+ /* As suggested by Alexander, atomic_long_read() may cover up the -+ * reference count errors, so avoid calling atomic_long_read() in -+ * the cases of freeing or draining the page_frags, where we would -+ * not expect it to match or that are slowpath anyway. -+ */ -+ if (__builtin_constant_p(nr) && -+ atomic_long_read(&page->pp_frag_count) == nr) -+ return 0; -+ -+ ret = atomic_long_sub_return(nr, &page->pp_frag_count); -+ WARN_ON(ret < 0); -+ return ret; - } - - static inline bool is_page_pool_compiled_in(void) -@@ -225,4 +291,23 @@ static inline void page_pool_nid_changed - if (unlikely(pool->p.nid != new_nid)) - page_pool_update_nid(pool, new_nid); - } -+ -+static inline void page_pool_ring_lock(struct page_pool *pool) -+ __acquires(&pool->ring.producer_lock) -+{ -+ if (in_serving_softirq()) -+ spin_lock(&pool->ring.producer_lock); -+ else -+ spin_lock_bh(&pool->ring.producer_lock); -+} -+ -+static inline void page_pool_ring_unlock(struct page_pool *pool) -+ __releases(&pool->ring.producer_lock) -+{ -+ if (in_serving_softirq()) -+ spin_unlock(&pool->ring.producer_lock); -+ else -+ spin_unlock_bh(&pool->ring.producer_lock); -+} -+ - #endif /* _NET_PAGE_POOL_H */ ---- a/net/core/page_pool.c -+++ b/net/core/page_pool.c -@@ -11,16 +11,22 @@ - #include - - #include -+#include -+ - #include - #include - #include - #include /* for __put_page() */ -+#include -+#include - - #include - - #define DEFER_TIME (msecs_to_jiffies(1000)) - #define DEFER_WARN_INTERVAL (60 * HZ) - -+#define BIAS_MAX LONG_MAX -+ - static int page_pool_init(struct page_pool *pool, - const struct page_pool_params *params) - { -@@ -64,6 +70,10 @@ static int page_pool_init(struct page_po - */ - } - -+ if (PAGE_POOL_DMA_USE_PP_FRAG_COUNT && -+ pool->p.flags & PP_FLAG_PAGE_FRAG) -+ return -EINVAL; -+ - if (ptr_ring_init(&pool->ring, ring_qsize, GFP_KERNEL) < 0) - return -ENOMEM; - -@@ -180,40 +190,10 @@ static void page_pool_dma_sync_for_devic - pool->p.dma_dir); - } - --/* slow path */ --noinline --static struct page *__page_pool_alloc_pages_slow(struct page_pool *pool, -- gfp_t _gfp) -+static bool page_pool_dma_map(struct page_pool *pool, struct page *page) - { -- struct page *page; -- gfp_t gfp = _gfp; - dma_addr_t dma; - -- /* We could always set __GFP_COMP, and avoid this branch, as -- * prep_new_page() can handle order-0 with __GFP_COMP. -- */ -- if (pool->p.order) -- gfp |= __GFP_COMP; -- -- /* FUTURE development: -- * -- * Current slow-path essentially falls back to single page -- * allocations, which doesn't improve performance. This code -- * need bulk allocation support from the page allocator code. -- */ -- -- /* Cache was empty, do real allocation */ --#ifdef CONFIG_NUMA -- page = alloc_pages_node(pool->p.nid, gfp, pool->p.order); --#else -- page = alloc_pages(gfp, pool->p.order); --#endif -- if (!page) -- return NULL; -- -- if (!(pool->p.flags & PP_FLAG_DMA_MAP)) -- goto skip_dma_map; -- - /* Setup DMA mapping: use 'struct page' area for storing DMA-addr - * since dma_addr_t can be either 32 or 64 bits and does not always fit - * into page private data (i.e 32bit cpu with 64bit DMA caps) -@@ -222,22 +202,53 @@ static struct page *__page_pool_alloc_pa - dma = dma_map_page_attrs(pool->p.dev, page, 0, - (PAGE_SIZE << pool->p.order), - pool->p.dma_dir, DMA_ATTR_SKIP_CPU_SYNC); -- if (dma_mapping_error(pool->p.dev, dma)) { -- put_page(page); -- return NULL; -- } -+ if (dma_mapping_error(pool->p.dev, dma)) -+ return false; -+ - page_pool_set_dma_addr(page, dma); - - if (pool->p.flags & PP_FLAG_DMA_SYNC_DEV) - page_pool_dma_sync_for_device(pool, page, pool->p.max_len); - --skip_dma_map: -+ return true; -+} -+ -+static void page_pool_set_pp_info(struct page_pool *pool, -+ struct page *page) -+{ -+ page->pp = pool; -+ page->pp_magic |= PP_SIGNATURE; -+} -+ -+static void page_pool_clear_pp_info(struct page *page) -+{ -+ page->pp_magic = 0; -+ page->pp = NULL; -+} -+ -+/* slow path */ -+noinline -+static struct page *__page_pool_alloc_pages_slow(struct page_pool *pool, -+ gfp_t gfp) -+{ -+ struct page *page; -+ -+ gfp |= __GFP_COMP; -+ page = alloc_pages_node(pool->p.nid, gfp, pool->p.order); -+ if (unlikely(!page)) -+ return NULL; -+ -+ if ((pool->p.flags & PP_FLAG_DMA_MAP) && -+ unlikely(!page_pool_dma_map(pool, page))) { -+ put_page(page); -+ return NULL; -+ } -+ -+ page_pool_set_pp_info(pool, page); -+ - /* Track how many pages are held 'in-flight' */ - pool->pages_state_hold_cnt++; -- - trace_page_pool_state_hold(pool, page, pool->pages_state_hold_cnt); -- -- /* When page just alloc'ed is should/must have refcnt 1. */ - return page; - } - -@@ -302,10 +313,12 @@ void page_pool_release_page(struct page_ - DMA_ATTR_SKIP_CPU_SYNC); - page_pool_set_dma_addr(page, 0); - skip_dma_unmap: -+ page_pool_clear_pp_info(page); -+ - /* This may be the last page returned, releasing the pool, so - * it is not safe to reference pool afterwards. - */ -- count = atomic_inc_return(&pool->pages_state_release_cnt); -+ count = atomic_inc_return_relaxed(&pool->pages_state_release_cnt); - trace_page_pool_state_release(pool, page, count); - } - EXPORT_SYMBOL(page_pool_release_page); -@@ -331,7 +344,10 @@ static bool page_pool_recycle_in_ring(st - else - ret = ptr_ring_produce_bh(&pool->ring, page); - -- return (ret == 0) ? true : false; -+ if (!ret) -+ return true; -+ -+ return false; - } - - /* Only allow direct recycling in special circumstances, into the -@@ -350,46 +366,43 @@ static bool page_pool_recycle_in_cache(s - return true; - } - --/* page is NOT reusable when: -- * 1) allocated when system is under some pressure. (page_is_pfmemalloc) -- */ --static bool pool_page_reusable(struct page_pool *pool, struct page *page) --{ -- return !page_is_pfmemalloc(page); --} -- - /* If the page refcnt == 1, this will try to recycle the page. - * if PP_FLAG_DMA_SYNC_DEV is set, we'll try to sync the DMA area for - * the configured size min(dma_sync_size, pool->max_len). - * If the page refcnt != 1, then the page will be returned to memory - * subsystem. - */ --void page_pool_put_page(struct page_pool *pool, struct page *page, -- unsigned int dma_sync_size, bool allow_direct) --{ -+static __always_inline struct page * -+__page_pool_put_page(struct page_pool *pool, struct page *page, -+ unsigned int dma_sync_size, bool allow_direct) -+{ -+ /* It is not the last user for the page frag case */ -+ if (pool->p.flags & PP_FLAG_PAGE_FRAG && -+ page_pool_atomic_sub_frag_count_return(page, 1)) -+ return NULL; -+ - /* This allocator is optimized for the XDP mode that uses - * one-frame-per-page, but have fallbacks that act like the - * regular page allocator APIs. - * - * refcnt == 1 means page_pool owns page, and can recycle it. -+ * -+ * page is NOT reusable when allocated when system is under -+ * some pressure. (page_is_pfmemalloc) - */ -- if (likely(page_ref_count(page) == 1 && -- pool_page_reusable(pool, page))) { -+ if (likely(page_ref_count(page) == 1 && !page_is_pfmemalloc(page))) { - /* Read barrier done in page_ref_count / READ_ONCE */ - - if (pool->p.flags & PP_FLAG_DMA_SYNC_DEV) - page_pool_dma_sync_for_device(pool, page, - dma_sync_size); - -- if (allow_direct && in_serving_softirq()) -- if (page_pool_recycle_in_cache(page, pool)) -- return; -+ if (allow_direct && in_serving_softirq() && -+ page_pool_recycle_in_cache(page, pool)) -+ return NULL; - -- if (!page_pool_recycle_in_ring(pool, page)) { -- /* Cache full, fallback to free pages */ -- page_pool_return_page(pool, page); -- } -- return; -+ /* Page found as candidate for recycling */ -+ return page; - } - /* Fallback/non-XDP mode: API user have elevated refcnt. - * -@@ -407,9 +420,98 @@ void page_pool_put_page(struct page_pool - /* Do not replace this with page_pool_return_page() */ - page_pool_release_page(pool, page); - put_page(page); -+ -+ return NULL; -+} -+ -+void page_pool_put_page(struct page_pool *pool, struct page *page, -+ unsigned int dma_sync_size, bool allow_direct) -+{ -+ page = __page_pool_put_page(pool, page, dma_sync_size, allow_direct); -+ if (page && !page_pool_recycle_in_ring(pool, page)) -+ /* Cache full, fallback to free pages */ -+ page_pool_return_page(pool, page); - } - EXPORT_SYMBOL(page_pool_put_page); - -+static struct page *page_pool_drain_frag(struct page_pool *pool, -+ struct page *page) -+{ -+ long drain_count = BIAS_MAX - pool->frag_users; -+ -+ /* Some user is still using the page frag */ -+ if (likely(page_pool_atomic_sub_frag_count_return(page, -+ drain_count))) -+ return NULL; -+ -+ if (page_ref_count(page) == 1 && !page_is_pfmemalloc(page)) { -+ if (pool->p.flags & PP_FLAG_DMA_SYNC_DEV) -+ page_pool_dma_sync_for_device(pool, page, -1); -+ -+ return page; -+ } -+ -+ page_pool_return_page(pool, page); -+ return NULL; -+} -+ -+static void page_pool_free_frag(struct page_pool *pool) -+{ -+ long drain_count = BIAS_MAX - pool->frag_users; -+ struct page *page = pool->frag_page; -+ -+ pool->frag_page = NULL; -+ -+ if (!page || -+ page_pool_atomic_sub_frag_count_return(page, drain_count)) -+ return; -+ -+ page_pool_return_page(pool, page); -+} -+ -+struct page *page_pool_alloc_frag(struct page_pool *pool, -+ unsigned int *offset, -+ unsigned int size, gfp_t gfp) -+{ -+ unsigned int max_size = PAGE_SIZE << pool->p.order; -+ struct page *page = pool->frag_page; -+ -+ if (WARN_ON(!(pool->p.flags & PP_FLAG_PAGE_FRAG) || -+ size > max_size)) -+ return NULL; -+ -+ size = ALIGN(size, dma_get_cache_alignment()); -+ *offset = pool->frag_offset; -+ -+ if (page && *offset + size > max_size) { -+ page = page_pool_drain_frag(pool, page); -+ if (page) -+ goto frag_reset; -+ } -+ -+ if (!page) { -+ page = page_pool_alloc_pages(pool, gfp); -+ if (unlikely(!page)) { -+ pool->frag_page = NULL; -+ return NULL; -+ } -+ -+ pool->frag_page = page; -+ -+frag_reset: -+ pool->frag_users = 1; -+ *offset = 0; -+ pool->frag_offset = size; -+ page_pool_set_frag_count(page, BIAS_MAX); -+ return page; -+ } -+ -+ pool->frag_users++; -+ pool->frag_offset = *offset + size; -+ return page; -+} -+EXPORT_SYMBOL(page_pool_alloc_frag); -+ - static void page_pool_empty_ring(struct page_pool *pool) - { - struct page *page; -@@ -515,6 +617,8 @@ void page_pool_destroy(struct page_pool - if (!page_pool_put(pool)) - return; - -+ page_pool_free_frag(pool); -+ - if (!page_pool_release(pool)) - return; - -@@ -541,3 +645,32 @@ void page_pool_update_nid(struct page_po - } - } - EXPORT_SYMBOL(page_pool_update_nid); -+ -+bool page_pool_return_skb_page(struct page *page) -+{ -+ struct page_pool *pp; -+ -+ page = compound_head(page); -+ -+ /* page->pp_magic is OR'ed with PP_SIGNATURE after the allocation -+ * in order to preserve any existing bits, such as bit 0 for the -+ * head page of compound page and bit 1 for pfmemalloc page, so -+ * mask those bits for freeing side when doing below checking, -+ * and page_is_pfmemalloc() is checked in __page_pool_put_page() -+ * to avoid recycling the pfmemalloc page. -+ */ -+ if (unlikely((page->pp_magic & ~0x3UL) != PP_SIGNATURE)) -+ return false; -+ -+ pp = page->pp; -+ -+ /* Driver set this to memory recycling info. Reset it on recycle. -+ * This will *not* work for NIC using a split-page memory model. -+ * The page will be returned to the pool here regardless of the -+ * 'flipped' fragment being in use or not. -+ */ -+ page_pool_put_full_page(pp, page, false); -+ -+ return true; -+} -+EXPORT_SYMBOL(page_pool_return_skb_page); ---- a/include/linux/mm_types.h -+++ b/include/linux/mm_types.h -@@ -97,10 +97,25 @@ struct page { - }; - struct { /* page_pool used by netstack */ - /** -- * @dma_addr: might require a 64-bit value on -- * 32-bit architectures. -+ * @pp_magic: magic value to avoid recycling non -+ * page_pool allocated pages. - */ -- unsigned long dma_addr[2]; -+ unsigned long pp_magic; -+ struct page_pool *pp; -+ unsigned long _pp_mapping_pad; -+ unsigned long dma_addr; -+ union { -+ /** -+ * dma_addr_upper: might require a 64-bit -+ * value on 32-bit architectures. -+ */ -+ unsigned long dma_addr_upper; -+ /** -+ * For frag page support, not supported in -+ * 32-bit architectures with 64-bit DMA. -+ */ -+ atomic_long_t pp_frag_count; -+ }; - }; - struct { /* slab, slob and slub */ - union { ---- a/net/core/skbuff.c -+++ b/net/core/skbuff.c -@@ -594,13 +594,22 @@ static void skb_clone_fraglist(struct sk - skb_get(list); - } - -+static bool skb_pp_recycle(struct sk_buff *skb, void *data) -+{ -+ if (!IS_ENABLED(CONFIG_PAGE_POOL) || !skb->pp_recycle) -+ return false; -+ return page_pool_return_skb_page(virt_to_page(data)); -+} -+ - static void skb_free_head(struct sk_buff *skb) - { - unsigned char *head = skb->head; - -- if (skb->head_frag) -+ if (skb->head_frag) { -+ if (skb_pp_recycle(skb, head)) -+ return; - skb_free_frag(head); -- else -+ } else - kfree(head); - } - -@@ -612,16 +621,27 @@ static void skb_release_data(struct sk_b - if (skb->cloned && - atomic_sub_return(skb->nohdr ? (1 << SKB_DATAREF_SHIFT) + 1 : 1, - &shinfo->dataref)) -- return; -+ goto exit; - - for (i = 0; i < shinfo->nr_frags; i++) -- __skb_frag_unref(&shinfo->frags[i]); -+ __skb_frag_unref(&shinfo->frags[i], skb->pp_recycle); - - if (shinfo->frag_list) - kfree_skb_list(shinfo->frag_list); - - skb_zcopy_clear(skb, true); - skb_free_head(skb); -+exit: -+ /* When we clone an SKB we copy the reycling bit. The pp_recycle -+ * bit is only set on the head though, so in order to avoid races -+ * while trying to recycle fragments on __skb_frag_unref() we need -+ * to make one SKB responsible for triggering the recycle path. -+ * So disable the recycling bit if an SKB is cloned and we have -+ * additional references to to the fragmented part of the SKB. -+ * Eventually the last SKB will have the recycling bit set and it's -+ * dataref set to 0, which will trigger the recycling -+ */ -+ skb->pp_recycle = 0; - } - - /* -@@ -1002,6 +1022,7 @@ static struct sk_buff *__skb_clone(struc - n->nohdr = 0; - n->peeked = 0; - C(pfmemalloc); -+ C(pp_recycle); - n->destructor = NULL; - C(tail); - C(end); -@@ -3420,7 +3441,7 @@ int skb_shift(struct sk_buff *tgt, struc - fragto = &skb_shinfo(tgt)->frags[merge]; - - skb_frag_size_add(fragto, skb_frag_size(fragfrom)); -- __skb_frag_unref(fragfrom); -+ __skb_frag_unref(fragfrom, skb->pp_recycle); - } - - /* Reposition in the original skb */ -@@ -5187,6 +5208,20 @@ bool skb_try_coalesce(struct sk_buff *to - if (skb_cloned(to)) - return false; - -+ /* In general, avoid mixing slab allocated and page_pool allocated -+ * pages within the same SKB. However when @to is not pp_recycle and -+ * @from is cloned, we can transition frag pages from page_pool to -+ * reference counted. -+ * -+ * On the other hand, don't allow coalescing two pp_recycle SKBs if -+ * @from is cloned, in case the SKB is using page_pool fragment -+ * references (PP_FLAG_PAGE_FRAG). Since we only take full page -+ * references for cloned SKBs at the moment that would result in -+ * inconsistent reference counts. -+ */ -+ if (to->pp_recycle != (from->pp_recycle && !skb_cloned(from))) -+ return false; -+ - if (len <= skb_tailroom(to)) { - if (len) - BUG_ON(skb_copy_bits(from, 0, skb_put(to, len), len)); ---- a/include/linux/skbuff.h -+++ b/include/linux/skbuff.h -@@ -37,6 +37,7 @@ - #include - #include - #include -+#include - #if IS_ENABLED(CONFIG_NF_CONNTRACK) - #include - #endif -@@ -787,7 +788,8 @@ struct sk_buff { - fclone:2, - peeked:1, - head_frag:1, -- pfmemalloc:1; -+ pfmemalloc:1, -+ pp_recycle:1; /* page_pool recycle indicator */ - #ifdef CONFIG_SKB_EXTENSIONS - __u8 active_extensions; - #endif -@@ -3030,9 +3032,15 @@ static inline void skb_frag_ref(struct s - * - * Releases a reference on the paged fragment @frag. - */ --static inline void __skb_frag_unref(skb_frag_t *frag) -+static inline void __skb_frag_unref(skb_frag_t *frag, bool recycle) - { -- put_page(skb_frag_page(frag)); -+ struct page *page = skb_frag_page(frag); -+ -+#ifdef CONFIG_PAGE_POOL -+ if (recycle && page_pool_return_skb_page(page)) -+ return; -+#endif -+ put_page(page); - } - - /** -@@ -3044,7 +3052,7 @@ static inline void __skb_frag_unref(skb_ - */ - static inline void skb_frag_unref(struct sk_buff *skb, int f) - { -- __skb_frag_unref(&skb_shinfo(skb)->frags[f]); -+ __skb_frag_unref(&skb_shinfo(skb)->frags[f], skb->pp_recycle); - } - - /** -@@ -4643,5 +4651,12 @@ static inline u64 skb_get_kcov_handle(st - #endif - } - -+#ifdef CONFIG_PAGE_POOL -+static inline void skb_mark_for_recycle(struct sk_buff *skb) -+{ -+ skb->pp_recycle = 1; -+} -+#endif -+ - #endif /* __KERNEL__ */ - #endif /* _LINUX_SKBUFF_H */ ---- a/drivers/net/ethernet/marvell/sky2.c -+++ b/drivers/net/ethernet/marvell/sky2.c -@@ -2501,7 +2501,7 @@ static void skb_put_frags(struct sk_buff - - if (length == 0) { - /* don't need this page */ -- __skb_frag_unref(frag); -+ __skb_frag_unref(frag, false); - --skb_shinfo(skb)->nr_frags; - } else { - size = min(length, (unsigned) PAGE_SIZE); ---- a/drivers/net/ethernet/mellanox/mlx4/en_rx.c -+++ b/drivers/net/ethernet/mellanox/mlx4/en_rx.c -@@ -526,7 +526,7 @@ static int mlx4_en_complete_rx_desc(stru - fail: - while (nr > 0) { - nr--; -- __skb_frag_unref(skb_shinfo(skb)->frags + nr); -+ __skb_frag_unref(skb_shinfo(skb)->frags + nr, false); - } - return 0; - } ---- a/net/tls/tls_device.c -+++ b/net/tls/tls_device.c -@@ -131,7 +131,7 @@ static void destroy_record(struct tls_re - int i; - - for (i = 0; i < record->num_frags; i++) -- __skb_frag_unref(&record->frags[i]); -+ __skb_frag_unref(&record->frags[i], false); - kfree(record); - } - ---- a/include/linux/poison.h -+++ b/include/linux/poison.h -@@ -82,4 +82,7 @@ - /********** security/ **********/ - #define KEY_DESTROY 0xbd - -+/********** net/core/page_pool.c **********/ -+#define PP_SIGNATURE (0x40 + POISON_POINTER_DELTA) -+ - #endif ---- a/include/linux/mm.h -+++ b/include/linux/mm.h -@@ -1602,7 +1602,7 @@ static inline bool page_is_pfmemalloc(st - * Page index cannot be this large so this must be - * a pfmemalloc page. - */ -- return page->index == -1UL; -+ return (uintptr_t)page->lru.next & BIT(1); - } - - /* -@@ -1611,12 +1611,12 @@ static inline bool page_is_pfmemalloc(st - */ - static inline void set_page_pfmemalloc(struct page *page) - { -- page->index = -1UL; -+ page->lru.next = (void *)BIT(1); - } - - static inline void clear_page_pfmemalloc(struct page *page) - { -- page->index = 0; -+ page->lru.next = NULL; - } - - /* diff --git a/target/linux/generic/backport-5.10/631-v6.3-net-page_pool-use-in_softirq-instead.patch b/target/linux/generic/backport-5.10/631-v6.3-net-page_pool-use-in_softirq-instead.patch deleted file mode 100644 index e0d5b2451b..0000000000 --- a/target/linux/generic/backport-5.10/631-v6.3-net-page_pool-use-in_softirq-instead.patch +++ /dev/null @@ -1,56 +0,0 @@ -From: Qingfang DENG -Date: Fri, 3 Feb 2023 09:16:11 +0800 -Subject: [PATCH] net: page_pool: use in_softirq() instead - -We use BH context only for synchronization, so we don't care if it's -actually serving softirq or not. - -As a side node, in case of threaded NAPI, in_serving_softirq() will -return false because it's in process context with BH off, making -page_pool_recycle_in_cache() unreachable. - -Signed-off-by: Qingfang DENG ---- - ---- a/include/net/page_pool.h -+++ b/include/net/page_pool.h -@@ -295,7 +295,7 @@ static inline void page_pool_nid_changed - static inline void page_pool_ring_lock(struct page_pool *pool) - __acquires(&pool->ring.producer_lock) - { -- if (in_serving_softirq()) -+ if (in_softirq()) - spin_lock(&pool->ring.producer_lock); - else - spin_lock_bh(&pool->ring.producer_lock); -@@ -304,7 +304,7 @@ static inline void page_pool_ring_lock(s - static inline void page_pool_ring_unlock(struct page_pool *pool) - __releases(&pool->ring.producer_lock) - { -- if (in_serving_softirq()) -+ if (in_softirq()) - spin_unlock(&pool->ring.producer_lock); - else - spin_unlock_bh(&pool->ring.producer_lock); ---- a/net/core/page_pool.c -+++ b/net/core/page_pool.c -@@ -338,8 +338,8 @@ static void page_pool_return_page(struct - static bool page_pool_recycle_in_ring(struct page_pool *pool, struct page *page) - { - int ret; -- /* BH protection not needed if current is serving softirq */ -- if (in_serving_softirq()) -+ /* BH protection not needed if current is softirq */ -+ if (in_softirq()) - ret = ptr_ring_produce(&pool->ring, page); - else - ret = ptr_ring_produce_bh(&pool->ring, page); -@@ -397,7 +397,7 @@ __page_pool_put_page(struct page_pool *p - page_pool_dma_sync_for_device(pool, page, - dma_sync_size); - -- if (allow_direct && in_serving_softirq() && -+ if (allow_direct && in_softirq() && - page_pool_recycle_in_cache(page, pool)) - return NULL; - diff --git a/target/linux/generic/backport-5.10/632-v6.3-net-add-helper-eth_addr_add.patch b/target/linux/generic/backport-5.10/632-v6.3-net-add-helper-eth_addr_add.patch deleted file mode 100644 index ac556e53af..0000000000 --- a/target/linux/generic/backport-5.10/632-v6.3-net-add-helper-eth_addr_add.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 7390609b0121a1b982c5ecdfcd72dc328e5784ee Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 6 Feb 2023 13:43:42 +0000 -Subject: [PATCH] net: add helper eth_addr_add() - -Add a helper to add an offset to a ethernet address. This comes in handy -if you have a base ethernet address for multiple interfaces. - -Signed-off-by: Michael Walle -Reviewed-by: Andrew Lunn -Acked-by: Jakub Kicinski -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-9-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - include/linux/etherdevice.h | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/include/linux/etherdevice.h -+++ b/include/linux/etherdevice.h -@@ -466,6 +466,20 @@ static inline void eth_addr_inc(u8 *addr - } - - /** -+ * eth_addr_add() - Add (or subtract) an offset to/from the given MAC address. -+ * -+ * @offset: Offset to add. -+ * @addr: Pointer to a six-byte array containing Ethernet address to increment. -+ */ -+static inline void eth_addr_add(u8 *addr, long offset) -+{ -+ u64 u = ether_addr_to_u64(addr); -+ -+ u += offset; -+ u64_to_ether_addr(u, addr); -+} -+ -+/** - * is_etherdev_addr - Tell if given Ethernet address belongs to the device. - * @dev: Pointer to a device structure - * @addr: Pointer to a six-byte array containing the Ethernet address diff --git a/target/linux/generic/backport-5.10/633-v6.3-skbuff-Fix-a-race-between-coalescing-and-releasing-S.patch b/target/linux/generic/backport-5.10/633-v6.3-skbuff-Fix-a-race-between-coalescing-and-releasing-S.patch deleted file mode 100644 index 2ad315d7f9..0000000000 --- a/target/linux/generic/backport-5.10/633-v6.3-skbuff-Fix-a-race-between-coalescing-and-releasing-S.patch +++ /dev/null @@ -1,85 +0,0 @@ -From: Liang Chen -Date: Thu, 13 Apr 2023 17:03:53 +0800 -Subject: [PATCH] skbuff: Fix a race between coalescing and releasing SKBs - -Commit 1effe8ca4e34 ("skbuff: fix coalescing for page_pool fragment -recycling") allowed coalescing to proceed with non page pool page and page -pool page when @from is cloned, i.e. - -to->pp_recycle --> false -from->pp_recycle --> true -skb_cloned(from) --> true - -However, it actually requires skb_cloned(@from) to hold true until -coalescing finishes in this situation. If the other cloned SKB is -released while the merging is in process, from_shinfo->nr_frags will be -set to 0 toward the end of the function, causing the increment of frag -page _refcount to be unexpectedly skipped resulting in inconsistent -reference counts. Later when SKB(@to) is released, it frees the page -directly even though the page pool page is still in use, leading to -use-after-free or double-free errors. So it should be prohibited. - -The double-free error message below prompted us to investigate: -BUG: Bad page state in process swapper/1 pfn:0e0d1 -page:00000000c6548b28 refcount:-1 mapcount:0 mapping:0000000000000000 -index:0x2 pfn:0xe0d1 -flags: 0xfffffc0000000(node=0|zone=1|lastcpupid=0x1fffff) -raw: 000fffffc0000000 0000000000000000 ffffffff00000101 0000000000000000 -raw: 0000000000000002 0000000000000000 ffffffffffffffff 0000000000000000 -page dumped because: nonzero _refcount - -CPU: 1 PID: 0 Comm: swapper/1 Tainted: G E 6.2.0+ -Call Trace: - -dump_stack_lvl+0x32/0x50 -bad_page+0x69/0xf0 -free_pcp_prepare+0x260/0x2f0 -free_unref_page+0x20/0x1c0 -skb_release_data+0x10b/0x1a0 -napi_consume_skb+0x56/0x150 -net_rx_action+0xf0/0x350 -? __napi_schedule+0x79/0x90 -__do_softirq+0xc8/0x2b1 -__irq_exit_rcu+0xb9/0xf0 -common_interrupt+0x82/0xa0 - - -asm_common_interrupt+0x22/0x40 -RIP: 0010:default_idle+0xb/0x20 - -Fixes: 53e0961da1c7 ("page_pool: add frag page recycling support in page pool") -Signed-off-by: Liang Chen -Reviewed-by: Eric Dumazet -Link: https://lore.kernel.org/r/20230413090353.14448-1-liangchen.linux@gmail.com -Signed-off-by: Jakub Kicinski ---- - ---- a/net/core/skbuff.c -+++ b/net/core/skbuff.c -@@ -5208,18 +5208,18 @@ bool skb_try_coalesce(struct sk_buff *to - if (skb_cloned(to)) - return false; - -- /* In general, avoid mixing slab allocated and page_pool allocated -- * pages within the same SKB. However when @to is not pp_recycle and -- * @from is cloned, we can transition frag pages from page_pool to -- * reference counted. -- * -- * On the other hand, don't allow coalescing two pp_recycle SKBs if -- * @from is cloned, in case the SKB is using page_pool fragment -+ /* In general, avoid mixing page_pool and non-page_pool allocated -+ * pages within the same SKB. Additionally avoid dealing with clones -+ * with page_pool pages, in case the SKB is using page_pool fragment - * references (PP_FLAG_PAGE_FRAG). Since we only take full page - * references for cloned SKBs at the moment that would result in - * inconsistent reference counts. -+ * In theory we could take full references if @from is cloned and -+ * !@to->pp_recycle but its tricky (due to potential race with -+ * the clone disappearing) and rare, so not worth dealing with. - */ -- if (to->pp_recycle != (from->pp_recycle && !skb_cloned(from))) -+ if (to->pp_recycle != from->pp_recycle || -+ (from->pp_recycle && skb_cloned(from))) - return false; - - if (len <= skb_tailroom(to)) { diff --git a/target/linux/generic/backport-5.10/705-net-phy-at803x-select-correct-page-on-config-init.patch b/target/linux/generic/backport-5.10/705-net-phy-at803x-select-correct-page-on-config-init.patch deleted file mode 100644 index 00be403299..0000000000 --- a/target/linux/generic/backport-5.10/705-net-phy-at803x-select-correct-page-on-config-init.patch +++ /dev/null @@ -1,108 +0,0 @@ -From c329e5afb42ff0a88285eb4d8a391a18793e4777 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Thu, 15 Apr 2021 03:26:50 +0200 -Subject: [PATCH] net: phy: at803x: select correct page on config init - -The Atheros AR8031 and AR8033 expose different registers for SGMII/Fiber -as well as the copper side of the PHY depending on the BT_BX_REG_SEL bit -in the chip configure register. - -The driver assumes the copper side is selected on probe, but this might -not be the case depending which page was last selected by the -bootloader. Notably, Ubiquiti UniFi bootloaders show this behavior. - -Select the copper page when probing to circumvent this. - -Signed-off-by: David Bauer -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 50 +++++++++++++++++++++++++++++++++++++++- - 1 file changed, 49 insertions(+), 1 deletion(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -139,6 +139,9 @@ - #define ATH8035_PHY_ID 0x004dd072 - #define AT8030_PHY_ID_MASK 0xffffffef - -+#define AT803X_PAGE_FIBER 0 -+#define AT803X_PAGE_COPPER 1 -+ - MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); - MODULE_AUTHOR("Matus Ujhelyi"); - MODULE_LICENSE("GPL"); -@@ -190,6 +193,35 @@ static int at803x_debug_reg_mask(struct - return phy_write(phydev, AT803X_DEBUG_DATA, val); - } - -+static int at803x_write_page(struct phy_device *phydev, int page) -+{ -+ int mask; -+ int set; -+ -+ if (page == AT803X_PAGE_COPPER) { -+ set = AT803X_BT_BX_REG_SEL; -+ mask = 0; -+ } else { -+ set = 0; -+ mask = AT803X_BT_BX_REG_SEL; -+ } -+ -+ return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set); -+} -+ -+static int at803x_read_page(struct phy_device *phydev) -+{ -+ int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG); -+ -+ if (ccr < 0) -+ return ccr; -+ -+ if (ccr & AT803X_BT_BX_REG_SEL) -+ return AT803X_PAGE_COPPER; -+ -+ return AT803X_PAGE_FIBER; -+} -+ - static int at803x_enable_rx_delay(struct phy_device *phydev) - { - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, -@@ -508,6 +540,7 @@ static int at803x_probe(struct phy_devic - { - struct device *dev = &phydev->mdio.dev; - struct at803x_priv *priv; -+ int ret; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) -@@ -515,7 +548,20 @@ static int at803x_probe(struct phy_devic - - phydev->priv = priv; - -- return at803x_parse_dt(phydev); -+ ret = at803x_parse_dt(phydev); -+ if (ret) -+ return ret; -+ -+ /* Some bootloaders leave the fiber page selected. -+ * Switch to the copper page, as otherwise we read -+ * the PHY capabilities from the fiber side. -+ */ -+ if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { -+ ret = phy_select_page(phydev, AT803X_PAGE_COPPER); -+ ret = phy_restore_page(phydev, AT803X_PAGE_COPPER, ret); -+ } -+ -+ return ret; - } - - static void at803x_remove(struct phy_device *phydev) -@@ -1097,6 +1143,8 @@ static struct phy_driver at803x_driver[] - .get_wol = at803x_get_wol, - .suspend = at803x_suspend, - .resume = at803x_resume, -+ .read_page = at803x_read_page, -+ .write_page = at803x_write_page, - /* PHY_GBIT_FEATURES */ - .read_status = at803x_read_status, - .aneg_done = at803x_aneg_done, diff --git a/target/linux/generic/backport-5.10/706-net-phy-at803x-fix-probe-error-if-copper-page-is-sel.patch b/target/linux/generic/backport-5.10/706-net-phy-at803x-fix-probe-error-if-copper-page-is-sel.patch deleted file mode 100644 index d6ec7450e8..0000000000 --- a/target/linux/generic/backport-5.10/706-net-phy-at803x-fix-probe-error-if-copper-page-is-sel.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 8f7e876273e294b732b42af2e5e6bba91d798954 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Tue, 20 Apr 2021 12:29:29 +0200 -Subject: [PATCH] net: phy: at803x: fix probe error if copper page is selected - -The commit c329e5afb42f ("net: phy: at803x: select correct page on -config init") selects the copper page during probe. This fails if the -copper page was already selected. In this case, the value of the copper -page (which is 1) is propagated through phy_restore_page() and is -finally returned for at803x_probe(). Fix it, by just using the -at803x_page_write() directly. - -Also in case of an error, the regulator is not disabled and leads to a -WARN_ON() when the probe fails. This couldn't happen before, because -at803x_parse_dt() was the last call in at803x_probe(). It is hard to -see, that the parse_dt() actually enables the regulator. Thus move the -regulator_enable() to the probe function and undo it in case of an -error. - -Fixes: c329e5afb42f ("net: phy: at803x: select correct page on config init") -Signed-off-by: Michael Walle -Reviewed-by: David Bauer -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 23 +++++++++++++++++------ - 1 file changed, 17 insertions(+), 6 deletions(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -527,10 +527,6 @@ static int at803x_parse_dt(struct phy_de - phydev_err(phydev, "failed to get VDDIO regulator\n"); - return PTR_ERR(priv->vddio); - } -- -- ret = regulator_enable(priv->vddio); -- if (ret < 0) -- return ret; - } - - return 0; -@@ -552,15 +548,30 @@ static int at803x_probe(struct phy_devic - if (ret) - return ret; - -+ if (priv->vddio) { -+ ret = regulator_enable(priv->vddio); -+ if (ret < 0) -+ return ret; -+ } -+ - /* Some bootloaders leave the fiber page selected. - * Switch to the copper page, as otherwise we read - * the PHY capabilities from the fiber side. - */ - if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { -- ret = phy_select_page(phydev, AT803X_PAGE_COPPER); -- ret = phy_restore_page(phydev, AT803X_PAGE_COPPER, ret); -+ phy_lock_mdio_bus(phydev); -+ ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); -+ phy_unlock_mdio_bus(phydev); -+ if (ret) -+ goto err; - } - -+ return 0; -+ -+err: -+ if (priv->vddio) -+ regulator_disable(priv->vddio); -+ - return ret; - } - diff --git a/target/linux/generic/backport-5.10/710-v5.12-net-phy-Add-100-base-x-mode.patch b/target/linux/generic/backport-5.10/710-v5.12-net-phy-Add-100-base-x-mode.patch deleted file mode 100644 index 5c7f97ea90..0000000000 --- a/target/linux/generic/backport-5.10/710-v5.12-net-phy-Add-100-base-x-mode.patch +++ /dev/null @@ -1,56 +0,0 @@ -From b1ae3587d16a8c8fc9453e147c8708d6f006ffbb Mon Sep 17 00:00:00 2001 -From: Bjarni Jonasson -Date: Wed, 13 Jan 2021 12:56:25 +0100 -Subject: [PATCH] net: phy: Add 100 base-x mode - -Sparx-5 supports this mode and it is missing in the PHY core. - -Signed-off-by: Bjarni Jonasson -Reviewed-by: Russell King -Signed-off-by: Jakub Kicinski ---- - Documentation/networking/phy.rst | 5 +++++ - include/linux/phy.h | 4 ++++ - 2 files changed, 9 insertions(+) - ---- a/Documentation/networking/phy.rst -+++ b/Documentation/networking/phy.rst -@@ -286,6 +286,11 @@ Some of the interface modes are describe - Note: due to legacy usage, some 10GBASE-R usage incorrectly makes - use of this definition. - -+``PHY_INTERFACE_MODE_100BASEX`` -+ This defines IEEE 802.3 Clause 24. The link operates at a fixed data -+ rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying -+ data rate of 100Mpbs. -+ - Pause frames / flow control - =========================== - ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -104,6 +104,7 @@ extern const int phy_10gbit_features_arr - * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax - * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII - * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII -+ * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX - * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX - * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX - * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI -@@ -135,6 +136,7 @@ typedef enum { - PHY_INTERFACE_MODE_MOCA, - PHY_INTERFACE_MODE_QSGMII, - PHY_INTERFACE_MODE_TRGMII, -+ PHY_INTERFACE_MODE_100BASEX, - PHY_INTERFACE_MODE_1000BASEX, - PHY_INTERFACE_MODE_2500BASEX, - PHY_INTERFACE_MODE_RXAUI, -@@ -217,6 +219,8 @@ static inline const char *phy_modes(phy_ - return "usxgmii"; - case PHY_INTERFACE_MODE_10GKR: - return "10gbase-kr"; -+ case PHY_INTERFACE_MODE_100BASEX: -+ return "100base-x"; - default: - return "unknown"; - } diff --git a/target/linux/generic/backport-5.10/711-v5.12-sfp-add-support-for-100-base-x-SFPs.patch b/target/linux/generic/backport-5.10/711-v5.12-sfp-add-support-for-100-base-x-SFPs.patch deleted file mode 100644 index 0c87532e13..0000000000 --- a/target/linux/generic/backport-5.10/711-v5.12-sfp-add-support-for-100-base-x-SFPs.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 6e12f35cef6b8a458d7ecf507ae330e0bffaad8c Mon Sep 17 00:00:00 2001 -From: Bjarni Jonasson -Date: Wed, 13 Jan 2021 12:56:26 +0100 -Subject: [PATCH] sfp: add support for 100 base-x SFPs - -Add support for 100Base-FX, 100Base-LX, 100Base-PX and 100Base-BX10 modules -This is needed for Sparx-5 switch. - -Signed-off-by: Bjarni Jonasson -Reviewed-by: Russell King -Signed-off-by: Jakub Kicinski ---- - drivers/net/phy/sfp-bus.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/drivers/net/phy/sfp-bus.c -+++ b/drivers/net/phy/sfp-bus.c -@@ -286,6 +286,12 @@ void sfp_parse_support(struct sfp_bus *b - br_min <= 1300 && br_max >= 1200) - phylink_set(modes, 1000baseX_Full); - -+ /* 100Base-FX, 100Base-LX, 100Base-PX, 100Base-BX10 */ -+ if (id->base.e100_base_fx || id->base.e100_base_lx) -+ phylink_set(modes, 100baseFX_Full); -+ if ((id->base.e_base_px || id->base.e_base_bx10) && br_nom == 100) -+ phylink_set(modes, 100baseFX_Full); -+ - /* For active or passive cables, select the link modes - * based on the bit rates and the cable compliance bytes. - */ -@@ -405,6 +411,9 @@ phy_interface_t sfp_select_interface(str - if (phylink_test(link_modes, 1000baseX_Full)) - return PHY_INTERFACE_MODE_1000BASEX; - -+ if (phylink_test(link_modes, 100baseFX_Full)) -+ return PHY_INTERFACE_MODE_100BASEX; -+ - dev_warn(bus->sfp_dev, "Unable to ascertain link mode\n"); - - return PHY_INTERFACE_MODE_NA; diff --git a/target/linux/generic/backport-5.10/712-v5.13-net-phy-marvell-refactor-HWMON-OOP-style.patch b/target/linux/generic/backport-5.10/712-v5.13-net-phy-marvell-refactor-HWMON-OOP-style.patch deleted file mode 100644 index 278df46313..0000000000 --- a/target/linux/generic/backport-5.10/712-v5.13-net-phy-marvell-refactor-HWMON-OOP-style.patch +++ /dev/null @@ -1,549 +0,0 @@ -From 41d26bf4aba070dfd2ab48866cc27a48ee6228c7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Tue, 20 Apr 2021 09:53:59 +0200 -Subject: [PATCH] net: phy: marvell: refactor HWMON OOP style -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Use a structure of Marvell PHY specific HWMON methods to reduce code -duplication. Store a pointer to this structure into the PHY driver's -driver_data member. - -Signed-off-by: Marek Behún -Signed-off-by: David S. Miller ---- - drivers/net/phy/marvell.c | 369 +++++++++++++------------------------- - 1 file changed, 125 insertions(+), 244 deletions(-) - ---- a/drivers/net/phy/marvell.c -+++ b/drivers/net/phy/marvell.c -@@ -2141,6 +2141,19 @@ static int marvell_vct7_cable_test_get_s - } - - #ifdef CONFIG_HWMON -+struct marvell_hwmon_ops { -+ int (*get_temp)(struct phy_device *phydev, long *temp); -+ int (*get_temp_critical)(struct phy_device *phydev, long *temp); -+ int (*set_temp_critical)(struct phy_device *phydev, long temp); -+ int (*get_temp_alarm)(struct phy_device *phydev, long *alarm); -+}; -+ -+static const struct marvell_hwmon_ops * -+to_marvell_hwmon_ops(const struct phy_device *phydev) -+{ -+ return phydev->drv->driver_data; -+} -+ - static int m88e1121_get_temp(struct phy_device *phydev, long *temp) - { - int oldpage; -@@ -2184,75 +2197,6 @@ error: - return phy_restore_page(phydev, oldpage, ret); - } - --static int m88e1121_hwmon_read(struct device *dev, -- enum hwmon_sensor_types type, -- u32 attr, int channel, long *temp) --{ -- struct phy_device *phydev = dev_get_drvdata(dev); -- int err; -- -- switch (attr) { -- case hwmon_temp_input: -- err = m88e1121_get_temp(phydev, temp); -- break; -- default: -- return -EOPNOTSUPP; -- } -- -- return err; --} -- --static umode_t m88e1121_hwmon_is_visible(const void *data, -- enum hwmon_sensor_types type, -- u32 attr, int channel) --{ -- if (type != hwmon_temp) -- return 0; -- -- switch (attr) { -- case hwmon_temp_input: -- return 0444; -- default: -- return 0; -- } --} -- --static u32 m88e1121_hwmon_chip_config[] = { -- HWMON_C_REGISTER_TZ, -- 0 --}; -- --static const struct hwmon_channel_info m88e1121_hwmon_chip = { -- .type = hwmon_chip, -- .config = m88e1121_hwmon_chip_config, --}; -- --static u32 m88e1121_hwmon_temp_config[] = { -- HWMON_T_INPUT, -- 0 --}; -- --static const struct hwmon_channel_info m88e1121_hwmon_temp = { -- .type = hwmon_temp, -- .config = m88e1121_hwmon_temp_config, --}; -- --static const struct hwmon_channel_info *m88e1121_hwmon_info[] = { -- &m88e1121_hwmon_chip, -- &m88e1121_hwmon_temp, -- NULL --}; -- --static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = { -- .is_visible = m88e1121_hwmon_is_visible, -- .read = m88e1121_hwmon_read, --}; -- --static const struct hwmon_chip_info m88e1121_hwmon_chip_info = { -- .ops = &m88e1121_hwmon_hwmon_ops, -- .info = m88e1121_hwmon_info, --}; -- - static int m88e1510_get_temp(struct phy_device *phydev, long *temp) - { - int ret; -@@ -2315,92 +2259,6 @@ static int m88e1510_get_temp_alarm(struc - return 0; - } - --static int m88e1510_hwmon_read(struct device *dev, -- enum hwmon_sensor_types type, -- u32 attr, int channel, long *temp) --{ -- struct phy_device *phydev = dev_get_drvdata(dev); -- int err; -- -- switch (attr) { -- case hwmon_temp_input: -- err = m88e1510_get_temp(phydev, temp); -- break; -- case hwmon_temp_crit: -- err = m88e1510_get_temp_critical(phydev, temp); -- break; -- case hwmon_temp_max_alarm: -- err = m88e1510_get_temp_alarm(phydev, temp); -- break; -- default: -- return -EOPNOTSUPP; -- } -- -- return err; --} -- --static int m88e1510_hwmon_write(struct device *dev, -- enum hwmon_sensor_types type, -- u32 attr, int channel, long temp) --{ -- struct phy_device *phydev = dev_get_drvdata(dev); -- int err; -- -- switch (attr) { -- case hwmon_temp_crit: -- err = m88e1510_set_temp_critical(phydev, temp); -- break; -- default: -- return -EOPNOTSUPP; -- } -- return err; --} -- --static umode_t m88e1510_hwmon_is_visible(const void *data, -- enum hwmon_sensor_types type, -- u32 attr, int channel) --{ -- if (type != hwmon_temp) -- return 0; -- -- switch (attr) { -- case hwmon_temp_input: -- case hwmon_temp_max_alarm: -- return 0444; -- case hwmon_temp_crit: -- return 0644; -- default: -- return 0; -- } --} -- --static u32 m88e1510_hwmon_temp_config[] = { -- HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM, -- 0 --}; -- --static const struct hwmon_channel_info m88e1510_hwmon_temp = { -- .type = hwmon_temp, -- .config = m88e1510_hwmon_temp_config, --}; -- --static const struct hwmon_channel_info *m88e1510_hwmon_info[] = { -- &m88e1121_hwmon_chip, -- &m88e1510_hwmon_temp, -- NULL --}; -- --static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = { -- .is_visible = m88e1510_hwmon_is_visible, -- .read = m88e1510_hwmon_read, -- .write = m88e1510_hwmon_write, --}; -- --static const struct hwmon_chip_info m88e1510_hwmon_chip_info = { -- .ops = &m88e1510_hwmon_hwmon_ops, -- .info = m88e1510_hwmon_info, --}; -- - static int m88e6390_get_temp(struct phy_device *phydev, long *temp) - { - int sum = 0; -@@ -2459,63 +2317,112 @@ error: - return ret; - } - --static int m88e6390_hwmon_read(struct device *dev, -- enum hwmon_sensor_types type, -- u32 attr, int channel, long *temp) -+static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *temp) - { - struct phy_device *phydev = dev_get_drvdata(dev); -- int err; -+ const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev); -+ int err = -EOPNOTSUPP; - - switch (attr) { - case hwmon_temp_input: -- err = m88e6390_get_temp(phydev, temp); -+ if (ops->get_temp) -+ err = ops->get_temp(phydev, temp); -+ break; -+ case hwmon_temp_crit: -+ if (ops->get_temp_critical) -+ err = ops->get_temp_critical(phydev, temp); -+ break; -+ case hwmon_temp_max_alarm: -+ if (ops->get_temp_alarm) -+ err = ops->get_temp_alarm(phydev, temp); -+ break; -+ } -+ -+ return err; -+} -+ -+static int marvell_hwmon_write(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long temp) -+{ -+ struct phy_device *phydev = dev_get_drvdata(dev); -+ const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev); -+ int err = -EOPNOTSUPP; -+ -+ switch (attr) { -+ case hwmon_temp_crit: -+ if (ops->set_temp_critical) -+ err = ops->set_temp_critical(phydev, temp); - break; - default: -- return -EOPNOTSUPP; -+ fallthrough; - } - - return err; - } - --static umode_t m88e6390_hwmon_is_visible(const void *data, -- enum hwmon_sensor_types type, -- u32 attr, int channel) -+static umode_t marvell_hwmon_is_visible(const void *data, -+ enum hwmon_sensor_types type, -+ u32 attr, int channel) - { -+ const struct phy_device *phydev = data; -+ const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev); -+ - if (type != hwmon_temp) - return 0; - - switch (attr) { - case hwmon_temp_input: -- return 0444; -+ return ops->get_temp ? 0444 : 0; -+ case hwmon_temp_max_alarm: -+ return ops->get_temp_alarm ? 0444 : 0; -+ case hwmon_temp_crit: -+ return (ops->get_temp_critical ? 0444 : 0) | -+ (ops->set_temp_critical ? 0200 : 0); - default: - return 0; - } - } - --static u32 m88e6390_hwmon_temp_config[] = { -- HWMON_T_INPUT, -+static u32 marvell_hwmon_chip_config[] = { -+ HWMON_C_REGISTER_TZ, - 0 - }; - --static const struct hwmon_channel_info m88e6390_hwmon_temp = { -+static const struct hwmon_channel_info marvell_hwmon_chip = { -+ .type = hwmon_chip, -+ .config = marvell_hwmon_chip_config, -+}; -+ -+/* we can define HWMON_T_CRIT and HWMON_T_MAX_ALARM even though these are not -+ * defined for all PHYs, because the hwmon code checks whether the attributes -+ * exists via the .is_visible method -+ */ -+static u32 marvell_hwmon_temp_config[] = { -+ HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM, -+ 0 -+}; -+ -+static const struct hwmon_channel_info marvell_hwmon_temp = { - .type = hwmon_temp, -- .config = m88e6390_hwmon_temp_config, -+ .config = marvell_hwmon_temp_config, - }; - --static const struct hwmon_channel_info *m88e6390_hwmon_info[] = { -- &m88e1121_hwmon_chip, -- &m88e6390_hwmon_temp, -+static const struct hwmon_channel_info *marvell_hwmon_info[] = { -+ &marvell_hwmon_chip, -+ &marvell_hwmon_temp, - NULL - }; - --static const struct hwmon_ops m88e6390_hwmon_hwmon_ops = { -- .is_visible = m88e6390_hwmon_is_visible, -- .read = m88e6390_hwmon_read, -+static const struct hwmon_ops marvell_hwmon_hwmon_ops = { -+ .is_visible = marvell_hwmon_is_visible, -+ .read = marvell_hwmon_read, -+ .write = marvell_hwmon_write, - }; - --static const struct hwmon_chip_info m88e6390_hwmon_chip_info = { -- .ops = &m88e6390_hwmon_hwmon_ops, -- .info = m88e6390_hwmon_info, -+static const struct hwmon_chip_info marvell_hwmon_chip_info = { -+ .ops = &marvell_hwmon_hwmon_ops, -+ .info = marvell_hwmon_info, - }; - - static int marvell_hwmon_name(struct phy_device *phydev) -@@ -2538,49 +2445,48 @@ static int marvell_hwmon_name(struct phy - return 0; - } - --static int marvell_hwmon_probe(struct phy_device *phydev, -- const struct hwmon_chip_info *chip) -+static int marvell_hwmon_probe(struct phy_device *phydev) - { -+ const struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev); - struct marvell_priv *priv = phydev->priv; - struct device *dev = &phydev->mdio.dev; - int err; - -+ if (!ops) -+ return 0; -+ - err = marvell_hwmon_name(phydev); - if (err) - return err; - - priv->hwmon_dev = devm_hwmon_device_register_with_info( -- dev, priv->hwmon_name, phydev, chip, NULL); -+ dev, priv->hwmon_name, phydev, &marvell_hwmon_chip_info, NULL); - - return PTR_ERR_OR_ZERO(priv->hwmon_dev); - } - --static int m88e1121_hwmon_probe(struct phy_device *phydev) --{ -- return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info); --} -+static const struct marvell_hwmon_ops m88e1121_hwmon_ops = { -+ .get_temp = m88e1121_get_temp, -+}; - --static int m88e1510_hwmon_probe(struct phy_device *phydev) --{ -- return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info); --} -+static const struct marvell_hwmon_ops m88e1510_hwmon_ops = { -+ .get_temp = m88e1510_get_temp, -+ .get_temp_critical = m88e1510_get_temp_critical, -+ .set_temp_critical = m88e1510_set_temp_critical, -+ .get_temp_alarm = m88e1510_get_temp_alarm, -+}; -+ -+static const struct marvell_hwmon_ops m88e6390_hwmon_ops = { -+ .get_temp = m88e6390_get_temp, -+}; -+ -+#define DEF_MARVELL_HWMON_OPS(s) (&(s)) - --static int m88e6390_hwmon_probe(struct phy_device *phydev) --{ -- return marvell_hwmon_probe(phydev, &m88e6390_hwmon_chip_info); --} - #else --static int m88e1121_hwmon_probe(struct phy_device *phydev) --{ -- return 0; --} - --static int m88e1510_hwmon_probe(struct phy_device *phydev) --{ -- return 0; --} -+#define DEF_MARVELL_HWMON_OPS(s) NULL - --static int m88e6390_hwmon_probe(struct phy_device *phydev) -+static int marvell_hwmon_probe(struct phy_device *phydev) - { - return 0; - } -@@ -2596,40 +2502,7 @@ static int marvell_probe(struct phy_devi - - phydev->priv = priv; - -- return 0; --} -- --static int m88e1121_probe(struct phy_device *phydev) --{ -- int err; -- -- err = marvell_probe(phydev); -- if (err) -- return err; -- -- return m88e1121_hwmon_probe(phydev); --} -- --static int m88e1510_probe(struct phy_device *phydev) --{ -- int err; -- -- err = marvell_probe(phydev); -- if (err) -- return err; -- -- return m88e1510_hwmon_probe(phydev); --} -- --static int m88e6390_probe(struct phy_device *phydev) --{ -- int err; -- -- err = marvell_probe(phydev); -- if (err) -- return err; -- -- return m88e6390_hwmon_probe(phydev); -+ return marvell_hwmon_probe(phydev); - } - - static struct phy_driver marvell_drivers[] = { -@@ -2714,8 +2587,9 @@ static struct phy_driver marvell_drivers - .phy_id = MARVELL_PHY_ID_88E1121R, - .phy_id_mask = MARVELL_PHY_ID_MASK, - .name = "Marvell 88E1121R", -+ .driver_data = DEF_MARVELL_HWMON_OPS(m88e1121_hwmon_ops), - /* PHY_GBIT_FEATURES */ -- .probe = m88e1121_probe, -+ .probe = marvell_probe, - .config_init = marvell_config_init, - .config_aneg = m88e1121_config_aneg, - .read_status = marvell_read_status, -@@ -2834,9 +2708,10 @@ static struct phy_driver marvell_drivers - .phy_id = MARVELL_PHY_ID_88E1510, - .phy_id_mask = MARVELL_PHY_ID_MASK, - .name = "Marvell 88E1510", -+ .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops), - .features = PHY_GBIT_FIBRE_FEATURES, - .flags = PHY_POLL_CABLE_TEST, -- .probe = m88e1510_probe, -+ .probe = marvell_probe, - .config_init = m88e1510_config_init, - .config_aneg = m88e1510_config_aneg, - .read_status = marvell_read_status, -@@ -2863,9 +2738,10 @@ static struct phy_driver marvell_drivers - .phy_id = MARVELL_PHY_ID_88E1540, - .phy_id_mask = MARVELL_PHY_ID_MASK, - .name = "Marvell 88E1540", -+ .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops), - /* PHY_GBIT_FEATURES */ - .flags = PHY_POLL_CABLE_TEST, -- .probe = m88e1510_probe, -+ .probe = marvell_probe, - .config_init = marvell_config_init, - .config_aneg = m88e1510_config_aneg, - .read_status = marvell_read_status, -@@ -2889,7 +2765,8 @@ static struct phy_driver marvell_drivers - .phy_id = MARVELL_PHY_ID_88E1545, - .phy_id_mask = MARVELL_PHY_ID_MASK, - .name = "Marvell 88E1545", -- .probe = m88e1510_probe, -+ .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops), -+ .probe = marvell_probe, - /* PHY_GBIT_FEATURES */ - .flags = PHY_POLL_CABLE_TEST, - .config_init = marvell_config_init, -@@ -2935,9 +2812,10 @@ static struct phy_driver marvell_drivers - .phy_id = MARVELL_PHY_ID_88E6341_FAMILY, - .phy_id_mask = MARVELL_PHY_ID_MASK, - .name = "Marvell 88E6341 Family", -+ .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops), - /* PHY_GBIT_FEATURES */ - .flags = PHY_POLL_CABLE_TEST, -- .probe = m88e1510_probe, -+ .probe = marvell_probe, - .config_init = marvell_config_init, - .config_aneg = m88e6390_config_aneg, - .read_status = marvell_read_status, -@@ -2961,9 +2839,10 @@ static struct phy_driver marvell_drivers - .phy_id = MARVELL_PHY_ID_88E6390_FAMILY, - .phy_id_mask = MARVELL_PHY_ID_MASK, - .name = "Marvell 88E6390 Family", -+ .driver_data = DEF_MARVELL_HWMON_OPS(m88e6390_hwmon_ops), - /* PHY_GBIT_FEATURES */ - .flags = PHY_POLL_CABLE_TEST, -- .probe = m88e6390_probe, -+ .probe = marvell_probe, - .config_init = marvell_config_init, - .config_aneg = m88e6390_config_aneg, - .read_status = marvell_read_status, -@@ -2987,7 +2866,8 @@ static struct phy_driver marvell_drivers - .phy_id = MARVELL_PHY_ID_88E1340S, - .phy_id_mask = MARVELL_PHY_ID_MASK, - .name = "Marvell 88E1340S", -- .probe = m88e1510_probe, -+ .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops), -+ .probe = marvell_probe, - /* PHY_GBIT_FEATURES */ - .config_init = marvell_config_init, - .config_aneg = m88e1510_config_aneg, -@@ -3009,7 +2889,8 @@ static struct phy_driver marvell_drivers - .phy_id = MARVELL_PHY_ID_88E1548P, - .phy_id_mask = MARVELL_PHY_ID_MASK, - .name = "Marvell 88E1548P", -- .probe = m88e1510_probe, -+ .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops), -+ .probe = marvell_probe, - .features = PHY_GBIT_FIBRE_FEATURES, - .config_init = marvell_config_init, - .config_aneg = m88e1510_config_aneg, diff --git a/target/linux/generic/backport-5.10/713-v5.15-net-phy-marvell-add-SFP-support-for-88E1510.patch b/target/linux/generic/backport-5.10/713-v5.15-net-phy-marvell-add-SFP-support-for-88E1510.patch deleted file mode 100644 index b86e9bf640..0000000000 --- a/target/linux/generic/backport-5.10/713-v5.15-net-phy-marvell-add-SFP-support-for-88E1510.patch +++ /dev/null @@ -1,161 +0,0 @@ -From b697d9d38a5a5ab405d7cc4743d39fe2c5d7517c Mon Sep 17 00:00:00 2001 -From: Ivan Bornyakov -Date: Thu, 12 Aug 2021 16:42:56 +0300 -Subject: [PATCH] net: phy: marvell: add SFP support for 88E1510 - -Add support for SFP cages connected to the Marvell 88E1512 transceiver. -88E1512 supports for SGMII/1000Base-X/100Base-FX media type with RGMII -on system interface. Configure PHY to appropriate mode depending on the -type of SFP inserted. On SFP removal configure PHY to the RGMII-copper -mode so RJ-45 port can still work. - -Signed-off-by: Ivan Bornyakov -Link: https://lore.kernel.org/r/20210812134256.2436-1-i.bornyakov@metrotek.ru -Signed-off-by: Jakub Kicinski ---- - drivers/net/phy/marvell.c | 105 +++++++++++++++++++++++++++++++++++++- - 1 file changed, 104 insertions(+), 1 deletion(-) - ---- a/drivers/net/phy/marvell.c -+++ b/drivers/net/phy/marvell.c -@@ -32,6 +32,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -46,6 +47,7 @@ - #define MII_MARVELL_MISC_TEST_PAGE 0x06 - #define MII_MARVELL_VCT7_PAGE 0x07 - #define MII_MARVELL_WOL_PAGE 0x11 -+#define MII_MARVELL_MODE_PAGE 0x12 - - #define MII_M1011_IEVENT 0x13 - #define MII_M1011_IEVENT_CLEAR 0x0000 -@@ -162,7 +164,14 @@ - - #define MII_88E1510_GEN_CTRL_REG_1 0x14 - #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7 -+#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII 0x0 /* RGMII to copper */ - #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */ -+/* RGMII to 1000BASE-X */ -+#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X 0x2 -+/* RGMII to 100BASE-FX */ -+#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX 0x3 -+/* RGMII to SGMII */ -+#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII 0x4 - #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */ - - #define MII_VCT5_TX_RX_MDI0_COUPLING 0x10 -@@ -2505,6 +2514,100 @@ static int marvell_probe(struct phy_devi - return marvell_hwmon_probe(phydev); - } - -+static int m88e1510_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) -+{ -+ struct phy_device *phydev = upstream; -+ phy_interface_t interface; -+ struct device *dev; -+ int oldpage; -+ int ret = 0; -+ u16 mode; -+ -+ __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, }; -+ -+ dev = &phydev->mdio.dev; -+ -+ sfp_parse_support(phydev->sfp_bus, id, supported); -+ interface = sfp_select_interface(phydev->sfp_bus, supported); -+ -+ dev_info(dev, "%s SFP module inserted\n", phy_modes(interface)); -+ -+ switch (interface) { -+ case PHY_INTERFACE_MODE_1000BASEX: -+ mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X; -+ -+ break; -+ case PHY_INTERFACE_MODE_100BASEX: -+ mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX; -+ -+ break; -+ case PHY_INTERFACE_MODE_SGMII: -+ mode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII; -+ -+ break; -+ default: -+ dev_err(dev, "Incompatible SFP module inserted\n"); -+ -+ return -EINVAL; -+ } -+ -+ oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE); -+ if (oldpage < 0) -+ goto error; -+ -+ ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1, -+ MII_88E1510_GEN_CTRL_REG_1_MODE_MASK, mode); -+ if (ret < 0) -+ goto error; -+ -+ ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1, -+ MII_88E1510_GEN_CTRL_REG_1_RESET); -+ -+error: -+ return phy_restore_page(phydev, oldpage, ret); -+} -+ -+static void m88e1510_sfp_remove(void *upstream) -+{ -+ struct phy_device *phydev = upstream; -+ int oldpage; -+ int ret = 0; -+ -+ oldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE); -+ if (oldpage < 0) -+ goto error; -+ -+ ret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1, -+ MII_88E1510_GEN_CTRL_REG_1_MODE_MASK, -+ MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII); -+ if (ret < 0) -+ goto error; -+ -+ ret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1, -+ MII_88E1510_GEN_CTRL_REG_1_RESET); -+ -+error: -+ phy_restore_page(phydev, oldpage, ret); -+} -+ -+static const struct sfp_upstream_ops m88e1510_sfp_ops = { -+ .module_insert = m88e1510_sfp_insert, -+ .module_remove = m88e1510_sfp_remove, -+ .attach = phy_sfp_attach, -+ .detach = phy_sfp_detach, -+}; -+ -+static int m88e1510_probe(struct phy_device *phydev) -+{ -+ int err; -+ -+ err = marvell_probe(phydev); -+ if (err) -+ return err; -+ -+ return phy_sfp_probe(phydev, &m88e1510_sfp_ops); -+} -+ - static struct phy_driver marvell_drivers[] = { - { - .phy_id = MARVELL_PHY_ID_88E1101, -@@ -2711,7 +2814,7 @@ static struct phy_driver marvell_drivers - .driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops), - .features = PHY_GBIT_FIBRE_FEATURES, - .flags = PHY_POLL_CABLE_TEST, -- .probe = marvell_probe, -+ .probe = m88e1510_probe, - .config_init = m88e1510_config_init, - .config_aneg = m88e1510_config_aneg, - .read_status = marvell_read_status, diff --git a/target/linux/generic/backport-5.10/719-v5.12-net-dsa-automatically-bring-up-DSA-master-when-openi.patch b/target/linux/generic/backport-5.10/719-v5.12-net-dsa-automatically-bring-up-DSA-master-when-openi.patch deleted file mode 100644 index 3b630377f9..0000000000 --- a/target/linux/generic/backport-5.10/719-v5.12-net-dsa-automatically-bring-up-DSA-master-when-openi.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 9d5ef190e5615a7b63af89f88c4106a5bc127974 Mon Sep 17 00:00:00 2001 -From: Vladimir Oltean -Date: Fri, 5 Feb 2021 15:37:10 +0200 -Subject: [PATCH] net: dsa: automatically bring up DSA master when opening user - port - -DSA wants the master interface to be open before the user port is due to -historical reasons. The promiscuity of interfaces that are down used to -have issues, as referenced Lennert Buytenhek in commit df02c6ff2e39 -("dsa: fix master interface allmulti/promisc handling"). - -The bugfix mentioned there, commit b6c40d68ff64 ("net: only invoke -dev->change_rx_flags when device is UP"), was basically a "don't do -that" approach to working around the promiscuity while down issue. - -Further work done by Vlad Yasevich in commit d2615bf45069 ("net: core: -Always propagate flag changes to interfaces") has resolved the -underlying issue, and it is strictly up to the DSA and 8021q drivers -now, it is no longer mandated by the networking core that the master -interface must be up when changing its promiscuity. - -From DSA's point of view, deciding to error out in dsa_slave_open -because the master isn't up is -(a) a bad user experience and -(b) knocking at an open door. -Even if there still was an issue with promiscuity while down, DSA could -still just open the master and avoid it. - -Doing it this way has the additional benefit that user space can now -remove DSA-specific workarounds, like systemd-networkd with BindCarrier: -https://github.com/systemd/systemd/issues/7478 - -And we can finally remove one of the 2 bullets in the "Common pitfalls -using DSA setups" chapter. - -Tested with two cascaded DSA switches: - -$ ip link set sw0p2 up -fsl_enetc 0000:00:00.2 eno2: configuring for fixed/internal link mode -fsl_enetc 0000:00:00.2 eno2: Link is Up - 1Gbps/Full - flow control rx/tx -mscc_felix 0000:00:00.5 swp0: configuring for fixed/sgmii link mode -mscc_felix 0000:00:00.5 swp0: Link is Up - 1Gbps/Full - flow control off -8021q: adding VLAN 0 to HW filter on device swp0 -sja1105 spi2.0 sw0p2: configuring for phy/rgmii-id link mode -IPv6: ADDRCONF(NETDEV_CHANGE): eno2: link becomes ready -IPv6: ADDRCONF(NETDEV_CHANGE): swp0: link becomes ready - -Signed-off-by: Vladimir Oltean -Reviewed-by: Andrew Lunn -Reviewed-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - Documentation/networking/dsa/dsa.rst | 4 ---- - net/dsa/slave.c | 7 +++++-- - 2 files changed, 5 insertions(+), 6 deletions(-) - ---- a/Documentation/networking/dsa/dsa.rst -+++ b/Documentation/networking/dsa/dsa.rst -@@ -273,10 +273,6 @@ will not make us go through the switch t - the Ethernet switch on the other end, expecting a tag will typically drop this - frame. - --Slave network devices check that the master network device is UP before allowing --you to administratively bring UP these slave network devices. A common --configuration mistake is forgetting to bring UP the master network device first. -- - Interactions with other subsystems - ================================== - ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -68,8 +68,11 @@ static int dsa_slave_open(struct net_dev - struct dsa_port *dp = dsa_slave_to_port(dev); - int err; - -- if (!(master->flags & IFF_UP)) -- return -ENETDOWN; -+ err = dev_open(master, NULL); -+ if (err < 0) { -+ netdev_err(dev, "failed to open master %s\n", master->name); -+ goto out; -+ } - - if (!ether_addr_equal(dev->dev_addr, master->dev_addr)) { - err = dev_uc_add(master, dev->dev_addr); diff --git a/target/linux/generic/backport-5.10/720-v5.12-net-bridge-notify-switchdev-of-disappearance-of-old-.patch b/target/linux/generic/backport-5.10/720-v5.12-net-bridge-notify-switchdev-of-disappearance-of-old-.patch deleted file mode 100644 index c43cb4d1f2..0000000000 --- a/target/linux/generic/backport-5.10/720-v5.12-net-bridge-notify-switchdev-of-disappearance-of-old-.patch +++ /dev/null @@ -1,126 +0,0 @@ -From 90dc8fd36078a536671adae884d0b929cce6480a Mon Sep 17 00:00:00 2001 -From: Vladimir Oltean -Date: Wed, 6 Jan 2021 11:51:30 +0200 -Subject: [PATCH] net: bridge: notify switchdev of disappearance of old FDB - entry upon migration - -Currently the bridge emits atomic switchdev notifications for -dynamically learnt FDB entries. Monitoring these notifications works -wonders for switchdev drivers that want to keep their hardware FDB in -sync with the bridge's FDB. - -For example station A wants to talk to station B in the diagram below, -and we are concerned with the behavior of the bridge on the DUT device: - - DUT - +-------------------------------------+ - | br0 | - | +------+ +------+ +------+ +------+ | - | | | | | | | | | | - | | swp0 | | swp1 | | swp2 | | eth0 | | - +-------------------------------------+ - | | | - Station A | | - | | - +--+------+--+ +--+------+--+ - | | | | | | | | - | | swp0 | | | | swp0 | | - Another | +------+ | | +------+ | Another - switch | br0 | | br0 | switch - | +------+ | | +------+ | - | | | | | | | | - | | swp1 | | | | swp1 | | - +--+------+--+ +--+------+--+ - | - Station B - -Interfaces swp0, swp1, swp2 are handled by a switchdev driver that has -the following property: frames injected from its control interface bypass -the internal address analyzer logic, and therefore, this hardware does -not learn from the source address of packets transmitted by the network -stack through it. So, since bridging between eth0 (where Station B is -attached) and swp0 (where Station A is attached) is done in software, -the switchdev hardware will never learn the source address of Station B. -So the traffic towards that destination will be treated as unknown, i.e. -flooded. - -This is where the bridge notifications come in handy. When br0 on the -DUT sees frames with Station B's MAC address on eth0, the switchdev -driver gets these notifications and can install a rule to send frames -towards Station B's address that are incoming from swp0, swp1, swp2, -only towards the control interface. This is all switchdev driver private -business, which the notification makes possible. - -All is fine until someone unplugs Station B's cable and moves it to the -other switch: - - DUT - +-------------------------------------+ - | br0 | - | +------+ +------+ +------+ +------+ | - | | | | | | | | | | - | | swp0 | | swp1 | | swp2 | | eth0 | | - +-------------------------------------+ - | | | - Station A | | - | | - +--+------+--+ +--+------+--+ - | | | | | | | | - | | swp0 | | | | swp0 | | - Another | +------+ | | +------+ | Another - switch | br0 | | br0 | switch - | +------+ | | +------+ | - | | | | | | | | - | | swp1 | | | | swp1 | | - +--+------+--+ +--+------+--+ - | - Station B - -Luckily for the use cases we care about, Station B is noisy enough that -the DUT hears it (on swp1 this time). swp1 receives the frames and -delivers them to the bridge, who enters the unlikely path in br_fdb_update -of updating an existing entry. It moves the entry in the software bridge -to swp1 and emits an addition notification towards that. - -As far as the switchdev driver is concerned, all that it needs to ensure -is that traffic between Station A and Station B is not forever broken. -If it does nothing, then the stale rule to send frames for Station B -towards the control interface remains in place. But Station B is no -longer reachable via the control interface, but via a port that can -offload the bridge port learning attribute. It's just that the port is -prevented from learning this address, since the rule overrides FDB -updates. So the rule needs to go. The question is via what mechanism. - -It sure would be possible for this switchdev driver to keep track of all -addresses which are sent to the control interface, and then also listen -for bridge notifier events on its own ports, searching for the ones that -have a MAC address which was previously sent to the control interface. -But this is cumbersome and inefficient. Instead, with one small change, -the bridge could notify of the address deletion from the old port, in a -symmetrical manner with how it did for the insertion. Then the switchdev -driver would not be required to monitor learn/forget events for its own -ports. It could just delete the rule towards the control interface upon -bridge entry migration. This would make hardware address learning be -possible again. Then it would take a few more packets until the hardware -and software FDB would be in sync again. - -Signed-off-by: Vladimir Oltean -Acked-by: Nikolay Aleksandrov -Reviewed-by: Ido Schimmel -Reviewed-by: Andrew Lunn -Reviewed-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - net/bridge/br_fdb.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/net/bridge/br_fdb.c -+++ b/net/bridge/br_fdb.c -@@ -602,6 +602,7 @@ void br_fdb_update(struct net_bridge *br - /* fastpath: update of existing entry */ - if (unlikely(source != fdb->dst && - !test_bit(BR_FDB_STICKY, &fdb->flags))) { -+ br_switchdev_fdb_notify(fdb, RTM_DELNEIGH); - fdb->dst = source; - fdb_modified = true; - /* Take over HW learned entry */ diff --git a/target/linux/generic/backport-5.10/721-v5.12-net-dsa-be-louder-when-a-non-legacy-FDB-operation-fa.patch b/target/linux/generic/backport-5.10/721-v5.12-net-dsa-be-louder-when-a-non-legacy-FDB-operation-fa.patch deleted file mode 100644 index f9337590f7..0000000000 --- a/target/linux/generic/backport-5.10/721-v5.12-net-dsa-be-louder-when-a-non-legacy-FDB-operation-fa.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 2fd186501b1cff155cc4a755c210793cfc0dffb5 Mon Sep 17 00:00:00 2001 -From: Vladimir Oltean -Date: Wed, 6 Jan 2021 11:51:31 +0200 -Subject: [PATCH] net: dsa: be louder when a non-legacy FDB operation fails - -The dev_close() call was added in commit c9eb3e0f8701 ("net: dsa: Add -support for learning FDB through notification") "to indicate inconsistent -situation" when we could not delete an FDB entry from the port. - -bridge fdb del d8:58:d7:00:ca:6d dev swp0 self master - -It is a bit drastic and at the same time not helpful if the above fails -to only print with netdev_dbg log level, but on the other hand to bring -the interface down. - -So increase the verbosity of the error message, and drop dev_close(). - -Signed-off-by: Vladimir Oltean -Reviewed-by: Andrew Lunn -Reviewed-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - net/dsa/slave.c | 10 +++++++--- - 1 file changed, 7 insertions(+), 3 deletions(-) - ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -2112,7 +2112,9 @@ static void dsa_slave_switchdev_event_wo - - err = dsa_port_fdb_add(dp, fdb_info->addr, fdb_info->vid); - if (err) { -- netdev_dbg(dev, "fdb add failed err=%d\n", err); -+ netdev_err(dev, -+ "failed to add %pM vid %d to fdb: %d\n", -+ fdb_info->addr, fdb_info->vid, err); - break; - } - fdb_info->offloaded = true; -@@ -2127,9 +2129,11 @@ static void dsa_slave_switchdev_event_wo - - err = dsa_port_fdb_del(dp, fdb_info->addr, fdb_info->vid); - if (err) { -- netdev_dbg(dev, "fdb del failed err=%d\n", err); -- dev_close(dev); -+ netdev_err(dev, -+ "failed to delete %pM vid %d from fdb: %d\n", -+ fdb_info->addr, fdb_info->vid, err); - } -+ - break; - } - rtnl_unlock(); diff --git a/target/linux/generic/backport-5.10/722-v5.12-net-dsa-don-t-use-switchdev_notifier_fdb_info-in-dsa.patch b/target/linux/generic/backport-5.10/722-v5.12-net-dsa-don-t-use-switchdev_notifier_fdb_info-in-dsa.patch deleted file mode 100644 index c1aa8fda82..0000000000 --- a/target/linux/generic/backport-5.10/722-v5.12-net-dsa-don-t-use-switchdev_notifier_fdb_info-in-dsa.patch +++ /dev/null @@ -1,226 +0,0 @@ -From c4bb76a9a0ef87c4cc1f636defed5f12deb9f5a7 Mon Sep 17 00:00:00 2001 -From: Vladimir Oltean -Date: Wed, 6 Jan 2021 11:51:32 +0200 -Subject: [PATCH] net: dsa: don't use switchdev_notifier_fdb_info in - dsa_switchdev_event_work - -Currently DSA doesn't add FDB entries on the CPU port, because it only -does so through switchdev, which is associated with a net_device, and -there are none of those for the CPU port. - -But actually FDB addresses on the CPU port have some use cases of their -own, if the switchdev operations are initiated from within the DSA -layer. There is just one problem with the existing code: it passes a -structure in dsa_switchdev_event_work which was retrieved directly from -switchdev, so it contains a net_device. We need to generalize the -contents to something that covers the CPU port as well: the "ds, port" -tuple is fine for that. - -Note that the new procedure for notifying the successful FDB offload is -inspired from the rocker model. - -Also, nothing was being done if added_by_user was false. Let's check for -that a lot earlier, and don't actually bother to schedule the worker -for nothing. - -Signed-off-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - net/dsa/dsa_priv.h | 12 +++++ - net/dsa/slave.c | 106 ++++++++++++++++++++++----------------------- - 2 files changed, 65 insertions(+), 53 deletions(-) - ---- a/net/dsa/dsa_priv.h -+++ b/net/dsa/dsa_priv.h -@@ -73,6 +73,18 @@ struct dsa_notifier_mtu_info { - int mtu; - }; - -+struct dsa_switchdev_event_work { -+ struct dsa_switch *ds; -+ int port; -+ struct work_struct work; -+ unsigned long event; -+ /* Specific for SWITCHDEV_FDB_ADD_TO_DEVICE and -+ * SWITCHDEV_FDB_DEL_TO_DEVICE -+ */ -+ unsigned char addr[ETH_ALEN]; -+ u16 vid; -+}; -+ - struct dsa_slave_priv { - /* Copy of CPU port xmit for faster access in slave transmit hot path */ - struct sk_buff * (*xmit)(struct sk_buff *skb, ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -2087,76 +2087,66 @@ static int dsa_slave_netdevice_event(str - return NOTIFY_DONE; - } - --struct dsa_switchdev_event_work { -- struct work_struct work; -- struct switchdev_notifier_fdb_info fdb_info; -- struct net_device *dev; -- unsigned long event; --}; -+static void -+dsa_fdb_offload_notify(struct dsa_switchdev_event_work *switchdev_work) -+{ -+ struct dsa_switch *ds = switchdev_work->ds; -+ struct switchdev_notifier_fdb_info info; -+ struct dsa_port *dp; -+ -+ if (!dsa_is_user_port(ds, switchdev_work->port)) -+ return; -+ -+ info.addr = switchdev_work->addr; -+ info.vid = switchdev_work->vid; -+ info.offloaded = true; -+ dp = dsa_to_port(ds, switchdev_work->port); -+ call_switchdev_notifiers(SWITCHDEV_FDB_OFFLOADED, -+ dp->slave, &info.info, NULL); -+} - - static void dsa_slave_switchdev_event_work(struct work_struct *work) - { - struct dsa_switchdev_event_work *switchdev_work = - container_of(work, struct dsa_switchdev_event_work, work); -- struct net_device *dev = switchdev_work->dev; -- struct switchdev_notifier_fdb_info *fdb_info; -- struct dsa_port *dp = dsa_slave_to_port(dev); -+ struct dsa_switch *ds = switchdev_work->ds; -+ struct dsa_port *dp; - int err; - -+ dp = dsa_to_port(ds, switchdev_work->port); -+ - rtnl_lock(); - switch (switchdev_work->event) { - case SWITCHDEV_FDB_ADD_TO_DEVICE: -- fdb_info = &switchdev_work->fdb_info; -- if (!fdb_info->added_by_user) -- break; -- -- err = dsa_port_fdb_add(dp, fdb_info->addr, fdb_info->vid); -+ err = dsa_port_fdb_add(dp, switchdev_work->addr, -+ switchdev_work->vid); - if (err) { -- netdev_err(dev, -- "failed to add %pM vid %d to fdb: %d\n", -- fdb_info->addr, fdb_info->vid, err); -+ dev_err(ds->dev, -+ "port %d failed to add %pM vid %d to fdb: %d\n", -+ dp->index, switchdev_work->addr, -+ switchdev_work->vid, err); - break; - } -- fdb_info->offloaded = true; -- call_switchdev_notifiers(SWITCHDEV_FDB_OFFLOADED, dev, -- &fdb_info->info, NULL); -+ dsa_fdb_offload_notify(switchdev_work); - break; - - case SWITCHDEV_FDB_DEL_TO_DEVICE: -- fdb_info = &switchdev_work->fdb_info; -- if (!fdb_info->added_by_user) -- break; -- -- err = dsa_port_fdb_del(dp, fdb_info->addr, fdb_info->vid); -+ err = dsa_port_fdb_del(dp, switchdev_work->addr, -+ switchdev_work->vid); - if (err) { -- netdev_err(dev, -- "failed to delete %pM vid %d from fdb: %d\n", -- fdb_info->addr, fdb_info->vid, err); -+ dev_err(ds->dev, -+ "port %d failed to delete %pM vid %d from fdb: %d\n", -+ dp->index, switchdev_work->addr, -+ switchdev_work->vid, err); - } - - break; - } - rtnl_unlock(); - -- kfree(switchdev_work->fdb_info.addr); - kfree(switchdev_work); -- dev_put(dev); --} -- --static int --dsa_slave_switchdev_fdb_work_init(struct dsa_switchdev_event_work * -- switchdev_work, -- const struct switchdev_notifier_fdb_info * -- fdb_info) --{ -- memcpy(&switchdev_work->fdb_info, fdb_info, -- sizeof(switchdev_work->fdb_info)); -- switchdev_work->fdb_info.addr = kzalloc(ETH_ALEN, GFP_ATOMIC); -- if (!switchdev_work->fdb_info.addr) -- return -ENOMEM; -- ether_addr_copy((u8 *)switchdev_work->fdb_info.addr, -- fdb_info->addr); -- return 0; -+ if (dsa_is_user_port(ds, dp->index)) -+ dev_put(dp->slave); - } - - /* Called under rcu_read_lock() */ -@@ -2164,7 +2154,9 @@ static int dsa_slave_switchdev_event(str - unsigned long event, void *ptr) - { - struct net_device *dev = switchdev_notifier_info_to_dev(ptr); -+ const struct switchdev_notifier_fdb_info *fdb_info; - struct dsa_switchdev_event_work *switchdev_work; -+ struct dsa_port *dp; - int err; - - if (event == SWITCHDEV_PORT_ATTR_SET) { -@@ -2177,20 +2169,32 @@ static int dsa_slave_switchdev_event(str - if (!dsa_slave_dev_check(dev)) - return NOTIFY_DONE; - -+ dp = dsa_slave_to_port(dev); -+ - switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC); - if (!switchdev_work) - return NOTIFY_BAD; - - INIT_WORK(&switchdev_work->work, - dsa_slave_switchdev_event_work); -- switchdev_work->dev = dev; -+ switchdev_work->ds = dp->ds; -+ switchdev_work->port = dp->index; - switchdev_work->event = event; - - switch (event) { - case SWITCHDEV_FDB_ADD_TO_DEVICE: - case SWITCHDEV_FDB_DEL_TO_DEVICE: -- if (dsa_slave_switchdev_fdb_work_init(switchdev_work, ptr)) -- goto err_fdb_work_init; -+ fdb_info = ptr; -+ -+ if (!fdb_info->added_by_user) { -+ kfree(switchdev_work); -+ return NOTIFY_OK; -+ } -+ -+ ether_addr_copy(switchdev_work->addr, -+ fdb_info->addr); -+ switchdev_work->vid = fdb_info->vid; -+ - dev_hold(dev); - break; - default: -@@ -2200,10 +2204,6 @@ static int dsa_slave_switchdev_event(str - - dsa_schedule_work(&switchdev_work->work); - return NOTIFY_OK; -- --err_fdb_work_init: -- kfree(switchdev_work); -- return NOTIFY_BAD; - } - - static int dsa_slave_switchdev_blocking_event(struct notifier_block *unused, diff --git a/target/linux/generic/backport-5.10/723-v5.12-net-dsa-move-switchdev-event-implementation-under-th.patch b/target/linux/generic/backport-5.10/723-v5.12-net-dsa-move-switchdev-event-implementation-under-th.patch deleted file mode 100644 index 9131df70d3..0000000000 --- a/target/linux/generic/backport-5.10/723-v5.12-net-dsa-move-switchdev-event-implementation-under-th.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 447d290a58bd335d68f665713842365d3d6447df Mon Sep 17 00:00:00 2001 -From: Vladimir Oltean -Date: Wed, 6 Jan 2021 11:51:33 +0200 -Subject: [PATCH] net: dsa: move switchdev event implementation under the same - switch/case statement - -We'll need to start listening to SWITCHDEV_FDB_{ADD,DEL}_TO_DEVICE -events even for interfaces where dsa_slave_dev_check returns false, so -we need that check inside the switch-case statement for SWITCHDEV_FDB_*. - -This movement also avoids a useless allocation / free of switchdev_work -on the untreated "default event" case. - -Signed-off-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - net/dsa/slave.c | 35 ++++++++++++++++------------------- - 1 file changed, 16 insertions(+), 19 deletions(-) - ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -2159,31 +2159,29 @@ static int dsa_slave_switchdev_event(str - struct dsa_port *dp; - int err; - -- if (event == SWITCHDEV_PORT_ATTR_SET) { -+ switch (event) { -+ case SWITCHDEV_PORT_ATTR_SET: - err = switchdev_handle_port_attr_set(dev, ptr, - dsa_slave_dev_check, - dsa_slave_port_attr_set); - return notifier_from_errno(err); -- } -- -- if (!dsa_slave_dev_check(dev)) -- return NOTIFY_DONE; -+ case SWITCHDEV_FDB_ADD_TO_DEVICE: -+ case SWITCHDEV_FDB_DEL_TO_DEVICE: -+ if (!dsa_slave_dev_check(dev)) -+ return NOTIFY_DONE; - -- dp = dsa_slave_to_port(dev); -+ dp = dsa_slave_to_port(dev); - -- switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC); -- if (!switchdev_work) -- return NOTIFY_BAD; -- -- INIT_WORK(&switchdev_work->work, -- dsa_slave_switchdev_event_work); -- switchdev_work->ds = dp->ds; -- switchdev_work->port = dp->index; -- switchdev_work->event = event; -+ switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC); -+ if (!switchdev_work) -+ return NOTIFY_BAD; -+ -+ INIT_WORK(&switchdev_work->work, -+ dsa_slave_switchdev_event_work); -+ switchdev_work->ds = dp->ds; -+ switchdev_work->port = dp->index; -+ switchdev_work->event = event; - -- switch (event) { -- case SWITCHDEV_FDB_ADD_TO_DEVICE: -- case SWITCHDEV_FDB_DEL_TO_DEVICE: - fdb_info = ptr; - - if (!fdb_info->added_by_user) { -@@ -2196,13 +2194,12 @@ static int dsa_slave_switchdev_event(str - switchdev_work->vid = fdb_info->vid; - - dev_hold(dev); -+ dsa_schedule_work(&switchdev_work->work); - break; - default: -- kfree(switchdev_work); - return NOTIFY_DONE; - } - -- dsa_schedule_work(&switchdev_work->work); - return NOTIFY_OK; - } - diff --git a/target/linux/generic/backport-5.10/724-v5.12-net-dsa-exit-early-in-dsa_slave_switchdev_event-if-w.patch b/target/linux/generic/backport-5.10/724-v5.12-net-dsa-exit-early-in-dsa_slave_switchdev_event-if-w.patch deleted file mode 100644 index b7b6ebe461..0000000000 --- a/target/linux/generic/backport-5.10/724-v5.12-net-dsa-exit-early-in-dsa_slave_switchdev_event-if-w.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 5fb4a451a87d8ed3363d28b63a3295399373d6c4 Mon Sep 17 00:00:00 2001 -From: Vladimir Oltean -Date: Wed, 6 Jan 2021 11:51:34 +0200 -Subject: [PATCH] net: dsa: exit early in dsa_slave_switchdev_event if we can't - program the FDB - -Right now, the following would happen for a switch driver that does not -implement .port_fdb_add or .port_fdb_del. - -dsa_slave_switchdev_event returns NOTIFY_OK and schedules: --> dsa_slave_switchdev_event_work - -> dsa_port_fdb_add - -> dsa_port_notify(DSA_NOTIFIER_FDB_ADD) - -> dsa_switch_fdb_add - -> if (!ds->ops->port_fdb_add) return -EOPNOTSUPP; - -> an error is printed with dev_dbg, and - dsa_fdb_offload_notify(switchdev_work) is not called. - -We can avoid scheduling the worker for nothing and say NOTIFY_DONE. -Because we don't call dsa_fdb_offload_notify, the static FDB entry will -remain just in the software bridge. - -Signed-off-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Reviewed-by: Andrew Lunn -Signed-off-by: Jakub Kicinski ---- - net/dsa/slave.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -2172,6 +2172,9 @@ static int dsa_slave_switchdev_event(str - - dp = dsa_slave_to_port(dev); - -+ if (!dp->ds->ops->port_fdb_add || !dp->ds->ops->port_fdb_del) -+ return NOTIFY_DONE; -+ - switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC); - if (!switchdev_work) - return NOTIFY_BAD; diff --git a/target/linux/generic/backport-5.10/725-v5.12-net-dsa-listen-for-SWITCHDEV_-FDB-DEL-_ADD_TO_DEVICE.patch b/target/linux/generic/backport-5.10/725-v5.12-net-dsa-listen-for-SWITCHDEV_-FDB-DEL-_ADD_TO_DEVICE.patch deleted file mode 100644 index e7b9af1951..0000000000 --- a/target/linux/generic/backport-5.10/725-v5.12-net-dsa-listen-for-SWITCHDEV_-FDB-DEL-_ADD_TO_DEVICE.patch +++ /dev/null @@ -1,264 +0,0 @@ -From d5f19486cee79d04c054427577ac96ed123706db Mon Sep 17 00:00:00 2001 -From: Vladimir Oltean -Date: Wed, 6 Jan 2021 11:51:35 +0200 -Subject: [PATCH] net: dsa: listen for SWITCHDEV_{FDB,DEL}_ADD_TO_DEVICE on - foreign bridge neighbors - -Some DSA switches (and not only) cannot learn source MAC addresses from -packets injected from the CPU. They only perform hardware address -learning from inbound traffic. - -This can be problematic when we have a bridge spanning some DSA switch -ports and some non-DSA ports (which we'll call "foreign interfaces" from -DSA's perspective). - -There are 2 classes of problems created by the lack of learning on -CPU-injected traffic: -- excessive flooding, due to the fact that DSA treats those addresses as - unknown -- the risk of stale routes, which can lead to temporary packet loss - -To illustrate the second class, consider the following situation, which -is common in production equipment (wireless access points, where there -is a WLAN interface and an Ethernet switch, and these form a single -bridging domain). - - AP 1: - +------------------------------------------------------------------------+ - | br0 | - +------------------------------------------------------------------------+ - +------------+ +------------+ +------------+ +------------+ +------------+ - | swp0 | | swp1 | | swp2 | | swp3 | | wlan0 | - +------------+ +------------+ +------------+ +------------+ +------------+ - | ^ ^ - | | | - | | | - | Client A Client B - | - | - | - +------------+ +------------+ +------------+ +------------+ +------------+ - | swp0 | | swp1 | | swp2 | | swp3 | | wlan0 | - +------------+ +------------+ +------------+ +------------+ +------------+ - +------------------------------------------------------------------------+ - | br0 | - +------------------------------------------------------------------------+ - AP 2 - -- br0 of AP 1 will know that Clients A and B are reachable via wlan0 -- the hardware fdb of a DSA switch driver today is not kept in sync with - the software entries on other bridge ports, so it will not know that - clients A and B are reachable via the CPU port UNLESS the hardware - switch itself performs SA learning from traffic injected from the CPU. - Nonetheless, a substantial number of switches don't. -- the hardware fdb of the DSA switch on AP 2 may autonomously learn that - Client A and B are reachable through swp0. Therefore, the software br0 - of AP 2 also may or may not learn this. In the example we're - illustrating, some Ethernet traffic has been going on, and br0 from AP - 2 has indeed learnt that it can reach Client B through swp0. - -One of the wireless clients, say Client B, disconnects from AP 1 and -roams to AP 2. The topology now looks like this: - - AP 1: - +------------------------------------------------------------------------+ - | br0 | - +------------------------------------------------------------------------+ - +------------+ +------------+ +------------+ +------------+ +------------+ - | swp0 | | swp1 | | swp2 | | swp3 | | wlan0 | - +------------+ +------------+ +------------+ +------------+ +------------+ - | ^ - | | - | Client A - | - | - | Client B - | | - | v - +------------+ +------------+ +------------+ +------------+ +------------+ - | swp0 | | swp1 | | swp2 | | swp3 | | wlan0 | - +------------+ +------------+ +------------+ +------------+ +------------+ - +------------------------------------------------------------------------+ - | br0 | - +------------------------------------------------------------------------+ - AP 2 - -- br0 of AP 1 still knows that Client A is reachable via wlan0 (no change) -- br0 of AP 1 will (possibly) know that Client B has left wlan0. There - are cases where it might never find out though. Either way, DSA today - does not process that notification in any way. -- the hardware FDB of the DSA switch on AP 1 may learn autonomously that - Client B can be reached via swp0, if it receives any packet with - Client 1's source MAC address over Ethernet. -- the hardware FDB of the DSA switch on AP 2 still thinks that Client B - can be reached via swp0. It does not know that it has roamed to wlan0, - because it doesn't perform SA learning from the CPU port. - -Now Client A contacts Client B. -AP 1 routes the packet fine towards swp0 and delivers it on the Ethernet -segment. -AP 2 sees a frame on swp0 and its fdb says that the destination is swp0. -Hairpinning is disabled => drop. - -This problem comes from the fact that these switches have a 'blind spot' -for addresses coming from software bridging. The generic solution is not -to assume that hardware learning can be enabled somehow, but to listen -to more bridge learning events. It turns out that the bridge driver does -learn in software from all inbound frames, in __br_handle_local_finish. -A proper SWITCHDEV_FDB_ADD_TO_DEVICE notification is emitted for the -addresses serviced by the bridge on 'foreign' interfaces. The software -bridge also does the right thing on migration, by notifying that the old -entry is deleted, so that does not need to be special-cased in DSA. When -it is deleted, we just need to delete our static FDB entry towards the -CPU too, and wait. - -The problem is that DSA currently only cares about SWITCHDEV_FDB_ADD_TO_DEVICE -events received on its own interfaces, such as static FDB entries. - -Luckily we can change that, and DSA can listen to all switchdev FDB -add/del events in the system and figure out if those events were emitted -by a bridge that spans at least one of DSA's own ports. In case that is -true, DSA will also offload that address towards its own CPU port, in -the eventuality that there might be bridge clients attached to the DSA -switch who want to talk to the station connected to the foreign -interface. - -In terms of implementation, we need to keep the fdb_info->added_by_user -check for the case where the switchdev event was targeted directly at a -DSA switch port. But we don't need to look at that flag for snooped -events. So the check is currently too late, we need to move it earlier. -This also simplifies the code a bit, since we avoid uselessly allocating -and freeing switchdev_work. - -We could probably do some improvements in the future. For example, -multi-bridge support is rudimentary at the moment. If there are two -bridges spanning a DSA switch's ports, and both of them need to service -the same MAC address, then what will happen is that the migration of one -of those stations will trigger the deletion of the FDB entry from the -CPU port while it is still used by other bridge. That could be improved -with reference counting but is left for another time. - -This behavior needs to be enabled at driver level by setting -ds->assisted_learning_on_cpu_port = true. This is because we don't want -to inflict a potential performance penalty (accesses through -MDIO/I2C/SPI are expensive) to hardware that really doesn't need it -because address learning on the CPU port works there. - -Reported-by: DENG Qingfang -Signed-off-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Reviewed-by: Andrew Lunn -Signed-off-by: Jakub Kicinski ---- - include/net/dsa.h | 5 +++++ - net/dsa/slave.c | 66 +++++++++++++++++++++++++++++++++++++++++++++---------- - 2 files changed, 60 insertions(+), 11 deletions(-) - ---- a/include/net/dsa.h -+++ b/include/net/dsa.h -@@ -317,6 +317,11 @@ struct dsa_switch { - */ - bool untag_bridge_pvid; - -+ /* Let DSA manage the FDB entries towards the CPU, based on the -+ * software bridge database. -+ */ -+ bool assisted_learning_on_cpu_port; -+ - /* In case vlan_filtering_is_global is set, the VLAN awareness state - * should be retrieved from here and not from the per-port settings. - */ ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -2149,6 +2149,28 @@ static void dsa_slave_switchdev_event_wo - dev_put(dp->slave); - } - -+static int dsa_lower_dev_walk(struct net_device *lower_dev, -+ struct netdev_nested_priv *priv) -+{ -+ if (dsa_slave_dev_check(lower_dev)) { -+ priv->data = (void *)netdev_priv(lower_dev); -+ return 1; -+ } -+ -+ return 0; -+} -+ -+static struct dsa_slave_priv *dsa_slave_dev_lower_find(struct net_device *dev) -+{ -+ struct netdev_nested_priv priv = { -+ .data = NULL, -+ }; -+ -+ netdev_walk_all_lower_dev_rcu(dev, dsa_lower_dev_walk, &priv); -+ -+ return (struct dsa_slave_priv *)priv.data; -+} -+ - /* Called under rcu_read_lock() */ - static int dsa_slave_switchdev_event(struct notifier_block *unused, - unsigned long event, void *ptr) -@@ -2167,10 +2189,37 @@ static int dsa_slave_switchdev_event(str - return notifier_from_errno(err); - case SWITCHDEV_FDB_ADD_TO_DEVICE: - case SWITCHDEV_FDB_DEL_TO_DEVICE: -- if (!dsa_slave_dev_check(dev)) -- return NOTIFY_DONE; -+ fdb_info = ptr; -+ -+ if (dsa_slave_dev_check(dev)) { -+ if (!fdb_info->added_by_user) -+ return NOTIFY_OK; -+ -+ dp = dsa_slave_to_port(dev); -+ } else { -+ /* Snoop addresses learnt on foreign interfaces -+ * bridged with us, for switches that don't -+ * automatically learn SA from CPU-injected traffic -+ */ -+ struct net_device *br_dev; -+ struct dsa_slave_priv *p; -+ -+ br_dev = netdev_master_upper_dev_get_rcu(dev); -+ if (!br_dev) -+ return NOTIFY_DONE; -+ -+ if (!netif_is_bridge_master(br_dev)) -+ return NOTIFY_DONE; -+ -+ p = dsa_slave_dev_lower_find(br_dev); -+ if (!p) -+ return NOTIFY_DONE; - -- dp = dsa_slave_to_port(dev); -+ dp = p->dp->cpu_dp; -+ -+ if (!dp->ds->assisted_learning_on_cpu_port) -+ return NOTIFY_DONE; -+ } - - if (!dp->ds->ops->port_fdb_add || !dp->ds->ops->port_fdb_del) - return NOTIFY_DONE; -@@ -2185,18 +2234,13 @@ static int dsa_slave_switchdev_event(str - switchdev_work->port = dp->index; - switchdev_work->event = event; - -- fdb_info = ptr; -- -- if (!fdb_info->added_by_user) { -- kfree(switchdev_work); -- return NOTIFY_OK; -- } -- - ether_addr_copy(switchdev_work->addr, - fdb_info->addr); - switchdev_work->vid = fdb_info->vid; - -- dev_hold(dev); -+ /* Hold a reference on the slave for dsa_fdb_offload_notify */ -+ if (dsa_is_user_port(dp->ds, dp->index)) -+ dev_hold(dev); - dsa_schedule_work(&switchdev_work->work); - break; - default: diff --git a/target/linux/generic/backport-5.10/729-v5.14-net-phy-at803x-mask-1000-Base-X-link-mode.patch b/target/linux/generic/backport-5.10/729-v5.14-net-phy-at803x-mask-1000-Base-X-link-mode.patch deleted file mode 100644 index a977db0b6c..0000000000 --- a/target/linux/generic/backport-5.10/729-v5.14-net-phy-at803x-mask-1000-Base-X-link-mode.patch +++ /dev/null @@ -1,68 +0,0 @@ -From b856150c8098f12996ee81c3ab2a65adbaeeb3ec Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sun, 27 Jun 2021 12:16:07 +0200 -Subject: [PATCH] net: phy: at803x: mask 1000 Base-X link mode - -AR8031/AR8033 have different status registers for copper -and fiber operation. However, the extended status register -is the same for both operation modes. - -As a result of that, ESTATUS_1000_XFULL is set to 1 even when -operating in copper TP mode. - -Remove this mode from the supported link modes, as this driver -currently only supports copper operation. - -Signed-off-by: David Bauer -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 30 +++++++++++++++++++++++++++++- - 1 file changed, 29 insertions(+), 1 deletion(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -583,6 +583,34 @@ static void at803x_remove(struct phy_dev - regulator_disable(priv->vddio); - } - -+static int at803x_get_features(struct phy_device *phydev) -+{ -+ int err; -+ -+ err = genphy_read_abilities(phydev); -+ if (err) -+ return err; -+ -+ if (!at803x_match_phy_id(phydev, ATH8031_PHY_ID)) -+ return 0; -+ -+ /* AR8031/AR8033 have different status registers -+ * for copper and fiber operation. However, the -+ * extended status register is the same for both -+ * operation modes. -+ * -+ * As a result of that, ESTATUS_1000_XFULL is set -+ * to 1 even when operating in copper TP mode. -+ * -+ * Remove this mode from the supported link modes, -+ * as this driver currently only supports copper -+ * operation. -+ */ -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, -+ phydev->supported); -+ return 0; -+} -+ - static int at803x_clk_out_config(struct phy_device *phydev) - { - struct at803x_priv *priv = phydev->priv; -@@ -1156,7 +1184,7 @@ static struct phy_driver at803x_driver[] - .resume = at803x_resume, - .read_page = at803x_read_page, - .write_page = at803x_write_page, -- /* PHY_GBIT_FEATURES */ -+ .get_features = at803x_get_features, - .read_status = at803x_read_status, - .aneg_done = at803x_aneg_done, - .ack_interrupt = &at803x_ack_interrupt, diff --git a/target/linux/generic/backport-5.10/730-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch b/target/linux/generic/backport-5.10/730-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch deleted file mode 100644 index f3a6f948ad..0000000000 --- a/target/linux/generic/backport-5.10/730-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch +++ /dev/null @@ -1,84 +0,0 @@ -From c3b8e07909dbe67b0d580416c1a5257643a73be7 Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Fri, 12 Mar 2021 00:07:03 -0800 -Subject: [PATCH] net: dsa: mt7530: setup core clock even in TRGMII mode - -A recent change to MIPS ralink reset logic made it so mt7530 actually -resets the switch on platforms such as mt7621 (where bit 2 is the reset -line for the switch). That exposed an issue where the switch would not -function properly in TRGMII mode after a reset. - -Reconfigure core clock in TRGMII mode to fix the issue. - -Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled. - -Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines") -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: David S. Miller ---- - drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++--------------------- - 1 file changed, 25 insertions(+), 27 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch * - TD_DM_DRVP(8) | TD_DM_DRVN(8)); - - /* Setup core clock for MT7530 */ -- if (!trgint) { -- /* Disable MT7530 core clock */ -- core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); -- -- /* Disable PLL, since phy_device has not yet been created -- * provided for phy_[read,write]_mmd_indirect is called, we -- * provide our own core_write_mmd_indirect to complete this -- * function. -- */ -- core_write_mmd_indirect(priv, -- CORE_GSWPLL_GRP1, -- MDIO_MMD_VEND2, -- 0); -- -- /* Set core clock into 500Mhz */ -- core_write(priv, CORE_GSWPLL_GRP2, -- RG_GSWPLL_POSDIV_500M(1) | -- RG_GSWPLL_FBKDIV_500M(25)); -- -- /* Enable PLL */ -- core_write(priv, CORE_GSWPLL_GRP1, -- RG_GSWPLL_EN_PRE | -- RG_GSWPLL_POSDIV_200M(2) | -- RG_GSWPLL_FBKDIV_200M(32)); -- -- /* Enable MT7530 core clock */ -- core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); -- } -+ /* Disable MT7530 core clock */ -+ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); -+ -+ /* Disable PLL, since phy_device has not yet been created -+ * provided for phy_[read,write]_mmd_indirect is called, we -+ * provide our own core_write_mmd_indirect to complete this -+ * function. -+ */ -+ core_write_mmd_indirect(priv, -+ CORE_GSWPLL_GRP1, -+ MDIO_MMD_VEND2, -+ 0); -+ -+ /* Set core clock into 500Mhz */ -+ core_write(priv, CORE_GSWPLL_GRP2, -+ RG_GSWPLL_POSDIV_500M(1) | -+ RG_GSWPLL_FBKDIV_500M(25)); -+ -+ /* Enable PLL */ -+ core_write(priv, CORE_GSWPLL_GRP1, -+ RG_GSWPLL_EN_PRE | -+ RG_GSWPLL_POSDIV_200M(2) | -+ RG_GSWPLL_FBKDIV_200M(32)); -+ -+ /* Enable MT7530 core clock */ -+ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); - - /* Setup the MT7530 TRGMII Tx Clock */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); diff --git a/target/linux/generic/backport-5.10/731-v5.12-net-dsa-mt7530-MT7530-optional-GPIO-support.patch b/target/linux/generic/backport-5.10/731-v5.12-net-dsa-mt7530-MT7530-optional-GPIO-support.patch deleted file mode 100644 index bd60df37e3..0000000000 --- a/target/linux/generic/backport-5.10/731-v5.12-net-dsa-mt7530-MT7530-optional-GPIO-support.patch +++ /dev/null @@ -1,181 +0,0 @@ -From 429a0edeefd88cbfca5c417dfb8561047bb50769 Mon Sep 17 00:00:00 2001 -From: DENG Qingfang -Date: Mon, 25 Jan 2021 12:43:22 +0800 -Subject: [PATCH] net: dsa: mt7530: MT7530 optional GPIO support - -MT7530's LED controller can drive up to 15 LED/GPIOs. - -Add support for GPIO control and allow users to use its GPIOs by -setting gpio-controller property in device tree. - -Signed-off-by: DENG Qingfang -Reviewed-by: Linus Walleij -Reviewed-by: Andrew Lunn -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/mt7530.c | 110 +++++++++++++++++++++++++++++++++++++++ - drivers/net/dsa/mt7530.h | 20 +++++++ - 2 files changed, 130 insertions(+) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -18,6 +18,7 @@ - #include - #include - #include -+#include - #include - - #include "mt7530.h" -@@ -1537,6 +1538,109 @@ mtk_get_tag_protocol(struct dsa_switch * - } - } - -+static inline u32 -+mt7530_gpio_to_bit(unsigned int offset) -+{ -+ /* Map GPIO offset to register bit -+ * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 -+ * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 -+ * [10: 8] port 2 LED 0..2 as GPIO 6..8 -+ * [14:12] port 3 LED 0..2 as GPIO 9..11 -+ * [18:16] port 4 LED 0..2 as GPIO 12..14 -+ */ -+ return BIT(offset + offset / 3); -+} -+ -+static int -+mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) -+{ -+ struct mt7530_priv *priv = gpiochip_get_data(gc); -+ u32 bit = mt7530_gpio_to_bit(offset); -+ -+ return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); -+} -+ -+static void -+mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) -+{ -+ struct mt7530_priv *priv = gpiochip_get_data(gc); -+ u32 bit = mt7530_gpio_to_bit(offset); -+ -+ if (value) -+ mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); -+ else -+ mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); -+} -+ -+static int -+mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) -+{ -+ struct mt7530_priv *priv = gpiochip_get_data(gc); -+ u32 bit = mt7530_gpio_to_bit(offset); -+ -+ return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? -+ GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; -+} -+ -+static int -+mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) -+{ -+ struct mt7530_priv *priv = gpiochip_get_data(gc); -+ u32 bit = mt7530_gpio_to_bit(offset); -+ -+ mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); -+ mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); -+ -+ return 0; -+} -+ -+static int -+mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) -+{ -+ struct mt7530_priv *priv = gpiochip_get_data(gc); -+ u32 bit = mt7530_gpio_to_bit(offset); -+ -+ mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); -+ -+ if (value) -+ mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); -+ else -+ mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); -+ -+ mt7530_set(priv, MT7530_LED_GPIO_OE, bit); -+ -+ return 0; -+} -+ -+static int -+mt7530_setup_gpio(struct mt7530_priv *priv) -+{ -+ struct device *dev = priv->dev; -+ struct gpio_chip *gc; -+ -+ gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); -+ if (!gc) -+ return -ENOMEM; -+ -+ mt7530_write(priv, MT7530_LED_GPIO_OE, 0); -+ mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); -+ mt7530_write(priv, MT7530_LED_IO_MODE, 0); -+ -+ gc->label = "mt7530"; -+ gc->parent = dev; -+ gc->owner = THIS_MODULE; -+ gc->get_direction = mt7530_gpio_get_direction; -+ gc->direction_input = mt7530_gpio_direction_input; -+ gc->direction_output = mt7530_gpio_direction_output; -+ gc->get = mt7530_gpio_get; -+ gc->set = mt7530_gpio_set; -+ gc->base = -1; -+ gc->ngpio = 15; -+ gc->can_sleep = true; -+ -+ return devm_gpiochip_add_data(dev, gc, priv); -+} -+ - static int - mt7530_setup(struct dsa_switch *ds) - { -@@ -1679,6 +1783,12 @@ mt7530_setup(struct dsa_switch *ds) - } - } - -+ if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { -+ ret = mt7530_setup_gpio(priv); -+ if (ret) -+ return ret; -+ } -+ - mt7530_setup_port5(ds, interface); - - /* Flush the FDB table */ ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -529,6 +529,26 @@ enum mt7531_clk_skew { - #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) - #define MT7531_EXT_P_MDIO_12 (2 << 16) - -+/* Registers for LED GPIO control (MT7530 only) -+ * All registers follow this pattern: -+ * [ 2: 0] port 0 -+ * [ 6: 4] port 1 -+ * [10: 8] port 2 -+ * [14:12] port 3 -+ * [18:16] port 4 -+ */ -+ -+/* LED enable, 0: Disable, 1: Enable (Default) */ -+#define MT7530_LED_EN 0x7d00 -+/* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ -+#define MT7530_LED_IO_MODE 0x7d04 -+/* GPIO direction, 0: Input, 1: Output */ -+#define MT7530_LED_GPIO_DIR 0x7d10 -+/* GPIO output enable, 0: Disable, 1: Enable */ -+#define MT7530_LED_GPIO_OE 0x7d14 -+/* GPIO value, 0: Low, 1: High */ -+#define MT7530_LED_GPIO_DATA 0x7d18 -+ - #define MT7530_CREV 0x7ffc - #define CHIP_NAME_SHIFT 16 - #define MT7530_ID 0x7530 diff --git a/target/linux/generic/backport-5.10/731-v5.13-net-dsa-mt7530-Add-support-for-EEE-features.patch b/target/linux/generic/backport-5.10/731-v5.13-net-dsa-mt7530-Add-support-for-EEE-features.patch deleted file mode 100644 index 2ba6c604a8..0000000000 --- a/target/linux/generic/backport-5.10/731-v5.13-net-dsa-mt7530-Add-support-for-EEE-features.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 40b5d2f15c091fa9c854acde91ad2acb504027d7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= -Date: Mon, 12 Apr 2021 08:50:31 +0200 -Subject: [PATCH] net: dsa: mt7530: Add support for EEE features -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This patch adds EEE support. - -Signed-off-by: René van Dorst -Signed-off-by: David S. Miller ---- - drivers/net/dsa/mt7530.c | 43 ++++++++++++++++++++++++++++++++++++++++ - drivers/net/dsa/mt7530.h | 14 ++++++++++++- - 2 files changed, 56 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -2371,6 +2371,17 @@ static void mt753x_phylink_mac_link_up(s - mcr |= PMCR_RX_FC_EN; - } - -+ if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) { -+ switch (speed) { -+ case SPEED_1000: -+ mcr |= PMCR_FORCE_EEE1G; -+ break; -+ case SPEED_100: -+ mcr |= PMCR_FORCE_EEE100; -+ break; -+ } -+ } -+ - mt7530_set(priv, MT7530_PMCR_P(port), mcr); - } - -@@ -2599,6 +2610,36 @@ mt753x_phy_write(struct dsa_switch *ds, - return priv->info->phy_write(ds, port, regnum, val); - } - -+static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, -+ struct ethtool_eee *e) -+{ -+ struct mt7530_priv *priv = ds->priv; -+ u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); -+ -+ e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); -+ e->tx_lpi_timer = GET_LPI_THRESH(eeecr); -+ -+ return 0; -+} -+ -+static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, -+ struct ethtool_eee *e) -+{ -+ struct mt7530_priv *priv = ds->priv; -+ u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; -+ -+ if (e->tx_lpi_timer > 0xFFF) -+ return -EINVAL; -+ -+ set = SET_LPI_THRESH(e->tx_lpi_timer); -+ if (!e->tx_lpi_enabled) -+ /* Force LPI Mode without a delay */ -+ set |= LPI_MODE_EN; -+ mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); -+ -+ return 0; -+} -+ - static const struct dsa_switch_ops mt7530_switch_ops = { - .get_tag_protocol = mtk_get_tag_protocol, - .setup = mt753x_setup, -@@ -2627,6 +2668,8 @@ static const struct dsa_switch_ops mt753 - .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, - .phylink_mac_link_down = mt753x_phylink_mac_link_down, - .phylink_mac_link_up = mt753x_phylink_mac_link_up, -+ .get_mac_eee = mt753x_get_mac_eee, -+ .set_mac_eee = mt753x_set_mac_eee, - }; - - static const struct mt753x_info mt753x_table[] = { ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -240,6 +240,8 @@ enum mt7530_vlan_port_attr { - #define PMCR_RX_EN BIT(13) - #define PMCR_BACKOFF_EN BIT(9) - #define PMCR_BACKPR_EN BIT(8) -+#define PMCR_FORCE_EEE1G BIT(7) -+#define PMCR_FORCE_EEE100 BIT(6) - #define PMCR_TX_FC_EN BIT(5) - #define PMCR_RX_FC_EN BIT(4) - #define PMCR_FORCE_SPEED_1000 BIT(3) -@@ -264,7 +266,8 @@ enum mt7530_vlan_port_attr { - #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ - PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ - PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ -- PMCR_FORCE_FDX | PMCR_FORCE_LNK) -+ PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ -+ PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) - #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \ - PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ - PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ -@@ -273,6 +276,15 @@ enum mt7530_vlan_port_attr { - PMCR_FORCE_SPEED_1000 | \ - PMCR_FORCE_FDX | PMCR_FORCE_LNK) - -+#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) -+#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) -+#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) -+#define LPI_THRESH_MASK GENMASK(15, 4) -+#define LPI_THRESH_SHT 4 -+#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) -+#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) -+#define LPI_MODE_EN BIT(0) -+ - #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) - #define PMSR_EEE1G BIT(7) - #define PMSR_EEE100M BIT(6) diff --git a/target/linux/generic/backport-5.10/732-v5.13-0003-of-base-Fix-some-formatting-issues-and-provide-missi.patch b/target/linux/generic/backport-5.10/732-v5.13-0003-of-base-Fix-some-formatting-issues-and-provide-missi.patch deleted file mode 100644 index 33808f88a3..0000000000 --- a/target/linux/generic/backport-5.10/732-v5.13-0003-of-base-Fix-some-formatting-issues-and-provide-missi.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 3637d49e11219512920aca8b8ccd0994be33fa8b Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Thu, 18 Mar 2021 10:40:30 +0000 -Subject: [PATCH] of: base: Fix some formatting issues and provide missing - descriptions - -Fixes the following W=1 kernel build warning(s): - - drivers/of/base.c:315: warning: Function parameter or member 'cpun' not described in '__of_find_n_match_cpu_property' - drivers/of/base.c:315: warning: Function parameter or member 'prop_name' not described in '__of_find_n_match_cpu_property' - drivers/of/base.c:315: warning: Function parameter or member 'cpu' not described in '__of_find_n_match_cpu_property' - drivers/of/base.c:315: warning: Function parameter or member 'thread' not described in '__of_find_n_match_cpu_property' - drivers/of/base.c:315: warning: expecting prototype for property holds the physical id of the(). Prototype was for __of_find_n_match_cpu_property() instead - drivers/of/base.c:1139: warning: Function parameter or member 'match' not described in 'of_find_matching_node_and_match' - drivers/of/base.c:1779: warning: Function parameter or member 'np' not described in '__of_add_property' - drivers/of/base.c:1779: warning: Function parameter or member 'prop' not described in '__of_add_property' - drivers/of/base.c:1800: warning: Function parameter or member 'np' not described in 'of_add_property' - drivers/of/base.c:1800: warning: Function parameter or member 'prop' not described in 'of_add_property' - drivers/of/base.c:1849: warning: Function parameter or member 'np' not described in 'of_remove_property' - drivers/of/base.c:1849: warning: Function parameter or member 'prop' not described in 'of_remove_property' - drivers/of/base.c:2137: warning: Function parameter or member 'dn' not described in 'of_console_check' - drivers/of/base.c:2137: warning: Function parameter or member 'name' not described in 'of_console_check' - drivers/of/base.c:2137: warning: Function parameter or member 'index' not described in 'of_console_check' - -Cc: Rob Herring -Cc: Frank Rowand -Cc: "David S. Miller" -Cc: devicetree@vger.kernel.org -Signed-off-by: Lee Jones -Signed-off-by: Rob Herring -Link: https://lore.kernel.org/r/20210318104036.3175910-5-lee.jones@linaro.org ---- - drivers/of/base.c | 16 +++++++++++----- - 1 file changed, 11 insertions(+), 5 deletions(-) - ---- a/drivers/of/base.c -+++ b/drivers/of/base.c -@@ -305,7 +305,7 @@ bool __weak arch_match_cpu_phys_id(int c - return (u32)phys_id == cpu; - } - --/** -+/* - * Checks if the given "prop_name" property holds the physical id of the - * core/thread corresponding to the logical cpu 'cpu'. If 'thread' is not - * NULL, local thread number within the core is returned in it. -@@ -1128,7 +1128,7 @@ EXPORT_SYMBOL(of_match_node); - * will; typically, you pass what the previous call - * returned. of_node_put() will be called on it - * @matches: array of of device match structures to search in -- * @match Updated to point at the matches entry which matched -+ * @match: Updated to point at the matches entry which matched - * - * Returns a node pointer with refcount incremented, use - * of_node_put() on it when done. -@@ -1779,6 +1779,8 @@ EXPORT_SYMBOL(of_count_phandle_with_args - - /** - * __of_add_property - Add a property to a node without lock operations -+ * @np: Caller's Device Node -+ * @prob: Property to add - */ - int __of_add_property(struct device_node *np, struct property *prop) - { -@@ -1800,6 +1802,8 @@ int __of_add_property(struct device_node - - /** - * of_add_property - Add a property to a node -+ * @np: Caller's Device Node -+ * @prob: Property to add - */ - int of_add_property(struct device_node *np, struct property *prop) - { -@@ -1844,6 +1848,8 @@ int __of_remove_property(struct device_n - - /** - * of_remove_property - Remove a property from a node. -+ * @np: Caller's Device Node -+ * @prob: Property to remove - * - * Note that we don't actually remove it, since we have given out - * who-knows-how-many pointers to the data using get-property. -@@ -2130,9 +2136,9 @@ EXPORT_SYMBOL_GPL(of_alias_get_highest_i - - /** - * of_console_check() - Test and setup console for DT setup -- * @dn - Pointer to device node -- * @name - Name to use for preferred console without index. ex. "ttyS" -- * @index - Index to use for preferred console. -+ * @dn: Pointer to device node -+ * @name: Name to use for preferred console without index. ex. "ttyS" -+ * @index: Index to use for preferred console. - * - * Check if the given device node matches the stdout-path property in the - * /chosen node. If it does then register it as the preferred console and return diff --git a/target/linux/generic/backport-5.10/732-v5.13-0005-of-Fix-kerneldoc-output-formatting.patch b/target/linux/generic/backport-5.10/732-v5.13-0005-of-Fix-kerneldoc-output-formatting.patch deleted file mode 100644 index bda03b9c4c..0000000000 --- a/target/linux/generic/backport-5.10/732-v5.13-0005-of-Fix-kerneldoc-output-formatting.patch +++ /dev/null @@ -1,489 +0,0 @@ -From 62f026f082e4d762a47b43ea693b38f025122332 Mon Sep 17 00:00:00 2001 -From: Rob Herring -Date: Fri, 26 Mar 2021 13:26:06 -0600 -Subject: [PATCH] of: Fix kerneldoc output formatting - -The indentation of the kerneldoc comments affects the output formatting. -Leading tabs in particular don't work, sections need to be indented -under the section header, and several code blocks are reformatted. - -Cc: Frank Rowand -Cc: Mauro Carvalho Chehab -Signed-off-by: Rob Herring -Reviewed-by: Mauro Carvalho Chehab -Link: https://lore.kernel.org/r/20210326192606.3702739-1-robh@kernel.org ---- - drivers/of/base.c | 275 +++++++++++++++++++++++----------------------- - drivers/of/fdt.c | 9 +- - 2 files changed, 141 insertions(+), 143 deletions(-) - ---- a/drivers/of/base.c -+++ b/drivers/of/base.c -@@ -651,11 +651,11 @@ bool of_device_is_big_endian(const struc - EXPORT_SYMBOL(of_device_is_big_endian); - - /** -- * of_get_parent - Get a node's parent if any -- * @node: Node to get parent -+ * of_get_parent - Get a node's parent if any -+ * @node: Node to get parent - * -- * Returns a node pointer with refcount incremented, use -- * of_node_put() on it when done. -+ * Return: A node pointer with refcount incremented, use -+ * of_node_put() on it when done. - */ - struct device_node *of_get_parent(const struct device_node *node) - { -@@ -673,15 +673,15 @@ struct device_node *of_get_parent(const - EXPORT_SYMBOL(of_get_parent); - - /** -- * of_get_next_parent - Iterate to a node's parent -- * @node: Node to get parent of -+ * of_get_next_parent - Iterate to a node's parent -+ * @node: Node to get parent of - * -- * This is like of_get_parent() except that it drops the -- * refcount on the passed node, making it suitable for iterating -- * through a node's parents. -+ * This is like of_get_parent() except that it drops the -+ * refcount on the passed node, making it suitable for iterating -+ * through a node's parents. - * -- * Returns a node pointer with refcount incremented, use -- * of_node_put() on it when done. -+ * Return: A node pointer with refcount incremented, use -+ * of_node_put() on it when done. - */ - struct device_node *of_get_next_parent(struct device_node *node) - { -@@ -719,13 +719,13 @@ static struct device_node *__of_get_next - child = __of_get_next_child(parent, child)) - - /** -- * of_get_next_child - Iterate a node childs -- * @node: parent node -- * @prev: previous child of the parent node, or NULL to get first -- * -- * Returns a node pointer with refcount incremented, use of_node_put() on -- * it when done. Returns NULL when prev is the last child. Decrements the -- * refcount of prev. -+ * of_get_next_child - Iterate a node childs -+ * @node: parent node -+ * @prev: previous child of the parent node, or NULL to get first -+ * -+ * Return: A node pointer with refcount incremented, use of_node_put() on -+ * it when done. Returns NULL when prev is the last child. Decrements the -+ * refcount of prev. - */ - struct device_node *of_get_next_child(const struct device_node *node, - struct device_node *prev) -@@ -741,12 +741,12 @@ struct device_node *of_get_next_child(co - EXPORT_SYMBOL(of_get_next_child); - - /** -- * of_get_next_available_child - Find the next available child node -- * @node: parent node -- * @prev: previous child of the parent node, or NULL to get first -+ * of_get_next_available_child - Find the next available child node -+ * @node: parent node -+ * @prev: previous child of the parent node, or NULL to get first - * -- * This function is like of_get_next_child(), except that it -- * automatically skips any disabled nodes (i.e. status = "disabled"). -+ * This function is like of_get_next_child(), except that it -+ * automatically skips any disabled nodes (i.e. status = "disabled"). - */ - struct device_node *of_get_next_available_child(const struct device_node *node, - struct device_node *prev) -@@ -772,12 +772,12 @@ struct device_node *of_get_next_availabl - EXPORT_SYMBOL(of_get_next_available_child); - - /** -- * of_get_next_cpu_node - Iterate on cpu nodes -- * @prev: previous child of the /cpus node, or NULL to get first -+ * of_get_next_cpu_node - Iterate on cpu nodes -+ * @prev: previous child of the /cpus node, or NULL to get first - * -- * Returns a cpu node pointer with refcount incremented, use of_node_put() -- * on it when done. Returns NULL when prev is the last child. Decrements -- * the refcount of prev. -+ * Return: A cpu node pointer with refcount incremented, use of_node_put() -+ * on it when done. Returns NULL when prev is the last child. Decrements -+ * the refcount of prev. - */ - struct device_node *of_get_next_cpu_node(struct device_node *prev) - { -@@ -834,15 +834,15 @@ struct device_node *of_get_compatible_ch - EXPORT_SYMBOL(of_get_compatible_child); - - /** -- * of_get_child_by_name - Find the child node by name for a given parent -- * @node: parent node -- * @name: child name to look for. -- * -- * This function looks for child node for given matching name -- * -- * Returns a node pointer if found, with refcount incremented, use -- * of_node_put() on it when done. -- * Returns NULL if node is not found. -+ * of_get_child_by_name - Find the child node by name for a given parent -+ * @node: parent node -+ * @name: child name to look for. -+ * -+ * This function looks for child node for given matching name -+ * -+ * Return: A node pointer if found, with refcount incremented, use -+ * of_node_put() on it when done. -+ * Returns NULL if node is not found. - */ - struct device_node *of_get_child_by_name(const struct device_node *node, - const char *name) -@@ -893,22 +893,22 @@ struct device_node *__of_find_node_by_fu - } - - /** -- * of_find_node_opts_by_path - Find a node matching a full OF path -- * @path: Either the full path to match, or if the path does not -- * start with '/', the name of a property of the /aliases -- * node (an alias). In the case of an alias, the node -- * matching the alias' value will be returned. -- * @opts: Address of a pointer into which to store the start of -- * an options string appended to the end of the path with -- * a ':' separator. -- * -- * Valid paths: -- * /foo/bar Full path -- * foo Valid alias -- * foo/bar Valid alias + relative path -+ * of_find_node_opts_by_path - Find a node matching a full OF path -+ * @path: Either the full path to match, or if the path does not -+ * start with '/', the name of a property of the /aliases -+ * node (an alias). In the case of an alias, the node -+ * matching the alias' value will be returned. -+ * @opts: Address of a pointer into which to store the start of -+ * an options string appended to the end of the path with -+ * a ':' separator. -+ * -+ * Valid paths: -+ * * /foo/bar Full path -+ * * foo Valid alias -+ * * foo/bar Valid alias + relative path - * -- * Returns a node pointer with refcount incremented, use -- * of_node_put() on it when done. -+ * Return: A node pointer with refcount incremented, use -+ * of_node_put() on it when done. - */ - struct device_node *of_find_node_opts_by_path(const char *path, const char **opts) - { -@@ -958,15 +958,15 @@ struct device_node *of_find_node_opts_by - EXPORT_SYMBOL(of_find_node_opts_by_path); - - /** -- * of_find_node_by_name - Find a node by its "name" property -- * @from: The node to start searching from or NULL; the node -+ * of_find_node_by_name - Find a node by its "name" property -+ * @from: The node to start searching from or NULL; the node - * you pass will not be searched, only the next one - * will. Typically, you pass what the previous call - * returned. of_node_put() will be called on @from. -- * @name: The name string to match against -+ * @name: The name string to match against - * -- * Returns a node pointer with refcount incremented, use -- * of_node_put() on it when done. -+ * Return: A node pointer with refcount incremented, use -+ * of_node_put() on it when done. - */ - struct device_node *of_find_node_by_name(struct device_node *from, - const char *name) -@@ -985,16 +985,16 @@ struct device_node *of_find_node_by_name - EXPORT_SYMBOL(of_find_node_by_name); - - /** -- * of_find_node_by_type - Find a node by its "device_type" property -- * @from: The node to start searching from, or NULL to start searching -+ * of_find_node_by_type - Find a node by its "device_type" property -+ * @from: The node to start searching from, or NULL to start searching - * the entire device tree. The node you pass will not be - * searched, only the next one will; typically, you pass - * what the previous call returned. of_node_put() will be - * called on from for you. -- * @type: The type string to match against -+ * @type: The type string to match against - * -- * Returns a node pointer with refcount incremented, use -- * of_node_put() on it when done. -+ * Return: A node pointer with refcount incremented, use -+ * of_node_put() on it when done. - */ - struct device_node *of_find_node_by_type(struct device_node *from, - const char *type) -@@ -1013,18 +1013,18 @@ struct device_node *of_find_node_by_type - EXPORT_SYMBOL(of_find_node_by_type); - - /** -- * of_find_compatible_node - Find a node based on type and one of the -+ * of_find_compatible_node - Find a node based on type and one of the - * tokens in its "compatible" property -- * @from: The node to start searching from or NULL, the node -- * you pass will not be searched, only the next one -- * will; typically, you pass what the previous call -- * returned. of_node_put() will be called on it -- * @type: The type string to match "device_type" or NULL to ignore -- * @compatible: The string to match to one of the tokens in the device -- * "compatible" list. -+ * @from: The node to start searching from or NULL, the node -+ * you pass will not be searched, only the next one -+ * will; typically, you pass what the previous call -+ * returned. of_node_put() will be called on it -+ * @type: The type string to match "device_type" or NULL to ignore -+ * @compatible: The string to match to one of the tokens in the device -+ * "compatible" list. - * -- * Returns a node pointer with refcount incremented, use -- * of_node_put() on it when done. -+ * Return: A node pointer with refcount incremented, use -+ * of_node_put() on it when done. - */ - struct device_node *of_find_compatible_node(struct device_node *from, - const char *type, const char *compatible) -@@ -1044,16 +1044,16 @@ struct device_node *of_find_compatible_n - EXPORT_SYMBOL(of_find_compatible_node); - - /** -- * of_find_node_with_property - Find a node which has a property with -- * the given name. -- * @from: The node to start searching from or NULL, the node -- * you pass will not be searched, only the next one -- * will; typically, you pass what the previous call -- * returned. of_node_put() will be called on it -- * @prop_name: The name of the property to look for. -+ * of_find_node_with_property - Find a node which has a property with -+ * the given name. -+ * @from: The node to start searching from or NULL, the node -+ * you pass will not be searched, only the next one -+ * will; typically, you pass what the previous call -+ * returned. of_node_put() will be called on it -+ * @prop_name: The name of the property to look for. - * -- * Returns a node pointer with refcount incremented, use -- * of_node_put() on it when done. -+ * Return: A node pointer with refcount incremented, use -+ * of_node_put() on it when done. - */ - struct device_node *of_find_node_with_property(struct device_node *from, - const char *prop_name) -@@ -1102,10 +1102,10 @@ const struct of_device_id *__of_match_no - - /** - * of_match_node - Tell if a device_node has a matching of_match structure -- * @matches: array of of device match structures to search in -- * @node: the of device structure to match against -+ * @matches: array of of device match structures to search in -+ * @node: the of device structure to match against - * -- * Low level utility function used by device matching. -+ * Low level utility function used by device matching. - */ - const struct of_device_id *of_match_node(const struct of_device_id *matches, - const struct device_node *node) -@@ -1121,17 +1121,17 @@ const struct of_device_id *of_match_node - EXPORT_SYMBOL(of_match_node); - - /** -- * of_find_matching_node_and_match - Find a node based on an of_device_id -- * match table. -- * @from: The node to start searching from or NULL, the node -- * you pass will not be searched, only the next one -- * will; typically, you pass what the previous call -- * returned. of_node_put() will be called on it -- * @matches: array of of device match structures to search in -- * @match: Updated to point at the matches entry which matched -+ * of_find_matching_node_and_match - Find a node based on an of_device_id -+ * match table. -+ * @from: The node to start searching from or NULL, the node -+ * you pass will not be searched, only the next one -+ * will; typically, you pass what the previous call -+ * returned. of_node_put() will be called on it -+ * @matches: array of of device match structures to search in -+ * @match: Updated to point at the matches entry which matched - * -- * Returns a node pointer with refcount incremented, use -- * of_node_put() on it when done. -+ * Return: A node pointer with refcount incremented, use -+ * of_node_put() on it when done. - */ - struct device_node *of_find_matching_node_and_match(struct device_node *from, - const struct of_device_id *matches, -@@ -1465,21 +1465,21 @@ EXPORT_SYMBOL(of_parse_phandle); - * Caller is responsible to call of_node_put() on the returned out_args->np - * pointer. - * -- * Example: -+ * Example:: - * -- * phandle1: node1 { -+ * phandle1: node1 { - * #list-cells = <2>; -- * } -+ * }; - * -- * phandle2: node2 { -+ * phandle2: node2 { - * #list-cells = <1>; -- * } -+ * }; - * -- * node3 { -+ * node3 { - * list = <&phandle1 1 2 &phandle2 3>; -- * } -+ * }; - * -- * To get a device_node of the `node2' node you may call this: -+ * To get a device_node of the ``node2`` node you may call this: - * of_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args); - */ - int of_parse_phandle_with_args(const struct device_node *np, const char *list_name, -@@ -1517,29 +1517,29 @@ EXPORT_SYMBOL(of_parse_phandle_with_args - * Caller is responsible to call of_node_put() on the returned out_args->np - * pointer. - * -- * Example: -- * -- * phandle1: node1 { -- * #list-cells = <2>; -- * } -- * -- * phandle2: node2 { -- * #list-cells = <1>; -- * } -+ * Example:: - * -- * phandle3: node3 { -- * #list-cells = <1>; -- * list-map = <0 &phandle2 3>, -- * <1 &phandle2 2>, -- * <2 &phandle1 5 1>; -- * list-map-mask = <0x3>; -- * }; -- * -- * node4 { -- * list = <&phandle1 1 2 &phandle3 0>; -- * } -+ * phandle1: node1 { -+ * #list-cells = <2>; -+ * }; -+ * -+ * phandle2: node2 { -+ * #list-cells = <1>; -+ * }; -+ * -+ * phandle3: node3 { -+ * #list-cells = <1>; -+ * list-map = <0 &phandle2 3>, -+ * <1 &phandle2 2>, -+ * <2 &phandle1 5 1>; -+ * list-map-mask = <0x3>; -+ * }; -+ * -+ * node4 { -+ * list = <&phandle1 1 2 &phandle3 0>; -+ * }; - * -- * To get a device_node of the `node2' node you may call this: -+ * To get a device_node of the ``node2`` node you may call this: - * of_parse_phandle_with_args(node4, "list", "list", 1, &args); - */ - int of_parse_phandle_with_args_map(const struct device_node *np, -@@ -1699,19 +1699,19 @@ EXPORT_SYMBOL(of_parse_phandle_with_args - * Caller is responsible to call of_node_put() on the returned out_args->np - * pointer. - * -- * Example: -+ * Example:: - * -- * phandle1: node1 { -- * } -+ * phandle1: node1 { -+ * }; - * -- * phandle2: node2 { -- * } -+ * phandle2: node2 { -+ * }; - * -- * node3 { -- * list = <&phandle1 0 2 &phandle2 2 3>; -- * } -+ * node3 { -+ * list = <&phandle1 0 2 &phandle2 2 3>; -+ * }; - * -- * To get a device_node of the `node2' node you may call this: -+ * To get a device_node of the ``node2`` node you may call this: - * of_parse_phandle_with_fixed_args(node3, "list", 2, 1, &args); - */ - int of_parse_phandle_with_fixed_args(const struct device_node *np, -@@ -1957,13 +1957,12 @@ static void of_alias_add(struct alias_pr - - /** - * of_alias_scan - Scan all properties of the 'aliases' node -+ * @dt_alloc: An allocator that provides a virtual address to memory -+ * for storing the resulting tree - * - * The function scans all the properties of the 'aliases' node and populates - * the global lookup table with the properties. It returns the - * number of alias properties found, or an error code in case of failure. -- * -- * @dt_alloc: An allocator that provides a virtual address to memory -- * for storing the resulting tree - */ - void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align)) - { -@@ -2158,12 +2157,12 @@ bool of_console_check(struct device_node - EXPORT_SYMBOL_GPL(of_console_check); - - /** -- * of_find_next_cache_node - Find a node's subsidiary cache -- * @np: node of type "cpu" or "cache" -+ * of_find_next_cache_node - Find a node's subsidiary cache -+ * @np: node of type "cpu" or "cache" - * -- * Returns a node pointer with refcount incremented, use -- * of_node_put() on it when done. Caller should hold a reference -- * to np. -+ * Return: A node pointer with refcount incremented, use -+ * of_node_put() on it when done. Caller should hold a reference -+ * to np. - */ - struct device_node *of_find_next_cache_node(const struct device_node *np) - { ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -349,11 +349,6 @@ static int unflatten_dt_nodes(const void - - /** - * __unflatten_device_tree - create tree of device_nodes from flat blob -- * -- * unflattens a device-tree, creating the -- * tree of struct device_node. It also fills the "name" and "type" -- * pointers of the nodes so the normal device-tree walking functions -- * can be used. - * @blob: The blob to expand - * @dad: Parent device node - * @mynodes: The device_node tree created by the call -@@ -361,6 +356,10 @@ static int unflatten_dt_nodes(const void - * for the resulting tree - * @detached: if true set OF_DETACHED on @mynodes - * -+ * unflattens a device-tree, creating the tree of struct device_node. It also -+ * fills the "name" and "type" pointers of the nodes so the normal device-tree -+ * walking functions can be used. -+ * - * Returns NULL on failure or the memory chunk containing the unflattened - * device tree on success. - */ diff --git a/target/linux/generic/backport-5.10/732-v5.13-0006-of-Add-missing-Return-section-in-kerneldoc-comments.patch b/target/linux/generic/backport-5.10/732-v5.13-0006-of-Add-missing-Return-section-in-kerneldoc-comments.patch deleted file mode 100644 index 9c99ccb1db..0000000000 --- a/target/linux/generic/backport-5.10/732-v5.13-0006-of-Add-missing-Return-section-in-kerneldoc-comments.patch +++ /dev/null @@ -1,787 +0,0 @@ -From 8c8239c2c1fb82f171cb22a707f3bb88a2f22109 Mon Sep 17 00:00:00 2001 -From: Rob Herring -Date: Thu, 25 Mar 2021 10:47:12 -0600 -Subject: [PATCH] of: Add missing 'Return' section in kerneldoc comments - -Many of the DT kerneldoc comments are lacking a 'Return' section. Let's -add the section in cases we have a description of return values. There's -still some cases where the return values are not documented. - -Cc: Frank Rowand -Cc: Mauro Carvalho Chehab -Signed-off-by: Rob Herring -Reviewed-by: Mauro Carvalho Chehab -Link: https://lore.kernel.org/r/20210325164713.1296407-8-robh@kernel.org ---- - drivers/of/base.c | 39 +++++++++++++------------ - drivers/of/dynamic.c | 19 ++++++++----- - drivers/of/fdt.c | 8 +++--- - drivers/of/irq.c | 14 ++++----- - drivers/of/overlay.c | 16 +++++------ - drivers/of/platform.c | 10 +++---- - drivers/of/property.c | 66 +++++++++++++++++++++++++++---------------- - include/linux/of.h | 63 ++++++++++++++++++++++++++--------------- - 8 files changed, 140 insertions(+), 95 deletions(-) - ---- a/drivers/of/base.c -+++ b/drivers/of/base.c -@@ -244,7 +244,7 @@ struct device_node *__of_find_all_nodes( - * @prev: Previous node or NULL to start iteration - * of_node_put() will be called on it - * -- * Returns a node pointer with refcount incremented, use -+ * Return: A node pointer with refcount incremented, use - * of_node_put() on it when done. - */ - struct device_node *of_find_all_nodes(struct device_node *prev) -@@ -374,7 +374,7 @@ bool __weak arch_find_n_match_cpu_physic - * before booting secondary cores. This function uses arch_match_cpu_phys_id - * which can be overridden by architecture specific implementation. - * -- * Returns a node pointer for the logical cpu with refcount incremented, use -+ * Return: A node pointer for the logical cpu with refcount incremented, use - * of_node_put() on it when done. Returns NULL if not found. - */ - struct device_node *of_get_cpu_node(int cpu, unsigned int *thread) -@@ -394,8 +394,8 @@ EXPORT_SYMBOL(of_get_cpu_node); - * - * @cpu_node: Pointer to the device_node for CPU. - * -- * Returns the logical CPU number of the given CPU device_node. -- * Returns -ENODEV if the CPU is not found. -+ * Return: The logical CPU number of the given CPU device_node or -ENODEV if the -+ * CPU is not found. - */ - int of_cpu_node_to_id(struct device_node *cpu_node) - { -@@ -427,7 +427,7 @@ EXPORT_SYMBOL(of_cpu_node_to_id); - * bindings. This function check for both and returns the idle state node for - * the requested index. - * -- * In case an idle state node is found at @index, the refcount is incremented -+ * Return: An idle state node if found at @index. The refcount is incremented - * for it, so call of_node_put() on it when done. Returns NULL if not found. - */ - struct device_node *of_get_cpu_state_node(struct device_node *cpu_node, -@@ -561,7 +561,7 @@ int of_device_compatible_match(struct de - * of_machine_is_compatible - Test root of device tree for a given compatible value - * @compat: compatible string to look for in root node's compatible property. - * -- * Returns a positive integer if the root node has the given value in its -+ * Return: A positive integer if the root node has the given value in its - * compatible property. - */ - int of_machine_is_compatible(const char *compat) -@@ -583,7 +583,7 @@ EXPORT_SYMBOL(of_machine_is_compatible); - * - * @device: Node to check for availability, with locks already held - * -- * Returns true if the status property is absent or set to "okay" or "ok", -+ * Return: True if the status property is absent or set to "okay" or "ok", - * false otherwise - */ - static bool __of_device_is_available(const struct device_node *device) -@@ -611,7 +611,7 @@ static bool __of_device_is_available(con - * - * @device: Node to check for availability - * -- * Returns true if the status property is absent or set to "okay" or "ok", -+ * Return: True if the status property is absent or set to "okay" or "ok", - * false otherwise - */ - bool of_device_is_available(const struct device_node *device) -@@ -632,7 +632,7 @@ EXPORT_SYMBOL(of_device_is_available); - * - * @device: Node to check for endianness - * -- * Returns true if the device has a "big-endian" property, or if the kernel -+ * Return: True if the device has a "big-endian" property, or if the kernel - * was compiled for BE *and* the device has a "native-endian" property. - * Returns false otherwise. - * -@@ -816,7 +816,7 @@ EXPORT_SYMBOL(of_get_next_cpu_node); - * Lookup child node whose compatible property contains the given compatible - * string. - * -- * Returns a node pointer with refcount incremented, use of_node_put() on it -+ * Return: a node pointer with refcount incremented, use of_node_put() on it - * when done; or NULL if not found. - */ - struct device_node *of_get_compatible_child(const struct device_node *parent, -@@ -1170,7 +1170,7 @@ EXPORT_SYMBOL(of_find_matching_node_and_ - * It does this by stripping the manufacturer prefix (as delimited by a ',') - * from the first entry in the compatible list property. - * -- * This routine returns 0 on success, <0 on failure. -+ * Return: This routine returns 0 on success, <0 on failure. - */ - int of_modalias_node(struct device_node *node, char *modalias, int len) - { -@@ -1190,7 +1190,7 @@ EXPORT_SYMBOL_GPL(of_modalias_node); - * of_find_node_by_phandle - Find a node given a phandle - * @handle: phandle of the node to find - * -- * Returns a node pointer with refcount incremented, use -+ * Return: A node pointer with refcount incremented, use - * of_node_put() on it when done. - */ - struct device_node *of_find_node_by_phandle(phandle handle) -@@ -1431,7 +1431,7 @@ static int __of_parse_phandle_with_args( - * @index: For properties holding a table of phandles, this is the index into - * the table - * -- * Returns the device_node pointer with refcount incremented. Use -+ * Return: The device_node pointer with refcount incremented. Use - * of_node_put() on it when done. - */ - struct device_node *of_parse_phandle(const struct device_node *np, -@@ -1731,7 +1731,7 @@ EXPORT_SYMBOL(of_parse_phandle_with_fixe - * @list_name: property name that contains a list - * @cells_name: property name that specifies phandles' arguments count - * -- * Returns the number of phandle + argument tuples within a property. It -+ * Return: The number of phandle + argument tuples within a property. It - * is a typical pattern to encode a list of phandle and variable - * arguments into a single property. The number of arguments is encoded - * by a property in the phandle-target node. For example, a gpios -@@ -2031,7 +2031,9 @@ void of_alias_scan(void * (*dt_alloc)(u6 - * @stem: Alias stem of the given device_node - * - * The function travels the lookup table to get the alias id for the given -- * device_node and alias stem. It returns the alias id if found. -+ * device_node and alias stem. -+ * -+ * Return: The alias id if found. - */ - int of_alias_get_id(struct device_node *np, const char *stem) - { -@@ -2140,8 +2142,9 @@ EXPORT_SYMBOL_GPL(of_alias_get_highest_i - * @index: Index to use for preferred console. - * - * Check if the given device node matches the stdout-path property in the -- * /chosen node. If it does then register it as the preferred console and return -- * TRUE. Otherwise return FALSE. -+ * /chosen node. If it does then register it as the preferred console. -+ * -+ * Return: TRUE if console successfully setup. Otherwise return FALSE. - */ - bool of_console_check(struct device_node *dn, char *name, int index) - { -@@ -2192,7 +2195,7 @@ struct device_node *of_find_next_cache_n - * - * @cpu: cpu number(logical index) for which the last cache level is needed - * -- * Returns the the level at which the last cache is present. It is exactly -+ * Return: The the level at which the last cache is present. It is exactly - * same as the total number of cache levels for the given logical cpu. - */ - int of_find_last_cache_level(unsigned int cpu) ---- a/drivers/of/dynamic.c -+++ b/drivers/of/dynamic.c -@@ -27,7 +27,7 @@ static struct device_node *kobj_to_devic - * @node: Node to inc refcount, NULL is supported to simplify writing of - * callers - * -- * Returns node. -+ * Return: The node with refcount incremented. - */ - struct device_node *of_node_get(struct device_node *node) - { -@@ -104,7 +104,8 @@ int of_reconfig_notify(unsigned long act - * @arg - argument of the of notifier - * - * Returns the new state of a device based on the notifier used. -- * Returns 0 on device going from enabled to disabled, 1 on device -+ * -+ * Return: 0 on device going from enabled to disabled, 1 on device - * going from disabled to enabled and -1 on no change. - */ - int of_reconfig_get_state_change(unsigned long action, struct of_reconfig_data *pr) -@@ -371,7 +372,8 @@ void of_node_release(struct kobject *kob - * property structure and the property name & contents. The property's - * flags have the OF_DYNAMIC bit set so that we can differentiate between - * dynamically allocated properties and not. -- * Returns the newly allocated property or NULL on out of memory error. -+ * -+ * Return: The newly allocated property or NULL on out of memory error. - */ - struct property *__of_prop_dup(const struct property *prop, gfp_t allocflags) - { -@@ -414,7 +416,7 @@ struct property *__of_prop_dup(const str - * another node. The node data are dynamically allocated and all the node - * flags have the OF_DYNAMIC & OF_DETACHED bits set. - * -- * Returns the newly allocated node or NULL on out of memory error. -+ * Return: The newly allocated node or NULL on out of memory error. - */ - struct device_node *__of_node_dup(const struct device_node *np, - const char *full_name) -@@ -780,7 +782,8 @@ static int __of_changeset_apply(struct o - * Any side-effects of live tree state changes are applied here on - * success, like creation/destruction of devices and side-effects - * like creation of sysfs properties and directories. -- * Returns 0 on success, a negative error value in case of an error. -+ * -+ * Return: 0 on success, a negative error value in case of an error. - * On error the partially applied effects are reverted. - */ - int of_changeset_apply(struct of_changeset *ocs) -@@ -874,7 +877,8 @@ static int __of_changeset_revert(struct - * was before the application. - * Any side-effects like creation/destruction of devices and - * removal of sysfs properties and directories are applied. -- * Returns 0 on success, a negative error value in case of an error. -+ * -+ * Return: 0 on success, a negative error value in case of an error. - */ - int of_changeset_revert(struct of_changeset *ocs) - { -@@ -902,7 +906,8 @@ EXPORT_SYMBOL_GPL(of_changeset_revert); - * + OF_RECONFIG_ADD_PROPERTY - * + OF_RECONFIG_REMOVE_PROPERTY, - * + OF_RECONFIG_UPDATE_PROPERTY -- * Returns 0 on success, a negative error value in case of an error. -+ * -+ * Return: 0 on success, a negative error value in case of an error. - */ - int of_changeset_action(struct of_changeset *ocs, unsigned long action, - struct device_node *np, struct property *prop) ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -282,7 +282,7 @@ static void reverse_nodes(struct device_ - * @dad: Parent struct device_node - * @nodepp: The device_node tree created by the call - * -- * It returns the size of unflattened device tree or error code -+ * Return: The size of unflattened device tree or error code - */ - static int unflatten_dt_nodes(const void *blob, - void *mem, -@@ -360,7 +360,7 @@ static int unflatten_dt_nodes(const void - * fills the "name" and "type" pointers of the nodes so the normal device-tree - * walking functions can be used. - * -- * Returns NULL on failure or the memory chunk containing the unflattened -+ * Return: NULL on failure or the memory chunk containing the unflattened - * device tree on success. - */ - void *__unflatten_device_tree(const void *blob, -@@ -441,7 +441,7 @@ static DEFINE_MUTEX(of_fdt_unflatten_mut - * pointers of the nodes so the normal device-tree walking functions - * can be used. - * -- * Returns NULL on failure or the memory chunk containing the unflattened -+ * Return: NULL on failure or the memory chunk containing the unflattened - * device tree on success. - */ - void *of_fdt_unflatten_tree(const unsigned long *blob, -@@ -715,7 +715,7 @@ const void *__init of_get_flat_dt_prop(u - * @node: node to test - * @compat: compatible string to compare with compatible list. - * -- * On match, returns a non-zero value with smaller values returned for more -+ * Return: a non-zero value on match with smaller values returned for more - * specific compatible values. - */ - static int of_fdt_is_compatible(const void *blob, ---- a/drivers/of/irq.c -+++ b/drivers/of/irq.c -@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(irq_of_parse_and_map); - * of_irq_find_parent - Given a device node, find its interrupt parent node - * @child: pointer to device node - * -- * Returns a pointer to the interrupt parent node, or NULL if the interrupt -+ * Return: A pointer to the interrupt parent node, or NULL if the interrupt - * parent could not be determined. - */ - struct device_node *of_irq_find_parent(struct device_node *child) -@@ -81,14 +81,14 @@ EXPORT_SYMBOL_GPL(of_irq_find_parent); - * @addr: address specifier (start of "reg" property of the device) in be32 format - * @out_irq: structure of_phandle_args updated by this function - * -- * Returns 0 on success and a negative number on error -- * - * This function is a low-level interrupt tree walking function. It - * can be used to do a partial walk with synthetized reg and interrupts - * properties, for example when resolving PCI interrupts when no device - * node exist for the parent. It takes an interrupt specifier structure as - * input, walks the tree looking for any interrupt-map properties, translates - * the specifier for each map, and then returns the translated map. -+ * -+ * Return: 0 on success and a negative number on error - */ - int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq) - { -@@ -380,7 +380,7 @@ EXPORT_SYMBOL_GPL(of_irq_to_resource); - * @dev: pointer to device tree node - * @index: zero-based index of the IRQ - * -- * Returns Linux IRQ number on success, or 0 on the IRQ mapping failure, or -+ * Return: Linux IRQ number on success, or 0 on the IRQ mapping failure, or - * -EPROBE_DEFER if the IRQ domain is not yet created, or error code in case - * of any other failure. - */ -@@ -407,7 +407,7 @@ EXPORT_SYMBOL_GPL(of_irq_get); - * @dev: pointer to device tree node - * @name: IRQ name - * -- * Returns Linux IRQ number on success, or 0 on the IRQ mapping failure, or -+ * Return: Linux IRQ number on success, or 0 on the IRQ mapping failure, or - * -EPROBE_DEFER if the IRQ domain is not yet created, or error code in case - * of any other failure. - */ -@@ -447,7 +447,7 @@ int of_irq_count(struct device_node *dev - * @res: array of resources to fill in - * @nr_irqs: the number of IRQs (and upper bound for num of @res elements) - * -- * Returns the size of the filled in table (up to @nr_irqs). -+ * Return: The size of the filled in table (up to @nr_irqs). - */ - int of_irq_to_resource_table(struct device_node *dev, struct resource *res, - int nr_irqs) -@@ -602,7 +602,7 @@ static u32 __of_msi_map_id(struct device - * Walk up the device hierarchy looking for devices with a "msi-map" - * property. If found, apply the mapping to @id_in. - * -- * Returns the mapped MSI ID. -+ * Return: The mapped MSI ID. - */ - u32 of_msi_map_id(struct device *dev, struct device_node *msi_np, u32 id_in) - { ---- a/drivers/of/overlay.c -+++ b/drivers/of/overlay.c -@@ -296,7 +296,7 @@ err_free_target_path: - * - * Update of property in symbols node is not allowed. - * -- * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if -+ * Return: 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if - * invalid @overlay. - */ - static int add_changeset_property(struct overlay_changeset *ovcs, -@@ -401,7 +401,7 @@ static int add_changeset_property(struct - * - * NOTE_2: Multiple mods of created nodes not supported. - * -- * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if -+ * Return: 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if - * invalid @overlay. - */ - static int add_changeset_node(struct overlay_changeset *ovcs, -@@ -473,7 +473,7 @@ static int add_changeset_node(struct ove - * - * Do not allow symbols node to have any children. - * -- * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if -+ * Return: 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if - * invalid @overlay_node. - */ - static int build_changeset_next_level(struct overlay_changeset *ovcs, -@@ -604,7 +604,7 @@ static int find_dup_cset_prop(struct ove - * the same node or duplicate {add, delete, or update} properties entries - * for the same property. - * -- * Returns 0 on success, or -EINVAL if duplicate changeset entry found. -+ * Return: 0 on success, or -EINVAL if duplicate changeset entry found. - */ - static int changeset_dup_entry_check(struct overlay_changeset *ovcs) - { -@@ -628,7 +628,7 @@ static int changeset_dup_entry_check(str - * any portions of the changeset that were successfully created will remain - * in @ovcs->cset. - * -- * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if -+ * Return: 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if - * invalid overlay in @ovcs->fragments[]. - */ - static int build_changeset(struct overlay_changeset *ovcs) -@@ -724,7 +724,7 @@ static struct device_node *find_target(s - * the top level of @tree. The relevant top level nodes are the fragment - * nodes and the __symbols__ node. Any other top level node will be ignored. - * -- * Returns 0 on success, -ENOMEM if memory allocation failure, -EINVAL if error -+ * Return: 0 on success, -ENOMEM if memory allocation failure, -EINVAL if error - * detected in @tree, or -ENOSPC if idr_alloc() error. - */ - static int init_overlay_changeset(struct overlay_changeset *ovcs, -@@ -1179,7 +1179,7 @@ static int overlay_removal_is_ok(struct - * If an error is returned by an overlay changeset post-remove notifier - * then no further overlay changeset post-remove notifier will be called. - * -- * Returns 0 on success, or a negative error number. *ovcs_id is set to -+ * Return: 0 on success, or a negative error number. *ovcs_id is set to - * zero after reverting the changeset, even if a subsequent error occurs. - */ - int of_overlay_remove(int *ovcs_id) -@@ -1257,7 +1257,7 @@ EXPORT_SYMBOL_GPL(of_overlay_remove); - * - * Removes all overlays from the system in the correct order. - * -- * Returns 0 on success, or a negative error number -+ * Return: 0 on success, or a negative error number - */ - int of_overlay_remove_all(void) - { ---- a/drivers/of/platform.c -+++ b/drivers/of/platform.c -@@ -44,7 +44,7 @@ static const struct of_device_id of_skip - * Takes a reference to the embedded struct device which needs to be dropped - * after use. - * -- * Returns platform_device pointer, or NULL if not found -+ * Return: platform_device pointer, or NULL if not found - */ - struct platform_device *of_find_device_by_node(struct device_node *np) - { -@@ -160,7 +160,7 @@ EXPORT_SYMBOL(of_device_alloc); - * @platform_data: pointer to populate platform_data pointer with - * @parent: Linux device model parent device. - * -- * Returns pointer to created platform device, or NULL if a device was not -+ * Return: Pointer to created platform device, or NULL if a device was not - * registered. Unavailable devices will not get registered. - */ - static struct platform_device *of_platform_device_create_pdata( -@@ -204,7 +204,7 @@ err_clear_flag: - * @bus_id: name to assign device - * @parent: Linux device model parent device. - * -- * Returns pointer to created platform device, or NULL if a device was not -+ * Return: Pointer to created platform device, or NULL if a device was not - * registered. Unavailable devices will not get registered. - */ - struct platform_device *of_platform_device_create(struct device_node *np, -@@ -463,7 +463,7 @@ EXPORT_SYMBOL(of_platform_bus_probe); - * New board support should be using this function instead of - * of_platform_bus_probe(). - * -- * Returns 0 on success, < 0 on failure. -+ * Return: 0 on success, < 0 on failure. - */ - int of_platform_populate(struct device_node *root, - const struct of_device_id *matches, -@@ -608,7 +608,7 @@ static void devm_of_platform_populate_re - * Similar to of_platform_populate(), but will automatically call - * of_platform_depopulate() when the device is unbound from the bus. - * -- * Returns 0 on success, < 0 on failure. -+ * Return: 0 on success, < 0 on failure. - */ - int devm_of_platform_populate(struct device *dev) - { ---- a/drivers/of/property.c -+++ b/drivers/of/property.c -@@ -60,9 +60,11 @@ EXPORT_SYMBOL(of_graph_is_present); - * @elem_size: size of the individual element - * - * Search for a property in a device node and count the number of elements of -- * size elem_size in it. Returns number of elements on sucess, -EINVAL if the -- * property does not exist or its length does not match a multiple of elem_size -- * and -ENODATA if the property does not have a value. -+ * size elem_size in it. -+ * -+ * Return: The number of elements on sucess, -EINVAL if the property does not -+ * exist or its length does not match a multiple of elem_size and -ENODATA if -+ * the property does not have a value. - */ - int of_property_count_elems_of_size(const struct device_node *np, - const char *propname, int elem_size) -@@ -94,8 +96,9 @@ EXPORT_SYMBOL_GPL(of_property_count_elem - * @len: if !=NULL, actual length is written to here - * - * Search for a property in a device node and valid the requested size. -- * Returns the property value on success, -EINVAL if the property does not -- * exist, -ENODATA if property does not have a value, and -EOVERFLOW if the -+ * -+ * Return: The property value on success, -EINVAL if the property does not -+ * exist, -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data is too small or too large. - * - */ -@@ -128,7 +131,9 @@ static void *of_find_property_value_of_s - * @out_value: pointer to return value, modified only if no error. - * - * Search for a property in a device node and read nth 32-bit value from -- * it. Returns 0 on success, -EINVAL if the property does not exist, -+ * it. -+ * -+ * Return: 0 on success, -EINVAL if the property does not exist, - * -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data isn't large enough. - * -@@ -160,7 +165,9 @@ EXPORT_SYMBOL_GPL(of_property_read_u32_i - * @out_value: pointer to return value, modified only if no error. - * - * Search for a property in a device node and read nth 64-bit value from -- * it. Returns 0 on success, -EINVAL if the property does not exist, -+ * it. -+ * -+ * Return: 0 on success, -EINVAL if the property does not exist, - * -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data isn't large enough. - * -@@ -195,12 +202,14 @@ EXPORT_SYMBOL_GPL(of_property_read_u64_i - * sz_min will be read. - * - * Search for a property in a device node and read 8-bit value(s) from -- * it. Returns number of elements read on success, -EINVAL if the property -- * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW -- * if the property data is smaller than sz_min or longer than sz_max. -+ * it. - * - * dts entry of array should be like: -- * property = /bits/ 8 <0x50 0x60 0x70>; -+ * ``property = /bits/ 8 <0x50 0x60 0x70>;`` -+ * -+ * Return: The number of elements read on success, -EINVAL if the property -+ * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW -+ * if the property data is smaller than sz_min or longer than sz_max. - * - * The out_values is modified only if a valid u8 value can be decoded. - */ -@@ -243,12 +252,14 @@ EXPORT_SYMBOL_GPL(of_property_read_varia - * sz_min will be read. - * - * Search for a property in a device node and read 16-bit value(s) from -- * it. Returns number of elements read on success, -EINVAL if the property -- * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW -- * if the property data is smaller than sz_min or longer than sz_max. -+ * it. - * - * dts entry of array should be like: -- * property = /bits/ 16 <0x5000 0x6000 0x7000>; -+ * ``property = /bits/ 16 <0x5000 0x6000 0x7000>;`` -+ * -+ * Return: The number of elements read on success, -EINVAL if the property -+ * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW -+ * if the property data is smaller than sz_min or longer than sz_max. - * - * The out_values is modified only if a valid u16 value can be decoded. - */ -@@ -291,7 +302,9 @@ EXPORT_SYMBOL_GPL(of_property_read_varia - * sz_min will be read. - * - * Search for a property in a device node and read 32-bit value(s) from -- * it. Returns number of elements read on success, -EINVAL if the property -+ * it. -+ * -+ * Return: The number of elements read on success, -EINVAL if the property - * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW - * if the property data is smaller than sz_min or longer than sz_max. - * -@@ -330,7 +343,9 @@ EXPORT_SYMBOL_GPL(of_property_read_varia - * @out_value: pointer to return value, modified only if return value is 0. - * - * Search for a property in a device node and read a 64-bit value from -- * it. Returns 0 on success, -EINVAL if the property does not exist, -+ * it. -+ * -+ * Return: 0 on success, -EINVAL if the property does not exist, - * -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data isn't large enough. - * -@@ -365,7 +380,9 @@ EXPORT_SYMBOL_GPL(of_property_read_u64); - * sz_min will be read. - * - * Search for a property in a device node and read 64-bit value(s) from -- * it. Returns number of elements read on success, -EINVAL if the property -+ * it. -+ * -+ * Return: The number of elements read on success, -EINVAL if the property - * does not exist, -ENODATA if property does not have a value, and -EOVERFLOW - * if the property data is smaller than sz_min or longer than sz_max. - * -@@ -407,10 +424,11 @@ EXPORT_SYMBOL_GPL(of_property_read_varia - * return value is 0. - * - * Search for a property in a device tree node and retrieve a null -- * terminated string value (pointer to data, not a copy). Returns 0 on -- * success, -EINVAL if the property does not exist, -ENODATA if property -- * does not have a value, and -EILSEQ if the string is not null-terminated -- * within the length of the property data. -+ * terminated string value (pointer to data, not a copy). -+ * -+ * Return: 0 on success, -EINVAL if the property does not exist, -ENODATA if -+ * property does not have a value, and -EILSEQ if the string is not -+ * null-terminated within the length of the property data. - * - * The out_string pointer is modified only if a valid string can be decoded. - */ -@@ -774,7 +792,7 @@ EXPORT_SYMBOL(of_graph_get_remote_port_p - * @node: pointer to a local endpoint device_node - * - * Return: Remote port node associated with remote endpoint node linked -- * to @node. Use of_node_put() on it when done. -+ * to @node. Use of_node_put() on it when done. - */ - struct device_node *of_graph_get_remote_port(const struct device_node *node) - { -@@ -807,7 +825,7 @@ EXPORT_SYMBOL(of_graph_get_endpoint_coun - * @endpoint: identifier (value of reg property) of the endpoint node - * - * Return: Remote device node associated with remote endpoint node linked -- * to @node. Use of_node_put() on it when done. -+ * to @node. Use of_node_put() on it when done. - */ - struct device_node *of_graph_get_remote_node(const struct device_node *node, - u32 port, u32 endpoint) ---- a/include/linux/of.h -+++ b/include/linux/of.h -@@ -424,12 +424,14 @@ extern int of_detach_node(struct device_ - * @sz: number of array elements to read - * - * Search for a property in a device node and read 8-bit value(s) from -- * it. Returns 0 on success, -EINVAL if the property does not exist, -- * -ENODATA if property does not have a value, and -EOVERFLOW if the -- * property data isn't large enough. -+ * it. - * - * dts entry of array should be like: -- * property = /bits/ 8 <0x50 0x60 0x70>; -+ * ``property = /bits/ 8 <0x50 0x60 0x70>;`` -+ * -+ * Return: 0 on success, -EINVAL if the property does not exist, -+ * -ENODATA if property does not have a value, and -EOVERFLOW if the -+ * property data isn't large enough. - * - * The out_values is modified only if a valid u8 value can be decoded. - */ -@@ -454,12 +456,14 @@ static inline int of_property_read_u8_ar - * @sz: number of array elements to read - * - * Search for a property in a device node and read 16-bit value(s) from -- * it. Returns 0 on success, -EINVAL if the property does not exist, -- * -ENODATA if property does not have a value, and -EOVERFLOW if the -- * property data isn't large enough. -+ * it. - * - * dts entry of array should be like: -- * property = /bits/ 16 <0x5000 0x6000 0x7000>; -+ * ``property = /bits/ 16 <0x5000 0x6000 0x7000>;`` -+ * -+ * Return: 0 on success, -EINVAL if the property does not exist, -+ * -ENODATA if property does not have a value, and -EOVERFLOW if the -+ * property data isn't large enough. - * - * The out_values is modified only if a valid u16 value can be decoded. - */ -@@ -485,7 +489,9 @@ static inline int of_property_read_u16_a - * @sz: number of array elements to read - * - * Search for a property in a device node and read 32-bit value(s) from -- * it. Returns 0 on success, -EINVAL if the property does not exist, -+ * it. -+ * -+ * Return: 0 on success, -EINVAL if the property does not exist, - * -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data isn't large enough. - * -@@ -513,7 +519,9 @@ static inline int of_property_read_u32_a - * @sz: number of array elements to read - * - * Search for a property in a device node and read 64-bit value(s) from -- * it. Returns 0 on success, -EINVAL if the property does not exist, -+ * it. -+ * -+ * Return: 0 on success, -EINVAL if the property does not exist, - * -ENODATA if property does not have a value, and -EOVERFLOW if the - * property data isn't large enough. - * -@@ -1063,7 +1071,9 @@ static inline bool of_node_is_type(const - * @propname: name of the property to be searched. - * - * Search for a property in a device node and count the number of u8 elements -- * in it. Returns number of elements on sucess, -EINVAL if the property does -+ * in it. -+ * -+ * Return: The number of elements on sucess, -EINVAL if the property does - * not exist or its length does not match a multiple of u8 and -ENODATA if the - * property does not have a value. - */ -@@ -1080,7 +1090,9 @@ static inline int of_property_count_u8_e - * @propname: name of the property to be searched. - * - * Search for a property in a device node and count the number of u16 elements -- * in it. Returns number of elements on sucess, -EINVAL if the property does -+ * in it. -+ * -+ * Return: The number of elements on sucess, -EINVAL if the property does - * not exist or its length does not match a multiple of u16 and -ENODATA if the - * property does not have a value. - */ -@@ -1097,7 +1109,9 @@ static inline int of_property_count_u16_ - * @propname: name of the property to be searched. - * - * Search for a property in a device node and count the number of u32 elements -- * in it. Returns number of elements on sucess, -EINVAL if the property does -+ * in it. -+ * -+ * Return: The number of elements on sucess, -EINVAL if the property does - * not exist or its length does not match a multiple of u32 and -ENODATA if the - * property does not have a value. - */ -@@ -1114,7 +1128,9 @@ static inline int of_property_count_u32_ - * @propname: name of the property to be searched. - * - * Search for a property in a device node and count the number of u64 elements -- * in it. Returns number of elements on sucess, -EINVAL if the property does -+ * in it. -+ * -+ * Return: The number of elements on sucess, -EINVAL if the property does - * not exist or its length does not match a multiple of u64 and -ENODATA if the - * property does not have a value. - */ -@@ -1135,7 +1151,7 @@ static inline int of_property_count_u64_ - * Search for a property in a device tree node and retrieve a list of - * terminated string values (pointer to data, not a copy) in that property. - * -- * If @out_strs is NULL, the number of strings in the property is returned. -+ * Return: If @out_strs is NULL, the number of strings in the property is returned. - */ - static inline int of_property_read_string_array(const struct device_node *np, - const char *propname, const char **out_strs, -@@ -1151,10 +1167,11 @@ static inline int of_property_read_strin - * @propname: name of the property to be searched. - * - * Search for a property in a device tree node and retrieve the number of null -- * terminated string contain in it. Returns the number of strings on -- * success, -EINVAL if the property does not exist, -ENODATA if property -- * does not have a value, and -EILSEQ if the string is not null-terminated -- * within the length of the property data. -+ * terminated string contain in it. -+ * -+ * Return: The number of strings on success, -EINVAL if the property does not -+ * exist, -ENODATA if property does not have a value, and -EILSEQ if the string -+ * is not null-terminated within the length of the property data. - */ - static inline int of_property_count_strings(const struct device_node *np, - const char *propname) -@@ -1174,7 +1191,8 @@ static inline int of_property_count_stri - * Search for a property in a device tree node and retrieve a null - * terminated string value (pointer to data, not a copy) in the list of strings - * contained in that property. -- * Returns 0 on success, -EINVAL if the property does not exist, -ENODATA if -+ * -+ * Return: 0 on success, -EINVAL if the property does not exist, -ENODATA if - * property does not have a value, and -EILSEQ if the string is not - * null-terminated within the length of the property data. - * -@@ -1194,7 +1212,8 @@ static inline int of_property_read_strin - * @propname: name of the property to be searched. - * - * Search for a property in a device node. -- * Returns true if the property exists false otherwise. -+ * -+ * Return: true if the property exists false otherwise. - */ - static inline bool of_property_read_bool(const struct device_node *np, - const char *propname) -@@ -1440,7 +1459,7 @@ static inline int of_reconfig_get_state_ - * of_device_is_system_power_controller - Tells if system-power-controller is found for device_node - * @np: Pointer to the given device_node - * -- * return true if present false otherwise -+ * Return: true if present false otherwise - */ - static inline bool of_device_is_system_power_controller(const struct device_node *np) - { diff --git a/target/linux/generic/backport-5.10/732-v5.13-0007-of-base-Fix-spelling-issue-with-function-param-prop.patch b/target/linux/generic/backport-5.10/732-v5.13-0007-of-base-Fix-spelling-issue-with-function-param-prop.patch deleted file mode 100644 index 64197d7482..0000000000 --- a/target/linux/generic/backport-5.10/732-v5.13-0007-of-base-Fix-spelling-issue-with-function-param-prop.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 31e46db02ac1351c84e56a18606d17fc1b8390dd Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Mon, 29 Mar 2021 16:24:35 +0100 -Subject: [PATCH] of: base: Fix spelling issue with function param 'prop' - -Fixes the following W=1 kernel build warning(s): - - drivers/of/base.c:1781: warning: Function parameter or member 'prop' not described in '__of_add_property' - drivers/of/base.c:1781: warning: Excess function parameter 'prob' description in '__of_add_property' - drivers/of/base.c:1804: warning: Function parameter or member 'prop' not described in 'of_add_property' - drivers/of/base.c:1804: warning: Excess function parameter 'prob' description in 'of_add_property' - drivers/of/base.c:1855: warning: Function parameter or member 'prop' not described in 'of_remove_property' - drivers/of/base.c:1855: warning: Excess function parameter 'prob' description in 'of_remove_property' - -Cc: Rob Herring -Cc: Frank Rowand -Cc: "David S. Miller" -Cc: devicetree@vger.kernel.org -Signed-off-by: Lee Jones -Link: https://lore.kernel.org/r/20210329152435.900225-1-lee.jones@linaro.org -Signed-off-by: Rob Herring ---- - drivers/of/base.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/of/base.c -+++ b/drivers/of/base.c -@@ -1780,7 +1780,7 @@ EXPORT_SYMBOL(of_count_phandle_with_args - /** - * __of_add_property - Add a property to a node without lock operations - * @np: Caller's Device Node -- * @prob: Property to add -+ * @prop: Property to add - */ - int __of_add_property(struct device_node *np, struct property *prop) - { -@@ -1803,7 +1803,7 @@ int __of_add_property(struct device_node - /** - * of_add_property - Add a property to a node - * @np: Caller's Device Node -- * @prob: Property to add -+ * @prop: Property to add - */ - int of_add_property(struct device_node *np, struct property *prop) - { -@@ -1849,7 +1849,7 @@ int __of_remove_property(struct device_n - /** - * of_remove_property - Remove a property from a node. - * @np: Caller's Device Node -- * @prob: Property to remove -+ * @prop: Property to remove - * - * Note that we don't actually remove it, since we have given out - * who-knows-how-many pointers to the data using get-property. diff --git a/target/linux/generic/backport-5.10/732-v5.13-0008-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch b/target/linux/generic/backport-5.10/732-v5.13-0008-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch deleted file mode 100644 index 583abc9c80..0000000000 --- a/target/linux/generic/backport-5.10/732-v5.13-0008-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch +++ /dev/null @@ -1,1935 +0,0 @@ -From 83216e3988cd196183542937c9bd58b279f946af Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 12 Apr 2021 19:47:17 +0200 -Subject: [PATCH] of: net: pass the dst buffer to of_get_mac_address() - -of_get_mac_address() returns a "const void*" pointer to a MAC address. -Lately, support to fetch the MAC address by an NVMEM provider was added. -But this will only work with platform devices. It will not work with -PCI devices (e.g. of an integrated root complex) and esp. not with DSA -ports. - -There is an of_* variant of the nvmem binding which works without -devices. The returned data of a nvmem_cell_read() has to be freed after -use. On the other hand the return of_get_mac_address() points to some -static data without a lifetime. The trick for now, was to allocate a -device resource managed buffer which is then returned. This will only -work if we have an actual device. - -Change it, so that the caller of of_get_mac_address() has to supply a -buffer where the MAC address is written to. Unfortunately, this will -touch all drivers which use the of_get_mac_address(). - -Usually the code looks like: - - const char *addr; - addr = of_get_mac_address(np); - if (!IS_ERR(addr)) - ether_addr_copy(ndev->dev_addr, addr); - -This can then be simply rewritten as: - - of_get_mac_address(np, ndev->dev_addr); - -Sometimes is_valid_ether_addr() is used to test the MAC address. -of_get_mac_address() already makes sure, it just returns a valid MAC -address. Thus we can just test its return code. But we have to be -careful if there are still other sources for the MAC address before the -of_get_mac_address(). In this case we have to keep the -is_valid_ether_addr() call. - -The following coccinelle patch was used to convert common cases to the -new style. Afterwards, I've manually gone over the drivers and fixed the -return code variable: either used a new one or if one was already -available use that. Mansour Moufid, thanks for that coccinelle patch! - - -@a@ -identifier x; -expression y, z; -@@ -- x = of_get_mac_address(y); -+ x = of_get_mac_address(y, z); - <... -- ether_addr_copy(z, x); - ...> - -@@ -identifier a.x; -@@ -- if (<+... x ...+>) {} - -@@ -identifier a.x; -@@ - if (<+... x ...+>) { - ... - } -- else {} - -@@ -identifier a.x; -expression e; -@@ -- if (<+... x ...+>@e) -- {} -- else -+ if (!(e)) - {...} - -@@ -expression x, y, z; -@@ -- x = of_get_mac_address(y, z); -+ of_get_mac_address(y, z); - ... when != x - - -All drivers, except drivers/net/ethernet/aeroflex/greth.c, were -compile-time tested. - -Suggested-by: Andrew Lunn -Signed-off-by: Michael Walle -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - arch/arm/mach-mvebu/kirkwood.c | 3 +- - arch/powerpc/sysdev/tsi108_dev.c | 5 +- - drivers/net/ethernet/aeroflex/greth.c | 6 +-- - drivers/net/ethernet/allwinner/sun4i-emac.c | 10 ++-- - drivers/net/ethernet/altera/altera_tse_main.c | 7 +-- - drivers/net/ethernet/arc/emac_main.c | 8 +-- - drivers/net/ethernet/atheros/ag71xx.c | 7 +-- - drivers/net/ethernet/broadcom/bcm4908_enet.c | 7 +-- - drivers/net/ethernet/broadcom/bcmsysport.c | 7 +-- - drivers/net/ethernet/broadcom/bgmac-bcma.c | 10 ++-- - drivers/net/ethernet/broadcom/bgmac-platform.c | 11 ++-- - drivers/net/ethernet/cadence/macb_main.c | 11 ++-- - drivers/net/ethernet/cavium/octeon/octeon_mgmt.c | 8 +-- - drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 5 +- - drivers/net/ethernet/davicom/dm9000.c | 10 ++-- - drivers/net/ethernet/ethoc.c | 6 +-- - drivers/net/ethernet/ezchip/nps_enet.c | 7 +-- - drivers/net/ethernet/freescale/fec_main.c | 7 +-- - drivers/net/ethernet/freescale/fec_mpc52xx.c | 7 +-- - drivers/net/ethernet/freescale/fman/mac.c | 9 ++-- - .../net/ethernet/freescale/fs_enet/fs_enet-main.c | 5 +- - drivers/net/ethernet/freescale/gianfar.c | 8 +-- - drivers/net/ethernet/freescale/ucc_geth.c | 5 +- - drivers/net/ethernet/hisilicon/hisi_femac.c | 7 +-- - drivers/net/ethernet/hisilicon/hix5hd2_gmac.c | 7 +-- - drivers/net/ethernet/lantiq_xrx200.c | 7 +-- - drivers/net/ethernet/marvell/mv643xx_eth.c | 5 +- - drivers/net/ethernet/marvell/mvneta.c | 6 +-- - .../net/ethernet/marvell/prestera/prestera_main.c | 11 ++-- - drivers/net/ethernet/marvell/pxa168_eth.c | 9 +--- - drivers/net/ethernet/marvell/sky2.c | 8 ++- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 11 ++-- - drivers/net/ethernet/micrel/ks8851_common.c | 7 ++- - drivers/net/ethernet/microchip/lan743x_main.c | 5 +- - drivers/net/ethernet/nxp/lpc_eth.c | 4 +- - drivers/net/ethernet/qualcomm/qca_spi.c | 10 ++-- - drivers/net/ethernet/qualcomm/qca_uart.c | 9 +--- - drivers/net/ethernet/renesas/ravb_main.c | 12 +++-- - drivers/net/ethernet/renesas/sh_eth.c | 5 +- - .../net/ethernet/samsung/sxgbe/sxgbe_platform.c | 13 ++--- - drivers/net/ethernet/socionext/sni_ave.c | 10 ++-- - .../net/ethernet/stmicro/stmmac/dwmac-anarion.c | 2 +- - .../ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c | 2 +- - .../net/ethernet/stmicro/stmmac/dwmac-generic.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 2 +- - .../net/ethernet/stmicro/stmmac/dwmac-intel-plat.c | 2 +- - .../net/ethernet/stmicro/stmmac/dwmac-ipq806x.c | 2 +- - .../net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c | 2 +- - .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c | 2 +- - .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c | 2 +- - .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 2 +- - .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 2 +- - .../net/ethernet/stmicro/stmmac/dwmac-visconti.c | 2 +- - drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 +- - drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +- - .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 14 ++--- - .../net/ethernet/stmicro/stmmac/stmmac_platform.h | 2 +- - drivers/net/ethernet/ti/am65-cpsw-nuss.c | 19 ++++--- - drivers/net/ethernet/ti/cpsw.c | 7 +-- - drivers/net/ethernet/ti/cpsw_new.c | 7 +-- - drivers/net/ethernet/ti/davinci_emac.c | 8 +-- - drivers/net/ethernet/ti/netcp_core.c | 7 +-- - drivers/net/ethernet/wiznet/w5100-spi.c | 8 ++- - drivers/net/ethernet/wiznet/w5100.c | 2 +- - drivers/net/ethernet/xilinx/ll_temac_main.c | 8 +-- - drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 15 +++--- - drivers/net/ethernet/xilinx/xilinx_emaclite.c | 8 +-- - drivers/net/wireless/ath/ath9k/init.c | 5 +- - drivers/net/wireless/mediatek/mt76/eeprom.c | 9 +--- - drivers/net/wireless/ralink/rt2x00/rt2x00dev.c | 6 +-- - drivers/of/of_net.c | 60 ++++++++++------------ - drivers/staging/octeon/ethernet.c | 10 ++-- - drivers/staging/wfx/main.c | 7 ++- - include/linux/of_net.h | 6 +-- - include/net/dsa.h | 2 +- - net/dsa/dsa2.c | 2 +- - net/dsa/slave.c | 2 +- - net/ethernet/eth.c | 11 ++-- - 85 files changed, 218 insertions(+), 364 deletions(-) - ---- a/arch/arm/mach-mvebu/kirkwood.c -+++ b/arch/arm/mach-mvebu/kirkwood.c -@@ -84,6 +84,7 @@ static void __init kirkwood_dt_eth_fixup - struct device_node *pnp = of_get_parent(np); - struct clk *clk; - struct property *pmac; -+ u8 tmpmac[ETH_ALEN]; - void __iomem *io; - u8 *macaddr; - u32 reg; -@@ -93,7 +94,7 @@ static void __init kirkwood_dt_eth_fixup - - /* skip disabled nodes or nodes with valid MAC address*/ - if (!of_device_is_available(pnp) || -- !IS_ERR(of_get_mac_address(np))) -+ !of_get_mac_address(np, tmpmac)) - goto eth_fixup_skip; - - clk = of_clk_get(pnp, 0); ---- a/arch/powerpc/sysdev/tsi108_dev.c -+++ b/arch/powerpc/sysdev/tsi108_dev.c -@@ -73,7 +73,6 @@ static int __init tsi108_eth_of_init(voi - struct device_node *phy, *mdio; - hw_info tsi_eth_data; - const unsigned int *phy_id; -- const void *mac_addr; - const phandle *ph; - - memset(r, 0, sizeof(r)); -@@ -101,9 +100,7 @@ static int __init tsi108_eth_of_init(voi - goto err; - } - -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(tsi_eth_data.mac_addr, mac_addr); -+ of_get_mac_address(np, tsi_eth_data.mac_addr); - - ph = of_get_property(np, "mdio-handle", NULL); - mdio = of_find_node_by_phandle(*ph); ---- a/drivers/net/ethernet/aeroflex/greth.c -+++ b/drivers/net/ethernet/aeroflex/greth.c -@@ -1450,10 +1450,10 @@ static int greth_of_probe(struct platfor - break; - } - if (i == 6) { -- const u8 *addr; -+ u8 addr[ETH_ALEN]; - -- addr = of_get_mac_address(ofdev->dev.of_node); -- if (!IS_ERR(addr)) { -+ err = of_get_mac_address(ofdev->dev.of_node, addr); -+ if (!err) { - for (i = 0; i < 6; i++) - macaddr[i] = (unsigned int) addr[i]; - } else { ---- a/drivers/net/ethernet/allwinner/sun4i-emac.c -+++ b/drivers/net/ethernet/allwinner/sun4i-emac.c -@@ -790,7 +790,6 @@ static int emac_probe(struct platform_de - struct emac_board_info *db; - struct net_device *ndev; - int ret = 0; -- const char *mac_addr; - - ndev = alloc_etherdev(sizeof(struct emac_board_info)); - if (!ndev) { -@@ -853,12 +852,9 @@ static int emac_probe(struct platform_de - } - - /* Read MAC-address from DT */ -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(ndev->dev_addr, mac_addr); -- -- /* Check if the MAC address is valid, if not get a random one */ -- if (!is_valid_ether_addr(ndev->dev_addr)) { -+ ret = of_get_mac_address(np, ndev->dev_addr); -+ if (ret) { -+ /* if the MAC address is invalid get a random one */ - eth_hw_addr_random(ndev); - dev_warn(&pdev->dev, "using random MAC address %pM\n", - ndev->dev_addr); ---- a/drivers/net/ethernet/altera/altera_tse_main.c -+++ b/drivers/net/ethernet/altera/altera_tse_main.c -@@ -1355,7 +1355,6 @@ static int altera_tse_probe(struct platf - struct resource *control_port; - struct resource *dma_res; - struct altera_tse_private *priv; -- const unsigned char *macaddr; - void __iomem *descmap; - const struct of_device_id *of_id = NULL; - -@@ -1532,10 +1531,8 @@ static int altera_tse_probe(struct platf - priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE; - - /* get default MAC address from device tree */ -- macaddr = of_get_mac_address(pdev->dev.of_node); -- if (!IS_ERR(macaddr)) -- ether_addr_copy(ndev->dev_addr, macaddr); -- else -+ ret = of_get_mac_address(pdev->dev.of_node, ndev->dev_addr); -+ if (ret) - eth_hw_addr_random(ndev); - - /* get phy addr and create mdio */ ---- a/drivers/net/ethernet/arc/emac_main.c -+++ b/drivers/net/ethernet/arc/emac_main.c -@@ -857,7 +857,6 @@ int arc_emac_probe(struct net_device *nd - struct device_node *phy_node; - struct phy_device *phydev = NULL; - struct arc_emac_priv *priv; -- const char *mac_addr; - unsigned int id, clock_frequency, irq; - int err; - -@@ -942,11 +941,8 @@ int arc_emac_probe(struct net_device *nd - } - - /* Get MAC address from device tree */ -- mac_addr = of_get_mac_address(dev->of_node); -- -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(ndev->dev_addr, mac_addr); -- else -+ err = of_get_mac_address(dev->of_node, ndev->dev_addr); -+ if (err) - eth_hw_addr_random(ndev); - - arc_emac_set_address_internal(ndev); ---- a/drivers/net/ethernet/atheros/ag71xx.c -+++ b/drivers/net/ethernet/atheros/ag71xx.c -@@ -1857,7 +1857,6 @@ static int ag71xx_probe(struct platform_ - const struct ag71xx_dcfg *dcfg; - struct net_device *ndev; - struct resource *res; -- const void *mac_addr; - int tx_size, err, i; - struct ag71xx *ag; - -@@ -1953,10 +1952,8 @@ static int ag71xx_probe(struct platform_ - ag->stop_desc->ctrl = 0; - ag->stop_desc->next = (u32)ag->stop_desc_dma; - -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) -- memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); -- if (IS_ERR(mac_addr) || !is_valid_ether_addr(ndev->dev_addr)) { -+ err = of_get_mac_address(np, ndev->dev_addr); -+ if (err) { - netif_err(ag, probe, ndev, "invalid MAC address, using random address\n"); - eth_random_addr(ndev->dev_addr); - } ---- a/drivers/net/ethernet/broadcom/bcmsysport.c -+++ b/drivers/net/ethernet/broadcom/bcmsysport.c -@@ -2468,7 +2468,6 @@ static int bcm_sysport_probe(struct plat - struct bcm_sysport_priv *priv; - struct device_node *dn; - struct net_device *dev; -- const void *macaddr; - u32 txq, rxq; - int ret; - -@@ -2563,12 +2562,10 @@ static int bcm_sysport_probe(struct plat - } - - /* Initialize netdevice members */ -- macaddr = of_get_mac_address(dn); -- if (IS_ERR(macaddr)) { -+ ret = of_get_mac_address(dn, dev->dev_addr); -+ if (ret) { - dev_warn(&pdev->dev, "using random Ethernet MAC\n"); - eth_hw_addr_random(dev); -- } else { -- ether_addr_copy(dev->dev_addr, macaddr); - } - - SET_NETDEV_DEV(dev, &pdev->dev); ---- a/drivers/net/ethernet/broadcom/bgmac-bcma.c -+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c -@@ -115,7 +115,7 @@ static int bgmac_probe(struct bcma_devic - struct ssb_sprom *sprom = &core->bus->sprom; - struct mii_bus *mii_bus; - struct bgmac *bgmac; -- const u8 *mac = NULL; -+ const u8 *mac; - int err; - - bgmac = bgmac_alloc(&core->dev); -@@ -128,11 +128,10 @@ static int bgmac_probe(struct bcma_devic - - bcma_set_drvdata(core, bgmac); - -- if (bgmac->dev->of_node) -- mac = of_get_mac_address(bgmac->dev->of_node); -+ err = of_get_mac_address(bgmac->dev->of_node, bgmac->net_dev->dev_addr); - - /* If no MAC address assigned via device tree, check SPROM */ -- if (IS_ERR_OR_NULL(mac)) { -+ if (err) { - switch (core->core_unit) { - case 0: - mac = sprom->et0mac; -@@ -149,10 +148,9 @@ static int bgmac_probe(struct bcma_devic - err = -ENOTSUPP; - goto err; - } -+ ether_addr_copy(bgmac->net_dev->dev_addr, mac); - } - -- ether_addr_copy(bgmac->net_dev->dev_addr, mac); -- - /* On BCM4706 we need common core to access PHY */ - if (core->id.id == BCMA_CORE_4706_MAC_GBIT && - !core->bus->drv_gmac_cmn.core) { ---- a/drivers/net/ethernet/broadcom/bgmac-platform.c -+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c -@@ -173,7 +173,7 @@ static int bgmac_probe(struct platform_d - struct device_node *np = pdev->dev.of_node; - struct bgmac *bgmac; - struct resource *regs; -- const u8 *mac_addr; -+ int ret; - - bgmac = bgmac_alloc(&pdev->dev); - if (!bgmac) -@@ -192,11 +192,10 @@ static int bgmac_probe(struct platform_d - bgmac->dev = &pdev->dev; - bgmac->dma_dev = &pdev->dev; - -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(bgmac->net_dev->dev_addr, mac_addr); -- else -- dev_warn(&pdev->dev, "MAC address not present in device tree\n"); -+ ret = of_get_mac_address(np, bgmac->net_dev->dev_addr); -+ if (ret) -+ dev_warn(&pdev->dev, -+ "MAC address not present in device tree\n"); - - bgmac->irq = platform_get_irq(pdev, 0); - if (bgmac->irq < 0) ---- a/drivers/net/ethernet/cadence/macb_main.c -+++ b/drivers/net/ethernet/cadence/macb_main.c -@@ -4484,7 +4484,6 @@ static int macb_probe(struct platform_de - struct net_device *dev; - struct resource *regs; - void __iomem *mem; -- const char *mac; - struct macb *bp; - int err, val; - -@@ -4597,15 +4596,11 @@ static int macb_probe(struct platform_de - if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR) - bp->rx_intr_mask |= MACB_BIT(RXUBR); - -- mac = of_get_mac_address(np); -- if (PTR_ERR(mac) == -EPROBE_DEFER) { -- err = -EPROBE_DEFER; -+ err = of_get_mac_address(np, bp->dev->dev_addr); -+ if (err == -EPROBE_DEFER) - goto err_out_free_netdev; -- } else if (!IS_ERR_OR_NULL(mac)) { -- ether_addr_copy(bp->dev->dev_addr, mac); -- } else { -+ else if (err) - macb_get_hwaddr(bp); -- } - - err = of_get_phy_mode(np, &interface); - if (err) ---- a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c -+++ b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c -@@ -1385,7 +1385,6 @@ static int octeon_mgmt_probe(struct plat - struct net_device *netdev; - struct octeon_mgmt *p; - const __be32 *data; -- const u8 *mac; - struct resource *res_mix; - struct resource *res_agl; - struct resource *res_agl_prt_ctl; -@@ -1502,11 +1501,8 @@ static int octeon_mgmt_probe(struct plat - netdev->min_mtu = 64 - OCTEON_MGMT_RX_HEADROOM; - netdev->max_mtu = 16383 - OCTEON_MGMT_RX_HEADROOM - VLAN_HLEN; - -- mac = of_get_mac_address(pdev->dev.of_node); -- -- if (!IS_ERR(mac)) -- ether_addr_copy(netdev->dev_addr, mac); -- else -+ result = of_get_mac_address(pdev->dev.of_node, netdev->dev_addr); -+ if (result) - eth_hw_addr_random(netdev); - - p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); ---- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c -+++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c -@@ -1476,7 +1476,6 @@ static int bgx_init_of_phy(struct bgx *b - device_for_each_child_node(&bgx->pdev->dev, fwn) { - struct phy_device *pd; - struct device_node *phy_np; -- const char *mac; - - /* Should always be an OF node. But if it is not, we - * cannot handle it, so exit the loop. -@@ -1485,9 +1484,7 @@ static int bgx_init_of_phy(struct bgx *b - if (!node) - break; - -- mac = of_get_mac_address(node); -- if (!IS_ERR(mac)) -- ether_addr_copy(bgx->lmac[lmac].mac, mac); -+ of_get_mac_address(node, bgx->lmac[lmac].mac); - - SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev); - bgx->lmac[lmac].lmacid = lmac; ---- a/drivers/net/ethernet/davicom/dm9000.c -+++ b/drivers/net/ethernet/davicom/dm9000.c -@@ -1388,7 +1388,7 @@ static struct dm9000_plat_data *dm9000_p - { - struct dm9000_plat_data *pdata; - struct device_node *np = dev->of_node; -- const void *mac_addr; -+ int ret; - - if (!IS_ENABLED(CONFIG_OF) || !np) - return ERR_PTR(-ENXIO); -@@ -1402,11 +1402,9 @@ static struct dm9000_plat_data *dm9000_p - if (of_find_property(np, "davicom,no-eeprom", NULL)) - pdata->flags |= DM9000_PLATF_NO_EEPROM; - -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(pdata->dev_addr, mac_addr); -- else if (PTR_ERR(mac_addr) == -EPROBE_DEFER) -- return ERR_CAST(mac_addr); -+ ret = of_get_mac_address(np, pdata->dev_addr); -+ if (ret == -EPROBE_DEFER) -+ return ERR_PTR(ret); - - return pdata; - } ---- a/drivers/net/ethernet/ethoc.c -+++ b/drivers/net/ethernet/ethoc.c -@@ -1151,11 +1151,7 @@ static int ethoc_probe(struct platform_d - ether_addr_copy(netdev->dev_addr, pdata->hwaddr); - priv->phy_id = pdata->phy_id; - } else { -- const void *mac; -- -- mac = of_get_mac_address(pdev->dev.of_node); -- if (!IS_ERR(mac)) -- ether_addr_copy(netdev->dev_addr, mac); -+ of_get_mac_address(pdev->dev.of_node, netdev->dev_addr); - priv->phy_id = -1; - } - ---- a/drivers/net/ethernet/ezchip/nps_enet.c -+++ b/drivers/net/ethernet/ezchip/nps_enet.c -@@ -575,7 +575,6 @@ static s32 nps_enet_probe(struct platfor - struct net_device *ndev; - struct nps_enet_priv *priv; - s32 err = 0; -- const char *mac_addr; - - if (!dev->of_node) - return -ENODEV; -@@ -602,10 +601,8 @@ static s32 nps_enet_probe(struct platfor - dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base); - - /* set kernel MAC address to dev */ -- mac_addr = of_get_mac_address(dev->of_node); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(ndev->dev_addr, mac_addr); -- else -+ err = of_get_mac_address(dev->of_node, ndev->dev_addr); -+ if (err) - eth_hw_addr_random(ndev); - - /* Get IRQ number */ ---- a/drivers/net/ethernet/freescale/fec_main.c -+++ b/drivers/net/ethernet/freescale/fec_main.c -@@ -1666,6 +1666,7 @@ static void fec_get_mac(struct net_devic - struct fec_enet_private *fep = netdev_priv(ndev); - struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev); - unsigned char *iap, tmpaddr[ETH_ALEN]; -+ int ret; - - /* - * try to get mac address in following order: -@@ -1681,9 +1682,9 @@ static void fec_get_mac(struct net_devic - if (!is_valid_ether_addr(iap)) { - struct device_node *np = fep->pdev->dev.of_node; - if (np) { -- const char *mac = of_get_mac_address(np); -- if (!IS_ERR(mac)) -- iap = (unsigned char *) mac; -+ ret = of_get_mac_address(np, tmpaddr); -+ if (!ret) -+ iap = tmpaddr; - } - } - ---- a/drivers/net/ethernet/freescale/fec_mpc52xx.c -+++ b/drivers/net/ethernet/freescale/fec_mpc52xx.c -@@ -813,7 +813,6 @@ static int mpc52xx_fec_probe(struct plat - const u32 *prop; - int prop_size; - struct device_node *np = op->dev.of_node; -- const char *mac_addr; - - phys_addr_t rx_fifo; - phys_addr_t tx_fifo; -@@ -891,10 +890,8 @@ static int mpc52xx_fec_probe(struct plat - * - * First try to read MAC address from DT - */ -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) { -- ether_addr_copy(ndev->dev_addr, mac_addr); -- } else { -+ rv = of_get_mac_address(np, ndev->dev_addr); -+ if (rv) { - struct mpc52xx_fec __iomem *fec = priv->fec; - - /* ---- a/drivers/net/ethernet/freescale/fman/mac.c -+++ b/drivers/net/ethernet/freescale/fman/mac.c -@@ -616,7 +616,6 @@ static int mac_probe(struct platform_dev - struct platform_device *of_dev; - struct resource res; - struct mac_priv_s *priv; -- const u8 *mac_addr; - u32 val; - u8 fman_id; - phy_interface_t phy_if; -@@ -734,11 +733,9 @@ static int mac_probe(struct platform_dev - priv->cell_index = (u8)val; - - /* Get the MAC address */ -- mac_addr = of_get_mac_address(mac_node); -- if (IS_ERR(mac_addr)) -+ err = of_get_mac_address(mac_node, mac_dev->addr); -+ if (err) - dev_warn(dev, "of_get_mac_address(%pOF) failed\n", mac_node); -- else -- ether_addr_copy(mac_dev->addr, mac_addr); - - /* Get the port handles */ - nph = of_count_phandle_with_args(mac_node, "fsl,fman-ports", NULL); -@@ -864,7 +861,7 @@ static int mac_probe(struct platform_dev - if (err < 0) - dev_err(dev, "fman_set_mac_active_pause() = %d\n", err); - -- if (!IS_ERR(mac_addr)) -+ if (!is_zero_ether_addr(mac_dev->addr)) - dev_info(dev, "FMan MAC address: %pM\n", mac_dev->addr); - - priv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev); ---- a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c -+++ b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c -@@ -918,7 +918,6 @@ static int fs_enet_probe(struct platform - const u32 *data; - struct clk *clk; - int err; -- const u8 *mac_addr; - const char *phy_connection_type; - int privsize, len, ret = -ENODEV; - -@@ -1006,9 +1005,7 @@ static int fs_enet_probe(struct platform - spin_lock_init(&fep->lock); - spin_lock_init(&fep->tx_lock); - -- mac_addr = of_get_mac_address(ofdev->dev.of_node); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(ndev->dev_addr, mac_addr); -+ of_get_mac_address(ofdev->dev.of_node, ndev->dev_addr); - - ret = fep->ops->allocate_bd(ndev); - if (ret) ---- a/drivers/net/ethernet/freescale/gianfar.c -+++ b/drivers/net/ethernet/freescale/gianfar.c -@@ -641,7 +641,6 @@ static phy_interface_t gfar_get_interfac - static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) - { - const char *model; -- const void *mac_addr; - int err = 0, i; - phy_interface_t interface; - struct net_device *dev = NULL; -@@ -783,11 +782,8 @@ static int gfar_of_init(struct platform_ - if (stash_len || stash_idx) - priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; - -- mac_addr = of_get_mac_address(np); -- -- if (!IS_ERR(mac_addr)) { -- ether_addr_copy(dev->dev_addr, mac_addr); -- } else { -+ err = of_get_mac_address(np, dev->dev_addr); -+ if (err) { - eth_hw_addr_random(dev); - dev_info(&ofdev->dev, "Using random MAC address: %pM\n", dev->dev_addr); - } ---- a/drivers/net/ethernet/freescale/ucc_geth.c -+++ b/drivers/net/ethernet/freescale/ucc_geth.c -@@ -3696,7 +3696,6 @@ static int ucc_geth_probe(struct platfor - int err, ucc_num, max_speed = 0; - const unsigned int *prop; - const char *sprop; -- const void *mac_addr; - phy_interface_t phy_interface; - static const int enet_to_speed[] = { - SPEED_10, SPEED_10, SPEED_10, -@@ -3906,9 +3905,7 @@ static int ucc_geth_probe(struct platfor - goto err_free_netdev; - } - -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(dev->dev_addr, mac_addr); -+ of_get_mac_address(np, dev->dev_addr); - - ugeth->ug_info = ug_info; - ugeth->dev = device; ---- a/drivers/net/ethernet/hisilicon/hisi_femac.c -+++ b/drivers/net/ethernet/hisilicon/hisi_femac.c -@@ -772,7 +772,6 @@ static int hisi_femac_drv_probe(struct p - struct net_device *ndev; - struct hisi_femac_priv *priv; - struct phy_device *phy; -- const char *mac_addr; - int ret; - - ndev = alloc_etherdev(sizeof(*priv)); -@@ -842,10 +841,8 @@ static int hisi_femac_drv_probe(struct p - (unsigned long)phy->phy_id, - phy_modes(phy->interface)); - -- mac_addr = of_get_mac_address(node); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(ndev->dev_addr, mac_addr); -- if (!is_valid_ether_addr(ndev->dev_addr)) { -+ ret = of_get_mac_address(node, ndev->dev_addr); -+ if (ret) { - eth_hw_addr_random(ndev); - dev_warn(dev, "using random MAC address %pM\n", - ndev->dev_addr); ---- a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c -+++ b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c -@@ -1098,7 +1098,6 @@ static int hix5hd2_dev_probe(struct plat - struct net_device *ndev; - struct hix5hd2_priv *priv; - struct mii_bus *bus; -- const char *mac_addr; - int ret; - - ndev = alloc_etherdev(sizeof(struct hix5hd2_priv)); -@@ -1220,10 +1219,8 @@ static int hix5hd2_dev_probe(struct plat - goto out_phy_node; - } - -- mac_addr = of_get_mac_address(node); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(ndev->dev_addr, mac_addr); -- if (!is_valid_ether_addr(ndev->dev_addr)) { -+ ret = of_get_mac_address(node, ndev->dev_addr); -+ if (ret) { - eth_hw_addr_random(ndev); - netdev_warn(ndev, "using random MAC address %pM\n", - ndev->dev_addr); ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -440,7 +440,6 @@ static int xrx200_probe(struct platform_ - struct resource *res; - struct xrx200_priv *priv; - struct net_device *net_dev; -- const u8 *mac; - int err; - - /* alloc the network device */ -@@ -484,10 +483,8 @@ static int xrx200_probe(struct platform_ - return PTR_ERR(priv->clk); - } - -- mac = of_get_mac_address(np); -- if (!IS_ERR(mac)) -- ether_addr_copy(net_dev->dev_addr, mac); -- else -+ err = of_get_mac_address(np, net_dev->dev_addr); -+ if (err) - eth_hw_addr_random(net_dev); - - /* bring up the dma engine and IP core */ ---- a/drivers/net/ethernet/marvell/mv643xx_eth.c -+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c -@@ -2701,7 +2701,6 @@ static int mv643xx_eth_shared_of_add_por - struct platform_device *ppdev; - struct mv643xx_eth_platform_data ppd; - struct resource res; -- const char *mac_addr; - int ret; - int dev_num = 0; - -@@ -2732,9 +2731,7 @@ static int mv643xx_eth_shared_of_add_por - return -EINVAL; - } - -- mac_addr = of_get_mac_address(pnp); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(ppd.mac_addr, mac_addr); -+ of_get_mac_address(pnp, ppd.mac_addr); - - mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size); - mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr); ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -5062,7 +5062,6 @@ static int mvneta_probe(struct platform_ - struct net_device *dev; - struct phylink *phylink; - struct phy *comphy; -- const char *dt_mac_addr; - char hw_mac_addr[ETH_ALEN]; - phy_interface_t phy_mode; - const char *mac_from; -@@ -5158,10 +5157,9 @@ static int mvneta_probe(struct platform_ - goto err_free_ports; - } - -- dt_mac_addr = of_get_mac_address(dn); -- if (!IS_ERR(dt_mac_addr)) { -+ err = of_get_mac_address(dn, dev->dev_addr); -+ if (!err) { - mac_from = "device tree"; -- ether_addr_copy(dev->dev_addr, dt_mac_addr); - } else { - mvneta_get_mac_addr(pp, hw_mac_addr); - if (is_valid_ether_addr(hw_mac_addr)) { ---- a/drivers/net/ethernet/marvell/prestera/prestera_main.c -+++ b/drivers/net/ethernet/marvell/prestera/prestera_main.c -@@ -466,20 +466,17 @@ static int prestera_switch_set_base_mac_ - { - struct device_node *base_mac_np; - struct device_node *np; -- const char *base_mac; -+ int ret; - - np = of_find_compatible_node(NULL, NULL, "marvell,prestera"); - base_mac_np = of_parse_phandle(np, "base-mac-provider", 0); - -- base_mac = of_get_mac_address(base_mac_np); -- of_node_put(base_mac_np); -- if (!IS_ERR(base_mac)) -- ether_addr_copy(sw->base_mac, base_mac); -- -- if (!is_valid_ether_addr(sw->base_mac)) { -+ ret = of_get_mac_address(base_mac_np, sw->base_mac); -+ if (ret) { - eth_random_addr(sw->base_mac); - dev_info(prestera_dev(sw), "using random base mac address\n"); - } -+ of_node_put(base_mac_np); - - return prestera_hw_switch_mac_set(sw, sw->base_mac); - } ---- a/drivers/net/ethernet/marvell/pxa168_eth.c -+++ b/drivers/net/ethernet/marvell/pxa168_eth.c -@@ -1392,7 +1392,6 @@ static int pxa168_eth_probe(struct platf - struct resource *res; - struct clk *clk; - struct device_node *np; -- const unsigned char *mac_addr = NULL; - int err; - - printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n"); -@@ -1435,12 +1434,8 @@ static int pxa168_eth_probe(struct platf - - INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task); - -- if (pdev->dev.of_node) -- mac_addr = of_get_mac_address(pdev->dev.of_node); -- -- if (!IS_ERR_OR_NULL(mac_addr)) { -- ether_addr_copy(dev->dev_addr, mac_addr); -- } else { -+ err = of_get_mac_address(pdev->dev.of_node, dev->dev_addr); -+ if (err) { - /* try reading the mac address, if set by the bootloader */ - pxa168_eth_get_mac_address(dev, dev->dev_addr); - if (!is_valid_ether_addr(dev->dev_addr)) { ---- a/drivers/net/ethernet/marvell/sky2.c -+++ b/drivers/net/ethernet/marvell/sky2.c -@@ -4725,7 +4725,7 @@ static struct net_device *sky2_init_netd - { - struct sky2_port *sky2; - struct net_device *dev = alloc_etherdev(sizeof(*sky2)); -- const void *iap; -+ int ret; - - if (!dev) - return NULL; -@@ -4795,10 +4795,8 @@ static struct net_device *sky2_init_netd - * 1) from device tree data - * 2) from internal registers set by bootloader - */ -- iap = of_get_mac_address(hw->pdev->dev.of_node); -- if (!IS_ERR(iap)) -- ether_addr_copy(dev->dev_addr, iap); -- else -+ ret = of_get_mac_address(hw->pdev->dev.of_node, dev->dev_addr); -+ if (ret) - memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, - ETH_ALEN); - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2605,14 +2605,11 @@ static int __init mtk_init(struct net_de - { - struct mtk_mac *mac = netdev_priv(dev); - struct mtk_eth *eth = mac->hw; -- const char *mac_addr; -+ int ret; - -- mac_addr = of_get_mac_address(mac->of_node); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(dev->dev_addr, mac_addr); -- -- /* If the mac address is invalid, use random mac address */ -- if (!is_valid_ether_addr(dev->dev_addr)) { -+ ret = of_get_mac_address(mac->of_node, dev->dev_addr); -+ if (ret) { -+ /* If the mac address is invalid, use random mac address */ - eth_hw_addr_random(dev); - dev_err(eth->dev, "generated random MAC address %pM\n", - dev->dev_addr); ---- a/drivers/net/ethernet/micrel/ks8851_common.c -+++ b/drivers/net/ethernet/micrel/ks8851_common.c -@@ -194,11 +194,10 @@ static void ks8851_read_mac_addr(struct - static void ks8851_init_mac(struct ks8851_net *ks, struct device_node *np) - { - struct net_device *dev = ks->netdev; -- const u8 *mac_addr; -+ int ret; - -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) { -- ether_addr_copy(dev->dev_addr, mac_addr); -+ ret = of_get_mac_address(np, dev->dev_addr); -+ if (!ret) { - ks8851_write_mac_addr(dev); - return; - } ---- a/drivers/net/ethernet/microchip/lan743x_main.c -+++ b/drivers/net/ethernet/microchip/lan743x_main.c -@@ -2831,7 +2831,6 @@ static int lan743x_pcidev_probe(struct p - { - struct lan743x_adapter *adapter = NULL; - struct net_device *netdev = NULL; -- const void *mac_addr; - int ret = -ENODEV; - - netdev = devm_alloc_etherdev(&pdev->dev, -@@ -2848,9 +2847,7 @@ static int lan743x_pcidev_probe(struct p - NETIF_MSG_IFDOWN | NETIF_MSG_TX_QUEUED; - netdev->max_mtu = LAN743X_MAX_FRAME_SIZE; - -- mac_addr = of_get_mac_address(pdev->dev.of_node); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(adapter->mac_address, mac_addr); -+ of_get_mac_address(pdev->dev.of_node, adapter->mac_address); - - ret = lan743x_pci_init(adapter, pdev); - if (ret) ---- a/drivers/net/ethernet/nxp/lpc_eth.c -+++ b/drivers/net/ethernet/nxp/lpc_eth.c -@@ -1347,9 +1347,7 @@ static int lpc_eth_drv_probe(struct plat - __lpc_get_mac(pldat, ndev->dev_addr); - - if (!is_valid_ether_addr(ndev->dev_addr)) { -- const char *macaddr = of_get_mac_address(np); -- if (!IS_ERR(macaddr)) -- ether_addr_copy(ndev->dev_addr, macaddr); -+ of_get_mac_address(np, ndev->dev_addr); - } - if (!is_valid_ether_addr(ndev->dev_addr)) - eth_hw_addr_random(ndev); ---- a/drivers/net/ethernet/qualcomm/qca_spi.c -+++ b/drivers/net/ethernet/qualcomm/qca_spi.c -@@ -885,7 +885,7 @@ qca_spi_probe(struct spi_device *spi) - struct net_device *qcaspi_devs = NULL; - u8 legacy_mode = 0; - u16 signature; -- const char *mac; -+ int ret; - - if (!spi->dev.of_node) { - dev_err(&spi->dev, "Missing device tree\n"); -@@ -962,12 +962,8 @@ qca_spi_probe(struct spi_device *spi) - - spi_set_drvdata(spi, qcaspi_devs); - -- mac = of_get_mac_address(spi->dev.of_node); -- -- if (!IS_ERR(mac)) -- ether_addr_copy(qca->net_dev->dev_addr, mac); -- -- if (!is_valid_ether_addr(qca->net_dev->dev_addr)) { -+ ret = of_get_mac_address(spi->dev.of_node, qca->net_dev->dev_addr); -+ if (ret) { - eth_hw_addr_random(qca->net_dev); - dev_info(&spi->dev, "Using random MAC address: %pM\n", - qca->net_dev->dev_addr); ---- a/drivers/net/ethernet/qualcomm/qca_uart.c -+++ b/drivers/net/ethernet/qualcomm/qca_uart.c -@@ -323,7 +323,6 @@ static int qca_uart_probe(struct serdev_ - { - struct net_device *qcauart_dev = alloc_etherdev(sizeof(struct qcauart)); - struct qcauart *qca; -- const char *mac; - u32 speed = 115200; - int ret; - -@@ -348,12 +347,8 @@ static int qca_uart_probe(struct serdev_ - - of_property_read_u32(serdev->dev.of_node, "current-speed", &speed); - -- mac = of_get_mac_address(serdev->dev.of_node); -- -- if (!IS_ERR(mac)) -- ether_addr_copy(qca->net_dev->dev_addr, mac); -- -- if (!is_valid_ether_addr(qca->net_dev->dev_addr)) { -+ ret = of_get_mac_address(serdev->dev.of_node, qca->net_dev->dev_addr); -+ if (ret) { - eth_hw_addr_random(qca->net_dev); - dev_info(&serdev->dev, "Using random MAC address: %pM\n", - qca->net_dev->dev_addr); ---- a/drivers/net/ethernet/renesas/ravb_main.c -+++ b/drivers/net/ethernet/renesas/ravb_main.c -@@ -109,11 +109,13 @@ static void ravb_set_buffer_align(struct - * Ethernet AVB device doesn't have ROM for MAC address. - * This function gets the MAC address that was used by a bootloader. - */ --static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) -+static void ravb_read_mac_address(struct device_node *np, -+ struct net_device *ndev) - { -- if (!IS_ERR(mac)) { -- ether_addr_copy(ndev->dev_addr, mac); -- } else { -+ int ret; -+ -+ ret = of_get_mac_address(np, ndev->dev_addr); -+ if (ret) { - u32 mahr = ravb_read(ndev, MAHR); - u32 malr = ravb_read(ndev, MALR); - -@@ -2189,7 +2191,7 @@ static int ravb_probe(struct platform_de - priv->msg_enable = RAVB_DEF_MSG_ENABLE; - - /* Read and set MAC address */ -- ravb_read_mac_address(ndev, of_get_mac_address(np)); -+ ravb_read_mac_address(np, ndev); - if (!is_valid_ether_addr(ndev->dev_addr)) { - dev_warn(&pdev->dev, - "no valid MAC address supplied, using a random one\n"); ---- a/drivers/net/ethernet/renesas/sh_eth.c -+++ b/drivers/net/ethernet/renesas/sh_eth.c -@@ -3145,7 +3145,6 @@ static struct sh_eth_plat_data *sh_eth_p - struct device_node *np = dev->of_node; - struct sh_eth_plat_data *pdata; - phy_interface_t interface; -- const char *mac_addr; - int ret; - - pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); -@@ -3157,9 +3156,7 @@ static struct sh_eth_plat_data *sh_eth_p - return NULL; - pdata->phy_interface = interface; - -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(pdata->mac_addr, mac_addr); -+ of_get_mac_address(np, pdata->mac_addr); - - pdata->no_ether_link = - of_property_read_bool(np, "renesas,no-ether-link"); ---- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c -+++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c -@@ -25,8 +25,7 @@ - - #ifdef CONFIG_OF - static int sxgbe_probe_config_dt(struct platform_device *pdev, -- struct sxgbe_plat_data *plat, -- const char **mac) -+ struct sxgbe_plat_data *plat) - { - struct device_node *np = pdev->dev.of_node; - struct sxgbe_dma_cfg *dma_cfg; -@@ -35,7 +34,6 @@ static int sxgbe_probe_config_dt(struct - if (!np) - return -ENODEV; - -- *mac = of_get_mac_address(np); - err = of_get_phy_mode(np, &plat->interface); - if (err && err != -ENODEV) - return err; -@@ -63,8 +61,7 @@ static int sxgbe_probe_config_dt(struct - } - #else - static int sxgbe_probe_config_dt(struct platform_device *pdev, -- struct sxgbe_plat_data *plat, -- const char **mac) -+ struct sxgbe_plat_data *plat) - { - return -ENOSYS; - } -@@ -85,7 +82,6 @@ static int sxgbe_platform_probe(struct p - void __iomem *addr; - struct sxgbe_priv_data *priv = NULL; - struct sxgbe_plat_data *plat_dat = NULL; -- const char *mac = NULL; - struct net_device *ndev = platform_get_drvdata(pdev); - struct device_node *node = dev->of_node; - -@@ -101,7 +97,7 @@ static int sxgbe_platform_probe(struct p - if (!plat_dat) - return -ENOMEM; - -- ret = sxgbe_probe_config_dt(pdev, plat_dat, &mac); -+ ret = sxgbe_probe_config_dt(pdev, plat_dat); - if (ret) { - pr_err("%s: main dt probe failed\n", __func__); - return ret; -@@ -122,8 +118,7 @@ static int sxgbe_platform_probe(struct p - } - - /* Get MAC address if available (DT) */ -- if (!IS_ERR_OR_NULL(mac)) -- ether_addr_copy(priv->dev->dev_addr, mac); -+ of_get_mac_address(node, priv->dev->dev_addr); - - /* Get the TX/RX IRQ numbers */ - for (i = 0, chan = 1; i < SXGBE_TX_QUEUES; i++) { ---- a/drivers/net/ethernet/socionext/sni_ave.c -+++ b/drivers/net/ethernet/socionext/sni_ave.c -@@ -1559,7 +1559,6 @@ static int ave_probe(struct platform_dev - struct ave_private *priv; - struct net_device *ndev; - struct device_node *np; -- const void *mac_addr; - void __iomem *base; - const char *name; - int i, irq, ret; -@@ -1600,12 +1599,9 @@ static int ave_probe(struct platform_dev - - ndev->max_mtu = AVE_MAX_ETHFRAME - (ETH_HLEN + ETH_FCS_LEN); - -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(ndev->dev_addr, mac_addr); -- -- /* if the mac address is invalid, use random mac address */ -- if (!is_valid_ether_addr(ndev->dev_addr)) { -+ ret = of_get_mac_address(np, ndev->dev_addr); -+ if (ret) { -+ /* if the mac address is invalid, use random mac address */ - eth_hw_addr_random(ndev); - dev_warn(dev, "Using random MAC address: %pM\n", - ndev->dev_addr); ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c -@@ -115,7 +115,7 @@ static int anarion_dwmac_probe(struct pl - if (IS_ERR(gmac)) - return PTR_ERR(gmac); - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c -@@ -445,7 +445,7 @@ static int dwc_eth_dwmac_probe(struct pl - if (IS_ERR(stmmac_res.addr)) - return PTR_ERR(stmmac_res.addr); - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c -@@ -27,7 +27,7 @@ static int dwmac_generic_probe(struct pl - return ret; - - if (pdev->dev.of_node) { -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) { - dev_err(&pdev->dev, "dt configuration failed\n"); - return PTR_ERR(plat_dat); ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c -@@ -226,7 +226,7 @@ static int imx_dwmac_probe(struct platfo - if (!dwmac) - return -ENOMEM; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel-plat.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel-plat.c -@@ -88,7 +88,7 @@ static int intel_eth_plat_probe(struct p - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) { - dev_err(&pdev->dev, "dt configuration failed\n"); - return PTR_ERR(plat_dat); ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -@@ -255,7 +255,7 @@ static int ipq806x_gmac_probe(struct pla - if (val) - return val; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c -@@ -37,7 +37,7 @@ static int lpc18xx_dwmac_probe(struct pl - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c -@@ -407,7 +407,7 @@ static int mediatek_dwmac_probe(struct p - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c -@@ -52,7 +52,7 @@ static int meson6_dwmac_probe(struct pla - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c -@@ -370,7 +370,7 @@ static int meson8b_dwmac_probe(struct pl - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c -@@ -118,7 +118,7 @@ static int oxnas_dwmac_probe(struct plat - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c -@@ -461,7 +461,7 @@ static int qcom_ethqos_probe(struct plat - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) { - dev_err(&pdev->dev, "dt configuration failed\n"); - return PTR_ERR(plat_dat); ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -@@ -1392,7 +1392,7 @@ static int rk_gmac_probe(struct platform - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c -@@ -397,7 +397,7 @@ static int socfpga_dwmac_probe(struct pl - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c -@@ -325,7 +325,7 @@ static int sti_dwmac_probe(struct platfo - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c -@@ -371,7 +371,7 @@ static int stm32_dwmac_probe(struct plat - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c -@@ -1203,7 +1203,7 @@ static int sun8i_dwmac_probe(struct plat - if (ret) - return -EINVAL; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c -@@ -108,7 +108,7 @@ static int sun7i_gmac_probe(struct platf - if (ret) - return ret; - -- plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h -@@ -25,7 +25,7 @@ - - struct stmmac_resources { - void __iomem *addr; -- const char *mac; -+ u8 mac[ETH_ALEN]; - int wol_irq; - int lpi_irq; - int irq; ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5019,7 +5019,7 @@ int stmmac_dvr_probe(struct device *devi - priv->wol_irq = res->wol_irq; - priv->lpi_irq = res->lpi_irq; - -- if (!IS_ERR_OR_NULL(res->mac)) -+ if (!is_zero_ether_addr(res->mac)) - memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); - - dev_set_drvdata(device, priv->dev); ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -@@ -395,7 +395,7 @@ static int stmmac_of_get_mac_mode(struct - * set some private fields that will be used by the main at runtime. - */ - struct plat_stmmacenet_data * --stmmac_probe_config_dt(struct platform_device *pdev, const char **mac) -+stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac) - { - struct device_node *np = pdev->dev.of_node; - struct plat_stmmacenet_data *plat; -@@ -407,12 +407,12 @@ stmmac_probe_config_dt(struct platform_d - if (!plat) - return ERR_PTR(-ENOMEM); - -- *mac = of_get_mac_address(np); -- if (IS_ERR(*mac)) { -- if (PTR_ERR(*mac) == -EPROBE_DEFER) -- return ERR_CAST(*mac); -+ rc = of_get_mac_address(np, mac); -+ if (rc) { -+ if (rc == -EPROBE_DEFER) -+ return ERR_PTR(rc); - -- *mac = NULL; -+ eth_zero_addr(mac); - } - - phy_mode = device_get_phy_mode(&pdev->dev); -@@ -643,7 +643,7 @@ void stmmac_remove_config_dt(struct plat - } - #else - struct plat_stmmacenet_data * --stmmac_probe_config_dt(struct platform_device *pdev, const char **mac) -+stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac) - { - return ERR_PTR(-EINVAL); - } ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h -@@ -12,7 +12,7 @@ - #include "stmmac.h" - - struct plat_stmmacenet_data * --stmmac_probe_config_dt(struct platform_device *pdev, const char **mac); -+stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac); - void stmmac_remove_config_dt(struct platform_device *pdev, - struct plat_stmmacenet_data *plat); - ---- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c -+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c -@@ -1713,7 +1713,6 @@ static int am65_cpsw_nuss_init_slave_por - - for_each_child_of_node(node, port_np) { - struct am65_cpsw_port *port; -- const void *mac_addr; - u32 port_id; - - /* it is not a slave port node, continue */ -@@ -1796,15 +1795,15 @@ static int am65_cpsw_nuss_init_slave_por - goto of_node_put; - } - -- mac_addr = of_get_mac_address(port_np); -- if (!IS_ERR(mac_addr)) { -- ether_addr_copy(port->slave.mac_addr, mac_addr); -- } else if (am65_cpsw_am654_get_efuse_macid(port_np, -- port->port_id, -- port->slave.mac_addr) || -- !is_valid_ether_addr(port->slave.mac_addr)) { -- random_ether_addr(port->slave.mac_addr); -- dev_err(dev, "Use random MAC address\n"); -+ ret = of_get_mac_address(port_np, port->slave.mac_addr); -+ if (ret) { -+ am65_cpsw_am654_get_efuse_macid(port_np, -+ port->port_id, -+ port->slave.mac_addr); -+ if (!is_valid_ether_addr(port->slave.mac_addr)) { -+ random_ether_addr(port->slave.mac_addr); -+ dev_err(dev, "Use random MAC address\n"); -+ } - } - } - of_node_put(node); ---- a/drivers/net/ethernet/ti/cpsw.c -+++ b/drivers/net/ethernet/ti/cpsw.c -@@ -1308,7 +1308,6 @@ static int cpsw_probe_dt(struct cpsw_pla - - for_each_available_child_of_node(node, slave_node) { - struct cpsw_slave_data *slave_data = data->slave_data + i; -- const void *mac_addr = NULL; - int lenp; - const __be32 *parp; - -@@ -1380,10 +1379,8 @@ static int cpsw_probe_dt(struct cpsw_pla - } - - no_phy_slave: -- mac_addr = of_get_mac_address(slave_node); -- if (!IS_ERR(mac_addr)) { -- ether_addr_copy(slave_data->mac_addr, mac_addr); -- } else { -+ ret = of_get_mac_address(slave_node, slave_data->mac_addr); -+ if (ret) { - ret = ti_cm_get_macid(&pdev->dev, i, - slave_data->mac_addr); - if (ret) ---- a/drivers/net/ethernet/ti/cpsw_new.c -+++ b/drivers/net/ethernet/ti/cpsw_new.c -@@ -1269,7 +1269,6 @@ static int cpsw_probe_dt(struct cpsw_com - - for_each_child_of_node(tmp_node, port_np) { - struct cpsw_slave_data *slave_data; -- const void *mac_addr; - u32 port_id; - - ret = of_property_read_u32(port_np, "reg", &port_id); -@@ -1328,10 +1327,8 @@ static int cpsw_probe_dt(struct cpsw_com - goto err_node_put; - } - -- mac_addr = of_get_mac_address(port_np); -- if (!IS_ERR(mac_addr)) { -- ether_addr_copy(slave_data->mac_addr, mac_addr); -- } else { -+ ret = of_get_mac_address(port_np, slave_data->mac_addr); -+ if (ret) { - ret = ti_cm_get_macid(dev, port_id - 1, - slave_data->mac_addr); - if (ret) ---- a/drivers/net/ethernet/ti/davinci_emac.c -+++ b/drivers/net/ethernet/ti/davinci_emac.c -@@ -1699,7 +1699,6 @@ davinci_emac_of_get_pdata(struct platfor - const struct of_device_id *match; - const struct emac_platform_data *auxdata; - struct emac_platform_data *pdata = NULL; -- const u8 *mac_addr; - - if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) - return dev_get_platdata(&pdev->dev); -@@ -1711,11 +1710,8 @@ davinci_emac_of_get_pdata(struct platfor - np = pdev->dev.of_node; - pdata->version = EMAC_VERSION_2; - -- if (!is_valid_ether_addr(pdata->mac_addr)) { -- mac_addr = of_get_mac_address(np); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(pdata->mac_addr, mac_addr); -- } -+ if (!is_valid_ether_addr(pdata->mac_addr)) -+ of_get_mac_address(np, pdata->mac_addr); - - of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", - &pdata->ctrl_reg_offset); ---- a/drivers/net/ethernet/ti/netcp_core.c -+++ b/drivers/net/ethernet/ti/netcp_core.c -@@ -1966,7 +1966,6 @@ static int netcp_create_interface(struct - struct resource res; - void __iomem *efuse = NULL; - u32 efuse_mac = 0; -- const void *mac_addr; - u8 efuse_mac_addr[6]; - u32 temp[2]; - int ret = 0; -@@ -2036,10 +2035,8 @@ static int netcp_create_interface(struct - devm_iounmap(dev, efuse); - devm_release_mem_region(dev, res.start, size); - } else { -- mac_addr = of_get_mac_address(node_interface); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(ndev->dev_addr, mac_addr); -- else -+ ret = of_get_mac_address(node_interface, ndev->dev_addr); -+ if (ret) - eth_random_addr(ndev->dev_addr); - } - ---- a/drivers/net/ethernet/wiznet/w5100-spi.c -+++ b/drivers/net/ethernet/wiznet/w5100-spi.c -@@ -423,8 +423,14 @@ static int w5100_spi_probe(struct spi_de - const struct of_device_id *of_id; - const struct w5100_ops *ops; - kernel_ulong_t driver_data; -+ const void *mac = NULL; -+ u8 tmpmac[ETH_ALEN]; - int priv_size; -- const void *mac = of_get_mac_address(spi->dev.of_node); -+ int ret; -+ -+ ret = of_get_mac_address(spi->dev.of_node, tmpmac); -+ if (!ret) -+ mac = tmpmac; - - if (spi->dev.of_node) { - of_id = of_match_device(w5100_of_match, &spi->dev); ---- a/drivers/net/ethernet/wiznet/w5100.c -+++ b/drivers/net/ethernet/wiznet/w5100.c -@@ -1159,7 +1159,7 @@ int w5100_probe(struct device *dev, cons - INIT_WORK(&priv->setrx_work, w5100_setrx_work); - INIT_WORK(&priv->restart_work, w5100_restart_work); - -- if (!IS_ERR_OR_NULL(mac_addr)) -+ if (mac_addr) - memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); - else - eth_hw_addr_random(ndev); ---- a/drivers/net/ethernet/xilinx/ll_temac_main.c -+++ b/drivers/net/ethernet/xilinx/ll_temac_main.c -@@ -438,7 +438,7 @@ static void temac_do_set_mac_address(str - - static int temac_init_mac_address(struct net_device *ndev, const void *address) - { -- ether_addr_copy(ndev->dev_addr, address); -+ memcpy(ndev->dev_addr, address, ETH_ALEN); - if (!is_valid_ether_addr(ndev->dev_addr)) - eth_hw_addr_random(ndev); - temac_do_set_mac_address(ndev); -@@ -1370,7 +1370,7 @@ static int temac_probe(struct platform_d - struct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np; - struct temac_local *lp; - struct net_device *ndev; -- const void *addr; -+ u8 addr[ETH_ALEN]; - __be32 *p; - bool little_endian; - int rc = 0; -@@ -1563,8 +1563,8 @@ static int temac_probe(struct platform_d - - if (temac_np) { - /* Retrieve the MAC address */ -- addr = of_get_mac_address(temac_np); -- if (IS_ERR(addr)) { -+ rc = of_get_mac_address(temac_np, addr); -+ if (rc) { - dev_err(&pdev->dev, "could not find MAC address\n"); - return -ENODEV; - } ---- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c -+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c -@@ -1843,8 +1843,8 @@ static int axienet_probe(struct platform - struct device_node *np; - struct axienet_local *lp; - struct net_device *ndev; -- const void *mac_addr; - struct resource *ethres; -+ u8 mac_addr[ETH_ALEN]; - int addr_width = 32; - u32 value; - -@@ -2044,13 +2044,14 @@ static int axienet_probe(struct platform - dev_info(&pdev->dev, "Ethernet core IRQ not defined\n"); - - /* Retrieve the MAC address */ -- mac_addr = of_get_mac_address(pdev->dev.of_node); -- if (IS_ERR(mac_addr)) { -- dev_warn(&pdev->dev, "could not find MAC address property: %ld\n", -- PTR_ERR(mac_addr)); -- mac_addr = NULL; -+ ret = of_get_mac_address(pdev->dev.of_node, mac_addr); -+ if (!ret) { -+ axienet_set_mac_address(ndev, mac_addr); -+ } else { -+ dev_warn(&pdev->dev, "could not find MAC address property: %d\n", -+ ret); -+ axienet_set_mac_address(ndev, NULL); - } -- axienet_set_mac_address(ndev, mac_addr); - - lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD; - lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD; ---- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c -+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c -@@ -1107,7 +1107,6 @@ static int xemaclite_of_probe(struct pla - struct net_device *ndev = NULL; - struct net_local *lp = NULL; - struct device *dev = &ofdev->dev; -- const void *mac_address; - - int rc = 0; - -@@ -1149,12 +1148,9 @@ static int xemaclite_of_probe(struct pla - lp->next_rx_buf_to_use = 0x0; - lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); - lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); -- mac_address = of_get_mac_address(ofdev->dev.of_node); - -- if (!IS_ERR(mac_address)) { -- /* Set the MAC address. */ -- ether_addr_copy(ndev->dev_addr, mac_address); -- } else { -+ rc = of_get_mac_address(ofdev->dev.of_node, ndev->dev_addr); -+ if (rc) { - dev_warn(dev, "No MAC address found, using random\n"); - eth_hw_addr_random(ndev); - } ---- a/drivers/net/wireless/ath/ath9k/init.c -+++ b/drivers/net/wireless/ath/ath9k/init.c -@@ -618,7 +618,6 @@ static int ath9k_of_init(struct ath_soft - struct ath_hw *ah = sc->sc_ah; - struct ath_common *common = ath9k_hw_common(ah); - enum ath_bus_type bus_type = common->bus_ops->ath_bus_type; -- const char *mac; - char eeprom_name[100]; - int ret; - -@@ -641,9 +640,7 @@ static int ath9k_of_init(struct ath_soft - ah->ah_flags |= AH_NO_EEP_SWAP; - } - -- mac = of_get_mac_address(np); -- if (!IS_ERR(mac)) -- ether_addr_copy(common->macaddr, mac); -+ of_get_mac_address(np, common->macaddr); - - return 0; - } ---- a/drivers/net/wireless/mediatek/mt76/eeprom.c -+++ b/drivers/net/wireless/mediatek/mt76/eeprom.c -@@ -90,15 +90,9 @@ out_put_node: - void - mt76_eeprom_override(struct mt76_dev *dev) - { --#ifdef CONFIG_OF - struct device_node *np = dev->dev->of_node; -- const u8 *mac = NULL; - -- if (np) -- mac = of_get_mac_address(np); -- if (!IS_ERR_OR_NULL(mac)) -- ether_addr_copy(dev->macaddr, mac); --#endif -+ of_get_mac_address(np, dev->macaddr); - - if (!is_valid_ether_addr(dev->macaddr)) { - eth_random_addr(dev->macaddr); ---- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c -+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c -@@ -990,11 +990,7 @@ static void rt2x00lib_rate(struct ieee80 - - void rt2x00lib_set_mac_address(struct rt2x00_dev *rt2x00dev, u8 *eeprom_mac_addr) - { -- const char *mac_addr; -- -- mac_addr = of_get_mac_address(rt2x00dev->dev->of_node); -- if (!IS_ERR(mac_addr)) -- ether_addr_copy(eeprom_mac_addr, mac_addr); -+ of_get_mac_address(rt2x00dev->dev->of_node, eeprom_mac_addr); - - if (!is_valid_ether_addr(eeprom_mac_addr)) { - eth_random_addr(eeprom_mac_addr); ---- a/drivers/of/of_net.c -+++ b/drivers/of/of_net.c -@@ -45,37 +45,29 @@ int of_get_phy_mode(struct device_node * - } - EXPORT_SYMBOL_GPL(of_get_phy_mode); - --static const void *of_get_mac_addr(struct device_node *np, const char *name) -+static int of_get_mac_addr(struct device_node *np, const char *name, u8 *addr) - { - struct property *pp = of_find_property(np, name, NULL); - -- if (pp && pp->length == ETH_ALEN && is_valid_ether_addr(pp->value)) -- return pp->value; -- return NULL; -+ if (pp && pp->length == ETH_ALEN && is_valid_ether_addr(pp->value)) { -+ memcpy(addr, pp->value, ETH_ALEN); -+ return 0; -+ } -+ return -ENODEV; - } - --static const void *of_get_mac_addr_nvmem(struct device_node *np) -+static int of_get_mac_addr_nvmem(struct device_node *np, u8 *addr) - { -- int ret; -- const void *mac; -- u8 nvmem_mac[ETH_ALEN]; - struct platform_device *pdev = of_find_device_by_node(np); -+ int ret; - - if (!pdev) -- return ERR_PTR(-ENODEV); -+ return -ENODEV; - -- ret = nvmem_get_mac_address(&pdev->dev, &nvmem_mac); -- if (ret) { -- put_device(&pdev->dev); -- return ERR_PTR(ret); -- } -- -- mac = devm_kmemdup(&pdev->dev, nvmem_mac, ETH_ALEN, GFP_KERNEL); -+ ret = nvmem_get_mac_address(&pdev->dev, addr); - put_device(&pdev->dev); -- if (!mac) -- return ERR_PTR(-ENOMEM); - -- return mac; -+ return ret; - } - - /** -@@ -98,24 +90,27 @@ static const void *of_get_mac_addr_nvmem - * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists - * but is all zeros. - * -- * Return: Will be a valid pointer on success and ERR_PTR in case of error. -+ * Return: 0 on success and errno in case of error. - */ --const void *of_get_mac_address(struct device_node *np) -+int of_get_mac_address(struct device_node *np, u8 *addr) - { -- const void *addr; -- -- addr = of_get_mac_addr(np, "mac-address"); -- if (addr) -- return addr; -+ int ret; - -- addr = of_get_mac_addr(np, "local-mac-address"); -- if (addr) -- return addr; -+ if (!np) -+ return -ENODEV; - -- addr = of_get_mac_addr(np, "address"); -- if (addr) -- return addr; -+ ret = of_get_mac_addr(np, "mac-address", addr); -+ if (!ret) -+ return 0; -+ -+ ret = of_get_mac_addr(np, "local-mac-address", addr); -+ if (!ret) -+ return 0; -+ -+ ret = of_get_mac_addr(np, "address", addr); -+ if (!ret) -+ return 0; - -- return of_get_mac_addr_nvmem(np); -+ return of_get_mac_addr_nvmem(np, addr); - } - EXPORT_SYMBOL(of_get_mac_address); ---- a/drivers/staging/octeon/ethernet.c -+++ b/drivers/staging/octeon/ethernet.c -@@ -407,14 +407,10 @@ static int cvm_oct_common_set_mac_addres - int cvm_oct_common_init(struct net_device *dev) - { - struct octeon_ethernet *priv = netdev_priv(dev); -- const u8 *mac = NULL; -+ int ret; - -- if (priv->of_node) -- mac = of_get_mac_address(priv->of_node); -- -- if (!IS_ERR_OR_NULL(mac)) -- ether_addr_copy(dev->dev_addr, mac); -- else -+ ret = of_get_mac_address(priv->of_node, dev->dev_addr); -+ if (ret) - eth_hw_addr_random(dev); - - /* ---- a/drivers/staging/wfx/main.c -+++ b/drivers/staging/wfx/main.c -@@ -339,7 +339,6 @@ int wfx_probe(struct wfx_dev *wdev) - { - int i; - int err; -- const void *macaddr; - struct gpio_desc *gpio_saved; - - // During first part of boot, gpio_wakeup cannot yet been used. So -@@ -428,9 +427,9 @@ int wfx_probe(struct wfx_dev *wdev) - - for (i = 0; i < ARRAY_SIZE(wdev->addresses); i++) { - eth_zero_addr(wdev->addresses[i].addr); -- macaddr = of_get_mac_address(wdev->dev->of_node); -- if (!IS_ERR_OR_NULL(macaddr)) { -- ether_addr_copy(wdev->addresses[i].addr, macaddr); -+ err = of_get_mac_address(wdev->dev->of_node, -+ wdev->addresses[i].addr); -+ if (!err) { - wdev->addresses[i].addr[ETH_ALEN - 1] += i; - } else { - ether_addr_copy(wdev->addresses[i].addr, ---- a/include/linux/of_net.h -+++ b/include/linux/of_net.h -@@ -13,7 +13,7 @@ - - struct net_device; - extern int of_get_phy_mode(struct device_node *np, phy_interface_t *interface); --extern const void *of_get_mac_address(struct device_node *np); -+extern int of_get_mac_address(struct device_node *np, u8 *mac); - extern struct net_device *of_find_net_device_by_node(struct device_node *np); - #else - static inline int of_get_phy_mode(struct device_node *np, -@@ -22,9 +22,9 @@ static inline int of_get_phy_mode(struct - return -ENODEV; - } - --static inline const void *of_get_mac_address(struct device_node *np) -+static inline int of_get_mac_address(struct device_node *np, u8 *mac) - { -- return ERR_PTR(-ENODEV); -+ return -ENODEV; - } - - static inline struct net_device *of_find_net_device_by_node(struct device_node *np) ---- a/include/net/dsa.h -+++ b/include/net/dsa.h -@@ -208,7 +208,7 @@ struct dsa_port { - unsigned int index; - const char *name; - struct dsa_port *cpu_dp; -- const char *mac; -+ u8 mac[ETH_ALEN]; - struct device_node *dn; - unsigned int ageing_time; - bool vlan_filtering; ---- a/net/dsa/dsa2.c -+++ b/net/dsa/dsa2.c -@@ -288,7 +288,7 @@ static int dsa_port_setup(struct dsa_por - - break; - case DSA_PORT_TYPE_USER: -- dp->mac = of_get_mac_address(dp->dn); -+ of_get_mac_address(dp->dn, dp->mac); - err = dsa_slave_create(dp); - if (err) - break; ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -1855,7 +1855,7 @@ int dsa_slave_create(struct dsa_port *po - slave_dev->hw_features |= NETIF_F_HW_TC; - slave_dev->features |= NETIF_F_LLTX; - slave_dev->ethtool_ops = &dsa_slave_ethtool_ops; -- if (!IS_ERR_OR_NULL(port->mac)) -+ if (!is_zero_ether_addr(port->mac)) - ether_addr_copy(slave_dev->dev_addr, port->mac); - else - eth_hw_addr_inherit(slave_dev, master); ---- a/net/ethernet/eth.c -+++ b/net/ethernet/eth.c -@@ -506,13 +506,14 @@ unsigned char * __weak arch_get_platform - - int eth_platform_get_mac_address(struct device *dev, u8 *mac_addr) - { -- const unsigned char *addr = NULL; -+ unsigned char *addr; -+ int ret; - -- if (dev->of_node) -- addr = of_get_mac_address(dev->of_node); -- if (IS_ERR_OR_NULL(addr)) -- addr = arch_get_platform_mac_address(); -+ ret = of_get_mac_address(dev->of_node, mac_addr); -+ if (!ret) -+ return 0; - -+ addr = arch_get_platform_mac_address(); - if (!addr) - return -ENODEV; - diff --git a/target/linux/generic/backport-5.10/732-v5.13-0009-of-net-fix-of_get_mac_addr_nvmem-for-non-platform-de.patch b/target/linux/generic/backport-5.10/732-v5.13-0009-of-net-fix-of_get_mac_addr_nvmem-for-non-platform-de.patch deleted file mode 100644 index 260a3258bb..0000000000 --- a/target/linux/generic/backport-5.10/732-v5.13-0009-of-net-fix-of_get_mac_addr_nvmem-for-non-platform-de.patch +++ /dev/null @@ -1,77 +0,0 @@ -From f10843e04a075202dbb39dfcee047e3a2fdf5a8d Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 12 Apr 2021 19:47:18 +0200 -Subject: [PATCH] of: net: fix of_get_mac_addr_nvmem() for non-platform devices - -of_get_mac_address() already supports fetching the MAC address by an -nvmem provider. But until now, it was just working for platform devices. -Esp. it was not working for DSA ports and PCI devices. It gets more -common that PCI devices have a device tree binding since SoCs contain -integrated root complexes. - -Use the nvmem of_* binding to fetch the nvmem cells by a struct -device_node. We still have to try to read the cell by device first -because there might be a nvmem_cell_lookup associated with that device. - -Signed-off-by: Michael Walle -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/of/of_net.c | 35 ++++++++++++++++++++++++++++++----- - 1 file changed, 30 insertions(+), 5 deletions(-) - ---- a/drivers/of/of_net.c -+++ b/drivers/of/of_net.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - - /** - * of_get_phy_mode - Get phy mode for given device_node -@@ -59,15 +60,39 @@ static int of_get_mac_addr(struct device - static int of_get_mac_addr_nvmem(struct device_node *np, u8 *addr) - { - struct platform_device *pdev = of_find_device_by_node(np); -+ struct nvmem_cell *cell; -+ const void *mac; -+ size_t len; - int ret; - -- if (!pdev) -- return -ENODEV; -+ /* Try lookup by device first, there might be a nvmem_cell_lookup -+ * associated with a given device. -+ */ -+ if (pdev) { -+ ret = nvmem_get_mac_address(&pdev->dev, addr); -+ put_device(&pdev->dev); -+ return ret; -+ } -+ -+ cell = of_nvmem_cell_get(np, "mac-address"); -+ if (IS_ERR(cell)) -+ return PTR_ERR(cell); -+ -+ mac = nvmem_cell_read(cell, &len); -+ nvmem_cell_put(cell); -+ -+ if (IS_ERR(mac)) -+ return PTR_ERR(mac); -+ -+ if (len != ETH_ALEN || !is_valid_ether_addr(mac)) { -+ kfree(mac); -+ return -EINVAL; -+ } - -- ret = nvmem_get_mac_address(&pdev->dev, addr); -- put_device(&pdev->dev); -+ memcpy(addr, mac, ETH_ALEN); -+ kfree(mac); - -- return ret; -+ return 0; - } - - /** diff --git a/target/linux/generic/backport-5.10/733-v5.15-0001-net-bgmac-bcma-handle-deferred-probe-error-due-to-ma.patch b/target/linux/generic/backport-5.10/733-v5.15-0001-net-bgmac-bcma-handle-deferred-probe-error-due-to-ma.patch deleted file mode 100644 index 6e7f20634f..0000000000 --- a/target/linux/generic/backport-5.10/733-v5.15-0001-net-bgmac-bcma-handle-deferred-probe-error-due-to-ma.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 029497e66bdc762e001880e4c85a91f35a54b1e2 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Sun, 19 Sep 2021 13:57:25 +0200 -Subject: [PATCH] net: bgmac-bcma: handle deferred probe error due to - mac-address -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Due to the inclusion of nvmem handling into the mac-address getter -function of_get_mac_address() by -commit d01f449c008a ("of_net: add NVMEM support to of_get_mac_address") -it is now possible to get a -EPROBE_DEFER return code. Which did cause -bgmac to assign a random ethernet address. - -This exact issue happened on my Meraki MR32. The nvmem provider is -an EEPROM (at24c64) which gets instantiated once the module -driver is loaded... This happens once the filesystem becomes available. - -With this patch, bgmac_probe() will propagate the -EPROBE_DEFER error. -Then the driver subsystem will reschedule the probe at a later time. - -Cc: Petr Å tetiar -Cc: Michael Walle -Fixes: d01f449c008a ("of_net: add NVMEM support to of_get_mac_address") -Signed-off-by: Christian Lamparter -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bgmac-bcma.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/net/ethernet/broadcom/bgmac-bcma.c -+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c -@@ -129,6 +129,8 @@ static int bgmac_probe(struct bcma_devic - bcma_set_drvdata(core, bgmac); - - err = of_get_mac_address(bgmac->dev->of_node, bgmac->net_dev->dev_addr); -+ if (err == -EPROBE_DEFER) -+ return err; - - /* If no MAC address assigned via device tree, check SPROM */ - if (err) { diff --git a/target/linux/generic/backport-5.10/733-v5.15-0002-net-bgmac-platform-handle-mac-address-deferral.patch b/target/linux/generic/backport-5.10/733-v5.15-0002-net-bgmac-platform-handle-mac-address-deferral.patch deleted file mode 100644 index bde62f3b1b..0000000000 --- a/target/linux/generic/backport-5.10/733-v5.15-0002-net-bgmac-platform-handle-mac-address-deferral.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 763716a55cb1f480ffe1a9702e6b5d9ea1a80a24 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Sat, 25 Sep 2021 11:36:27 +0000 -Subject: [PATCH] net: bgmac-platform: handle mac-address deferral - -This patch is a replication of Christian Lamparter's "net: bgmac-bcma: -handle deferred probe error due to mac-address" patch for the -bgmac-platform driver [1]. - -As is the case with the bgmac-bcma driver, this change is to cover the -scenario where the MAC address cannot yet be discovered due to reliance -on an nvmem provider which is yet to be instantiated, resulting in a -random address being assigned that has to be manually overridden. - -[1] https://lore.kernel.org/netdev/20210919115725.29064-1-chunkeey@gmail.com - -Signed-off-by: Matthew Hagan -Reviewed-by: Andrew Lunn -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bgmac-platform.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/net/ethernet/broadcom/bgmac-platform.c -+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c -@@ -193,6 +193,9 @@ static int bgmac_probe(struct platform_d - bgmac->dma_dev = &pdev->dev; - - ret = of_get_mac_address(np, bgmac->net_dev->dev_addr); -+ if (ret == -EPROBE_DEFER) -+ return ret; -+ - if (ret) - dev_warn(&pdev->dev, - "MAC address not present in device tree\n"); diff --git a/target/linux/generic/backport-5.10/734-v5.16-0001-net-bgmac-improve-handling-PHY.patch b/target/linux/generic/backport-5.10/734-v5.16-0001-net-bgmac-improve-handling-PHY.patch deleted file mode 100644 index 6788a2ec35..0000000000 --- a/target/linux/generic/backport-5.10/734-v5.16-0001-net-bgmac-improve-handling-PHY.patch +++ /dev/null @@ -1,84 +0,0 @@ -From b5375509184dc23d2b7fa0c5ed8763899ccc9674 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sat, 2 Oct 2021 19:58:11 +0200 -Subject: [PATCH] net: bgmac: improve handling PHY -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. Use info from DT if available - -It allows describing for example a fixed link. It's more accurate than -just guessing there may be one (depending on a chipset). - -2. Verify PHY ID before trying to connect PHY - -PHY addr 0x1e (30) is special in Broadcom routers and means a switch -connected as MDIO devices instead of a real PHY. Don't try connecting to -it. - -Signed-off-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bgmac-bcma.c | 33 ++++++++++++++-------- - 1 file changed, 21 insertions(+), 12 deletions(-) - ---- a/drivers/net/ethernet/broadcom/bgmac-bcma.c -+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - #include "bgmac.h" - -@@ -86,17 +87,28 @@ static int bcma_phy_connect(struct bgmac - struct phy_device *phy_dev; - char bus_id[MII_BUS_ID_SIZE + 3]; - -+ /* DT info should be the most accurate */ -+ phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node, -+ bgmac_adjust_link); -+ if (phy_dev) -+ return 0; -+ - /* Connect to the PHY */ -- snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id, -- bgmac->phyaddr); -- phy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link, -- PHY_INTERFACE_MODE_MII); -- if (IS_ERR(phy_dev)) { -- dev_err(bgmac->dev, "PHY connection failed\n"); -- return PTR_ERR(phy_dev); -+ if (bgmac->mii_bus && bgmac->phyaddr != BGMAC_PHY_NOREGS) { -+ snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id, -+ bgmac->phyaddr); -+ phy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link, -+ PHY_INTERFACE_MODE_MII); -+ if (IS_ERR(phy_dev)) { -+ dev_err(bgmac->dev, "PHY connection failed\n"); -+ return PTR_ERR(phy_dev); -+ } -+ -+ return 0; - } - -- return 0; -+ /* Assume a fixed link to the switch port */ -+ return bgmac_phy_connect_direct(bgmac); - } - - static const struct bcma_device_id bgmac_bcma_tbl[] = { -@@ -297,10 +309,7 @@ static int bgmac_probe(struct bcma_devic - bgmac->cco_ctl_maskset = bcma_bgmac_cco_ctl_maskset; - bgmac->get_bus_clock = bcma_bgmac_get_bus_clock; - bgmac->cmn_maskset32 = bcma_bgmac_cmn_maskset32; -- if (bgmac->mii_bus) -- bgmac->phy_connect = bcma_phy_connect; -- else -- bgmac->phy_connect = bgmac_phy_connect_direct; -+ bgmac->phy_connect = bcma_phy_connect; - - err = bgmac_enet_probe(bgmac); - if (err) diff --git a/target/linux/generic/backport-5.10/734-v5.16-0002-net-bgmac-support-MDIO-described-in-DT.patch b/target/linux/generic/backport-5.10/734-v5.16-0002-net-bgmac-support-MDIO-described-in-DT.patch deleted file mode 100644 index f134828273..0000000000 --- a/target/linux/generic/backport-5.10/734-v5.16-0002-net-bgmac-support-MDIO-described-in-DT.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 45c9d966688e7fad7f24bfc450547d91e4304d0b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sat, 2 Oct 2021 19:58:12 +0200 -Subject: [PATCH] net: bgmac: support MDIO described in DT -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Check ethernet controller DT node for "mdio" subnode and use it with -of_mdiobus_register() when present. That allows specifying MDIO and its -PHY devices in a standard DT based way. - -This is required for BCM53573 SoC support. That family is sometimes -called Northstar (by marketing?) but is quite different from it. It uses -different CPU(s) and many different hw blocks. - -One of shared blocks in BCM53573 is Ethernet controller. Switch however -is not SRAB accessible (as it Northstar) but is MDIO attached. - -Signed-off-by: Rafał Miłecki -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c -+++ b/drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c -@@ -10,6 +10,7 @@ - - #include - #include -+#include - #include "bgmac.h" - - static bool bcma_mdio_wait_value(struct bcma_device *core, u16 reg, u32 mask, -@@ -211,6 +212,7 @@ struct mii_bus *bcma_mdio_mii_register(s - { - struct bcma_device *core = bgmac->bcma.core; - struct mii_bus *mii_bus; -+ struct device_node *np; - int err; - - mii_bus = mdiobus_alloc(); -@@ -229,7 +231,9 @@ struct mii_bus *bcma_mdio_mii_register(s - mii_bus->parent = &core->dev; - mii_bus->phy_mask = ~(1 << bgmac->phyaddr); - -- err = mdiobus_register(mii_bus); -+ np = of_get_child_by_name(core->dev.of_node, "mdio"); -+ -+ err = of_mdiobus_register(mii_bus, np); - if (err) { - dev_err(&core->dev, "Registration of mii bus failed\n"); - goto err_free_bus; diff --git a/target/linux/generic/backport-5.10/735-v5.14-01-net-dsa-qca8k-change-simple-print-to-dev-variant.patch b/target/linux/generic/backport-5.10/735-v5.14-01-net-dsa-qca8k-change-simple-print-to-dev-variant.patch deleted file mode 100644 index b8e6d9b613..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-01-net-dsa-qca8k-change-simple-print-to-dev-variant.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 5d9e068402dcf7354cc8ee66c2152845306d2ccb Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 22:59:51 +0200 -Subject: [PATCH] net: dsa: qca8k: change simple print to dev variant - -Change pr_err and pr_warn to dev variant. - -Signed-off-by: Ansuel Smith -Reviewed-by: Florian Fainelli -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -701,7 +701,7 @@ qca8k_setup(struct dsa_switch *ds) - - /* Make sure that port 0 is the cpu port */ - if (!dsa_is_cpu_port(ds, 0)) { -- pr_err("port 0 is not the CPU port\n"); -+ dev_err(priv->dev, "port 0 is not the CPU port"); - return -EINVAL; - } - -@@ -711,7 +711,7 @@ qca8k_setup(struct dsa_switch *ds) - priv->regmap = devm_regmap_init(ds->dev, NULL, priv, - &qca8k_regmap_config); - if (IS_ERR(priv->regmap)) -- pr_warn("regmap initialization failed"); -+ dev_warn(priv->dev, "regmap initialization failed"); - - ret = qca8k_setup_mdio_bus(priv); - if (ret) diff --git a/target/linux/generic/backport-5.10/735-v5.14-02-net-dsa-qca8k-use-iopoll-macro-for-qca8k_busy_wait.patch b/target/linux/generic/backport-5.10/735-v5.14-02-net-dsa-qca8k-use-iopoll-macro-for-qca8k_busy_wait.patch deleted file mode 100644 index ff8288d484..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-02-net-dsa-qca8k-use-iopoll-macro-for-qca8k_busy_wait.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 2ad255f2faaffb3af786031fba2e7955454b558a Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 22:59:52 +0200 -Subject: [PATCH] net: dsa: qca8k: use iopoll macro for qca8k_busy_wait - -Use iopoll macro instead of while loop. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 23 +++++++++++------------ - drivers/net/dsa/qca8k.h | 2 ++ - 2 files changed, 13 insertions(+), 12 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -262,21 +262,20 @@ static struct regmap_config qca8k_regmap - static int - qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) - { -- unsigned long timeout; -+ u32 val; -+ int ret; - -- timeout = jiffies + msecs_to_jiffies(20); -+ ret = read_poll_timeout(qca8k_read, val, !(val & mask), -+ 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, -+ priv, reg); - -- /* loop until the busy flag has cleared */ -- do { -- u32 val = qca8k_read(priv, reg); -- int busy = val & mask; -+ /* Check if qca8k_read has failed for a different reason -+ * before returning -ETIMEDOUT -+ */ -+ if (ret < 0 && val < 0) -+ return val; - -- if (!busy) -- break; -- cond_resched(); -- } while (!time_after_eq(jiffies, timeout)); -- -- return time_after_eq(jiffies, timeout); -+ return ret; - } - - static void ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -18,6 +18,8 @@ - #define PHY_ID_QCA8337 0x004dd036 - #define QCA8K_ID_QCA8337 0x13 - -+#define QCA8K_BUSY_WAIT_TIMEOUT 20 -+ - #define QCA8K_NUM_FDB_RECORDS 2048 - - #define QCA8K_CPU_PORT 0 diff --git a/target/linux/generic/backport-5.10/735-v5.14-03-net-dsa-qca8k-improve-qca8k-read-write-rmw-bus-acces.patch b/target/linux/generic/backport-5.10/735-v5.14-03-net-dsa-qca8k-improve-qca8k-read-write-rmw-bus-acces.patch deleted file mode 100644 index c403589874..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-03-net-dsa-qca8k-improve-qca8k-read-write-rmw-bus-acces.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 504bf65931824eda83494e5b5d75686e27ace03e Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 22:59:53 +0200 -Subject: [PATCH] net: dsa: qca8k: improve qca8k read/write/rmw bus access - -Put bus in local variable to improve faster access to the mdio bus. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 29 ++++++++++++++++------------- - 1 file changed, 16 insertions(+), 13 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -142,17 +142,18 @@ qca8k_set_page(struct mii_bus *bus, u16 - static u32 - qca8k_read(struct qca8k_priv *priv, u32 reg) - { -+ struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - u32 val; - - qca8k_split_addr(reg, &r1, &r2, &page); - -- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); -+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - -- qca8k_set_page(priv->bus, page); -- val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); -+ qca8k_set_page(bus, page); -+ val = qca8k_mii_read32(bus, 0x10 | r2, r1); - -- mutex_unlock(&priv->bus->mdio_lock); -+ mutex_unlock(&bus->mdio_lock); - - return val; - } -@@ -160,35 +161,37 @@ qca8k_read(struct qca8k_priv *priv, u32 - static void - qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) - { -+ struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - - qca8k_split_addr(reg, &r1, &r2, &page); - -- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); -+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - -- qca8k_set_page(priv->bus, page); -- qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); -+ qca8k_set_page(bus, page); -+ qca8k_mii_write32(bus, 0x10 | r2, r1, val); - -- mutex_unlock(&priv->bus->mdio_lock); -+ mutex_unlock(&bus->mdio_lock); - } - - static u32 - qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) - { -+ struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - u32 ret; - - qca8k_split_addr(reg, &r1, &r2, &page); - -- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); -+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - -- qca8k_set_page(priv->bus, page); -- ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); -+ qca8k_set_page(bus, page); -+ ret = qca8k_mii_read32(bus, 0x10 | r2, r1); - ret &= ~mask; - ret |= val; -- qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret); -+ qca8k_mii_write32(bus, 0x10 | r2, r1, ret); - -- mutex_unlock(&priv->bus->mdio_lock); -+ mutex_unlock(&bus->mdio_lock); - - return ret; - } diff --git a/target/linux/generic/backport-5.10/735-v5.14-04-net-dsa-qca8k-handle-qca8k_set_page-errors.patch b/target/linux/generic/backport-5.10/735-v5.14-04-net-dsa-qca8k-handle-qca8k_set_page-errors.patch deleted file mode 100644 index 6be494a8c7..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-04-net-dsa-qca8k-handle-qca8k_set_page-errors.patch +++ /dev/null @@ -1,101 +0,0 @@ -From ba5707ec58cfb6853dff41c2aae72deb6a03d389 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 22:59:54 +0200 -Subject: [PATCH] net: dsa: qca8k: handle qca8k_set_page errors - -With a remote possibility, the set_page function can fail. Since this is -a critical part of the write/read qca8k regs, propagate the error and -terminate any read/write operation. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 33 ++++++++++++++++++++++++++------- - 1 file changed, 26 insertions(+), 7 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -127,16 +127,23 @@ qca8k_mii_write32(struct mii_bus *bus, i - "failed to write qca8k 32bit register\n"); - } - --static void -+static int - qca8k_set_page(struct mii_bus *bus, u16 page) - { -+ int ret; -+ - if (page == qca8k_current_page) -- return; -+ return 0; - -- if (bus->write(bus, 0x18, 0, page) < 0) -+ ret = bus->write(bus, 0x18, 0, page); -+ if (ret < 0) { - dev_err_ratelimited(&bus->dev, - "failed to set qca8k page\n"); -+ return ret; -+ } -+ - qca8k_current_page = page; -+ return 0; - } - - static u32 -@@ -150,11 +157,14 @@ qca8k_read(struct qca8k_priv *priv, u32 - - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - -- qca8k_set_page(bus, page); -+ val = qca8k_set_page(bus, page); -+ if (val < 0) -+ goto exit; -+ - val = qca8k_mii_read32(bus, 0x10 | r2, r1); - -+exit: - mutex_unlock(&bus->mdio_lock); -- - return val; - } - -@@ -163,14 +173,19 @@ qca8k_write(struct qca8k_priv *priv, u32 - { - struct mii_bus *bus = priv->bus; - u16 r1, r2, page; -+ int ret; - - qca8k_split_addr(reg, &r1, &r2, &page); - - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - -- qca8k_set_page(bus, page); -+ ret = qca8k_set_page(bus, page); -+ if (ret < 0) -+ goto exit; -+ - qca8k_mii_write32(bus, 0x10 | r2, r1, val); - -+exit: - mutex_unlock(&bus->mdio_lock); - } - -@@ -185,12 +200,16 @@ qca8k_rmw(struct qca8k_priv *priv, u32 r - - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - -- qca8k_set_page(bus, page); -+ ret = qca8k_set_page(bus, page); -+ if (ret < 0) -+ goto exit; -+ - ret = qca8k_mii_read32(bus, 0x10 | r2, r1); - ret &= ~mask; - ret |= val; - qca8k_mii_write32(bus, 0x10 | r2, r1, ret); - -+exit: - mutex_unlock(&bus->mdio_lock); - - return ret; diff --git a/target/linux/generic/backport-5.10/735-v5.14-05-net-dsa-qca8k-handle-error-with-qca8k_read-operation.patch b/target/linux/generic/backport-5.10/735-v5.14-05-net-dsa-qca8k-handle-error-with-qca8k_read-operation.patch deleted file mode 100644 index 3349b7897a..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-05-net-dsa-qca8k-handle-error-with-qca8k_read-operation.patch +++ /dev/null @@ -1,207 +0,0 @@ -From 028f5f8ef44fcf87a456772cbb9f0d90a0a22884 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 22:59:55 +0200 -Subject: [PATCH] net: dsa: qca8k: handle error with qca8k_read operation - -qca8k_read can fail. Rework any user to handle error values and -correctly return. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 73 ++++++++++++++++++++++++++++++++--------- - 1 file changed, 58 insertions(+), 15 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -231,8 +231,13 @@ static int - qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ctx; -+ int ret; -+ -+ ret = qca8k_read(priv, reg); -+ if (ret < 0) -+ return ret; - -- *val = qca8k_read(priv, reg); -+ *val = ret; - - return 0; - } -@@ -300,15 +305,20 @@ qca8k_busy_wait(struct qca8k_priv *priv, - return ret; - } - --static void -+static int - qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) - { -- u32 reg[4]; -+ u32 reg[4], val; - int i; - - /* load the ARL table into an array */ -- for (i = 0; i < 4; i++) -- reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4)); -+ for (i = 0; i < 4; i++) { -+ val = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4)); -+ if (val < 0) -+ return val; -+ -+ reg[i] = val; -+ } - - /* vid - 83:72 */ - fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M; -@@ -323,6 +333,8 @@ qca8k_fdb_read(struct qca8k_priv *priv, - fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff; - fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff; - fdb->mac[5] = reg[0] & 0xff; -+ -+ return 0; - } - - static void -@@ -374,6 +386,8 @@ qca8k_fdb_access(struct qca8k_priv *priv - /* Check for table full violation when adding an entry */ - if (cmd == QCA8K_FDB_LOAD) { - reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC); -+ if (reg < 0) -+ return reg; - if (reg & QCA8K_ATU_FUNC_FULL) - return -1; - } -@@ -388,10 +402,10 @@ qca8k_fdb_next(struct qca8k_priv *priv, - - qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); - ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); -- if (ret >= 0) -- qca8k_fdb_read(priv, fdb); -+ if (ret < 0) -+ return ret; - -- return ret; -+ return qca8k_fdb_read(priv, fdb); - } - - static int -@@ -449,6 +463,8 @@ qca8k_vlan_access(struct qca8k_priv *pri - /* Check for table full violation when adding an entry */ - if (cmd == QCA8K_VLAN_LOAD) { - reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1); -+ if (reg < 0) -+ return reg; - if (reg & QCA8K_VTU_FUNC1_FULL) - return -ENOMEM; - } -@@ -475,6 +491,8 @@ qca8k_vlan_add(struct qca8k_priv *priv, - goto out; - - reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); -+ if (reg < 0) -+ return reg; - reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; - reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port)); - if (untagged) -@@ -506,6 +524,8 @@ qca8k_vlan_del(struct qca8k_priv *priv, - goto out; - - reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); -+ if (reg < 0) -+ return reg; - reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port)); - reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT << - QCA8K_VTU_FUNC0_EG_MODE_S(port); -@@ -621,8 +641,11 @@ qca8k_mdio_read(struct qca8k_priv *priv, - QCA8K_MDIO_MASTER_BUSY)) - return -ETIMEDOUT; - -- val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & -- QCA8K_MDIO_MASTER_DATA_MASK); -+ val = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL); -+ if (val < 0) -+ return val; -+ -+ val &= QCA8K_MDIO_MASTER_DATA_MASK; - - return val; - } -@@ -978,6 +1001,8 @@ qca8k_phylink_mac_link_state(struct dsa_ - u32 reg; - - reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port)); -+ if (reg < 0) -+ return reg; - - state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); - state->an_complete = state->link; -@@ -1078,18 +1103,26 @@ qca8k_get_ethtool_stats(struct dsa_switc - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - const struct qca8k_mib_desc *mib; -- u32 reg, i; -+ u32 reg, i, val; - u64 hi; - - for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) { - mib = &ar8327_mib[i]; - reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; - -- data[i] = qca8k_read(priv, reg); -+ val = qca8k_read(priv, reg); -+ if (val < 0) -+ continue; -+ - if (mib->size == 2) { - hi = qca8k_read(priv, reg + 4); -- data[i] |= hi << 32; -+ if (hi < 0) -+ continue; - } -+ -+ data[i] = val; -+ if (mib->size == 2) -+ data[i] |= hi << 32; - } - } - -@@ -1107,18 +1140,25 @@ qca8k_set_mac_eee(struct dsa_switch *ds, - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); -+ int ret = 0; - u32 reg; - - mutex_lock(&priv->reg_mutex); - reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL); -+ if (reg < 0) { -+ ret = reg; -+ goto exit; -+ } -+ - if (eee->eee_enabled) - reg |= lpi_en; - else - reg &= ~lpi_en; - qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); -- mutex_unlock(&priv->reg_mutex); - -- return 0; -+exit: -+ mutex_unlock(&priv->reg_mutex); -+ return ret; - } - - static int -@@ -1456,6 +1496,9 @@ qca8k_sw_probe(struct mdio_device *mdiod - - /* read the switches ID register */ - id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); -+ if (id < 0) -+ return id; -+ - id >>= QCA8K_MASK_CTRL_ID_S; - id &= QCA8K_MASK_CTRL_ID_M; - if (id != QCA8K_ID_QCA8337) diff --git a/target/linux/generic/backport-5.10/735-v5.14-06-net-dsa-qca8k-handle-error-with-qca8k_write-operatio.patch b/target/linux/generic/backport-5.10/735-v5.14-06-net-dsa-qca8k-handle-error-with-qca8k_write-operatio.patch deleted file mode 100644 index 1e0e224c39..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-06-net-dsa-qca8k-handle-error-with-qca8k_write-operatio.patch +++ /dev/null @@ -1,263 +0,0 @@ -From d7805757c75c76e9518fc1023a29f0c4eed5b581 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 22:59:56 +0200 -Subject: [PATCH] net: dsa: qca8k: handle error with qca8k_write operation - -qca8k_write can fail. Rework any user to handle error values and -correctly return. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 102 ++++++++++++++++++++++++++-------------- - 1 file changed, 67 insertions(+), 35 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -168,7 +168,7 @@ exit: - return val; - } - --static void -+static int - qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) - { - struct mii_bus *bus = priv->bus; -@@ -187,6 +187,7 @@ qca8k_write(struct qca8k_priv *priv, u32 - - exit: - mutex_unlock(&bus->mdio_lock); -+ return ret; - } - - static u32 -@@ -247,9 +248,7 @@ qca8k_regmap_write(void *ctx, uint32_t r - { - struct qca8k_priv *priv = (struct qca8k_priv *)ctx; - -- qca8k_write(priv, reg, val); -- -- return 0; -+ return qca8k_write(priv, reg, val); - } - - static const struct regmap_range qca8k_readable_ranges[] = { -@@ -367,6 +366,7 @@ static int - qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port) - { - u32 reg; -+ int ret; - - /* Set the command and FDB index */ - reg = QCA8K_ATU_FUNC_BUSY; -@@ -377,7 +377,9 @@ qca8k_fdb_access(struct qca8k_priv *priv - } - - /* Write the function register triggering the table access */ -- qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); -+ ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); -+ if (ret) -+ return ret; - - /* wait for completion */ - if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY)) -@@ -447,6 +449,7 @@ static int - qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) - { - u32 reg; -+ int ret; - - /* Set the command and VLAN index */ - reg = QCA8K_VTU_FUNC1_BUSY; -@@ -454,7 +457,9 @@ qca8k_vlan_access(struct qca8k_priv *pri - reg |= vid << QCA8K_VTU_FUNC1_VID_S; - - /* Write the function register triggering the table access */ -- qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); -+ ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); -+ if (ret) -+ return ret; - - /* wait for completion */ - if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY)) -@@ -502,7 +507,9 @@ qca8k_vlan_add(struct qca8k_priv *priv, - reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG << - QCA8K_VTU_FUNC0_EG_MODE_S(port); - -- qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); -+ ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); -+ if (ret) -+ return ret; - ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); - - out: -@@ -545,7 +552,9 @@ qca8k_vlan_del(struct qca8k_priv *priv, - if (del) { - ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid); - } else { -- qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); -+ ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); -+ if (ret) -+ return ret; - ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); - } - -@@ -555,15 +564,20 @@ out: - return ret; - } - --static void -+static int - qca8k_mib_init(struct qca8k_priv *priv) - { -+ int ret; -+ - mutex_lock(&priv->reg_mutex); - qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); - qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); - qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); -- qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); -+ -+ ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); -+ - mutex_unlock(&priv->reg_mutex); -+ return ret; - } - - static void -@@ -600,6 +614,7 @@ static int - qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) - { - u32 phy, val; -+ int ret; - - if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) - return -EINVAL; -@@ -613,7 +628,9 @@ qca8k_mdio_write(struct qca8k_priv *priv - QCA8K_MDIO_MASTER_REG_ADDR(regnum) | - QCA8K_MDIO_MASTER_DATA(data); - -- qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); -+ ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); -+ if (ret) -+ return ret; - - return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); -@@ -623,6 +640,7 @@ static int - qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) - { - u32 phy, val; -+ int ret; - - if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) - return -EINVAL; -@@ -635,7 +653,9 @@ qca8k_mdio_read(struct qca8k_priv *priv, - QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | - QCA8K_MDIO_MASTER_REG_ADDR(regnum); - -- qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); -+ ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); -+ if (ret) -+ return ret; - - if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY)) -@@ -766,12 +786,18 @@ qca8k_setup(struct dsa_switch *ds) - QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); - - /* Enable MIB counters */ -- qca8k_mib_init(priv); -+ ret = qca8k_mib_init(priv); -+ if (ret) -+ dev_warn(priv->dev, "mib init failed"); - - /* Enable QCA header mode on the cpu port */ -- qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), -- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | -- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); -+ ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), -+ QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | -+ QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); -+ if (ret) { -+ dev_err(priv->dev, "failed enabling QCA header mode"); -+ return ret; -+ } - - /* Disable forwarding by default on all ports */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) -@@ -783,11 +809,13 @@ qca8k_setup(struct dsa_switch *ds) - qca8k_port_set_status(priv, i, 0); - - /* Forward all unknown frames to CPU port for Linux processing */ -- qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, -- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | -- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | -- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | -- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); -+ ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, -+ BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | -+ BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | -+ BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | -+ BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); -+ if (ret) -+ return ret; - - /* Setup connection between CPU port & user ports */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) { -@@ -815,16 +843,20 @@ qca8k_setup(struct dsa_switch *ds) - qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), - 0xfff << shift, - QCA8K_PORT_VID_DEF << shift); -- qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), -- QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | -- QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); -+ ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), -+ QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | -+ QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); -+ if (ret) -+ return ret; - } - } - - /* Setup our port MTUs to match power on defaults */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) - priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; -- qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); -+ ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); -+ if (ret) -+ dev_warn(priv->dev, "failed setting MTU settings"); - - /* Flush the FDB table */ - qca8k_fdb_flush(priv); -@@ -1140,8 +1172,8 @@ qca8k_set_mac_eee(struct dsa_switch *ds, - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); -- int ret = 0; - u32 reg; -+ int ret; - - mutex_lock(&priv->reg_mutex); - reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL); -@@ -1154,7 +1186,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds, - reg |= lpi_en; - else - reg &= ~lpi_en; -- qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); -+ ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); - - exit: - mutex_unlock(&priv->reg_mutex); -@@ -1284,9 +1316,7 @@ qca8k_port_change_mtu(struct dsa_switch - mtu = priv->port_mtu[i]; - - /* Include L2 header / FCS length */ -- qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN); -- -- return 0; -+ return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN); - } - - static int diff --git a/target/linux/generic/backport-5.10/735-v5.14-07-net-dsa-qca8k-handle-error-with-qca8k_rmw-operation.patch b/target/linux/generic/backport-5.10/735-v5.14-07-net-dsa-qca8k-handle-error-with-qca8k_rmw-operation.patch deleted file mode 100644 index 506966f1af..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-07-net-dsa-qca8k-handle-error-with-qca8k_rmw-operation.patch +++ /dev/null @@ -1,226 +0,0 @@ -From aaf421425cbdec4eb6fd75a29e65c2867b0b7bbd Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 22:59:57 +0200 -Subject: [PATCH] net: dsa: qca8k: handle error with qca8k_rmw operation - -qca8k_rmw can fail. Rework any user to handle error values and -correctly return. Change qca8k_rmw to return the error code or 0 instead -of the reg value. The reg returned by qca8k_rmw wasn't used anywhere, -so this doesn't cause any functional change. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 133 +++++++++++++++++++++++++--------------- - 1 file changed, 83 insertions(+), 50 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -190,12 +190,13 @@ exit: - return ret; - } - --static u32 --qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) -+static int -+qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) - { - struct mii_bus *bus = priv->bus; - u16 r1, r2, page; -- u32 ret; -+ u32 val; -+ int ret; - - qca8k_split_addr(reg, &r1, &r2, &page); - -@@ -205,10 +206,15 @@ qca8k_rmw(struct qca8k_priv *priv, u32 r - if (ret < 0) - goto exit; - -- ret = qca8k_mii_read32(bus, 0x10 | r2, r1); -- ret &= ~mask; -- ret |= val; -- qca8k_mii_write32(bus, 0x10 | r2, r1, ret); -+ val = qca8k_mii_read32(bus, 0x10 | r2, r1); -+ if (val < 0) { -+ ret = val; -+ goto exit; -+ } -+ -+ val &= ~mask; -+ val |= write_val; -+ qca8k_mii_write32(bus, 0x10 | r2, r1, val); - - exit: - mutex_unlock(&bus->mdio_lock); -@@ -216,16 +222,16 @@ exit: - return ret; - } - --static void -+static int - qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val) - { -- qca8k_rmw(priv, reg, 0, val); -+ return qca8k_rmw(priv, reg, 0, val); - } - --static void -+static int - qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val) - { -- qca8k_rmw(priv, reg, val, 0); -+ return qca8k_rmw(priv, reg, val, 0); - } - - static int -@@ -570,12 +576,19 @@ qca8k_mib_init(struct qca8k_priv *priv) - int ret; - - mutex_lock(&priv->reg_mutex); -- qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); -+ ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); -+ if (ret) -+ goto exit; -+ - qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); -- qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); -+ -+ ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); -+ if (ret) -+ goto exit; - - ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); - -+exit: - mutex_unlock(&priv->reg_mutex); - return ret; - } -@@ -747,9 +760,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv * - * a dt-overlay and driver reload changed the configuration - */ - -- qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, -- QCA8K_MDIO_MASTER_EN); -- return 0; -+ return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, -+ QCA8K_MDIO_MASTER_EN); - } - - priv->ops.phy_read = qca8k_phy_read; -@@ -782,8 +794,12 @@ qca8k_setup(struct dsa_switch *ds) - return ret; - - /* Enable CPU Port */ -- qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, -- QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); -+ ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, -+ QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); -+ if (ret) { -+ dev_err(priv->dev, "failed enabling CPU port"); -+ return ret; -+ } - - /* Enable MIB counters */ - ret = qca8k_mib_init(priv); -@@ -800,9 +816,12 @@ qca8k_setup(struct dsa_switch *ds) - } - - /* Disable forwarding by default on all ports */ -- for (i = 0; i < QCA8K_NUM_PORTS; i++) -- qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), -- QCA8K_PORT_LOOKUP_MEMBER, 0); -+ for (i = 0; i < QCA8K_NUM_PORTS; i++) { -+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), -+ QCA8K_PORT_LOOKUP_MEMBER, 0); -+ if (ret) -+ return ret; -+ } - - /* Disable MAC by default on all ports */ - for (i = 1; i < QCA8K_NUM_PORTS; i++) -@@ -821,28 +840,37 @@ qca8k_setup(struct dsa_switch *ds) - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - /* CPU port gets connected to all user ports of the switch */ - if (dsa_is_cpu_port(ds, i)) { -- qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), -- QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); -+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), -+ QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); -+ if (ret) -+ return ret; - } - - /* Individual user ports get connected to CPU port only */ - if (dsa_is_user_port(ds, i)) { - int shift = 16 * (i % 2); - -- qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), -- QCA8K_PORT_LOOKUP_MEMBER, -- BIT(QCA8K_CPU_PORT)); -+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), -+ QCA8K_PORT_LOOKUP_MEMBER, -+ BIT(QCA8K_CPU_PORT)); -+ if (ret) -+ return ret; - - /* Enable ARP Auto-learning by default */ -- qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), -- QCA8K_PORT_LOOKUP_LEARN); -+ ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), -+ QCA8K_PORT_LOOKUP_LEARN); -+ if (ret) -+ return ret; - - /* For port based vlans to work we need to set the - * default egress vid - */ -- qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), -- 0xfff << shift, -- QCA8K_PORT_VID_DEF << shift); -+ ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), -+ 0xfff << shift, -+ QCA8K_PORT_VID_DEF << shift); -+ if (ret) -+ return ret; -+ - ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), - QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | - QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); -@@ -1234,7 +1262,7 @@ qca8k_port_bridge_join(struct dsa_switch - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int port_mask = BIT(QCA8K_CPU_PORT); -- int i; -+ int i, ret; - - for (i = 1; i < QCA8K_NUM_PORTS; i++) { - if (dsa_to_port(ds, i)->bridge_dev != br) -@@ -1242,17 +1270,20 @@ qca8k_port_bridge_join(struct dsa_switch - /* Add this port to the portvlan mask of the other ports - * in the bridge - */ -- qca8k_reg_set(priv, -- QCA8K_PORT_LOOKUP_CTRL(i), -- BIT(port)); -+ ret = qca8k_reg_set(priv, -+ QCA8K_PORT_LOOKUP_CTRL(i), -+ BIT(port)); -+ if (ret) -+ return ret; - if (i != port) - port_mask |= BIT(i); - } -+ - /* Add all other ports to this ports portvlan mask */ -- qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), -- QCA8K_PORT_LOOKUP_MEMBER, port_mask); -+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), -+ QCA8K_PORT_LOOKUP_MEMBER, port_mask); - -- return 0; -+ return ret; - } - - static void diff --git a/target/linux/generic/backport-5.10/735-v5.14-08-net-dsa-qca8k-handle-error-from-qca8k_busy_wait.patch b/target/linux/generic/backport-5.10/735-v5.14-08-net-dsa-qca8k-handle-error-from-qca8k_busy_wait.patch deleted file mode 100644 index 360ce1d947..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-08-net-dsa-qca8k-handle-error-from-qca8k_busy_wait.patch +++ /dev/null @@ -1,66 +0,0 @@ -From b7c818d194927bdc60ed15db55bb8654496a36b7 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 22:59:58 +0200 -Subject: [PATCH] net: dsa: qca8k: handle error from qca8k_busy_wait - -Propagate errors from qca8k_busy_wait instead of hardcoding return -value. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 21 +++++++++++++-------- - 1 file changed, 13 insertions(+), 8 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -388,8 +388,9 @@ qca8k_fdb_access(struct qca8k_priv *priv - return ret; - - /* wait for completion */ -- if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY)) -- return -1; -+ ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY); -+ if (ret) -+ return ret; - - /* Check for table full violation when adding an entry */ - if (cmd == QCA8K_FDB_LOAD) { -@@ -468,8 +469,9 @@ qca8k_vlan_access(struct qca8k_priv *pri - return ret; - - /* wait for completion */ -- if (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY)) -- return -ETIMEDOUT; -+ ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY); -+ if (ret) -+ return ret; - - /* Check for table full violation when adding an entry */ - if (cmd == QCA8K_VLAN_LOAD) { -@@ -580,7 +582,9 @@ qca8k_mib_init(struct qca8k_priv *priv) - if (ret) - goto exit; - -- qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); -+ ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); -+ if (ret) -+ goto exit; - - ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); - if (ret) -@@ -670,9 +674,10 @@ qca8k_mdio_read(struct qca8k_priv *priv, - if (ret) - return ret; - -- if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -- QCA8K_MDIO_MASTER_BUSY)) -- return -ETIMEDOUT; -+ ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -+ QCA8K_MDIO_MASTER_BUSY); -+ if (ret) -+ return ret; - - val = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL); - if (val < 0) diff --git a/target/linux/generic/backport-5.10/735-v5.14-09-net-dsa-qca8k-add-support-for-qca8327-switch.patch b/target/linux/generic/backport-5.10/735-v5.14-09-net-dsa-qca8k-add-support-for-qca8327-switch.patch deleted file mode 100644 index 72305850ca..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-09-net-dsa-qca8k-add-support-for-qca8327-switch.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 6e82a457e06252b59102486767539cc9c2aba60b Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 22:59:59 +0200 -Subject: [PATCH] net: dsa: qca8k: add support for qca8327 switch - -qca8327 switch is a low tier version of the more recent qca8337. -It does share the same regs used by the qca8k driver and can be -supported with minimal change. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Reviewed-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++--- - drivers/net/dsa/qca8k.h | 6 ++++++ - 2 files changed, 26 insertions(+), 3 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1533,6 +1533,7 @@ static const struct dsa_switch_ops qca8k - static int - qca8k_sw_probe(struct mdio_device *mdiodev) - { -+ const struct qca8k_match_data *data; - struct qca8k_priv *priv; - u32 id; - -@@ -1560,6 +1561,11 @@ qca8k_sw_probe(struct mdio_device *mdiod - gpiod_set_value_cansleep(priv->reset_gpio, 0); - } - -+ /* get the switches ID from the compatible */ -+ data = of_device_get_match_data(&mdiodev->dev); -+ if (!data) -+ return -ENODEV; -+ - /* read the switches ID register */ - id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); - if (id < 0) -@@ -1567,8 +1573,10 @@ qca8k_sw_probe(struct mdio_device *mdiod - - id >>= QCA8K_MASK_CTRL_ID_S; - id &= QCA8K_MASK_CTRL_ID_M; -- if (id != QCA8K_ID_QCA8337) -+ if (id != data->id) { -+ dev_err(&mdiodev->dev, "Switch id detected %x but expected %x", id, data->id); - return -ENODEV; -+ } - - priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); - if (!priv->ds) -@@ -1634,9 +1642,18 @@ static int qca8k_resume(struct device *d - static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, - qca8k_suspend, qca8k_resume); - -+static const struct qca8k_match_data qca832x = { -+ .id = QCA8K_ID_QCA8327, -+}; -+ -+static const struct qca8k_match_data qca833x = { -+ .id = QCA8K_ID_QCA8337, -+}; -+ - static const struct of_device_id qca8k_of_match[] = { -- { .compatible = "qca,qca8334" }, -- { .compatible = "qca,qca8337" }, -+ { .compatible = "qca,qca8327", .data = &qca832x }, -+ { .compatible = "qca,qca8334", .data = &qca833x }, -+ { .compatible = "qca,qca8337", .data = &qca833x }, - { /* sentinel */ }, - }; - ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -15,6 +15,8 @@ - #define QCA8K_NUM_PORTS 7 - #define QCA8K_MAX_MTU 9000 - -+#define PHY_ID_QCA8327 0x004dd034 -+#define QCA8K_ID_QCA8327 0x12 - #define PHY_ID_QCA8337 0x004dd036 - #define QCA8K_ID_QCA8337 0x13 - -@@ -213,6 +215,10 @@ struct ar8xxx_port_status { - int enabled; - }; - -+struct qca8k_match_data { -+ u8 id; -+}; -+ - struct qca8k_priv { - struct regmap *regmap; - struct mii_bus *bus; diff --git a/target/linux/generic/backport-5.10/735-v5.14-10-devicetree-net-dsa-qca8k-Document-new-compatible-qca.patch b/target/linux/generic/backport-5.10/735-v5.14-10-devicetree-net-dsa-qca8k-Document-new-compatible-qca.patch deleted file mode 100644 index 3c4a14bd0b..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-10-devicetree-net-dsa-qca8k-Document-new-compatible-qca.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 227a9ffc1bc77037339530607fe129af3824620e Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:00 +0200 -Subject: [PATCH] devicetree: net: dsa: qca8k: Document new compatible qca8327 - -Add support for qca8327 in the compatible list. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Acked-by: Rob Herring -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - Documentation/devicetree/bindings/net/dsa/qca8k.txt | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt -+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt -@@ -3,6 +3,7 @@ - Required properties: - - - compatible: should be one of: -+ "qca,qca8327" - "qca,qca8334" - "qca,qca8337" - diff --git a/target/linux/generic/backport-5.10/735-v5.14-11-net-dsa-qca8k-add-priority-tweak-to-qca8337-switch.patch b/target/linux/generic/backport-5.10/735-v5.14-11-net-dsa-qca8k-add-priority-tweak-to-qca8337-switch.patch deleted file mode 100644 index cd3050ef71..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-11-net-dsa-qca8k-add-priority-tweak-to-qca8337-switch.patch +++ /dev/null @@ -1,130 +0,0 @@ -From 83a3ceb39b2495171aabe9446271b94c678354f3 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:01 +0200 -Subject: [PATCH] net: dsa: qca8k: add priority tweak to qca8337 switch - -The port 5 of the qca8337 have some problem in flood condition. The -original legacy driver had some specific buffer and priority settings -for the different port suggested by the QCA switch team. Add this -missing settings to improve switch stability under load condition. -The packet priority tweak is only needed for the qca8337 switch and -other qca8k switch are not affected. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 47 +++++++++++++++++++++++++++++++++++++++++ - drivers/net/dsa/qca8k.h | 25 ++++++++++++++++++++++ - 2 files changed, 72 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -779,6 +779,7 @@ qca8k_setup(struct dsa_switch *ds) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - int ret, i; -+ u32 mask; - - /* Make sure that port 0 is the cpu port */ - if (!dsa_is_cpu_port(ds, 0)) { -@@ -884,6 +885,51 @@ qca8k_setup(struct dsa_switch *ds) - } - } - -+ /* The port 5 of the qca8337 have some problem in flood condition. The -+ * original legacy driver had some specific buffer and priority settings -+ * for the different port suggested by the QCA switch team. Add this -+ * missing settings to improve switch stability under load condition. -+ * This problem is limited to qca8337 and other qca8k switch are not affected. -+ */ -+ if (priv->switch_id == QCA8K_ID_QCA8337) { -+ for (i = 0; i < QCA8K_NUM_PORTS; i++) { -+ switch (i) { -+ /* The 2 CPU port and port 5 requires some different -+ * priority than any other ports. -+ */ -+ case 0: -+ case 5: -+ case 6: -+ mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | -+ QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | -+ QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | -+ QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | -+ QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | -+ QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | -+ QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); -+ break; -+ default: -+ mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | -+ QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | -+ QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | -+ QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | -+ QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); -+ } -+ qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); -+ -+ mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | -+ QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | -+ QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | -+ QCA8K_PORT_HOL_CTRL1_WRED_EN; -+ qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), -+ QCA8K_PORT_HOL_CTRL1_ING_BUF | -+ QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | -+ QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | -+ QCA8K_PORT_HOL_CTRL1_WRED_EN, -+ mask); -+ } -+ } -+ - /* Setup our port MTUs to match power on defaults */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) - priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; -@@ -1578,6 +1624,7 @@ qca8k_sw_probe(struct mdio_device *mdiod - return -ENODEV; - } - -+ priv->switch_id = id; - priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); - if (!priv->ds) - return -ENOMEM; ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -168,6 +168,30 @@ - #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) - #define QCA8K_PORT_LOOKUP_LEARN BIT(20) - -+#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20) -+#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24) -+#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24) -+ -+#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) -+#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0) -+#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0) -+#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) -+#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) -+#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8) -+#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) -+ - /* Pkt edit registers */ - #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) - -@@ -220,6 +244,7 @@ struct qca8k_match_data { - }; - - struct qca8k_priv { -+ u8 switch_id; - struct regmap *regmap; - struct mii_bus *bus; - struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; diff --git a/target/linux/generic/backport-5.10/735-v5.14-12-net-dsa-qca8k-limit-port5-delay-to-qca8337.patch b/target/linux/generic/backport-5.10/735-v5.14-12-net-dsa-qca8k-limit-port5-delay-to-qca8337.patch deleted file mode 100644 index d25edbb1aa..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-12-net-dsa-qca8k-limit-port5-delay-to-qca8337.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 5bf9ff3b9fb5ecb67a1a3517b26db3a00f2a2f11 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:02 +0200 -Subject: [PATCH] net: dsa: qca8k: limit port5 delay to qca8337 - -Limit port5 rx delay to qca8337. This is taken from the legacy QSDK code -that limits the rx delay on port5 to only this particular switch version, -on other switch only the tx and rx delay for port0 are needed. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1003,8 +1003,10 @@ qca8k_phylink_mac_config(struct dsa_swit - QCA8K_PORT_PAD_RGMII_EN | - QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) | - QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY)); -- qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, -- QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); -+ /* QCA8337 requires to set rgmii rx delay */ -+ if (priv->switch_id == QCA8K_ID_QCA8337) -+ qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, -+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); - break; - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_1000BASEX: diff --git a/target/linux/generic/backport-5.10/735-v5.14-13-net-dsa-qca8k-add-GLOBAL_FC-settings-needed-for-qca8.patch b/target/linux/generic/backport-5.10/735-v5.14-13-net-dsa-qca8k-add-GLOBAL_FC-settings-needed-for-qca8.patch deleted file mode 100644 index 2b393d242a..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-13-net-dsa-qca8k-add-GLOBAL_FC-settings-needed-for-qca8.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 0fc57e4b5e39461fc0a54aae0afe4241363a7267 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:03 +0200 -Subject: [PATCH] net: dsa: qca8k: add GLOBAL_FC settings needed for qca8327 - -Switch qca8327 needs special settings for the GLOBAL_FC_THRES regs. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 10 ++++++++++ - drivers/net/dsa/qca8k.h | 6 ++++++ - 2 files changed, 16 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -930,6 +930,16 @@ qca8k_setup(struct dsa_switch *ds) - } - } - -+ /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */ -+ if (priv->switch_id == QCA8K_ID_QCA8327) { -+ mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) | -+ QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496); -+ qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH, -+ QCA8K_GLOBAL_FC_GOL_XON_THRES_S | -+ QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S, -+ mask); -+ } -+ - /* Setup our port MTUs to match power on defaults */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) - priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -168,6 +168,12 @@ - #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) - #define QCA8K_PORT_LOOKUP_LEARN BIT(20) - -+#define QCA8K_REG_GLOBAL_FC_THRESH 0x800 -+#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16) -+#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16) -+#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0) -+#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0) -+ - #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) - #define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) - #define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) diff --git a/target/linux/generic/backport-5.10/735-v5.14-14-net-dsa-qca8k-add-support-for-switch-rev.patch b/target/linux/generic/backport-5.10/735-v5.14-14-net-dsa-qca8k-add-support-for-switch-rev.patch deleted file mode 100644 index ed9b8188de..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-14-net-dsa-qca8k-add-support-for-switch-rev.patch +++ /dev/null @@ -1,114 +0,0 @@ -From 95ffeaf18b3bb90eeef52cbf7d79ccc9d0345ff5 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:04 +0200 -Subject: [PATCH] net: dsa: qca8k: add support for switch rev - -qca8k internal phy driver require some special debug value to be set -based on the switch revision. Rework the switch id read function to -also read the chip revision. - -Signed-off-by: Ansuel Smith -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 53 ++++++++++++++++++++++++++--------------- - drivers/net/dsa/qca8k.h | 7 ++++-- - 2 files changed, 39 insertions(+), 21 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1588,12 +1588,40 @@ static const struct dsa_switch_ops qca8k - .phylink_mac_link_up = qca8k_phylink_mac_link_up, - }; - -+static int qca8k_read_switch_id(struct qca8k_priv *priv) -+{ -+ const struct qca8k_match_data *data; -+ u32 val; -+ u8 id; -+ -+ /* get the switches ID from the compatible */ -+ data = of_device_get_match_data(priv->dev); -+ if (!data) -+ return -ENODEV; -+ -+ val = qca8k_read(priv, QCA8K_REG_MASK_CTRL); -+ if (val < 0) -+ return -ENODEV; -+ -+ id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK); -+ if (id != data->id) { -+ dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id); -+ return -ENODEV; -+ } -+ -+ priv->switch_id = id; -+ -+ /* Save revision to communicate to the internal PHY driver */ -+ priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK); -+ -+ return 0; -+} -+ - static int - qca8k_sw_probe(struct mdio_device *mdiodev) - { -- const struct qca8k_match_data *data; - struct qca8k_priv *priv; -- u32 id; -+ int ret; - - /* allocate the private data struct so that we can probe the switches - * ID register -@@ -1619,24 +1647,11 @@ qca8k_sw_probe(struct mdio_device *mdiod - gpiod_set_value_cansleep(priv->reset_gpio, 0); - } - -- /* get the switches ID from the compatible */ -- data = of_device_get_match_data(&mdiodev->dev); -- if (!data) -- return -ENODEV; -+ /* Check the detected switch id */ -+ ret = qca8k_read_switch_id(priv); -+ if (ret) -+ return ret; - -- /* read the switches ID register */ -- id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); -- if (id < 0) -- return id; -- -- id >>= QCA8K_MASK_CTRL_ID_S; -- id &= QCA8K_MASK_CTRL_ID_M; -- if (id != data->id) { -- dev_err(&mdiodev->dev, "Switch id detected %x but expected %x", id, data->id); -- return -ENODEV; -- } -- -- priv->switch_id = id; - priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); - if (!priv->ds) - return -ENOMEM; ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -30,8 +30,10 @@ - - /* Global control registers */ - #define QCA8K_REG_MASK_CTRL 0x000 --#define QCA8K_MASK_CTRL_ID_M 0xff --#define QCA8K_MASK_CTRL_ID_S 8 -+#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0) -+#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0) -+#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) -+#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) - #define QCA8K_REG_PORT0_PAD_CTRL 0x004 - #define QCA8K_REG_PORT5_PAD_CTRL 0x008 - #define QCA8K_REG_PORT6_PAD_CTRL 0x00c -@@ -251,6 +253,7 @@ struct qca8k_match_data { - - struct qca8k_priv { - u8 switch_id; -+ u8 switch_revision; - struct regmap *regmap; - struct mii_bus *bus; - struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; diff --git a/target/linux/generic/backport-5.10/735-v5.14-15-net-dsa-qca8k-add-ethernet-ports-fallback-to-setup_m.patch b/target/linux/generic/backport-5.10/735-v5.14-15-net-dsa-qca8k-add-ethernet-ports-fallback-to-setup_m.patch deleted file mode 100644 index 629cb324e0..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-15-net-dsa-qca8k-add-ethernet-ports-fallback-to-setup_m.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 1ee0591a1093c2448642c33433483e9260275f7b Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:05 +0200 -Subject: [PATCH] net: dsa: qca8k: add ethernet-ports fallback to - setup_mdio_bus - -Dsa now also supports ethernet-ports. Add this new binding as a fallback -if the ports node can't be found. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -719,6 +719,9 @@ qca8k_setup_mdio_bus(struct qca8k_priv * - - ports = of_get_child_by_name(priv->dev->of_node, "ports"); - if (!ports) -+ ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports"); -+ -+ if (!ports) - return -EINVAL; - - for_each_available_child_of_node(ports, port) { diff --git a/target/linux/generic/backport-5.10/735-v5.14-16-net-dsa-qca8k-make-rgmii-delay-configurable.patch b/target/linux/generic/backport-5.10/735-v5.14-16-net-dsa-qca8k-make-rgmii-delay-configurable.patch deleted file mode 100644 index 6dc2dc6e3e..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-16-net-dsa-qca8k-make-rgmii-delay-configurable.patch +++ /dev/null @@ -1,188 +0,0 @@ -From e4b9977cee1583da38a6e9118078bb728aaccf7b Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:06 +0200 -Subject: [PATCH] net: dsa: qca8k: make rgmii delay configurable - -The legacy qsdk code used a different delay instead of the max value. -Qsdk use 1 ns for rx and 2 ns for tx. Make these values configurable -using the standard rx/tx-internal-delay-ps ethernet binding and apply -qsdk values by default. The connected gmac doesn't add any delay so no -additional delay is added to tx/rx. -On this switch the delay is actually in ns so value should be in the -1000 order. Any value converted from ps to ns by dividing it by 1000 -as the switch max value for delay is 3ns. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 82 ++++++++++++++++++++++++++++++++++++++++- - drivers/net/dsa/qca8k.h | 11 +++--- - 2 files changed, 86 insertions(+), 7 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -778,6 +778,68 @@ qca8k_setup_mdio_bus(struct qca8k_priv * - } - - static int -+qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) -+{ -+ struct device_node *port_dn; -+ phy_interface_t mode; -+ struct dsa_port *dp; -+ u32 val; -+ -+ /* CPU port is already checked */ -+ dp = dsa_to_port(priv->ds, 0); -+ -+ port_dn = dp->dn; -+ -+ /* Check if port 0 is set to the correct type */ -+ of_get_phy_mode(port_dn, &mode); -+ if (mode != PHY_INTERFACE_MODE_RGMII_ID && -+ mode != PHY_INTERFACE_MODE_RGMII_RXID && -+ mode != PHY_INTERFACE_MODE_RGMII_TXID) { -+ return 0; -+ } -+ -+ switch (mode) { -+ case PHY_INTERFACE_MODE_RGMII_ID: -+ case PHY_INTERFACE_MODE_RGMII_RXID: -+ if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val)) -+ val = 2; -+ else -+ /* Switch regs accept value in ns, convert ps to ns */ -+ val = val / 1000; -+ -+ if (val > QCA8K_MAX_DELAY) { -+ dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); -+ val = 3; -+ } -+ -+ priv->rgmii_rx_delay = val; -+ /* Stop here if we need to check only for rx delay */ -+ if (mode != PHY_INTERFACE_MODE_RGMII_ID) -+ break; -+ -+ fallthrough; -+ case PHY_INTERFACE_MODE_RGMII_TXID: -+ if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val)) -+ val = 1; -+ else -+ /* Switch regs accept value in ns, convert ps to ns */ -+ val = val / 1000; -+ -+ if (val > QCA8K_MAX_DELAY) { -+ dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); -+ val = 3; -+ } -+ -+ priv->rgmii_tx_delay = val; -+ break; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static int - qca8k_setup(struct dsa_switch *ds) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; -@@ -802,6 +864,10 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - return ret; - -+ ret = qca8k_setup_of_rgmii_delay(priv); -+ if (ret) -+ return ret; -+ - /* Enable CPU Port */ - ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, - QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); -@@ -970,6 +1036,8 @@ qca8k_phylink_mac_config(struct dsa_swit - case 0: /* 1st CPU port */ - if (state->interface != PHY_INTERFACE_MODE_RGMII && - state->interface != PHY_INTERFACE_MODE_RGMII_ID && -+ state->interface != PHY_INTERFACE_MODE_RGMII_TXID && -+ state->interface != PHY_INTERFACE_MODE_RGMII_RXID && - state->interface != PHY_INTERFACE_MODE_SGMII) - return; - -@@ -985,6 +1053,8 @@ qca8k_phylink_mac_config(struct dsa_swit - case 6: /* 2nd CPU port / external PHY */ - if (state->interface != PHY_INTERFACE_MODE_RGMII && - state->interface != PHY_INTERFACE_MODE_RGMII_ID && -+ state->interface != PHY_INTERFACE_MODE_RGMII_TXID && -+ state->interface != PHY_INTERFACE_MODE_RGMII_RXID && - state->interface != PHY_INTERFACE_MODE_SGMII && - state->interface != PHY_INTERFACE_MODE_1000BASEX) - return; -@@ -1008,14 +1078,18 @@ qca8k_phylink_mac_config(struct dsa_swit - qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN); - break; - case PHY_INTERFACE_MODE_RGMII_ID: -+ case PHY_INTERFACE_MODE_RGMII_TXID: -+ case PHY_INTERFACE_MODE_RGMII_RXID: - /* RGMII_ID needs internal delay. This is enabled through - * PORT5_PAD_CTRL for all ports, rather than individual port - * registers - */ - qca8k_write(priv, reg, - QCA8K_PORT_PAD_RGMII_EN | -- QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) | -- QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY)); -+ QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) | -+ QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) | -+ QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | -+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); - /* QCA8337 requires to set rgmii rx delay */ - if (priv->switch_id == QCA8K_ID_QCA8337) - qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, -@@ -1073,6 +1147,8 @@ qca8k_phylink_validate(struct dsa_switch - if (state->interface != PHY_INTERFACE_MODE_NA && - state->interface != PHY_INTERFACE_MODE_RGMII && - state->interface != PHY_INTERFACE_MODE_RGMII_ID && -+ state->interface != PHY_INTERFACE_MODE_RGMII_TXID && -+ state->interface != PHY_INTERFACE_MODE_RGMII_RXID && - state->interface != PHY_INTERFACE_MODE_SGMII) - goto unsupported; - break; -@@ -1090,6 +1166,8 @@ qca8k_phylink_validate(struct dsa_switch - if (state->interface != PHY_INTERFACE_MODE_NA && - state->interface != PHY_INTERFACE_MODE_RGMII && - state->interface != PHY_INTERFACE_MODE_RGMII_ID && -+ state->interface != PHY_INTERFACE_MODE_RGMII_TXID && -+ state->interface != PHY_INTERFACE_MODE_RGMII_RXID && - state->interface != PHY_INTERFACE_MODE_SGMII && - state->interface != PHY_INTERFACE_MODE_1000BASEX) - goto unsupported; ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -38,12 +38,11 @@ - #define QCA8K_REG_PORT5_PAD_CTRL 0x008 - #define QCA8K_REG_PORT6_PAD_CTRL 0x00c - #define QCA8K_PORT_PAD_RGMII_EN BIT(26) --#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \ -- ((0x8 + (x & 0x3)) << 22) --#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \ -- ((0x10 + (x & 0x3)) << 20) --#define QCA8K_MAX_DELAY 3 -+#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) -+#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) -+#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) - #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) -+#define QCA8K_MAX_DELAY 3 - #define QCA8K_PORT_PAD_SGMII_EN BIT(7) - #define QCA8K_REG_PWS 0x010 - #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) -@@ -254,6 +253,8 @@ struct qca8k_match_data { - struct qca8k_priv { - u8 switch_id; - u8 switch_revision; -+ u8 rgmii_tx_delay; -+ u8 rgmii_rx_delay; - struct regmap *regmap; - struct mii_bus *bus; - struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; diff --git a/target/linux/generic/backport-5.10/735-v5.14-17-net-dsa-qca8k-clear-MASTER_EN-after-phy-read-write.patch b/target/linux/generic/backport-5.10/735-v5.14-17-net-dsa-qca8k-clear-MASTER_EN-after-phy-read-write.patch deleted file mode 100644 index 4593da032b..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-17-net-dsa-qca8k-clear-MASTER_EN-after-phy-read-write.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 63c33bbfeb6842a956a0eb12901e28eb335bdb18 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:07 +0200 -Subject: [PATCH] net: dsa: qca8k: clear MASTER_EN after phy read/write - -Clear MDIO_MASTER_EN bit from MDIO_MASTER_CTRL after read/write -operation. The MDIO_MASTER_EN bit is not reset after read/write -operation and the next operation can be wrongly interpreted by the -switch as a mdio operation. This cause a production of wrong/garbage -data from the switch and underfined bheavior. (random port drop, -unplugged port flagged with link up, wrong port speed) -Also on driver remove the MASTER_CTRL can be left set and cause the -malfunction of any next driver using the mdio device. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 14 ++++++++++++-- - 1 file changed, 12 insertions(+), 2 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -649,8 +649,14 @@ qca8k_mdio_write(struct qca8k_priv *priv - if (ret) - return ret; - -- return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -- QCA8K_MDIO_MASTER_BUSY); -+ ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -+ QCA8K_MDIO_MASTER_BUSY); -+ -+ /* even if the busy_wait timeouts try to clear the MASTER_EN */ -+ qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, -+ QCA8K_MDIO_MASTER_EN); -+ -+ return ret; - } - - static int -@@ -685,6 +691,10 @@ qca8k_mdio_read(struct qca8k_priv *priv, - - val &= QCA8K_MDIO_MASTER_DATA_MASK; - -+ /* even if the busy_wait timeouts try to clear the MASTER_EN */ -+ qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, -+ QCA8K_MDIO_MASTER_EN); -+ - return val; - } - diff --git a/target/linux/generic/backport-5.10/735-v5.14-18-net-dsa-qca8k-dsa-qca8k-protect-MASTER-busy_wait-wit.patch b/target/linux/generic/backport-5.10/735-v5.14-18-net-dsa-qca8k-dsa-qca8k-protect-MASTER-busy_wait-wit.patch deleted file mode 100644 index b6684d7210..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-18-net-dsa-qca8k-dsa-qca8k-protect-MASTER-busy_wait-wit.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 60df02b6ea4581d72eb7a3ab7204504a54059b72 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:08 +0200 -Subject: [PATCH] net: dsa: qca8k: dsa: qca8k: protect MASTER busy_wait with - mdio mutex - -MDIO_MASTER operation have a dedicated busy wait that is not protected -by the mdio mutex. This can cause situation where the MASTER operation -is done and a normal operation is executed between the MASTER read/write -and the MASTER busy_wait. Rework the qca8k_mdio_read/write function to -address this issue by binding the lock for the whole MASTER operation -and not only the mdio read/write common operation. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 68 +++++++++++++++++++++++++++++++++-------- - 1 file changed, 55 insertions(+), 13 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -628,8 +628,31 @@ qca8k_port_to_phy(int port) - } - - static int -+qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) -+{ -+ u16 r1, r2, page; -+ u32 val; -+ int ret; -+ -+ qca8k_split_addr(reg, &r1, &r2, &page); -+ -+ ret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0, -+ QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, -+ priv->bus, 0x10 | r2, r1); -+ -+ /* Check if qca8k_read has failed for a different reason -+ * before returnting -ETIMEDOUT -+ */ -+ if (ret < 0 && val < 0) -+ return val; -+ -+ return ret; -+} -+ -+static int - qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) - { -+ u16 r1, r2, page; - u32 phy, val; - int ret; - -@@ -645,12 +668,21 @@ qca8k_mdio_write(struct qca8k_priv *priv - QCA8K_MDIO_MASTER_REG_ADDR(regnum) | - QCA8K_MDIO_MASTER_DATA(data); - -- ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); -+ qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); -+ -+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); -+ -+ ret = qca8k_set_page(priv->bus, page); - if (ret) -- return ret; -+ goto exit; -+ -+ qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); - -- ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -- QCA8K_MDIO_MASTER_BUSY); -+ ret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -+ QCA8K_MDIO_MASTER_BUSY); -+ -+exit: -+ mutex_unlock(&priv->bus->mdio_lock); - - /* even if the busy_wait timeouts try to clear the MASTER_EN */ - qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, -@@ -662,6 +694,7 @@ qca8k_mdio_write(struct qca8k_priv *priv - static int - qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) - { -+ u16 r1, r2, page; - u32 phy, val; - int ret; - -@@ -676,21 +709,30 @@ qca8k_mdio_read(struct qca8k_priv *priv, - QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | - QCA8K_MDIO_MASTER_REG_ADDR(regnum); - -- ret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); -- if (ret) -- return ret; -+ qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); -+ -+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); - -- ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -- QCA8K_MDIO_MASTER_BUSY); -+ ret = qca8k_set_page(priv->bus, page); - if (ret) -- return ret; -+ goto exit; - -- val = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL); -- if (val < 0) -- return val; -+ qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); -+ -+ ret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -+ QCA8K_MDIO_MASTER_BUSY); -+ if (ret) -+ goto exit; - -+ val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); - val &= QCA8K_MDIO_MASTER_DATA_MASK; - -+exit: -+ mutex_unlock(&priv->bus->mdio_lock); -+ -+ if (val >= 0) -+ val &= QCA8K_MDIO_MASTER_DATA_MASK; -+ - /* even if the busy_wait timeouts try to clear the MASTER_EN */ - qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_EN); diff --git a/target/linux/generic/backport-5.10/735-v5.14-19-net-dsa-qca8k-enlarge-mdio-delay-and-timeout.patch b/target/linux/generic/backport-5.10/735-v5.14-19-net-dsa-qca8k-enlarge-mdio-delay-and-timeout.patch deleted file mode 100644 index 30eeed361e..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-19-net-dsa-qca8k-enlarge-mdio-delay-and-timeout.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 617960d72e93de0f3fa52407e2d39e8c43e73b0a Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:09 +0200 -Subject: [PATCH] net: dsa: qca8k: enlarge mdio delay and timeout - -The witch require some extra delay after setting page or the next -read/write can use still use the old page. Add a delay after the -set_page function to address this as it's done in QSDK legacy driver. -Some timeouts were notice with VLAN and phy function, enlarge the -mdio busy wait timeout to fix these problems. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 1 + - drivers/net/dsa/qca8k.h | 2 +- - 2 files changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -143,6 +143,7 @@ qca8k_set_page(struct mii_bus *bus, u16 - } - - qca8k_current_page = page; -+ usleep_range(1000, 2000); - return 0; - } - ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -20,7 +20,7 @@ - #define PHY_ID_QCA8337 0x004dd036 - #define QCA8K_ID_QCA8337 0x13 - --#define QCA8K_BUSY_WAIT_TIMEOUT 20 -+#define QCA8K_BUSY_WAIT_TIMEOUT 2000 - - #define QCA8K_NUM_FDB_RECORDS 2048 - diff --git a/target/linux/generic/backport-5.10/735-v5.14-20-net-dsa-qca8k-add-support-for-internal-phy-and-inter.patch b/target/linux/generic/backport-5.10/735-v5.14-20-net-dsa-qca8k-add-support-for-internal-phy-and-inter.patch deleted file mode 100644 index 88d3c1ef43..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-20-net-dsa-qca8k-add-support-for-internal-phy-and-inter.patch +++ /dev/null @@ -1,267 +0,0 @@ -From 759bafb8a3226326ca357613bc90acf738f80c32 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:10 +0200 -Subject: [PATCH] net: dsa: qca8k: add support for internal phy and internal - mdio - -Add support to setup_mdio_bus for internal phy declaration. Introduce a -flag to use the legacy port phy mapping by default and use the direct -mapping if a mdio node is detected in the switch node. Register a -dedicated mdio internal mdio bus to address the different mapping -between port and phy if the mdio node is detected. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 112 +++++++++++++++++++++++++++++----------- - drivers/net/dsa/qca8k.h | 1 + - 2 files changed, 83 insertions(+), 30 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -629,7 +630,7 @@ qca8k_port_to_phy(int port) - } - - static int --qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) -+qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask) - { - u16 r1, r2, page; - u32 val; -@@ -639,7 +640,7 @@ qca8k_mdio_busy_wait(struct qca8k_priv * - - ret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0, - QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, -- priv->bus, 0x10 | r2, r1); -+ bus, 0x10 | r2, r1); - - /* Check if qca8k_read has failed for a different reason - * before returnting -ETIMEDOUT -@@ -651,19 +652,16 @@ qca8k_mdio_busy_wait(struct qca8k_priv * - } - - static int --qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) -+qca8k_mdio_write(struct mii_bus *salve_bus, int phy, int regnum, u16 data) - { -+ struct qca8k_priv *priv = salve_bus->priv; - u16 r1, r2, page; -- u32 phy, val; -+ u32 val; - int ret; - - if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) - return -EINVAL; - -- /* callee is responsible for not passing bad ports, -- * but we still would like to make spills impossible. -- */ -- phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; - val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | - QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | - QCA8K_MDIO_MASTER_REG_ADDR(regnum) | -@@ -679,33 +677,29 @@ qca8k_mdio_write(struct qca8k_priv *priv - - qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); - -- ret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -+ ret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); - - exit: -- mutex_unlock(&priv->bus->mdio_lock); -- - /* even if the busy_wait timeouts try to clear the MASTER_EN */ -- qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, -- QCA8K_MDIO_MASTER_EN); -+ qca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0); -+ -+ mutex_unlock(&priv->bus->mdio_lock); - - return ret; - } - - static int --qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) -+qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum) - { -+ struct qca8k_priv *priv = salve_bus->priv; - u16 r1, r2, page; -- u32 phy, val; -+ u32 val; - int ret; - - if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) - return -EINVAL; - -- /* callee is responsible for not passing bad ports, -- * but we still would like to make spills impossible. -- */ -- phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; - val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | - QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | - QCA8K_MDIO_MASTER_REG_ADDR(regnum); -@@ -720,24 +714,22 @@ qca8k_mdio_read(struct qca8k_priv *priv, - - qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); - -- ret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, -+ ret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); - if (ret) - goto exit; - - val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); -- val &= QCA8K_MDIO_MASTER_DATA_MASK; - - exit: -+ /* even if the busy_wait timeouts try to clear the MASTER_EN */ -+ qca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0); -+ - mutex_unlock(&priv->bus->mdio_lock); - - if (val >= 0) - val &= QCA8K_MDIO_MASTER_DATA_MASK; - -- /* even if the busy_wait timeouts try to clear the MASTER_EN */ -- qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, -- QCA8K_MDIO_MASTER_EN); -- - return val; - } - -@@ -746,7 +738,14 @@ qca8k_phy_write(struct dsa_switch *ds, i - { - struct qca8k_priv *priv = ds->priv; - -- return qca8k_mdio_write(priv, port, regnum, data); -+ /* Check if the legacy mapping should be used and the -+ * port is not correctly mapped to the right PHY in the -+ * devicetree -+ */ -+ if (priv->legacy_phy_port_mapping) -+ port = qca8k_port_to_phy(port) % PHY_MAX_ADDR; -+ -+ return qca8k_mdio_write(priv->bus, port, regnum, data); - } - - static int -@@ -755,7 +754,14 @@ qca8k_phy_read(struct dsa_switch *ds, in - struct qca8k_priv *priv = ds->priv; - int ret; - -- ret = qca8k_mdio_read(priv, port, regnum); -+ /* Check if the legacy mapping should be used and the -+ * port is not correctly mapped to the right PHY in the -+ * devicetree -+ */ -+ if (priv->legacy_phy_port_mapping) -+ port = qca8k_port_to_phy(port) % PHY_MAX_ADDR; -+ -+ ret = qca8k_mdio_read(priv->bus, port, regnum); - - if (ret < 0) - return 0xffff; -@@ -764,10 +770,37 @@ qca8k_phy_read(struct dsa_switch *ds, in - } - - static int -+qca8k_mdio_register(struct qca8k_priv *priv, struct device_node *mdio) -+{ -+ struct dsa_switch *ds = priv->ds; -+ struct mii_bus *bus; -+ -+ bus = devm_mdiobus_alloc(ds->dev); -+ -+ if (!bus) -+ return -ENOMEM; -+ -+ bus->priv = (void *)priv; -+ bus->name = "qca8k slave mii"; -+ bus->read = qca8k_mdio_read; -+ bus->write = qca8k_mdio_write; -+ snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d", -+ ds->index); -+ -+ bus->parent = ds->dev; -+ bus->phy_mask = ~ds->phys_mii_mask; -+ -+ ds->slave_mii_bus = bus; -+ -+ return devm_of_mdiobus_register(priv->dev, bus, mdio); -+} -+ -+static int - qca8k_setup_mdio_bus(struct qca8k_priv *priv) - { - u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg; -- struct device_node *ports, *port; -+ struct device_node *ports, *port, *mdio; -+ phy_interface_t mode; - int err; - - ports = of_get_child_by_name(priv->dev->of_node, "ports"); -@@ -788,7 +821,10 @@ qca8k_setup_mdio_bus(struct qca8k_priv * - if (!dsa_is_user_port(priv->ds, reg)) - continue; - -- if (of_property_read_bool(port, "phy-handle")) -+ of_get_phy_mode(port, &mode); -+ -+ if (of_property_read_bool(port, "phy-handle") && -+ mode != PHY_INTERFACE_MODE_INTERNAL) - external_mdio_mask |= BIT(reg); - else - internal_mdio_mask |= BIT(reg); -@@ -825,8 +861,23 @@ qca8k_setup_mdio_bus(struct qca8k_priv * - QCA8K_MDIO_MASTER_EN); - } - -+ /* Check if the devicetree declare the port:phy mapping */ -+ mdio = of_get_child_by_name(priv->dev->of_node, "mdio"); -+ if (of_device_is_available(mdio)) { -+ err = qca8k_mdio_register(priv, mdio); -+ if (err) -+ of_node_put(mdio); -+ -+ return err; -+ } -+ -+ /* If a mapping can't be found the legacy mapping is used, -+ * using the qca8k_port_to_phy function -+ */ -+ priv->legacy_phy_port_mapping = true; - priv->ops.phy_read = qca8k_phy_read; - priv->ops.phy_write = qca8k_phy_write; -+ - return 0; - } - -@@ -1212,7 +1263,8 @@ qca8k_phylink_validate(struct dsa_switch - case 5: - /* Internal PHY */ - if (state->interface != PHY_INTERFACE_MODE_NA && -- state->interface != PHY_INTERFACE_MODE_GMII) -+ state->interface != PHY_INTERFACE_MODE_GMII && -+ state->interface != PHY_INTERFACE_MODE_INTERNAL) - goto unsupported; - break; - case 6: /* 2nd CPU port / external PHY */ ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -255,6 +255,7 @@ struct qca8k_priv { - u8 switch_revision; - u8 rgmii_tx_delay; - u8 rgmii_rx_delay; -+ bool legacy_phy_port_mapping; - struct regmap *regmap; - struct mii_bus *bus; - struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; diff --git a/target/linux/generic/backport-5.10/735-v5.14-21-devicetree-bindings-dsa-qca8k-Document-internal-mdio.patch b/target/linux/generic/backport-5.10/735-v5.14-21-devicetree-bindings-dsa-qca8k-Document-internal-mdio.patch deleted file mode 100644 index 6db01b4b41..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-21-devicetree-bindings-dsa-qca8k-Document-internal-mdio.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 0c994a28e7518f098c84a3049cb2915780db873a Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:11 +0200 -Subject: [PATCH] devicetree: bindings: dsa: qca8k: Document internal mdio - definition - -Document new way of declare mapping of internal PHY to port. -The new implementation directly declare the PHY connected to the port -by adding a node in the switch node. The driver detect this and register -an internal mdiobus using the mapping defined in the mdio node. - -Signed-off-by: Ansuel Smith -Reviewed-by: Rob Herring -Signed-off-by: David S. Miller ---- - .../devicetree/bindings/net/dsa/qca8k.txt | 39 +++++++++++++++++++ - 1 file changed, 39 insertions(+) - ---- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt -+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt -@@ -21,6 +21,10 @@ described in dsa/dsa.txt. If the QCA8K s - mdio-bus each subnode describing a port needs to have a valid phandle - referencing the internal PHY it is connected to. This is because there's no - N:N mapping of port and PHY id. -+To declare the internal mdio-bus configuration, declare a mdio node in the -+switch node and declare the phandle for the port referencing the internal -+PHY is connected to. In this config a internal mdio-bus is registered and -+the mdio MASTER is used as communication. - - Don't use mixed external and internal mdio-bus configurations, as this is - not supported by the hardware. -@@ -150,26 +154,61 @@ for the internal master mdio-bus configu - port@1 { - reg = <1>; - label = "lan1"; -+ phy-mode = "internal"; -+ phy-handle = <&phy_port1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; -+ phy-mode = "internal"; -+ phy-handle = <&phy_port2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; -+ phy-mode = "internal"; -+ phy-handle = <&phy_port3>; - }; - - port@4 { - reg = <4>; - label = "lan4"; -+ phy-mode = "internal"; -+ phy-handle = <&phy_port4>; - }; - - port@5 { - reg = <5>; - label = "wan"; -+ phy-mode = "internal"; -+ phy-handle = <&phy_port5>; -+ }; -+ }; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ phy_port1: phy@0 { -+ reg = <0>; -+ }; -+ -+ phy_port2: phy@1 { -+ reg = <1>; -+ }; -+ -+ phy_port3: phy@2 { -+ reg = <2>; -+ }; -+ -+ phy_port4: phy@3 { -+ reg = <3>; -+ }; -+ -+ phy_port5: phy@4 { -+ reg = <4>; - }; - }; - }; diff --git a/target/linux/generic/backport-5.10/735-v5.14-22-net-dsa-qca8k-improve-internal-mdio-read-write-bus-a.patch b/target/linux/generic/backport-5.10/735-v5.14-22-net-dsa-qca8k-improve-internal-mdio-read-write-bus-a.patch deleted file mode 100644 index da8d5b3462..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-22-net-dsa-qca8k-improve-internal-mdio-read-write-bus-a.patch +++ /dev/null @@ -1,95 +0,0 @@ -From b7ebac354d54f1657bb89b7a7ca149db50203e6a Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:12 +0200 -Subject: [PATCH] net: dsa: qca8k: improve internal mdio read/write bus access - -Improve the internal mdio read/write bus access by caching the value -without accessing it for every read/write. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 28 +++++++++++++++------------- - 1 file changed, 15 insertions(+), 13 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -655,6 +655,7 @@ static int - qca8k_mdio_write(struct mii_bus *salve_bus, int phy, int regnum, u16 data) - { - struct qca8k_priv *priv = salve_bus->priv; -+ struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - u32 val; - int ret; -@@ -669,22 +670,22 @@ qca8k_mdio_write(struct mii_bus *salve_b - - qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); - -- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); -+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - -- ret = qca8k_set_page(priv->bus, page); -+ ret = qca8k_set_page(bus, page); - if (ret) - goto exit; - -- qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); -+ qca8k_mii_write32(bus, 0x10 | r2, r1, val); - -- ret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL, -+ ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); - - exit: - /* even if the busy_wait timeouts try to clear the MASTER_EN */ -- qca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0); -+ qca8k_mii_write32(bus, 0x10 | r2, r1, 0); - -- mutex_unlock(&priv->bus->mdio_lock); -+ mutex_unlock(&bus->mdio_lock); - - return ret; - } -@@ -693,6 +694,7 @@ static int - qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum) - { - struct qca8k_priv *priv = salve_bus->priv; -+ struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - u32 val; - int ret; -@@ -706,26 +708,26 @@ qca8k_mdio_read(struct mii_bus *salve_bu - - qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); - -- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); -+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - -- ret = qca8k_set_page(priv->bus, page); -+ ret = qca8k_set_page(bus, page); - if (ret) - goto exit; - -- qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); -+ qca8k_mii_write32(bus, 0x10 | r2, r1, val); - -- ret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL, -+ ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); - if (ret) - goto exit; - -- val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); -+ val = qca8k_mii_read32(bus, 0x10 | r2, r1); - - exit: - /* even if the busy_wait timeouts try to clear the MASTER_EN */ -- qca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0); -+ qca8k_mii_write32(bus, 0x10 | r2, r1, 0); - -- mutex_unlock(&priv->bus->mdio_lock); -+ mutex_unlock(&bus->mdio_lock); - - if (val >= 0) - val &= QCA8K_MDIO_MASTER_DATA_MASK; diff --git a/target/linux/generic/backport-5.10/735-v5.14-23-net-dsa-qca8k-pass-switch_revision-info-to-phy-dev_f.patch b/target/linux/generic/backport-5.10/735-v5.14-23-net-dsa-qca8k-pass-switch_revision-info-to-phy-dev_f.patch deleted file mode 100644 index 1179cf152d..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-23-net-dsa-qca8k-pass-switch_revision-info-to-phy-dev_f.patch +++ /dev/null @@ -1,48 +0,0 @@ -From a46aec02bc06ac2c33f326339e4ef88c735dc30d Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:13 +0200 -Subject: [PATCH] net: dsa: qca8k: pass switch_revision info to phy dev_flags - -Define get_phy_flags to pass switch_Revision needed to tweak the -internal PHY with debug values based on the revision. - -Signed-off-by: Ansuel Smith -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1740,6 +1740,22 @@ qca8k_port_vlan_del(struct dsa_switch *d - return ret; - } - -+static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port) -+{ -+ struct qca8k_priv *priv = ds->priv; -+ -+ /* Communicate to the phy internal driver the switch revision. -+ * Based on the switch revision different values needs to be -+ * set to the dbg and mmd reg on the phy. -+ * The first 2 bit are used to communicate the switch revision -+ * to the phy driver. -+ */ -+ if (port > 0 && port < 6) -+ return priv->switch_revision; -+ -+ return 0; -+} -+ - static enum dsa_tag_protocol - qca8k_get_tag_protocol(struct dsa_switch *ds, int port, - enum dsa_tag_protocol mp) -@@ -1774,6 +1790,7 @@ static const struct dsa_switch_ops qca8k - .phylink_mac_config = qca8k_phylink_mac_config, - .phylink_mac_link_down = qca8k_phylink_mac_link_down, - .phylink_mac_link_up = qca8k_phylink_mac_link_up, -+ .get_phy_flags = qca8k_get_phy_flags, - }; - - static int qca8k_read_switch_id(struct qca8k_priv *priv) diff --git a/target/linux/generic/backport-5.10/735-v5.14-25-net-phy-add-support-for-qca8k-switch-internal-PHY-in.patch b/target/linux/generic/backport-5.10/735-v5.14-25-net-phy-add-support-for-qca8k-switch-internal-PHY-in.patch deleted file mode 100644 index 0b03c78bdc..0000000000 --- a/target/linux/generic/backport-5.10/735-v5.14-25-net-phy-add-support-for-qca8k-switch-internal-PHY-in.patch +++ /dev/null @@ -1,229 +0,0 @@ -From 272833b9b3b3969be7a91839121d86662c8c4253 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 14 May 2021 23:00:15 +0200 -Subject: [PATCH] net: phy: add support for qca8k switch internal PHY in at803x - -Since the at803x share the same regs, it's assumed they are based on the -same implementation. Make it part of the at803x PHY driver to skip -having redudant code. -Add initial support for qca8k internal PHYs. The internal PHYs requires -special mmd and debug values to be set based on the switch revision -passwd using the dev_flags. Supports output of idle, receive and eee_wake -errors stats. -Some debug values sets can't be translated as the documentation lacks any -reference about them. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/phy/Kconfig | 5 +- - drivers/net/phy/at803x.c | 132 ++++++++++++++++++++++++++++++++++++++- - 2 files changed, 134 insertions(+), 3 deletions(-) - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -235,10 +235,11 @@ config NXP_TJA11XX_PHY - Currently supports the NXP TJA1100 and TJA1101 PHY. - - config AT803X_PHY -- tristate "Qualcomm Atheros AR803X PHYs" -+ tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs" - depends on REGULATOR - help -- Currently supports the AR8030, AR8031, AR8033 and AR8035 model -+ Currently supports the AR8030, AR8031, AR8033, AR8035 and internal -+ QCA8337(Internal qca8k PHY) model - - config QSEMI_PHY - tristate "Quality Semiconductor PHYs" ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -92,10 +92,16 @@ - #define AT803X_DEBUG_REG_5 0x05 - #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) - -+#define AT803X_DEBUG_REG_3C 0x3C -+ -+#define AT803X_DEBUG_REG_3D 0x3D -+ - #define AT803X_DEBUG_REG_1F 0x1F - #define AT803X_DEBUG_PLL_ON BIT(2) - #define AT803X_DEBUG_RGMII_1V8 BIT(3) - -+#define MDIO_AZ_DEBUG 0x800D -+ - /* AT803x supports either the XTAL input pad, an internal PLL or the - * DSP as clock reference for the clock output pad. The XTAL reference - * is only used for 25 MHz output, all other frequencies need the PLL. -@@ -142,10 +148,34 @@ - #define AT803X_PAGE_FIBER 0 - #define AT803X_PAGE_COPPER 1 - -+#define QCA8327_PHY_ID 0x004dd034 -+#define QCA8337_PHY_ID 0x004dd036 -+#define QCA8K_PHY_ID_MASK 0xffffffff -+ -+#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0) -+ - MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); - MODULE_AUTHOR("Matus Ujhelyi"); - MODULE_LICENSE("GPL"); - -+enum stat_access_type { -+ PHY, -+ MMD -+}; -+ -+struct at803x_hw_stat { -+ const char *string; -+ u8 reg; -+ u32 mask; -+ enum stat_access_type access_type; -+}; -+ -+static struct at803x_hw_stat at803x_hw_stats[] = { -+ { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY}, -+ { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY}, -+ { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD}, -+}; -+ - struct at803x_priv { - int flags; - #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ -@@ -154,6 +184,7 @@ struct at803x_priv { - struct regulator_dev *vddio_rdev; - struct regulator_dev *vddh_rdev; - struct regulator *vddio; -+ u64 stats[ARRAY_SIZE(at803x_hw_stats)]; - }; - - struct at803x_context { -@@ -165,6 +196,17 @@ struct at803x_context { - u16 led_control; - }; - -+static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data) -+{ -+ int ret; -+ -+ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg); -+ if (ret < 0) -+ return ret; -+ -+ return phy_write(phydev, AT803X_DEBUG_DATA, data); -+} -+ - static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg) - { - int ret; -@@ -327,6 +369,53 @@ static void at803x_get_wol(struct phy_de - wol->wolopts |= WAKE_MAGIC; - } - -+static int at803x_get_sset_count(struct phy_device *phydev) -+{ -+ return ARRAY_SIZE(at803x_hw_stats); -+} -+ -+static void at803x_get_strings(struct phy_device *phydev, u8 *data) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) { -+ strscpy(data + i * ETH_GSTRING_LEN, -+ at803x_hw_stats[i].string, ETH_GSTRING_LEN); -+ } -+} -+ -+static u64 at803x_get_stat(struct phy_device *phydev, int i) -+{ -+ struct at803x_hw_stat stat = at803x_hw_stats[i]; -+ struct at803x_priv *priv = phydev->priv; -+ int val; -+ u64 ret; -+ -+ if (stat.access_type == MMD) -+ val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg); -+ else -+ val = phy_read(phydev, stat.reg); -+ -+ if (val < 0) { -+ ret = U64_MAX; -+ } else { -+ val = val & stat.mask; -+ priv->stats[i] += val; -+ ret = priv->stats[i]; -+ } -+ -+ return ret; -+} -+ -+static void at803x_get_stats(struct phy_device *phydev, -+ struct ethtool_stats *stats, u64 *data) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) -+ data[i] = at803x_get_stat(phydev, i); -+} -+ - static int at803x_suspend(struct phy_device *phydev) - { - int value; -@@ -1130,6 +1219,34 @@ static int at803x_cable_test_start(struc - return 0; - } - -+static int qca83xx_config_init(struct phy_device *phydev) -+{ -+ u8 switch_revision; -+ -+ switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK; -+ -+ switch (switch_revision) { -+ case 1: -+ /* For 100M waveform */ -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea); -+ /* Turn on Gigabit clock */ -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0); -+ break; -+ -+ case 2: -+ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0); -+ fallthrough; -+ case 4: -+ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); -+ break; -+ } -+ -+ return 0; -+} -+ - static struct phy_driver at803x_driver[] = { - { - /* Qualcomm Atheros AR8035 */ -@@ -1226,7 +1343,20 @@ static struct phy_driver at803x_driver[] - .read_status = at803x_read_status, - .soft_reset = genphy_soft_reset, - .config_aneg = at803x_config_aneg, --} }; -+}, { -+ /* QCA8337 */ -+ .phy_id = QCA8337_PHY_ID, -+ .phy_id_mask = QCA8K_PHY_ID_MASK, -+ .name = "QCA PHY 8337", -+ /* PHY_GBIT_FEATURES */ -+ .probe = at803x_probe, -+ .flags = PHY_IS_INTERNAL, -+ .config_init = qca83xx_config_init, -+ .soft_reset = genphy_soft_reset, -+ .get_sset_count = at803x_get_sset_count, -+ .get_strings = at803x_get_strings, -+ .get_stats = at803x_get_stats, -+}, }; - - module_phy_driver(at803x_driver); - diff --git a/target/linux/generic/backport-5.10/736-v5.14-net-dsa-qca8k-fix-missing-unlock-on-error-in-qca8k-vlan.patch b/target/linux/generic/backport-5.10/736-v5.14-net-dsa-qca8k-fix-missing-unlock-on-error-in-qca8k-vlan.patch deleted file mode 100644 index a68e3b1821..0000000000 --- a/target/linux/generic/backport-5.10/736-v5.14-net-dsa-qca8k-fix-missing-unlock-on-error-in-qca8k-vlan.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0d56e5c191b197e1d30a0a4c92628836dafced0f Mon Sep 17 00:00:00 2001 -From: Wei Yongjun -Date: Tue, 18 May 2021 11:24:13 +0000 -Subject: [PATCH] net: dsa: qca8k: fix missing unlock on error in - qca8k_vlan_(add|del) - -Add the missing unlock before return from function qca8k_vlan_add() -and qca8k_vlan_del() in the error handling case. - -Fixes: 028f5f8ef44f ("net: dsa: qca8k: handle error with qca8k_read operation") -Reported-by: Hulk Robot -Signed-off-by: Wei Yongjun -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 16 ++++++++++------ - 1 file changed, 10 insertions(+), 6 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -506,8 +506,10 @@ qca8k_vlan_add(struct qca8k_priv *priv, - goto out; - - reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); -- if (reg < 0) -- return reg; -+ if (reg < 0) { -+ ret = reg; -+ goto out; -+ } - reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; - reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port)); - if (untagged) -@@ -519,7 +521,7 @@ qca8k_vlan_add(struct qca8k_priv *priv, - - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); - if (ret) -- return ret; -+ goto out; - ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); - - out: -@@ -541,8 +543,10 @@ qca8k_vlan_del(struct qca8k_priv *priv, - goto out; - - reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); -- if (reg < 0) -- return reg; -+ if (reg < 0) { -+ ret = reg; -+ goto out; -+ } - reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port)); - reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT << - QCA8K_VTU_FUNC0_EG_MODE_S(port); -@@ -564,7 +568,7 @@ qca8k_vlan_del(struct qca8k_priv *priv, - } else { - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); - if (ret) -- return ret; -+ goto out; - ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); - } - diff --git a/target/linux/generic/backport-5.10/737-v5.14-01-net-dsa-qca8k-check-return-value-of-read-functions-c.patch b/target/linux/generic/backport-5.10/737-v5.14-01-net-dsa-qca8k-check-return-value-of-read-functions-c.patch deleted file mode 100644 index 451b0e9446..0000000000 --- a/target/linux/generic/backport-5.10/737-v5.14-01-net-dsa-qca8k-check-return-value-of-read-functions-c.patch +++ /dev/null @@ -1,348 +0,0 @@ -From 7c9896e37807862e276064dd9331860f5d27affc Mon Sep 17 00:00:00 2001 -From: Yang Yingliang -Date: Sat, 29 May 2021 11:04:38 +0800 -Subject: [PATCH] net: dsa: qca8k: check return value of read functions - correctly - -Current return type of qca8k_mii_read32() and qca8k_read() are -unsigned, it can't be negative, so the return value check is -unuseful. For check the return value correctly, change return -type of the read functions and add a output parameter to store -the read value. - -Signed-off-by: Yang Yingliang -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/qca8k.c | 130 +++++++++++++++++++--------------------- - 1 file changed, 60 insertions(+), 70 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -89,26 +89,26 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u - *page = regaddr & 0x3ff; - } - --static u32 --qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum) -+static int -+qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val) - { -- u32 val; - int ret; - - ret = bus->read(bus, phy_id, regnum); - if (ret >= 0) { -- val = ret; -+ *val = ret; - ret = bus->read(bus, phy_id, regnum + 1); -- val |= ret << 16; -+ *val |= ret << 16; - } - - if (ret < 0) { - dev_err_ratelimited(&bus->dev, - "failed to read qca8k 32bit register\n"); -+ *val = 0; - return ret; - } - -- return val; -+ return 0; - } - - static void -@@ -148,26 +148,26 @@ qca8k_set_page(struct mii_bus *bus, u16 - return 0; - } - --static u32 --qca8k_read(struct qca8k_priv *priv, u32 reg) -+static int -+qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val) - { - struct mii_bus *bus = priv->bus; - u16 r1, r2, page; -- u32 val; -+ int ret; - - qca8k_split_addr(reg, &r1, &r2, &page); - - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - -- val = qca8k_set_page(bus, page); -- if (val < 0) -+ ret = qca8k_set_page(bus, page); -+ if (ret < 0) - goto exit; - -- val = qca8k_mii_read32(bus, 0x10 | r2, r1); -+ ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val); - - exit: - mutex_unlock(&bus->mdio_lock); -- return val; -+ return ret; - } - - static int -@@ -208,11 +208,9 @@ qca8k_rmw(struct qca8k_priv *priv, u32 r - if (ret < 0) - goto exit; - -- val = qca8k_mii_read32(bus, 0x10 | r2, r1); -- if (val < 0) { -- ret = val; -+ ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val); -+ if (ret < 0) - goto exit; -- } - - val &= ~mask; - val |= write_val; -@@ -240,15 +238,8 @@ static int - qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ctx; -- int ret; -- -- ret = qca8k_read(priv, reg); -- if (ret < 0) -- return ret; -- -- *val = ret; - -- return 0; -+ return qca8k_read(priv, reg, val); - } - - static int -@@ -296,18 +287,18 @@ static struct regmap_config qca8k_regmap - static int - qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) - { -+ int ret, ret1; - u32 val; -- int ret; - -- ret = read_poll_timeout(qca8k_read, val, !(val & mask), -+ ret = read_poll_timeout(qca8k_read, ret1, !(val & mask), - 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, -- priv, reg); -+ priv, reg, &val); - - /* Check if qca8k_read has failed for a different reason - * before returning -ETIMEDOUT - */ -- if (ret < 0 && val < 0) -- return val; -+ if (ret < 0 && ret1 < 0) -+ return ret1; - - return ret; - } -@@ -316,13 +307,13 @@ static int - qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) - { - u32 reg[4], val; -- int i; -+ int i, ret; - - /* load the ARL table into an array */ - for (i = 0; i < 4; i++) { -- val = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4)); -- if (val < 0) -- return val; -+ ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val); -+ if (ret < 0) -+ return ret; - - reg[i] = val; - } -@@ -396,9 +387,9 @@ qca8k_fdb_access(struct qca8k_priv *priv - - /* Check for table full violation when adding an entry */ - if (cmd == QCA8K_FDB_LOAD) { -- reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC); -- if (reg < 0) -- return reg; -+ ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®); -+ if (ret < 0) -+ return ret; - if (reg & QCA8K_ATU_FUNC_FULL) - return -1; - } -@@ -477,9 +468,9 @@ qca8k_vlan_access(struct qca8k_priv *pri - - /* Check for table full violation when adding an entry */ - if (cmd == QCA8K_VLAN_LOAD) { -- reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1); -- if (reg < 0) -- return reg; -+ ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®); -+ if (ret < 0) -+ return ret; - if (reg & QCA8K_VTU_FUNC1_FULL) - return -ENOMEM; - } -@@ -505,11 +496,9 @@ qca8k_vlan_add(struct qca8k_priv *priv, - if (ret < 0) - goto out; - -- reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); -- if (reg < 0) { -- ret = reg; -+ ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); -+ if (ret < 0) - goto out; -- } - reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; - reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port)); - if (untagged) -@@ -542,11 +531,9 @@ qca8k_vlan_del(struct qca8k_priv *priv, - if (ret < 0) - goto out; - -- reg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0); -- if (reg < 0) { -- ret = reg; -+ ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); -+ if (ret < 0) - goto out; -- } - reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port)); - reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT << - QCA8K_VTU_FUNC0_EG_MODE_S(port); -@@ -638,19 +625,19 @@ qca8k_mdio_busy_wait(struct mii_bus *bus - { - u16 r1, r2, page; - u32 val; -- int ret; -+ int ret, ret1; - - qca8k_split_addr(reg, &r1, &r2, &page); - -- ret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0, -+ ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0, - QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, -- bus, 0x10 | r2, r1); -+ bus, 0x10 | r2, r1, &val); - - /* Check if qca8k_read has failed for a different reason - * before returnting -ETIMEDOUT - */ -- if (ret < 0 && val < 0) -- return val; -+ if (ret < 0 && ret1 < 0) -+ return ret1; - - return ret; - } -@@ -725,7 +712,7 @@ qca8k_mdio_read(struct mii_bus *salve_bu - if (ret) - goto exit; - -- val = qca8k_mii_read32(bus, 0x10 | r2, r1); -+ ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val); - - exit: - /* even if the busy_wait timeouts try to clear the MASTER_EN */ -@@ -733,10 +720,10 @@ exit: - - mutex_unlock(&bus->mdio_lock); - -- if (val >= 0) -- val &= QCA8K_MDIO_MASTER_DATA_MASK; -+ if (ret >= 0) -+ ret = val & QCA8K_MDIO_MASTER_DATA_MASK; - -- return val; -+ return ret; - } - - static int -@@ -1211,7 +1198,7 @@ qca8k_phylink_mac_config(struct dsa_swit - qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); - - /* Enable/disable SerDes auto-negotiation as necessary */ -- val = qca8k_read(priv, QCA8K_REG_PWS); -+ qca8k_read(priv, QCA8K_REG_PWS, &val); - if (phylink_autoneg_inband(mode)) - val &= ~QCA8K_PWS_SERDES_AEN_DIS; - else -@@ -1219,7 +1206,7 @@ qca8k_phylink_mac_config(struct dsa_swit - qca8k_write(priv, QCA8K_REG_PWS, val); - - /* Configure the SGMII parameters */ -- val = qca8k_read(priv, QCA8K_REG_SGMII_CTRL); -+ qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val); - - val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | - QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD; -@@ -1314,10 +1301,11 @@ qca8k_phylink_mac_link_state(struct dsa_ - { - struct qca8k_priv *priv = ds->priv; - u32 reg; -+ int ret; - -- reg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port)); -- if (reg < 0) -- return reg; -+ ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®); -+ if (ret < 0) -+ return ret; - - state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); - state->an_complete = state->link; -@@ -1419,19 +1407,20 @@ qca8k_get_ethtool_stats(struct dsa_switc - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - const struct qca8k_mib_desc *mib; - u32 reg, i, val; -- u64 hi; -+ u64 hi = 0; -+ int ret; - - for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) { - mib = &ar8327_mib[i]; - reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; - -- val = qca8k_read(priv, reg); -- if (val < 0) -+ ret = qca8k_read(priv, reg, &val); -+ if (ret < 0) - continue; - - if (mib->size == 2) { -- hi = qca8k_read(priv, reg + 4); -- if (hi < 0) -+ ret = qca8k_read(priv, reg + 4, (u32 *)&hi); -+ if (ret < 0) - continue; - } - -@@ -1459,7 +1448,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds, - int ret; - - mutex_lock(&priv->reg_mutex); -- reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL); -+ ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®); - if (reg < 0) { - ret = reg; - goto exit; -@@ -1802,14 +1791,15 @@ static int qca8k_read_switch_id(struct q - const struct qca8k_match_data *data; - u32 val; - u8 id; -+ int ret; - - /* get the switches ID from the compatible */ - data = of_device_get_match_data(priv->dev); - if (!data) - return -ENODEV; - -- val = qca8k_read(priv, QCA8K_REG_MASK_CTRL); -- if (val < 0) -+ ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val); -+ if (ret < 0) - return -ENODEV; - - id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK); diff --git a/target/linux/generic/backport-5.10/737-v5.14-02-net-dsa-qca8k-add-missing-check-return-value-in-qca8.patch b/target/linux/generic/backport-5.10/737-v5.14-02-net-dsa-qca8k-add-missing-check-return-value-in-qca8.patch deleted file mode 100644 index d20da5b85e..0000000000 --- a/target/linux/generic/backport-5.10/737-v5.14-02-net-dsa-qca8k-add-missing-check-return-value-in-qca8.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 9fe99de01440d9ede74d447ac76e9c445d8daae9 Mon Sep 17 00:00:00 2001 -From: Yang Yingliang -Date: Sat, 29 May 2021 11:04:39 +0800 -Subject: [PATCH] net: dsa: qca8k: add missing check return value in - qca8k_phylink_mac_config() - -Now we can check qca8k_read() return value correctly, so if -it fails, we need return directly. - -Signed-off-by: Yang Yingliang -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/qca8k.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1128,6 +1128,7 @@ qca8k_phylink_mac_config(struct dsa_swit - { - struct qca8k_priv *priv = ds->priv; - u32 reg, val; -+ int ret; - - switch (port) { - case 0: /* 1st CPU port */ -@@ -1198,7 +1199,9 @@ qca8k_phylink_mac_config(struct dsa_swit - qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); - - /* Enable/disable SerDes auto-negotiation as necessary */ -- qca8k_read(priv, QCA8K_REG_PWS, &val); -+ ret = qca8k_read(priv, QCA8K_REG_PWS, &val); -+ if (ret) -+ return; - if (phylink_autoneg_inband(mode)) - val &= ~QCA8K_PWS_SERDES_AEN_DIS; - else -@@ -1206,7 +1209,9 @@ qca8k_phylink_mac_config(struct dsa_swit - qca8k_write(priv, QCA8K_REG_PWS, val); - - /* Configure the SGMII parameters */ -- qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val); -+ ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val); -+ if (ret) -+ return; - - val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | - QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD; diff --git a/target/linux/generic/backport-5.10/738-v5.14-01-net-dsa-qca8k-fix-an-endian-bug-in-qca8k-get-ethtool.patch b/target/linux/generic/backport-5.10/738-v5.14-01-net-dsa-qca8k-fix-an-endian-bug-in-qca8k-get-ethtool.patch deleted file mode 100644 index aed97d0549..0000000000 --- a/target/linux/generic/backport-5.10/738-v5.14-01-net-dsa-qca8k-fix-an-endian-bug-in-qca8k-get-ethtool.patch +++ /dev/null @@ -1,47 +0,0 @@ -From aa3d020b22cb844ab7bdbb9e5d861a64666e2b74 Mon Sep 17 00:00:00 2001 -From: Dan Carpenter -Date: Wed, 9 Jun 2021 12:52:12 +0300 -Subject: [PATCH] net: dsa: qca8k: fix an endian bug in - qca8k_get_ethtool_stats() - -The "hi" variable is a u64 but the qca8k_read() writes to the top 32 -bits of it. That will work on little endian systems but it's a bit -subtle. It's cleaner to make declare "hi" as a u32. We will still need -to cast it when we shift it later on in the function but that's fine. - -Fixes: 7c9896e37807 ("net: dsa: qca8k: check return value of read functions correctly") -Signed-off-by: Dan Carpenter -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1412,7 +1412,7 @@ qca8k_get_ethtool_stats(struct dsa_switc - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; - const struct qca8k_mib_desc *mib; - u32 reg, i, val; -- u64 hi = 0; -+ u32 hi = 0; - int ret; - - for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) { -@@ -1424,14 +1424,14 @@ qca8k_get_ethtool_stats(struct dsa_switc - continue; - - if (mib->size == 2) { -- ret = qca8k_read(priv, reg + 4, (u32 *)&hi); -+ ret = qca8k_read(priv, reg + 4, &hi); - if (ret < 0) - continue; - } - - data[i] = val; - if (mib->size == 2) -- data[i] |= hi << 32; -+ data[i] |= (u64)hi << 32; - } - } - diff --git a/target/linux/generic/backport-5.10/738-v5.14-02-net-dsa-qca8k-check-the-correct-variable-in-qca8k-se.patch b/target/linux/generic/backport-5.10/738-v5.14-02-net-dsa-qca8k-check-the-correct-variable-in-qca8k-se.patch deleted file mode 100644 index c58f79cd8b..0000000000 --- a/target/linux/generic/backport-5.10/738-v5.14-02-net-dsa-qca8k-check-the-correct-variable-in-qca8k-se.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 3d0167f2a627528032821cdeb78b4eab0510460f Mon Sep 17 00:00:00 2001 -From: Dan Carpenter -Date: Wed, 9 Jun 2021 12:53:03 +0300 -Subject: [PATCH] net: dsa: qca8k: check the correct variable in - qca8k_set_mac_eee() - -This code check "reg" but "ret" was intended so the error handling will -never trigger. - -Fixes: 7c9896e37807 ("net: dsa: qca8k: check return value of read functions correctly") -Signed-off-by: Dan Carpenter -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1454,10 +1454,8 @@ qca8k_set_mac_eee(struct dsa_switch *ds, - - mutex_lock(&priv->reg_mutex); - ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®); -- if (reg < 0) { -- ret = reg; -+ if (ret < 0) - goto exit; -- } - - if (eee->eee_enabled) - reg |= lpi_en; diff --git a/target/linux/generic/backport-5.10/739-v5.15-net-dsa-qca8k-fix-kernel-panic-with-legacy-mdio-mapping.patch b/target/linux/generic/backport-5.10/739-v5.15-net-dsa-qca8k-fix-kernel-panic-with-legacy-mdio-mapping.patch deleted file mode 100644 index 1e293d3a0b..0000000000 --- a/target/linux/generic/backport-5.10/739-v5.15-net-dsa-qca8k-fix-kernel-panic-with-legacy-mdio-mapping.patch +++ /dev/null @@ -1,80 +0,0 @@ -From ce062a0adbfe933b1932235fdfd874c4c91d1bb0 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 11 Sep 2021 17:50:09 +0200 -Subject: net: dsa: qca8k: fix kernel panic with legacy mdio mapping - -When the mdio legacy mapping is used the mii_bus priv registered by DSA -refer to the dsa switch struct instead of the qca8k_priv struct and -causes a kernel panic. Create dedicated function when the internal -dedicated mdio driver is used to properly handle the 2 different -implementation. - -Fixes: 759bafb8a322 ("net: dsa: qca8k: add support for internal phy and internal mdio") -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 30 ++++++++++++++++++++++-------- - 1 file changed, 22 insertions(+), 8 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -643,10 +643,8 @@ qca8k_mdio_busy_wait(struct mii_bus *bus - } - - static int --qca8k_mdio_write(struct mii_bus *salve_bus, int phy, int regnum, u16 data) -+qca8k_mdio_write(struct mii_bus *bus, int phy, int regnum, u16 data) - { -- struct qca8k_priv *priv = salve_bus->priv; -- struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - u32 val; - int ret; -@@ -682,10 +680,8 @@ exit: - } - - static int --qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum) -+qca8k_mdio_read(struct mii_bus *bus, int phy, int regnum) - { -- struct qca8k_priv *priv = salve_bus->priv; -- struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - u32 val; - int ret; -@@ -727,6 +723,24 @@ exit: - } - - static int -+qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data) -+{ -+ struct qca8k_priv *priv = slave_bus->priv; -+ struct mii_bus *bus = priv->bus; -+ -+ return qca8k_mdio_write(bus, phy, regnum, data); -+} -+ -+static int -+qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum) -+{ -+ struct qca8k_priv *priv = slave_bus->priv; -+ struct mii_bus *bus = priv->bus; -+ -+ return qca8k_mdio_read(bus, phy, regnum); -+} -+ -+static int - qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data) - { - struct qca8k_priv *priv = ds->priv; -@@ -775,8 +789,8 @@ qca8k_mdio_register(struct qca8k_priv *p - - bus->priv = (void *)priv; - bus->name = "qca8k slave mii"; -- bus->read = qca8k_mdio_read; -- bus->write = qca8k_mdio_write; -+ bus->read = qca8k_internal_mdio_read; -+ bus->write = qca8k_internal_mdio_write; - snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d", - ds->index); - diff --git a/target/linux/generic/backport-5.10/740-v5.13-0001-net-dsa-b53-Add-debug-prints-in-b53_vlan_enable.patch b/target/linux/generic/backport-5.10/740-v5.13-0001-net-dsa-b53-Add-debug-prints-in-b53_vlan_enable.patch deleted file mode 100644 index 91cf55b18a..0000000000 --- a/target/linux/generic/backport-5.10/740-v5.13-0001-net-dsa-b53-Add-debug-prints-in-b53_vlan_enable.patch +++ /dev/null @@ -1,65 +0,0 @@ -From ee47ed08d75e8f16b3cf882061ee19c2ea19dd6c Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Wed, 10 Mar 2021 10:52:26 -0800 -Subject: [PATCH] net: dsa: b53: Add debug prints in b53_vlan_enable() - -Having dynamic debug prints in b53_vlan_enable() has been helpful to -uncover a recent but update the function to indicate the port being -configured (or -1 for initial setup) and include the global VLAN enabled -and VLAN filtering enable status. - -Signed-off-by: Florian Fainelli -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/dsa/b53/b53_common.c | 11 +++++++---- - 1 file changed, 7 insertions(+), 4 deletions(-) - ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -349,7 +349,7 @@ static void b53_set_forwarding(struct b5 - b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt); - } - --static void b53_enable_vlan(struct b53_device *dev, bool enable, -+static void b53_enable_vlan(struct b53_device *dev, int port, bool enable, - bool enable_filtering) - { - u8 mgmt, vc0, vc1, vc4 = 0, vc5; -@@ -431,6 +431,9 @@ static void b53_enable_vlan(struct b53_d - b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt); - - dev->vlan_enabled = enable; -+ -+ dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n", -+ port, enable, enable_filtering); - } - - static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100) -@@ -708,7 +711,7 @@ int b53_configure_vlan(struct dsa_switch - b53_do_vlan_op(dev, VTA_CMD_CLEAR); - } - -- b53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering); -+ b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); - - b53_for_each_port(dev, i) - b53_write16(dev, B53_VLAN_PAGE, -@@ -1390,7 +1393,7 @@ int b53_vlan_filtering(struct dsa_switch - if (switchdev_trans_ph_prepare(trans)) - return 0; - -- b53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering); -+ b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering); - - return 0; - } -@@ -1415,7 +1418,7 @@ int b53_vlan_prepare(struct dsa_switch * - if (vlan->vid_end >= dev->num_vlans) - return -ERANGE; - -- b53_enable_vlan(dev, true, ds->vlan_filtering); -+ b53_enable_vlan(dev, port, true, ds->vlan_filtering); - - return 0; - } diff --git a/target/linux/generic/backport-5.10/740-v5.13-0002-net-dsa-b53-spi-allow-device-tree-probing.patch b/target/linux/generic/backport-5.10/740-v5.13-0002-net-dsa-b53-spi-allow-device-tree-probing.patch deleted file mode 100644 index 56579b2d36..0000000000 --- a/target/linux/generic/backport-5.10/740-v5.13-0002-net-dsa-b53-spi-allow-device-tree-probing.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 6d16eadab6db0c1d61e59fee7ed1ecc2d10269be Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Mon, 15 Mar 2021 15:14:23 +0100 -Subject: [PATCH] net: dsa: b53: spi: allow device tree probing -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add missing of_match_table to allow device tree probing. - -Signed-off-by: Álvaro Fernández Rojas -Signed-off-by: David S. Miller ---- - drivers/net/dsa/b53/b53_spi.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/net/dsa/b53/b53_spi.c -+++ b/drivers/net/dsa/b53/b53_spi.c -@@ -324,9 +324,22 @@ static int b53_spi_remove(struct spi_dev - return 0; - } - -+static const struct of_device_id b53_spi_of_match[] = { -+ { .compatible = "brcm,bcm5325" }, -+ { .compatible = "brcm,bcm5365" }, -+ { .compatible = "brcm,bcm5395" }, -+ { .compatible = "brcm,bcm5397" }, -+ { .compatible = "brcm,bcm5398" }, -+ { .compatible = "brcm,bcm53115" }, -+ { .compatible = "brcm,bcm53125" }, -+ { .compatible = "brcm,bcm53128" }, -+ { /* sentinel */ } -+}; -+ - static struct spi_driver b53_spi_driver = { - .driver = { - .name = "b53-switch", -+ .of_match_table = b53_spi_of_match, - }, - .probe = b53_spi_probe, - .remove = b53_spi_remove, diff --git a/target/linux/generic/backport-5.10/740-v5.13-0003-net-dsa-b53-relax-is63xx-condition.patch b/target/linux/generic/backport-5.10/740-v5.13-0003-net-dsa-b53-relax-is63xx-condition.patch deleted file mode 100644 index 99eced1b6a..0000000000 --- a/target/linux/generic/backport-5.10/740-v5.13-0003-net-dsa-b53-relax-is63xx-condition.patch +++ /dev/null @@ -1,31 +0,0 @@ -From ad426d7d966b525b73ed5a1842dd830312bbba71 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Mar 2021 09:42:01 +0100 -Subject: [PATCH] net: dsa: b53: relax is63xx() condition -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM63xx switches are present on bcm63xx and bmips devices. - -Signed-off-by: Álvaro Fernández Rojas -Acked-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/b53/b53_priv.h | 4 ---- - 1 file changed, 4 deletions(-) - ---- a/drivers/net/dsa/b53/b53_priv.h -+++ b/drivers/net/dsa/b53/b53_priv.h -@@ -186,11 +186,7 @@ static inline int is531x5(struct b53_dev - - static inline int is63xx(struct b53_device *dev) - { --#ifdef CONFIG_BCM63XX - return dev->chip_id == BCM63XX_DEVICE_ID; --#else -- return 0; --#endif - } - - static inline int is5301x(struct b53_device *dev) diff --git a/target/linux/generic/backport-5.10/740-v5.13-0004-net-dsa-tag_brcm-add-support-for-legacy-tags.patch b/target/linux/generic/backport-5.10/740-v5.13-0004-net-dsa-tag_brcm-add-support-for-legacy-tags.patch deleted file mode 100644 index 3b7d8f37cd..0000000000 --- a/target/linux/generic/backport-5.10/740-v5.13-0004-net-dsa-tag_brcm-add-support-for-legacy-tags.patch +++ /dev/null @@ -1,180 +0,0 @@ -From 964dbf186eaa84d409c359ddf09c827a3fbe8228 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Mar 2021 11:29:26 +0100 -Subject: [PATCH] net: dsa: tag_brcm: add support for legacy tags -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add support for legacy Broadcom tags, which are similar to DSA_TAG_PROTO_BRCM. -These tags are used on BCM5325, BCM5365 and BCM63xx switches. - -Signed-off-by: Álvaro Fernández Rojas -Signed-off-by: David S. Miller ---- - include/net/dsa.h | 2 + - net/dsa/Kconfig | 7 +++ - net/dsa/tag_brcm.c | 107 +++++++++++++++++++++++++++++++++++++++++++-- - 3 files changed, 113 insertions(+), 3 deletions(-) - ---- a/include/net/dsa.h -+++ b/include/net/dsa.h -@@ -45,10 +45,12 @@ struct phylink_link_state; - #define DSA_TAG_PROTO_OCELOT_VALUE 15 - #define DSA_TAG_PROTO_AR9331_VALUE 16 - #define DSA_TAG_PROTO_RTL4_A_VALUE 17 -+#define DSA_TAG_PROTO_BRCM_LEGACY_VALUE 22 - - enum dsa_tag_protocol { - DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE, - DSA_TAG_PROTO_BRCM = DSA_TAG_PROTO_BRCM_VALUE, -+ DSA_TAG_PROTO_BRCM_LEGACY = DSA_TAG_PROTO_BRCM_LEGACY_VALUE, - DSA_TAG_PROTO_BRCM_PREPEND = DSA_TAG_PROTO_BRCM_PREPEND_VALUE, - DSA_TAG_PROTO_DSA = DSA_TAG_PROTO_DSA_VALUE, - DSA_TAG_PROTO_EDSA = DSA_TAG_PROTO_EDSA_VALUE, ---- a/net/dsa/Kconfig -+++ b/net/dsa/Kconfig -@@ -47,6 +47,13 @@ config NET_DSA_TAG_BRCM - Say Y if you want to enable support for tagging frames for the - Broadcom switches which place the tag after the MAC source address. - -+config NET_DSA_TAG_BRCM_LEGACY -+ tristate "Tag driver for Broadcom legacy switches using in-frame headers" -+ select NET_DSA_TAG_BRCM_COMMON -+ help -+ Say Y if you want to enable support for tagging frames for the -+ Broadcom legacy switches which place the tag after the MAC source -+ address. - - config NET_DSA_TAG_BRCM_PREPEND - tristate "Tag driver for Broadcom switches using prepended headers" ---- a/net/dsa/tag_brcm.c -+++ b/net/dsa/tag_brcm.c -@@ -11,9 +11,26 @@ - - #include "dsa_priv.h" - --/* This tag length is 4 bytes, older ones were 6 bytes, we do not -- * handle them -- */ -+/* Legacy Broadcom tag (6 bytes) */ -+#define BRCM_LEG_TAG_LEN 6 -+ -+/* Type fields */ -+/* 1st byte in the tag */ -+#define BRCM_LEG_TYPE_HI 0x88 -+/* 2nd byte in the tag */ -+#define BRCM_LEG_TYPE_LO 0x74 -+ -+/* Tag fields */ -+/* 3rd byte in the tag */ -+#define BRCM_LEG_UNICAST (0 << 5) -+#define BRCM_LEG_MULTICAST (1 << 5) -+#define BRCM_LEG_EGRESS (2 << 5) -+#define BRCM_LEG_INGRESS (3 << 5) -+ -+/* 6th byte in the tag */ -+#define BRCM_LEG_PORT_ID (0xf) -+ -+/* Newer Broadcom tag (4 bytes) */ - #define BRCM_TAG_LEN 4 - - /* Tag is constructed and desconstructed using byte by byte access -@@ -194,6 +211,87 @@ DSA_TAG_DRIVER(brcm_netdev_ops); - MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM); - #endif - -+#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_LEGACY) -+static struct sk_buff *brcm_leg_tag_xmit(struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ struct dsa_port *dp = dsa_slave_to_port(dev); -+ u8 *brcm_tag; -+ -+ /* The Ethernet switch we are interfaced with needs packets to be at -+ * least 64 bytes (including FCS) otherwise they will be discarded when -+ * they enter the switch port logic. When Broadcom tags are enabled, we -+ * need to make sure that packets are at least 70 bytes -+ * (including FCS and tag) because the length verification is done after -+ * the Broadcom tag is stripped off the ingress packet. -+ * -+ * Let dsa_slave_xmit() free the SKB -+ */ -+ if (__skb_put_padto(skb, ETH_ZLEN + BRCM_LEG_TAG_LEN, false)) -+ return NULL; -+ -+ skb_push(skb, BRCM_LEG_TAG_LEN); -+ -+ memmove(skb->data, skb->data + BRCM_LEG_TAG_LEN, 2 * ETH_ALEN); -+ -+ brcm_tag = skb->data + 2 * ETH_ALEN; -+ -+ /* Broadcom tag type */ -+ brcm_tag[0] = BRCM_LEG_TYPE_HI; -+ brcm_tag[1] = BRCM_LEG_TYPE_LO; -+ -+ /* Broadcom tag value */ -+ brcm_tag[2] = BRCM_LEG_EGRESS; -+ brcm_tag[3] = 0; -+ brcm_tag[4] = 0; -+ brcm_tag[5] = dp->index & BRCM_LEG_PORT_ID; -+ -+ return skb; -+} -+ -+static struct sk_buff *brcm_leg_tag_rcv(struct sk_buff *skb, -+ struct net_device *dev, -+ struct packet_type *pt) -+{ -+ int source_port; -+ u8 *brcm_tag; -+ -+ if (unlikely(!pskb_may_pull(skb, BRCM_LEG_PORT_ID))) -+ return NULL; -+ -+ brcm_tag = skb->data - 2; -+ -+ source_port = brcm_tag[5] & BRCM_LEG_PORT_ID; -+ -+ skb->dev = dsa_master_find_slave(dev, 0, source_port); -+ if (!skb->dev) -+ return NULL; -+ -+ /* Remove Broadcom tag and update checksum */ -+ skb_pull_rcsum(skb, BRCM_LEG_TAG_LEN); -+ -+ skb->offload_fwd_mark = 1; -+ -+ /* Move the Ethernet DA and SA */ -+ memmove(skb->data - ETH_HLEN, -+ skb->data - ETH_HLEN - BRCM_LEG_TAG_LEN, -+ 2 * ETH_ALEN); -+ -+ return skb; -+} -+ -+static const struct dsa_device_ops brcm_legacy_netdev_ops = { -+ .name = "brcm-legacy", -+ .proto = DSA_TAG_PROTO_BRCM_LEGACY, -+ .xmit = brcm_leg_tag_xmit, -+ .rcv = brcm_leg_tag_rcv, -+ .overhead = BRCM_LEG_TAG_LEN, -+}; -+ -+DSA_TAG_DRIVER(brcm_legacy_netdev_ops); -+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM_LEGACY); -+#endif /* CONFIG_NET_DSA_TAG_BRCM_LEGACY */ -+ - #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND) - static struct sk_buff *brcm_tag_xmit_prepend(struct sk_buff *skb, - struct net_device *dev) -@@ -226,6 +324,9 @@ static struct dsa_tag_driver *dsa_tag_dr - #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) - &DSA_TAG_DRIVER_NAME(brcm_netdev_ops), - #endif -+#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_LEGACY) -+ &DSA_TAG_DRIVER_NAME(brcm_legacy_netdev_ops), -+#endif - #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND) - &DSA_TAG_DRIVER_NAME(brcm_prepend_netdev_ops), - #endif diff --git a/target/linux/generic/backport-5.10/740-v5.13-0005-net-dsa-b53-support-legacy-tags.patch b/target/linux/generic/backport-5.10/740-v5.13-0005-net-dsa-b53-support-legacy-tags.patch deleted file mode 100644 index 838e78a057..0000000000 --- a/target/linux/generic/backport-5.10/740-v5.13-0005-net-dsa-b53-support-legacy-tags.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 46c5176c586c81306bf9e7024c13b95da775490f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Mar 2021 11:29:27 +0100 -Subject: [PATCH] net: dsa: b53: support legacy tags -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -These tags are used on BCM5325, BCM5365 and BCM63xx switches. - -Signed-off-by: Álvaro Fernández Rojas -Acked-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/b53/Kconfig | 1 + - drivers/net/dsa/b53/b53_common.c | 12 +++++++----- - 2 files changed, 8 insertions(+), 5 deletions(-) - ---- a/drivers/net/dsa/b53/Kconfig -+++ b/drivers/net/dsa/b53/Kconfig -@@ -3,6 +3,7 @@ menuconfig B53 - tristate "Broadcom BCM53xx managed switch support" - depends on NET_DSA - select NET_DSA_TAG_BRCM -+ select NET_DSA_TAG_BRCM_LEGACY - select NET_DSA_TAG_BRCM_PREPEND - help - This driver adds support for Broadcom managed switch chips. It supports ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -2024,15 +2024,17 @@ enum dsa_tag_protocol b53_get_tag_protoc - { - struct b53_device *dev = ds->priv; - -- /* Older models (5325, 5365) support a different tag format that we do -- * not support in net/dsa/tag_brcm.c yet. -- */ -- if (is5325(dev) || is5365(dev) || -- !b53_can_enable_brcm_tags(ds, port, mprot)) { -+ if (!b53_can_enable_brcm_tags(ds, port, mprot)) { - dev->tag_protocol = DSA_TAG_PROTO_NONE; - goto out; - } - -+ /* Older models require a different 6 byte tag */ -+ if (is5325(dev) || is5365(dev) || is63xx(dev)) { -+ dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY; -+ goto out; -+ } -+ - /* Broadcom BCM58xx chips have a flow accelerator on Port 8 - * which requires us to use the prepended Broadcom tag type - */ diff --git a/target/linux/generic/backport-5.10/740-v5.13-0006-net-dsa-b53-mmap-Add-device-tree-support.patch b/target/linux/generic/backport-5.10/740-v5.13-0006-net-dsa-b53-mmap-Add-device-tree-support.patch deleted file mode 100644 index 48494d13e4..0000000000 --- a/target/linux/generic/backport-5.10/740-v5.13-0006-net-dsa-b53-mmap-Add-device-tree-support.patch +++ /dev/null @@ -1,92 +0,0 @@ -From a5538a777b73b35750ed1ffff8c1ef539e861624 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Wed, 17 Mar 2021 10:23:17 +0100 -Subject: [PATCH] net: dsa: b53: mmap: Add device tree support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add device tree support to b53_mmap.c while keeping platform devices support. - -Signed-off-by: Álvaro Fernández Rojas -Signed-off-by: David S. Miller ---- - drivers/net/dsa/b53/b53_mmap.c | 55 ++++++++++++++++++++++++++++++++++ - 1 file changed, 55 insertions(+) - ---- a/drivers/net/dsa/b53/b53_mmap.c -+++ b/drivers/net/dsa/b53/b53_mmap.c -@@ -16,6 +16,7 @@ - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -+#include - #include - #include - #include -@@ -242,11 +243,65 @@ static const struct b53_io_ops b53_mmap_ - .phy_write16 = b53_mmap_phy_write16, - }; - -+static int b53_mmap_probe_of(struct platform_device *pdev, -+ struct b53_platform_data **ppdata) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct device_node *of_ports, *of_port; -+ struct device *dev = &pdev->dev; -+ struct b53_platform_data *pdata; -+ void __iomem *mem; -+ -+ mem = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(mem)) -+ return PTR_ERR(mem); -+ -+ pdata = devm_kzalloc(dev, sizeof(struct b53_platform_data), -+ GFP_KERNEL); -+ if (!pdata) -+ return -ENOMEM; -+ -+ pdata->regs = mem; -+ pdata->chip_id = BCM63XX_DEVICE_ID; -+ pdata->big_endian = of_property_read_bool(np, "big-endian"); -+ -+ of_ports = of_get_child_by_name(np, "ports"); -+ if (!of_ports) { -+ dev_err(dev, "no ports child node found\n"); -+ return -EINVAL; -+ } -+ -+ for_each_available_child_of_node(of_ports, of_port) { -+ u32 reg; -+ -+ if (of_property_read_u32(of_port, "reg", ®)) -+ continue; -+ -+ if (reg < B53_CPU_PORT) -+ pdata->enabled_ports |= BIT(reg); -+ } -+ -+ of_node_put(of_ports); -+ *ppdata = pdata; -+ -+ return 0; -+} -+ - static int b53_mmap_probe(struct platform_device *pdev) - { -+ struct device_node *np = pdev->dev.of_node; - struct b53_platform_data *pdata = pdev->dev.platform_data; - struct b53_mmap_priv *priv; - struct b53_device *dev; -+ int ret; -+ -+ if (!pdata && np) { -+ ret = b53_mmap_probe_of(pdev, &pdata); -+ if (ret) { -+ dev_err(&pdev->dev, "OF probe error\n"); -+ return ret; -+ } -+ } - - if (!pdata) - return -EINVAL; diff --git a/target/linux/generic/backport-5.10/740-v5.13-0007-net-dsa-b53-spi-add-missing-MODULE_DEVICE_TABLE.patch b/target/linux/generic/backport-5.10/740-v5.13-0007-net-dsa-b53-spi-add-missing-MODULE_DEVICE_TABLE.patch deleted file mode 100644 index ea36755732..0000000000 --- a/target/linux/generic/backport-5.10/740-v5.13-0007-net-dsa-b53-spi-add-missing-MODULE_DEVICE_TABLE.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 866f1577ba69bde2b9f36c300f603596c7d84a62 Mon Sep 17 00:00:00 2001 -From: Qinglang Miao -Date: Thu, 25 Mar 2021 17:19:54 +0800 -Subject: [PATCH] net: dsa: b53: spi: add missing MODULE_DEVICE_TABLE - -This patch adds missing MODULE_DEVICE_TABLE definition which generates -correct modalias for automatic loading of this driver when it is built -as an external module. - -Reported-by: Hulk Robot -Signed-off-by: Qinglang Miao -Acked-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/b53/b53_spi.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/dsa/b53/b53_spi.c -+++ b/drivers/net/dsa/b53/b53_spi.c -@@ -335,6 +335,7 @@ static const struct of_device_id b53_spi - { .compatible = "brcm,bcm53128" }, - { /* sentinel */ } - }; -+MODULE_DEVICE_TABLE(of, b53_spi_of_match); - - static struct spi_driver b53_spi_driver = { - .driver = { diff --git a/target/linux/generic/backport-5.10/741-v5.14-0001-net-dsa-b53-Do-not-force-CPU-to-be-always-tagged.patch b/target/linux/generic/backport-5.10/741-v5.14-0001-net-dsa-b53-Do-not-force-CPU-to-be-always-tagged.patch deleted file mode 100644 index 2a8def39b8..0000000000 --- a/target/linux/generic/backport-5.10/741-v5.14-0001-net-dsa-b53-Do-not-force-CPU-to-be-always-tagged.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 2c32a3d3c233b855943677609fe388f82b1f0975 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Tue, 8 Jun 2021 14:22:04 -0700 -Subject: [PATCH] net: dsa: b53: Do not force CPU to be always tagged - -Commit ca8931948344 ("net: dsa: b53: Keep CPU port as tagged in all -VLANs") forced the CPU port to be always tagged in any VLAN membership. -This was necessary back then because we did not support Broadcom tags -for all configurations so the only way to differentiate tagged and -untagged traffic while DSA_TAG_PROTO_NONE was used was to force the CPU -port into being always tagged. - -With most configurations enabling Broadcom tags, especially after -8fab459e69ab ("net: dsa: b53: Enable Broadcom tags for 531x5/539x -families") we do not need to apply this unconditional force tagging of -the CPU port in all VLANs. - -A helper function is introduced to faciliate the encapsulation of the -specific condition requiring the CPU port to be tagged in all VLANs and -the dsa_switch_ops::untag_bridge_pvid boolean is moved to when -dsa_switch_ops::setup is called when we have already determined the -tagging protocol we will be using. - -Reported-by: Matthew Hagan -Signed-off-by: Florian Fainelli -Reviewed-by: Vladimir Oltean -Tested-by: Matthew Hagan -Signed-off-by: David S. Miller ---- - drivers/net/dsa/b53/b53_common.c | 17 ++++++++++++++--- - 1 file changed, 14 insertions(+), 3 deletions(-) - ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -1049,6 +1049,11 @@ static int b53_setup(struct dsa_switch * - unsigned int port; - int ret; - -+ /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set -+ * which forces the CPU port to be tagged in all VLANs. -+ */ -+ ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE; -+ - ret = b53_reset_switch(dev); - if (ret) { - dev_err(ds->dev, "failed to reset switch\n"); -@@ -1423,6 +1428,13 @@ int b53_vlan_prepare(struct dsa_switch * - return 0; - } - EXPORT_SYMBOL(b53_vlan_prepare); -+ -+static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) -+{ -+ struct b53_device *dev = ds->priv; -+ -+ return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); -+} - - void b53_vlan_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan) -@@ -1442,7 +1454,7 @@ void b53_vlan_add(struct dsa_switch *ds, - untagged = true; - - vl->members |= BIT(port); -- if (untagged && !dsa_is_cpu_port(ds, port)) -+ if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) - vl->untag |= BIT(port); - else - vl->untag &= ~BIT(port); -@@ -1480,7 +1492,7 @@ int b53_vlan_del(struct dsa_switch *ds, - if (pvid == vid) - pvid = b53_default_pvid(dev); - -- if (untagged && !dsa_is_cpu_port(ds, port)) -+ if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port)) - vl->untag &= ~(BIT(port)); - - b53_set_vlan_entry(dev, vid, vl); -@@ -2644,7 +2656,6 @@ struct b53_device *b53_switch_alloc(stru - dev->ops = ops; - ds->ops = &b53_switch_ops; - ds->configure_vlan_while_not_filtering = true; -- ds->untag_bridge_pvid = true; - dev->vlan_enabled = ds->configure_vlan_while_not_filtering; - /* Let DSA handle the case were multiple bridges span the same switch - * device and different VLAN awareness settings are requested, which diff --git a/target/linux/generic/backport-5.10/741-v5.14-0002-net-dsa-b53-remove-redundant-null-check-on-dev.patch b/target/linux/generic/backport-5.10/741-v5.14-0002-net-dsa-b53-remove-redundant-null-check-on-dev.patch deleted file mode 100644 index ee3a71ffa5..0000000000 --- a/target/linux/generic/backport-5.10/741-v5.14-0002-net-dsa-b53-remove-redundant-null-check-on-dev.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 11b57faf951cd3a570e3d9e463fc7c41023bc8c6 Mon Sep 17 00:00:00 2001 -From: Colin Ian King -Date: Tue, 15 Jun 2021 10:05:16 +0100 -Subject: [PATCH] net: dsa: b53: remove redundant null check on dev - -The pointer dev can never be null, the null check is redundant -and can be removed. Cleans up a static analysis warning that -pointer priv is dereferencing dev before dev is being null -checked. - -Addresses-Coverity: ("Dereference before null check") -Signed-off-by: Colin Ian King -Acked-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/b53/b53_srab.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/net/dsa/b53/b53_srab.c -+++ b/drivers/net/dsa/b53/b53_srab.c -@@ -632,8 +632,7 @@ static int b53_srab_remove(struct platfo - struct b53_srab_priv *priv = dev->priv; - - b53_srab_intr_set(priv, false); -- if (dev) -- b53_switch_remove(dev); -+ b53_switch_remove(dev); - - return 0; - } diff --git a/target/linux/generic/backport-5.10/741-v5.14-0003-net-dsa-b53-Create-default-VLAN-entry-explicitly.patch b/target/linux/generic/backport-5.10/741-v5.14-0003-net-dsa-b53-Create-default-VLAN-entry-explicitly.patch deleted file mode 100644 index df891d68ab..0000000000 --- a/target/linux/generic/backport-5.10/741-v5.14-0003-net-dsa-b53-Create-default-VLAN-entry-explicitly.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 64a81b24487f0d2fba0f033029eec2abc7d82cee Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Mon, 21 Jun 2021 15:10:55 -0700 -Subject: [PATCH] net: dsa: b53: Create default VLAN entry explicitly - -In case CONFIG_VLAN_8021Q is not set, there will be no call down to the -b53 driver to ensure that the default PVID VLAN entry will be configured -with the appropriate untagged attribute towards the CPU port. We were -implicitly relying on dsa_slave_vlan_rx_add_vid() to do that for us, -instead make it explicit. - -Reported-by: Vladimir Oltean -Signed-off-by: Florian Fainelli -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/b53/b53_common.c | 27 +++++++++++++++++++-------- - 1 file changed, 19 insertions(+), 8 deletions(-) - ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -693,6 +693,13 @@ static u16 b53_default_pvid(struct b53_d - return 0; - } - -+static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) -+{ -+ struct b53_device *dev = ds->priv; -+ -+ return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); -+} -+ - int b53_configure_vlan(struct dsa_switch *ds) - { - struct b53_device *dev = ds->priv; -@@ -713,9 +720,20 @@ int b53_configure_vlan(struct dsa_switch - - b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering); - -- b53_for_each_port(dev, i) -+ /* Create an untagged VLAN entry for the default PVID in case -+ * CONFIG_VLAN_8021Q is disabled and there are no calls to -+ * dsa_slave_vlan_rx_add_vid() to create the default VLAN -+ * entry. Do this only when the tagging protocol is not -+ * DSA_TAG_PROTO_NONE -+ */ -+ b53_for_each_port(dev, i) { -+ v = &dev->vlans[def_vid]; -+ v->members |= BIT(i); -+ if (!b53_vlan_port_needs_forced_tagged(ds, i)) -+ v->untag = v->members; - b53_write16(dev, B53_VLAN_PAGE, - B53_VLAN_PORT_DEF_TAG(i), def_vid); -+ } - - /* Upon initial call we have not set-up any VLANs, but upon - * system resume, we need to restore all VLAN entries. -@@ -1429,13 +1447,6 @@ int b53_vlan_prepare(struct dsa_switch * - } - EXPORT_SYMBOL(b53_vlan_prepare); - --static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port) --{ -- struct b53_device *dev = ds->priv; -- -- return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port); --} -- - void b53_vlan_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan) - { diff --git a/target/linux/generic/backport-5.10/742-v5.16-net-phy-at803x-add-support-for-qca-8327-internal-phy.patch b/target/linux/generic/backport-5.10/742-v5.16-net-phy-at803x-add-support-for-qca-8327-internal-phy.patch deleted file mode 100644 index e356d549bb..0000000000 --- a/target/linux/generic/backport-5.10/742-v5.16-net-phy-at803x-add-support-for-qca-8327-internal-phy.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 0ccf8511182436183c031e8a2f740ae91a02c625 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 14 Sep 2021 14:33:45 +0200 -Subject: net: phy: at803x: add support for qca 8327 internal phy - -Add support for qca8327 internal phy needed for correct init of the -switch port. It does use the same qca8337 function and reg just with a -different id. - -Signed-off-by: Ansuel Smith -Tested-by: Rosen Penev -Tested-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -1356,6 +1356,19 @@ static struct phy_driver at803x_driver[] - .get_sset_count = at803x_get_sset_count, - .get_strings = at803x_get_strings, - .get_stats = at803x_get_stats, -+}, { -+ /* QCA8327 */ -+ .phy_id = QCA8327_PHY_ID, -+ .phy_id_mask = QCA8K_PHY_ID_MASK, -+ .name = "QCA PHY 8327", -+ /* PHY_GBIT_FEATURES */ -+ .probe = at803x_probe, -+ .flags = PHY_IS_INTERNAL, -+ .config_init = qca83xx_config_init, -+ .soft_reset = genphy_soft_reset, -+ .get_sset_count = at803x_get_sset_count, -+ .get_strings = at803x_get_strings, -+ .get_stats = at803x_get_stats, - }, }; - - module_phy_driver(at803x_driver); -@@ -1366,6 +1379,8 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, - { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, - { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(QCA8327_PHY_ID) }, - { } - }; - diff --git a/target/linux/generic/backport-5.10/743-v5.16-0001-net-dsa-b53-Include-all-ports-in-enabled_ports.patch b/target/linux/generic/backport-5.10/743-v5.16-0001-net-dsa-b53-Include-all-ports-in-enabled_ports.patch deleted file mode 100644 index d80b5db714..0000000000 --- a/target/linux/generic/backport-5.10/743-v5.16-0001-net-dsa-b53-Include-all-ports-in-enabled_ports.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 983d96a9116a328668601555d96736261d33170c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 16 Sep 2021 14:03:51 +0200 -Subject: [PATCH] net: dsa: b53: Include all ports in "enabled_ports" -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Make "enabled_ports" bitfield contain all available switch ports -including a CPU port. This way there is no need for fixup during -initialization. - -For BCM53010, BCM53018 and BCM53019 include also other available ports. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Tested-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/b53/b53_common.c | 23 +++++++++++------------ - 1 file changed, 11 insertions(+), 12 deletions(-) - ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -2288,7 +2288,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM5325_DEVICE_ID, - .dev_name = "BCM5325", - .vlans = 16, -- .enabled_ports = 0x1f, -+ .enabled_ports = 0x3f, - .arl_bins = 2, - .arl_buckets = 1024, - .imp_port = 5, -@@ -2299,7 +2299,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM5365_DEVICE_ID, - .dev_name = "BCM5365", - .vlans = 256, -- .enabled_ports = 0x1f, -+ .enabled_ports = 0x3f, - .arl_bins = 2, - .arl_buckets = 1024, - .imp_port = 5, -@@ -2310,7 +2310,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM5389_DEVICE_ID, - .dev_name = "BCM5389", - .vlans = 4096, -- .enabled_ports = 0x1f, -+ .enabled_ports = 0x11f, - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -@@ -2324,7 +2324,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM5395_DEVICE_ID, - .dev_name = "BCM5395", - .vlans = 4096, -- .enabled_ports = 0x1f, -+ .enabled_ports = 0x11f, - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -@@ -2338,7 +2338,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM5397_DEVICE_ID, - .dev_name = "BCM5397", - .vlans = 4096, -- .enabled_ports = 0x1f, -+ .enabled_ports = 0x11f, - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -@@ -2352,7 +2352,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM5398_DEVICE_ID, - .dev_name = "BCM5398", - .vlans = 4096, -- .enabled_ports = 0x7f, -+ .enabled_ports = 0x17f, - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -@@ -2366,7 +2366,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM53115_DEVICE_ID, - .dev_name = "BCM53115", - .vlans = 4096, -- .enabled_ports = 0x1f, -+ .enabled_ports = 0x11f, - .arl_bins = 4, - .arl_buckets = 1024, - .vta_regs = B53_VTA_REGS, -@@ -2380,7 +2380,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM53125_DEVICE_ID, - .dev_name = "BCM53125", - .vlans = 4096, -- .enabled_ports = 0xff, -+ .enabled_ports = 0x1ff, - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -@@ -2422,7 +2422,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM53010_DEVICE_ID, - .dev_name = "BCM53010", - .vlans = 4096, -- .enabled_ports = 0x1f, -+ .enabled_ports = 0x1bf, - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -@@ -2464,7 +2464,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM53018_DEVICE_ID, - .dev_name = "BCM53018", - .vlans = 4096, -- .enabled_ports = 0x1f, -+ .enabled_ports = 0x1bf, - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -@@ -2478,7 +2478,7 @@ static const struct b53_chip_data b53_sw - .chip_id = BCM53019_DEVICE_ID, - .dev_name = "BCM53019", - .vlans = 4096, -- .enabled_ports = 0x1f, -+ .enabled_ports = 0x1bf, - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -@@ -2605,7 +2605,6 @@ static int b53_switch_init(struct b53_de - dev->cpu_port = 5; - } - -- dev->enabled_ports |= BIT(dev->cpu_port); - dev->num_ports = fls(dev->enabled_ports); - - dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS); diff --git a/target/linux/generic/backport-5.10/743-v5.16-0002-net-dsa-b53-Drop-BCM5301x-workaround-for-a-wrong-CPU.patch b/target/linux/generic/backport-5.10/743-v5.16-0002-net-dsa-b53-Drop-BCM5301x-workaround-for-a-wrong-CPU.patch deleted file mode 100644 index 4a4f8e940d..0000000000 --- a/target/linux/generic/backport-5.10/743-v5.16-0002-net-dsa-b53-Drop-BCM5301x-workaround-for-a-wrong-CPU.patch +++ /dev/null @@ -1,42 +0,0 @@ -From b290c6384afabbca5ae6e2af72fb1b2bc37922be Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 16 Sep 2021 14:03:52 +0200 -Subject: [PATCH] net: dsa: b53: Drop BCM5301x workaround for a wrong CPU/IMP - port -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -On BCM5301x port 8 requires a fixed link when used. - -Years ago when b53 was an OpenWrt downstream driver (with configuration -based on sometimes bugged NVRAM) there was a need for a fixup. In case -of forcing fixed link for (incorrectly specified) port 5 the code had to -actually setup port 8 link. - -For upstream b53 driver with setup based on DT there is no need for that -workaround. In DT we have and require correct ports setup. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Tested-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/b53/b53_common.c | 6 ------ - 1 file changed, 6 deletions(-) - ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -1256,12 +1256,6 @@ static void b53_adjust_link(struct dsa_s - return; - } - } -- } else if (is5301x(dev)) { -- if (port != dev->cpu_port) { -- b53_force_port_config(dev, dev->cpu_port, 2000, -- DUPLEX_FULL, true, true); -- b53_force_link(dev, dev->cpu_port, 1); -- } - } - - /* Re-negotiate EEE if it was enabled already */ diff --git a/target/linux/generic/backport-5.10/743-v5.16-0003-net-dsa-b53-Improve-flow-control-setup-on-BCM5301x.patch b/target/linux/generic/backport-5.10/743-v5.16-0003-net-dsa-b53-Improve-flow-control-setup-on-BCM5301x.patch deleted file mode 100644 index 3954ee4aac..0000000000 --- a/target/linux/generic/backport-5.10/743-v5.16-0003-net-dsa-b53-Improve-flow-control-setup-on-BCM5301x.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 3ff26b29230c54fea2353b63124c589b61953e14 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 16 Sep 2021 14:03:53 +0200 -Subject: [PATCH] net: dsa: b53: Improve flow control setup on BCM5301x -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -According to the Broadcom's reference driver flow control needs to be -enabled for any CPU switch port (5, 7 or 8 - depending on which one is -used). Current code makes it work only for the port 5. Use -dsa_is_cpu_port() which solved that problem. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Tested-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/b53/b53_common.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -1187,7 +1187,7 @@ static void b53_adjust_link(struct dsa_s - return; - - /* Enable flow control on BCM5301x's CPU port */ -- if (is5301x(dev) && port == dev->cpu_port) -+ if (is5301x(dev) && dsa_is_cpu_port(ds, port)) - tx_pause = rx_pause = true; - - if (phydev->pause) { diff --git a/target/linux/generic/backport-5.10/743-v5.16-0004-net-dsa-b53-Drop-unused-cpu_port-field.patch b/target/linux/generic/backport-5.10/743-v5.16-0004-net-dsa-b53-Drop-unused-cpu_port-field.patch deleted file mode 100644 index 9e687b1488..0000000000 --- a/target/linux/generic/backport-5.10/743-v5.16-0004-net-dsa-b53-Drop-unused-cpu_port-field.patch +++ /dev/null @@ -1,205 +0,0 @@ -From 7d5af56418d7d01e43247a33b6fe6492ea871923 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 16 Sep 2021 14:03:54 +0200 -Subject: [PATCH] net: dsa: b53: Drop unused "cpu_port" field -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's set but never used anymore. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Tested-by: Florian Fainelli -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/b53/b53_common.c | 28 ---------------------------- - drivers/net/dsa/b53/b53_priv.h | 1 - - 2 files changed, 29 deletions(-) - ---- a/drivers/net/dsa/b53/b53_common.c -+++ b/drivers/net/dsa/b53/b53_common.c -@@ -2286,7 +2286,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 2, - .arl_buckets = 1024, - .imp_port = 5, -- .cpu_port = B53_CPU_PORT_25, - .duplex_reg = B53_DUPLEX_STAT_FE, - }, - { -@@ -2297,7 +2296,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 2, - .arl_buckets = 1024, - .imp_port = 5, -- .cpu_port = B53_CPU_PORT_25, - .duplex_reg = B53_DUPLEX_STAT_FE, - }, - { -@@ -2308,7 +2306,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2322,7 +2319,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2336,7 +2332,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS_9798, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2350,7 +2345,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS_9798, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2365,7 +2359,6 @@ static const struct b53_chip_data b53_sw - .arl_buckets = 1024, - .vta_regs = B53_VTA_REGS, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, - .jumbo_size_reg = B53_JUMBO_MAX_SIZE, -@@ -2378,7 +2371,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2392,7 +2384,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2406,7 +2397,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS_63XX, - .duplex_reg = B53_DUPLEX_STAT_63XX, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX, -@@ -2420,7 +2410,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2434,7 +2423,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2448,7 +2436,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2462,7 +2449,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2476,7 +2462,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */ - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2490,7 +2475,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2504,7 +2488,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2518,7 +2501,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 1024, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2532,7 +2514,6 @@ static const struct b53_chip_data b53_sw - .arl_bins = 4, - .arl_buckets = 256, - .imp_port = 8, -- .cpu_port = B53_CPU_PORT, - .vta_regs = B53_VTA_REGS, - .duplex_reg = B53_DUPLEX_STAT_GE, - .jumbo_pm_reg = B53_JUMBO_PORT_MASK, -@@ -2558,7 +2539,6 @@ static int b53_switch_init(struct b53_de - dev->vta_regs[2] = chip->vta_regs[2]; - dev->jumbo_pm_reg = chip->jumbo_pm_reg; - dev->imp_port = chip->imp_port; -- dev->cpu_port = chip->cpu_port; - dev->num_vlans = chip->vlans; - dev->num_arl_bins = chip->arl_bins; - dev->num_arl_buckets = chip->arl_buckets; -@@ -2590,13 +2570,6 @@ static int b53_switch_init(struct b53_de - break; - #endif - } -- } else if (dev->chip_id == BCM53115_DEVICE_ID) { -- u64 strap_value; -- -- b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value); -- /* use second IMP port if GMII is enabled */ -- if (strap_value & SV_GMII_CTRL_115) -- dev->cpu_port = 5; - } - - dev->num_ports = fls(dev->enabled_ports); ---- a/drivers/net/dsa/b53/b53_priv.h -+++ b/drivers/net/dsa/b53/b53_priv.h -@@ -123,7 +123,6 @@ struct b53_device { - /* used ports mask */ - u16 enabled_ports; - unsigned int imp_port; -- unsigned int cpu_port; - - /* connect specific data */ - u8 current_page; diff --git a/target/linux/generic/backport-5.10/744-v5.15-net-dsa-don-t-set-skb-offload_fwd_mark-when-not-offl.patch b/target/linux/generic/backport-5.10/744-v5.15-net-dsa-don-t-set-skb-offload_fwd_mark-when-not-offl.patch deleted file mode 100644 index 51f87904ef..0000000000 --- a/target/linux/generic/backport-5.10/744-v5.15-net-dsa-don-t-set-skb-offload_fwd_mark-when-not-offl.patch +++ /dev/null @@ -1,138 +0,0 @@ -From bea7907837c57a0aaac009931eb14efb056dafab Mon Sep 17 00:00:00 2001 -From: Vladimir Oltean -Date: Thu, 29 Jul 2021 17:56:00 +0300 -Subject: [PATCH] net: dsa: don't set skb->offload_fwd_mark when not offloading - the bridge - -DSA has gained the recent ability to deal gracefully with upper -interfaces it cannot offload, such as the bridge, bonding or team -drivers. When such uppers exist, the ports are still in standalone mode -as far as the hardware is concerned. - -But when we deliver packets to the software bridge in order for that to -do the forwarding, there is an unpleasant surprise in that the bridge -will refuse to forward them. This is because we unconditionally set -skb->offload_fwd_mark = true, meaning that the bridge thinks the frames -were already forwarded in hardware by us. - -Since dp->bridge_dev is populated only when there is hardware offload -for it, but not in the software fallback case, let's introduce a new -helper that can be called from the tagger data path which sets the -skb->offload_fwd_mark accordingly to zero when there is no hardware -offload for bridging. This lets the bridge forward packets back to other -interfaces of our switch, if needed. - -Signed-off-by: Vladimir Oltean -Reviewed-by: Tobias Waldekranz -Signed-off-by: David S. Miller ---- - net/dsa/dsa_priv.h | 14 ++++++++++++++ - net/dsa/tag_brcm.c | 4 ++-- - net/dsa/tag_dsa.c | 15 +++++++++++---- - net/dsa/tag_ksz.c | 2 +- - net/dsa/tag_lan9303.c | 3 ++- - net/dsa/tag_mtk.c | 2 +- - net/dsa/tag_ocelot.c | 2 +- - net/dsa/tag_rtl4_a.c | 2 +- - net/dsa/tag_sja1105.c | 20 ++++++++++++++------ - 9 files changed, 47 insertions(+), 17 deletions(-) - ---- a/net/dsa/dsa_priv.h -+++ b/net/dsa/dsa_priv.h -@@ -266,6 +266,20 @@ static inline struct sk_buff *dsa_untag_ - return skb; - } - -+/* If the ingress port offloads the bridge, we mark the frame as autonomously -+ * forwarded by hardware, so the software bridge doesn't forward in twice, back -+ * to us, because we already did. However, if we're in fallback mode and we do -+ * software bridging, we are not offloading it, therefore the dp->bridge_dev -+ * pointer is not populated, and flooding needs to be done by software (we are -+ * effectively operating in standalone ports mode). -+ */ -+static inline void dsa_default_offload_fwd_mark(struct sk_buff *skb) -+{ -+ struct dsa_port *dp = dsa_slave_to_port(skb->dev); -+ -+ skb->offload_fwd_mark = !!(dp->bridge_dev); -+} -+ - /* switch.c */ - int dsa_switch_register_notifier(struct dsa_switch *ds); - void dsa_switch_unregister_notifier(struct dsa_switch *ds); ---- a/net/dsa/tag_brcm.c -+++ b/net/dsa/tag_brcm.c -@@ -166,7 +166,7 @@ static struct sk_buff *brcm_tag_rcv_ll(s - /* Remove Broadcom tag and update checksum */ - skb_pull_rcsum(skb, BRCM_TAG_LEN); - -- skb->offload_fwd_mark = 1; -+ dsa_default_offload_fwd_mark(skb); - - return skb; - } -@@ -270,7 +270,7 @@ static struct sk_buff *brcm_leg_tag_rcv( - /* Remove Broadcom tag and update checksum */ - skb_pull_rcsum(skb, BRCM_LEG_TAG_LEN); - -- skb->offload_fwd_mark = 1; -+ dsa_default_offload_fwd_mark(skb); - - /* Move the Ethernet DA and SA */ - memmove(skb->data - ETH_HLEN, ---- a/net/dsa/tag_ksz.c -+++ b/net/dsa/tag_ksz.c -@@ -25,7 +25,7 @@ static struct sk_buff *ksz_common_rcv(st - if (pskb_trim_rcsum(skb, skb->len - len)) - return NULL; - -- skb->offload_fwd_mark = true; -+ dsa_default_offload_fwd_mark(skb); - - return skb; - } ---- a/net/dsa/tag_lan9303.c -+++ b/net/dsa/tag_lan9303.c -@@ -115,7 +115,8 @@ static struct sk_buff *lan9303_rcv(struc - skb_pull_rcsum(skb, 2 + 2); - memmove(skb->data - ETH_HLEN, skb->data - (ETH_HLEN + LAN9303_TAG_LEN), - 2 * ETH_ALEN); -- skb->offload_fwd_mark = !(lan9303_tag1 & LAN9303_TAG_RX_TRAPPED_TO_CPU); -+ if (!(lan9303_tag1 & LAN9303_TAG_RX_TRAPPED_TO_CPU)) -+ dsa_default_offload_fwd_mark(skb); - - return skb; - } ---- a/net/dsa/tag_mtk.c -+++ b/net/dsa/tag_mtk.c -@@ -104,7 +104,7 @@ static struct sk_buff *mtk_tag_rcv(struc - - /* Only unicast or broadcast frames are offloaded */ - if (likely(!is_multicast_skb)) -- skb->offload_fwd_mark = 1; -+ dsa_default_offload_fwd_mark(skb); - - return skb; - } ---- a/net/dsa/tag_ocelot.c -+++ b/net/dsa/tag_ocelot.c -@@ -225,7 +225,7 @@ static struct sk_buff *ocelot_rcv(struct - */ - return NULL; - -- skb->offload_fwd_mark = 1; -+ dsa_default_offload_fwd_mark(skb); - skb->priority = qos_class; - - /* Ocelot switches copy frames unmodified to the CPU. However, it is ---- a/net/dsa/tag_rtl4_a.c -+++ b/net/dsa/tag_rtl4_a.c -@@ -115,7 +115,7 @@ static struct sk_buff *rtl4a_tag_rcv(str - skb->data - ETH_HLEN - RTL4_A_HDR_LEN, - 2 * ETH_ALEN); - -- skb->offload_fwd_mark = 1; -+ dsa_default_offload_fwd_mark(skb); - - return skb; - } diff --git a/target/linux/generic/backport-5.10/745-v5.16-01-net-phy-at803x-add-support-for-qca-8327-A-variant.patch b/target/linux/generic/backport-5.10/745-v5.16-01-net-phy-at803x-add-support-for-qca-8327-A-variant.patch deleted file mode 100644 index f13b80b531..0000000000 --- a/target/linux/generic/backport-5.10/745-v5.16-01-net-phy-at803x-add-support-for-qca-8327-A-variant.patch +++ /dev/null @@ -1,65 +0,0 @@ -From b4df02b562f4aa14ff6811f30e1b4d2159585c59 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 19 Sep 2021 18:28:15 +0200 -Subject: net: phy: at803x: add support for qca 8327 A variant internal phy - -For qca8327 internal phy there are 2 different switch variant with 2 -different phy id. Add this missing variant so the internal phy can be -correctly identified and fixed. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 25 ++++++++++++++++++++----- - 1 file changed, 20 insertions(+), 5 deletions(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -148,7 +148,8 @@ - #define AT803X_PAGE_FIBER 0 - #define AT803X_PAGE_COPPER 1 - --#define QCA8327_PHY_ID 0x004dd034 -+#define QCA8327_A_PHY_ID 0x004dd033 -+#define QCA8327_B_PHY_ID 0x004dd034 - #define QCA8337_PHY_ID 0x004dd036 - #define QCA8K_PHY_ID_MASK 0xffffffff - -@@ -1357,10 +1358,23 @@ static struct phy_driver at803x_driver[] - .get_strings = at803x_get_strings, - .get_stats = at803x_get_stats, - }, { -- /* QCA8327 */ -- .phy_id = QCA8327_PHY_ID, -+ /* QCA8327-A from switch QCA8327-AL1A */ -+ .phy_id = QCA8327_A_PHY_ID, - .phy_id_mask = QCA8K_PHY_ID_MASK, -- .name = "QCA PHY 8327", -+ .name = "QCA PHY 8327-A", -+ /* PHY_GBIT_FEATURES */ -+ .probe = at803x_probe, -+ .flags = PHY_IS_INTERNAL, -+ .config_init = qca83xx_config_init, -+ .soft_reset = genphy_soft_reset, -+ .get_sset_count = at803x_get_sset_count, -+ .get_strings = at803x_get_strings, -+ .get_stats = at803x_get_stats, -+}, { -+ /* QCA8327-B from switch QCA8327-BL1A */ -+ .phy_id = QCA8327_B_PHY_ID, -+ .phy_id_mask = QCA8K_PHY_ID_MASK, -+ .name = "QCA PHY 8327-B", - /* PHY_GBIT_FEATURES */ - .probe = at803x_probe, - .flags = PHY_IS_INTERNAL, -@@ -1380,7 +1394,8 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, - { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, - { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, -- { PHY_ID_MATCH_EXACT(QCA8327_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) }, -+ { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, - { } - }; - diff --git a/target/linux/generic/backport-5.10/745-v5.16-02-net-phy-at803x-add-resume-suspend-function-to-qca83x.patch b/target/linux/generic/backport-5.10/745-v5.16-02-net-phy-at803x-add-resume-suspend-function-to-qca83x.patch deleted file mode 100644 index 25b05aa33f..0000000000 --- a/target/linux/generic/backport-5.10/745-v5.16-02-net-phy-at803x-add-resume-suspend-function-to-qca83x.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 15b9df4ece17d084f14eb0ca1cf05f2ad497e425 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 19 Sep 2021 18:28:16 +0200 -Subject: net: phy: at803x: add resume/suspend function to qca83xx phy - -Add resume/suspend function to qca83xx internal phy. -We can't use the at803x generic function as the documentation lacks of -any support for WoL regs. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -1357,6 +1357,8 @@ static struct phy_driver at803x_driver[] - .get_sset_count = at803x_get_sset_count, - .get_strings = at803x_get_strings, - .get_stats = at803x_get_stats, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, - }, { - /* QCA8327-A from switch QCA8327-AL1A */ - .phy_id = QCA8327_A_PHY_ID, -@@ -1370,6 +1372,8 @@ static struct phy_driver at803x_driver[] - .get_sset_count = at803x_get_sset_count, - .get_strings = at803x_get_strings, - .get_stats = at803x_get_stats, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, - }, { - /* QCA8327-B from switch QCA8327-BL1A */ - .phy_id = QCA8327_B_PHY_ID, -@@ -1383,6 +1387,8 @@ static struct phy_driver at803x_driver[] - .get_sset_count = at803x_get_sset_count, - .get_strings = at803x_get_strings, - .get_stats = at803x_get_stats, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, - }, }; - - module_phy_driver(at803x_driver); diff --git a/target/linux/generic/backport-5.10/745-v5.16-03-net-phy-at803x-fix-spacing-and-improve-name-for-83xx.patch b/target/linux/generic/backport-5.10/745-v5.16-03-net-phy-at803x-fix-spacing-and-improve-name-for-83xx.patch deleted file mode 100644 index 8e53e0e639..0000000000 --- a/target/linux/generic/backport-5.10/745-v5.16-03-net-phy-at803x-fix-spacing-and-improve-name-for-83xx.patch +++ /dev/null @@ -1,95 +0,0 @@ -From d44fd8604a4ab92119adb35f05fd87612af722b5 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 19 Sep 2021 18:28:17 +0200 -Subject: net: phy: at803x: fix spacing and improve name for 83xx phy - -Fix spacing and improve name for 83xx phy following other phy in the -same driver. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 60 ++++++++++++++++++++++++------------------------ - 1 file changed, 30 insertions(+), 30 deletions(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -1346,47 +1346,47 @@ static struct phy_driver at803x_driver[] - .config_aneg = at803x_config_aneg, - }, { - /* QCA8337 */ -- .phy_id = QCA8337_PHY_ID, -- .phy_id_mask = QCA8K_PHY_ID_MASK, -- .name = "QCA PHY 8337", -+ .phy_id = QCA8337_PHY_ID, -+ .phy_id_mask = QCA8K_PHY_ID_MASK, -+ .name = "Qualcomm Atheros 8337 internal PHY", - /* PHY_GBIT_FEATURES */ -- .probe = at803x_probe, -- .flags = PHY_IS_INTERNAL, -- .config_init = qca83xx_config_init, -- .soft_reset = genphy_soft_reset, -- .get_sset_count = at803x_get_sset_count, -- .get_strings = at803x_get_strings, -- .get_stats = at803x_get_stats, -+ .probe = at803x_probe, -+ .flags = PHY_IS_INTERNAL, -+ .config_init = qca83xx_config_init, -+ .soft_reset = genphy_soft_reset, -+ .get_sset_count = at803x_get_sset_count, -+ .get_strings = at803x_get_strings, -+ .get_stats = at803x_get_stats, - .suspend = genphy_suspend, - .resume = genphy_resume, - }, { - /* QCA8327-A from switch QCA8327-AL1A */ -- .phy_id = QCA8327_A_PHY_ID, -- .phy_id_mask = QCA8K_PHY_ID_MASK, -- .name = "QCA PHY 8327-A", -+ .phy_id = QCA8327_A_PHY_ID, -+ .phy_id_mask = QCA8K_PHY_ID_MASK, -+ .name = "Qualcomm Atheros 8327-A internal PHY", - /* PHY_GBIT_FEATURES */ -- .probe = at803x_probe, -- .flags = PHY_IS_INTERNAL, -- .config_init = qca83xx_config_init, -- .soft_reset = genphy_soft_reset, -- .get_sset_count = at803x_get_sset_count, -- .get_strings = at803x_get_strings, -- .get_stats = at803x_get_stats, -+ .probe = at803x_probe, -+ .flags = PHY_IS_INTERNAL, -+ .config_init = qca83xx_config_init, -+ .soft_reset = genphy_soft_reset, -+ .get_sset_count = at803x_get_sset_count, -+ .get_strings = at803x_get_strings, -+ .get_stats = at803x_get_stats, - .suspend = genphy_suspend, - .resume = genphy_resume, - }, { - /* QCA8327-B from switch QCA8327-BL1A */ -- .phy_id = QCA8327_B_PHY_ID, -- .phy_id_mask = QCA8K_PHY_ID_MASK, -- .name = "QCA PHY 8327-B", -+ .phy_id = QCA8327_B_PHY_ID, -+ .phy_id_mask = QCA8K_PHY_ID_MASK, -+ .name = "Qualcomm Atheros 8327-B internal PHY", - /* PHY_GBIT_FEATURES */ -- .probe = at803x_probe, -- .flags = PHY_IS_INTERNAL, -- .config_init = qca83xx_config_init, -- .soft_reset = genphy_soft_reset, -- .get_sset_count = at803x_get_sset_count, -- .get_strings = at803x_get_strings, -- .get_stats = at803x_get_stats, -+ .probe = at803x_probe, -+ .flags = PHY_IS_INTERNAL, -+ .config_init = qca83xx_config_init, -+ .soft_reset = genphy_soft_reset, -+ .get_sset_count = at803x_get_sset_count, -+ .get_strings = at803x_get_strings, -+ .get_stats = at803x_get_stats, - .suspend = genphy_suspend, - .resume = genphy_resume, - }, }; diff --git a/target/linux/generic/backport-5.10/746-v5.16-01-net-phy-at803x-fix-resume-for-QCA8327-phy.patch b/target/linux/generic/backport-5.10/746-v5.16-01-net-phy-at803x-fix-resume-for-QCA8327-phy.patch deleted file mode 100644 index 1f803e582b..0000000000 --- a/target/linux/generic/backport-5.10/746-v5.16-01-net-phy-at803x-fix-resume-for-QCA8327-phy.patch +++ /dev/null @@ -1,131 +0,0 @@ -From ba3c01ee02ed0d821c9f241f179bbc9457542b8f Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 10 Oct 2021 00:46:15 +0200 -Subject: net: phy: at803x: fix resume for QCA8327 phy - -From Documentation phy resume triggers phy reset and restart -auto-negotiation. Add a dedicated function to wait reset to finish as -it was notice a regression where port sometime are not reliable after a -suspend/resume session. The reset wait logic is copied from phy_poll_reset. -Add dedicated suspend function to use genphy_suspend only with QCA8337 -phy and set only additional debug settings for QCA8327. With more test -it was reported that QCA8327 doesn't proprely support this mode and -using this cause the unreliability of the switch ports, especially the -malfunction of the port0. - -Fixes: 15b9df4ece17 ("net: phy: at803x: add resume/suspend function to qca83xx phy") -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 69 +++++++++++++++++++++++++++++++++++++++++++----- - 1 file changed, 63 insertions(+), 6 deletions(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -92,9 +92,14 @@ - #define AT803X_DEBUG_REG_5 0x05 - #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) - -+#define AT803X_DEBUG_REG_HIB_CTRL 0x0b -+#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10) -+#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13) -+ - #define AT803X_DEBUG_REG_3C 0x3C - - #define AT803X_DEBUG_REG_3D 0x3D -+#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) - - #define AT803X_DEBUG_REG_1F 0x1F - #define AT803X_DEBUG_PLL_ON BIT(2) -@@ -1248,6 +1253,58 @@ static int qca83xx_config_init(struct ph - return 0; - } - -+static int qca83xx_resume(struct phy_device *phydev) -+{ -+ int ret, val; -+ -+ /* Skip reset if not suspended */ -+ if (!phydev->suspended) -+ return 0; -+ -+ /* Reinit the port, reset values set by suspend */ -+ qca83xx_config_init(phydev); -+ -+ /* Reset the port on port resume */ -+ phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); -+ -+ /* On resume from suspend the switch execute a reset and -+ * restart auto-negotiation. Wait for reset to complete. -+ */ -+ ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET), -+ 50000, 600000, true); -+ if (ret) -+ return ret; -+ -+ msleep(1); -+ -+ return 0; -+} -+ -+static int qca83xx_suspend(struct phy_device *phydev) -+{ -+ u16 mask = 0; -+ -+ /* Only QCA8337 support actual suspend. -+ * QCA8327 cause port unreliability when phy suspend -+ * is set. -+ */ -+ if (phydev->drv->phy_id == QCA8337_PHY_ID) { -+ genphy_suspend(phydev); -+ } else { -+ mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX); -+ phy_modify(phydev, MII_BMCR, mask, 0); -+ } -+ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D, -+ AT803X_DEBUG_GATE_CLK_IN1000, 0); -+ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, -+ AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE | -+ AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0); -+ -+ return 0; -+} -+ - static struct phy_driver at803x_driver[] = { - { - /* Qualcomm Atheros AR8035 */ -@@ -1357,8 +1414,8 @@ static struct phy_driver at803x_driver[] - .get_sset_count = at803x_get_sset_count, - .get_strings = at803x_get_strings, - .get_stats = at803x_get_stats, -- .suspend = genphy_suspend, -- .resume = genphy_resume, -+ .suspend = qca83xx_suspend, -+ .resume = qca83xx_resume, - }, { - /* QCA8327-A from switch QCA8327-AL1A */ - .phy_id = QCA8327_A_PHY_ID, -@@ -1372,8 +1429,8 @@ static struct phy_driver at803x_driver[] - .get_sset_count = at803x_get_sset_count, - .get_strings = at803x_get_strings, - .get_stats = at803x_get_stats, -- .suspend = genphy_suspend, -- .resume = genphy_resume, -+ .suspend = qca83xx_suspend, -+ .resume = qca83xx_resume, - }, { - /* QCA8327-B from switch QCA8327-BL1A */ - .phy_id = QCA8327_B_PHY_ID, -@@ -1387,8 +1444,8 @@ static struct phy_driver at803x_driver[] - .get_sset_count = at803x_get_sset_count, - .get_strings = at803x_get_strings, - .get_stats = at803x_get_stats, -- .suspend = genphy_suspend, -- .resume = genphy_resume, -+ .suspend = qca83xx_suspend, -+ .resume = qca83xx_resume, - }, }; - - module_phy_driver(at803x_driver); diff --git a/target/linux/generic/backport-5.10/746-v5.16-02-net-phy-at803x-add-DAC-amplitude-fix-for-8327-phy.patch b/target/linux/generic/backport-5.10/746-v5.16-02-net-phy-at803x-add-DAC-amplitude-fix-for-8327-phy.patch deleted file mode 100644 index b82b6595fa..0000000000 --- a/target/linux/generic/backport-5.10/746-v5.16-02-net-phy-at803x-add-DAC-amplitude-fix-for-8327-phy.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 1ca8311949aec5c9447645731ef1c6bc5bd71350 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 10 Oct 2021 00:46:16 +0200 -Subject: net: phy: at803x: add DAC amplitude fix for 8327 phy - -QCA8327 internal phy require DAC amplitude adjustement set to +6% with -100m speed. Also add additional define to report a change of the same -reg in QCA8337. (different scope it does set 1000m voltage) -Add link_change_notify function to set the proper amplitude adjustement -on PHY_RUNNING state and disable on any other state. - -Fixes: b4df02b562f4 ("net: phy: at803x: add support for qca 8327 A variant internal phy") -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 33 +++++++++++++++++++++++++++++++++ - 1 file changed, 33 insertions(+) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -87,6 +87,8 @@ - #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 - - #define AT803X_DEBUG_REG_0 0x00 -+#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) -+#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) - #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) - - #define AT803X_DEBUG_REG_5 0x05 -@@ -1250,9 +1252,37 @@ static int qca83xx_config_init(struct ph - break; - } - -+ /* QCA8327 require DAC amplitude adjustment for 100m set to +6%. -+ * Disable on init and enable only with 100m speed following -+ * qca original source code. -+ */ -+ if (phydev->drv->phy_id == QCA8327_A_PHY_ID || -+ phydev->drv->phy_id == QCA8327_B_PHY_ID) -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, -+ QCA8327_DEBUG_MANU_CTRL_EN, 0); -+ - return 0; - } - -+static void qca83xx_link_change_notify(struct phy_device *phydev) -+{ -+ /* QCA8337 doesn't require DAC Amplitude adjustement */ -+ if (phydev->drv->phy_id == QCA8337_PHY_ID) -+ return; -+ -+ /* Set DAC Amplitude adjustment to +6% for 100m on link running */ -+ if (phydev->state == PHY_RUNNING) { -+ if (phydev->speed == SPEED_100) -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, -+ QCA8327_DEBUG_MANU_CTRL_EN, -+ QCA8327_DEBUG_MANU_CTRL_EN); -+ } else { -+ /* Reset DAC Amplitude adjustment */ -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, -+ QCA8327_DEBUG_MANU_CTRL_EN, 0); -+ } -+} -+ - static int qca83xx_resume(struct phy_device *phydev) - { - int ret, val; -@@ -1407,6 +1437,7 @@ static struct phy_driver at803x_driver[] - .phy_id_mask = QCA8K_PHY_ID_MASK, - .name = "Qualcomm Atheros 8337 internal PHY", - /* PHY_GBIT_FEATURES */ -+ .link_change_notify = qca83xx_link_change_notify, - .probe = at803x_probe, - .flags = PHY_IS_INTERNAL, - .config_init = qca83xx_config_init, -@@ -1422,6 +1453,7 @@ static struct phy_driver at803x_driver[] - .phy_id_mask = QCA8K_PHY_ID_MASK, - .name = "Qualcomm Atheros 8327-A internal PHY", - /* PHY_GBIT_FEATURES */ -+ .link_change_notify = qca83xx_link_change_notify, - .probe = at803x_probe, - .flags = PHY_IS_INTERNAL, - .config_init = qca83xx_config_init, -@@ -1437,6 +1469,7 @@ static struct phy_driver at803x_driver[] - .phy_id_mask = QCA8K_PHY_ID_MASK, - .name = "Qualcomm Atheros 8327-B internal PHY", - /* PHY_GBIT_FEATURES */ -+ .link_change_notify = qca83xx_link_change_notify, - .probe = at803x_probe, - .flags = PHY_IS_INTERNAL, - .config_init = qca83xx_config_init, diff --git a/target/linux/generic/backport-5.10/746-v5.16-03-net-phy-at803x-enable-prefer-master-for-83xx-interna.patch b/target/linux/generic/backport-5.10/746-v5.16-03-net-phy-at803x-enable-prefer-master-for-83xx-interna.patch deleted file mode 100644 index 023d203c46..0000000000 --- a/target/linux/generic/backport-5.10/746-v5.16-03-net-phy-at803x-enable-prefer-master-for-83xx-interna.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 9d1c29b4028557a496be9c5eb2b4b86063700636 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 10 Oct 2021 00:46:17 +0200 -Subject: net: phy: at803x: enable prefer master for 83xx internal phy - -From original QCA source code the port was set to prefer master as port -type in 1000BASE-T mode. Apply the same settings also here. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -1261,6 +1261,9 @@ static int qca83xx_config_init(struct ph - at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, - QCA8327_DEBUG_MANU_CTRL_EN, 0); - -+ /* Following original QCA sourcecode set port to prefer master */ -+ phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER); -+ - return 0; - } - diff --git a/target/linux/generic/backport-5.10/746-v5.16-04-net-phy-at803x-better-describe-debug-regs.patch b/target/linux/generic/backport-5.10/746-v5.16-04-net-phy-at803x-better-describe-debug-regs.patch deleted file mode 100644 index f54dc4276a..0000000000 --- a/target/linux/generic/backport-5.10/746-v5.16-04-net-phy-at803x-better-describe-debug-regs.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 67999555ff42e91de7654488d9a7735bd9e84555 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 10 Oct 2021 00:46:18 +0200 -Subject: net: phy: at803x: better describe debug regs - -Give a name to known debug regs from Documentation instead of using -unknown hex values. - -Signed-off-by: Ansuel Smith -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 30 +++++++++++++++--------------- - 1 file changed, 15 insertions(+), 15 deletions(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -86,12 +86,12 @@ - #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ - #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 - --#define AT803X_DEBUG_REG_0 0x00 -+#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00 - #define QCA8327_DEBUG_MANU_CTRL_EN BIT(2) - #define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2) - #define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15) - --#define AT803X_DEBUG_REG_5 0x05 -+#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05 - #define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8) - - #define AT803X_DEBUG_REG_HIB_CTRL 0x0b -@@ -100,7 +100,7 @@ - - #define AT803X_DEBUG_REG_3C 0x3C - --#define AT803X_DEBUG_REG_3D 0x3D -+#define AT803X_DEBUG_REG_GREEN 0x3D - #define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6) - - #define AT803X_DEBUG_REG_1F 0x1F -@@ -274,25 +274,25 @@ static int at803x_read_page(struct phy_d - - static int at803x_enable_rx_delay(struct phy_device *phydev) - { -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0, - AT803X_DEBUG_RX_CLK_DLY_EN); - } - - static int at803x_enable_tx_delay(struct phy_device *phydev) - { -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0, - AT803X_DEBUG_TX_CLK_DLY_EN); - } - - static int at803x_disable_rx_delay(struct phy_device *phydev) - { -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, - AT803X_DEBUG_RX_CLK_DLY_EN, 0); - } - - static int at803x_disable_tx_delay(struct phy_device *phydev) - { -- return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, -+ return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, - AT803X_DEBUG_TX_CLK_DLY_EN, 0); - } - -@@ -1236,9 +1236,9 @@ static int qca83xx_config_init(struct ph - switch (switch_revision) { - case 1: - /* For 100M waveform */ -- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea); - /* Turn on Gigabit clock */ -- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0); - break; - - case 2: -@@ -1246,8 +1246,8 @@ static int qca83xx_config_init(struct ph - fallthrough; - case 4: - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f); -- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860); -- at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860); -+ at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46); - at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000); - break; - } -@@ -1258,7 +1258,7 @@ static int qca83xx_config_init(struct ph - */ - if (phydev->drv->phy_id == QCA8327_A_PHY_ID || - phydev->drv->phy_id == QCA8327_B_PHY_ID) -- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, - QCA8327_DEBUG_MANU_CTRL_EN, 0); - - /* Following original QCA sourcecode set port to prefer master */ -@@ -1276,12 +1276,12 @@ static void qca83xx_link_change_notify(s - /* Set DAC Amplitude adjustment to +6% for 100m on link running */ - if (phydev->state == PHY_RUNNING) { - if (phydev->speed == SPEED_100) -- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, - QCA8327_DEBUG_MANU_CTRL_EN, - QCA8327_DEBUG_MANU_CTRL_EN); - } else { - /* Reset DAC Amplitude adjustment */ -- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, - QCA8327_DEBUG_MANU_CTRL_EN, 0); - } - } -@@ -1328,7 +1328,7 @@ static int qca83xx_suspend(struct phy_de - phy_modify(phydev, MII_BMCR, mask, 0); - } - -- at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D, -+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN, - AT803X_DEBUG_GATE_CLK_IN1000, 0); - - at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL, diff --git a/target/linux/generic/backport-5.10/747-v5.16-01-dsa-qca8k-add-mac-power-sel-support.patch b/target/linux/generic/backport-5.10/747-v5.16-01-dsa-qca8k-add-mac-power-sel-support.patch deleted file mode 100644 index c8d424de38..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-01-dsa-qca8k-add-mac-power-sel-support.patch +++ /dev/null @@ -1,80 +0,0 @@ -From d8b6f5bae6d3b648a67b6958cb98e4e97256d652 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:06 +0200 -Subject: dsa: qca8k: add mac_power_sel support - -Add missing mac power sel support needed for ipq8064/5 SoC that require -1.8v for the internal regulator port instead of the default 1.5v. -If other device needs this, consider adding a dedicated binding to -support this. - -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 31 +++++++++++++++++++++++++++++++ - drivers/net/dsa/qca8k.h | 5 +++++ - 2 files changed, 36 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -951,6 +951,33 @@ qca8k_setup_of_rgmii_delay(struct qca8k_ - } - - static int -+qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) -+{ -+ u32 mask = 0; -+ int ret = 0; -+ -+ /* SoC specific settings for ipq8064. -+ * If more device require this consider adding -+ * a dedicated binding. -+ */ -+ if (of_machine_is_compatible("qcom,ipq8064")) -+ mask |= QCA8K_MAC_PWR_RGMII0_1_8V; -+ -+ /* SoC specific settings for ipq8065 */ -+ if (of_machine_is_compatible("qcom,ipq8065")) -+ mask |= QCA8K_MAC_PWR_RGMII1_1_8V; -+ -+ if (mask) { -+ ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL, -+ QCA8K_MAC_PWR_RGMII0_1_8V | -+ QCA8K_MAC_PWR_RGMII1_1_8V, -+ mask); -+ } -+ -+ return ret; -+} -+ -+static int - qca8k_setup(struct dsa_switch *ds) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; -@@ -979,6 +1006,10 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - return ret; - -+ ret = qca8k_setup_mac_pwr_sel(priv); -+ if (ret) -+ return ret; -+ - /* Enable CPU Port */ - ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, - QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -100,6 +100,11 @@ - #define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22) - #define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22) - -+/* MAC_PWR_SEL registers */ -+#define QCA8K_REG_MAC_PWR_SEL 0x0e4 -+#define QCA8K_MAC_PWR_RGMII1_1_8V BIT(18) -+#define QCA8K_MAC_PWR_RGMII0_1_8V BIT(19) -+ - /* EEE control registers */ - #define QCA8K_REG_EEE_CTRL 0x100 - #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2) diff --git a/target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch b/target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch deleted file mode 100644 index bd768ec27d..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch +++ /dev/null @@ -1,30 +0,0 @@ -From fdbf35df9c091db9c46e57e9938e3f7a4f603a7c Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:07 +0200 -Subject: dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties - -Add names and descriptions of additional PORT0_PAD_CTRL properties. -qca,sgmii-(rx|tx)clk-falling-edge are for setting the respective clock -phase to failling edge. - -Co-developed-by: Matthew Hagan -Signed-off-by: Matthew Hagan -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - Documentation/devicetree/bindings/net/dsa/qca8k.txt | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt -+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt -@@ -37,6 +37,10 @@ A CPU port node has the following option - managed entity. See - Documentation/devicetree/bindings/net/fixed-link.txt - for details. -+- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge. -+ Mostly used in qca8327 with CPU port 0 set to -+ sgmii. -+- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. - - For QCA8K the 'fixed-link' sub-node supports only the following properties: - diff --git a/target/linux/generic/backport-5.10/747-v5.16-03-net-dsa-qca8k-add-support-for-sgmii-falling-edge.patch b/target/linux/generic/backport-5.10/747-v5.16-03-net-dsa-qca8k-add-support-for-sgmii-falling-edge.patch deleted file mode 100644 index e464452d82..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-03-net-dsa-qca8k-add-support-for-sgmii-falling-edge.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 6c43809bf1bee76c434e365a26546a92a5fbec14 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:08 +0200 -Subject: net: dsa: qca8k: add support for sgmii falling edge - -Add support for this in the qca8k driver. Also add support for SGMII -rx/tx clock falling edge. This is only present for pad0, pad5 and -pad6 have these bit reserved from Documentation. Add a comment that this -is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and -setting falling in port0 applies to both configuration with sgmii used -for port0 or port6. - -Co-developed-by: Matthew Hagan -Signed-off-by: Matthew Hagan -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++ - drivers/net/dsa/qca8k.h | 4 ++++ - 2 files changed, 67 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -978,6 +978,42 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri - } - - static int -+qca8k_parse_port_config(struct qca8k_priv *priv) -+{ -+ struct device_node *port_dn; -+ phy_interface_t mode; -+ struct dsa_port *dp; -+ int port, ret; -+ -+ /* We have 2 CPU port. Check them */ -+ for (port = 0; port < QCA8K_NUM_PORTS; port++) { -+ /* Skip every other port */ -+ if (port != 0 && port != 6) -+ continue; -+ -+ dp = dsa_to_port(priv->ds, port); -+ port_dn = dp->dn; -+ -+ if (!of_device_is_available(port_dn)) -+ continue; -+ -+ ret = of_get_phy_mode(port_dn, &mode); -+ if (ret) -+ continue; -+ -+ if (mode == PHY_INTERFACE_MODE_SGMII) { -+ if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) -+ priv->sgmii_tx_clk_falling_edge = true; -+ -+ if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) -+ priv->sgmii_rx_clk_falling_edge = true; -+ } -+ } -+ -+ return 0; -+} -+ -+static int - qca8k_setup(struct dsa_switch *ds) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; -@@ -990,6 +1026,11 @@ qca8k_setup(struct dsa_switch *ds) - return -EINVAL; - } - -+ /* Parse CPU port config to be later used in phy_link mac_config */ -+ ret = qca8k_parse_port_config(priv); -+ if (ret) -+ return ret; -+ - mutex_init(&priv->reg_mutex); - - /* Start by setting up the register mapping */ -@@ -1274,6 +1315,28 @@ qca8k_phylink_mac_config(struct dsa_swit - } - - qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val); -+ -+ /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and -+ * falling edge is set writing in the PORT0 PAD reg -+ */ -+ if (priv->switch_id == QCA8K_ID_QCA8327 || -+ priv->switch_id == QCA8K_ID_QCA8337) -+ reg = QCA8K_REG_PORT0_PAD_CTRL; -+ -+ val = 0; -+ -+ /* SGMII Clock phase configuration */ -+ if (priv->sgmii_rx_clk_falling_edge) -+ val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE; -+ -+ if (priv->sgmii_tx_clk_falling_edge) -+ val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE; -+ -+ if (val) -+ ret = qca8k_rmw(priv, reg, -+ QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE | -+ QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE, -+ val); - break; - default: - dev_err(ds->dev, "xMII mode %s not supported for port %d\n", ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -35,6 +35,8 @@ - #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) - #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) - #define QCA8K_REG_PORT0_PAD_CTRL 0x004 -+#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19) -+#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18) - #define QCA8K_REG_PORT5_PAD_CTRL 0x008 - #define QCA8K_REG_PORT6_PAD_CTRL 0x00c - #define QCA8K_PORT_PAD_RGMII_EN BIT(26) -@@ -260,6 +262,8 @@ struct qca8k_priv { - u8 switch_revision; - u8 rgmii_tx_delay; - u8 rgmii_rx_delay; -+ bool sgmii_rx_clk_falling_edge; -+ bool sgmii_tx_clk_falling_edge; - bool legacy_phy_port_mapping; - struct regmap *regmap; - struct mii_bus *bus; diff --git a/target/linux/generic/backport-5.10/747-v5.16-04-dt-bindings-net-dsa-qca8k-Document-support-for-CPU-p.patch b/target/linux/generic/backport-5.10/747-v5.16-04-dt-bindings-net-dsa-qca8k-Document-support-for-CPU-p.patch deleted file mode 100644 index 606ac0af3d..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-04-dt-bindings-net-dsa-qca8k-Document-support-for-CPU-p.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 731d613338ec6de482053ffa3f71be2325b0f8eb Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:09 +0200 -Subject: dt-bindings: net: dsa: qca8k: Document support for CPU port 6 - -The switch now support CPU port to be set 6 instead of be hardcoded to -0. Document support for it and describe logic selection. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - Documentation/devicetree/bindings/net/dsa/qca8k.txt | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt -+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt -@@ -29,7 +29,11 @@ the mdio MASTER is used as communication - Don't use mixed external and internal mdio-bus configurations, as this is - not supported by the hardware. - --The CPU port of this switch is always port 0. -+This switch support 2 CPU port. Normally and advised configuration is with -+CPU port set to port 0. It is also possible to set the CPU port to port 6 -+if the device requires it. The driver will configure the switch to the defined -+port. With both CPU port declared the first CPU port is selected as primary -+and the secondary CPU ignored. - - A CPU port node has the following optional node: - diff --git a/target/linux/generic/backport-5.10/747-v5.16-05-net-dsa-qca8k-add-support-for-cpu-port-6.patch b/target/linux/generic/backport-5.10/747-v5.16-05-net-dsa-qca8k-add-support-for-cpu-port-6.patch deleted file mode 100644 index 320db8fa9f..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-05-net-dsa-qca8k-add-support-for-cpu-port-6.patch +++ /dev/null @@ -1,153 +0,0 @@ -From 3fcf734aa482487df83cf8f18608438fcf59127f Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:10 +0200 -Subject: net: dsa: qca8k: add support for cpu port 6 - -Currently CPU port is always hardcoded to port 0. This switch have 2 CPU -ports. The original intention of this driver seems to be use the -mac06_exchange bit to swap MAC0 with MAC6 in the strange configuration -where device have connected only the CPU port 6. To skip the -introduction of a new binding, rework the driver to address the -secondary CPU port as primary and drop any reference of hardcoded port. -With configuration of mac06 exchange, just skip the definition of port0 -and define the CPU port as a secondary. The driver will autoconfigure -the switch to use that as the primary CPU port. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 51 ++++++++++++++++++++++++++++++++++--------------- - drivers/net/dsa/qca8k.h | 2 -- - 2 files changed, 36 insertions(+), 17 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -977,6 +977,22 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri - return ret; - } - -+static int qca8k_find_cpu_port(struct dsa_switch *ds) -+{ -+ struct qca8k_priv *priv = ds->priv; -+ -+ /* Find the connected cpu port. Valid port are 0 or 6 */ -+ if (dsa_is_cpu_port(ds, 0)) -+ return 0; -+ -+ dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); -+ -+ if (dsa_is_cpu_port(ds, 6)) -+ return 6; -+ -+ return -EINVAL; -+} -+ - static int - qca8k_parse_port_config(struct qca8k_priv *priv) - { -@@ -1017,13 +1033,13 @@ static int - qca8k_setup(struct dsa_switch *ds) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; -- int ret, i; -+ int cpu_port, ret, i; - u32 mask; - -- /* Make sure that port 0 is the cpu port */ -- if (!dsa_is_cpu_port(ds, 0)) { -- dev_err(priv->dev, "port 0 is not the CPU port"); -- return -EINVAL; -+ cpu_port = qca8k_find_cpu_port(ds); -+ if (cpu_port < 0) { -+ dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6"); -+ return cpu_port; - } - - /* Parse CPU port config to be later used in phy_link mac_config */ -@@ -1065,7 +1081,7 @@ qca8k_setup(struct dsa_switch *ds) - dev_warn(priv->dev, "mib init failed"); - - /* Enable QCA header mode on the cpu port */ -- ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), -+ ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(cpu_port), - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); - if (ret) { -@@ -1087,10 +1103,10 @@ qca8k_setup(struct dsa_switch *ds) - - /* Forward all unknown frames to CPU port for Linux processing */ - ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, -- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | -- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | -- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | -- BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); -+ BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | -+ BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | -+ BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | -+ BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); - if (ret) - return ret; - -@@ -1098,7 +1114,7 @@ qca8k_setup(struct dsa_switch *ds) - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - /* CPU port gets connected to all user ports of the switch */ - if (dsa_is_cpu_port(ds, i)) { -- ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT), -+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port), - QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); - if (ret) - return ret; -@@ -1110,7 +1126,7 @@ qca8k_setup(struct dsa_switch *ds) - - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, -- BIT(QCA8K_CPU_PORT)); -+ BIT(cpu_port)); - if (ret) - return ret; - -@@ -1616,9 +1632,12 @@ static int - qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; -- int port_mask = BIT(QCA8K_CPU_PORT); -+ int port_mask, cpu_port; - int i, ret; - -+ cpu_port = dsa_to_port(ds, port)->cpu_dp->index; -+ port_mask = BIT(cpu_port); -+ - for (i = 1; i < QCA8K_NUM_PORTS; i++) { - if (dsa_to_port(ds, i)->bridge_dev != br) - continue; -@@ -1645,7 +1664,9 @@ static void - qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; -- int i; -+ int cpu_port, i; -+ -+ cpu_port = dsa_to_port(ds, port)->cpu_dp->index; - - for (i = 1; i < QCA8K_NUM_PORTS; i++) { - if (dsa_to_port(ds, i)->bridge_dev != br) -@@ -1662,7 +1683,7 @@ qca8k_port_bridge_leave(struct dsa_switc - * this port - */ - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), -- QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT)); -+ QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); - } - - static int ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -24,8 +24,6 @@ - - #define QCA8K_NUM_FDB_RECORDS 2048 - --#define QCA8K_CPU_PORT 0 -- - #define QCA8K_PORT_VID_DEF 1 - - /* Global control registers */ diff --git a/target/linux/generic/backport-5.10/747-v5.16-06-net-dsa-qca8k-rework-rgmii-delay-logic-and-scan-for-.patch b/target/linux/generic/backport-5.10/747-v5.16-06-net-dsa-qca8k-rework-rgmii-delay-logic-and-scan-for-.patch deleted file mode 100644 index de201764f9..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-06-net-dsa-qca8k-rework-rgmii-delay-logic-and-scan-for-.patch +++ /dev/null @@ -1,295 +0,0 @@ -From 5654ec78dd7e64b1e04777b24007344329e6a63b Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:11 +0200 -Subject: net: dsa: qca8k: rework rgmii delay logic and scan for cpu port 6 - -Future proof commit. This switch have 2 CPU ports and one valid -configuration is first CPU port set to sgmii and second CPU port set to -rgmii-id. The current implementation detects delay only for CPU port -zero set to rgmii and doesn't count any delay set in a secondary CPU -port. Drop the current delay scan function and move it to the sgmii -parser function to generalize and implicitly add support for secondary -CPU port set to rgmii-id. Introduce new logic where delay is enabled -also with internal delay binding declared and rgmii set as PHY mode. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 165 ++++++++++++++++++++++++------------------------ - drivers/net/dsa/qca8k.h | 10 ++- - 2 files changed, 89 insertions(+), 86 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -889,68 +889,6 @@ qca8k_setup_mdio_bus(struct qca8k_priv * - } - - static int --qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv) --{ -- struct device_node *port_dn; -- phy_interface_t mode; -- struct dsa_port *dp; -- u32 val; -- -- /* CPU port is already checked */ -- dp = dsa_to_port(priv->ds, 0); -- -- port_dn = dp->dn; -- -- /* Check if port 0 is set to the correct type */ -- of_get_phy_mode(port_dn, &mode); -- if (mode != PHY_INTERFACE_MODE_RGMII_ID && -- mode != PHY_INTERFACE_MODE_RGMII_RXID && -- mode != PHY_INTERFACE_MODE_RGMII_TXID) { -- return 0; -- } -- -- switch (mode) { -- case PHY_INTERFACE_MODE_RGMII_ID: -- case PHY_INTERFACE_MODE_RGMII_RXID: -- if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val)) -- val = 2; -- else -- /* Switch regs accept value in ns, convert ps to ns */ -- val = val / 1000; -- -- if (val > QCA8K_MAX_DELAY) { -- dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); -- val = 3; -- } -- -- priv->rgmii_rx_delay = val; -- /* Stop here if we need to check only for rx delay */ -- if (mode != PHY_INTERFACE_MODE_RGMII_ID) -- break; -- -- fallthrough; -- case PHY_INTERFACE_MODE_RGMII_TXID: -- if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val)) -- val = 1; -- else -- /* Switch regs accept value in ns, convert ps to ns */ -- val = val / 1000; -- -- if (val > QCA8K_MAX_DELAY) { -- dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); -- val = 3; -- } -- -- priv->rgmii_tx_delay = val; -- break; -- default: -- return 0; -- } -- -- return 0; --} -- --static int - qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) - { - u32 mask = 0; -@@ -996,19 +934,21 @@ static int qca8k_find_cpu_port(struct ds - static int - qca8k_parse_port_config(struct qca8k_priv *priv) - { -+ int port, cpu_port_index = 0, ret; - struct device_node *port_dn; - phy_interface_t mode; - struct dsa_port *dp; -- int port, ret; -+ u32 delay; - - /* We have 2 CPU port. Check them */ -- for (port = 0; port < QCA8K_NUM_PORTS; port++) { -+ for (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) { - /* Skip every other port */ - if (port != 0 && port != 6) - continue; - - dp = dsa_to_port(priv->ds, port); - port_dn = dp->dn; -+ cpu_port_index++; - - if (!of_device_is_available(port_dn)) - continue; -@@ -1017,12 +957,54 @@ qca8k_parse_port_config(struct qca8k_pri - if (ret) - continue; - -- if (mode == PHY_INTERFACE_MODE_SGMII) { -+ switch (mode) { -+ case PHY_INTERFACE_MODE_RGMII: -+ case PHY_INTERFACE_MODE_RGMII_ID: -+ case PHY_INTERFACE_MODE_RGMII_TXID: -+ case PHY_INTERFACE_MODE_RGMII_RXID: -+ delay = 0; -+ -+ if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) -+ /* Switch regs accept value in ns, convert ps to ns */ -+ delay = delay / 1000; -+ else if (mode == PHY_INTERFACE_MODE_RGMII_ID || -+ mode == PHY_INTERFACE_MODE_RGMII_TXID) -+ delay = 1; -+ -+ if (delay > QCA8K_MAX_DELAY) { -+ dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); -+ delay = 3; -+ } -+ -+ priv->rgmii_tx_delay[cpu_port_index] = delay; -+ -+ delay = 0; -+ -+ if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) -+ /* Switch regs accept value in ns, convert ps to ns */ -+ delay = delay / 1000; -+ else if (mode == PHY_INTERFACE_MODE_RGMII_ID || -+ mode == PHY_INTERFACE_MODE_RGMII_RXID) -+ delay = 2; -+ -+ if (delay > QCA8K_MAX_DELAY) { -+ dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); -+ delay = 3; -+ } -+ -+ priv->rgmii_rx_delay[cpu_port_index] = delay; -+ -+ break; -+ case PHY_INTERFACE_MODE_SGMII: - if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) - priv->sgmii_tx_clk_falling_edge = true; - - if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) - priv->sgmii_rx_clk_falling_edge = true; -+ -+ break; -+ default: -+ continue; - } - } - -@@ -1059,10 +1041,6 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - return ret; - -- ret = qca8k_setup_of_rgmii_delay(priv); -- if (ret) -- return ret; -- - ret = qca8k_setup_mac_pwr_sel(priv); - if (ret) - return ret; -@@ -1229,8 +1207,8 @@ qca8k_phylink_mac_config(struct dsa_swit - const struct phylink_link_state *state) - { - struct qca8k_priv *priv = ds->priv; -- u32 reg, val; -- int ret; -+ int cpu_port_index, ret; -+ u32 reg, val, delay; - - switch (port) { - case 0: /* 1st CPU port */ -@@ -1242,6 +1220,7 @@ qca8k_phylink_mac_config(struct dsa_swit - return; - - reg = QCA8K_REG_PORT0_PAD_CTRL; -+ cpu_port_index = QCA8K_CPU_PORT0; - break; - case 1: - case 2: -@@ -1260,6 +1239,7 @@ qca8k_phylink_mac_config(struct dsa_swit - return; - - reg = QCA8K_REG_PORT6_PAD_CTRL; -+ cpu_port_index = QCA8K_CPU_PORT6; - break; - default: - dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); -@@ -1274,23 +1254,40 @@ qca8k_phylink_mac_config(struct dsa_swit - - switch (state->interface) { - case PHY_INTERFACE_MODE_RGMII: -- /* RGMII mode means no delay so don't enable the delay */ -- qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN); -- break; - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: -- /* RGMII_ID needs internal delay. This is enabled through -- * PORT5_PAD_CTRL for all ports, rather than individual port -- * registers -+ val = QCA8K_PORT_PAD_RGMII_EN; -+ -+ /* Delay can be declared in 3 different way. -+ * Mode to rgmii and internal-delay standard binding defined -+ * rgmii-id or rgmii-tx/rx phy mode set. -+ * The parse logic set a delay different than 0 only when one -+ * of the 3 different way is used. In all other case delay is -+ * not enabled. With ID or TX/RXID delay is enabled and set -+ * to the default and recommended value. -+ */ -+ if (priv->rgmii_tx_delay[cpu_port_index]) { -+ delay = priv->rgmii_tx_delay[cpu_port_index]; -+ -+ val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | -+ QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; -+ } -+ -+ if (priv->rgmii_rx_delay[cpu_port_index]) { -+ delay = priv->rgmii_rx_delay[cpu_port_index]; -+ -+ val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | -+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; -+ } -+ -+ /* Set RGMII delay based on the selected values */ -+ qca8k_write(priv, reg, val); -+ -+ /* QCA8337 requires to set rgmii rx delay for all ports. -+ * This is enabled through PORT5_PAD_CTRL for all ports, -+ * rather than individual port registers. - */ -- qca8k_write(priv, reg, -- QCA8K_PORT_PAD_RGMII_EN | -- QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) | -- QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) | -- QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | -- QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); -- /* QCA8337 requires to set rgmii rx delay */ - if (priv->switch_id == QCA8K_ID_QCA8337) - qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -13,6 +13,7 @@ - #include - - #define QCA8K_NUM_PORTS 7 -+#define QCA8K_NUM_CPU_PORTS 2 - #define QCA8K_MAX_MTU 9000 - - #define PHY_ID_QCA8327 0x004dd034 -@@ -255,13 +256,18 @@ struct qca8k_match_data { - u8 id; - }; - -+enum { -+ QCA8K_CPU_PORT0, -+ QCA8K_CPU_PORT6, -+}; -+ - struct qca8k_priv { - u8 switch_id; - u8 switch_revision; -- u8 rgmii_tx_delay; -- u8 rgmii_rx_delay; - bool sgmii_rx_clk_falling_edge; - bool sgmii_tx_clk_falling_edge; -+ u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */ -+ u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */ - bool legacy_phy_port_mapping; - struct regmap *regmap; - struct mii_bus *bus; diff --git a/target/linux/generic/backport-5.10/747-v5.16-07-dt-bindings-net-dsa-qca8k-Document-qca-sgmii-enable-.patch b/target/linux/generic/backport-5.10/747-v5.16-07-dt-bindings-net-dsa-qca8k-Document-qca-sgmii-enable-.patch deleted file mode 100644 index 8abd264e79..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-07-dt-bindings-net-dsa-qca8k-Document-qca-sgmii-enable-.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 13ad5ccc093ff448b99ac7e138e91e78796adb48 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:12 +0200 -Subject: dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll - -Document qca,sgmii-enable-pll binding used in the CPU nodes to -enable SGMII PLL on MAC config. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - Documentation/devicetree/bindings/net/dsa/qca8k.txt | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt -+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt -@@ -45,6 +45,16 @@ A CPU port node has the following option - Mostly used in qca8327 with CPU port 0 set to - sgmii. - - qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. -+- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX -+ chain along with Signal Detection. -+ This should NOT be enabled for qca8327. If enabled with -+ qca8327 the sgmii port won't correctly init and an err -+ is printed. -+ This can be required for qca8337 switch with revision 2. -+ A warning is displayed when used with revision greater -+ 2. -+ With CPU port set to sgmii and qca8337 it is advised -+ to set this unless a communication problem is observed. - - For QCA8K the 'fixed-link' sub-node supports only the following properties: - diff --git a/target/linux/generic/backport-5.10/747-v5.16-08-net-dsa-qca8k-add-explicit-SGMII-PLL-enable.patch b/target/linux/generic/backport-5.10/747-v5.16-08-net-dsa-qca8k-add-explicit-SGMII-PLL-enable.patch deleted file mode 100644 index 2b5a84a1b0..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-08-net-dsa-qca8k-add-explicit-SGMII-PLL-enable.patch +++ /dev/null @@ -1,65 +0,0 @@ -From bbc4799e8bb6c397e3b3fec13de68e179f5db9ff Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:13 +0200 -Subject: net: dsa: qca8k: add explicit SGMII PLL enable - -Support enabling PLL on the SGMII CPU port. Some device require this -special configuration or no traffic is transmitted and the switch -doesn't work at all. A dedicated binding is added to the CPU node -port to apply the correct reg on mac config. -Fail to correctly configure sgmii with qca8327 switch and warn if pll is -used on qca8337 with a revision greater than 1. - -Signed-off-by: Ansuel Smith -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 19 +++++++++++++++++-- - drivers/net/dsa/qca8k.h | 1 + - 2 files changed, 18 insertions(+), 2 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1002,6 +1002,18 @@ qca8k_parse_port_config(struct qca8k_pri - if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) - priv->sgmii_rx_clk_falling_edge = true; - -+ if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) { -+ priv->sgmii_enable_pll = true; -+ -+ if (priv->switch_id == QCA8K_ID_QCA8327) { -+ dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling"); -+ priv->sgmii_enable_pll = false; -+ } -+ -+ if (priv->switch_revision < 2) -+ dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more."); -+ } -+ - break; - default: - continue; -@@ -1312,8 +1324,11 @@ qca8k_phylink_mac_config(struct dsa_swit - if (ret) - return; - -- val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | -- QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD; -+ val |= QCA8K_SGMII_EN_SD; -+ -+ if (priv->sgmii_enable_pll) -+ val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | -+ QCA8K_SGMII_EN_TX; - - if (dsa_is_cpu_port(ds, port)) { - /* CPU port, we're talking to the CPU MAC, be a PHY */ ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -266,6 +266,7 @@ struct qca8k_priv { - u8 switch_revision; - bool sgmii_rx_clk_falling_edge; - bool sgmii_tx_clk_falling_edge; -+ bool sgmii_enable_pll; - u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */ - u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */ - bool legacy_phy_port_mapping; diff --git a/target/linux/generic/backport-5.10/747-v5.16-09-dt-bindings-net-dsa-qca8k-Document-qca-led-open-drai.patch b/target/linux/generic/backport-5.10/747-v5.16-09-dt-bindings-net-dsa-qca8k-Document-qca-led-open-drai.patch deleted file mode 100644 index 38dc954e8c..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-09-dt-bindings-net-dsa-qca8k-Document-qca-led-open-drai.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 924087c5c3d41553700b0eb83ca2a53b91643dca Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:14 +0200 -Subject: dt-bindings: net: dsa: qca8k: Document qca,led-open-drain binding - -Document new binding qca,ignore-power-on-sel used to ignore -power on strapping and use sw regs instead. -Document qca,led-open.drain to set led to open drain mode, the -qca,ignore-power-on-sel is mandatory with this enabled or an error will -be reported. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - Documentation/devicetree/bindings/net/dsa/qca8k.txt | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt -+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt -@@ -13,6 +13,17 @@ Required properties: - Optional properties: - - - reset-gpios: GPIO to be used to reset the whole device -+- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open -+ drain or eeprom presence. This is needed for broken -+ devices that have wrong configuration or when the oem -+ decided to not use pin strapping and fallback to sw -+ regs. -+- qca,led-open-drain: Set leds to open-drain mode. This requires the -+ qca,ignore-power-on-sel to be set or the driver will fail -+ to probe. This is needed if the oem doesn't use pin -+ strapping to set this mode and prefers to set it using sw -+ regs. The pin strapping related to led open drain mode is -+ the pin B68 for QCA832x and B49 for QCA833x - - Subnodes: - diff --git a/target/linux/generic/backport-5.10/747-v5.16-10-net-dsa-qca8k-add-support-for-pws-config-reg.patch b/target/linux/generic/backport-5.10/747-v5.16-10-net-dsa-qca8k-add-support-for-pws-config-reg.patch deleted file mode 100644 index aa5d92a4fd..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-10-net-dsa-qca8k-add-support-for-pws-config-reg.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 362bb238d8bf1470424214a8a5968d9c6cce68fa Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:15 +0200 -Subject: net: dsa: qca8k: add support for pws config reg - -Some qca8327 switch require to force the ignore of power on sel -strapping. Some switch require to set the led open drain mode in regs -instead of using strapping. While most of the device implements this -using the correct way using pin strapping, there are still some broken -device that require to be set using sw regs. -Introduce a new binding and support these special configuration. -As led open drain require to ignore pin strapping to work, the probe -fails with EINVAL error with incorrect configuration. - -Signed-off-by: Ansuel Smith -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 39 +++++++++++++++++++++++++++++++++++++++ - drivers/net/dsa/qca8k.h | 6 ++++++ - 2 files changed, 45 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -932,6 +932,41 @@ static int qca8k_find_cpu_port(struct ds - } - - static int -+qca8k_setup_of_pws_reg(struct qca8k_priv *priv) -+{ -+ struct device_node *node = priv->dev->of_node; -+ u32 val = 0; -+ int ret; -+ -+ /* QCA8327 require to set to the correct mode. -+ * His bigger brother QCA8328 have the 172 pin layout. -+ * Should be applied by default but we set this just to make sure. -+ */ -+ if (priv->switch_id == QCA8K_ID_QCA8327) { -+ ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN, -+ QCA8327_PWS_PACKAGE148_EN); -+ if (ret) -+ return ret; -+ } -+ -+ if (of_property_read_bool(node, "qca,ignore-power-on-sel")) -+ val |= QCA8K_PWS_POWER_ON_SEL; -+ -+ if (of_property_read_bool(node, "qca,led-open-drain")) { -+ if (!(val & QCA8K_PWS_POWER_ON_SEL)) { -+ dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set."); -+ return -EINVAL; -+ } -+ -+ val |= QCA8K_PWS_LED_OPEN_EN_CSR; -+ } -+ -+ return qca8k_rmw(priv, QCA8K_REG_PWS, -+ QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL, -+ val); -+} -+ -+static int - qca8k_parse_port_config(struct qca8k_priv *priv) - { - int port, cpu_port_index = 0, ret; -@@ -1053,6 +1088,10 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - return ret; - -+ ret = qca8k_setup_of_pws_reg(priv); -+ if (ret) -+ return ret; -+ - ret = qca8k_setup_mac_pwr_sel(priv); - if (ret) - return ret; ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -46,6 +46,12 @@ - #define QCA8K_MAX_DELAY 3 - #define QCA8K_PORT_PAD_SGMII_EN BIT(7) - #define QCA8K_REG_PWS 0x010 -+#define QCA8K_PWS_POWER_ON_SEL BIT(31) -+/* This reg is only valid for QCA832x and toggle the package -+ * type from 176 pin (by default) to 148 pin used on QCA8327 -+ */ -+#define QCA8327_PWS_PACKAGE148_EN BIT(30) -+#define QCA8K_PWS_LED_OPEN_EN_CSR BIT(24) - #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) - #define QCA8K_REG_MODULE_EN 0x030 - #define QCA8K_MODULE_EN_MIB BIT(0) diff --git a/target/linux/generic/backport-5.10/747-v5.16-11-dt-bindings-net-dsa-qca8k-document-support-for-qca83.patch b/target/linux/generic/backport-5.10/747-v5.16-11-dt-bindings-net-dsa-qca8k-document-support-for-qca83.patch deleted file mode 100644 index 1bfb00c5b2..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-11-dt-bindings-net-dsa-qca8k-document-support-for-qca83.patch +++ /dev/null @@ -1,32 +0,0 @@ -From ed7988d77fbfb79366b68f9e7fa60a6080da23d4 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:16 +0200 -Subject: dt-bindings: net: dsa: qca8k: document support for qca8328 - -QCA8328 is the bigger brother of qca8327. Document the new compatible -binding and add some information to understand the various switch -compatible. - -Signed-off-by: Ansuel Smith -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - Documentation/devicetree/bindings/net/dsa/qca8k.txt | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - ---- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt -+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt -@@ -3,9 +3,10 @@ - Required properties: - - - compatible: should be one of: -- "qca,qca8327" -- "qca,qca8334" -- "qca,qca8337" -+ "qca,qca8328": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package -+ "qca,qca8327": referenced as AR8327(N)-AL1A DR-QFN 148 pin package -+ "qca,qca8334": referenced as QCA8334-AL3C QFN 88 pin package -+ "qca,qca8337": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package - - - #size-cells: must be 0 - - #address-cells: must be 1 diff --git a/target/linux/generic/backport-5.10/747-v5.16-12-net-dsa-qca8k-add-support-for-QCA8328.patch b/target/linux/generic/backport-5.10/747-v5.16-12-net-dsa-qca8k-add-support-for-QCA8328.patch deleted file mode 100644 index 6e118f5a14..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-12-net-dsa-qca8k-add-support-for-QCA8328.patch +++ /dev/null @@ -1,78 +0,0 @@ -From f477d1c8bdbef4f400718238e350f16f521d2a3e Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:17 +0200 -Subject: net: dsa: qca8k: add support for QCA8328 - -QCA8328 switch is the bigger brother of the qca8327. Same regs different -chip. Change the function to set the correct pin layout and introduce a -new match_data to differentiate the 2 switch as they have the same ID -and their internal PHY have the same ID. - -Signed-off-by: Ansuel Smith -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 19 ++++++++++++++++--- - drivers/net/dsa/qca8k.h | 1 + - 2 files changed, 17 insertions(+), 3 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -935,6 +935,7 @@ static int - qca8k_setup_of_pws_reg(struct qca8k_priv *priv) - { - struct device_node *node = priv->dev->of_node; -+ const struct qca8k_match_data *data; - u32 val = 0; - int ret; - -@@ -943,8 +944,14 @@ qca8k_setup_of_pws_reg(struct qca8k_priv - * Should be applied by default but we set this just to make sure. - */ - if (priv->switch_id == QCA8K_ID_QCA8327) { -+ data = of_device_get_match_data(priv->dev); -+ -+ /* Set the correct package of 148 pin for QCA8327 */ -+ if (data->reduced_package) -+ val |= QCA8327_PWS_PACKAGE148_EN; -+ - ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN, -- QCA8327_PWS_PACKAGE148_EN); -+ val); - if (ret) - return ret; - } -@@ -2098,7 +2105,12 @@ static int qca8k_resume(struct device *d - static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, - qca8k_suspend, qca8k_resume); - --static const struct qca8k_match_data qca832x = { -+static const struct qca8k_match_data qca8327 = { -+ .id = QCA8K_ID_QCA8327, -+ .reduced_package = true, -+}; -+ -+static const struct qca8k_match_data qca8328 = { - .id = QCA8K_ID_QCA8327, - }; - -@@ -2107,7 +2119,8 @@ static const struct qca8k_match_data qca - }; - - static const struct of_device_id qca8k_of_match[] = { -- { .compatible = "qca,qca8327", .data = &qca832x }, -+ { .compatible = "qca,qca8327", .data = &qca8327 }, -+ { .compatible = "qca,qca8328", .data = &qca8328 }, - { .compatible = "qca,qca8334", .data = &qca833x }, - { .compatible = "qca,qca8337", .data = &qca833x }, - { /* sentinel */ }, ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -260,6 +260,7 @@ struct ar8xxx_port_status { - - struct qca8k_match_data { - u8 id; -+ bool reduced_package; - }; - - enum { diff --git a/target/linux/generic/backport-5.10/747-v5.16-13-net-dsa-qca8k-set-internal-delay-also-for-sgmii.patch b/target/linux/generic/backport-5.10/747-v5.16-13-net-dsa-qca8k-set-internal-delay-also-for-sgmii.patch deleted file mode 100644 index 27f94dca02..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-13-net-dsa-qca8k-set-internal-delay-also-for-sgmii.patch +++ /dev/null @@ -1,159 +0,0 @@ -From cef08115846e581f80ff99abf7bf218da1840616 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:18 +0200 -Subject: net: dsa: qca8k: set internal delay also for sgmii - -QCA original code report port instability and sa that SGMII also require -to set internal delay. Generalize the rgmii delay function and apply the -advised value if they are not defined in DT. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 88 +++++++++++++++++++++++++++++++++---------------- - drivers/net/dsa/qca8k.h | 2 ++ - 2 files changed, 62 insertions(+), 28 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1004,6 +1004,7 @@ qca8k_parse_port_config(struct qca8k_pri - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: -+ case PHY_INTERFACE_MODE_SGMII: - delay = 0; - - if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) -@@ -1036,8 +1037,13 @@ qca8k_parse_port_config(struct qca8k_pri - - priv->rgmii_rx_delay[cpu_port_index] = delay; - -- break; -- case PHY_INTERFACE_MODE_SGMII: -+ /* Skip sgmii parsing for rgmii* mode */ -+ if (mode == PHY_INTERFACE_MODE_RGMII || -+ mode == PHY_INTERFACE_MODE_RGMII_ID || -+ mode == PHY_INTERFACE_MODE_RGMII_TXID || -+ mode == PHY_INTERFACE_MODE_RGMII_RXID) -+ break; -+ - if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) - priv->sgmii_tx_clk_falling_edge = true; - -@@ -1261,12 +1267,53 @@ qca8k_setup(struct dsa_switch *ds) - } - - static void -+qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index, -+ u32 reg) -+{ -+ u32 delay, val = 0; -+ int ret; -+ -+ /* Delay can be declared in 3 different way. -+ * Mode to rgmii and internal-delay standard binding defined -+ * rgmii-id or rgmii-tx/rx phy mode set. -+ * The parse logic set a delay different than 0 only when one -+ * of the 3 different way is used. In all other case delay is -+ * not enabled. With ID or TX/RXID delay is enabled and set -+ * to the default and recommended value. -+ */ -+ if (priv->rgmii_tx_delay[cpu_port_index]) { -+ delay = priv->rgmii_tx_delay[cpu_port_index]; -+ -+ val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | -+ QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; -+ } -+ -+ if (priv->rgmii_rx_delay[cpu_port_index]) { -+ delay = priv->rgmii_rx_delay[cpu_port_index]; -+ -+ val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | -+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; -+ } -+ -+ /* Set RGMII delay based on the selected values */ -+ ret = qca8k_rmw(priv, reg, -+ QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK | -+ QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK | -+ QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | -+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN, -+ val); -+ if (ret) -+ dev_err(priv->dev, "Failed to set internal delay for CPU port%d", -+ cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6); -+} -+ -+static void - qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, - const struct phylink_link_state *state) - { - struct qca8k_priv *priv = ds->priv; - int cpu_port_index, ret; -- u32 reg, val, delay; -+ u32 reg, val; - - switch (port) { - case 0: /* 1st CPU port */ -@@ -1315,32 +1362,10 @@ qca8k_phylink_mac_config(struct dsa_swit - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: -- val = QCA8K_PORT_PAD_RGMII_EN; -- -- /* Delay can be declared in 3 different way. -- * Mode to rgmii and internal-delay standard binding defined -- * rgmii-id or rgmii-tx/rx phy mode set. -- * The parse logic set a delay different than 0 only when one -- * of the 3 different way is used. In all other case delay is -- * not enabled. With ID or TX/RXID delay is enabled and set -- * to the default and recommended value. -- */ -- if (priv->rgmii_tx_delay[cpu_port_index]) { -- delay = priv->rgmii_tx_delay[cpu_port_index]; -- -- val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | -- QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; -- } -- -- if (priv->rgmii_rx_delay[cpu_port_index]) { -- delay = priv->rgmii_rx_delay[cpu_port_index]; -- -- val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | -- QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; -- } -+ qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN); - -- /* Set RGMII delay based on the selected values */ -- qca8k_write(priv, reg, val); -+ /* Configure rgmii delay */ -+ qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg); - - /* QCA8337 requires to set rgmii rx delay for all ports. - * This is enabled through PORT5_PAD_CTRL for all ports, -@@ -1411,6 +1436,13 @@ qca8k_phylink_mac_config(struct dsa_swit - QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE | - QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE, - val); -+ -+ /* From original code is reported port instability as SGMII also -+ * require delay set. Apply advised values here or take them from DT. -+ */ -+ if (state->interface == PHY_INTERFACE_MODE_SGMII) -+ qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg); -+ - break; - default: - dev_err(ds->dev, "xMII mode %s not supported for port %d\n", ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -39,7 +39,9 @@ - #define QCA8K_REG_PORT5_PAD_CTRL 0x008 - #define QCA8K_REG_PORT6_PAD_CTRL 0x00c - #define QCA8K_PORT_PAD_RGMII_EN BIT(26) -+#define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22) - #define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) -+#define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20) - #define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) - #define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) - #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) diff --git a/target/linux/generic/backport-5.10/747-v5.16-14-net-dsa-qca8k-move-port-config-to-dedicated-struct.patch b/target/linux/generic/backport-5.10/747-v5.16-14-net-dsa-qca8k-move-port-config-to-dedicated-struct.patch deleted file mode 100644 index b991798c87..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-14-net-dsa-qca8k-move-port-config-to-dedicated-struct.patch +++ /dev/null @@ -1,124 +0,0 @@ -From fd0bb28c547f7c8affb1691128cece38f5b626a1 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:19 +0200 -Subject: net: dsa: qca8k: move port config to dedicated struct - -Move ports related config to dedicated struct to keep things organized. - -Signed-off-by: Ansuel Smith -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 26 +++++++++++++------------- - drivers/net/dsa/qca8k.h | 10 +++++++--- - 2 files changed, 20 insertions(+), 16 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1019,7 +1019,7 @@ qca8k_parse_port_config(struct qca8k_pri - delay = 3; - } - -- priv->rgmii_tx_delay[cpu_port_index] = delay; -+ priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay; - - delay = 0; - -@@ -1035,7 +1035,7 @@ qca8k_parse_port_config(struct qca8k_pri - delay = 3; - } - -- priv->rgmii_rx_delay[cpu_port_index] = delay; -+ priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay; - - /* Skip sgmii parsing for rgmii* mode */ - if (mode == PHY_INTERFACE_MODE_RGMII || -@@ -1045,17 +1045,17 @@ qca8k_parse_port_config(struct qca8k_pri - break; - - if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) -- priv->sgmii_tx_clk_falling_edge = true; -+ priv->ports_config.sgmii_tx_clk_falling_edge = true; - - if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) -- priv->sgmii_rx_clk_falling_edge = true; -+ priv->ports_config.sgmii_rx_clk_falling_edge = true; - - if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) { -- priv->sgmii_enable_pll = true; -+ priv->ports_config.sgmii_enable_pll = true; - - if (priv->switch_id == QCA8K_ID_QCA8327) { - dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling"); -- priv->sgmii_enable_pll = false; -+ priv->ports_config.sgmii_enable_pll = false; - } - - if (priv->switch_revision < 2) -@@ -1281,15 +1281,15 @@ qca8k_mac_config_setup_internal_delay(st - * not enabled. With ID or TX/RXID delay is enabled and set - * to the default and recommended value. - */ -- if (priv->rgmii_tx_delay[cpu_port_index]) { -- delay = priv->rgmii_tx_delay[cpu_port_index]; -+ if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) { -+ delay = priv->ports_config.rgmii_tx_delay[cpu_port_index]; - - val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | - QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; - } - -- if (priv->rgmii_rx_delay[cpu_port_index]) { -- delay = priv->rgmii_rx_delay[cpu_port_index]; -+ if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) { -+ delay = priv->ports_config.rgmii_rx_delay[cpu_port_index]; - - val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; -@@ -1397,7 +1397,7 @@ qca8k_phylink_mac_config(struct dsa_swit - - val |= QCA8K_SGMII_EN_SD; - -- if (priv->sgmii_enable_pll) -+ if (priv->ports_config.sgmii_enable_pll) - val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | - QCA8K_SGMII_EN_TX; - -@@ -1425,10 +1425,10 @@ qca8k_phylink_mac_config(struct dsa_swit - val = 0; - - /* SGMII Clock phase configuration */ -- if (priv->sgmii_rx_clk_falling_edge) -+ if (priv->ports_config.sgmii_rx_clk_falling_edge) - val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE; - -- if (priv->sgmii_tx_clk_falling_edge) -+ if (priv->ports_config.sgmii_tx_clk_falling_edge) - val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE; - - if (val) ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -270,15 +270,19 @@ enum { - QCA8K_CPU_PORT6, - }; - --struct qca8k_priv { -- u8 switch_id; -- u8 switch_revision; -+struct qca8k_ports_config { - bool sgmii_rx_clk_falling_edge; - bool sgmii_tx_clk_falling_edge; - bool sgmii_enable_pll; - u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */ - u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */ -+}; -+ -+struct qca8k_priv { -+ u8 switch_id; -+ u8 switch_revision; - bool legacy_phy_port_mapping; -+ struct qca8k_ports_config ports_config; - struct regmap *regmap; - struct mii_bus *bus; - struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; diff --git a/target/linux/generic/backport-5.10/747-v5.16-15-dt-bindings-net-ipq8064-mdio-fix-warning-with-new-qc.patch b/target/linux/generic/backport-5.10/747-v5.16-15-dt-bindings-net-ipq8064-mdio-fix-warning-with-new-qc.patch deleted file mode 100644 index f7cb514176..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-15-dt-bindings-net-ipq8064-mdio-fix-warning-with-new-qc.patch +++ /dev/null @@ -1,26 +0,0 @@ -From e52073a8e3086046a098b8a7cbeb282ff0cdb424 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 14 Oct 2021 00:39:20 +0200 -Subject: dt-bindings: net: ipq8064-mdio: fix warning with new qca8k switch - -Fix warning now that we have qca8k switch Documentation using yaml. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml -+++ b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml -@@ -51,6 +51,9 @@ examples: - switch@10 { - compatible = "qca,qca8337"; - reg = <0x10>; -- /* ... */ -+ -+ ports { -+ /* ... */ -+ }; - }; - }; diff --git a/target/linux/generic/backport-5.10/747-v5.16-16-dt-bindings-net-dsa-qca8k-convert-to-YAML-schema.patch b/target/linux/generic/backport-5.10/747-v5.16-16-dt-bindings-net-dsa-qca8k-convert-to-YAML-schema.patch deleted file mode 100644 index b9bce97dd3..0000000000 --- a/target/linux/generic/backport-5.10/747-v5.16-16-dt-bindings-net-dsa-qca8k-convert-to-YAML-schema.patch +++ /dev/null @@ -1,631 +0,0 @@ -From d291fbb8245d5ba04979fed85575860a5cea7196 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Thu, 14 Oct 2021 00:39:21 +0200 -Subject: dt-bindings: net: dsa: qca8k: convert to YAML schema - -Convert the qca8k bindings to YAML format. - -Signed-off-by: Matthew Hagan -Co-developed-by: Ansuel Smith -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - .../devicetree/bindings/net/dsa/qca8k.txt | 245 -------------- - .../devicetree/bindings/net/dsa/qca8k.yaml | 362 +++++++++++++++++++++ - 2 files changed, 362 insertions(+), 245 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.txt - create mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.yaml - ---- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt -+++ /dev/null -@@ -1,245 +0,0 @@ --* Qualcomm Atheros QCA8xxx switch family -- --Required properties: -- --- compatible: should be one of: -- "qca,qca8328": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package -- "qca,qca8327": referenced as AR8327(N)-AL1A DR-QFN 148 pin package -- "qca,qca8334": referenced as QCA8334-AL3C QFN 88 pin package -- "qca,qca8337": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package -- --- #size-cells: must be 0 --- #address-cells: must be 1 -- --Optional properties: -- --- reset-gpios: GPIO to be used to reset the whole device --- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open -- drain or eeprom presence. This is needed for broken -- devices that have wrong configuration or when the oem -- decided to not use pin strapping and fallback to sw -- regs. --- qca,led-open-drain: Set leds to open-drain mode. This requires the -- qca,ignore-power-on-sel to be set or the driver will fail -- to probe. This is needed if the oem doesn't use pin -- strapping to set this mode and prefers to set it using sw -- regs. The pin strapping related to led open drain mode is -- the pin B68 for QCA832x and B49 for QCA833x -- --Subnodes: -- --The integrated switch subnode should be specified according to the binding --described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external --mdio-bus each subnode describing a port needs to have a valid phandle --referencing the internal PHY it is connected to. This is because there's no --N:N mapping of port and PHY id. --To declare the internal mdio-bus configuration, declare a mdio node in the --switch node and declare the phandle for the port referencing the internal --PHY is connected to. In this config a internal mdio-bus is registered and --the mdio MASTER is used as communication. -- --Don't use mixed external and internal mdio-bus configurations, as this is --not supported by the hardware. -- --This switch support 2 CPU port. Normally and advised configuration is with --CPU port set to port 0. It is also possible to set the CPU port to port 6 --if the device requires it. The driver will configure the switch to the defined --port. With both CPU port declared the first CPU port is selected as primary --and the secondary CPU ignored. -- --A CPU port node has the following optional node: -- --- fixed-link : Fixed-link subnode describing a link to a non-MDIO -- managed entity. See -- Documentation/devicetree/bindings/net/fixed-link.txt -- for details. --- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge. -- Mostly used in qca8327 with CPU port 0 set to -- sgmii. --- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge. --- qca,sgmii-enable-pll : For SGMII CPU port, explicitly enable PLL, TX and RX -- chain along with Signal Detection. -- This should NOT be enabled for qca8327. If enabled with -- qca8327 the sgmii port won't correctly init and an err -- is printed. -- This can be required for qca8337 switch with revision 2. -- A warning is displayed when used with revision greater -- 2. -- With CPU port set to sgmii and qca8337 it is advised -- to set this unless a communication problem is observed. -- --For QCA8K the 'fixed-link' sub-node supports only the following properties: -- --- 'speed' (integer, mandatory), to indicate the link speed. Accepted -- values are 10, 100 and 1000 --- 'full-duplex' (boolean, optional), to indicate that full duplex is -- used. When absent, half duplex is assumed. -- --Examples: -- --for the external mdio-bus configuration: -- -- &mdio0 { -- phy_port1: phy@0 { -- reg = <0>; -- }; -- -- phy_port2: phy@1 { -- reg = <1>; -- }; -- -- phy_port3: phy@2 { -- reg = <2>; -- }; -- -- phy_port4: phy@3 { -- reg = <3>; -- }; -- -- phy_port5: phy@4 { -- reg = <4>; -- }; -- -- switch@10 { -- compatible = "qca,qca8337"; -- #address-cells = <1>; -- #size-cells = <0>; -- -- reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; -- reg = <0x10>; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- port@0 { -- reg = <0>; -- label = "cpu"; -- ethernet = <&gmac1>; -- phy-mode = "rgmii"; -- fixed-link { -- speed = 1000; -- full-duplex; -- }; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan1"; -- phy-handle = <&phy_port1>; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan2"; -- phy-handle = <&phy_port2>; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan3"; -- phy-handle = <&phy_port3>; -- }; -- -- port@4 { -- reg = <4>; -- label = "lan4"; -- phy-handle = <&phy_port4>; -- }; -- -- port@5 { -- reg = <5>; -- label = "wan"; -- phy-handle = <&phy_port5>; -- }; -- }; -- }; -- }; -- --for the internal master mdio-bus configuration: -- -- &mdio0 { -- switch@10 { -- compatible = "qca,qca8337"; -- #address-cells = <1>; -- #size-cells = <0>; -- -- reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; -- reg = <0x10>; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- label = "cpu"; -- ethernet = <&gmac1>; -- phy-mode = "rgmii"; -- fixed-link { -- speed = 1000; -- full-duplex; -- }; -- }; -- -- port@1 { -- reg = <1>; -- label = "lan1"; -- phy-mode = "internal"; -- phy-handle = <&phy_port1>; -- }; -- -- port@2 { -- reg = <2>; -- label = "lan2"; -- phy-mode = "internal"; -- phy-handle = <&phy_port2>; -- }; -- -- port@3 { -- reg = <3>; -- label = "lan3"; -- phy-mode = "internal"; -- phy-handle = <&phy_port3>; -- }; -- -- port@4 { -- reg = <4>; -- label = "lan4"; -- phy-mode = "internal"; -- phy-handle = <&phy_port4>; -- }; -- -- port@5 { -- reg = <5>; -- label = "wan"; -- phy-mode = "internal"; -- phy-handle = <&phy_port5>; -- }; -- }; -- -- mdio { -- #address-cells = <1>; -- #size-cells = <0>; -- -- phy_port1: phy@0 { -- reg = <0>; -- }; -- -- phy_port2: phy@1 { -- reg = <1>; -- }; -- -- phy_port3: phy@2 { -- reg = <2>; -- }; -- -- phy_port4: phy@3 { -- reg = <3>; -- }; -- -- phy_port5: phy@4 { -- reg = <4>; -- }; -- }; -- }; -- }; ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.yaml -@@ -0,0 +1,362 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Qualcomm Atheros QCA83xx switch family -+ -+maintainers: -+ - John Crispin -+ -+description: -+ If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode -+ describing a port needs to have a valid phandle referencing the internal PHY -+ it is connected to. This is because there is no N:N mapping of port and PHY -+ ID. To declare the internal mdio-bus configuration, declare an MDIO node in -+ the switch node and declare the phandle for the port, referencing the internal -+ PHY it is connected to. In this config, an internal mdio-bus is registered and -+ the MDIO master is used for communication. Mixed external and internal -+ mdio-bus configurations are not supported by the hardware. -+ -+properties: -+ compatible: -+ oneOf: -+ - enum: -+ - qca,qca8327 -+ - qca,qca8328 -+ - qca,qca8334 -+ - qca,qca8337 -+ description: | -+ qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package -+ qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package -+ qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package -+ qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package -+ -+ reg: -+ maxItems: 1 -+ -+ reset-gpios: -+ description: -+ GPIO to be used to reset the whole device -+ maxItems: 1 -+ -+ qca,ignore-power-on-sel: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: -+ Ignore power-on pin strapping to configure LED open-drain or EEPROM -+ presence. This is needed for devices with incorrect configuration or when -+ the OEM has decided not to use pin strapping and falls back to SW regs. -+ -+ qca,led-open-drain: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: -+ Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to -+ be set, otherwise the driver will fail at probe. This is required if the -+ OEM does not use pin strapping to set this mode and prefers to set it -+ using SW regs. The pin strappings related to LED open-drain mode are -+ B68 on the QCA832x and B49 on the QCA833x. -+ -+ mdio: -+ type: object -+ description: Qca8k switch have an internal mdio to access switch port. -+ If this is not present, the legacy mapping is used and the -+ internal mdio access is used. -+ With the legacy mapping the reg corresponding to the internal -+ mdio is the switch reg with an offset of -1. -+ -+ properties: -+ '#address-cells': -+ const: 1 -+ '#size-cells': -+ const: 0 -+ -+ patternProperties: -+ "^(ethernet-)?phy@[0-4]$": -+ type: object -+ -+ allOf: -+ - $ref: "http://devicetree.org/schemas/net/mdio.yaml#" -+ -+ properties: -+ reg: -+ maxItems: 1 -+ -+ required: -+ - reg -+ -+patternProperties: -+ "^(ethernet-)?ports$": -+ type: object -+ properties: -+ '#address-cells': -+ const: 1 -+ '#size-cells': -+ const: 0 -+ -+ patternProperties: -+ "^(ethernet-)?port@[0-6]$": -+ type: object -+ description: Ethernet switch ports -+ -+ properties: -+ reg: -+ description: Port number -+ -+ label: -+ description: -+ Describes the label associated with this port, which will become -+ the netdev name -+ $ref: /schemas/types.yaml#/definitions/string -+ -+ link: -+ description: -+ Should be a list of phandles to other switch's DSA port. This -+ port is used as the outgoing port towards the phandle ports. The -+ full routing information must be given, not just the one hop -+ routes to neighbouring switches -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ -+ ethernet: -+ description: -+ Should be a phandle to a valid Ethernet device node. This host -+ device is what the switch port is connected to -+ $ref: /schemas/types.yaml#/definitions/phandle -+ -+ phy-handle: true -+ -+ phy-mode: true -+ -+ fixed-link: true -+ -+ mac-address: true -+ -+ sfp: true -+ -+ qca,sgmii-rxclk-falling-edge: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: -+ Set the receive clock phase to falling edge. Mostly commonly used on -+ the QCA8327 with CPU port 0 set to SGMII. -+ -+ qca,sgmii-txclk-falling-edge: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: -+ Set the transmit clock phase to falling edge. -+ -+ qca,sgmii-enable-pll: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: -+ For SGMII CPU port, explicitly enable PLL, TX and RX chain along with -+ Signal Detection. On the QCA8327 this should not be enabled, otherwise -+ the SGMII port will not initialize. When used on the QCA8337, revision 3 -+ or greater, a warning will be displayed. When the CPU port is set to -+ SGMII on the QCA8337, it is advised to set this unless a communication -+ issue is observed. -+ -+ required: -+ - reg -+ -+ additionalProperties: false -+ -+oneOf: -+ - required: -+ - ports -+ - required: -+ - ethernet-ports -+ -+required: -+ - compatible -+ - reg -+ -+additionalProperties: true -+ -+examples: -+ - | -+ #include -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ external_phy_port1: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ external_phy_port2: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ external_phy_port3: ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ external_phy_port4: ethernet-phy@3 { -+ reg = <3>; -+ }; -+ -+ external_phy_port5: ethernet-phy@4 { -+ reg = <4>; -+ }; -+ -+ switch@10 { -+ compatible = "qca,qca8337"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; -+ reg = <0x10>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ label = "cpu"; -+ ethernet = <&gmac1>; -+ phy-mode = "rgmii"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ phy-handle = <&external_phy_port1>; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ phy-handle = <&external_phy_port2>; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ phy-handle = <&external_phy_port3>; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan4"; -+ phy-handle = <&external_phy_port4>; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "wan"; -+ phy-handle = <&external_phy_port5>; -+ }; -+ }; -+ }; -+ }; -+ - | -+ #include -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ switch@10 { -+ compatible = "qca,qca8337"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; -+ reg = <0x10>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ label = "cpu"; -+ ethernet = <&gmac1>; -+ phy-mode = "rgmii"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan1"; -+ phy-mode = "internal"; -+ phy-handle = <&internal_phy_port1>; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan2"; -+ phy-mode = "internal"; -+ phy-handle = <&internal_phy_port2>; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan3"; -+ phy-mode = "internal"; -+ phy-handle = <&internal_phy_port3>; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan4"; -+ phy-mode = "internal"; -+ phy-handle = <&internal_phy_port4>; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "wan"; -+ phy-mode = "internal"; -+ phy-handle = <&internal_phy_port5>; -+ }; -+ -+ port@6 { -+ reg = <0>; -+ label = "cpu"; -+ ethernet = <&gmac1>; -+ phy-mode = "sgmii"; -+ -+ qca,sgmii-rxclk-falling-edge; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ }; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ internal_phy_port1: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ -+ internal_phy_port2: ethernet-phy@1 { -+ reg = <1>; -+ }; -+ -+ internal_phy_port3: ethernet-phy@2 { -+ reg = <2>; -+ }; -+ -+ internal_phy_port4: ethernet-phy@3 { -+ reg = <3>; -+ }; -+ -+ internal_phy_port5: ethernet-phy@4 { -+ reg = <4>; -+ }; -+ }; -+ }; -+ }; diff --git a/target/linux/generic/backport-5.10/748-v5.16-net-dsa-qca8k-fix-delay-applied-to-wrong-cpu-in-parse-p.patch b/target/linux/generic/backport-5.10/748-v5.16-net-dsa-qca8k-fix-delay-applied-to-wrong-cpu-in-parse-p.patch deleted file mode 100644 index a510cfdc18..0000000000 --- a/target/linux/generic/backport-5.10/748-v5.16-net-dsa-qca8k-fix-delay-applied-to-wrong-cpu-in-parse-p.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 06dd34a628ae5b6a839b757e746de165d6789ca8 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 17 Oct 2021 16:56:46 +0200 -Subject: net: dsa: qca8k: fix delay applied to wrong cpu in parse_port_config - -Fix delay settings applied to wrong cpu in parse_port_config. The delay -values is set to the wrong index as the cpu_port_index is incremented -too early. Start the cpu_port_index to -1 so the correct value is -applied to address also the case with invalid phy mode and not available -port. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -976,7 +976,7 @@ qca8k_setup_of_pws_reg(struct qca8k_priv - static int - qca8k_parse_port_config(struct qca8k_priv *priv) - { -- int port, cpu_port_index = 0, ret; -+ int port, cpu_port_index = -1, ret; - struct device_node *port_dn; - phy_interface_t mode; - struct dsa_port *dp; diff --git a/target/linux/generic/backport-5.10/749-v5.16-net-dsa-qca8k-tidy-for-loop-in-setup-and-add-cpu-port-c.patch b/target/linux/generic/backport-5.10/749-v5.16-net-dsa-qca8k-tidy-for-loop-in-setup-and-add-cpu-port-c.patch deleted file mode 100644 index 71fa3022d5..0000000000 --- a/target/linux/generic/backport-5.10/749-v5.16-net-dsa-qca8k-tidy-for-loop-in-setup-and-add-cpu-port-c.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 040e926f5813a5f4cc18dbff7c942d1e52f368f2 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 19 Oct 2021 02:08:50 +0200 -Subject: net: dsa: qca8k: tidy for loop in setup and add cpu port check - -Tidy and organize qca8k setup function from multiple for loop. -Change for loop in bridge leave/join to scan all port and skip cpu port. -No functional change intended. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 74 +++++++++++++++++++++++++++++-------------------- - 1 file changed, 44 insertions(+), 30 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1122,28 +1122,34 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - dev_warn(priv->dev, "mib init failed"); - -- /* Enable QCA header mode on the cpu port */ -- ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(cpu_port), -- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | -- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); -- if (ret) { -- dev_err(priv->dev, "failed enabling QCA header mode"); -- return ret; -- } -- -- /* Disable forwarding by default on all ports */ -+ /* Initial setup of all ports */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) { -+ /* Disable forwarding by default on all ports */ - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, 0); - if (ret) - return ret; -- } - -- /* Disable MAC by default on all ports */ -- for (i = 1; i < QCA8K_NUM_PORTS; i++) -- qca8k_port_set_status(priv, i, 0); -+ /* Enable QCA header mode on all cpu ports */ -+ if (dsa_is_cpu_port(ds, i)) { -+ ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i), -+ QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | -+ QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); -+ if (ret) { -+ dev_err(priv->dev, "failed enabling QCA header mode"); -+ return ret; -+ } -+ } -+ -+ /* Disable MAC by default on all user ports */ -+ if (dsa_is_user_port(ds, i)) -+ qca8k_port_set_status(priv, i, 0); -+ } - -- /* Forward all unknown frames to CPU port for Linux processing */ -+ /* Forward all unknown frames to CPU port for Linux processing -+ * Notice that in multi-cpu config only one port should be set -+ * for igmp, unknown, multicast and broadcast packet -+ */ - ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | -@@ -1152,11 +1158,13 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - return ret; - -- /* Setup connection between CPU port & user ports */ -+ /* Setup connection between CPU port & user ports -+ * Configure specific switch configuration for ports -+ */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - /* CPU port gets connected to all user ports of the switch */ - if (dsa_is_cpu_port(ds, i)) { -- ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port), -+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); - if (ret) - return ret; -@@ -1193,16 +1201,14 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - return ret; - } -- } - -- /* The port 5 of the qca8337 have some problem in flood condition. The -- * original legacy driver had some specific buffer and priority settings -- * for the different port suggested by the QCA switch team. Add this -- * missing settings to improve switch stability under load condition. -- * This problem is limited to qca8337 and other qca8k switch are not affected. -- */ -- if (priv->switch_id == QCA8K_ID_QCA8337) { -- for (i = 0; i < QCA8K_NUM_PORTS; i++) { -+ /* The port 5 of the qca8337 have some problem in flood condition. The -+ * original legacy driver had some specific buffer and priority settings -+ * for the different port suggested by the QCA switch team. Add this -+ * missing settings to improve switch stability under load condition. -+ * This problem is limited to qca8337 and other qca8k switch are not affected. -+ */ -+ if (priv->switch_id == QCA8K_ID_QCA8337) { - switch (i) { - /* The 2 CPU port and port 5 requires some different - * priority than any other ports. -@@ -1238,6 +1244,12 @@ qca8k_setup(struct dsa_switch *ds) - QCA8K_PORT_HOL_CTRL1_WRED_EN, - mask); - } -+ -+ /* Set initial MTU for every port. -+ * We have only have a general MTU setting. So track -+ * every port and set the max across all port. -+ */ -+ priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; - } - - /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */ -@@ -1251,8 +1263,6 @@ qca8k_setup(struct dsa_switch *ds) - } - - /* Setup our port MTUs to match power on defaults */ -- for (i = 0; i < QCA8K_NUM_PORTS; i++) -- priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; - ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); - if (ret) - dev_warn(priv->dev, "failed setting MTU settings"); -@@ -1728,7 +1738,9 @@ qca8k_port_bridge_join(struct dsa_switch - cpu_port = dsa_to_port(ds, port)->cpu_dp->index; - port_mask = BIT(cpu_port); - -- for (i = 1; i < QCA8K_NUM_PORTS; i++) { -+ for (i = 0; i < QCA8K_NUM_PORTS; i++) { -+ if (dsa_is_cpu_port(ds, i)) -+ continue; - if (dsa_to_port(ds, i)->bridge_dev != br) - continue; - /* Add this port to the portvlan mask of the other ports -@@ -1758,7 +1770,9 @@ qca8k_port_bridge_leave(struct dsa_switc - - cpu_port = dsa_to_port(ds, port)->cpu_dp->index; - -- for (i = 1; i < QCA8K_NUM_PORTS; i++) { -+ for (i = 0; i < QCA8K_NUM_PORTS; i++) { -+ if (dsa_is_cpu_port(ds, i)) -+ continue; - if (dsa_to_port(ds, i)->bridge_dev != br) - continue; - /* Remove this port to the portvlan mask of the other ports diff --git a/target/linux/generic/backport-5.10/750-v5.16-net-dsa-qca8k-make-sure-pad0-mac06-exchange-is-disabled.patch b/target/linux/generic/backport-5.10/750-v5.16-net-dsa-qca8k-make-sure-pad0-mac06-exchange-is-disabled.patch deleted file mode 100644 index 4a61703c52..0000000000 --- a/target/linux/generic/backport-5.10/750-v5.16-net-dsa-qca8k-make-sure-pad0-mac06-exchange-is-disabled.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 5f15d392dcb4aa250a63d6f2c5adfc26c0aedc78 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 2 Nov 2021 19:30:41 +0100 -Subject: net: dsa: qca8k: make sure PAD0 MAC06 exchange is disabled - -Some device set MAC06 exchange in the bootloader. This cause some -problem as we don't support this strange mode and we just set the port6 -as the primary CPU port. With MAC06 exchange, PAD0 reg configure port6 -instead of port0. Add an extra check and explicitly disable MAC06 exchange -to correctly configure the port PAD config. - -Signed-off-by: Ansuel Smith -Fixes: 3fcf734aa482 ("net: dsa: qca8k: add support for cpu port 6") -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 8 ++++++++ - drivers/net/dsa/qca8k.h | 1 + - 2 files changed, 9 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1109,6 +1109,14 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - return ret; - -+ /* Make sure MAC06 is disabled */ -+ ret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL, -+ QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN); -+ if (ret) { -+ dev_err(priv->dev, "failed disabling MAC06 exchange"); -+ return ret; -+ } -+ - /* Enable CPU Port */ - ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, - QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -34,6 +34,7 @@ - #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) - #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) - #define QCA8K_REG_PORT0_PAD_CTRL 0x004 -+#define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31) - #define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19) - #define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18) - #define QCA8K_REG_PORT5_PAD_CTRL 0x008 diff --git a/target/linux/generic/backport-5.10/751-v5.16-net-dsa-qca8k-fix-internal-delay-applied-to-the-wrong-PAD.patch b/target/linux/generic/backport-5.10/751-v5.16-net-dsa-qca8k-fix-internal-delay-applied-to-the-wrong-PAD.patch deleted file mode 100644 index df9518d86c..0000000000 --- a/target/linux/generic/backport-5.10/751-v5.16-net-dsa-qca8k-fix-internal-delay-applied-to-the-wrong-PAD.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 3b00a07c2443745d62babfe08dbb2ad8e649526e Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 19 Nov 2021 03:03:49 +0100 -Subject: [PATCH] net: dsa: qca8k: fix internal delay applied to the wrong PAD - config - -With SGMII phy the internal delay is always applied to the PAD0 config. -This is caused by the falling edge configuration that hardcode the reg -to PAD0 (as the falling edge bits are present only in PAD0 reg) -Move the delay configuration before the reg overwrite to correctly apply -the delay. - -Fixes: cef08115846e ("net: dsa: qca8k: set internal delay also for sgmii") -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1433,6 +1433,12 @@ qca8k_phylink_mac_config(struct dsa_swit - - qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val); - -+ /* From original code is reported port instability as SGMII also -+ * require delay set. Apply advised values here or take them from DT. -+ */ -+ if (state->interface == PHY_INTERFACE_MODE_SGMII) -+ qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg); -+ - /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and - * falling edge is set writing in the PORT0 PAD reg - */ -@@ -1455,12 +1461,6 @@ qca8k_phylink_mac_config(struct dsa_swit - QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE, - val); - -- /* From original code is reported port instability as SGMII also -- * require delay set. Apply advised values here or take them from DT. -- */ -- if (state->interface == PHY_INTERFACE_MODE_SGMII) -- qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg); -- - break; - default: - dev_err(ds->dev, "xMII mode %s not supported for port %d\n", diff --git a/target/linux/generic/backport-5.10/752-v5.16-net-dsa-qca8k-fix-MTU-calculation.patch b/target/linux/generic/backport-5.10/752-v5.16-net-dsa-qca8k-fix-MTU-calculation.patch deleted file mode 100644 index 7348d93ec4..0000000000 --- a/target/linux/generic/backport-5.10/752-v5.16-net-dsa-qca8k-fix-MTU-calculation.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 65258b9d8cde45689bdc86ca39b50f01f983733b Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Fri, 19 Nov 2021 03:03:50 +0100 -Subject: [PATCH] net: dsa: qca8k: fix MTU calculation - -qca8k has a global MTU, so its tracking the MTU per port to make sure -that the largest MTU gets applied. -Since it uses the frame size instead of MTU the driver MTU change function -will then add the size of Ethernet header and checksum on top of MTU. - -The driver currently populates the per port MTU size as Ethernet frame -length + checksum which equals 1518. - -The issue is that then MTU change function will go through all of the -ports, find the largest MTU and apply the Ethernet header + checksum on -top of it again, so for a desired MTU of 1500 you will end up with 1536. - -This is obviously incorrect, so to correct it populate the per port struct -MTU with just the MTU and not include the Ethernet header + checksum size -as those will be added by the MTU change function. - -Fixes: f58d2598cf70 ("net: dsa: qca8k: implement the port MTU callbacks") -Signed-off-by: Robert Marko -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1256,8 +1256,12 @@ qca8k_setup(struct dsa_switch *ds) - /* Set initial MTU for every port. - * We have only have a general MTU setting. So track - * every port and set the max across all port. -+ * Set per port MTU to 1500 as the MTU change function -+ * will add the overhead and if its set to 1518 then it -+ * will apply the overhead again and we will end up with -+ * MTU of 1536 instead of 1518 - */ -- priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; -+ priv->port_mtu[i] = ETH_DATA_LEN; - } - - /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */ diff --git a/target/linux/generic/backport-5.10/753-net-next-net-dsa-qca8k-remove-redundant-check-in-parse_port_config.patch b/target/linux/generic/backport-5.10/753-net-next-net-dsa-qca8k-remove-redundant-check-in-parse_port_config.patch deleted file mode 100644 index f477b1b929..0000000000 --- a/target/linux/generic/backport-5.10/753-net-next-net-dsa-qca8k-remove-redundant-check-in-parse_port_config.patch +++ /dev/null @@ -1,29 +0,0 @@ -From b9133f3ef5a2659730cf47a74bd0a9259f1cf8ff Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 22 Nov 2021 16:23:40 +0100 -Subject: net: dsa: qca8k: remove redundant check in parse_port_config - -The very next check for port 0 and 6 already makes sure we don't go out -of bounds with the ports_config delay table. -Remove the redundant check. - -Reported-by: kernel test robot -Reported-by: Dan Carpenter -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -983,7 +983,7 @@ qca8k_parse_port_config(struct qca8k_pri - u32 delay; - - /* We have 2 CPU port. Check them */ -- for (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) { -+ for (port = 0; port < QCA8K_NUM_PORTS; port++) { - /* Skip every other port */ - if (port != 0 && port != 6) - continue; diff --git a/target/linux/generic/backport-5.10/754-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch b/target/linux/generic/backport-5.10/754-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch deleted file mode 100644 index c1489fd9a8..0000000000 --- a/target/linux/generic/backport-5.10/754-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch +++ /dev/null @@ -1,508 +0,0 @@ -From 90ae68bfc2ffcb54a4ba4f64edbeb84a80cbb57c Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 22 Nov 2021 16:23:41 +0100 -Subject: net: dsa: qca8k: convert to GENMASK/FIELD_PREP/FIELD_GET - -Convert and try to standardize bit fields using -GENMASK/FIELD_PREP/FIELD_GET macros. Rework some logic to support the -standard macro and tidy things up. No functional change intended. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 98 +++++++++++++++---------------- - drivers/net/dsa/qca8k.h | 153 ++++++++++++++++++++++++++---------------------- - 2 files changed, 130 insertions(+), 121 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -319,18 +320,18 @@ qca8k_fdb_read(struct qca8k_priv *priv, - } - - /* vid - 83:72 */ -- fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M; -+ fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]); - /* aging - 67:64 */ -- fdb->aging = reg[2] & QCA8K_ATU_STATUS_M; -+ fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]); - /* portmask - 54:48 */ -- fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M; -+ fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]); - /* mac - 47:0 */ -- fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff; -- fdb->mac[1] = reg[1] & 0xff; -- fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff; -- fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff; -- fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff; -- fdb->mac[5] = reg[0] & 0xff; -+ fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]); -+ fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]); -+ fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]); -+ fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]); -+ fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]); -+ fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]); - - return 0; - } -@@ -343,18 +344,18 @@ qca8k_fdb_write(struct qca8k_priv *priv, - int i; - - /* vid - 83:72 */ -- reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S; -+ reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid); - /* aging - 67:64 */ -- reg[2] |= aging & QCA8K_ATU_STATUS_M; -+ reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging); - /* portmask - 54:48 */ -- reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S; -+ reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask); - /* mac - 47:0 */ -- reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S; -- reg[1] |= mac[1]; -- reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S; -- reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S; -- reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S; -- reg[0] |= mac[5]; -+ reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]); -+ reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]); -+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]); -+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]); -+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]); -+ reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]); - - /* load the array into the ARL table */ - for (i = 0; i < 3; i++) -@@ -372,7 +373,7 @@ qca8k_fdb_access(struct qca8k_priv *priv - reg |= cmd; - if (port >= 0) { - reg |= QCA8K_ATU_FUNC_PORT_EN; -- reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S; -+ reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port); - } - - /* Write the function register triggering the table access */ -@@ -454,7 +455,7 @@ qca8k_vlan_access(struct qca8k_priv *pri - /* Set the command and VLAN index */ - reg = QCA8K_VTU_FUNC1_BUSY; - reg |= cmd; -- reg |= vid << QCA8K_VTU_FUNC1_VID_S; -+ reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid); - - /* Write the function register triggering the table access */ - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); -@@ -500,13 +501,11 @@ qca8k_vlan_add(struct qca8k_priv *priv, - if (ret < 0) - goto out; - reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; -- reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port)); -+ reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); - if (untagged) -- reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG << -- QCA8K_VTU_FUNC0_EG_MODE_S(port); -+ reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port); - else -- reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG << -- QCA8K_VTU_FUNC0_EG_MODE_S(port); -+ reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port); - - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); - if (ret) -@@ -534,15 +533,13 @@ qca8k_vlan_del(struct qca8k_priv *priv, - ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); - if (ret < 0) - goto out; -- reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port)); -- reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT << -- QCA8K_VTU_FUNC0_EG_MODE_S(port); -+ reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); -+ reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port); - - /* Check if we're the last member to be removed */ - del = true; - for (i = 0; i < QCA8K_NUM_PORTS; i++) { -- mask = QCA8K_VTU_FUNC0_EG_MODE_NOT; -- mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i); -+ mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i); - - if ((reg & mask) != mask) { - del = false; -@@ -1014,7 +1011,7 @@ qca8k_parse_port_config(struct qca8k_pri - mode == PHY_INTERFACE_MODE_RGMII_TXID) - delay = 1; - -- if (delay > QCA8K_MAX_DELAY) { -+ if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) { - dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); - delay = 3; - } -@@ -1030,7 +1027,7 @@ qca8k_parse_port_config(struct qca8k_pri - mode == PHY_INTERFACE_MODE_RGMII_RXID) - delay = 2; - -- if (delay > QCA8K_MAX_DELAY) { -+ if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) { - dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); - delay = 3; - } -@@ -1141,8 +1138,8 @@ qca8k_setup(struct dsa_switch *ds) - /* Enable QCA header mode on all cpu ports */ - if (dsa_is_cpu_port(ds, i)) { - ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i), -- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S | -- QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S); -+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) | -+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL)); - if (ret) { - dev_err(priv->dev, "failed enabling QCA header mode"); - return ret; -@@ -1159,10 +1156,10 @@ qca8k_setup(struct dsa_switch *ds) - * for igmp, unknown, multicast and broadcast packet - */ - ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, -- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S | -- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S | -- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S | -- BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S); -+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) | -+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) | -+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) | -+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port))); - if (ret) - return ret; - -@@ -1180,8 +1177,6 @@ qca8k_setup(struct dsa_switch *ds) - - /* Individual user ports get connected to CPU port only */ - if (dsa_is_user_port(ds, i)) { -- int shift = 16 * (i % 2); -- - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), - QCA8K_PORT_LOOKUP_MEMBER, - BIT(cpu_port)); -@@ -1198,8 +1193,8 @@ qca8k_setup(struct dsa_switch *ds) - * default egress vid - */ - ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), -- 0xfff << shift, -- QCA8K_PORT_VID_DEF << shift); -+ QCA8K_EGREES_VLAN_PORT_MASK(i), -+ QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF)); - if (ret) - return ret; - -@@ -1246,7 +1241,7 @@ qca8k_setup(struct dsa_switch *ds) - QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | - QCA8K_PORT_HOL_CTRL1_WRED_EN; - qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), -- QCA8K_PORT_HOL_CTRL1_ING_BUF | -+ QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK | - QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | - QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | - QCA8K_PORT_HOL_CTRL1_WRED_EN, -@@ -1269,8 +1264,8 @@ qca8k_setup(struct dsa_switch *ds) - mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) | - QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496); - qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH, -- QCA8K_GLOBAL_FC_GOL_XON_THRES_S | -- QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S, -+ QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK | -+ QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, - mask); - } - -@@ -1918,11 +1913,11 @@ qca8k_port_vlan_filtering(struct dsa_swi - - if (vlan_filtering) { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), -- QCA8K_PORT_LOOKUP_VLAN_MODE, -+ QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, - QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); - } else { - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), -- QCA8K_PORT_LOOKUP_VLAN_MODE, -+ QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, - QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); - } - -@@ -1953,11 +1948,9 @@ qca8k_port_vlan_add(struct dsa_switch *d - dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret); - - if (pvid) { -- int shift = 16 * (port % 2); -- - qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), -- 0xfff << shift, -- vlan->vid_end << shift); -+ QCA8K_EGREES_VLAN_PORT_MASK(port), -+ QCA8K_EGREES_VLAN_PORT(port, vlan->vid_end)); - qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), - QCA8K_PORT_VLAN_CVID(vlan->vid_end) | - QCA8K_PORT_VLAN_SVID(vlan->vid_end)); -@@ -2050,7 +2043,7 @@ static int qca8k_read_switch_id(struct q - if (ret < 0) - return -ENODEV; - -- id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK); -+ id = QCA8K_MASK_CTRL_DEVICE_ID(val); - if (id != data->id) { - dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id); - return -ENODEV; -@@ -2059,7 +2052,7 @@ static int qca8k_read_switch_id(struct q - priv->switch_id = id; - - /* Save revision to communicate to the internal PHY driver */ -- priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK); -+ priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val); - - return 0; - } ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -30,9 +30,9 @@ - /* Global control registers */ - #define QCA8K_REG_MASK_CTRL 0x000 - #define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0) --#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0) -+#define QCA8K_MASK_CTRL_REV_ID(x) FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x) - #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) --#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) -+#define QCA8K_MASK_CTRL_DEVICE_ID(x) FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x) - #define QCA8K_REG_PORT0_PAD_CTRL 0x004 - #define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31) - #define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19) -@@ -41,12 +41,11 @@ - #define QCA8K_REG_PORT6_PAD_CTRL 0x00c - #define QCA8K_PORT_PAD_RGMII_EN BIT(26) - #define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22) --#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) -+#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x) - #define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20) --#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) -+#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x) - #define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) - #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) --#define QCA8K_MAX_DELAY 3 - #define QCA8K_PORT_PAD_SGMII_EN BIT(7) - #define QCA8K_REG_PWS 0x010 - #define QCA8K_PWS_POWER_ON_SEL BIT(31) -@@ -68,10 +67,12 @@ - #define QCA8K_MDIO_MASTER_READ BIT(27) - #define QCA8K_MDIO_MASTER_WRITE 0 - #define QCA8K_MDIO_MASTER_SUP_PRE BIT(26) --#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21) --#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16) --#define QCA8K_MDIO_MASTER_DATA(x) (x) -+#define QCA8K_MDIO_MASTER_PHY_ADDR_MASK GENMASK(25, 21) -+#define QCA8K_MDIO_MASTER_PHY_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x) -+#define QCA8K_MDIO_MASTER_REG_ADDR_MASK GENMASK(20, 16) -+#define QCA8K_MDIO_MASTER_REG_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x) - #define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0) -+#define QCA8K_MDIO_MASTER_DATA(x) FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x) - #define QCA8K_MDIO_MASTER_MAX_PORTS 5 - #define QCA8K_MDIO_MASTER_MAX_REG 32 - #define QCA8K_GOL_MAC_ADDR0 0x60 -@@ -93,9 +94,7 @@ - #define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12) - #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4)) - #define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2) --#define QCA8K_PORT_HDR_CTRL_RX_S 2 - #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0) --#define QCA8K_PORT_HDR_CTRL_TX_S 0 - #define QCA8K_PORT_HDR_CTRL_ALL 2 - #define QCA8K_PORT_HDR_CTRL_MGMT 1 - #define QCA8K_PORT_HDR_CTRL_NONE 0 -@@ -105,10 +104,11 @@ - #define QCA8K_SGMII_EN_TX BIT(3) - #define QCA8K_SGMII_EN_SD BIT(4) - #define QCA8K_SGMII_CLK125M_DELAY BIT(7) --#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23)) --#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22) --#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22) --#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22) -+#define QCA8K_SGMII_MODE_CTRL_MASK GENMASK(23, 22) -+#define QCA8K_SGMII_MODE_CTRL(x) FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x) -+#define QCA8K_SGMII_MODE_CTRL_BASEX QCA8K_SGMII_MODE_CTRL(0x0) -+#define QCA8K_SGMII_MODE_CTRL_PHY QCA8K_SGMII_MODE_CTRL(0x1) -+#define QCA8K_SGMII_MODE_CTRL_MAC QCA8K_SGMII_MODE_CTRL(0x2) - - /* MAC_PWR_SEL registers */ - #define QCA8K_REG_MAC_PWR_SEL 0x0e4 -@@ -121,100 +121,115 @@ - - /* ACL registers */ - #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8)) --#define QCA8K_PORT_VLAN_CVID(x) (x << 16) --#define QCA8K_PORT_VLAN_SVID(x) x -+#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16) -+#define QCA8K_PORT_VLAN_CVID(x) FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x) -+#define QCA8K_PORT_VLAN_SVID_MASK GENMASK(11, 0) -+#define QCA8K_PORT_VLAN_SVID(x) FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x) - #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8)) - #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470 - #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474 - - /* Lookup registers */ - #define QCA8K_REG_ATU_DATA0 0x600 --#define QCA8K_ATU_ADDR2_S 24 --#define QCA8K_ATU_ADDR3_S 16 --#define QCA8K_ATU_ADDR4_S 8 -+#define QCA8K_ATU_ADDR2_MASK GENMASK(31, 24) -+#define QCA8K_ATU_ADDR3_MASK GENMASK(23, 16) -+#define QCA8K_ATU_ADDR4_MASK GENMASK(15, 8) -+#define QCA8K_ATU_ADDR5_MASK GENMASK(7, 0) - #define QCA8K_REG_ATU_DATA1 0x604 --#define QCA8K_ATU_PORT_M 0x7f --#define QCA8K_ATU_PORT_S 16 --#define QCA8K_ATU_ADDR0_S 8 -+#define QCA8K_ATU_PORT_MASK GENMASK(22, 16) -+#define QCA8K_ATU_ADDR0_MASK GENMASK(15, 8) -+#define QCA8K_ATU_ADDR1_MASK GENMASK(7, 0) - #define QCA8K_REG_ATU_DATA2 0x608 --#define QCA8K_ATU_VID_M 0xfff --#define QCA8K_ATU_VID_S 8 --#define QCA8K_ATU_STATUS_M 0xf -+#define QCA8K_ATU_VID_MASK GENMASK(19, 8) -+#define QCA8K_ATU_STATUS_MASK GENMASK(3, 0) - #define QCA8K_ATU_STATUS_STATIC 0xf - #define QCA8K_REG_ATU_FUNC 0x60c - #define QCA8K_ATU_FUNC_BUSY BIT(31) - #define QCA8K_ATU_FUNC_PORT_EN BIT(14) - #define QCA8K_ATU_FUNC_MULTI_EN BIT(13) - #define QCA8K_ATU_FUNC_FULL BIT(12) --#define QCA8K_ATU_FUNC_PORT_M 0xf --#define QCA8K_ATU_FUNC_PORT_S 8 -+#define QCA8K_ATU_FUNC_PORT_MASK GENMASK(11, 8) - #define QCA8K_REG_VTU_FUNC0 0x610 - #define QCA8K_VTU_FUNC0_VALID BIT(20) - #define QCA8K_VTU_FUNC0_IVL_EN BIT(19) --#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) --#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3 --#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0 --#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1 --#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2 --#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3 -+/* QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(17, 4) -+ * It does contain VLAN_MODE for each port [5:4] for port0, -+ * [7:6] for port1 ... [17:16] for port6. Use virtual port -+ * define to handle this. -+ */ -+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i) (4 + (_i) * 2) -+#define QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(1, 0) -+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i) (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)) -+#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0) -+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)) -+#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1) -+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)) -+#define QCA8K_VTU_FUNC0_EG_MODE_TAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2) -+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)) -+#define QCA8K_VTU_FUNC0_EG_MODE_NOT FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3) -+#define QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i) (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)) - #define QCA8K_REG_VTU_FUNC1 0x614 - #define QCA8K_VTU_FUNC1_BUSY BIT(31) --#define QCA8K_VTU_FUNC1_VID_S 16 -+#define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16) - #define QCA8K_VTU_FUNC1_FULL BIT(4) - #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620 - #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10) - #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624 --#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24 --#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16 --#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8 --#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0 -+#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24) -+#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16) -+#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8) -+#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0) - #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc) - #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0) --#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8) --#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8) --#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8) --#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8) --#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8) -+#define QCA8K_PORT_LOOKUP_VLAN_MODE_MASK GENMASK(9, 8) -+#define QCA8K_PORT_LOOKUP_VLAN_MODE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x) -+#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE QCA8K_PORT_LOOKUP_VLAN_MODE(0x0) -+#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK QCA8K_PORT_LOOKUP_VLAN_MODE(0x1) -+#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK QCA8K_PORT_LOOKUP_VLAN_MODE(0x2) -+#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE QCA8K_PORT_LOOKUP_VLAN_MODE(0x3) - #define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16) --#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16) --#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16) --#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16) --#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16) --#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16) --#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) -+#define QCA8K_PORT_LOOKUP_STATE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x) -+#define QCA8K_PORT_LOOKUP_STATE_DISABLED QCA8K_PORT_LOOKUP_STATE(0x0) -+#define QCA8K_PORT_LOOKUP_STATE_BLOCKING QCA8K_PORT_LOOKUP_STATE(0x1) -+#define QCA8K_PORT_LOOKUP_STATE_LISTENING QCA8K_PORT_LOOKUP_STATE(0x2) -+#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3) -+#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4) - #define QCA8K_PORT_LOOKUP_LEARN BIT(20) - - #define QCA8K_REG_GLOBAL_FC_THRESH 0x800 --#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16) --#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16) --#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0) --#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0) -+#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16) -+#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x) -+#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK GENMASK(8, 0) -+#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x) - - #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20) --#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20) --#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24) --#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK GENMASK(3, 0) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK GENMASK(7, 4) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK GENMASK(11, 8) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK GENMASK(15, 12) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK GENMASK(19, 16) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK GENMASK(23, 20) -+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x) -+#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK GENMASK(29, 24) -+#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x) - - #define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) --#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0) --#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0) -+#define QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK GENMASK(3, 0) -+#define QCA8K_PORT_HOL_CTRL1_ING(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x) - #define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) - #define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) - #define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8) - #define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) - - /* Pkt edit registers */ -+#define QCA8K_EGREES_VLAN_PORT_SHIFT(_i) (16 * ((_i) % 2)) -+#define QCA8K_EGREES_VLAN_PORT_MASK(_i) (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i)) -+#define QCA8K_EGREES_VLAN_PORT(_i, x) ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i)) - #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) - - /* L3 registers */ diff --git a/target/linux/generic/backport-5.10/755-net-next-net-dsa-qca8k-remove-extra-mutex_init-in-qca8k_setup.patch b/target/linux/generic/backport-5.10/755-net-next-net-dsa-qca8k-remove-extra-mutex_init-in-qca8k_setup.patch deleted file mode 100644 index 8c39b8ea29..0000000000 --- a/target/linux/generic/backport-5.10/755-net-next-net-dsa-qca8k-remove-extra-mutex_init-in-qca8k_setup.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 994c28b6f971fa5db8ae977daea37eee87d93d51 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 22 Nov 2021 16:23:42 +0100 -Subject: net: dsa: qca8k: remove extra mutex_init in qca8k_setup - -Mutex is already init in sw_probe. Remove the extra init in qca8k_setup. - -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1086,8 +1086,6 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - return ret; - -- mutex_init(&priv->reg_mutex); -- - /* Start by setting up the register mapping */ - priv->regmap = devm_regmap_init(ds->dev, NULL, priv, - &qca8k_regmap_config); diff --git a/target/linux/generic/backport-5.10/756-net-next-net-dsa-qca8k-move-regmap-init-in-probe-and-set-it.patch b/target/linux/generic/backport-5.10/756-net-next-net-dsa-qca8k-move-regmap-init-in-probe-and-set-it.patch deleted file mode 100644 index 9fcc74a7ce..0000000000 --- a/target/linux/generic/backport-5.10/756-net-next-net-dsa-qca8k-move-regmap-init-in-probe-and-set-it.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 36b8af12f424e7a7f60a935c60a0fd4aa0822378 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 22 Nov 2021 16:23:43 +0100 -Subject: net: dsa: qca8k: move regmap init in probe and set it mandatory - -In preparation for regmap conversion, move regmap init in the probe -function and make it mandatory as any read/write/rmw operation will be -converted to regmap API. - -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 14 ++++++++------ - 1 file changed, 8 insertions(+), 6 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1086,12 +1086,6 @@ qca8k_setup(struct dsa_switch *ds) - if (ret) - return ret; - -- /* Start by setting up the register mapping */ -- priv->regmap = devm_regmap_init(ds->dev, NULL, priv, -- &qca8k_regmap_config); -- if (IS_ERR(priv->regmap)) -- dev_warn(priv->dev, "regmap initialization failed"); -- - ret = qca8k_setup_mdio_bus(priv); - if (ret) - return ret; -@@ -2085,6 +2079,14 @@ qca8k_sw_probe(struct mdio_device *mdiod - gpiod_set_value_cansleep(priv->reset_gpio, 0); - } - -+ /* Start by setting up the register mapping */ -+ priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv, -+ &qca8k_regmap_config); -+ if (IS_ERR(priv->regmap)) { -+ dev_err(priv->dev, "regmap initialization failed"); -+ return PTR_ERR(priv->regmap); -+ } -+ - /* Check the detected switch id */ - ret = qca8k_read_switch_id(priv); - if (ret) diff --git a/target/linux/generic/backport-5.10/757-net-next-net-dsa-qca8k-initial-conversion-to-regmap-heper.patch b/target/linux/generic/backport-5.10/757-net-next-net-dsa-qca8k-initial-conversion-to-regmap-heper.patch deleted file mode 100644 index 4ca9c8ba41..0000000000 --- a/target/linux/generic/backport-5.10/757-net-next-net-dsa-qca8k-initial-conversion-to-regmap-heper.patch +++ /dev/null @@ -1,249 +0,0 @@ -From 8b5f3f29a81a71934d004e21a1292c1148b05926 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 22 Nov 2021 16:23:44 +0100 -Subject: net: dsa: qca8k: initial conversion to regmap helper - -Convert any qca8k set/clear/pool to regmap helper and add -missing config to regmap_config struct. -Read/write/rmw operation are reworked to use the regmap helper -internally to keep the delta of this patch low. These additional -function will then be dropped when the code split will be proposed. - -Ipq40xx SoC have the internal switch based on the qca8k regmap but use -mmio for read/write/rmw operation instead of mdio. -In preparation for the support of this internal switch, convert the -driver to regmap API to later split the driver to common and specific -code. The overhead introduced by the use of regamp API is marginal as the -internal mdio will bypass it by using its direct access and regmap will be -used only by configuration functions or fdb access. - -Signed-off-by: Ansuel Smith -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 107 +++++++++++++++++++++--------------------------- - 1 file changed, 47 insertions(+), 60 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -152,6 +153,25 @@ qca8k_set_page(struct mii_bus *bus, u16 - static int - qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val) - { -+ return regmap_read(priv->regmap, reg, val); -+} -+ -+static int -+qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) -+{ -+ return regmap_write(priv->regmap, reg, val); -+} -+ -+static int -+qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) -+{ -+ return regmap_update_bits(priv->regmap, reg, mask, write_val); -+} -+ -+static int -+qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) -+{ -+ struct qca8k_priv *priv = (struct qca8k_priv *)ctx; - struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - int ret; -@@ -172,8 +192,9 @@ exit: - } - - static int --qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) -+qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val) - { -+ struct qca8k_priv *priv = (struct qca8k_priv *)ctx; - struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - int ret; -@@ -194,8 +215,9 @@ exit: - } - - static int --qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) -+qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val) - { -+ struct qca8k_priv *priv = (struct qca8k_priv *)ctx; - struct mii_bus *bus = priv->bus; - u16 r1, r2, page; - u32 val; -@@ -223,34 +245,6 @@ exit: - return ret; - } - --static int --qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val) --{ -- return qca8k_rmw(priv, reg, 0, val); --} -- --static int --qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val) --{ -- return qca8k_rmw(priv, reg, val, 0); --} -- --static int --qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val) --{ -- struct qca8k_priv *priv = (struct qca8k_priv *)ctx; -- -- return qca8k_read(priv, reg, val); --} -- --static int --qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val) --{ -- struct qca8k_priv *priv = (struct qca8k_priv *)ctx; -- -- return qca8k_write(priv, reg, val); --} -- - static const struct regmap_range qca8k_readable_ranges[] = { - regmap_reg_range(0x0000, 0x00e4), /* Global control */ - regmap_reg_range(0x0100, 0x0168), /* EEE control */ -@@ -282,26 +276,19 @@ static struct regmap_config qca8k_regmap - .max_register = 0x16ac, /* end MIB - Port6 range */ - .reg_read = qca8k_regmap_read, - .reg_write = qca8k_regmap_write, -+ .reg_update_bits = qca8k_regmap_update_bits, - .rd_table = &qca8k_readable_table, -+ .disable_locking = true, /* Locking is handled by qca8k read/write */ -+ .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */ - }; - - static int - qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) - { -- int ret, ret1; - u32 val; - -- ret = read_poll_timeout(qca8k_read, ret1, !(val & mask), -- 0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, -- priv, reg, &val); -- -- /* Check if qca8k_read has failed for a different reason -- * before returning -ETIMEDOUT -- */ -- if (ret < 0 && ret1 < 0) -- return ret1; -- -- return ret; -+ return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0, -+ QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); - } - - static int -@@ -568,7 +555,7 @@ qca8k_mib_init(struct qca8k_priv *priv) - int ret; - - mutex_lock(&priv->reg_mutex); -- ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); -+ ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY); - if (ret) - goto exit; - -@@ -576,7 +563,7 @@ qca8k_mib_init(struct qca8k_priv *priv) - if (ret) - goto exit; - -- ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); -+ ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); - if (ret) - goto exit; - -@@ -597,9 +584,9 @@ qca8k_port_set_status(struct qca8k_priv - mask |= QCA8K_PORT_STATUS_LINK_AUTO; - - if (enable) -- qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask); -+ regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); - else -- qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask); -+ regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); - } - - static u32 -@@ -861,8 +848,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv * - * a dt-overlay and driver reload changed the configuration - */ - -- return qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, -- QCA8K_MDIO_MASTER_EN); -+ return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL, -+ QCA8K_MDIO_MASTER_EN); - } - - /* Check if the devicetree declare the port:phy mapping */ -@@ -1099,16 +1086,16 @@ qca8k_setup(struct dsa_switch *ds) - return ret; - - /* Make sure MAC06 is disabled */ -- ret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL, -- QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN); -+ ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL, -+ QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN); - if (ret) { - dev_err(priv->dev, "failed disabling MAC06 exchange"); - return ret; - } - - /* Enable CPU Port */ -- ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0, -- QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); -+ ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, -+ QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); - if (ret) { - dev_err(priv->dev, "failed enabling CPU port"); - return ret; -@@ -1176,8 +1163,8 @@ qca8k_setup(struct dsa_switch *ds) - return ret; - - /* Enable ARP Auto-learning by default */ -- ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i), -- QCA8K_PORT_LOOKUP_LEARN); -+ ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i), -+ QCA8K_PORT_LOOKUP_LEARN); - if (ret) - return ret; - -@@ -1745,9 +1732,9 @@ qca8k_port_bridge_join(struct dsa_switch - /* Add this port to the portvlan mask of the other ports - * in the bridge - */ -- ret = qca8k_reg_set(priv, -- QCA8K_PORT_LOOKUP_CTRL(i), -- BIT(port)); -+ ret = regmap_set_bits(priv->regmap, -+ QCA8K_PORT_LOOKUP_CTRL(i), -+ BIT(port)); - if (ret) - return ret; - if (i != port) -@@ -1777,9 +1764,9 @@ qca8k_port_bridge_leave(struct dsa_switc - /* Remove this port to the portvlan mask of the other ports - * in the bridge - */ -- qca8k_reg_clear(priv, -- QCA8K_PORT_LOOKUP_CTRL(i), -- BIT(port)); -+ regmap_clear_bits(priv->regmap, -+ QCA8K_PORT_LOOKUP_CTRL(i), -+ BIT(port)); - } - - /* Set the cpu port to be the only one in the portvlan mask of diff --git a/target/linux/generic/backport-5.10/758-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch b/target/linux/generic/backport-5.10/758-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch deleted file mode 100644 index 78bdf7f77d..0000000000 --- a/target/linux/generic/backport-5.10/758-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch +++ /dev/null @@ -1,120 +0,0 @@ -From c126f118b330ccf0db0dda4a4bd6c729865a205f Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 22 Nov 2021 16:23:45 +0100 -Subject: net: dsa: qca8k: add additional MIB counter and make it dynamic - -We are currently missing 2 additionals MIB counter present in QCA833x -switch. -QC832x switch have 39 MIB counter and QCA833X have 41 MIB counter. -Add the additional MIB counter and rework the MIB function to print the -correct supported counter from the match_data struct. - -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++--- - drivers/net/dsa/qca8k.h | 4 ++++ - 2 files changed, 24 insertions(+), 3 deletions(-) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -70,6 +70,8 @@ static const struct qca8k_mib_desc ar832 - MIB_DESC(1, 0x9c, "TxExcDefer"), - MIB_DESC(1, 0xa0, "TxDefer"), - MIB_DESC(1, 0xa4, "TxLateCol"), -+ MIB_DESC(1, 0xa8, "RXUnicast"), -+ MIB_DESC(1, 0xac, "TXUnicast"), - }; - - /* The 32bit switch registers are accessed indirectly. To achieve this we need -@@ -1605,12 +1607,16 @@ qca8k_phylink_mac_link_up(struct dsa_swi - static void - qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data) - { -+ const struct qca8k_match_data *match_data; -+ struct qca8k_priv *priv = ds->priv; - int i; - - if (stringset != ETH_SS_STATS) - return; - -- for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) -+ match_data = of_device_get_match_data(priv->dev); -+ -+ for (i = 0; i < match_data->mib_count; i++) - strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name, - ETH_GSTRING_LEN); - } -@@ -1620,12 +1626,15 @@ qca8k_get_ethtool_stats(struct dsa_switc - uint64_t *data) - { - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; -+ const struct qca8k_match_data *match_data; - const struct qca8k_mib_desc *mib; - u32 reg, i, val; - u32 hi = 0; - int ret; - -- for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) { -+ match_data = of_device_get_match_data(priv->dev); -+ -+ for (i = 0; i < match_data->mib_count; i++) { - mib = &ar8327_mib[i]; - reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; - -@@ -1648,10 +1657,15 @@ qca8k_get_ethtool_stats(struct dsa_switc - static int - qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset) - { -+ const struct qca8k_match_data *match_data; -+ struct qca8k_priv *priv = ds->priv; -+ - if (sset != ETH_SS_STATS) - return 0; - -- return ARRAY_SIZE(ar8327_mib); -+ match_data = of_device_get_match_data(priv->dev); -+ -+ return match_data->mib_count; - } - - static int -@@ -2146,14 +2160,17 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, - static const struct qca8k_match_data qca8327 = { - .id = QCA8K_ID_QCA8327, - .reduced_package = true, -+ .mib_count = QCA8K_QCA832X_MIB_COUNT, - }; - - static const struct qca8k_match_data qca8328 = { - .id = QCA8K_ID_QCA8327, -+ .mib_count = QCA8K_QCA832X_MIB_COUNT, - }; - - static const struct qca8k_match_data qca833x = { - .id = QCA8K_ID_QCA8337, -+ .mib_count = QCA8K_QCA833X_MIB_COUNT, - }; - - static const struct of_device_id qca8k_of_match[] = { ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -21,6 +21,9 @@ - #define PHY_ID_QCA8337 0x004dd036 - #define QCA8K_ID_QCA8337 0x13 - -+#define QCA8K_QCA832X_MIB_COUNT 39 -+#define QCA8K_QCA833X_MIB_COUNT 41 -+ - #define QCA8K_BUSY_WAIT_TIMEOUT 2000 - - #define QCA8K_NUM_FDB_RECORDS 2048 -@@ -279,6 +282,7 @@ struct ar8xxx_port_status { - struct qca8k_match_data { - u8 id; - bool reduced_package; -+ u8 mib_count; - }; - - enum { diff --git a/target/linux/generic/backport-5.10/759-net-next-net-dsa-qca8k-add-support-for-port-fast-aging.patch b/target/linux/generic/backport-5.10/759-net-next-net-dsa-qca8k-add-support-for-port-fast-aging.patch deleted file mode 100644 index 41efa89b5e..0000000000 --- a/target/linux/generic/backport-5.10/759-net-next-net-dsa-qca8k-add-support-for-port-fast-aging.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 4592538bfb0d5d3c3c8a1d7071724d081412ac91 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 22 Nov 2021 16:23:46 +0100 -Subject: net: dsa: qca8k: add support for port fast aging - -The switch supports fast aging by flushing any rule in the ARL -table for a specific port. - -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 11 +++++++++++ - drivers/net/dsa/qca8k.h | 1 + - 2 files changed, 12 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1790,6 +1790,16 @@ qca8k_port_bridge_leave(struct dsa_switc - QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); - } - -+static void -+qca8k_port_fast_age(struct dsa_switch *ds, int port) -+{ -+ struct qca8k_priv *priv = ds->priv; -+ -+ mutex_lock(&priv->reg_mutex); -+ qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port); -+ mutex_unlock(&priv->reg_mutex); -+} -+ - static int - qca8k_port_enable(struct dsa_switch *ds, int port, - struct phy_device *phy) -@@ -2005,6 +2015,7 @@ static const struct dsa_switch_ops qca8k - .port_stp_state_set = qca8k_port_stp_state_set, - .port_bridge_join = qca8k_port_bridge_join, - .port_bridge_leave = qca8k_port_bridge_leave, -+ .port_fast_age = qca8k_port_fast_age, - .port_fdb_add = qca8k_port_fdb_add, - .port_fdb_del = qca8k_port_fdb_del, - .port_fdb_dump = qca8k_port_fdb_dump, ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -262,6 +262,7 @@ enum qca8k_fdb_cmd { - QCA8K_FDB_FLUSH = 1, - QCA8K_FDB_LOAD = 2, - QCA8K_FDB_PURGE = 3, -+ QCA8K_FDB_FLUSH_PORT = 5, - QCA8K_FDB_NEXT = 6, - QCA8K_FDB_SEARCH = 7, - }; diff --git a/target/linux/generic/backport-5.10/760-net-next-net-dsa-qca8k-add-set_ageing_time-support.patch b/target/linux/generic/backport-5.10/760-net-next-net-dsa-qca8k-add-set_ageing_time-support.patch deleted file mode 100644 index f32e6ae93a..0000000000 --- a/target/linux/generic/backport-5.10/760-net-next-net-dsa-qca8k-add-set_ageing_time-support.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 6a3bdc5209f45d2af83aa92433ab6e5cf2297aa4 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 22 Nov 2021 16:23:47 +0100 -Subject: net: dsa: qca8k: add set_ageing_time support - -qca8k support setting ageing time in step of 7s. Add support for it and -set the max value accepted of 7645m. -Documentation talks about support for 10000m but that values doesn't -make sense as the value doesn't match the max value in the reg. - -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 25 +++++++++++++++++++++++++ - drivers/net/dsa/qca8k.h | 3 +++ - 2 files changed, 28 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -1261,6 +1261,10 @@ qca8k_setup(struct dsa_switch *ds) - /* We don't have interrupts for link changes, so we need to poll */ - ds->pcs_poll = true; - -+ /* Set min a max ageing value supported */ -+ ds->ageing_time_min = 7000; -+ ds->ageing_time_max = 458745000; -+ - return 0; - } - -@@ -1801,6 +1805,26 @@ qca8k_port_fast_age(struct dsa_switch *d - } - - static int -+qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) -+{ -+ struct qca8k_priv *priv = ds->priv; -+ unsigned int secs = msecs / 1000; -+ u32 val; -+ -+ /* AGE_TIME reg is set in 7s step */ -+ val = secs / 7; -+ -+ /* Handle case with 0 as val to NOT disable -+ * learning -+ */ -+ if (!val) -+ val = 1; -+ -+ return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, QCA8K_ATU_AGE_TIME_MASK, -+ QCA8K_ATU_AGE_TIME(val)); -+} -+ -+static int - qca8k_port_enable(struct dsa_switch *ds, int port, - struct phy_device *phy) - { -@@ -2006,6 +2030,7 @@ static const struct dsa_switch_ops qca8k - .get_strings = qca8k_get_strings, - .get_ethtool_stats = qca8k_get_ethtool_stats, - .get_sset_count = qca8k_get_sset_count, -+ .set_ageing_time = qca8k_set_ageing_time, - .get_mac_eee = qca8k_get_mac_eee, - .set_mac_eee = qca8k_set_mac_eee, - .port_enable = qca8k_port_enable, ---- a/drivers/net/dsa/qca8k.h -+++ b/drivers/net/dsa/qca8k.h -@@ -175,6 +175,9 @@ - #define QCA8K_VTU_FUNC1_BUSY BIT(31) - #define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16) - #define QCA8K_VTU_FUNC1_FULL BIT(4) -+#define QCA8K_REG_ATU_CTRL 0x618 -+#define QCA8K_ATU_AGE_TIME_MASK GENMASK(15, 0) -+#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x)) - #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620 - #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10) - #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624 diff --git a/target/linux/generic/backport-5.10/761-net-next-net-dsa-qca8k-add-support-for-mdb_add-del.patch b/target/linux/generic/backport-5.10/761-net-next-net-dsa-qca8k-add-support-for-mdb_add-del.patch deleted file mode 100644 index e0daa88c31..0000000000 --- a/target/linux/generic/backport-5.10/761-net-next-net-dsa-qca8k-add-support-for-mdb_add-del.patch +++ /dev/null @@ -1,142 +0,0 @@ -From ba8f870dfa635113ce6e8095a5eb1835ecde2e9e Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 22 Nov 2021 16:23:48 +0100 -Subject: net: dsa: qca8k: add support for mdb_add/del - -Add support for mdb add/del function. The ARL table is used to insert -the rule. The rule will be searched, deleted and reinserted with the -port mask updated. The function will check if the rule has to be updated -or insert directly with no deletion of the old rule. -If every port is removed from the port mask, the rule is removed. -The rule is set STATIC in the ARL table (aka it doesn't age) to not be -flushed by fast age function. - -Signed-off-by: Ansuel Smith -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/qca8k.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 99 insertions(+) - ---- a/drivers/net/dsa/qca8k.c -+++ b/drivers/net/dsa/qca8k.c -@@ -436,6 +436,81 @@ qca8k_fdb_flush(struct qca8k_priv *priv) - } - - static int -+qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask, -+ const u8 *mac, u16 vid) -+{ -+ struct qca8k_fdb fdb = { 0 }; -+ int ret; -+ -+ mutex_lock(&priv->reg_mutex); -+ -+ qca8k_fdb_write(priv, vid, 0, mac, 0); -+ ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); -+ if (ret < 0) -+ goto exit; -+ -+ ret = qca8k_fdb_read(priv, &fdb); -+ if (ret < 0) -+ goto exit; -+ -+ /* Rule exist. Delete first */ -+ if (!fdb.aging) { -+ ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); -+ if (ret) -+ goto exit; -+ } -+ -+ /* Add port to fdb portmask */ -+ fdb.port_mask |= port_mask; -+ -+ qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); -+ ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); -+ -+exit: -+ mutex_unlock(&priv->reg_mutex); -+ return ret; -+} -+ -+static int -+qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask, -+ const u8 *mac, u16 vid) -+{ -+ struct qca8k_fdb fdb = { 0 }; -+ int ret; -+ -+ mutex_lock(&priv->reg_mutex); -+ -+ qca8k_fdb_write(priv, vid, 0, mac, 0); -+ ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); -+ if (ret < 0) -+ goto exit; -+ -+ /* Rule doesn't exist. Why delete? */ -+ if (!fdb.aging) { -+ ret = -EINVAL; -+ goto exit; -+ } -+ -+ ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); -+ if (ret) -+ goto exit; -+ -+ /* Only port in the rule is this port. Don't re insert */ -+ if (fdb.port_mask == port_mask) -+ goto exit; -+ -+ /* Remove port from port mask */ -+ fdb.port_mask &= ~port_mask; -+ -+ qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); -+ ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); -+ -+exit: -+ mutex_unlock(&priv->reg_mutex); -+ return ret; -+} -+ -+static int - qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid) - { - u32 reg; -@@ -1929,6 +2004,28 @@ qca8k_port_fdb_dump(struct dsa_switch *d - return 0; - } - -+static void -+qca8k_port_mdb_add(struct dsa_switch *ds, int port, -+ const struct switchdev_obj_port_mdb *mdb) -+{ -+ struct qca8k_priv *priv = ds->priv; -+ const u8 *addr = mdb->addr; -+ u16 vid = mdb->vid; -+ -+ qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid); -+} -+ -+static int -+qca8k_port_mdb_del(struct dsa_switch *ds, int port, -+ const struct switchdev_obj_port_mdb *mdb) -+{ -+ struct qca8k_priv *priv = ds->priv; -+ const u8 *addr = mdb->addr; -+ u16 vid = mdb->vid; -+ -+ return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid); -+} -+ - static int - qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, - struct switchdev_trans *trans) -@@ -2044,6 +2141,8 @@ static const struct dsa_switch_ops qca8k - .port_fdb_add = qca8k_port_fdb_add, - .port_fdb_del = qca8k_port_fdb_del, - .port_fdb_dump = qca8k_port_fdb_dump, -+ .port_mdb_add = qca8k_port_mdb_add, -+ .port_mdb_del = qca8k_port_mdb_del, - .port_vlan_filtering = qca8k_port_vlan_filtering, - .port_vlan_prepare = qca8k_port_vlan_prepare, - .port_vlan_add = qca8k_port_vlan_add, diff --git a/target/linux/generic/backport-5.10/762-v5.11-net-dsa-mt7530-support-setting-MTU.patch b/target/linux/generic/backport-5.10/762-v5.11-net-dsa-mt7530-support-setting-MTU.patch deleted file mode 100644 index f1fa461aec..0000000000 --- a/target/linux/generic/backport-5.10/762-v5.11-net-dsa-mt7530-support-setting-MTU.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 9470174e7581e75a8ebd78964997314dfc2e706c Mon Sep 17 00:00:00 2001 -From: DENG Qingfang -Date: Tue, 3 Nov 2020 13:06:18 +0800 -Subject: [PATCH] net: dsa: mt7530: support setting MTU - -MT7530/7531 has a global RX packet length register, which can be used -to set MTU. - -Supported packet length values are 1522 (1518 if untagged), 1536, -1552, and multiple of 1024 (from 2048 to 15360). - -Signed-off-by: DENG Qingfang -Link: https://lore.kernel.org/r/20201103050618.11419-1-dqfext@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/mt7530.c | 49 ++++++++++++++++++++++++++++++++++++++++ - drivers/net/dsa/mt7530.h | 12 ++++++++++ - 2 files changed, 61 insertions(+) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1018,6 +1018,53 @@ mt7530_port_disable(struct dsa_switch *d - mutex_unlock(&priv->reg_mutex); - } - -+static int -+mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) -+{ -+ struct mt7530_priv *priv = ds->priv; -+ struct mii_bus *bus = priv->bus; -+ int length; -+ u32 val; -+ -+ /* When a new MTU is set, DSA always set the CPU port's MTU to the -+ * largest MTU of the slave ports. Because the switch only has a global -+ * RX length register, only allowing CPU port here is enough. -+ */ -+ if (!dsa_is_cpu_port(ds, port)) -+ return 0; -+ -+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); -+ -+ val = mt7530_mii_read(priv, MT7530_GMACCR); -+ val &= ~MAX_RX_PKT_LEN_MASK; -+ -+ /* RX length also includes Ethernet header, MTK tag, and FCS length */ -+ length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; -+ if (length <= 1522) { -+ val |= MAX_RX_PKT_LEN_1522; -+ } else if (length <= 1536) { -+ val |= MAX_RX_PKT_LEN_1536; -+ } else if (length <= 1552) { -+ val |= MAX_RX_PKT_LEN_1552; -+ } else { -+ val &= ~MAX_RX_JUMBO_MASK; -+ val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); -+ val |= MAX_RX_PKT_LEN_JUMBO; -+ } -+ -+ mt7530_mii_write(priv, MT7530_GMACCR, val); -+ -+ mutex_unlock(&bus->mdio_lock); -+ -+ return 0; -+} -+ -+static int -+mt7530_port_max_mtu(struct dsa_switch *ds, int port) -+{ -+ return MT7530_MAX_MTU; -+} -+ - static void - mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) - { -@@ -2650,6 +2697,8 @@ static const struct dsa_switch_ops mt753 - .get_sset_count = mt7530_get_sset_count, - .port_enable = mt7530_port_enable, - .port_disable = mt7530_port_disable, -+ .port_change_mtu = mt7530_port_change_mtu, -+ .port_max_mtu = mt7530_port_max_mtu, - .port_stp_state_set = mt7530_stp_state_set, - .port_bridge_join = mt7530_port_bridge_join, - .port_bridge_leave = mt7530_port_bridge_leave, ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -11,6 +11,9 @@ - #define MT7530_NUM_FDB_RECORDS 2048 - #define MT7530_ALL_MEMBERS 0xff - -+#define MTK_HDR_LEN 4 -+#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) -+ - enum mt753x_id { - ID_MT7530 = 0, - ID_MT7621 = 1, -@@ -301,6 +304,15 @@ enum mt7530_vlan_port_attr { - #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) - #define MT7531_DIS_CLR BIT(31) - -+#define MT7530_GMACCR 0x30e0 -+#define MAX_RX_JUMBO(x) ((x) << 2) -+#define MAX_RX_JUMBO_MASK GENMASK(5, 2) -+#define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) -+#define MAX_RX_PKT_LEN_1522 0x0 -+#define MAX_RX_PKT_LEN_1536 0x1 -+#define MAX_RX_PKT_LEN_1552 0x2 -+#define MAX_RX_PKT_LEN_JUMBO 0x3 -+ - /* Register for MIB */ - #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) - #define MT7530_MIB_CCR 0x4fe0 diff --git a/target/linux/generic/backport-5.10/763-v5.11-net-dsa-mt7530-enable-MTU-normalization.patch b/target/linux/generic/backport-5.10/763-v5.11-net-dsa-mt7530-enable-MTU-normalization.patch deleted file mode 100644 index a239549758..0000000000 --- a/target/linux/generic/backport-5.10/763-v5.11-net-dsa-mt7530-enable-MTU-normalization.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 771c8901568dd8776a260aa93db41be88a60389e Mon Sep 17 00:00:00 2001 -From: DENG Qingfang -Date: Fri, 11 Dec 2020 01:03:22 +0800 -Subject: [PATCH] net: dsa: mt7530: enable MTU normalization - -MT7530 has a global RX length register, so we are actually changing its -MRU. -Enable MTU normalization for this reason. - -Signed-off-by: DENG Qingfang -Acked-by: Landen Chao -Reviewed-by: Vladimir Oltean -Link: https://lore.kernel.org/r/20201210170322.3433-1-dqfext@gmail.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/mt7530.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1706,6 +1706,7 @@ mt7530_setup(struct dsa_switch *ds) - */ - dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; - ds->configure_vlan_while_not_filtering = true; -+ ds->mtu_enforcement_ingress = true; - - if (priv->id == ID_MT7530) { - regulator_set_voltage(priv->core_pwr, 1000000, 1000000); -@@ -1953,6 +1954,7 @@ mt7531_setup(struct dsa_switch *ds) - } - - ds->configure_vlan_while_not_filtering = true; -+ ds->mtu_enforcement_ingress = true; - - /* Flush the FDB table */ - ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); diff --git a/target/linux/generic/backport-5.10/764-v5.11-net-dsa-mt7530-support-setting-ageing-time.patch b/target/linux/generic/backport-5.10/764-v5.11-net-dsa-mt7530-support-setting-ageing-time.patch deleted file mode 100644 index 0b28a4626e..0000000000 --- a/target/linux/generic/backport-5.10/764-v5.11-net-dsa-mt7530-support-setting-ageing-time.patch +++ /dev/null @@ -1,99 +0,0 @@ -From ea6d5c924e391872d402acac38461a5f8261e57f Mon Sep 17 00:00:00 2001 -From: DENG Qingfang -Date: Tue, 8 Dec 2020 15:00:28 +0800 -Subject: [PATCH] net: dsa: mt7530: support setting ageing time - -MT7530 has a global address age control register, so use it to set -ageing time. - -The applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds - -Signed-off-by: DENG Qingfang -Reviewed-by: Andrew Lunn -Reviewed-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller ---- - drivers/net/dsa/mt7530.c | 41 ++++++++++++++++++++++++++++++++++++++++ - drivers/net/dsa/mt7530.h | 13 +++++++++++++ - 2 files changed, 54 insertions(+) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -873,6 +873,46 @@ mt7530_get_sset_count(struct dsa_switch - return ARRAY_SIZE(mt7530_mib); - } - -+static int -+mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) -+{ -+ struct mt7530_priv *priv = ds->priv; -+ unsigned int secs = msecs / 1000; -+ unsigned int tmp_age_count; -+ unsigned int error = -1; -+ unsigned int age_count; -+ unsigned int age_unit; -+ -+ /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ -+ if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) -+ return -ERANGE; -+ -+ /* iterate through all possible age_count to find the closest pair */ -+ for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { -+ unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; -+ -+ if (tmp_age_unit <= AGE_UNIT_MAX) { -+ unsigned int tmp_error = secs - -+ (tmp_age_count + 1) * (tmp_age_unit + 1); -+ -+ /* found a closer pair */ -+ if (error > tmp_error) { -+ error = tmp_error; -+ age_count = tmp_age_count; -+ age_unit = tmp_age_unit; -+ } -+ -+ /* found the exact match, so break the loop */ -+ if (!error) -+ break; -+ } -+ } -+ -+ mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); -+ -+ return 0; -+} -+ - static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) - { - struct mt7530_priv *priv = ds->priv; -@@ -2697,6 +2737,7 @@ static const struct dsa_switch_ops mt753 - .phy_write = mt753x_phy_write, - .get_ethtool_stats = mt7530_get_ethtool_stats, - .get_sset_count = mt7530_get_sset_count, -+ .set_ageing_time = mt7530_set_ageing_time, - .port_enable = mt7530_port_enable, - .port_disable = mt7530_port_disable, - .port_change_mtu = mt7530_port_change_mtu, ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -161,6 +161,19 @@ enum mt7530_vlan_egress_attr { - MT7530_VLAN_EGRESS_STACK = 3, - }; - -+/* Register for address age control */ -+#define MT7530_AAC 0xa0 -+/* Disable ageing */ -+#define AGE_DIS BIT(20) -+/* Age count */ -+#define AGE_CNT_MASK GENMASK(19, 12) -+#define AGE_CNT_MAX 0xff -+#define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) -+/* Age unit */ -+#define AGE_UNIT_MASK GENMASK(11, 0) -+#define AGE_UNIT_MAX 0xfff -+#define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) -+ - /* Register for port STP state control */ - #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) - #define FID_PST(x) ((x) & 0x3) diff --git a/target/linux/generic/backport-5.10/770-v5.15-net-dsa-mt7530-support-MDB-operations.patch b/target/linux/generic/backport-5.10/770-v5.15-net-dsa-mt7530-support-MDB-operations.patch deleted file mode 100644 index 99f49972ff..0000000000 --- a/target/linux/generic/backport-5.10/770-v5.15-net-dsa-mt7530-support-MDB-operations.patch +++ /dev/null @@ -1,171 +0,0 @@ -From 1f11a07a33bc26997c18b633d63f088bf75d11f2 Mon Sep 17 00:00:00 2001 -From: DENG Qingfang -Date: Tue, 24 Aug 2021 11:37:50 +0800 -Subject: [PATCH] net: dsa: mt7530: support MDB operations - -This is a partial backport of commit 5a30833b9a16f8d1aa15de06636f9317ca51f9df -("net: dsa: mt7530: support MDB and bridge flag operations") upstream. - -Signed-off-by: DENG Qingfang ---- - drivers/net/dsa/mt7530.c | 78 ++++++++++++++++++++++++++++++++++++++-- - net/dsa/tag_mtk.c | 14 +------- - 2 files changed, 76 insertions(+), 16 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -1001,9 +1001,6 @@ mt753x_cpu_port_enable(struct dsa_switch - mt7530_write(priv, MT7530_PVC_P(port), - PORT_SPEC_TAG); - -- /* Unknown multicast frame forwarding to the cpu port */ -- mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port))); -- - /* Set CPU port number */ - if (priv->id == ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); -@@ -1134,6 +1131,20 @@ mt7530_stp_state_set(struct dsa_switch * - } - - static int -+mt7530_port_egress_floods(struct dsa_switch *ds, int port, -+ bool unicast, bool multicast) -+{ -+ struct mt7530_priv *priv = ds->priv; -+ -+ mt7530_rmw(priv, MT7530_MFC, -+ UNU_FFP(BIT(port)) | UNM_FFP(BIT(port)), -+ (unicast ? UNU_FFP(BIT(port)) : 0) | -+ (multicast ? UNM_FFP(BIT(port)) : 0)); -+ -+ return 0; -+} -+ -+static int - mt7530_port_bridge_join(struct dsa_switch *ds, int port, - struct net_device *bridge) - { -@@ -1334,6 +1345,63 @@ err: - } - - static int -+mt7530_port_mdb_prepare(struct dsa_switch *ds, int port, -+ const struct switchdev_obj_port_mdb *mdb) -+{ -+ return 0; -+} -+ -+static void -+mt7530_port_mdb_add(struct dsa_switch *ds, int port, -+ const struct switchdev_obj_port_mdb *mdb) -+{ -+ struct mt7530_priv *priv = ds->priv; -+ const u8 *addr = mdb->addr; -+ u16 vid = mdb->vid; -+ u8 port_mask = 0; -+ -+ mutex_lock(&priv->reg_mutex); -+ -+ mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); -+ if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) -+ port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) -+ & PORT_MAP_MASK; -+ -+ port_mask |= BIT(port); -+ mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); -+ mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); -+ -+ mutex_unlock(&priv->reg_mutex); -+} -+ -+static int -+mt7530_port_mdb_del(struct dsa_switch *ds, int port, -+ const struct switchdev_obj_port_mdb *mdb) -+{ -+ struct mt7530_priv *priv = ds->priv; -+ const u8 *addr = mdb->addr; -+ u16 vid = mdb->vid; -+ u8 port_mask = 0; -+ int ret; -+ -+ mutex_lock(&priv->reg_mutex); -+ -+ mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); -+ if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) -+ port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) -+ & PORT_MAP_MASK; -+ -+ port_mask &= ~BIT(port); -+ mt7530_fdb_write(priv, vid, port_mask, addr, -1, -+ port_mask ? STATIC_ENT : STATIC_EMP); -+ ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); -+ -+ mutex_unlock(&priv->reg_mutex); -+ -+ return ret; -+} -+ -+static int - mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) - { - struct mt7530_dummy_poll p; -@@ -2743,11 +2811,15 @@ static const struct dsa_switch_ops mt753 - .port_change_mtu = mt7530_port_change_mtu, - .port_max_mtu = mt7530_port_max_mtu, - .port_stp_state_set = mt7530_stp_state_set, -+ .port_egress_floods = mt7530_port_egress_floods, - .port_bridge_join = mt7530_port_bridge_join, - .port_bridge_leave = mt7530_port_bridge_leave, - .port_fdb_add = mt7530_port_fdb_add, - .port_fdb_del = mt7530_port_fdb_del, - .port_fdb_dump = mt7530_port_fdb_dump, -+ .port_mdb_prepare = mt7530_port_mdb_prepare, -+ .port_mdb_add = mt7530_port_mdb_add, -+ .port_mdb_del = mt7530_port_mdb_del, - .port_vlan_filtering = mt7530_port_vlan_filtering, - .port_vlan_prepare = mt7530_port_vlan_prepare, - .port_vlan_add = mt7530_port_vlan_add, ---- a/net/dsa/tag_mtk.c -+++ b/net/dsa/tag_mtk.c -@@ -24,9 +24,6 @@ static struct sk_buff *mtk_tag_xmit(stru - struct dsa_port *dp = dsa_slave_to_port(dev); - u8 xmit_tpid; - u8 *mtk_tag; -- unsigned char *dest = eth_hdr(skb)->h_dest; -- bool is_multicast_skb = is_multicast_ether_addr(dest) && -- !is_broadcast_ether_addr(dest); - - /* Build the special tag after the MAC Source Address. If VLAN header - * is present, it's required that VLAN header and special tag is -@@ -55,10 +52,6 @@ static struct sk_buff *mtk_tag_xmit(stru - mtk_tag[0] = xmit_tpid; - mtk_tag[1] = (1 << dp->index) & MTK_HDR_XMIT_DP_BIT_MASK; - -- /* Disable SA learning for multicast frames */ -- if (unlikely(is_multicast_skb)) -- mtk_tag[1] |= MTK_HDR_XMIT_SA_DIS; -- - /* Tag control information is kept for 802.1Q */ - if (xmit_tpid == MTK_HDR_XMIT_UNTAGGED) { - mtk_tag[2] = 0; -@@ -74,9 +67,6 @@ static struct sk_buff *mtk_tag_rcv(struc - u16 hdr; - int port; - __be16 *phdr; -- unsigned char *dest = eth_hdr(skb)->h_dest; -- bool is_multicast_skb = is_multicast_ether_addr(dest) && -- !is_broadcast_ether_addr(dest); - - if (unlikely(!pskb_may_pull(skb, MTK_HDR_LEN))) - return NULL; -@@ -102,9 +92,7 @@ static struct sk_buff *mtk_tag_rcv(struc - if (!skb->dev) - return NULL; - -- /* Only unicast or broadcast frames are offloaded */ -- if (likely(!is_multicast_skb)) -- dsa_default_offload_fwd_mark(skb); -+ dsa_default_offload_fwd_mark(skb); - - return skb; - } diff --git a/target/linux/generic/backport-5.10/771-v5.14-net-phy-add-MediaTek-Gigabit-Ethernet-PHY-driver.patch b/target/linux/generic/backport-5.10/771-v5.14-net-phy-add-MediaTek-Gigabit-Ethernet-PHY-driver.patch deleted file mode 100644 index 67e3ca91ed..0000000000 --- a/target/linux/generic/backport-5.10/771-v5.14-net-phy-add-MediaTek-Gigabit-Ethernet-PHY-driver.patch +++ /dev/null @@ -1,159 +0,0 @@ -From e40d2cca01893c1941f5959b14bb0cd0d4f4d099 Mon Sep 17 00:00:00 2001 -From: DENG Qingfang -Date: Wed, 19 May 2021 11:31:59 +0800 -Subject: [PATCH] net: phy: add MediaTek Gigabit Ethernet PHY driver - -Add support for MediaTek Gigabit Ethernet PHYs found in MT7530 and -MT7531 switches. -The initialization procedure is from the vendor driver, but due to lack -of documentation, the function of some register values remains unknown. - -Signed-off-by: DENG Qingfang -Signed-off-by: David S. Miller ---- - drivers/net/phy/Kconfig | 5 ++ - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-ge.c | 116 ++++++++++++++++++++++++++++++++++ - 3 files changed, 122 insertions(+) - create mode 100644 drivers/net/phy/mediatek-ge.c - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -201,6 +201,11 @@ config MARVELL_10G_PHY - help - Support for the Marvell Alaska MV88X3310 and compatible PHYs. - -+config MEDIATEK_GE_PHY -+ tristate "MediaTek PHYs" -+ help -+ Supports the MediaTek switch integrated PHYs. -+ - config MICREL_PHY - tristate "Micrel PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -63,6 +63,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c - obj-$(CONFIG_LXT_PHY) += lxt.o - obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o - obj-$(CONFIG_MARVELL_PHY) += marvell.o -+obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_MICREL_PHY) += micrel.o ---- /dev/null -+++ b/drivers/net/phy/mediatek-ge.c -@@ -0,0 +1,113 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+#include -+#include -+#include -+ -+#define MTK_T10_TEST_CONTROL 0x145 -+#define MTK_PHY_TP_MASK GENMASK(4, 3) -+#define MTK_PHY_TP_AUTO 0 -+#define MTK_PHY_TP_MDI 2 -+#define MTK_PHY_TP_MDIX 3 -+ -+#define MTK_EXT_PAGE_ACCESS 0x1f -+#define MTK_PHY_PAGE_STANDARD 0x0000 -+#define MTK_PHY_PAGE_EXTENDED 0x0001 -+#define MTK_PHY_PAGE_EXTENDED_2 0x0002 -+#define MTK_PHY_PAGE_EXTENDED_3 0x0003 -+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 -+#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 -+ -+static int mtk_gephy_read_page(struct phy_device *phydev) -+{ -+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -+} -+ -+static int mtk_gephy_write_page(struct phy_device *phydev, int page) -+{ -+ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -+} -+ -+static void mtk_gephy_config_init(struct phy_device *phydev) -+{ -+ /* Disable EEE */ -+ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); -+ -+ /* Enable HW auto downshift */ -+ phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); -+ -+ /* Increase SlvDPSready time */ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ __phy_write(phydev, 0x10, 0xafae); -+ __phy_write(phydev, 0x12, 0x2f); -+ __phy_write(phydev, 0x10, 0x8fae); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ /* Adjust 100_mse_threshold */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); -+ -+ /* Disable mcc */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); -+} -+ -+static int mt7530_phy_config_init(struct phy_device *phydev) -+{ -+ mtk_gephy_config_init(phydev); -+ -+ /* Increase post_update_timer */ -+ phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); -+ -+ return 0; -+} -+ -+static int mt7531_phy_config_init(struct phy_device *phydev) -+{ -+ mtk_gephy_config_init(phydev); -+ -+ /* PHY link down power saving enable */ -+ phy_set_bits(phydev, 0x17, BIT(4)); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); -+ -+ /* Set TX Pair delay selection */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); -+ -+ return 0; -+} -+ -+static struct phy_driver mtk_gephy_driver[] = { -+ { -+ PHY_ID_MATCH_EXACT(0x03a29412), -+ .name = "MediaTek MT7530 PHY", -+ .config_init = mt7530_phy_config_init, -+ /* Interrupts are handled by the switch, not the PHY -+ * itself. -+ */ -+ .config_intr = genphy_no_config_intr, -+ .ack_interrupt = genphy_no_ack_interrupt, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_gephy_read_page, -+ .write_page = mtk_gephy_write_page, -+ }, -+ { -+ PHY_ID_MATCH_EXACT(0x03a29441), -+ .name = "MediaTek MT7531 PHY", -+ .config_init = mt7531_phy_config_init, -+ /* Interrupts are handled by the switch, not the PHY -+ * itself. -+ */ -+ .config_intr = genphy_no_config_intr, -+ .ack_interrupt = genphy_no_ack_interrupt, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_gephy_read_page, -+ .write_page = mtk_gephy_write_page, -+ }, -+}; -+ -+module_phy_driver(mtk_gephy_driver); -+ -+static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { -+ { PHY_ID_MATCH_VENDOR(0x03a29400) }, -+ { } -+}; diff --git a/target/linux/generic/backport-5.10/772-v5.14-net-dsa-mt7530-add-interrupt-support.patch b/target/linux/generic/backport-5.10/772-v5.14-net-dsa-mt7530-add-interrupt-support.patch deleted file mode 100644 index c7e3a4ceb4..0000000000 --- a/target/linux/generic/backport-5.10/772-v5.14-net-dsa-mt7530-add-interrupt-support.patch +++ /dev/null @@ -1,425 +0,0 @@ -From ba751e28d44255744a30190faad0ca09b455c44d Mon Sep 17 00:00:00 2001 -From: DENG Qingfang -Date: Wed, 19 May 2021 11:32:00 +0800 -Subject: [PATCH] net: dsa: mt7530: add interrupt support - -Add support for MT7530 interrupt controller to handle internal PHYs. -In order to assign an IRQ number to each PHY, the registration of MDIO bus -is also done in this driver. - -Signed-off-by: DENG Qingfang -Reviewed-by: Andrew Lunn -Reviewed-by: Florian Fainelli -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller ---- - drivers/net/dsa/mt7530.c | 264 +++++++++++++++++++++++++++++++++++---- - drivers/net/dsa/mt7530.h | 20 ++- - 2 files changed, 256 insertions(+), 28 deletions(-) - ---- a/drivers/net/dsa/mt7530.c -+++ b/drivers/net/dsa/mt7530.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -603,18 +604,14 @@ mt7530_mib_reset(struct dsa_switch *ds) - mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); - } - --static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) -+static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) - { -- struct mt7530_priv *priv = ds->priv; -- - return mdiobus_read_nested(priv->bus, port, regnum); - } - --static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, -+static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, - u16 val) - { -- struct mt7530_priv *priv = ds->priv; -- - return mdiobus_write_nested(priv->bus, port, regnum, val); - } - -@@ -792,9 +789,8 @@ out: - } - - static int --mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) -+mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) - { -- struct mt7530_priv *priv = ds->priv; - int devad; - int ret; - -@@ -810,10 +806,9 @@ mt7531_ind_phy_read(struct dsa_switch *d - } - - static int --mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, -+mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, - u16 data) - { -- struct mt7530_priv *priv = ds->priv; - int devad; - int ret; - -@@ -829,6 +824,22 @@ mt7531_ind_phy_write(struct dsa_switch * - return ret; - } - -+static int -+mt753x_phy_read(struct mii_bus *bus, int port, int regnum) -+{ -+ struct mt7530_priv *priv = bus->priv; -+ -+ return priv->info->phy_read(priv, port, regnum); -+} -+ -+static int -+mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) -+{ -+ struct mt7530_priv *priv = bus->priv; -+ -+ return priv->info->phy_write(priv, port, regnum, val); -+} -+ - static void - mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, - uint8_t *data) -@@ -1796,6 +1807,210 @@ mt7530_setup_gpio(struct mt7530_priv *pr - return devm_gpiochip_add_data(dev, gc, priv); - } - -+static irqreturn_t -+mt7530_irq_thread_fn(int irq, void *dev_id) -+{ -+ struct mt7530_priv *priv = dev_id; -+ bool handled = false; -+ u32 val; -+ int p; -+ -+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); -+ val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); -+ mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); -+ mutex_unlock(&priv->bus->mdio_lock); -+ -+ for (p = 0; p < MT7530_NUM_PHYS; p++) { -+ if (BIT(p) & val) { -+ unsigned int irq; -+ -+ irq = irq_find_mapping(priv->irq_domain, p); -+ handle_nested_irq(irq); -+ handled = true; -+ } -+ } -+ -+ return IRQ_RETVAL(handled); -+} -+ -+static void -+mt7530_irq_mask(struct irq_data *d) -+{ -+ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); -+ -+ priv->irq_enable &= ~BIT(d->hwirq); -+} -+ -+static void -+mt7530_irq_unmask(struct irq_data *d) -+{ -+ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); -+ -+ priv->irq_enable |= BIT(d->hwirq); -+} -+ -+static void -+mt7530_irq_bus_lock(struct irq_data *d) -+{ -+ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); -+ -+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); -+} -+ -+static void -+mt7530_irq_bus_sync_unlock(struct irq_data *d) -+{ -+ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); -+ -+ mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); -+ mutex_unlock(&priv->bus->mdio_lock); -+} -+ -+static struct irq_chip mt7530_irq_chip = { -+ .name = KBUILD_MODNAME, -+ .irq_mask = mt7530_irq_mask, -+ .irq_unmask = mt7530_irq_unmask, -+ .irq_bus_lock = mt7530_irq_bus_lock, -+ .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, -+}; -+ -+static int -+mt7530_irq_map(struct irq_domain *domain, unsigned int irq, -+ irq_hw_number_t hwirq) -+{ -+ irq_set_chip_data(irq, domain->host_data); -+ irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); -+ irq_set_nested_thread(irq, true); -+ irq_set_noprobe(irq); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops mt7530_irq_domain_ops = { -+ .map = mt7530_irq_map, -+ .xlate = irq_domain_xlate_onecell, -+}; -+ -+static void -+mt7530_setup_mdio_irq(struct mt7530_priv *priv) -+{ -+ struct dsa_switch *ds = priv->ds; -+ int p; -+ -+ for (p = 0; p < MT7530_NUM_PHYS; p++) { -+ if (BIT(p) & ds->phys_mii_mask) { -+ unsigned int irq; -+ -+ irq = irq_create_mapping(priv->irq_domain, p); -+ ds->slave_mii_bus->irq[p] = irq; -+ } -+ } -+} -+ -+static int -+mt7530_setup_irq(struct mt7530_priv *priv) -+{ -+ struct device *dev = priv->dev; -+ struct device_node *np = dev->of_node; -+ int ret; -+ -+ if (!of_property_read_bool(np, "interrupt-controller")) { -+ dev_info(dev, "no interrupt support\n"); -+ return 0; -+ } -+ -+ priv->irq = of_irq_get(np, 0); -+ if (priv->irq <= 0) { -+ dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); -+ return priv->irq ? : -EINVAL; -+ } -+ -+ priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, -+ &mt7530_irq_domain_ops, priv); -+ if (!priv->irq_domain) { -+ dev_err(dev, "failed to create IRQ domain\n"); -+ return -ENOMEM; -+ } -+ -+ /* This register must be set for MT7530 to properly fire interrupts */ -+ if (priv->id != ID_MT7531) -+ mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); -+ -+ ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, -+ IRQF_ONESHOT, KBUILD_MODNAME, priv); -+ if (ret) { -+ irq_domain_remove(priv->irq_domain); -+ dev_err(dev, "failed to request IRQ: %d\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void -+mt7530_free_mdio_irq(struct mt7530_priv *priv) -+{ -+ int p; -+ -+ for (p = 0; p < MT7530_NUM_PHYS; p++) { -+ if (BIT(p) & priv->ds->phys_mii_mask) { -+ unsigned int irq; -+ -+ irq = irq_find_mapping(priv->irq_domain, p); -+ irq_dispose_mapping(irq); -+ } -+ } -+} -+ -+static void -+mt7530_free_irq_common(struct mt7530_priv *priv) -+{ -+ free_irq(priv->irq, priv); -+ irq_domain_remove(priv->irq_domain); -+} -+ -+static void -+mt7530_free_irq(struct mt7530_priv *priv) -+{ -+ mt7530_free_mdio_irq(priv); -+ mt7530_free_irq_common(priv); -+} -+ -+static int -+mt7530_setup_mdio(struct mt7530_priv *priv) -+{ -+ struct dsa_switch *ds = priv->ds; -+ struct device *dev = priv->dev; -+ struct mii_bus *bus; -+ static int idx; -+ int ret; -+ -+ bus = devm_mdiobus_alloc(dev); -+ if (!bus) -+ return -ENOMEM; -+ -+ ds->slave_mii_bus = bus; -+ bus->priv = priv; -+ bus->name = KBUILD_MODNAME "-mii"; -+ snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); -+ bus->read = mt753x_phy_read; -+ bus->write = mt753x_phy_write; -+ bus->parent = dev; -+ bus->phy_mask = ~ds->phys_mii_mask; -+ -+ if (priv->irq) -+ mt7530_setup_mdio_irq(priv); -+ -+ ret = devm_mdiobus_register(dev, bus); -+ if (ret) { -+ dev_err(dev, "failed to register MDIO bus: %d\n", ret); -+ if (priv->irq) -+ mt7530_free_mdio_irq(priv); -+ } -+ -+ return ret; -+} -+ - static int - mt7530_setup(struct dsa_switch *ds) - { -@@ -2747,24 +2962,20 @@ static int - mt753x_setup(struct dsa_switch *ds) - { - struct mt7530_priv *priv = ds->priv; -+ int ret = priv->info->sw_setup(ds); - -- return priv->info->sw_setup(ds); --} -- --static int --mt753x_phy_read(struct dsa_switch *ds, int port, int regnum) --{ -- struct mt7530_priv *priv = ds->priv; -+ if (ret) -+ return ret; - -- return priv->info->phy_read(ds, port, regnum); --} -+ ret = mt7530_setup_irq(priv); -+ if (ret) -+ return ret; - --static int --mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) --{ -- struct mt7530_priv *priv = ds->priv; -+ ret = mt7530_setup_mdio(priv); -+ if (ret && priv->irq) -+ mt7530_free_irq_common(priv); - -- return priv->info->phy_write(ds, port, regnum, val); -+ return ret; - } - - static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, -@@ -2801,8 +3012,6 @@ static const struct dsa_switch_ops mt753 - .get_tag_protocol = mtk_get_tag_protocol, - .setup = mt753x_setup, - .get_strings = mt7530_get_strings, -- .phy_read = mt753x_phy_read, -- .phy_write = mt753x_phy_write, - .get_ethtool_stats = mt7530_get_ethtool_stats, - .get_sset_count = mt7530_get_sset_count, - .set_ageing_time = mt7530_set_ageing_time, -@@ -2985,6 +3194,9 @@ mt7530_remove(struct mdio_device *mdiode - dev_err(priv->dev, "Failed to disable io pwr: %d\n", - ret); - -+ if (priv->irq) -+ mt7530_free_irq(priv); -+ - dsa_unregister_switch(priv->ds); - mutex_destroy(&priv->reg_mutex); - } ---- a/drivers/net/dsa/mt7530.h -+++ b/drivers/net/dsa/mt7530.h -@@ -7,6 +7,7 @@ - #define __MT7530_H - - #define MT7530_NUM_PORTS 7 -+#define MT7530_NUM_PHYS 5 - #define MT7530_CPU_PORT 6 - #define MT7530_NUM_FDB_RECORDS 2048 - #define MT7530_ALL_MEMBERS 0xff -@@ -392,6 +393,12 @@ enum mt7531_sgmii_force_duplex { - #define SYS_CTRL_SW_RST BIT(1) - #define SYS_CTRL_REG_RST BIT(0) - -+/* Register for system interrupt */ -+#define MT7530_SYS_INT_EN 0x7008 -+ -+/* Register for system interrupt status */ -+#define MT7530_SYS_INT_STS 0x700c -+ - /* Register for PHY Indirect Access Control */ - #define MT7531_PHY_IAC 0x701C - #define MT7531_PHY_ACS_ST BIT(31) -@@ -713,6 +720,8 @@ static const char *p5_intf_modes(unsigne - } - } - -+struct mt7530_priv; -+ - /* struct mt753x_info - This is the main data structure for holding the specific - * part for each supported device - * @sw_setup: Holding the handler to a device initialization -@@ -737,8 +746,8 @@ struct mt753x_info { - enum mt753x_id id; - - int (*sw_setup)(struct dsa_switch *ds); -- int (*phy_read)(struct dsa_switch *ds, int port, int regnum); -- int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val); -+ int (*phy_read)(struct mt7530_priv *priv, int port, int regnum); -+ int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); - int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); - int (*cpu_port_config)(struct dsa_switch *ds, int port); - bool (*phy_mode_supported)(struct dsa_switch *ds, int port, -@@ -772,6 +781,10 @@ struct mt753x_info { - * registers - * @p6_interface Holding the current port 6 interface - * @p5_intf_sel: Holding the current port 5 interface select -+ * -+ * @irq: IRQ number of the switch -+ * @irq_domain: IRQ domain of the switch irq_chip -+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN - */ - struct mt7530_priv { - struct device *dev; -@@ -793,6 +806,9 @@ struct mt7530_priv { - struct mt7530_port ports[MT7530_NUM_PORTS]; - /* protect among processes for registers access*/ - struct mutex reg_mutex; -+ int irq; -+ struct irq_domain *irq_domain; -+ u32 irq_enable; - }; - - struct mt7530_hw_vlan_entry { diff --git a/target/linux/generic/backport-5.10/773-v5.18-1-net-dsa-Move-VLAN-filtering-syncing-out-of-dsa_switc.patch b/target/linux/generic/backport-5.10/773-v5.18-1-net-dsa-Move-VLAN-filtering-syncing-out-of-dsa_switc.patch deleted file mode 100644 index eb60134a1e..0000000000 --- a/target/linux/generic/backport-5.10/773-v5.18-1-net-dsa-Move-VLAN-filtering-syncing-out-of-dsa_switc.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 7164a8cde4b42f76474088ccaf53f1e463d4e2f6 Mon Sep 17 00:00:00 2001 -From: Tobias Waldekranz -Date: Mon, 24 Jan 2022 22:09:43 +0100 -Subject: [PATCH 5.10 1/2] net: dsa: Move VLAN filtering syncing out of - dsa_switch_bridge_leave -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit 381a730182f1d174e1950cd4e63e885b1c302051 upstream. - -Most of dsa_switch_bridge_leave was, in fact, dealing with the syncing -of VLAN filtering for switches on which that is a global -setting. Separate the two phases to prepare for the cross-chip related -bugfix in the following commit. - -Signed-off-by: Tobias Waldekranz -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller -Signed-off-by: Marek Behún ---- - net/dsa/switch.c | 39 ++++++++++++++++++++++++++------------- - 1 file changed, 26 insertions(+), 13 deletions(-) - ---- a/net/dsa/switch.c -+++ b/net/dsa/switch.c -@@ -104,23 +104,12 @@ static int dsa_switch_bridge_join(struct - return 0; - } - --static int dsa_switch_bridge_leave(struct dsa_switch *ds, -- struct dsa_notifier_bridge_info *info) -+static int dsa_switch_sync_vlan_filtering(struct dsa_switch *ds, -+ struct dsa_notifier_bridge_info *info) - { - bool unset_vlan_filtering = br_vlan_enabled(info->br); -- struct dsa_switch_tree *dst = ds->dst; - int err, i; - -- if (dst->index == info->tree_index && ds->index == info->sw_index && -- ds->ops->port_bridge_leave) -- ds->ops->port_bridge_leave(ds, info->port, info->br); -- -- if ((dst->index != info->tree_index || ds->index != info->sw_index) && -- ds->ops->crosschip_bridge_leave) -- ds->ops->crosschip_bridge_leave(ds, info->tree_index, -- info->sw_index, info->port, -- info->br); -- - /* If the bridge was vlan_filtering, the bridge core doesn't trigger an - * event for changing vlan_filtering setting upon slave ports leaving - * it. That is a good thing, because that lets us handle it and also -@@ -153,6 +142,30 @@ static int dsa_switch_bridge_leave(struc - if (err && err != EOPNOTSUPP) - return err; - } -+ -+ return 0; -+} -+ -+static int dsa_switch_bridge_leave(struct dsa_switch *ds, -+ struct dsa_notifier_bridge_info *info) -+{ -+ struct dsa_switch_tree *dst = ds->dst; -+ int err; -+ -+ if (dst->index == info->tree_index && ds->index == info->sw_index && -+ ds->ops->port_bridge_leave) -+ ds->ops->port_bridge_leave(ds, info->port, info->br); -+ -+ if ((dst->index != info->tree_index || ds->index != info->sw_index) && -+ ds->ops->crosschip_bridge_leave) -+ ds->ops->crosschip_bridge_leave(ds, info->tree_index, -+ info->sw_index, info->port, -+ info->br); -+ -+ err = dsa_switch_sync_vlan_filtering(ds, info); -+ if (err) -+ return err; -+ - return 0; - } - diff --git a/target/linux/generic/backport-5.10/773-v5.18-2-net-dsa-Avoid-cross-chip-syncing-of-VLAN-filtering.patch b/target/linux/generic/backport-5.10/773-v5.18-2-net-dsa-Avoid-cross-chip-syncing-of-VLAN-filtering.patch deleted file mode 100644 index 0b36ef7cec..0000000000 --- a/target/linux/generic/backport-5.10/773-v5.18-2-net-dsa-Avoid-cross-chip-syncing-of-VLAN-filtering.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 6948a6654ffc878fc0258b363da77e7fd775b2d9 Mon Sep 17 00:00:00 2001 -From: Tobias Waldekranz -Date: Mon, 24 Jan 2022 22:09:44 +0100 -Subject: [PATCH 5.10 2/2] net: dsa: Avoid cross-chip syncing of VLAN filtering -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -commit 108dc8741c203e9d6ce4e973367f1bac20c7192b upstream. - -Changes to VLAN filtering are not applicable to cross-chip -notifications. - -On a system like this: - -.-----. .-----. .-----. -| sw1 +---+ sw2 +---+ sw3 | -'-1-2-' '-1-2-' '-1-2-' - -Before this change, upon sw1p1 leaving a bridge, a call to -dsa_port_vlan_filtering would also be made to sw2p1 and sw3p1. - -In this scenario: - -.---------. .-----. .-----. -| sw1 +---+ sw2 +---+ sw3 | -'-1-2-3-4-' '-1-2-' '-1-2-' - -When sw1p4 would leave a bridge, dsa_port_vlan_filtering would be -called for sw2 and sw3 with a non-existing port - leading to array -out-of-bounds accesses and crashes on mv88e6xxx. - -Fixes: d371b7c92d19 ("net: dsa: Unset vlan_filtering when ports leave the bridge") -Signed-off-by: Tobias Waldekranz -Reviewed-by: Vladimir Oltean -Signed-off-by: David S. Miller -Signed-off-by: Marek Behún ---- - net/dsa/switch.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - ---- a/net/dsa/switch.c -+++ b/net/dsa/switch.c -@@ -162,9 +162,11 @@ static int dsa_switch_bridge_leave(struc - info->sw_index, info->port, - info->br); - -- err = dsa_switch_sync_vlan_filtering(ds, info); -- if (err) -- return err; -+ if (dst->index == info->tree_index && ds->index == info->sw_index) { -+ err = dsa_switch_sync_vlan_filtering(ds, info); -+ if (err) -+ return err; -+ } - - return 0; - } diff --git a/target/linux/generic/backport-5.10/774-v5.15-net-dsa-mv88e6xxx-keep-the-pvid-at-0-when-VLAN-unawa.patch b/target/linux/generic/backport-5.10/774-v5.15-net-dsa-mv88e6xxx-keep-the-pvid-at-0-when-VLAN-unawa.patch deleted file mode 100644 index 13cc8f3d69..0000000000 --- a/target/linux/generic/backport-5.10/774-v5.15-net-dsa-mv88e6xxx-keep-the-pvid-at-0-when-VLAN-unawa.patch +++ /dev/null @@ -1,225 +0,0 @@ -From 675992be6f7b603b8cfda4678f173e1021fc1ab6 Mon Sep 17 00:00:00 2001 -From: Vladimir Oltean -Date: Thu, 7 Oct 2021 19:47:10 +0300 -Subject: [PATCH] net: dsa: mv88e6xxx: keep the pvid at 0 when VLAN-unaware - -The VLAN support in mv88e6xxx has a loaded history. Commit 2ea7a679ca2a -("net: dsa: Don't add vlans when vlan filtering is disabled") noticed -some issues with VLAN and decided the best way to deal with them was to -make the DSA core ignore VLANs added by the bridge while VLAN awareness -is turned off. Those issues were never explained, just presented as -"at least one corner case". - -That approach had problems of its own, presented by -commit 54a0ed0df496 ("net: dsa: provide an option for drivers to always -receive bridge VLANs") for the DSA core, followed by -commit 1fb74191988f ("net: dsa: mv88e6xxx: fix vlan setup") which -applied ds->configure_vlan_while_not_filtering = true for mv88e6xxx in -particular. - -We still don't know what corner case Andrew saw when he wrote -commit 2ea7a679ca2a ("net: dsa: Don't add vlans when vlan filtering is -disabled"), but Tobias now reports that when we use TX forwarding -offload, pinging an external station from the bridge device is broken if -the front-facing DSA user port has flooding turned off. The full -description is in the link below, but for short, when a mv88e6xxx port -is under a VLAN-unaware bridge, it inherits that bridge's pvid. -So packets ingressing a user port will be classified to e.g. VID 1 -(assuming that value for the bridge_default_pvid), whereas when -tag_dsa.c xmits towards a user port, it always sends packets using a VID -of 0 if that port is standalone or under a VLAN-unaware bridge - or at -least it did so prior to commit d82f8ab0d874 ("net: dsa: tag_dsa: -offload the bridge forwarding process"). - -In any case, when there is a conversation between the CPU and a station -connected to a user port, the station's MAC address is learned in VID 1 -but the CPU tries to transmit through VID 0. The packets reach the -intended station, but via flooding and not by virtue of matching the -existing ATU entry. - -DSA has established (and enforced in other drivers: sja1105, felix, -mt7530) that a VLAN-unaware port should use a private pvid, and not -inherit the one from the bridge. The bridge's pvid should only be -inherited when that bridge is VLAN-aware, so all state transitions need -to be handled. On the other hand, all bridge VLANs should sit in the VTU -starting with the moment when the bridge offloads them via switchdev, -they are just not used. - -This solves the problem that Tobias sees because packets ingressing on -VLAN-unaware user ports now get classified to VID 0, which is also the -VID used by tag_dsa.c on xmit. - -Fixes: d82f8ab0d874 ("net: dsa: tag_dsa: offload the bridge forwarding process") -Link: https://patchwork.kernel.org/project/netdevbpf/patch/20211003222312.284175-2-vladimir.oltean@nxp.com/#24491503 -Reported-by: Tobias Waldekranz -Signed-off-by: Vladimir Oltean -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/mv88e6xxx/chip.c | 56 +++++++++++++++++++++++++++++--- - drivers/net/dsa/mv88e6xxx/chip.h | 6 ++++ - drivers/net/dsa/mv88e6xxx/port.c | 21 ++++++++++++ - drivers/net/dsa/mv88e6xxx/port.h | 2 ++ - 4 files changed, 81 insertions(+), 4 deletions(-) - ---- a/drivers/net/dsa/mv88e6xxx/chip.c -+++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -1590,6 +1590,26 @@ static int mv88e6xxx_port_check_hw_vlan( - return 0; - } - -+static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) -+{ -+ struct dsa_port *dp = dsa_to_port(chip->ds, port); -+ struct mv88e6xxx_port *p = &chip->ports[port]; -+ bool drop_untagged = false; -+ u16 pvid = 0; -+ int err; -+ -+ if (dp->bridge_dev && br_vlan_enabled(dp->bridge_dev)) { -+ pvid = p->bridge_pvid.vid; -+ drop_untagged = !p->bridge_pvid.valid; -+ } -+ -+ err = mv88e6xxx_port_set_pvid(chip, port, pvid); -+ if (err) -+ return err; -+ -+ return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); -+} -+ - static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, - bool vlan_filtering, - struct switchdev_trans *trans) -@@ -1603,7 +1623,16 @@ static int mv88e6xxx_port_vlan_filtering - return chip->info->max_vid ? 0 : -EOPNOTSUPP; - - mv88e6xxx_reg_lock(chip); -+ - err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); -+ if (err) -+ goto unlock; -+ -+ err = mv88e6xxx_port_commit_pvid(chip, port); -+ if (err) -+ goto unlock; -+ -+unlock: - mv88e6xxx_reg_unlock(chip); - - return err; -@@ -1986,8 +2015,10 @@ static void mv88e6xxx_port_vlan_add(stru - struct mv88e6xxx_chip *chip = ds->priv; - bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; - bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; -+ struct mv88e6xxx_port *p = &chip->ports[port]; - bool warn; - u8 member; -+ int err; - u16 vid; - - if (!chip->info->max_vid) -@@ -2012,9 +2043,23 @@ static void mv88e6xxx_port_vlan_add(stru - dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, - vid, untagged ? 'u' : 't'); - -- if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) -- dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, -- vlan->vid_end); -+ if (pvid) { -+ p->bridge_pvid.vid = vlan->vid_end; -+ p->bridge_pvid.valid = true; -+ -+ err = mv88e6xxx_port_commit_pvid(chip, port); -+ if (err) -+ dev_err(ds->dev, "p%d: failed to set PVID %d", port, -+ vlan->vid_end); -+ } else if (vlan->vid_end && p->bridge_pvid.vid == vlan->vid_end) { -+ /* The old pvid was reinstalled as a non-pvid VLAN */ -+ p->bridge_pvid.valid = false; -+ -+ err = mv88e6xxx_port_commit_pvid(chip, port); -+ if (err) -+ dev_err(ds->dev, "p%d: failed to unset PVID %d", port, -+ vlan->vid_end); -+ } - - mv88e6xxx_reg_unlock(chip); - } -@@ -2065,6 +2110,7 @@ static int mv88e6xxx_port_vlan_del(struc - const struct switchdev_obj_port_vlan *vlan) - { - struct mv88e6xxx_chip *chip = ds->priv; -+ struct mv88e6xxx_port *p = &chip->ports[port]; - u16 pvid, vid; - int err = 0; - -@@ -2083,7 +2129,9 @@ static int mv88e6xxx_port_vlan_del(struc - goto unlock; - - if (vid == pvid) { -- err = mv88e6xxx_port_set_pvid(chip, port, 0); -+ p->bridge_pvid.valid = false; -+ -+ err = mv88e6xxx_port_commit_pvid(chip, port); - if (err) - goto unlock; - } ---- a/drivers/net/dsa/mv88e6xxx/chip.h -+++ b/drivers/net/dsa/mv88e6xxx/chip.h -@@ -224,9 +224,15 @@ struct mv88e6xxx_policy { - u16 vid; - }; - -+struct mv88e6xxx_vlan { -+ u16 vid; -+ bool valid; -+}; -+ - struct mv88e6xxx_port { - struct mv88e6xxx_chip *chip; - int port; -+ struct mv88e6xxx_vlan bridge_pvid; - u64 serdes_stats[2]; - u64 atu_member_violation; - u64 atu_miss_violation; ---- a/drivers/net/dsa/mv88e6xxx/port.c -+++ b/drivers/net/dsa/mv88e6xxx/port.c -@@ -1062,6 +1062,27 @@ int mv88e6xxx_port_set_8021q_mode(struct - return 0; - } - -+int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, -+ bool drop_untagged) -+{ -+ u16 old, new; -+ int err; -+ -+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old); -+ if (err) -+ return err; -+ -+ if (drop_untagged) -+ new = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; -+ else -+ new = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED; -+ -+ if (new == old) -+ return 0; -+ -+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new); -+} -+ - int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port) - { - u16 reg; ---- a/drivers/net/dsa/mv88e6xxx/port.h -+++ b/drivers/net/dsa/mv88e6xxx/port.h -@@ -364,6 +364,8 @@ int mv88e6390x_port_set_cmode(struct mv8 - phy_interface_t mode); - int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); - int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); -+int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, -+ bool drop_untagged); - int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port); - int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, - int upstream_port); diff --git a/target/linux/generic/backport-5.10/775-v5.18-01-net-phy-at803x-move-page-selection-fix-to-config_init.patch b/target/linux/generic/backport-5.10/775-v5.18-01-net-phy-at803x-move-page-selection-fix-to-config_init.patch deleted file mode 100644 index 5d1246893b..0000000000 --- a/target/linux/generic/backport-5.10/775-v5.18-01-net-phy-at803x-move-page-selection-fix-to-config_init.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 4f3a00c7f5b2cfe4e127fd3fe49b55e1b318c01f Mon Sep 17 00:00:00 2001 -From: Robert Hancock -Date: Tue, 25 Jan 2022 10:54:08 -0600 -Subject: [PATCH] net: phy: at803x: move page selection fix to config_init - -The fix to select the copper page on AR8031 was being done in the probe -function rather than config_init, so it would not be redone after resume -from suspend. Move this to config_init so it is always redone when -needed. - -Fixes: c329e5afb42f ("net: phy: at803x: select correct page on config init") -Signed-off-by: Robert Hancock -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 40 ++++++++++++++++------------------------ - 1 file changed, 16 insertions(+), 24 deletions(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -651,25 +651,7 @@ static int at803x_probe(struct phy_devic - return ret; - } - -- /* Some bootloaders leave the fiber page selected. -- * Switch to the copper page, as otherwise we read -- * the PHY capabilities from the fiber side. -- */ -- if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { -- phy_lock_mdio_bus(phydev); -- ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); -- phy_unlock_mdio_bus(phydev); -- if (ret) -- goto err; -- } -- - return 0; -- --err: -- if (priv->vddio) -- regulator_disable(priv->vddio); -- -- return ret; - } - - static void at803x_remove(struct phy_device *phydev) -@@ -745,6 +727,22 @@ static int at803x_config_init(struct phy - { - int ret; - -+ if (phydev->drv->phy_id == ATH8031_PHY_ID) { -+ /* Some bootloaders leave the fiber page selected. -+ * Switch to the copper page, as otherwise we read -+ * the PHY capabilities from the fiber side. -+ */ -+ phy_lock_mdio_bus(phydev); -+ ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); -+ phy_unlock_mdio_bus(phydev); -+ if (ret) -+ return ret; -+ -+ ret = at8031_pll_config(phydev); -+ if (ret < 0) -+ return ret; -+ } -+ - /* The RX and TX delay default is: - * after HW reset: RX delay enabled and TX delay disabled - * after SW reset: RX delay enabled, while TX delay retains the -@@ -770,12 +768,6 @@ static int at803x_config_init(struct phy - if (ret < 0) - return ret; - -- if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) { -- ret = at8031_pll_config(phydev); -- if (ret < 0) -- return ret; -- } -- - return 0; - } - diff --git a/target/linux/generic/backport-5.10/775-v5.18-02-net-phy-at803x-add-fiber-support.patch b/target/linux/generic/backport-5.10/775-v5.18-02-net-phy-at803x-add-fiber-support.patch deleted file mode 100644 index 18526591f8..0000000000 --- a/target/linux/generic/backport-5.10/775-v5.18-02-net-phy-at803x-add-fiber-support.patch +++ /dev/null @@ -1,193 +0,0 @@ -From 3265f421887847db9ae2c01a00645e33608556d8 Mon Sep 17 00:00:00 2001 -From: Robert Hancock -Date: Tue, 25 Jan 2022 10:54:09 -0600 -Subject: [PATCH] net: phy: at803x: add fiber support - -Previously this driver always forced the copper page to be selected, -however for AR8031 in 100Base-FX or 1000Base-X modes, the fiber page -needs to be selected. Set the appropriate mode based on the hardware -mode_cfg strap selection. - -Enable the appropriate interrupt bits to detect fiber-side link up -or down events. - -Update config_aneg and read_status methods to use the appropriate -Clause 37 calls when fiber mode is in use. - -Signed-off-by: Robert Hancock -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 76 +++++++++++++++++++++++++++++++++++----- - 1 file changed, 67 insertions(+), 9 deletions(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -48,6 +48,8 @@ - #define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12) - #define AT803X_INTR_ENABLE_LINK_FAIL BIT(11) - #define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10) -+#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8) -+#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7) - #define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5) - #define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1) - #define AT803X_INTR_ENABLE_WOL BIT(0) -@@ -82,6 +84,17 @@ - - #define AT803X_MODE_CFG_MASK 0x0F - #define AT803X_MODE_CFG_SGMII 0x01 -+#define AT803X_MODE_CFG_BASET_RGMII 0x00 -+#define AT803X_MODE_CFG_BASET_SGMII 0x01 -+#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02 -+#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03 -+#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04 -+#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05 -+#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06 -+#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07 -+#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B -+#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E -+#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F - - #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/ - #define AT803X_PSSR_MR_AN_COMPLETE 0x0200 -@@ -189,6 +202,8 @@ struct at803x_priv { - #define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ - u16 clk_25m_reg; - u16 clk_25m_mask; -+ bool is_fiber; -+ bool is_1000basex; - struct regulator_dev *vddio_rdev; - struct regulator_dev *vddh_rdev; - struct regulator *vddio; -@@ -651,7 +666,33 @@ static int at803x_probe(struct phy_devic - return ret; - } - -+ if (phydev->drv->phy_id == ATH8031_PHY_ID) { -+ int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); -+ int mode_cfg; -+ -+ if (ccr < 0) -+ goto err; -+ mode_cfg = ccr & AT803X_MODE_CFG_MASK; -+ -+ switch (mode_cfg) { -+ case AT803X_MODE_CFG_BX1000_RGMII_50OHM: -+ case AT803X_MODE_CFG_BX1000_RGMII_75OHM: -+ priv->is_1000basex = true; -+ fallthrough; -+ case AT803X_MODE_CFG_FX100_RGMII_50OHM: -+ case AT803X_MODE_CFG_FX100_RGMII_75OHM: -+ priv->is_fiber = true; -+ break; -+ } -+ } -+ - return 0; -+ -+err: -+ if (priv->vddio) -+ regulator_disable(priv->vddio); -+ -+ return ret; - } - - static void at803x_remove(struct phy_device *phydev) -@@ -664,6 +705,7 @@ static void at803x_remove(struct phy_dev - - static int at803x_get_features(struct phy_device *phydev) - { -+ struct at803x_priv *priv = phydev->priv; - int err; - - err = genphy_read_abilities(phydev); -@@ -681,12 +723,13 @@ static int at803x_get_features(struct ph - * As a result of that, ESTATUS_1000_XFULL is set - * to 1 even when operating in copper TP mode. - * -- * Remove this mode from the supported link modes, -- * as this driver currently only supports copper -- * operation. -+ * Remove this mode from the supported link modes -+ * when not operating in 1000BaseX mode. - */ -- linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, -- phydev->supported); -+ if (!priv->is_1000basex) -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, -+ phydev->supported); -+ - return 0; - } - -@@ -725,15 +768,18 @@ static int at8031_pll_config(struct phy_ - - static int at803x_config_init(struct phy_device *phydev) - { -+ struct at803x_priv *priv = phydev->priv; - int ret; - - if (phydev->drv->phy_id == ATH8031_PHY_ID) { - /* Some bootloaders leave the fiber page selected. -- * Switch to the copper page, as otherwise we read -- * the PHY capabilities from the fiber side. -+ * Switch to the appropriate page (fiber or copper), as otherwise we -+ * read the PHY capabilities from the wrong page. - */ - phy_lock_mdio_bus(phydev); -- ret = at803x_write_page(phydev, AT803X_PAGE_COPPER); -+ ret = at803x_write_page(phydev, -+ priv->is_fiber ? AT803X_PAGE_FIBER : -+ AT803X_PAGE_COPPER); - phy_unlock_mdio_bus(phydev); - if (ret) - return ret; -@@ -782,6 +828,7 @@ static int at803x_ack_interrupt(struct p - - static int at803x_config_intr(struct phy_device *phydev) - { -+ struct at803x_priv *priv = phydev->priv; - int err; - int value; - -@@ -793,6 +840,10 @@ static int at803x_config_intr(struct phy - value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED; - value |= AT803X_INTR_ENABLE_LINK_FAIL; - value |= AT803X_INTR_ENABLE_LINK_SUCCESS; -+ if (priv->is_fiber) { -+ value |= AT803X_INTR_ENABLE_LINK_FAIL_BX; -+ value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX; -+ } - - err = phy_write(phydev, AT803X_INTR_ENABLE, value); - } -@@ -859,8 +910,12 @@ static int at803x_aneg_done(struct phy_d - - static int at803x_read_status(struct phy_device *phydev) - { -+ struct at803x_priv *priv = phydev->priv; - int ss, err, old_link = phydev->link; - -+ if (priv->is_1000basex) -+ return genphy_c37_read_status(phydev); -+ - /* Update the link, but return if there was an error */ - err = genphy_update_link(phydev); - if (err) -@@ -959,6 +1014,7 @@ static int at803x_config_mdix(struct phy - - static int at803x_config_aneg(struct phy_device *phydev) - { -+ struct at803x_priv *priv = phydev->priv; - int ret; - - ret = at803x_config_mdix(phydev, phydev->mdix_ctrl); -@@ -975,6 +1031,9 @@ static int at803x_config_aneg(struct phy - return ret; - } - -+ if (priv->is_1000basex) -+ return genphy_c37_config_aneg(phydev); -+ - return genphy_config_aneg(phydev); - } - diff --git a/target/linux/generic/backport-5.10/775-v5.18-03-net-phy-at803x-support-downstream-SFP-cage.patch b/target/linux/generic/backport-5.10/775-v5.18-03-net-phy-at803x-support-downstream-SFP-cage.patch deleted file mode 100644 index 73dea9c265..0000000000 --- a/target/linux/generic/backport-5.10/775-v5.18-03-net-phy-at803x-support-downstream-SFP-cage.patch +++ /dev/null @@ -1,95 +0,0 @@ -From dc4d5fcc5d365c9f70ea3f5c09bdf70e988fad50 Mon Sep 17 00:00:00 2001 -From: Robert Hancock -Date: Tue, 25 Jan 2022 10:54:10 -0600 -Subject: [PATCH] net: phy: at803x: Support downstream SFP cage - -Add support for downstream SFP cages for AR8031 and AR8033. This is -primarily intended for fiber modules or direct-attach cables, however -copper modules which work in 1000Base-X mode may also function. Such -modules are allowed with a warning. - -Signed-off-by: Robert Hancock -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 56 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 56 insertions(+) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -19,6 +19,8 @@ - #include - #include - #include -+#include -+#include - #include - - #define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10 -@@ -551,6 +553,55 @@ static bool at803x_match_phy_id(struct p - == (phy_id & phydev->drv->phy_id_mask); - } - -+static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) -+{ -+ struct phy_device *phydev = upstream; -+ __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support); -+ __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support); -+ phy_interface_t iface; -+ -+ linkmode_zero(phy_support); -+ phylink_set(phy_support, 1000baseX_Full); -+ phylink_set(phy_support, 1000baseT_Full); -+ phylink_set(phy_support, Autoneg); -+ phylink_set(phy_support, Pause); -+ phylink_set(phy_support, Asym_Pause); -+ -+ linkmode_zero(sfp_support); -+ sfp_parse_support(phydev->sfp_bus, id, sfp_support); -+ /* Some modules support 10G modes as well as others we support. -+ * Mask out non-supported modes so the correct interface is picked. -+ */ -+ linkmode_and(sfp_support, phy_support, sfp_support); -+ -+ if (linkmode_empty(sfp_support)) { -+ dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); -+ return -EINVAL; -+ } -+ -+ iface = sfp_select_interface(phydev->sfp_bus, sfp_support); -+ -+ /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes -+ * interface for use with SFP modules. -+ * However, some copper modules detected as having a preferred SGMII -+ * interface do default to and function in 1000Base-X mode, so just -+ * print a warning and allow such modules, as they may have some chance -+ * of working. -+ */ -+ if (iface == PHY_INTERFACE_MODE_SGMII) -+ dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n"); -+ else if (iface != PHY_INTERFACE_MODE_1000BASEX) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static const struct sfp_upstream_ops at803x_sfp_ops = { -+ .attach = phy_sfp_attach, -+ .detach = phy_sfp_detach, -+ .module_insert = at803x_sfp_insert, -+}; -+ - static int at803x_parse_dt(struct phy_device *phydev) - { - struct device_node *node = phydev->mdio.dev.of_node; -@@ -639,6 +690,11 @@ static int at803x_parse_dt(struct phy_de - phydev_err(phydev, "failed to get VDDIO regulator\n"); - return PTR_ERR(priv->vddio); - } -+ -+ /* Only AR8031/8033 support 1000Base-X for SFP modules */ -+ ret = phy_sfp_probe(phydev, &at803x_sfp_ops); -+ if (ret < 0) -+ return ret; - } - - return 0; diff --git a/target/linux/generic/backport-5.10/775-v5.18-04-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch b/target/linux/generic/backport-5.10/775-v5.18-04-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch deleted file mode 100644 index 61fe3d259d..0000000000 --- a/target/linux/generic/backport-5.10/775-v5.18-04-net-phy-at803x-fix-NULL-pointer-dereference-on-AR9331-PHY.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 9926de7315be3d606cc011a305ad9adb9e8e14c9 Mon Sep 17 00:00:00 2001 -From: Oleksij Rempel -Date: Sat, 18 Jun 2022 14:23:33 +0200 -Subject: [PATCH] net: phy: at803x: fix NULL pointer dereference on AR9331 PHY - -Latest kernel will explode on the PHY interrupt config, since it depends -now on allocated priv. So, run probe to allocate priv to fix it. - - ar9331_switch ethernet.1:10 lan0 (uninitialized): PHY [!ahb!ethernet@1a000000!mdio!switch@10:00] driver [Qualcomm Atheros AR9331 built-in PHY] (irq=13) - CPU 0 Unable to handle kernel paging request at virtual address 0000000a, epc == 8050e8a8, ra == 80504b34 - ... - Call Trace: - [<8050e8a8>] at803x_config_intr+0x5c/0xd0 - [<80504b34>] phy_request_interrupt+0xa8/0xd0 - [<8050289c>] phylink_bringup_phy+0x2d8/0x3ac - [<80502b68>] phylink_fwnode_phy_connect+0x118/0x130 - [<8074d8ec>] dsa_slave_create+0x270/0x420 - [<80743b04>] dsa_port_setup+0x12c/0x148 - [<8074580c>] dsa_register_switch+0xaf0/0xcc0 - [<80511344>] ar9331_sw_probe+0x370/0x388 - [<8050cb78>] mdio_probe+0x44/0x70 - [<804df300>] really_probe+0x200/0x424 - [<804df7b4>] __driver_probe_device+0x290/0x298 - [<804df810>] driver_probe_device+0x54/0xe4 - [<804dfd50>] __device_attach_driver+0xe4/0x130 - [<804dcb00>] bus_for_each_drv+0xb4/0xd8 - [<804dfac4>] __device_attach+0x104/0x1a4 - [<804ddd24>] bus_probe_device+0x48/0xc4 - [<804deb44>] deferred_probe_work_func+0xf0/0x10c - [<800a0ffc>] process_one_work+0x314/0x4d4 - [<800a17fc>] worker_thread+0x2a4/0x354 - [<800a9a54>] kthread+0x134/0x13c - [<8006306c>] ret_from_kernel_thread+0x14/0x1c - -Same Issue would affect some other PHYs (QCA8081, QCA9561), so fix it -too. - -Fixes: 3265f4218878 ("net: phy: at803x: add fiber support") -Signed-off-by: Oleksij Rempel -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - drivers/net/phy/at803x.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -1530,6 +1530,8 @@ static struct phy_driver at803x_driver[] - /* ATHEROS AR9331 */ - PHY_ID_MATCH_EXACT(ATH9331_PHY_ID), - .name = "Qualcomm Atheros AR9331 built-in PHY", -+ .probe = at803x_probe, -+ .remove = at803x_remove, - .suspend = at803x_suspend, - .resume = at803x_resume, - .flags = PHY_POLL_CABLE_TEST, diff --git a/target/linux/generic/backport-5.10/775-v5.18-05-net-phy-at803x-fix-error-return-code-in-at803x_probe.patch b/target/linux/generic/backport-5.10/775-v5.18-05-net-phy-at803x-fix-error-return-code-in-at803x_probe.patch deleted file mode 100644 index fc31775c19..0000000000 --- a/target/linux/generic/backport-5.10/775-v5.18-05-net-phy-at803x-fix-error-return-code-in-at803x_probe.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 1f0dd412e34e177621769866bef347f0b22364df Mon Sep 17 00:00:00 2001 -From: Wei Yongjun -Date: Fri, 18 Nov 2022 10:36:35 +0000 -Subject: [PATCH] net: phy: at803x: fix error return code in at803x_probe() - -Fix to return a negative error code from the ccr read error handling -case instead of 0, as done elsewhere in this function. - -Fixes: 3265f4218878 ("net: phy: at803x: add fiber support") -Signed-off-by: Wei Yongjun -Reviewed-by: Andrew Lunn -Link: https://lore.kernel.org/r/20221118103635.254256-1-weiyongjun@huaweicloud.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/phy/at803x.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/net/phy/at803x.c -+++ b/drivers/net/phy/at803x.c -@@ -726,8 +726,10 @@ static int at803x_probe(struct phy_devic - int ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG); - int mode_cfg; - -- if (ccr < 0) -+ if (ccr < 0) { -+ ret = ccr; - goto err; -+ } - mode_cfg = ccr & AT803X_MODE_CFG_MASK; - - switch (mode_cfg) { diff --git a/target/linux/generic/backport-5.10/780-v5.11-net-usb-r8152-Provide-missing-documentation-for-some.patch b/target/linux/generic/backport-5.10/780-v5.11-net-usb-r8152-Provide-missing-documentation-for-some.patch deleted file mode 100644 index e69144fcd8..0000000000 --- a/target/linux/generic/backport-5.10/780-v5.11-net-usb-r8152-Provide-missing-documentation-for-some.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 586f04ce6a391419ca3cc9cef6b6f38570cede88 Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Mon, 2 Nov 2020 11:45:04 +0000 -Subject: [PATCH] net: usb: r8152: Provide missing documentation for - some struct members - -commit 34e653efb602e0651867fb5ab14369b555a61dcd upstream. - -Fixes the following W=1 kernel build warning(s): - - drivers/net/usb/r8152.c:934: warning: Function parameter or member 'blk_hdr' not described in 'fw_mac' - drivers/net/usb/r8152.c:934: warning: Function parameter or member 'reserved' not described in 'fw_mac' - drivers/net/usb/r8152.c:947: warning: Function parameter or member 'blk_hdr' not described in 'fw_phy_patch_key' - drivers/net/usb/r8152.c:947: warning: Function parameter or member 'reserved' not described in 'fw_phy_patch_key' - drivers/net/usb/r8152.c:986: warning: Function parameter or member 'blk_hdr' not described in 'fw_phy_nc' - drivers/net/usb/r8152.c:986: warning: Function parameter or member 'mode_pre' not described in 'fw_phy_nc' - drivers/net/usb/r8152.c:986: warning: Function parameter or member 'mode_post' not described in 'fw_phy_nc' - drivers/net/usb/r8152.c:986: warning: Function parameter or member 'reserved' not described in 'fw_phy_nc' - -Signed-off-by: Lee Jones -Acked-by: Hayes Wang -Link: https://lore.kernel.org/r/20201102114512.1062724-23-lee.jones@linaro.org -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -898,6 +898,7 @@ struct fw_header { - * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB. - * The layout of the firmware block is: - * + + . -+ * @blk_hdr: firmware descriptor (type, length) - * @fw_offset: offset of the firmware binary data. The start address of - * the data would be the address of struct fw_mac + @fw_offset. - * @fw_reg: the register to load the firmware. Depends on chip. -@@ -911,6 +912,7 @@ struct fw_header { - * @bp_num: the break point number which needs to be set for this firmware. - * Depends on the firmware. - * @bp: break points. Depends on firmware. -+ * @reserved: reserved space (unused) - * @fw_ver_reg: the register to store the fw version. - * @fw_ver_data: the firmware version of the current type. - * @info: additional information for debugging, and is followed by the -@@ -936,8 +938,10 @@ struct fw_mac { - /** - * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START. - * This is used to set patch key when loading the firmware of PHY. -+ * @blk_hdr: firmware descriptor (type, length) - * @key_reg: the register to write the patch key. - * @key_data: patch key. -+ * @reserved: reserved space (unused) - */ - struct fw_phy_patch_key { - struct fw_block blk_hdr; -@@ -950,6 +954,7 @@ struct fw_phy_patch_key { - * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC. - * The layout of the firmware block is: - * + + . -+ * @blk_hdr: firmware descriptor (type, length) - * @fw_offset: offset of the firmware binary data. The start address of - * the data would be the address of struct fw_phy_nc + @fw_offset. - * @fw_reg: the register to load the firmware. Depends on chip. -@@ -960,6 +965,7 @@ struct fw_phy_patch_key { - * @mode_reg: the regitster of switching the mode. - * @mod_pre: the mode needing to be set before loading the firmware. - * @mod_post: the mode to be set when finishing to load the firmware. -+ * @reserved: reserved space (unused) - * @bp_start: the start register of break points. Depends on chip. - * @bp_num: the break point number which needs to be set for this firmware. - * Depends on the firmware. diff --git a/target/linux/generic/backport-5.10/781-v5.11-net-usb-r8152-Fix-a-couple-of-spelling-errors-in-fw_.patch b/target/linux/generic/backport-5.10/781-v5.11-net-usb-r8152-Fix-a-couple-of-spelling-errors-in-fw_.patch deleted file mode 100644 index 96a9a3363d..0000000000 --- a/target/linux/generic/backport-5.10/781-v5.11-net-usb-r8152-Fix-a-couple-of-spelling-errors-in-fw_.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 5fcfa846181de6676509696c4cd7b60a22e74077 Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Mon, 2 Nov 2020 11:45:09 +0000 -Subject: [PATCH] net: usb: r8152: Fix a couple of spelling errors in - fw_phy_nc's docs - -commit 9f07814d01ad085b2d9f1d55b4ce532fb2c27110 upstream. - -Fixes the following W=1 kernel build warning(s): - - drivers/net/usb/r8152.c:992: warning: Function parameter or member 'mode_pre' not described in 'fw_phy_nc' - drivers/net/usb/r8152.c:992: warning: Function parameter or member 'mode_post' not described in 'fw_phy_nc' - -Signed-off-by: Lee Jones -Acked-by: Hayes Wang -Link: https://lore.kernel.org/r/20201102114512.1062724-28-lee.jones@linaro.org -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -963,8 +963,8 @@ struct fw_phy_patch_key { - * @patch_en_addr: the register of enabling patch mode. Depends on chip. - * @patch_en_value: patch mode enabled mask. Depends on the firmware. - * @mode_reg: the regitster of switching the mode. -- * @mod_pre: the mode needing to be set before loading the firmware. -- * @mod_post: the mode to be set when finishing to load the firmware. -+ * @mode_pre: the mode needing to be set before loading the firmware. -+ * @mode_post: the mode to be set when finishing to load the firmware. - * @reserved: reserved space (unused) - * @bp_start: the start register of break points. Depends on chip. - * @bp_num: the break point number which needs to be set for this firmware. diff --git a/target/linux/generic/backport-5.10/782-v5.11-net-usb-r8153_ecm-support-ECM-mode-for-RTL8153.patch b/target/linux/generic/backport-5.10/782-v5.11-net-usb-r8153_ecm-support-ECM-mode-for-RTL8153.patch deleted file mode 100644 index 67c762d28c..0000000000 --- a/target/linux/generic/backport-5.10/782-v5.11-net-usb-r8153_ecm-support-ECM-mode-for-RTL8153.patch +++ /dev/null @@ -1,320 +0,0 @@ -From 0ef50460f7f053bd2a911ec53e01bfda646a5574 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Wed, 4 Nov 2020 10:19:22 +0800 -Subject: [PATCH] net/usb/r8153_ecm: support ECM mode for RTL8153 - -commit c1aedf015ebdd0232757a66e2daccf1246bd609c upstream. - -Support ECM mode based on cdc_ether with relative mii functions, -when CONFIG_USB_RTL8152 is not set, or the device is not supported -by r8152 driver. - -Both r8152 and r8153_ecm would check the return value of -rtl8152_get_version() in porbe(). If rtl8152_get_version() -return none zero value, the r8152 is used for the device -with vendor mode. Otherwise, the r8153_ecm is used for the -device with ECM mode. - -Signed-off-by: Hayes Wang -Link: https://lore.kernel.org/r/1394712342-15778-392-Taiwan-albertk@realtek.com -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/Makefile | 2 +- - drivers/net/usb/r8152.c | 30 +------ - drivers/net/usb/r8153_ecm.c | 162 ++++++++++++++++++++++++++++++++++++ - include/linux/usb/r8152.h | 37 ++++++++ - 4 files changed, 204 insertions(+), 27 deletions(-) - create mode 100644 drivers/net/usb/r8153_ecm.c - create mode 100644 include/linux/usb/r8152.h - ---- a/drivers/net/usb/Makefile -+++ b/drivers/net/usb/Makefile -@@ -13,7 +13,7 @@ obj-$(CONFIG_USB_LAN78XX) += lan78xx.o - obj-$(CONFIG_USB_NET_AX8817X) += asix.o - asix-y := asix_devices.o asix_common.o ax88172a.o - obj-$(CONFIG_USB_NET_AX88179_178A) += ax88179_178a.o --obj-$(CONFIG_USB_NET_CDCETHER) += cdc_ether.o -+obj-$(CONFIG_USB_NET_CDCETHER) += cdc_ether.o r8153_ecm.o - obj-$(CONFIG_USB_NET_CDC_EEM) += cdc_eem.o - obj-$(CONFIG_USB_NET_DM9601) += dm9601.o - obj-$(CONFIG_USB_NET_SR9700) += sr9700.o ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - - /* Information for net-next */ - #define NETNEXT_VERSION "11" -@@ -653,18 +654,6 @@ enum rtl_register_content { - - #define INTR_LINK 0x0004 - --#define RTL8152_REQT_READ 0xc0 --#define RTL8152_REQT_WRITE 0x40 --#define RTL8152_REQ_GET_REGS 0x05 --#define RTL8152_REQ_SET_REGS 0x05 -- --#define BYTE_EN_DWORD 0xff --#define BYTE_EN_WORD 0x33 --#define BYTE_EN_BYTE 0x11 --#define BYTE_EN_SIX_BYTES 0x3f --#define BYTE_EN_START_MASK 0x0f --#define BYTE_EN_END_MASK 0xf0 -- - #define RTL8153_MAX_PACKET 9216 /* 9K */ - #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ - ETH_FCS_LEN) -@@ -689,21 +678,9 @@ enum rtl8152_flags { - LENOVO_MACPASSTHRU, - }; - --/* Define these values to match your device */ --#define VENDOR_ID_REALTEK 0x0bda --#define VENDOR_ID_MICROSOFT 0x045e --#define VENDOR_ID_SAMSUNG 0x04e8 --#define VENDOR_ID_LENOVO 0x17ef --#define VENDOR_ID_LINKSYS 0x13b1 --#define VENDOR_ID_NVIDIA 0x0955 --#define VENDOR_ID_TPLINK 0x2357 -- - #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082 - #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387 - --#define MCU_TYPE_PLA 0x0100 --#define MCU_TYPE_USB 0x0000 -- - struct tally_counter { - __le64 tx_packets; - __le64 rx_packets; -@@ -6604,7 +6581,7 @@ static int rtl_fw_init(struct r8152 *tp) - return 0; - } - --static u8 rtl_get_version(struct usb_interface *intf) -+u8 rtl8152_get_version(struct usb_interface *intf) - { - struct usb_device *udev = interface_to_usbdev(intf); - u32 ocp_data = 0; -@@ -6662,12 +6639,13 @@ static u8 rtl_get_version(struct usb_int - - return version; - } -+EXPORT_SYMBOL_GPL(rtl8152_get_version); - - static int rtl8152_probe(struct usb_interface *intf, - const struct usb_device_id *id) - { - struct usb_device *udev = interface_to_usbdev(intf); -- u8 version = rtl_get_version(intf); -+ u8 version = rtl8152_get_version(intf); - struct r8152 *tp; - struct net_device *netdev; - int ret; ---- /dev/null -+++ b/drivers/net/usb/r8153_ecm.c -@@ -0,0 +1,162 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define OCP_BASE 0xe86c -+ -+static int pla_read_word(struct usbnet *dev, u16 index) -+{ -+ u16 byen = BYTE_EN_WORD; -+ u8 shift = index & 2; -+ __le32 tmp; -+ int ret; -+ -+ if (shift) -+ byen <<= shift; -+ -+ index &= ~3; -+ -+ ret = usbnet_read_cmd(dev, RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, index, -+ MCU_TYPE_PLA | byen, &tmp, sizeof(tmp)); -+ if (ret < 0) -+ goto out; -+ -+ ret = __le32_to_cpu(tmp); -+ ret >>= (shift * 8); -+ ret &= 0xffff; -+ -+out: -+ return ret; -+} -+ -+static int pla_write_word(struct usbnet *dev, u16 index, u32 data) -+{ -+ u32 mask = 0xffff; -+ u16 byen = BYTE_EN_WORD; -+ u8 shift = index & 2; -+ __le32 tmp; -+ int ret; -+ -+ data &= mask; -+ -+ if (shift) { -+ byen <<= shift; -+ mask <<= (shift * 8); -+ data <<= (shift * 8); -+ } -+ -+ index &= ~3; -+ -+ ret = usbnet_read_cmd(dev, RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, index, -+ MCU_TYPE_PLA | byen, &tmp, sizeof(tmp)); -+ -+ if (ret < 0) -+ goto out; -+ -+ data |= __le32_to_cpu(tmp) & ~mask; -+ tmp = __cpu_to_le32(data); -+ -+ ret = usbnet_write_cmd(dev, RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, index, -+ MCU_TYPE_PLA | byen, &tmp, sizeof(tmp)); -+ -+out: -+ return ret; -+} -+ -+static int r8153_ecm_mdio_read(struct net_device *netdev, int phy_id, int reg) -+{ -+ struct usbnet *dev = netdev_priv(netdev); -+ int ret; -+ -+ ret = pla_write_word(dev, OCP_BASE, 0xa000); -+ if (ret < 0) -+ goto out; -+ -+ ret = pla_read_word(dev, 0xb400 + reg * 2); -+ -+out: -+ return ret; -+} -+ -+static void r8153_ecm_mdio_write(struct net_device *netdev, int phy_id, int reg, int val) -+{ -+ struct usbnet *dev = netdev_priv(netdev); -+ int ret; -+ -+ ret = pla_write_word(dev, OCP_BASE, 0xa000); -+ if (ret < 0) -+ return; -+ -+ ret = pla_write_word(dev, 0xb400 + reg * 2, val); -+} -+ -+static int r8153_bind(struct usbnet *dev, struct usb_interface *intf) -+{ -+ int status; -+ -+ status = usbnet_cdc_bind(dev, intf); -+ if (status < 0) -+ return status; -+ -+ dev->mii.dev = dev->net; -+ dev->mii.mdio_read = r8153_ecm_mdio_read; -+ dev->mii.mdio_write = r8153_ecm_mdio_write; -+ dev->mii.reg_num_mask = 0x1f; -+ dev->mii.supports_gmii = 1; -+ -+ return status; -+} -+ -+static const struct driver_info r8153_info = { -+ .description = "RTL8153 ECM Device", -+ .flags = FLAG_ETHER, -+ .bind = r8153_bind, -+ .unbind = usbnet_cdc_unbind, -+ .status = usbnet_cdc_status, -+ .manage_power = usbnet_manage_power, -+}; -+ -+static const struct usb_device_id products[] = { -+{ -+ USB_DEVICE_AND_INTERFACE_INFO(VENDOR_ID_REALTEK, 0x8153, USB_CLASS_COMM, -+ USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), -+ .driver_info = (unsigned long)&r8153_info, -+}, -+ -+ { }, /* END */ -+}; -+MODULE_DEVICE_TABLE(usb, products); -+ -+static int rtl8153_ecm_probe(struct usb_interface *intf, -+ const struct usb_device_id *id) -+{ -+#if IS_REACHABLE(CONFIG_USB_RTL8152) -+ if (rtl8152_get_version(intf)) -+ return -ENODEV; -+#endif -+ -+ return usbnet_probe(intf, id); -+} -+ -+static struct usb_driver r8153_ecm_driver = { -+ .name = "r8153_ecm", -+ .id_table = products, -+ .probe = rtl8153_ecm_probe, -+ .disconnect = usbnet_disconnect, -+ .suspend = usbnet_suspend, -+ .resume = usbnet_resume, -+ .reset_resume = usbnet_resume, -+ .supports_autosuspend = 1, -+ .disable_hub_initiated_lpm = 1, -+}; -+ -+module_usb_driver(r8153_ecm_driver); -+ -+MODULE_AUTHOR("Hayes Wang"); -+MODULE_DESCRIPTION("Realtek USB ECM device"); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/include/linux/usb/r8152.h -@@ -0,0 +1,37 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* -+ * Copyright (c) 2020 Realtek Semiconductor Corp. All rights reserved. -+ */ -+ -+#ifndef __LINUX_R8152_H -+#define __LINUX_R8152_H -+ -+#define RTL8152_REQT_READ 0xc0 -+#define RTL8152_REQT_WRITE 0x40 -+#define RTL8152_REQ_GET_REGS 0x05 -+#define RTL8152_REQ_SET_REGS 0x05 -+ -+#define BYTE_EN_DWORD 0xff -+#define BYTE_EN_WORD 0x33 -+#define BYTE_EN_BYTE 0x11 -+#define BYTE_EN_SIX_BYTES 0x3f -+#define BYTE_EN_START_MASK 0x0f -+#define BYTE_EN_END_MASK 0xf0 -+ -+#define MCU_TYPE_PLA 0x0100 -+#define MCU_TYPE_USB 0x0000 -+ -+/* Define these values to match your device */ -+#define VENDOR_ID_REALTEK 0x0bda -+#define VENDOR_ID_MICROSOFT 0x045e -+#define VENDOR_ID_SAMSUNG 0x04e8 -+#define VENDOR_ID_LENOVO 0x17ef -+#define VENDOR_ID_LINKSYS 0x13b1 -+#define VENDOR_ID_NVIDIA 0x0955 -+#define VENDOR_ID_TPLINK 0x2357 -+ -+#if IS_REACHABLE(CONFIG_USB_RTL8152) -+extern u8 rtl8152_get_version(struct usb_interface *intf); -+#endif -+ -+#endif /* __LINUX_R8152_H */ diff --git a/target/linux/generic/backport-5.10/783-v5.12-net-usb-r8152-use-new-tasklet-API.patch b/target/linux/generic/backport-5.10/783-v5.12-net-usb-r8152-use-new-tasklet-API.patch deleted file mode 100644 index 1f43340c68..0000000000 --- a/target/linux/generic/backport-5.10/783-v5.12-net-usb-r8152-use-new-tasklet-API.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 90f1afc7f96c8f7cf19c82e5f4b39e61a63b053d Mon Sep 17 00:00:00 2001 -From: Emil Renner Berthing -Date: Sun, 31 Jan 2021 00:47:29 +0100 -Subject: [PATCH] net: usb: r8152: use new tasklet API - -commit f3163f1cb87141c7a41a15a5d4c98b353f807b04 upstream. - -This converts the driver to use the new tasklet API introduced in -commit 12cc923f1ccc ("tasklet: Introduce new initialization API") - -Signed-off-by: Emil Renner Berthing -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 8 +++----- - 1 file changed, 3 insertions(+), 5 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -2395,11 +2395,9 @@ static void tx_bottom(struct r8152 *tp) - } while (res == 0); - } - --static void bottom_half(unsigned long data) -+static void bottom_half(struct tasklet_struct *t) - { -- struct r8152 *tp; -- -- tp = (struct r8152 *)data; -+ struct r8152 *tp = from_tasklet(tp, t, tx_tl); - - if (test_bit(RTL8152_UNPLUG, &tp->flags)) - return; -@@ -6697,7 +6695,7 @@ static int rtl8152_probe(struct usb_inte - mutex_init(&tp->control); - INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); - INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); -- tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp); -+ tasklet_setup(&tp->tx_tl, bottom_half); - tasklet_disable(&tp->tx_tl); - - netdev->netdev_ops = &rtl8152_netdev_ops; diff --git a/target/linux/generic/backport-5.10/784-v5.12-r8152-replace-several-functions-about-phy-patch-requ.patch b/target/linux/generic/backport-5.10/784-v5.12-r8152-replace-several-functions-about-phy-patch-requ.patch deleted file mode 100644 index 759a09ae09..0000000000 --- a/target/linux/generic/backport-5.10/784-v5.12-r8152-replace-several-functions-about-phy-patch-requ.patch +++ /dev/null @@ -1,198 +0,0 @@ -From 86b98abf4f8c691c260c5113d6a2d32f5377caca Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Wed, 3 Feb 2021 17:14:28 +0800 -Subject: [PATCH] r8152: replace several functions about phy patch - request - -commit a08c0d309d8c078d22717d815cf9853f6f2c07bd upstream. - -Replace r8153_patch_request() with rtl_phy_patch_request(). -Replace r8153_pre_ram_code() with rtl_pre_ram_code(). -Replace r8153_post_ram_code() with rtl_post_ram_code(). -Add rtl_patch_key_set(). - -The new functions have an additional parameter. It is used to wait -the patch request command finished. When the PHY is resumed from -the state of power cut, the PHY is at a safe mode and the -OCP_PHY_PATCH_STAT wouldn't be updated. For this situation, it is -safe to set patch request command without waiting OCP_PHY_PATCH_STAT. - -Signed-off-by: Hayes Wang -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 84 ++++++++++++++++++++++++----------------- - 1 file changed, 50 insertions(+), 34 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -3445,59 +3445,76 @@ static void rtl_clear_bp(struct r8152 *t - ocp_write_word(tp, type, PLA_BP_BA, 0); - } - --static int r8153_patch_request(struct r8152 *tp, bool request) -+static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait) - { -- u16 data; -+ u16 data, check; - int i; - - data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); -- if (request) -+ if (request) { - data |= PATCH_REQUEST; -- else -+ check = 0; -+ } else { - data &= ~PATCH_REQUEST; -+ check = PATCH_READY; -+ } - ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); - -- for (i = 0; request && i < 5000; i++) { -+ for (i = 0; wait && i < 5000; i++) { -+ u32 ocp_data; -+ - usleep_range(1000, 2000); -- if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) -+ ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT); -+ if ((ocp_data & PATCH_READY) ^ check) - break; - } - -- if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { -- netif_err(tp, drv, tp->netdev, "patch request fail\n"); -- r8153_patch_request(tp, false); -+ if (request && wait && -+ !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { -+ dev_err(&tp->intf->dev, "PHY patch request fail\n"); -+ rtl_phy_patch_request(tp, false, false); - return -ETIME; - } else { - return 0; - } - } - --static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key) -+static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key) - { -- if (r8153_patch_request(tp, true)) { -- dev_err(&tp->intf->dev, "patch request fail\n"); -- return -ETIME; -- } -+ if (patch_key && key_addr) { -+ sram_write(tp, key_addr, patch_key); -+ sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK); -+ } else if (key_addr) { -+ u16 data; - -- sram_write(tp, key_addr, patch_key); -- sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK); -+ sram_write(tp, 0x0000, 0x0000); - -- return 0; -+ data = ocp_reg_read(tp, OCP_PHY_LOCK); -+ data &= ~PATCH_LOCK; -+ ocp_reg_write(tp, OCP_PHY_LOCK, data); -+ -+ sram_write(tp, key_addr, 0x0000); -+ } else { -+ WARN_ON_ONCE(1); -+ } - } - --static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr) -+static int -+rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait) - { -- u16 data; -+ if (rtl_phy_patch_request(tp, true, wait)) -+ return -ETIME; - -- sram_write(tp, 0x0000, 0x0000); -+ rtl_patch_key_set(tp, key_addr, patch_key); - -- data = ocp_reg_read(tp, OCP_PHY_LOCK); -- data &= ~PATCH_LOCK; -- ocp_reg_write(tp, OCP_PHY_LOCK, data); -+ return 0; -+} - -- sram_write(tp, key_addr, 0x0000); -+static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait) -+{ -+ rtl_patch_key_set(tp, key_addr, 0); - -- r8153_patch_request(tp, false); -+ rtl_phy_patch_request(tp, false, wait); - - ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base); - -@@ -3982,7 +3999,7 @@ static void rtl8152_fw_mac_apply(struct - dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info); - } - --static void rtl8152_apply_firmware(struct r8152 *tp) -+static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut) - { - struct rtl_fw *rtl_fw = &tp->rtl_fw; - const struct firmware *fw; -@@ -4013,12 +4030,11 @@ static void rtl8152_apply_firmware(struc - case RTL_FW_PHY_START: - key = (struct fw_phy_patch_key *)block; - key_addr = __le16_to_cpu(key->key_reg); -- r8153_pre_ram_code(tp, key_addr, -- __le16_to_cpu(key->key_data)); -+ rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut); - break; - case RTL_FW_PHY_STOP: - WARN_ON(!key_addr); -- r8153_post_ram_code(tp, key_addr); -+ rtl_post_ram_code(tp, key_addr, !power_cut); - break; - case RTL_FW_PHY_NC: - rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block); -@@ -4223,7 +4239,7 @@ static void rtl8152_disable(struct r8152 - - static void r8152b_hw_phy_cfg(struct r8152 *tp) - { -- rtl8152_apply_firmware(tp); -+ rtl8152_apply_firmware(tp, false); - rtl_eee_enable(tp, tp->eee_en); - r8152_aldps_en(tp, true); - r8152b_enable_fc(tp); -@@ -4505,7 +4521,7 @@ static void r8153_hw_phy_cfg(struct r815 - /* disable EEE before updating the PHY parameters */ - rtl_eee_enable(tp, false); - -- rtl8152_apply_firmware(tp); -+ rtl8152_apply_firmware(tp, false); - - if (tp->version == RTL_VER_03) { - data = ocp_reg_read(tp, OCP_EEE_CFG); -@@ -4579,7 +4595,7 @@ static void r8153b_hw_phy_cfg(struct r81 - /* disable EEE before updating the PHY parameters */ - rtl_eee_enable(tp, false); - -- rtl8152_apply_firmware(tp); -+ rtl8152_apply_firmware(tp, false); - - r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); - -@@ -4620,7 +4636,7 @@ static void r8153b_hw_phy_cfg(struct r81 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); - - /* Advnace EEE */ -- if (!r8153_patch_request(tp, true)) { -+ if (!rtl_phy_patch_request(tp, true, true)) { - data = ocp_reg_read(tp, OCP_POWER_CFG); - data |= EEE_CLKDIV_EN; - ocp_reg_write(tp, OCP_POWER_CFG, data); -@@ -4637,7 +4653,7 @@ static void r8153b_hw_phy_cfg(struct r81 - ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); - tp->ups_info._250m_ckdiv = true; - -- r8153_patch_request(tp, false); -+ rtl_phy_patch_request(tp, false, true); - } - - if (tp->eee_en) diff --git a/target/linux/generic/backport-5.10/785-v5.12-r8152-adjust-the-flow-of-power-cut-for-RTL8153B.patch b/target/linux/generic/backport-5.10/785-v5.12-r8152-adjust-the-flow-of-power-cut-for-RTL8153B.patch deleted file mode 100644 index 33969c7a54..0000000000 --- a/target/linux/generic/backport-5.10/785-v5.12-r8152-adjust-the-flow-of-power-cut-for-RTL8153B.patch +++ /dev/null @@ -1,134 +0,0 @@ -From 29a61d8564ad3439d03c7ec135016a4e70072af1 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Wed, 3 Feb 2021 17:14:29 +0800 -Subject: [PATCH] r8152: adjust the flow of power cut for RTL8153B - -commit 80fd850b31f09263ad175b2f640d5c5c6f76ed41 upstream. - -For runtime resuming, the RTL8153B may be resumed from the state -of power cut, when enabling the feature of UPS. Then, the PHY -would be reset, so it is necessary to be initailized again. - -Besides, the USB_U1U2_TIMER also has to be set again, so I move -it from r8153b_init() to r8153b_hw_phy_cfg(). - -Signed-off-by: Hayes Wang -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 68 ++++++++++++++++++++++++----------------- - 1 file changed, 40 insertions(+), 28 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -1371,6 +1371,10 @@ void write_mii_word(struct net_device *n - static int - r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); - -+static int -+rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, -+ u32 advertising); -+ - static int rtl8152_set_mac_address(struct net_device *netdev, void *p) - { - struct r8152 *tp = netdev_priv(netdev); -@@ -3184,8 +3188,6 @@ static void r8153b_ups_en(struct r8152 * - ocp_data |= BIT(0); - ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); - } else { -- u16 data; -- - ocp_data &= ~(UPS_EN | USP_PREWAKE); - ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); - -@@ -3193,31 +3195,20 @@ static void r8153b_ups_en(struct r8152 * - ocp_data &= ~BIT(0); - ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); - -- ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); -- ocp_data &= ~PCUT_STATUS; -- ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); -+ if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { -+ int i; - -- data = r8153_phy_status(tp, 0); -+ for (i = 0; i < 500; i++) { -+ if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & -+ AUTOLOAD_DONE) -+ break; -+ msleep(20); -+ } - -- switch (data) { -- case PHY_STAT_PWRDN: -- case PHY_STAT_EXT_INIT: -- r8153b_green_en(tp, -- test_bit(GREEN_ETHERNET, &tp->flags)); -- -- data = r8152_mdio_read(tp, MII_BMCR); -- data &= ~BMCR_PDOWN; -- data |= BMCR_RESET; -- r8152_mdio_write(tp, MII_BMCR, data); -+ tp->rtl_ops.hw_phy_cfg(tp); - -- data = r8153_phy_status(tp, PHY_STAT_LAN_ON); -- fallthrough; -- -- default: -- if (data != PHY_STAT_LAN_ON) -- netif_warn(tp, link, tp->netdev, -- "PHY not ready"); -- break; -+ rtl8152_set_speed(tp, tp->autoneg, tp->speed, -+ tp->duplex, tp->advertising); - } - } - } -@@ -4589,13 +4580,37 @@ static void r8153b_hw_phy_cfg(struct r81 - u32 ocp_data; - u16 data; - -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); -+ if (ocp_data & PCUT_STATUS) { -+ ocp_data &= ~PCUT_STATUS; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); -+ } -+ - /* disable ALDPS before updating the PHY parameters */ - r8153_aldps_en(tp, false); - - /* disable EEE before updating the PHY parameters */ - rtl_eee_enable(tp, false); - -- rtl8152_apply_firmware(tp, false); -+ /* U1/U2/L1 idle timer. 500 us */ -+ ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); -+ -+ data = r8153_phy_status(tp, 0); -+ -+ switch (data) { -+ case PHY_STAT_PWRDN: -+ case PHY_STAT_EXT_INIT: -+ rtl8152_apply_firmware(tp, true); -+ -+ data = r8152_mdio_read(tp, MII_BMCR); -+ data &= ~BMCR_PDOWN; -+ r8152_mdio_write(tp, MII_BMCR, data); -+ break; -+ case PHY_STAT_LAN_ON: -+ default: -+ rtl8152_apply_firmware(tp, false); -+ break; -+ } - - r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); - -@@ -5524,9 +5539,6 @@ static void r8153b_init(struct r8152 *tp - /* MSC timer = 0xfff * 8ms = 32760 ms */ - ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); - -- /* U1/U2/L1 idle timer. 500 us */ -- ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); -- - r8153b_power_cut_en(tp, false); - r8153b_ups_en(tp, false); - r8153_queue_wake(tp, false); diff --git a/target/linux/generic/backport-5.10/786-v5.12-r8152-enable-U1-U2-for-USB_SPEED_SUPER.patch b/target/linux/generic/backport-5.10/786-v5.12-r8152-enable-U1-U2-for-USB_SPEED_SUPER.patch deleted file mode 100644 index 6815fabe10..0000000000 --- a/target/linux/generic/backport-5.10/786-v5.12-r8152-enable-U1-U2-for-USB_SPEED_SUPER.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 69b4339c0b9f3edc6a8f681f05efaaf4add1bb0e Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 19 Feb 2021 17:04:40 +0800 -Subject: [PATCH] r8152: enable U1/U2 for USB_SPEED_SUPER - -commit 7a0ae61acde2cebd69665837170405eced86a6c7 upstream. - -U1/U2 shoued be enabled for USB 3.0 or later. The USB 2.0 doesn't -support it. - -Signed-off-by: Hayes Wang -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -3337,7 +3337,7 @@ static void rtl8153b_runtime_enable(stru - r8153b_ups_en(tp, false); - r8153_queue_wake(tp, false); - rtl_runtime_suspend_enable(tp, false); -- if (tp->udev->speed != USB_SPEED_HIGH) -+ if (tp->udev->speed >= USB_SPEED_SUPER) - r8153b_u1u2en(tp, true); - } - } -@@ -5030,7 +5030,7 @@ static void rtl8153b_up(struct r8152 *tp - - r8153_aldps_en(tp, true); - -- if (tp->udev->speed != USB_SPEED_HIGH) -+ if (tp->udev->speed >= USB_SPEED_SUPER) - r8153b_u1u2en(tp, true); - } - -@@ -5552,8 +5552,9 @@ static void r8153b_init(struct r8152 *tp - ocp_data |= POLL_LINK_CHG; - ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); - -- if (tp->udev->speed != USB_SPEED_HIGH) -+ if (tp->udev->speed >= USB_SPEED_SUPER) - r8153b_u1u2en(tp, true); -+ - usb_enable_lpm(tp->udev); - - /* MAC clock speed down */ diff --git a/target/linux/generic/backport-5.10/787-v5.12-r8152-check-if-the-pointer-of-the-function-exists.patch b/target/linux/generic/backport-5.10/787-v5.12-r8152-check-if-the-pointer-of-the-function-exists.patch deleted file mode 100644 index f13626faf0..0000000000 --- a/target/linux/generic/backport-5.10/787-v5.12-r8152-check-if-the-pointer-of-the-function-exists.patch +++ /dev/null @@ -1,51 +0,0 @@ -From e78b75f5be204a0a235da995d01c778dc282bb42 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 19 Feb 2021 17:04:41 +0800 -Subject: [PATCH] r8152: check if the pointer of the function exists - -commit c79515e47935c747282c6ed2ee5b2ef039756eeb upstream. - -Return error code if autosuspend_en, eee_get, or eee_set don't exist. - -Signed-off-by: Hayes Wang -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -5737,6 +5737,9 @@ static int rtl8152_runtime_suspend(struc - struct net_device *netdev = tp->netdev; - int ret = 0; - -+ if (!tp->rtl_ops.autosuspend_en) -+ return -EBUSY; -+ - set_bit(SELECTIVE_SUSPEND, &tp->flags); - smp_mb__after_atomic(); - -@@ -6136,6 +6139,11 @@ rtl_ethtool_get_eee(struct net_device *n - struct r8152 *tp = netdev_priv(net); - int ret; - -+ if (!tp->rtl_ops.eee_get) { -+ ret = -EOPNOTSUPP; -+ goto out; -+ } -+ - ret = usb_autopm_get_interface(tp->intf); - if (ret < 0) - goto out; -@@ -6158,6 +6166,11 @@ rtl_ethtool_set_eee(struct net_device *n - struct r8152 *tp = netdev_priv(net); - int ret; - -+ if (!tp->rtl_ops.eee_set) { -+ ret = -EOPNOTSUPP; -+ goto out; -+ } -+ - ret = usb_autopm_get_interface(tp->intf); - if (ret < 0) - goto out; diff --git a/target/linux/generic/backport-5.10/788-v5.12-r8152-replace-netif_err-with-dev_err.patch b/target/linux/generic/backport-5.10/788-v5.12-r8152-replace-netif_err-with-dev_err.patch deleted file mode 100644 index 24c606b5f5..0000000000 --- a/target/linux/generic/backport-5.10/788-v5.12-r8152-replace-netif_err-with-dev_err.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 38e44c7926512cff0b2809dc329de2a8e769e523 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 19 Feb 2021 17:04:42 +0800 -Subject: [PATCH] r8152: replace netif_err with dev_err - -commit 156c3207611262266f0eea589ac3f00c5657320e upstream. - -Some messages are before calling register_netdev(), so replace -netif_err() with dev_err(). - -Signed-off-by: Hayes Wang -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -6573,7 +6573,7 @@ static int rtl_ops_init(struct r8152 *tp - - default: - ret = -ENODEV; -- netif_err(tp, probe, tp->netdev, "Unknown Device\n"); -+ dev_err(&tp->intf->dev, "Unknown Device\n"); - break; - } - -@@ -6830,7 +6830,7 @@ static int rtl8152_probe(struct usb_inte - - ret = register_netdev(netdev); - if (ret != 0) { -- netif_err(tp, probe, netdev, "couldn't register the device\n"); -+ dev_err(&intf->dev, "couldn't register the device\n"); - goto out1; - } - diff --git a/target/linux/generic/backport-5.10/789-v5.12-r8152-spilt-rtl_set_eee_plus-and-r8153b_green_en.patch b/target/linux/generic/backport-5.10/789-v5.12-r8152-spilt-rtl_set_eee_plus-and-r8153b_green_en.patch deleted file mode 100644 index c5e7ff9624..0000000000 --- a/target/linux/generic/backport-5.10/789-v5.12-r8152-spilt-rtl_set_eee_plus-and-r8153b_green_en.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 260814de2d6cb958767785ffcb2e76915d1be32b Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 19 Feb 2021 17:04:43 +0800 -Subject: [PATCH] r8152: spilt rtl_set_eee_plus and r8153b_green_en - -commit 40fa7568ac230446d888b7ad402cff9e20fe3ad5 upstream. - -Add rtl_eee_plus_en() and rtl_green_en(). - -Signed-off-by: Hayes Wang -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 43 ++++++++++++++++++++++++++--------------- - 1 file changed, 27 insertions(+), 16 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -2634,21 +2634,24 @@ static inline u8 rtl8152_get_speed(struc - return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); - } - --static void rtl_set_eee_plus(struct r8152 *tp) -+static void rtl_eee_plus_en(struct r8152 *tp, bool enable) - { - u32 ocp_data; -- u8 speed; - -- speed = rtl8152_get_speed(tp); -- if (speed & _10bps) { -- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); -+ if (enable) - ocp_data |= EEEP_CR_EEEP_TX; -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); -- } else { -- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); -+ else - ocp_data &= ~EEEP_CR_EEEP_TX; -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); -- } -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); -+} -+ -+static void rtl_set_eee_plus(struct r8152 *tp) -+{ -+ if (rtl8152_get_speed(tp) & _10bps) -+ rtl_eee_plus_en(tp, true); -+ else -+ rtl_eee_plus_en(tp, false); - } - - static void rxdy_gated_en(struct r8152 *tp, bool enable) -@@ -3129,10 +3132,22 @@ static void r8153b_ups_flags(struct r815 - ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); - } - --static void r8153b_green_en(struct r8152 *tp, bool enable) -+static void rtl_green_en(struct r8152 *tp, bool enable) - { - u16 data; - -+ data = sram_read(tp, SRAM_GREEN_CFG); -+ if (enable) -+ data |= GREEN_ETH_EN; -+ else -+ data &= ~GREEN_ETH_EN; -+ sram_write(tp, SRAM_GREEN_CFG, data); -+ -+ tp->ups_info.green = enable; -+} -+ -+static void r8153b_green_en(struct r8152 *tp, bool enable) -+{ - if (enable) { - sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ - sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ -@@ -3143,11 +3158,7 @@ static void r8153b_green_en(struct r8152 - sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ - } - -- data = sram_read(tp, SRAM_GREEN_CFG); -- data |= GREEN_ETH_EN; -- sram_write(tp, SRAM_GREEN_CFG, data); -- -- tp->ups_info.green = enable; -+ rtl_green_en(tp, true); - } - - static u16 r8153_phy_status(struct r8152 *tp, u16 desired) diff --git a/target/linux/generic/backport-5.10/790-v5.13-r8152-set-inter-fram-gap-time-depending-on-speed.patch b/target/linux/generic/backport-5.10/790-v5.13-r8152-set-inter-fram-gap-time-depending-on-speed.patch deleted file mode 100644 index 9ed92328c3..0000000000 --- a/target/linux/generic/backport-5.10/790-v5.13-r8152-set-inter-fram-gap-time-depending-on-speed.patch +++ /dev/null @@ -1,75 +0,0 @@ -From f1bbbb260a8016373adf239c716d2da90e6ced0b Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 16 Apr 2021 16:04:32 +0800 -Subject: [PATCH] r8152: set inter fram gap time depending on speed - -commit 5133bcc7481528e36fff0a3b056601efb704fb32 upstream. - -Set the maximum inter frame gap time (144ns) for speed 10M/half and -100M/half. It improves the performance for those speeds. And, there -is no effect for the other speeds. - -For 10M/half and 100M/half, the fast inter frame gap time let the -device couldn't use the feature of the aggregation effectively, -because the transfer would be completed fastly. Therefore, use the -maximum value to improve the effect of the aggregation. However, you -may not feel the improvement for fast CPUs, because they compensate -for the effect of the aggregation. - -Signed-off-by: Hayes Wang -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -249,6 +249,9 @@ - - /* PLA_TCR1 */ - #define VERSION_MASK 0x7cf0 -+#define IFG_MASK (BIT(3) | BIT(9) | BIT(8)) -+#define IFG_144NS BIT(9) -+#define IFG_96NS (BIT(9) | BIT(8)) - - /* PLA_MTPS */ - #define MTPS_JUMBO (12 * 1024 / 64) -@@ -2749,6 +2752,29 @@ static int rtl_stop_rx(struct r8152 *tp) - return 0; - } - -+static void rtl_set_ifg(struct r8152 *tp, u16 speed) -+{ -+ u32 ocp_data; -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); -+ ocp_data &= ~IFG_MASK; -+ if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) { -+ ocp_data |= IFG_144NS; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); -+ ocp_data &= ~TX10MIDLE_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); -+ } else { -+ ocp_data |= IFG_96NS; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); -+ ocp_data |= TX10MIDLE_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); -+ } -+} -+ - static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) - { - ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, -@@ -2852,6 +2878,8 @@ static int rtl8153_enable(struct r8152 * - r8153_set_rx_early_timeout(tp); - r8153_set_rx_early_size(tp); - -+ rtl_set_ifg(tp, rtl8152_get_speed(tp)); -+ - if (tp->version == RTL_VER_09) { - u32 ocp_data; - diff --git a/target/linux/generic/backport-5.10/791-v5.13-r8152-adjust-rtl8152_check_firmware-function.patch b/target/linux/generic/backport-5.10/791-v5.13-r8152-adjust-rtl8152_check_firmware-function.patch deleted file mode 100644 index c61c4bb98a..0000000000 --- a/target/linux/generic/backport-5.10/791-v5.13-r8152-adjust-rtl8152_check_firmware-function.patch +++ /dev/null @@ -1,152 +0,0 @@ -From f10c9edf47d3fa240d965e151a48c670f5035b73 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 16 Apr 2021 16:04:33 +0800 -Subject: [PATCH] r8152: adjust rtl8152_check_firmware function - -commit a8a7be178e81a3d4b6972cbeb0ccd091ca2f9f89 upstream. - -Use bits operations to record and check the firmware. - -Signed-off-by: Hayes Wang -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 51 +++++++++++++++++++++++------------------ - 1 file changed, 29 insertions(+), 22 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -874,6 +874,14 @@ struct fw_header { - struct fw_block blocks[]; - } __packed; - -+enum rtl8152_fw_flags { -+ FW_FLAGS_USB = 0, -+ FW_FLAGS_PLA, -+ FW_FLAGS_START, -+ FW_FLAGS_STOP, -+ FW_FLAGS_NC, -+}; -+ - /** - * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB. - * The layout of the firmware block is: -@@ -3802,10 +3810,7 @@ static long rtl8152_check_firmware(struc - { - const struct firmware *fw = rtl_fw->fw; - struct fw_header *fw_hdr = (struct fw_header *)fw->data; -- struct fw_mac *pla = NULL, *usb = NULL; -- struct fw_phy_patch_key *start = NULL; -- struct fw_phy_nc *phy_nc = NULL; -- struct fw_block *stop = NULL; -+ unsigned long fw_flags = 0; - long ret = -EFAULT; - int i; - -@@ -3834,50 +3839,52 @@ static long rtl8152_check_firmware(struc - goto fail; - goto fw_end; - case RTL_FW_PLA: -- if (pla) { -+ if (test_bit(FW_FLAGS_PLA, &fw_flags)) { - dev_err(&tp->intf->dev, - "multiple PLA firmware encountered"); - goto fail; - } - -- pla = (struct fw_mac *)block; -- if (!rtl8152_is_fw_mac_ok(tp, pla)) { -+ if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { - dev_err(&tp->intf->dev, - "check PLA firmware failed\n"); - goto fail; - } -+ __set_bit(FW_FLAGS_PLA, &fw_flags); - break; - case RTL_FW_USB: -- if (usb) { -+ if (test_bit(FW_FLAGS_USB, &fw_flags)) { - dev_err(&tp->intf->dev, - "multiple USB firmware encountered"); - goto fail; - } - -- usb = (struct fw_mac *)block; -- if (!rtl8152_is_fw_mac_ok(tp, usb)) { -+ if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { - dev_err(&tp->intf->dev, - "check USB firmware failed\n"); - goto fail; - } -+ __set_bit(FW_FLAGS_USB, &fw_flags); - break; - case RTL_FW_PHY_START: -- if (start || phy_nc || stop) { -+ if (test_bit(FW_FLAGS_START, &fw_flags) || -+ test_bit(FW_FLAGS_NC, &fw_flags) || -+ test_bit(FW_FLAGS_STOP, &fw_flags)) { - dev_err(&tp->intf->dev, - "check PHY_START fail\n"); - goto fail; - } - -- if (__le32_to_cpu(block->length) != sizeof(*start)) { -+ if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) { - dev_err(&tp->intf->dev, - "Invalid length for PHY_START\n"); - goto fail; - } -- -- start = (struct fw_phy_patch_key *)block; -+ __set_bit(FW_FLAGS_START, &fw_flags); - break; - case RTL_FW_PHY_STOP: -- if (stop || !start) { -+ if (test_bit(FW_FLAGS_STOP, &fw_flags) || -+ !test_bit(FW_FLAGS_START, &fw_flags)) { - dev_err(&tp->intf->dev, - "Check PHY_STOP fail\n"); - goto fail; -@@ -3888,28 +3895,28 @@ static long rtl8152_check_firmware(struc - "Invalid length for PHY_STOP\n"); - goto fail; - } -- -- stop = block; -+ __set_bit(FW_FLAGS_STOP, &fw_flags); - break; - case RTL_FW_PHY_NC: -- if (!start || stop) { -+ if (!test_bit(FW_FLAGS_START, &fw_flags) || -+ test_bit(FW_FLAGS_STOP, &fw_flags)) { - dev_err(&tp->intf->dev, - "check PHY_NC fail\n"); - goto fail; - } - -- if (phy_nc) { -+ if (test_bit(FW_FLAGS_NC, &fw_flags)) { - dev_err(&tp->intf->dev, - "multiple PHY NC encountered\n"); - goto fail; - } - -- phy_nc = (struct fw_phy_nc *)block; -- if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) { -+ if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) { - dev_err(&tp->intf->dev, - "check PHY NC firmware failed\n"); - goto fail; - } -+ __set_bit(FW_FLAGS_NC, &fw_flags); - - break; - default: -@@ -3923,7 +3930,7 @@ static long rtl8152_check_firmware(struc - } - - fw_end: -- if ((phy_nc || start) && !stop) { -+ if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) { - dev_err(&tp->intf->dev, "without PHY_STOP\n"); - goto fail; - } diff --git a/target/linux/generic/backport-5.10/792-v5.13-r8152-add-help-function-to-change-mtu.patch b/target/linux/generic/backport-5.10/792-v5.13-r8152-add-help-function-to-change-mtu.patch deleted file mode 100644 index cd7a514b71..0000000000 --- a/target/linux/generic/backport-5.10/792-v5.13-r8152-add-help-function-to-change-mtu.patch +++ /dev/null @@ -1,157 +0,0 @@ -From f010a7d51cbb42bdb956f0a28b8868b15d7a3816 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 16 Apr 2021 16:04:34 +0800 -Subject: [PATCH] r8152: add help function to change mtu - -commit 67ce1a806f164e59a074fea8809725d3411eaa20 upstream. - -The different chips may have different requests when changing mtu. -Therefore, add a new help function of rtl_ops to change mtu. Besides, -reset the tx/rx after changing mtu. - -Additionally, add mtu_to_size() and size_to_mtu() macros to simplify -the code. - -Signed-off-by: Hayes Wang -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 53 ++++++++++++++++++++++++----------------- - 1 file changed, 31 insertions(+), 22 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -657,15 +657,13 @@ enum rtl_register_content { - - #define INTR_LINK 0x0004 - --#define RTL8153_MAX_PACKET 9216 /* 9K */ --#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ -- ETH_FCS_LEN) - #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) - #define RTL8153_RMS RTL8153_MAX_PACKET - #define RTL8152_TX_TIMEOUT (5 * HZ) - #define RTL8152_NAPI_WEIGHT 64 --#define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ -- sizeof(struct rx_desc) + RX_ALIGN) -+#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) -+#define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN) -+#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) - - /* rtl8152 flags */ - enum rtl8152_flags { -@@ -795,6 +793,7 @@ struct r8152 { - bool (*in_nway)(struct r8152 *tp); - void (*hw_phy_cfg)(struct r8152 *tp); - void (*autosuspend_en)(struct r8152 *tp, bool enable); -+ void (*change_mtu)(struct r8152 *tp); - } rtl_ops; - - struct ups_info { -@@ -1021,8 +1020,7 @@ enum tx_csum_stat { - static const int multicast_filter_limit = 32; - static unsigned int agg_buf_sz = 16384; - --#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ -- VLAN_ETH_HLEN - ETH_FCS_LEN) -+#define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc)) - - static - int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) -@@ -2634,10 +2632,7 @@ static void rtl8152_nic_reset(struct r81 - - static void set_tx_qlen(struct r8152 *tp) - { -- struct net_device *netdev = tp->netdev; -- -- tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + -- sizeof(struct tx_desc)); -+ tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc)); - } - - static inline u8 rtl8152_get_speed(struct r8152 *tp) -@@ -4726,6 +4721,12 @@ static void r8153b_hw_phy_cfg(struct r81 - set_bit(PHY_RESET, &tp->flags); - } - -+static void rtl8153_change_mtu(struct r8152 *tp) -+{ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); -+} -+ - static void r8153_first_init(struct r8152 *tp) - { - u32 ocp_data; -@@ -4758,9 +4759,7 @@ static void r8153_first_init(struct r815 - - rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); - -- ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); -- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); -+ rtl8153_change_mtu(tp); - - ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); - ocp_data |= TCR0_AUTO_FIFO; -@@ -4795,8 +4794,7 @@ static void r8153_enter_oob(struct r8152 - - wait_oob_link_list_ready(tp); - -- ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); - - switch (tp->version) { - case RTL_VER_03: -@@ -6497,12 +6495,21 @@ static int rtl8152_change_mtu(struct net - dev->mtu = new_mtu; - - if (netif_running(dev)) { -- u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; -- -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); -+ if (tp->rtl_ops.change_mtu) -+ tp->rtl_ops.change_mtu(tp); - -- if (netif_carrier_ok(dev)) -- r8153_set_rx_early_size(tp); -+ if (netif_carrier_ok(dev)) { -+ netif_stop_queue(dev); -+ napi_disable(&tp->napi); -+ tasklet_disable(&tp->tx_tl); -+ tp->rtl_ops.disable(tp); -+ tp->rtl_ops.enable(tp); -+ rtl_start_rx(tp); -+ tasklet_enable(&tp->tx_tl); -+ napi_enable(&tp->napi); -+ rtl8152_set_rx_mode(dev); -+ netif_wake_queue(dev); -+ } - } - - mutex_unlock(&tp->control); -@@ -6591,6 +6598,7 @@ static int rtl_ops_init(struct r8152 *tp - ops->in_nway = rtl8153_in_nway; - ops->hw_phy_cfg = r8153_hw_phy_cfg; - ops->autosuspend_en = rtl8153_runtime_enable; -+ ops->change_mtu = rtl8153_change_mtu; - if (tp->udev->speed < USB_SPEED_SUPER) - tp->rx_buf_sz = 16 * 1024; - else -@@ -6612,6 +6620,7 @@ static int rtl_ops_init(struct r8152 *tp - ops->in_nway = rtl8153_in_nway; - ops->hw_phy_cfg = r8153b_hw_phy_cfg; - ops->autosuspend_en = rtl8153b_runtime_enable; -+ ops->change_mtu = rtl8153_change_mtu; - tp->rx_buf_sz = 32 * 1024; - tp->eee_en = true; - tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; -@@ -6832,7 +6841,7 @@ static int rtl8152_probe(struct usb_inte - netdev->max_mtu = ETH_DATA_LEN; - break; - default: -- netdev->max_mtu = RTL8153_MAX_MTU; -+ netdev->max_mtu = size_to_mtu(9 * 1024); - break; - } - diff --git a/target/linux/generic/backport-5.10/793-v5.13-r8152-support-new-chips.patch b/target/linux/generic/backport-5.10/793-v5.13-r8152-support-new-chips.patch deleted file mode 100644 index 1533229564..0000000000 --- a/target/linux/generic/backport-5.10/793-v5.13-r8152-support-new-chips.patch +++ /dev/null @@ -1,2886 +0,0 @@ -From e7439e7fd384f55f55837f7e4866e74d8dca3827 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 16 Apr 2021 16:04:35 +0800 -Subject: [PATCH] r8152: support new chips - -commit 195aae321c829dd1945900d75561e6aa79cce208 upstream. - -Support RTL8153C, RTL8153D, RTL8156A, and RTL8156B. The RTL8156A -and RTL8156B are the 2.5G ethernet. - -Signed-off-by: Hayes Wang -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 2634 +++++++++++++++++++++++++++++++++++---- - 1 file changed, 2359 insertions(+), 275 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -43,10 +43,14 @@ - - #define PLA_IDR 0xc000 - #define PLA_RCR 0xc010 -+#define PLA_RCR1 0xc012 - #define PLA_RMS 0xc016 - #define PLA_RXFIFO_CTRL0 0xc0a0 -+#define PLA_RXFIFO_FULL 0xc0a2 - #define PLA_RXFIFO_CTRL1 0xc0a4 -+#define PLA_RX_FIFO_FULL 0xc0a6 - #define PLA_RXFIFO_CTRL2 0xc0a8 -+#define PLA_RX_FIFO_EMPTY 0xc0aa - #define PLA_DMY_REG0 0xc0b0 - #define PLA_FMC 0xc0b4 - #define PLA_CFG_WOL 0xc0b6 -@@ -63,6 +67,8 @@ - #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */ - #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */ - #define PLA_EXTRA_STATUS 0xd398 -+#define PLA_GPHY_CTRL 0xd3ae -+#define PLA_POL_GPIO_CTRL 0xdc6a - #define PLA_EFUSE_DATA 0xdd00 - #define PLA_EFUSE_CMD 0xdd02 - #define PLA_LEDSEL 0xdd90 -@@ -72,6 +78,8 @@ - #define PLA_LWAKE_CTRL_REG 0xe007 - #define PLA_GPHY_INTR_IMR 0xe022 - #define PLA_EEE_CR 0xe040 -+#define PLA_EEE_TXTWSYS 0xe04c -+#define PLA_EEE_TXTWSYS_2P5G 0xe058 - #define PLA_EEEP_CR 0xe080 - #define PLA_MAC_PWR_CTRL 0xe0c0 - #define PLA_MAC_PWR_CTRL2 0xe0ca -@@ -82,6 +90,7 @@ - #define PLA_TCR1 0xe612 - #define PLA_MTPS 0xe615 - #define PLA_TXFIFO_CTRL 0xe618 -+#define PLA_TXFIFO_FULL 0xe61a - #define PLA_RSTTALLY 0xe800 - #define PLA_CR 0xe813 - #define PLA_CRWECR 0xe81c -@@ -98,6 +107,7 @@ - #define PLA_SFF_STS_7 0xe8de - #define PLA_PHYSTATUS 0xe908 - #define PLA_CONFIG6 0xe90a /* CONFIG6 */ -+#define PLA_USB_CFG 0xe952 - #define PLA_BP_BA 0xfc26 - #define PLA_BP_0 0xfc28 - #define PLA_BP_1 0xfc2a -@@ -112,6 +122,7 @@ - #define USB_USB2PHY 0xb41e - #define USB_SSPHYLINK1 0xb426 - #define USB_SSPHYLINK2 0xb428 -+#define USB_L1_CTRL 0xb45e - #define USB_U2P3_CTRL 0xb460 - #define USB_CSR_DUMMY1 0xb464 - #define USB_CSR_DUMMY2 0xb466 -@@ -122,7 +133,12 @@ - #define USB_FW_FIX_EN0 0xcfca - #define USB_FW_FIX_EN1 0xcfcc - #define USB_LPM_CONFIG 0xcfd8 -+#define USB_ECM_OPTION 0xcfee - #define USB_CSTMR 0xcfef /* RTL8153A */ -+#define USB_MISC_2 0xcfff -+#define USB_ECM_OP 0xd26b -+#define USB_GPHY_CTRL 0xd284 -+#define USB_SPEED_OPTION 0xd32a - #define USB_FW_CTRL 0xd334 /* RTL8153B */ - #define USB_FC_TIMER 0xd340 - #define USB_USB_CTRL 0xd406 -@@ -136,16 +152,20 @@ - #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ - #define USB_TX_DMA 0xd434 - #define USB_UPT_RXDMA_OWN 0xd437 -+#define USB_UPHY3_MDCMDIO 0xd480 - #define USB_TOLERANCE 0xd490 - #define USB_LPM_CTRL 0xd41a - #define USB_BMU_RESET 0xd4b0 -+#define USB_BMU_CONFIG 0xd4b4 - #define USB_U1U2_TIMER 0xd4da - #define USB_FW_TASK 0xd4e8 /* RTL8153B */ -+#define USB_RX_AGGR_NUM 0xd4ee - #define USB_UPS_CTRL 0xd800 - #define USB_POWER_CUT 0xd80a - #define USB_MISC_0 0xd81a - #define USB_MISC_1 0xd81f - #define USB_AFE_CTRL2 0xd824 -+#define USB_UPHY_XTAL 0xd826 - #define USB_UPS_CFG 0xd842 - #define USB_UPS_FLAGS 0xd848 - #define USB_WDT1_CTRL 0xe404 -@@ -188,6 +208,9 @@ - #define OCP_EEE_ABLE 0xa5c4 - #define OCP_EEE_ADV 0xa5d0 - #define OCP_EEE_LPABLE 0xa5d2 -+#define OCP_10GBT_CTRL 0xa5d4 -+#define OCP_10GBT_STAT 0xa5d6 -+#define OCP_EEE_ADV2 0xa6d4 - #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ - #define OCP_PHY_PATCH_STAT 0xb800 - #define OCP_PHY_PATCH_CMD 0xb820 -@@ -199,6 +222,7 @@ - /* SRAM Register */ - #define SRAM_GREEN_CFG 0x8011 - #define SRAM_LPF_CFG 0x8012 -+#define SRAM_GPHY_FW_VER 0x801e - #define SRAM_10M_AMP1 0x8080 - #define SRAM_10M_AMP2 0x8082 - #define SRAM_IMPEDANCE 0x8084 -@@ -210,11 +234,19 @@ - #define RCR_AM 0x00000004 - #define RCR_AB 0x00000008 - #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) -+#define SLOT_EN BIT(11) -+ -+/* PLA_RCR1 */ -+#define OUTER_VLAN BIT(7) -+#define INNER_VLAN BIT(6) - - /* PLA_RXFIFO_CTRL0 */ - #define RXFIFO_THR1_NORMAL 0x00080002 - #define RXFIFO_THR1_OOB 0x01800003 - -+/* PLA_RXFIFO_FULL */ -+#define RXFIFO_FULL_MASK 0xfff -+ - /* PLA_RXFIFO_CTRL1 */ - #define RXFIFO_THR2_FULL 0x00000060 - #define RXFIFO_THR2_HIGH 0x00000038 -@@ -285,6 +317,7 @@ - #define MCU_BORW_EN 0x4000 - - /* PLA_CPCR */ -+#define FLOW_CTRL_EN BIT(0) - #define CPCR_RX_VLAN 0x0040 - - /* PLA_CFG_WOL */ -@@ -310,6 +343,10 @@ - /* PLA_CONFIG6 */ - #define LANWAKE_CLR_EN BIT(0) - -+/* PLA_USB_CFG */ -+#define EN_XG_LIP BIT(1) -+#define EN_G_LIP BIT(2) -+ - /* PLA_CONFIG5 */ - #define BWF_EN 0x0040 - #define MWF_EN 0x0020 -@@ -333,6 +370,7 @@ - /* PLA_MAC_PWR_CTRL2 */ - #define EEE_SPDWN_RATIO 0x8007 - #define MAC_CLK_SPDWN_EN BIT(15) -+#define EEE_SPDWN_RATIO_MASK 0xff - - /* PLA_MAC_PWR_CTRL3 */ - #define PLA_MCU_SPDWN_EN BIT(14) -@@ -345,6 +383,7 @@ - #define PWRSAVE_SPDWN_EN 0x1000 - #define RXDV_SPDWN_EN 0x0800 - #define TX10MIDLE_EN 0x0100 -+#define IDLE_SPDWN_EN BIT(6) - #define TP100_SPDWN_EN 0x0020 - #define TP500_SPDWN_EN 0x0010 - #define TP1000_SPDWN_EN 0x0008 -@@ -385,6 +424,13 @@ - #define LINK_CHANGE_FLAG BIT(8) - #define POLL_LINK_CHG BIT(0) - -+/* PLA_GPHY_CTRL */ -+#define GPHY_FLASH BIT(1) -+ -+/* PLA_POL_GPIO_CTRL */ -+#define DACK_DET_EN BIT(15) -+#define POL_GPHY_PATCH BIT(4) -+ - /* USB_USB2PHY */ - #define USB2PHY_SUSPEND 0x0001 - #define USB2PHY_L1 0x0002 -@@ -433,6 +479,9 @@ - #define BMU_RESET_EP_IN 0x01 - #define BMU_RESET_EP_OUT 0x02 - -+/* USB_BMU_CONFIG */ -+#define ACT_ODMA BIT(1) -+ - /* USB_UPT_RXDMA_OWN */ - #define OWN_UPDATE BIT(0) - #define OWN_CLEAR BIT(1) -@@ -440,27 +489,52 @@ - /* USB_FW_TASK */ - #define FC_PATCH_TASK BIT(1) - -+/* USB_RX_AGGR_NUM */ -+#define RX_AGGR_NUM_MASK 0x1ff -+ - /* USB_UPS_CTRL */ - #define POWER_CUT 0x0100 - - /* USB_PM_CTRL_STATUS */ - #define RESUME_INDICATE 0x0001 - -+/* USB_ECM_OPTION */ -+#define BYPASS_MAC_RESET BIT(5) -+ - /* USB_CSTMR */ - #define FORCE_SUPER BIT(0) - -+/* USB_MISC_2 */ -+#define UPS_FORCE_PWR_DOWN BIT(0) -+ -+/* USB_ECM_OP */ -+#define EN_ALL_SPEED BIT(0) -+ -+/* USB_GPHY_CTRL */ -+#define GPHY_PATCH_DONE BIT(2) -+#define BYPASS_FLASH BIT(5) -+#define BACKUP_RESTRORE BIT(6) -+ -+/* USB_SPEED_OPTION */ -+#define RG_PWRDN_EN BIT(8) -+#define ALL_SPEED_OFF BIT(9) -+ - /* USB_FW_CTRL */ - #define FLOW_CTRL_PATCH_OPT BIT(1) -+#define AUTO_SPEEDUP BIT(3) -+#define FLOW_CTRL_PATCH_2 BIT(8) - - /* USB_FC_TIMER */ - #define CTRL_TIMER_EN BIT(15) - - /* USB_USB_CTRL */ -+#define CDC_ECM_EN BIT(3) - #define RX_AGG_DISABLE 0x0010 - #define RX_ZERO_EN 0x0080 - - /* USB_U2P3_CTRL */ - #define U2P3_ENABLE 0x0001 -+#define RX_DETECT8 BIT(3) - - /* USB_POWER_CUT */ - #define PWR_EN 0x0001 -@@ -496,8 +570,12 @@ - #define SEN_VAL_NORMAL 0xa000 - #define SEL_RXIDLE 0x0100 - -+/* USB_UPHY_XTAL */ -+#define OOBS_POLLING BIT(8) -+ - /* USB_UPS_CFG */ - #define SAW_CNT_1MS_MASK 0x0fff -+#define MID_REVERSE BIT(5) /* RTL8156A */ - - /* USB_UPS_FLAGS */ - #define UPS_FLAGS_R_TUNE BIT(0) -@@ -505,6 +583,7 @@ - #define UPS_FLAGS_250M_CKDIV BIT(2) - #define UPS_FLAGS_EN_ALDPS BIT(3) - #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) -+#define UPS_FLAGS_SPEED_MASK (0xf << 16) - #define ups_flags_speed(x) ((x) << 16) - #define UPS_FLAGS_EN_EEE BIT(20) - #define UPS_FLAGS_EN_500M_EEE BIT(21) -@@ -525,6 +604,8 @@ enum spd_duplex { - FORCE_10M_FULL, - FORCE_100M_HALF, - FORCE_100M_FULL, -+ FORCE_1000M_FULL, -+ NWAY_2500M_FULL, - }; - - /* OCP_ALDPS_CONFIG */ -@@ -589,6 +670,9 @@ enum spd_duplex { - #define EN_10M_CLKDIV BIT(11) - #define EN_10M_BGOFF 0x0080 - -+/* OCP_10GBT_CTRL */ -+#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */ -+ - /* OCP_PHY_STATE */ - #define TXDIS_STATE 0x01 - #define ABD_STATE 0x02 -@@ -608,7 +692,8 @@ enum spd_duplex { - #define EN_EMI_L 0x0040 - - /* OCP_SYSCLK_CFG */ --#define clk_div_expo(x) (min(x, 5) << 8) -+#define sysclk_div_expo(x) (min(x, 5) << 8) -+#define clk_div_expo(x) (min(x, 5) << 4) - - /* SRAM_GREEN_CFG */ - #define GREEN_ETH_EN BIT(15) -@@ -639,6 +724,11 @@ enum spd_duplex { - #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */ - - enum rtl_register_content { -+ _2500bps = BIT(10), -+ _1250bps = BIT(9), -+ _500bps = BIT(8), -+ _tx_flow = BIT(6), -+ _rx_flow = BIT(5), - _1000bps = 0x10, - _100bps = 0x08, - _10bps = 0x04, -@@ -646,6 +736,9 @@ enum rtl_register_content { - FULL_DUP = 0x01, - }; - -+#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS)) -+#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow)) -+ - #define RTL8152_MAX_TX 4 - #define RTL8152_MAX_RX 10 - #define INTBUFSIZE 2 -@@ -660,7 +753,6 @@ enum rtl_register_content { - #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) - #define RTL8153_RMS RTL8153_MAX_PACKET - #define RTL8152_TX_TIMEOUT (5 * HZ) --#define RTL8152_NAPI_WEIGHT 64 - #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) - #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN) - #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) -@@ -797,6 +889,7 @@ struct r8152 { - } rtl_ops; - - struct ups_info { -+ u32 r_tune:1; - u32 _10m_ckdiv:1; - u32 _250m_ckdiv:1; - u32 aldps:1; -@@ -838,7 +931,9 @@ struct r8152 { - u32 rx_buf_sz; - u32 rx_copybreak; - u32 rx_pending; -+ u32 fc_pause_on, fc_pause_off; - -+ u32 support_2500full:1; - u16 ocp_base; - u16 speed; - u16 eee_adv; -@@ -998,6 +1093,15 @@ enum rtl_version { - RTL_VER_07, - RTL_VER_08, - RTL_VER_09, -+ -+ RTL_TEST_01, -+ RTL_VER_10, -+ RTL_VER_11, -+ RTL_VER_12, -+ RTL_VER_13, -+ RTL_VER_14, -+ RTL_VER_15, -+ - RTL_VER_MAX - }; - -@@ -1013,6 +1117,7 @@ enum tx_csum_stat { - #define RTL_ADVERTISED_100_FULL BIT(3) - #define RTL_ADVERTISED_1000_HALF BIT(4) - #define RTL_ADVERTISED_1000_FULL BIT(5) -+#define RTL_ADVERTISED_2500_FULL BIT(6) - - /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). - * The RTL chips use a 64 element hash table based on the Ethernet CRC. -@@ -2608,7 +2713,7 @@ static netdev_tx_t rtl8152_start_xmit(st - - static void r8152b_reset_packet_filter(struct r8152 *tp) - { -- u32 ocp_data; -+ u32 ocp_data; - - ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); - ocp_data &= ~FMC_FCR_MCU_EN; -@@ -2619,14 +2724,47 @@ static void r8152b_reset_packet_filter(s - - static void rtl8152_nic_reset(struct r8152 *tp) - { -- int i; -+ u32 ocp_data; -+ int i; - -- ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); -+ switch (tp->version) { -+ case RTL_TEST_01: -+ case RTL_VER_10: -+ case RTL_VER_11: -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); -+ ocp_data &= ~CR_TE; -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); -+ ocp_data &= ~BMU_RESET_EP_IN; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); -+ ocp_data |= CDC_ECM_EN; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); -+ ocp_data &= ~CR_RE; -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); -+ ocp_data |= BMU_RESET_EP_IN; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); -+ ocp_data &= ~CDC_ECM_EN; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); -+ break; - -- for (i = 0; i < 1000; i++) { -- if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) -- break; -- usleep_range(100, 400); -+ default: -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); -+ -+ for (i = 0; i < 1000; i++) { -+ if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) -+ break; -+ usleep_range(100, 400); -+ } -+ break; - } - } - -@@ -2635,9 +2773,9 @@ static void set_tx_qlen(struct r8152 *tp - tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc)); - } - --static inline u8 rtl8152_get_speed(struct r8152 *tp) -+static inline u16 rtl8152_get_speed(struct r8152 *tp) - { -- return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); -+ return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); - } - - static void rtl_eee_plus_en(struct r8152 *tp, bool enable) -@@ -2797,6 +2935,7 @@ static int rtl_enable(struct r8152 *tp) - switch (tp->version) { - case RTL_VER_08: - case RTL_VER_09: -+ case RTL_VER_14: - r8153b_rx_agg_chg_indicate(tp); - break; - default: -@@ -2834,6 +2973,7 @@ static void r8153_set_rx_early_timeout(s - - case RTL_VER_08: - case RTL_VER_09: -+ case RTL_VER_14: - /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout - * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. - */ -@@ -2843,6 +2983,18 @@ static void r8153_set_rx_early_timeout(s - ocp_data); - break; - -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_15: -+ ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, -+ 640 / 8); -+ ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, -+ ocp_data); -+ r8153b_rx_agg_chg_indicate(tp); -+ break; -+ - default: - break; - } -@@ -2862,8 +3014,19 @@ static void r8153_set_rx_early_size(stru - break; - case RTL_VER_08: - case RTL_VER_09: -+ case RTL_VER_14: -+ ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, -+ ocp_data / 8); -+ break; -+ case RTL_TEST_01: -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_15: - ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, - ocp_data / 8); -+ r8153b_rx_agg_chg_indicate(tp); - break; - default: - WARN_ON_ONCE(1); -@@ -2873,6 +3036,8 @@ static void r8153_set_rx_early_size(stru - - static int rtl8153_enable(struct r8152 *tp) - { -+ u32 ocp_data; -+ - if (test_bit(RTL8152_UNPLUG, &tp->flags)) - return -ENODEV; - -@@ -2883,15 +3048,18 @@ static int rtl8153_enable(struct r8152 * - - rtl_set_ifg(tp, rtl8152_get_speed(tp)); - -- if (tp->version == RTL_VER_09) { -- u32 ocp_data; -- -+ switch (tp->version) { -+ case RTL_VER_09: -+ case RTL_VER_14: - ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); - ocp_data &= ~FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); - usleep_range(1000, 2000); - ocp_data |= FC_PATCH_TASK; - ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); -+ break; -+ default: -+ break; - } - - return rtl_enable(tp); -@@ -2956,12 +3124,40 @@ static void rtl_rx_vlan_en(struct r8152 - { - u32 ocp_data; - -- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); -- if (enable) -- ocp_data |= CPCR_RX_VLAN; -- else -- ocp_data &= ~CPCR_RX_VLAN; -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); -+ switch (tp->version) { -+ case RTL_VER_01: -+ case RTL_VER_02: -+ case RTL_VER_03: -+ case RTL_VER_04: -+ case RTL_VER_05: -+ case RTL_VER_06: -+ case RTL_VER_07: -+ case RTL_VER_08: -+ case RTL_VER_09: -+ case RTL_VER_14: -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); -+ if (enable) -+ ocp_data |= CPCR_RX_VLAN; -+ else -+ ocp_data &= ~CPCR_RX_VLAN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); -+ break; -+ -+ case RTL_TEST_01: -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_15: -+ default: -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1); -+ if (enable) -+ ocp_data |= OUTER_VLAN | INNER_VLAN; -+ else -+ ocp_data &= ~(OUTER_VLAN | INNER_VLAN); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data); -+ break; -+ } - } - - static int rtl8152_set_features(struct net_device *dev, -@@ -3054,6 +3250,40 @@ static void __rtl_set_wol(struct r8152 * - device_set_wakeup_enable(&tp->udev->dev, false); - } - -+static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable) -+{ -+ u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); -+ -+ /* MAC clock speed down */ -+ if (enable) -+ ocp_data |= MAC_CLK_SPDWN_EN; -+ else -+ ocp_data &= ~MAC_CLK_SPDWN_EN; -+ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); -+} -+ -+static void r8156_mac_clk_spd(struct r8152 *tp, bool enable) -+{ -+ u32 ocp_data; -+ -+ /* MAC clock speed down */ -+ if (enable) { -+ /* aldps_spdwn_ratio, tp10_spdwn_ratio */ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, -+ 0x0403); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); -+ ocp_data &= ~EEE_SPDWN_RATIO_MASK; -+ ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); -+ } else { -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); -+ ocp_data &= ~MAC_CLK_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); -+ } -+} -+ - static void r8153_u1u2en(struct r8152 *tp, bool enable) - { - u8 u1u2[8]; -@@ -3113,6 +3343,9 @@ static void r8153b_ups_flags(struct r815 - if (tp->ups_info.eee_cmod_lv) - ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN; - -+ if (tp->ups_info.r_tune) -+ ups_flags |= UPS_FLAGS_R_TUNE; -+ - if (tp->ups_info._10m_ckdiv) - ups_flags |= UPS_FLAGS_EN_10M_CKDIV; - -@@ -3163,6 +3396,88 @@ static void r8153b_ups_flags(struct r815 - ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); - } - -+static void r8156_ups_flags(struct r8152 *tp) -+{ -+ u32 ups_flags = 0; -+ -+ if (tp->ups_info.green) -+ ups_flags |= UPS_FLAGS_EN_GREEN; -+ -+ if (tp->ups_info.aldps) -+ ups_flags |= UPS_FLAGS_EN_ALDPS; -+ -+ if (tp->ups_info.eee) -+ ups_flags |= UPS_FLAGS_EN_EEE; -+ -+ if (tp->ups_info.flow_control) -+ ups_flags |= UPS_FLAGS_EN_FLOW_CTR; -+ -+ if (tp->ups_info.eee_ckdiv) -+ ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; -+ -+ if (tp->ups_info._10m_ckdiv) -+ ups_flags |= UPS_FLAGS_EN_10M_CKDIV; -+ -+ if (tp->ups_info.eee_plloff_100) -+ ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; -+ -+ if (tp->ups_info.eee_plloff_giga) -+ ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; -+ -+ if (tp->ups_info._250m_ckdiv) -+ ups_flags |= UPS_FLAGS_250M_CKDIV; -+ -+ switch (tp->ups_info.speed_duplex) { -+ case FORCE_10M_HALF: -+ ups_flags |= ups_flags_speed(0); -+ break; -+ case FORCE_10M_FULL: -+ ups_flags |= ups_flags_speed(1); -+ break; -+ case FORCE_100M_HALF: -+ ups_flags |= ups_flags_speed(2); -+ break; -+ case FORCE_100M_FULL: -+ ups_flags |= ups_flags_speed(3); -+ break; -+ case NWAY_10M_HALF: -+ ups_flags |= ups_flags_speed(4); -+ break; -+ case NWAY_10M_FULL: -+ ups_flags |= ups_flags_speed(5); -+ break; -+ case NWAY_100M_HALF: -+ ups_flags |= ups_flags_speed(6); -+ break; -+ case NWAY_100M_FULL: -+ ups_flags |= ups_flags_speed(7); -+ break; -+ case NWAY_1000M_FULL: -+ ups_flags |= ups_flags_speed(8); -+ break; -+ case NWAY_2500M_FULL: -+ ups_flags |= ups_flags_speed(9); -+ break; -+ default: -+ break; -+ } -+ -+ switch (tp->ups_info.lite_mode) { -+ case 1: -+ ups_flags |= 0 << 5; -+ break; -+ case 2: -+ ups_flags |= 2 << 5; -+ break; -+ case 0: -+ default: -+ ups_flags |= 1 << 5; -+ break; -+ } -+ -+ ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); -+} -+ - static void rtl_green_en(struct r8152 *tp, bool enable) - { - u16 data; -@@ -3226,16 +3541,16 @@ static void r8153b_ups_en(struct r8152 * - ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; - ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); - -- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); -- ocp_data |= BIT(0); -- ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); -+ ocp_data |= UPS_FORCE_PWR_DOWN; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); - } else { - ocp_data &= ~(UPS_EN | USP_PREWAKE); - ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); - -- ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); -- ocp_data &= ~BIT(0); -- ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); -+ ocp_data &= ~UPS_FORCE_PWR_DOWN; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); - - if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { - int i; -@@ -3255,6 +3570,95 @@ static void r8153b_ups_en(struct r8152 * - } - } - -+static void r8153c_ups_en(struct r8152 *tp, bool enable) -+{ -+ u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); -+ -+ if (enable) { -+ r8153b_ups_flags(tp); -+ -+ ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); -+ ocp_data |= UPS_FORCE_PWR_DOWN; -+ ocp_data &= ~BIT(7); -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); -+ } else { -+ ocp_data &= ~(UPS_EN | USP_PREWAKE); -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); -+ ocp_data &= ~UPS_FORCE_PWR_DOWN; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); -+ -+ if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { -+ int i; -+ -+ for (i = 0; i < 500; i++) { -+ if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & -+ AUTOLOAD_DONE) -+ break; -+ msleep(20); -+ } -+ -+ tp->rtl_ops.hw_phy_cfg(tp); -+ -+ rtl8152_set_speed(tp, tp->autoneg, tp->speed, -+ tp->duplex, tp->advertising); -+ } -+ -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); -+ ocp_data |= BIT(8); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); -+ -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); -+ } -+} -+ -+static void r8156_ups_en(struct r8152 *tp, bool enable) -+{ -+ u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); -+ -+ if (enable) { -+ r8156_ups_flags(tp); -+ -+ ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); -+ ocp_data |= UPS_FORCE_PWR_DOWN; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); -+ -+ switch (tp->version) { -+ case RTL_VER_13: -+ case RTL_VER_15: -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL); -+ ocp_data &= ~OOBS_POLLING; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); -+ break; -+ default: -+ break; -+ } -+ } else { -+ ocp_data &= ~(UPS_EN | USP_PREWAKE); -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); -+ ocp_data &= ~UPS_FORCE_PWR_DOWN; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); -+ -+ if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { -+ tp->rtl_ops.hw_phy_cfg(tp); -+ -+ rtl8152_set_speed(tp, tp->autoneg, tp->speed, -+ tp->duplex, tp->advertising); -+ } -+ } -+} -+ - static void r8153_power_cut_en(struct r8152 *tp, bool enable) - { - u32 ocp_data; -@@ -3384,6 +3788,38 @@ static void rtl8153b_runtime_enable(stru - } - } - -+static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable) -+{ -+ if (enable) { -+ r8153_queue_wake(tp, true); -+ r8153b_u1u2en(tp, false); -+ r8153_u2p3en(tp, false); -+ rtl_runtime_suspend_enable(tp, true); -+ r8153c_ups_en(tp, true); -+ } else { -+ r8153c_ups_en(tp, false); -+ r8153_queue_wake(tp, false); -+ rtl_runtime_suspend_enable(tp, false); -+ r8153b_u1u2en(tp, true); -+ } -+} -+ -+static void rtl8156_runtime_enable(struct r8152 *tp, bool enable) -+{ -+ if (enable) { -+ r8153_queue_wake(tp, true); -+ r8153b_u1u2en(tp, false); -+ r8153_u2p3en(tp, false); -+ rtl_runtime_suspend_enable(tp, true); -+ } else { -+ r8153_queue_wake(tp, false); -+ rtl_runtime_suspend_enable(tp, false); -+ r8153_u2p3en(tp, true); -+ if (tp->udev->speed >= USB_SPEED_SUPER) -+ r8153b_u1u2en(tp, true); -+ } -+} -+ - static void r8153_teredo_off(struct r8152 *tp) - { - u32 ocp_data; -@@ -3404,14 +3840,19 @@ static void r8153_teredo_off(struct r815 - - case RTL_VER_08: - case RTL_VER_09: -+ case RTL_TEST_01: -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_14: -+ case RTL_VER_15: -+ default: - /* The bit 0 ~ 7 are relative with teredo settings. They are - * W1C (write 1 to clear), so set all 1 to disable it. - */ - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); - break; -- -- default: -- break; - } - - ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); -@@ -3446,6 +3887,12 @@ static void rtl_clear_bp(struct r8152 *t - break; - case RTL_VER_08: - case RTL_VER_09: -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_14: -+ case RTL_VER_15: - default: - if (type == MCU_TYPE_USB) { - ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0); -@@ -3655,6 +4102,11 @@ static bool rtl8152_is_fw_mac_ok(struct - case RTL_VER_06: - case RTL_VER_08: - case RTL_VER_09: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_14: -+ case RTL_VER_15: - fw_reg = 0xf800; - bp_ba_addr = PLA_BP_BA; - bp_en_addr = PLA_BP_EN; -@@ -3678,6 +4130,11 @@ static bool rtl8152_is_fw_mac_ok(struct - break; - case RTL_VER_08: - case RTL_VER_09: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_14: -+ case RTL_VER_15: - fw_reg = 0xe600; - bp_ba_addr = USB_BP_BA; - bp_en_addr = USB_BP2_EN; -@@ -4217,6 +4674,22 @@ static void r8153_eee_en(struct r8152 *t - tp->ups_info.eee = enable; - } - -+static void r8156_eee_en(struct r8152 *tp, bool enable) -+{ -+ u16 config; -+ -+ r8153_eee_en(tp, enable); -+ -+ config = ocp_reg_read(tp, OCP_EEE_ADV2); -+ -+ if (enable) -+ config |= MDIO_EEE_2_5GT; -+ else -+ config &= ~MDIO_EEE_2_5GT; -+ -+ ocp_reg_write(tp, OCP_EEE_ADV2, config); -+} -+ - static void rtl_eee_enable(struct r8152 *tp, bool enable) - { - switch (tp->version) { -@@ -4238,6 +4711,7 @@ static void rtl_eee_enable(struct r8152 - case RTL_VER_06: - case RTL_VER_08: - case RTL_VER_09: -+ case RTL_VER_14: - if (enable) { - r8153_eee_en(tp, true); - ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); -@@ -4246,6 +4720,19 @@ static void rtl_eee_enable(struct r8152 - ocp_reg_write(tp, OCP_EEE_ADV, 0); - } - break; -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_15: -+ if (enable) { -+ r8156_eee_en(tp, true); -+ ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); -+ } else { -+ r8156_eee_en(tp, false); -+ ocp_reg_write(tp, OCP_EEE_ADV, 0); -+ } -+ break; - default: - break; - } -@@ -4292,6 +4779,20 @@ static void wait_oob_link_list_ready(str - } - } - -+static void r8156b_wait_loading_flash(struct r8152 *tp) -+{ -+ if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) && -+ !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) { -+ int i; -+ -+ for (i = 0; i < 100; i++) { -+ if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE) -+ break; -+ usleep_range(1000, 2000); -+ } -+ } -+} -+ - static void r8152b_exit_oob(struct r8152 *tp) - { - u32 ocp_data; -@@ -4342,7 +4843,7 @@ static void r8152b_exit_oob(struct r8152 - } - - /* TX share fifo free credit full threshold */ -- ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); -+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); - - ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); - ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); -@@ -4519,6 +5020,21 @@ static int r8153b_post_firmware_1(struct - return 0; - } - -+static int r8153c_post_firmware_1(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); -+ ocp_data |= FLOW_CTRL_PATCH_2; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); -+ ocp_data |= FC_PATCH_TASK; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); -+ -+ return 0; -+} -+ - static void r8153_aldps_en(struct r8152 *tp, bool enable) - { - u16 data; -@@ -4721,6 +5237,13 @@ static void r8153b_hw_phy_cfg(struct r81 - set_bit(PHY_RESET, &tp->flags); - } - -+static void r8153c_hw_phy_cfg(struct r8152 *tp) -+{ -+ r8153b_hw_phy_cfg(tp); -+ -+ tp->ups_info.r_tune = true; -+} -+ - static void rtl8153_change_mtu(struct r8152 *tp) - { - ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); -@@ -4808,6 +5331,7 @@ static void r8153_enter_oob(struct r8152 - - case RTL_VER_08: - case RTL_VER_09: -+ case RTL_VER_14: - /* Clear teredo wake event. bit[15:8] is the teredo wakeup - * type. Set it to zero. bits[7:0] are the W1C bits about - * the events. Set them to all 1 to clear them. -@@ -4844,6 +5368,96 @@ static void rtl8153_disable(struct r8152 - r8153_aldps_en(tp, true); - } - -+static int rtl8156_enable(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ u16 speed; -+ -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return -ENODEV; -+ -+ set_tx_qlen(tp); -+ rtl_set_eee_plus(tp); -+ r8153_set_rx_early_timeout(tp); -+ r8153_set_rx_early_size(tp); -+ -+ speed = rtl8152_get_speed(tp); -+ rtl_set_ifg(tp, speed); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); -+ if (speed & _2500bps) -+ ocp_data &= ~IDLE_SPDWN_EN; -+ else -+ ocp_data |= IDLE_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); -+ -+ if (speed & _1000bps) -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); -+ else if (speed & _500bps) -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); -+ -+ if (tp->udev->speed == USB_SPEED_HIGH) { -+ /* USB 0xb45e[3:0] l1_nyet_hird */ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); -+ ocp_data &= ~0xf; -+ if (is_flow_control(speed)) -+ ocp_data |= 0xf; -+ else -+ ocp_data |= 0x1; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); -+ } -+ -+ return rtl_enable(tp); -+} -+ -+static int rtl8156b_enable(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ u16 speed; -+ -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return -ENODEV; -+ -+ set_tx_qlen(tp); -+ rtl_set_eee_plus(tp); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM); -+ ocp_data &= ~RX_AGGR_NUM_MASK; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data); -+ -+ r8153_set_rx_early_timeout(tp); -+ r8153_set_rx_early_size(tp); -+ -+ speed = rtl8152_get_speed(tp); -+ rtl_set_ifg(tp, speed); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); -+ if (speed & _2500bps) -+ ocp_data &= ~IDLE_SPDWN_EN; -+ else -+ ocp_data |= IDLE_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); -+ -+ if (tp->udev->speed == USB_SPEED_HIGH) { -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); -+ ocp_data &= ~0xf; -+ if (is_flow_control(speed)) -+ ocp_data |= 0xf; -+ else -+ ocp_data |= 0x1; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); -+ } -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); -+ ocp_data &= ~FC_PATCH_TASK; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); -+ usleep_range(1000, 2000); -+ ocp_data |= FC_PATCH_TASK; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); -+ -+ return rtl_enable(tp); -+} -+ - static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, - u32 advertising) - { -@@ -4892,58 +5506,73 @@ static int rtl8152_set_speed(struct r815 - - tp->mii.force_media = 1; - } else { -- u16 anar, tmp1; -+ u16 orig, new1; - u32 support; - - support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | - RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; - -- if (tp->mii.supports_gmii) -+ if (tp->mii.supports_gmii) { - support |= RTL_ADVERTISED_1000_FULL; - -+ if (tp->support_2500full) -+ support |= RTL_ADVERTISED_2500_FULL; -+ } -+ - if (!(advertising & support)) - return -EINVAL; - -- anar = r8152_mdio_read(tp, MII_ADVERTISE); -- tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL | -+ orig = r8152_mdio_read(tp, MII_ADVERTISE); -+ new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL | - ADVERTISE_100HALF | ADVERTISE_100FULL); - if (advertising & RTL_ADVERTISED_10_HALF) { -- tmp1 |= ADVERTISE_10HALF; -+ new1 |= ADVERTISE_10HALF; - tp->ups_info.speed_duplex = NWAY_10M_HALF; - } - if (advertising & RTL_ADVERTISED_10_FULL) { -- tmp1 |= ADVERTISE_10FULL; -+ new1 |= ADVERTISE_10FULL; - tp->ups_info.speed_duplex = NWAY_10M_FULL; - } - - if (advertising & RTL_ADVERTISED_100_HALF) { -- tmp1 |= ADVERTISE_100HALF; -+ new1 |= ADVERTISE_100HALF; - tp->ups_info.speed_duplex = NWAY_100M_HALF; - } - if (advertising & RTL_ADVERTISED_100_FULL) { -- tmp1 |= ADVERTISE_100FULL; -+ new1 |= ADVERTISE_100FULL; - tp->ups_info.speed_duplex = NWAY_100M_FULL; - } - -- if (anar != tmp1) { -- r8152_mdio_write(tp, MII_ADVERTISE, tmp1); -- tp->mii.advertising = tmp1; -+ if (orig != new1) { -+ r8152_mdio_write(tp, MII_ADVERTISE, new1); -+ tp->mii.advertising = new1; - } - - if (tp->mii.supports_gmii) { -- u16 gbcr; -- -- gbcr = r8152_mdio_read(tp, MII_CTRL1000); -- tmp1 = gbcr & ~(ADVERTISE_1000FULL | -+ orig = r8152_mdio_read(tp, MII_CTRL1000); -+ new1 = orig & ~(ADVERTISE_1000FULL | - ADVERTISE_1000HALF); - - if (advertising & RTL_ADVERTISED_1000_FULL) { -- tmp1 |= ADVERTISE_1000FULL; -+ new1 |= ADVERTISE_1000FULL; - tp->ups_info.speed_duplex = NWAY_1000M_FULL; - } - -- if (gbcr != tmp1) -- r8152_mdio_write(tp, MII_CTRL1000, tmp1); -+ if (orig != new1) -+ r8152_mdio_write(tp, MII_CTRL1000, new1); -+ } -+ -+ if (tp->support_2500full) { -+ orig = ocp_reg_read(tp, OCP_10GBT_CTRL); -+ new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G; -+ -+ if (advertising & RTL_ADVERTISED_2500_FULL) { -+ new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G; -+ tp->ups_info.speed_duplex = NWAY_2500M_FULL; -+ } -+ -+ if (orig != new1) -+ ocp_reg_write(tp, OCP_10GBT_CTRL, new1); - } - - bmcr = BMCR_ANENABLE | BMCR_ANRESTART; -@@ -5099,6 +5728,253 @@ static void rtl8153b_down(struct r8152 * - r8153_aldps_en(tp, true); - } - -+static void rtl8153c_change_mtu(struct r8152 *tp) -+{ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64); -+ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); -+ -+ /* Adjust the tx fifo free credit full threshold, otherwise -+ * the fifo would be too small to send a jumbo frame packet. -+ */ -+ if (tp->netdev->mtu < 8000) -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8); -+ else -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8); -+} -+ -+static void rtl8153c_up(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return; -+ -+ r8153b_u1u2en(tp, false); -+ r8153_u2p3en(tp, false); -+ r8153_aldps_en(tp, false); -+ -+ rxdy_gated_en(tp, true); -+ r8153_teredo_off(tp); -+ -+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); -+ ocp_data &= ~RCR_ACPT_ALL; -+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); -+ -+ rtl8152_nic_reset(tp); -+ rtl_reset_bmu(tp); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); -+ ocp_data &= ~NOW_IS_OOB; -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); -+ ocp_data &= ~MCU_BORW_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); -+ -+ wait_oob_link_list_ready(tp); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); -+ ocp_data |= RE_INIT_LL; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); -+ -+ wait_oob_link_list_ready(tp); -+ -+ rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); -+ -+ rtl8153c_change_mtu(tp); -+ -+ rtl8152_nic_reset(tp); -+ -+ /* rx share fifo credit full threshold */ -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02); -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); -+ -+ ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); -+ -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); -+ ocp_data |= BIT(8); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); -+ -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); -+ ocp_data &= ~PLA_MCU_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); -+ -+ r8153_aldps_en(tp, true); -+ r8153b_u1u2en(tp, true); -+} -+ -+static inline u32 fc_pause_on_auto(struct r8152 *tp) -+{ -+ return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024); -+} -+ -+static inline u32 fc_pause_off_auto(struct r8152 *tp) -+{ -+ return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024); -+} -+ -+static void r8156_fc_parameter(struct r8152 *tp) -+{ -+ u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp); -+ u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp); -+ -+ switch (tp->version) { -+ case RTL_VER_10: -+ case RTL_VER_11: -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8); -+ break; -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_15: -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16); -+ break; -+ default: -+ break; -+ } -+} -+ -+static void rtl8156_change_mtu(struct r8152 *tp) -+{ -+ u32 rx_max_size = mtu_to_size(tp->netdev->mtu); -+ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size); -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); -+ r8156_fc_parameter(tp); -+ -+ /* TX share fifo free credit full threshold */ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, -+ ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16); -+} -+ -+static void rtl8156_up(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return; -+ -+ r8153b_u1u2en(tp, false); -+ r8153_u2p3en(tp, false); -+ r8153_aldps_en(tp, false); -+ -+ rxdy_gated_en(tp, true); -+ r8153_teredo_off(tp); -+ -+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); -+ ocp_data &= ~RCR_ACPT_ALL; -+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); -+ -+ rtl8152_nic_reset(tp); -+ rtl_reset_bmu(tp); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); -+ ocp_data &= ~NOW_IS_OOB; -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); -+ ocp_data &= ~MCU_BORW_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); -+ -+ rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); -+ -+ rtl8156_change_mtu(tp); -+ -+ switch (tp->version) { -+ case RTL_TEST_01: -+ case RTL_VER_10: -+ case RTL_VER_11: -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG); -+ ocp_data |= ACT_ODMA; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); -+ break; -+ default: -+ break; -+ } -+ -+ /* share FIFO settings */ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL); -+ ocp_data &= ~RXFIFO_FULL_MASK; -+ ocp_data |= 0x08; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); -+ ocp_data &= ~PLA_MCU_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION); -+ ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF); -+ ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data); -+ -+ ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); -+ -+ if (tp->saved_wolopts != __rtl_get_wol(tp)) { -+ netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n"); -+ __rtl_set_wol(tp, tp->saved_wolopts); -+ } -+ -+ r8153_aldps_en(tp, true); -+ r8153_u2p3en(tp, true); -+ -+ if (tp->udev->speed >= USB_SPEED_SUPER) -+ r8153b_u1u2en(tp, true); -+} -+ -+static void rtl8156_down(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ rtl_drop_queued_tx(tp); -+ return; -+ } -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); -+ ocp_data |= PLA_MCU_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); -+ -+ r8153b_u1u2en(tp, false); -+ r8153_u2p3en(tp, false); -+ r8153b_power_cut_en(tp, false); -+ r8153_aldps_en(tp, false); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); -+ ocp_data &= ~NOW_IS_OOB; -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); -+ -+ rtl_disable(tp); -+ rtl_reset_bmu(tp); -+ -+ /* Clear teredo wake event. bit[15:8] is the teredo wakeup -+ * type. Set it to zero. bits[7:0] are the W1C bits about -+ * the events. Set them to all 1 to clear them. -+ */ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); -+ ocp_data |= NOW_IS_OOB; -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); -+ -+ rtl_rx_vlan_en(tp, true); -+ rxdy_gated_en(tp, false); -+ -+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); -+ ocp_data |= RCR_APM | RCR_AM | RCR_AB; -+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); -+ -+ r8153_aldps_en(tp, true); -+} -+ - static bool rtl8152_in_nway(struct r8152 *tp) - { - u16 nway_state; -@@ -5129,7 +6005,7 @@ static void set_carrier(struct r8152 *tp - { - struct net_device *netdev = tp->netdev; - struct napi_struct *napi = &tp->napi; -- u8 speed; -+ u16 speed; - - speed = rtl8152_get_speed(tp); - -@@ -5142,7 +6018,7 @@ static void set_carrier(struct r8152 *tp - rtl_start_rx(tp); - clear_bit(RTL8152_SET_RX_MODE, &tp->flags); - _rtl8152_set_rx_mode(netdev); -- napi_enable(&tp->napi); -+ napi_enable(napi); - netif_wake_queue(netdev); - netif_info(tp, link, netdev, "carrier on\n"); - } else if (netif_queue_stopped(netdev) && -@@ -5504,14 +6380,9 @@ static void r8153_init(struct r8152 *tp) - - ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); - -- /* MAC clock speed down */ -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); -- - r8153_power_cut_en(tp, false); - rtl_runtime_suspend_enable(tp, false); -+ r8153_mac_clk_speed_down(tp, false); - r8153_u1u2en(tp, true); - usb_enable_lpm(tp->udev); - -@@ -5602,9 +6473,7 @@ static void r8153b_init(struct r8152 *tp - usb_enable_lpm(tp->udev); - - /* MAC clock speed down */ -- ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); -- ocp_data |= MAC_CLK_SPDWN_EN; -- ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); -+ r8153_mac_clk_speed_down(tp, true); - - ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); - ocp_data &= ~PLA_MCU_SPDWN_EN; -@@ -5631,6 +6500,1069 @@ static void r8153b_init(struct r8152 *tp - tp->coalesce = 15000; /* 15 us */ - } - -+static void r8153c_init(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ u16 data; -+ int i; -+ -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return; -+ -+ r8153b_u1u2en(tp, false); -+ -+ /* Disable spi_en */ -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); -+ ocp_data &= ~BIT(3); -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0); -+ ocp_data |= BIT(1); -+ ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data); -+ -+ for (i = 0; i < 500; i++) { -+ if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & -+ AUTOLOAD_DONE) -+ break; -+ -+ msleep(20); -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return; -+ } -+ -+ data = r8153_phy_status(tp, 0); -+ -+ data = r8152_mdio_read(tp, MII_BMCR); -+ if (data & BMCR_PDOWN) { -+ data &= ~BMCR_PDOWN; -+ r8152_mdio_write(tp, MII_BMCR, data); -+ } -+ -+ data = r8153_phy_status(tp, PHY_STAT_LAN_ON); -+ -+ r8153_u2p3en(tp, false); -+ -+ /* MSC timer = 0xfff * 8ms = 32760 ms */ -+ ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); -+ -+ r8153b_power_cut_en(tp, false); -+ r8153c_ups_en(tp, false); -+ r8153_queue_wake(tp, false); -+ rtl_runtime_suspend_enable(tp, false); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); -+ if (rtl8152_get_speed(tp) & LINK_STATUS) -+ ocp_data |= CUR_LINK_OK; -+ else -+ ocp_data &= ~CUR_LINK_OK; -+ -+ ocp_data |= POLL_LINK_CHG; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); -+ -+ r8153b_u1u2en(tp, true); -+ -+ usb_enable_lpm(tp->udev); -+ -+ /* MAC clock speed down */ -+ r8153_mac_clk_speed_down(tp, true); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); -+ ocp_data &= ~BIT(7); -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); -+ -+ set_bit(GREEN_ETHERNET, &tp->flags); -+ -+ /* rx aggregation */ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); -+ ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); -+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); -+ -+ rtl_tally_reset(tp); -+ -+ tp->coalesce = 15000; /* 15 us */ -+} -+ -+static void r8156_hw_phy_cfg(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ u16 data; -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); -+ if (ocp_data & PCUT_STATUS) { -+ ocp_data &= ~PCUT_STATUS; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); -+ } -+ -+ data = r8153_phy_status(tp, 0); -+ switch (data) { -+ case PHY_STAT_EXT_INIT: -+ rtl8152_apply_firmware(tp, true); -+ -+ data = ocp_reg_read(tp, 0xa468); -+ data &= ~(BIT(3) | BIT(1)); -+ ocp_reg_write(tp, 0xa468, data); -+ break; -+ case PHY_STAT_LAN_ON: -+ case PHY_STAT_PWRDN: -+ default: -+ rtl8152_apply_firmware(tp, false); -+ break; -+ } -+ -+ /* disable ALDPS before updating the PHY parameters */ -+ r8153_aldps_en(tp, false); -+ -+ /* disable EEE before updating the PHY parameters */ -+ rtl_eee_enable(tp, false); -+ -+ data = r8153_phy_status(tp, PHY_STAT_LAN_ON); -+ WARN_ON_ONCE(data != PHY_STAT_LAN_ON); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); -+ ocp_data |= PFM_PWM_SWITCH; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); -+ -+ switch (tp->version) { -+ case RTL_VER_10: -+ data = ocp_reg_read(tp, 0xad40); -+ data &= ~0x3ff; -+ data |= BIT(7) | BIT(2); -+ ocp_reg_write(tp, 0xad40, data); -+ -+ data = ocp_reg_read(tp, 0xad4e); -+ data |= BIT(4); -+ ocp_reg_write(tp, 0xad4e, data); -+ data = ocp_reg_read(tp, 0xad16); -+ data &= ~0x3ff; -+ data |= 0x6; -+ ocp_reg_write(tp, 0xad16, data); -+ data = ocp_reg_read(tp, 0xad32); -+ data &= ~0x3f; -+ data |= 6; -+ ocp_reg_write(tp, 0xad32, data); -+ data = ocp_reg_read(tp, 0xac08); -+ data &= ~(BIT(12) | BIT(8)); -+ ocp_reg_write(tp, 0xac08, data); -+ data = ocp_reg_read(tp, 0xac8a); -+ data |= BIT(12) | BIT(13) | BIT(14); -+ data &= ~BIT(15); -+ ocp_reg_write(tp, 0xac8a, data); -+ data = ocp_reg_read(tp, 0xad18); -+ data |= BIT(10); -+ ocp_reg_write(tp, 0xad18, data); -+ data = ocp_reg_read(tp, 0xad1a); -+ data |= 0x3ff; -+ ocp_reg_write(tp, 0xad1a, data); -+ data = ocp_reg_read(tp, 0xad1c); -+ data |= 0x3ff; -+ ocp_reg_write(tp, 0xad1c, data); -+ -+ data = sram_read(tp, 0x80ea); -+ data &= ~0xff00; -+ data |= 0xc400; -+ sram_write(tp, 0x80ea, data); -+ data = sram_read(tp, 0x80eb); -+ data &= ~0x0700; -+ data |= 0x0300; -+ sram_write(tp, 0x80eb, data); -+ data = sram_read(tp, 0x80f8); -+ data &= ~0xff00; -+ data |= 0x1c00; -+ sram_write(tp, 0x80f8, data); -+ data = sram_read(tp, 0x80f1); -+ data &= ~0xff00; -+ data |= 0x3000; -+ sram_write(tp, 0x80f1, data); -+ -+ data = sram_read(tp, 0x80fe); -+ data &= ~0xff00; -+ data |= 0xa500; -+ sram_write(tp, 0x80fe, data); -+ data = sram_read(tp, 0x8102); -+ data &= ~0xff00; -+ data |= 0x5000; -+ sram_write(tp, 0x8102, data); -+ data = sram_read(tp, 0x8015); -+ data &= ~0xff00; -+ data |= 0x3300; -+ sram_write(tp, 0x8015, data); -+ data = sram_read(tp, 0x8100); -+ data &= ~0xff00; -+ data |= 0x7000; -+ sram_write(tp, 0x8100, data); -+ data = sram_read(tp, 0x8014); -+ data &= ~0xff00; -+ data |= 0xf000; -+ sram_write(tp, 0x8014, data); -+ data = sram_read(tp, 0x8016); -+ data &= ~0xff00; -+ data |= 0x6500; -+ sram_write(tp, 0x8016, data); -+ data = sram_read(tp, 0x80dc); -+ data &= ~0xff00; -+ data |= 0xed00; -+ sram_write(tp, 0x80dc, data); -+ data = sram_read(tp, 0x80df); -+ data |= BIT(8); -+ sram_write(tp, 0x80df, data); -+ data = sram_read(tp, 0x80e1); -+ data &= ~BIT(8); -+ sram_write(tp, 0x80e1, data); -+ -+ data = ocp_reg_read(tp, 0xbf06); -+ data &= ~0x003f; -+ data |= 0x0038; -+ ocp_reg_write(tp, 0xbf06, data); -+ -+ sram_write(tp, 0x819f, 0xddb6); -+ -+ ocp_reg_write(tp, 0xbc34, 0x5555); -+ data = ocp_reg_read(tp, 0xbf0a); -+ data &= ~0x0e00; -+ data |= 0x0a00; -+ ocp_reg_write(tp, 0xbf0a, data); -+ -+ data = ocp_reg_read(tp, 0xbd2c); -+ data &= ~BIT(13); -+ ocp_reg_write(tp, 0xbd2c, data); -+ break; -+ case RTL_VER_11: -+ data = ocp_reg_read(tp, 0xad16); -+ data |= 0x3ff; -+ ocp_reg_write(tp, 0xad16, data); -+ data = ocp_reg_read(tp, 0xad32); -+ data &= ~0x3f; -+ data |= 6; -+ ocp_reg_write(tp, 0xad32, data); -+ data = ocp_reg_read(tp, 0xac08); -+ data &= ~(BIT(12) | BIT(8)); -+ ocp_reg_write(tp, 0xac08, data); -+ data = ocp_reg_read(tp, 0xacc0); -+ data &= ~0x3; -+ data |= BIT(1); -+ ocp_reg_write(tp, 0xacc0, data); -+ data = ocp_reg_read(tp, 0xad40); -+ data &= ~0xe7; -+ data |= BIT(6) | BIT(2); -+ ocp_reg_write(tp, 0xad40, data); -+ data = ocp_reg_read(tp, 0xac14); -+ data &= ~BIT(7); -+ ocp_reg_write(tp, 0xac14, data); -+ data = ocp_reg_read(tp, 0xac80); -+ data &= ~(BIT(8) | BIT(9)); -+ ocp_reg_write(tp, 0xac80, data); -+ data = ocp_reg_read(tp, 0xac5e); -+ data &= ~0x7; -+ data |= BIT(1); -+ ocp_reg_write(tp, 0xac5e, data); -+ ocp_reg_write(tp, 0xad4c, 0x00a8); -+ ocp_reg_write(tp, 0xac5c, 0x01ff); -+ data = ocp_reg_read(tp, 0xac8a); -+ data &= ~0xf0; -+ data |= BIT(4) | BIT(5); -+ ocp_reg_write(tp, 0xac8a, data); -+ ocp_reg_write(tp, 0xb87c, 0x8157); -+ data = ocp_reg_read(tp, 0xb87e); -+ data &= ~0xff00; -+ data |= 0x0500; -+ ocp_reg_write(tp, 0xb87e, data); -+ ocp_reg_write(tp, 0xb87c, 0x8159); -+ data = ocp_reg_read(tp, 0xb87e); -+ data &= ~0xff00; -+ data |= 0x0700; -+ ocp_reg_write(tp, 0xb87e, data); -+ -+ /* AAGC */ -+ ocp_reg_write(tp, 0xb87c, 0x80a2); -+ ocp_reg_write(tp, 0xb87e, 0x0153); -+ ocp_reg_write(tp, 0xb87c, 0x809c); -+ ocp_reg_write(tp, 0xb87e, 0x0153); -+ -+ /* EEE parameter */ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG); -+ ocp_data |= EN_XG_LIP | EN_G_LIP; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); -+ -+ sram_write(tp, 0x8257, 0x020f); /* XG PLL */ -+ sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */ -+ -+ if (rtl_phy_patch_request(tp, true, true)) -+ return; -+ -+ /* Advance EEE */ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); -+ ocp_data |= EEE_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); -+ -+ data = ocp_reg_read(tp, OCP_DOWN_SPEED); -+ data &= ~(EN_EEE_100 | EN_EEE_1000); -+ data |= EN_10M_CLKDIV; -+ ocp_reg_write(tp, OCP_DOWN_SPEED, data); -+ tp->ups_info._10m_ckdiv = true; -+ tp->ups_info.eee_plloff_100 = false; -+ tp->ups_info.eee_plloff_giga = false; -+ -+ data = ocp_reg_read(tp, OCP_POWER_CFG); -+ data &= ~EEE_CLKDIV_EN; -+ ocp_reg_write(tp, OCP_POWER_CFG, data); -+ tp->ups_info.eee_ckdiv = false; -+ -+ ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); -+ ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5)); -+ tp->ups_info._250m_ckdiv = false; -+ -+ rtl_phy_patch_request(tp, false, true); -+ -+ /* enable ADC Ibias Cal */ -+ data = ocp_reg_read(tp, 0xd068); -+ data |= BIT(13); -+ ocp_reg_write(tp, 0xd068, data); -+ -+ /* enable Thermal Sensor */ -+ data = sram_read(tp, 0x81a2); -+ data &= ~BIT(8); -+ sram_write(tp, 0x81a2, data); -+ data = ocp_reg_read(tp, 0xb54c); -+ data &= ~0xff00; -+ data |= 0xdb00; -+ ocp_reg_write(tp, 0xb54c, data); -+ -+ /* Nway 2.5G Lite */ -+ data = ocp_reg_read(tp, 0xa454); -+ data &= ~BIT(0); -+ ocp_reg_write(tp, 0xa454, data); -+ -+ /* CS DSP solution */ -+ data = ocp_reg_read(tp, OCP_10GBT_CTRL); -+ data |= RTL_ADV2_5G_F_R; -+ ocp_reg_write(tp, OCP_10GBT_CTRL, data); -+ data = ocp_reg_read(tp, 0xad4e); -+ data &= ~BIT(4); -+ ocp_reg_write(tp, 0xad4e, data); -+ data = ocp_reg_read(tp, 0xa86a); -+ data &= ~BIT(0); -+ ocp_reg_write(tp, 0xa86a, data); -+ -+ /* MDI SWAP */ -+ if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) && -+ (ocp_reg_read(tp, 0xd068) & BIT(1))) { -+ u16 swap_a, swap_b; -+ -+ data = ocp_reg_read(tp, 0xd068); -+ data &= ~0x1f; -+ data |= 0x1; /* p0 */ -+ ocp_reg_write(tp, 0xd068, data); -+ swap_a = ocp_reg_read(tp, 0xd06a); -+ data &= ~0x18; -+ data |= 0x18; /* p3 */ -+ ocp_reg_write(tp, 0xd068, data); -+ swap_b = ocp_reg_read(tp, 0xd06a); -+ data &= ~0x18; /* p0 */ -+ ocp_reg_write(tp, 0xd068, data); -+ ocp_reg_write(tp, 0xd06a, -+ (swap_a & ~0x7ff) | (swap_b & 0x7ff)); -+ data |= 0x18; /* p3 */ -+ ocp_reg_write(tp, 0xd068, data); -+ ocp_reg_write(tp, 0xd06a, -+ (swap_b & ~0x7ff) | (swap_a & 0x7ff)); -+ data &= ~0x18; -+ data |= 0x08; /* p1 */ -+ ocp_reg_write(tp, 0xd068, data); -+ swap_a = ocp_reg_read(tp, 0xd06a); -+ data &= ~0x18; -+ data |= 0x10; /* p2 */ -+ ocp_reg_write(tp, 0xd068, data); -+ swap_b = ocp_reg_read(tp, 0xd06a); -+ data &= ~0x18; -+ data |= 0x08; /* p1 */ -+ ocp_reg_write(tp, 0xd068, data); -+ ocp_reg_write(tp, 0xd06a, -+ (swap_a & ~0x7ff) | (swap_b & 0x7ff)); -+ data &= ~0x18; -+ data |= 0x10; /* p2 */ -+ ocp_reg_write(tp, 0xd068, data); -+ ocp_reg_write(tp, 0xd06a, -+ (swap_b & ~0x7ff) | (swap_a & 0x7ff)); -+ swap_a = ocp_reg_read(tp, 0xbd5a); -+ swap_b = ocp_reg_read(tp, 0xbd5c); -+ ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) | -+ ((swap_b & 0x1f) << 8) | -+ ((swap_b >> 8) & 0x1f)); -+ ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) | -+ ((swap_a & 0x1f) << 8) | -+ ((swap_a >> 8) & 0x1f)); -+ swap_a = ocp_reg_read(tp, 0xbc18); -+ swap_b = ocp_reg_read(tp, 0xbc1a); -+ ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) | -+ ((swap_b & 0x1f) << 8) | -+ ((swap_b >> 8) & 0x1f)); -+ ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) | -+ ((swap_a & 0x1f) << 8) | -+ ((swap_a >> 8) & 0x1f)); -+ } -+ break; -+ default: -+ break; -+ } -+ -+ rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); -+ -+ data = ocp_reg_read(tp, 0xa428); -+ data &= ~BIT(9); -+ ocp_reg_write(tp, 0xa428, data); -+ data = ocp_reg_read(tp, 0xa5ea); -+ data &= ~BIT(0); -+ ocp_reg_write(tp, 0xa5ea, data); -+ tp->ups_info.lite_mode = 0; -+ -+ if (tp->eee_en) -+ rtl_eee_enable(tp, true); -+ -+ r8153_aldps_en(tp, true); -+ r8152b_enable_fc(tp); -+ r8153_u2p3en(tp, true); -+ -+ set_bit(PHY_RESET, &tp->flags); -+} -+ -+static void r8156b_hw_phy_cfg(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ u16 data; -+ -+ switch (tp->version) { -+ case RTL_VER_12: -+ ocp_reg_write(tp, 0xbf86, 0x9000); -+ data = ocp_reg_read(tp, 0xc402); -+ data |= BIT(10); -+ ocp_reg_write(tp, 0xc402, data); -+ data &= ~BIT(10); -+ ocp_reg_write(tp, 0xc402, data); -+ ocp_reg_write(tp, 0xbd86, 0x1010); -+ ocp_reg_write(tp, 0xbd88, 0x1010); -+ data = ocp_reg_read(tp, 0xbd4e); -+ data &= ~(BIT(10) | BIT(11)); -+ data |= BIT(11); -+ ocp_reg_write(tp, 0xbd4e, data); -+ data = ocp_reg_read(tp, 0xbf46); -+ data &= ~0xf00; -+ data |= 0x700; -+ ocp_reg_write(tp, 0xbf46, data); -+ break; -+ case RTL_VER_13: -+ case RTL_VER_15: -+ r8156b_wait_loading_flash(tp); -+ break; -+ default: -+ break; -+ } -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); -+ if (ocp_data & PCUT_STATUS) { -+ ocp_data &= ~PCUT_STATUS; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); -+ } -+ -+ data = r8153_phy_status(tp, 0); -+ switch (data) { -+ case PHY_STAT_EXT_INIT: -+ rtl8152_apply_firmware(tp, true); -+ -+ data = ocp_reg_read(tp, 0xa466); -+ data &= ~BIT(0); -+ ocp_reg_write(tp, 0xa466, data); -+ -+ data = ocp_reg_read(tp, 0xa468); -+ data &= ~(BIT(3) | BIT(1)); -+ ocp_reg_write(tp, 0xa468, data); -+ break; -+ case PHY_STAT_LAN_ON: -+ case PHY_STAT_PWRDN: -+ default: -+ rtl8152_apply_firmware(tp, false); -+ break; -+ } -+ -+ data = r8152_mdio_read(tp, MII_BMCR); -+ if (data & BMCR_PDOWN) { -+ data &= ~BMCR_PDOWN; -+ r8152_mdio_write(tp, MII_BMCR, data); -+ } -+ -+ /* disable ALDPS before updating the PHY parameters */ -+ r8153_aldps_en(tp, false); -+ -+ /* disable EEE before updating the PHY parameters */ -+ rtl_eee_enable(tp, false); -+ -+ data = r8153_phy_status(tp, PHY_STAT_LAN_ON); -+ WARN_ON_ONCE(data != PHY_STAT_LAN_ON); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); -+ ocp_data |= PFM_PWM_SWITCH; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); -+ -+ switch (tp->version) { -+ case RTL_VER_12: -+ data = ocp_reg_read(tp, 0xbc08); -+ data |= BIT(3) | BIT(2); -+ ocp_reg_write(tp, 0xbc08, data); -+ -+ data = sram_read(tp, 0x8fff); -+ data &= ~0xff00; -+ data |= 0x0400; -+ sram_write(tp, 0x8fff, data); -+ -+ data = ocp_reg_read(tp, 0xacda); -+ data |= 0xff00; -+ ocp_reg_write(tp, 0xacda, data); -+ data = ocp_reg_read(tp, 0xacde); -+ data |= 0xf000; -+ ocp_reg_write(tp, 0xacde, data); -+ ocp_reg_write(tp, 0xac8c, 0x0ffc); -+ ocp_reg_write(tp, 0xac46, 0xb7b4); -+ ocp_reg_write(tp, 0xac50, 0x0fbc); -+ ocp_reg_write(tp, 0xac3c, 0x9240); -+ ocp_reg_write(tp, 0xac4e, 0x0db4); -+ ocp_reg_write(tp, 0xacc6, 0x0707); -+ ocp_reg_write(tp, 0xacc8, 0xa0d3); -+ ocp_reg_write(tp, 0xad08, 0x0007); -+ -+ ocp_reg_write(tp, 0xb87c, 0x8560); -+ ocp_reg_write(tp, 0xb87e, 0x19cc); -+ ocp_reg_write(tp, 0xb87c, 0x8562); -+ ocp_reg_write(tp, 0xb87e, 0x19cc); -+ ocp_reg_write(tp, 0xb87c, 0x8564); -+ ocp_reg_write(tp, 0xb87e, 0x19cc); -+ ocp_reg_write(tp, 0xb87c, 0x8566); -+ ocp_reg_write(tp, 0xb87e, 0x147d); -+ ocp_reg_write(tp, 0xb87c, 0x8568); -+ ocp_reg_write(tp, 0xb87e, 0x147d); -+ ocp_reg_write(tp, 0xb87c, 0x856a); -+ ocp_reg_write(tp, 0xb87e, 0x147d); -+ ocp_reg_write(tp, 0xb87c, 0x8ffe); -+ ocp_reg_write(tp, 0xb87e, 0x0907); -+ ocp_reg_write(tp, 0xb87c, 0x80d6); -+ ocp_reg_write(tp, 0xb87e, 0x2801); -+ ocp_reg_write(tp, 0xb87c, 0x80f2); -+ ocp_reg_write(tp, 0xb87e, 0x2801); -+ ocp_reg_write(tp, 0xb87c, 0x80f4); -+ ocp_reg_write(tp, 0xb87e, 0x6077); -+ ocp_reg_write(tp, 0xb506, 0x01e7); -+ -+ ocp_reg_write(tp, 0xb87c, 0x8013); -+ ocp_reg_write(tp, 0xb87e, 0x0700); -+ ocp_reg_write(tp, 0xb87c, 0x8fb9); -+ ocp_reg_write(tp, 0xb87e, 0x2801); -+ ocp_reg_write(tp, 0xb87c, 0x8fba); -+ ocp_reg_write(tp, 0xb87e, 0x0100); -+ ocp_reg_write(tp, 0xb87c, 0x8fbc); -+ ocp_reg_write(tp, 0xb87e, 0x1900); -+ ocp_reg_write(tp, 0xb87c, 0x8fbe); -+ ocp_reg_write(tp, 0xb87e, 0xe100); -+ ocp_reg_write(tp, 0xb87c, 0x8fc0); -+ ocp_reg_write(tp, 0xb87e, 0x0800); -+ ocp_reg_write(tp, 0xb87c, 0x8fc2); -+ ocp_reg_write(tp, 0xb87e, 0xe500); -+ ocp_reg_write(tp, 0xb87c, 0x8fc4); -+ ocp_reg_write(tp, 0xb87e, 0x0f00); -+ ocp_reg_write(tp, 0xb87c, 0x8fc6); -+ ocp_reg_write(tp, 0xb87e, 0xf100); -+ ocp_reg_write(tp, 0xb87c, 0x8fc8); -+ ocp_reg_write(tp, 0xb87e, 0x0400); -+ ocp_reg_write(tp, 0xb87c, 0x8fca); -+ ocp_reg_write(tp, 0xb87e, 0xf300); -+ ocp_reg_write(tp, 0xb87c, 0x8fcc); -+ ocp_reg_write(tp, 0xb87e, 0xfd00); -+ ocp_reg_write(tp, 0xb87c, 0x8fce); -+ ocp_reg_write(tp, 0xb87e, 0xff00); -+ ocp_reg_write(tp, 0xb87c, 0x8fd0); -+ ocp_reg_write(tp, 0xb87e, 0xfb00); -+ ocp_reg_write(tp, 0xb87c, 0x8fd2); -+ ocp_reg_write(tp, 0xb87e, 0x0100); -+ ocp_reg_write(tp, 0xb87c, 0x8fd4); -+ ocp_reg_write(tp, 0xb87e, 0xf400); -+ ocp_reg_write(tp, 0xb87c, 0x8fd6); -+ ocp_reg_write(tp, 0xb87e, 0xff00); -+ ocp_reg_write(tp, 0xb87c, 0x8fd8); -+ ocp_reg_write(tp, 0xb87e, 0xf600); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG); -+ ocp_data |= EN_XG_LIP | EN_G_LIP; -+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); -+ ocp_reg_write(tp, 0xb87c, 0x813d); -+ ocp_reg_write(tp, 0xb87e, 0x390e); -+ ocp_reg_write(tp, 0xb87c, 0x814f); -+ ocp_reg_write(tp, 0xb87e, 0x790e); -+ ocp_reg_write(tp, 0xb87c, 0x80b0); -+ ocp_reg_write(tp, 0xb87e, 0x0f31); -+ data = ocp_reg_read(tp, 0xbf4c); -+ data |= BIT(1); -+ ocp_reg_write(tp, 0xbf4c, data); -+ data = ocp_reg_read(tp, 0xbcca); -+ data |= BIT(9) | BIT(8); -+ ocp_reg_write(tp, 0xbcca, data); -+ ocp_reg_write(tp, 0xb87c, 0x8141); -+ ocp_reg_write(tp, 0xb87e, 0x320e); -+ ocp_reg_write(tp, 0xb87c, 0x8153); -+ ocp_reg_write(tp, 0xb87e, 0x720e); -+ ocp_reg_write(tp, 0xb87c, 0x8529); -+ ocp_reg_write(tp, 0xb87e, 0x050e); -+ data = ocp_reg_read(tp, OCP_EEE_CFG); -+ data &= ~CTAP_SHORT_EN; -+ ocp_reg_write(tp, OCP_EEE_CFG, data); -+ -+ sram_write(tp, 0x816c, 0xc4a0); -+ sram_write(tp, 0x8170, 0xc4a0); -+ sram_write(tp, 0x8174, 0x04a0); -+ sram_write(tp, 0x8178, 0x04a0); -+ sram_write(tp, 0x817c, 0x0719); -+ sram_write(tp, 0x8ff4, 0x0400); -+ sram_write(tp, 0x8ff1, 0x0404); -+ -+ ocp_reg_write(tp, 0xbf4a, 0x001b); -+ ocp_reg_write(tp, 0xb87c, 0x8033); -+ ocp_reg_write(tp, 0xb87e, 0x7c13); -+ ocp_reg_write(tp, 0xb87c, 0x8037); -+ ocp_reg_write(tp, 0xb87e, 0x7c13); -+ ocp_reg_write(tp, 0xb87c, 0x803b); -+ ocp_reg_write(tp, 0xb87e, 0xfc32); -+ ocp_reg_write(tp, 0xb87c, 0x803f); -+ ocp_reg_write(tp, 0xb87e, 0x7c13); -+ ocp_reg_write(tp, 0xb87c, 0x8043); -+ ocp_reg_write(tp, 0xb87e, 0x7c13); -+ ocp_reg_write(tp, 0xb87c, 0x8047); -+ ocp_reg_write(tp, 0xb87e, 0x7c13); -+ -+ ocp_reg_write(tp, 0xb87c, 0x8145); -+ ocp_reg_write(tp, 0xb87e, 0x370e); -+ ocp_reg_write(tp, 0xb87c, 0x8157); -+ ocp_reg_write(tp, 0xb87e, 0x770e); -+ ocp_reg_write(tp, 0xb87c, 0x8169); -+ ocp_reg_write(tp, 0xb87e, 0x0d0a); -+ ocp_reg_write(tp, 0xb87c, 0x817b); -+ ocp_reg_write(tp, 0xb87e, 0x1d0a); -+ -+ data = sram_read(tp, 0x8217); -+ data &= ~0xff00; -+ data |= 0x5000; -+ sram_write(tp, 0x8217, data); -+ data = sram_read(tp, 0x821a); -+ data &= ~0xff00; -+ data |= 0x5000; -+ sram_write(tp, 0x821a, data); -+ sram_write(tp, 0x80da, 0x0403); -+ data = sram_read(tp, 0x80dc); -+ data &= ~0xff00; -+ data |= 0x1000; -+ sram_write(tp, 0x80dc, data); -+ sram_write(tp, 0x80b3, 0x0384); -+ sram_write(tp, 0x80b7, 0x2007); -+ data = sram_read(tp, 0x80ba); -+ data &= ~0xff00; -+ data |= 0x6c00; -+ sram_write(tp, 0x80ba, data); -+ sram_write(tp, 0x80b5, 0xf009); -+ data = sram_read(tp, 0x80bd); -+ data &= ~0xff00; -+ data |= 0x9f00; -+ sram_write(tp, 0x80bd, data); -+ sram_write(tp, 0x80c7, 0xf083); -+ sram_write(tp, 0x80dd, 0x03f0); -+ data = sram_read(tp, 0x80df); -+ data &= ~0xff00; -+ data |= 0x1000; -+ sram_write(tp, 0x80df, data); -+ sram_write(tp, 0x80cb, 0x2007); -+ data = sram_read(tp, 0x80ce); -+ data &= ~0xff00; -+ data |= 0x6c00; -+ sram_write(tp, 0x80ce, data); -+ sram_write(tp, 0x80c9, 0x8009); -+ data = sram_read(tp, 0x80d1); -+ data &= ~0xff00; -+ data |= 0x8000; -+ sram_write(tp, 0x80d1, data); -+ sram_write(tp, 0x80a3, 0x200a); -+ sram_write(tp, 0x80a5, 0xf0ad); -+ sram_write(tp, 0x809f, 0x6073); -+ sram_write(tp, 0x80a1, 0x000b); -+ data = sram_read(tp, 0x80a9); -+ data &= ~0xff00; -+ data |= 0xc000; -+ sram_write(tp, 0x80a9, data); -+ -+ if (rtl_phy_patch_request(tp, true, true)) -+ return; -+ -+ data = ocp_reg_read(tp, 0xb896); -+ data &= ~BIT(0); -+ ocp_reg_write(tp, 0xb896, data); -+ data = ocp_reg_read(tp, 0xb892); -+ data &= ~0xff00; -+ ocp_reg_write(tp, 0xb892, data); -+ ocp_reg_write(tp, 0xb88e, 0xc23e); -+ ocp_reg_write(tp, 0xb890, 0x0000); -+ ocp_reg_write(tp, 0xb88e, 0xc240); -+ ocp_reg_write(tp, 0xb890, 0x0103); -+ ocp_reg_write(tp, 0xb88e, 0xc242); -+ ocp_reg_write(tp, 0xb890, 0x0507); -+ ocp_reg_write(tp, 0xb88e, 0xc244); -+ ocp_reg_write(tp, 0xb890, 0x090b); -+ ocp_reg_write(tp, 0xb88e, 0xc246); -+ ocp_reg_write(tp, 0xb890, 0x0c0e); -+ ocp_reg_write(tp, 0xb88e, 0xc248); -+ ocp_reg_write(tp, 0xb890, 0x1012); -+ ocp_reg_write(tp, 0xb88e, 0xc24a); -+ ocp_reg_write(tp, 0xb890, 0x1416); -+ data = ocp_reg_read(tp, 0xb896); -+ data |= BIT(0); -+ ocp_reg_write(tp, 0xb896, data); -+ -+ rtl_phy_patch_request(tp, false, true); -+ -+ data = ocp_reg_read(tp, 0xa86a); -+ data |= BIT(0); -+ ocp_reg_write(tp, 0xa86a, data); -+ data = ocp_reg_read(tp, 0xa6f0); -+ data |= BIT(0); -+ ocp_reg_write(tp, 0xa6f0, data); -+ -+ ocp_reg_write(tp, 0xbfa0, 0xd70d); -+ ocp_reg_write(tp, 0xbfa2, 0x4100); -+ ocp_reg_write(tp, 0xbfa4, 0xe868); -+ ocp_reg_write(tp, 0xbfa6, 0xdc59); -+ ocp_reg_write(tp, 0xb54c, 0x3c18); -+ data = ocp_reg_read(tp, 0xbfa4); -+ data &= ~BIT(5); -+ ocp_reg_write(tp, 0xbfa4, data); -+ data = sram_read(tp, 0x817d); -+ data |= BIT(12); -+ sram_write(tp, 0x817d, data); -+ break; -+ case RTL_VER_13: -+ /* 2.5G INRX */ -+ data = ocp_reg_read(tp, 0xac46); -+ data &= ~0x00f0; -+ data |= 0x0090; -+ ocp_reg_write(tp, 0xac46, data); -+ data = ocp_reg_read(tp, 0xad30); -+ data &= ~0x0003; -+ data |= 0x0001; -+ ocp_reg_write(tp, 0xad30, data); -+ fallthrough; -+ case RTL_VER_15: -+ /* EEE parameter */ -+ ocp_reg_write(tp, 0xb87c, 0x80f5); -+ ocp_reg_write(tp, 0xb87e, 0x760e); -+ ocp_reg_write(tp, 0xb87c, 0x8107); -+ ocp_reg_write(tp, 0xb87e, 0x360e); -+ ocp_reg_write(tp, 0xb87c, 0x8551); -+ data = ocp_reg_read(tp, 0xb87e); -+ data &= ~0xff00; -+ data |= 0x0800; -+ ocp_reg_write(tp, 0xb87e, data); -+ -+ /* ADC_PGA parameter */ -+ data = ocp_reg_read(tp, 0xbf00); -+ data &= ~0xe000; -+ data |= 0xa000; -+ ocp_reg_write(tp, 0xbf00, data); -+ data = ocp_reg_read(tp, 0xbf46); -+ data &= ~0x0f00; -+ data |= 0x0300; -+ ocp_reg_write(tp, 0xbf46, data); -+ -+ /* Green Table-PGA, 1G full viterbi */ -+ sram_write(tp, 0x8044, 0x2417); -+ sram_write(tp, 0x804a, 0x2417); -+ sram_write(tp, 0x8050, 0x2417); -+ sram_write(tp, 0x8056, 0x2417); -+ sram_write(tp, 0x805c, 0x2417); -+ sram_write(tp, 0x8062, 0x2417); -+ sram_write(tp, 0x8068, 0x2417); -+ sram_write(tp, 0x806e, 0x2417); -+ sram_write(tp, 0x8074, 0x2417); -+ sram_write(tp, 0x807a, 0x2417); -+ -+ /* XG PLL */ -+ data = ocp_reg_read(tp, 0xbf84); -+ data &= ~0xe000; -+ data |= 0xa000; -+ ocp_reg_write(tp, 0xbf84, data); -+ break; -+ default: -+ break; -+ } -+ -+ if (rtl_phy_patch_request(tp, true, true)) -+ return; -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); -+ ocp_data |= EEE_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); -+ -+ data = ocp_reg_read(tp, OCP_DOWN_SPEED); -+ data &= ~(EN_EEE_100 | EN_EEE_1000); -+ data |= EN_10M_CLKDIV; -+ ocp_reg_write(tp, OCP_DOWN_SPEED, data); -+ tp->ups_info._10m_ckdiv = true; -+ tp->ups_info.eee_plloff_100 = false; -+ tp->ups_info.eee_plloff_giga = false; -+ -+ data = ocp_reg_read(tp, OCP_POWER_CFG); -+ data &= ~EEE_CLKDIV_EN; -+ ocp_reg_write(tp, OCP_POWER_CFG, data); -+ tp->ups_info.eee_ckdiv = false; -+ -+ rtl_phy_patch_request(tp, false, true); -+ -+ rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); -+ -+ data = ocp_reg_read(tp, 0xa428); -+ data &= ~BIT(9); -+ ocp_reg_write(tp, 0xa428, data); -+ data = ocp_reg_read(tp, 0xa5ea); -+ data &= ~BIT(0); -+ ocp_reg_write(tp, 0xa5ea, data); -+ tp->ups_info.lite_mode = 0; -+ -+ if (tp->eee_en) -+ rtl_eee_enable(tp, true); -+ -+ r8153_aldps_en(tp, true); -+ r8152b_enable_fc(tp); -+ r8153_u2p3en(tp, true); -+ -+ set_bit(PHY_RESET, &tp->flags); -+} -+ -+static void r8156_init(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ u16 data; -+ int i; -+ -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return; -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); -+ ocp_data &= ~EN_ALL_SPEED; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); -+ -+ ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); -+ ocp_data |= BYPASS_MAC_RESET; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); -+ -+ r8153b_u1u2en(tp, false); -+ -+ for (i = 0; i < 500; i++) { -+ if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & -+ AUTOLOAD_DONE) -+ break; -+ -+ msleep(20); -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return; -+ } -+ -+ data = r8153_phy_status(tp, 0); -+ if (data == PHY_STAT_EXT_INIT) { -+ data = ocp_reg_read(tp, 0xa468); -+ data &= ~(BIT(3) | BIT(1)); -+ ocp_reg_write(tp, 0xa468, data); -+ } -+ -+ data = r8152_mdio_read(tp, MII_BMCR); -+ if (data & BMCR_PDOWN) { -+ data &= ~BMCR_PDOWN; -+ r8152_mdio_write(tp, MII_BMCR, data); -+ } -+ -+ data = r8153_phy_status(tp, PHY_STAT_LAN_ON); -+ WARN_ON_ONCE(data != PHY_STAT_LAN_ON); -+ -+ r8153_u2p3en(tp, false); -+ -+ /* MSC timer = 0xfff * 8ms = 32760 ms */ -+ ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); -+ -+ /* U1/U2/L1 idle timer. 500 us */ -+ ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); -+ -+ r8153b_power_cut_en(tp, false); -+ r8156_ups_en(tp, false); -+ r8153_queue_wake(tp, false); -+ rtl_runtime_suspend_enable(tp, false); -+ -+ if (tp->udev->speed >= USB_SPEED_SUPER) -+ r8153b_u1u2en(tp, true); -+ -+ usb_enable_lpm(tp->udev); -+ -+ r8156_mac_clk_spd(tp, true); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); -+ ocp_data &= ~PLA_MCU_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); -+ if (rtl8152_get_speed(tp) & LINK_STATUS) -+ ocp_data |= CUR_LINK_OK; -+ else -+ ocp_data &= ~CUR_LINK_OK; -+ ocp_data |= POLL_LINK_CHG; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); -+ -+ set_bit(GREEN_ETHERNET, &tp->flags); -+ -+ /* rx aggregation */ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); -+ ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); -+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG); -+ ocp_data |= ACT_ODMA; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); -+ -+ rtl_tally_reset(tp); -+ -+ tp->coalesce = 15000; /* 15 us */ -+} -+ -+static void r8156b_init(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ u16 data; -+ int i; -+ -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return; -+ -+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); -+ ocp_data &= ~EN_ALL_SPEED; -+ ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); -+ -+ ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); -+ ocp_data |= BYPASS_MAC_RESET; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); -+ ocp_data |= RX_DETECT8; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); -+ -+ r8153b_u1u2en(tp, false); -+ -+ switch (tp->version) { -+ case RTL_VER_13: -+ case RTL_VER_15: -+ r8156b_wait_loading_flash(tp); -+ break; -+ default: -+ break; -+ } -+ -+ for (i = 0; i < 500; i++) { -+ if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & -+ AUTOLOAD_DONE) -+ break; -+ -+ msleep(20); -+ if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ return; -+ } -+ -+ data = r8153_phy_status(tp, 0); -+ if (data == PHY_STAT_EXT_INIT) { -+ data = ocp_reg_read(tp, 0xa468); -+ data &= ~(BIT(3) | BIT(1)); -+ ocp_reg_write(tp, 0xa468, data); -+ -+ data = ocp_reg_read(tp, 0xa466); -+ data &= ~BIT(0); -+ ocp_reg_write(tp, 0xa466, data); -+ } -+ -+ data = r8152_mdio_read(tp, MII_BMCR); -+ if (data & BMCR_PDOWN) { -+ data &= ~BMCR_PDOWN; -+ r8152_mdio_write(tp, MII_BMCR, data); -+ } -+ -+ data = r8153_phy_status(tp, PHY_STAT_LAN_ON); -+ -+ r8153_u2p3en(tp, false); -+ -+ /* MSC timer = 0xfff * 8ms = 32760 ms */ -+ ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); -+ -+ /* U1/U2/L1 idle timer. 500 us */ -+ ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); -+ -+ r8153b_power_cut_en(tp, false); -+ r8156_ups_en(tp, false); -+ r8153_queue_wake(tp, false); -+ rtl_runtime_suspend_enable(tp, false); -+ -+ if (tp->udev->speed >= USB_SPEED_SUPER) -+ r8153b_u1u2en(tp, true); -+ -+ usb_enable_lpm(tp->udev); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR); -+ ocp_data &= ~SLOT_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); -+ ocp_data |= FLOW_CTRL_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); -+ -+ /* enable fc timer and set timer to 600 ms. */ -+ ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, -+ CTRL_TIMER_EN | (600 / 8)); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); -+ if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) -+ ocp_data |= FLOW_CTRL_PATCH_2; -+ ocp_data &= ~AUTO_SPEEDUP; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); -+ ocp_data |= FC_PATCH_TASK; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); -+ -+ r8156_mac_clk_spd(tp, true); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); -+ ocp_data &= ~PLA_MCU_SPDWN_EN; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); -+ if (rtl8152_get_speed(tp) & LINK_STATUS) -+ ocp_data |= CUR_LINK_OK; -+ else -+ ocp_data &= ~CUR_LINK_OK; -+ ocp_data |= POLL_LINK_CHG; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); -+ -+ set_bit(GREEN_ETHERNET, &tp->flags); -+ -+ /* rx aggregation */ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); -+ ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); -+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); -+ -+ rtl_tally_reset(tp); -+ -+ tp->coalesce = 15000; /* 15 us */ -+} -+ - static int rtl8152_pre_reset(struct usb_interface *intf) - { - struct r8152 *tp = usb_get_intfdata(intf); -@@ -5994,6 +7926,22 @@ int rtl8152_get_link_ksettings(struct ne - - mii_ethtool_get_link_ksettings(&tp->mii, cmd); - -+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, -+ cmd->link_modes.supported, tp->support_2500full); -+ -+ if (tp->support_2500full) { -+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, -+ cmd->link_modes.advertising, -+ ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G); -+ -+ linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, -+ cmd->link_modes.lp_advertising, -+ ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G); -+ -+ if (is_speed_2500(rtl8152_get_speed(tp))) -+ cmd->base.speed = SPEED_2500; -+ } -+ - mutex_unlock(&tp->control); - - usb_autopm_put_interface(tp->intf); -@@ -6037,6 +7985,10 @@ static int rtl8152_set_link_ksettings(st - cmd->link_modes.advertising)) - advertising |= RTL_ADVERTISED_1000_FULL; - -+ if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, -+ cmd->link_modes.advertising)) -+ advertising |= RTL_ADVERTISED_2500_FULL; -+ - mutex_lock(&tp->control); - - ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, -@@ -6626,6 +8578,67 @@ static int rtl_ops_init(struct r8152 *tp - tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; - break; - -+ case RTL_VER_11: -+ tp->eee_en = true; -+ tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; -+ fallthrough; -+ case RTL_VER_10: -+ ops->init = r8156_init; -+ ops->enable = rtl8156_enable; -+ ops->disable = rtl8153_disable; -+ ops->up = rtl8156_up; -+ ops->down = rtl8156_down; -+ ops->unload = rtl8153_unload; -+ ops->eee_get = r8153_get_eee; -+ ops->eee_set = r8152_set_eee; -+ ops->in_nway = rtl8153_in_nway; -+ ops->hw_phy_cfg = r8156_hw_phy_cfg; -+ ops->autosuspend_en = rtl8156_runtime_enable; -+ ops->change_mtu = rtl8156_change_mtu; -+ tp->rx_buf_sz = 48 * 1024; -+ tp->support_2500full = 1; -+ break; -+ -+ case RTL_VER_12: -+ case RTL_VER_13: -+ tp->support_2500full = 1; -+ fallthrough; -+ case RTL_VER_15: -+ tp->eee_en = true; -+ tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; -+ ops->init = r8156b_init; -+ ops->enable = rtl8156b_enable; -+ ops->disable = rtl8153_disable; -+ ops->up = rtl8156_up; -+ ops->down = rtl8156_down; -+ ops->unload = rtl8153_unload; -+ ops->eee_get = r8153_get_eee; -+ ops->eee_set = r8152_set_eee; -+ ops->in_nway = rtl8153_in_nway; -+ ops->hw_phy_cfg = r8156b_hw_phy_cfg; -+ ops->autosuspend_en = rtl8156_runtime_enable; -+ ops->change_mtu = rtl8156_change_mtu; -+ tp->rx_buf_sz = 48 * 1024; -+ break; -+ -+ case RTL_VER_14: -+ ops->init = r8153c_init; -+ ops->enable = rtl8153_enable; -+ ops->disable = rtl8153_disable; -+ ops->up = rtl8153c_up; -+ ops->down = rtl8153b_down; -+ ops->unload = rtl8153_unload; -+ ops->eee_get = r8153_get_eee; -+ ops->eee_set = r8152_set_eee; -+ ops->in_nway = rtl8153_in_nway; -+ ops->hw_phy_cfg = r8153c_hw_phy_cfg; -+ ops->autosuspend_en = rtl8153c_runtime_enable; -+ ops->change_mtu = rtl8153c_change_mtu; -+ tp->rx_buf_sz = 32 * 1024; -+ tp->eee_en = true; -+ tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; -+ break; -+ - default: - ret = -ENODEV; - dev_err(&tp->intf->dev, "Unknown Device\n"); -@@ -6639,11 +8652,13 @@ static int rtl_ops_init(struct r8152 *tp - #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw" - #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw" - #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw" -+#define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw" - - MODULE_FIRMWARE(FIRMWARE_8153A_2); - MODULE_FIRMWARE(FIRMWARE_8153A_3); - MODULE_FIRMWARE(FIRMWARE_8153A_4); - MODULE_FIRMWARE(FIRMWARE_8153B_2); -+MODULE_FIRMWARE(FIRMWARE_8153C_1); - - static int rtl_fw_init(struct r8152 *tp) - { -@@ -6669,6 +8684,11 @@ static int rtl_fw_init(struct r8152 *tp) - rtl_fw->pre_fw = r8153b_pre_firmware_1; - rtl_fw->post_fw = r8153b_post_firmware_1; - break; -+ case RTL_VER_14: -+ rtl_fw->fw_name = FIRMWARE_8153C_1; -+ rtl_fw->pre_fw = r8153b_pre_firmware_1; -+ rtl_fw->post_fw = r8153c_post_firmware_1; -+ break; - default: - break; - } -@@ -6724,6 +8744,27 @@ u8 rtl8152_get_version(struct usb_interf - case 0x6010: - version = RTL_VER_09; - break; -+ case 0x7010: -+ version = RTL_TEST_01; -+ break; -+ case 0x7020: -+ version = RTL_VER_10; -+ break; -+ case 0x7030: -+ version = RTL_VER_11; -+ break; -+ case 0x7400: -+ version = RTL_VER_12; -+ break; -+ case 0x7410: -+ version = RTL_VER_13; -+ break; -+ case 0x6400: -+ version = RTL_VER_14; -+ break; -+ case 0x7420: -+ version = RTL_VER_15; -+ break; - default: - version = RTL_VER_UNKNOWN; - dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); -@@ -6836,12 +8877,29 @@ static int rtl8152_probe(struct usb_inte - /* MTU range: 68 - 1500 or 9194 */ - netdev->min_mtu = ETH_MIN_MTU; - switch (tp->version) { -+ case RTL_VER_03: -+ case RTL_VER_04: -+ case RTL_VER_05: -+ case RTL_VER_06: -+ case RTL_VER_08: -+ case RTL_VER_09: -+ case RTL_VER_14: -+ netdev->max_mtu = size_to_mtu(9 * 1024); -+ break; -+ case RTL_VER_10: -+ case RTL_VER_11: -+ netdev->max_mtu = size_to_mtu(15 * 1024); -+ break; -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_15: -+ netdev->max_mtu = size_to_mtu(16 * 1024); -+ break; - case RTL_VER_01: - case RTL_VER_02: -- netdev->max_mtu = ETH_DATA_LEN; -- break; -+ case RTL_VER_07: - default: -- netdev->max_mtu = size_to_mtu(9 * 1024); -+ netdev->max_mtu = ETH_DATA_LEN; - break; - } - -@@ -6857,7 +8915,13 @@ static int rtl8152_probe(struct usb_inte - tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | - RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; - if (tp->mii.supports_gmii) { -- tp->speed = SPEED_1000; -+ if (tp->support_2500full && -+ tp->udev->speed >= USB_SPEED_SUPER) { -+ tp->speed = SPEED_2500; -+ tp->advertising |= RTL_ADVERTISED_2500_FULL; -+ } else { -+ tp->speed = SPEED_1000; -+ } - tp->advertising |= RTL_ADVERTISED_1000_FULL; - } - tp->duplex = DUPLEX_FULL; -@@ -6881,7 +8945,11 @@ static int rtl8152_probe(struct usb_inte - set_ethernet_addr(tp); - - usb_set_intfdata(intf, tp); -- netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); -+ -+ if (tp->support_2500full) -+ netif_napi_add(netdev, &tp->napi, r8152_poll, 256); -+ else -+ netif_napi_add(netdev, &tp->napi, r8152_poll, 64); - - ret = register_netdev(netdev); - if (ret != 0) { -@@ -6917,7 +8985,8 @@ static void rtl8152_disconnect(struct us - unregister_netdev(tp->netdev); - tasklet_kill(&tp->tx_tl); - cancel_delayed_work_sync(&tp->hw_phy_work); -- tp->rtl_ops.unload(tp); -+ if (tp->rtl_ops.unload) -+ tp->rtl_ops.unload(tp); - rtl8152_release_firmware(tp); - free_netdev(tp->netdev); - } -@@ -6937,13 +9006,28 @@ static void rtl8152_disconnect(struct us - .idProduct = (prod), \ - .bInterfaceClass = USB_CLASS_COMM, \ - .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ -+ .bInterfaceProtocol = USB_CDC_PROTO_NONE \ -+}, \ -+{ \ -+ .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ -+ USB_DEVICE_ID_MATCH_DEVICE, \ -+ .idVendor = (vend), \ -+ .idProduct = (prod), \ -+ .bInterfaceClass = USB_CLASS_COMM, \ -+ .bInterfaceSubClass = USB_CDC_SUBCLASS_NCM, \ - .bInterfaceProtocol = USB_CDC_PROTO_NONE - - /* table of devices that work with this driver */ - static const struct usb_device_id rtl8152_table[] = { -+ /* Realtek */ - {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, -+ {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053)}, - {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, - {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, -+ {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155)}, -+ {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156)}, -+ -+ /* Microsoft */ - {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, - {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, - {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)}, diff --git a/target/linux/generic/backport-5.10/794-v5.13-r8152-support-PHY-firmware-for-RTL8156-series.patch b/target/linux/generic/backport-5.10/794-v5.13-r8152-support-PHY-firmware-for-RTL8156-series.patch deleted file mode 100644 index 40dae54f8c..0000000000 --- a/target/linux/generic/backport-5.10/794-v5.13-r8152-support-PHY-firmware-for-RTL8156-series.patch +++ /dev/null @@ -1,691 +0,0 @@ -From ca09589a72a0aa17389754fb75a5cd1a5d46818f Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 16 Apr 2021 16:04:36 +0800 -Subject: [PATCH] r8152: support PHY firmware for RTL8156 series - -commit 4a51b0e8a0143b0e83d51d9c58c6416c3818a9f2 upstream. - -Support new firmware type and method for RTL8156 series. - -Signed-off-by: Hayes Wang -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 563 +++++++++++++++++++++++++++++++++++++++- - 1 file changed, 561 insertions(+), 2 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -974,8 +974,60 @@ enum rtl8152_fw_flags { - FW_FLAGS_START, - FW_FLAGS_STOP, - FW_FLAGS_NC, -+ FW_FLAGS_NC1, -+ FW_FLAGS_NC2, -+ FW_FLAGS_UC2, -+ FW_FLAGS_UC, -+ FW_FLAGS_SPEED_UP, -+ FW_FLAGS_VER, - }; - -+enum rtl8152_fw_fixup_cmd { -+ FW_FIXUP_AND = 0, -+ FW_FIXUP_OR, -+ FW_FIXUP_NOT, -+ FW_FIXUP_XOR, -+}; -+ -+struct fw_phy_set { -+ __le16 addr; -+ __le16 data; -+} __packed; -+ -+struct fw_phy_speed_up { -+ struct fw_block blk_hdr; -+ __le16 fw_offset; -+ __le16 version; -+ __le16 fw_reg; -+ __le16 reserved; -+ char info[]; -+} __packed; -+ -+struct fw_phy_ver { -+ struct fw_block blk_hdr; -+ struct fw_phy_set ver; -+ __le32 reserved; -+} __packed; -+ -+struct fw_phy_fixup { -+ struct fw_block blk_hdr; -+ struct fw_phy_set setting; -+ __le16 bit_cmd; -+ __le16 reserved; -+} __packed; -+ -+struct fw_phy_union { -+ struct fw_block blk_hdr; -+ __le16 fw_offset; -+ __le16 fw_reg; -+ struct fw_phy_set pre_set[2]; -+ struct fw_phy_set bp[8]; -+ struct fw_phy_set bp_en; -+ u8 pre_num; -+ u8 bp_num; -+ char info[]; -+} __packed; -+ - /** - * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB. - * The layout of the firmware block is: -@@ -1080,6 +1132,15 @@ enum rtl_fw_type { - RTL_FW_PHY_START, - RTL_FW_PHY_STOP, - RTL_FW_PHY_NC, -+ RTL_FW_PHY_FIXUP, -+ RTL_FW_PHY_UNION_NC, -+ RTL_FW_PHY_UNION_NC1, -+ RTL_FW_PHY_UNION_NC2, -+ RTL_FW_PHY_UNION_UC2, -+ RTL_FW_PHY_UNION_UC, -+ RTL_FW_PHY_UNION_MISC, -+ RTL_FW_PHY_SPEED_UP, -+ RTL_FW_PHY_VER, - }; - - enum rtl_version { -@@ -4001,6 +4062,162 @@ static int rtl_post_ram_code(struct r815 - return 0; - } - -+static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy) -+{ -+ u16 fw_offset; -+ u32 length; -+ bool rc = false; -+ -+ switch (tp->version) { -+ case RTL_VER_01: -+ case RTL_VER_02: -+ case RTL_VER_03: -+ case RTL_VER_04: -+ case RTL_VER_05: -+ case RTL_VER_06: -+ case RTL_VER_07: -+ case RTL_VER_08: -+ case RTL_VER_09: -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_14: -+ goto out; -+ case RTL_VER_13: -+ case RTL_VER_15: -+ default: -+ break; -+ } -+ -+ fw_offset = __le16_to_cpu(phy->fw_offset); -+ length = __le32_to_cpu(phy->blk_hdr.length); -+ if (fw_offset < sizeof(*phy) || length <= fw_offset) { -+ dev_err(&tp->intf->dev, "invalid fw_offset\n"); -+ goto out; -+ } -+ -+ length -= fw_offset; -+ if (length & 3) { -+ dev_err(&tp->intf->dev, "invalid block length\n"); -+ goto out; -+ } -+ -+ if (__le16_to_cpu(phy->fw_reg) != 0x9A00) { -+ dev_err(&tp->intf->dev, "invalid register to load firmware\n"); -+ goto out; -+ } -+ -+ rc = true; -+out: -+ return rc; -+} -+ -+static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver) -+{ -+ bool rc = false; -+ -+ switch (tp->version) { -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_15: -+ break; -+ default: -+ goto out; -+ } -+ -+ if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) { -+ dev_err(&tp->intf->dev, "invalid block length\n"); -+ goto out; -+ } -+ -+ if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) { -+ dev_err(&tp->intf->dev, "invalid phy ver addr\n"); -+ goto out; -+ } -+ -+ rc = true; -+out: -+ return rc; -+} -+ -+static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix) -+{ -+ bool rc = false; -+ -+ switch (tp->version) { -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_15: -+ break; -+ default: -+ goto out; -+ } -+ -+ if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) { -+ dev_err(&tp->intf->dev, "invalid block length\n"); -+ goto out; -+ } -+ -+ if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD || -+ __le16_to_cpu(fix->setting.data) != BIT(7)) { -+ dev_err(&tp->intf->dev, "invalid phy fixup\n"); -+ goto out; -+ } -+ -+ rc = true; -+out: -+ return rc; -+} -+ -+static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy) -+{ -+ u16 fw_offset; -+ u32 length; -+ bool rc = false; -+ -+ switch (tp->version) { -+ case RTL_VER_10: -+ case RTL_VER_11: -+ case RTL_VER_12: -+ case RTL_VER_13: -+ case RTL_VER_15: -+ break; -+ default: -+ goto out; -+ } -+ -+ fw_offset = __le16_to_cpu(phy->fw_offset); -+ length = __le32_to_cpu(phy->blk_hdr.length); -+ if (fw_offset < sizeof(*phy) || length <= fw_offset) { -+ dev_err(&tp->intf->dev, "invalid fw_offset\n"); -+ goto out; -+ } -+ -+ length -= fw_offset; -+ if (length & 1) { -+ dev_err(&tp->intf->dev, "invalid block length\n"); -+ goto out; -+ } -+ -+ if (phy->pre_num > 2) { -+ dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num); -+ goto out; -+ } -+ -+ if (phy->bp_num > 8) { -+ dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num); -+ goto out; -+ } -+ -+ rc = true; -+out: -+ return rc; -+} -+ - static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy) - { - u32 length; -@@ -4321,6 +4538,10 @@ static long rtl8152_check_firmware(struc - case RTL_FW_PHY_START: - if (test_bit(FW_FLAGS_START, &fw_flags) || - test_bit(FW_FLAGS_NC, &fw_flags) || -+ test_bit(FW_FLAGS_NC1, &fw_flags) || -+ test_bit(FW_FLAGS_NC2, &fw_flags) || -+ test_bit(FW_FLAGS_UC2, &fw_flags) || -+ test_bit(FW_FLAGS_UC, &fw_flags) || - test_bit(FW_FLAGS_STOP, &fw_flags)) { - dev_err(&tp->intf->dev, - "check PHY_START fail\n"); -@@ -4369,7 +4590,153 @@ static long rtl8152_check_firmware(struc - goto fail; - } - __set_bit(FW_FLAGS_NC, &fw_flags); -+ break; -+ case RTL_FW_PHY_UNION_NC: -+ if (!test_bit(FW_FLAGS_START, &fw_flags) || -+ test_bit(FW_FLAGS_NC1, &fw_flags) || -+ test_bit(FW_FLAGS_NC2, &fw_flags) || -+ test_bit(FW_FLAGS_UC2, &fw_flags) || -+ test_bit(FW_FLAGS_UC, &fw_flags) || -+ test_bit(FW_FLAGS_STOP, &fw_flags)) { -+ dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n"); -+ goto fail; -+ } -+ -+ if (test_bit(FW_FLAGS_NC, &fw_flags)) { -+ dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n"); -+ goto fail; -+ } - -+ if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { -+ dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n"); -+ goto fail; -+ } -+ __set_bit(FW_FLAGS_NC, &fw_flags); -+ break; -+ case RTL_FW_PHY_UNION_NC1: -+ if (!test_bit(FW_FLAGS_START, &fw_flags) || -+ test_bit(FW_FLAGS_NC2, &fw_flags) || -+ test_bit(FW_FLAGS_UC2, &fw_flags) || -+ test_bit(FW_FLAGS_UC, &fw_flags) || -+ test_bit(FW_FLAGS_STOP, &fw_flags)) { -+ dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n"); -+ goto fail; -+ } -+ -+ if (test_bit(FW_FLAGS_NC1, &fw_flags)) { -+ dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n"); -+ goto fail; -+ } -+ -+ if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { -+ dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n"); -+ goto fail; -+ } -+ __set_bit(FW_FLAGS_NC1, &fw_flags); -+ break; -+ case RTL_FW_PHY_UNION_NC2: -+ if (!test_bit(FW_FLAGS_START, &fw_flags) || -+ test_bit(FW_FLAGS_UC2, &fw_flags) || -+ test_bit(FW_FLAGS_UC, &fw_flags) || -+ test_bit(FW_FLAGS_STOP, &fw_flags)) { -+ dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n"); -+ goto fail; -+ } -+ -+ if (test_bit(FW_FLAGS_NC2, &fw_flags)) { -+ dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n"); -+ goto fail; -+ } -+ -+ if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { -+ dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n"); -+ goto fail; -+ } -+ __set_bit(FW_FLAGS_NC2, &fw_flags); -+ break; -+ case RTL_FW_PHY_UNION_UC2: -+ if (!test_bit(FW_FLAGS_START, &fw_flags) || -+ test_bit(FW_FLAGS_UC, &fw_flags) || -+ test_bit(FW_FLAGS_STOP, &fw_flags)) { -+ dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n"); -+ goto fail; -+ } -+ -+ if (test_bit(FW_FLAGS_UC2, &fw_flags)) { -+ dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n"); -+ goto fail; -+ } -+ -+ if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { -+ dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n"); -+ goto fail; -+ } -+ __set_bit(FW_FLAGS_UC2, &fw_flags); -+ break; -+ case RTL_FW_PHY_UNION_UC: -+ if (!test_bit(FW_FLAGS_START, &fw_flags) || -+ test_bit(FW_FLAGS_STOP, &fw_flags)) { -+ dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n"); -+ goto fail; -+ } -+ -+ if (test_bit(FW_FLAGS_UC, &fw_flags)) { -+ dev_err(&tp->intf->dev, "multiple PHY UC encountered\n"); -+ goto fail; -+ } -+ -+ if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { -+ dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n"); -+ goto fail; -+ } -+ __set_bit(FW_FLAGS_UC, &fw_flags); -+ break; -+ case RTL_FW_PHY_UNION_MISC: -+ if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { -+ dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n"); -+ goto fail; -+ } -+ break; -+ case RTL_FW_PHY_FIXUP: -+ if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) { -+ dev_err(&tp->intf->dev, "check PHY fixup failed\n"); -+ goto fail; -+ } -+ break; -+ case RTL_FW_PHY_SPEED_UP: -+ if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) { -+ dev_err(&tp->intf->dev, "multiple PHY firmware encountered"); -+ goto fail; -+ } -+ -+ if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) { -+ dev_err(&tp->intf->dev, "check PHY speed up failed\n"); -+ goto fail; -+ } -+ __set_bit(FW_FLAGS_SPEED_UP, &fw_flags); -+ break; -+ case RTL_FW_PHY_VER: -+ if (test_bit(FW_FLAGS_START, &fw_flags) || -+ test_bit(FW_FLAGS_NC, &fw_flags) || -+ test_bit(FW_FLAGS_NC1, &fw_flags) || -+ test_bit(FW_FLAGS_NC2, &fw_flags) || -+ test_bit(FW_FLAGS_UC2, &fw_flags) || -+ test_bit(FW_FLAGS_UC, &fw_flags) || -+ test_bit(FW_FLAGS_STOP, &fw_flags)) { -+ dev_err(&tp->intf->dev, "Invalid order to set PHY version\n"); -+ goto fail; -+ } -+ -+ if (test_bit(FW_FLAGS_VER, &fw_flags)) { -+ dev_err(&tp->intf->dev, "multiple PHY version encountered"); -+ goto fail; -+ } -+ -+ if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) { -+ dev_err(&tp->intf->dev, "check PHY version failed\n"); -+ goto fail; -+ } -+ __set_bit(FW_FLAGS_VER, &fw_flags); - break; - default: - dev_warn(&tp->intf->dev, "Unknown type %u is found\n", -@@ -4392,6 +4759,143 @@ fail: - return ret; - } - -+static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait) -+{ -+ u32 len; -+ u8 *data; -+ -+ if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) { -+ dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); -+ return; -+ } -+ -+ len = __le32_to_cpu(phy->blk_hdr.length); -+ len -= __le16_to_cpu(phy->fw_offset); -+ data = (u8 *)phy + __le16_to_cpu(phy->fw_offset); -+ -+ if (rtl_phy_patch_request(tp, true, wait)) -+ return; -+ -+ while (len) { -+ u32 ocp_data, size; -+ int i; -+ -+ if (len < 2048) -+ size = len; -+ else -+ size = 2048; -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL); -+ ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data); -+ -+ generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB); -+ -+ data += size; -+ len -= size; -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); -+ ocp_data |= POL_GPHY_PATCH; -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data); -+ -+ for (i = 0; i < 1000; i++) { -+ if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH)) -+ break; -+ } -+ -+ if (i == 1000) { -+ dev_err(&tp->intf->dev, "ram code speedup mode timeout\n"); -+ return; -+ } -+ } -+ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base); -+ rtl_phy_patch_request(tp, false, wait); -+ -+ if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version)) -+ dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); -+ else -+ dev_err(&tp->intf->dev, "ram code speedup mode fail\n"); -+} -+ -+static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver) -+{ -+ u16 ver_addr, ver; -+ -+ ver_addr = __le16_to_cpu(phy_ver->ver.addr); -+ ver = __le16_to_cpu(phy_ver->ver.data); -+ -+ if (sram_read(tp, ver_addr) >= ver) { -+ dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); -+ return 0; -+ } -+ -+ sram_write(tp, ver_addr, ver); -+ -+ dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver); -+ -+ return ver; -+} -+ -+static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix) -+{ -+ u16 addr, data; -+ -+ addr = __le16_to_cpu(fix->setting.addr); -+ data = ocp_reg_read(tp, addr); -+ -+ switch (__le16_to_cpu(fix->bit_cmd)) { -+ case FW_FIXUP_AND: -+ data &= __le16_to_cpu(fix->setting.data); -+ break; -+ case FW_FIXUP_OR: -+ data |= __le16_to_cpu(fix->setting.data); -+ break; -+ case FW_FIXUP_NOT: -+ data &= ~__le16_to_cpu(fix->setting.data); -+ break; -+ case FW_FIXUP_XOR: -+ data ^= __le16_to_cpu(fix->setting.data); -+ break; -+ default: -+ return; -+ } -+ -+ ocp_reg_write(tp, addr, data); -+ -+ dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data); -+} -+ -+static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy) -+{ -+ __le16 *data; -+ u32 length; -+ int i, num; -+ -+ num = phy->pre_num; -+ for (i = 0; i < num; i++) -+ sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr), -+ __le16_to_cpu(phy->pre_set[i].data)); -+ -+ length = __le32_to_cpu(phy->blk_hdr.length); -+ length -= __le16_to_cpu(phy->fw_offset); -+ num = length / 2; -+ data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset)); -+ -+ ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg)); -+ for (i = 0; i < num; i++) -+ ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i])); -+ -+ num = phy->bp_num; -+ for (i = 0; i < num; i++) -+ sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data)); -+ -+ if (phy->bp_num && phy->bp_en.addr) -+ sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data)); -+ -+ dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); -+} -+ - static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy) - { - u16 mode_reg, bp_index; -@@ -4445,6 +4949,12 @@ static void rtl8152_fw_mac_apply(struct - return; - } - -+ fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg); -+ if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) { -+ dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB"); -+ return; -+ } -+ - rtl_clear_bp(tp, type); - - /* Enable backup/restore of MACDBG. This is required after clearing PLA -@@ -4480,7 +4990,6 @@ static void rtl8152_fw_mac_apply(struct - ocp_write_word(tp, type, bp_en_addr, - __le16_to_cpu(mac->bp_en_value)); - -- fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg); - if (fw_ver_reg) - ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg, - mac->fw_ver_data); -@@ -4495,7 +5004,7 @@ static void rtl8152_apply_firmware(struc - struct fw_header *fw_hdr; - struct fw_phy_patch_key *key; - u16 key_addr = 0; -- int i; -+ int i, patch_phy = 1; - - if (IS_ERR_OR_NULL(rtl_fw->fw)) - return; -@@ -4517,17 +5026,40 @@ static void rtl8152_apply_firmware(struc - rtl8152_fw_mac_apply(tp, (struct fw_mac *)block); - break; - case RTL_FW_PHY_START: -+ if (!patch_phy) -+ break; - key = (struct fw_phy_patch_key *)block; - key_addr = __le16_to_cpu(key->key_reg); - rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut); - break; - case RTL_FW_PHY_STOP: -+ if (!patch_phy) -+ break; - WARN_ON(!key_addr); - rtl_post_ram_code(tp, key_addr, !power_cut); - break; - case RTL_FW_PHY_NC: - rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block); - break; -+ case RTL_FW_PHY_VER: -+ patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block); -+ break; -+ case RTL_FW_PHY_UNION_NC: -+ case RTL_FW_PHY_UNION_NC1: -+ case RTL_FW_PHY_UNION_NC2: -+ case RTL_FW_PHY_UNION_UC2: -+ case RTL_FW_PHY_UNION_UC: -+ case RTL_FW_PHY_UNION_MISC: -+ if (patch_phy) -+ rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block); -+ break; -+ case RTL_FW_PHY_FIXUP: -+ if (patch_phy) -+ rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block); -+ break; -+ case RTL_FW_PHY_SPEED_UP: -+ rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut); -+ break; - default: - break; - } -@@ -5035,6 +5567,21 @@ static int r8153c_post_firmware_1(struct - return 0; - } - -+static int r8156a_post_firmware_1(struct r8152 *tp) -+{ -+ u32 ocp_data; -+ -+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); -+ ocp_data |= FW_IP_RESET_EN; -+ ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); -+ -+ /* Modify U3PHY parameter for compatibility issue */ -+ ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e); -+ ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9); -+ -+ return 0; -+} -+ - static void r8153_aldps_en(struct r8152 *tp, bool enable) - { - u16 data; -@@ -8653,12 +9200,16 @@ static int rtl_ops_init(struct r8152 *tp - #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw" - #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw" - #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw" -+#define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw" -+#define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw" - - MODULE_FIRMWARE(FIRMWARE_8153A_2); - MODULE_FIRMWARE(FIRMWARE_8153A_3); - MODULE_FIRMWARE(FIRMWARE_8153A_4); - MODULE_FIRMWARE(FIRMWARE_8153B_2); - MODULE_FIRMWARE(FIRMWARE_8153C_1); -+MODULE_FIRMWARE(FIRMWARE_8156A_2); -+MODULE_FIRMWARE(FIRMWARE_8156B_2); - - static int rtl_fw_init(struct r8152 *tp) - { -@@ -8684,6 +9235,14 @@ static int rtl_fw_init(struct r8152 *tp) - rtl_fw->pre_fw = r8153b_pre_firmware_1; - rtl_fw->post_fw = r8153b_post_firmware_1; - break; -+ case RTL_VER_11: -+ rtl_fw->fw_name = FIRMWARE_8156A_2; -+ rtl_fw->post_fw = r8156a_post_firmware_1; -+ break; -+ case RTL_VER_13: -+ case RTL_VER_15: -+ rtl_fw->fw_name = FIRMWARE_8156B_2; -+ break; - case RTL_VER_14: - rtl_fw->fw_name = FIRMWARE_8153C_1; - rtl_fw->pre_fw = r8153b_pre_firmware_1; diff --git a/target/linux/generic/backport-5.10/795-v5.13-r8152-search-the-configuration-of-vendor-mode.patch b/target/linux/generic/backport-5.10/795-v5.13-r8152-search-the-configuration-of-vendor-mode.patch deleted file mode 100644 index 751ff3d30c..0000000000 --- a/target/linux/generic/backport-5.10/795-v5.13-r8152-search-the-configuration-of-vendor-mode.patch +++ /dev/null @@ -1,79 +0,0 @@ -From 579f58dd2819910354753bc5489fc1588fe9cfe2 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Fri, 16 Apr 2021 16:04:37 +0800 -Subject: [PATCH] r8152: search the configuration of vendor mode - -commit c2198943e33b100ed21dfb636c8fa6baef841e9d upstream. - -The vendor mode is not always at config #1, so it is necessary to -set the correct configuration number. - -Signed-off-by: Hayes Wang -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 39 +++++++++++++++++++++++++++++++++++---- - 1 file changed, 35 insertions(+), 4 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -29,7 +29,7 @@ - #include - - /* Information for net-next */ --#define NETNEXT_VERSION "11" -+#define NETNEXT_VERSION "12" - - /* Information for net */ - #define NET_VERSION "11" -@@ -8110,6 +8110,39 @@ static void r8156b_init(struct r8152 *tp - tp->coalesce = 15000; /* 15 us */ - } - -+static bool rtl_vendor_mode(struct usb_interface *intf) -+{ -+ struct usb_host_interface *alt = intf->cur_altsetting; -+ struct usb_device *udev; -+ struct usb_host_config *c; -+ int i, num_configs; -+ -+ if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC) -+ return true; -+ -+ /* The vendor mode is not always config #1, so to find it out. */ -+ udev = interface_to_usbdev(intf); -+ c = udev->config; -+ num_configs = udev->descriptor.bNumConfigurations; -+ for (i = 0; i < num_configs; (i++, c++)) { -+ struct usb_interface_descriptor *desc = NULL; -+ -+ if (c->desc.bNumInterfaces > 0) -+ desc = &c->intf_cache[0]->altsetting->desc; -+ else -+ continue; -+ -+ if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) { -+ usb_driver_set_configuration(udev, c->desc.bConfigurationValue); -+ break; -+ } -+ } -+ -+ WARN_ON_ONCE(i == num_configs); -+ -+ return false; -+} -+ - static int rtl8152_pre_reset(struct usb_interface *intf) - { - struct r8152 *tp = usb_get_intfdata(intf); -@@ -9348,10 +9381,8 @@ static int rtl8152_probe(struct usb_inte - if (version == RTL_VER_UNKNOWN) - return -ENODEV; - -- if (udev->actconfig->desc.bConfigurationValue != 1) { -- usb_driver_set_configuration(udev, 1); -+ if (!rtl_vendor_mode(intf)) - return -ENODEV; -- } - - if (intf->cur_altsetting->desc.bNumEndpoints < 3) - return -ENODEV; diff --git a/target/linux/generic/backport-5.10/796-v5.14-net-phy-realtek-add-dt-property-to-disable-CLKOUT-cl.patch b/target/linux/generic/backport-5.10/796-v5.14-net-phy-realtek-add-dt-property-to-disable-CLKOUT-cl.patch deleted file mode 100644 index 52a6f83500..0000000000 --- a/target/linux/generic/backport-5.10/796-v5.14-net-phy-realtek-add-dt-property-to-disable-CLKOUT-cl.patch +++ /dev/null @@ -1,119 +0,0 @@ -From 0a4355c2b7f8ecd5e61cc262ecdbd4a2cce1ea7e Mon Sep 17 00:00:00 2001 -From: Joakim Zhang -Date: Tue, 8 Jun 2021 11:15:33 +0800 -Subject: [PATCH] net: phy: realtek: add dt property to disable CLKOUT clock - -CLKOUT is enabled by default after PHY hardware reset, this patch adds -"realtek,clkout-disable" property for user to disable CLKOUT clock -to save PHY power. - -Per RTL8211F guide, a PHY reset should be issued after setting these -bits in PHYCR2 register. After this patch, CLKOUT clock output to be -disabled. - -Signed-off-by: Joakim Zhang -Signed-off-by: David S. Miller ---- - drivers/net/phy/realtek.c | 42 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 41 insertions(+), 1 deletion(-) - ---- a/drivers/net/phy/realtek.c -+++ b/drivers/net/phy/realtek.c -@@ -8,6 +8,7 @@ - * Copyright (c) 2004 Freescale Semiconductor, Inc. - */ - #include -+#include - #include - #include - #include -@@ -27,6 +28,7 @@ - #define RTL821x_PAGE_SELECT 0x1f - - #define RTL8211F_PHYCR1 0x18 -+#define RTL8211F_PHYCR2 0x19 - #define RTL8211F_INSR 0x1d - - #define RTL8211F_TX_DELAY BIT(8) -@@ -40,6 +42,8 @@ - #define RTL8211E_TX_DELAY BIT(12) - #define RTL8211E_RX_DELAY BIT(11) - -+#define RTL8211F_CLKOUT_EN BIT(0) -+ - #define RTL8201F_ISR 0x1e - #define RTL8201F_IER 0x13 - -@@ -62,6 +66,10 @@ MODULE_DESCRIPTION("Realtek PHY driver") - MODULE_AUTHOR("Johnson Leung"); - MODULE_LICENSE("GPL"); - -+struct rtl821x_priv { -+ u16 phycr2; -+}; -+ - static int rtl821x_read_page(struct phy_device *phydev) - { - return __phy_read(phydev, RTL821x_PAGE_SELECT); -@@ -72,6 +80,28 @@ static int rtl821x_write_page(struct phy - return __phy_write(phydev, RTL821x_PAGE_SELECT, page); - } - -+static int rtl821x_probe(struct phy_device *phydev) -+{ -+ struct device *dev = &phydev->mdio.dev; -+ struct rtl821x_priv *priv; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->phycr2 = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2); -+ if (priv->phycr2 < 0) -+ return priv->phycr2; -+ -+ priv->phycr2 &= RTL8211F_CLKOUT_EN; -+ if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) -+ priv->phycr2 &= ~RTL8211F_CLKOUT_EN; -+ -+ phydev->priv = priv; -+ -+ return 0; -+} -+ - static int rtl8201_ack_interrupt(struct phy_device *phydev) - { - int err; -@@ -180,6 +210,7 @@ static int rtl8211c_config_init(struct p - - static int rtl8211f_config_init(struct phy_device *phydev) - { -+ struct rtl821x_priv *priv = phydev->priv; - struct device *dev = &phydev->mdio.dev; - u16 val_txdly, val_rxdly; - u16 val; -@@ -243,7 +274,15 @@ static int rtl8211f_config_init(struct p - val_rxdly ? "enabled" : "disabled"); - } - -- return 0; -+ ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2, -+ RTL8211F_CLKOUT_EN, priv->phycr2); -+ if (ret < 0) { -+ dev_err(dev, "clkout configuration failed: %pe\n", -+ ERR_PTR(ret)); -+ return ret; -+ } -+ -+ return genphy_soft_reset(phydev); - } - - static int rtl821x_resume(struct phy_device *phydev) -@@ -633,6 +672,7 @@ static struct phy_driver realtek_drvs[] - }, { - PHY_ID_MATCH_EXACT(0x001cc916), - .name = "RTL8211F Gigabit Ethernet", -+ .probe = rtl821x_probe, - .config_init = &rtl8211f_config_init, - .ack_interrupt = &rtl8211f_ack_interrupt, - .config_intr = &rtl8211f_config_intr, diff --git a/target/linux/generic/backport-5.10/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch b/target/linux/generic/backport-5.10/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch deleted file mode 100644 index a2168aaba5..0000000000 --- a/target/linux/generic/backport-5.10/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 16b1c4e01c89ba07367461e0bc4cb84993c2d027 Mon Sep 17 00:00:00 2001 -From: Jacky Chou -Date: Mon, 15 Nov 2021 11:49:41 +0800 -Subject: [PATCH] net: usb: ax88179_178a: add TSO feature - -On low-effciency embedded platforms, transmission performance is poor -due to on Bulk-out with single packet. -Adding TSO feature improves the transmission performance and reduces -the number of interrupt caused by Bulk-out complete. - -Reference to module, net: usb: aqc111. - -Signed-off-by: Jacky Chou -Signed-off-by: David S. Miller ---- - drivers/net/usb/ax88179_178a.c | 17 +++++++++++------ - 1 file changed, 11 insertions(+), 6 deletions(-) - ---- a/drivers/net/usb/ax88179_178a.c -+++ b/drivers/net/usb/ax88179_178a.c -@@ -1377,11 +1377,12 @@ static int ax88179_bind(struct usbnet *d - dev->mii.phy_id = 0x03; - dev->mii.supports_gmii = 1; - -- dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | -- NETIF_F_RXCSUM; -+ dev->net->features |= NETIF_F_SG | NETIF_F_IP_CSUM | -+ NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | NETIF_F_TSO; - -- dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | -- NETIF_F_RXCSUM; -+ dev->net->hw_features |= dev->net->features; -+ -+ netif_set_gso_max_size(dev->net, 16384); - - /* Enable checksum offload */ - *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | -@@ -1587,17 +1588,19 @@ ax88179_tx_fixup(struct usbnet *dev, str - { - u32 tx_hdr1, tx_hdr2; - int frame_size = dev->maxpacket; -- int mss = skb_shinfo(skb)->gso_size; - int headroom; - void *ptr; - - tx_hdr1 = skb->len; -- tx_hdr2 = mss; -+ tx_hdr2 = skb_shinfo(skb)->gso_size; /* Set TSO mss */ - if (((skb->len + 8) % frame_size) == 0) - tx_hdr2 |= 0x80008000; /* Enable padding */ - - headroom = skb_headroom(skb) - 8; - -+ if ((dev->net->features & NETIF_F_SG) && skb_linearize(skb)) -+ return NULL; -+ - if ((skb_header_cloned(skb) || headroom < 0) && - pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) { - dev_kfree_skb_any(skb); -@@ -1608,6 +1611,8 @@ ax88179_tx_fixup(struct usbnet *dev, str - put_unaligned_le32(tx_hdr1, ptr); - put_unaligned_le32(tx_hdr2, ptr + 4); - -+ usbnet_set_skb_tx_stats(skb, (skb_shinfo(skb)->gso_segs ?: 1), 0); -+ - return skb; - } - diff --git a/target/linux/generic/backport-5.10/800-v5.13-0001-firmware-bcm47xx_nvram-rename-finding-function-and-i.patch b/target/linux/generic/backport-5.10/800-v5.13-0001-firmware-bcm47xx_nvram-rename-finding-function-and-i.patch deleted file mode 100644 index 19938704b7..0000000000 --- a/target/linux/generic/backport-5.10/800-v5.13-0001-firmware-bcm47xx_nvram-rename-finding-function-and-i.patch +++ /dev/null @@ -1,80 +0,0 @@ -From fb009cbdd0693bd633f11e99526617b3d392cfad Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 8 Mar 2021 10:03:16 +0100 -Subject: [PATCH] firmware: bcm47xx_nvram: rename finding function and its - variables -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. Use "bcm47xx_" function name prefix for consistency -2. It takes flash start as argument so s/iobase/flash_start/ -3. "off" was used for finding flash end so just call it "flash_size" - -Signed-off-by: Rafał Miłecki -Signed-off-by: Thomas Bogendoerfer ---- - drivers/firmware/broadcom/bcm47xx_nvram.c | 24 ++++++++++++----------- - 1 file changed, 13 insertions(+), 11 deletions(-) - ---- a/drivers/firmware/broadcom/bcm47xx_nvram.c -+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c -@@ -48,11 +48,13 @@ static u32 find_nvram_size(void __iomem - return 0; - } - --/* Probe for NVRAM header */ --static int nvram_find_and_copy(void __iomem *iobase, u32 lim) -+/** -+ * bcm47xx_nvram_find_and_copy - find NVRAM on flash mapping & copy it -+ */ -+static int bcm47xx_nvram_find_and_copy(void __iomem *flash_start, size_t res_size) - { - struct nvram_header __iomem *header; -- u32 off; -+ size_t flash_size; - u32 size; - - if (nvram_len) { -@@ -61,25 +63,25 @@ static int nvram_find_and_copy(void __io - } - - /* TODO: when nvram is on nand flash check for bad blocks first. */ -- off = FLASH_MIN; -- while (off <= lim) { -+ flash_size = FLASH_MIN; -+ while (flash_size <= res_size) { - /* Windowed flash access */ -- size = find_nvram_size(iobase + off); -+ size = find_nvram_size(flash_start + flash_size); - if (size) { -- header = (struct nvram_header *)(iobase + off - size); -+ header = (struct nvram_header *)(flash_start + flash_size - size); - goto found; - } -- off <<= 1; -+ flash_size <<= 1; - } - - /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */ -- header = (struct nvram_header *)(iobase + 4096); -+ header = (struct nvram_header *)(flash_start + 4096); - if (header->magic == NVRAM_MAGIC) { - size = NVRAM_SPACE; - goto found; - } - -- header = (struct nvram_header *)(iobase + 1024); -+ header = (struct nvram_header *)(flash_start + 1024); - if (header->magic == NVRAM_MAGIC) { - size = NVRAM_SPACE; - goto found; -@@ -124,7 +126,7 @@ int bcm47xx_nvram_init_from_mem(u32 base - if (!iobase) - return -ENOMEM; - -- err = nvram_find_and_copy(iobase, lim); -+ err = bcm47xx_nvram_find_and_copy(iobase, lim); - - iounmap(iobase); - diff --git a/target/linux/generic/backport-5.10/800-v5.13-0002-firmware-bcm47xx_nvram-add-helper-checking-for-NVRAM.patch b/target/linux/generic/backport-5.10/800-v5.13-0002-firmware-bcm47xx_nvram-add-helper-checking-for-NVRAM.patch deleted file mode 100644 index 6ab072883d..0000000000 --- a/target/linux/generic/backport-5.10/800-v5.13-0002-firmware-bcm47xx_nvram-add-helper-checking-for-NVRAM.patch +++ /dev/null @@ -1,90 +0,0 @@ -From 0a24b51a3264a3f942a75025ea5ff6133c8989b0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 8 Mar 2021 10:03:17 +0100 -Subject: [PATCH] firmware: bcm47xx_nvram: add helper checking for NVRAM -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This avoids duplicating code doing casting and checking for NVRAM magic. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Thomas Bogendoerfer ---- - drivers/firmware/broadcom/bcm47xx_nvram.c | 30 ++++++++++++++--------- - 1 file changed, 18 insertions(+), 12 deletions(-) - ---- a/drivers/firmware/broadcom/bcm47xx_nvram.c -+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c -@@ -34,14 +34,20 @@ static char nvram_buf[NVRAM_SPACE]; - static size_t nvram_len; - static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000}; - -+/** -+ * bcm47xx_nvram_is_valid - check for a valid NVRAM at specified memory -+ */ -+static bool bcm47xx_nvram_is_valid(void __iomem *nvram) -+{ -+ return ((struct nvram_header *)nvram)->magic == NVRAM_MAGIC; -+} -+ - static u32 find_nvram_size(void __iomem *end) - { -- struct nvram_header __iomem *header; - int i; - - for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) { -- header = (struct nvram_header *)(end - nvram_sizes[i]); -- if (header->magic == NVRAM_MAGIC) -+ if (bcm47xx_nvram_is_valid(end - nvram_sizes[i])) - return nvram_sizes[i]; - } - -@@ -55,6 +61,7 @@ static int bcm47xx_nvram_find_and_copy(v - { - struct nvram_header __iomem *header; - size_t flash_size; -+ size_t offset; - u32 size; - - if (nvram_len) { -@@ -68,31 +75,30 @@ static int bcm47xx_nvram_find_and_copy(v - /* Windowed flash access */ - size = find_nvram_size(flash_start + flash_size); - if (size) { -- header = (struct nvram_header *)(flash_start + flash_size - size); -+ offset = flash_size - size; - goto found; - } - flash_size <<= 1; - } - - /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */ -- header = (struct nvram_header *)(flash_start + 4096); -- if (header->magic == NVRAM_MAGIC) { -- size = NVRAM_SPACE; -+ -+ offset = 4096; -+ if (bcm47xx_nvram_is_valid(flash_start + offset)) - goto found; -- } - -- header = (struct nvram_header *)(flash_start + 1024); -- if (header->magic == NVRAM_MAGIC) { -- size = NVRAM_SPACE; -+ offset = 1024; -+ if (bcm47xx_nvram_is_valid(flash_start + offset)) - goto found; -- } - - pr_err("no nvram found\n"); - return -ENXIO; - - found: -+ header = (struct nvram_header *)(flash_start + offset); - __ioread32_copy(nvram_buf, header, sizeof(*header) / 4); - nvram_len = ((struct nvram_header *)(nvram_buf))->len; -+ size = res_size - offset; - if (nvram_len > size) { - pr_err("The nvram size according to the header seems to be bigger than the partition on flash\n"); - nvram_len = size; diff --git a/target/linux/generic/backport-5.10/800-v5.13-0003-firmware-bcm47xx_nvram-extract-code-copying-NVRAM.patch b/target/linux/generic/backport-5.10/800-v5.13-0003-firmware-bcm47xx_nvram-extract-code-copying-NVRAM.patch deleted file mode 100644 index a1351f1197..0000000000 --- a/target/linux/generic/backport-5.10/800-v5.13-0003-firmware-bcm47xx_nvram-extract-code-copying-NVRAM.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 298923cf999cecd2ef06df126f85a3d68da8c4d8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 8 Mar 2021 10:03:18 +0100 -Subject: [PATCH] firmware: bcm47xx_nvram: extract code copying NVRAM -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This simplifies function finding NVRAM. It doesn't directly deal with -NVRAM structure anymore and is a bit smaller. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Thomas Bogendoerfer ---- - drivers/firmware/broadcom/bcm47xx_nvram.c | 43 +++++++++++++---------- - 1 file changed, 25 insertions(+), 18 deletions(-) - ---- a/drivers/firmware/broadcom/bcm47xx_nvram.c -+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c -@@ -55,11 +55,34 @@ static u32 find_nvram_size(void __iomem - } - - /** -+ * bcm47xx_nvram_copy - copy NVRAM to internal buffer -+ */ -+static void bcm47xx_nvram_copy(void __iomem *nvram_start, size_t res_size) -+{ -+ struct nvram_header __iomem *header = nvram_start; -+ size_t copy_size; -+ -+ copy_size = header->len; -+ if (copy_size > res_size) { -+ pr_err("The nvram size according to the header seems to be bigger than the partition on flash\n"); -+ copy_size = res_size; -+ } -+ if (copy_size >= NVRAM_SPACE) { -+ pr_err("nvram on flash (%zu bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", -+ copy_size, NVRAM_SPACE - 1); -+ copy_size = NVRAM_SPACE - 1; -+ } -+ -+ __ioread32_copy(nvram_buf, nvram_start, DIV_ROUND_UP(copy_size, 4)); -+ nvram_buf[NVRAM_SPACE - 1] = '\0'; -+ nvram_len = copy_size; -+} -+ -+/** - * bcm47xx_nvram_find_and_copy - find NVRAM on flash mapping & copy it - */ - static int bcm47xx_nvram_find_and_copy(void __iomem *flash_start, size_t res_size) - { -- struct nvram_header __iomem *header; - size_t flash_size; - size_t offset; - u32 size; -@@ -95,23 +118,7 @@ static int bcm47xx_nvram_find_and_copy(v - return -ENXIO; - - found: -- header = (struct nvram_header *)(flash_start + offset); -- __ioread32_copy(nvram_buf, header, sizeof(*header) / 4); -- nvram_len = ((struct nvram_header *)(nvram_buf))->len; -- size = res_size - offset; -- if (nvram_len > size) { -- pr_err("The nvram size according to the header seems to be bigger than the partition on flash\n"); -- nvram_len = size; -- } -- if (nvram_len >= NVRAM_SPACE) { -- pr_err("nvram on flash (%zu bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n", -- nvram_len, NVRAM_SPACE - 1); -- nvram_len = NVRAM_SPACE - 1; -- } -- /* proceed reading data after header */ -- __ioread32_copy(nvram_buf + sizeof(*header), header + 1, -- DIV_ROUND_UP(nvram_len, 4)); -- nvram_buf[NVRAM_SPACE - 1] = '\0'; -+ bcm47xx_nvram_copy(flash_start + offset, res_size - offset); - - return 0; - } diff --git a/target/linux/generic/backport-5.10/800-v5.13-0004-firmware-bcm47xx_nvram-look-for-NVRAM-with-for-inste.patch b/target/linux/generic/backport-5.10/800-v5.13-0004-firmware-bcm47xx_nvram-look-for-NVRAM-with-for-inste.patch deleted file mode 100644 index 059a13220b..0000000000 --- a/target/linux/generic/backport-5.10/800-v5.13-0004-firmware-bcm47xx_nvram-look-for-NVRAM-with-for-inste.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 98b68324f67236e8c9152976535dc1f27fb67ba8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 8 Mar 2021 10:03:19 +0100 -Subject: [PATCH] firmware: bcm47xx_nvram: look for NVRAM with for instead of - while -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This loop requires variable initialization, stop condition and post -iteration increment. It's pretty much a for loop definition. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Thomas Bogendoerfer ---- - drivers/firmware/broadcom/bcm47xx_nvram.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/firmware/broadcom/bcm47xx_nvram.c -+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c -@@ -93,15 +93,13 @@ static int bcm47xx_nvram_find_and_copy(v - } - - /* TODO: when nvram is on nand flash check for bad blocks first. */ -- flash_size = FLASH_MIN; -- while (flash_size <= res_size) { -+ for (flash_size = FLASH_MIN; flash_size <= res_size; flash_size <<= 1) { - /* Windowed flash access */ - size = find_nvram_size(flash_start + flash_size); - if (size) { - offset = flash_size - size; - goto found; - } -- flash_size <<= 1; - } - - /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */ diff --git a/target/linux/generic/backport-5.10/800-v5.13-0005-firmware-bcm47xx_nvram-inline-code-checking-NVRAM-si.patch b/target/linux/generic/backport-5.10/800-v5.13-0005-firmware-bcm47xx_nvram-inline-code-checking-NVRAM-si.patch deleted file mode 100644 index 21d250049e..0000000000 --- a/target/linux/generic/backport-5.10/800-v5.13-0005-firmware-bcm47xx_nvram-inline-code-checking-NVRAM-si.patch +++ /dev/null @@ -1,70 +0,0 @@ -From f52da4ccfec9192e17f5c16260dfdd6d3ea76f65 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 8 Mar 2021 10:03:20 +0100 -Subject: [PATCH] firmware: bcm47xx_nvram: inline code checking NVRAM size -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Separated function was not improving code quality much (or at all). -Moreover it expected possible flash end address as argument and it was -returning NVRAM size. - -The new code always operates on offsets which means less logic and less -calculations. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Thomas Bogendoerfer ---- - drivers/firmware/broadcom/bcm47xx_nvram.c | 25 +++++++---------------- - 1 file changed, 7 insertions(+), 18 deletions(-) - ---- a/drivers/firmware/broadcom/bcm47xx_nvram.c -+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c -@@ -42,18 +42,6 @@ static bool bcm47xx_nvram_is_valid(void - return ((struct nvram_header *)nvram)->magic == NVRAM_MAGIC; - } - --static u32 find_nvram_size(void __iomem *end) --{ -- int i; -- -- for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) { -- if (bcm47xx_nvram_is_valid(end - nvram_sizes[i])) -- return nvram_sizes[i]; -- } -- -- return 0; --} -- - /** - * bcm47xx_nvram_copy - copy NVRAM to internal buffer - */ -@@ -85,7 +73,7 @@ static int bcm47xx_nvram_find_and_copy(v - { - size_t flash_size; - size_t offset; -- u32 size; -+ int i; - - if (nvram_len) { - pr_warn("nvram already initialized\n"); -@@ -93,12 +81,13 @@ static int bcm47xx_nvram_find_and_copy(v - } - - /* TODO: when nvram is on nand flash check for bad blocks first. */ -+ -+ /* Try every possible flash size and check for NVRAM at its end */ - for (flash_size = FLASH_MIN; flash_size <= res_size; flash_size <<= 1) { -- /* Windowed flash access */ -- size = find_nvram_size(flash_start + flash_size); -- if (size) { -- offset = flash_size - size; -- goto found; -+ for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) { -+ offset = flash_size - nvram_sizes[i]; -+ if (bcm47xx_nvram_is_valid(flash_start + offset)) -+ goto found; - } - } - diff --git a/target/linux/generic/backport-5.10/801-v5.11-0001-nvmem-core-Add-support-for-keepout-regions.patch b/target/linux/generic/backport-5.10/801-v5.11-0001-nvmem-core-Add-support-for-keepout-regions.patch deleted file mode 100644 index a0f8c4715e..0000000000 --- a/target/linux/generic/backport-5.10/801-v5.11-0001-nvmem-core-Add-support-for-keepout-regions.patch +++ /dev/null @@ -1,267 +0,0 @@ -From fd3bb8f54a88107570334c156efb0c724a261003 Mon Sep 17 00:00:00 2001 -From: Evan Green -Date: Fri, 27 Nov 2020 10:28:34 +0000 -Subject: [PATCH] nvmem: core: Add support for keepout regions - -Introduce support into the nvmem core for arrays of register ranges -that should not result in actual device access. For these regions a -constant byte (repeated) is returned instead on read, and writes are -quietly ignored and returned as successful. - -This is useful for instance if certain efuse regions are protected -from access by Linux because they contain secret info to another part -of the system (like an integrated modem). - -Signed-off-by: Evan Green -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20201127102837.19366-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 153 ++++++++++++++++++++++++++++++++- - include/linux/nvmem-provider.h | 17 ++++ - 2 files changed, 166 insertions(+), 4 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -34,6 +34,8 @@ struct nvmem_device { - struct bin_attribute eeprom; - struct device *base_dev; - struct list_head cells; -+ const struct nvmem_keepout *keepout; -+ unsigned int nkeepout; - nvmem_reg_read_t reg_read; - nvmem_reg_write_t reg_write; - struct gpio_desc *wp_gpio; -@@ -66,8 +68,8 @@ static LIST_HEAD(nvmem_lookup_list); - - static BLOCKING_NOTIFIER_HEAD(nvmem_notifier); - --static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset, -- void *val, size_t bytes) -+static int __nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset, -+ void *val, size_t bytes) - { - if (nvmem->reg_read) - return nvmem->reg_read(nvmem->priv, offset, val, bytes); -@@ -75,8 +77,8 @@ static int nvmem_reg_read(struct nvmem_d - return -EINVAL; - } - --static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset, -- void *val, size_t bytes) -+static int __nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset, -+ void *val, size_t bytes) - { - int ret; - -@@ -90,6 +92,88 @@ static int nvmem_reg_write(struct nvmem_ - return -EINVAL; - } - -+static int nvmem_access_with_keepouts(struct nvmem_device *nvmem, -+ unsigned int offset, void *val, -+ size_t bytes, int write) -+{ -+ -+ unsigned int end = offset + bytes; -+ unsigned int kend, ksize; -+ const struct nvmem_keepout *keepout = nvmem->keepout; -+ const struct nvmem_keepout *keepoutend = keepout + nvmem->nkeepout; -+ int rc; -+ -+ /* -+ * Skip all keepouts before the range being accessed. -+ * Keepouts are sorted. -+ */ -+ while ((keepout < keepoutend) && (keepout->end <= offset)) -+ keepout++; -+ -+ while ((offset < end) && (keepout < keepoutend)) { -+ /* Access the valid portion before the keepout. */ -+ if (offset < keepout->start) { -+ kend = min(end, keepout->start); -+ ksize = kend - offset; -+ if (write) -+ rc = __nvmem_reg_write(nvmem, offset, val, ksize); -+ else -+ rc = __nvmem_reg_read(nvmem, offset, val, ksize); -+ -+ if (rc) -+ return rc; -+ -+ offset += ksize; -+ val += ksize; -+ } -+ -+ /* -+ * Now we're aligned to the start of this keepout zone. Go -+ * through it. -+ */ -+ kend = min(end, keepout->end); -+ ksize = kend - offset; -+ if (!write) -+ memset(val, keepout->value, ksize); -+ -+ val += ksize; -+ offset += ksize; -+ keepout++; -+ } -+ -+ /* -+ * If we ran out of keepouts but there's still stuff to do, send it -+ * down directly -+ */ -+ if (offset < end) { -+ ksize = end - offset; -+ if (write) -+ return __nvmem_reg_write(nvmem, offset, val, ksize); -+ else -+ return __nvmem_reg_read(nvmem, offset, val, ksize); -+ } -+ -+ return 0; -+} -+ -+static int nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset, -+ void *val, size_t bytes) -+{ -+ if (!nvmem->nkeepout) -+ return __nvmem_reg_read(nvmem, offset, val, bytes); -+ -+ return nvmem_access_with_keepouts(nvmem, offset, val, bytes, false); -+} -+ -+static int nvmem_reg_write(struct nvmem_device *nvmem, unsigned int offset, -+ void *val, size_t bytes) -+{ -+ if (!nvmem->nkeepout) -+ return __nvmem_reg_write(nvmem, offset, val, bytes); -+ -+ return nvmem_access_with_keepouts(nvmem, offset, val, bytes, true); -+} -+ - #ifdef CONFIG_NVMEM_SYSFS - static const char * const nvmem_type_str[] = { - [NVMEM_TYPE_UNKNOWN] = "Unknown", -@@ -535,6 +619,59 @@ nvmem_find_cell_by_name(struct nvmem_dev - return cell; - } - -+static int nvmem_validate_keepouts(struct nvmem_device *nvmem) -+{ -+ unsigned int cur = 0; -+ const struct nvmem_keepout *keepout = nvmem->keepout; -+ const struct nvmem_keepout *keepoutend = keepout + nvmem->nkeepout; -+ -+ while (keepout < keepoutend) { -+ /* Ensure keepouts are sorted and don't overlap. */ -+ if (keepout->start < cur) { -+ dev_err(&nvmem->dev, -+ "Keepout regions aren't sorted or overlap.\n"); -+ -+ return -ERANGE; -+ } -+ -+ if (keepout->end < keepout->start) { -+ dev_err(&nvmem->dev, -+ "Invalid keepout region.\n"); -+ -+ return -EINVAL; -+ } -+ -+ /* -+ * Validate keepouts (and holes between) don't violate -+ * word_size constraints. -+ */ -+ if ((keepout->end - keepout->start < nvmem->word_size) || -+ ((keepout->start != cur) && -+ (keepout->start - cur < nvmem->word_size))) { -+ -+ dev_err(&nvmem->dev, -+ "Keepout regions violate word_size constraints.\n"); -+ -+ return -ERANGE; -+ } -+ -+ /* Validate keepouts don't violate stride (alignment). */ -+ if (!IS_ALIGNED(keepout->start, nvmem->stride) || -+ !IS_ALIGNED(keepout->end, nvmem->stride)) { -+ -+ dev_err(&nvmem->dev, -+ "Keepout regions violate stride.\n"); -+ -+ return -EINVAL; -+ } -+ -+ cur = keepout->end; -+ keepout++; -+ } -+ -+ return 0; -+} -+ - static int nvmem_add_cells_from_of(struct nvmem_device *nvmem) - { - struct device_node *parent, *child; -@@ -656,6 +793,8 @@ struct nvmem_device *nvmem_register(cons - nvmem->type = config->type; - nvmem->reg_read = config->reg_read; - nvmem->reg_write = config->reg_write; -+ nvmem->keepout = config->keepout; -+ nvmem->nkeepout = config->nkeepout; - if (!config->no_of_node) - nvmem->dev.of_node = config->dev->of_node; - -@@ -703,6 +842,12 @@ struct nvmem_device *nvmem_register(cons - if (rval) - goto err_remove_cells; - -+ if (nvmem->nkeepout) { -+ rval = nvmem_validate_keepouts(nvmem); -+ if (rval) -+ goto err_put_device; -+ } -+ - dev_dbg(&nvmem->dev, "Registering nvmem device %s\n", config->name); - - rval = device_add(&nvmem->dev); ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -31,6 +31,19 @@ enum nvmem_type { - #define NVMEM_DEVID_AUTO (-2) - - /** -+ * struct nvmem_keepout - NVMEM register keepout range. -+ * -+ * @start: The first byte offset to avoid. -+ * @end: One beyond the last byte offset to avoid. -+ * @value: The byte to fill reads with for this region. -+ */ -+struct nvmem_keepout { -+ unsigned int start; -+ unsigned int end; -+ unsigned char value; -+}; -+ -+/** - * struct nvmem_config - NVMEM device configuration - * - * @dev: Parent device. -@@ -39,6 +52,8 @@ enum nvmem_type { - * @owner: Pointer to exporter module. Used for refcounting. - * @cells: Optional array of pre-defined NVMEM cells. - * @ncells: Number of elements in cells. -+ * @keepout: Optional array of keepout ranges (sorted ascending by start). -+ * @nkeepout: Number of elements in the keepout array. - * @type: Type of the nvmem storage - * @read_only: Device is read-only. - * @root_only: Device is accessibly to root only. -@@ -65,6 +80,8 @@ struct nvmem_config { - struct module *owner; - const struct nvmem_cell_info *cells; - int ncells; -+ const struct nvmem_keepout *keepout; -+ unsigned int nkeepout; - enum nvmem_type type; - bool read_only; - bool root_only; diff --git a/target/linux/generic/backport-5.10/801-v5.11-0002-nvmem-qfprom-Don-t-touch-certain-fuses.patch b/target/linux/generic/backport-5.10/801-v5.11-0002-nvmem-qfprom-Don-t-touch-certain-fuses.patch deleted file mode 100644 index ae499e7498..0000000000 --- a/target/linux/generic/backport-5.10/801-v5.11-0002-nvmem-qfprom-Don-t-touch-certain-fuses.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 044ee8f85267599a9b0112911f5c16d4548b4289 Mon Sep 17 00:00:00 2001 -From: Evan Green -Date: Fri, 27 Nov 2020 10:28:36 +0000 -Subject: [PATCH] nvmem: qfprom: Don't touch certain fuses - -Some fuse ranges are protected by the XPU such that the AP cannot -access them. Attempting to do so causes an SError. Use the newly -introduced per-soc compatible string, and the newly introduced -nvmem keepout support to attach the set of regions -we should not access. - -Reviewed-by: Douglas Anderson -Signed-off-by: Evan Green -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20201127102837.19366-5-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qfprom.c | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/drivers/nvmem/qfprom.c -+++ b/drivers/nvmem/qfprom.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - - /* Blow timer clock frequency in Mhz */ -@@ -89,6 +90,28 @@ struct qfprom_touched_values { - }; - - /** -+ * struct qfprom_soc_compatible_data - Data matched against the SoC -+ * compatible string. -+ * -+ * @keepout: Array of keepout regions for this SoC. -+ * @nkeepout: Number of elements in the keepout array. -+ */ -+struct qfprom_soc_compatible_data { -+ const struct nvmem_keepout *keepout; -+ unsigned int nkeepout; -+}; -+ -+static const struct nvmem_keepout sc7180_qfprom_keepout[] = { -+ {.start = 0x128, .end = 0x148}, -+ {.start = 0x220, .end = 0x228} -+}; -+ -+static const struct qfprom_soc_compatible_data sc7180_qfprom = { -+ .keepout = sc7180_qfprom_keepout, -+ .nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout) -+}; -+ -+/** - * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing. - * @priv: Our driver data. - * @old: The data that was stashed from before fuse blowing. -@@ -302,6 +325,7 @@ static int qfprom_probe(struct platform_ - struct device *dev = &pdev->dev; - struct resource *res; - struct nvmem_device *nvmem; -+ const struct qfprom_soc_compatible_data *soc_data; - struct qfprom_priv *priv; - int ret; - -@@ -320,6 +344,11 @@ static int qfprom_probe(struct platform_ - econfig.priv = priv; - - priv->dev = dev; -+ soc_data = device_get_match_data(dev); -+ if (soc_data) { -+ econfig.keepout = soc_data->keepout; -+ econfig.nkeepout = soc_data->nkeepout; -+ } - - /* - * If more than one region is provided then the OS has the ability -@@ -375,6 +404,7 @@ static int qfprom_probe(struct platform_ - - static const struct of_device_id qfprom_of_match[] = { - { .compatible = "qcom,qfprom",}, -+ { .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom}, - {/* sentinel */}, - }; - MODULE_DEVICE_TABLE(of, qfprom_of_match); diff --git a/target/linux/generic/backport-5.10/801-v5.11-0003-nvmem-imx-ocotp-add-support-for-the-unaliged-word-co.patch b/target/linux/generic/backport-5.10/801-v5.11-0003-nvmem-imx-ocotp-add-support-for-the-unaliged-word-co.patch deleted file mode 100644 index 0a05e0a97f..0000000000 --- a/target/linux/generic/backport-5.10/801-v5.11-0003-nvmem-imx-ocotp-add-support-for-the-unaliged-word-co.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 3311bf18467272388039922a5e29c4925b291f73 Mon Sep 17 00:00:00 2001 -From: Peng Fan -Date: Fri, 27 Nov 2020 10:28:37 +0000 -Subject: [PATCH] nvmem: imx-ocotp: add support for the unaliged word count - -When offset is not 4 bytes aligned, directly shift righty by 2 bits -will cause reading out wrong data. Since imx ocotp only supports -4 bytes reading once, we need handle offset is not 4 bytes aligned -and enlarge the bytes to 4 bytes aligned. After reading finished, -copy the needed data from buffer to caller and free buffer. - -Signed-off-by: Peng Fan -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20201127102837.19366-6-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/imx-ocotp.c | 30 ++++++++++++++++++++++++------ - 1 file changed, 24 insertions(+), 6 deletions(-) - ---- a/drivers/nvmem/imx-ocotp.c -+++ b/drivers/nvmem/imx-ocotp.c -@@ -4,6 +4,8 @@ - * - * Copyright (c) 2015 Pengutronix, Philipp Zabel - * -+ * Copyright 2019 NXP -+ * - * Based on the barebox ocotp driver, - * Copyright (c) 2010 Baruch Siach , - * Orex Computed Radiography -@@ -158,22 +160,30 @@ static int imx_ocotp_read(void *context, - { - struct ocotp_priv *priv = context; - unsigned int count; -- u32 *buf = val; -+ u8 *buf, *p; - int i, ret; -- u32 index; -+ u32 index, num_bytes; - - index = offset >> 2; -- count = bytes >> 2; -+ num_bytes = round_up((offset % 4) + bytes, 4); -+ count = num_bytes >> 2; - - if (count > (priv->params->nregs - index)) - count = priv->params->nregs - index; - -+ p = kzalloc(num_bytes, GFP_KERNEL); -+ if (!p) -+ return -ENOMEM; -+ - mutex_lock(&ocotp_mutex); - -+ buf = p; -+ - ret = clk_prepare_enable(priv->clk); - if (ret < 0) { - mutex_unlock(&ocotp_mutex); - dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); -+ kfree(p); - return ret; - } - -@@ -184,7 +194,7 @@ static int imx_ocotp_read(void *context, - } - - for (i = index; i < (index + count); i++) { -- *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 + -+ *(u32 *)buf = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 + - i * IMX_OCOTP_OFFSET_PER_WORD); - - /* 47.3.1.2 -@@ -193,13 +203,21 @@ static int imx_ocotp_read(void *context, - * software before any new write, read or reload access can be - * issued - */ -- if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL) -+ if (*((u32 *)buf) == IMX_OCOTP_READ_LOCKED_VAL) - imx_ocotp_clr_err_if_set(priv); -+ -+ buf += 4; - } - -+ index = offset % 4; -+ memcpy(val, &p[index], bytes); -+ - read_end: - clk_disable_unprepare(priv->clk); - mutex_unlock(&ocotp_mutex); -+ -+ kfree(p); -+ - return ret; - } - -@@ -447,7 +465,7 @@ static struct nvmem_config imx_ocotp_nvm - .name = "imx-ocotp", - .read_only = false, - .word_size = 4, -- .stride = 4, -+ .stride = 1, - .reg_read = imx_ocotp_read, - .reg_write = imx_ocotp_write, - }; diff --git a/target/linux/generic/backport-5.10/802-v5.12-0002-nvmem-imx-iim-Use-of_device_get_match_data.patch b/target/linux/generic/backport-5.10/802-v5.12-0002-nvmem-imx-iim-Use-of_device_get_match_data.patch deleted file mode 100644 index 9a7ba7f565..0000000000 --- a/target/linux/generic/backport-5.10/802-v5.12-0002-nvmem-imx-iim-Use-of_device_get_match_data.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 579db09c6106977c0496f2cca48606b289df4bdf Mon Sep 17 00:00:00 2001 -From: Fabio Estevam -Date: Fri, 29 Jan 2021 17:14:27 +0000 -Subject: [PATCH] nvmem: imx-iim: Use of_device_get_match_data() - -The retrieval of driver data via of_device_get_match_data() can make -the code simpler. - -Use of_device_get_match_data() to simplify the code. - -Signed-off-by: Fabio Estevam -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210129171430.11328-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/imx-iim.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - ---- a/drivers/nvmem/imx-iim.c -+++ b/drivers/nvmem/imx-iim.c -@@ -96,7 +96,6 @@ MODULE_DEVICE_TABLE(of, imx_iim_dt_ids); - - static int imx_iim_probe(struct platform_device *pdev) - { -- const struct of_device_id *of_id; - struct device *dev = &pdev->dev; - struct iim_priv *iim; - struct nvmem_device *nvmem; -@@ -111,11 +110,7 @@ static int imx_iim_probe(struct platform - if (IS_ERR(iim->base)) - return PTR_ERR(iim->base); - -- of_id = of_match_device(imx_iim_dt_ids, dev); -- if (!of_id) -- return -ENODEV; -- -- drvdata = of_id->data; -+ drvdata = of_device_get_match_data(&pdev->dev); - - iim->clk = devm_clk_get(dev, NULL); - if (IS_ERR(iim->clk)) diff --git a/target/linux/generic/backport-5.10/802-v5.12-0003-nvmem-Add-driver-to-expose-reserved-memory-as-nvmem.patch b/target/linux/generic/backport-5.10/802-v5.12-0003-nvmem-Add-driver-to-expose-reserved-memory-as-nvmem.patch deleted file mode 100644 index f3ed563d20..0000000000 --- a/target/linux/generic/backport-5.10/802-v5.12-0003-nvmem-Add-driver-to-expose-reserved-memory-as-nvmem.patch +++ /dev/null @@ -1,160 +0,0 @@ -From 5a3fa75a4d9cb6bcfc9081ef224a4cdcd4b3eafe Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Fri, 29 Jan 2021 17:14:29 +0000 -Subject: [PATCH] nvmem: Add driver to expose reserved memory as nvmem - -Firmware/co-processors might use reserved memory areas in order to pass -data stemming from an nvmem device otherwise non accessible to Linux. -For example an EEPROM memory only physically accessible to firmware, or -data only accessible early at boot time. - -In order to expose this data to other drivers and user-space, the driver -models the reserved memory area as an nvmem device. - -Tested-by: Tim Gover -Reviewed-by: Rob Herring -Signed-off-by: Nicolas Saenz Julienne -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210129171430.11328-5-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 8 ++++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/rmem.c | 97 ++++++++++++++++++++++++++++++++++++++++++ - drivers/of/platform.c | 1 + - 4 files changed, 108 insertions(+) - create mode 100644 drivers/nvmem/rmem.c - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -270,4 +270,12 @@ config SPRD_EFUSE - This driver can also be built as a module. If so, the module - will be called nvmem-sprd-efuse. - -+config NVMEM_RMEM -+ tristate "Reserved Memory Based Driver Support" -+ help -+ This drivers maps reserved memory into an nvmem device. It might be -+ useful to expose information left by firmware in memory. -+ -+ This driver can also be built as a module. If so, the module -+ will be called nvmem-rmem. - endif ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -55,3 +55,5 @@ obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynq - nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o - obj-$(CONFIG_SPRD_EFUSE) += nvmem_sprd_efuse.o - nvmem_sprd_efuse-y := sprd-efuse.o -+obj-$(CONFIG_NVMEM_RMEM) += nvmem-rmem.o -+nvmem-rmem-y := rmem.o ---- /dev/null -+++ b/drivers/nvmem/rmem.c -@@ -0,0 +1,97 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2020 Nicolas Saenz Julienne -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+struct rmem { -+ struct device *dev; -+ struct nvmem_device *nvmem; -+ struct reserved_mem *mem; -+ -+ phys_addr_t size; -+}; -+ -+static int rmem_read(void *context, unsigned int offset, -+ void *val, size_t bytes) -+{ -+ struct rmem *priv = context; -+ size_t available = priv->mem->size; -+ loff_t off = offset; -+ void *addr; -+ int count; -+ -+ /* -+ * Only map the reserved memory at this point to avoid potential rogue -+ * kernel threads inadvertently modifying it. Based on the current -+ * uses-cases for this driver, the performance hit isn't a concern. -+ * Nor is likely to be, given the nature of the subsystem. Most nvmem -+ * devices operate over slow buses to begin with. -+ * -+ * An alternative would be setting the memory as RO, set_memory_ro(), -+ * but as of Dec 2020 this isn't possible on arm64. -+ */ -+ addr = memremap(priv->mem->base, available, MEMREMAP_WB); -+ if (IS_ERR(addr)) { -+ dev_err(priv->dev, "Failed to remap memory region\n"); -+ return PTR_ERR(addr); -+ } -+ -+ count = memory_read_from_buffer(val, bytes, &off, addr, available); -+ -+ memunmap(addr); -+ -+ return count; -+} -+ -+static int rmem_probe(struct platform_device *pdev) -+{ -+ struct nvmem_config config = { }; -+ struct device *dev = &pdev->dev; -+ struct reserved_mem *mem; -+ struct rmem *priv; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ priv->dev = dev; -+ -+ mem = of_reserved_mem_lookup(dev->of_node); -+ if (!mem) { -+ dev_err(dev, "Failed to lookup reserved memory\n"); -+ return -EINVAL; -+ } -+ priv->mem = mem; -+ -+ config.dev = dev; -+ config.priv = priv; -+ config.name = "rmem"; -+ config.size = mem->size; -+ config.reg_read = rmem_read; -+ -+ return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config)); -+} -+ -+static const struct of_device_id rmem_match[] = { -+ { .compatible = "nvmem-rmem", }, -+ { /* sentinel */ }, -+}; -+MODULE_DEVICE_TABLE(of, rmem_match); -+ -+static struct platform_driver rmem_driver = { -+ .probe = rmem_probe, -+ .driver = { -+ .name = "rmem", -+ .of_match_table = rmem_match, -+ }, -+}; -+module_platform_driver(rmem_driver); -+ -+MODULE_AUTHOR("Nicolas Saenz Julienne "); -+MODULE_DESCRIPTION("Reserved Memory Based nvmem Driver"); -+MODULE_LICENSE("GPL"); ---- a/drivers/of/platform.c -+++ b/drivers/of/platform.c -@@ -511,6 +511,7 @@ static const struct of_device_id reserve - { .compatible = "qcom,rmtfs-mem" }, - { .compatible = "qcom,cmd-db" }, - { .compatible = "ramoops" }, -+ { .compatible = "nvmem-rmem" }, - {} - }; - diff --git a/target/linux/generic/backport-5.10/802-v5.12-0005-nvmem-Kconfig-Correct-typo-in-NVMEM_RMEM.patch b/target/linux/generic/backport-5.10/802-v5.12-0005-nvmem-Kconfig-Correct-typo-in-NVMEM_RMEM.patch deleted file mode 100644 index 129d070a62..0000000000 --- a/target/linux/generic/backport-5.10/802-v5.12-0005-nvmem-Kconfig-Correct-typo-in-NVMEM_RMEM.patch +++ /dev/null @@ -1,28 +0,0 @@ -From b31f1eb41c140d7979f855df73064b3a3ae8055a Mon Sep 17 00:00:00 2001 -From: Nicolas Saenz Julienne -Date: Fri, 5 Feb 2021 10:08:52 +0000 -Subject: [PATCH] nvmem: Kconfig: Correct typo in NVMEM_RMEM - -s/drivers/driver/ as the configuration selects a single driver. - -Suggested-by: Randy Dunlap -Acked-by: Randy Dunlap -Signed-off-by: Nicolas Saenz Julienne -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210205100853.32372-2-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -273,7 +273,7 @@ config SPRD_EFUSE - config NVMEM_RMEM - tristate "Reserved Memory Based Driver Support" - help -- This drivers maps reserved memory into an nvmem device. It might be -+ This driver maps reserved memory into an nvmem device. It might be - useful to expose information left by firmware in memory. - - This driver can also be built as a module. If so, the module diff --git a/target/linux/generic/backport-5.10/803-v5.13-0001-nvmem-convert-comma-to-semicolon.patch b/target/linux/generic/backport-5.10/803-v5.13-0001-nvmem-convert-comma-to-semicolon.patch deleted file mode 100644 index b611ffe645..0000000000 --- a/target/linux/generic/backport-5.10/803-v5.13-0001-nvmem-convert-comma-to-semicolon.patch +++ /dev/null @@ -1,39 +0,0 @@ -From e050f160d4832ce5227fb6ca934969cec0fc48be Mon Sep 17 00:00:00 2001 -From: Zheng Yongjun -Date: Tue, 30 Mar 2021 12:12:33 +0100 -Subject: [PATCH] nvmem: convert comma to semicolon - -Replace a comma between expression statements by a semicolon. - -Reviewed-by: Bjorn Andersson -Signed-off-by: Zheng Yongjun -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210330111241.19401-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qcom-spmi-sdam.c | 2 +- - drivers/nvmem/snvs_lpgpr.c | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/nvmem/qcom-spmi-sdam.c -+++ b/drivers/nvmem/qcom-spmi-sdam.c -@@ -141,7 +141,7 @@ static int sdam_probe(struct platform_de - sdam->sdam_config.dev = &pdev->dev; - sdam->sdam_config.name = "spmi_sdam"; - sdam->sdam_config.id = NVMEM_DEVID_AUTO; -- sdam->sdam_config.owner = THIS_MODULE, -+ sdam->sdam_config.owner = THIS_MODULE; - sdam->sdam_config.stride = 1; - sdam->sdam_config.word_size = 1; - sdam->sdam_config.reg_read = sdam_read; ---- a/drivers/nvmem/snvs_lpgpr.c -+++ b/drivers/nvmem/snvs_lpgpr.c -@@ -123,7 +123,7 @@ static int snvs_lpgpr_probe(struct platf - cfg->dev = dev; - cfg->stride = 4; - cfg->word_size = 4; -- cfg->size = dcfg->size, -+ cfg->size = dcfg->size; - cfg->owner = THIS_MODULE; - cfg->reg_read = snvs_lpgpr_read; - cfg->reg_write = snvs_lpgpr_write; diff --git a/target/linux/generic/backport-5.10/803-v5.13-0003-nvmem-brcm_nvram-new-driver-exposing-Broadcom-s-NVRA.patch b/target/linux/generic/backport-5.10/803-v5.13-0003-nvmem-brcm_nvram-new-driver-exposing-Broadcom-s-NVRA.patch deleted file mode 100644 index 17be01c14f..0000000000 --- a/target/linux/generic/backport-5.10/803-v5.13-0003-nvmem-brcm_nvram-new-driver-exposing-Broadcom-s-NVRA.patch +++ /dev/null @@ -1,126 +0,0 @@ -From 3fef9ed0627af30753a2404b8bd59d92cdb4c0ce Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 30 Mar 2021 12:12:36 +0100 -Subject: [PATCH] nvmem: brcm_nvram: new driver exposing Broadcom's NVRAM -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This driver provides access to Broadcom's NVRAM. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210330111241.19401-6-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 9 +++++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/brcm_nvram.c | 78 ++++++++++++++++++++++++++++++++++++++ - 3 files changed, 89 insertions(+) - create mode 100644 drivers/nvmem/brcm_nvram.c - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -278,4 +278,13 @@ config NVMEM_RMEM - - This driver can also be built as a module. If so, the module - will be called nvmem-rmem. -+ -+config NVMEM_BRCM_NVRAM -+ tristate "Broadcom's NVRAM support" -+ depends on ARCH_BCM_5301X || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ This driver provides support for Broadcom's NVRAM that can be accessed -+ using I/O mapping. -+ - endif ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -57,3 +57,5 @@ obj-$(CONFIG_SPRD_EFUSE) += nvmem_sprd_e - nvmem_sprd_efuse-y := sprd-efuse.o - obj-$(CONFIG_NVMEM_RMEM) += nvmem-rmem.o - nvmem-rmem-y := rmem.o -+obj-$(CONFIG_NVMEM_BRCM_NVRAM) += nvmem_brcm_nvram.o -+nvmem_brcm_nvram-y := brcm_nvram.o ---- /dev/null -+++ b/drivers/nvmem/brcm_nvram.c -@@ -0,0 +1,78 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2021 Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+struct brcm_nvram { -+ struct device *dev; -+ void __iomem *base; -+}; -+ -+static int brcm_nvram_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct brcm_nvram *priv = context; -+ u8 *dst = val; -+ -+ while (bytes--) -+ *dst++ = readb(priv->base + offset++); -+ -+ return 0; -+} -+ -+static int brcm_nvram_probe(struct platform_device *pdev) -+{ -+ struct nvmem_config config = { -+ .name = "brcm-nvram", -+ .reg_read = brcm_nvram_read, -+ }; -+ struct device *dev = &pdev->dev; -+ struct resource *res; -+ struct brcm_nvram *priv; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ priv->dev = dev; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ priv->base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(priv->base)) -+ return PTR_ERR(priv->base); -+ -+ config.dev = dev; -+ config.priv = priv; -+ config.size = resource_size(res); -+ -+ return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config)); -+} -+ -+static const struct of_device_id brcm_nvram_of_match_table[] = { -+ { .compatible = "brcm,nvram", }, -+ {}, -+}; -+ -+static struct platform_driver brcm_nvram_driver = { -+ .probe = brcm_nvram_probe, -+ .driver = { -+ .name = "brcm_nvram", -+ .of_match_table = brcm_nvram_of_match_table, -+ }, -+}; -+ -+static int __init brcm_nvram_init(void) -+{ -+ return platform_driver_register(&brcm_nvram_driver); -+} -+ -+subsys_initcall_sync(brcm_nvram_init); -+ -+MODULE_AUTHOR("Rafał Miłecki"); -+MODULE_LICENSE("GPL"); -+MODULE_DEVICE_TABLE(of, brcm_nvram_of_match_table); diff --git a/target/linux/generic/backport-5.10/803-v5.13-0004-nvmem-core-Add-functions-to-make-number-reading-easy.patch b/target/linux/generic/backport-5.10/803-v5.13-0004-nvmem-core-Add-functions-to-make-number-reading-easy.patch deleted file mode 100644 index f791aea8ae..0000000000 --- a/target/linux/generic/backport-5.10/803-v5.13-0004-nvmem-core-Add-functions-to-make-number-reading-easy.patch +++ /dev/null @@ -1,174 +0,0 @@ -From a28e824fb8270eda43fd0f65c2a5fdf33f55c5eb Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Tue, 30 Mar 2021 12:12:37 +0100 -Subject: [PATCH] nvmem: core: Add functions to make number reading easy - -Sometimes the clients of nvmem just want to get a number out of -nvmem. They don't want to think about exactly how many bytes the nvmem -cell took up. They just want the number. Let's make it easy. - -In general this concept is useful because nvmem space is precious and -usually the fewest bits are allocated that will hold a given value on -a given system. However, even though small numbers might be fine on -one system that doesn't mean that logically the number couldn't be -bigger. Imagine nvmem containing a max frequency for a component. On -one system perhaps that fits in 16 bits. On another system it might -fit in 32 bits. The code reading this number doesn't care--it just -wants the number. - -We'll provide two functions: nvmem_cell_read_variable_le_u32() and -nvmem_cell_read_variable_le_u64(). - -Comparing these to the existing functions like nvmem_cell_read_u32(): -* These new functions have no problems if the value was stored in - nvmem in fewer bytes. It's OK to use these function as long as the - value stored will fit in 32-bits (or 64-bits). -* These functions avoid problems that the earlier APIs had with bit - offsets. For instance, you can't use nvmem_cell_read_u32() to read a - value has nbits=32 and bit_offset=4 because the nvmem cell must be - at least 5 bytes big to hold this value. The new API accounts for - this and works fine. -* These functions make it very explicit that they assume that the - number was stored in little endian format. The old functions made - this assumption whenever bit_offset was non-zero (see - nvmem_shift_read_buffer_in_place()) but didn't whenever the - bit_offset was zero. - -NOTE: it's assumed that we don't need an 8-bit or 16-bit version of -this function. The 32-bit version of the function can be used to read -8-bit or 16-bit data. - -At the moment, I'm only adding the "unsigned" versions of these -functions, but if it ends up being useful someone could add a "signed" -version that did 2's complement sign extension. - -At the moment, I'm only adding the "little endian" versions of these -functions. Adding the "big endian" version would require adding "big -endian" support to nvmem_shift_read_buffer_in_place(). - -Signed-off-by: Douglas Anderson -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210330111241.19401-7-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 95 ++++++++++++++++++++++++++++++++++ - include/linux/nvmem-consumer.h | 4 ++ - 2 files changed, 99 insertions(+) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -1613,6 +1613,101 @@ int nvmem_cell_read_u64(struct device *d - } - EXPORT_SYMBOL_GPL(nvmem_cell_read_u64); - -+static void *nvmem_cell_read_variable_common(struct device *dev, -+ const char *cell_id, -+ size_t max_len, size_t *len) -+{ -+ struct nvmem_cell *cell; -+ int nbits; -+ void *buf; -+ -+ cell = nvmem_cell_get(dev, cell_id); -+ if (IS_ERR(cell)) -+ return cell; -+ -+ nbits = cell->nbits; -+ buf = nvmem_cell_read(cell, len); -+ nvmem_cell_put(cell); -+ if (IS_ERR(buf)) -+ return buf; -+ -+ /* -+ * If nbits is set then nvmem_cell_read() can significantly exaggerate -+ * the length of the real data. Throw away the extra junk. -+ */ -+ if (nbits) -+ *len = DIV_ROUND_UP(nbits, 8); -+ -+ if (*len > max_len) { -+ kfree(buf); -+ return ERR_PTR(-ERANGE); -+ } -+ -+ return buf; -+} -+ -+/** -+ * nvmem_cell_read_variable_le_u32() - Read up to 32-bits of data as a little endian number. -+ * -+ * @dev: Device that requests the nvmem cell. -+ * @cell_id: Name of nvmem cell to read. -+ * @val: pointer to output value. -+ * -+ * Return: 0 on success or negative errno. -+ */ -+int nvmem_cell_read_variable_le_u32(struct device *dev, const char *cell_id, -+ u32 *val) -+{ -+ size_t len; -+ u8 *buf; -+ int i; -+ -+ buf = nvmem_cell_read_variable_common(dev, cell_id, sizeof(*val), &len); -+ if (IS_ERR(buf)) -+ return PTR_ERR(buf); -+ -+ /* Copy w/ implicit endian conversion */ -+ *val = 0; -+ for (i = 0; i < len; i++) -+ *val |= buf[i] << (8 * i); -+ -+ kfree(buf); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(nvmem_cell_read_variable_le_u32); -+ -+/** -+ * nvmem_cell_read_variable_le_u64() - Read up to 64-bits of data as a little endian number. -+ * -+ * @dev: Device that requests the nvmem cell. -+ * @cell_id: Name of nvmem cell to read. -+ * @val: pointer to output value. -+ * -+ * Return: 0 on success or negative errno. -+ */ -+int nvmem_cell_read_variable_le_u64(struct device *dev, const char *cell_id, -+ u64 *val) -+{ -+ size_t len; -+ u8 *buf; -+ int i; -+ -+ buf = nvmem_cell_read_variable_common(dev, cell_id, sizeof(*val), &len); -+ if (IS_ERR(buf)) -+ return PTR_ERR(buf); -+ -+ /* Copy w/ implicit endian conversion */ -+ *val = 0; -+ for (i = 0; i < len; i++) -+ *val |= buf[i] << (8 * i); -+ -+ kfree(buf); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(nvmem_cell_read_variable_le_u64); -+ - /** - * nvmem_device_cell_read() - Read a given nvmem device and cell - * ---- a/include/linux/nvmem-consumer.h -+++ b/include/linux/nvmem-consumer.h -@@ -65,6 +65,10 @@ int nvmem_cell_read_u8(struct device *de - int nvmem_cell_read_u16(struct device *dev, const char *cell_id, u16 *val); - int nvmem_cell_read_u32(struct device *dev, const char *cell_id, u32 *val); - int nvmem_cell_read_u64(struct device *dev, const char *cell_id, u64 *val); -+int nvmem_cell_read_variable_le_u32(struct device *dev, const char *cell_id, -+ u32 *val); -+int nvmem_cell_read_variable_le_u64(struct device *dev, const char *cell_id, -+ u64 *val); - - /* direct nvmem device read/write interface */ - struct nvmem_device *nvmem_device_get(struct device *dev, const char *name); diff --git a/target/linux/generic/backport-5.10/803-v5.13-0005-nvmem-core-Fix-unintentional-sign-extension-issue.patch b/target/linux/generic/backport-5.10/803-v5.13-0005-nvmem-core-Fix-unintentional-sign-extension-issue.patch deleted file mode 100644 index 958dc65073..0000000000 --- a/target/linux/generic/backport-5.10/803-v5.13-0005-nvmem-core-Fix-unintentional-sign-extension-issue.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 55022fdeace8e432f008787ce03703bdcc9c3ca9 Mon Sep 17 00:00:00 2001 -From: Colin Ian King -Date: Tue, 30 Mar 2021 12:12:38 +0100 -Subject: [PATCH] nvmem: core: Fix unintentional sign extension issue - -The shifting of the u8 integer buf[3] by 24 bits to the left will -be promoted to a 32 bit signed int and then sign-extended to a -u64. In the event that the top bit of buf[3] is set then all -then all the upper 32 bits of the u64 end up as also being set -because of the sign-extension. Fix this by casting buf[i] to -a u64 before the shift. - -Fixes: a28e824fb827 ("nvmem: core: Add functions to make number reading easy") -Reviewed-by: Douglas Anderson -Signed-off-by: Colin Ian King -Signed-off-by: Srinivas Kandagatla -Addresses-Coverity: ("Unintended sign extension") -Link: https://lore.kernel.org/r/20210330111241.19401-8-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -1700,7 +1700,7 @@ int nvmem_cell_read_variable_le_u64(stru - /* Copy w/ implicit endian conversion */ - *val = 0; - for (i = 0; i < len; i++) -- *val |= buf[i] << (8 * i); -+ *val |= (uint64_t)buf[i] << (8 * i); - - kfree(buf); - diff --git a/target/linux/generic/backport-5.10/803-v5.13-0006-nvmem-rmem-fix-undefined-reference-to-memremap.patch b/target/linux/generic/backport-5.10/803-v5.13-0006-nvmem-rmem-fix-undefined-reference-to-memremap.patch deleted file mode 100644 index 9e13fb6708..0000000000 --- a/target/linux/generic/backport-5.10/803-v5.13-0006-nvmem-rmem-fix-undefined-reference-to-memremap.patch +++ /dev/null @@ -1,29 +0,0 @@ -From cc1bc56fdc76a55bb8fae9a145a2e60bf22fb129 Mon Sep 17 00:00:00 2001 -From: Srinivas Kandagatla -Date: Tue, 30 Mar 2021 12:12:39 +0100 -Subject: [PATCH] nvmem: rmem: fix undefined reference to memremap - -Fix below error reporte by kernel test robot -rmem.c:(.text+0x14e): undefined reference to memremap -s390x-linux-gnu-ld: rmem.c:(.text+0x1b6): undefined reference to memunmap - -Fixes: 5a3fa75a4d9c ("nvmem: Add driver to expose reserved memory as nvmem") -Reported-by: kernel test robot -Reviewed-by: Nicolas Saenz Julienne -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210330111241.19401-9-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -272,6 +272,7 @@ config SPRD_EFUSE - - config NVMEM_RMEM - tristate "Reserved Memory Based Driver Support" -+ depends on HAS_IOMEM - help - This driver maps reserved memory into an nvmem device. It might be - useful to expose information left by firmware in memory. diff --git a/target/linux/generic/backport-5.10/803-v5.13-0007-nvmem-qfprom-Add-support-for-fuse-blowing-on-sc7280.patch b/target/linux/generic/backport-5.10/803-v5.13-0007-nvmem-qfprom-Add-support-for-fuse-blowing-on-sc7280.patch deleted file mode 100644 index 0e75d4c93d..0000000000 --- a/target/linux/generic/backport-5.10/803-v5.13-0007-nvmem-qfprom-Add-support-for-fuse-blowing-on-sc7280.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 5a1bea2a2572ce5eb4bdcf432a6929681ee381f2 Mon Sep 17 00:00:00 2001 -From: Rajendra Nayak -Date: Tue, 30 Mar 2021 12:12:41 +0100 -Subject: [PATCH] nvmem: qfprom: Add support for fuse blowing on sc7280 - -Handle the differences across LDO voltage needed for blowing fuses, -and the blow timer value, identified using a minor version of 15 -on sc7280. - -Signed-off-by: Rajendra Nayak -Signed-off-by: Ravi Kumar Bokka -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210330111241.19401-11-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qfprom.c | 27 +++++++++++++++++++++++++-- - 1 file changed, 25 insertions(+), 2 deletions(-) - ---- a/drivers/nvmem/qfprom.c -+++ b/drivers/nvmem/qfprom.c -@@ -45,11 +45,13 @@ MODULE_PARM_DESC(read_raw_data, "Read ra - * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow. - * @qfprom_blow_set_freq: The frequency required to set when we start the - * fuse blowing. -+ * @qfprom_blow_uV: LDO voltage to be set when doing efuse blow - */ - struct qfprom_soc_data { - u32 accel_value; - u32 qfprom_blow_timer_value; - u32 qfprom_blow_set_freq; -+ int qfprom_blow_uV; - }; - - /** -@@ -111,6 +113,15 @@ static const struct qfprom_soc_compatibl - .nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout) - }; - -+static const struct nvmem_keepout sc7280_qfprom_keepout[] = { -+ {.start = 0x128, .end = 0x148}, -+ {.start = 0x238, .end = 0x248} -+}; -+ -+static const struct qfprom_soc_compatible_data sc7280_qfprom = { -+ .keepout = sc7280_qfprom_keepout, -+ .nkeepout = ARRAY_SIZE(sc7280_qfprom_keepout) -+}; - /** - * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing. - * @priv: Our driver data. -@@ -168,6 +179,7 @@ static int qfprom_enable_fuse_blowing(co - struct qfprom_touched_values *old) - { - int ret; -+ int qfprom_blow_uV = priv->soc_data->qfprom_blow_uV; - - ret = clk_prepare_enable(priv->secclk); - if (ret) { -@@ -187,9 +199,9 @@ static int qfprom_enable_fuse_blowing(co - * a rail shared do don't specify a max--regulator constraints - * will handle. - */ -- ret = regulator_set_voltage(priv->vcc, 1800000, INT_MAX); -+ ret = regulator_set_voltage(priv->vcc, qfprom_blow_uV, INT_MAX); - if (ret) { -- dev_err(priv->dev, "Failed to set 1.8 voltage\n"); -+ dev_err(priv->dev, "Failed to set %duV\n", qfprom_blow_uV); - goto err_clk_rate_set; - } - -@@ -311,6 +323,14 @@ static const struct qfprom_soc_data qfpr - .accel_value = 0xD10, - .qfprom_blow_timer_value = 25, - .qfprom_blow_set_freq = 4800000, -+ .qfprom_blow_uV = 1800000, -+}; -+ -+static const struct qfprom_soc_data qfprom_7_15_data = { -+ .accel_value = 0xD08, -+ .qfprom_blow_timer_value = 24, -+ .qfprom_blow_set_freq = 4800000, -+ .qfprom_blow_uV = 1900000, - }; - - static int qfprom_probe(struct platform_device *pdev) -@@ -379,6 +399,8 @@ static int qfprom_probe(struct platform_ - - if (major_version == 7 && minor_version == 8) - priv->soc_data = &qfprom_7_8_data; -+ if (major_version == 7 && minor_version == 15) -+ priv->soc_data = &qfprom_7_15_data; - - priv->vcc = devm_regulator_get(&pdev->dev, "vcc"); - if (IS_ERR(priv->vcc)) -@@ -405,6 +427,7 @@ static int qfprom_probe(struct platform_ - static const struct of_device_id qfprom_of_match[] = { - { .compatible = "qcom,qfprom",}, - { .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom}, -+ { .compatible = "qcom,sc7280-qfprom", .data = &sc7280_qfprom}, - {/* sentinel */}, - }; - MODULE_DEVICE_TABLE(of, qfprom_of_match); diff --git a/target/linux/generic/backport-5.10/804-v5.14-0001-nvmem-core-allow-specifying-of_node.patch b/target/linux/generic/backport-5.10/804-v5.14-0001-nvmem-core-allow-specifying-of_node.patch deleted file mode 100644 index f3debe84f3..0000000000 --- a/target/linux/generic/backport-5.10/804-v5.14-0001-nvmem-core-allow-specifying-of_node.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 1333a6779501f4cc662ff5c8b36b0a22f3a7ddc6 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Sat, 24 Apr 2021 13:06:04 +0200 -Subject: [PATCH] nvmem: core: allow specifying of_node - -Until now, the of_node of the parent device is used. Some devices -provide more than just the nvmem provider. To avoid name space clashes, -add a way to allow specifying the nvmem cells in subnodes. Consider the -following example: - - flash@0 { - compatible = "jedec,spi-nor"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x000000 0x010000>; - }; - }; - - otp { - compatible = "user-otp"; - #address-cells = <1>; - #size-cells = <1>; - - serial-number@0 { - reg = <0x0 0x8>; - }; - }; - }; - -There the nvmem provider might be the MTD partition or the OTP region of -the flash. - -Add a new config->of_node parameter, which if set, will be used instead -of the parent's of_node. - -Signed-off-by: Michael Walle -Acked-by: Srinivas Kandagatla -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210424110608.15748-2-michael@walle.cc ---- - drivers/nvmem/core.c | 4 +++- - include/linux/nvmem-provider.h | 2 ++ - 2 files changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -795,7 +795,9 @@ struct nvmem_device *nvmem_register(cons - nvmem->reg_write = config->reg_write; - nvmem->keepout = config->keepout; - nvmem->nkeepout = config->nkeepout; -- if (!config->no_of_node) -+ if (config->of_node) -+ nvmem->dev.of_node = config->of_node; -+ else if (!config->no_of_node) - nvmem->dev.of_node = config->dev->of_node; - - switch (config->id) { ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -57,6 +57,7 @@ struct nvmem_keepout { - * @type: Type of the nvmem storage - * @read_only: Device is read-only. - * @root_only: Device is accessibly to root only. -+ * @of_node: If given, this will be used instead of the parent's of_node. - * @no_of_node: Device should not use the parent's of_node even if it's !NULL. - * @reg_read: Callback to read data. - * @reg_write: Callback to write data. -@@ -85,6 +86,7 @@ struct nvmem_config { - enum nvmem_type type; - bool read_only; - bool root_only; -+ struct device_node *of_node; - bool ignore_wp; - bool no_of_node; - nvmem_reg_read_t reg_read; diff --git a/target/linux/generic/backport-5.10/804-v5.14-0002-nvmem-sprd-Fix-an-error-message.patch b/target/linux/generic/backport-5.10/804-v5.14-0002-nvmem-sprd-Fix-an-error-message.patch deleted file mode 100644 index db88328a11..0000000000 --- a/target/linux/generic/backport-5.10/804-v5.14-0002-nvmem-sprd-Fix-an-error-message.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 20be064ec864086bca7a4eb62c772a397b44afb7 Mon Sep 17 00:00:00 2001 -From: Christophe JAILLET -Date: Fri, 7 May 2021 19:02:48 +0200 -Subject: [PATCH] nvmem: sprd: Fix an error message - -'ret' is known to be 0 here. -The expected error status is stored in 'status', so use it instead. - -Also change %d in %u, because status is an u32, not a int. - -Fixes: 096030e7f449 ("nvmem: sprd: Add Spreadtrum SoCs eFuse support") -Acked-by: Chunyan Zhang -Signed-off-by: Christophe JAILLET -Link: https://lore.kernel.org/r/5bc44aace2fe7e1c91d8b35c8fe31e7134ceab2c.1620406852.git.christophe.jaillet@wanadoo.fr -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/sprd-efuse.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/sprd-efuse.c -+++ b/drivers/nvmem/sprd-efuse.c -@@ -234,7 +234,7 @@ static int sprd_efuse_raw_prog(struct sp - status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG); - if (status) { - dev_err(efuse->dev, -- "write error status %d of block %d\n", ret, blk); -+ "write error status %u of block %d\n", status, blk); - - writel(SPRD_EFUSE_ERR_CLR_MASK, - efuse->base + SPRD_EFUSE_ERR_CLR); diff --git a/target/linux/generic/backport-5.10/804-v5.14-0003-nvmem-sunxi_sid-Set-type-to-OTP.patch b/target/linux/generic/backport-5.10/804-v5.14-0003-nvmem-sunxi_sid-Set-type-to-OTP.patch deleted file mode 100644 index 37694e5424..0000000000 --- a/target/linux/generic/backport-5.10/804-v5.14-0003-nvmem-sunxi_sid-Set-type-to-OTP.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 78a005a22d5608b266eafa011b093a33284c52ce Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 11 Jun 2021 09:33:45 +0100 -Subject: [PATCH] nvmem: sunxi_sid: Set type to OTP - -This device currently reports an "Unknown" type in sysfs. -Since it is an eFuse hardware device, set its type to OTP. - -Signed-off-by: Samuel Holland -Acked-by: Chen-Yu Tsai -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210611083348.20170-7-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/sunxi_sid.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/nvmem/sunxi_sid.c -+++ b/drivers/nvmem/sunxi_sid.c -@@ -142,6 +142,7 @@ static int sunxi_sid_probe(struct platfo - - nvmem_cfg->dev = dev; - nvmem_cfg->name = "sunxi-sid"; -+ nvmem_cfg->type = NVMEM_TYPE_OTP; - nvmem_cfg->read_only = true; - nvmem_cfg->size = cfg->size; - nvmem_cfg->word_size = 1; diff --git a/target/linux/generic/backport-5.10/804-v5.14-0004-nvmem-qfprom-minor-nit-fixes.patch b/target/linux/generic/backport-5.10/804-v5.14-0004-nvmem-qfprom-minor-nit-fixes.patch deleted file mode 100644 index bcab3e41fd..0000000000 --- a/target/linux/generic/backport-5.10/804-v5.14-0004-nvmem-qfprom-minor-nit-fixes.patch +++ /dev/null @@ -1,46 +0,0 @@ -From c813bb37bd32cb967060a2c573fae4ea518d32eb Mon Sep 17 00:00:00 2001 -From: Rajendra Nayak -Date: Fri, 11 Jun 2021 09:33:46 +0100 -Subject: [PATCH] nvmem: qfprom: minor nit fixes - -Fix a missed newline, change an 'if' to 'else if' and update -a comment which is stale after the merge of '5a1bea2a: nvmem: -qfprom: Add support for fuseblowing on sc7280' - -Signed-off-by: Rajendra Nayak -Reviewed-by: Douglas Anderson -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210611083348.20170-8-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qfprom.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/nvmem/qfprom.c -+++ b/drivers/nvmem/qfprom.c -@@ -122,6 +122,7 @@ static const struct qfprom_soc_compatibl - .keepout = sc7280_qfprom_keepout, - .nkeepout = ARRAY_SIZE(sc7280_qfprom_keepout) - }; -+ - /** - * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing. - * @priv: Our driver data. -@@ -195,7 +196,7 @@ static int qfprom_enable_fuse_blowing(co - } - - /* -- * Hardware requires 1.8V min for fuse blowing; this may be -+ * Hardware requires a min voltage for fuse blowing; this may be - * a rail shared do don't specify a max--regulator constraints - * will handle. - */ -@@ -399,7 +400,7 @@ static int qfprom_probe(struct platform_ - - if (major_version == 7 && minor_version == 8) - priv->soc_data = &qfprom_7_8_data; -- if (major_version == 7 && minor_version == 15) -+ else if (major_version == 7 && minor_version == 15) - priv->soc_data = &qfprom_7_15_data; - - priv->vcc = devm_regulator_get(&pdev->dev, "vcc"); diff --git a/target/linux/generic/backport-5.10/804-v5.14-0005-nvmem-core-constify-nvmem_cell_read_variable_common-.patch b/target/linux/generic/backport-5.10/804-v5.14-0005-nvmem-core-constify-nvmem_cell_read_variable_common-.patch deleted file mode 100644 index 3162a5362e..0000000000 --- a/target/linux/generic/backport-5.10/804-v5.14-0005-nvmem-core-constify-nvmem_cell_read_variable_common-.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 1f7b4d87874624f4beb25253900a25306a193b8b Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Fri, 11 Jun 2021 09:33:47 +0100 -Subject: [PATCH] nvmem: core: constify nvmem_cell_read_variable_common() - return value - -The caller doesn't modify the memory pointed to by the pointer so it -can be const. - -Suggested-by: Stephen Boyd -Signed-off-by: Douglas Anderson -Reviewed-by: Stephen Boyd -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210611083348.20170-9-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -1615,9 +1615,9 @@ int nvmem_cell_read_u64(struct device *d - } - EXPORT_SYMBOL_GPL(nvmem_cell_read_u64); - --static void *nvmem_cell_read_variable_common(struct device *dev, -- const char *cell_id, -- size_t max_len, size_t *len) -+static const void *nvmem_cell_read_variable_common(struct device *dev, -+ const char *cell_id, -+ size_t max_len, size_t *len) - { - struct nvmem_cell *cell; - int nbits; -@@ -1661,7 +1661,7 @@ int nvmem_cell_read_variable_le_u32(stru - u32 *val) - { - size_t len; -- u8 *buf; -+ const u8 *buf; - int i; - - buf = nvmem_cell_read_variable_common(dev, cell_id, sizeof(*val), &len); -@@ -1692,7 +1692,7 @@ int nvmem_cell_read_variable_le_u64(stru - u64 *val) - { - size_t len; -- u8 *buf; -+ const u8 *buf; - int i; - - buf = nvmem_cell_read_variable_common(dev, cell_id, sizeof(*val), &len); diff --git a/target/linux/generic/backport-5.10/804-v5.14-0006-nvmem-qfprom-Improve-the-comment-about-regulator-set.patch b/target/linux/generic/backport-5.10/804-v5.14-0006-nvmem-qfprom-Improve-the-comment-about-regulator-set.patch deleted file mode 100644 index d7ef8e620f..0000000000 --- a/target/linux/generic/backport-5.10/804-v5.14-0006-nvmem-qfprom-Improve-the-comment-about-regulator-set.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 989f77e3fdee2e8f414dd1da9b6397d8763d414e Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Fri, 11 Jun 2021 09:33:48 +0100 -Subject: [PATCH] nvmem: qfprom: Improve the comment about regulator setting - -In review feedback Joe Perches found the existing comment -confusing. Let's use something based on the wording proposed by Joe. - -Suggested-by: Joe Perches -Signed-off-by: Douglas Anderson -Reviewed-by: Stephen Boyd -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210611083348.20170-10-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qfprom.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/nvmem/qfprom.c -+++ b/drivers/nvmem/qfprom.c -@@ -196,9 +196,9 @@ static int qfprom_enable_fuse_blowing(co - } - - /* -- * Hardware requires a min voltage for fuse blowing; this may be -- * a rail shared do don't specify a max--regulator constraints -- * will handle. -+ * Hardware requires a minimum voltage for fuse blowing. -+ * This may be a shared rail so don't specify a maximum. -+ * Regulator constraints will cap to the actual maximum. - */ - ret = regulator_set_voltage(priv->vcc, qfprom_blow_uV, INT_MAX); - if (ret) { diff --git a/target/linux/generic/backport-5.10/804-v5.14-0007-nvmem-add-NVMEM_TYPE_FRAM.patch b/target/linux/generic/backport-5.10/804-v5.14-0007-nvmem-add-NVMEM_TYPE_FRAM.patch deleted file mode 100644 index 06c541b8e6..0000000000 --- a/target/linux/generic/backport-5.10/804-v5.14-0007-nvmem-add-NVMEM_TYPE_FRAM.patch +++ /dev/null @@ -1,36 +0,0 @@ -From: Rafał Miłecki -Subject: [PATCH] nvmem: add NVMEM_TYPE_FRAM - -Signed-off-by: Rafał Miłecki ---- - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -180,6 +180,7 @@ static const char * const nvmem_type_str - [NVMEM_TYPE_EEPROM] = "EEPROM", - [NVMEM_TYPE_OTP] = "OTP", - [NVMEM_TYPE_BATTERY_BACKED] = "Battery backed", -+ [NVMEM_TYPE_FRAM] = "FRAM", - }; - - #ifdef CONFIG_DEBUG_LOCK_ALLOC -@@ -361,6 +362,9 @@ static int nvmem_sysfs_setup_compat(stru - if (!config->base_dev) - return -EINVAL; - -+ if (config->type == NVMEM_TYPE_FRAM) -+ bin_attr_nvmem_eeprom_compat.attr.name = "fram"; -+ - nvmem->eeprom = bin_attr_nvmem_eeprom_compat; - nvmem->eeprom.attr.mode = nvmem_bin_attr_get_umode(nvmem); - nvmem->eeprom.size = nvmem->size; ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -25,6 +25,7 @@ enum nvmem_type { - NVMEM_TYPE_EEPROM, - NVMEM_TYPE_OTP, - NVMEM_TYPE_BATTERY_BACKED, -+ NVMEM_TYPE_FRAM, - }; - - #define NVMEM_DEVID_NONE (-1) diff --git a/target/linux/generic/backport-5.10/805-v5.15-0002-nvmem-qfprom-sc7280-Handle-the-additional-power-doma.patch b/target/linux/generic/backport-5.10/805-v5.15-0002-nvmem-qfprom-sc7280-Handle-the-additional-power-doma.patch deleted file mode 100644 index b71edd0306..0000000000 --- a/target/linux/generic/backport-5.10/805-v5.15-0002-nvmem-qfprom-sc7280-Handle-the-additional-power-doma.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 7b808449f572d07bee840cd9da7e2fe6a1b8f4b5 Mon Sep 17 00:00:00 2001 -From: Rajendra Nayak -Date: Fri, 6 Aug 2021 09:59:46 +0100 -Subject: [PATCH] nvmem: qfprom: sc7280: Handle the additional power-domains - vote - -On sc7280, to reliably blow fuses, we need an additional vote -on max performance state of 'MX' power-domain. -Add support for power-domain performance state voting in the -driver. - -Reviewed-by: Douglas Anderson -Signed-off-by: Rajendra Nayak -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210806085947.22682-4-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qfprom.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/drivers/nvmem/qfprom.c -+++ b/drivers/nvmem/qfprom.c -@@ -12,6 +12,8 @@ - #include - #include - #include -+#include -+#include - #include - #include - -@@ -142,6 +144,9 @@ static void qfprom_disable_fuse_blowing( - writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET); - writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET); - -+ dev_pm_genpd_set_performance_state(priv->dev, 0); -+ pm_runtime_put(priv->dev); -+ - /* - * This may be a shared rail and may be able to run at a lower rate - * when we're not blowing fuses. At the moment, the regulator framework -@@ -212,6 +217,14 @@ static int qfprom_enable_fuse_blowing(co - goto err_clk_rate_set; - } - -+ ret = pm_runtime_get_sync(priv->dev); -+ if (ret < 0) { -+ pm_runtime_put_noidle(priv->dev); -+ dev_err(priv->dev, "Failed to enable power-domain\n"); -+ goto err_reg_enable; -+ } -+ dev_pm_genpd_set_performance_state(priv->dev, INT_MAX); -+ - old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET); - old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET); - writel(priv->soc_data->qfprom_blow_timer_value, -@@ -221,6 +234,8 @@ static int qfprom_enable_fuse_blowing(co - - return 0; - -+err_reg_enable: -+ regulator_disable(priv->vcc); - err_clk_rate_set: - clk_set_rate(priv->secclk, old->clk_rate); - err_clk_prepared: -@@ -320,6 +335,11 @@ static int qfprom_reg_read(void *context - return 0; - } - -+static void qfprom_runtime_disable(void *data) -+{ -+ pm_runtime_disable(data); -+} -+ - static const struct qfprom_soc_data qfprom_7_8_data = { - .accel_value = 0xD10, - .qfprom_blow_timer_value = 25, -@@ -420,6 +440,11 @@ static int qfprom_probe(struct platform_ - econfig.reg_write = qfprom_reg_write; - } - -+ pm_runtime_enable(dev); -+ ret = devm_add_action_or_reset(dev, qfprom_runtime_disable, dev); -+ if (ret) -+ return ret; -+ - nvmem = devm_nvmem_register(dev, &econfig); - - return PTR_ERR_OR_ZERO(nvmem); diff --git a/target/linux/generic/backport-5.10/805-v5.15-0003-nvmem-core-fix-error-handling-while-validating-keepo.patch b/target/linux/generic/backport-5.10/805-v5.15-0003-nvmem-core-fix-error-handling-while-validating-keepo.patch deleted file mode 100644 index 7951cc7300..0000000000 --- a/target/linux/generic/backport-5.10/805-v5.15-0003-nvmem-core-fix-error-handling-while-validating-keepo.patch +++ /dev/null @@ -1,36 +0,0 @@ -From de0534df93474f268486c486ea7e01b44a478026 Mon Sep 17 00:00:00 2001 -From: Srinivas Kandagatla -Date: Fri, 6 Aug 2021 09:59:47 +0100 -Subject: [PATCH] nvmem: core: fix error handling while validating keepout - regions - -Current error path on failure of validating keepout regions is calling -put_device, eventhough the device is not even registered at that point. - -Fix this by adding proper error handling of freeing ida and nvmem. - -Fixes: fd3bb8f54a88 ("nvmem: core: Add support for keepout regions") -Cc: -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210806085947.22682-5-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -850,8 +850,11 @@ struct nvmem_device *nvmem_register(cons - - if (nvmem->nkeepout) { - rval = nvmem_validate_keepouts(nvmem); -- if (rval) -- goto err_put_device; -+ if (rval) { -+ ida_free(&nvmem_ida, nvmem->id); -+ kfree(nvmem); -+ return ERR_PTR(rval); -+ } - } - - dev_dbg(&nvmem->dev, "Registering nvmem device %s\n", config->name); diff --git a/target/linux/generic/backport-5.10/805-v5.15-0004-nvmem-nintendo-otp-Add-new-driver-for-the-Wii-and-Wi.patch b/target/linux/generic/backport-5.10/805-v5.15-0004-nvmem-nintendo-otp-Add-new-driver-for-the-Wii-and-Wi.patch deleted file mode 100644 index 62d9e2aa0f..0000000000 --- a/target/linux/generic/backport-5.10/805-v5.15-0004-nvmem-nintendo-otp-Add-new-driver-for-the-Wii-and-Wi.patch +++ /dev/null @@ -1,191 +0,0 @@ -From 3683b761fe3a10ad18515acd5368dd601268cfe5 Mon Sep 17 00:00:00 2001 -From: Emmanuel Gil Peyrot -Date: Tue, 10 Aug 2021 16:30:36 +0100 -Subject: [PATCH] nvmem: nintendo-otp: Add new driver for the Wii and Wii U OTP -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This OTP is read-only and contains various keys used by the console to -decrypt, encrypt or verify various pieces of storage. - -Its size depends on the console, it is 128 bytes on the Wii and -1024 bytes on the Wii U (split into eight 128 bytes banks). - -It can be used directly by writing into one register and reading from -the other one, without any additional synchronisation. - -This driver was written based on reversed documentation, see: -https://wiiubrew.org/wiki/Hardware/OTP - -Tested-by: Jonathan Neuschäfer # on Wii -Tested-by: Emmanuel Gil Peyrot # on Wii U -Signed-off-by: Emmanuel Gil Peyrot -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20210810153036.1494-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 11 ++++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/nintendo-otp.c | 124 +++++++++++++++++++++++++++++++++++ - 3 files changed, 137 insertions(+) - create mode 100644 drivers/nvmem/nintendo-otp.c - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -107,6 +107,17 @@ config MTK_EFUSE - This driver can also be built as a module. If so, the module - will be called efuse-mtk. - -+config NVMEM_NINTENDO_OTP -+ tristate "Nintendo Wii and Wii U OTP Support" -+ help -+ This is a driver exposing the OTP of a Nintendo Wii or Wii U console. -+ -+ This memory contains common and per-console keys, signatures and -+ related data required to access peripherals. -+ -+ This driver can also be built as a module. If so, the module -+ will be called nvmem-nintendo-otp. -+ - config QCOM_QFPROM - tristate "QCOM QFPROM Support" - depends on ARCH_QCOM || COMPILE_TEST ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -23,6 +23,8 @@ obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem - nvmem_lpc18xx_otp-y := lpc18xx_otp.o - obj-$(CONFIG_NVMEM_MXS_OCOTP) += nvmem-mxs-ocotp.o - nvmem-mxs-ocotp-y := mxs-ocotp.o -+obj-$(CONFIG_NVMEM_NINTENDO_OTP) += nvmem-nintendo-otp.o -+nvmem-nintendo-otp-y := nintendo-otp.o - obj-$(CONFIG_MTK_EFUSE) += nvmem_mtk-efuse.o - nvmem_mtk-efuse-y := mtk-efuse.o - obj-$(CONFIG_QCOM_QFPROM) += nvmem_qfprom.o ---- /dev/null -+++ b/drivers/nvmem/nintendo-otp.c -@@ -0,0 +1,124 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Nintendo Wii and Wii U OTP driver -+ * -+ * This is a driver exposing the OTP of a Nintendo Wii or Wii U console. -+ * -+ * This memory contains common and per-console keys, signatures and -+ * related data required to access peripherals. -+ * -+ * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware/OTP -+ * -+ * Copyright (C) 2021 Emmanuel Gil Peyrot -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define HW_OTPCMD 0 -+#define HW_OTPDATA 4 -+#define OTP_READ 0x80000000 -+#define BANK_SIZE 128 -+#define WORD_SIZE 4 -+ -+struct nintendo_otp_priv { -+ void __iomem *regs; -+}; -+ -+struct nintendo_otp_devtype_data { -+ const char *name; -+ unsigned int num_banks; -+}; -+ -+static const struct nintendo_otp_devtype_data hollywood_otp_data = { -+ .name = "wii-otp", -+ .num_banks = 1, -+}; -+ -+static const struct nintendo_otp_devtype_data latte_otp_data = { -+ .name = "wiiu-otp", -+ .num_banks = 8, -+}; -+ -+static int nintendo_otp_reg_read(void *context, -+ unsigned int reg, void *_val, size_t bytes) -+{ -+ struct nintendo_otp_priv *priv = context; -+ u32 *val = _val; -+ int words = bytes / WORD_SIZE; -+ u32 bank, addr; -+ -+ while (words--) { -+ bank = (reg / BANK_SIZE) << 8; -+ addr = (reg / WORD_SIZE) % (BANK_SIZE / WORD_SIZE); -+ iowrite32be(OTP_READ | bank | addr, priv->regs + HW_OTPCMD); -+ *val++ = ioread32be(priv->regs + HW_OTPDATA); -+ reg += WORD_SIZE; -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id nintendo_otp_of_table[] = { -+ { .compatible = "nintendo,hollywood-otp", .data = &hollywood_otp_data }, -+ { .compatible = "nintendo,latte-otp", .data = &latte_otp_data }, -+ {/* sentinel */}, -+}; -+MODULE_DEVICE_TABLE(of, nintendo_otp_of_table); -+ -+static int nintendo_otp_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ const struct of_device_id *of_id = -+ of_match_device(nintendo_otp_of_table, dev); -+ struct resource *res; -+ struct nvmem_device *nvmem; -+ struct nintendo_otp_priv *priv; -+ -+ struct nvmem_config config = { -+ .stride = WORD_SIZE, -+ .word_size = WORD_SIZE, -+ .reg_read = nintendo_otp_reg_read, -+ .read_only = true, -+ .root_only = true, -+ }; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ priv->regs = devm_ioremap_resource(dev, res); -+ if (IS_ERR(priv->regs)) -+ return PTR_ERR(priv->regs); -+ -+ if (of_id->data) { -+ const struct nintendo_otp_devtype_data *data = of_id->data; -+ config.name = data->name; -+ config.size = data->num_banks * BANK_SIZE; -+ } -+ -+ config.dev = dev; -+ config.priv = priv; -+ -+ nvmem = devm_nvmem_register(dev, &config); -+ -+ return PTR_ERR_OR_ZERO(nvmem); -+} -+ -+static struct platform_driver nintendo_otp_driver = { -+ .probe = nintendo_otp_probe, -+ .driver = { -+ .name = "nintendo-otp", -+ .of_match_table = nintendo_otp_of_table, -+ }, -+}; -+module_platform_driver(nintendo_otp_driver); -+MODULE_AUTHOR("Emmanuel Gil Peyrot "); -+MODULE_DESCRIPTION("Nintendo Wii and Wii U OTP driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/generic/backport-5.10/805-v5.15-0005-nvmem-NVMEM_NINTENDO_OTP-should-depend-on-WII.patch b/target/linux/generic/backport-5.10/805-v5.15-0005-nvmem-NVMEM_NINTENDO_OTP-should-depend-on-WII.patch deleted file mode 100644 index 02f8b6c562..0000000000 --- a/target/linux/generic/backport-5.10/805-v5.15-0005-nvmem-NVMEM_NINTENDO_OTP-should-depend-on-WII.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 7af526c740bdbd5b4dcebba04ace5b3b0c07801f Mon Sep 17 00:00:00 2001 -From: Geert Uytterhoeven -Date: Tue, 14 Sep 2021 11:29:49 +0200 -Subject: [PATCH] nvmem: NVMEM_NINTENDO_OTP should depend on WII - -The Nintendo Wii and Wii U OTP is only present on Nintendo Wii and Wii U -consoles. Hence add a dependency on WII, to prevent asking the user -about this driver when configuring a kernel without Nintendo Wii and Wii -U console support. - -Fixes: 3683b761fe3a10ad ("nvmem: nintendo-otp: Add new driver for the Wii and Wii U OTP") -Reviewed-by: Emmanuel Gil Peyrot -Signed-off-by: Geert Uytterhoeven -Link: https://lore.kernel.org/r/01318920709dddc4d85fe895e2083ca0eee234d8.1631611652.git.geert+renesas@glider.be -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -109,6 +109,7 @@ config MTK_EFUSE - - config NVMEM_NINTENDO_OTP - tristate "Nintendo Wii and Wii U OTP Support" -+ depends on WII || COMPILE_TEST - help - This is a driver exposing the OTP of a Nintendo Wii or Wii U console. - diff --git a/target/linux/generic/backport-5.10/806-v5.16-0001-nvmem-core-rework-nvmem-cell-instance-creation.patch b/target/linux/generic/backport-5.10/806-v5.16-0001-nvmem-core-rework-nvmem-cell-instance-creation.patch deleted file mode 100644 index 0b87172b2d..0000000000 --- a/target/linux/generic/backport-5.10/806-v5.16-0001-nvmem-core-rework-nvmem-cell-instance-creation.patch +++ /dev/null @@ -1,456 +0,0 @@ -From 7ae6478b304bc004c3139b422665b0e23b57f05c Mon Sep 17 00:00:00 2001 -From: Srinivas Kandagatla -Date: Wed, 13 Oct 2021 14:19:55 +0100 -Subject: [PATCH] nvmem: core: rework nvmem cell instance creation - -In the existing design, we do not create a instance per nvmem cell consumer -but we directly refer cell from nvmem cell list that are added to provider. - -However this design has some limitations when consumers want to assign name -or connection id the nvmem cell instance, ex: via "nvmem-cell-names" or -id in nvmem_cell_get(id). - -Having a name associated with nvmem cell consumer instance will help -provider drivers in performing post processing of nvmem cell data if required -before data is seen by the consumers. This is pretty normal with some vendors -storing nvmem cells like mac-address in a vendor specific data layouts that -are not directly usable by the consumer drivers. - -With this patch nvmem cell will be created dynamically during nvmem_cell_get -and destroyed in nvmem_cell_put, allowing consumers to associate name with -nvmem cell consumer instance. - -With this patch a new struct nvmem_cell_entry replaces struct nvmem_cell -for storing nvmem cell information within the core. -This patch does not change nvmem-consumer interface based on nvmem_cell. - -Tested-by: Joakim Zhang -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20211013131957.30271-2-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 165 +++++++++++++++++++++++++++---------------- - 1 file changed, 105 insertions(+), 60 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -45,8 +45,7 @@ struct nvmem_device { - #define to_nvmem_device(d) container_of(d, struct nvmem_device, dev) - - #define FLAG_COMPAT BIT(0) -- --struct nvmem_cell { -+struct nvmem_cell_entry { - const char *name; - int offset; - int bytes; -@@ -57,6 +56,11 @@ struct nvmem_cell { - struct list_head node; - }; - -+struct nvmem_cell { -+ struct nvmem_cell_entry *entry; -+ const char *id; -+}; -+ - static DEFINE_MUTEX(nvmem_mutex); - static DEFINE_IDA(nvmem_ida); - -@@ -424,7 +428,7 @@ static struct bus_type nvmem_bus_type = - .name = "nvmem", - }; - --static void nvmem_cell_drop(struct nvmem_cell *cell) -+static void nvmem_cell_entry_drop(struct nvmem_cell_entry *cell) - { - blocking_notifier_call_chain(&nvmem_notifier, NVMEM_CELL_REMOVE, cell); - mutex_lock(&nvmem_mutex); -@@ -437,13 +441,13 @@ static void nvmem_cell_drop(struct nvmem - - static void nvmem_device_remove_all_cells(const struct nvmem_device *nvmem) - { -- struct nvmem_cell *cell, *p; -+ struct nvmem_cell_entry *cell, *p; - - list_for_each_entry_safe(cell, p, &nvmem->cells, node) -- nvmem_cell_drop(cell); -+ nvmem_cell_entry_drop(cell); - } - --static void nvmem_cell_add(struct nvmem_cell *cell) -+static void nvmem_cell_entry_add(struct nvmem_cell_entry *cell) - { - mutex_lock(&nvmem_mutex); - list_add_tail(&cell->node, &cell->nvmem->cells); -@@ -451,9 +455,9 @@ static void nvmem_cell_add(struct nvmem_ - blocking_notifier_call_chain(&nvmem_notifier, NVMEM_CELL_ADD, cell); - } - --static int nvmem_cell_info_to_nvmem_cell_nodup(struct nvmem_device *nvmem, -- const struct nvmem_cell_info *info, -- struct nvmem_cell *cell) -+static int nvmem_cell_info_to_nvmem_cell_entry_nodup(struct nvmem_device *nvmem, -+ const struct nvmem_cell_info *info, -+ struct nvmem_cell_entry *cell) - { - cell->nvmem = nvmem; - cell->offset = info->offset; -@@ -477,13 +481,13 @@ static int nvmem_cell_info_to_nvmem_cell - return 0; - } - --static int nvmem_cell_info_to_nvmem_cell(struct nvmem_device *nvmem, -- const struct nvmem_cell_info *info, -- struct nvmem_cell *cell) -+static int nvmem_cell_info_to_nvmem_cell_entry(struct nvmem_device *nvmem, -+ const struct nvmem_cell_info *info, -+ struct nvmem_cell_entry *cell) - { - int err; - -- err = nvmem_cell_info_to_nvmem_cell_nodup(nvmem, info, cell); -+ err = nvmem_cell_info_to_nvmem_cell_entry_nodup(nvmem, info, cell); - if (err) - return err; - -@@ -507,7 +511,7 @@ static int nvmem_add_cells(struct nvmem_ - const struct nvmem_cell_info *info, - int ncells) - { -- struct nvmem_cell **cells; -+ struct nvmem_cell_entry **cells; - int i, rval; - - cells = kcalloc(ncells, sizeof(*cells), GFP_KERNEL); -@@ -521,13 +525,13 @@ static int nvmem_add_cells(struct nvmem_ - goto err; - } - -- rval = nvmem_cell_info_to_nvmem_cell(nvmem, &info[i], cells[i]); -+ rval = nvmem_cell_info_to_nvmem_cell_entry(nvmem, &info[i], cells[i]); - if (rval) { - kfree(cells[i]); - goto err; - } - -- nvmem_cell_add(cells[i]); -+ nvmem_cell_entry_add(cells[i]); - } - - /* remove tmp array */ -@@ -536,7 +540,7 @@ static int nvmem_add_cells(struct nvmem_ - return 0; - err: - while (i--) -- nvmem_cell_drop(cells[i]); -+ nvmem_cell_entry_drop(cells[i]); - - kfree(cells); - -@@ -573,7 +577,7 @@ static int nvmem_add_cells_from_table(st - { - const struct nvmem_cell_info *info; - struct nvmem_cell_table *table; -- struct nvmem_cell *cell; -+ struct nvmem_cell_entry *cell; - int rval = 0, i; - - mutex_lock(&nvmem_cell_mutex); -@@ -588,15 +592,13 @@ static int nvmem_add_cells_from_table(st - goto out; - } - -- rval = nvmem_cell_info_to_nvmem_cell(nvmem, -- info, -- cell); -+ rval = nvmem_cell_info_to_nvmem_cell_entry(nvmem, info, cell); - if (rval) { - kfree(cell); - goto out; - } - -- nvmem_cell_add(cell); -+ nvmem_cell_entry_add(cell); - } - } - } -@@ -606,10 +608,10 @@ out: - return rval; - } - --static struct nvmem_cell * --nvmem_find_cell_by_name(struct nvmem_device *nvmem, const char *cell_id) -+static struct nvmem_cell_entry * -+nvmem_find_cell_entry_by_name(struct nvmem_device *nvmem, const char *cell_id) - { -- struct nvmem_cell *iter, *cell = NULL; -+ struct nvmem_cell_entry *iter, *cell = NULL; - - mutex_lock(&nvmem_mutex); - list_for_each_entry(iter, &nvmem->cells, node) { -@@ -680,7 +682,7 @@ static int nvmem_add_cells_from_of(struc - { - struct device_node *parent, *child; - struct device *dev = &nvmem->dev; -- struct nvmem_cell *cell; -+ struct nvmem_cell_entry *cell; - const __be32 *addr; - int len; - -@@ -729,7 +731,7 @@ static int nvmem_add_cells_from_of(struc - } - - cell->np = of_node_get(child); -- nvmem_cell_add(cell); -+ nvmem_cell_entry_add(cell); - } - - return 0; -@@ -1145,9 +1147,33 @@ struct nvmem_device *devm_nvmem_device_g - } - EXPORT_SYMBOL_GPL(devm_nvmem_device_get); - -+static struct nvmem_cell *nvmem_create_cell(struct nvmem_cell_entry *entry, const char *id) -+{ -+ struct nvmem_cell *cell; -+ const char *name = NULL; -+ -+ cell = kzalloc(sizeof(*cell), GFP_KERNEL); -+ if (!cell) -+ return ERR_PTR(-ENOMEM); -+ -+ if (id) { -+ name = kstrdup_const(id, GFP_KERNEL); -+ if (!name) { -+ kfree(cell); -+ return ERR_PTR(-ENOMEM); -+ } -+ } -+ -+ cell->id = name; -+ cell->entry = entry; -+ -+ return cell; -+} -+ - static struct nvmem_cell * - nvmem_cell_get_from_lookup(struct device *dev, const char *con_id) - { -+ struct nvmem_cell_entry *cell_entry; - struct nvmem_cell *cell = ERR_PTR(-ENOENT); - struct nvmem_cell_lookup *lookup; - struct nvmem_device *nvmem; -@@ -1172,11 +1198,15 @@ nvmem_cell_get_from_lookup(struct device - break; - } - -- cell = nvmem_find_cell_by_name(nvmem, -- lookup->cell_name); -- if (!cell) { -+ cell_entry = nvmem_find_cell_entry_by_name(nvmem, -+ lookup->cell_name); -+ if (!cell_entry) { - __nvmem_device_put(nvmem); - cell = ERR_PTR(-ENOENT); -+ } else { -+ cell = nvmem_create_cell(cell_entry, con_id); -+ if (IS_ERR(cell)) -+ __nvmem_device_put(nvmem); - } - break; - } -@@ -1187,10 +1217,10 @@ nvmem_cell_get_from_lookup(struct device - } - - #if IS_ENABLED(CONFIG_OF) --static struct nvmem_cell * --nvmem_find_cell_by_node(struct nvmem_device *nvmem, struct device_node *np) -+static struct nvmem_cell_entry * -+nvmem_find_cell_entry_by_node(struct nvmem_device *nvmem, struct device_node *np) - { -- struct nvmem_cell *iter, *cell = NULL; -+ struct nvmem_cell_entry *iter, *cell = NULL; - - mutex_lock(&nvmem_mutex); - list_for_each_entry(iter, &nvmem->cells, node) { -@@ -1220,6 +1250,7 @@ struct nvmem_cell *of_nvmem_cell_get(str - { - struct device_node *cell_np, *nvmem_np; - struct nvmem_device *nvmem; -+ struct nvmem_cell_entry *cell_entry; - struct nvmem_cell *cell; - int index = 0; - -@@ -1240,12 +1271,16 @@ struct nvmem_cell *of_nvmem_cell_get(str - if (IS_ERR(nvmem)) - return ERR_CAST(nvmem); - -- cell = nvmem_find_cell_by_node(nvmem, cell_np); -- if (!cell) { -+ cell_entry = nvmem_find_cell_entry_by_node(nvmem, cell_np); -+ if (!cell_entry) { - __nvmem_device_put(nvmem); - return ERR_PTR(-ENOENT); - } - -+ cell = nvmem_create_cell(cell_entry, id); -+ if (IS_ERR(cell)) -+ __nvmem_device_put(nvmem); -+ - return cell; - } - EXPORT_SYMBOL_GPL(of_nvmem_cell_get); -@@ -1351,13 +1386,17 @@ EXPORT_SYMBOL(devm_nvmem_cell_put); - */ - void nvmem_cell_put(struct nvmem_cell *cell) - { -- struct nvmem_device *nvmem = cell->nvmem; -+ struct nvmem_device *nvmem = cell->entry->nvmem; -+ -+ if (cell->id) -+ kfree_const(cell->id); - -+ kfree(cell); - __nvmem_device_put(nvmem); - } - EXPORT_SYMBOL_GPL(nvmem_cell_put); - --static void nvmem_shift_read_buffer_in_place(struct nvmem_cell *cell, void *buf) -+static void nvmem_shift_read_buffer_in_place(struct nvmem_cell_entry *cell, void *buf) - { - u8 *p, *b; - int i, extra, bit_offset = cell->bit_offset; -@@ -1391,8 +1430,8 @@ static void nvmem_shift_read_buffer_in_p - } - - static int __nvmem_cell_read(struct nvmem_device *nvmem, -- struct nvmem_cell *cell, -- void *buf, size_t *len) -+ struct nvmem_cell_entry *cell, -+ void *buf, size_t *len, const char *id) - { - int rc; - -@@ -1423,18 +1462,18 @@ static int __nvmem_cell_read(struct nvme - */ - void *nvmem_cell_read(struct nvmem_cell *cell, size_t *len) - { -- struct nvmem_device *nvmem = cell->nvmem; -+ struct nvmem_device *nvmem = cell->entry->nvmem; - u8 *buf; - int rc; - - if (!nvmem) - return ERR_PTR(-EINVAL); - -- buf = kzalloc(cell->bytes, GFP_KERNEL); -+ buf = kzalloc(cell->entry->bytes, GFP_KERNEL); - if (!buf) - return ERR_PTR(-ENOMEM); - -- rc = __nvmem_cell_read(nvmem, cell, buf, len); -+ rc = __nvmem_cell_read(nvmem, cell->entry, buf, len, cell->id); - if (rc) { - kfree(buf); - return ERR_PTR(rc); -@@ -1444,7 +1483,7 @@ void *nvmem_cell_read(struct nvmem_cell - } - EXPORT_SYMBOL_GPL(nvmem_cell_read); - --static void *nvmem_cell_prepare_write_buffer(struct nvmem_cell *cell, -+static void *nvmem_cell_prepare_write_buffer(struct nvmem_cell_entry *cell, - u8 *_buf, int len) - { - struct nvmem_device *nvmem = cell->nvmem; -@@ -1497,16 +1536,7 @@ err: - return ERR_PTR(rc); - } - --/** -- * nvmem_cell_write() - Write to a given nvmem cell -- * -- * @cell: nvmem cell to be written. -- * @buf: Buffer to be written. -- * @len: length of buffer to be written to nvmem cell. -- * -- * Return: length of bytes written or negative on failure. -- */ --int nvmem_cell_write(struct nvmem_cell *cell, void *buf, size_t len) -+static int __nvmem_cell_entry_write(struct nvmem_cell_entry *cell, void *buf, size_t len) - { - struct nvmem_device *nvmem = cell->nvmem; - int rc; -@@ -1532,6 +1562,21 @@ int nvmem_cell_write(struct nvmem_cell * - - return len; - } -+ -+/** -+ * nvmem_cell_write() - Write to a given nvmem cell -+ * -+ * @cell: nvmem cell to be written. -+ * @buf: Buffer to be written. -+ * @len: length of buffer to be written to nvmem cell. -+ * -+ * Return: length of bytes written or negative on failure. -+ */ -+int nvmem_cell_write(struct nvmem_cell *cell, void *buf, size_t len) -+{ -+ return __nvmem_cell_entry_write(cell->entry, buf, len); -+} -+ - EXPORT_SYMBOL_GPL(nvmem_cell_write); - - static int nvmem_cell_read_common(struct device *dev, const char *cell_id, -@@ -1634,7 +1679,7 @@ static const void *nvmem_cell_read_varia - if (IS_ERR(cell)) - return cell; - -- nbits = cell->nbits; -+ nbits = cell->entry->nbits; - buf = nvmem_cell_read(cell, len); - nvmem_cell_put(cell); - if (IS_ERR(buf)) -@@ -1730,18 +1775,18 @@ EXPORT_SYMBOL_GPL(nvmem_cell_read_variab - ssize_t nvmem_device_cell_read(struct nvmem_device *nvmem, - struct nvmem_cell_info *info, void *buf) - { -- struct nvmem_cell cell; -+ struct nvmem_cell_entry cell; - int rc; - ssize_t len; - - if (!nvmem) - return -EINVAL; - -- rc = nvmem_cell_info_to_nvmem_cell_nodup(nvmem, info, &cell); -+ rc = nvmem_cell_info_to_nvmem_cell_entry_nodup(nvmem, info, &cell); - if (rc) - return rc; - -- rc = __nvmem_cell_read(nvmem, &cell, buf, &len); -+ rc = __nvmem_cell_read(nvmem, &cell, buf, &len, NULL); - if (rc) - return rc; - -@@ -1761,17 +1806,17 @@ EXPORT_SYMBOL_GPL(nvmem_device_cell_read - int nvmem_device_cell_write(struct nvmem_device *nvmem, - struct nvmem_cell_info *info, void *buf) - { -- struct nvmem_cell cell; -+ struct nvmem_cell_entry cell; - int rc; - - if (!nvmem) - return -EINVAL; - -- rc = nvmem_cell_info_to_nvmem_cell_nodup(nvmem, info, &cell); -+ rc = nvmem_cell_info_to_nvmem_cell_entry_nodup(nvmem, info, &cell); - if (rc) - return rc; - -- return nvmem_cell_write(&cell, buf, cell.bytes); -+ return __nvmem_cell_entry_write(&cell, buf, cell.bytes); - } - EXPORT_SYMBOL_GPL(nvmem_device_cell_write); - diff --git a/target/linux/generic/backport-5.10/806-v5.16-0002-nvmem-core-add-nvmem-cell-post-processing-callback.patch b/target/linux/generic/backport-5.10/806-v5.16-0002-nvmem-core-add-nvmem-cell-post-processing-callback.patch deleted file mode 100644 index 16eb07147e..0000000000 --- a/target/linux/generic/backport-5.10/806-v5.16-0002-nvmem-core-add-nvmem-cell-post-processing-callback.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 5008062f1c3f5af3acf86164aa6fcc77b0c7bdce Mon Sep 17 00:00:00 2001 -From: Srinivas Kandagatla -Date: Wed, 13 Oct 2021 14:19:56 +0100 -Subject: [PATCH] nvmem: core: add nvmem cell post processing callback - -Some NVMEM providers have certain nvmem cells encoded, which requires -post processing before actually using it. - -For example mac-address is stored in either in ascii or delimited or reverse-order. - -Having a post-process callback hook to provider drivers would enable them to -do this vendor specific post processing before nvmem consumers see it. - -Tested-by: Joakim Zhang -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20211013131957.30271-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 9 +++++++++ - include/linux/nvmem-provider.h | 5 +++++ - 2 files changed, 14 insertions(+) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -38,6 +38,7 @@ struct nvmem_device { - unsigned int nkeepout; - nvmem_reg_read_t reg_read; - nvmem_reg_write_t reg_write; -+ nvmem_cell_post_process_t cell_post_process; - struct gpio_desc *wp_gpio; - void *priv; - }; -@@ -799,6 +800,7 @@ struct nvmem_device *nvmem_register(cons - nvmem->type = config->type; - nvmem->reg_read = config->reg_read; - nvmem->reg_write = config->reg_write; -+ nvmem->cell_post_process = config->cell_post_process; - nvmem->keepout = config->keepout; - nvmem->nkeepout = config->nkeepout; - if (config->of_node) -@@ -1444,6 +1446,13 @@ static int __nvmem_cell_read(struct nvme - if (cell->bit_offset || cell->nbits) - nvmem_shift_read_buffer_in_place(cell, buf); - -+ if (nvmem->cell_post_process) { -+ rc = nvmem->cell_post_process(nvmem->priv, id, -+ cell->offset, buf, cell->bytes); -+ if (rc) -+ return rc; -+ } -+ - if (len) - *len = cell->bytes; - ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -19,6 +19,9 @@ typedef int (*nvmem_reg_read_t)(void *pr - void *val, size_t bytes); - typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset, - void *val, size_t bytes); -+/* used for vendor specific post processing of cell data */ -+typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, unsigned int offset, -+ void *buf, size_t bytes); - - enum nvmem_type { - NVMEM_TYPE_UNKNOWN = 0, -@@ -62,6 +65,7 @@ struct nvmem_keepout { - * @no_of_node: Device should not use the parent's of_node even if it's !NULL. - * @reg_read: Callback to read data. - * @reg_write: Callback to write data. -+ * @cell_post_process: Callback for vendor specific post processing of cell data - * @size: Device size. - * @word_size: Minimum read/write access granularity. - * @stride: Minimum read/write access stride. -@@ -92,6 +96,7 @@ struct nvmem_config { - bool no_of_node; - nvmem_reg_read_t reg_read; - nvmem_reg_write_t reg_write; -+ nvmem_cell_post_process_t cell_post_process; - int size; - int word_size; - int stride; diff --git a/target/linux/generic/backport-5.10/806-v5.16-0003-nvmem-imx-ocotp-add-support-for-post-processing.patch b/target/linux/generic/backport-5.10/806-v5.16-0003-nvmem-imx-ocotp-add-support-for-post-processing.patch deleted file mode 100644 index ee19228270..0000000000 --- a/target/linux/generic/backport-5.10/806-v5.16-0003-nvmem-imx-ocotp-add-support-for-post-processing.patch +++ /dev/null @@ -1,92 +0,0 @@ -From d0221a780cbc99fec6c27a98dba2828dc5735c00 Mon Sep 17 00:00:00 2001 -From: Srinivas Kandagatla -Date: Wed, 13 Oct 2021 14:19:57 +0100 -Subject: [PATCH] nvmem: imx-ocotp: add support for post processing - -Add .cell_post_process callback for imx-ocotp to deal with MAC address, -since MAC address need to be reversed byte for some i.MX SoCs. - -Tested-by: Joakim Zhang -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20211013131957.30271-4-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/imx-ocotp.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/drivers/nvmem/imx-ocotp.c -+++ b/drivers/nvmem/imx-ocotp.c -@@ -97,6 +97,7 @@ struct ocotp_params { - unsigned int bank_address_words; - void (*set_timing)(struct ocotp_priv *priv); - struct ocotp_ctrl_reg ctrl; -+ bool reverse_mac_address; - }; - - static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags) -@@ -221,6 +222,25 @@ read_end: - return ret; - } - -+static int imx_ocotp_cell_pp(void *context, const char *id, unsigned int offset, -+ void *data, size_t bytes) -+{ -+ struct ocotp_priv *priv = context; -+ -+ /* Deal with some post processing of nvmem cell data */ -+ if (id && !strcmp(id, "mac-address")) { -+ if (priv->params->reverse_mac_address) { -+ u8 *buf = data; -+ int i; -+ -+ for (i = 0; i < bytes/2; i++) -+ swap(buf[i], buf[bytes - i - 1]); -+ } -+ } -+ -+ return 0; -+} -+ - static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv) - { - unsigned long clk_rate; -@@ -468,6 +488,7 @@ static struct nvmem_config imx_ocotp_nvm - .stride = 1, - .reg_read = imx_ocotp_read, - .reg_write = imx_ocotp_write, -+ .cell_post_process = imx_ocotp_cell_pp, - }; - - static const struct ocotp_params imx6q_params = { -@@ -530,6 +551,7 @@ static const struct ocotp_params imx8mq_ - .bank_address_words = 0, - .set_timing = imx_ocotp_set_imx6_timing, - .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, -+ .reverse_mac_address = true, - }; - - static const struct ocotp_params imx8mm_params = { -@@ -537,6 +559,7 @@ static const struct ocotp_params imx8mm_ - .bank_address_words = 0, - .set_timing = imx_ocotp_set_imx6_timing, - .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, -+ .reverse_mac_address = true, - }; - - static const struct ocotp_params imx8mn_params = { -@@ -544,6 +567,7 @@ static const struct ocotp_params imx8mn_ - .bank_address_words = 0, - .set_timing = imx_ocotp_set_imx6_timing, - .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT, -+ .reverse_mac_address = true, - }; - - static const struct ocotp_params imx8mp_params = { -@@ -551,6 +575,7 @@ static const struct ocotp_params imx8mp_ - .bank_address_words = 0, - .set_timing = imx_ocotp_set_imx6_timing, - .ctrl = IMX_OCOTP_BM_CTRL_8MP, -+ .reverse_mac_address = true, - }; - - static const struct of_device_id imx_ocotp_dt_ids[] = { diff --git a/target/linux/generic/backport-5.10/807-v5.17-0002-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch b/target/linux/generic/backport-5.10/807-v5.17-0002-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch deleted file mode 100644 index 785bfe53f5..0000000000 --- a/target/linux/generic/backport-5.10/807-v5.17-0002-nvmem-mtk-efuse-support-minimum-one-byte-access-stri.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 98e2c4efae214fb7086cac9117616eb6ea11475d Mon Sep 17 00:00:00 2001 -From: Chunfeng Yun -Date: Thu, 9 Dec 2021 17:42:34 +0000 -Subject: [PATCH] nvmem: mtk-efuse: support minimum one byte access stride and - granularity - -In order to support nvmem bits property, should support minimum 1 byte -read stride and minimum 1 byte read granularity at the same time. - -Signed-off-by: Chunfeng Yun -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20211209174235.14049-4-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/mtk-efuse.c | 13 +++++++------ - 1 file changed, 7 insertions(+), 6 deletions(-) - ---- a/drivers/nvmem/mtk-efuse.c -+++ b/drivers/nvmem/mtk-efuse.c -@@ -19,11 +19,12 @@ static int mtk_reg_read(void *context, - unsigned int reg, void *_val, size_t bytes) - { - struct mtk_efuse_priv *priv = context; -- u32 *val = _val; -- int i = 0, words = bytes / 4; -+ void __iomem *addr = priv->base + reg; -+ u8 *val = _val; -+ int i; - -- while (words--) -- *val++ = readl(priv->base + reg + (i++ * 4)); -+ for (i = 0; i < bytes; i++, val++) -+ *val = readb(addr + i); - - return 0; - } -@@ -45,8 +46,8 @@ static int mtk_efuse_probe(struct platfo - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - -- econfig.stride = 4; -- econfig.word_size = 4; -+ econfig.stride = 1; -+ econfig.word_size = 1; - econfig.reg_read = mtk_reg_read; - econfig.size = resource_size(res); - econfig.priv = priv; diff --git a/target/linux/generic/backport-5.10/808-v5.18-0001-nvmem-core-Remove-unused-devm_nvmem_unregister.patch b/target/linux/generic/backport-5.10/808-v5.18-0001-nvmem-core-Remove-unused-devm_nvmem_unregister.patch deleted file mode 100644 index 3fc5393fa9..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0001-nvmem-core-Remove-unused-devm_nvmem_unregister.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 190fae468592bc2f0efc8b928920f8f712b5831e Mon Sep 17 00:00:00 2001 -From: Andy Shevchenko -Date: Sun, 20 Feb 2022 15:15:15 +0000 -Subject: [PATCH] nvmem: core: Remove unused devm_nvmem_unregister() - -There are no users and seems no will come of the devm_nvmem_unregister(). -Remove the function and remove the unused devm_nvmem_match() along with it. - -Signed-off-by: Andy Shevchenko -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220220151527.17216-2-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 22 ---------------------- - include/linux/nvmem-provider.h | 8 -------- - 2 files changed, 30 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -946,28 +946,6 @@ struct nvmem_device *devm_nvmem_register - } - EXPORT_SYMBOL_GPL(devm_nvmem_register); - --static int devm_nvmem_match(struct device *dev, void *res, void *data) --{ -- struct nvmem_device **r = res; -- -- return *r == data; --} -- --/** -- * devm_nvmem_unregister() - Unregister previously registered managed nvmem -- * device. -- * -- * @dev: Device that uses the nvmem device. -- * @nvmem: Pointer to previously registered nvmem device. -- * -- * Return: Will be negative on error or zero on success. -- */ --int devm_nvmem_unregister(struct device *dev, struct nvmem_device *nvmem) --{ -- return devres_release(dev, devm_nvmem_release, devm_nvmem_match, nvmem); --} --EXPORT_SYMBOL(devm_nvmem_unregister); -- - static struct nvmem_device *__nvmem_device_get(void *data, - int (*match)(struct device *dev, const void *data)) - { ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -133,8 +133,6 @@ void nvmem_unregister(struct nvmem_devic - struct nvmem_device *devm_nvmem_register(struct device *dev, - const struct nvmem_config *cfg); - --int devm_nvmem_unregister(struct device *dev, struct nvmem_device *nvmem); -- - void nvmem_add_cell_table(struct nvmem_cell_table *table); - void nvmem_del_cell_table(struct nvmem_cell_table *table); - -@@ -153,12 +151,6 @@ devm_nvmem_register(struct device *dev, - return nvmem_register(c); - } - --static inline int --devm_nvmem_unregister(struct device *dev, struct nvmem_device *nvmem) --{ -- return -EOPNOTSUPP; --} -- - static inline void nvmem_add_cell_table(struct nvmem_cell_table *table) {} - static inline void nvmem_del_cell_table(struct nvmem_cell_table *table) {} - diff --git a/target/linux/generic/backport-5.10/808-v5.18-0002-nvmem-core-Use-devm_add_action_or_reset.patch b/target/linux/generic/backport-5.10/808-v5.18-0002-nvmem-core-Use-devm_add_action_or_reset.patch deleted file mode 100644 index 39c0525832..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0002-nvmem-core-Use-devm_add_action_or_reset.patch +++ /dev/null @@ -1,58 +0,0 @@ -From 5825b2c6762611e67ccaf3ccf64485365a120f0b Mon Sep 17 00:00:00 2001 -From: Andy Shevchenko -Date: Sun, 20 Feb 2022 15:15:16 +0000 -Subject: [PATCH] nvmem: core: Use devm_add_action_or_reset() - -Slightly simplify the devm_nvmem_register() by using the -devm_add_action_or_reset(). - -Signed-off-by: Andy Shevchenko -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220220151527.17216-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 22 +++++++++------------- - 1 file changed, 9 insertions(+), 13 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -908,9 +908,9 @@ void nvmem_unregister(struct nvmem_devic - } - EXPORT_SYMBOL_GPL(nvmem_unregister); - --static void devm_nvmem_release(struct device *dev, void *res) -+static void devm_nvmem_unregister(void *nvmem) - { -- nvmem_unregister(*(struct nvmem_device **)res); -+ nvmem_unregister(nvmem); - } - - /** -@@ -927,20 +927,16 @@ static void devm_nvmem_release(struct de - struct nvmem_device *devm_nvmem_register(struct device *dev, - const struct nvmem_config *config) - { -- struct nvmem_device **ptr, *nvmem; -- -- ptr = devres_alloc(devm_nvmem_release, sizeof(*ptr), GFP_KERNEL); -- if (!ptr) -- return ERR_PTR(-ENOMEM); -+ struct nvmem_device *nvmem; -+ int ret; - - nvmem = nvmem_register(config); -+ if (IS_ERR(nvmem)) -+ return nvmem; - -- if (!IS_ERR(nvmem)) { -- *ptr = nvmem; -- devres_add(dev, ptr); -- } else { -- devres_free(ptr); -- } -+ ret = devm_add_action_or_reset(dev, devm_nvmem_unregister, nvmem); -+ if (ret) -+ return ERR_PTR(ret); - - return nvmem; - } diff --git a/target/linux/generic/backport-5.10/808-v5.18-0003-nvmem-core-Check-input-parameter-for-NULL-in-nvmem_u.patch b/target/linux/generic/backport-5.10/808-v5.18-0003-nvmem-core-Check-input-parameter-for-NULL-in-nvmem_u.patch deleted file mode 100644 index 01170d3d09..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0003-nvmem-core-Check-input-parameter-for-NULL-in-nvmem_u.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 8c751e0d9a5264376935a84429a2d468c8877d99 Mon Sep 17 00:00:00 2001 -From: Andy Shevchenko -Date: Sun, 20 Feb 2022 15:15:17 +0000 -Subject: [PATCH] nvmem: core: Check input parameter for NULL in - nvmem_unregister() - -nvmem_unregister() frees resources and standard pattern is to allow -caller to not care if it's NULL or not. This will reduce burden on -the callers to perform this check. - -Signed-off-by: Andy Shevchenko -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220220151527.17216-4-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -904,7 +904,8 @@ static void nvmem_device_release(struct - */ - void nvmem_unregister(struct nvmem_device *nvmem) - { -- kref_put(&nvmem->refcnt, nvmem_device_release); -+ if (nvmem) -+ kref_put(&nvmem->refcnt, nvmem_device_release); - } - EXPORT_SYMBOL_GPL(nvmem_unregister); - diff --git a/target/linux/generic/backport-5.10/808-v5.18-0004-nvmem-qfprom-fix-kerneldoc-warning.patch b/target/linux/generic/backport-5.10/808-v5.18-0004-nvmem-qfprom-fix-kerneldoc-warning.patch deleted file mode 100644 index c98f8e9d54..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0004-nvmem-qfprom-fix-kerneldoc-warning.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 05196facc052385960028ac634447ecf6c764ec3 Mon Sep 17 00:00:00 2001 -From: Srinivas Kandagatla -Date: Sun, 20 Feb 2022 15:15:18 +0000 -Subject: [PATCH] nvmem: qfprom: fix kerneldoc warning - -This patch fixes below kernel doc warning, -warning: expecting prototype for qfprom_efuse_reg_write(). -Prototype was for qfprom_reg_write() instead - -No code changes. - -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220220151527.17216-5-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qfprom.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/qfprom.c -+++ b/drivers/nvmem/qfprom.c -@@ -244,7 +244,7 @@ err_clk_prepared: - } - - /** -- * qfprom_efuse_reg_write() - Write to fuses. -+ * qfprom_reg_write() - Write to fuses. - * @context: Our driver data. - * @reg: The offset to write at. - * @_val: Pointer to data to write. diff --git a/target/linux/generic/backport-5.10/808-v5.18-0005-nvmem-sunxi_sid-Add-support-for-D1-variant.patch b/target/linux/generic/backport-5.10/808-v5.18-0005-nvmem-sunxi_sid-Add-support-for-D1-variant.patch deleted file mode 100644 index 6aad6af080..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0005-nvmem-sunxi_sid-Add-support-for-D1-variant.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 07ae4fde9efada7878e1383d6ccc7da70315ca23 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sun, 20 Feb 2022 15:15:20 +0000 -Subject: [PATCH] nvmem: sunxi_sid: Add support for D1 variant - -D1 has a smaller eFuse block than some other recent SoCs, and it no -longer requires a workaround to read the eFuse data. - -Signed-off-by: Samuel Holland -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220220151527.17216-7-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/sunxi_sid.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/nvmem/sunxi_sid.c -+++ b/drivers/nvmem/sunxi_sid.c -@@ -184,6 +184,11 @@ static const struct sunxi_sid_cfg sun8i_ - .need_register_readout = true, - }; - -+static const struct sunxi_sid_cfg sun20i_d1_cfg = { -+ .value_offset = 0x200, -+ .size = 0x100, -+}; -+ - static const struct sunxi_sid_cfg sun50i_a64_cfg = { - .value_offset = 0x200, - .size = 0x100, -@@ -200,6 +205,7 @@ static const struct of_device_id sunxi_s - { .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg }, - { .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg }, - { .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg }, -+ { .compatible = "allwinner,sun20i-d1-sid", .data = &sun20i_d1_cfg }, - { .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg }, - { .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg }, - { .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg }, diff --git a/target/linux/generic/backport-5.10/808-v5.18-0006-nvmem-meson-mx-efuse-replace-unnecessary-devm_kstrdu.patch b/target/linux/generic/backport-5.10/808-v5.18-0006-nvmem-meson-mx-efuse-replace-unnecessary-devm_kstrdu.patch deleted file mode 100644 index a73b42c5de..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0006-nvmem-meson-mx-efuse-replace-unnecessary-devm_kstrdu.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 4dc8d89faed9bb05f116fa1794fc955b14910386 Mon Sep 17 00:00:00 2001 -From: Xiaoke Wang -Date: Sun, 20 Feb 2022 15:15:21 +0000 -Subject: [PATCH] nvmem: meson-mx-efuse: replace unnecessary devm_kstrdup() - -Replace unnecessary devm_kstrdup() so to avoid redundant memory allocation. - -Suggested-by: Martin Blumenstingl -Signed-off-by: Xiaoke Wang -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220220151527.17216-8-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/meson-mx-efuse.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/nvmem/meson-mx-efuse.c -+++ b/drivers/nvmem/meson-mx-efuse.c -@@ -209,8 +209,7 @@ static int meson_mx_efuse_probe(struct p - if (IS_ERR(efuse->base)) - return PTR_ERR(efuse->base); - -- efuse->config.name = devm_kstrdup(&pdev->dev, drvdata->name, -- GFP_KERNEL); -+ efuse->config.name = drvdata->name; - efuse->config.owner = THIS_MODULE; - efuse->config.dev = &pdev->dev; - efuse->config.priv = efuse; diff --git a/target/linux/generic/backport-5.10/808-v5.18-0007-nvmem-add-driver-for-Layerscape-SFP-Security-Fuse-Pr.patch b/target/linux/generic/backport-5.10/808-v5.18-0007-nvmem-add-driver-for-Layerscape-SFP-Security-Fuse-Pr.patch deleted file mode 100644 index 6afb68b3f9..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0007-nvmem-add-driver-for-Layerscape-SFP-Security-Fuse-Pr.patch +++ /dev/null @@ -1,139 +0,0 @@ -From f78451012b9e159afdba31c3eb69f223a9f42adc Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Sun, 20 Feb 2022 15:15:23 +0000 -Subject: [PATCH] nvmem: add driver for Layerscape SFP (Security Fuse - Processor) - -Add support for the Security Fuse Processor found on Layerscape SoCs. -This driver implements basic read access. - -Signed-off-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220220151527.17216-10-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 12 +++++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/layerscape-sfp.c | 89 ++++++++++++++++++++++++++++++++++ - 3 files changed, 103 insertions(+) - create mode 100644 drivers/nvmem/layerscape-sfp.c - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -300,4 +300,16 @@ config NVMEM_BRCM_NVRAM - This driver provides support for Broadcom's NVRAM that can be accessed - using I/O mapping. - -+config NVMEM_LAYERSCAPE_SFP -+ tristate "Layerscape SFP (Security Fuse Processor) support" -+ depends on ARCH_LAYERSCAPE || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ This driver provides support to read the eFuses on Freescale -+ Layerscape SoC's. For example, the vendor provides a per part -+ unique ID there. -+ -+ This driver can also be built as a module. If so, the module -+ will be called layerscape-sfp. -+ - endif ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -61,3 +61,5 @@ obj-$(CONFIG_NVMEM_RMEM) += nvmem-rmem. - nvmem-rmem-y := rmem.o - obj-$(CONFIG_NVMEM_BRCM_NVRAM) += nvmem_brcm_nvram.o - nvmem_brcm_nvram-y := brcm_nvram.o -+obj-$(CONFIG_NVMEM_LAYERSCAPE_SFP) += nvmem-layerscape-sfp.o -+nvmem-layerscape-sfp-y := layerscape-sfp.o ---- /dev/null -+++ b/drivers/nvmem/layerscape-sfp.c -@@ -0,0 +1,89 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Layerscape SFP driver -+ * -+ * Copyright (c) 2022 Michael Walle -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define LAYERSCAPE_SFP_OTP_OFFSET 0x0200 -+ -+struct layerscape_sfp_priv { -+ void __iomem *base; -+}; -+ -+struct layerscape_sfp_data { -+ int size; -+}; -+ -+static int layerscape_sfp_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct layerscape_sfp_priv *priv = context; -+ -+ memcpy_fromio(val, priv->base + LAYERSCAPE_SFP_OTP_OFFSET + offset, -+ bytes); -+ -+ return 0; -+} -+ -+static struct nvmem_config layerscape_sfp_nvmem_config = { -+ .name = "fsl-sfp", -+ .reg_read = layerscape_sfp_read, -+}; -+ -+static int layerscape_sfp_probe(struct platform_device *pdev) -+{ -+ const struct layerscape_sfp_data *data; -+ struct layerscape_sfp_priv *priv; -+ struct nvmem_device *nvmem; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(priv->base)) -+ return PTR_ERR(priv->base); -+ -+ data = device_get_match_data(&pdev->dev); -+ -+ layerscape_sfp_nvmem_config.size = data->size; -+ layerscape_sfp_nvmem_config.dev = &pdev->dev; -+ layerscape_sfp_nvmem_config.priv = priv; -+ -+ nvmem = devm_nvmem_register(&pdev->dev, &layerscape_sfp_nvmem_config); -+ -+ return PTR_ERR_OR_ZERO(nvmem); -+} -+ -+static const struct layerscape_sfp_data ls1028a_data = { -+ .size = 0x88, -+}; -+ -+static const struct of_device_id layerscape_sfp_dt_ids[] = { -+ { .compatible = "fsl,ls1028a-sfp", .data = &ls1028a_data }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, layerscape_sfp_dt_ids); -+ -+static struct platform_driver layerscape_sfp_driver = { -+ .probe = layerscape_sfp_probe, -+ .driver = { -+ .name = "layerscape_sfp", -+ .of_match_table = layerscape_sfp_dt_ids, -+ }, -+}; -+module_platform_driver(layerscape_sfp_driver); -+ -+MODULE_AUTHOR("Michael Walle "); -+MODULE_DESCRIPTION("Layerscape Security Fuse Processor driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/backport-5.10/808-v5.18-0008-nvmem-qfprom-Increase-fuse-blow-timeout-to-prevent-w.patch b/target/linux/generic/backport-5.10/808-v5.18-0008-nvmem-qfprom-Increase-fuse-blow-timeout-to-prevent-w.patch deleted file mode 100644 index 74bd4a7eb6..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0008-nvmem-qfprom-Increase-fuse-blow-timeout-to-prevent-w.patch +++ /dev/null @@ -1,32 +0,0 @@ -From bc5c75e0a5a9400f81a987cc720100ac475fa4d8 Mon Sep 17 00:00:00 2001 -From: Knox Chiou -Date: Wed, 23 Feb 2022 22:35:00 +0000 -Subject: [PATCH] nvmem: qfprom: Increase fuse blow timeout to prevent write - fail - -sc7180 blow fuses got slightly chances to hit qfprom_reg_write timeout. -Current timeout is simply too low. Since blowing fuses is a -very rare operation, so the risk associated with overestimating this -number is low. -Increase fuse blow timeout from 1ms to 10ms. - -Reviewed-by: Douglas Anderson -Signed-off-by: Knox Chiou -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220223223502.29454-2-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qfprom.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/qfprom.c -+++ b/drivers/nvmem/qfprom.c -@@ -22,7 +22,7 @@ - - /* Amount of time required to hold charge to blow fuse in micro-seconds */ - #define QFPROM_FUSE_BLOW_POLL_US 100 --#define QFPROM_FUSE_BLOW_TIMEOUT_US 1000 -+#define QFPROM_FUSE_BLOW_TIMEOUT_US 10000 - - #define QFPROM_BLOW_STATUS_OFFSET 0x048 - #define QFPROM_BLOW_STATUS_BUSY 0x1 diff --git a/target/linux/generic/backport-5.10/808-v5.18-0009-nvmem-Add-driver-for-OCOTP-in-Sunplus-SP7021.patch b/target/linux/generic/backport-5.10/808-v5.18-0009-nvmem-Add-driver-for-OCOTP-in-Sunplus-SP7021.patch deleted file mode 100644 index 9520140a67..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0009-nvmem-Add-driver-for-OCOTP-in-Sunplus-SP7021.patch +++ /dev/null @@ -1,277 +0,0 @@ -From 8747ec2e9762ed9ae53b3a590938f454b6a1abdf Mon Sep 17 00:00:00 2001 -From: Vincent Shih -Date: Wed, 23 Feb 2022 22:35:01 +0000 -Subject: [PATCH] nvmem: Add driver for OCOTP in Sunplus SP7021 - -Add driver for OCOTP in Sunplus SP7021 - -Signed-off-by: Vincent Shih -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220223223502.29454-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - MAINTAINERS | 5 + - drivers/nvmem/Kconfig | 12 ++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/sunplus-ocotp.c | 228 ++++++++++++++++++++++++++++++++++ - 4 files changed, 247 insertions(+) - create mode 100644 drivers/nvmem/sunplus-ocotp.c - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -312,4 +312,16 @@ config NVMEM_LAYERSCAPE_SFP - This driver can also be built as a module. If so, the module - will be called layerscape-sfp. - -+config NVMEM_SUNPLUS_OCOTP -+ tristate "Sunplus SoC OTP support" -+ depends on SOC_SP7021 || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ This is a driver for the On-chip OTP controller (OCOTP) available -+ on Sunplus SoCs. It provides access to 128 bytes of one-time -+ programmable eFuse. -+ -+ This driver can also be built as a module. If so, the module -+ will be called nvmem-sunplus-ocotp. -+ - endif ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -63,3 +63,5 @@ obj-$(CONFIG_NVMEM_BRCM_NVRAM) += nvmem_ - nvmem_brcm_nvram-y := brcm_nvram.o - obj-$(CONFIG_NVMEM_LAYERSCAPE_SFP) += nvmem-layerscape-sfp.o - nvmem-layerscape-sfp-y := layerscape-sfp.o -+obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o -+nvmem_sunplus_ocotp-y := sunplus-ocotp.o ---- /dev/null -+++ b/drivers/nvmem/sunplus-ocotp.c -@@ -0,0 +1,228 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+/* -+ * The OCOTP driver for Sunplus SP7021 -+ * -+ * Copyright (C) 2019 Sunplus Technology Inc., All rights reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * OTP memory -+ * Each bank contains 4 words (32 bits). -+ * Bank 0 starts at offset 0 from the base. -+ */ -+ -+#define OTP_WORDS_PER_BANK 4 -+#define OTP_WORD_SIZE sizeof(u32) -+#define OTP_BIT_ADDR_OF_BANK (8 * OTP_WORD_SIZE * OTP_WORDS_PER_BANK) -+#define QAC628_OTP_NUM_BANKS 8 -+#define QAC628_OTP_SIZE (QAC628_OTP_NUM_BANKS * OTP_WORDS_PER_BANK * OTP_WORD_SIZE) -+#define OTP_READ_TIMEOUT_US 200000 -+ -+/* HB_GPIO */ -+#define ADDRESS_8_DATA 0x20 -+ -+/* OTP_RX */ -+#define OTP_CONTROL_2 0x48 -+#define OTP_RD_PERIOD GENMASK(15, 8) -+#define OTP_RD_PERIOD_MASK ~GENMASK(15, 8) -+#define CPU_CLOCK FIELD_PREP(OTP_RD_PERIOD, 30) -+#define SEL_BAK_KEY2 BIT(5) -+#define SEL_BAK_KEY2_MASK ~BIT(5) -+#define SW_TRIM_EN BIT(4) -+#define SW_TRIM_EN_MASK ~BIT(4) -+#define SEL_BAK_KEY BIT(3) -+#define SEL_BAK_KEY_MASK ~BIT(3) -+#define OTP_READ BIT(2) -+#define OTP_LOAD_SECURE_DATA BIT(1) -+#define OTP_LOAD_SECURE_DATA_MASK ~BIT(1) -+#define OTP_DO_CRC BIT(0) -+#define OTP_DO_CRC_MASK ~BIT(0) -+#define OTP_STATUS 0x4c -+#define OTP_READ_DONE BIT(4) -+#define OTP_READ_DONE_MASK ~BIT(4) -+#define OTP_LOAD_SECURE_DONE_MASK ~BIT(2) -+#define OTP_READ_ADDRESS 0x50 -+ -+enum base_type { -+ HB_GPIO, -+ OTPRX, -+ BASEMAX, -+}; -+ -+struct sp_ocotp_priv { -+ struct device *dev; -+ void __iomem *base[BASEMAX]; -+ struct clk *clk; -+}; -+ -+struct sp_ocotp_data { -+ int size; -+}; -+ -+const struct sp_ocotp_data sp_otp_v0 = { -+ .size = QAC628_OTP_SIZE, -+}; -+ -+static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) -+{ -+ unsigned int addr_data; -+ unsigned int byte_shift; -+ unsigned int status; -+ int ret; -+ -+ addr_data = addr % (OTP_WORD_SIZE * OTP_WORDS_PER_BANK); -+ addr_data = addr_data / OTP_WORD_SIZE; -+ -+ byte_shift = addr % (OTP_WORD_SIZE * OTP_WORDS_PER_BANK); -+ byte_shift = byte_shift % OTP_WORD_SIZE; -+ -+ addr = addr / (OTP_WORD_SIZE * OTP_WORDS_PER_BANK); -+ addr = addr * OTP_BIT_ADDR_OF_BANK; -+ -+ writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & -+ OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); -+ writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); -+ writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, -+ otp->base[OTPRX] + OTP_CONTROL_2); -+ writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) & SEL_BAK_KEY2_MASK & SW_TRIM_EN_MASK -+ & SEL_BAK_KEY_MASK & OTP_LOAD_SECURE_DATA_MASK & OTP_DO_CRC_MASK, -+ otp->base[OTPRX] + OTP_CONTROL_2); -+ writel((readl(otp->base[OTPRX] + OTP_CONTROL_2) & OTP_RD_PERIOD_MASK) | CPU_CLOCK, -+ otp->base[OTPRX] + OTP_CONTROL_2); -+ -+ ret = readl_poll_timeout(otp->base[OTPRX] + OTP_STATUS, status, -+ status & OTP_READ_DONE, 10, OTP_READ_TIMEOUT_US); -+ -+ if (ret < 0) -+ return ret; -+ -+ *value = (readl(otp->base[HB_GPIO] + ADDRESS_8_DATA + addr_data * OTP_WORD_SIZE) -+ >> (8 * byte_shift)) & 0xff; -+ -+ return ret; -+} -+ -+static int sp_ocotp_read(void *priv, unsigned int offset, void *value, size_t bytes) -+{ -+ struct sp_ocotp_priv *otp = priv; -+ unsigned int addr; -+ char *buf = value; -+ char val[4]; -+ int ret; -+ -+ ret = clk_enable(otp->clk); -+ if (ret) -+ return ret; -+ -+ *buf = 0; -+ for (addr = offset; addr < (offset + bytes); addr++) { -+ ret = sp_otp_read_real(otp, addr, val); -+ if (ret < 0) { -+ dev_err(otp->dev, "OTP read fail:%d at %d", ret, addr); -+ goto disable_clk; -+ } -+ -+ *buf++ = *val; -+ } -+ -+disable_clk: -+ clk_disable(otp->clk); -+ -+ return ret; -+} -+ -+static struct nvmem_config sp_ocotp_nvmem_config = { -+ .name = "sp-ocotp", -+ .read_only = true, -+ .word_size = 1, -+ .size = QAC628_OTP_SIZE, -+ .stride = 1, -+ .reg_read = sp_ocotp_read, -+ .owner = THIS_MODULE, -+}; -+ -+static int sp_ocotp_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct nvmem_device *nvmem; -+ struct sp_ocotp_priv *otp; -+ struct resource *res; -+ int ret; -+ -+ otp = devm_kzalloc(dev, sizeof(*otp), GFP_KERNEL); -+ if (!otp) -+ return -ENOMEM; -+ -+ otp->dev = dev; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hb_gpio"); -+ otp->base[HB_GPIO] = devm_ioremap_resource(dev, res); -+ if (IS_ERR(otp->base[HB_GPIO])) -+ return PTR_ERR(otp->base[HB_GPIO]); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "otprx"); -+ otp->base[OTPRX] = devm_ioremap_resource(dev, res); -+ if (IS_ERR(otp->base[OTPRX])) -+ return PTR_ERR(otp->base[OTPRX]); -+ -+ otp->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(otp->clk)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(otp->clk), -+ "devm_clk_get fail\n"); -+ -+ ret = clk_prepare(otp->clk); -+ if (ret < 0) { -+ dev_err(dev, "failed to prepare clk: %d\n", ret); -+ return ret; -+ } -+ -+ sp_ocotp_nvmem_config.priv = otp; -+ sp_ocotp_nvmem_config.dev = dev; -+ -+ nvmem = devm_nvmem_register(dev, &sp_ocotp_nvmem_config); -+ if (IS_ERR(nvmem)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(nvmem), -+ "register nvmem device fail\n"); -+ -+ platform_set_drvdata(pdev, nvmem); -+ -+ dev_dbg(dev, "banks:%d x wpb:%d x wsize:%d = %d", -+ (int)QAC628_OTP_NUM_BANKS, (int)OTP_WORDS_PER_BANK, -+ (int)OTP_WORD_SIZE, (int)QAC628_OTP_SIZE); -+ -+ dev_info(dev, "by Sunplus (C) 2020"); -+ -+ return 0; -+} -+ -+static const struct of_device_id sp_ocotp_dt_ids[] = { -+ { .compatible = "sunplus,sp7021-ocotp", .data = &sp_otp_v0 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, sp_ocotp_dt_ids); -+ -+static struct platform_driver sp_otp_driver = { -+ .probe = sp_ocotp_probe, -+ .driver = { -+ .name = "sunplus,sp7021-ocotp", -+ .of_match_table = sp_ocotp_dt_ids, -+ } -+}; -+module_platform_driver(sp_otp_driver); -+ -+MODULE_AUTHOR("Vincent Shih "); -+MODULE_DESCRIPTION("Sunplus On-Chip OTP driver"); -+MODULE_LICENSE("GPL"); -+ diff --git a/target/linux/generic/backport-5.10/808-v5.18-0010-nvmem-brcm_nvram-parse-NVRAM-content-into-NVMEM-cell.patch b/target/linux/generic/backport-5.10/808-v5.18-0010-nvmem-brcm_nvram-parse-NVRAM-content-into-NVMEM-cell.patch deleted file mode 100644 index 99781b3a7b..0000000000 --- a/target/linux/generic/backport-5.10/808-v5.18-0010-nvmem-brcm_nvram-parse-NVRAM-content-into-NVMEM-cell.patch +++ /dev/null @@ -1,146 +0,0 @@ -From 6e977eaa8280e957b87904b536661550f2a6b3e8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 25 Feb 2022 17:58:20 +0000 -Subject: [PATCH] nvmem: brcm_nvram: parse NVRAM content into NVMEM cells -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -NVRAM consist of header and NUL separated key-value pairs. Parse it and -create NVMEM cell for every key-value entry. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220225175822.8293-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/brcm_nvram.c | 90 ++++++++++++++++++++++++++++++++++++++ - 1 file changed, 90 insertions(+) - ---- a/drivers/nvmem/brcm_nvram.c -+++ b/drivers/nvmem/brcm_nvram.c -@@ -6,12 +6,26 @@ - #include - #include - #include -+#include - #include - #include -+#include -+ -+#define NVRAM_MAGIC "FLSH" - - struct brcm_nvram { - struct device *dev; - void __iomem *base; -+ struct nvmem_cell_info *cells; -+ int ncells; -+}; -+ -+struct brcm_nvram_header { -+ char magic[4]; -+ __le32 len; -+ __le32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */ -+ __le32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */ -+ __le32 config_ncdl; /* ncdl values for memc */ - }; - - static int brcm_nvram_read(void *context, unsigned int offset, void *val, -@@ -26,6 +40,75 @@ static int brcm_nvram_read(void *context - return 0; - } - -+static int brcm_nvram_add_cells(struct brcm_nvram *priv, uint8_t *data, -+ size_t len) -+{ -+ struct device *dev = priv->dev; -+ char *var, *value, *eq; -+ int idx; -+ -+ priv->ncells = 0; -+ for (var = data + sizeof(struct brcm_nvram_header); -+ var < (char *)data + len && *var; -+ var += strlen(var) + 1) { -+ priv->ncells++; -+ } -+ -+ priv->cells = devm_kcalloc(dev, priv->ncells, sizeof(*priv->cells), GFP_KERNEL); -+ if (!priv->cells) -+ return -ENOMEM; -+ -+ for (var = data + sizeof(struct brcm_nvram_header), idx = 0; -+ var < (char *)data + len && *var; -+ var = value + strlen(value) + 1, idx++) { -+ eq = strchr(var, '='); -+ if (!eq) -+ break; -+ *eq = '\0'; -+ value = eq + 1; -+ -+ priv->cells[idx].name = devm_kstrdup(dev, var, GFP_KERNEL); -+ if (!priv->cells[idx].name) -+ return -ENOMEM; -+ priv->cells[idx].offset = value - (char *)data; -+ priv->cells[idx].bytes = strlen(value); -+ } -+ -+ return 0; -+} -+ -+static int brcm_nvram_parse(struct brcm_nvram *priv) -+{ -+ struct device *dev = priv->dev; -+ struct brcm_nvram_header header; -+ uint8_t *data; -+ size_t len; -+ int err; -+ -+ memcpy_fromio(&header, priv->base, sizeof(header)); -+ -+ if (memcmp(header.magic, NVRAM_MAGIC, 4)) { -+ dev_err(dev, "Invalid NVRAM magic\n"); -+ return -EINVAL; -+ } -+ -+ len = le32_to_cpu(header.len); -+ -+ data = kcalloc(1, len, GFP_KERNEL); -+ memcpy_fromio(data, priv->base, len); -+ data[len - 1] = '\0'; -+ -+ err = brcm_nvram_add_cells(priv, data, len); -+ if (err) { -+ dev_err(dev, "Failed to add cells: %d\n", err); -+ return err; -+ } -+ -+ kfree(data); -+ -+ return 0; -+} -+ - static int brcm_nvram_probe(struct platform_device *pdev) - { - struct nvmem_config config = { -@@ -35,6 +118,7 @@ static int brcm_nvram_probe(struct platf - struct device *dev = &pdev->dev; - struct resource *res; - struct brcm_nvram *priv; -+ int err; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) -@@ -46,7 +130,13 @@ static int brcm_nvram_probe(struct platf - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - -+ err = brcm_nvram_parse(priv); -+ if (err) -+ return err; -+ - config.dev = dev; -+ config.cells = priv->cells; -+ config.ncells = priv->ncells; - config.priv = priv; - config.size = resource_size(res); - diff --git a/target/linux/generic/backport-5.10/809-v5.19-0001-nvmem-bcm-ocotp-mark-ACPI-device-ID-table-as-maybe-u.patch b/target/linux/generic/backport-5.10/809-v5.19-0001-nvmem-bcm-ocotp-mark-ACPI-device-ID-table-as-maybe-u.patch deleted file mode 100644 index ef3107db94..0000000000 --- a/target/linux/generic/backport-5.10/809-v5.19-0001-nvmem-bcm-ocotp-mark-ACPI-device-ID-table-as-maybe-u.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 6bd0ffeaa389866089e9573b2298ae58d6359b75 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Mon, 21 Mar 2022 12:03:24 +0100 -Subject: [PATCH] nvmem: bcm-ocotp: mark ACPI device ID table as maybe unused -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -"bcm_otpc_acpi_ids" is used with ACPI_PTR, so a build with !CONFIG_ACPI -has a warning: - - drivers/nvmem/bcm-ocotp.c:247:36: error: - ‘bcm_otpc_acpi_ids’ defined but not used [-Werror=unused-const-variable=] - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220321110326.44652-1-krzk@kernel.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/bcm-ocotp.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/bcm-ocotp.c -+++ b/drivers/nvmem/bcm-ocotp.c -@@ -244,7 +244,7 @@ static const struct of_device_id bcm_otp - }; - MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids); - --static const struct acpi_device_id bcm_otpc_acpi_ids[] = { -+static const struct acpi_device_id bcm_otpc_acpi_ids[] __maybe_unused = { - { .id = "BRCM0700", .driver_data = (kernel_ulong_t)&otp_map }, - { .id = "BRCM0701", .driver_data = (kernel_ulong_t)&otp_map_v2 }, - { /* sentinel */ } diff --git a/target/linux/generic/backport-5.10/809-v5.19-0002-nvmem-sunplus-ocotp-staticize-sp_otp_v0.patch b/target/linux/generic/backport-5.10/809-v5.19-0002-nvmem-sunplus-ocotp-staticize-sp_otp_v0.patch deleted file mode 100644 index a84d2316f0..0000000000 --- a/target/linux/generic/backport-5.10/809-v5.19-0002-nvmem-sunplus-ocotp-staticize-sp_otp_v0.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 1066f8156351fcd997125257cea47cf805ba4f6d Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Mon, 21 Mar 2022 12:03:25 +0100 -Subject: [PATCH] nvmem: sunplus-ocotp: staticize sp_otp_v0 - -The "sp_otp_v0" file scope variable is not used outside, so make it -static to fix warning: - - drivers/nvmem/sunplus-ocotp.c:74:29: sparse: - sparse: symbol 'sp_otp_v0' was not declared. Should it be static? - -Reported-by: kernel test robot -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220321110326.44652-2-krzk@kernel.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/sunplus-ocotp.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/sunplus-ocotp.c -+++ b/drivers/nvmem/sunplus-ocotp.c -@@ -71,7 +71,7 @@ struct sp_ocotp_data { - int size; - }; - --const struct sp_ocotp_data sp_otp_v0 = { -+static const struct sp_ocotp_data sp_otp_v0 = { - .size = QAC628_OTP_SIZE, - }; - diff --git a/target/linux/generic/backport-5.10/809-v5.19-0003-nvmem-sunplus-ocotp-drop-useless-probe-confirmation.patch b/target/linux/generic/backport-5.10/809-v5.19-0003-nvmem-sunplus-ocotp-drop-useless-probe-confirmation.patch deleted file mode 100644 index 886ebc12a9..0000000000 --- a/target/linux/generic/backport-5.10/809-v5.19-0003-nvmem-sunplus-ocotp-drop-useless-probe-confirmation.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 874dfbcf219ccc42a2cbd187d087c7db82c3024b Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Mon, 21 Mar 2022 12:03:26 +0100 -Subject: [PATCH] nvmem: sunplus-ocotp: drop useless probe confirmation - -Printing probe success is discouraged, because we can use tracing for -this purpose. Remove useless print message after Sunplus OCOTP driver -probe. - -Signed-off-by: Krzysztof Kozlowski -Link: https://lore.kernel.org/r/20220321110326.44652-3-krzk@kernel.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/sunplus-ocotp.c | 2 -- - 1 file changed, 2 deletions(-) - ---- a/drivers/nvmem/sunplus-ocotp.c -+++ b/drivers/nvmem/sunplus-ocotp.c -@@ -202,8 +202,6 @@ static int sp_ocotp_probe(struct platfor - (int)QAC628_OTP_NUM_BANKS, (int)OTP_WORDS_PER_BANK, - (int)OTP_WORD_SIZE, (int)QAC628_OTP_SIZE); - -- dev_info(dev, "by Sunplus (C) 2020"); -- - return 0; - } - diff --git a/target/linux/generic/backport-5.10/809-v5.19-0004-nvmem-core-support-passing-DT-node-in-cell-info.patch b/target/linux/generic/backport-5.10/809-v5.19-0004-nvmem-core-support-passing-DT-node-in-cell-info.patch deleted file mode 100644 index 3b1e76147a..0000000000 --- a/target/linux/generic/backport-5.10/809-v5.19-0004-nvmem-core-support-passing-DT-node-in-cell-info.patch +++ /dev/null @@ -1,41 +0,0 @@ -From dbc2f62061c6bfba0aee93161ee3194dcee84bd0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 29 Apr 2022 17:26:46 +0100 -Subject: [PATCH] nvmem: core: support passing DT node in cell info -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Some hardware may have NVMEM cells described in Device Tree using -individual nodes. Let drivers pass such nodes to the NVMEM subsystem so -they can be later used by NVMEM consumers. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220429162701.2222-2-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 1 + - include/linux/nvmem-consumer.h | 1 + - 2 files changed, 2 insertions(+) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -467,6 +467,7 @@ static int nvmem_cell_info_to_nvmem_cell - - cell->bit_offset = info->bit_offset; - cell->nbits = info->nbits; -+ cell->np = info->np; - - if (cell->nbits) - cell->bytes = DIV_ROUND_UP(cell->nbits + cell->bit_offset, ---- a/include/linux/nvmem-consumer.h -+++ b/include/linux/nvmem-consumer.h -@@ -25,6 +25,7 @@ struct nvmem_cell_info { - unsigned int bytes; - unsigned int bit_offset; - unsigned int nbits; -+ struct device_node *np; - }; - - /** diff --git a/target/linux/generic/backport-5.10/809-v5.19-0005-nvmem-brcm_nvram-find-Device-Tree-nodes-for-NVMEM-ce.patch b/target/linux/generic/backport-5.10/809-v5.19-0005-nvmem-brcm_nvram-find-Device-Tree-nodes-for-NVMEM-ce.patch deleted file mode 100644 index a9eacd9419..0000000000 --- a/target/linux/generic/backport-5.10/809-v5.19-0005-nvmem-brcm_nvram-find-Device-Tree-nodes-for-NVMEM-ce.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 207775f7e17b8fd0426a2ac4a5b81e4e1d71849e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 29 Apr 2022 17:26:47 +0100 -Subject: [PATCH] nvmem: brcm_nvram: find Device Tree nodes for NVMEM cells -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -DT binding for Broadcom's NVRAM supports specifying NVMEM cells as NVMEM -device (provider) subnodes. Look for such subnodes when collecing NVMEM -cells. This allows NVMEM consumers to use NVRAM variables. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220429162701.2222-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/brcm_nvram.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/nvmem/brcm_nvram.c -+++ b/drivers/nvmem/brcm_nvram.c -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -72,6 +73,7 @@ static int brcm_nvram_add_cells(struct b - return -ENOMEM; - priv->cells[idx].offset = value - (char *)data; - priv->cells[idx].bytes = strlen(value); -+ priv->cells[idx].np = of_get_child_by_name(dev->of_node, priv->cells[idx].name); - } - - return 0; diff --git a/target/linux/generic/backport-5.10/809-v5.19-0006-nvmem-Add-Apple-eFuse-driver.patch b/target/linux/generic/backport-5.10/809-v5.19-0006-nvmem-Add-Apple-eFuse-driver.patch deleted file mode 100644 index ebeb6f5ad3..0000000000 --- a/target/linux/generic/backport-5.10/809-v5.19-0006-nvmem-Add-Apple-eFuse-driver.patch +++ /dev/null @@ -1,130 +0,0 @@ -From b6b7ef932ae838209254f016ecf8862d716a5ced Mon Sep 17 00:00:00 2001 -From: Sven Peter -Date: Fri, 29 Apr 2022 17:26:50 +0100 -Subject: [PATCH] nvmem: Add Apple eFuse driver - -Apple SoCs contain eFuses used to store factory-programmed data such -as calibration values for the PCIe or the Type-C PHY. They are organized -as 32bit values exposed as MMIO. - -Signed-off-by: Sven Peter -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220429162701.2222-6-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 12 ++++++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/apple-efuses.c | 80 ++++++++++++++++++++++++++++++++++++ - 3 files changed, 94 insertions(+) - create mode 100644 drivers/nvmem/apple-efuses.c - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -324,4 +324,16 @@ config NVMEM_SUNPLUS_OCOTP - This driver can also be built as a module. If so, the module - will be called nvmem-sunplus-ocotp. - -+config NVMEM_APPLE_EFUSES -+ tristate "Apple eFuse support" -+ depends on ARCH_APPLE || COMPILE_TEST -+ default ARCH_APPLE -+ help -+ Say y here to enable support for reading eFuses on Apple SoCs -+ such as the M1. These are e.g. used to store factory programmed -+ calibration data required for the PCIe or the USB-C PHY. -+ -+ This driver can also be built as a module. If so, the module will -+ be called nvmem-apple-efuses. -+ - endif ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -65,3 +65,5 @@ obj-$(CONFIG_NVMEM_LAYERSCAPE_SFP) += nv - nvmem-layerscape-sfp-y := layerscape-sfp.o - obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o - nvmem_sunplus_ocotp-y := sunplus-ocotp.o -+obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o -+nvmem-apple-efuses-y := apple-efuses.o ---- /dev/null -+++ b/drivers/nvmem/apple-efuses.c -@@ -0,0 +1,80 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Apple SoC eFuse driver -+ * -+ * Copyright (C) The Asahi Linux Contributors -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+struct apple_efuses_priv { -+ void __iomem *fuses; -+}; -+ -+static int apple_efuses_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct apple_efuses_priv *priv = context; -+ u32 *dst = val; -+ -+ while (bytes >= sizeof(u32)) { -+ *dst++ = readl_relaxed(priv->fuses + offset); -+ bytes -= sizeof(u32); -+ offset += sizeof(u32); -+ } -+ -+ return 0; -+} -+ -+static int apple_efuses_probe(struct platform_device *pdev) -+{ -+ struct apple_efuses_priv *priv; -+ struct resource *res; -+ struct nvmem_config config = { -+ .dev = &pdev->dev, -+ .read_only = true, -+ .reg_read = apple_efuses_read, -+ .stride = sizeof(u32), -+ .word_size = sizeof(u32), -+ .name = "apple_efuses_nvmem", -+ .id = NVMEM_DEVID_AUTO, -+ .root_only = true, -+ }; -+ -+ priv = devm_kzalloc(config.dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->fuses = devm_platform_get_and_ioremap_resource(pdev, 0, &res); -+ if (IS_ERR(priv->fuses)) -+ return PTR_ERR(priv->fuses); -+ -+ config.priv = priv; -+ config.size = resource_size(res); -+ -+ return PTR_ERR_OR_ZERO(devm_nvmem_register(config.dev, &config)); -+} -+ -+static const struct of_device_id apple_efuses_of_match[] = { -+ { .compatible = "apple,efuses", }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(of, apple_efuses_of_match); -+ -+static struct platform_driver apple_efuses_driver = { -+ .driver = { -+ .name = "apple_efuses", -+ .of_match_table = apple_efuses_of_match, -+ }, -+ .probe = apple_efuses_probe, -+}; -+ -+module_platform_driver(apple_efuses_driver); -+ -+MODULE_AUTHOR("Sven Peter "); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/backport-5.10/809-v5.19-0007-nvmem-qfprom-using-pm_runtime_resume_and_get-instead.patch b/target/linux/generic/backport-5.10/809-v5.19-0007-nvmem-qfprom-using-pm_runtime_resume_and_get-instead.patch deleted file mode 100644 index cd51d97006..0000000000 --- a/target/linux/generic/backport-5.10/809-v5.19-0007-nvmem-qfprom-using-pm_runtime_resume_and_get-instead.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 517f6e2641a2802dce5a5aa0d18c7d37a35678d2 Mon Sep 17 00:00:00 2001 -From: Minghao Chi -Date: Fri, 29 Apr 2022 17:26:54 +0100 -Subject: [PATCH] nvmem: qfprom: using pm_runtime_resume_and_get instead of - pm_runtime_get_sync - -Using pm_runtime_resume_and_get is more appropriate -for simplifing code - -Reported-by: Zeal Robot -Signed-off-by: Minghao Chi -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220429162701.2222-10-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qfprom.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/nvmem/qfprom.c -+++ b/drivers/nvmem/qfprom.c -@@ -217,9 +217,8 @@ static int qfprom_enable_fuse_blowing(co - goto err_clk_rate_set; - } - -- ret = pm_runtime_get_sync(priv->dev); -+ ret = pm_runtime_resume_and_get(priv->dev); - if (ret < 0) { -- pm_runtime_put_noidle(priv->dev); - dev_err(priv->dev, "Failed to enable power-domain\n"); - goto err_reg_enable; - } diff --git a/target/linux/generic/backport-5.10/809-v5.19-0008-nvmem-sfp-Use-regmap.patch b/target/linux/generic/backport-5.10/809-v5.19-0008-nvmem-sfp-Use-regmap.patch deleted file mode 100644 index e187238ca3..0000000000 --- a/target/linux/generic/backport-5.10/809-v5.19-0008-nvmem-sfp-Use-regmap.patch +++ /dev/null @@ -1,109 +0,0 @@ -From 943eadbdb11314b41eacbcc484dfb7f93e271ff4 Mon Sep 17 00:00:00 2001 -From: Sean Anderson -Date: Fri, 29 Apr 2022 17:27:00 +0100 -Subject: [PATCH] nvmem: sfp: Use regmap - -This converts the SFP driver to use regmap. This will allow easily -supporting devices with different endians. We disallow byte-level -access, as regmap_bulk_read doesn't support it (and it's unclear what -the correct result would be when we have an endianness difference). - -Signed-off-by: Sean Anderson -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220429162701.2222-16-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 1 + - drivers/nvmem/layerscape-sfp.c | 30 ++++++++++++++++++++++-------- - 2 files changed, 23 insertions(+), 8 deletions(-) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -304,6 +304,7 @@ config NVMEM_LAYERSCAPE_SFP - tristate "Layerscape SFP (Security Fuse Processor) support" - depends on ARCH_LAYERSCAPE || COMPILE_TEST - depends on HAS_IOMEM -+ select REGMAP_MMIO - help - This driver provides support to read the eFuses on Freescale - Layerscape SoC's. For example, the vendor provides a per part ---- a/drivers/nvmem/layerscape-sfp.c -+++ b/drivers/nvmem/layerscape-sfp.c -@@ -13,15 +13,17 @@ - #include - #include - #include -+#include - - #define LAYERSCAPE_SFP_OTP_OFFSET 0x0200 - - struct layerscape_sfp_priv { -- void __iomem *base; -+ struct regmap *regmap; - }; - - struct layerscape_sfp_data { - int size; -+ enum regmap_endian endian; - }; - - static int layerscape_sfp_read(void *context, unsigned int offset, void *val, -@@ -29,15 +31,16 @@ static int layerscape_sfp_read(void *con - { - struct layerscape_sfp_priv *priv = context; - -- memcpy_fromio(val, priv->base + LAYERSCAPE_SFP_OTP_OFFSET + offset, -- bytes); -- -- return 0; -+ return regmap_bulk_read(priv->regmap, -+ LAYERSCAPE_SFP_OTP_OFFSET + offset, val, -+ bytes / 4); - } - - static struct nvmem_config layerscape_sfp_nvmem_config = { - .name = "fsl-sfp", - .reg_read = layerscape_sfp_read, -+ .word_size = 4, -+ .stride = 4, - }; - - static int layerscape_sfp_probe(struct platform_device *pdev) -@@ -45,16 +48,26 @@ static int layerscape_sfp_probe(struct p - const struct layerscape_sfp_data *data; - struct layerscape_sfp_priv *priv; - struct nvmem_device *nvmem; -+ struct regmap_config config = { 0 }; -+ void __iomem *base; - - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - -- priv->base = devm_platform_ioremap_resource(pdev, 0); -- if (IS_ERR(priv->base)) -- return PTR_ERR(priv->base); -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); - - data = device_get_match_data(&pdev->dev); -+ config.reg_bits = 32; -+ config.reg_stride = 4; -+ config.val_bits = 32; -+ config.val_format_endian = data->endian; -+ config.max_register = LAYERSCAPE_SFP_OTP_OFFSET + data->size - 4; -+ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, &config); -+ if (IS_ERR(priv->regmap)) -+ return PTR_ERR(priv->regmap); - - layerscape_sfp_nvmem_config.size = data->size; - layerscape_sfp_nvmem_config.dev = &pdev->dev; -@@ -67,6 +80,7 @@ static int layerscape_sfp_probe(struct p - - static const struct layerscape_sfp_data ls1028a_data = { - .size = 0x88, -+ .endian = REGMAP_ENDIAN_LITTLE, - }; - - static const struct of_device_id layerscape_sfp_dt_ids[] = { diff --git a/target/linux/generic/backport-5.10/809-v5.19-0009-nvmem-sfp-Add-support-for-TA-2.1-devices.patch b/target/linux/generic/backport-5.10/809-v5.19-0009-nvmem-sfp-Add-support-for-TA-2.1-devices.patch deleted file mode 100644 index ee00098618..0000000000 --- a/target/linux/generic/backport-5.10/809-v5.19-0009-nvmem-sfp-Add-support-for-TA-2.1-devices.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 33a1c6618677fe33f8e84cb7bedc45abbce89a50 Mon Sep 17 00:00:00 2001 -From: Sean Anderson -Date: Fri, 29 Apr 2022 17:27:01 +0100 -Subject: [PATCH] nvmem: sfp: Add support for TA 2.1 devices - -This adds support for Trust Architecture (TA) 2.1 devices to the SFP driver. -There are few differences between TA 2.1 and TA 3.0, especially for -read-only support, so just re-use the existing data. - -Signed-off-by: Sean Anderson -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220429162701.2222-17-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/layerscape-sfp.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/nvmem/layerscape-sfp.c -+++ b/drivers/nvmem/layerscape-sfp.c -@@ -78,12 +78,18 @@ static int layerscape_sfp_probe(struct p - return PTR_ERR_OR_ZERO(nvmem); - } - -+static const struct layerscape_sfp_data ls1021a_data = { -+ .size = 0x88, -+ .endian = REGMAP_ENDIAN_BIG, -+}; -+ - static const struct layerscape_sfp_data ls1028a_data = { - .size = 0x88, - .endian = REGMAP_ENDIAN_LITTLE, - }; - - static const struct of_device_id layerscape_sfp_dt_ids[] = { -+ { .compatible = "fsl,ls1021a-sfp", .data = &ls1021a_data }, - { .compatible = "fsl,ls1028a-sfp", .data = &ls1028a_data }, - {}, - }; diff --git a/target/linux/generic/backport-5.10/810-v6.0-0001-nvmem-microchip-otpc-add-support.patch b/target/linux/generic/backport-5.10/810-v6.0-0001-nvmem-microchip-otpc-add-support.patch deleted file mode 100644 index eb99ec190c..0000000000 --- a/target/linux/generic/backport-5.10/810-v6.0-0001-nvmem-microchip-otpc-add-support.patch +++ /dev/null @@ -1,389 +0,0 @@ -From 98830350d3fc824c1ff5c338140fe20f041a5916 Mon Sep 17 00:00:00 2001 -From: Claudiu Beznea -Date: Wed, 6 Jul 2022 11:06:22 +0100 -Subject: [PATCH] nvmem: microchip-otpc: add support - -Add support for Microchip OTP controller available on SAMA7G5. The OTPC -controls the access to a non-volatile memory. The memory behind OTPC is -organized into packets, packets are composed by a fixed length header -(4 bytes long) and a variable length payload (payload length is available -in the header). When software request the data at an offset in memory -the OTPC will return (via header + data registers) the whole packet that -has a word at that offset. For the OTP memory layout like below: - -offset OTP Memory layout - - . . - . ... . - . . -0x0E +-----------+ <--- packet X - | header X | -0x12 +-----------+ - | payload X | -0x16 | | - | | -0x1A | | - +-----------+ - . . - . ... . - . . - -if user requests data at address 0x16 the data started at 0x0E will be -returned by controller. User will be able to fetch the whole packet -starting at 0x0E (or parts of the packet) via proper registers. The same -packet will be returned if software request the data at offset 0x0E or -0x12 or 0x1A. - -The OTP will be populated by Microchip with at least 2 packets first one -being boot configuration packet and the 2nd one being temperature -calibration packet. The packet order will be preserved b/w different chip -revisions but the packet sizes may change. - -For the above reasons and to keep the same software able to work on all -chip variants the read function of the driver is working with a packet -id instead of an offset in OTP memory. - -Signed-off-by: Claudiu Beznea -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220706100627.6534-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - MAINTAINERS | 8 + - drivers/nvmem/Kconfig | 7 + - drivers/nvmem/Makefile | 2 + - drivers/nvmem/microchip-otpc.c | 288 +++++++++++++++++++++++++++++++++ - 4 files changed, 305 insertions(+) - create mode 100644 drivers/nvmem/microchip-otpc.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -11565,6 +11565,14 @@ S: Supported - F: Documentation/devicetree/bindings/mtd/atmel-nand.txt - F: drivers/mtd/nand/raw/atmel/* - -+MICROCHIP OTPC DRIVER -+M: Claudiu Beznea -+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -+S: Supported -+F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml -+F: drivers/nvmem/microchip-otpc.c -+F: dt-bindings/nvmem/microchip,sama7g5-otpc.h -+ - MICROCHIP PWM DRIVER - M: Claudiu Beznea - L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -107,6 +107,13 @@ config MTK_EFUSE - This driver can also be built as a module. If so, the module - will be called efuse-mtk. - -+config MICROCHIP_OTPC -+ tristate "Microchip OTPC support" -+ depends on ARCH_AT91 || COMPILE_TEST -+ help -+ This driver enable the OTP controller available on Microchip SAMA7G5 -+ SoCs. It controlls the access to the OTP memory connected to it. -+ - config NVMEM_NINTENDO_OTP - tristate "Nintendo Wii and Wii U OTP Support" - depends on WII || COMPILE_TEST ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -67,3 +67,5 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvm - nvmem_sunplus_ocotp-y := sunplus-ocotp.o - obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o - nvmem-apple-efuses-y := apple-efuses.o -+obj-$(CONFIG_MICROCHIP_OTPC) += nvmem-microchip-otpc.o -+nvmem-microchip-otpc-y := microchip-otpc.o ---- /dev/null -+++ b/drivers/nvmem/microchip-otpc.c -@@ -0,0 +1,288 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * OTP Memory controller -+ * -+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries -+ * -+ * Author: Claudiu Beznea -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MCHP_OTPC_CR (0x0) -+#define MCHP_OTPC_CR_READ BIT(6) -+#define MCHP_OTPC_MR (0x4) -+#define MCHP_OTPC_MR_ADDR GENMASK(31, 16) -+#define MCHP_OTPC_AR (0x8) -+#define MCHP_OTPC_SR (0xc) -+#define MCHP_OTPC_SR_READ BIT(6) -+#define MCHP_OTPC_HR (0x20) -+#define MCHP_OTPC_HR_SIZE GENMASK(15, 8) -+#define MCHP_OTPC_DR (0x24) -+ -+#define MCHP_OTPC_NAME "mchp-otpc" -+#define MCHP_OTPC_SIZE (11 * 1024) -+ -+/** -+ * struct mchp_otpc - OTPC private data structure -+ * @base: base address -+ * @dev: struct device pointer -+ * @packets: list of packets in OTP memory -+ * @npackets: number of packets in OTP memory -+ */ -+struct mchp_otpc { -+ void __iomem *base; -+ struct device *dev; -+ struct list_head packets; -+ u32 npackets; -+}; -+ -+/** -+ * struct mchp_otpc_packet - OTPC packet data structure -+ * @list: list head -+ * @id: packet ID -+ * @offset: packet offset (in words) in OTP memory -+ */ -+struct mchp_otpc_packet { -+ struct list_head list; -+ u32 id; -+ u32 offset; -+}; -+ -+static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *otpc, -+ u32 id) -+{ -+ struct mchp_otpc_packet *packet; -+ -+ if (id >= otpc->npackets) -+ return NULL; -+ -+ list_for_each_entry(packet, &otpc->packets, list) { -+ if (packet->id == id) -+ return packet; -+ } -+ -+ return NULL; -+} -+ -+static int mchp_otpc_prepare_read(struct mchp_otpc *otpc, -+ unsigned int offset) -+{ -+ u32 tmp; -+ -+ /* Set address. */ -+ tmp = readl_relaxed(otpc->base + MCHP_OTPC_MR); -+ tmp &= ~MCHP_OTPC_MR_ADDR; -+ tmp |= FIELD_PREP(MCHP_OTPC_MR_ADDR, offset); -+ writel_relaxed(tmp, otpc->base + MCHP_OTPC_MR); -+ -+ /* Set read. */ -+ tmp = readl_relaxed(otpc->base + MCHP_OTPC_CR); -+ tmp |= MCHP_OTPC_CR_READ; -+ writel_relaxed(tmp, otpc->base + MCHP_OTPC_CR); -+ -+ /* Wait for packet to be transferred into temporary buffers. */ -+ return read_poll_timeout(readl_relaxed, tmp, !(tmp & MCHP_OTPC_SR_READ), -+ 10000, 2000, false, otpc->base + MCHP_OTPC_SR); -+} -+ -+/* -+ * OTPC memory is organized into packets. Each packets contains a header and -+ * a payload. Header is 4 bytes long and contains the size of the payload. -+ * Payload size varies. The memory footprint is something as follows: -+ * -+ * Memory offset Memory footprint Packet ID -+ * ------------- ---------------- --------- -+ * -+ * 0x0 +------------+ <-- packet 0 -+ * | header 0 | -+ * 0x4 +------------+ -+ * | payload 0 | -+ * . . -+ * . ... . -+ * . . -+ * offset1 +------------+ <-- packet 1 -+ * | header 1 | -+ * offset1 + 0x4 +------------+ -+ * | payload 1 | -+ * . . -+ * . ... . -+ * . . -+ * offset2 +------------+ <-- packet 2 -+ * . . -+ * . ... . -+ * . . -+ * offsetN +------------+ <-- packet N -+ * | header N | -+ * offsetN + 0x4 +------------+ -+ * | payload N | -+ * . . -+ * . ... . -+ * . . -+ * +------------+ -+ * -+ * where offset1, offset2, offsetN depends on the size of payload 0, payload 1, -+ * payload N-1. -+ * -+ * The access to memory is done on a per packet basis: the control registers -+ * need to be updated with an offset address (within a packet range) and the -+ * data registers will be update by controller with information contained by -+ * that packet. E.g. if control registers are updated with any address within -+ * the range [offset1, offset2) the data registers are updated by controller -+ * with packet 1. Header data is accessible though MCHP_OTPC_HR register. -+ * Payload data is accessible though MCHP_OTPC_DR and MCHP_OTPC_AR registers. -+ * There is no direct mapping b/w the offset requested by software and the -+ * offset returned by hardware. -+ * -+ * For this, the read function will return the first requested bytes in the -+ * packet. The user will have to be aware of the memory footprint before doing -+ * the read request. -+ */ -+static int mchp_otpc_read(void *priv, unsigned int off, void *val, -+ size_t bytes) -+{ -+ struct mchp_otpc *otpc = priv; -+ struct mchp_otpc_packet *packet; -+ u32 *buf = val; -+ u32 offset; -+ size_t len = 0; -+ int ret, payload_size; -+ -+ /* -+ * We reach this point with off being multiple of stride = 4 to -+ * be able to cross the subsystem. Inside the driver we use continuous -+ * unsigned integer numbers for packet id, thus devide off by 4 -+ * before passing it to mchp_otpc_id_to_packet(). -+ */ -+ packet = mchp_otpc_id_to_packet(otpc, off / 4); -+ if (!packet) -+ return -EINVAL; -+ offset = packet->offset; -+ -+ while (len < bytes) { -+ ret = mchp_otpc_prepare_read(otpc, offset); -+ if (ret) -+ return ret; -+ -+ /* Read and save header content. */ -+ *buf++ = readl_relaxed(otpc->base + MCHP_OTPC_HR); -+ len += sizeof(*buf); -+ offset++; -+ if (len >= bytes) -+ break; -+ -+ /* Read and save payload content. */ -+ payload_size = FIELD_GET(MCHP_OTPC_HR_SIZE, *(buf - 1)); -+ writel_relaxed(0UL, otpc->base + MCHP_OTPC_AR); -+ do { -+ *buf++ = readl_relaxed(otpc->base + MCHP_OTPC_DR); -+ len += sizeof(*buf); -+ offset++; -+ payload_size--; -+ } while (payload_size >= 0 && len < bytes); -+ } -+ -+ return 0; -+} -+ -+static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size) -+{ -+ struct mchp_otpc_packet *packet; -+ u32 word, word_pos = 0, id = 0, npackets = 0, payload_size; -+ int ret; -+ -+ INIT_LIST_HEAD(&otpc->packets); -+ *size = 0; -+ -+ while (*size < MCHP_OTPC_SIZE) { -+ ret = mchp_otpc_prepare_read(otpc, word_pos); -+ if (ret) -+ return ret; -+ -+ word = readl_relaxed(otpc->base + MCHP_OTPC_HR); -+ payload_size = FIELD_GET(MCHP_OTPC_HR_SIZE, word); -+ if (!payload_size) -+ break; -+ -+ packet = devm_kzalloc(otpc->dev, sizeof(*packet), GFP_KERNEL); -+ if (!packet) -+ return -ENOMEM; -+ -+ packet->id = id++; -+ packet->offset = word_pos; -+ INIT_LIST_HEAD(&packet->list); -+ list_add_tail(&packet->list, &otpc->packets); -+ -+ /* Count size by adding header and paload sizes. */ -+ *size += 4 * (payload_size + 1); -+ /* Next word: this packet (header, payload) position + 1. */ -+ word_pos += payload_size + 2; -+ -+ npackets++; -+ } -+ -+ otpc->npackets = npackets; -+ -+ return 0; -+} -+ -+static struct nvmem_config mchp_nvmem_config = { -+ .name = MCHP_OTPC_NAME, -+ .type = NVMEM_TYPE_OTP, -+ .read_only = true, -+ .word_size = 4, -+ .stride = 4, -+ .reg_read = mchp_otpc_read, -+}; -+ -+static int mchp_otpc_probe(struct platform_device *pdev) -+{ -+ struct nvmem_device *nvmem; -+ struct mchp_otpc *otpc; -+ u32 size; -+ int ret; -+ -+ otpc = devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL); -+ if (!otpc) -+ return -ENOMEM; -+ -+ otpc->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(otpc->base)) -+ return PTR_ERR(otpc->base); -+ -+ otpc->dev = &pdev->dev; -+ ret = mchp_otpc_init_packets_list(otpc, &size); -+ if (ret) -+ return ret; -+ -+ mchp_nvmem_config.dev = otpc->dev; -+ mchp_nvmem_config.size = size; -+ mchp_nvmem_config.priv = otpc; -+ nvmem = devm_nvmem_register(&pdev->dev, &mchp_nvmem_config); -+ -+ return PTR_ERR_OR_ZERO(nvmem); -+} -+ -+static const struct of_device_id __maybe_unused mchp_otpc_ids[] = { -+ { .compatible = "microchip,sama7g5-otpc", }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, mchp_otpc_ids); -+ -+static struct platform_driver mchp_otpc_driver = { -+ .probe = mchp_otpc_probe, -+ .driver = { -+ .name = MCHP_OTPC_NAME, -+ .of_match_table = of_match_ptr(mchp_otpc_ids), -+ }, -+}; -+module_platform_driver(mchp_otpc_driver); -+ -+MODULE_AUTHOR("Claudiu Beznea "); -+MODULE_DESCRIPTION("Microchip SAMA7G5 OTPC driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/backport-5.10/810-v6.0-0002-nvmem-mtk-efuse-Simplify-with-devm_platform_get_and_.patch b/target/linux/generic/backport-5.10/810-v6.0-0002-nvmem-mtk-efuse-Simplify-with-devm_platform_get_and_.patch deleted file mode 100644 index 6a4126b9de..0000000000 --- a/target/linux/generic/backport-5.10/810-v6.0-0002-nvmem-mtk-efuse-Simplify-with-devm_platform_get_and_.patch +++ /dev/null @@ -1,32 +0,0 @@ -From f5c97da8037b18d1256a58459fa96ed68e50fb41 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Wed, 6 Jul 2022 11:06:27 +0100 -Subject: [PATCH] nvmem: mtk-efuse: Simplify with - devm_platform_get_and_ioremap_resource() - -Convert platform_get_resource(), devm_ioremap_resource() to a single -call to devm_platform_get_and_ioremap_resource(), as this is exactly -what this function does. - -No functional changes. - -Signed-off-by: AngeloGioacchino Del Regno -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220706100627.6534-8-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/mtk-efuse.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/nvmem/mtk-efuse.c -+++ b/drivers/nvmem/mtk-efuse.c -@@ -41,8 +41,7 @@ static int mtk_efuse_probe(struct platfo - if (!priv) - return -ENOMEM; - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- priv->base = devm_ioremap_resource(dev, res); -+ priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - diff --git a/target/linux/generic/backport-5.10/811-v6.1-0001-nvmem-core-Fix-memleak-in-nvmem_register.patch b/target/linux/generic/backport-5.10/811-v6.1-0001-nvmem-core-Fix-memleak-in-nvmem_register.patch deleted file mode 100644 index 561af91893..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0001-nvmem-core-Fix-memleak-in-nvmem_register.patch +++ /dev/null @@ -1,53 +0,0 @@ -From bd1244561fa2a4531ded40dbf09c9599084f8b29 Mon Sep 17 00:00:00 2001 -From: Gaosheng Cui -Date: Fri, 16 Sep 2022 13:04:02 +0100 -Subject: [PATCH] nvmem: core: Fix memleak in nvmem_register() - -dev_set_name will alloc memory for nvmem->dev.kobj.name in -nvmem_register, when nvmem_validate_keepouts failed, nvmem's -memory will be freed and return, but nobody will free memory -for nvmem->dev.kobj.name, there will be memleak, so moving -nvmem_validate_keepouts() after device_register() and let -the device core deal with cleaning name in error cases. - -Fixes: de0534df9347 ("nvmem: core: fix error handling while validating keepout regions") -Cc: stable@vger.kernel.org -Signed-off-by: Gaosheng Cui -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220916120402.38753-1-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 15 ++++++--------- - 1 file changed, 6 insertions(+), 9 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -833,6 +833,12 @@ struct nvmem_device *nvmem_register(cons - nvmem->dev.groups = nvmem_dev_groups; - #endif - -+ if (nvmem->nkeepout) { -+ rval = nvmem_validate_keepouts(nvmem); -+ if (rval) -+ goto err_put_device; -+ } -+ - if (config->compat) { - rval = nvmem_sysfs_setup_compat(nvmem, config); - if (rval) -@@ -853,15 +859,6 @@ struct nvmem_device *nvmem_register(cons - if (rval) - goto err_remove_cells; - -- if (nvmem->nkeepout) { -- rval = nvmem_validate_keepouts(nvmem); -- if (rval) { -- ida_free(&nvmem_ida, nvmem->id); -- kfree(nvmem); -- return ERR_PTR(rval); -- } -- } -- - dev_dbg(&nvmem->dev, "Registering nvmem device %s\n", config->name); - - rval = device_add(&nvmem->dev); diff --git a/target/linux/generic/backport-5.10/811-v6.1-0002-nvmem-add-driver-handling-U-Boot-environment-variabl.patch b/target/linux/generic/backport-5.10/811-v6.1-0002-nvmem-add-driver-handling-U-Boot-environment-variabl.patch deleted file mode 100644 index 9138807bc9..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0002-nvmem-add-driver-handling-U-Boot-environment-variabl.patch +++ /dev/null @@ -1,286 +0,0 @@ -From d5542923f200f95bddf524f36fd495f78aa28e3c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 16 Sep 2022 13:20:48 +0100 -Subject: [PATCH] nvmem: add driver handling U-Boot environment variables -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -U-Boot stores its setup as environment variables. It's a list of -key-value pairs stored on flash device with a custom header. - -This commit adds an NVMEM driver that: -1. Provides NVMEM access to environment vars binary data -2. Extracts variables as NVMEM cells - -Current Linux's NVMEM sysfs API allows reading whole NVMEM data block. -It can be used by user-space tools for reading U-Boot env vars block -without the hassle of finding its location. Parsing will still need to -be re-done there. - -Kernel-parsed NVMEM cells can be read however by Linux drivers. This may -be useful for Ethernet drivers for reading device MAC address which is -often stored as U-Boot env variable. - -Reviewed-by: Ahmad Fatoum -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220916122100.170016-2-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - MAINTAINERS | 1 + - drivers/nvmem/Kconfig | 13 +++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/u-boot-env.c | 218 +++++++++++++++++++++++++++++++++++++ - 4 files changed, 234 insertions(+) - create mode 100644 drivers/nvmem/u-boot-env.c - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -344,4 +344,17 @@ config NVMEM_APPLE_EFUSES - This driver can also be built as a module. If so, the module will - be called nvmem-apple-efuses. - -+config NVMEM_U_BOOT_ENV -+ tristate "U-Boot environment variables support" -+ depends on OF && MTD -+ select CRC32 -+ help -+ U-Boot stores its setup as environment variables. This driver adds -+ support for verifying & exporting such data. It also exposes variables -+ as NVMEM cells so they can be referenced by other drivers. -+ -+ Currently this drivers works only with env variables on top of MTD. -+ -+ If compiled as module it will be called nvmem_u-boot-env. -+ - endif ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -69,3 +69,5 @@ obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvme - nvmem-apple-efuses-y := apple-efuses.o - obj-$(CONFIG_MICROCHIP_OTPC) += nvmem-microchip-otpc.o - nvmem-microchip-otpc-y := microchip-otpc.o -+obj-$(CONFIG_NVMEM_U_BOOT_ENV) += nvmem_u-boot-env.o -+nvmem_u-boot-env-y := u-boot-env.o ---- /dev/null -+++ b/drivers/nvmem/u-boot-env.c -@@ -0,0 +1,218 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2022 Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+enum u_boot_env_format { -+ U_BOOT_FORMAT_SINGLE, -+ U_BOOT_FORMAT_REDUNDANT, -+}; -+ -+struct u_boot_env { -+ struct device *dev; -+ enum u_boot_env_format format; -+ -+ struct mtd_info *mtd; -+ -+ /* Cells */ -+ struct nvmem_cell_info *cells; -+ int ncells; -+}; -+ -+struct u_boot_env_image_single { -+ __le32 crc32; -+ uint8_t data[]; -+} __packed; -+ -+struct u_boot_env_image_redundant { -+ __le32 crc32; -+ u8 mark; -+ uint8_t data[]; -+} __packed; -+ -+static int u_boot_env_read(void *context, unsigned int offset, void *val, -+ size_t bytes) -+{ -+ struct u_boot_env *priv = context; -+ struct device *dev = priv->dev; -+ size_t bytes_read; -+ int err; -+ -+ err = mtd_read(priv->mtd, offset, bytes, &bytes_read, val); -+ if (err && !mtd_is_bitflip(err)) { -+ dev_err(dev, "Failed to read from mtd: %d\n", err); -+ return err; -+ } -+ -+ if (bytes_read != bytes) { -+ dev_err(dev, "Failed to read %zu bytes\n", bytes); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int u_boot_env_add_cells(struct u_boot_env *priv, uint8_t *buf, -+ size_t data_offset, size_t data_len) -+{ -+ struct device *dev = priv->dev; -+ char *data = buf + data_offset; -+ char *var, *value, *eq; -+ int idx; -+ -+ priv->ncells = 0; -+ for (var = data; var < data + data_len && *var; var += strlen(var) + 1) -+ priv->ncells++; -+ -+ priv->cells = devm_kcalloc(dev, priv->ncells, sizeof(*priv->cells), GFP_KERNEL); -+ if (!priv->cells) -+ return -ENOMEM; -+ -+ for (var = data, idx = 0; -+ var < data + data_len && *var; -+ var = value + strlen(value) + 1, idx++) { -+ eq = strchr(var, '='); -+ if (!eq) -+ break; -+ *eq = '\0'; -+ value = eq + 1; -+ -+ priv->cells[idx].name = devm_kstrdup(dev, var, GFP_KERNEL); -+ if (!priv->cells[idx].name) -+ return -ENOMEM; -+ priv->cells[idx].offset = data_offset + value - data; -+ priv->cells[idx].bytes = strlen(value); -+ } -+ -+ if (WARN_ON(idx != priv->ncells)) -+ priv->ncells = idx; -+ -+ return 0; -+} -+ -+static int u_boot_env_parse(struct u_boot_env *priv) -+{ -+ struct device *dev = priv->dev; -+ size_t crc32_data_offset; -+ size_t crc32_data_len; -+ size_t crc32_offset; -+ size_t data_offset; -+ size_t data_len; -+ uint32_t crc32; -+ uint32_t calc; -+ size_t bytes; -+ uint8_t *buf; -+ int err; -+ -+ buf = kcalloc(1, priv->mtd->size, GFP_KERNEL); -+ if (!buf) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ err = mtd_read(priv->mtd, 0, priv->mtd->size, &bytes, buf); -+ if ((err && !mtd_is_bitflip(err)) || bytes != priv->mtd->size) { -+ dev_err(dev, "Failed to read from mtd: %d\n", err); -+ goto err_kfree; -+ } -+ -+ switch (priv->format) { -+ case U_BOOT_FORMAT_SINGLE: -+ crc32_offset = offsetof(struct u_boot_env_image_single, crc32); -+ crc32_data_offset = offsetof(struct u_boot_env_image_single, data); -+ data_offset = offsetof(struct u_boot_env_image_single, data); -+ break; -+ case U_BOOT_FORMAT_REDUNDANT: -+ crc32_offset = offsetof(struct u_boot_env_image_redundant, crc32); -+ crc32_data_offset = offsetof(struct u_boot_env_image_redundant, mark); -+ data_offset = offsetof(struct u_boot_env_image_redundant, data); -+ break; -+ } -+ crc32 = le32_to_cpu(*(uint32_t *)(buf + crc32_offset)); -+ crc32_data_len = priv->mtd->size - crc32_data_offset; -+ data_len = priv->mtd->size - data_offset; -+ -+ calc = crc32(~0, buf + crc32_data_offset, crc32_data_len) ^ ~0L; -+ if (calc != crc32) { -+ dev_err(dev, "Invalid calculated CRC32: 0x%08x (expected: 0x%08x)\n", calc, crc32); -+ err = -EINVAL; -+ goto err_kfree; -+ } -+ -+ buf[priv->mtd->size - 1] = '\0'; -+ err = u_boot_env_add_cells(priv, buf, data_offset, data_len); -+ if (err) -+ dev_err(dev, "Failed to add cells: %d\n", err); -+ -+err_kfree: -+ kfree(buf); -+err_out: -+ return err; -+} -+ -+static int u_boot_env_probe(struct platform_device *pdev) -+{ -+ struct nvmem_config config = { -+ .name = "u-boot-env", -+ .reg_read = u_boot_env_read, -+ }; -+ struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; -+ struct u_boot_env *priv; -+ int err; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ priv->dev = dev; -+ -+ priv->format = (uintptr_t)of_device_get_match_data(dev); -+ -+ priv->mtd = of_get_mtd_device_by_node(np); -+ if (IS_ERR(priv->mtd)) { -+ dev_err_probe(dev, PTR_ERR(priv->mtd), "Failed to get %pOF MTD\n", np); -+ return PTR_ERR(priv->mtd); -+ } -+ -+ err = u_boot_env_parse(priv); -+ if (err) -+ return err; -+ -+ config.dev = dev; -+ config.cells = priv->cells; -+ config.ncells = priv->ncells; -+ config.priv = priv; -+ config.size = priv->mtd->size; -+ -+ return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config)); -+} -+ -+static const struct of_device_id u_boot_env_of_match_table[] = { -+ { .compatible = "u-boot,env", .data = (void *)U_BOOT_FORMAT_SINGLE, }, -+ { .compatible = "u-boot,env-redundant-bool", .data = (void *)U_BOOT_FORMAT_REDUNDANT, }, -+ { .compatible = "u-boot,env-redundant-count", .data = (void *)U_BOOT_FORMAT_REDUNDANT, }, -+ {}, -+}; -+ -+static struct platform_driver u_boot_env_driver = { -+ .probe = u_boot_env_probe, -+ .driver = { -+ .name = "u_boot_env", -+ .of_match_table = u_boot_env_of_match_table, -+ }, -+}; -+module_platform_driver(u_boot_env_driver); -+ -+MODULE_AUTHOR("Rafał Miłecki"); -+MODULE_LICENSE("GPL"); -+MODULE_DEVICE_TABLE(of, u_boot_env_of_match_table); diff --git a/target/linux/generic/backport-5.10/811-v6.1-0004-nvmem-brcm_nvram-Use-kzalloc-for-allocating-only-one.patch b/target/linux/generic/backport-5.10/811-v6.1-0004-nvmem-brcm_nvram-Use-kzalloc-for-allocating-only-one.patch deleted file mode 100644 index 48ad63fab5..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0004-nvmem-brcm_nvram-Use-kzalloc-for-allocating-only-one.patch +++ /dev/null @@ -1,29 +0,0 @@ -From d3524bb5b9a0c567b853a0024526afe87dde01ed Mon Sep 17 00:00:00 2001 -From: Kenneth Lee -Date: Fri, 16 Sep 2022 13:20:52 +0100 -Subject: [PATCH] nvmem: brcm_nvram: Use kzalloc for allocating only one - element - -Use kzalloc(...) rather than kcalloc(1, ...) because the number of -elements we are specifying in this case is 1, so kzalloc would -accomplish the same thing and we can simplify. - -Signed-off-by: Kenneth Lee -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220916122100.170016-6-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/brcm_nvram.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/brcm_nvram.c -+++ b/drivers/nvmem/brcm_nvram.c -@@ -96,7 +96,7 @@ static int brcm_nvram_parse(struct brcm_ - - len = le32_to_cpu(header.len); - -- data = kcalloc(1, len, GFP_KERNEL); -+ data = kzalloc(len, GFP_KERNEL); - memcpy_fromio(data, priv->base, len); - data[len - 1] = '\0'; - diff --git a/target/linux/generic/backport-5.10/811-v6.1-0005-nvmem-prefix-all-symbols-with-NVMEM_.patch b/target/linux/generic/backport-5.10/811-v6.1-0005-nvmem-prefix-all-symbols-with-NVMEM_.patch deleted file mode 100644 index a3d256d5c7..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0005-nvmem-prefix-all-symbols-with-NVMEM_.patch +++ /dev/null @@ -1,270 +0,0 @@ -From 28fc7c986f01fdcfd28af648be2597624cac0e27 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 16 Sep 2022 13:20:54 +0100 -Subject: [PATCH] nvmem: prefix all symbols with NVMEM_ -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This unifies all NVMEM symbols. They follow one style now. - -Reviewed-by: Matthias Brugger -Acked-by: Arnd Bergmann -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220916122100.170016-8-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - arch/arm/configs/multi_v7_defconfig | 6 +++--- - arch/arm/configs/qcom_defconfig | 2 +- - arch/arm64/configs/defconfig | 10 +++++----- - arch/mips/configs/ci20_defconfig | 2 +- - drivers/cpufreq/Kconfig.arm | 2 +- - drivers/nvmem/Kconfig | 24 ++++++++++++------------ - drivers/nvmem/Makefile | 24 ++++++++++++------------ - drivers/soc/mediatek/Kconfig | 2 +- - drivers/thermal/qcom/Kconfig | 2 +- - 9 files changed, 37 insertions(+), 37 deletions(-) - ---- a/arch/arm/configs/multi_v7_defconfig -+++ b/arch/arm/configs/multi_v7_defconfig -@@ -1085,10 +1085,10 @@ CONFIG_OMAP_USB2=y - CONFIG_TI_PIPE3=y - CONFIG_TWL4030_USB=m - CONFIG_NVMEM_IMX_OCOTP=y --CONFIG_ROCKCHIP_EFUSE=m -+CONFIG_NVMEM_ROCKCHIP_EFUSE=m - CONFIG_NVMEM_SUNXI_SID=y - CONFIG_NVMEM_VF610_OCOTP=y --CONFIG_MESON_MX_EFUSE=m -+CONFIG_NVMEM_MESON_MX_EFUSE=m - CONFIG_FSI=m - CONFIG_FSI_MASTER_GPIO=m - CONFIG_FSI_MASTER_HUB=m ---- a/arch/arm/configs/qcom_defconfig -+++ b/arch/arm/configs/qcom_defconfig -@@ -257,7 +257,7 @@ CONFIG_PHY_QCOM_APQ8064_SATA=y - CONFIG_PHY_QCOM_IPQ806X_SATA=y - CONFIG_PHY_QCOM_USB_HS=y - CONFIG_PHY_QCOM_USB_HSIC=y --CONFIG_QCOM_QFPROM=y -+CONFIG_NVMEM_QCOM_QFPROM=y - CONFIG_INTERCONNECT=y - CONFIG_INTERCONNECT_QCOM=y - CONFIG_INTERCONNECT_QCOM_MSM8974=m ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -1022,11 +1022,11 @@ CONFIG_QCOM_L2_PMU=y - CONFIG_QCOM_L3_PMU=y - CONFIG_NVMEM_IMX_OCOTP=y - CONFIG_NVMEM_IMX_OCOTP_SCU=y --CONFIG_QCOM_QFPROM=y --CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_NVMEM_QCOM_QFPROM=y -+CONFIG_NVMEM_ROCKCHIP_EFUSE=y - CONFIG_NVMEM_SUNXI_SID=y --CONFIG_UNIPHIER_EFUSE=y --CONFIG_MESON_EFUSE=m -+CONFIG_NVMEM_UNIPHIER_EFUSE=y -+CONFIG_NVMEM_MESON_EFUSE=m - CONFIG_FPGA=y - CONFIG_FPGA_MGR_STRATIX10_SOC=m - CONFIG_FPGA_BRIDGE=m ---- a/drivers/cpufreq/Kconfig.arm -+++ b/drivers/cpufreq/Kconfig.arm -@@ -131,7 +131,7 @@ config ARM_OMAP2PLUS_CPUFREQ - config ARM_QCOM_CPUFREQ_NVMEM - tristate "Qualcomm nvmem based CPUFreq" - depends on ARCH_QCOM -- depends on QCOM_QFPROM -+ depends on NVMEM_QCOM_QFPROM - depends on QCOM_SMEM - select PM_OPP - help ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -52,7 +52,7 @@ config NVMEM_IMX_OCOTP_SCU - This is a driver for the SCU On-Chip OTP Controller (OCOTP) - available on i.MX8 SoCs. - --config JZ4780_EFUSE -+config NVMEM_JZ4780_EFUSE - tristate "JZ4780 EFUSE Memory Support" - depends on MACH_INGENIC || COMPILE_TEST - depends on HAS_IOMEM -@@ -96,7 +96,7 @@ config NVMEM_MXS_OCOTP - This driver can also be built as a module. If so, the module - will be called nvmem-mxs-ocotp. - --config MTK_EFUSE -+config NVMEM_MTK_EFUSE - tristate "Mediatek SoCs EFUSE support" - depends on ARCH_MEDIATEK || COMPILE_TEST - depends on HAS_IOMEM -@@ -107,7 +107,7 @@ config MTK_EFUSE - This driver can also be built as a module. If so, the module - will be called efuse-mtk. - --config MICROCHIP_OTPC -+config NVMEM_MICROCHIP_OTPC - tristate "Microchip OTPC support" - depends on ARCH_AT91 || COMPILE_TEST - help -@@ -126,7 +126,7 @@ config NVMEM_NINTENDO_OTP - This driver can also be built as a module. If so, the module - will be called nvmem-nintendo-otp. - --config QCOM_QFPROM -+config NVMEM_QCOM_QFPROM - tristate "QCOM QFPROM Support" - depends on ARCH_QCOM || COMPILE_TEST - depends on HAS_IOMEM -@@ -145,7 +145,7 @@ config NVMEM_SPMI_SDAM - Qualcomm Technologies, Inc. PMICs. It provides the clients - an interface to read/write to the SDAM module's shared memory. - --config ROCKCHIP_EFUSE -+config NVMEM_ROCKCHIP_EFUSE - tristate "Rockchip eFuse Support" - depends on ARCH_ROCKCHIP || COMPILE_TEST - depends on HAS_IOMEM -@@ -156,7 +156,7 @@ config ROCKCHIP_EFUSE - This driver can also be built as a module. If so, the module - will be called nvmem_rockchip_efuse. - --config ROCKCHIP_OTP -+config NVMEM_ROCKCHIP_OTP - tristate "Rockchip OTP controller support" - depends on ARCH_ROCKCHIP || COMPILE_TEST - depends on HAS_IOMEM -@@ -199,7 +199,7 @@ config NVMEM_SUNXI_SID - This driver can also be built as a module. If so, the module - will be called nvmem_sunxi_sid. - --config UNIPHIER_EFUSE -+config NVMEM_UNIPHIER_EFUSE - tristate "UniPhier SoCs eFuse support" - depends on ARCH_UNIPHIER || COMPILE_TEST - depends on HAS_IOMEM -@@ -221,7 +221,7 @@ config NVMEM_VF610_OCOTP - This driver can also be build as a module. If so, the module will - be called nvmem-vf610-ocotp. - --config MESON_EFUSE -+config NVMEM_MESON_EFUSE - tristate "Amlogic Meson GX eFuse Support" - depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM - help -@@ -231,7 +231,7 @@ config MESON_EFUSE - This driver can also be built as a module. If so, the module - will be called nvmem_meson_efuse. - --config MESON_MX_EFUSE -+config NVMEM_MESON_MX_EFUSE - tristate "Amlogic Meson6/Meson8/Meson8b eFuse Support" - depends on ARCH_MESON || COMPILE_TEST - help -@@ -251,13 +251,13 @@ config NVMEM_SNVS_LPGPR - This driver can also be built as a module. If so, the module - will be called nvmem-snvs-lpgpr. - --config RAVE_SP_EEPROM -+config NVMEM_RAVE_SP_EEPROM - tristate "Rave SP EEPROM Support" - depends on RAVE_SP_CORE - help - Say y here to enable Rave SP EEPROM support. - --config SC27XX_EFUSE -+config NVMEM_SC27XX_EFUSE - tristate "Spreadtrum SC27XX eFuse Support" - depends on MFD_SC27XX_PMIC || COMPILE_TEST - depends on HAS_IOMEM -@@ -278,7 +278,7 @@ config NVMEM_ZYNQMP - - If sure, say yes. If unsure, say no. - --config SPRD_EFUSE -+config NVMEM_SPRD_EFUSE - tristate "Spreadtrum SoC eFuse Support" - depends on ARCH_SPRD || COMPILE_TEST - depends on HAS_IOMEM ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -15,7 +15,7 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-i - nvmem-imx-ocotp-y := imx-ocotp.o - obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o - nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o --obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o -+obj-$(CONFIG_NVMEM_JZ4780_EFUSE) += nvmem_jz4780_efuse.o - nvmem_jz4780_efuse-y := jz4780-efuse.o - obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o - nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o -@@ -25,37 +25,37 @@ obj-$(CONFIG_NVMEM_MXS_OCOTP) += nvmem-m - nvmem-mxs-ocotp-y := mxs-ocotp.o - obj-$(CONFIG_NVMEM_NINTENDO_OTP) += nvmem-nintendo-otp.o - nvmem-nintendo-otp-y := nintendo-otp.o --obj-$(CONFIG_MTK_EFUSE) += nvmem_mtk-efuse.o -+obj-$(CONFIG_NVMEM_MTK_EFUSE) += nvmem_mtk-efuse.o - nvmem_mtk-efuse-y := mtk-efuse.o --obj-$(CONFIG_QCOM_QFPROM) += nvmem_qfprom.o -+obj-$(CONFIG_NVMEM_QCOM_QFPROM) += nvmem_qfprom.o - nvmem_qfprom-y := qfprom.o - obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o - nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o --obj-$(CONFIG_ROCKCHIP_EFUSE) += nvmem_rockchip_efuse.o -+obj-$(CONFIG_NVMEM_ROCKCHIP_EFUSE) += nvmem_rockchip_efuse.o - nvmem_rockchip_efuse-y := rockchip-efuse.o --obj-$(CONFIG_ROCKCHIP_OTP) += nvmem-rockchip-otp.o -+obj-$(CONFIG_NVMEM_ROCKCHIP_OTP) += nvmem-rockchip-otp.o - nvmem-rockchip-otp-y := rockchip-otp.o - obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o - nvmem_stm32_romem-y := stm32-romem.o - obj-$(CONFIG_NVMEM_STM32_ROMEM) += nvmem_stm32_romem.o - nvmem_sunxi_sid-y := sunxi_sid.o --obj-$(CONFIG_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o -+obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o - nvmem-uniphier-efuse-y := uniphier-efuse.o - obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o - nvmem-vf610-ocotp-y := vf610-ocotp.o --obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o -+obj-$(CONFIG_NVMEM_MESON_EFUSE) += nvmem_meson_efuse.o - nvmem_meson_efuse-y := meson-efuse.o --obj-$(CONFIG_MESON_MX_EFUSE) += nvmem_meson_mx_efuse.o -+obj-$(CONFIG_NVMEM_MESON_MX_EFUSE) += nvmem_meson_mx_efuse.o - nvmem_meson_mx_efuse-y := meson-mx-efuse.o - obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o - nvmem_snvs_lpgpr-y := snvs_lpgpr.o --obj-$(CONFIG_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o -+obj-$(CONFIG_NVMEM_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o - nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o --obj-$(CONFIG_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o -+obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o - nvmem-sc27xx-efuse-y := sc27xx-efuse.o - obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynqmp_nvmem.o - nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o --obj-$(CONFIG_SPRD_EFUSE) += nvmem_sprd_efuse.o -+obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o - nvmem_sprd_efuse-y := sprd-efuse.o - obj-$(CONFIG_NVMEM_RMEM) += nvmem-rmem.o - nvmem-rmem-y := rmem.o -@@ -67,7 +67,7 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvm - nvmem_sunplus_ocotp-y := sunplus-ocotp.o - obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o - nvmem-apple-efuses-y := apple-efuses.o --obj-$(CONFIG_MICROCHIP_OTPC) += nvmem-microchip-otpc.o -+obj-$(CONFIG_NVMEM_MICROCHIP_OTPC) += nvmem-microchip-otpc.o - nvmem-microchip-otpc-y := microchip-otpc.o - obj-$(CONFIG_NVMEM_U_BOOT_ENV) += nvmem_u-boot-env.o - nvmem_u-boot-env-y := u-boot-env.o ---- a/drivers/thermal/qcom/Kconfig -+++ b/drivers/thermal/qcom/Kconfig -@@ -1,7 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0-only - config QCOM_TSENS - tristate "Qualcomm TSENS Temperature Alarm" -- depends on QCOM_QFPROM -+ depends on NVMEM_QCOM_QFPROM - depends on ARCH_QCOM || COMPILE_TEST - help - This enables the thermal sysfs driver for the TSENS device. It shows diff --git a/target/linux/generic/backport-5.10/811-v6.1-0006-nvmem-sort-config-symbols-alphabetically.patch b/target/linux/generic/backport-5.10/811-v6.1-0006-nvmem-sort-config-symbols-alphabetically.patch deleted file mode 100644 index 4e45524bff..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0006-nvmem-sort-config-symbols-alphabetically.patch +++ /dev/null @@ -1,535 +0,0 @@ -From a06d9e5a63b7c2f622c908cd9600ce735e70f7c6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 16 Sep 2022 13:20:55 +0100 -Subject: [PATCH] nvmem: sort config symbols alphabetically -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -1. Match what most subsystems do -2. Simplify maintenance a bit -3. Reduce amount of conflicts for new drivers patches - -While at it unify indent level in Makefile. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220916122100.170016-9-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 300 +++++++++++++++++++++-------------------- - drivers/nvmem/Makefile | 114 ++++++++-------- - 2 files changed, 208 insertions(+), 206 deletions(-) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -21,6 +21,40 @@ config NVMEM_SYSFS - This interface is mostly used by userspace applications to - read/write directly into nvmem. - -+# Devices -+ -+config NVMEM_APPLE_EFUSES -+ tristate "Apple eFuse support" -+ depends on ARCH_APPLE || COMPILE_TEST -+ default ARCH_APPLE -+ help -+ Say y here to enable support for reading eFuses on Apple SoCs -+ such as the M1. These are e.g. used to store factory programmed -+ calibration data required for the PCIe or the USB-C PHY. -+ -+ This driver can also be built as a module. If so, the module will -+ be called nvmem-apple-efuses. -+ -+config NVMEM_BCM_OCOTP -+ tristate "Broadcom On-Chip OTP Controller support" -+ depends on ARCH_BCM_IPROC || COMPILE_TEST -+ depends on HAS_IOMEM -+ default ARCH_BCM_IPROC -+ help -+ Say y here to enable read/write access to the Broadcom OTP -+ controller. -+ -+ This driver can also be built as a module. If so, the module -+ will be called nvmem-bcm-ocotp. -+ -+config NVMEM_BRCM_NVRAM -+ tristate "Broadcom's NVRAM support" -+ depends on ARCH_BCM_5301X || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ This driver provides support for Broadcom's NVRAM that can be accessed -+ using I/O mapping. -+ - config NVMEM_IMX_IIM - tristate "i.MX IC Identification Module support" - depends on ARCH_MXC || COMPILE_TEST -@@ -64,6 +98,19 @@ config NVMEM_JZ4780_EFUSE - To compile this driver as a module, choose M here: the module - will be called nvmem_jz4780_efuse. - -+config NVMEM_LAYERSCAPE_SFP -+ tristate "Layerscape SFP (Security Fuse Processor) support" -+ depends on ARCH_LAYERSCAPE || COMPILE_TEST -+ depends on HAS_IOMEM -+ select REGMAP_MMIO -+ help -+ This driver provides support to read the eFuses on Freescale -+ Layerscape SoC's. For example, the vendor provides a per part -+ unique ID there. -+ -+ This driver can also be built as a module. If so, the module -+ will be called layerscape-sfp. -+ - config NVMEM_LPC18XX_EEPROM - tristate "NXP LPC18XX EEPROM Memory Support" - depends on ARCH_LPC18XX || COMPILE_TEST -@@ -84,17 +131,32 @@ config NVMEM_LPC18XX_OTP - To compile this driver as a module, choose M here: the module - will be called nvmem_lpc18xx_otp. - --config NVMEM_MXS_OCOTP -- tristate "Freescale MXS On-Chip OTP Memory Support" -- depends on ARCH_MXS || COMPILE_TEST -- depends on HAS_IOMEM -+config NVMEM_MESON_EFUSE -+ tristate "Amlogic Meson GX eFuse Support" -+ depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM - help -- If you say Y here, you will get readonly access to the -- One Time Programmable memory pages that are stored -- on the Freescale i.MX23/i.MX28 processor. -+ This is a driver to retrieve specific values from the eFuse found on -+ the Amlogic Meson GX SoCs. - - This driver can also be built as a module. If so, the module -- will be called nvmem-mxs-ocotp. -+ will be called nvmem_meson_efuse. -+ -+config NVMEM_MESON_MX_EFUSE -+ tristate "Amlogic Meson6/Meson8/Meson8b eFuse Support" -+ depends on ARCH_MESON || COMPILE_TEST -+ help -+ This is a driver to retrieve specific values from the eFuse found on -+ the Amlogic Meson6, Meson8 and Meson8b SoCs. -+ -+ This driver can also be built as a module. If so, the module -+ will be called nvmem_meson_mx_efuse. -+ -+config NVMEM_MICROCHIP_OTPC -+ tristate "Microchip OTPC support" -+ depends on ARCH_AT91 || COMPILE_TEST -+ help -+ This driver enable the OTP controller available on Microchip SAMA7G5 -+ SoCs. It controlls the access to the OTP memory connected to it. - - config NVMEM_MTK_EFUSE - tristate "Mediatek SoCs EFUSE support" -@@ -107,12 +169,17 @@ config NVMEM_MTK_EFUSE - This driver can also be built as a module. If so, the module - will be called efuse-mtk. - --config NVMEM_MICROCHIP_OTPC -- tristate "Microchip OTPC support" -- depends on ARCH_AT91 || COMPILE_TEST -+config NVMEM_MXS_OCOTP -+ tristate "Freescale MXS On-Chip OTP Memory Support" -+ depends on ARCH_MXS || COMPILE_TEST -+ depends on HAS_IOMEM - help -- This driver enable the OTP controller available on Microchip SAMA7G5 -- SoCs. It controlls the access to the OTP memory connected to it. -+ If you say Y here, you will get readonly access to the -+ One Time Programmable memory pages that are stored -+ on the Freescale i.MX23/i.MX28 processor. -+ -+ This driver can also be built as a module. If so, the module -+ will be called nvmem-mxs-ocotp. - - config NVMEM_NINTENDO_OTP - tristate "Nintendo Wii and Wii U OTP Support" -@@ -137,13 +204,21 @@ config NVMEM_QCOM_QFPROM - This driver can also be built as a module. If so, the module - will be called nvmem_qfprom. - --config NVMEM_SPMI_SDAM -- tristate "SPMI SDAM Support" -- depends on SPMI -+config NVMEM_RAVE_SP_EEPROM -+ tristate "Rave SP EEPROM Support" -+ depends on RAVE_SP_CORE - help -- This driver supports the Shared Direct Access Memory Module on -- Qualcomm Technologies, Inc. PMICs. It provides the clients -- an interface to read/write to the SDAM module's shared memory. -+ Say y here to enable Rave SP EEPROM support. -+ -+config NVMEM_RMEM -+ tristate "Reserved Memory Based Driver Support" -+ depends on HAS_IOMEM -+ help -+ This driver maps reserved memory into an nvmem device. It might be -+ useful to expose information left by firmware in memory. -+ -+ This driver can also be built as a module. If so, the module -+ will be called nvmem-rmem. - - config NVMEM_ROCKCHIP_EFUSE - tristate "Rockchip eFuse Support" -@@ -167,79 +242,16 @@ config NVMEM_ROCKCHIP_OTP - This driver can also be built as a module. If so, the module - will be called nvmem_rockchip_otp. - --config NVMEM_BCM_OCOTP -- tristate "Broadcom On-Chip OTP Controller support" -- depends on ARCH_BCM_IPROC || COMPILE_TEST -- depends on HAS_IOMEM -- default ARCH_BCM_IPROC -- help -- Say y here to enable read/write access to the Broadcom OTP -- controller. -- -- This driver can also be built as a module. If so, the module -- will be called nvmem-bcm-ocotp. -- --config NVMEM_STM32_ROMEM -- tristate "STMicroelectronics STM32 factory-programmed memory support" -- depends on ARCH_STM32 || COMPILE_TEST -- help -- Say y here to enable read-only access for STMicroelectronics STM32 -- factory-programmed memory area. -- -- This driver can also be built as a module. If so, the module -- will be called nvmem-stm32-romem. -- --config NVMEM_SUNXI_SID -- tristate "Allwinner SoCs SID support" -- depends on ARCH_SUNXI -- help -- This is a driver for the 'security ID' available on various Allwinner -- devices. -- -- This driver can also be built as a module. If so, the module -- will be called nvmem_sunxi_sid. -- --config NVMEM_UNIPHIER_EFUSE -- tristate "UniPhier SoCs eFuse support" -- depends on ARCH_UNIPHIER || COMPILE_TEST -- depends on HAS_IOMEM -- help -- This is a simple driver to dump specified values of UniPhier SoC -- from eFuse. -- -- This driver can also be built as a module. If so, the module -- will be called nvmem-uniphier-efuse. -- --config NVMEM_VF610_OCOTP -- tristate "VF610 SoC OCOTP support" -- depends on SOC_VF610 || COMPILE_TEST -+config NVMEM_SC27XX_EFUSE -+ tristate "Spreadtrum SC27XX eFuse Support" -+ depends on MFD_SC27XX_PMIC || COMPILE_TEST - depends on HAS_IOMEM - help -- This is a driver for the 'OCOTP' peripheral available on Vybrid -- devices like VF5xx and VF6xx. -- -- This driver can also be build as a module. If so, the module will -- be called nvmem-vf610-ocotp. -- --config NVMEM_MESON_EFUSE -- tristate "Amlogic Meson GX eFuse Support" -- depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM -- help -- This is a driver to retrieve specific values from the eFuse found on -- the Amlogic Meson GX SoCs. -- -- This driver can also be built as a module. If so, the module -- will be called nvmem_meson_efuse. -- --config NVMEM_MESON_MX_EFUSE -- tristate "Amlogic Meson6/Meson8/Meson8b eFuse Support" -- depends on ARCH_MESON || COMPILE_TEST -- help -- This is a driver to retrieve specific values from the eFuse found on -- the Amlogic Meson6, Meson8 and Meson8b SoCs. -+ This is a simple driver to dump specified values of Spreadtrum -+ SC27XX PMICs from eFuse. - - This driver can also be built as a module. If so, the module -- will be called nvmem_meson_mx_efuse. -+ will be called nvmem-sc27xx-efuse. - - config NVMEM_SNVS_LPGPR - tristate "Support for Low Power General Purpose Register" -@@ -251,32 +263,13 @@ config NVMEM_SNVS_LPGPR - This driver can also be built as a module. If so, the module - will be called nvmem-snvs-lpgpr. - --config NVMEM_RAVE_SP_EEPROM -- tristate "Rave SP EEPROM Support" -- depends on RAVE_SP_CORE -- help -- Say y here to enable Rave SP EEPROM support. -- --config NVMEM_SC27XX_EFUSE -- tristate "Spreadtrum SC27XX eFuse Support" -- depends on MFD_SC27XX_PMIC || COMPILE_TEST -- depends on HAS_IOMEM -- help -- This is a simple driver to dump specified values of Spreadtrum -- SC27XX PMICs from eFuse. -- -- This driver can also be built as a module. If so, the module -- will be called nvmem-sc27xx-efuse. -- --config NVMEM_ZYNQMP -- bool "Xilinx ZYNQMP SoC nvmem firmware support" -- depends on ARCH_ZYNQMP -+config NVMEM_SPMI_SDAM -+ tristate "SPMI SDAM Support" -+ depends on SPMI - help -- This is a driver to access hardware related data like -- soc revision, IDCODE... etc by using the firmware -- interface. -- -- If sure, say yes. If unsure, say no. -+ This driver supports the Shared Direct Access Memory Module on -+ Qualcomm Technologies, Inc. PMICs. It provides the clients -+ an interface to read/write to the SDAM module's shared memory. - - config NVMEM_SPRD_EFUSE - tristate "Spreadtrum SoC eFuse Support" -@@ -289,36 +282,15 @@ config NVMEM_SPRD_EFUSE - This driver can also be built as a module. If so, the module - will be called nvmem-sprd-efuse. - --config NVMEM_RMEM -- tristate "Reserved Memory Based Driver Support" -- depends on HAS_IOMEM -- help -- This driver maps reserved memory into an nvmem device. It might be -- useful to expose information left by firmware in memory. -- -- This driver can also be built as a module. If so, the module -- will be called nvmem-rmem. -- --config NVMEM_BRCM_NVRAM -- tristate "Broadcom's NVRAM support" -- depends on ARCH_BCM_5301X || COMPILE_TEST -- depends on HAS_IOMEM -- help -- This driver provides support for Broadcom's NVRAM that can be accessed -- using I/O mapping. -- --config NVMEM_LAYERSCAPE_SFP -- tristate "Layerscape SFP (Security Fuse Processor) support" -- depends on ARCH_LAYERSCAPE || COMPILE_TEST -- depends on HAS_IOMEM -- select REGMAP_MMIO -+config NVMEM_STM32_ROMEM -+ tristate "STMicroelectronics STM32 factory-programmed memory support" -+ depends on ARCH_STM32 || COMPILE_TEST - help -- This driver provides support to read the eFuses on Freescale -- Layerscape SoC's. For example, the vendor provides a per part -- unique ID there. -+ Say y here to enable read-only access for STMicroelectronics STM32 -+ factory-programmed memory area. - - This driver can also be built as a module. If so, the module -- will be called layerscape-sfp. -+ will be called nvmem-stm32-romem. - - config NVMEM_SUNPLUS_OCOTP - tristate "Sunplus SoC OTP support" -@@ -332,17 +304,15 @@ config NVMEM_SUNPLUS_OCOTP - This driver can also be built as a module. If so, the module - will be called nvmem-sunplus-ocotp. - --config NVMEM_APPLE_EFUSES -- tristate "Apple eFuse support" -- depends on ARCH_APPLE || COMPILE_TEST -- default ARCH_APPLE -+config NVMEM_SUNXI_SID -+ tristate "Allwinner SoCs SID support" -+ depends on ARCH_SUNXI - help -- Say y here to enable support for reading eFuses on Apple SoCs -- such as the M1. These are e.g. used to store factory programmed -- calibration data required for the PCIe or the USB-C PHY. -+ This is a driver for the 'security ID' available on various Allwinner -+ devices. - -- This driver can also be built as a module. If so, the module will -- be called nvmem-apple-efuses. -+ This driver can also be built as a module. If so, the module -+ will be called nvmem_sunxi_sid. - - config NVMEM_U_BOOT_ENV - tristate "U-Boot environment variables support" -@@ -357,4 +327,36 @@ config NVMEM_U_BOOT_ENV - - If compiled as module it will be called nvmem_u-boot-env. - -+config NVMEM_UNIPHIER_EFUSE -+ tristate "UniPhier SoCs eFuse support" -+ depends on ARCH_UNIPHIER || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ This is a simple driver to dump specified values of UniPhier SoC -+ from eFuse. -+ -+ This driver can also be built as a module. If so, the module -+ will be called nvmem-uniphier-efuse. -+ -+config NVMEM_VF610_OCOTP -+ tristate "VF610 SoC OCOTP support" -+ depends on SOC_VF610 || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ This is a driver for the 'OCOTP' peripheral available on Vybrid -+ devices like VF5xx and VF6xx. -+ -+ This driver can also be build as a module. If so, the module will -+ be called nvmem-vf610-ocotp. -+ -+config NVMEM_ZYNQMP -+ bool "Xilinx ZYNQMP SoC nvmem firmware support" -+ depends on ARCH_ZYNQMP -+ help -+ This is a driver to access hardware related data like -+ soc revision, IDCODE... etc by using the firmware -+ interface. -+ -+ If sure, say yes. If unsure, say no. -+ - endif ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -7,67 +7,67 @@ obj-$(CONFIG_NVMEM) += nvmem_core.o - nvmem_core-y := core.o - - # Devices --obj-$(CONFIG_NVMEM_BCM_OCOTP) += nvmem-bcm-ocotp.o --nvmem-bcm-ocotp-y := bcm-ocotp.o --obj-$(CONFIG_NVMEM_IMX_IIM) += nvmem-imx-iim.o --nvmem-imx-iim-y := imx-iim.o --obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o --nvmem-imx-ocotp-y := imx-ocotp.o -+obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o -+nvmem-apple-efuses-y := apple-efuses.o -+obj-$(CONFIG_NVMEM_BCM_OCOTP) += nvmem-bcm-ocotp.o -+nvmem-bcm-ocotp-y := bcm-ocotp.o -+obj-$(CONFIG_NVMEM_BRCM_NVRAM) += nvmem_brcm_nvram.o -+nvmem_brcm_nvram-y := brcm_nvram.o -+obj-$(CONFIG_NVMEM_IMX_IIM) += nvmem-imx-iim.o -+nvmem-imx-iim-y := imx-iim.o -+obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o -+nvmem-imx-ocotp-y := imx-ocotp.o - obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o --nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o --obj-$(CONFIG_NVMEM_JZ4780_EFUSE) += nvmem_jz4780_efuse.o --nvmem_jz4780_efuse-y := jz4780-efuse.o -+nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o -+obj-$(CONFIG_NVMEM_JZ4780_EFUSE) += nvmem_jz4780_efuse.o -+nvmem_jz4780_efuse-y := jz4780-efuse.o -+obj-$(CONFIG_NVMEM_LAYERSCAPE_SFP) += nvmem-layerscape-sfp.o -+nvmem-layerscape-sfp-y := layerscape-sfp.o - obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o --nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o --obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o --nvmem_lpc18xx_otp-y := lpc18xx_otp.o --obj-$(CONFIG_NVMEM_MXS_OCOTP) += nvmem-mxs-ocotp.o --nvmem-mxs-ocotp-y := mxs-ocotp.o --obj-$(CONFIG_NVMEM_NINTENDO_OTP) += nvmem-nintendo-otp.o --nvmem-nintendo-otp-y := nintendo-otp.o -+nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o -+obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o -+nvmem_lpc18xx_otp-y := lpc18xx_otp.o -+obj-$(CONFIG_NVMEM_MESON_EFUSE) += nvmem_meson_efuse.o -+nvmem_meson_efuse-y := meson-efuse.o -+obj-$(CONFIG_NVMEM_MESON_MX_EFUSE) += nvmem_meson_mx_efuse.o -+nvmem_meson_mx_efuse-y := meson-mx-efuse.o -+obj-$(CONFIG_NVMEM_MICROCHIP_OTPC) += nvmem-microchip-otpc.o -+nvmem-microchip-otpc-y := microchip-otpc.o - obj-$(CONFIG_NVMEM_MTK_EFUSE) += nvmem_mtk-efuse.o --nvmem_mtk-efuse-y := mtk-efuse.o --obj-$(CONFIG_NVMEM_QCOM_QFPROM) += nvmem_qfprom.o --nvmem_qfprom-y := qfprom.o --obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o --nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o -+nvmem_mtk-efuse-y := mtk-efuse.o -+obj-$(CONFIG_NVMEM_MXS_OCOTP) += nvmem-mxs-ocotp.o -+nvmem-mxs-ocotp-y := mxs-ocotp.o -+obj-$(CONFIG_NVMEM_NINTENDO_OTP) += nvmem-nintendo-otp.o -+nvmem-nintendo-otp-y := nintendo-otp.o -+obj-$(CONFIG_NVMEM_QCOM_QFPROM) += nvmem_qfprom.o -+nvmem_qfprom-y := qfprom.o -+obj-$(CONFIG_NVMEM_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o -+nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o -+obj-$(CONFIG_NVMEM_RMEM) += nvmem-rmem.o -+nvmem-rmem-y := rmem.o - obj-$(CONFIG_NVMEM_ROCKCHIP_EFUSE) += nvmem_rockchip_efuse.o --nvmem_rockchip_efuse-y := rockchip-efuse.o -+nvmem_rockchip_efuse-y := rockchip-efuse.o - obj-$(CONFIG_NVMEM_ROCKCHIP_OTP) += nvmem-rockchip-otp.o --nvmem-rockchip-otp-y := rockchip-otp.o --obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o --nvmem_stm32_romem-y := stm32-romem.o --obj-$(CONFIG_NVMEM_STM32_ROMEM) += nvmem_stm32_romem.o --nvmem_sunxi_sid-y := sunxi_sid.o --obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o --nvmem-uniphier-efuse-y := uniphier-efuse.o --obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o --nvmem-vf610-ocotp-y := vf610-ocotp.o --obj-$(CONFIG_NVMEM_MESON_EFUSE) += nvmem_meson_efuse.o --nvmem_meson_efuse-y := meson-efuse.o --obj-$(CONFIG_NVMEM_MESON_MX_EFUSE) += nvmem_meson_mx_efuse.o --nvmem_meson_mx_efuse-y := meson-mx-efuse.o --obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o --nvmem_snvs_lpgpr-y := snvs_lpgpr.o --obj-$(CONFIG_NVMEM_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o --nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o -+nvmem-rockchip-otp-y := rockchip-otp.o - obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o --nvmem-sc27xx-efuse-y := sc27xx-efuse.o --obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynqmp_nvmem.o --nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o --obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o --nvmem_sprd_efuse-y := sprd-efuse.o --obj-$(CONFIG_NVMEM_RMEM) += nvmem-rmem.o --nvmem-rmem-y := rmem.o --obj-$(CONFIG_NVMEM_BRCM_NVRAM) += nvmem_brcm_nvram.o --nvmem_brcm_nvram-y := brcm_nvram.o --obj-$(CONFIG_NVMEM_LAYERSCAPE_SFP) += nvmem-layerscape-sfp.o --nvmem-layerscape-sfp-y := layerscape-sfp.o -+nvmem-sc27xx-efuse-y := sc27xx-efuse.o -+obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o -+nvmem_snvs_lpgpr-y := snvs_lpgpr.o -+obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o -+nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o -+obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o -+nvmem_sprd_efuse-y := sprd-efuse.o -+obj-$(CONFIG_NVMEM_STM32_ROMEM) += nvmem_stm32_romem.o -+nvmem_stm32_romem-y := stm32-romem.o - obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o --nvmem_sunplus_ocotp-y := sunplus-ocotp.o --obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o --nvmem-apple-efuses-y := apple-efuses.o --obj-$(CONFIG_NVMEM_MICROCHIP_OTPC) += nvmem-microchip-otpc.o --nvmem-microchip-otpc-y := microchip-otpc.o --obj-$(CONFIG_NVMEM_U_BOOT_ENV) += nvmem_u-boot-env.o --nvmem_u-boot-env-y := u-boot-env.o -+nvmem_sunplus_ocotp-y := sunplus-ocotp.o -+obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o -+nvmem_sunxi_sid-y := sunxi_sid.o -+obj-$(CONFIG_NVMEM_U_BOOT_ENV) += nvmem_u-boot-env.o -+nvmem_u-boot-env-y := u-boot-env.o -+obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o -+nvmem-uniphier-efuse-y := uniphier-efuse.o -+obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o -+nvmem-vf610-ocotp-y := vf610-ocotp.o -+obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynqmp_nvmem.o -+nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o diff --git a/target/linux/generic/backport-5.10/811-v6.1-0007-nvmem-u-boot-env-find-Device-Tree-nodes-for-NVMEM-ce.patch b/target/linux/generic/backport-5.10/811-v6.1-0007-nvmem-u-boot-env-find-Device-Tree-nodes-for-NVMEM-ce.patch deleted file mode 100644 index e0a082adc4..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0007-nvmem-u-boot-env-find-Device-Tree-nodes-for-NVMEM-ce.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d4d432670f7dee0a5432fcffcfc8699b25181ace Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 16 Sep 2022 13:20:57 +0100 -Subject: [PATCH] nvmem: u-boot-env: find Device Tree nodes for NVMEM cells -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -DT binding allows specifying NVMEM cells as NVMEM device (provider) -subnodes. Looks for such subnodes when building NVMEM cells. - -This allows NVMEM consumers to use U-Boot environment variables. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220916122100.170016-11-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/u-boot-env.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/nvmem/u-boot-env.c -+++ b/drivers/nvmem/u-boot-env.c -@@ -92,6 +92,7 @@ static int u_boot_env_add_cells(struct u - return -ENOMEM; - priv->cells[idx].offset = data_offset + value - data; - priv->cells[idx].bytes = strlen(value); -+ priv->cells[idx].np = of_get_child_by_name(dev->of_node, priv->cells[idx].name); - } - - if (WARN_ON(idx != priv->ncells)) diff --git a/target/linux/generic/backport-5.10/811-v6.1-0008-nvmem-lan9662-otp-add-support.patch b/target/linux/generic/backport-5.10/811-v6.1-0008-nvmem-lan9662-otp-add-support.patch deleted file mode 100644 index 945c6128ff..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0008-nvmem-lan9662-otp-add-support.patch +++ /dev/null @@ -1,274 +0,0 @@ -From 9e8f208ad5229ddda97cd4a83ecf89c735d99592 Mon Sep 17 00:00:00 2001 -From: Horatiu Vultur -Date: Fri, 16 Sep 2022 13:20:59 +0100 -Subject: [PATCH] nvmem: lan9662-otp: add support - -Add support for OTP controller available on LAN9662. The OTPC controls -the access to a non-volatile memory. The size of the memory is 8KB. -The OTPC can access the memory based on an offset. -Implement both the read and the write functionality. - -Signed-off-by: Horatiu Vultur -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220916122100.170016-13-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 8 ++ - drivers/nvmem/Makefile | 2 + - drivers/nvmem/lan9662-otpc.c | 222 +++++++++++++++++++++++++++++++++++ - 3 files changed, 232 insertions(+) - create mode 100644 drivers/nvmem/lan9662-otpc.c - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -98,6 +98,14 @@ config NVMEM_JZ4780_EFUSE - To compile this driver as a module, choose M here: the module - will be called nvmem_jz4780_efuse. - -+config NVMEM_LAN9662_OTPC -+ tristate "Microchip LAN9662 OTP controller support" -+ depends on SOC_LAN966 || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ This driver enables the OTP controller available on Microchip LAN9662 -+ SoCs. It controls the access to the OTP memory connected to it. -+ - config NVMEM_LAYERSCAPE_SFP - tristate "Layerscape SFP (Security Fuse Processor) support" - depends on ARCH_LAYERSCAPE || COMPILE_TEST ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -21,6 +21,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvm - nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o - obj-$(CONFIG_NVMEM_JZ4780_EFUSE) += nvmem_jz4780_efuse.o - nvmem_jz4780_efuse-y := jz4780-efuse.o -+obj-$(CONFIG_NVMEM_LAN9662_OTPC) += nvmem-lan9662-otpc.o -+nvmem-lan9662-otpc-y := lan9662-otpc.o - obj-$(CONFIG_NVMEM_LAYERSCAPE_SFP) += nvmem-layerscape-sfp.o - nvmem-layerscape-sfp-y := layerscape-sfp.o - obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o ---- /dev/null -+++ b/drivers/nvmem/lan9662-otpc.c -@@ -0,0 +1,222 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define OTP_OTP_PWR_DN(t) (t + 0x00) -+#define OTP_OTP_PWR_DN_OTP_PWRDN_N BIT(0) -+#define OTP_OTP_ADDR_HI(t) (t + 0x04) -+#define OTP_OTP_ADDR_LO(t) (t + 0x08) -+#define OTP_OTP_PRGM_DATA(t) (t + 0x10) -+#define OTP_OTP_PRGM_MODE(t) (t + 0x14) -+#define OTP_OTP_PRGM_MODE_OTP_PGM_MODE_BYTE BIT(0) -+#define OTP_OTP_RD_DATA(t) (t + 0x18) -+#define OTP_OTP_FUNC_CMD(t) (t + 0x20) -+#define OTP_OTP_FUNC_CMD_OTP_PROGRAM BIT(1) -+#define OTP_OTP_FUNC_CMD_OTP_READ BIT(0) -+#define OTP_OTP_CMD_GO(t) (t + 0x28) -+#define OTP_OTP_CMD_GO_OTP_GO BIT(0) -+#define OTP_OTP_PASS_FAIL(t) (t + 0x2c) -+#define OTP_OTP_PASS_FAIL_OTP_READ_PROHIBITED BIT(3) -+#define OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED BIT(2) -+#define OTP_OTP_PASS_FAIL_OTP_FAIL BIT(0) -+#define OTP_OTP_STATUS(t) (t + 0x30) -+#define OTP_OTP_STATUS_OTP_CPUMPEN BIT(1) -+#define OTP_OTP_STATUS_OTP_BUSY BIT(0) -+ -+#define OTP_MEM_SIZE 8192 -+#define OTP_SLEEP_US 10 -+#define OTP_TIMEOUT_US 500000 -+ -+struct lan9662_otp { -+ struct device *dev; -+ void __iomem *base; -+}; -+ -+static bool lan9662_otp_wait_flag_clear(void __iomem *reg, u32 flag) -+{ -+ u32 val; -+ -+ return readl_poll_timeout(reg, val, !(val & flag), -+ OTP_SLEEP_US, OTP_TIMEOUT_US); -+} -+ -+static int lan9662_otp_power(struct lan9662_otp *otp, bool up) -+{ -+ void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); -+ -+ if (up) { -+ writel(readl(pwrdn) & ~OTP_OTP_PWR_DN_OTP_PWRDN_N, pwrdn); -+ if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), -+ OTP_OTP_STATUS_OTP_CPUMPEN)) -+ return -ETIMEDOUT; -+ } else { -+ writel(readl(pwrdn) | OTP_OTP_PWR_DN_OTP_PWRDN_N, pwrdn); -+ } -+ -+ return 0; -+} -+ -+static int lan9662_otp_execute(struct lan9662_otp *otp) -+{ -+ if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), -+ OTP_OTP_CMD_GO_OTP_GO)) -+ return -ETIMEDOUT; -+ -+ if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), -+ OTP_OTP_STATUS_OTP_BUSY)) -+ return -ETIMEDOUT; -+ -+ return 0; -+} -+ -+static void lan9662_otp_set_address(struct lan9662_otp *otp, u32 offset) -+{ -+ writel(0xff & (offset >> 8), OTP_OTP_ADDR_HI(otp->base)); -+ writel(0xff & offset, OTP_OTP_ADDR_LO(otp->base)); -+} -+ -+static int lan9662_otp_read_byte(struct lan9662_otp *otp, u32 offset, u8 *dst) -+{ -+ u32 pass; -+ int rc; -+ -+ lan9662_otp_set_address(otp, offset); -+ writel(OTP_OTP_FUNC_CMD_OTP_READ, OTP_OTP_FUNC_CMD(otp->base)); -+ writel(OTP_OTP_CMD_GO_OTP_GO, OTP_OTP_CMD_GO(otp->base)); -+ rc = lan9662_otp_execute(otp); -+ if (!rc) { -+ pass = readl(OTP_OTP_PASS_FAIL(otp->base)); -+ if (pass & OTP_OTP_PASS_FAIL_OTP_READ_PROHIBITED) -+ return -EACCES; -+ *dst = (u8) readl(OTP_OTP_RD_DATA(otp->base)); -+ } -+ return rc; -+} -+ -+static int lan9662_otp_write_byte(struct lan9662_otp *otp, u32 offset, u8 data) -+{ -+ u32 pass; -+ int rc; -+ -+ lan9662_otp_set_address(otp, offset); -+ writel(OTP_OTP_PRGM_MODE_OTP_PGM_MODE_BYTE, OTP_OTP_PRGM_MODE(otp->base)); -+ writel(data, OTP_OTP_PRGM_DATA(otp->base)); -+ writel(OTP_OTP_FUNC_CMD_OTP_PROGRAM, OTP_OTP_FUNC_CMD(otp->base)); -+ writel(OTP_OTP_CMD_GO_OTP_GO, OTP_OTP_CMD_GO(otp->base)); -+ -+ rc = lan9662_otp_execute(otp); -+ if (!rc) { -+ pass = readl(OTP_OTP_PASS_FAIL(otp->base)); -+ if (pass & OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED) -+ return -EACCES; -+ if (pass & OTP_OTP_PASS_FAIL_OTP_FAIL) -+ return -EIO; -+ } -+ return rc; -+} -+ -+static int lan9662_otp_read(void *context, unsigned int offset, -+ void *_val, size_t bytes) -+{ -+ struct lan9662_otp *otp = context; -+ u8 *val = _val; -+ uint8_t data; -+ int i, rc = 0; -+ -+ lan9662_otp_power(otp, true); -+ for (i = 0; i < bytes; i++) { -+ rc = lan9662_otp_read_byte(otp, offset + i, &data); -+ if (rc < 0) -+ break; -+ *val++ = data; -+ } -+ lan9662_otp_power(otp, false); -+ -+ return rc; -+} -+ -+static int lan9662_otp_write(void *context, unsigned int offset, -+ void *_val, size_t bytes) -+{ -+ struct lan9662_otp *otp = context; -+ u8 *val = _val; -+ u8 data, newdata; -+ int i, rc = 0; -+ -+ lan9662_otp_power(otp, true); -+ for (i = 0; i < bytes; i++) { -+ /* Skip zero bytes */ -+ if (val[i]) { -+ rc = lan9662_otp_read_byte(otp, offset + i, &data); -+ if (rc < 0) -+ break; -+ -+ newdata = data | val[i]; -+ if (newdata == data) -+ continue; -+ -+ rc = lan9662_otp_write_byte(otp, offset + i, -+ newdata); -+ if (rc < 0) -+ break; -+ } -+ } -+ lan9662_otp_power(otp, false); -+ -+ return rc; -+} -+ -+static struct nvmem_config otp_config = { -+ .name = "lan9662-otp", -+ .stride = 1, -+ .word_size = 1, -+ .reg_read = lan9662_otp_read, -+ .reg_write = lan9662_otp_write, -+ .size = OTP_MEM_SIZE, -+}; -+ -+static int lan9662_otp_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct nvmem_device *nvmem; -+ struct lan9662_otp *otp; -+ -+ otp = devm_kzalloc(&pdev->dev, sizeof(*otp), GFP_KERNEL); -+ if (!otp) -+ return -ENOMEM; -+ -+ otp->dev = dev; -+ otp->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(otp->base)) -+ return PTR_ERR(otp->base); -+ -+ otp_config.priv = otp; -+ otp_config.dev = dev; -+ -+ nvmem = devm_nvmem_register(dev, &otp_config); -+ -+ return PTR_ERR_OR_ZERO(nvmem); -+} -+ -+static const struct of_device_id lan9662_otp_match[] = { -+ { .compatible = "microchip,lan9662-otp", }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, lan9662_otp_match); -+ -+static struct platform_driver lan9662_otp_driver = { -+ .probe = lan9662_otp_probe, -+ .driver = { -+ .name = "lan9662-otp", -+ .of_match_table = lan9662_otp_match, -+ }, -+}; -+module_platform_driver(lan9662_otp_driver); -+ -+MODULE_AUTHOR("Horatiu Vultur "); -+MODULE_DESCRIPTION("lan9662 OTP driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/backport-5.10/811-v6.1-0009-nvmem-u-boot-env-fix-crc32-casting-type.patch b/target/linux/generic/backport-5.10/811-v6.1-0009-nvmem-u-boot-env-fix-crc32-casting-type.patch deleted file mode 100644 index 633a668a96..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0009-nvmem-u-boot-env-fix-crc32-casting-type.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 3717ca3e0cc8683f93b41d3f06ca79631eb58715 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 16 Sep 2022 13:21:00 +0100 -Subject: [PATCH] nvmem: u-boot-env: fix crc32 casting type -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This fixes: -drivers/nvmem/u-boot-env.c:141:17: sparse: sparse: cast to restricted __le32 - -Fixes: d5542923f200 ("nvmem: add driver handling U-Boot environment variables") -Reported-by: kernel test robot -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20220916122100.170016-14-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/u-boot-env.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/u-boot-env.c -+++ b/drivers/nvmem/u-boot-env.c -@@ -139,7 +139,7 @@ static int u_boot_env_parse(struct u_boo - data_offset = offsetof(struct u_boot_env_image_redundant, data); - break; - } -- crc32 = le32_to_cpu(*(uint32_t *)(buf + crc32_offset)); -+ crc32 = le32_to_cpu(*(__le32 *)(buf + crc32_offset)); - crc32_data_len = priv->mtd->size - crc32_data_offset; - data_len = priv->mtd->size - data_offset; - diff --git a/target/linux/generic/backport-5.10/811-v6.1-0010-nvmem-lan9662-otp-Fix-compatible-string.patch b/target/linux/generic/backport-5.10/811-v6.1-0010-nvmem-lan9662-otp-Fix-compatible-string.patch deleted file mode 100644 index b663a1328d..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0010-nvmem-lan9662-otp-Fix-compatible-string.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 1aeb122d214b92474c86fde00a03d6e2d69381b5 Mon Sep 17 00:00:00 2001 -From: Horatiu Vultur -Date: Wed, 28 Sep 2022 21:51:12 +0200 -Subject: [PATCH] nvmem: lan9662-otp: Fix compatible string - -The device tree bindings for lan9662-otp expects the compatible string -to be one of following compatible strings: -microchip,lan9662-otpc -microchip,lan9668-otpc - -The problem is that the lan9662-otp driver contains the -microchip,lan9662-otp compatible string instead of -microchip,lan9662-otpc. -Fix this by updating the compatible string in the driver. - -Fixes: 9e8f208ad5229d ("nvmem: lan9662-otp: add support") -Signed-off-by: Horatiu Vultur -Link: https://lore.kernel.org/r/20220928195112.630351-1-horatiu.vultur@microchip.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/lan9662-otpc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/lan9662-otpc.c -+++ b/drivers/nvmem/lan9662-otpc.c -@@ -203,7 +203,7 @@ static int lan9662_otp_probe(struct plat - } - - static const struct of_device_id lan9662_otp_match[] = { -- { .compatible = "microchip,lan9662-otp", }, -+ { .compatible = "microchip,lan9662-otpc", }, - { }, - }; - MODULE_DEVICE_TABLE(of, lan9662_otp_match); diff --git a/target/linux/generic/backport-5.10/811-v6.1-0011-nvmem-u-boot-env-fix-crc32_data_offset-on-redundant-.patch b/target/linux/generic/backport-5.10/811-v6.1-0011-nvmem-u-boot-env-fix-crc32_data_offset-on-redundant-.patch deleted file mode 100644 index 967e891dbd..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0011-nvmem-u-boot-env-fix-crc32_data_offset-on-redundant-.patch +++ /dev/null @@ -1,59 +0,0 @@ -From ee424f7d3960152f5f862bbb6943e59828dc7917 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Fri, 4 Nov 2022 17:52:03 +0100 -Subject: [PATCH] nvmem: u-boot-env: fix crc32_data_offset on redundant - u-boot-env - -The Western Digital MyBook Live (PowerPC 464/APM82181) -has a set of redundant u-boot-env. Loading up the driver -the following error: - -| u_boot_env: Invalid calculated CRC32: 0x4f8f2c86 (expected: 0x98b14514) -| u_boot_env: probe of partition@1e000 failed with error -22 - -Looking up the userspace libubootenv utilities source [0], -it looks like the "mark" or "flag" is not part of the -crc32 sum... which is unfortunate :( - -|static int libuboot_load(struct uboot_ctx *ctx) -|{ -|[...] -| if (ctx->redundant) { -| [...] -| offsetdata = offsetof(struct uboot_env_redund, data); -| [...] //-----^^ -| } -| usable_envsize = ctx->size - offsetdata; -| buf[0] = malloc(bufsize); -|[...] -| for (i = 0; i < copies; i++) { -| data = (uint8_t *)(buf[i] + offsetdata); -| uint32_t crc; -| -| ret = devread(ctx, i, buf[i]); -| [...] -| crc = *(uint32_t *)(buf[i] + offsetcrc); -| dev->crc = crc32(0, (uint8_t *)data, usable_envsize); -| - -[0] https://github.com/sbabic/libubootenv/blob/master/src/uboot_env.c#L951 - -Fixes: d5542923f200 ("nvmem: add driver handling U-Boot environment variables") -Signed-off-by: Christian Lamparter -Link: https://lore.kernel.org/r/70a16eae113e08db2390b76e174f4837caa135c3.1667580636.git.chunkeey@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/u-boot-env.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/u-boot-env.c -+++ b/drivers/nvmem/u-boot-env.c -@@ -135,7 +135,7 @@ static int u_boot_env_parse(struct u_boo - break; - case U_BOOT_FORMAT_REDUNDANT: - crc32_offset = offsetof(struct u_boot_env_image_redundant, crc32); -- crc32_data_offset = offsetof(struct u_boot_env_image_redundant, mark); -+ crc32_data_offset = offsetof(struct u_boot_env_image_redundant, data); - data_offset = offsetof(struct u_boot_env_image_redundant, data); - break; - } diff --git a/target/linux/generic/backport-5.10/811-v6.1-0012-nvmem-rmem-Fix-return-value-check-in-rmem_read.patch b/target/linux/generic/backport-5.10/811-v6.1-0012-nvmem-rmem-Fix-return-value-check-in-rmem_read.patch deleted file mode 100644 index b0e1b0c219..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0012-nvmem-rmem-Fix-return-value-check-in-rmem_read.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 58e92c4a496b27156020a59a98c7f4a92c2b1533 Mon Sep 17 00:00:00 2001 -From: Wei Yongjun -Date: Fri, 18 Nov 2022 06:38:38 +0000 -Subject: [PATCH] nvmem: rmem: Fix return value check in rmem_read() - -In case of error, the function memremap() returns NULL pointer -not ERR_PTR(). The IS_ERR() test in the return value check -should be replaced with NULL test. - -Fixes: 5a3fa75a4d9c ("nvmem: Add driver to expose reserved memory as nvmem") -Cc: Srinivas Kandagatla -Cc: Nicolas Saenz Julienne -Signed-off-by: Wei Yongjun -Acked-by: Nicolas Saenz Julienne -Signed-off-by: Yang Yingliang -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20221118063840.6357-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/rmem.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/nvmem/rmem.c -+++ b/drivers/nvmem/rmem.c -@@ -37,9 +37,9 @@ static int rmem_read(void *context, unsi - * but as of Dec 2020 this isn't possible on arm64. - */ - addr = memremap(priv->mem->base, available, MEMREMAP_WB); -- if (IS_ERR(addr)) { -+ if (!addr) { - dev_err(priv->dev, "Failed to remap memory region\n"); -- return PTR_ERR(addr); -+ return -ENOMEM; - } - - count = memory_read_from_buffer(val, bytes, &off, addr, available); diff --git a/target/linux/generic/backport-5.10/811-v6.1-0013-nvmem-lan9662-otp-Change-return-type-of-lan9662_otp_.patch b/target/linux/generic/backport-5.10/811-v6.1-0013-nvmem-lan9662-otp-Change-return-type-of-lan9662_otp_.patch deleted file mode 100644 index 0c842f0793..0000000000 --- a/target/linux/generic/backport-5.10/811-v6.1-0013-nvmem-lan9662-otp-Change-return-type-of-lan9662_otp_.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 022b68f271de0e53024e6d5e96fee8e76d25eb95 Mon Sep 17 00:00:00 2001 -From: Horatiu Vultur -Date: Fri, 18 Nov 2022 06:38:40 +0000 -Subject: [PATCH] nvmem: lan9662-otp: Change return type of - lan9662_otp_wait_flag_clear() - -The blamed commit introduced the following smatch warning in the -function lan9662_otp_wait_flag_clear: -drivers/nvmem/lan9662-otpc.c:43 lan9662_otp_wait_flag_clear() warn: signedness bug returning '(-110)' - -Fix this by changing the return type of the function -lan9662_otp_wait_flag_clear() to be int instead of bool. - -Fixes: 9e8f208ad5229d ("nvmem: lan9662-otp: add support") -Reported-by: kernel test robot -Reported-by: Dan Carpenter -Signed-off-by: Horatiu Vultur -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20221118063840.6357-5-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/lan9662-otpc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/lan9662-otpc.c -+++ b/drivers/nvmem/lan9662-otpc.c -@@ -36,7 +36,7 @@ struct lan9662_otp { - void __iomem *base; - }; - --static bool lan9662_otp_wait_flag_clear(void __iomem *reg, u32 flag) -+static int lan9662_otp_wait_flag_clear(void __iomem *reg, u32 flag) - { - u32 val; - diff --git a/target/linux/generic/backport-5.10/812-v6.2-0001-nvmem-stm32-move-STM32MP15_BSEC_NUM_LOWER-in-config.patch b/target/linux/generic/backport-5.10/812-v6.2-0001-nvmem-stm32-move-STM32MP15_BSEC_NUM_LOWER-in-config.patch deleted file mode 100644 index 33759632eb..0000000000 --- a/target/linux/generic/backport-5.10/812-v6.2-0001-nvmem-stm32-move-STM32MP15_BSEC_NUM_LOWER-in-config.patch +++ /dev/null @@ -1,82 +0,0 @@ -From fbfc4ca465a1f8d81bf2d67d95bf7fc67c3cf0c2 Mon Sep 17 00:00:00 2001 -From: Patrick Delaunay -Date: Fri, 18 Nov 2022 06:39:20 +0000 -Subject: [PATCH] nvmem: stm32: move STM32MP15_BSEC_NUM_LOWER in config - -Support STM32MP15_BSEC_NUM_LOWER in stm32 romem config to prepare -the next SoC in STM32MP family. - -Signed-off-by: Patrick Delaunay -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20221118063932.6418-2-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/stm32-romem.c | 21 ++++++++++++++++----- - 1 file changed, 16 insertions(+), 5 deletions(-) - ---- a/drivers/nvmem/stm32-romem.c -+++ b/drivers/nvmem/stm32-romem.c -@@ -22,16 +22,15 @@ - /* shadow registers offest */ - #define STM32MP15_BSEC_DATA0 0x200 - --/* 32 (x 32-bits) lower shadow registers */ --#define STM32MP15_BSEC_NUM_LOWER 32 -- - struct stm32_romem_cfg { - int size; -+ u8 lower; - }; - - struct stm32_romem_priv { - void __iomem *base; - struct nvmem_config cfg; -+ u8 lower; - }; - - static int stm32_romem_read(void *context, unsigned int offset, void *buf, -@@ -85,7 +84,7 @@ static int stm32_bsec_read(void *context - for (i = roffset; (i < roffset + rbytes); i += 4) { - u32 otp = i >> 2; - -- if (otp < STM32MP15_BSEC_NUM_LOWER) { -+ if (otp < priv->lower) { - /* read lower data from shadow registers */ - val = readl_relaxed( - priv->base + STM32MP15_BSEC_DATA0 + i); -@@ -159,6 +158,8 @@ static int stm32_romem_probe(struct plat - priv->cfg.priv = priv; - priv->cfg.owner = THIS_MODULE; - -+ priv->lower = 0; -+ - cfg = (const struct stm32_romem_cfg *) - of_match_device(dev->driver->of_match_table, dev)->data; - if (!cfg) { -@@ -167,6 +168,7 @@ static int stm32_romem_probe(struct plat - priv->cfg.reg_read = stm32_romem_read; - } else { - priv->cfg.size = cfg->size; -+ priv->lower = cfg->lower; - priv->cfg.reg_read = stm32_bsec_read; - priv->cfg.reg_write = stm32_bsec_write; - } -@@ -174,8 +176,17 @@ static int stm32_romem_probe(struct plat - return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg)); - } - -+/* -+ * STM32MP15 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits) -+ * => 96 x 32-bits data words -+ * - Lower: 1K bits, 2:1 redundancy, incremental bit programming -+ * => 32 (x 32-bits) lower shadow registers = words 0 to 31 -+ * - Upper: 2K bits, ECC protection, word programming only -+ * => 64 (x 32-bits) = words 32 to 95 -+ */ - static const struct stm32_romem_cfg stm32mp15_bsec_cfg = { -- .size = 384, /* 96 x 32-bits data words */ -+ .size = 384, -+ .lower = 32, - }; - - static const struct of_device_id stm32_romem_of_match[] = { diff --git a/target/linux/generic/backport-5.10/812-v6.2-0002-nvmem-stm32-add-warning-when-upper-OTPs-are-updated.patch b/target/linux/generic/backport-5.10/812-v6.2-0002-nvmem-stm32-add-warning-when-upper-OTPs-are-updated.patch deleted file mode 100644 index 5791df2606..0000000000 --- a/target/linux/generic/backport-5.10/812-v6.2-0002-nvmem-stm32-add-warning-when-upper-OTPs-are-updated.patch +++ /dev/null @@ -1,34 +0,0 @@ -From d61784e6410f3df2028e6eb91b06ffed37a660e0 Mon Sep 17 00:00:00 2001 -From: Patrick Delaunay -Date: Fri, 18 Nov 2022 06:39:21 +0000 -Subject: [PATCH] nvmem: stm32: add warning when upper OTPs are updated - -As the upper OTPs are ECC protected, they support only one 32 bits word -programming. -For a second modification of this word, these ECC become invalid and -this OTP will be no more accessible, the shadowed value is invalid. - -This patch adds a warning to indicate an upper OTP update, because this -operation is dangerous as OTP is not locked by the driver after the first -update to avoid a second update. - -Signed-off-by: Patrick Delaunay -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20221118063932.6418-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/stm32-romem.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/nvmem/stm32-romem.c -+++ b/drivers/nvmem/stm32-romem.c -@@ -132,6 +132,9 @@ static int stm32_bsec_write(void *contex - } - } - -+ if (offset + bytes >= priv->lower * 4) -+ dev_warn(dev, "Update of upper OTPs with ECC protection (word programming, only once)\n"); -+ - return 0; - } - diff --git a/target/linux/generic/backport-5.10/812-v6.2-0003-nvmem-stm32-add-nvmem-type-attribute.patch b/target/linux/generic/backport-5.10/812-v6.2-0003-nvmem-stm32-add-nvmem-type-attribute.patch deleted file mode 100644 index b83ad69c6b..0000000000 --- a/target/linux/generic/backport-5.10/812-v6.2-0003-nvmem-stm32-add-nvmem-type-attribute.patch +++ /dev/null @@ -1,26 +0,0 @@ -From a3816a7d7c097c1da46aad5f5d1e229b607dce04 Mon Sep 17 00:00:00 2001 -From: Patrick Delaunay -Date: Fri, 18 Nov 2022 06:39:22 +0000 -Subject: [PATCH] nvmem: stm32: add nvmem type attribute - -Inform NVMEM framework of type attribute for stm32-romem as NVMEM_TYPE_OTP -so userspace is able to know how the data is stored in BSEC. - -Signed-off-by: Patrick Delaunay -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20221118063932.6418-4-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/stm32-romem.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/nvmem/stm32-romem.c -+++ b/drivers/nvmem/stm32-romem.c -@@ -160,6 +160,7 @@ static int stm32_romem_probe(struct plat - priv->cfg.dev = dev; - priv->cfg.priv = priv; - priv->cfg.owner = THIS_MODULE; -+ priv->cfg.type = NVMEM_TYPE_OTP; - - priv->lower = 0; - diff --git a/target/linux/generic/backport-5.10/812-v6.2-0004-nvmem-stm32-fix-spelling-typo-in-comment.patch b/target/linux/generic/backport-5.10/812-v6.2-0004-nvmem-stm32-fix-spelling-typo-in-comment.patch deleted file mode 100644 index 52ba1e65b5..0000000000 --- a/target/linux/generic/backport-5.10/812-v6.2-0004-nvmem-stm32-fix-spelling-typo-in-comment.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 06aac0e11960a7ddccc1888326b5906d017e0f24 Mon Sep 17 00:00:00 2001 -From: Jiangshan Yi -Date: Fri, 18 Nov 2022 06:39:24 +0000 -Subject: [PATCH] nvmem: stm32: fix spelling typo in comment - -Fix spelling typo in comment. - -Reported-by: k2ci -Signed-off-by: Jiangshan Yi -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20221118063932.6418-6-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/stm32-romem.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/stm32-romem.c -+++ b/drivers/nvmem/stm32-romem.c -@@ -19,7 +19,7 @@ - #define STM32_SMC_WRITE_SHADOW 0x03 - #define STM32_SMC_READ_OTP 0x04 - --/* shadow registers offest */ -+/* shadow registers offset */ - #define STM32MP15_BSEC_DATA0 0x200 - - struct stm32_romem_cfg { diff --git a/target/linux/generic/backport-5.10/812-v6.2-0005-nvmem-Kconfig-Fix-spelling-mistake-controlls-control.patch b/target/linux/generic/backport-5.10/812-v6.2-0005-nvmem-Kconfig-Fix-spelling-mistake-controlls-control.patch deleted file mode 100644 index 8f024f4c1a..0000000000 --- a/target/linux/generic/backport-5.10/812-v6.2-0005-nvmem-Kconfig-Fix-spelling-mistake-controlls-control.patch +++ /dev/null @@ -1,27 +0,0 @@ -From fb817c4ef63e8cfb6e77ae4a2875ae854c80708f Mon Sep 17 00:00:00 2001 -From: Colin Ian King -Date: Fri, 18 Nov 2022 06:39:26 +0000 -Subject: [PATCH] nvmem: Kconfig: Fix spelling mistake "controlls" -> - "controls" - -There is a spelling mistake in a Kconfig description. Fix it. - -Signed-off-by: Colin Ian King -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20221118063932.6418-8-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -164,7 +164,7 @@ config NVMEM_MICROCHIP_OTPC - depends on ARCH_AT91 || COMPILE_TEST - help - This driver enable the OTP controller available on Microchip SAMA7G5 -- SoCs. It controlls the access to the OTP memory connected to it. -+ SoCs. It controls the access to the OTP memory connected to it. - - config NVMEM_MTK_EFUSE - tristate "Mediatek SoCs EFUSE support" diff --git a/target/linux/generic/backport-5.10/812-v6.2-0006-nvmem-u-boot-env-add-Broadcom-format-support.patch b/target/linux/generic/backport-5.10/812-v6.2-0006-nvmem-u-boot-env-add-Broadcom-format-support.patch deleted file mode 100644 index 861386ad31..0000000000 --- a/target/linux/generic/backport-5.10/812-v6.2-0006-nvmem-u-boot-env-add-Broadcom-format-support.patch +++ /dev/null @@ -1,67 +0,0 @@ -From ada84d07af6097b2addd18262668ce6cb9e15206 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Fri, 18 Nov 2022 06:39:27 +0000 -Subject: [PATCH] nvmem: u-boot-env: add Broadcom format support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Broadcom uses U-Boot for a lot of their bcmbca familiy chipsets. They -decided to store U-Boot environment data inside U-Boot partition and to -use a custom header (with "uEnv" magic and env data length). - -Add support for Broadcom's specific binding and their custom format. - -Ref: 6b0584c19d87 ("dt-bindings: nvmem: u-boot,env: add Broadcom's variant binding") -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20221118063932.6418-9-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/u-boot-env.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/nvmem/u-boot-env.c -+++ b/drivers/nvmem/u-boot-env.c -@@ -16,6 +16,7 @@ - enum u_boot_env_format { - U_BOOT_FORMAT_SINGLE, - U_BOOT_FORMAT_REDUNDANT, -+ U_BOOT_FORMAT_BROADCOM, - }; - - struct u_boot_env { -@@ -40,6 +41,13 @@ struct u_boot_env_image_redundant { - uint8_t data[]; - } __packed; - -+struct u_boot_env_image_broadcom { -+ __le32 magic; -+ __le32 len; -+ __le32 crc32; -+ uint8_t data[0]; -+} __packed; -+ - static int u_boot_env_read(void *context, unsigned int offset, void *val, - size_t bytes) - { -@@ -138,6 +146,11 @@ static int u_boot_env_parse(struct u_boo - crc32_data_offset = offsetof(struct u_boot_env_image_redundant, data); - data_offset = offsetof(struct u_boot_env_image_redundant, data); - break; -+ case U_BOOT_FORMAT_BROADCOM: -+ crc32_offset = offsetof(struct u_boot_env_image_broadcom, crc32); -+ crc32_data_offset = offsetof(struct u_boot_env_image_broadcom, data); -+ data_offset = offsetof(struct u_boot_env_image_broadcom, data); -+ break; - } - crc32 = le32_to_cpu(*(__le32 *)(buf + crc32_offset)); - crc32_data_len = priv->mtd->size - crc32_data_offset; -@@ -202,6 +215,7 @@ static const struct of_device_id u_boot_ - { .compatible = "u-boot,env", .data = (void *)U_BOOT_FORMAT_SINGLE, }, - { .compatible = "u-boot,env-redundant-bool", .data = (void *)U_BOOT_FORMAT_REDUNDANT, }, - { .compatible = "u-boot,env-redundant-count", .data = (void *)U_BOOT_FORMAT_REDUNDANT, }, -+ { .compatible = "brcm,env", .data = (void *)U_BOOT_FORMAT_BROADCOM, }, - {}, - }; - diff --git a/target/linux/generic/backport-5.10/812-v6.2-0007-nvmem-brcm_nvram-Add-check-for-kzalloc.patch b/target/linux/generic/backport-5.10/812-v6.2-0007-nvmem-brcm_nvram-Add-check-for-kzalloc.patch deleted file mode 100644 index 14108b5927..0000000000 --- a/target/linux/generic/backport-5.10/812-v6.2-0007-nvmem-brcm_nvram-Add-check-for-kzalloc.patch +++ /dev/null @@ -1,30 +0,0 @@ -From b0576ade3aaf24b376ea1a4406ae138e2a22b0c0 Mon Sep 17 00:00:00 2001 -From: Jiasheng Jiang -Date: Fri, 27 Jan 2023 10:40:06 +0000 -Subject: [PATCH] nvmem: brcm_nvram: Add check for kzalloc - -Add the check for the return value of kzalloc in order to avoid -NULL pointer dereference. - -Fixes: 6e977eaa8280 ("nvmem: brcm_nvram: parse NVRAM content into NVMEM cells") -Cc: stable@vger.kernel.org -Signed-off-by: Jiasheng Jiang -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230127104015.23839-2-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/brcm_nvram.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/nvmem/brcm_nvram.c -+++ b/drivers/nvmem/brcm_nvram.c -@@ -97,6 +97,9 @@ static int brcm_nvram_parse(struct brcm_ - len = le32_to_cpu(header.len); - - data = kzalloc(len, GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ - memcpy_fromio(data, priv->base, len); - data[len - 1] = '\0'; - diff --git a/target/linux/generic/backport-5.10/812-v6.2-0008-nvmem-sunxi_sid-Always-use-32-bit-MMIO-reads.patch b/target/linux/generic/backport-5.10/812-v6.2-0008-nvmem-sunxi_sid-Always-use-32-bit-MMIO-reads.patch deleted file mode 100644 index 632b01cb2a..0000000000 --- a/target/linux/generic/backport-5.10/812-v6.2-0008-nvmem-sunxi_sid-Always-use-32-bit-MMIO-reads.patch +++ /dev/null @@ -1,55 +0,0 @@ -From c151d5ed8e8fe0474bd61dce7f2076ca5916c683 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Fri, 27 Jan 2023 10:40:07 +0000 -Subject: [PATCH] nvmem: sunxi_sid: Always use 32-bit MMIO reads - -The SID SRAM on at least some SoCs (A64 and D1) returns different values -when read with bus cycles narrower than 32 bits. This is not immediately -obvious, because memcpy_fromio() uses word-size accesses as long as -enough data is being copied. - -The vendor driver always uses 32-bit MMIO reads, so do the same here. -This is faster than the register-based method, which is currently used -as a workaround on A64. And it fixes the values returned on D1, where -the SRAM method was being used. - -The special case for the last word is needed to maintain .word_size == 1 -for sysfs ABI compatibility, as noted previously in commit de2a3eaea552 -("nvmem: sunxi_sid: Optimize register read-out method"). - -Fixes: 07ae4fde9efa ("nvmem: sunxi_sid: Add support for D1 variant") -Cc: stable@vger.kernel.org -Tested-by: Heiko Stuebner -Signed-off-by: Samuel Holland -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230127104015.23839-3-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/sunxi_sid.c | 15 ++++++++++++++- - 1 file changed, 14 insertions(+), 1 deletion(-) - ---- a/drivers/nvmem/sunxi_sid.c -+++ b/drivers/nvmem/sunxi_sid.c -@@ -41,8 +41,21 @@ static int sunxi_sid_read(void *context, - void *val, size_t bytes) - { - struct sunxi_sid *sid = context; -+ u32 word; - -- memcpy_fromio(val, sid->base + sid->value_offset + offset, bytes); -+ /* .stride = 4 so offset is guaranteed to be aligned */ -+ __ioread32_copy(val, sid->base + sid->value_offset + offset, bytes / 4); -+ -+ val += round_down(bytes, 4); -+ offset += round_down(bytes, 4); -+ bytes = bytes % 4; -+ -+ if (!bytes) -+ return 0; -+ -+ /* Handle any trailing bytes */ -+ word = readl_relaxed(sid->base + sid->value_offset + offset); -+ memcpy(val, &word, bytes); - - return 0; - } diff --git a/target/linux/generic/backport-5.10/812-v6.2-0013-nvmem-core-fix-device-node-refcounting.patch b/target/linux/generic/backport-5.10/812-v6.2-0013-nvmem-core-fix-device-node-refcounting.patch deleted file mode 100644 index a229c303ad..0000000000 --- a/target/linux/generic/backport-5.10/812-v6.2-0013-nvmem-core-fix-device-node-refcounting.patch +++ /dev/null @@ -1,48 +0,0 @@ -From edcf2fb660526b5ed29f93bd17328a2b4835c8b2 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Fri, 27 Jan 2023 10:40:12 +0000 -Subject: [PATCH] nvmem: core: fix device node refcounting - -In of_nvmem_cell_get(), of_get_next_parent() is used on cell_np. This -will decrement the refcount on cell_np, but cell_np is still used later -in the code. Use of_get_parent() instead and of_node_put() in the -appropriate places. - -Fixes: 69aba7948cbe ("nvmem: Add a simple NVMEM framework for consumers") -Fixes: 7ae6478b304b ("nvmem: core: rework nvmem cell instance creation") -Cc: stable@vger.kernel.org -Signed-off-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230127104015.23839-8-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 11 ++++++++--- - 1 file changed, 8 insertions(+), 3 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -1237,16 +1237,21 @@ struct nvmem_cell *of_nvmem_cell_get(str - if (!cell_np) - return ERR_PTR(-ENOENT); - -- nvmem_np = of_get_next_parent(cell_np); -- if (!nvmem_np) -+ nvmem_np = of_get_parent(cell_np); -+ if (!nvmem_np) { -+ of_node_put(cell_np); - return ERR_PTR(-EINVAL); -+ } - - nvmem = __nvmem_device_get(nvmem_np, device_match_of_node); - of_node_put(nvmem_np); -- if (IS_ERR(nvmem)) -+ if (IS_ERR(nvmem)) { -+ of_node_put(cell_np); - return ERR_CAST(nvmem); -+ } - - cell_entry = nvmem_find_cell_entry_by_node(nvmem, cell_np); -+ of_node_put(cell_np); - if (!cell_entry) { - __nvmem_device_put(nvmem); - return ERR_PTR(-ENOENT); diff --git a/target/linux/generic/backport-5.10/813-v6.3-0001-nvmem-core-remove-spurious-white-space.patch b/target/linux/generic/backport-5.10/813-v6.3-0001-nvmem-core-remove-spurious-white-space.patch deleted file mode 100644 index 01400fd490..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0001-nvmem-core-remove-spurious-white-space.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2e8dc541ae207349b51c65391be625ffe1f86e0c Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Mon, 6 Feb 2023 13:43:41 +0000 -Subject: [PATCH] nvmem: core: remove spurious white space - -Remove a spurious white space in for the ida_alloc() call. - -Signed-off-by: Russell King (Oracle) -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-8-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -764,7 +764,7 @@ struct nvmem_device *nvmem_register(cons - if (!nvmem) - return ERR_PTR(-ENOMEM); - -- rval = ida_alloc(&nvmem_ida, GFP_KERNEL); -+ rval = ida_alloc(&nvmem_ida, GFP_KERNEL); - if (rval < 0) { - kfree(nvmem); - return ERR_PTR(rval); diff --git a/target/linux/generic/backport-5.10/813-v6.3-0002-nvmem-core-add-an-index-parameter-to-the-cell.patch b/target/linux/generic/backport-5.10/813-v6.3-0002-nvmem-core-add-an-index-parameter-to-the-cell.patch deleted file mode 100644 index 454d3bf0ed..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0002-nvmem-core-add-an-index-parameter-to-the-cell.patch +++ /dev/null @@ -1,180 +0,0 @@ -From 5d8e6e6c10a3d37486d263b16ddc15991a7e4a88 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 6 Feb 2023 13:43:46 +0000 -Subject: [PATCH] nvmem: core: add an index parameter to the cell - -Sometimes a cell can represend multiple values. For example, a base -ethernet address stored in the NVMEM can be expanded into multiple -discreet ones by adding an offset. - -For this use case, introduce an index parameter which is then used to -distiguish between values. This parameter will then be passed to the -post process hook which can then use it to create different values -during reading. - -At the moment, there is only support for the device tree path. You can -add the index to the phandle, e.g. - - &net { - nvmem-cells = <&base_mac_address 2>; - nvmem-cell-names = "mac-address"; - }; - - &nvmem_provider { - base_mac_address: base-mac-address@0 { - #nvmem-cell-cells = <1>; - reg = <0 6>; - }; - }; - -Signed-off-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-13-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 37 ++++++++++++++++++++++++---------- - drivers/nvmem/imx-ocotp.c | 4 ++-- - include/linux/nvmem-provider.h | 4 ++-- - 3 files changed, 30 insertions(+), 15 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -60,6 +60,7 @@ struct nvmem_cell_entry { - struct nvmem_cell { - struct nvmem_cell_entry *entry; - const char *id; -+ int index; - }; - - static DEFINE_MUTEX(nvmem_mutex); -@@ -1122,7 +1123,8 @@ struct nvmem_device *devm_nvmem_device_g - } - EXPORT_SYMBOL_GPL(devm_nvmem_device_get); - --static struct nvmem_cell *nvmem_create_cell(struct nvmem_cell_entry *entry, const char *id) -+static struct nvmem_cell *nvmem_create_cell(struct nvmem_cell_entry *entry, -+ const char *id, int index) - { - struct nvmem_cell *cell; - const char *name = NULL; -@@ -1141,6 +1143,7 @@ static struct nvmem_cell *nvmem_create_c - - cell->id = name; - cell->entry = entry; -+ cell->index = index; - - return cell; - } -@@ -1179,7 +1182,7 @@ nvmem_cell_get_from_lookup(struct device - __nvmem_device_put(nvmem); - cell = ERR_PTR(-ENOENT); - } else { -- cell = nvmem_create_cell(cell_entry, con_id); -+ cell = nvmem_create_cell(cell_entry, con_id, 0); - if (IS_ERR(cell)) - __nvmem_device_put(nvmem); - } -@@ -1227,15 +1230,27 @@ struct nvmem_cell *of_nvmem_cell_get(str - struct nvmem_device *nvmem; - struct nvmem_cell_entry *cell_entry; - struct nvmem_cell *cell; -+ struct of_phandle_args cell_spec; - int index = 0; -+ int cell_index = 0; -+ int ret; - - /* if cell name exists, find index to the name */ - if (id) - index = of_property_match_string(np, "nvmem-cell-names", id); - -- cell_np = of_parse_phandle(np, "nvmem-cells", index); -- if (!cell_np) -- return ERR_PTR(-ENOENT); -+ ret = of_parse_phandle_with_optional_args(np, "nvmem-cells", -+ "#nvmem-cell-cells", -+ index, &cell_spec); -+ if (ret) -+ return ERR_PTR(ret); -+ -+ if (cell_spec.args_count > 1) -+ return ERR_PTR(-EINVAL); -+ -+ cell_np = cell_spec.np; -+ if (cell_spec.args_count) -+ cell_index = cell_spec.args[0]; - - nvmem_np = of_get_parent(cell_np); - if (!nvmem_np) { -@@ -1257,7 +1272,7 @@ struct nvmem_cell *of_nvmem_cell_get(str - return ERR_PTR(-ENOENT); - } - -- cell = nvmem_create_cell(cell_entry, id); -+ cell = nvmem_create_cell(cell_entry, id, cell_index); - if (IS_ERR(cell)) - __nvmem_device_put(nvmem); - -@@ -1410,8 +1425,8 @@ static void nvmem_shift_read_buffer_in_p - } - - static int __nvmem_cell_read(struct nvmem_device *nvmem, -- struct nvmem_cell_entry *cell, -- void *buf, size_t *len, const char *id) -+ struct nvmem_cell_entry *cell, -+ void *buf, size_t *len, const char *id, int index) - { - int rc; - -@@ -1425,7 +1440,7 @@ static int __nvmem_cell_read(struct nvme - nvmem_shift_read_buffer_in_place(cell, buf); - - if (nvmem->cell_post_process) { -- rc = nvmem->cell_post_process(nvmem->priv, id, -+ rc = nvmem->cell_post_process(nvmem->priv, id, index, - cell->offset, buf, cell->bytes); - if (rc) - return rc; -@@ -1460,7 +1475,7 @@ void *nvmem_cell_read(struct nvmem_cell - if (!buf) - return ERR_PTR(-ENOMEM); - -- rc = __nvmem_cell_read(nvmem, cell->entry, buf, len, cell->id); -+ rc = __nvmem_cell_read(nvmem, cell->entry, buf, len, cell->id, cell->index); - if (rc) { - kfree(buf); - return ERR_PTR(rc); -@@ -1773,7 +1788,7 @@ ssize_t nvmem_device_cell_read(struct nv - if (rc) - return rc; - -- rc = __nvmem_cell_read(nvmem, &cell, buf, &len, NULL); -+ rc = __nvmem_cell_read(nvmem, &cell, buf, &len, NULL, 0); - if (rc) - return rc; - ---- a/drivers/nvmem/imx-ocotp.c -+++ b/drivers/nvmem/imx-ocotp.c -@@ -222,8 +222,8 @@ read_end: - return ret; - } - --static int imx_ocotp_cell_pp(void *context, const char *id, unsigned int offset, -- void *data, size_t bytes) -+static int imx_ocotp_cell_pp(void *context, const char *id, int index, -+ unsigned int offset, void *data, size_t bytes) - { - struct ocotp_priv *priv = context; - ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -20,8 +20,8 @@ typedef int (*nvmem_reg_read_t)(void *pr - typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset, - void *val, size_t bytes); - /* used for vendor specific post processing of cell data */ --typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, unsigned int offset, -- void *buf, size_t bytes); -+typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, int index, -+ unsigned int offset, void *buf, size_t bytes); - - enum nvmem_type { - NVMEM_TYPE_UNKNOWN = 0, diff --git a/target/linux/generic/backport-5.10/813-v6.3-0003-nvmem-core-move-struct-nvmem_cell_info-to-nvmem-prov.patch b/target/linux/generic/backport-5.10/813-v6.3-0003-nvmem-core-move-struct-nvmem_cell_info-to-nvmem-prov.patch deleted file mode 100644 index f3829b3e17..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0003-nvmem-core-move-struct-nvmem_cell_info-to-nvmem-prov.patch +++ /dev/null @@ -1,78 +0,0 @@ -From fbd03d27776c6121a483921601418e3c8f0ff37e Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 6 Feb 2023 13:43:47 +0000 -Subject: [PATCH] nvmem: core: move struct nvmem_cell_info to nvmem-provider.h - -struct nvmem_cell_info is used to describe a cell. Thus this should -really be in the nvmem-provider's header. There are two (unused) nvmem -access methods which use the nvmem_cell_info to describe the cell to be -accesses. One can argue, that they will create a cell before accessing, -thus they are both a provider and a consumer. - -struct nvmem_cell_info will get used more and more by nvmem-providers, -don't force them to also include the consumer header, although they are -not. - -Signed-off-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-14-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - include/linux/nvmem-consumer.h | 10 +--------- - include/linux/nvmem-provider.h | 19 ++++++++++++++++++- - 2 files changed, 19 insertions(+), 10 deletions(-) - ---- a/include/linux/nvmem-consumer.h -+++ b/include/linux/nvmem-consumer.h -@@ -18,15 +18,7 @@ struct device_node; - /* consumer cookie */ - struct nvmem_cell; - struct nvmem_device; -- --struct nvmem_cell_info { -- const char *name; -- unsigned int offset; -- unsigned int bytes; -- unsigned int bit_offset; -- unsigned int nbits; -- struct device_node *np; --}; -+struct nvmem_cell_info; - - /** - * struct nvmem_cell_lookup - cell lookup entry ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -14,7 +14,6 @@ - #include - - struct nvmem_device; --struct nvmem_cell_info; - typedef int (*nvmem_reg_read_t)(void *priv, unsigned int offset, - void *val, size_t bytes); - typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset, -@@ -48,6 +47,24 @@ struct nvmem_keepout { - }; - - /** -+ * struct nvmem_cell_info - NVMEM cell description -+ * @name: Name. -+ * @offset: Offset within the NVMEM device. -+ * @bytes: Length of the cell. -+ * @bit_offset: Bit offset if cell is smaller than a byte. -+ * @nbits: Number of bits. -+ * @np: Optional device_node pointer. -+ */ -+struct nvmem_cell_info { -+ const char *name; -+ unsigned int offset; -+ unsigned int bytes; -+ unsigned int bit_offset; -+ unsigned int nbits; -+ struct device_node *np; -+}; -+ -+/** - * struct nvmem_config - NVMEM device configuration - * - * @dev: Parent device. diff --git a/target/linux/generic/backport-5.10/813-v6.3-0004-nvmem-core-drop-the-removal-of-the-cells-in-nvmem_ad.patch b/target/linux/generic/backport-5.10/813-v6.3-0004-nvmem-core-drop-the-removal-of-the-cells-in-nvmem_ad.patch deleted file mode 100644 index 8f996eab34..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0004-nvmem-core-drop-the-removal-of-the-cells-in-nvmem_ad.patch +++ /dev/null @@ -1,65 +0,0 @@ -From cc5bdd323dde6494623f3ffe3a5b887fa21cd375 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 6 Feb 2023 13:43:48 +0000 -Subject: [PATCH] nvmem: core: drop the removal of the cells in - nvmem_add_cells() - -If nvmem_add_cells() fails, the whole nvmem_register() will fail -and the cells will then be removed anyway. This is a preparation -to introduce a nvmem_add_one_cell() which can then be used by -nvmem_add_cells(). - -This is then the same to what nvmem_add_cells_from_table() and -nvmem_add_cells_from_of() do. - -Signed-off-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-15-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 14 ++++---------- - 1 file changed, 4 insertions(+), 10 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -515,7 +515,7 @@ static int nvmem_add_cells(struct nvmem_ - int ncells) - { - struct nvmem_cell_entry **cells; -- int i, rval; -+ int i, rval = 0; - - cells = kcalloc(ncells, sizeof(*cells), GFP_KERNEL); - if (!cells) -@@ -525,28 +525,22 @@ static int nvmem_add_cells(struct nvmem_ - cells[i] = kzalloc(sizeof(**cells), GFP_KERNEL); - if (!cells[i]) { - rval = -ENOMEM; -- goto err; -+ goto out; - } - - rval = nvmem_cell_info_to_nvmem_cell_entry(nvmem, &info[i], cells[i]); - if (rval) { - kfree(cells[i]); -- goto err; -+ goto out; - } - - nvmem_cell_entry_add(cells[i]); - } - -+out: - /* remove tmp array */ - kfree(cells); - -- return 0; --err: -- while (i--) -- nvmem_cell_entry_drop(cells[i]); -- -- kfree(cells); -- - return rval; - } - diff --git a/target/linux/generic/backport-5.10/813-v6.3-0005-nvmem-core-add-nvmem_add_one_cell.patch b/target/linux/generic/backport-5.10/813-v6.3-0005-nvmem-core-add-nvmem_add_one_cell.patch deleted file mode 100644 index 711ce229b2..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0005-nvmem-core-add-nvmem_add_one_cell.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 2ded6830d376d5e7bf43d59f7f7fdf1a59abc676 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 6 Feb 2023 13:43:49 +0000 -Subject: [PATCH] nvmem: core: add nvmem_add_one_cell() - -Add a new function to add exactly one cell. This will be used by the -nvmem layout drivers to add custom cells. In contrast to the -nvmem_add_cells(), this has the advantage that we don't have to assemble -a list of cells on runtime. - -Signed-off-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-16-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 59 ++++++++++++++++++++-------------- - include/linux/nvmem-provider.h | 8 +++++ - 2 files changed, 43 insertions(+), 24 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -502,6 +502,36 @@ static int nvmem_cell_info_to_nvmem_cell - } - - /** -+ * nvmem_add_one_cell() - Add one cell information to an nvmem device -+ * -+ * @nvmem: nvmem device to add cells to. -+ * @info: nvmem cell info to add to the device -+ * -+ * Return: 0 or negative error code on failure. -+ */ -+int nvmem_add_one_cell(struct nvmem_device *nvmem, -+ const struct nvmem_cell_info *info) -+{ -+ struct nvmem_cell_entry *cell; -+ int rval; -+ -+ cell = kzalloc(sizeof(*cell), GFP_KERNEL); -+ if (!cell) -+ return -ENOMEM; -+ -+ rval = nvmem_cell_info_to_nvmem_cell_entry(nvmem, info, cell); -+ if (rval) { -+ kfree(cell); -+ return rval; -+ } -+ -+ nvmem_cell_entry_add(cell); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(nvmem_add_one_cell); -+ -+/** - * nvmem_add_cells() - Add cell information to an nvmem device - * - * @nvmem: nvmem device to add cells to. -@@ -514,34 +544,15 @@ static int nvmem_add_cells(struct nvmem_ - const struct nvmem_cell_info *info, - int ncells) - { -- struct nvmem_cell_entry **cells; -- int i, rval = 0; -- -- cells = kcalloc(ncells, sizeof(*cells), GFP_KERNEL); -- if (!cells) -- return -ENOMEM; -+ int i, rval; - - for (i = 0; i < ncells; i++) { -- cells[i] = kzalloc(sizeof(**cells), GFP_KERNEL); -- if (!cells[i]) { -- rval = -ENOMEM; -- goto out; -- } -- -- rval = nvmem_cell_info_to_nvmem_cell_entry(nvmem, &info[i], cells[i]); -- if (rval) { -- kfree(cells[i]); -- goto out; -- } -- -- nvmem_cell_entry_add(cells[i]); -+ rval = nvmem_add_one_cell(nvmem, &info[i]); -+ if (rval) -+ return rval; - } - --out: -- /* remove tmp array */ -- kfree(cells); -- -- return rval; -+ return 0; - } - - /** ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -153,6 +153,9 @@ struct nvmem_device *devm_nvmem_register - void nvmem_add_cell_table(struct nvmem_cell_table *table); - void nvmem_del_cell_table(struct nvmem_cell_table *table); - -+int nvmem_add_one_cell(struct nvmem_device *nvmem, -+ const struct nvmem_cell_info *info); -+ - #else - - static inline struct nvmem_device *nvmem_register(const struct nvmem_config *c) -@@ -170,6 +173,11 @@ devm_nvmem_register(struct device *dev, - - static inline void nvmem_add_cell_table(struct nvmem_cell_table *table) {} - static inline void nvmem_del_cell_table(struct nvmem_cell_table *table) {} -+static inline int nvmem_add_one_cell(struct nvmem_device *nvmem, -+ const struct nvmem_cell_info *info) -+{ -+ return -EOPNOTSUPP; -+} - - #endif /* CONFIG_NVMEM */ - #endif /* ifndef _LINUX_NVMEM_PROVIDER_H */ diff --git a/target/linux/generic/backport-5.10/813-v6.3-0006-nvmem-core-use-nvmem_add_one_cell-in-nvmem_add_cells.patch b/target/linux/generic/backport-5.10/813-v6.3-0006-nvmem-core-use-nvmem_add_one_cell-in-nvmem_add_cells.patch deleted file mode 100644 index e1791e5c83..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0006-nvmem-core-use-nvmem_add_one_cell-in-nvmem_add_cells.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 50014d659617dc58780a5d31ceb76c82779a9d8b Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 6 Feb 2023 13:43:50 +0000 -Subject: [PATCH] nvmem: core: use nvmem_add_one_cell() in - nvmem_add_cells_from_of() - -Convert nvmem_add_cells_from_of() to use the new nvmem_add_one_cell(). -This will remove duplicate code and it will make it possible to add a -hook to a nvmem layout in between, which can change fields before the -cell is finally added. - -Signed-off-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-17-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 45 ++++++++++++++------------------------------ - 1 file changed, 14 insertions(+), 31 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -688,15 +688,14 @@ static int nvmem_validate_keepouts(struc - - static int nvmem_add_cells_from_of(struct nvmem_device *nvmem) - { -- struct device_node *parent, *child; - struct device *dev = &nvmem->dev; -- struct nvmem_cell_entry *cell; -+ struct device_node *child; - const __be32 *addr; -- int len; -+ int len, ret; - -- parent = dev->of_node; -+ for_each_child_of_node(dev->of_node, child) { -+ struct nvmem_cell_info info = {0}; - -- for_each_child_of_node(parent, child) { - addr = of_get_property(child, "reg", &len); - if (!addr) - continue; -@@ -706,40 +705,24 @@ static int nvmem_add_cells_from_of(struc - return -EINVAL; - } - -- cell = kzalloc(sizeof(*cell), GFP_KERNEL); -- if (!cell) { -- of_node_put(child); -- return -ENOMEM; -- } -- -- cell->nvmem = nvmem; -- cell->offset = be32_to_cpup(addr++); -- cell->bytes = be32_to_cpup(addr); -- cell->name = kasprintf(GFP_KERNEL, "%pOFn", child); -+ info.offset = be32_to_cpup(addr++); -+ info.bytes = be32_to_cpup(addr); -+ info.name = kasprintf(GFP_KERNEL, "%pOFn", child); - - addr = of_get_property(child, "bits", &len); - if (addr && len == (2 * sizeof(u32))) { -- cell->bit_offset = be32_to_cpup(addr++); -- cell->nbits = be32_to_cpup(addr); -+ info.bit_offset = be32_to_cpup(addr++); -+ info.nbits = be32_to_cpup(addr); - } - -- if (cell->nbits) -- cell->bytes = DIV_ROUND_UP( -- cell->nbits + cell->bit_offset, -- BITS_PER_BYTE); -- -- if (!IS_ALIGNED(cell->offset, nvmem->stride)) { -- dev_err(dev, "cell %s unaligned to nvmem stride %d\n", -- cell->name, nvmem->stride); -- /* Cells already added will be freed later. */ -- kfree_const(cell->name); -- kfree(cell); -+ info.np = of_node_get(child); -+ -+ ret = nvmem_add_one_cell(nvmem, &info); -+ kfree(info.name); -+ if (ret) { - of_node_put(child); -- return -EINVAL; -+ return ret; - } -- -- cell->np = of_node_get(child); -- nvmem_cell_entry_add(cell); - } - - return 0; diff --git a/target/linux/generic/backport-5.10/813-v6.3-0007-nvmem-stm32-add-OP-TEE-support-for-STM32MP13x.patch b/target/linux/generic/backport-5.10/813-v6.3-0007-nvmem-stm32-add-OP-TEE-support-for-STM32MP13x.patch deleted file mode 100644 index 172a78b76a..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0007-nvmem-stm32-add-OP-TEE-support-for-STM32MP13x.patch +++ /dev/null @@ -1,562 +0,0 @@ -From 6a0bc3522e746025e2d9a63ab2cb5d7062c2d39c Mon Sep 17 00:00:00 2001 -From: Patrick Delaunay -Date: Mon, 6 Feb 2023 13:43:51 +0000 -Subject: [PATCH] nvmem: stm32: add OP-TEE support for STM32MP13x - -For boot with OP-TEE on STM32MP13, the communication with the secure -world no more use STMicroelectronics SMC but communication with the -STM32MP BSEC TA, for data access (read/write) or lock operation: -- all the request are sent to OP-TEE trusted application, -- for upper OTP with ECC protection and with word programming only - each OTP are permanently locked when programmed to avoid ECC error - on the second write operation - -Signed-off-by: Patrick Delaunay -Reviewed-by: Etienne Carriere -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-18-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 11 + - drivers/nvmem/Makefile | 1 + - drivers/nvmem/stm32-bsec-optee-ta.c | 298 ++++++++++++++++++++++++++++ - drivers/nvmem/stm32-bsec-optee-ta.h | 80 ++++++++ - drivers/nvmem/stm32-romem.c | 54 ++++- - 5 files changed, 441 insertions(+), 3 deletions(-) - create mode 100644 drivers/nvmem/stm32-bsec-optee-ta.c - create mode 100644 drivers/nvmem/stm32-bsec-optee-ta.h - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -290,9 +290,20 @@ config NVMEM_SPRD_EFUSE - This driver can also be built as a module. If so, the module - will be called nvmem-sprd-efuse. - -+config NVMEM_STM32_BSEC_OPTEE_TA -+ bool "STM32MP BSEC OP-TEE TA support for nvmem-stm32-romem driver" -+ depends on OPTEE -+ help -+ Say y here to enable the accesses to STM32MP SoC OTPs by the OP-TEE -+ trusted application STM32MP BSEC. -+ -+ This library is a used by stm32-romem driver or included in the module -+ called nvmem-stm32-romem. -+ - config NVMEM_STM32_ROMEM - tristate "STMicroelectronics STM32 factory-programmed memory support" - depends on ARCH_STM32 || COMPILE_TEST -+ imply NVMEM_STM32_BSEC_OPTEE_TA - help - Say y here to enable read-only access for STMicroelectronics STM32 - factory-programmed memory area. ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -61,6 +61,7 @@ obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem - nvmem_sprd_efuse-y := sprd-efuse.o - obj-$(CONFIG_NVMEM_STM32_ROMEM) += nvmem_stm32_romem.o - nvmem_stm32_romem-y := stm32-romem.o -+nvmem_stm32_romem-$(CONFIG_NVMEM_STM32_BSEC_OPTEE_TA) += stm32-bsec-optee-ta.o - obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o - nvmem_sunplus_ocotp-y := sunplus-ocotp.o - obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o ---- /dev/null -+++ b/drivers/nvmem/stm32-bsec-optee-ta.c -@@ -0,0 +1,298 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * OP-TEE STM32MP BSEC PTA interface, used by STM32 ROMEM driver -+ * -+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved -+ */ -+ -+#include -+ -+#include "stm32-bsec-optee-ta.h" -+ -+/* -+ * Read OTP memory -+ * -+ * [in] value[0].a OTP start offset in byte -+ * [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock) -+ * [out] memref[1].buffer Output buffer to store read values -+ * [out] memref[1].size Size of OTP to be read -+ * -+ * Return codes: -+ * TEE_SUCCESS - Invoke command success -+ * TEE_ERROR_BAD_PARAMETERS - Incorrect input param -+ * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller -+ */ -+#define PTA_BSEC_READ_MEM 0x0 -+ -+/* -+ * Write OTP memory -+ * -+ * [in] value[0].a OTP start offset in byte -+ * [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock) -+ * [in] memref[1].buffer Input buffer to read values -+ * [in] memref[1].size Size of OTP to be written -+ * -+ * Return codes: -+ * TEE_SUCCESS - Invoke command success -+ * TEE_ERROR_BAD_PARAMETERS - Incorrect input param -+ * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller -+ */ -+#define PTA_BSEC_WRITE_MEM 0x1 -+ -+/* value of PTA_BSEC access type = value[in] b */ -+#define SHADOW_ACCESS 0 -+#define FUSE_ACCESS 1 -+#define LOCK_ACCESS 2 -+ -+/* Bitfield definition for LOCK status */ -+#define LOCK_PERM BIT(30) -+ -+/* OP-TEE STM32MP BSEC TA UUID */ -+static const uuid_t stm32mp_bsec_ta_uuid = -+ UUID_INIT(0x94cf71ad, 0x80e6, 0x40b5, -+ 0xa7, 0xc6, 0x3d, 0xc5, 0x01, 0xeb, 0x28, 0x03); -+ -+/* -+ * Check whether this driver supports the BSEC TA in the TEE instance -+ * represented by the params (ver/data) to this function. -+ */ -+static int stm32_bsec_optee_ta_match(struct tee_ioctl_version_data *ver, -+ const void *data) -+{ -+ /* Currently this driver only supports GP compliant, OP-TEE based TA */ -+ if ((ver->impl_id == TEE_IMPL_ID_OPTEE) && -+ (ver->gen_caps & TEE_GEN_CAP_GP)) -+ return 1; -+ else -+ return 0; -+} -+ -+/* Open a session to OP-TEE for STM32MP BSEC TA */ -+static int stm32_bsec_ta_open_session(struct tee_context *ctx, u32 *id) -+{ -+ struct tee_ioctl_open_session_arg sess_arg; -+ int rc; -+ -+ memset(&sess_arg, 0, sizeof(sess_arg)); -+ export_uuid(sess_arg.uuid, &stm32mp_bsec_ta_uuid); -+ sess_arg.clnt_login = TEE_IOCTL_LOGIN_REE_KERNEL; -+ sess_arg.num_params = 0; -+ -+ rc = tee_client_open_session(ctx, &sess_arg, NULL); -+ if ((rc < 0) || (sess_arg.ret != 0)) { -+ pr_err("%s: tee_client_open_session failed err:%#x, ret:%#x\n", -+ __func__, sess_arg.ret, rc); -+ if (!rc) -+ rc = -EINVAL; -+ } else { -+ *id = sess_arg.session; -+ } -+ -+ return rc; -+} -+ -+/* close a session to OP-TEE for STM32MP BSEC TA */ -+static void stm32_bsec_ta_close_session(void *ctx, u32 id) -+{ -+ tee_client_close_session(ctx, id); -+} -+ -+/* stm32_bsec_optee_ta_open() - initialize the STM32MP BSEC TA */ -+int stm32_bsec_optee_ta_open(struct tee_context **ctx) -+{ -+ struct tee_context *tee_ctx; -+ u32 session_id; -+ int rc; -+ -+ /* Open context with TEE driver */ -+ tee_ctx = tee_client_open_context(NULL, stm32_bsec_optee_ta_match, NULL, NULL); -+ if (IS_ERR(tee_ctx)) { -+ rc = PTR_ERR(tee_ctx); -+ if (rc == -ENOENT) -+ return -EPROBE_DEFER; -+ pr_err("%s: tee_client_open_context failed (%d)\n", __func__, rc); -+ -+ return rc; -+ } -+ -+ /* Check STM32MP BSEC TA presence */ -+ rc = stm32_bsec_ta_open_session(tee_ctx, &session_id); -+ if (rc) { -+ tee_client_close_context(tee_ctx); -+ return rc; -+ } -+ -+ stm32_bsec_ta_close_session(tee_ctx, session_id); -+ -+ *ctx = tee_ctx; -+ -+ return 0; -+} -+ -+/* stm32_bsec_optee_ta_open() - release the PTA STM32MP BSEC TA */ -+void stm32_bsec_optee_ta_close(void *ctx) -+{ -+ tee_client_close_context(ctx); -+} -+ -+/* stm32_bsec_optee_ta_read() - nvmem read access using PTA client driver */ -+int stm32_bsec_optee_ta_read(struct tee_context *ctx, unsigned int offset, -+ void *buf, size_t bytes) -+{ -+ struct tee_shm *shm; -+ struct tee_ioctl_invoke_arg arg; -+ struct tee_param param[2]; -+ u8 *shm_buf; -+ u32 start, num_bytes; -+ int ret; -+ u32 session_id; -+ -+ ret = stm32_bsec_ta_open_session(ctx, &session_id); -+ if (ret) -+ return ret; -+ -+ memset(&arg, 0, sizeof(arg)); -+ memset(¶m, 0, sizeof(param)); -+ -+ arg.func = PTA_BSEC_READ_MEM; -+ arg.session = session_id; -+ arg.num_params = 2; -+ -+ /* align access on 32bits */ -+ start = ALIGN_DOWN(offset, 4); -+ num_bytes = round_up(offset + bytes - start, 4); -+ param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT; -+ param[0].u.value.a = start; -+ param[0].u.value.b = SHADOW_ACCESS; -+ -+ shm = tee_shm_alloc_kernel_buf(ctx, num_bytes); -+ if (IS_ERR(shm)) { -+ ret = PTR_ERR(shm); -+ goto out_tee_session; -+ } -+ -+ param[1].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT; -+ param[1].u.memref.shm = shm; -+ param[1].u.memref.size = num_bytes; -+ -+ ret = tee_client_invoke_func(ctx, &arg, param); -+ if (ret < 0 || arg.ret != 0) { -+ pr_err("TA_BSEC invoke failed TEE err:%#x, ret:%#x\n", -+ arg.ret, ret); -+ if (!ret) -+ ret = -EIO; -+ } -+ if (!ret) { -+ shm_buf = tee_shm_get_va(shm, 0); -+ if (IS_ERR(shm_buf)) { -+ ret = PTR_ERR(shm_buf); -+ pr_err("tee_shm_get_va failed for transmit (%d)\n", ret); -+ } else { -+ /* read data from 32 bits aligned buffer */ -+ memcpy(buf, &shm_buf[offset % 4], bytes); -+ } -+ } -+ -+ tee_shm_free(shm); -+ -+out_tee_session: -+ stm32_bsec_ta_close_session(ctx, session_id); -+ -+ return ret; -+} -+ -+/* stm32_bsec_optee_ta_write() - nvmem write access using PTA client driver */ -+int stm32_bsec_optee_ta_write(struct tee_context *ctx, unsigned int lower, -+ unsigned int offset, void *buf, size_t bytes) -+{ struct tee_shm *shm; -+ struct tee_ioctl_invoke_arg arg; -+ struct tee_param param[2]; -+ u8 *shm_buf; -+ int ret; -+ u32 session_id; -+ -+ ret = stm32_bsec_ta_open_session(ctx, &session_id); -+ if (ret) -+ return ret; -+ -+ /* Allow only writing complete 32-bits aligned words */ -+ if ((bytes % 4) || (offset % 4)) -+ return -EINVAL; -+ -+ memset(&arg, 0, sizeof(arg)); -+ memset(¶m, 0, sizeof(param)); -+ -+ arg.func = PTA_BSEC_WRITE_MEM; -+ arg.session = session_id; -+ arg.num_params = 2; -+ -+ param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT; -+ param[0].u.value.a = offset; -+ param[0].u.value.b = FUSE_ACCESS; -+ -+ shm = tee_shm_alloc_kernel_buf(ctx, bytes); -+ if (IS_ERR(shm)) { -+ ret = PTR_ERR(shm); -+ goto out_tee_session; -+ } -+ -+ param[1].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT; -+ param[1].u.memref.shm = shm; -+ param[1].u.memref.size = bytes; -+ -+ shm_buf = tee_shm_get_va(shm, 0); -+ if (IS_ERR(shm_buf)) { -+ ret = PTR_ERR(shm_buf); -+ pr_err("tee_shm_get_va failed for transmit (%d)\n", ret); -+ tee_shm_free(shm); -+ -+ goto out_tee_session; -+ } -+ -+ memcpy(shm_buf, buf, bytes); -+ -+ ret = tee_client_invoke_func(ctx, &arg, param); -+ if (ret < 0 || arg.ret != 0) { -+ pr_err("TA_BSEC invoke failed TEE err:%#x, ret:%#x\n", arg.ret, ret); -+ if (!ret) -+ ret = -EIO; -+ } -+ pr_debug("Write OTPs %d to %zu, ret=%d\n", offset / 4, (offset + bytes) / 4, ret); -+ -+ /* Lock the upper OTPs with ECC protection, word programming only */ -+ if (!ret && ((offset + bytes) >= (lower * 4))) { -+ u32 start, nb_lock; -+ u32 *lock = (u32 *)shm_buf; -+ int i; -+ -+ /* -+ * don't lock the lower OTPs, no ECC protection and incremental -+ * bit programming, a second write is allowed -+ */ -+ start = max_t(u32, offset, lower * 4); -+ nb_lock = (offset + bytes - start) / 4; -+ -+ param[0].u.value.a = start; -+ param[0].u.value.b = LOCK_ACCESS; -+ param[1].u.memref.size = nb_lock * 4; -+ -+ for (i = 0; i < nb_lock; i++) -+ lock[i] = LOCK_PERM; -+ -+ ret = tee_client_invoke_func(ctx, &arg, param); -+ if (ret < 0 || arg.ret != 0) { -+ pr_err("TA_BSEC invoke failed TEE err:%#x, ret:%#x\n", arg.ret, ret); -+ if (!ret) -+ ret = -EIO; -+ } -+ pr_debug("Lock upper OTPs %d to %d, ret=%d\n", -+ start / 4, start / 4 + nb_lock, ret); -+ } -+ -+ tee_shm_free(shm); -+ -+out_tee_session: -+ stm32_bsec_ta_close_session(ctx, session_id); -+ -+ return ret; -+} ---- /dev/null -+++ b/drivers/nvmem/stm32-bsec-optee-ta.h -@@ -0,0 +1,80 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * OP-TEE STM32MP BSEC PTA interface, used by STM32 ROMEM driver -+ * -+ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved -+ */ -+ -+#if IS_ENABLED(CONFIG_NVMEM_STM32_BSEC_OPTEE_TA) -+/** -+ * stm32_bsec_optee_ta_open() - initialize the STM32 BSEC TA -+ * @ctx: the OP-TEE context on success -+ * -+ * Return: -+ * On success, 0. On failure, -errno. -+ */ -+int stm32_bsec_optee_ta_open(struct tee_context **ctx); -+ -+/** -+ * stm32_bsec_optee_ta_close() - release the STM32 BSEC TA -+ * @ctx: the OP-TEE context -+ * -+ * This function used to clean the OP-TEE resources initialized in -+ * stm32_bsec_optee_ta_open(); it can be used as callback to -+ * devm_add_action_or_reset() -+ */ -+void stm32_bsec_optee_ta_close(void *ctx); -+ -+/** -+ * stm32_bsec_optee_ta_read() - nvmem read access using TA client driver -+ * @ctx: the OP-TEE context provided by stm32_bsec_optee_ta_open -+ * @offset: nvmem offset -+ * @buf: buffer to fill with nvem values -+ * @bytes: number of bytes to read -+ * -+ * Return: -+ * On success, 0. On failure, -errno. -+ */ -+int stm32_bsec_optee_ta_read(struct tee_context *ctx, unsigned int offset, -+ void *buf, size_t bytes); -+ -+/** -+ * stm32_bsec_optee_ta_write() - nvmem write access using TA client driver -+ * @ctx: the OP-TEE context provided by stm32_bsec_optee_ta_open -+ * @lower: number of lower OTP, not protected by ECC -+ * @offset: nvmem offset -+ * @buf: buffer with nvem values -+ * @bytes: number of bytes to write -+ * -+ * Return: -+ * On success, 0. On failure, -errno. -+ */ -+int stm32_bsec_optee_ta_write(struct tee_context *ctx, unsigned int lower, -+ unsigned int offset, void *buf, size_t bytes); -+ -+#else -+ -+static inline int stm32_bsec_optee_ta_open(struct tee_context **ctx) -+{ -+ return -EOPNOTSUPP; -+} -+ -+static inline void stm32_bsec_optee_ta_close(void *ctx) -+{ -+} -+ -+static inline int stm32_bsec_optee_ta_read(struct tee_context *ctx, -+ unsigned int offset, void *buf, -+ size_t bytes) -+{ -+ return -EOPNOTSUPP; -+} -+ -+static inline int stm32_bsec_optee_ta_write(struct tee_context *ctx, -+ unsigned int lower, -+ unsigned int offset, void *buf, -+ size_t bytes) -+{ -+ return -EOPNOTSUPP; -+} -+#endif /* CONFIG_NVMEM_STM32_BSEC_OPTEE_TA */ ---- a/drivers/nvmem/stm32-romem.c -+++ b/drivers/nvmem/stm32-romem.c -@@ -11,6 +11,9 @@ - #include - #include - #include -+#include -+ -+#include "stm32-bsec-optee-ta.h" - - /* BSEC secure service access from non-secure */ - #define STM32_SMC_BSEC 0x82001003 -@@ -25,12 +28,14 @@ - struct stm32_romem_cfg { - int size; - u8 lower; -+ bool ta; - }; - - struct stm32_romem_priv { - void __iomem *base; - struct nvmem_config cfg; - u8 lower; -+ struct tee_context *ctx; - }; - - static int stm32_romem_read(void *context, unsigned int offset, void *buf, -@@ -138,12 +143,29 @@ static int stm32_bsec_write(void *contex - return 0; - } - -+static int stm32_bsec_pta_read(void *context, unsigned int offset, void *buf, -+ size_t bytes) -+{ -+ struct stm32_romem_priv *priv = context; -+ -+ return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes); -+} -+ -+static int stm32_bsec_pta_write(void *context, unsigned int offset, void *buf, -+ size_t bytes) -+{ -+ struct stm32_romem_priv *priv = context; -+ -+ return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes); -+} -+ - static int stm32_romem_probe(struct platform_device *pdev) - { - const struct stm32_romem_cfg *cfg; - struct device *dev = &pdev->dev; - struct stm32_romem_priv *priv; - struct resource *res; -+ int rc; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) -@@ -173,15 +195,31 @@ static int stm32_romem_probe(struct plat - } else { - priv->cfg.size = cfg->size; - priv->lower = cfg->lower; -- priv->cfg.reg_read = stm32_bsec_read; -- priv->cfg.reg_write = stm32_bsec_write; -+ if (cfg->ta) { -+ rc = stm32_bsec_optee_ta_open(&priv->ctx); -+ /* wait for OP-TEE client driver to be up and ready */ -+ if (rc) -+ return rc; -+ } -+ if (priv->ctx) { -+ rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx); -+ if (rc) { -+ dev_err(dev, "devm_add_action_or_reset() failed (%d)\n", rc); -+ return rc; -+ } -+ priv->cfg.reg_read = stm32_bsec_pta_read; -+ priv->cfg.reg_write = stm32_bsec_pta_write; -+ } else { -+ priv->cfg.reg_read = stm32_bsec_read; -+ priv->cfg.reg_write = stm32_bsec_write; -+ } - } - - return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg)); - } - - /* -- * STM32MP15 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits) -+ * STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits) - * => 96 x 32-bits data words - * - Lower: 1K bits, 2:1 redundancy, incremental bit programming - * => 32 (x 32-bits) lower shadow registers = words 0 to 31 -@@ -191,6 +229,13 @@ static int stm32_romem_probe(struct plat - static const struct stm32_romem_cfg stm32mp15_bsec_cfg = { - .size = 384, - .lower = 32, -+ .ta = false, -+}; -+ -+static const struct stm32_romem_cfg stm32mp13_bsec_cfg = { -+ .size = 384, -+ .lower = 32, -+ .ta = true, - }; - - static const struct of_device_id stm32_romem_of_match[] = { -@@ -198,7 +243,10 @@ static const struct of_device_id stm32_r - .compatible = "st,stm32mp15-bsec", - .data = (void *)&stm32mp15_bsec_cfg, - }, { -+ .compatible = "st,stm32mp13-bsec", -+ .data = (void *)&stm32mp13_bsec_cfg, - }, -+ { /* sentinel */ }, - }; - MODULE_DEVICE_TABLE(of, stm32_romem_of_match); - diff --git a/target/linux/generic/backport-5.10/813-v6.3-0008-nvmem-stm32-detect-bsec-pta-presence-for-STM32MP15x.patch b/target/linux/generic/backport-5.10/813-v6.3-0008-nvmem-stm32-detect-bsec-pta-presence-for-STM32MP15x.patch deleted file mode 100644 index cea8e93858..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0008-nvmem-stm32-detect-bsec-pta-presence-for-STM32MP15x.patch +++ /dev/null @@ -1,85 +0,0 @@ -From df2f34ef1d924125ffaf29dfdaf7cdbd3183c321 Mon Sep 17 00:00:00 2001 -From: Patrick Delaunay -Date: Mon, 6 Feb 2023 13:43:52 +0000 -Subject: [PATCH] nvmem: stm32: detect bsec pta presence for STM32MP15x - -On STM32MP15x SoC, the SMC backend is optional when OP-TEE is used; -the PTA BSEC should be used as it is done on STM32MP13x platform, -but the BSEC SMC can be also used: it is a legacy mode in OP-TEE, -not recommended but used in previous OP-TEE firmware. - -The presence of OP-TEE is dynamically detected in STM32MP15x device tree -and the supported NVMEM backend is dynamically detected: -- PTA with stm32_bsec_pta_find -- SMC with stm32_bsec_check - -With OP-TEE but without PTA and SMC detection, the probe is deferred for -STM32MP15x devices. - -On STM32MP13x platform, only the PTA is supported with cfg->ta = true -and this detection is skipped. - -Signed-off-by: Patrick Delaunay -Reviewed-by: Etienne Carriere -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-19-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/stm32-romem.c | 38 +++++++++++++++++++++++++++++++++---- - 1 file changed, 34 insertions(+), 4 deletions(-) - ---- a/drivers/nvmem/stm32-romem.c -+++ b/drivers/nvmem/stm32-romem.c -@@ -159,6 +159,31 @@ static int stm32_bsec_pta_write(void *co - return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes); - } - -+static bool stm32_bsec_smc_check(void) -+{ -+ u32 val; -+ int ret; -+ -+ /* check that the OP-TEE support the BSEC SMC (legacy mode) */ -+ ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, 0, 0, &val); -+ -+ return !ret; -+} -+ -+static bool optee_presence_check(void) -+{ -+ struct device_node *np; -+ bool tee_detected = false; -+ -+ /* check that the OP-TEE node is present and available. */ -+ np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz"); -+ if (np && of_device_is_available(np)) -+ tee_detected = true; -+ of_node_put(np); -+ -+ return tee_detected; -+} -+ - static int stm32_romem_probe(struct platform_device *pdev) - { - const struct stm32_romem_cfg *cfg; -@@ -195,11 +220,16 @@ static int stm32_romem_probe(struct plat - } else { - priv->cfg.size = cfg->size; - priv->lower = cfg->lower; -- if (cfg->ta) { -+ if (cfg->ta || optee_presence_check()) { - rc = stm32_bsec_optee_ta_open(&priv->ctx); -- /* wait for OP-TEE client driver to be up and ready */ -- if (rc) -- return rc; -+ if (rc) { -+ /* wait for OP-TEE client driver to be up and ready */ -+ if (rc == -EPROBE_DEFER) -+ return -EPROBE_DEFER; -+ /* BSEC PTA is required or SMC not supported */ -+ if (cfg->ta || !stm32_bsec_smc_check()) -+ return rc; -+ } - } - if (priv->ctx) { - rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx); diff --git a/target/linux/generic/backport-5.10/813-v6.3-0009-nvmem-rave-sp-eeprm-fix-kernel-doc-bad-line-warning.patch b/target/linux/generic/backport-5.10/813-v6.3-0009-nvmem-rave-sp-eeprm-fix-kernel-doc-bad-line-warning.patch deleted file mode 100644 index 9d6275a737..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0009-nvmem-rave-sp-eeprm-fix-kernel-doc-bad-line-warning.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 3e5ac22aa564026e99defc3a8e02082521a5b231 Mon Sep 17 00:00:00 2001 -From: Randy Dunlap -Date: Mon, 6 Feb 2023 13:43:53 +0000 -Subject: [PATCH] nvmem: rave-sp-eeprm: fix kernel-doc bad line warning - -Convert an empty line to " *" to avoid a kernel-doc warning: - -drivers/nvmem/rave-sp-eeprom.c:48: warning: bad line: - -Signed-off-by: Randy Dunlap -Cc: Srinivas Kandagatla -Cc: Andrey Vostrikov -Cc: Nikita Yushchenko -Cc: Andrey Smirnov -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-20-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/rave-sp-eeprom.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/rave-sp-eeprom.c -+++ b/drivers/nvmem/rave-sp-eeprom.c -@@ -45,7 +45,7 @@ enum rave_sp_eeprom_header_size { - * @type: Access type (see enum rave_sp_eeprom_access_type) - * @success: Success flag (Success = 1, Failure = 0) - * @data: Read data -- -+ * - * Note this structure corresponds to RSP_*_EEPROM payload from RAVE - * SP ICD - */ diff --git a/target/linux/generic/backport-5.10/813-v6.3-0010-nvmem-qcom-spmi-sdam-register-at-device-init-time.patch b/target/linux/generic/backport-5.10/813-v6.3-0010-nvmem-qcom-spmi-sdam-register-at-device-init-time.patch deleted file mode 100644 index 1ab9e609d3..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0010-nvmem-qcom-spmi-sdam-register-at-device-init-time.patch +++ /dev/null @@ -1,43 +0,0 @@ -From eb7dda20f42a9137e9ee53d5ed3b743d49338cb5 Mon Sep 17 00:00:00 2001 -From: Johan Hovold -Date: Mon, 6 Feb 2023 13:43:54 +0000 -Subject: [PATCH] nvmem: qcom-spmi-sdam: register at device init time - -There are currently no in-tree users of the Qualcomm SDAM nvmem driver -and there is generally no point in registering a driver that can be -built as a module at subsys init time. - -Register the driver at the normal device init time instead and let -driver core sort out the probe order. - -Signed-off-by: Johan Hovold -Reviewed-by: Bjorn Andersson -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-21-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/qcom-spmi-sdam.c | 13 +------------ - 1 file changed, 1 insertion(+), 12 deletions(-) - ---- a/drivers/nvmem/qcom-spmi-sdam.c -+++ b/drivers/nvmem/qcom-spmi-sdam.c -@@ -175,18 +175,7 @@ static struct platform_driver sdam_drive - }, - .probe = sdam_probe, - }; -- --static int __init sdam_init(void) --{ -- return platform_driver_register(&sdam_driver); --} --subsys_initcall(sdam_init); -- --static void __exit sdam_exit(void) --{ -- return platform_driver_unregister(&sdam_driver); --} --module_exit(sdam_exit); -+module_platform_driver(sdam_driver); - - MODULE_DESCRIPTION("QCOM SPMI SDAM driver"); - MODULE_LICENSE("GPL v2"); diff --git a/target/linux/generic/backport-5.10/813-v6.3-0011-nvmem-stm32-fix-OPTEE-dependency.patch b/target/linux/generic/backport-5.10/813-v6.3-0011-nvmem-stm32-fix-OPTEE-dependency.patch deleted file mode 100644 index dcf704c6ff..0000000000 --- a/target/linux/generic/backport-5.10/813-v6.3-0011-nvmem-stm32-fix-OPTEE-dependency.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 1dc7e37bb0ec1c997fac82031332a38c7610352f Mon Sep 17 00:00:00 2001 -From: Arnd Bergmann -Date: Mon, 6 Feb 2023 13:43:56 +0000 -Subject: [PATCH] nvmem: stm32: fix OPTEE dependency - -The stm32 nvmem driver fails to link as built-in when OPTEE -is a loadable module: - -aarch64-linux-ld: drivers/nvmem/stm32-bsec-optee-ta.o: in function `stm32_bsec: -stm32-bsec-optee-ta.c:(.text+0xc8): undefined reference to `tee_client_open_session' -aarch64-linux-ld: drivers/nvmem/stm32-bsec-optee-ta.o: in function `stm32_bsec: -stm32-bsec-optee-ta.c:(.text+0x1fc): undefined reference to `tee_client_open_context' - -Change the CONFIG_NVMEM_STM32_ROMEM definition so it can only -be built-in if OPTEE is either built-in or disabled, and -make NVMEM_STM32_BSEC_OPTEE_TA a hidden symbol instead. - -Signed-off-by: Arnd Bergmann -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-23-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -291,8 +291,7 @@ config NVMEM_SPRD_EFUSE - will be called nvmem-sprd-efuse. - - config NVMEM_STM32_BSEC_OPTEE_TA -- bool "STM32MP BSEC OP-TEE TA support for nvmem-stm32-romem driver" -- depends on OPTEE -+ def_bool NVMEM_STM32_ROMEM && OPTEE - help - Say y here to enable the accesses to STM32MP SoC OTPs by the OP-TEE - trusted application STM32MP BSEC. -@@ -303,7 +302,7 @@ config NVMEM_STM32_BSEC_OPTEE_TA - config NVMEM_STM32_ROMEM - tristate "STMicroelectronics STM32 factory-programmed memory support" - depends on ARCH_STM32 || COMPILE_TEST -- imply NVMEM_STM32_BSEC_OPTEE_TA -+ depends on OPTEE || !OPTEE - help - Say y here to enable read-only access for STMicroelectronics STM32 - factory-programmed memory area. diff --git a/target/linux/generic/backport-5.10/814-v6.4-0001-nvmem-xilinx-zynqmp-make-modular.patch b/target/linux/generic/backport-5.10/814-v6.4-0001-nvmem-xilinx-zynqmp-make-modular.patch deleted file mode 100644 index 8328e87c0a..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0001-nvmem-xilinx-zynqmp-make-modular.patch +++ /dev/null @@ -1,35 +0,0 @@ -From bcd1fe07def0f070eb5f31594620aaee6f81d31a Mon Sep 17 00:00:00 2001 -From: Nick Alcock -Date: Tue, 4 Apr 2023 18:21:11 +0100 -Subject: [PATCH] nvmem: xilinx: zynqmp: make modular - -This driver has a MODULE_LICENSE but is not tristate so cannot be -built as a module, unlike all its peers: make it modular to match. - -Signed-off-by: Nick Alcock -Suggested-by: Michal Simek -Cc: Luis Chamberlain -Cc: linux-modules@vger.kernel.org -Cc: linux-kernel@vger.kernel.org -Cc: Hitomi Hasegawa -Cc: Srinivas Kandagatla -Cc: Michal Simek -Cc: linux-arm-kernel@lists.infradead.org -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-4-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -368,7 +368,7 @@ config NVMEM_VF610_OCOTP - be called nvmem-vf610-ocotp. - - config NVMEM_ZYNQMP -- bool "Xilinx ZYNQMP SoC nvmem firmware support" -+ tristate "Xilinx ZYNQMP SoC nvmem firmware support" - depends on ARCH_ZYNQMP - help - This is a driver to access hardware related data like diff --git a/target/linux/generic/backport-5.10/814-v6.4-0002-nvmem-core-introduce-NVMEM-layouts.patch b/target/linux/generic/backport-5.10/814-v6.4-0002-nvmem-core-introduce-NVMEM-layouts.patch deleted file mode 100644 index 8b886aea2e..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0002-nvmem-core-introduce-NVMEM-layouts.patch +++ /dev/null @@ -1,387 +0,0 @@ -From 266570f496b90dea8fda893c2cf7c28d63ae2bd9 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Tue, 4 Apr 2023 18:21:21 +0100 -Subject: [PATCH] nvmem: core: introduce NVMEM layouts - -NVMEM layouts are used to generate NVMEM cells during runtime. Think of -an EEPROM with a well-defined conent. For now, the content can be -described by a device tree or a board file. But this only works if the -offsets and lengths are static and don't change. One could also argue -that putting the layout of the EEPROM in the device tree is the wrong -place. Instead, the device tree should just have a specific compatible -string. - -Right now there are two use cases: - (1) The NVMEM cell needs special processing. E.g. if it only specifies - a base MAC address offset and you need to add an offset, or it - needs to parse a MAC from ASCII format or some proprietary format. - (Post processing of cells is added in a later commit). - (2) u-boot environment parsing. The cells don't have a particular - offset but it needs parsing the content to determine the offsets - and length. - -Co-developed-by: Miquel Raynal -Signed-off-by: Miquel Raynal -Signed-off-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-14-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - Documentation/driver-api/nvmem.rst | 15 ++++ - drivers/nvmem/Kconfig | 4 + - drivers/nvmem/Makefile | 1 + - drivers/nvmem/core.c | 120 +++++++++++++++++++++++++++++ - drivers/nvmem/layouts/Kconfig | 5 ++ - drivers/nvmem/layouts/Makefile | 4 + - include/linux/nvmem-consumer.h | 7 ++ - include/linux/nvmem-provider.h | 51 ++++++++++++ - 8 files changed, 207 insertions(+) - create mode 100644 drivers/nvmem/layouts/Kconfig - create mode 100644 drivers/nvmem/layouts/Makefile - ---- a/Documentation/driver-api/nvmem.rst -+++ b/Documentation/driver-api/nvmem.rst -@@ -189,3 +189,18 @@ ex:: - ===================== - - See Documentation/devicetree/bindings/nvmem/nvmem.txt -+ -+8. NVMEM layouts -+================ -+ -+NVMEM layouts are yet another mechanism to create cells. With the device -+tree binding it is possible to specify simple cells by using an offset -+and a length. Sometimes, the cells doesn't have a static offset, but -+the content is still well defined, e.g. tag-length-values. In this case, -+the NVMEM device content has to be first parsed and the cells need to -+be added accordingly. Layouts let you read the content of the NVMEM device -+and let you add cells dynamically. -+ -+Another use case for layouts is the post processing of cells. With layouts, -+it is possible to associate a custom post processing hook to a cell. It -+even possible to add this hook to cells not created by the layout itself. ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -21,6 +21,10 @@ config NVMEM_SYSFS - This interface is mostly used by userspace applications to - read/write directly into nvmem. - -+# Layouts -+ -+source "drivers/nvmem/layouts/Kconfig" -+ - # Devices - - config NVMEM_APPLE_EFUSES ---- a/drivers/nvmem/Makefile -+++ b/drivers/nvmem/Makefile -@@ -5,6 +5,7 @@ - - obj-$(CONFIG_NVMEM) += nvmem_core.o - nvmem_core-y := core.o -+obj-y += layouts/ - - # Devices - obj-$(CONFIG_NVMEM_APPLE_EFUSES) += nvmem-apple-efuses.o ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -40,6 +40,7 @@ struct nvmem_device { - nvmem_reg_write_t reg_write; - nvmem_cell_post_process_t cell_post_process; - struct gpio_desc *wp_gpio; -+ struct nvmem_layout *layout; - void *priv; - }; - -@@ -74,6 +75,9 @@ static LIST_HEAD(nvmem_lookup_list); - - static BLOCKING_NOTIFIER_HEAD(nvmem_notifier); - -+static DEFINE_SPINLOCK(nvmem_layout_lock); -+static LIST_HEAD(nvmem_layouts); -+ - static int __nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset, - void *val, size_t bytes) - { -@@ -728,6 +732,101 @@ static int nvmem_add_cells_from_of(struc - return 0; - } - -+int __nvmem_layout_register(struct nvmem_layout *layout, struct module *owner) -+{ -+ layout->owner = owner; -+ -+ spin_lock(&nvmem_layout_lock); -+ list_add(&layout->node, &nvmem_layouts); -+ spin_unlock(&nvmem_layout_lock); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(__nvmem_layout_register); -+ -+void nvmem_layout_unregister(struct nvmem_layout *layout) -+{ -+ spin_lock(&nvmem_layout_lock); -+ list_del(&layout->node); -+ spin_unlock(&nvmem_layout_lock); -+} -+EXPORT_SYMBOL_GPL(nvmem_layout_unregister); -+ -+static struct nvmem_layout *nvmem_layout_get(struct nvmem_device *nvmem) -+{ -+ struct device_node *layout_np, *np = nvmem->dev.of_node; -+ struct nvmem_layout *l, *layout = NULL; -+ -+ layout_np = of_get_child_by_name(np, "nvmem-layout"); -+ if (!layout_np) -+ return NULL; -+ -+ spin_lock(&nvmem_layout_lock); -+ -+ list_for_each_entry(l, &nvmem_layouts, node) { -+ if (of_match_node(l->of_match_table, layout_np)) { -+ if (try_module_get(l->owner)) -+ layout = l; -+ -+ break; -+ } -+ } -+ -+ spin_unlock(&nvmem_layout_lock); -+ of_node_put(layout_np); -+ -+ return layout; -+} -+ -+static void nvmem_layout_put(struct nvmem_layout *layout) -+{ -+ if (layout) -+ module_put(layout->owner); -+} -+ -+static int nvmem_add_cells_from_layout(struct nvmem_device *nvmem) -+{ -+ struct nvmem_layout *layout = nvmem->layout; -+ int ret; -+ -+ if (layout && layout->add_cells) { -+ ret = layout->add_cells(&nvmem->dev, nvmem, layout); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+#if IS_ENABLED(CONFIG_OF) -+/** -+ * of_nvmem_layout_get_container() - Get OF node to layout container. -+ * -+ * @nvmem: nvmem device. -+ * -+ * Return: a node pointer with refcount incremented or NULL if no -+ * container exists. Use of_node_put() on it when done. -+ */ -+struct device_node *of_nvmem_layout_get_container(struct nvmem_device *nvmem) -+{ -+ return of_get_child_by_name(nvmem->dev.of_node, "nvmem-layout"); -+} -+EXPORT_SYMBOL_GPL(of_nvmem_layout_get_container); -+#endif -+ -+const void *nvmem_layout_get_match_data(struct nvmem_device *nvmem, -+ struct nvmem_layout *layout) -+{ -+ struct device_node __maybe_unused *layout_np; -+ const struct of_device_id *match; -+ -+ layout_np = of_nvmem_layout_get_container(nvmem); -+ match = of_match_node(layout->of_match_table, layout_np); -+ -+ return match ? match->data : NULL; -+} -+EXPORT_SYMBOL_GPL(nvmem_layout_get_match_data); -+ - /** - * nvmem_register() - Register a nvmem device for given nvmem_config. - * Also creates a binary entry in /sys/bus/nvmem/devices/dev-name/nvmem -@@ -834,6 +933,12 @@ struct nvmem_device *nvmem_register(cons - goto err_put_device; - } - -+ /* -+ * If the driver supplied a layout by config->layout, the module -+ * pointer will be NULL and nvmem_layout_put() will be a noop. -+ */ -+ nvmem->layout = config->layout ?: nvmem_layout_get(nvmem); -+ - if (config->cells) { - rval = nvmem_add_cells(nvmem, config->cells, config->ncells); - if (rval) -@@ -854,12 +959,17 @@ struct nvmem_device *nvmem_register(cons - if (rval) - goto err_remove_cells; - -+ rval = nvmem_add_cells_from_layout(nvmem); -+ if (rval) -+ goto err_remove_cells; -+ - blocking_notifier_call_chain(&nvmem_notifier, NVMEM_ADD, nvmem); - - return nvmem; - - err_remove_cells: - nvmem_device_remove_all_cells(nvmem); -+ nvmem_layout_put(nvmem->layout); - if (config->compat) - nvmem_sysfs_remove_compat(nvmem, config); - err_put_device: -@@ -881,6 +991,7 @@ static void nvmem_device_release(struct - device_remove_bin_file(nvmem->base_dev, &nvmem->eeprom); - - nvmem_device_remove_all_cells(nvmem); -+ nvmem_layout_put(nvmem->layout); - device_unregister(&nvmem->dev); - } - -@@ -1246,6 +1357,15 @@ struct nvmem_cell *of_nvmem_cell_get(str - return ERR_PTR(-EINVAL); - } - -+ /* nvmem layouts produce cells within the nvmem-layout container */ -+ if (of_node_name_eq(nvmem_np, "nvmem-layout")) { -+ nvmem_np = of_get_next_parent(nvmem_np); -+ if (!nvmem_np) { -+ of_node_put(cell_np); -+ return ERR_PTR(-EINVAL); -+ } -+ } -+ - nvmem = __nvmem_device_get(nvmem_np, device_match_of_node); - of_node_put(nvmem_np); - if (IS_ERR(nvmem)) { ---- /dev/null -+++ b/drivers/nvmem/layouts/Kconfig -@@ -0,0 +1,5 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+menu "Layout Types" -+ -+endmenu ---- /dev/null -+++ b/drivers/nvmem/layouts/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0 -+# -+# Makefile for nvmem layouts. -+# ---- a/include/linux/nvmem-consumer.h -+++ b/include/linux/nvmem-consumer.h -@@ -225,6 +225,7 @@ struct nvmem_cell *of_nvmem_cell_get(str - const char *id); - struct nvmem_device *of_nvmem_device_get(struct device_node *np, - const char *name); -+struct device_node *of_nvmem_layout_get_container(struct nvmem_device *nvmem); - #else - static inline struct nvmem_cell *of_nvmem_cell_get(struct device_node *np, - const char *id) -@@ -237,6 +238,12 @@ static inline struct nvmem_device *of_nv - { - return ERR_PTR(-EOPNOTSUPP); - } -+ -+static inline struct device_node * -+of_nvmem_layout_get_container(struct nvmem_device *nvmem) -+{ -+ return ERR_PTR(-EOPNOTSUPP); -+} - #endif /* CONFIG_NVMEM && CONFIG_OF */ - - #endif /* ifndef _LINUX_NVMEM_CONSUMER_H */ ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -88,6 +88,7 @@ struct nvmem_cell_info { - * @stride: Minimum read/write access stride. - * @priv: User context passed to read/write callbacks. - * @ignore_wp: Write Protect pin is managed by the provider. -+ * @layout: Fixed layout associated with this nvmem device. - * - * Note: A default "nvmem" name will be assigned to the device if - * no name is specified in its configuration. In such case "" is -@@ -110,6 +111,7 @@ struct nvmem_config { - bool root_only; - struct device_node *of_node; - bool ignore_wp; -+ struct nvmem_layout *layout; - bool no_of_node; - nvmem_reg_read_t reg_read; - nvmem_reg_write_t reg_write; -@@ -142,6 +144,33 @@ struct nvmem_cell_table { - struct list_head node; - }; - -+/** -+ * struct nvmem_layout - NVMEM layout definitions -+ * -+ * @name: Layout name. -+ * @of_match_table: Open firmware match table. -+ * @add_cells: Will be called if a nvmem device is found which -+ * has this layout. The function will add layout -+ * specific cells with nvmem_add_one_cell(). -+ * @owner: Pointer to struct module. -+ * @node: List node. -+ * -+ * A nvmem device can hold a well defined structure which can just be -+ * evaluated during runtime. For example a TLV list, or a list of "name=val" -+ * pairs. A nvmem layout can parse the nvmem device and add appropriate -+ * cells. -+ */ -+struct nvmem_layout { -+ const char *name; -+ const struct of_device_id *of_match_table; -+ int (*add_cells)(struct device *dev, struct nvmem_device *nvmem, -+ struct nvmem_layout *layout); -+ -+ /* private */ -+ struct module *owner; -+ struct list_head node; -+}; -+ - #if IS_ENABLED(CONFIG_NVMEM) - - struct nvmem_device *nvmem_register(const struct nvmem_config *cfg); -@@ -156,6 +185,14 @@ void nvmem_del_cell_table(struct nvmem_c - int nvmem_add_one_cell(struct nvmem_device *nvmem, - const struct nvmem_cell_info *info); - -+int __nvmem_layout_register(struct nvmem_layout *layout, struct module *owner); -+#define nvmem_layout_register(layout) \ -+ __nvmem_layout_register(layout, THIS_MODULE) -+void nvmem_layout_unregister(struct nvmem_layout *layout); -+ -+const void *nvmem_layout_get_match_data(struct nvmem_device *nvmem, -+ struct nvmem_layout *layout); -+ - #else - - static inline struct nvmem_device *nvmem_register(const struct nvmem_config *c) -@@ -179,5 +216,19 @@ static inline int nvmem_add_one_cell(str - return -EOPNOTSUPP; - } - -+static inline int nvmem_layout_register(struct nvmem_layout *layout) -+{ -+ return -EOPNOTSUPP; -+} -+ -+static inline void nvmem_layout_unregister(struct nvmem_layout *layout) {} -+ -+static inline const void * -+nvmem_layout_get_match_data(struct nvmem_device *nvmem, -+ struct nvmem_layout *layout) -+{ -+ return NULL; -+} -+ - #endif /* CONFIG_NVMEM */ - #endif /* ifndef _LINUX_NVMEM_PROVIDER_H */ diff --git a/target/linux/generic/backport-5.10/814-v6.4-0003-nvmem-core-handle-the-absence-of-expected-layouts.patch b/target/linux/generic/backport-5.10/814-v6.4-0003-nvmem-core-handle-the-absence-of-expected-layouts.patch deleted file mode 100644 index 6fa7b6382d..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0003-nvmem-core-handle-the-absence-of-expected-layouts.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 6468a6f45148fb5e95c86b4efebf63f9abcd2137 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:22 +0100 -Subject: [PATCH] nvmem: core: handle the absence of expected layouts - -Make nvmem_layout_get() return -EPROBE_DEFER while the expected layout -is not available. This condition cannot be triggered today as nvmem -layout drivers are initialed as part of an early init call, but soon -these drivers will be converted into modules and be initialized with a -standard priority, so the unavailability of the drivers might become a -reality that must be taken care of. - -Let's anticipate this by telling the caller the layout might not yet be -available. A probe deferral is requested in this case. - -Please note this does not affect any nvmem device not using layouts, -because an early check against the "nvmem-layout" container presence -will return NULL in this case. - -Signed-off-by: Miquel Raynal -Tested-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-15-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 10 +++++++++- - 1 file changed, 9 insertions(+), 1 deletion(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -755,7 +755,7 @@ EXPORT_SYMBOL_GPL(nvmem_layout_unregiste - static struct nvmem_layout *nvmem_layout_get(struct nvmem_device *nvmem) - { - struct device_node *layout_np, *np = nvmem->dev.of_node; -- struct nvmem_layout *l, *layout = NULL; -+ struct nvmem_layout *l, *layout = ERR_PTR(-EPROBE_DEFER); - - layout_np = of_get_child_by_name(np, "nvmem-layout"); - if (!layout_np) -@@ -938,6 +938,13 @@ struct nvmem_device *nvmem_register(cons - * pointer will be NULL and nvmem_layout_put() will be a noop. - */ - nvmem->layout = config->layout ?: nvmem_layout_get(nvmem); -+ if (IS_ERR(nvmem->layout)) { -+ rval = PTR_ERR(nvmem->layout); -+ nvmem->layout = NULL; -+ -+ if (rval == -EPROBE_DEFER) -+ goto err_teardown_compat; -+ } - - if (config->cells) { - rval = nvmem_add_cells(nvmem, config->cells, config->ncells); -@@ -970,6 +977,7 @@ struct nvmem_device *nvmem_register(cons - err_remove_cells: - nvmem_device_remove_all_cells(nvmem); - nvmem_layout_put(nvmem->layout); -+err_teardown_compat: - if (config->compat) - nvmem_sysfs_remove_compat(nvmem, config); - err_put_device: diff --git a/target/linux/generic/backport-5.10/814-v6.4-0004-nvmem-core-request-layout-modules-loading.patch b/target/linux/generic/backport-5.10/814-v6.4-0004-nvmem-core-request-layout-modules-loading.patch deleted file mode 100644 index b9341666f9..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0004-nvmem-core-request-layout-modules-loading.patch +++ /dev/null @@ -1,52 +0,0 @@ -From b1c37bec1ccfe5ccab72bc0ddc0dfa45c43e2de2 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:23 +0100 -Subject: [PATCH] nvmem: core: request layout modules loading - -When a storage device like an eeprom or an mtd device probes, it -registers an nvmem device if the nvmem subsystem has been enabled (bool -symbol). During nvmem registration, if the device is using layouts to -expose dynamic nvmem cells, the core will first try to get a reference -over the layout driver callbacks. In practice there is not relationship -that can be described between the storage driver and the nvmem -layout. So there is no way we can enforce both drivers will be built-in -or both will be modules. If the storage device driver is built-in but -the layout is built as a module, instead of badly failing with an -endless probe deferral loop, lets just make a modprobe call in case the -driver was made available in an initramfs with -of_device_node_request_module(), and offer a fully functional system to -the user. - -Signed-off-by: Miquel Raynal -Tested-by: Michael Walle -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-16-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - #include - - struct nvmem_device { -@@ -761,6 +762,13 @@ static struct nvmem_layout *nvmem_layout - if (!layout_np) - return NULL; - -+ /* -+ * In case the nvmem device was built-in while the layout was built as a -+ * module, we shall manually request the layout driver loading otherwise -+ * we'll never have any match. -+ */ -+ of_request_module(layout_np); -+ - spin_lock(&nvmem_layout_lock); - - list_for_each_entry(l, &nvmem_layouts, node) { diff --git a/target/linux/generic/backport-5.10/814-v6.4-0005-nvmem-core-add-per-cell-post-processing.patch b/target/linux/generic/backport-5.10/814-v6.4-0005-nvmem-core-add-per-cell-post-processing.patch deleted file mode 100644 index 53628cd4e4..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0005-nvmem-core-add-per-cell-post-processing.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 345ec382cd4b736c36e01f155d08c913b225b736 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Tue, 4 Apr 2023 18:21:24 +0100 -Subject: [PATCH] nvmem: core: add per-cell post processing - -Instead of relying on the name the consumer is using for the cell, like -it is done for the nvmem .cell_post_process configuration parameter, -provide a per-cell post processing hook. This can then be populated by -the NVMEM provider (or the NVMEM layout) when adding the cell. - -Signed-off-by: Michael Walle -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-17-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 17 +++++++++++++++++ - include/linux/nvmem-provider.h | 3 +++ - 2 files changed, 20 insertions(+) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -54,6 +54,7 @@ struct nvmem_cell_entry { - int bytes; - int bit_offset; - int nbits; -+ nvmem_cell_post_process_t read_post_process; - struct device_node *np; - struct nvmem_device *nvmem; - struct list_head node; -@@ -470,6 +471,7 @@ static int nvmem_cell_info_to_nvmem_cell - cell->offset = info->offset; - cell->bytes = info->bytes; - cell->name = info->name; -+ cell->read_post_process = info->read_post_process; - - cell->bit_offset = info->bit_offset; - cell->nbits = info->nbits; -@@ -1563,6 +1565,13 @@ static int __nvmem_cell_read(struct nvme - if (cell->bit_offset || cell->nbits) - nvmem_shift_read_buffer_in_place(cell, buf); - -+ if (cell->read_post_process) { -+ rc = cell->read_post_process(nvmem->priv, id, index, -+ cell->offset, buf, cell->bytes); -+ if (rc) -+ return rc; -+ } -+ - if (nvmem->cell_post_process) { - rc = nvmem->cell_post_process(nvmem->priv, id, index, - cell->offset, buf, cell->bytes); -@@ -1671,6 +1680,14 @@ static int __nvmem_cell_entry_write(stru - (cell->bit_offset == 0 && len != cell->bytes)) - return -EINVAL; - -+ /* -+ * Any cells which have a read_post_process hook are read-only because -+ * we cannot reverse the operation and it might affect other cells, -+ * too. -+ */ -+ if (cell->read_post_process) -+ return -EINVAL; -+ - if (cell->bit_offset || cell->nbits) { - buf = nvmem_cell_prepare_write_buffer(cell, buf, len); - if (IS_ERR(buf)) ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -54,6 +54,8 @@ struct nvmem_keepout { - * @bit_offset: Bit offset if cell is smaller than a byte. - * @nbits: Number of bits. - * @np: Optional device_node pointer. -+ * @read_post_process: Callback for optional post processing of cell data -+ * on reads. - */ - struct nvmem_cell_info { - const char *name; -@@ -62,6 +64,7 @@ struct nvmem_cell_info { - unsigned int bit_offset; - unsigned int nbits; - struct device_node *np; -+ nvmem_cell_post_process_t read_post_process; - }; - - /** diff --git a/target/linux/generic/backport-5.10/814-v6.4-0006-nvmem-core-allow-to-modify-a-cell-before-adding-it.patch b/target/linux/generic/backport-5.10/814-v6.4-0006-nvmem-core-allow-to-modify-a-cell-before-adding-it.patch deleted file mode 100644 index 32990148c8..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0006-nvmem-core-allow-to-modify-a-cell-before-adding-it.patch +++ /dev/null @@ -1,59 +0,0 @@ -From de12c9691501ccba41a154c223869f82be4c12fd Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Tue, 4 Apr 2023 18:21:25 +0100 -Subject: [PATCH] nvmem: core: allow to modify a cell before adding it - -Provide a way to modify a cell before it will get added. This is useful -to attach a custom post processing hook via a layout. - -Signed-off-by: Michael Walle -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-18-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 4 ++++ - include/linux/nvmem-provider.h | 5 +++++ - 2 files changed, 9 insertions(+) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -695,6 +695,7 @@ static int nvmem_validate_keepouts(struc - - static int nvmem_add_cells_from_of(struct nvmem_device *nvmem) - { -+ struct nvmem_layout *layout = nvmem->layout; - struct device *dev = &nvmem->dev; - struct device_node *child; - const __be32 *addr; -@@ -724,6 +725,9 @@ static int nvmem_add_cells_from_of(struc - - info.np = of_node_get(child); - -+ if (layout && layout->fixup_cell_info) -+ layout->fixup_cell_info(nvmem, layout, &info); -+ - ret = nvmem_add_one_cell(nvmem, &info); - kfree(info.name); - if (ret) { ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -155,6 +155,8 @@ struct nvmem_cell_table { - * @add_cells: Will be called if a nvmem device is found which - * has this layout. The function will add layout - * specific cells with nvmem_add_one_cell(). -+ * @fixup_cell_info: Will be called before a cell is added. Can be -+ * used to modify the nvmem_cell_info. - * @owner: Pointer to struct module. - * @node: List node. - * -@@ -168,6 +170,9 @@ struct nvmem_layout { - const struct of_device_id *of_match_table; - int (*add_cells)(struct device *dev, struct nvmem_device *nvmem, - struct nvmem_layout *layout); -+ void (*fixup_cell_info)(struct nvmem_device *nvmem, -+ struct nvmem_layout *layout, -+ struct nvmem_cell_info *cell); - - /* private */ - struct module *owner; diff --git a/target/linux/generic/backport-5.10/814-v6.4-0007-nvmem-imx-ocotp-replace-global-post-processing-with-.patch b/target/linux/generic/backport-5.10/814-v6.4-0007-nvmem-imx-ocotp-replace-global-post-processing-with-.patch deleted file mode 100644 index 2a5fa618ea..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0007-nvmem-imx-ocotp-replace-global-post-processing-with-.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 6c56a82d7895a213a43182a5d01a21a906a79847 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Tue, 4 Apr 2023 18:21:26 +0100 -Subject: [PATCH] nvmem: imx-ocotp: replace global post processing with layouts - -In preparation of retiring the global post processing hook change this -driver to use layouts. The layout will be supplied during registration -and will be used to add the post processing hook to all added cells. - -Signed-off-by: Michael Walle -Tested-by: Michael Walle # on kontron-pitx-imx8m -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-19-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/imx-ocotp.c | 30 +++++++++++++++++++----------- - 1 file changed, 19 insertions(+), 11 deletions(-) - ---- a/drivers/nvmem/imx-ocotp.c -+++ b/drivers/nvmem/imx-ocotp.c -@@ -225,18 +225,13 @@ read_end: - static int imx_ocotp_cell_pp(void *context, const char *id, int index, - unsigned int offset, void *data, size_t bytes) - { -- struct ocotp_priv *priv = context; -+ u8 *buf = data; -+ int i; - - /* Deal with some post processing of nvmem cell data */ -- if (id && !strcmp(id, "mac-address")) { -- if (priv->params->reverse_mac_address) { -- u8 *buf = data; -- int i; -- -- for (i = 0; i < bytes/2; i++) -- swap(buf[i], buf[bytes - i - 1]); -- } -- } -+ if (id && !strcmp(id, "mac-address")) -+ for (i = 0; i < bytes / 2; i++) -+ swap(buf[i], buf[bytes - i - 1]); - - return 0; - } -@@ -488,7 +483,6 @@ static struct nvmem_config imx_ocotp_nvm - .stride = 1, - .reg_read = imx_ocotp_read, - .reg_write = imx_ocotp_write, -- .cell_post_process = imx_ocotp_cell_pp, - }; - - static const struct ocotp_params imx6q_params = { -@@ -595,6 +589,17 @@ static const struct of_device_id imx_oco - }; - MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids); - -+static void imx_ocotp_fixup_cell_info(struct nvmem_device *nvmem, -+ struct nvmem_layout *layout, -+ struct nvmem_cell_info *cell) -+{ -+ cell->read_post_process = imx_ocotp_cell_pp; -+} -+ -+struct nvmem_layout imx_ocotp_layout = { -+ .fixup_cell_info = imx_ocotp_fixup_cell_info, -+}; -+ - static int imx_ocotp_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -619,6 +624,9 @@ static int imx_ocotp_probe(struct platfo - imx_ocotp_nvmem_config.size = 4 * priv->params->nregs; - imx_ocotp_nvmem_config.dev = dev; - imx_ocotp_nvmem_config.priv = priv; -+ if (priv->params->reverse_mac_address) -+ imx_ocotp_nvmem_config.layout = &imx_ocotp_layout; -+ - priv->config = &imx_ocotp_nvmem_config; - - clk_prepare_enable(priv->clk); diff --git a/target/linux/generic/backport-5.10/814-v6.4-0008-nvmem-cell-drop-global-cell_post_process.patch b/target/linux/generic/backport-5.10/814-v6.4-0008-nvmem-cell-drop-global-cell_post_process.patch deleted file mode 100644 index eac202b882..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0008-nvmem-cell-drop-global-cell_post_process.patch +++ /dev/null @@ -1,68 +0,0 @@ -From 011e40a166fdaa65fb9946b7cd91efec85b70dbb Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Tue, 4 Apr 2023 18:21:27 +0100 -Subject: [PATCH] nvmem: cell: drop global cell_post_process - -There are no users anymore for the global cell_post_process callback -anymore. New users should use proper nvmem layouts. - -Signed-off-by: Michael Walle -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-20-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 9 --------- - include/linux/nvmem-provider.h | 2 -- - 2 files changed, 11 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -39,7 +39,6 @@ struct nvmem_device { - unsigned int nkeepout; - nvmem_reg_read_t reg_read; - nvmem_reg_write_t reg_write; -- nvmem_cell_post_process_t cell_post_process; - struct gpio_desc *wp_gpio; - struct nvmem_layout *layout; - void *priv; -@@ -903,7 +902,6 @@ struct nvmem_device *nvmem_register(cons - nvmem->type = config->type; - nvmem->reg_read = config->reg_read; - nvmem->reg_write = config->reg_write; -- nvmem->cell_post_process = config->cell_post_process; - nvmem->keepout = config->keepout; - nvmem->nkeepout = config->nkeepout; - if (config->of_node) -@@ -1575,13 +1573,6 @@ static int __nvmem_cell_read(struct nvme - if (rc) - return rc; - } -- -- if (nvmem->cell_post_process) { -- rc = nvmem->cell_post_process(nvmem->priv, id, index, -- cell->offset, buf, cell->bytes); -- if (rc) -- return rc; -- } - - if (len) - *len = cell->bytes; ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -85,7 +85,6 @@ struct nvmem_cell_info { - * @no_of_node: Device should not use the parent's of_node even if it's !NULL. - * @reg_read: Callback to read data. - * @reg_write: Callback to write data. -- * @cell_post_process: Callback for vendor specific post processing of cell data - * @size: Device size. - * @word_size: Minimum read/write access granularity. - * @stride: Minimum read/write access stride. -@@ -118,7 +117,6 @@ struct nvmem_config { - bool no_of_node; - nvmem_reg_read_t reg_read; - nvmem_reg_write_t reg_write; -- nvmem_cell_post_process_t cell_post_process; - int size; - int word_size; - int stride; diff --git a/target/linux/generic/backport-5.10/814-v6.4-0009-nvmem-core-provide-own-priv-pointer-in-post-process-.patch b/target/linux/generic/backport-5.10/814-v6.4-0009-nvmem-core-provide-own-priv-pointer-in-post-process-.patch deleted file mode 100644 index 46b30a2ed9..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0009-nvmem-core-provide-own-priv-pointer-in-post-process-.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 8a134fd9f9323f4c39ec27055b3d3723cfb5c1e9 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Tue, 4 Apr 2023 18:21:28 +0100 -Subject: [PATCH] nvmem: core: provide own priv pointer in post process - callback - -It doesn't make any more sense to have a opaque pointer set up by the -nvmem device. Usually, the layout isn't associated with a particular -nvmem device. Instead, let the caller who set the post process callback -provide the priv pointer. - -Signed-off-by: Michael Walle -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-21-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 4 +++- - include/linux/nvmem-provider.h | 5 ++++- - 2 files changed, 7 insertions(+), 2 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -54,6 +54,7 @@ struct nvmem_cell_entry { - int bit_offset; - int nbits; - nvmem_cell_post_process_t read_post_process; -+ void *priv; - struct device_node *np; - struct nvmem_device *nvmem; - struct list_head node; -@@ -471,6 +472,7 @@ static int nvmem_cell_info_to_nvmem_cell - cell->bytes = info->bytes; - cell->name = info->name; - cell->read_post_process = info->read_post_process; -+ cell->priv = info->priv; - - cell->bit_offset = info->bit_offset; - cell->nbits = info->nbits; -@@ -1568,7 +1570,7 @@ static int __nvmem_cell_read(struct nvme - nvmem_shift_read_buffer_in_place(cell, buf); - - if (cell->read_post_process) { -- rc = cell->read_post_process(nvmem->priv, id, index, -+ rc = cell->read_post_process(cell->priv, id, index, - cell->offset, buf, cell->bytes); - if (rc) - return rc; ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -20,7 +20,8 @@ typedef int (*nvmem_reg_write_t)(void *p - void *val, size_t bytes); - /* used for vendor specific post processing of cell data */ - typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, int index, -- unsigned int offset, void *buf, size_t bytes); -+ unsigned int offset, void *buf, -+ size_t bytes); - - enum nvmem_type { - NVMEM_TYPE_UNKNOWN = 0, -@@ -56,6 +57,7 @@ struct nvmem_keepout { - * @np: Optional device_node pointer. - * @read_post_process: Callback for optional post processing of cell data - * on reads. -+ * @priv: Opaque data passed to the read_post_process hook. - */ - struct nvmem_cell_info { - const char *name; -@@ -65,6 +67,7 @@ struct nvmem_cell_info { - unsigned int nbits; - struct device_node *np; - nvmem_cell_post_process_t read_post_process; -+ void *priv; - }; - - /** diff --git a/target/linux/generic/backport-5.10/814-v6.4-0010-nvmem-layouts-sl28vpd-Add-new-layout-driver.patch b/target/linux/generic/backport-5.10/814-v6.4-0010-nvmem-layouts-sl28vpd-Add-new-layout-driver.patch deleted file mode 100644 index 7d97658b60..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0010-nvmem-layouts-sl28vpd-Add-new-layout-driver.patch +++ /dev/null @@ -1,215 +0,0 @@ -From d9fae023fe86069750092fc1c2f3a73e2fb18512 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Tue, 4 Apr 2023 18:21:29 +0100 -Subject: [PATCH] nvmem: layouts: sl28vpd: Add new layout driver - -This layout applies to the VPD of the Kontron sl28 boards. The VPD only -contains a base MAC address. Therefore, we have to add an individual -offset to it. This is done by taking the second argument of the nvmem -phandle into account. Also this let us checking the VPD version and the -checksum. - -Signed-off-by: Michael Walle -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-22-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/layouts/Kconfig | 9 ++ - drivers/nvmem/layouts/Makefile | 2 + - drivers/nvmem/layouts/sl28vpd.c | 165 ++++++++++++++++++++++++++++++++ - 3 files changed, 176 insertions(+) - create mode 100644 drivers/nvmem/layouts/sl28vpd.c - ---- a/drivers/nvmem/layouts/Kconfig -+++ b/drivers/nvmem/layouts/Kconfig -@@ -2,4 +2,13 @@ - - menu "Layout Types" - -+config NVMEM_LAYOUT_SL28_VPD -+ tristate "Kontron sl28 VPD layout support" -+ select CRC8 -+ help -+ Say Y here if you want to support the VPD layout of the Kontron -+ SMARC-sAL28 boards. -+ -+ If unsure, say N. -+ - endmenu ---- a/drivers/nvmem/layouts/Makefile -+++ b/drivers/nvmem/layouts/Makefile -@@ -2,3 +2,5 @@ - # - # Makefile for nvmem layouts. - # -+ -+obj-$(CONFIG_NVMEM_LAYOUT_SL28_VPD) += sl28vpd.o ---- /dev/null -+++ b/drivers/nvmem/layouts/sl28vpd.c -@@ -0,0 +1,165 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SL28VPD_MAGIC 'V' -+ -+struct sl28vpd_header { -+ u8 magic; -+ u8 version; -+} __packed; -+ -+struct sl28vpd_v1 { -+ struct sl28vpd_header header; -+ char serial_number[15]; -+ u8 base_mac_address[ETH_ALEN]; -+ u8 crc8; -+} __packed; -+ -+static int sl28vpd_mac_address_pp(void *priv, const char *id, int index, -+ unsigned int offset, void *buf, -+ size_t bytes) -+{ -+ if (bytes != ETH_ALEN) -+ return -EINVAL; -+ -+ if (index < 0) -+ return -EINVAL; -+ -+ if (!is_valid_ether_addr(buf)) -+ return -EINVAL; -+ -+ eth_addr_add(buf, index); -+ -+ return 0; -+} -+ -+static const struct nvmem_cell_info sl28vpd_v1_entries[] = { -+ { -+ .name = "serial-number", -+ .offset = offsetof(struct sl28vpd_v1, serial_number), -+ .bytes = sizeof_field(struct sl28vpd_v1, serial_number), -+ }, -+ { -+ .name = "base-mac-address", -+ .offset = offsetof(struct sl28vpd_v1, base_mac_address), -+ .bytes = sizeof_field(struct sl28vpd_v1, base_mac_address), -+ .read_post_process = sl28vpd_mac_address_pp, -+ }, -+}; -+ -+static int sl28vpd_v1_check_crc(struct device *dev, struct nvmem_device *nvmem) -+{ -+ struct sl28vpd_v1 data_v1; -+ u8 table[CRC8_TABLE_SIZE]; -+ int ret; -+ u8 crc; -+ -+ crc8_populate_msb(table, 0x07); -+ -+ ret = nvmem_device_read(nvmem, 0, sizeof(data_v1), &data_v1); -+ if (ret < 0) -+ return ret; -+ else if (ret != sizeof(data_v1)) -+ return -EIO; -+ -+ crc = crc8(table, (void *)&data_v1, sizeof(data_v1) - 1, 0); -+ -+ if (crc != data_v1.crc8) { -+ dev_err(dev, -+ "Checksum is invalid (got %02x, expected %02x).\n", -+ crc, data_v1.crc8); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int sl28vpd_add_cells(struct device *dev, struct nvmem_device *nvmem, -+ struct nvmem_layout *layout) -+{ -+ const struct nvmem_cell_info *pinfo; -+ struct nvmem_cell_info info = {0}; -+ struct device_node *layout_np; -+ struct sl28vpd_header hdr; -+ int ret, i; -+ -+ /* check header */ -+ ret = nvmem_device_read(nvmem, 0, sizeof(hdr), &hdr); -+ if (ret < 0) -+ return ret; -+ else if (ret != sizeof(hdr)) -+ return -EIO; -+ -+ if (hdr.magic != SL28VPD_MAGIC) { -+ dev_err(dev, "Invalid magic value (%02x)\n", hdr.magic); -+ return -EINVAL; -+ } -+ -+ if (hdr.version != 1) { -+ dev_err(dev, "Version %d is unsupported.\n", hdr.version); -+ return -EINVAL; -+ } -+ -+ ret = sl28vpd_v1_check_crc(dev, nvmem); -+ if (ret) -+ return ret; -+ -+ layout_np = of_nvmem_layout_get_container(nvmem); -+ if (!layout_np) -+ return -ENOENT; -+ -+ for (i = 0; i < ARRAY_SIZE(sl28vpd_v1_entries); i++) { -+ pinfo = &sl28vpd_v1_entries[i]; -+ -+ info.name = pinfo->name; -+ info.offset = pinfo->offset; -+ info.bytes = pinfo->bytes; -+ info.read_post_process = pinfo->read_post_process; -+ info.np = of_get_child_by_name(layout_np, pinfo->name); -+ -+ ret = nvmem_add_one_cell(nvmem, &info); -+ if (ret) { -+ of_node_put(layout_np); -+ return ret; -+ } -+ } -+ -+ of_node_put(layout_np); -+ -+ return 0; -+} -+ -+static const struct of_device_id sl28vpd_of_match_table[] = { -+ { .compatible = "kontron,sl28-vpd" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, sl28vpd_of_match_table); -+ -+struct nvmem_layout sl28vpd_layout = { -+ .name = "sl28-vpd", -+ .of_match_table = sl28vpd_of_match_table, -+ .add_cells = sl28vpd_add_cells, -+}; -+ -+static int __init sl28vpd_init(void) -+{ -+ return nvmem_layout_register(&sl28vpd_layout); -+} -+ -+static void __exit sl28vpd_exit(void) -+{ -+ nvmem_layout_unregister(&sl28vpd_layout); -+} -+ -+module_init(sl28vpd_init); -+module_exit(sl28vpd_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Michael Walle "); -+MODULE_DESCRIPTION("NVMEM layout driver for the VPD of Kontron sl28 boards"); diff --git a/target/linux/generic/backport-5.10/814-v6.4-0011-nvmem-layouts-onie-tlv-Add-new-layout-driver.patch b/target/linux/generic/backport-5.10/814-v6.4-0011-nvmem-layouts-onie-tlv-Add-new-layout-driver.patch deleted file mode 100644 index ca8b4bc069..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0011-nvmem-layouts-onie-tlv-Add-new-layout-driver.patch +++ /dev/null @@ -1,306 +0,0 @@ -From d3c0d12f6474216bf386101e2449cc73e5c5b61d Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:31 +0100 -Subject: [PATCH] nvmem: layouts: onie-tlv: Add new layout driver - -This layout applies on top of any non volatile storage device containing -an ONIE table factory flashed. This table follows the tlv -(type-length-value) organization described in the link below. We cannot -afford using regular parsers because the content of these tables is -manufacturer specific and must be dynamically discovered. - -Link: https://opencomputeproject.github.io/onie/design-spec/hw_requirements.html -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-24-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/layouts/Kconfig | 9 ++ - drivers/nvmem/layouts/Makefile | 1 + - drivers/nvmem/layouts/onie-tlv.c | 257 +++++++++++++++++++++++++++++++ - 3 files changed, 267 insertions(+) - create mode 100644 drivers/nvmem/layouts/onie-tlv.c - ---- a/drivers/nvmem/layouts/Kconfig -+++ b/drivers/nvmem/layouts/Kconfig -@@ -11,4 +11,13 @@ config NVMEM_LAYOUT_SL28_VPD - - If unsure, say N. - -+config NVMEM_LAYOUT_ONIE_TLV -+ tristate "ONIE tlv support" -+ select CRC32 -+ help -+ Say Y here if you want to support the Open Compute Project ONIE -+ Type-Length-Value standard table. -+ -+ If unsure, say N. -+ - endmenu ---- a/drivers/nvmem/layouts/Makefile -+++ b/drivers/nvmem/layouts/Makefile -@@ -4,3 +4,4 @@ - # - - obj-$(CONFIG_NVMEM_LAYOUT_SL28_VPD) += sl28vpd.o -+obj-$(CONFIG_NVMEM_LAYOUT_ONIE_TLV) += onie-tlv.o ---- /dev/null -+++ b/drivers/nvmem/layouts/onie-tlv.c -@@ -0,0 +1,257 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * ONIE tlv NVMEM cells provider -+ * -+ * Copyright (C) 2022 Open Compute Group ONIE -+ * Author: Miquel Raynal -+ * Based on the nvmem driver written by: Vadym Kochan -+ * Inspired by the first layout written by: Rafał Miłecki -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define ONIE_TLV_MAX_LEN 2048 -+#define ONIE_TLV_CRC_FIELD_SZ 6 -+#define ONIE_TLV_CRC_SZ 4 -+#define ONIE_TLV_HDR_ID "TlvInfo" -+ -+struct onie_tlv_hdr { -+ u8 id[8]; -+ u8 version; -+ __be16 data_len; -+} __packed; -+ -+struct onie_tlv { -+ u8 type; -+ u8 len; -+} __packed; -+ -+static const char *onie_tlv_cell_name(u8 type) -+{ -+ switch (type) { -+ case 0x21: -+ return "product-name"; -+ case 0x22: -+ return "part-number"; -+ case 0x23: -+ return "serial-number"; -+ case 0x24: -+ return "mac-address"; -+ case 0x25: -+ return "manufacture-date"; -+ case 0x26: -+ return "device-version"; -+ case 0x27: -+ return "label-revision"; -+ case 0x28: -+ return "platform-name"; -+ case 0x29: -+ return "onie-version"; -+ case 0x2A: -+ return "num-macs"; -+ case 0x2B: -+ return "manufacturer"; -+ case 0x2C: -+ return "country-code"; -+ case 0x2D: -+ return "vendor"; -+ case 0x2E: -+ return "diag-version"; -+ case 0x2F: -+ return "service-tag"; -+ case 0xFD: -+ return "vendor-extension"; -+ case 0xFE: -+ return "crc32"; -+ default: -+ break; -+ } -+ -+ return NULL; -+} -+ -+static int onie_tlv_mac_read_cb(void *priv, const char *id, int index, -+ unsigned int offset, void *buf, -+ size_t bytes) -+{ -+ eth_addr_add(buf, index); -+ -+ return 0; -+} -+ -+static nvmem_cell_post_process_t onie_tlv_read_cb(u8 type, u8 *buf) -+{ -+ switch (type) { -+ case 0x24: -+ return &onie_tlv_mac_read_cb; -+ default: -+ break; -+ } -+ -+ return NULL; -+} -+ -+static int onie_tlv_add_cells(struct device *dev, struct nvmem_device *nvmem, -+ size_t data_len, u8 *data) -+{ -+ struct nvmem_cell_info cell = {}; -+ struct device_node *layout; -+ struct onie_tlv tlv; -+ unsigned int hdr_len = sizeof(struct onie_tlv_hdr); -+ unsigned int offset = 0; -+ int ret; -+ -+ layout = of_nvmem_layout_get_container(nvmem); -+ if (!layout) -+ return -ENOENT; -+ -+ while (offset < data_len) { -+ memcpy(&tlv, data + offset, sizeof(tlv)); -+ if (offset + tlv.len >= data_len) { -+ dev_err(dev, "Out of bounds field (0x%x bytes at 0x%x)\n", -+ tlv.len, hdr_len + offset); -+ break; -+ } -+ -+ cell.name = onie_tlv_cell_name(tlv.type); -+ if (!cell.name) -+ continue; -+ -+ cell.offset = hdr_len + offset + sizeof(tlv.type) + sizeof(tlv.len); -+ cell.bytes = tlv.len; -+ cell.np = of_get_child_by_name(layout, cell.name); -+ cell.read_post_process = onie_tlv_read_cb(tlv.type, data + offset + sizeof(tlv)); -+ -+ ret = nvmem_add_one_cell(nvmem, &cell); -+ if (ret) { -+ of_node_put(layout); -+ return ret; -+ } -+ -+ offset += sizeof(tlv) + tlv.len; -+ } -+ -+ of_node_put(layout); -+ -+ return 0; -+} -+ -+static bool onie_tlv_hdr_is_valid(struct device *dev, struct onie_tlv_hdr *hdr) -+{ -+ if (memcmp(hdr->id, ONIE_TLV_HDR_ID, sizeof(hdr->id))) { -+ dev_err(dev, "Invalid header\n"); -+ return false; -+ } -+ -+ if (hdr->version != 0x1) { -+ dev_err(dev, "Invalid version number\n"); -+ return false; -+ } -+ -+ return true; -+} -+ -+static bool onie_tlv_crc_is_valid(struct device *dev, size_t table_len, u8 *table) -+{ -+ struct onie_tlv crc_hdr; -+ u32 read_crc, calc_crc; -+ __be32 crc_be; -+ -+ memcpy(&crc_hdr, table + table_len - ONIE_TLV_CRC_FIELD_SZ, sizeof(crc_hdr)); -+ if (crc_hdr.type != 0xfe || crc_hdr.len != ONIE_TLV_CRC_SZ) { -+ dev_err(dev, "Invalid CRC field\n"); -+ return false; -+ } -+ -+ /* The table contains a JAMCRC, which is XOR'ed compared to the original -+ * CRC32 implementation as known in the Ethernet world. -+ */ -+ memcpy(&crc_be, table + table_len - ONIE_TLV_CRC_SZ, ONIE_TLV_CRC_SZ); -+ read_crc = be32_to_cpu(crc_be); -+ calc_crc = crc32(~0, table, table_len - ONIE_TLV_CRC_SZ) ^ 0xFFFFFFFF; -+ if (read_crc != calc_crc) { -+ dev_err(dev, "Invalid CRC read: 0x%08x, expected: 0x%08x\n", -+ read_crc, calc_crc); -+ return false; -+ } -+ -+ return true; -+} -+ -+static int onie_tlv_parse_table(struct device *dev, struct nvmem_device *nvmem, -+ struct nvmem_layout *layout) -+{ -+ struct onie_tlv_hdr hdr; -+ size_t table_len, data_len, hdr_len; -+ u8 *table, *data; -+ int ret; -+ -+ ret = nvmem_device_read(nvmem, 0, sizeof(hdr), &hdr); -+ if (ret < 0) -+ return ret; -+ -+ if (!onie_tlv_hdr_is_valid(dev, &hdr)) { -+ dev_err(dev, "Invalid ONIE TLV header\n"); -+ return -EINVAL; -+ } -+ -+ hdr_len = sizeof(hdr.id) + sizeof(hdr.version) + sizeof(hdr.data_len); -+ data_len = be16_to_cpu(hdr.data_len); -+ table_len = hdr_len + data_len; -+ if (table_len > ONIE_TLV_MAX_LEN) { -+ dev_err(dev, "Invalid ONIE TLV data length\n"); -+ return -EINVAL; -+ } -+ -+ table = devm_kmalloc(dev, table_len, GFP_KERNEL); -+ if (!table) -+ return -ENOMEM; -+ -+ ret = nvmem_device_read(nvmem, 0, table_len, table); -+ if (ret != table_len) -+ return ret; -+ -+ if (!onie_tlv_crc_is_valid(dev, table_len, table)) -+ return -EINVAL; -+ -+ data = table + hdr_len; -+ ret = onie_tlv_add_cells(dev, nvmem, data_len, data); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static const struct of_device_id onie_tlv_of_match_table[] = { -+ { .compatible = "onie,tlv-layout", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, onie_tlv_of_match_table); -+ -+static struct nvmem_layout onie_tlv_layout = { -+ .name = "ONIE tlv layout", -+ .of_match_table = onie_tlv_of_match_table, -+ .add_cells = onie_tlv_parse_table, -+}; -+ -+static int __init onie_tlv_init(void) -+{ -+ return nvmem_layout_register(&onie_tlv_layout); -+} -+ -+static void __exit onie_tlv_exit(void) -+{ -+ nvmem_layout_unregister(&onie_tlv_layout); -+} -+ -+module_init(onie_tlv_init); -+module_exit(onie_tlv_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Miquel Raynal "); -+MODULE_DESCRIPTION("NVMEM layout driver for Onie TLV table parsing"); -+MODULE_ALIAS("NVMEM layout driver for Onie TLV table parsing"); diff --git a/target/linux/generic/backport-5.10/814-v6.4-0012-nvmem-stm32-romem-mark-OF-related-data-as-maybe-unus.patch b/target/linux/generic/backport-5.10/814-v6.4-0012-nvmem-stm32-romem-mark-OF-related-data-as-maybe-unus.patch deleted file mode 100644 index 94a0911d73..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0012-nvmem-stm32-romem-mark-OF-related-data-as-maybe-unus.patch +++ /dev/null @@ -1,32 +0,0 @@ -From a4fb434ef96ace5af758ca2c52c3a3f8f3abc87c Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Tue, 4 Apr 2023 18:21:34 +0100 -Subject: [PATCH] nvmem: stm32-romem: mark OF related data as maybe unused -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The driver can be compile tested with !CONFIG_OF making certain data -unused: - - drivers/nvmem/stm32-romem.c:271:34: error: ‘stm32_romem_of_match’ defined but not used [-Werror=unused-const-variable=] - -Signed-off-by: Krzysztof Kozlowski -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-27-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/stm32-romem.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/stm32-romem.c -+++ b/drivers/nvmem/stm32-romem.c -@@ -268,7 +268,7 @@ static const struct stm32_romem_cfg stm3 - .ta = true, - }; - --static const struct of_device_id stm32_romem_of_match[] = { -+static const struct of_device_id stm32_romem_of_match[] __maybe_unused = { - { .compatible = "st,stm32f4-otp", }, { - .compatible = "st,stm32mp15-bsec", - .data = (void *)&stm32mp15_bsec_cfg, diff --git a/target/linux/generic/backport-5.10/814-v6.4-0013-nvmem-mtk-efuse-Support-postprocessing-for-GPU-speed.patch b/target/linux/generic/backport-5.10/814-v6.4-0013-nvmem-mtk-efuse-Support-postprocessing-for-GPU-speed.patch deleted file mode 100644 index abda402bdd..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0013-nvmem-mtk-efuse-Support-postprocessing-for-GPU-speed.patch +++ /dev/null @@ -1,120 +0,0 @@ -From de6e05097f7db066afb0ad4c88b730949f7b7749 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Tue, 4 Apr 2023 18:21:35 +0100 -Subject: [PATCH] nvmem: mtk-efuse: Support postprocessing for GPU speed - binning data - -On some MediaTek SoCs GPU speed binning data is available for read -in the SoC's eFuse array but it has a format that is incompatible -with what the OPP API expects, as we read a number from 0 to 7 but -opp-supported-hw is expecting a bitmask to enable an OPP entry: -being what we read limited to 0-7, it's straightforward to simply -convert the value to BIT(value) as a post-processing action. - -So, introduce post-processing support and enable it by evaluating -the newly introduced platform data's `uses_post_processing` member, -currently enabled only for MT8186. - -Signed-off-by: AngeloGioacchino Del Regno -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-28-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/mtk-efuse.c | 53 +++++++++++++++++++++++++++++++++++++-- - 1 file changed, 51 insertions(+), 2 deletions(-) - ---- a/drivers/nvmem/mtk-efuse.c -+++ b/drivers/nvmem/mtk-efuse.c -@@ -10,6 +10,11 @@ - #include - #include - #include -+#include -+ -+struct mtk_efuse_pdata { -+ bool uses_post_processing; -+}; - - struct mtk_efuse_priv { - void __iomem *base; -@@ -29,6 +34,37 @@ static int mtk_reg_read(void *context, - return 0; - } - -+static int mtk_efuse_gpu_speedbin_pp(void *context, const char *id, int index, -+ unsigned int offset, void *data, size_t bytes) -+{ -+ u8 *val = data; -+ -+ if (val[0] < 8) -+ val[0] = BIT(val[0]); -+ -+ return 0; -+} -+ -+static void mtk_efuse_fixup_cell_info(struct nvmem_device *nvmem, -+ struct nvmem_layout *layout, -+ struct nvmem_cell_info *cell) -+{ -+ size_t sz = strlen(cell->name); -+ -+ /* -+ * On some SoCs, the GPU speedbin is not read as bitmask but as -+ * a number with range [0-7] (max 3 bits): post process to use -+ * it in OPP tables to describe supported-hw. -+ */ -+ if (cell->nbits <= 3 && -+ strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0) -+ cell->read_post_process = mtk_efuse_gpu_speedbin_pp; -+} -+ -+static struct nvmem_layout mtk_efuse_layout = { -+ .fixup_cell_info = mtk_efuse_fixup_cell_info, -+}; -+ - static int mtk_efuse_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -@@ -36,6 +72,7 @@ static int mtk_efuse_probe(struct platfo - struct nvmem_device *nvmem; - struct nvmem_config econfig = {}; - struct mtk_efuse_priv *priv; -+ const struct mtk_efuse_pdata *pdata; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) -@@ -45,20 +82,32 @@ static int mtk_efuse_probe(struct platfo - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - -+ pdata = device_get_match_data(dev); - econfig.stride = 1; - econfig.word_size = 1; - econfig.reg_read = mtk_reg_read; - econfig.size = resource_size(res); - econfig.priv = priv; - econfig.dev = dev; -+ if (pdata->uses_post_processing) -+ econfig.layout = &mtk_efuse_layout; - nvmem = devm_nvmem_register(dev, &econfig); - - return PTR_ERR_OR_ZERO(nvmem); - } - -+static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = { -+ .uses_post_processing = true, -+}; -+ -+static const struct mtk_efuse_pdata mtk_efuse_pdata = { -+ .uses_post_processing = false, -+}; -+ - static const struct of_device_id mtk_efuse_of_match[] = { -- { .compatible = "mediatek,mt8173-efuse",}, -- { .compatible = "mediatek,efuse",}, -+ { .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata }, -+ { .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata }, -+ { .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata }, - {/* sentinel */}, - }; - MODULE_DEVICE_TABLE(of, mtk_efuse_of_match); diff --git a/target/linux/generic/backport-5.10/814-v6.4-0014-nvmem-bcm-ocotp-Use-devm_platform_ioremap_resource.patch b/target/linux/generic/backport-5.10/814-v6.4-0014-nvmem-bcm-ocotp-Use-devm_platform_ioremap_resource.patch deleted file mode 100644 index a0874f73d1..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0014-nvmem-bcm-ocotp-Use-devm_platform_ioremap_resource.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 1dc552fa33cf98af3e784dbc0500da93cae3b24a Mon Sep 17 00:00:00 2001 -From: Yang Li -Date: Tue, 4 Apr 2023 18:21:38 +0100 -Subject: [PATCH] nvmem: bcm-ocotp: Use devm_platform_ioremap_resource() - -According to commit 7945f929f1a7 ("drivers: provide -devm_platform_ioremap_resource()"), convert platform_get_resource(), -devm_ioremap_resource() to a single call to use -devm_platform_ioremap_resource(), as this is exactly what this function -does. - -Signed-off-by: Yang Li -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-31-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/bcm-ocotp.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/nvmem/bcm-ocotp.c -+++ b/drivers/nvmem/bcm-ocotp.c -@@ -254,7 +254,6 @@ MODULE_DEVICE_TABLE(acpi, bcm_otpc_acpi_ - static int bcm_otpc_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -- struct resource *res; - struct otpc_priv *priv; - struct nvmem_device *nvmem; - int err; -@@ -269,8 +268,7 @@ static int bcm_otpc_probe(struct platfor - return -ENODEV; - - /* Get OTP base address register. */ -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- priv->base = devm_ioremap_resource(dev, res); -+ priv->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) { - dev_err(dev, "unable to map I/O memory\n"); - return PTR_ERR(priv->base); diff --git a/target/linux/generic/backport-5.10/814-v6.4-0015-nvmem-nintendo-otp-Use-devm_platform_ioremap_resourc.patch b/target/linux/generic/backport-5.10/814-v6.4-0015-nvmem-nintendo-otp-Use-devm_platform_ioremap_resourc.patch deleted file mode 100644 index 890dacd08d..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0015-nvmem-nintendo-otp-Use-devm_platform_ioremap_resourc.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 649409990d2e93fac657be7c6960c28a2c601d65 Mon Sep 17 00:00:00 2001 -From: Yang Li -Date: Tue, 4 Apr 2023 18:21:39 +0100 -Subject: [PATCH] nvmem: nintendo-otp: Use devm_platform_ioremap_resource() - -According to commit 7945f929f1a7 ("drivers: provide -devm_platform_ioremap_resource()"), convert platform_get_resource(), -devm_ioremap_resource() to a single call to use -devm_platform_ioremap_resource(), as this is exactly what this function -does. - -Signed-off-by: Yang Li -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-32-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/nintendo-otp.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/nvmem/nintendo-otp.c -+++ b/drivers/nvmem/nintendo-otp.c -@@ -76,7 +76,6 @@ static int nintendo_otp_probe(struct pla - struct device *dev = &pdev->dev; - const struct of_device_id *of_id = - of_match_device(nintendo_otp_of_table, dev); -- struct resource *res; - struct nvmem_device *nvmem; - struct nintendo_otp_priv *priv; - -@@ -92,8 +91,7 @@ static int nintendo_otp_probe(struct pla - if (!priv) - return -ENOMEM; - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- priv->regs = devm_ioremap_resource(dev, res); -+ priv->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->regs)) - return PTR_ERR(priv->regs); - diff --git a/target/linux/generic/backport-5.10/814-v6.4-0016-nvmem-vf610-ocotp-Use-devm_platform_get_and_ioremap_.patch b/target/linux/generic/backport-5.10/814-v6.4-0016-nvmem-vf610-ocotp-Use-devm_platform_get_and_ioremap_.patch deleted file mode 100644 index 3f5d3c1ad4..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0016-nvmem-vf610-ocotp-Use-devm_platform_get_and_ioremap_.patch +++ /dev/null @@ -1,32 +0,0 @@ -From c2367aa60d5e34d48582362c6de34b4131d92be7 Mon Sep 17 00:00:00 2001 -From: Yang Li -Date: Tue, 4 Apr 2023 18:21:40 +0100 -Subject: [PATCH] nvmem: vf610-ocotp: Use - devm_platform_get_and_ioremap_resource() - -According to commit 890cc39a8799 ("drivers: provide -devm_platform_get_and_ioremap_resource()"), convert -platform_get_resource(), devm_ioremap_resource() to a single -call to devm_platform_get_and_ioremap_resource(), as this is exactly -what this function does. - -Signed-off-by: Yang Li -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-33-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/vf610-ocotp.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/nvmem/vf610-ocotp.c -+++ b/drivers/nvmem/vf610-ocotp.c -@@ -219,8 +219,7 @@ static int vf610_ocotp_probe(struct plat - if (!ocotp_dev) - return -ENOMEM; - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- ocotp_dev->base = devm_ioremap_resource(dev, res); -+ ocotp_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(ocotp_dev->base)) - return PTR_ERR(ocotp_dev->base); - diff --git a/target/linux/generic/backport-5.10/814-v6.4-0017-nvmem-core-support-specifying-both-cell-raw-data-pos.patch b/target/linux/generic/backport-5.10/814-v6.4-0017-nvmem-core-support-specifying-both-cell-raw-data-pos.patch deleted file mode 100644 index eeb407e9bb..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0017-nvmem-core-support-specifying-both-cell-raw-data-pos.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 55d4980ce55b6bb4be66877de4dbec513911b988 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 4 Apr 2023 18:21:42 +0100 -Subject: [PATCH] nvmem: core: support specifying both: cell raw data & post - read lengths -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Callback .read_post_process() is designed to modify raw cell content -before providing it to the consumer. So far we were dealing with -modifications that didn't affect cell size (length). In some cases -however cell content needs to be reformatted and resized. - -It's required e.g. to provide properly formatted MAC address in case -it's stored in a non-binary format (e.g. using ASCII). - -There were few discussions how to optimally handle that. Following -possible solutions were considered: -1. Allow .read_post_process() to realloc (resize) content buffer -2. Allow .read_post_process() to adjust (decrease) just buffer length -3. Register NVMEM cells using post-read sizes - -The preferred solution was the last one. The problem is that simply -adjusting "bytes" in NVMEM providers would result in core code NOT -passing whole raw data to .read_post_process() callbacks. It means -callback functions couldn't do their job without somehow manually -reading original cell content on their own. - -This patch deals with that by registering NVMEM cells with both lengths: -raw content one and post read one. It allows: -1. Core code to read whole raw cell content -2. Callbacks to return content they want - -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-35-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/core.c | 11 +++++++---- - include/linux/nvmem-provider.h | 2 ++ - 2 files changed, 9 insertions(+), 4 deletions(-) - ---- a/drivers/nvmem/core.c -+++ b/drivers/nvmem/core.c -@@ -50,6 +50,7 @@ struct nvmem_device { - struct nvmem_cell_entry { - const char *name; - int offset; -+ size_t raw_len; - int bytes; - int bit_offset; - int nbits; -@@ -469,6 +470,7 @@ static int nvmem_cell_info_to_nvmem_cell - { - cell->nvmem = nvmem; - cell->offset = info->offset; -+ cell->raw_len = info->raw_len ?: info->bytes; - cell->bytes = info->bytes; - cell->name = info->name; - cell->read_post_process = info->read_post_process; -@@ -1560,7 +1562,7 @@ static int __nvmem_cell_read(struct nvme - { - int rc; - -- rc = nvmem_reg_read(nvmem, cell->offset, buf, cell->bytes); -+ rc = nvmem_reg_read(nvmem, cell->offset, buf, cell->raw_len); - - if (rc) - return rc; -@@ -1571,7 +1573,7 @@ static int __nvmem_cell_read(struct nvme - - if (cell->read_post_process) { - rc = cell->read_post_process(cell->priv, id, index, -- cell->offset, buf, cell->bytes); -+ cell->offset, buf, cell->raw_len); - if (rc) - return rc; - } -@@ -1594,14 +1596,15 @@ static int __nvmem_cell_read(struct nvme - */ - void *nvmem_cell_read(struct nvmem_cell *cell, size_t *len) - { -- struct nvmem_device *nvmem = cell->entry->nvmem; -+ struct nvmem_cell_entry *entry = cell->entry; -+ struct nvmem_device *nvmem = entry->nvmem; - u8 *buf; - int rc; - - if (!nvmem) - return ERR_PTR(-EINVAL); - -- buf = kzalloc(cell->entry->bytes, GFP_KERNEL); -+ buf = kzalloc(max_t(size_t, entry->raw_len, entry->bytes), GFP_KERNEL); - if (!buf) - return ERR_PTR(-ENOMEM); - ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -51,6 +51,7 @@ struct nvmem_keepout { - * struct nvmem_cell_info - NVMEM cell description - * @name: Name. - * @offset: Offset within the NVMEM device. -+ * @raw_len: Length of raw data (without post processing). - * @bytes: Length of the cell. - * @bit_offset: Bit offset if cell is smaller than a byte. - * @nbits: Number of bits. -@@ -62,6 +63,7 @@ struct nvmem_keepout { - struct nvmem_cell_info { - const char *name; - unsigned int offset; -+ size_t raw_len; - unsigned int bytes; - unsigned int bit_offset; - unsigned int nbits; diff --git a/target/linux/generic/backport-5.10/814-v6.4-0018-nvmem-u-boot-env-post-process-ethaddr-env-variable.patch b/target/linux/generic/backport-5.10/814-v6.4-0018-nvmem-u-boot-env-post-process-ethaddr-env-variable.patch deleted file mode 100644 index adde0ffc4b..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0018-nvmem-u-boot-env-post-process-ethaddr-env-variable.patch +++ /dev/null @@ -1,81 +0,0 @@ -From c49f1a8af6bcf6d18576bca898f8083ca4b129e1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 4 Apr 2023 18:21:43 +0100 -Subject: [PATCH] nvmem: u-boot-env: post-process "ethaddr" env variable -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -U-Boot environment variables are stored in ASCII format so "ethaddr" -requires parsing into binary to make it work with Ethernet interfaces. - -This includes support for indexes to support #nvmem-cell-cells = <1>. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-36-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/Kconfig | 1 + - drivers/nvmem/u-boot-env.c | 26 ++++++++++++++++++++++++++ - 2 files changed, 27 insertions(+) - ---- a/drivers/nvmem/Kconfig -+++ b/drivers/nvmem/Kconfig -@@ -340,6 +340,7 @@ config NVMEM_U_BOOT_ENV - tristate "U-Boot environment variables support" - depends on OF && MTD - select CRC32 -+ select GENERIC_NET_UTILS - help - U-Boot stores its setup as environment variables. This driver adds - support for verifying & exporting such data. It also exposes variables ---- a/drivers/nvmem/u-boot-env.c -+++ b/drivers/nvmem/u-boot-env.c -@@ -4,6 +4,8 @@ - */ - - #include -+#include -+#include - #include - #include - #include -@@ -70,6 +72,25 @@ static int u_boot_env_read(void *context - return 0; - } - -+static int u_boot_env_read_post_process_ethaddr(void *context, const char *id, int index, -+ unsigned int offset, void *buf, size_t bytes) -+{ -+ u8 mac[ETH_ALEN]; -+ -+ if (bytes != 3 * ETH_ALEN - 1) -+ return -EINVAL; -+ -+ if (!mac_pton(buf, mac)) -+ return -EINVAL; -+ -+ if (index) -+ eth_addr_add(mac, index); -+ -+ ether_addr_copy(buf, mac); -+ -+ return 0; -+} -+ - static int u_boot_env_add_cells(struct u_boot_env *priv, uint8_t *buf, - size_t data_offset, size_t data_len) - { -@@ -101,6 +122,11 @@ static int u_boot_env_add_cells(struct u - priv->cells[idx].offset = data_offset + value - data; - priv->cells[idx].bytes = strlen(value); - priv->cells[idx].np = of_get_child_by_name(dev->of_node, priv->cells[idx].name); -+ if (!strcmp(var, "ethaddr")) { -+ priv->cells[idx].raw_len = strlen(value); -+ priv->cells[idx].bytes = ETH_ALEN; -+ priv->cells[idx].read_post_process = u_boot_env_read_post_process_ethaddr; -+ } - } - - if (WARN_ON(idx != priv->ncells)) diff --git a/target/linux/generic/backport-5.10/814-v6.4-0019-nvmem-Add-macro-to-register-nvmem-layout-drivers.patch b/target/linux/generic/backport-5.10/814-v6.4-0019-nvmem-Add-macro-to-register-nvmem-layout-drivers.patch deleted file mode 100644 index 7c6fe22b5f..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0019-nvmem-Add-macro-to-register-nvmem-layout-drivers.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 814c978f02db17f16e6aa2efa2a929372f06da09 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:44 +0100 -Subject: [PATCH] nvmem: Add macro to register nvmem layout drivers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Provide a module_nvmem_layout_driver() macro at the end of the -nvmem-provider.h header to reduce the boilerplate when registering nvmem -layout drivers. - -Suggested-by: Srinivas Kandagatla -Signed-off-by: Miquel Raynal -Acked-by: Rafał Miłecki -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-37-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - include/linux/nvmem-provider.h | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/include/linux/nvmem-provider.h -+++ b/include/linux/nvmem-provider.h -@@ -9,6 +9,7 @@ - #ifndef _LINUX_NVMEM_PROVIDER_H - #define _LINUX_NVMEM_PROVIDER_H - -+#include - #include - #include - #include -@@ -242,4 +243,9 @@ nvmem_layout_get_match_data(struct nvmem - } - - #endif /* CONFIG_NVMEM */ -+ -+#define module_nvmem_layout_driver(__layout_driver) \ -+ module_driver(__layout_driver, nvmem_layout_register, \ -+ nvmem_layout_unregister) -+ - #endif /* ifndef _LINUX_NVMEM_PROVIDER_H */ diff --git a/target/linux/generic/backport-5.10/814-v6.4-0020-nvmem-layouts-sl28vpd-Use-module_nvmem_layout_driver.patch b/target/linux/generic/backport-5.10/814-v6.4-0020-nvmem-layouts-sl28vpd-Use-module_nvmem_layout_driver.patch deleted file mode 100644 index 06646dd68b..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0020-nvmem-layouts-sl28vpd-Use-module_nvmem_layout_driver.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0abdf99fe0c86252ba274703425f8d543d7e7f0d Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:45 +0100 -Subject: [PATCH] nvmem: layouts: sl28vpd: Use module_nvmem_layout_driver() - -Stop open-coding the module init/exit functions. Use the -module_nvmem_layout_driver() instead. - -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-38-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/layouts/sl28vpd.c | 14 +------------- - 1 file changed, 1 insertion(+), 13 deletions(-) - ---- a/drivers/nvmem/layouts/sl28vpd.c -+++ b/drivers/nvmem/layouts/sl28vpd.c -@@ -146,19 +146,7 @@ struct nvmem_layout sl28vpd_layout = { - .of_match_table = sl28vpd_of_match_table, - .add_cells = sl28vpd_add_cells, - }; -- --static int __init sl28vpd_init(void) --{ -- return nvmem_layout_register(&sl28vpd_layout); --} -- --static void __exit sl28vpd_exit(void) --{ -- nvmem_layout_unregister(&sl28vpd_layout); --} -- --module_init(sl28vpd_init); --module_exit(sl28vpd_exit); -+module_nvmem_layout_driver(sl28vpd_layout); - - MODULE_LICENSE("GPL"); - MODULE_AUTHOR("Michael Walle "); diff --git a/target/linux/generic/backport-5.10/814-v6.4-0021-nvmem-layouts-onie-tlv-Use-module_nvmem_layout_drive.patch b/target/linux/generic/backport-5.10/814-v6.4-0021-nvmem-layouts-onie-tlv-Use-module_nvmem_layout_drive.patch deleted file mode 100644 index 826f4378c2..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0021-nvmem-layouts-onie-tlv-Use-module_nvmem_layout_drive.patch +++ /dev/null @@ -1,39 +0,0 @@ -From d119eb38faab61125aaa4f63c74eef61585cf34c Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:46 +0100 -Subject: [PATCH] nvmem: layouts: onie-tlv: Use module_nvmem_layout_driver() - -Stop open-coding the module init/exit functions. Use the -module_nvmem_layout_driver() instead. - -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-39-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/layouts/onie-tlv.c | 14 +------------- - 1 file changed, 1 insertion(+), 13 deletions(-) - ---- a/drivers/nvmem/layouts/onie-tlv.c -+++ b/drivers/nvmem/layouts/onie-tlv.c -@@ -237,19 +237,7 @@ static struct nvmem_layout onie_tlv_layo - .of_match_table = onie_tlv_of_match_table, - .add_cells = onie_tlv_parse_table, - }; -- --static int __init onie_tlv_init(void) --{ -- return nvmem_layout_register(&onie_tlv_layout); --} -- --static void __exit onie_tlv_exit(void) --{ -- nvmem_layout_unregister(&onie_tlv_layout); --} -- --module_init(onie_tlv_init); --module_exit(onie_tlv_exit); -+module_nvmem_layout_driver(onie_tlv_layout); - - MODULE_LICENSE("GPL"); - MODULE_AUTHOR("Miquel Raynal "); diff --git a/target/linux/generic/backport-5.10/814-v6.4-0022-nvmem-layouts-onie-tlv-Drop-wrong-module-alias.patch b/target/linux/generic/backport-5.10/814-v6.4-0022-nvmem-layouts-onie-tlv-Drop-wrong-module-alias.patch deleted file mode 100644 index f20db85ceb..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0022-nvmem-layouts-onie-tlv-Drop-wrong-module-alias.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 6b13e4b6a9a45028ac730e550380077df1845912 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:47 +0100 -Subject: [PATCH] nvmem: layouts: onie-tlv: Drop wrong module alias - -The MODULE_ALIAS macro is misused here as it carries the -description. There is currently no relevant alias to provide so let's -just drop it. - -Signed-off-by: Miquel Raynal -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-40-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/layouts/onie-tlv.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/nvmem/layouts/onie-tlv.c -+++ b/drivers/nvmem/layouts/onie-tlv.c -@@ -242,4 +242,3 @@ module_nvmem_layout_driver(onie_tlv_layo - MODULE_LICENSE("GPL"); - MODULE_AUTHOR("Miquel Raynal "); - MODULE_DESCRIPTION("NVMEM layout driver for Onie TLV table parsing"); --MODULE_ALIAS("NVMEM layout driver for Onie TLV table parsing"); diff --git a/target/linux/generic/backport-5.10/814-v6.4-0023-nvmem-layouts-sl28vpd-set-varaiable-sl28vpd_layout-s.patch b/target/linux/generic/backport-5.10/814-v6.4-0023-nvmem-layouts-sl28vpd-set-varaiable-sl28vpd_layout-s.patch deleted file mode 100644 index 5cf847b57a..0000000000 --- a/target/linux/generic/backport-5.10/814-v6.4-0023-nvmem-layouts-sl28vpd-set-varaiable-sl28vpd_layout-s.patch +++ /dev/null @@ -1,31 +0,0 @@ -From a8642cd11635a35a5f1dc31857887900d6610778 Mon Sep 17 00:00:00 2001 -From: Tom Rix -Date: Tue, 4 Apr 2023 18:21:48 +0100 -Subject: [PATCH] nvmem: layouts: sl28vpd: set varaiable sl28vpd_layout - storage-class-specifier to static - -smatch reports -drivers/nvmem/layouts/sl28vpd.c:144:21: warning: symbol - 'sl28vpd_layout' was not declared. Should it be static? - -This variable is only used in one file so it should be static. - -Signed-off-by: Tom Rix -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-41-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/nvmem/layouts/sl28vpd.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/layouts/sl28vpd.c -+++ b/drivers/nvmem/layouts/sl28vpd.c -@@ -141,7 +141,7 @@ static const struct of_device_id sl28vpd - }; - MODULE_DEVICE_TABLE(of, sl28vpd_of_match_table); - --struct nvmem_layout sl28vpd_layout = { -+static struct nvmem_layout sl28vpd_layout = { - .name = "sl28-vpd", - .of_match_table = sl28vpd_of_match_table, - .add_cells = sl28vpd_add_cells, diff --git a/target/linux/generic/backport-5.10/818-v5.13-usb-ehci-add-spurious-flag-to-disable-overcurrent-ch.patch b/target/linux/generic/backport-5.10/818-v5.13-usb-ehci-add-spurious-flag-to-disable-overcurrent-ch.patch deleted file mode 100644 index 6b75b08717..0000000000 --- a/target/linux/generic/backport-5.10/818-v5.13-usb-ehci-add-spurious-flag-to-disable-overcurrent-ch.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 2d5ba37461013253d2ff0a3641b727fd32ea97a9 Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Tue, 23 Feb 2021 18:44:53 +0100 -Subject: [PATCH 1/3] usb: ehci: add spurious flag to disable overcurrent - checking -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This patch adds an ignore_oc flag which can be set by EHCI controller -not supporting or wanting to disable overcurrent checking. The EHCI -platform data in include/linux/usb/ehci_pdriver.h is also augmented to -take advantage of this new flag. - -Signed-off-by: Florian Fainelli -Signed-off-by: Álvaro Fernández Rojas -Link: https://lore.kernel.org/r/20210223174455.1378-2-noltari@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/usb/host/ehci-hcd.c | 2 +- - drivers/usb/host/ehci-hub.c | 4 ++-- - drivers/usb/host/ehci-platform.c | 2 ++ - drivers/usb/host/ehci.h | 1 + - include/linux/usb/ehci_pdriver.h | 1 + - 5 files changed, 7 insertions(+), 3 deletions(-) - ---- a/drivers/usb/host/ehci-hcd.c -+++ b/drivers/usb/host/ehci-hcd.c -@@ -660,7 +660,7 @@ static int ehci_run (struct usb_hcd *hcd - "USB %x.%x started, EHCI %x.%02x%s\n", - ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), - temp >> 8, temp & 0xff, -- ignore_oc ? ", overcurrent ignored" : ""); -+ (ignore_oc || ehci->spurious_oc) ? ", overcurrent ignored" : ""); - - ehci_writel(ehci, INTR_MASK, - &ehci->regs->intr_enable); /* Turn On Interrupts */ ---- a/drivers/usb/host/ehci-hub.c -+++ b/drivers/usb/host/ehci-hub.c -@@ -643,7 +643,7 @@ ehci_hub_status_data (struct usb_hcd *hc - * always set, seem to clear PORT_OCC and PORT_CSC when writing to - * PORT_POWER; that's surprising, but maybe within-spec. - */ -- if (!ignore_oc) -+ if (!ignore_oc && !ehci->spurious_oc) - mask = PORT_CSC | PORT_PEC | PORT_OCC; - else - mask = PORT_CSC | PORT_PEC; -@@ -1013,7 +1013,7 @@ int ehci_hub_control( - if (temp & PORT_PEC) - status |= USB_PORT_STAT_C_ENABLE << 16; - -- if ((temp & PORT_OCC) && !ignore_oc){ -+ if ((temp & PORT_OCC) && (!ignore_oc && !ehci->spurious_oc)){ - status |= USB_PORT_STAT_C_OVERCURRENT << 16; - - /* ---- a/drivers/usb/host/ehci-platform.c -+++ b/drivers/usb/host/ehci-platform.c -@@ -333,6 +333,8 @@ static int ehci_platform_probe(struct pl - hcd->has_tt = 1; - if (pdata->reset_on_resume) - priv->reset_on_resume = true; -+ if (pdata->spurious_oc) -+ ehci->spurious_oc = 1; - - #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO - if (ehci->big_endian_mmio) { ---- a/drivers/usb/host/ehci.h -+++ b/drivers/usb/host/ehci.h -@@ -219,6 +219,7 @@ struct ehci_hcd { /* one per controlle - unsigned need_oc_pp_cycle:1; /* MPC834X port power */ - unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ - unsigned is_aspeed:1; -+ unsigned spurious_oc:1; - - /* required for usb32 quirk */ - #define OHCI_CTRL_HCFS (3 << 6) ---- a/include/linux/usb/ehci_pdriver.h -+++ b/include/linux/usb/ehci_pdriver.h -@@ -50,6 +50,7 @@ struct usb_ehci_pdata { - unsigned no_io_watchdog:1; - unsigned reset_on_resume:1; - unsigned dma_mask_64:1; -+ unsigned spurious_oc:1; - - /* Turn on all power and clocks */ - int (*power_on)(struct platform_device *pdev); diff --git a/target/linux/generic/backport-5.10/819-v5.13-usb-host-ehci-platform-add-spurious_oc-DT-support.patch b/target/linux/generic/backport-5.10/819-v5.13-usb-host-ehci-platform-add-spurious_oc-DT-support.patch deleted file mode 100644 index 0094d47718..0000000000 --- a/target/linux/generic/backport-5.10/819-v5.13-usb-host-ehci-platform-add-spurious_oc-DT-support.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 4da57dbbffdfa7fe4e2b70b047fc5ff95ff25a3d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Tue, 23 Feb 2021 18:44:55 +0100 -Subject: [PATCH 3/3] usb: host: ehci-platform: add spurious_oc DT support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Over-current reporting isn't supported on some platforms such as bcm63xx. -These devices will incorrectly report over-current if this flag isn't properly -activated. - -Signed-off-by: Álvaro Fernández Rojas -Link: https://lore.kernel.org/r/20210223174455.1378-4-noltari@gmail.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/usb/host/ehci-platform.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/usb/host/ehci-platform.c -+++ b/drivers/usb/host/ehci-platform.c -@@ -286,6 +286,9 @@ static int ehci_platform_probe(struct pl - if (of_property_read_bool(dev->dev.of_node, "big-endian")) - ehci->big_endian_mmio = ehci->big_endian_desc = 1; - -+ if (of_property_read_bool(dev->dev.of_node, "spurious-oc")) -+ ehci->spurious_oc = 1; -+ - if (of_property_read_bool(dev->dev.of_node, - "needs-reset-on-resume")) - priv->reset_on_resume = true; diff --git a/target/linux/generic/backport-5.10/820-v5.13-make-pci_host_common_probe-declare-its-reliance-on-msi-domains.patch b/target/linux/generic/backport-5.10/820-v5.13-make-pci_host_common_probe-declare-its-reliance-on-msi-domains.patch deleted file mode 100644 index 8ca2b78f74..0000000000 --- a/target/linux/generic/backport-5.10/820-v5.13-make-pci_host_common_probe-declare-its-reliance-on-msi-domains.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 9ec37efb87832b578d7972fc80b04d94f5d2bbe3 Mon Sep 17 00:00:00 2001 -From: Marc Zyngier -Date: Tue, 30 Mar 2021 16:11:42 +0100 -Subject: PCI/MSI: Make pci_host_common_probe() declare its reliance on MSI - domains - -The generic PCI host driver relies on MSI domains for MSIs to -be provided to its end-points. Make this dependency explicit. - -This cures the warnings occuring on arm/arm64 VMs when booted -with PCI virtio devices and no MSI controller (no GICv3 ITS, -for example). - -It is likely that other drivers will need to express the same -dependency. - -Link: https://lore.kernel.org/r/20210330151145.997953-12-maz@kernel.org -Signed-off-by: Marc Zyngier -Signed-off-by: Lorenzo Pieralisi -Acked-by: Bjorn Helgaas ---- - drivers/pci/controller/pci-host-common.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/pci/controller/pci-host-common.c -+++ b/drivers/pci/controller/pci-host-common.c -@@ -77,6 +77,7 @@ int pci_host_common_probe(struct platfor - - bridge->sysdata = cfg; - bridge->ops = (struct pci_ops *)&ops->pci_ops; -+ bridge->msi_domain = true; - - platform_set_drvdata(pdev, bridge); - diff --git a/target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch b/target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch deleted file mode 100644 index ee1acf4b9c..0000000000 --- a/target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 94e89b145371b68fa0ea294855adebcd03e0522e Mon Sep 17 00:00:00 2001 -From: Marc Zyngier -Date: Tue, 30 Mar 2021 16:11:41 +0100 -Subject: PCI/MSI: Let PCI host bridges declare their reliance on MSI domains - -There is a whole class of host bridges that cannot know whether -MSIs will be provided or not, as they rely on other blocks -to provide the MSI functionnality, using MSI domains. This is -the case for example on systems that use the ARM GIC architecture. - -Introduce a new attribute ('msi_domain') indicating that implicit -dependency, and use this property to set the NO_MSI flag when -no MSI domain is found at probe time. - -Link: https://lore.kernel.org/r/20210330151145.997953-11-maz@kernel.org -Signed-off-by: Marc Zyngier -Signed-off-by: Lorenzo Pieralisi -Acked-by: Bjorn Helgaas ---- - drivers/pci/probe.c | 2 ++ - include/linux/pci.h | 1 + - 2 files changed, 3 insertions(+) - ---- a/drivers/pci/probe.c -+++ b/drivers/pci/probe.c -@@ -925,6 +925,8 @@ static int pci_register_host_bridge(stru - device_enable_async_suspend(bus->bridge); - pci_set_bus_of_node(bus); - pci_set_bus_msi_domain(bus); -+ if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev)) -+ bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; - - if (!parent) - set_dev_node(bus->bridge, pcibus_to_node(bus)); ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -548,6 +548,7 @@ struct pci_host_bridge { - unsigned int native_dpc:1; /* OS may use PCIe DPC */ - unsigned int preserve_config:1; /* Preserve FW resource setup */ - unsigned int size_windows:1; /* Enable root bus sizing */ -+ unsigned int msi_domain:1; /* Bridge wants MSI domain */ - - /* Resource alignment requirements */ - resource_size_t (*align_resource)(struct pci_dev *dev, diff --git a/target/linux/generic/backport-5.10/822-v5.13-advertise-lack-of-built-in-msi-handling.patch b/target/linux/generic/backport-5.10/822-v5.13-advertise-lack-of-built-in-msi-handling.patch deleted file mode 100644 index c11aedd814..0000000000 --- a/target/linux/generic/backport-5.10/822-v5.13-advertise-lack-of-built-in-msi-handling.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 645e9c38383d7fcde2784ee537fa18ec9bed54d9 Mon Sep 17 00:00:00 2001 -From: Thomas Gleixner -Date: Tue, 30 Mar 2021 16:11:43 +0100 -Subject: PCI: mediatek: Advertise lack of built-in MSI handling - -Some Mediatek host bridges cannot handle MSIs, which is sad. -This also results in an ugly warning at device probe time, -as the core PCI code wasn't told that MSIs were not available. - -Advertise this fact to the rest of the core PCI code by -using the 'msi_domain' attribute, which still opens the possibility -for another block to provide the MSI functionnality. - -[maz: commit message, switched over to msi_domain attribute] - -Link: https://lore.kernel.org/r/20210330151145.997953-13-maz@kernel.org -Reported-by: Frank Wunderlich -Signed-off-by: Thomas Gleixner -Signed-off-by: Marc Zyngier -Signed-off-by: Lorenzo Pieralisi -Acked-by: Bjorn Helgaas ---- - drivers/pci/controller/pcie-mediatek.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -143,6 +143,7 @@ struct mtk_pcie_port; - * struct mtk_pcie_soc - differentiate between host generations - * @need_fix_class_id: whether this host's class ID needed to be fixed or not - * @need_fix_device_id: whether this host's device ID needed to be fixed or not -+ * @no_msi: Bridge has no MSI support, and relies on an external block - * @device_id: device ID which this host need to be fixed - * @ops: pointer to configuration access functions - * @startup: pointer to controller setting functions -@@ -151,6 +152,7 @@ struct mtk_pcie_port; - struct mtk_pcie_soc { - bool need_fix_class_id; - bool need_fix_device_id; -+ bool no_msi; - unsigned int device_id; - struct pci_ops *ops; - int (*startup)(struct mtk_pcie_port *port); -@@ -1087,6 +1089,7 @@ static int mtk_pcie_probe(struct platfor - - host->ops = pcie->soc->ops; - host->sysdata = pcie; -+ host->msi_domain = pcie->soc->no_msi; - - err = pci_host_probe(host); - if (err) -@@ -1176,6 +1179,7 @@ static const struct dev_pm_ops mtk_pcie_ - }; - - static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { -+ .no_msi = true, - .ops = &mtk_pcie_ops, - .startup = mtk_pcie_startup_port, - }; diff --git a/target/linux/generic/backport-5.10/825-v5.15-of-unify-of_count_phandle_with_args-arguments-with-C.patch b/target/linux/generic/backport-5.10/825-v5.15-of-unify-of_count_phandle_with_args-arguments-with-C.patch deleted file mode 100644 index ee5b7a0f7e..0000000000 --- a/target/linux/generic/backport-5.10/825-v5.15-of-unify-of_count_phandle_with_args-arguments-with-C.patch +++ /dev/null @@ -1,27 +0,0 @@ -From a065d5615fc83908ef21ed8159ffb63d816ff5de Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Wed, 28 Jul 2021 16:42:27 +0200 -Subject: [PATCH] of: unify of_count_phandle_with_args() arguments with - !CONFIG_OF - -Unify the declaration of of_count_phandle_with_args() between enabled -and disabled OF by making constifying pointed device_node. - -Signed-off-by: Krzysztof Kozlowski -Reviewed-by: Rob Herring -Signed-off-by: Bartosz Golaszewski ---- - include/linux/of.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/include/linux/of.h -+++ b/include/linux/of.h -@@ -889,7 +889,7 @@ static inline int of_parse_phandle_with_ - return -ENOSYS; - } - --static inline int of_count_phandle_with_args(struct device_node *np, -+static inline int of_count_phandle_with_args(const struct device_node *np, - const char *list_name, - const char *cells_name) - { diff --git a/target/linux/generic/backport-5.10/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch b/target/linux/generic/backport-5.10/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch deleted file mode 100644 index b6ef67dfa7..0000000000 --- a/target/linux/generic/backport-5.10/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch +++ /dev/null @@ -1,359 +0,0 @@ -From 66a8f7f04979f4ad739085f01d99c8caf620b4f5 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Tue, 18 Jan 2022 18:35:02 +0100 -Subject: [PATCH] of: base: make small of_parse_phandle() variants static - inline - -Make all the smaller variants of the of_parse_phandle() static inline. -This also let us remove the empty function stubs if CONFIG_OF is not -defined. - -Suggested-by: Rob Herring -Signed-off-by: Michael Walle -[robh: move index < 0 check into __of_parse_phandle_with_args] -Signed-off-by: Rob Herring -Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc ---- - drivers/of/base.c | 131 +++------------------------------------ - include/linux/of.h | 148 ++++++++++++++++++++++++++++++++++++--------- - 2 files changed, 129 insertions(+), 150 deletions(-) - ---- a/drivers/of/base.c -+++ b/drivers/of/base.c -@@ -1372,15 +1372,18 @@ int of_phandle_iterator_args(struct of_p - return count; - } - --static int __of_parse_phandle_with_args(const struct device_node *np, -- const char *list_name, -- const char *cells_name, -- int cell_count, int index, -- struct of_phandle_args *out_args) -+int __of_parse_phandle_with_args(const struct device_node *np, -+ const char *list_name, -+ const char *cells_name, -+ int cell_count, int index, -+ struct of_phandle_args *out_args) - { - struct of_phandle_iterator it; - int rc, cur_index = 0; - -+ if (index < 0) -+ return -EINVAL; -+ - /* Loop over the phandles until all the requested entry is found */ - of_for_each_phandle(&it, rc, np, list_name, cells_name, cell_count) { - /* -@@ -1423,82 +1426,7 @@ static int __of_parse_phandle_with_args( - of_node_put(it.node); - return rc; - } -- --/** -- * of_parse_phandle - Resolve a phandle property to a device_node pointer -- * @np: Pointer to device node holding phandle property -- * @phandle_name: Name of property holding a phandle value -- * @index: For properties holding a table of phandles, this is the index into -- * the table -- * -- * Return: The device_node pointer with refcount incremented. Use -- * of_node_put() on it when done. -- */ --struct device_node *of_parse_phandle(const struct device_node *np, -- const char *phandle_name, int index) --{ -- struct of_phandle_args args; -- -- if (index < 0) -- return NULL; -- -- if (__of_parse_phandle_with_args(np, phandle_name, NULL, 0, -- index, &args)) -- return NULL; -- -- return args.np; --} --EXPORT_SYMBOL(of_parse_phandle); -- --/** -- * of_parse_phandle_with_args() - Find a node pointed by phandle in a list -- * @np: pointer to a device tree node containing a list -- * @list_name: property name that contains a list -- * @cells_name: property name that specifies phandles' arguments count -- * @index: index of a phandle to parse out -- * @out_args: optional pointer to output arguments structure (will be filled) -- * -- * This function is useful to parse lists of phandles and their arguments. -- * Returns 0 on success and fills out_args, on error returns appropriate -- * errno value. -- * -- * Caller is responsible to call of_node_put() on the returned out_args->np -- * pointer. -- * -- * Example:: -- * -- * phandle1: node1 { -- * #list-cells = <2>; -- * }; -- * -- * phandle2: node2 { -- * #list-cells = <1>; -- * }; -- * -- * node3 { -- * list = <&phandle1 1 2 &phandle2 3>; -- * }; -- * -- * To get a device_node of the ``node2`` node you may call this: -- * of_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args); -- */ --int of_parse_phandle_with_args(const struct device_node *np, const char *list_name, -- const char *cells_name, int index, -- struct of_phandle_args *out_args) --{ -- int cell_count = -1; -- -- if (index < 0) -- return -EINVAL; -- -- /* If cells_name is NULL we assume a cell count of 0 */ -- if (!cells_name) -- cell_count = 0; -- -- return __of_parse_phandle_with_args(np, list_name, cells_name, -- cell_count, index, out_args); --} --EXPORT_SYMBOL(of_parse_phandle_with_args); -+EXPORT_SYMBOL(__of_parse_phandle_with_args); - - /** - * of_parse_phandle_with_args_map() - Find a node pointed by phandle in a list and remap it -@@ -1685,47 +1613,6 @@ free: - EXPORT_SYMBOL(of_parse_phandle_with_args_map); - - /** -- * of_parse_phandle_with_fixed_args() - Find a node pointed by phandle in a list -- * @np: pointer to a device tree node containing a list -- * @list_name: property name that contains a list -- * @cell_count: number of argument cells following the phandle -- * @index: index of a phandle to parse out -- * @out_args: optional pointer to output arguments structure (will be filled) -- * -- * This function is useful to parse lists of phandles and their arguments. -- * Returns 0 on success and fills out_args, on error returns appropriate -- * errno value. -- * -- * Caller is responsible to call of_node_put() on the returned out_args->np -- * pointer. -- * -- * Example:: -- * -- * phandle1: node1 { -- * }; -- * -- * phandle2: node2 { -- * }; -- * -- * node3 { -- * list = <&phandle1 0 2 &phandle2 2 3>; -- * }; -- * -- * To get a device_node of the ``node2`` node you may call this: -- * of_parse_phandle_with_fixed_args(node3, "list", 2, 1, &args); -- */ --int of_parse_phandle_with_fixed_args(const struct device_node *np, -- const char *list_name, int cell_count, -- int index, struct of_phandle_args *out_args) --{ -- if (index < 0) -- return -EINVAL; -- return __of_parse_phandle_with_args(np, list_name, NULL, cell_count, -- index, out_args); --} --EXPORT_SYMBOL(of_parse_phandle_with_fixed_args); -- --/** - * of_count_phandle_with_args() - Find the number of phandles references in a property - * @np: pointer to a device tree node containing a list - * @list_name: property name that contains a list ---- a/include/linux/of.h -+++ b/include/linux/of.h -@@ -363,18 +363,12 @@ extern const struct of_device_id *of_mat - const struct of_device_id *matches, const struct device_node *node); - extern int of_modalias_node(struct device_node *node, char *modalias, int len); - extern void of_print_phandle_args(const char *msg, const struct of_phandle_args *args); --extern struct device_node *of_parse_phandle(const struct device_node *np, -- const char *phandle_name, -- int index); --extern int of_parse_phandle_with_args(const struct device_node *np, -- const char *list_name, const char *cells_name, int index, -- struct of_phandle_args *out_args); -+extern int __of_parse_phandle_with_args(const struct device_node *np, -+ const char *list_name, const char *cells_name, int cell_count, -+ int index, struct of_phandle_args *out_args); - extern int of_parse_phandle_with_args_map(const struct device_node *np, - const char *list_name, const char *stem_name, int index, - struct of_phandle_args *out_args); --extern int of_parse_phandle_with_fixed_args(const struct device_node *np, -- const char *list_name, int cells_count, int index, -- struct of_phandle_args *out_args); - extern int of_count_phandle_with_args(const struct device_node *np, - const char *list_name, const char *cells_name); - -@@ -857,18 +851,12 @@ static inline int of_property_read_strin - return -ENOSYS; - } - --static inline struct device_node *of_parse_phandle(const struct device_node *np, -- const char *phandle_name, -- int index) --{ -- return NULL; --} -- --static inline int of_parse_phandle_with_args(const struct device_node *np, -- const char *list_name, -- const char *cells_name, -- int index, -- struct of_phandle_args *out_args) -+static inline int __of_parse_phandle_with_args(const struct device_node *np, -+ const char *list_name, -+ const char *cells_name, -+ int cell_count, -+ int index, -+ struct of_phandle_args *out_args) - { - return -ENOSYS; - } -@@ -882,13 +870,6 @@ static inline int of_parse_phandle_with_ - return -ENOSYS; - } - --static inline int of_parse_phandle_with_fixed_args(const struct device_node *np, -- const char *list_name, int cells_count, int index, -- struct of_phandle_args *out_args) --{ -- return -ENOSYS; --} -- - static inline int of_count_phandle_with_args(const struct device_node *np, - const char *list_name, - const char *cells_name) -@@ -1065,6 +1046,117 @@ static inline bool of_node_is_type(const - } - - /** -+ * of_parse_phandle - Resolve a phandle property to a device_node pointer -+ * @np: Pointer to device node holding phandle property -+ * @phandle_name: Name of property holding a phandle value -+ * @index: For properties holding a table of phandles, this is the index into -+ * the table -+ * -+ * Return: The device_node pointer with refcount incremented. Use -+ * of_node_put() on it when done. -+ */ -+static inline struct device_node *of_parse_phandle(const struct device_node *np, -+ const char *phandle_name, -+ int index) -+{ -+ struct of_phandle_args args; -+ -+ if (__of_parse_phandle_with_args(np, phandle_name, NULL, 0, -+ index, &args)) -+ return NULL; -+ -+ return args.np; -+} -+ -+/** -+ * of_parse_phandle_with_args() - Find a node pointed by phandle in a list -+ * @np: pointer to a device tree node containing a list -+ * @list_name: property name that contains a list -+ * @cells_name: property name that specifies phandles' arguments count -+ * @index: index of a phandle to parse out -+ * @out_args: optional pointer to output arguments structure (will be filled) -+ * -+ * This function is useful to parse lists of phandles and their arguments. -+ * Returns 0 on success and fills out_args, on error returns appropriate -+ * errno value. -+ * -+ * Caller is responsible to call of_node_put() on the returned out_args->np -+ * pointer. -+ * -+ * Example:: -+ * -+ * phandle1: node1 { -+ * #list-cells = <2>; -+ * }; -+ * -+ * phandle2: node2 { -+ * #list-cells = <1>; -+ * }; -+ * -+ * node3 { -+ * list = <&phandle1 1 2 &phandle2 3>; -+ * }; -+ * -+ * To get a device_node of the ``node2`` node you may call this: -+ * of_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args); -+ */ -+static inline int of_parse_phandle_with_args(const struct device_node *np, -+ const char *list_name, -+ const char *cells_name, -+ int index, -+ struct of_phandle_args *out_args) -+{ -+ int cell_count = -1; -+ -+ /* If cells_name is NULL we assume a cell count of 0 */ -+ if (!cells_name) -+ cell_count = 0; -+ -+ return __of_parse_phandle_with_args(np, list_name, cells_name, -+ cell_count, index, out_args); -+} -+ -+/** -+ * of_parse_phandle_with_fixed_args() - Find a node pointed by phandle in a list -+ * @np: pointer to a device tree node containing a list -+ * @list_name: property name that contains a list -+ * @cell_count: number of argument cells following the phandle -+ * @index: index of a phandle to parse out -+ * @out_args: optional pointer to output arguments structure (will be filled) -+ * -+ * This function is useful to parse lists of phandles and their arguments. -+ * Returns 0 on success and fills out_args, on error returns appropriate -+ * errno value. -+ * -+ * Caller is responsible to call of_node_put() on the returned out_args->np -+ * pointer. -+ * -+ * Example:: -+ * -+ * phandle1: node1 { -+ * }; -+ * -+ * phandle2: node2 { -+ * }; -+ * -+ * node3 { -+ * list = <&phandle1 0 2 &phandle2 2 3>; -+ * }; -+ * -+ * To get a device_node of the ``node2`` node you may call this: -+ * of_parse_phandle_with_fixed_args(node3, "list", 2, 1, &args); -+ */ -+static inline int of_parse_phandle_with_fixed_args(const struct device_node *np, -+ const char *list_name, -+ int cell_count, -+ int index, -+ struct of_phandle_args *out_args) -+{ -+ return __of_parse_phandle_with_args(np, list_name, NULL, cell_count, -+ index, out_args); -+} -+ -+/** - * of_property_count_u8_elems - Count the number of u8 elements in a property - * - * @np: device node from which the property value is to be read. diff --git a/target/linux/generic/backport-5.10/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch b/target/linux/generic/backport-5.10/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch deleted file mode 100644 index 3606034b9b..0000000000 --- a/target/linux/generic/backport-5.10/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch +++ /dev/null @@ -1,58 +0,0 @@ -From c5d264d4b527c96ae8903376a4b195df47b05203 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 6 Feb 2023 13:43:43 +0000 -Subject: [PATCH] of: base: add of_parse_phandle_with_optional_args() - -Add a new variant of the of_parse_phandle_with_args() which treats the -cells name as optional. If it's missing, it is assumed that the phandle -has no arguments. - -Up until now, a nvmem node didn't have any arguments, so all the device -trees haven't any '#*-cells' property. But there is a need for an -additional argument for the phandle, for which we need a '#*-cells' -property. Therefore, we need to support nvmem nodes with and without -this property. - -Signed-off-by: Michael Walle -Reviewed-by: Rob Herring -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-10-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - include/linux/of.h | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/include/linux/of.h -+++ b/include/linux/of.h -@@ -1157,6 +1157,31 @@ static inline int of_parse_phandle_with_ - } - - /** -+ * of_parse_phandle_with_optional_args() - Find a node pointed by phandle in a list -+ * @np: pointer to a device tree node containing a list -+ * @list_name: property name that contains a list -+ * @cells_name: property name that specifies phandles' arguments count -+ * @index: index of a phandle to parse out -+ * @out_args: optional pointer to output arguments structure (will be filled) -+ * -+ * Same as of_parse_phandle_with_args() except that if the cells_name property -+ * is not found, cell_count of 0 is assumed. -+ * -+ * This is used to useful, if you have a phandle which didn't have arguments -+ * before and thus doesn't have a '#*-cells' property but is now migrated to -+ * having arguments while retaining backwards compatibility. -+ */ -+static inline int of_parse_phandle_with_optional_args(const struct device_node *np, -+ const char *list_name, -+ const char *cells_name, -+ int index, -+ struct of_phandle_args *out_args) -+{ -+ return __of_parse_phandle_with_args(np, list_name, cells_name, -+ 0, index, out_args); -+} -+ -+/** - * of_property_count_u8_elems - Count the number of u8 elements in a property - * - * @np: device node from which the property value is to be read. diff --git a/target/linux/generic/backport-5.10/827-v6.3-0002-of-property-make-.-cells-optional-for-simple-props.patch b/target/linux/generic/backport-5.10/827-v6.3-0002-of-property-make-.-cells-optional-for-simple-props.patch deleted file mode 100644 index 0c45679e9d..0000000000 --- a/target/linux/generic/backport-5.10/827-v6.3-0002-of-property-make-.-cells-optional-for-simple-props.patch +++ /dev/null @@ -1,34 +0,0 @@ -From ff24fed10ba414d19579e26e60b126fad2f2bb07 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 6 Feb 2023 13:43:44 +0000 -Subject: [PATCH] of: property: make #.*-cells optional for simple props - -Sometimes, future bindings for phandles will get additional arguments. -Thus the target node of the phandle will need a new #.*-cells property. -To be backwards compatible, this needs to be optional. - -Prepare the DEFINE_SIMPLE_PROPS() to handle the cells name as optional. - -Signed-off-by: Michael Walle -Tested-by: Miquel Raynal -Reviewed-by: Rob Herring -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-11-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/of/property.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/of/property.c -+++ b/drivers/of/property.c -@@ -1213,8 +1213,8 @@ static struct device_node *parse_prop_ce - if (strcmp(prop_name, list_name)) - return NULL; - -- if (of_parse_phandle_with_args(np, list_name, cells_name, index, -- &sup_args)) -+ if (__of_parse_phandle_with_args(np, list_name, cells_name, 0, index, -+ &sup_args)) - return NULL; - - return sup_args.np; diff --git a/target/linux/generic/backport-5.10/827-v6.3-0003-of-property-add-nvmem-cell-cells-property.patch b/target/linux/generic/backport-5.10/827-v6.3-0003-of-property-add-nvmem-cell-cells-property.patch deleted file mode 100644 index 75ade39232..0000000000 --- a/target/linux/generic/backport-5.10/827-v6.3-0003-of-property-add-nvmem-cell-cells-property.patch +++ /dev/null @@ -1,30 +0,0 @@ -From e2d8172043d2e50df19fcd59c11e5593de8188d7 Mon Sep 17 00:00:00 2001 -From: Michael Walle -Date: Mon, 6 Feb 2023 13:43:45 +0000 -Subject: [PATCH] of: property: add #nvmem-cell-cells property - -Bindings describe the new '#nvmem-cell-cells' property. Now that the -arguments count property is optional, we just add this property to the -nvmem-cells. - -Signed-off-by: Michael Walle -Tested-by: Miquel Raynal -Reviewed-by: Rob Herring -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230206134356.839737-12-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/of/property.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/of/property.c -+++ b/drivers/of/property.c -@@ -1314,7 +1314,7 @@ DEFINE_SIMPLE_PROP(hwlocks, "hwlocks", " - DEFINE_SIMPLE_PROP(extcon, "extcon", NULL) - DEFINE_SIMPLE_PROP(interrupts_extended, "interrupts-extended", - "#interrupt-cells") --DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", NULL) -+DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", "#nvmem-cell-cells") - DEFINE_SIMPLE_PROP(phys, "phys", "#phy-cells") - DEFINE_SIMPLE_PROP(wakeup_parent, "wakeup-parent", NULL) - DEFINE_SIMPLE_PROP(pinctrl0, "pinctrl-0", NULL) diff --git a/target/linux/generic/backport-5.10/827-v6.3-0004-of-device-Ignore-modalias-of-reused-nodes.patch b/target/linux/generic/backport-5.10/827-v6.3-0004-of-device-Ignore-modalias-of-reused-nodes.patch deleted file mode 100644 index eed9dcc54e..0000000000 --- a/target/linux/generic/backport-5.10/827-v6.3-0004-of-device-Ignore-modalias-of-reused-nodes.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 553bd29700145e1849698985e9800f14e967da49 Mon Sep 17 00:00:00 2001 -From: Alexander Stein -Date: Tue, 7 Feb 2023 12:05:29 +0100 -Subject: [PATCH] of: device: Ignore modalias of reused nodes - -If of_node is reused, do not use that node's modalias. This will hide -the name of the actual device. This is rather prominent in USB glue -drivers creating a platform device for the host controller. - -Signed-off-by: Alexander Stein -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/20230207110531.1060252-2-alexander.stein@ew.tq-group.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/of/device.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/of/device.c -+++ b/drivers/of/device.c -@@ -223,7 +223,7 @@ static ssize_t of_device_get_modalias(st - ssize_t csize; - ssize_t tsize; - -- if ((!dev) || (!dev->of_node)) -+ if ((!dev) || (!dev->of_node) || dev->of_node_reused) - return -ENODEV; - - /* Name & Type */ -@@ -338,7 +338,7 @@ int of_device_uevent_modalias(struct dev - { - int sl; - -- if ((!dev) || (!dev->of_node)) -+ if ((!dev) || (!dev->of_node) || dev->of_node_reused) - return -ENODEV; - - /* Devicetree modalias is tricky, we add it in 2 steps */ diff --git a/target/linux/generic/backport-5.10/827-v6.3-0005-of-device-Do-not-ignore-error-code-in-of_device_ueve.patch b/target/linux/generic/backport-5.10/827-v6.3-0005-of-device-Do-not-ignore-error-code-in-of_device_ueve.patch deleted file mode 100644 index 64a2a20aa2..0000000000 --- a/target/linux/generic/backport-5.10/827-v6.3-0005-of-device-Do-not-ignore-error-code-in-of_device_ueve.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 2295bed9bebe8d1eef276194fed5b5fbe89c5363 Mon Sep 17 00:00:00 2001 -From: Alexander Stein -Date: Tue, 7 Feb 2023 12:05:30 +0100 -Subject: [PATCH] of: device: Do not ignore error code in - of_device_uevent_modalias - -of_device_get_modalias might return an error code, propagate that one. -Otherwise the negative, signed integer is propagated to unsigned integer -for the comparison resulting in a huge 'sl' size. - -Signed-off-by: Alexander Stein -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/20230207110531.1060252-3-alexander.stein@ew.tq-group.com -Signed-off-by: Greg Kroah-Hartman ---- - drivers/of/device.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/of/device.c -+++ b/drivers/of/device.c -@@ -347,6 +347,8 @@ int of_device_uevent_modalias(struct dev - - sl = of_device_get_modalias(dev, &env->buf[env->buflen-1], - sizeof(env->buf) - env->buflen); -+ if (sl < 0) -+ return sl; - if (sl >= (sizeof(env->buf) - env->buflen)) - return -ENOMEM; - env->buflen += sl; diff --git a/target/linux/generic/backport-5.10/828-v6.4-0001-of-Fix-modalias-string-generation.patch b/target/linux/generic/backport-5.10/828-v6.4-0001-of-Fix-modalias-string-generation.patch deleted file mode 100644 index 580a897e98..0000000000 --- a/target/linux/generic/backport-5.10/828-v6.4-0001-of-Fix-modalias-string-generation.patch +++ /dev/null @@ -1,70 +0,0 @@ -From b19a4266c52de78496fe40f0b37580a3b762e67d Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:09 +0100 -Subject: [PATCH] of: Fix modalias string generation - -The helper generating an OF based modalias (of_device_get_modalias()) -works fine, but due to the use of snprintf() internally it needs a -buffer one byte longer than what should be needed just for the entire -string (excluding the '\0'). Most users of this helper are sysfs hooks -providing the modalias string to users. They all provide a PAGE_SIZE -buffer which is way above the number of bytes required to fit the -modalias string and hence do not suffer from this issue. - -There is another user though, of_device_request_module(), which is only -called by drivers/usb/common/ulpi.c. This request module function is -faulty, but maybe because in most cases there is an alternative, ULPI -driver users have not noticed it. - -In this function, of_device_get_modalias() is called twice. The first -time without buffer just to get the number of bytes required by the -modalias string (excluding the null byte), and a second time, after -buffer allocation, to fill the buffer. The allocation asks for an -additional byte, in order to store the trailing '\0'. However, the -buffer *length* provided to of_device_get_modalias() excludes this extra -byte. The internal use of snprintf() with a length that is exactly the -number of bytes to be written has the effect of using the last available -byte to store a '\0', which then smashes the last character of the -modalias string. - -Provide the actual size of the buffer to of_device_get_modalias() to fix -this issue. - -Note: the "str[size - 1] = '\0';" line is not really needed as snprintf -will anyway end the string with a null byte, but there is a possibility -that this function might be called on a struct device_node without -compatible, in this case snprintf() would not be executed. So we keep it -just to avoid possible unbounded strings. - -Cc: Stephen Boyd -Cc: Peter Chen -Fixes: 9c829c097f2f ("of: device: Support loading a module with OF based modalias") -Signed-off-by: Miquel Raynal -Reviewed-by: Rob Herring -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-2-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/of/device.c | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - ---- a/drivers/of/device.c -+++ b/drivers/of/device.c -@@ -264,12 +264,15 @@ int of_device_request_module(struct devi - if (size < 0) - return size; - -- str = kmalloc(size + 1, GFP_KERNEL); -+ /* Reserve an additional byte for the trailing '\0' */ -+ size++; -+ -+ str = kmalloc(size, GFP_KERNEL); - if (!str) - return -ENOMEM; - - of_device_get_modalias(dev, str, size); -- str[size] = '\0'; -+ str[size - 1] = '\0'; - ret = request_module(str); - kfree(str); - diff --git a/target/linux/generic/backport-5.10/828-v6.4-0002-of-Update-of_device_get_modalias.patch b/target/linux/generic/backport-5.10/828-v6.4-0002-of-Update-of_device_get_modalias.patch deleted file mode 100644 index eac4ced5ab..0000000000 --- a/target/linux/generic/backport-5.10/828-v6.4-0002-of-Update-of_device_get_modalias.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 5c3d15e127ebfc0754cd18def7124633b6d46672 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:15 +0100 -Subject: [PATCH] of: Update of_device_get_modalias() - -This function only needs a "struct device_node" to work, but for -convenience the author (and only user) of this helper did use a "struct -device" and put it in device.c. - -Let's convert this helper to take a "struct device node" instead. This -change asks for two additional changes: renaming it "of_modalias()" -to fit the current naming, and moving it outside of device.c which will -be done in a follow-up commit. - -Signed-off-by: Miquel Raynal -Reviewed-by: Rob Herring -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-8-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/of/device.c | 29 +++++++++++++++++------------ - 1 file changed, 17 insertions(+), 12 deletions(-) - ---- a/drivers/of/device.c -+++ b/drivers/of/device.c -@@ -215,7 +215,7 @@ const void *of_device_get_match_data(con - } - EXPORT_SYMBOL(of_device_get_match_data); - --static ssize_t of_device_get_modalias(struct device *dev, char *str, ssize_t len) -+static ssize_t of_modalias(const struct device_node *np, char *str, ssize_t len) - { - const char *compat; - char *c; -@@ -223,19 +223,16 @@ static ssize_t of_device_get_modalias(st - ssize_t csize; - ssize_t tsize; - -- if ((!dev) || (!dev->of_node) || dev->of_node_reused) -- return -ENODEV; -- - /* Name & Type */ - /* %p eats all alphanum characters, so %c must be used here */ -- csize = snprintf(str, len, "of:N%pOFn%c%s", dev->of_node, 'T', -- of_node_get_device_type(dev->of_node)); -+ csize = snprintf(str, len, "of:N%pOFn%c%s", np, 'T', -+ of_node_get_device_type(np)); - tsize = csize; - len -= csize; - if (str) - str += csize; - -- of_property_for_each_string(dev->of_node, "compatible", p, compat) { -+ of_property_for_each_string(np, "compatible", p, compat) { - csize = strlen(compat) + 1; - tsize += csize; - if (csize > len) -@@ -260,7 +257,10 @@ int of_device_request_module(struct devi - ssize_t size; - int ret; - -- size = of_device_get_modalias(dev, NULL, 0); -+ if (!dev || !dev->of_node) -+ return -ENODEV; -+ -+ size = of_modalias(dev->of_node, NULL, 0); - if (size < 0) - return size; - -@@ -271,7 +271,7 @@ int of_device_request_module(struct devi - if (!str) - return -ENOMEM; - -- of_device_get_modalias(dev, str, size); -+ of_modalias(dev->of_node, str, size); - str[size - 1] = '\0'; - ret = request_module(str); - kfree(str); -@@ -285,7 +285,12 @@ EXPORT_SYMBOL_GPL(of_device_request_modu - */ - ssize_t of_device_modalias(struct device *dev, char *str, ssize_t len) - { -- ssize_t sl = of_device_get_modalias(dev, str, len - 2); -+ ssize_t sl; -+ -+ if (!dev || !dev->of_node || dev->of_node_reused) -+ return -ENODEV; -+ -+ sl = of_modalias(dev->of_node, str, len - 2); - if (sl < 0) - return sl; - if (sl > len - 2) -@@ -348,8 +353,8 @@ int of_device_uevent_modalias(struct dev - if (add_uevent_var(env, "MODALIAS=")) - return -ENOMEM; - -- sl = of_device_get_modalias(dev, &env->buf[env->buflen-1], -- sizeof(env->buf) - env->buflen); -+ sl = of_modalias(dev->of_node, &env->buf[env->buflen-1], -+ sizeof(env->buf) - env->buflen); - if (sl < 0) - return sl; - if (sl >= (sizeof(env->buf) - env->buflen)) diff --git a/target/linux/generic/backport-5.10/828-v6.4-0003-of-Rename-of_modalias_node.patch b/target/linux/generic/backport-5.10/828-v6.4-0003-of-Rename-of_modalias_node.patch deleted file mode 100644 index 7e641211e6..0000000000 --- a/target/linux/generic/backport-5.10/828-v6.4-0003-of-Rename-of_modalias_node.patch +++ /dev/null @@ -1,173 +0,0 @@ -From 673aa1ed1c9b6710bf24e3f0957d85e2f46c77db Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:16 +0100 -Subject: [PATCH] of: Rename of_modalias_node() - -This helper does not produce a real modalias, but tries to get the -"product" compatible part of the "vendor,product" compatibles only. It -is far from creating a purely useful modalias string and does not seem -to be used like that directly anyway, so let's try to give this helper a -more meaningful name before moving there a real modalias helper (already -existing under of/device.c). - -Also update the various documentations to refer to the strings as -"aliases" rather than "modaliases" which has a real meaning in the Linux -kernel. - -There is no functional change. - -Cc: Rafael J. Wysocki -Cc: Len Brown -Cc: Maarten Lankhorst -Cc: Maxime Ripard -Cc: Thomas Zimmermann -Cc: Sebastian Reichel -Cc: Wolfram Sang -Cc: Mark Brown -Signed-off-by: Miquel Raynal -Reviewed-by: Rob Herring -Acked-by: Mark Brown -Signed-off-by: Srinivas Kandagatla -Acked-by: Sebastian Reichel -Link: https://lore.kernel.org/r/20230404172148.82422-9-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/acpi/bus.c | 7 ++++--- - drivers/gpu/drm/drm_mipi_dsi.c | 2 +- - drivers/hsi/hsi_core.c | 2 +- - drivers/i2c/busses/i2c-powermac.c | 2 +- - drivers/i2c/i2c-core-of.c | 2 +- - drivers/of/base.c | 18 +++++++++++------- - drivers/spi/spi.c | 4 ++-- - include/linux/of.h | 3 ++- - 8 files changed, 23 insertions(+), 17 deletions(-) - ---- a/drivers/acpi/bus.c -+++ b/drivers/acpi/bus.c -@@ -693,9 +693,10 @@ static bool acpi_of_modalias(struct acpi - * @modalias: Pointer to buffer that modalias value will be copied into - * @len: Length of modalias buffer - * -- * This is a counterpart of of_modalias_node() for struct acpi_device objects. -- * If there is a compatible string for @adev, it will be copied to @modalias -- * with the vendor prefix stripped; otherwise, @default_id will be used. -+ * This is a counterpart of of_alias_from_compatible() for struct acpi_device -+ * objects. If there is a compatible string for @adev, it will be copied to -+ * @modalias with the vendor prefix stripped; otherwise, @default_id will be -+ * used. - */ - void acpi_set_modalias(struct acpi_device *adev, const char *default_id, - char *modalias, size_t len) ---- a/drivers/gpu/drm/drm_mipi_dsi.c -+++ b/drivers/gpu/drm/drm_mipi_dsi.c -@@ -160,7 +160,7 @@ of_mipi_dsi_device_add(struct mipi_dsi_h - int ret; - u32 reg; - -- if (of_modalias_node(node, info.type, sizeof(info.type)) < 0) { -+ if (of_alias_from_compatible(node, info.type, sizeof(info.type)) < 0) { - drm_err(host, "modalias failure on %pOF\n", node); - return ERR_PTR(-EINVAL); - } ---- a/drivers/hsi/hsi_core.c -+++ b/drivers/hsi/hsi_core.c -@@ -207,7 +207,7 @@ static void hsi_add_client_from_dt(struc - if (!cl) - return; - -- err = of_modalias_node(client, name, sizeof(name)); -+ err = of_alias_from_compatible(client, name, sizeof(name)); - if (err) - goto err; - ---- a/drivers/i2c/busses/i2c-powermac.c -+++ b/drivers/i2c/busses/i2c-powermac.c -@@ -289,7 +289,7 @@ static bool i2c_powermac_get_type(struct - */ - - /* First try proper modalias */ -- if (of_modalias_node(node, tmp, sizeof(tmp)) >= 0) { -+ if (of_alias_from_compatible(node, tmp, sizeof(tmp)) >= 0) { - snprintf(type, type_size, "MAC,%s", tmp); - return true; - } ---- a/drivers/i2c/i2c-core-of.c -+++ b/drivers/i2c/i2c-core-of.c -@@ -27,7 +27,7 @@ int of_i2c_get_board_info(struct device - - memset(info, 0, sizeof(*info)); - -- if (of_modalias_node(node, info->type, sizeof(info->type)) < 0) { -+ if (of_alias_from_compatible(node, info->type, sizeof(info->type)) < 0) { - dev_err(dev, "of_i2c: modalias failure on %pOF\n", node); - return -EINVAL; - } ---- a/drivers/of/base.c -+++ b/drivers/of/base.c -@@ -1160,19 +1160,23 @@ struct device_node *of_find_matching_nod - EXPORT_SYMBOL(of_find_matching_node_and_match); - - /** -- * of_modalias_node - Lookup appropriate modalias for a device node -+ * of_alias_from_compatible - Lookup appropriate alias for a device node -+ * depending on compatible - * @node: pointer to a device tree node -- * @modalias: Pointer to buffer that modalias value will be copied into -- * @len: Length of modalias value -+ * @alias: Pointer to buffer that alias value will be copied into -+ * @len: Length of alias value - * - * Based on the value of the compatible property, this routine will attempt -- * to choose an appropriate modalias value for a particular device tree node. -+ * to choose an appropriate alias value for a particular device tree node. - * It does this by stripping the manufacturer prefix (as delimited by a ',') - * from the first entry in the compatible list property. - * -+ * Note: The matching on just the "product" side of the compatible is a relic -+ * from I2C and SPI. Please do not add any new user. -+ * - * Return: This routine returns 0 on success, <0 on failure. - */ --int of_modalias_node(struct device_node *node, char *modalias, int len) -+int of_alias_from_compatible(const struct device_node *node, char *alias, int len) - { - const char *compatible, *p; - int cplen; -@@ -1181,10 +1185,10 @@ int of_modalias_node(struct device_node - if (!compatible || strlen(compatible) > cplen) - return -ENODEV; - p = strchr(compatible, ','); -- strlcpy(modalias, p ? p + 1 : compatible, len); -+ strlcpy(alias, p ? p + 1 : compatible, len); - return 0; - } --EXPORT_SYMBOL_GPL(of_modalias_node); -+EXPORT_SYMBOL_GPL(of_alias_from_compatible); - - /** - * of_find_node_by_phandle - Find a node given a phandle ---- a/drivers/spi/spi.c -+++ b/drivers/spi/spi.c -@@ -2038,8 +2038,8 @@ of_register_spi_device(struct spi_contro - } - - /* Select device driver */ -- rc = of_modalias_node(nc, spi->modalias, -- sizeof(spi->modalias)); -+ rc = of_alias_from_compatible(nc, spi->modalias, -+ sizeof(spi->modalias)); - if (rc < 0) { - dev_err(&ctlr->dev, "cannot find modalias for %pOF\n", nc); - goto err_out; ---- a/include/linux/of.h -+++ b/include/linux/of.h -@@ -361,7 +361,8 @@ extern int of_n_addr_cells(struct device - extern int of_n_size_cells(struct device_node *np); - extern const struct of_device_id *of_match_node( - const struct of_device_id *matches, const struct device_node *node); --extern int of_modalias_node(struct device_node *node, char *modalias, int len); -+extern int of_alias_from_compatible(const struct device_node *node, char *alias, -+ int len); - extern void of_print_phandle_args(const char *msg, const struct of_phandle_args *args); - extern int __of_parse_phandle_with_args(const struct device_node *np, - const char *list_name, const char *cells_name, int cell_count, diff --git a/target/linux/generic/backport-5.10/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch b/target/linux/generic/backport-5.10/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch deleted file mode 100644 index 62d1232bcd..0000000000 --- a/target/linux/generic/backport-5.10/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch +++ /dev/null @@ -1,160 +0,0 @@ -From bd7a7ed774afd1a4174df34227626c95573be517 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:17 +0100 -Subject: [PATCH] of: Move of_modalias() to module.c - -Create a specific .c file for OF related module handling. -Move of_modalias() inside as a first step. - -The helper is exposed through of.h even though it is only used by core -files because the users from device.c will soon be split into an OF-only -helper in module.c as well as a device-oriented inline helper in -of_device.h. Putting this helper in of_private.h would require to -include of_private.h from of_device.h, which is not acceptable. - -Suggested-by: Rob Herring -Signed-off-by: Miquel Raynal -Reviewed-by: Rob Herring -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-10-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/of/Makefile | 2 +- - drivers/of/device.c | 37 ------------------------------------- - drivers/of/module.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ - include/linux/of.h | 9 +++++++++ - 4 files changed, 54 insertions(+), 38 deletions(-) - create mode 100644 drivers/of/module.c - ---- a/drivers/of/Makefile -+++ b/drivers/of/Makefile -@@ -1,5 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 --obj-y = base.o device.o platform.o property.o -+obj-y = base.o device.o module.o platform.o property.o - obj-$(CONFIG_OF_KOBJ) += kobj.o - obj-$(CONFIG_OF_DYNAMIC) += dynamic.o - obj-$(CONFIG_OF_FLATTREE) += fdt.o ---- a/drivers/of/device.c -+++ b/drivers/of/device.c -@@ -1,5 +1,4 @@ - // SPDX-License-Identifier: GPL-2.0 --#include - #include - #include - #include -@@ -215,42 +214,6 @@ const void *of_device_get_match_data(con - } - EXPORT_SYMBOL(of_device_get_match_data); - --static ssize_t of_modalias(const struct device_node *np, char *str, ssize_t len) --{ -- const char *compat; -- char *c; -- struct property *p; -- ssize_t csize; -- ssize_t tsize; -- -- /* Name & Type */ -- /* %p eats all alphanum characters, so %c must be used here */ -- csize = snprintf(str, len, "of:N%pOFn%c%s", np, 'T', -- of_node_get_device_type(np)); -- tsize = csize; -- len -= csize; -- if (str) -- str += csize; -- -- of_property_for_each_string(np, "compatible", p, compat) { -- csize = strlen(compat) + 1; -- tsize += csize; -- if (csize > len) -- continue; -- -- csize = snprintf(str, len, "C%s", compat); -- for (c = str; c; ) { -- c = strchr(c, ' '); -- if (c) -- *c++ = '_'; -- } -- len -= csize; -- str += csize; -- } -- -- return tsize; --} -- - int of_device_request_module(struct device *dev) - { - char *str; ---- /dev/null -+++ b/drivers/of/module.c -@@ -0,0 +1,44 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Linux kernel module helpers. -+ */ -+ -+#include -+#include -+#include -+ -+ssize_t of_modalias(const struct device_node *np, char *str, ssize_t len) -+{ -+ const char *compat; -+ char *c; -+ struct property *p; -+ ssize_t csize; -+ ssize_t tsize; -+ -+ /* Name & Type */ -+ /* %p eats all alphanum characters, so %c must be used here */ -+ csize = snprintf(str, len, "of:N%pOFn%c%s", np, 'T', -+ of_node_get_device_type(np)); -+ tsize = csize; -+ len -= csize; -+ if (str) -+ str += csize; -+ -+ of_property_for_each_string(np, "compatible", p, compat) { -+ csize = strlen(compat) + 1; -+ tsize += csize; -+ if (csize > len) -+ continue; -+ -+ csize = snprintf(str, len, "C%s", compat); -+ for (c = str; c; ) { -+ c = strchr(c, ' '); -+ if (c) -+ *c++ = '_'; -+ } -+ len -= csize; -+ str += csize; -+ } -+ -+ return tsize; -+} ---- a/include/linux/of.h -+++ b/include/linux/of.h -@@ -373,6 +373,9 @@ extern int of_parse_phandle_with_args_ma - extern int of_count_phandle_with_args(const struct device_node *np, - const char *list_name, const char *cells_name); - -+/* module functions */ -+extern ssize_t of_modalias(const struct device_node *np, char *str, ssize_t len); -+ - /* phandle iterator functions */ - extern int of_phandle_iterator_init(struct of_phandle_iterator *it, - const struct device_node *np, -@@ -878,6 +881,12 @@ static inline int of_count_phandle_with_ - return -ENOSYS; - } - -+static inline ssize_t of_modalias(const struct device_node *np, char *str, -+ ssize_t len) -+{ -+ return -ENODEV; -+} -+ - static inline int of_phandle_iterator_init(struct of_phandle_iterator *it, - const struct device_node *np, - const char *list_name, diff --git a/target/linux/generic/backport-5.10/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch b/target/linux/generic/backport-5.10/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch deleted file mode 100644 index c176ff8f13..0000000000 --- a/target/linux/generic/backport-5.10/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch +++ /dev/null @@ -1,131 +0,0 @@ -From e6506f06d5e82765666902ccf9e9162f3e31d518 Mon Sep 17 00:00:00 2001 -From: Miquel Raynal -Date: Tue, 4 Apr 2023 18:21:18 +0100 -Subject: [PATCH] of: Move the request module helper logic to module.c - -Depending on device.c for pure OF handling is considered -backwards. Let's extract the content of of_device_request_module() to -have the real logic under module.c. - -The next step will be to convert users of of_device_request_module() to -use the new helper. - -Signed-off-by: Miquel Raynal -Reviewed-by: Rob Herring -Signed-off-by: Srinivas Kandagatla -Link: https://lore.kernel.org/r/20230404172148.82422-11-srinivas.kandagatla@linaro.org -Signed-off-by: Greg Kroah-Hartman ---- - drivers/of/device.c | 25 ++----------------------- - drivers/of/module.c | 30 ++++++++++++++++++++++++++++++ - include/linux/of.h | 6 ++++++ - 3 files changed, 38 insertions(+), 23 deletions(-) - ---- a/drivers/of/device.c -+++ b/drivers/of/device.c -@@ -7,7 +7,6 @@ - #include /* for bus_dma_region */ - #include - #include --#include - #include - #include - #include -@@ -216,30 +215,10 @@ EXPORT_SYMBOL(of_device_get_match_data); - - int of_device_request_module(struct device *dev) - { -- char *str; -- ssize_t size; -- int ret; -- -- if (!dev || !dev->of_node) -+ if (!dev) - return -ENODEV; - -- size = of_modalias(dev->of_node, NULL, 0); -- if (size < 0) -- return size; -- -- /* Reserve an additional byte for the trailing '\0' */ -- size++; -- -- str = kmalloc(size, GFP_KERNEL); -- if (!str) -- return -ENOMEM; -- -- of_modalias(dev->of_node, str, size); -- str[size - 1] = '\0'; -- ret = request_module(str); -- kfree(str); -- -- return ret; -+ return of_request_module(dev->of_node); - } - EXPORT_SYMBOL_GPL(of_device_request_module); - ---- a/drivers/of/module.c -+++ b/drivers/of/module.c -@@ -4,6 +4,7 @@ - */ - - #include -+#include - #include - #include - -@@ -42,3 +43,32 @@ ssize_t of_modalias(const struct device_ - - return tsize; - } -+ -+int of_request_module(const struct device_node *np) -+{ -+ char *str; -+ ssize_t size; -+ int ret; -+ -+ if (!np) -+ return -ENODEV; -+ -+ size = of_modalias(np, NULL, 0); -+ if (size < 0) -+ return size; -+ -+ /* Reserve an additional byte for the trailing '\0' */ -+ size++; -+ -+ str = kmalloc(size, GFP_KERNEL); -+ if (!str) -+ return -ENOMEM; -+ -+ of_modalias(np, str, size); -+ str[size - 1] = '\0'; -+ ret = request_module(str); -+ kfree(str); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(of_request_module); ---- a/include/linux/of.h -+++ b/include/linux/of.h -@@ -375,6 +375,7 @@ extern int of_count_phandle_with_args(co - - /* module functions */ - extern ssize_t of_modalias(const struct device_node *np, char *str, ssize_t len); -+extern int of_request_module(const struct device_node *np); - - /* phandle iterator functions */ - extern int of_phandle_iterator_init(struct of_phandle_iterator *it, -@@ -886,6 +887,11 @@ static inline ssize_t of_modalias(const - { - return -ENODEV; - } -+ -+static inline int of_request_module(const struct device_node *np) -+{ -+ return -ENODEV; -+} - - static inline int of_phandle_iterator_init(struct of_phandle_iterator *it, - const struct device_node *np, diff --git a/target/linux/generic/backport-5.10/830-v5.14-leds-lp55xx-Initialize-enable-GPIO-direction-to-outp.patch b/target/linux/generic/backport-5.10/830-v5.14-leds-lp55xx-Initialize-enable-GPIO-direction-to-outp.patch deleted file mode 100644 index 75b9947392..0000000000 --- a/target/linux/generic/backport-5.10/830-v5.14-leds-lp55xx-Initialize-enable-GPIO-direction-to-outp.patch +++ /dev/null @@ -1,28 +0,0 @@ -From a5d3d1adc95f4ac5968b7a77ee95a3abbbb96f49 Mon Sep 17 00:00:00 2001 -From: Doug Zobel -Date: Mon, 10 May 2021 15:40:00 -0500 -Subject: [PATCH] leds: lp55xx: Initialize enable GPIO direction to output - -The "Convert to use GPIO descriptors" commit changed the -initialization of the enable GPIO from GPIOF_DIR_OUT to -GPIOD_ASIS. This breaks systems where the GPIO does not -default to output. Changing the enable initialization -to GPIOD_OUT_LOW. - -Signed-off-by: Doug Zobel -Signed-off-by: Pavel Machek ---- - drivers/leds/leds-lp55xx-common.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/leds/leds-lp55xx-common.c -+++ b/drivers/leds/leds-lp55xx-common.c -@@ -694,7 +694,7 @@ struct lp55xx_platform_data *lp55xx_of_p - of_property_read_u8(np, "clock-mode", &pdata->clock_mode); - - pdata->enable_gpiod = devm_gpiod_get_optional(dev, "enable", -- GPIOD_ASIS); -+ GPIOD_OUT_LOW); - if (IS_ERR(pdata->enable_gpiod)) - return ERR_CAST(pdata->enable_gpiod); - diff --git a/target/linux/generic/backport-5.10/840-v5.15-leds-pca955x-clean-up-code-formatting.patch b/target/linux/generic/backport-5.10/840-v5.15-leds-pca955x-clean-up-code-formatting.patch deleted file mode 100644 index 80257c2ea0..0000000000 --- a/target/linux/generic/backport-5.10/840-v5.15-leds-pca955x-clean-up-code-formatting.patch +++ /dev/null @@ -1,176 +0,0 @@ -From 2420ae02ce0a926819ebe18f809a57bff3edeac2 Mon Sep 17 00:00:00 2001 -From: Eddie James -Date: Fri, 16 Jul 2021 17:03:27 -0500 -Subject: [PATCH] leds: pca955x: Clean up code formatting - -Format the code. Add some variables to help shorten lines. - -Signed-off-by: Eddie James -Signed-off-by: Pavel Machek ---- - drivers/leds/leds-pca955x.c | 63 ++++++++++++++++++------------------- - 1 file changed, 30 insertions(+), 33 deletions(-) - ---- a/drivers/leds/leds-pca955x.c -+++ b/drivers/leds/leds-pca955x.c -@@ -166,11 +166,10 @@ static inline u8 pca955x_ledsel(u8 oldva - static int pca955x_write_psc(struct i2c_client *client, int n, u8 val) - { - struct pca955x *pca955x = i2c_get_clientdata(client); -+ u8 cmd = pca95xx_num_input_regs(pca955x->chipdef->bits) + (2 * n); - int ret; - -- ret = i2c_smbus_write_byte_data(client, -- pca95xx_num_input_regs(pca955x->chipdef->bits) + 2*n, -- val); -+ ret = i2c_smbus_write_byte_data(client, cmd, val); - if (ret < 0) - dev_err(&client->dev, "%s: reg 0x%x, val 0x%x, err %d\n", - __func__, n, val, ret); -@@ -187,11 +186,10 @@ static int pca955x_write_psc(struct i2c_ - static int pca955x_write_pwm(struct i2c_client *client, int n, u8 val) - { - struct pca955x *pca955x = i2c_get_clientdata(client); -+ u8 cmd = pca95xx_num_input_regs(pca955x->chipdef->bits) + 1 + (2 * n); - int ret; - -- ret = i2c_smbus_write_byte_data(client, -- pca95xx_num_input_regs(pca955x->chipdef->bits) + 1 + 2*n, -- val); -+ ret = i2c_smbus_write_byte_data(client, cmd, val); - if (ret < 0) - dev_err(&client->dev, "%s: reg 0x%x, val 0x%x, err %d\n", - __func__, n, val, ret); -@@ -205,11 +203,10 @@ static int pca955x_write_pwm(struct i2c_ - static int pca955x_write_ls(struct i2c_client *client, int n, u8 val) - { - struct pca955x *pca955x = i2c_get_clientdata(client); -+ u8 cmd = pca95xx_num_input_regs(pca955x->chipdef->bits) + 4 + n; - int ret; - -- ret = i2c_smbus_write_byte_data(client, -- pca95xx_num_input_regs(pca955x->chipdef->bits) + 4 + n, -- val); -+ ret = i2c_smbus_write_byte_data(client, cmd, val); - if (ret < 0) - dev_err(&client->dev, "%s: reg 0x%x, val 0x%x, err %d\n", - __func__, n, val, ret); -@@ -223,10 +220,10 @@ static int pca955x_write_ls(struct i2c_c - static int pca955x_read_ls(struct i2c_client *client, int n, u8 *val) - { - struct pca955x *pca955x = i2c_get_clientdata(client); -+ u8 cmd = pca95xx_num_input_regs(pca955x->chipdef->bits) + 4 + n; - int ret; - -- ret = i2c_smbus_read_byte_data(client, -- pca95xx_num_input_regs(pca955x->chipdef->bits) + 4 + n); -+ ret = i2c_smbus_read_byte_data(client, cmd); - if (ret < 0) { - dev_err(&client->dev, "%s: reg 0x%x, err %d\n", - __func__, n, ret); -@@ -371,6 +368,7 @@ static struct pca955x_platform_data * - pca955x_get_pdata(struct i2c_client *client, struct pca955x_chipdef *chip) - { - struct pca955x_platform_data *pdata; -+ struct pca955x_led *led; - struct fwnode_handle *child; - int count; - -@@ -401,13 +399,13 @@ pca955x_get_pdata(struct i2c_client *cli - if ((res != 0) && is_of_node(child)) - name = to_of_node(child)->name; - -- snprintf(pdata->leds[reg].name, sizeof(pdata->leds[reg].name), -- "%s", name); -+ led = &pdata->leds[reg]; -+ snprintf(led->name, sizeof(led->name), "%s", name); - -- pdata->leds[reg].type = PCA955X_TYPE_LED; -- fwnode_property_read_u32(child, "type", &pdata->leds[reg].type); -+ led->type = PCA955X_TYPE_LED; -+ fwnode_property_read_u32(child, "type", &led->type); - fwnode_property_read_string(child, "linux,default-trigger", -- &pdata->leds[reg].default_trigger); -+ &led->default_trigger); - } - - pdata->num_leds = chip->bits; -@@ -426,11 +424,12 @@ static const struct of_device_id of_pca9 - MODULE_DEVICE_TABLE(of, of_pca955x_match); - - static int pca955x_probe(struct i2c_client *client, -- const struct i2c_device_id *id) -+ const struct i2c_device_id *id) - { - struct pca955x *pca955x; - struct pca955x_led *pca955x_led; - struct pca955x_chipdef *chip; -+ struct led_classdev *led; - struct i2c_adapter *adapter; - int i, err; - struct pca955x_platform_data *pdata; -@@ -449,13 +448,13 @@ static int pca955x_probe(struct i2c_clie - if ((client->addr & ~((1 << chip->slv_addr_shift) - 1)) != - chip->slv_addr) { - dev_err(&client->dev, "invalid slave address %02x\n", -- client->addr); -+ client->addr); - return -ENODEV; - } - - dev_info(&client->dev, "leds-pca955x: Using %s %d-bit LED driver at " -- "slave address 0x%02x\n", -- client->name, chip->bits, client->addr); -+ "slave address 0x%02x\n", client->name, chip->bits, -+ client->addr); - - if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) - return -EIO; -@@ -471,8 +470,8 @@ static int pca955x_probe(struct i2c_clie - if (!pca955x) - return -ENOMEM; - -- pca955x->leds = devm_kcalloc(&client->dev, -- chip->bits, sizeof(*pca955x_led), GFP_KERNEL); -+ pca955x->leds = devm_kcalloc(&client->dev, chip->bits, -+ sizeof(*pca955x_led), GFP_KERNEL); - if (!pca955x->leds) - return -ENOMEM; - -@@ -501,27 +500,25 @@ static int pca955x_probe(struct i2c_clie - */ - if (pdata->leds[i].name[0] == '\0') - snprintf(pdata->leds[i].name, -- sizeof(pdata->leds[i].name), "%d", i); -+ sizeof(pdata->leds[i].name), "%d", i); - -- snprintf(pca955x_led->name, -- sizeof(pca955x_led->name), "pca955x:%s", -- pdata->leds[i].name); -+ snprintf(pca955x_led->name, sizeof(pca955x_led->name), -+ "pca955x:%s", pdata->leds[i].name); - -+ led = &pca955x_led->led_cdev; - if (pdata->leds[i].default_trigger) -- pca955x_led->led_cdev.default_trigger = -+ led->default_trigger = - pdata->leds[i].default_trigger; - -- pca955x_led->led_cdev.name = pca955x_led->name; -- pca955x_led->led_cdev.brightness_set_blocking = -- pca955x_led_set; -+ led->name = pca955x_led->name; -+ led->brightness_set_blocking = pca955x_led_set; - -- err = devm_led_classdev_register(&client->dev, -- &pca955x_led->led_cdev); -+ err = devm_led_classdev_register(&client->dev, led); - if (err) - return err; - - /* Turn off LED */ -- err = pca955x_led_set(&pca955x_led->led_cdev, LED_OFF); -+ err = pca955x_led_set(led, LED_OFF); - if (err) - return err; - } diff --git a/target/linux/generic/backport-5.10/841-v5.15-leds-pca955x-add-brightness-get-function.patch b/target/linux/generic/backport-5.10/841-v5.15-leds-pca955x-add-brightness-get-function.patch deleted file mode 100644 index bdb095dc2e..0000000000 --- a/target/linux/generic/backport-5.10/841-v5.15-leds-pca955x-add-brightness-get-function.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 7086625fde6538b2c0623eb767ad23c7ac3d7f3a Mon Sep 17 00:00:00 2001 -From: Eddie James -Date: Fri, 16 Jul 2021 17:03:28 -0500 -Subject: [PATCH] leds: pca955x: Add brightness_get function - -Add a function to fetch the state of the hardware LED. - -Signed-off-by: Eddie James -Signed-off-by: Pavel Machek ---- - drivers/leds/leds-pca955x.c | 52 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 52 insertions(+) - ---- a/drivers/leds/leds-pca955x.c -+++ b/drivers/leds/leds-pca955x.c -@@ -233,6 +233,57 @@ static int pca955x_read_ls(struct i2c_cl - return 0; - } - -+static int pca955x_read_pwm(struct i2c_client *client, int n, u8 *val) -+{ -+ struct pca955x *pca955x = i2c_get_clientdata(client); -+ u8 cmd = pca95xx_num_input_regs(pca955x->chipdef->bits) + 1 + (2 * n); -+ int ret; -+ -+ ret = i2c_smbus_read_byte_data(client, cmd); -+ if (ret < 0) { -+ dev_err(&client->dev, "%s: reg 0x%x, err %d\n", -+ __func__, n, ret); -+ return ret; -+ } -+ *val = (u8)ret; -+ return 0; -+} -+ -+static enum led_brightness pca955x_led_get(struct led_classdev *led_cdev) -+{ -+ struct pca955x_led *pca955x_led = container_of(led_cdev, -+ struct pca955x_led, -+ led_cdev); -+ struct pca955x *pca955x = pca955x_led->pca955x; -+ u8 ls, pwm; -+ int ret; -+ -+ ret = pca955x_read_ls(pca955x->client, pca955x_led->led_num / 4, &ls); -+ if (ret) -+ return ret; -+ -+ ls = (ls >> ((pca955x_led->led_num % 4) << 1)) & 0x3; -+ switch (ls) { -+ case PCA955X_LS_LED_ON: -+ ret = LED_FULL; -+ break; -+ case PCA955X_LS_LED_OFF: -+ ret = LED_OFF; -+ break; -+ case PCA955X_LS_BLINK0: -+ ret = LED_HALF; -+ break; -+ case PCA955X_LS_BLINK1: -+ ret = pca955x_read_pwm(pca955x->client, 1, &pwm); -+ if (ret) -+ return ret; -+ ret = 255 - pwm; -+ break; -+ } -+ -+ return ret; -+} -+ - static int pca955x_led_set(struct led_classdev *led_cdev, - enum led_brightness value) - { -@@ -512,6 +563,7 @@ static int pca955x_probe(struct i2c_clie - - led->name = pca955x_led->name; - led->brightness_set_blocking = pca955x_led_set; -+ led->brightness_get = pca955x_led_get; - - err = devm_led_classdev_register(&client->dev, led); - if (err) diff --git a/target/linux/generic/backport-5.10/842-v5.15-leds-pca955x-implement-the-default-state-property.patch b/target/linux/generic/backport-5.10/842-v5.15-leds-pca955x-implement-the-default-state-property.patch deleted file mode 100644 index 8c79eb1b67..0000000000 --- a/target/linux/generic/backport-5.10/842-v5.15-leds-pca955x-implement-the-default-state-property.patch +++ /dev/null @@ -1,117 +0,0 @@ -From e46cb6d0c760a5b15e38138845fad99628fafcb8 Mon Sep 17 00:00:00 2001 -From: Eddie James -Date: Fri, 16 Jul 2021 17:03:29 -0500 -Subject: [PATCH] leds: pca955x: Implement the default-state property - -In order to retain the LED state after a system reboot, check the -documented default-state device tree property during initialization. -Modify the behavior of the probe according to the property. - -Signed-off-by: Eddie James -Signed-off-by: Pavel Machek ---- - drivers/leds/leds-pca955x.c | 54 +++++++++++++++++++++++++++++++------ - 1 file changed, 46 insertions(+), 8 deletions(-) - ---- a/drivers/leds/leds-pca955x.c -+++ b/drivers/leds/leds-pca955x.c -@@ -129,6 +129,7 @@ struct pca955x_led { - int led_num; /* 0 .. 15 potentially */ - char name[32]; - u32 type; -+ int default_state; - const char *default_trigger; - }; - -@@ -439,6 +440,7 @@ pca955x_get_pdata(struct i2c_client *cli - - device_for_each_child_node(&client->dev, child) { - const char *name; -+ const char *state; - u32 reg; - int res; - -@@ -457,6 +459,18 @@ pca955x_get_pdata(struct i2c_client *cli - fwnode_property_read_u32(child, "type", &led->type); - fwnode_property_read_string(child, "linux,default-trigger", - &led->default_trigger); -+ -+ if (!fwnode_property_read_string(child, "default-state", -+ &state)) { -+ if (!strcmp(state, "keep")) -+ led->default_state = LEDS_GPIO_DEFSTATE_KEEP; -+ else if (!strcmp(state, "on")) -+ led->default_state = LEDS_GPIO_DEFSTATE_ON; -+ else -+ led->default_state = LEDS_GPIO_DEFSTATE_OFF; -+ } else { -+ led->default_state = LEDS_GPIO_DEFSTATE_OFF; -+ } - } - - pdata->num_leds = chip->bits; -@@ -485,6 +499,7 @@ static int pca955x_probe(struct i2c_clie - int i, err; - struct pca955x_platform_data *pdata; - int ngpios = 0; -+ bool keep_pwm = false; - - chip = &pca955x_chipdefs[id->driver_data]; - adapter = client->adapter; -@@ -565,14 +580,35 @@ static int pca955x_probe(struct i2c_clie - led->brightness_set_blocking = pca955x_led_set; - led->brightness_get = pca955x_led_get; - -+ if (pdata->leds[i].default_state == -+ LEDS_GPIO_DEFSTATE_OFF) { -+ err = pca955x_led_set(led, LED_OFF); -+ if (err) -+ return err; -+ } else if (pdata->leds[i].default_state == -+ LEDS_GPIO_DEFSTATE_ON) { -+ err = pca955x_led_set(led, LED_FULL); -+ if (err) -+ return err; -+ } -+ - err = devm_led_classdev_register(&client->dev, led); - if (err) - return err; - -- /* Turn off LED */ -- err = pca955x_led_set(led, LED_OFF); -- if (err) -- return err; -+ /* -+ * For default-state == "keep", let the core update the -+ * brightness from the hardware, then check the -+ * brightness to see if it's using PWM1. If so, PWM1 -+ * should not be written below. -+ */ -+ if (pdata->leds[i].default_state == -+ LEDS_GPIO_DEFSTATE_KEEP) { -+ if (led->brightness != LED_FULL && -+ led->brightness != LED_OFF && -+ led->brightness != LED_HALF) -+ keep_pwm = true; -+ } - } - } - -@@ -581,10 +617,12 @@ static int pca955x_probe(struct i2c_clie - if (err) - return err; - -- /* PWM1 is used for variable brightness, default to OFF */ -- err = pca955x_write_pwm(client, 1, 0); -- if (err) -- return err; -+ if (!keep_pwm) { -+ /* PWM1 is used for variable brightness, default to OFF */ -+ err = pca955x_write_pwm(client, 1, 0); -+ if (err) -+ return err; -+ } - - /* Set to fast frequency so we do not see flashing */ - err = pca955x_write_psc(client, 0, 0); diff --git a/target/linux/generic/backport-5.10/843-v5.15-leds-pca955x-let-the-core-process-the-fwnode.patch b/target/linux/generic/backport-5.10/843-v5.15-leds-pca955x-let-the-core-process-the-fwnode.patch deleted file mode 100644 index 11311b8b2b..0000000000 --- a/target/linux/generic/backport-5.10/843-v5.15-leds-pca955x-let-the-core-process-the-fwnode.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 7c4815929276b2e223eb6f2e49afe5071d4294a5 Mon Sep 17 00:00:00 2001 -From: Eddie James -Date: Fri, 16 Jul 2021 17:03:30 -0500 -Subject: [PATCH] leds: pca955x: Let the core process the fwnode - -Much of the fwnode processing in the PCA955x driver is now in the -LEDs core driver, so pass the fwnode in the init data when -registering the LED device. In order to preserve the existing naming -scheme, check for an empty name and set it to the LED number. - -Signed-off-by: Eddie James -Signed-off-by: Pavel Machek ---- - drivers/leds/leds-pca955x.c | 58 +++++++++++++++++++------------------ - 1 file changed, 30 insertions(+), 28 deletions(-) - ---- a/drivers/leds/leds-pca955x.c -+++ b/drivers/leds/leds-pca955x.c -@@ -127,10 +127,9 @@ struct pca955x_led { - struct pca955x *pca955x; - struct led_classdev led_cdev; - int led_num; /* 0 .. 15 potentially */ -- char name[32]; - u32 type; - int default_state; -- const char *default_trigger; -+ struct fwnode_handle *fwnode; - }; - - struct pca955x_platform_data { -@@ -439,7 +438,6 @@ pca955x_get_pdata(struct i2c_client *cli - return ERR_PTR(-ENOMEM); - - device_for_each_child_node(&client->dev, child) { -- const char *name; - const char *state; - u32 reg; - int res; -@@ -448,17 +446,10 @@ pca955x_get_pdata(struct i2c_client *cli - if ((res != 0) || (reg >= chip->bits)) - continue; - -- res = fwnode_property_read_string(child, "label", &name); -- if ((res != 0) && is_of_node(child)) -- name = to_of_node(child)->name; -- - led = &pdata->leds[reg]; -- snprintf(led->name, sizeof(led->name), "%s", name); -- - led->type = PCA955X_TYPE_LED; -+ led->fwnode = child; - fwnode_property_read_u32(child, "type", &led->type); -- fwnode_property_read_string(child, "linux,default-trigger", -- &led->default_trigger); - - if (!fwnode_property_read_string(child, "default-state", - &state)) { -@@ -495,11 +486,14 @@ static int pca955x_probe(struct i2c_clie - struct pca955x_led *pca955x_led; - struct pca955x_chipdef *chip; - struct led_classdev *led; -+ struct led_init_data init_data; - struct i2c_adapter *adapter; - int i, err; - struct pca955x_platform_data *pdata; - int ngpios = 0; -+ bool set_default_label = false; - bool keep_pwm = false; -+ char default_label[8]; - - chip = &pca955x_chipdefs[id->driver_data]; - adapter = client->adapter; -@@ -547,6 +541,9 @@ static int pca955x_probe(struct i2c_clie - pca955x->client = client; - pca955x->chipdef = chip; - -+ init_data.devname_mandatory = false; -+ init_data.devicename = "pca955x"; -+ - for (i = 0; i < chip->bits; i++) { - pca955x_led = &pca955x->leds[i]; - pca955x_led->led_num = i; -@@ -560,23 +557,7 @@ static int pca955x_probe(struct i2c_clie - ngpios++; - break; - case PCA955X_TYPE_LED: -- /* -- * Platform data can specify LED names and -- * default triggers -- */ -- if (pdata->leds[i].name[0] == '\0') -- snprintf(pdata->leds[i].name, -- sizeof(pdata->leds[i].name), "%d", i); -- -- snprintf(pca955x_led->name, sizeof(pca955x_led->name), -- "pca955x:%s", pdata->leds[i].name); -- - led = &pca955x_led->led_cdev; -- if (pdata->leds[i].default_trigger) -- led->default_trigger = -- pdata->leds[i].default_trigger; -- -- led->name = pca955x_led->name; - led->brightness_set_blocking = pca955x_led_set; - led->brightness_get = pca955x_led_get; - -@@ -592,7 +573,28 @@ static int pca955x_probe(struct i2c_clie - return err; - } - -- err = devm_led_classdev_register(&client->dev, led); -+ init_data.fwnode = pdata->leds[i].fwnode; -+ -+ if (is_of_node(init_data.fwnode)) { -+ if (to_of_node(init_data.fwnode)->name[0] == -+ '\0') -+ set_default_label = true; -+ else -+ set_default_label = false; -+ } else { -+ set_default_label = true; -+ } -+ -+ if (set_default_label) { -+ snprintf(default_label, sizeof(default_label), -+ "%d", i); -+ init_data.default_label = default_label; -+ } else { -+ init_data.default_label = NULL; -+ } -+ -+ err = devm_led_classdev_register_ext(&client->dev, led, -+ &init_data); - if (err) - return err; - diff --git a/target/linux/generic/backport-5.10/844-v5.15-leds-pca955x-switch-to-i2c-probe-new.patch b/target/linux/generic/backport-5.10/844-v5.15-leds-pca955x-switch-to-i2c-probe-new.patch deleted file mode 100644 index 8154cd66f1..0000000000 --- a/target/linux/generic/backport-5.10/844-v5.15-leds-pca955x-switch-to-i2c-probe-new.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 239f32b4f161c1584cd4b386d6ab8766432a6ede Mon Sep 17 00:00:00 2001 -From: Eddie James -Date: Fri, 16 Jul 2021 17:03:31 -0500 -Subject: [PATCH] leds: pca955x: Switch to i2c probe_new - -The deprecated i2c probe functionality doesn't work with OF -compatible strings, as it only checks for the i2c device id. Switch -to the new way of probing and grab the match data to select the -chip type. - -Signed-off-by: Eddie James -Signed-off-by: Pavel Machek ---- - drivers/leds/leds-pca955x.c | 23 +++++++++++++++++++---- - 1 file changed, 19 insertions(+), 4 deletions(-) - ---- a/drivers/leds/leds-pca955x.c -+++ b/drivers/leds/leds-pca955x.c -@@ -479,8 +479,7 @@ static const struct of_device_id of_pca9 - }; - MODULE_DEVICE_TABLE(of, of_pca955x_match); - --static int pca955x_probe(struct i2c_client *client, -- const struct i2c_device_id *id) -+static int pca955x_probe(struct i2c_client *client) - { - struct pca955x *pca955x; - struct pca955x_led *pca955x_led; -@@ -494,8 +493,24 @@ static int pca955x_probe(struct i2c_clie - bool set_default_label = false; - bool keep_pwm = false; - char default_label[8]; -+ enum pca955x_type chip_type; -+ const void *md = device_get_match_data(&client->dev); - -- chip = &pca955x_chipdefs[id->driver_data]; -+ if (md) { -+ chip_type = (enum pca955x_type)md; -+ } else { -+ const struct i2c_device_id *id = i2c_match_id(pca955x_id, -+ client); -+ -+ if (id) { -+ chip_type = (enum pca955x_type)id->driver_data; -+ } else { -+ dev_err(&client->dev, "unknown chip\n"); -+ return -ENODEV; -+ } -+ } -+ -+ chip = &pca955x_chipdefs[chip_type]; - adapter = client->adapter; - pdata = dev_get_platdata(&client->dev); - if (!pdata) { -@@ -670,7 +685,7 @@ static struct i2c_driver pca955x_driver - .name = "leds-pca955x", - .of_match_table = of_pca955x_match, - }, -- .probe = pca955x_probe, -+ .probe_new = pca955x_probe, - .id_table = pca955x_id, - }; - diff --git a/target/linux/generic/backport-5.10/845-v6.0-0001-dt-bindings-leds-add-Broadcom-s-BCM63138-controller.patch b/target/linux/generic/backport-5.10/845-v6.0-0001-dt-bindings-leds-add-Broadcom-s-BCM63138-controller.patch deleted file mode 100644 index b1072ce640..0000000000 --- a/target/linux/generic/backport-5.10/845-v6.0-0001-dt-bindings-leds-add-Broadcom-s-BCM63138-controller.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 13344f8ce8a0d98aa7f5d69ce3b47393c73a343b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 27 Dec 2021 15:59:04 +0100 -Subject: [PATCH] dt-bindings: leds: add Broadcom's BCM63138 controller -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Broadcom used 2 LEDs hardware blocks for their BCM63xx SoCs: -1. Older one (BCM6318, BCM6328, BCM6362, BCM63268, BCM6838) -2. Newer one (BCM6848, BCM6858, BCM63138, BCM63148, BCM63381, BCM68360) - -The newer one was also later also used on BCM4908 SoC. - -Old block is already documented in the leds-bcm6328.yaml. This binding -documents the new one which uses different registers & programming. It's -first used in BCM63138 thus the binding name. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Rob Herring -Reviewed-by: Florian Fainelli -Signed-off-by: Pavel Machek ---- - .../bindings/leds/leds-bcm63138.yaml | 95 +++++++++++++++++++ - 1 file changed, 95 insertions(+) - create mode 100644 Documentation/devicetree/bindings/leds/leds-bcm63138.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/leds/leds-bcm63138.yaml -@@ -0,0 +1,95 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/leds/leds-bcm63138.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Broadcom's BCM63138 LEDs controller -+ -+maintainers: -+ - Rafał Miłecki -+ -+description: | -+ This LEDs controller was first used on BCM63138 and later reused on BCM4908, -+ BCM6848, BCM6858, BCM63138, BCM63148, BCM63381 and BCM68360 SoCs. -+ -+ It supports up to 32 LEDs that can be connected parallelly or serially. It -+ also includes limited support for hardware blinking. -+ -+ Binding serially connected LEDs isn't documented yet. -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - brcm,bcm4908-leds -+ - brcm,bcm6848-leds -+ - brcm,bcm6858-leds -+ - brcm,bcm63148-leds -+ - brcm,bcm63381-leds -+ - brcm,bcm68360-leds -+ - const: brcm,bcm63138-leds -+ - const: brcm,bcm63138-leds -+ -+ reg: -+ maxItems: 1 -+ -+ "#address-cells": -+ const: 1 -+ -+ "#size-cells": -+ const: 0 -+ -+patternProperties: -+ "^led@[a-f0-9]+$": -+ type: object -+ -+ $ref: common.yaml# -+ -+ properties: -+ reg: -+ maxItems: 1 -+ description: LED pin number -+ -+ active-low: -+ type: boolean -+ description: Makes LED active low. -+ -+ required: -+ - reg -+ -+ unevaluatedProperties: false -+ -+required: -+ - reg -+ - "#address-cells" -+ - "#size-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ -+ leds@ff800800 { -+ compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds"; -+ reg = <0xff800800 0xdc>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ led@0 { -+ reg = <0x0>; -+ function = LED_FUNCTION_POWER; -+ color = ; -+ default-state = "on"; -+ }; -+ -+ led@3 { -+ reg = <0x3>; -+ function = LED_FUNCTION_STATUS; -+ color = ; -+ active-low; -+ }; -+ }; diff --git a/target/linux/generic/backport-5.10/845-v6.0-0002-leds-bcm63138-add-support-for-BCM63138-controller.patch b/target/linux/generic/backport-5.10/845-v6.0-0002-leds-bcm63138-add-support-for-BCM63138-controller.patch deleted file mode 100644 index 8ebe8f180b..0000000000 --- a/target/linux/generic/backport-5.10/845-v6.0-0002-leds-bcm63138-add-support-for-BCM63138-controller.patch +++ /dev/null @@ -1,371 +0,0 @@ -From a0ba692072d89075d0a75c7ad9df31f2c1ee9a1c Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 27 Dec 2021 15:59:05 +0100 -Subject: [PATCH] leds: bcm63138: add support for BCM63138 controller -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's a new controller first introduced in BCM63138 SoC. Later it was -also used in BCM4908, some BCM68xx and some BCM63xxx SoCs. - -Signed-off-by: Rafał Miłecki -Reviewed-by: Florian Fainelli -Signed-off-by: Pavel Machek ---- - drivers/leds/blink/Kconfig | 12 ++ - drivers/leds/blink/Makefile | 1 + - drivers/leds/blink/leds-bcm63138.c | 308 +++++++++++++++++++++++++++++ - 3 files changed, 321 insertions(+) - create mode 100644 drivers/leds/blink/leds-bcm63138.c - ---- /dev/null -+++ b/drivers/leds/blink/Kconfig -@@ -0,0 +1,11 @@ -+config LEDS_BCM63138 -+ tristate "LED Support for Broadcom BCM63138 SoC" -+ depends on LEDS_CLASS -+ depends on ARCH_BCM4908 || ARCH_BCM_5301X || BCM63XX || COMPILE_TEST -+ depends on HAS_IOMEM -+ depends on OF -+ default ARCH_BCM4908 -+ help -+ This option enables support for LED controller that is part of -+ BCM63138 SoC. The same hardware block is known to be also used -+ in BCM4908, BCM6848, BCM6858, BCM63148, BCM63381 and BCM68360. ---- /dev/null -+++ b/drivers/leds/blink/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_LEDS_BCM63138) += leds-bcm63138.o ---- /dev/null -+++ b/drivers/leds/blink/leds-bcm63138.c -@@ -0,0 +1,308 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2021 Rafał Miłecki -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BCM63138_MAX_LEDS 32 -+#define BCM63138_MAX_BRIGHTNESS 9 -+ -+#define BCM63138_LED_BITS 4 /* how many bits control a single LED */ -+#define BCM63138_LED_MASK ((1 << BCM63138_LED_BITS) - 1) /* 0xf */ -+#define BCM63138_LEDS_PER_REG (32 / BCM63138_LED_BITS) /* 8 */ -+ -+#define BCM63138_GLB_CTRL 0x00 -+#define BCM63138_GLB_CTRL_SERIAL_LED_DATA_PPOL 0x00000002 -+#define BCM63138_GLB_CTRL_SERIAL_LED_EN_POL 0x00000008 -+#define BCM63138_MASK 0x04 -+#define BCM63138_HW_LED_EN 0x08 -+#define BCM63138_SERIAL_LED_SHIFT_SEL 0x0c -+#define BCM63138_FLASH_RATE_CTRL1 0x10 -+#define BCM63138_FLASH_RATE_CTRL2 0x14 -+#define BCM63138_FLASH_RATE_CTRL3 0x18 -+#define BCM63138_FLASH_RATE_CTRL4 0x1c -+#define BCM63138_BRIGHT_CTRL1 0x20 -+#define BCM63138_BRIGHT_CTRL2 0x24 -+#define BCM63138_BRIGHT_CTRL3 0x28 -+#define BCM63138_BRIGHT_CTRL4 0x2c -+#define BCM63138_POWER_LED_CFG 0x30 -+#define BCM63138_HW_POLARITY 0xb4 -+#define BCM63138_SW_DATA 0xb8 -+#define BCM63138_SW_POLARITY 0xbc -+#define BCM63138_PARALLEL_LED_POLARITY 0xc0 -+#define BCM63138_SERIAL_LED_POLARITY 0xc4 -+#define BCM63138_HW_LED_STATUS 0xc8 -+#define BCM63138_FLASH_CTRL_STATUS 0xcc -+#define BCM63138_FLASH_BRT_CTRL 0xd0 -+#define BCM63138_FLASH_P_LED_OUT_STATUS 0xd4 -+#define BCM63138_FLASH_S_LED_OUT_STATUS 0xd8 -+ -+struct bcm63138_leds { -+ struct device *dev; -+ void __iomem *base; -+ spinlock_t lock; -+}; -+ -+struct bcm63138_led { -+ struct bcm63138_leds *leds; -+ struct led_classdev cdev; -+ u32 pin; -+ bool active_low; -+}; -+ -+/* -+ * I/O access -+ */ -+ -+static void bcm63138_leds_write(struct bcm63138_leds *leds, unsigned int reg, -+ u32 data) -+{ -+ writel(data, leds->base + reg); -+} -+ -+static unsigned long bcm63138_leds_read(struct bcm63138_leds *leds, -+ unsigned int reg) -+{ -+ return readl(leds->base + reg); -+} -+ -+static void bcm63138_leds_update_bits(struct bcm63138_leds *leds, -+ unsigned int reg, u32 mask, u32 val) -+{ -+ WARN_ON(val & ~mask); -+ -+ bcm63138_leds_write(leds, reg, (bcm63138_leds_read(leds, reg) & ~mask) | (val & mask)); -+} -+ -+/* -+ * Helpers -+ */ -+ -+static void bcm63138_leds_set_flash_rate(struct bcm63138_leds *leds, -+ struct bcm63138_led *led, -+ u8 value) -+{ -+ int reg_offset = (led->pin >> fls((BCM63138_LEDS_PER_REG - 1))) * 4; -+ int shift = (led->pin & (BCM63138_LEDS_PER_REG - 1)) * BCM63138_LED_BITS; -+ -+ bcm63138_leds_update_bits(leds, BCM63138_FLASH_RATE_CTRL1 + reg_offset, -+ BCM63138_LED_MASK << shift, value << shift); -+} -+ -+static void bcm63138_leds_set_bright(struct bcm63138_leds *leds, -+ struct bcm63138_led *led, -+ u8 value) -+{ -+ int reg_offset = (led->pin >> fls((BCM63138_LEDS_PER_REG - 1))) * 4; -+ int shift = (led->pin & (BCM63138_LEDS_PER_REG - 1)) * BCM63138_LED_BITS; -+ -+ bcm63138_leds_update_bits(leds, BCM63138_BRIGHT_CTRL1 + reg_offset, -+ BCM63138_LED_MASK << shift, value << shift); -+} -+ -+static void bcm63138_leds_enable_led(struct bcm63138_leds *leds, -+ struct bcm63138_led *led, -+ enum led_brightness value) -+{ -+ u32 bit = BIT(led->pin); -+ -+ bcm63138_leds_update_bits(leds, BCM63138_SW_DATA, bit, -+ value == LED_OFF ? 0 : bit); -+} -+ -+/* -+ * API callbacks -+ */ -+ -+static void bcm63138_leds_brightness_set(struct led_classdev *led_cdev, -+ enum led_brightness value) -+{ -+ struct bcm63138_led *led = container_of(led_cdev, struct bcm63138_led, cdev); -+ struct bcm63138_leds *leds = led->leds; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&leds->lock, flags); -+ -+ bcm63138_leds_enable_led(leds, led, value); -+ if (!value) -+ bcm63138_leds_set_flash_rate(leds, led, 0); -+ else -+ bcm63138_leds_set_bright(leds, led, value); -+ -+ spin_unlock_irqrestore(&leds->lock, flags); -+} -+ -+static int bcm63138_leds_blink_set(struct led_classdev *led_cdev, -+ unsigned long *delay_on, -+ unsigned long *delay_off) -+{ -+ struct bcm63138_led *led = container_of(led_cdev, struct bcm63138_led, cdev); -+ struct bcm63138_leds *leds = led->leds; -+ unsigned long flags; -+ u8 value; -+ -+ if (!*delay_on && !*delay_off) { -+ *delay_on = 640; -+ *delay_off = 640; -+ } -+ -+ if (*delay_on != *delay_off) { -+ dev_dbg(led_cdev->dev, "Blinking at unequal delays is not supported\n"); -+ return -EINVAL; -+ } -+ -+ switch (*delay_on) { -+ case 1152 ... 1408: /* 1280 ms ± 10% */ -+ value = 0x7; -+ break; -+ case 576 ... 704: /* 640 ms ± 10% */ -+ value = 0x6; -+ break; -+ case 288 ... 352: /* 320 ms ± 10% */ -+ value = 0x5; -+ break; -+ case 126 ... 154: /* 140 ms ± 10% */ -+ value = 0x4; -+ break; -+ case 59 ... 72: /* 65 ms ± 10% */ -+ value = 0x3; -+ break; -+ default: -+ dev_dbg(led_cdev->dev, "Blinking delay value %lu is unsupported\n", -+ *delay_on); -+ return -EINVAL; -+ } -+ -+ spin_lock_irqsave(&leds->lock, flags); -+ -+ bcm63138_leds_enable_led(leds, led, BCM63138_MAX_BRIGHTNESS); -+ bcm63138_leds_set_flash_rate(leds, led, value); -+ -+ spin_unlock_irqrestore(&leds->lock, flags); -+ -+ return 0; -+} -+ -+/* -+ * LED driver -+ */ -+ -+static void bcm63138_leds_create_led(struct bcm63138_leds *leds, -+ struct device_node *np) -+{ -+ struct led_init_data init_data = { -+ .fwnode = of_fwnode_handle(np), -+ }; -+ struct device *dev = leds->dev; -+ struct bcm63138_led *led; -+ struct pinctrl *pinctrl; -+ u32 bit; -+ int err; -+ -+ led = devm_kzalloc(dev, sizeof(*led), GFP_KERNEL); -+ if (!led) { -+ dev_err(dev, "Failed to alloc LED\n"); -+ return; -+ } -+ -+ led->leds = leds; -+ -+ if (of_property_read_u32(np, "reg", &led->pin)) { -+ dev_err(dev, "Missing \"reg\" property in %pOF\n", np); -+ goto err_free; -+ } -+ -+ if (led->pin >= BCM63138_MAX_LEDS) { -+ dev_err(dev, "Invalid \"reg\" value %d\n", led->pin); -+ goto err_free; -+ } -+ -+ led->active_low = of_property_read_bool(np, "active-low"); -+ -+ led->cdev.max_brightness = BCM63138_MAX_BRIGHTNESS; -+ led->cdev.brightness_set = bcm63138_leds_brightness_set; -+ led->cdev.blink_set = bcm63138_leds_blink_set; -+ -+ err = devm_led_classdev_register_ext(dev, &led->cdev, &init_data); -+ if (err) { -+ dev_err(dev, "Failed to register LED %pOF: %d\n", np, err); -+ goto err_free; -+ } -+ -+ pinctrl = devm_pinctrl_get_select_default(led->cdev.dev); -+ if (IS_ERR(pinctrl) && PTR_ERR(pinctrl) != -ENODEV) { -+ dev_warn(led->cdev.dev, "Failed to select %pOF pinctrl: %ld\n", -+ np, PTR_ERR(pinctrl)); -+ } -+ -+ bit = BIT(led->pin); -+ bcm63138_leds_update_bits(leds, BCM63138_PARALLEL_LED_POLARITY, bit, -+ led->active_low ? 0 : bit); -+ bcm63138_leds_update_bits(leds, BCM63138_HW_LED_EN, bit, 0); -+ bcm63138_leds_set_flash_rate(leds, led, 0); -+ bcm63138_leds_enable_led(leds, led, led->cdev.brightness); -+ -+ return; -+ -+err_free: -+ devm_kfree(dev, led); -+} -+ -+static int bcm63138_leds_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = dev_of_node(&pdev->dev); -+ struct device *dev = &pdev->dev; -+ struct bcm63138_leds *leds; -+ struct device_node *child; -+ -+ leds = devm_kzalloc(dev, sizeof(*leds), GFP_KERNEL); -+ if (!leds) -+ return -ENOMEM; -+ -+ leds->dev = dev; -+ -+ leds->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(leds->base)) -+ return PTR_ERR(leds->base); -+ -+ spin_lock_init(&leds->lock); -+ -+ bcm63138_leds_write(leds, BCM63138_GLB_CTRL, -+ BCM63138_GLB_CTRL_SERIAL_LED_DATA_PPOL | -+ BCM63138_GLB_CTRL_SERIAL_LED_EN_POL); -+ bcm63138_leds_write(leds, BCM63138_HW_LED_EN, 0); -+ bcm63138_leds_write(leds, BCM63138_SERIAL_LED_POLARITY, 0); -+ bcm63138_leds_write(leds, BCM63138_PARALLEL_LED_POLARITY, 0); -+ -+ for_each_available_child_of_node(np, child) { -+ bcm63138_leds_create_led(leds, child); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm63138_leds_of_match_table[] = { -+ { .compatible = "brcm,bcm63138-leds", }, -+ { }, -+}; -+ -+static struct platform_driver bcm63138_leds_driver = { -+ .probe = bcm63138_leds_probe, -+ .driver = { -+ .name = "leds-bcm63xxx", -+ .of_match_table = bcm63138_leds_of_match_table, -+ }, -+}; -+ -+module_platform_driver(bcm63138_leds_driver); -+ -+MODULE_AUTHOR("Rafał Miłecki"); -+MODULE_LICENSE("GPL"); -+MODULE_DEVICE_TABLE(of, bcm63138_leds_of_match_table); ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -929,6 +929,8 @@ config LEDS_ACER_A500 - This option enables support for the Power Button LED of - Acer Iconia Tab A500. - -+source "drivers/leds/blink/Kconfig" -+ - comment "LED Triggers" - source "drivers/leds/trigger/Kconfig" - ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -105,3 +105,6 @@ obj-$(CONFIG_LEDS_USER) += uleds.o - - # LED Triggers - obj-$(CONFIG_LEDS_TRIGGERS) += trigger/ -+ -+# LED Blink -+obj-y += blink/ diff --git a/target/linux/generic/backport-5.10/846-v6.0-0001-dt-bindings-leds-leds-bcm63138-unify-full-stops-in-d.patch b/target/linux/generic/backport-5.10/846-v6.0-0001-dt-bindings-leds-leds-bcm63138-unify-full-stops-in-d.patch deleted file mode 100644 index 483826abed..0000000000 --- a/target/linux/generic/backport-5.10/846-v6.0-0001-dt-bindings-leds-leds-bcm63138-unify-full-stops-in-d.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 13b64a0c19059b38150c79d65d350ae44034c5df Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sun, 17 Jul 2022 14:42:46 +0200 -Subject: [PATCH] dt-bindings: leds: leds-bcm63138: unify full stops in - descriptions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Description of "reg" doesn't have full stop at the end. It makes sense -as it's a one-sentence only. Use the same style for "active-low". - -Reported-by: Pavel Machek -Signed-off-by: Rafał Miłecki -Signed-off-by: Pavel Machek ---- - Documentation/devicetree/bindings/leds/leds-bcm63138.yaml | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/leds/leds-bcm63138.yaml -+++ b/Documentation/devicetree/bindings/leds/leds-bcm63138.yaml -@@ -54,7 +54,7 @@ patternProperties: - - active-low: - type: boolean -- description: Makes LED active low. -+ description: Makes LED active low - - required: - - reg diff --git a/target/linux/generic/backport-5.10/846-v6.0-0002-leds-add-help-info-about-BCM63138-module-name.patch b/target/linux/generic/backport-5.10/846-v6.0-0002-leds-add-help-info-about-BCM63138-module-name.patch deleted file mode 100644 index 44e8be86fd..0000000000 --- a/target/linux/generic/backport-5.10/846-v6.0-0002-leds-add-help-info-about-BCM63138-module-name.patch +++ /dev/null @@ -1,25 +0,0 @@ -From bcc607cdbb1f931111196699426f0cb83bfb296a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sun, 17 Jul 2022 14:42:47 +0200 -Subject: [PATCH] leds: add help info about BCM63138 module name -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It's what we do for all other LEDs drivers. - -Reported-by: Pavel Machek -Signed-off-by: Rafał Miłecki -Signed-off-by: Pavel Machek ---- - drivers/leds/blink/Kconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/leds/blink/Kconfig -+++ b/drivers/leds/blink/Kconfig -@@ -9,3 +9,5 @@ config LEDS_BCM63138 - This option enables support for LED controller that is part of - BCM63138 SoC. The same hardware block is known to be also used - in BCM4908, BCM6848, BCM6858, BCM63148, BCM63381 and BCM68360. -+ -+ If compiled as module it will be called leds-bcm63138. diff --git a/target/linux/generic/backport-5.10/846-v6.0-0003-leds-leds-bcm63138-get-rid-of-LED_OFF.patch b/target/linux/generic/backport-5.10/846-v6.0-0003-leds-leds-bcm63138-get-rid-of-LED_OFF.patch deleted file mode 100644 index e125a54613..0000000000 --- a/target/linux/generic/backport-5.10/846-v6.0-0003-leds-leds-bcm63138-get-rid-of-LED_OFF.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 92cfc71ee2ddfb499ed53e21b28bdf8739bc70bc Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Sun, 17 Jul 2022 14:42:48 +0200 -Subject: [PATCH] leds: leds-bcm63138: get rid of LED_OFF -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The whole "enum led_brightness" is marked as obsolete. Replace it with a -(non-)zero check. - -Reported-by: Pavel Machek -Signed-off-by: Rafał Miłecki -Signed-off-by: Pavel Machek ---- - drivers/leds/blink/leds-bcm63138.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/leds/blink/leds-bcm63138.c -+++ b/drivers/leds/blink/leds-bcm63138.c -@@ -113,8 +113,7 @@ static void bcm63138_leds_enable_led(str - { - u32 bit = BIT(led->pin); - -- bcm63138_leds_update_bits(leds, BCM63138_SW_DATA, bit, -- value == LED_OFF ? 0 : bit); -+ bcm63138_leds_update_bits(leds, BCM63138_SW_DATA, bit, value ? bit : 0); - } - - /* diff --git a/target/linux/generic/backport-5.10/850-v5.17-0001-PCI-pci-bridge-emul-Add-description-for-class_revisi.patch b/target/linux/generic/backport-5.10/850-v5.17-0001-PCI-pci-bridge-emul-Add-description-for-class_revisi.patch deleted file mode 100644 index 19a4be2a9d..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0001-PCI-pci-bridge-emul-Add-description-for-class_revisi.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 9319230ac147067652b58fe849ffe0ceec098665 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:03 +0100 -Subject: [PATCH] PCI: pci-bridge-emul: Add description for class_revision - field -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The current assignment to the class_revision member - - class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16); - -can make the reader think that class is at high 16 bits of the member and -revision at low 16 bits. - -In reality, class is at high 24 bits, but the class for PCI Bridge Normal -Decode is PCI_CLASS_BRIDGE_PCI << 8. - -Change the assignment and add a comment to make this clearer. - -Link: https://lore.kernel.org/r/20211130172913.9727-2-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/pci-bridge-emul.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/pci/pci-bridge-emul.c -+++ b/drivers/pci/pci-bridge-emul.c -@@ -284,7 +284,11 @@ int pci_bridge_emul_init(struct pci_brid - { - BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END); - -- bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16); -+ /* -+ * class_revision: Class is high 24 bits and revision is low 8 bit of this member, -+ * while class for PCI Bridge Normal Decode has the 24-bit value: PCI_CLASS_BRIDGE_PCI << 8 -+ */ -+ bridge->conf.class_revision |= cpu_to_le32((PCI_CLASS_BRIDGE_PCI << 8) << 8); - bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE; - bridge->conf.cache_line_size = 0x10; - bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST); diff --git a/target/linux/generic/backport-5.10/850-v5.17-0002-PCI-pci-bridge-emul-Add-definitions-for-missing-capa.patch b/target/linux/generic/backport-5.10/850-v5.17-0002-PCI-pci-bridge-emul-Add-definitions-for-missing-capa.patch deleted file mode 100644 index 3dd82710e6..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0002-PCI-pci-bridge-emul-Add-definitions-for-missing-capa.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 8ea673a8b30b4a32516b8adabb15e2a68ff02ec8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:04 +0100 -Subject: [PATCH] PCI: pci-bridge-emul: Add definitions for missing - capabilities registers -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -pci-bridge-emul driver already allocates buffer for capabilities up to the -PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these -registers. Add these missing definitions. - -Link: https://lore.kernel.org/r/20211130172913.9727-3-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/pci-bridge-emul.c | 43 +++++++++++++++++++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/drivers/pci/pci-bridge-emul.c -+++ b/drivers/pci/pci-bridge-emul.c -@@ -270,6 +270,49 @@ struct pci_bridge_reg_behavior pcie_cap_ - .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING, - .w1c = PCI_EXP_RTSTA_PME, - }, -+ -+ [PCI_EXP_DEVCAP2 / 4] = { -+ /* -+ * Device capabilities 2 register has reserved bits [30:27]. -+ * Also bits [26:24] are reserved for non-upstream ports. -+ */ -+ .ro = BIT(31) | GENMASK(23, 0), -+ }, -+ -+ [PCI_EXP_DEVCTL2 / 4] = { -+ /* -+ * Device control 2 register is RW. Bit 11 is reserved for -+ * non-upstream ports. -+ * -+ * Device status 2 register is reserved. -+ */ -+ .rw = GENMASK(15, 12) | GENMASK(10, 0), -+ }, -+ -+ [PCI_EXP_LNKCAP2 / 4] = { -+ /* Link capabilities 2 register has reserved bits [30:25] and 0. */ -+ .ro = BIT(31) | GENMASK(24, 1), -+ }, -+ -+ [PCI_EXP_LNKCTL2 / 4] = { -+ /* -+ * Link control 2 register is RW. -+ * -+ * Link status 2 register has bits 5, 15 W1C; -+ * bits 10, 11 reserved and others are RO. -+ */ -+ .rw = GENMASK(15, 0), -+ .w1c = (BIT(15) | BIT(5)) << 16, -+ .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16, -+ }, -+ -+ [PCI_EXP_SLTCAP2 / 4] = { -+ /* Slot capabilities 2 register is reserved. */ -+ }, -+ -+ [PCI_EXP_SLTCTL2 / 4] = { -+ /* Both Slot control 2 and Slot status 2 registers are reserved. */ -+ }, - }; - - /* diff --git a/target/linux/generic/backport-5.10/850-v5.17-0003-PCI-aardvark-Add-support-for-DEVCAP2-DEVCTL2-LNKCAP2.patch b/target/linux/generic/backport-5.10/850-v5.17-0003-PCI-aardvark-Add-support-for-DEVCAP2-DEVCTL2-LNKCAP2.patch deleted file mode 100644 index 4d1135bf6c..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0003-PCI-aardvark-Add-support-for-DEVCAP2-DEVCTL2-LNKCAP2.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 1d3e170344dff2cef8827db6c09909b78cbc11d7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:05 +0100 -Subject: [PATCH] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and - LNKCTL2 registers on emulated bridge -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -PCI aardvark hardware supports access to DEVCAP2, DEVCTL2, LNKCAP2 and -LNKCTL2 configuration registers of PCIe core via PCIE_CORE_PCIEXP_CAP. -Export them via emulated software root bridge. - -Link: https://lore.kernel.org/r/20211130172913.9727-4-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/pci-aardvark.c | 15 +++++++++++---- - 1 file changed, 11 insertions(+), 4 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -885,8 +885,13 @@ advk_pci_bridge_emul_pcie_conf_read(stru - - case PCI_EXP_DEVCAP: - case PCI_EXP_DEVCTL: -+ case PCI_EXP_DEVCAP2: -+ case PCI_EXP_DEVCTL2: -+ case PCI_EXP_LNKCAP2: -+ case PCI_EXP_LNKCTL2: - *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); - return PCI_BRIDGE_EMUL_HANDLED; -+ - default: - return PCI_BRIDGE_EMUL_NOT_HANDLED; - } -@@ -900,10 +905,6 @@ advk_pci_bridge_emul_pcie_conf_write(str - struct advk_pcie *pcie = bridge->data; - - switch (reg) { -- case PCI_EXP_DEVCTL: -- advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); -- break; -- - case PCI_EXP_LNKCTL: - advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); - if (new & PCI_EXP_LNKCTL_RL) -@@ -925,6 +926,12 @@ advk_pci_bridge_emul_pcie_conf_write(str - advk_writel(pcie, new, PCIE_ISR0_REG); - break; - -+ case PCI_EXP_DEVCTL: -+ case PCI_EXP_DEVCTL2: -+ case PCI_EXP_LNKCTL2: -+ advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); -+ break; -+ - default: - break; - } diff --git a/target/linux/generic/backport-5.10/850-v5.17-0005-PCI-aardvark-Comment-actions-in-driver-remove-method.patch b/target/linux/generic/backport-5.10/850-v5.17-0005-PCI-aardvark-Comment-actions-in-driver-remove-method.patch deleted file mode 100644 index b724422d40..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0005-PCI-aardvark-Comment-actions-in-driver-remove-method.patch +++ /dev/null @@ -1,34 +0,0 @@ -From a4ca7948e1d47275f8f3e5023243440c40561916 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:07 +0100 -Subject: [PATCH] PCI: aardvark: Comment actions in driver remove method -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add two more comments into the advk_pcie_remove() method. - -Link: https://lore.kernel.org/r/20211130172913.9727-6-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/pci-aardvark.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1692,11 +1692,13 @@ static int advk_pcie_remove(struct platf - struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); - int i; - -+ /* Remove PCI bus with all devices */ - pci_lock_rescan_remove(); - pci_stop_root_bus(bridge->bus); - pci_remove_root_bus(bridge->bus); - pci_unlock_rescan_remove(); - -+ /* Remove IRQ domains */ - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); - diff --git a/target/linux/generic/backport-5.10/850-v5.17-0006-PCI-aardvark-Disable-bus-mastering-when-unbinding-dr.patch b/target/linux/generic/backport-5.10/850-v5.17-0006-PCI-aardvark-Disable-bus-mastering-when-unbinding-dr.patch deleted file mode 100644 index c8d5e391b8..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0006-PCI-aardvark-Disable-bus-mastering-when-unbinding-dr.patch +++ /dev/null @@ -1,41 +0,0 @@ -From a46f2f6dd4093438d9615dfbf5c0fea2a9835dba Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:08 +0100 -Subject: [PATCH] PCI: aardvark: Disable bus mastering when unbinding driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Ensure that after driver unbind PCIe cards are not able to forward -memory and I/O requests in the upstream direction. - -Link: https://lore.kernel.org/r/20211130172913.9727-7-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/pci-aardvark.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1690,6 +1690,7 @@ static int advk_pcie_remove(struct platf - { - struct advk_pcie *pcie = platform_get_drvdata(pdev); - struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); -+ u32 val; - int i; - - /* Remove PCI bus with all devices */ -@@ -1698,6 +1699,11 @@ static int advk_pcie_remove(struct platf - pci_remove_root_bus(bridge->bus); - pci_unlock_rescan_remove(); - -+ /* Disable Root Bridge I/O space, memory space and bus mastering */ -+ val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); -+ val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); -+ advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG); -+ - /* Remove IRQ domains */ - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); diff --git a/target/linux/generic/backport-5.10/850-v5.17-0007-PCI-aardvark-Mask-all-interrupts-when-unbinding-driv.patch b/target/linux/generic/backport-5.10/850-v5.17-0007-PCI-aardvark-Mask-all-interrupts-when-unbinding-driv.patch deleted file mode 100644 index 05d350e922..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0007-PCI-aardvark-Mask-all-interrupts-when-unbinding-driv.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 13bcdf07cb2ecff5d45d2c141df2539b15211448 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:09 +0100 -Subject: [PATCH] PCI: aardvark: Mask all interrupts when unbinding driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Ensure that no interrupt can be triggered after driver unbind. - -Link: https://lore.kernel.org/r/20211130172913.9727-8-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/pci-aardvark.c | 21 +++++++++++++++++++++ - 1 file changed, 21 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1704,6 +1704,27 @@ static int advk_pcie_remove(struct platf - val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG); - -+ /* Disable MSI */ -+ val = advk_readl(pcie, PCIE_CORE_CTRL2_REG); -+ val &= ~PCIE_CORE_CTRL2_MSI_ENABLE; -+ advk_writel(pcie, val, PCIE_CORE_CTRL2_REG); -+ -+ /* Clear MSI address */ -+ advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG); -+ advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG); -+ -+ /* Mask all interrupts */ -+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); -+ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); -+ advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); -+ advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG); -+ -+ /* Clear all interrupts */ -+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); -+ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); -+ advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); -+ advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); -+ - /* Remove IRQ domains */ - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); diff --git a/target/linux/generic/backport-5.10/850-v5.17-0008-PCI-aardvark-Fix-memory-leak-in-driver-unbind.patch b/target/linux/generic/backport-5.10/850-v5.17-0008-PCI-aardvark-Fix-memory-leak-in-driver-unbind.patch deleted file mode 100644 index 435acda1e2..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0008-PCI-aardvark-Fix-memory-leak-in-driver-unbind.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 2f040a17f5061457ae95035326d3159eddc1e5cc Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:10 +0100 -Subject: [PATCH] PCI: aardvark: Fix memory leak in driver unbind -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Free config space for emulated root bridge when unbinding driver to fix -memory leak. Do it after disabling and masking all interrupts, since -aardvark interrupt handler accesses config space of emulated root -bridge. - -Link: https://lore.kernel.org/r/20211130172913.9727-9-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/pci-aardvark.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1729,6 +1729,9 @@ static int advk_pcie_remove(struct platf - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); - -+ /* Free config space for emulated root bridge */ -+ pci_bridge_emul_cleanup(&pcie->bridge); -+ - /* Disable outbound address windows mapping */ - for (i = 0; i < OB_WIN_COUNT; i++) - advk_pcie_disable_ob_win(pcie, i); diff --git a/target/linux/generic/backport-5.10/850-v5.17-0009-PCI-aardvark-Assert-PERST-when-unbinding-driver.patch b/target/linux/generic/backport-5.10/850-v5.17-0009-PCI-aardvark-Assert-PERST-when-unbinding-driver.patch deleted file mode 100644 index c5dfdd3923..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0009-PCI-aardvark-Assert-PERST-when-unbinding-driver.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 1f54391be8ce0c981d312cb93acdc5608def576a Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:11 +0100 -Subject: [PATCH] PCI: aardvark: Assert PERST# when unbinding driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Put the PCIe card into reset by asserting PERST# signal when unbinding -driver. It doesn't make sense to leave the card working if it can't -communicate with the host. This should also save some power. - -Link: https://lore.kernel.org/r/20211130172913.9727-10-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/pci-aardvark.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1732,6 +1732,10 @@ static int advk_pcie_remove(struct platf - /* Free config space for emulated root bridge */ - pci_bridge_emul_cleanup(&pcie->bridge); - -+ /* Assert PERST# signal which prepares PCIe card for power down */ -+ if (pcie->reset_gpio) -+ gpiod_set_value_cansleep(pcie->reset_gpio, 1); -+ - /* Disable outbound address windows mapping */ - for (i = 0; i < OB_WIN_COUNT; i++) - advk_pcie_disable_ob_win(pcie, i); diff --git a/target/linux/generic/backport-5.10/850-v5.17-0010-PCI-aardvark-Disable-link-training-when-unbinding-dr.patch b/target/linux/generic/backport-5.10/850-v5.17-0010-PCI-aardvark-Disable-link-training-when-unbinding-dr.patch deleted file mode 100644 index 7f4e2575f5..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0010-PCI-aardvark-Disable-link-training-when-unbinding-dr.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 759dec2e3dfdbd261c41d2279f04f2351c971a49 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:12 +0100 -Subject: [PATCH] PCI: aardvark: Disable link training when unbinding driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Disable link training circuit in driver unbind sequence. We want to -leave link training in the same state as it was before the driver was -probed. - -Link: https://lore.kernel.org/r/20211130172913.9727-11-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/pci-aardvark.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1736,6 +1736,11 @@ static int advk_pcie_remove(struct platf - if (pcie->reset_gpio) - gpiod_set_value_cansleep(pcie->reset_gpio, 1); - -+ /* Disable link training */ -+ val = advk_readl(pcie, PCIE_CORE_CTRL0_REG); -+ val &= ~LINK_TRAINING_EN; -+ advk_writel(pcie, val, PCIE_CORE_CTRL0_REG); -+ - /* Disable outbound address windows mapping */ - for (i = 0; i < OB_WIN_COUNT; i++) - advk_pcie_disable_ob_win(pcie, i); diff --git a/target/linux/generic/backport-5.10/850-v5.17-0011-PCI-aardvark-Disable-common-PHY-when-unbinding-drive.patch b/target/linux/generic/backport-5.10/850-v5.17-0011-PCI-aardvark-Disable-common-PHY-when-unbinding-drive.patch deleted file mode 100644 index 495c34aa9e..0000000000 --- a/target/linux/generic/backport-5.10/850-v5.17-0011-PCI-aardvark-Disable-common-PHY-when-unbinding-drive.patch +++ /dev/null @@ -1,30 +0,0 @@ -From fdbbe242c15a8f2cd0e3ad8a56cd0a447b771d0d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Tue, 30 Nov 2021 18:29:13 +0100 -Subject: [PATCH] PCI: aardvark: Disable common PHY when unbinding driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Disable the PCIe PHY when unbinding driver. This should save some power. - -Link: https://lore.kernel.org/r/20211130172913.9727-12-kabel@kernel.org -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Signed-off-by: Lorenzo Pieralisi ---- - drivers/pci/controller/pci-aardvark.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1745,6 +1745,9 @@ static int advk_pcie_remove(struct platf - for (i = 0; i < OB_WIN_COUNT; i++) - advk_pcie_disable_ob_win(pcie, i); - -+ /* Disable phy */ -+ advk_pcie_disable_phy(pcie); -+ - return 0; - } - diff --git a/target/linux/generic/backport-5.10/851-v5.15-0001-phy-marvell-phy-mvebu-a3700-comphy-Rename-HS-SGMMI-t.patch b/target/linux/generic/backport-5.10/851-v5.15-0001-phy-marvell-phy-mvebu-a3700-comphy-Rename-HS-SGMMI-t.patch deleted file mode 100644 index 4f867724ac..0000000000 --- a/target/linux/generic/backport-5.10/851-v5.15-0001-phy-marvell-phy-mvebu-a3700-comphy-Rename-HS-SGMMI-t.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 40da06da15c1718b02072687bbfb2d08f5eb9399 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 27 Aug 2021 11:27:52 +0200 -Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Rename HS-SGMMI to - 2500Base-X -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Comphy phy mode 0x3 is incorrectly named. It is not SGMII but rather -2500Base-X mode which runs at 3.125 Gbps speed. - -Rename macro names and comments to 2500Base-X. - -Signed-off-by: Pali Rohár -Fixes: 9695375a3f4a ("phy: add A3700 COMPHY support") -Signed-off-by: David S. Miller ---- - drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - ---- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c -+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c -@@ -29,7 +29,7 @@ - - #define COMPHY_FW_MODE_SATA 0x1 - #define COMPHY_FW_MODE_SGMII 0x2 --#define COMPHY_FW_MODE_HS_SGMII 0x3 -+#define COMPHY_FW_MODE_2500BASEX 0x3 - #define COMPHY_FW_MODE_USB3H 0x4 - #define COMPHY_FW_MODE_USB3D 0x5 - #define COMPHY_FW_MODE_PCIE 0x6 -@@ -40,7 +40,7 @@ - - #define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */ - #define COMPHY_FW_SPEED_2_5G 1 --#define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */ -+#define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */ - #define COMPHY_FW_SPEED_5G 3 - #define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */ - #define COMPHY_FW_SPEED_6G 5 -@@ -84,14 +84,14 @@ static const struct mvebu_a3700_comphy_c - MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1, - COMPHY_FW_MODE_SGMII), - MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1, -- COMPHY_FW_MODE_HS_SGMII), -+ COMPHY_FW_MODE_2500BASEX), - /* lane 1 */ - MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0, - COMPHY_FW_MODE_PCIE), - MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0, - COMPHY_FW_MODE_SGMII), - MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0, -- COMPHY_FW_MODE_HS_SGMII), -+ COMPHY_FW_MODE_2500BASEX), - /* lane 2 */ - MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0, - COMPHY_FW_MODE_SATA), -@@ -205,7 +205,7 @@ static int mvebu_a3700_comphy_power_on(s - COMPHY_FW_SPEED_1_25G); - break; - case PHY_INTERFACE_MODE_2500BASEX: -- dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n", -+ dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n", - lane->id); - fw_param = COMPHY_FW_NET(fw_mode, lane->port, - COMPHY_FW_SPEED_3_125G); diff --git a/target/linux/generic/backport-5.10/851-v5.15-0002-phy-marvell-phy-mvebu-a3700-comphy-Remove-unsupporte.patch b/target/linux/generic/backport-5.10/851-v5.15-0002-phy-marvell-phy-mvebu-a3700-comphy-Remove-unsupporte.patch deleted file mode 100644 index 99f56f1c57..0000000000 --- a/target/linux/generic/backport-5.10/851-v5.15-0002-phy-marvell-phy-mvebu-a3700-comphy-Remove-unsupporte.patch +++ /dev/null @@ -1,40 +0,0 @@ -From e1dbe9ecf621b6f71f3d2df3e50731d583f3d27f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 27 Aug 2021 11:27:53 +0200 -Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove unsupported - modes -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Armada 3700 does not support RXAUI, XFI and neither SFI. Remove unused -macros for these unsupported modes. - -Signed-off-by: Pali Rohár -Fixes: 9695375a3f4a ("phy: add A3700 COMPHY support") -Signed-off-by: David S. Miller ---- - drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 6 ------ - 1 file changed, 6 deletions(-) - ---- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c -+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c -@@ -33,18 +33,12 @@ - #define COMPHY_FW_MODE_USB3H 0x4 - #define COMPHY_FW_MODE_USB3D 0x5 - #define COMPHY_FW_MODE_PCIE 0x6 --#define COMPHY_FW_MODE_RXAUI 0x7 --#define COMPHY_FW_MODE_XFI 0x8 --#define COMPHY_FW_MODE_SFI 0x9 - #define COMPHY_FW_MODE_USB3 0xa - - #define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */ - #define COMPHY_FW_SPEED_2_5G 1 - #define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */ - #define COMPHY_FW_SPEED_5G 3 --#define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */ --#define COMPHY_FW_SPEED_6G 5 --#define COMPHY_FW_SPEED_10_3125G 6 /* XFI 10G */ - #define COMPHY_FW_SPEED_MAX 0x3F - - #define COMPHY_FW_MODE(mode) ((mode) << 12) diff --git a/target/linux/generic/backport-5.10/860-v5.17-MIPS-ath79-drop-_machine_restart-again.patch b/target/linux/generic/backport-5.10/860-v5.17-MIPS-ath79-drop-_machine_restart-again.patch deleted file mode 100644 index 971562a8f7..0000000000 --- a/target/linux/generic/backport-5.10/860-v5.17-MIPS-ath79-drop-_machine_restart-again.patch +++ /dev/null @@ -1,49 +0,0 @@ -From d3115128bdafb62628ab41861a4f06f6d02ac320 Mon Sep 17 00:00:00 2001 -From: Lech Perczak -Date: Mon, 10 Jan 2022 23:48:44 +0100 -Subject: MIPS: ath79: drop _machine_restart again - -Commit 81424d0ad0d4 ("MIPS: ath79: Use the reset controller to restart -OF machines") removed setup of _machine_restart on OF machines to use -reset handler in reset controller driver. -While removing remnants of non-OF machines in commit 3a77e0d75eed -("MIPS: ath79: drop machfiles"), this was introduced again, making it -impossible to use additional restart handlers registered through device -tree. Drop setting _machine_restart altogether, and ath79_restart -function, which is no longer used after this. - -Fixes: 3a77e0d75eed ("MIPS: ath79: drop machfiles") -Cc: John Crispin -Cc: Florian Fainelli -Signed-off-by: Lech Perczak -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/ath79/setup.c | 10 ---------- - 1 file changed, 10 deletions(-) - ---- a/arch/mips/ath79/setup.c -+++ b/arch/mips/ath79/setup.c -@@ -34,15 +34,6 @@ - - static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; - --static void ath79_restart(char *command) --{ -- local_irq_disable(); -- ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); -- for (;;) -- if (cpu_wait) -- cpu_wait(); --} -- - static void ath79_halt(void) - { - while (1) -@@ -233,7 +224,6 @@ void __init plat_mem_setup(void) - - detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); - -- _machine_restart = ath79_restart; - _machine_halt = ath79_halt; - pm_power_off = ath79_halt; - } diff --git a/target/linux/generic/backport-5.10/870-hwmon-next-hwmon-lm70-Add-ti-tmp125-support.patch b/target/linux/generic/backport-5.10/870-hwmon-next-hwmon-lm70-Add-ti-tmp125-support.patch deleted file mode 100644 index fabf177628..0000000000 --- a/target/linux/generic/backport-5.10/870-hwmon-next-hwmon-lm70-Add-ti-tmp125-support.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 31d8f414e1596ba54a4315418e4c0086fda9e428 Mon Sep 17 00:00:00 2001 -From: Christian Lamparter -Date: Fri, 18 Feb 2022 10:06:43 +0100 -Subject: hwmon: (lm70) Add ti,tmp125 support - -The TMP125 is a 2 degree Celsius accurate Digital -Temperature Sensor with a SPI interface. - -The temperature register is a 16-bit, read-only register. -The MSB (Bit 15) is a leading zero and never set. Bits 14 -to 5 are the 1+9 temperature data bits in a two's -complement format. Bits 4 to 0 are useless copies of -Bit 5 value and therefore ignored. - -Signed-off-by: Christian Lamparter -Link: https://lore.kernel.org/r/43b19cbd4e7f51e9509e561b02b5d8d0e7079fac.1645175187.git.chunkeey@gmail.com -Signed-off-by: Guenter Roeck ---- ---- a/drivers/hwmon/lm70.c -+++ b/drivers/hwmon/lm70.c -@@ -34,6 +34,7 @@ - #define LM70_CHIP_LM71 2 /* NS LM71 */ - #define LM70_CHIP_LM74 3 /* NS LM74 */ - #define LM70_CHIP_TMP122 4 /* TI TMP122/TMP124 */ -+#define LM70_CHIP_TMP125 5 /* TI TMP125 */ - - struct lm70 { - struct spi_device *spi; -@@ -87,6 +88,12 @@ static ssize_t temp1_input_show(struct d - * LM71: - * 14 bits of 2's complement data, discard LSB 2 bits, - * resolution 0.0312 degrees celsius. -+ * -+ * TMP125: -+ * MSB/D15 is a leading zero. D14 is the sign-bit. This is -+ * followed by 9 temperature bits (D13..D5) in 2's complement -+ * data format with a resolution of 0.25 degrees celsius per unit. -+ * LSB 5 bits (D4..D0) share the same value as D5 and get discarded. - */ - switch (p_lm70->chip) { - case LM70_CHIP_LM70: -@@ -102,6 +109,10 @@ static ssize_t temp1_input_show(struct d - case LM70_CHIP_LM71: - val = ((int)raw / 4) * 3125 / 100; - break; -+ -+ case LM70_CHIP_TMP125: -+ val = (sign_extend32(raw, 14) / 32) * 250; -+ break; - } - - status = sprintf(buf, "%d\n", val); /* millidegrees Celsius */ -@@ -136,6 +147,10 @@ static const struct of_device_id lm70_of - .data = (void *) LM70_CHIP_TMP122, - }, - { -+ .compatible = "ti,tmp125", -+ .data = (void *) LM70_CHIP_TMP125, -+ }, -+ { - .compatible = "ti,lm71", - .data = (void *) LM70_CHIP_LM71, - }, -@@ -184,6 +199,7 @@ static const struct spi_device_id lm70_i - { "lm70", LM70_CHIP_LM70 }, - { "tmp121", LM70_CHIP_TMP121 }, - { "tmp122", LM70_CHIP_TMP122 }, -+ { "tmp125", LM70_CHIP_TMP125 }, - { "lm71", LM70_CHIP_LM71 }, - { "lm74", LM70_CHIP_LM74 }, - { }, diff --git a/target/linux/generic/backport-5.10/871-v5.12-hwmon-add-Texas-Instruments-TPS23861-driver.patch b/target/linux/generic/backport-5.10/871-v5.12-hwmon-add-Texas-Instruments-TPS23861-driver.patch deleted file mode 100644 index 8c0329960c..0000000000 --- a/target/linux/generic/backport-5.10/871-v5.12-hwmon-add-Texas-Instruments-TPS23861-driver.patch +++ /dev/null @@ -1,711 +0,0 @@ -From 97c95dbbba64dbd6e98e033e396695f328033966 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 21 Jan 2021 14:44:33 +0100 -Subject: [PATCH 1/4] hwmon: add Texas Instruments TPS23861 driver - -Add basic monitoring support as well as port on/off control for Texas -Instruments TPS23861 PoE PSE IC. - -Signed-off-by: Robert Marko -Cc: Luka Perkov -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/20210121134434.2782405-2-robert.marko@sartura.hr -Signed-off-by: Guenter Roeck ---- - Documentation/hwmon/index.rst | 1 + - Documentation/hwmon/tps23861.rst | 41 +++ - drivers/hwmon/Kconfig | 11 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/tps23861.c | 601 +++++++++++++++++++++++++++++++ - 5 files changed, 655 insertions(+) - create mode 100644 Documentation/hwmon/tps23861.rst - create mode 100644 drivers/hwmon/tps23861.c - ---- a/Documentation/hwmon/index.rst -+++ b/Documentation/hwmon/index.rst -@@ -172,6 +172,7 @@ Hardware Monitoring Kernel Drivers - tmp401 - tmp421 - tmp513 -+ tps23861 - tps40422 - tps53679 - twl4030-madc-hwmon ---- /dev/null -+++ b/Documentation/hwmon/tps23861.rst -@@ -0,0 +1,41 @@ -+.. SPDX-License-Identifier: GPL-2.0-only -+ -+Kernel driver tps23861 -+====================== -+ -+Supported chips: -+ * Texas Instruments TPS23861 -+ -+ Prefix: 'tps23861' -+ -+ Datasheet: https://www.ti.com/lit/gpn/tps23861 -+ -+Author: Robert Marko -+ -+Description -+----------- -+ -+This driver supports hardware monitoring for Texas Instruments TPS23861 PoE PSE. -+ -+TPS23861 is a quad port IEEE802.3at PSE controller with optional I2C control -+and monitoring capabilities. -+ -+TPS23861 offers three modes of operation: Auto, Semi-Auto and Manual. -+ -+This driver only supports the Auto mode of operation providing monitoring -+as well as enabling/disabling the four ports. -+ -+Sysfs entries -+------------- -+ -+======================= ===================================================================== -+in[0-3]_input Voltage on ports [1-4] -+in[0-3]_label "Port[1-4]" -+in4_input IC input voltage -+in4_label "Input" -+temp1_input IC die temperature -+temp1_label "Die" -+curr[1-4]_input Current on ports [1-4] -+in[1-4]_label "Port[1-4]" -+in[0-3]_enable Enable/disable ports [1-4] -+======================= ===================================================================== ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -1103,6 +1103,17 @@ config SENSORS_TC654 - This driver can also be built as a module. If so, the module - will be called tc654. - -+config SENSORS_TPS23861 -+ tristate "Texas Instruments TPS23861 PoE PSE" -+ depends on I2C -+ select REGMAP_I2C -+ help -+ If you say yes here you get support for Texas Instruments -+ TPS23861 802.3at PoE PSE chips. -+ -+ This driver can also be built as a module. If so, the module -+ will be called tps23861. -+ - config SENSORS_MENF21BMC_HWMON - tristate "MEN 14F021P00 BMC Hardware Monitoring" - depends on MFD_MENF21BMC ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -141,6 +141,7 @@ obj-$(CONFIG_SENSORS_MAX31790) += max317 - obj-$(CONFIG_SENSORS_MC13783_ADC)+= mc13783-adc.o - obj-$(CONFIG_SENSORS_MCP3021) += mcp3021.o - obj-$(CONFIG_SENSORS_TC654) += tc654.o -+obj-$(CONFIG_SENSORS_TPS23861) += tps23861.o - obj-$(CONFIG_SENSORS_MLXREG_FAN) += mlxreg-fan.o - obj-$(CONFIG_SENSORS_MENF21BMC_HWMON) += menf21bmc_hwmon.o - obj-$(CONFIG_SENSORS_MR75203) += mr75203.o ---- /dev/null -+++ b/drivers/hwmon/tps23861.c -@@ -0,0 +1,601 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2020 Sartura Ltd. -+ * -+ * Driver for the TI TPS23861 PoE PSE. -+ * -+ * Author: Robert Marko -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TEMPERATURE 0x2c -+#define INPUT_VOLTAGE_LSB 0x2e -+#define INPUT_VOLTAGE_MSB 0x2f -+#define PORT_1_CURRENT_LSB 0x30 -+#define PORT_1_CURRENT_MSB 0x31 -+#define PORT_1_VOLTAGE_LSB 0x32 -+#define PORT_1_VOLTAGE_MSB 0x33 -+#define PORT_2_CURRENT_LSB 0x34 -+#define PORT_2_CURRENT_MSB 0x35 -+#define PORT_2_VOLTAGE_LSB 0x36 -+#define PORT_2_VOLTAGE_MSB 0x37 -+#define PORT_3_CURRENT_LSB 0x38 -+#define PORT_3_CURRENT_MSB 0x39 -+#define PORT_3_VOLTAGE_LSB 0x3a -+#define PORT_3_VOLTAGE_MSB 0x3b -+#define PORT_4_CURRENT_LSB 0x3c -+#define PORT_4_CURRENT_MSB 0x3d -+#define PORT_4_VOLTAGE_LSB 0x3e -+#define PORT_4_VOLTAGE_MSB 0x3f -+#define PORT_N_CURRENT_LSB_OFFSET 0x04 -+#define PORT_N_VOLTAGE_LSB_OFFSET 0x04 -+#define VOLTAGE_CURRENT_MASK GENMASK(13, 0) -+#define PORT_1_RESISTANCE_LSB 0x60 -+#define PORT_1_RESISTANCE_MSB 0x61 -+#define PORT_2_RESISTANCE_LSB 0x62 -+#define PORT_2_RESISTANCE_MSB 0x63 -+#define PORT_3_RESISTANCE_LSB 0x64 -+#define PORT_3_RESISTANCE_MSB 0x65 -+#define PORT_4_RESISTANCE_LSB 0x66 -+#define PORT_4_RESISTANCE_MSB 0x67 -+#define PORT_N_RESISTANCE_LSB_OFFSET 0x02 -+#define PORT_RESISTANCE_MASK GENMASK(13, 0) -+#define PORT_RESISTANCE_RSN_MASK GENMASK(15, 14) -+#define PORT_RESISTANCE_RSN_OTHER 0 -+#define PORT_RESISTANCE_RSN_LOW 1 -+#define PORT_RESISTANCE_RSN_OPEN 2 -+#define PORT_RESISTANCE_RSN_SHORT 3 -+#define PORT_1_STATUS 0x0c -+#define PORT_2_STATUS 0x0d -+#define PORT_3_STATUS 0x0e -+#define PORT_4_STATUS 0x0f -+#define PORT_STATUS_CLASS_MASK GENMASK(7, 4) -+#define PORT_STATUS_DETECT_MASK GENMASK(3, 0) -+#define PORT_CLASS_UNKNOWN 0 -+#define PORT_CLASS_1 1 -+#define PORT_CLASS_2 2 -+#define PORT_CLASS_3 3 -+#define PORT_CLASS_4 4 -+#define PORT_CLASS_RESERVED 5 -+#define PORT_CLASS_0 6 -+#define PORT_CLASS_OVERCURRENT 7 -+#define PORT_CLASS_MISMATCH 8 -+#define PORT_DETECT_UNKNOWN 0 -+#define PORT_DETECT_SHORT 1 -+#define PORT_DETECT_RESERVED 2 -+#define PORT_DETECT_RESISTANCE_LOW 3 -+#define PORT_DETECT_RESISTANCE_OK 4 -+#define PORT_DETECT_RESISTANCE_HIGH 5 -+#define PORT_DETECT_OPEN_CIRCUIT 6 -+#define PORT_DETECT_RESERVED_2 7 -+#define PORT_DETECT_MOSFET_FAULT 8 -+#define PORT_DETECT_LEGACY 9 -+/* Measurment beyond clamp voltage */ -+#define PORT_DETECT_CAPACITANCE_INVALID_BEYOND 10 -+/* Insufficient voltage delta */ -+#define PORT_DETECT_CAPACITANCE_INVALID_DELTA 11 -+#define PORT_DETECT_CAPACITANCE_OUT_OF_RANGE 12 -+#define POE_PLUS 0x40 -+#define OPERATING_MODE 0x12 -+#define OPERATING_MODE_OFF 0 -+#define OPERATING_MODE_MANUAL 1 -+#define OPERATING_MODE_SEMI 2 -+#define OPERATING_MODE_AUTO 3 -+#define OPERATING_MODE_PORT_1_MASK GENMASK(1, 0) -+#define OPERATING_MODE_PORT_2_MASK GENMASK(3, 2) -+#define OPERATING_MODE_PORT_3_MASK GENMASK(5, 4) -+#define OPERATING_MODE_PORT_4_MASK GENMASK(7, 6) -+ -+#define DETECT_CLASS_RESTART 0x18 -+#define POWER_ENABLE 0x19 -+#define TPS23861_NUM_PORTS 4 -+ -+#define TEMPERATURE_LSB 652 /* 0.652 degrees Celsius */ -+#define VOLTAGE_LSB 3662 /* 3.662 mV */ -+#define SHUNT_RESISTOR_DEFAULT 255000 /* 255 mOhm */ -+#define CURRENT_LSB_255 62260 /* 62.260 uA */ -+#define CURRENT_LSB_250 61039 /* 61.039 uA */ -+#define RESISTANCE_LSB 110966 /* 11.0966 Ohm*/ -+#define RESISTANCE_LSB_LOW 157216 /* 15.7216 Ohm*/ -+ -+struct tps23861_data { -+ struct regmap *regmap; -+ u32 shunt_resistor; -+ struct i2c_client *client; -+ struct dentry *debugfs_dir; -+}; -+ -+static struct regmap_config tps23861_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+}; -+ -+static int tps23861_read_temp(struct tps23861_data *data, long *val) -+{ -+ unsigned int regval; -+ int err; -+ -+ err = regmap_read(data->regmap, TEMPERATURE, ®val); -+ if (err < 0) -+ return err; -+ -+ *val = (regval * TEMPERATURE_LSB) - 20000; -+ -+ return 0; -+} -+ -+static int tps23861_read_voltage(struct tps23861_data *data, int channel, -+ long *val) -+{ -+ unsigned int regval; -+ int err; -+ -+ if (channel < TPS23861_NUM_PORTS) { -+ err = regmap_bulk_read(data->regmap, -+ PORT_1_VOLTAGE_LSB + channel * PORT_N_VOLTAGE_LSB_OFFSET, -+ ®val, 2); -+ } else { -+ err = regmap_bulk_read(data->regmap, -+ INPUT_VOLTAGE_LSB, -+ ®val, 2); -+ } -+ if (err < 0) -+ return err; -+ -+ *val = (FIELD_GET(VOLTAGE_CURRENT_MASK, regval) * VOLTAGE_LSB) / 1000; -+ -+ return 0; -+} -+ -+static int tps23861_read_current(struct tps23861_data *data, int channel, -+ long *val) -+{ -+ unsigned int current_lsb; -+ unsigned int regval; -+ int err; -+ -+ if (data->shunt_resistor == SHUNT_RESISTOR_DEFAULT) -+ current_lsb = CURRENT_LSB_255; -+ else -+ current_lsb = CURRENT_LSB_250; -+ -+ err = regmap_bulk_read(data->regmap, -+ PORT_1_CURRENT_LSB + channel * PORT_N_CURRENT_LSB_OFFSET, -+ ®val, 2); -+ if (err < 0) -+ return err; -+ -+ *val = (FIELD_GET(VOLTAGE_CURRENT_MASK, regval) * current_lsb) / 1000000; -+ -+ return 0; -+} -+ -+static int tps23861_port_disable(struct tps23861_data *data, int channel) -+{ -+ unsigned int regval = 0; -+ int err; -+ -+ regval |= BIT(channel + 4); -+ err = regmap_write(data->regmap, POWER_ENABLE, regval); -+ -+ return err; -+} -+ -+static int tps23861_port_enable(struct tps23861_data *data, int channel) -+{ -+ unsigned int regval = 0; -+ int err; -+ -+ regval |= BIT(channel); -+ regval |= BIT(channel + 4); -+ err = regmap_write(data->regmap, DETECT_CLASS_RESTART, regval); -+ -+ return err; -+} -+ -+static umode_t tps23861_is_visible(const void *data, enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ switch (type) { -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_input: -+ case hwmon_temp_label: -+ return 0444; -+ default: -+ return 0; -+ } -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ case hwmon_in_label: -+ return 0444; -+ case hwmon_in_enable: -+ return 0200; -+ default: -+ return 0; -+ } -+ case hwmon_curr: -+ switch (attr) { -+ case hwmon_curr_input: -+ case hwmon_curr_label: -+ return 0444; -+ default: -+ return 0; -+ } -+ default: -+ return 0; -+ } -+} -+ -+static int tps23861_write(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long val) -+{ -+ struct tps23861_data *data = dev_get_drvdata(dev); -+ int err; -+ -+ switch (type) { -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_enable: -+ if (val == 0) -+ err = tps23861_port_disable(data, channel); -+ else if (val == 1) -+ err = tps23861_port_enable(data, channel); -+ else -+ err = -EINVAL; -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return err; -+} -+ -+static int tps23861_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *val) -+{ -+ struct tps23861_data *data = dev_get_drvdata(dev); -+ int err; -+ -+ switch (type) { -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_input: -+ err = tps23861_read_temp(data, val); -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ break; -+ case hwmon_in: -+ switch (attr) { -+ case hwmon_in_input: -+ err = tps23861_read_voltage(data, channel, val); -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ break; -+ case hwmon_curr: -+ switch (attr) { -+ case hwmon_curr_input: -+ err = tps23861_read_current(data, channel, val); -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return err; -+} -+ -+static const char * const tps23861_port_label[] = { -+ "Port1", -+ "Port2", -+ "Port3", -+ "Port4", -+ "Input", -+}; -+ -+static int tps23861_read_string(struct device *dev, -+ enum hwmon_sensor_types type, -+ u32 attr, int channel, const char **str) -+{ -+ switch (type) { -+ case hwmon_in: -+ case hwmon_curr: -+ *str = tps23861_port_label[channel]; -+ break; -+ case hwmon_temp: -+ *str = "Die"; -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ -+ return 0; -+} -+ -+static const struct hwmon_channel_info *tps23861_info[] = { -+ HWMON_CHANNEL_INFO(chip, -+ HWMON_C_REGISTER_TZ), -+ HWMON_CHANNEL_INFO(temp, -+ HWMON_T_INPUT | HWMON_T_LABEL), -+ HWMON_CHANNEL_INFO(in, -+ HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, -+ HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, -+ HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, -+ HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, -+ HWMON_I_INPUT | HWMON_I_LABEL), -+ HWMON_CHANNEL_INFO(curr, -+ HWMON_C_INPUT | HWMON_C_LABEL, -+ HWMON_C_INPUT | HWMON_C_LABEL, -+ HWMON_C_INPUT | HWMON_C_LABEL, -+ HWMON_C_INPUT | HWMON_C_LABEL), -+ NULL -+}; -+ -+static const struct hwmon_ops tps23861_hwmon_ops = { -+ .is_visible = tps23861_is_visible, -+ .write = tps23861_write, -+ .read = tps23861_read, -+ .read_string = tps23861_read_string, -+}; -+ -+static const struct hwmon_chip_info tps23861_chip_info = { -+ .ops = &tps23861_hwmon_ops, -+ .info = tps23861_info, -+}; -+ -+static char *tps23861_port_operating_mode(struct tps23861_data *data, int port) -+{ -+ unsigned int regval; -+ int mode; -+ -+ regmap_read(data->regmap, OPERATING_MODE, ®val); -+ -+ switch (port) { -+ case 1: -+ mode = FIELD_GET(OPERATING_MODE_PORT_1_MASK, regval); -+ break; -+ case 2: -+ mode = FIELD_GET(OPERATING_MODE_PORT_2_MASK, regval); -+ break; -+ case 3: -+ mode = FIELD_GET(OPERATING_MODE_PORT_3_MASK, regval); -+ break; -+ case 4: -+ mode = FIELD_GET(OPERATING_MODE_PORT_4_MASK, regval); -+ break; -+ default: -+ mode = -EINVAL; -+ } -+ -+ switch (mode) { -+ case OPERATING_MODE_OFF: -+ return "Off"; -+ case OPERATING_MODE_MANUAL: -+ return "Manual"; -+ case OPERATING_MODE_SEMI: -+ return "Semi-Auto"; -+ case OPERATING_MODE_AUTO: -+ return "Auto"; -+ default: -+ return "Invalid"; -+ } -+} -+ -+static char *tps23861_port_detect_status(struct tps23861_data *data, int port) -+{ -+ unsigned int regval; -+ -+ regmap_read(data->regmap, -+ PORT_1_STATUS + (port - 1), -+ ®val); -+ -+ switch (FIELD_GET(PORT_STATUS_DETECT_MASK, regval)) { -+ case PORT_DETECT_UNKNOWN: -+ return "Unknown device"; -+ case PORT_DETECT_SHORT: -+ return "Short circuit"; -+ case PORT_DETECT_RESISTANCE_LOW: -+ return "Too low resistance"; -+ case PORT_DETECT_RESISTANCE_OK: -+ return "Valid resistance"; -+ case PORT_DETECT_RESISTANCE_HIGH: -+ return "Too high resistance"; -+ case PORT_DETECT_OPEN_CIRCUIT: -+ return "Open circuit"; -+ case PORT_DETECT_MOSFET_FAULT: -+ return "MOSFET fault"; -+ case PORT_DETECT_LEGACY: -+ return "Legacy device"; -+ case PORT_DETECT_CAPACITANCE_INVALID_BEYOND: -+ return "Invalid capacitance, beyond clamp voltage"; -+ case PORT_DETECT_CAPACITANCE_INVALID_DELTA: -+ return "Invalid capacitance, insufficient voltage delta"; -+ case PORT_DETECT_CAPACITANCE_OUT_OF_RANGE: -+ return "Valid capacitance, outside of legacy range"; -+ case PORT_DETECT_RESERVED: -+ case PORT_DETECT_RESERVED_2: -+ default: -+ return "Invalid"; -+ } -+} -+ -+static char *tps23861_port_class_status(struct tps23861_data *data, int port) -+{ -+ unsigned int regval; -+ -+ regmap_read(data->regmap, -+ PORT_1_STATUS + (port - 1), -+ ®val); -+ -+ switch (FIELD_GET(PORT_STATUS_CLASS_MASK, regval)) { -+ case PORT_CLASS_UNKNOWN: -+ return "Unknown"; -+ case PORT_CLASS_RESERVED: -+ case PORT_CLASS_0: -+ return "0"; -+ case PORT_CLASS_1: -+ return "1"; -+ case PORT_CLASS_2: -+ return "2"; -+ case PORT_CLASS_3: -+ return "3"; -+ case PORT_CLASS_4: -+ return "4"; -+ case PORT_CLASS_OVERCURRENT: -+ return "Overcurrent"; -+ case PORT_CLASS_MISMATCH: -+ return "Mismatch"; -+ default: -+ return "Invalid"; -+ } -+} -+ -+static char *tps23861_port_poe_plus_status(struct tps23861_data *data, int port) -+{ -+ unsigned int regval; -+ -+ regmap_read(data->regmap, POE_PLUS, ®val); -+ -+ if (BIT(port + 3) & regval) -+ return "Yes"; -+ else -+ return "No"; -+} -+ -+static int tps23861_port_resistance(struct tps23861_data *data, int port) -+{ -+ u16 regval; -+ -+ regmap_bulk_read(data->regmap, -+ PORT_1_RESISTANCE_LSB + PORT_N_RESISTANCE_LSB_OFFSET * (port - 1), -+ ®val, -+ 2); -+ -+ switch (FIELD_GET(PORT_RESISTANCE_RSN_MASK, regval)) { -+ case PORT_RESISTANCE_RSN_OTHER: -+ return (FIELD_GET(PORT_RESISTANCE_MASK, regval) * RESISTANCE_LSB) / 10000; -+ case PORT_RESISTANCE_RSN_LOW: -+ return (FIELD_GET(PORT_RESISTANCE_MASK, regval) * RESISTANCE_LSB_LOW) / 10000; -+ case PORT_RESISTANCE_RSN_SHORT: -+ case PORT_RESISTANCE_RSN_OPEN: -+ default: -+ return 0; -+ } -+} -+ -+static int tps23861_port_status_show(struct seq_file *s, void *data) -+{ -+ struct tps23861_data *priv = s->private; -+ int i; -+ -+ for (i = 1; i < TPS23861_NUM_PORTS + 1; i++) { -+ seq_printf(s, "Port: \t\t%d\n", i); -+ seq_printf(s, "Operating mode: %s\n", tps23861_port_operating_mode(priv, i)); -+ seq_printf(s, "Detected: \t%s\n", tps23861_port_detect_status(priv, i)); -+ seq_printf(s, "Class: \t\t%s\n", tps23861_port_class_status(priv, i)); -+ seq_printf(s, "PoE Plus: \t%s\n", tps23861_port_poe_plus_status(priv, i)); -+ seq_printf(s, "Resistance: \t%d\n", tps23861_port_resistance(priv, i)); -+ seq_putc(s, '\n'); -+ } -+ -+ return 0; -+} -+ -+DEFINE_SHOW_ATTRIBUTE(tps23861_port_status); -+ -+static void tps23861_init_debugfs(struct tps23861_data *data) -+{ -+ data->debugfs_dir = debugfs_create_dir(data->client->name, NULL); -+ -+ debugfs_create_file("port_status", -+ 0400, -+ data->debugfs_dir, -+ data, -+ &tps23861_port_status_fops); -+} -+ -+static int tps23861_probe(struct i2c_client *client) -+{ -+ struct device *dev = &client->dev; -+ struct tps23861_data *data; -+ struct device *hwmon_dev; -+ u32 shunt_resistor; -+ -+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ data->client = client; -+ i2c_set_clientdata(client, data); -+ -+ data->regmap = devm_regmap_init_i2c(client, &tps23861_regmap_config); -+ if (IS_ERR(data->regmap)) { -+ dev_err(dev, "failed to allocate register map\n"); -+ return PTR_ERR(data->regmap); -+ } -+ -+ if (!of_property_read_u32(dev->of_node, "shunt-resistor-micro-ohms", &shunt_resistor)) -+ data->shunt_resistor = shunt_resistor; -+ else -+ data->shunt_resistor = SHUNT_RESISTOR_DEFAULT; -+ -+ hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, -+ data, &tps23861_chip_info, -+ NULL); -+ if (IS_ERR(hwmon_dev)) -+ return PTR_ERR(hwmon_dev); -+ -+ tps23861_init_debugfs(data); -+ -+ return 0; -+} -+ -+static int tps23861_remove(struct i2c_client *client) -+{ -+ struct tps23861_data *data = i2c_get_clientdata(client); -+ -+ debugfs_remove_recursive(data->debugfs_dir); -+ -+ return 0; -+} -+ -+static const struct of_device_id __maybe_unused tps23861_of_match[] = { -+ { .compatible = "ti,tps23861", }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, tps23861_of_match); -+ -+static struct i2c_driver tps23861_driver = { -+ .probe_new = tps23861_probe, -+ .remove = tps23861_remove, -+ .driver = { -+ .name = "tps23861", -+ .of_match_table = of_match_ptr(tps23861_of_match), -+ }, -+}; -+module_i2c_driver(tps23861_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Robert Marko "); -+MODULE_DESCRIPTION("TI TPS23861 PoE PSE"); diff --git a/target/linux/generic/backport-5.10/872-v5.13-01-hwmon-tps23861-define-regmap-max-register.patch b/target/linux/generic/backport-5.10/872-v5.13-01-hwmon-tps23861-define-regmap-max-register.patch deleted file mode 100644 index f7ed386944..0000000000 --- a/target/linux/generic/backport-5.10/872-v5.13-01-hwmon-tps23861-define-regmap-max-register.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 3d61a7b3a714eb3ef1777e3c576576aca2b85365 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 10 Jun 2021 00:07:26 +0200 -Subject: [PATCH 2/4] hwmon: (tps23861) define regmap max register - -Define the max register address the device supports. -This allows reading the whole register space via -regmap debugfs, without it only register 0x0 is visible. - -This was forgotten in the original driver commit. - -Fixes: fff7b8ab2255 ("hwmon: add Texas Instruments TPS23861 driver") -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20210609220728.499879-1-robert.marko@sartura.hr -Signed-off-by: Guenter Roeck ---- - drivers/hwmon/tps23861.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/hwmon/tps23861.c -+++ b/drivers/hwmon/tps23861.c -@@ -117,6 +117,7 @@ struct tps23861_data { - static struct regmap_config tps23861_regmap_config = { - .reg_bits = 8, - .val_bits = 8, -+ .max_register = 0x6f, - }; - - static int tps23861_read_temp(struct tps23861_data *data, long *val) diff --git a/target/linux/generic/backport-5.10/872-v5.13-02-hwmon-tps23861-set-current-shunt-value.patch b/target/linux/generic/backport-5.10/872-v5.13-02-hwmon-tps23861-set-current-shunt-value.patch deleted file mode 100644 index f1051f77d5..0000000000 --- a/target/linux/generic/backport-5.10/872-v5.13-02-hwmon-tps23861-set-current-shunt-value.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 9bca598d4a86e88afb29fdb516c68b2519bd0fb9 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 10 Jun 2021 00:07:27 +0200 -Subject: [PATCH 3/4] hwmon: (tps23861) set current shunt value - -TPS23861 has a configuration bit for setting of the -current shunt value used on the board. -Its bit 0 of the General Mask 1 register. - -According to the datasheet bit values are: -0 for 255 mOhm (Default) -1 for 250 mOhm - -So, configure the bit before registering the hwmon -device according to the value passed in the DTS or -default one if none is passed. - -This caused potentially reading slightly skewed values -due to max current value being 1.02A when 250mOhm shunt -is used instead of 1.0A when 255mOhm is used. - -Fixes: fff7b8ab2255 ("hwmon: add Texas Instruments TPS23861 driver") -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20210609220728.499879-2-robert.marko@sartura.hr -Signed-off-by: Guenter Roeck ---- - drivers/hwmon/tps23861.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/hwmon/tps23861.c -+++ b/drivers/hwmon/tps23861.c -@@ -99,6 +99,9 @@ - #define POWER_ENABLE 0x19 - #define TPS23861_NUM_PORTS 4 - -+#define TPS23861_GENERAL_MASK_1 0x17 -+#define TPS23861_CURRENT_SHUNT_MASK BIT(0) -+ - #define TEMPERATURE_LSB 652 /* 0.652 degrees Celsius */ - #define VOLTAGE_LSB 3662 /* 3.662 mV */ - #define SHUNT_RESISTOR_DEFAULT 255000 /* 255 mOhm */ -@@ -561,6 +564,15 @@ static int tps23861_probe(struct i2c_cli - else - data->shunt_resistor = SHUNT_RESISTOR_DEFAULT; - -+ if (data->shunt_resistor == SHUNT_RESISTOR_DEFAULT) -+ regmap_clear_bits(data->regmap, -+ TPS23861_GENERAL_MASK_1, -+ TPS23861_CURRENT_SHUNT_MASK); -+ else -+ regmap_set_bits(data->regmap, -+ TPS23861_GENERAL_MASK_1, -+ TPS23861_CURRENT_SHUNT_MASK); -+ - hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, - data, &tps23861_chip_info, - NULL); diff --git a/target/linux/generic/backport-5.10/872-v5.13-03-hwmon-tps23861-correct-shunt-LSB-values.patch b/target/linux/generic/backport-5.10/872-v5.13-03-hwmon-tps23861-correct-shunt-LSB-values.patch deleted file mode 100644 index 2485d7a0ee..0000000000 --- a/target/linux/generic/backport-5.10/872-v5.13-03-hwmon-tps23861-correct-shunt-LSB-values.patch +++ /dev/null @@ -1,34 +0,0 @@ -From b447e689a26614ce08a431e8000e8a650a63dcb3 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Thu, 10 Jun 2021 00:07:28 +0200 -Subject: [PATCH 4/4] hwmon: (tps23861) correct shunt LSB values - -Current shunt LSB values got reversed during in the -original driver commit. - -So, correct the current shunt LSB values according to -the datasheet. - -This caused reading slightly skewed current values. - -Fixes: fff7b8ab2255 ("hwmon: add Texas Instruments TPS23861 driver") -Signed-off-by: Robert Marko -Link: https://lore.kernel.org/r/20210609220728.499879-3-robert.marko@sartura.hr -Signed-off-by: Guenter Roeck ---- - drivers/hwmon/tps23861.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/hwmon/tps23861.c -+++ b/drivers/hwmon/tps23861.c -@@ -105,8 +105,8 @@ - #define TEMPERATURE_LSB 652 /* 0.652 degrees Celsius */ - #define VOLTAGE_LSB 3662 /* 3.662 mV */ - #define SHUNT_RESISTOR_DEFAULT 255000 /* 255 mOhm */ --#define CURRENT_LSB_255 62260 /* 62.260 uA */ --#define CURRENT_LSB_250 61039 /* 61.039 uA */ -+#define CURRENT_LSB_250 62260 /* 62.260 uA */ -+#define CURRENT_LSB_255 61039 /* 61.039 uA */ - #define RESISTANCE_LSB 110966 /* 11.0966 Ohm*/ - #define RESISTANCE_LSB_LOW 157216 /* 15.7216 Ohm*/ - diff --git a/target/linux/generic/backport-5.10/873-v6.0-hwmon-tps23861-fix-byte-order-in-current-and-voltage.patch b/target/linux/generic/backport-5.10/873-v6.0-hwmon-tps23861-fix-byte-order-in-current-and-voltage.patch deleted file mode 100644 index 45c2d0b4a4..0000000000 --- a/target/linux/generic/backport-5.10/873-v6.0-hwmon-tps23861-fix-byte-order-in-current-and-voltage.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 0eabb1396656f215a5333a9444158b17b0fd3247 Mon Sep 17 00:00:00 2001 -From: Alexandru Gagniuc -Date: Wed, 20 Jul 2022 22:22:55 -0500 -Subject: hwmon: (tps23861) fix byte order in current and voltage registers - -Trying to use this driver on a big-endian machine results in garbage -values for voltage and current. The tps23861 registers are little- -endian, and regmap_read_bulk() does not do byte order conversion. Thus -on BE machines, the most significant bytes got modified, and were -trimmed by the VOLTAGE_CURRENT_MASK. - -To resolve this use uint16_t values, and convert them to host byte -order using le16_to_cpu(). This results in correct readings on MIPS. - -Signed-off-by: Alexandru Gagniuc -Link: https://lore.kernel.org/r/20220721032255.2850647-1-mr.nuke.me@gmail.com -[groeck: Use __le16 instead of uint16_t] -Signed-off-by: Guenter Roeck ---- - drivers/hwmon/tps23861.c | 14 +++++++++----- - 1 file changed, 9 insertions(+), 5 deletions(-) - ---- a/drivers/hwmon/tps23861.c -+++ b/drivers/hwmon/tps23861.c -@@ -140,7 +140,8 @@ static int tps23861_read_temp(struct tps - static int tps23861_read_voltage(struct tps23861_data *data, int channel, - long *val) - { -- unsigned int regval; -+ __le16 regval; -+ long raw_val; - int err; - - if (channel < TPS23861_NUM_PORTS) { -@@ -155,7 +156,8 @@ static int tps23861_read_voltage(struct - if (err < 0) - return err; - -- *val = (FIELD_GET(VOLTAGE_CURRENT_MASK, regval) * VOLTAGE_LSB) / 1000; -+ raw_val = le16_to_cpu(regval); -+ *val = (FIELD_GET(VOLTAGE_CURRENT_MASK, raw_val) * VOLTAGE_LSB) / 1000; - - return 0; - } -@@ -163,8 +165,9 @@ static int tps23861_read_voltage(struct - static int tps23861_read_current(struct tps23861_data *data, int channel, - long *val) - { -- unsigned int current_lsb; -- unsigned int regval; -+ long raw_val, current_lsb; -+ __le16 regval; -+ - int err; - - if (data->shunt_resistor == SHUNT_RESISTOR_DEFAULT) -@@ -178,7 +181,8 @@ static int tps23861_read_current(struct - if (err < 0) - return err; - -- *val = (FIELD_GET(VOLTAGE_CURRENT_MASK, regval) * current_lsb) / 1000000; -+ raw_val = le16_to_cpu(regval); -+ *val = (FIELD_GET(VOLTAGE_CURRENT_MASK, raw_val) * current_lsb) / 1000000; - - return 0; - } diff --git a/target/linux/generic/backport-5.10/880-v5.19-cdc_ether-export-usbnet_cdc_zte_rx_fixup.patch b/target/linux/generic/backport-5.10/880-v5.19-cdc_ether-export-usbnet_cdc_zte_rx_fixup.patch deleted file mode 100644 index b5a226181e..0000000000 --- a/target/linux/generic/backport-5.10/880-v5.19-cdc_ether-export-usbnet_cdc_zte_rx_fixup.patch +++ /dev/null @@ -1,58 +0,0 @@ -From d91a03b72c5f9c25e5b976f8f67bcf279601d644 Mon Sep 17 00:00:00 2001 -From: Lech Perczak -Date: Fri, 1 Apr 2022 22:03:55 +0200 -Subject: [PATCH 1/3] cdc_ether: export usbnet_cdc_zte_rx_fixup -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Commit bfe9b9d2df66 ("cdc_ether: Improve ZTE MF823/831/910 handling") -introduces a workaround for certain ZTE modems reporting invalid MAC -addresses over CDC-ECM. -The same issue was present on their RNDIS interface,which was fixed in -commit a5a18bdf7453 ("rndis_host: Set valid random MAC on buggy devices"). - -However, internal modem of ZTE MF286R router, on its RNDIS interface, also -exhibits a second issue fixed already in CDC-ECM, of the device not -respecting configured random MAC address. In order to share the fixup for -this with rndis_host driver, export the workaround function, which will -be re-used in the following commit in rndis_host. - -Cc: Kristian Evensen -Cc: Bjørn Mork -Cc: Oliver Neukum -Signed-off-by: Lech Perczak ---- - drivers/net/usb/cdc_ether.c | 3 ++- - include/linux/usb/usbnet.h | 1 + - 2 files changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/net/usb/cdc_ether.c -+++ b/drivers/net/usb/cdc_ether.c -@@ -466,7 +466,7 @@ static int usbnet_cdc_zte_bind(struct us - * device MAC address has been updated). Always set MAC address to that of the - * device. - */ --static int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb) -+int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb) - { - if (skb->len < ETH_HLEN || !(skb->data[0] & 0x02)) - return 1; -@@ -476,6 +476,7 @@ static int usbnet_cdc_zte_rx_fixup(struc - - return 1; - } -+EXPORT_SYMBOL_GPL(usbnet_cdc_zte_rx_fixup); - - /* Ensure correct link state - * ---- a/include/linux/usb/usbnet.h -+++ b/include/linux/usb/usbnet.h -@@ -215,6 +215,7 @@ extern int usbnet_ether_cdc_bind(struct - extern int usbnet_cdc_bind(struct usbnet *, struct usb_interface *); - extern void usbnet_cdc_unbind(struct usbnet *, struct usb_interface *); - extern void usbnet_cdc_status(struct usbnet *, struct urb *); -+extern int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb); - - /* CDC and RNDIS support the same host-chosen packet filters for IN transfers */ - #define DEFAULT_FILTER (USB_CDC_PACKET_TYPE_BROADCAST \ diff --git a/target/linux/generic/backport-5.10/881-v5.19-rndis_host-enable-the-bogus-MAC-fixup-for-ZTE-device.patch b/target/linux/generic/backport-5.10/881-v5.19-rndis_host-enable-the-bogus-MAC-fixup-for-ZTE-device.patch deleted file mode 100644 index e37c89a360..0000000000 --- a/target/linux/generic/backport-5.10/881-v5.19-rndis_host-enable-the-bogus-MAC-fixup-for-ZTE-device.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 69a9efb689b43fedf5f19431f1889aa6b8d35d55 Mon Sep 17 00:00:00 2001 -From: Lech Perczak -Date: Fri, 1 Apr 2022 22:04:01 +0200 -Subject: [PATCH 2/3] rndis_host: enable the bogus MAC fixup for ZTE devices - from cdc_ether -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Certain ZTE modems, namely: MF823. MF831, MF910, built-in modem from -MF286R, expose both CDC-ECM and RNDIS network interfaces. -They have a trait of ignoring the locally-administered MAC address -configured on the interface both in CDC-ECM and RNDIS part, -and this leads to dropping of incoming traffic by the host. -However, the workaround was only present in CDC-ECM, and MF286R -explicitly requires it in RNDIS mode. - -Re-use the workaround in rndis_host as well, to fix operation of MF286R -module, some versions of which expose only the RNDIS interface. Do so by -introducing new flag, RNDIS_DRIVER_DATA_DST_MAC_FIXUP, and testing for it -in rndis_rx_fixup. This is required, as RNDIS uses frame batching, and all -of the packets inside the batch need the fixup. This might introduce a -performance penalty, because test is done for every returned Ethernet -frame. - -Apply the workaround to both "flavors" of RNDIS interfaces, as older ZTE -modems, like MF823 found in the wild, report the USB_CLASS_COMM class -interfaces, while MF286R reports USB_CLASS_WIRELESS_CONTROLLER. - -Suggested-by: Bjørn Mork -Cc: Kristian Evensen -Cc: Oliver Neukum -Signed-off-by: Lech Perczak ---- - drivers/net/usb/rndis_host.c | 32 ++++++++++++++++++++++++++++++++ - include/linux/usb/rndis_host.h | 1 + - 2 files changed, 33 insertions(+) - ---- a/drivers/net/usb/rndis_host.c -+++ b/drivers/net/usb/rndis_host.c -@@ -486,10 +486,14 @@ EXPORT_SYMBOL_GPL(rndis_unbind); - */ - int rndis_rx_fixup(struct usbnet *dev, struct sk_buff *skb) - { -+ bool dst_mac_fixup; -+ - /* This check is no longer done by usbnet */ - if (skb->len < dev->net->hard_header_len) - return 0; - -+ dst_mac_fixup = !!(dev->driver_info->data & RNDIS_DRIVER_DATA_DST_MAC_FIXUP); -+ - /* peripheral may have batched packets to us... */ - while (likely(skb->len)) { - struct rndis_data_hdr *hdr = (void *)skb->data; -@@ -524,10 +528,17 @@ int rndis_rx_fixup(struct usbnet *dev, s - break; - skb_pull(skb, msg_len - sizeof *hdr); - skb_trim(skb2, data_len); -+ -+ if (unlikely(dst_mac_fixup)) -+ usbnet_cdc_zte_rx_fixup(dev, skb2); -+ - usbnet_skb_return(dev, skb2); - } - - /* caller will usbnet_skb_return the remaining packet */ -+ if (unlikely(dst_mac_fixup)) -+ usbnet_cdc_zte_rx_fixup(dev, skb); -+ - return 1; - } - EXPORT_SYMBOL_GPL(rndis_rx_fixup); -@@ -601,6 +612,17 @@ static const struct driver_info rndis_po - .tx_fixup = rndis_tx_fixup, - }; - -+static const struct driver_info zte_rndis_info = { -+ .description = "ZTE RNDIS device", -+ .flags = FLAG_ETHER | FLAG_POINTTOPOINT | FLAG_FRAMING_RN | FLAG_NO_SETINT, -+ .data = RNDIS_DRIVER_DATA_DST_MAC_FIXUP, -+ .bind = rndis_bind, -+ .unbind = rndis_unbind, -+ .status = rndis_status, -+ .rx_fixup = rndis_rx_fixup, -+ .tx_fixup = rndis_tx_fixup, -+}; -+ - /*-------------------------------------------------------------------------*/ - - static const struct usb_device_id products [] = { -@@ -610,6 +632,16 @@ static const struct usb_device_id produc - USB_CLASS_COMM, 2 /* ACM */, 0x0ff), - .driver_info = (unsigned long) &rndis_poll_status_info, - }, { -+ /* ZTE WWAN modules */ -+ USB_VENDOR_AND_INTERFACE_INFO(0x19d2, -+ USB_CLASS_WIRELESS_CONTROLLER, 1, 3), -+ .driver_info = (unsigned long)&zte_rndis_info, -+}, { -+ /* ZTE WWAN modules, ACM flavour */ -+ USB_VENDOR_AND_INTERFACE_INFO(0x19d2, -+ USB_CLASS_COMM, 2 /* ACM */, 0x0ff), -+ .driver_info = (unsigned long)&zte_rndis_info, -+}, { - /* Hytera Communications DMR radios' "Radio to PC Network" */ - USB_VENDOR_AND_INTERFACE_INFO(0x238b, - USB_CLASS_COMM, 2 /* ACM */, 0x0ff), ---- a/include/linux/usb/rndis_host.h -+++ b/include/linux/usb/rndis_host.h -@@ -197,6 +197,7 @@ struct rndis_keepalive_c { /* IN (option - - /* Flags for driver_info::data */ - #define RNDIS_DRIVER_DATA_POLL_STATUS 1 /* poll status before control */ -+#define RNDIS_DRIVER_DATA_DST_MAC_FIXUP 2 /* device ignores configured MAC address */ - - extern void rndis_status(struct usbnet *dev, struct urb *urb); - extern int diff --git a/target/linux/generic/backport-5.10/882-v5.19-rndis_host-limit-scope-of-bogus-MAC-address-detectio.patch b/target/linux/generic/backport-5.10/882-v5.19-rndis_host-limit-scope-of-bogus-MAC-address-detectio.patch deleted file mode 100644 index 38d0227714..0000000000 --- a/target/linux/generic/backport-5.10/882-v5.19-rndis_host-limit-scope-of-bogus-MAC-address-detectio.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 1bfbe1799b9ec5d00f7f032d6e7db1980e466aeb Mon Sep 17 00:00:00 2001 -From: Lech Perczak -Date: Sat, 2 Apr 2022 02:19:57 +0200 -Subject: [PATCH 3/3] rndis_host: limit scope of bogus MAC address detection to - ZTE devices -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Reporting of bogus MAC addresses and ignoring configuration of new -destination address wasn't observed outside of a range of ZTE devices, -among which this seems to be the common bug. Align rndis_host driver -with implementation found in cdc_ether, which also limits this workaround -to ZTE devices. - -Suggested-by: Bjørn Mork -Cc: Kristian Evensen -Cc: Oliver Neukum -Signed-off-by: Lech Perczak ---- - drivers/net/usb/rndis_host.c | 17 ++++++++++++----- - 1 file changed, 12 insertions(+), 5 deletions(-) - ---- a/drivers/net/usb/rndis_host.c -+++ b/drivers/net/usb/rndis_host.c -@@ -419,10 +419,7 @@ generic_rndis_bind(struct usbnet *dev, s - goto halt_fail_and_release; - } - -- if (bp[0] & 0x02) -- eth_hw_addr_random(net); -- else -- ether_addr_copy(net->dev_addr, bp); -+ ether_addr_copy(net->dev_addr, bp); - - /* set a nonzero filter to enable data transfers */ - memset(u.set, 0, sizeof *u.set); -@@ -464,6 +461,16 @@ static int rndis_bind(struct usbnet *dev - return generic_rndis_bind(dev, intf, FLAG_RNDIS_PHYM_NOT_WIRELESS); - } - -+static int zte_rndis_bind(struct usbnet *dev, struct usb_interface *intf) -+{ -+ int status = rndis_bind(dev, intf); -+ -+ if (!status && (dev->net->dev_addr[0] & 0x02)) -+ eth_hw_addr_random(dev->net); -+ -+ return status; -+} -+ - void rndis_unbind(struct usbnet *dev, struct usb_interface *intf) - { - struct rndis_halt *halt; -@@ -616,7 +623,7 @@ static const struct driver_info zte_rndi - .description = "ZTE RNDIS device", - .flags = FLAG_ETHER | FLAG_POINTTOPOINT | FLAG_FRAMING_RN | FLAG_NO_SETINT, - .data = RNDIS_DRIVER_DATA_DST_MAC_FIXUP, -- .bind = rndis_bind, -+ .bind = zte_rndis_bind, - .unbind = rndis_unbind, - .status = rndis_status, - .rx_fixup = rndis_rx_fixup, diff --git a/target/linux/generic/backport-5.10/883-v5.11-Bluetooth-btrtl-Refine-the-ic_id_table-for-clearer-a.patch b/target/linux/generic/backport-5.10/883-v5.11-Bluetooth-btrtl-Refine-the-ic_id_table-for-clearer-a.patch deleted file mode 100644 index 0975033d83..0000000000 --- a/target/linux/generic/backport-5.10/883-v5.11-Bluetooth-btrtl-Refine-the-ic_id_table-for-clearer-a.patch +++ /dev/null @@ -1,183 +0,0 @@ -From 6f9ff24645f55ffae12ef717b4f221c3e7dfe115 Mon Sep 17 00:00:00 2001 -From: Max Chou -Date: Wed, 4 Nov 2020 20:04:14 +0800 -Subject: [PATCH] Bluetooth: btrtl: Refine the ic_id_table for clearer and more - regular - -Enhance the ic_id_table that it's able to maintain regularly. -To judge which chip should be initialized by LMP subversion, HCI revision, - HCI version and HCI bus which were given in the ic_id_table. -Also, refine the incorrect LMP subversion of ROM for RTL8723D and -RTL8723A. - -Suggested-by: Alex Lu -Signed-off-by: Max Chou -Signed-off-by: Marcel Holtmann ---- - drivers/bluetooth/btrtl.c | 65 ++++++++++++--------------------------- - 1 file changed, 19 insertions(+), 46 deletions(-) - ---- a/drivers/bluetooth/btrtl.c -+++ b/drivers/bluetooth/btrtl.c -@@ -18,10 +18,8 @@ - #define VERSION "0.1" - - #define RTL_EPATCH_SIGNATURE "Realtech" --#define RTL_ROM_LMP_3499 0x3499 - #define RTL_ROM_LMP_8723A 0x1200 - #define RTL_ROM_LMP_8723B 0x8723 --#define RTL_ROM_LMP_8723D 0x8873 - #define RTL_ROM_LMP_8821A 0x8821 - #define RTL_ROM_LMP_8761A 0x8761 - #define RTL_ROM_LMP_8822B 0x8822 -@@ -31,10 +29,13 @@ - #define IC_MATCH_FL_HCIREV (1 << 1) - #define IC_MATCH_FL_HCIVER (1 << 2) - #define IC_MATCH_FL_HCIBUS (1 << 3) --#define IC_INFO(lmps, hcir) \ -- .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV, \ -+#define IC_INFO(lmps, hcir, hciv, bus) \ -+ .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV | \ -+ IC_MATCH_FL_HCIVER | IC_MATCH_FL_HCIBUS, \ - .lmp_subver = (lmps), \ -- .hci_rev = (hcir) -+ .hci_rev = (hcir), \ -+ .hci_ver = (hciv), \ -+ .hci_bus = (bus) - - struct id_table { - __u16 match_flags; -@@ -58,112 +59,85 @@ struct btrtl_device_info { - }; - - static const struct id_table ic_id_table[] = { -- { IC_MATCH_FL_LMPSUBV, RTL_ROM_LMP_8723A, 0x0, -- .config_needed = false, -- .has_rom_version = false, -- .fw_name = "rtl_bt/rtl8723a_fw.bin", -- .cfg_name = NULL }, -- -- { IC_MATCH_FL_LMPSUBV, RTL_ROM_LMP_3499, 0x0, -+ /* 8723A */ -+ { IC_INFO(RTL_ROM_LMP_8723A, 0xb, 0x6, HCI_USB), - .config_needed = false, - .has_rom_version = false, - .fw_name = "rtl_bt/rtl8723a_fw.bin", - .cfg_name = NULL }, - - /* 8723BS */ -- { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV | -- IC_MATCH_FL_HCIVER | IC_MATCH_FL_HCIBUS, -- .lmp_subver = RTL_ROM_LMP_8723B, -- .hci_rev = 0xb, -- .hci_ver = 6, -- .hci_bus = HCI_UART, -+ { IC_INFO(RTL_ROM_LMP_8723B, 0xb, 0x6, HCI_UART), - .config_needed = true, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8723bs_fw.bin", - .cfg_name = "rtl_bt/rtl8723bs_config" }, - - /* 8723B */ -- { IC_INFO(RTL_ROM_LMP_8723B, 0xb), -+ { IC_INFO(RTL_ROM_LMP_8723B, 0xb, 0x6, HCI_USB), - .config_needed = false, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8723b_fw.bin", - .cfg_name = "rtl_bt/rtl8723b_config" }, - - /* 8723D */ -- { IC_INFO(RTL_ROM_LMP_8723B, 0xd), -+ { IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_USB), - .config_needed = true, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8723d_fw.bin", - .cfg_name = "rtl_bt/rtl8723d_config" }, - - /* 8723DS */ -- { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV | -- IC_MATCH_FL_HCIVER | IC_MATCH_FL_HCIBUS, -- .lmp_subver = RTL_ROM_LMP_8723B, -- .hci_rev = 0xd, -- .hci_ver = 8, -- .hci_bus = HCI_UART, -+ { IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_UART), - .config_needed = true, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8723ds_fw.bin", - .cfg_name = "rtl_bt/rtl8723ds_config" }, - -- /* 8723DU */ -- { IC_INFO(RTL_ROM_LMP_8723D, 0x826C), -- .config_needed = true, -- .has_rom_version = true, -- .fw_name = "rtl_bt/rtl8723d_fw.bin", -- .cfg_name = "rtl_bt/rtl8723d_config" }, -- - /* 8821A */ -- { IC_INFO(RTL_ROM_LMP_8821A, 0xa), -+ { IC_INFO(RTL_ROM_LMP_8821A, 0xa, 0x6, HCI_USB), - .config_needed = false, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8821a_fw.bin", - .cfg_name = "rtl_bt/rtl8821a_config" }, - - /* 8821C */ -- { IC_INFO(RTL_ROM_LMP_8821A, 0xc), -+ { IC_INFO(RTL_ROM_LMP_8821A, 0xc, 0x8, HCI_USB), - .config_needed = false, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8821c_fw.bin", - .cfg_name = "rtl_bt/rtl8821c_config" }, - - /* 8761A */ -- { IC_INFO(RTL_ROM_LMP_8761A, 0xa), -+ { IC_INFO(RTL_ROM_LMP_8761A, 0xa, 0x6, HCI_USB), - .config_needed = false, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8761a_fw.bin", - .cfg_name = "rtl_bt/rtl8761a_config" }, - - /* 8761B */ -- { IC_INFO(RTL_ROM_LMP_8761A, 0xb), -+ { IC_INFO(RTL_ROM_LMP_8761A, 0xb, 0xa, HCI_USB), - .config_needed = false, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8761b_fw.bin", - .cfg_name = "rtl_bt/rtl8761b_config" }, - - /* 8822C with UART interface */ -- { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV | -- IC_MATCH_FL_HCIBUS, -- .lmp_subver = RTL_ROM_LMP_8822B, -- .hci_rev = 0x000c, -- .hci_ver = 0x0a, -- .hci_bus = HCI_UART, -+ { IC_INFO(RTL_ROM_LMP_8822B, 0xc, 0xa, HCI_UART), - .config_needed = true, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8822cs_fw.bin", - .cfg_name = "rtl_bt/rtl8822cs_config" }, - - /* 8822C with USB interface */ -- { IC_INFO(RTL_ROM_LMP_8822B, 0xc), -+ { IC_INFO(RTL_ROM_LMP_8822B, 0xc, 0xa, HCI_USB), - .config_needed = false, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8822cu_fw.bin", - .cfg_name = "rtl_bt/rtl8822cu_config" }, - - /* 8822B */ -- { IC_INFO(RTL_ROM_LMP_8822B, 0xb), -+ { IC_INFO(RTL_ROM_LMP_8822B, 0xb, 0x7, HCI_USB), - .config_needed = true, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8822b_fw.bin", -@@ -654,7 +628,6 @@ int btrtl_download_firmware(struct hci_d - - switch (btrtl_dev->ic_info->lmp_subver) { - case RTL_ROM_LMP_8723A: -- case RTL_ROM_LMP_3499: - return btrtl_setup_rtl8723a(hdev, btrtl_dev); - case RTL_ROM_LMP_8723B: - case RTL_ROM_LMP_8821A: diff --git a/target/linux/generic/backport-5.10/884-v5.14-Bluetooth-btrtl-rename-USB-fw-for-RTL8761.patch b/target/linux/generic/backport-5.10/884-v5.14-Bluetooth-btrtl-rename-USB-fw-for-RTL8761.patch deleted file mode 100644 index 5372ce874a..0000000000 --- a/target/linux/generic/backport-5.10/884-v5.14-Bluetooth-btrtl-rename-USB-fw-for-RTL8761.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 9fd2e2949b43dea869f7fce0f8f51df44f635d59 Mon Sep 17 00:00:00 2001 -From: Joakim Tjernlund -Date: Fri, 28 May 2021 17:26:44 +0200 -Subject: [PATCH] Bluetooth: btrtl: rename USB fw for RTL8761 - -According Realteks own BT drivers firmware RTL8761B is for UART -and RTL8761BU is for USB. - -Change existing 8761B to UART and add an 8761BU entry for USB - -Signed-off-by: Joakim Tjernlund -Signed-off-by: Marcel Holtmann ---- - drivers/bluetooth/btrtl.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/drivers/bluetooth/btrtl.c -+++ b/drivers/bluetooth/btrtl.c -@@ -116,12 +116,19 @@ static const struct id_table ic_id_table - .cfg_name = "rtl_bt/rtl8761a_config" }, - - /* 8761B */ -- { IC_INFO(RTL_ROM_LMP_8761A, 0xb, 0xa, HCI_USB), -+ { IC_INFO(RTL_ROM_LMP_8761A, 0xb, 0xa, HCI_UART), - .config_needed = false, - .has_rom_version = true, - .fw_name = "rtl_bt/rtl8761b_fw.bin", - .cfg_name = "rtl_bt/rtl8761b_config" }, - -+ /* 8761BU */ -+ { IC_INFO(RTL_ROM_LMP_8761A, 0xb, 0xa, HCI_USB), -+ .config_needed = false, -+ .has_rom_version = true, -+ .fw_name = "rtl_bt/rtl8761bu_fw.bin", -+ .cfg_name = "rtl_bt/rtl8761bu_config" }, -+ - /* 8822C with UART interface */ - { IC_INFO(RTL_ROM_LMP_8822B, 0xc, 0xa, HCI_UART), - .config_needed = true, diff --git a/target/linux/generic/backport-5.10/885-v5.14-Bluetooth-btusb-Add-0x0b05-0x190e-Realtek-8761BU-ASU.patch b/target/linux/generic/backport-5.10/885-v5.14-Bluetooth-btusb-Add-0x0b05-0x190e-Realtek-8761BU-ASU.patch deleted file mode 100644 index c9c5413b14..0000000000 --- a/target/linux/generic/backport-5.10/885-v5.14-Bluetooth-btusb-Add-0x0b05-0x190e-Realtek-8761BU-ASU.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 33404381c5e875cbd57eec6d9bbacd3b13b404c9 Mon Sep 17 00:00:00 2001 -From: Joakim Tjernlund -Date: Fri, 28 May 2021 17:26:45 +0200 -Subject: [PATCH] Bluetooth: btusb: Add 0x0b05:0x190e Realtek 8761BU (ASUS - BT500) device. - -T: Bus=01 Lev=01 Prnt=01 Port=08 Cnt=04 Dev#= 18 Spd=12 MxCh= 0 -D: Ver= 1.10 Cls=e0(wlcon) Sub=01 Prot=01 MxPS=64 #Cfgs= 1 -P: Vendor=0b05 ProdID=190e Rev= 2.00 -S: Manufacturer=Realtek -S: Product=ASUS USB-BT500 -S: SerialNumber=xxxxxxxx -C:* #Ifs= 2 Cfg#= 1 Atr=e0 MxPwr=500mA -I:* If#= 0 Alt= 0 #EPs= 3 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=81(I) Atr=03(Int.) MxPS= 16 Ivl=1ms -E: Ad=02(O) Atr=02(Bulk) MxPS= 64 Ivl=0ms -E: Ad=82(I) Atr=02(Bulk) MxPS= 64 Ivl=0ms -I:* If#= 1 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 0 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 0 Ivl=1ms -I: If#= 1 Alt= 1 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 9 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 9 Ivl=1ms -I: If#= 1 Alt= 2 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 17 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 17 Ivl=1ms -I: If#= 1 Alt= 3 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 25 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 25 Ivl=1ms -I: If#= 1 Alt= 4 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 33 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 33 Ivl=1ms -I: If#= 1 Alt= 5 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 49 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 49 Ivl=1ms -Signed-off-by: Joakim Tjernlund -Signed-off-by: Marcel Holtmann ---- - drivers/bluetooth/btusb.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/bluetooth/btusb.c -+++ b/drivers/bluetooth/btusb.c -@@ -455,6 +455,10 @@ static const struct usb_device_id blackl - { USB_DEVICE(0x0bda, 0xb009), .driver_info = BTUSB_REALTEK }, - { USB_DEVICE(0x2ff8, 0xb011), .driver_info = BTUSB_REALTEK }, - -+ /* Additional Realtek 8761BU Bluetooth devices */ -+ { USB_DEVICE(0x0b05, 0x190e), .driver_info = BTUSB_REALTEK | -+ BTUSB_WIDEBAND_SPEECH }, -+ - /* Additional Realtek 8821AE Bluetooth devices */ - { USB_DEVICE(0x0b05, 0x17dc), .driver_info = BTUSB_REALTEK }, - { USB_DEVICE(0x13d3, 0x3414), .driver_info = BTUSB_REALTEK }, diff --git a/target/linux/generic/backport-5.10/886-v5.16-Bluetooth-btusb-Add-support-for-TP-Link-UB500-Adapte.patch b/target/linux/generic/backport-5.10/886-v5.16-Bluetooth-btusb-Add-support-for-TP-Link-UB500-Adapte.patch deleted file mode 100644 index dee77c63eb..0000000000 --- a/target/linux/generic/backport-5.10/886-v5.16-Bluetooth-btusb-Add-support-for-TP-Link-UB500-Adapte.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 4fd6d490796171bf786090fee782e252186632e4 Mon Sep 17 00:00:00 2001 -From: Nicholas Flintham -Date: Thu, 30 Sep 2021 09:22:39 +0100 -Subject: [PATCH] Bluetooth: btusb: Add support for TP-Link UB500 Adapter - -Add support for TP-Link UB500 Adapter (RTL8761B) - -* /sys/kernel/debug/usb/devices -T: Bus=01 Lev=02 Prnt=05 Port=01 Cnt=01 Dev#= 78 Spd=12 MxCh= 0 -D: Ver= 1.10 Cls=e0(wlcon) Sub=01 Prot=01 MxPS=64 #Cfgs= 1 -P: Vendor=2357 ProdID=0604 Rev= 2.00 -S: Manufacturer= -S: Product=TP-Link UB500 Adapter -S: SerialNumber=E848B8C82000 -C:* #Ifs= 2 Cfg#= 1 Atr=e0 MxPwr=500mA -I:* If#= 0 Alt= 0 #EPs= 3 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=81(I) Atr=03(Int.) MxPS= 16 Ivl=1ms -E: Ad=02(O) Atr=02(Bulk) MxPS= 64 Ivl=0ms -E: Ad=82(I) Atr=02(Bulk) MxPS= 64 Ivl=0ms -I:* If#= 1 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 0 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 0 Ivl=1ms -I: If#= 1 Alt= 1 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 9 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 9 Ivl=1ms -I: If#= 1 Alt= 2 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 17 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 17 Ivl=1ms -I: If#= 1 Alt= 3 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 25 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 25 Ivl=1ms -I: If#= 1 Alt= 4 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 33 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 33 Ivl=1ms -I: If#= 1 Alt= 5 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 49 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 49 Ivl=1ms - -Signed-off-by: Nicholas Flintham -Signed-off-by: Marcel Holtmann ---- - drivers/bluetooth/btusb.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/bluetooth/btusb.c -+++ b/drivers/bluetooth/btusb.c -@@ -455,6 +455,10 @@ static const struct usb_device_id blackl - { USB_DEVICE(0x0bda, 0xb009), .driver_info = BTUSB_REALTEK }, - { USB_DEVICE(0x2ff8, 0xb011), .driver_info = BTUSB_REALTEK }, - -+ /* Additional Realtek 8761B Bluetooth devices */ -+ { USB_DEVICE(0x2357, 0x0604), .driver_info = BTUSB_REALTEK | -+ BTUSB_WIDEBAND_SPEECH }, -+ - /* Additional Realtek 8761BU Bluetooth devices */ - { USB_DEVICE(0x0b05, 0x190e), .driver_info = BTUSB_REALTEK | - BTUSB_WIDEBAND_SPEECH }, diff --git a/target/linux/generic/backport-5.10/887-v5.18-Bluetooth-btusb-Add-another-Realtek-8761BU.patch b/target/linux/generic/backport-5.10/887-v5.18-Bluetooth-btusb-Add-another-Realtek-8761BU.patch deleted file mode 100644 index dd6476d1d2..0000000000 --- a/target/linux/generic/backport-5.10/887-v5.18-Bluetooth-btusb-Add-another-Realtek-8761BU.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 6dfbe29f45fb0bde29213dbd754a79e8bfc6ecef Mon Sep 17 00:00:00 2001 -From: Helmut Grohne -Date: Sat, 26 Feb 2022 16:22:56 +0100 -Subject: [PATCH] Bluetooth: btusb: Add another Realtek 8761BU - -This device is sometimes wrapped with a label "EDUP". - -T: Bus=01 Lev=02 Prnt=02 Port=02 Cnt=03 Dev#=107 Spd=12 MxCh= 0 -D: Ver= 1.10 Cls=e0(wlcon) Sub=01 Prot=01 MxPS=64 #Cfgs= 1 -P: Vendor=2550 ProdID=8761 Rev= 2.00 -S: Manufacturer=Realtek -S: Product=Bluetooth Radio -S: SerialNumber=00E04C239987 -C:* #Ifs= 2 Cfg#= 1 Atr=e0 MxPwr=500mA -I:* If#= 0 Alt= 0 #EPs= 3 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=81(I) Atr=03(Int.) MxPS= 16 Ivl=1ms -E: Ad=02(O) Atr=02(Bulk) MxPS= 64 Ivl=0ms -E: Ad=82(I) Atr=02(Bulk) MxPS= 64 Ivl=0ms -I:* If#= 1 Alt= 0 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 0 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 0 Ivl=1ms -I: If#= 1 Alt= 1 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 9 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 9 Ivl=1ms -I: If#= 1 Alt= 2 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 17 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 17 Ivl=1ms -I: If#= 1 Alt= 3 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 25 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 25 Ivl=1ms -I: If#= 1 Alt= 4 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 33 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 33 Ivl=1ms -I: If#= 1 Alt= 5 #EPs= 2 Cls=e0(wlcon) Sub=01 Prot=01 Driver=btusb -E: Ad=03(O) Atr=01(Isoc) MxPS= 49 Ivl=1ms -E: Ad=83(I) Atr=01(Isoc) MxPS= 49 Ivl=1ms - -Signed-off-by: Helmut Grohne -Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1955351 -Signed-off-by: Marcel Holtmann ---- - drivers/bluetooth/btusb.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/bluetooth/btusb.c -+++ b/drivers/bluetooth/btusb.c -@@ -462,6 +462,8 @@ static const struct usb_device_id blackl - /* Additional Realtek 8761BU Bluetooth devices */ - { USB_DEVICE(0x0b05, 0x190e), .driver_info = BTUSB_REALTEK | - BTUSB_WIDEBAND_SPEECH }, -+ { USB_DEVICE(0x2550, 0x8761), .driver_info = BTUSB_REALTEK | -+ BTUSB_WIDEBAND_SPEECH }, - - /* Additional Realtek 8821AE Bluetooth devices */ - { USB_DEVICE(0x0b05, 0x17dc), .driver_info = BTUSB_REALTEK }, diff --git a/target/linux/generic/config-5.10 b/target/linux/generic/config-5.10 deleted file mode 100644 index 9c4aad86c1..0000000000 --- a/target/linux/generic/config-5.10 +++ /dev/null @@ -1,7205 +0,0 @@ -# CONFIG_104_QUAD_8 is not set -CONFIG_32BIT=y -CONFIG_64BIT_TIME=y -# CONFIG_6LOWPAN is not set -# CONFIG_6LOWPAN_DEBUGFS is not set -# CONFIG_6PACK is not set -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_9P_FS is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_AB8500_CORE is not set -# CONFIG_ABP060MG is not set -# CONFIG_ABX500_CORE is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_ACENIC is not set -# CONFIG_ACERHDF is not set -# CONFIG_ACER_WIRELESS is not set -# CONFIG_ACORN_PARTITION is not set -# CONFIG_ACPI_ALS is not set -# CONFIG_ACPI_APEI is not set -# CONFIG_ACPI_BUTTON is not set -# CONFIG_ACPI_CONFIGFS is not set -# CONFIG_ACPI_CUSTOM_METHOD is not set -# CONFIG_ACPI_EXTLOG is not set -# CONFIG_ACPI_HED is not set -# CONFIG_ACPI_NFIT is not set -# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set -# CONFIG_ACPI_TABLE_UPGRADE is not set -# CONFIG_ACPI_VIDEO is not set -# CONFIG_AD2S1200 is not set -# CONFIG_AD2S1210 is not set -# CONFIG_AD2S90 is not set -# CONFIG_AD5064 is not set -# CONFIG_AD525X_DPOT is not set -# CONFIG_AD5272 is not set -# CONFIG_AD5360 is not set -# CONFIG_AD5380 is not set -# CONFIG_AD5421 is not set -# CONFIG_AD5446 is not set -# CONFIG_AD5449 is not set -# CONFIG_AD5504 is not set -# CONFIG_AD5592R is not set -# CONFIG_AD5593R is not set -# CONFIG_AD5624R_SPI is not set -# CONFIG_AD5686 is not set -# CONFIG_AD5686_SPI is not set -# CONFIG_AD5696_I2C is not set -# CONFIG_AD5755 is not set -# CONFIG_AD5758 is not set -# CONFIG_AD5761 is not set -# CONFIG_AD5764 is not set -# CONFIG_AD5770R is not set -# CONFIG_AD5791 is not set -# CONFIG_AD5933 is not set -# CONFIG_AD7091R5 is not set -# CONFIG_AD7124 is not set -# CONFIG_AD7150 is not set -# CONFIG_AD7152 is not set -# CONFIG_AD7192 is not set -# CONFIG_AD7266 is not set -# CONFIG_AD7280 is not set -# CONFIG_AD7291 is not set -# CONFIG_AD7292 is not set -# CONFIG_AD7298 is not set -# CONFIG_AD7303 is not set -# CONFIG_AD7476 is not set -# CONFIG_AD7606 is not set -# CONFIG_AD7606_IFACE_PARALLEL is not set -# CONFIG_AD7606_IFACE_SPI is not set -# CONFIG_AD7746 is not set -# CONFIG_AD7766 is not set -# CONFIG_AD7768_1 is not set -# CONFIG_AD7780 is not set -# CONFIG_AD7791 is not set -# CONFIG_AD7793 is not set -# CONFIG_AD7816 is not set -# CONFIG_AD7887 is not set -# CONFIG_AD7923 is not set -# CONFIG_AD7949 is not set -# CONFIG_AD799X is not set -# CONFIG_AD8366 is not set -# CONFIG_AD8801 is not set -# CONFIG_AD9467 is not set -# CONFIG_AD9523 is not set -# CONFIG_AD9832 is not set -# CONFIG_AD9834 is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_ADE7854 is not set -# CONFIG_ADF4350 is not set -# CONFIG_ADF4371 is not set -# CONFIG_ADFS_FS is not set -# CONFIG_ADIN_PHY is not set -# CONFIG_ADIS16080 is not set -# CONFIG_ADIS16130 is not set -# CONFIG_ADIS16136 is not set -# CONFIG_ADIS16201 is not set -# CONFIG_ADIS16203 is not set -# CONFIG_ADIS16209 is not set -# CONFIG_ADIS16240 is not set -# CONFIG_ADIS16260 is not set -# CONFIG_ADIS16400 is not set -# CONFIG_ADIS16460 is not set -# CONFIG_ADIS16475 is not set -# CONFIG_ADIS16480 is not set -# CONFIG_ADI_AXI_ADC is not set -# CONFIG_ADJD_S311 is not set -# CONFIG_ADM6996_PHY is not set -# CONFIG_ADM8211 is not set -# CONFIG_ADT7316 is not set -# CONFIG_ADUX1020 is not set -CONFIG_ADVISE_SYSCALLS=y -# CONFIG_ADXL345_I2C is not set -# CONFIG_ADXL345_SPI is not set -# CONFIG_ADXL372_I2C is not set -# CONFIG_ADXL372_SPI is not set -# CONFIG_ADXRS290 is not set -# CONFIG_ADXRS450 is not set -CONFIG_AEABI=y -# CONFIG_AFE4403 is not set -# CONFIG_AFE4404 is not set -# CONFIG_AFFS_FS is not set -# CONFIG_AFS_DEBUG_CURSOR is not set -# CONFIG_AFS_FS is not set -# CONFIG_AF_KCM is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_AF_RXRPC_INJECT_LOSS is not set -# CONFIG_AF_RXRPC_IPV6 is not set -# CONFIG_AGP is not set -# CONFIG_AHCI_BRCM is not set -# CONFIG_AHCI_CEVA is not set -# CONFIG_AHCI_IMX is not set -# CONFIG_AHCI_MVEBU is not set -# CONFIG_AHCI_QORIQ is not set -# CONFIG_AHCI_XGENE is not set -CONFIG_AIO=y -# CONFIG_AIRO is not set -# CONFIG_AIRO_CS is not set -# CONFIG_AIX_PARTITION is not set -# CONFIG_AK09911 is not set -# CONFIG_AK8974 is not set -# CONFIG_AK8975 is not set -# CONFIG_AL3010 is not set -# CONFIG_AL3320A is not set -# CONFIG_ALIM7101_WDT is not set -CONFIG_ALLOW_DEV_COREDUMP=y -# CONFIG_ALTERA_MBOX is not set -# CONFIG_ALTERA_MSGDMA is not set -# CONFIG_ALTERA_STAPL is not set -# CONFIG_ALTERA_TSE is not set -# CONFIG_ALX is not set -# CONFIG_AL_FIC is not set -# CONFIG_AM2315 is not set -# CONFIG_AM335X_PHY_USB is not set -# CONFIG_AMBA_PL08X is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_AMD_MEM_ENCRYPT is not set -# CONFIG_AMD_PHY is not set -# CONFIG_AMD_XGBE is not set -# CONFIG_AMD_XGBE_HAVE_ECC is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_AMILO_RFKILL is not set -# CONFIG_ANDROID is not set -CONFIG_ANON_INODES=y -# CONFIG_APDS9300 is not set -# CONFIG_APDS9802ALS is not set -# CONFIG_APDS9960 is not set -# CONFIG_APM8018X is not set -# CONFIG_APM_EMULATION is not set -# CONFIG_APPLE_GMUX is not set -# CONFIG_APPLE_MFI_FASTCHARGE is not set -# CONFIG_APPLE_PROPERTIES is not set -# CONFIG_APPLICOM is not set -# CONFIG_AQTION is not set -# CONFIG_AQUANTIA_PHY is not set -# CONFIG_AR5523 is not set -# CONFIG_AR7 is not set -# CONFIG_AR8216_PHY is not set -# CONFIG_AR8216_PHY_LEDS is not set -# CONFIG_ARCH_ACTIONS is not set -# CONFIG_ARCH_AGILEX is not set -# CONFIG_ARCH_ALPINE is not set -# CONFIG_ARCH_ARTPEC is not set -# CONFIG_ARCH_ASPEED is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_AXXIA is not set -# CONFIG_ARCH_BCM is not set -# CONFIG_ARCH_BCM2835 is not set -# CONFIG_ARCH_BCM_21664 is not set -# CONFIG_ARCH_BCM_23550 is not set -# CONFIG_ARCH_BCM_281XX is not set -# CONFIG_ARCH_BCM_5301X is not set -# CONFIG_ARCH_BCM_53573 is not set -# CONFIG_ARCH_BCM_63XX is not set -# CONFIG_ARCH_BCM_CYGNUS is not set -# CONFIG_ARCH_BCM_IPROC is not set -# CONFIG_ARCH_BCM_NSP is not set -# CONFIG_ARCH_BERLIN is not set -CONFIG_ARCH_BINFMT_ELF_STATE=y -# CONFIG_ARCH_BITMAIN is not set -# CONFIG_ARCH_BRCMSTB is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CNS3XXX is not set -# CONFIG_ARCH_DAVINCI is not set -# CONFIG_ARCH_DIGICOLOR is not set -# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_EXYNOS is not set -CONFIG_ARCH_FLATMEM_ENABLE=y -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_GEMINI is not set -# CONFIG_ARCH_HI3xxx is not set -# CONFIG_ARCH_HIGHBANK is not set -# CONFIG_ARCH_HISI is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP13XX is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IOP33X is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_K3 is not set -# CONFIG_ARCH_KEEMBAY is not set -# CONFIG_ARCH_KEYSTONE is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_LAYERSCAPE is not set -# CONFIG_ARCH_LG1K is not set -# CONFIG_ARCH_LPC32XX is not set -# CONFIG_ARCH_MEDIATEK is not set -# CONFIG_ARCH_MESON is not set -# CONFIG_ARCH_MILBEAUT is not set -CONFIG_ARCH_MMAP_RND_BITS=8 -CONFIG_ARCH_MMAP_RND_BITS_MAX=16 -CONFIG_ARCH_MMAP_RND_BITS_MIN=8 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_MSTARV7 is not set -# CONFIG_ARCH_MULTIPLATFORM is not set -# CONFIG_ARCH_MULTI_V6 is not set -# CONFIG_ARCH_MULTI_V7 is not set -# CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_MVEBU is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_MXS is not set -# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set -# CONFIG_ARCH_NETX is not set -# CONFIG_ARCH_NOMADIK is not set -# CONFIG_ARCH_NPCM is not set -# CONFIG_ARCH_NSPIRE is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_OMAP1 is not set -# CONFIG_ARCH_OMAP2 is not set -# CONFIG_ARCH_OMAP2PLUS is not set -# CONFIG_ARCH_OMAP3 is not set -# CONFIG_ARCH_OMAP4 is not set -# CONFIG_ARCH_ORION5X is not set -# CONFIG_ARCH_OXNAS is not set -# CONFIG_ARCH_PICOXCELL is not set -# CONFIG_ARCH_PRIMA2 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_QCOM is not set -# CONFIG_ARCH_RANDOM is not set -# CONFIG_ARCH_RDA is not set -# CONFIG_ARCH_REALTEK is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_ROCKCHIP is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_S32 is not set -# CONFIG_ARCH_S3C24XX is not set -# CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5PV210 is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_SEATTLE is not set -# CONFIG_ARCH_SHMOBILE is not set -# CONFIG_ARCH_SIRF is not set -# CONFIG_ARCH_SOCFPGA is not set -# CONFIG_ARCH_SPARX5 is not set -# CONFIG_ARCH_SPRD is not set -# CONFIG_ARCH_STI is not set -# CONFIG_ARCH_STM32 is not set -# CONFIG_ARCH_STRATIX10 is not set -# CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_SYNQUACER is not set -# CONFIG_ARCH_TANGO is not set -# CONFIG_ARCH_TEGRA is not set -# CONFIG_ARCH_THUNDER is not set -# CONFIG_ARCH_THUNDER2 is not set -# CONFIG_ARCH_U300 is not set -# CONFIG_ARCH_U8500 is not set -# CONFIG_ARCH_UNIPHIER is not set -# CONFIG_ARCH_VERSATILE is not set -# CONFIG_ARCH_VEXPRESS is not set -# CONFIG_ARCH_VIRT is not set -# CONFIG_ARCH_VISCONTI is not set -# CONFIG_ARCH_VT8500 is not set -# CONFIG_ARCH_VULCAN is not set -# CONFIG_ARCH_W90X900 is not set -# CONFIG_ARCH_WANTS_THP_SWAP is not set -# CONFIG_ARCH_WM8505 is not set -# CONFIG_ARCH_WM8750 is not set -# CONFIG_ARCH_WM8850 is not set -# CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZX is not set -# CONFIG_ARCH_ZYNQ is not set -# CONFIG_ARCH_ZYNQMP is not set -# CONFIG_ARCNET is not set -# CONFIG_ARC_EMAC is not set -# CONFIG_ARC_IRQ_NO_AUTOSAVE is not set -# CONFIG_ARM64_16K_PAGES is not set -# CONFIG_ARM64_64K_PAGES is not set -# CONFIG_ARM64_AMU_EXTN is not set -# CONFIG_ARM64_BTI is not set -# CONFIG_ARM64_CRYPTO is not set -# CONFIG_ARM64_E0PD is not set -# CONFIG_ARM64_ERRATUM_1024718 is not set -# CONFIG_ARM64_ERRATUM_1165522 is not set -# CONFIG_ARM64_ERRATUM_1286807 is not set -# CONFIG_ARM64_ERRATUM_1319367 is not set -# CONFIG_ARM64_ERRATUM_1418040 is not set -# CONFIG_ARM64_ERRATUM_1463225 is not set -# CONFIG_ARM64_ERRATUM_1508412 is not set -# CONFIG_ARM64_ERRATUM_1530923 is not set -# CONFIG_ARM64_ERRATUM_1542419 is not set -# CONFIG_ARM64_ERRATUM_819472 is not set -# CONFIG_ARM64_ERRATUM_824069 is not set -# CONFIG_ARM64_ERRATUM_826319 is not set -# CONFIG_ARM64_ERRATUM_827319 is not set -# CONFIG_ARM64_ERRATUM_832075 is not set -# CONFIG_ARM64_ERRATUM_834220 is not set -# CONFIG_ARM64_ERRATUM_843419 is not set -# CONFIG_ARM64_ERRATUM_845719 is not set -# CONFIG_ARM64_ERRATUM_858921 is not set -# CONFIG_ARM64_HW_AFDBM is not set -# CONFIG_ARM64_LSE_ATOMICS is not set -# CONFIG_ARM64_MODULE_PLTS is not set -# CONFIG_ARM64_MTE is not set -# CONFIG_ARM64_PAN is not set -# CONFIG_ARM64_PMEM is not set -# CONFIG_ARM64_PSEUDO_NMI is not set -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -# CONFIG_ARM64_RAS_EXTN is not set -# CONFIG_ARM64_RELOC_TEST is not set -CONFIG_ARM64_SW_TTBR0_PAN=y -# CONFIG_ARM64_TLB_RANGE is not set -# CONFIG_ARM64_UAO is not set -# CONFIG_ARM64_USE_LSE_ATOMICS is not set -# CONFIG_ARM64_VA_BITS_48 is not set -# CONFIG_ARM64_VHE is not set -# CONFIG_ARM_APPENDED_DTB is not set -# CONFIG_ARM_ARCH_TIMER is not set -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set -# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set -# CONFIG_ARM_CCI is not set -# CONFIG_ARM_CCI400_PMU is not set -# CONFIG_ARM_CCI5xx_PMU is not set -# CONFIG_ARM_CCI_PMU is not set -# CONFIG_ARM_CCN is not set -# CONFIG_ARM_CMN is not set -# CONFIG_ARM_CPUIDLE is not set -CONFIG_ARM_CPU_TOPOLOGY=y -# CONFIG_ARM_CRYPTO is not set -CONFIG_ARM_DMA_MEM_BUFFERABLE=y -# CONFIG_ARM_DSU_PMU is not set -# CONFIG_ARM_ERRATA_326103 is not set -# CONFIG_ARM_ERRATA_364296 is not set -# CONFIG_ARM_ERRATA_411920 is not set -# CONFIG_ARM_ERRATA_430973 is not set -# CONFIG_ARM_ERRATA_458693 is not set -# CONFIG_ARM_ERRATA_460075 is not set -# CONFIG_ARM_ERRATA_643719 is not set -# CONFIG_ARM_ERRATA_720789 is not set -# CONFIG_ARM_ERRATA_742230 is not set -# CONFIG_ARM_ERRATA_742231 is not set -# CONFIG_ARM_ERRATA_743622 is not set -# CONFIG_ARM_ERRATA_751472 is not set -# CONFIG_ARM_ERRATA_754322 is not set -# CONFIG_ARM_ERRATA_754327 is not set -# CONFIG_ARM_ERRATA_764369 is not set -# CONFIG_ARM_ERRATA_773022 is not set -# CONFIG_ARM_ERRATA_775420 is not set -# CONFIG_ARM_ERRATA_798181 is not set -# CONFIG_ARM_ERRATA_814220 is not set -# CONFIG_ARM_ERRATA_818325_852422 is not set -# CONFIG_ARM_ERRATA_821420 is not set -# CONFIG_ARM_ERRATA_825619 is not set -# CONFIG_ARM_ERRATA_852421 is not set -# CONFIG_ARM_ERRATA_852423 is not set -# CONFIG_ARM_ERRATA_857271 is not set -# CONFIG_ARM_ERRATA_857272 is not set -CONFIG_ARM_GIC_MAX_NR=1 -# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set -# CONFIG_ARM_KPROBES_TEST is not set -# CONFIG_ARM_LPAE is not set -# CONFIG_ARM_MHU is not set -# CONFIG_ARM_MODULE_PLTS is not set -# CONFIG_ARM_PATCH_PHYS_VIRT is not set -# CONFIG_ARM_PSCI is not set -# CONFIG_ARM_PSCI_CHECKER is not set -# CONFIG_ARM_PSCI_CPUIDLE is not set -# CONFIG_ARM_PTDUMP_DEBUGFS is not set -# CONFIG_ARM_SBSA_WATCHDOG is not set -# CONFIG_ARM_SCMI_PROTOCOL is not set -# CONFIG_ARM_SCPI_PROTOCOL is not set -# CONFIG_ARM_SDE_INTERFACE is not set -# CONFIG_ARM_SMCCC_SOC_ID is not set -# CONFIG_ARM_SMC_WATCHDOG is not set -# CONFIG_ARM_SP805_WATCHDOG is not set -# CONFIG_ARM_SPE_PMU is not set -# CONFIG_ARM_THUMBEE is not set -# CONFIG_ARM_TIMER_SP804 is not set -# CONFIG_ARM_UNWIND is not set -# CONFIG_ARM_VIRT_EXT is not set -# CONFIG_AS3935 is not set -# CONFIG_AS73211 is not set -# CONFIG_ASM9260_TIMER is not set -# CONFIG_ASN1 is not set -# CONFIG_ASUS_LAPTOP is not set -# CONFIG_ASUS_WIRELESS is not set -# CONFIG_ASYMMETRIC_KEY_TYPE is not set -# CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE is not set -# CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE is not set -# CONFIG_ASYNC_RAID6_TEST is not set -# CONFIG_ASYNC_TX_DMA is not set -# CONFIG_AT76C50X_USB is not set -# CONFIG_AT803X_PHY is not set -# CONFIG_AT91_SAMA5D2_ADC is not set -# CONFIG_ATA is not set -# CONFIG_ATAGS is not set -CONFIG_ATAGS_PROC=y -# CONFIG_ATALK is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_ATA_ACPI is not set -CONFIG_ATA_BMDMA=y -# CONFIG_ATA_FORCE is not set -# CONFIG_ATA_GENERIC is not set -# CONFIG_ATA_LEDS is not set -# CONFIG_ATA_NONSTANDARD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_ATA_PIIX is not set -CONFIG_ATA_SFF=y -# CONFIG_ATA_VERBOSE_ERROR is not set -# CONFIG_ATH10K is not set -# CONFIG_ATH25 is not set -# CONFIG_ATH5K is not set -# CONFIG_ATH6KL is not set -# CONFIG_ATH79 is not set -# CONFIG_ATH9K is not set -# CONFIG_ATH9K_HTC is not set -# CONFIG_ATH_DEBUG is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1C is not set -# CONFIG_ATL1E is not set -# CONFIG_ATL2 is not set -# CONFIG_ATLAS_EZO_SENSOR is not set -# CONFIG_ATLAS_PH_SENSOR is not set -# CONFIG_ATM is not set -# CONFIG_ATMEL is not set -# CONFIG_ATMEL_PIT is not set -# CONFIG_ATMEL_SSC is not set -# CONFIG_ATM_AMBASSADOR is not set -# CONFIG_ATM_BR2684 is not set -CONFIG_ATM_BR2684_IPFILTER=y -# CONFIG_ATM_CLIP is not set -CONFIG_ATM_CLIP_NO_ICMP=y -# CONFIG_ATM_DRIVERS is not set -# CONFIG_ATM_DUMMY is not set -# CONFIG_ATM_ENI is not set -# CONFIG_ATM_FIRESTREAM is not set -# CONFIG_ATM_FORE200E is not set -# CONFIG_ATM_HE is not set -# CONFIG_ATM_HORIZON is not set -# CONFIG_ATM_IA is not set -# CONFIG_ATM_IDT77252 is not set -# CONFIG_ATM_LANAI is not set -# CONFIG_ATM_LANE is not set -# CONFIG_ATM_MPOA is not set -# CONFIG_ATM_NICSTAR is not set -# CONFIG_ATM_SOLOS is not set -# CONFIG_ATM_TCP is not set -# CONFIG_ATM_ZATM is not set -# CONFIG_ATOMIC64_SELFTEST is not set -# CONFIG_ATP is not set -# CONFIG_AUDIT is not set -# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set -# CONFIG_AURORA_NB8800 is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTO_ZRELADDR is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_AX25 is not set -# CONFIG_AX25_DAMA_SLAVE is not set -# CONFIG_AX88796 is not set -# CONFIG_AX88796B_PHY is not set -# CONFIG_AXP20X_ADC is not set -# CONFIG_AXP20X_POWER is not set -# CONFIG_AXP288_ADC is not set -# CONFIG_AXP288_FUEL_GAUGE is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -# CONFIG_B44 is not set -# CONFIG_B53 is not set -# CONFIG_B53_MDIO_DRIVER is not set -# CONFIG_B53_MMAP_DRIVER is not set -# CONFIG_B53_SERDES is not set -# CONFIG_B53_SPI_DRIVER is not set -# CONFIG_B53_SRAB_DRIVER is not set -# CONFIG_BACKLIGHT_ADP8860 is not set -# CONFIG_BACKLIGHT_ADP8870 is not set -# CONFIG_BACKLIGHT_APPLE is not set -# CONFIG_BACKLIGHT_ARCXCNN is not set -# CONFIG_BACKLIGHT_BD6107 is not set -# CONFIG_BACKLIGHT_CLASS_DEVICE is not set -# CONFIG_BACKLIGHT_GENERIC is not set -# CONFIG_BACKLIGHT_GPIO is not set -# CONFIG_BACKLIGHT_KTD253 is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -# CONFIG_BACKLIGHT_LED is not set -# CONFIG_BACKLIGHT_LM3630A is not set -# CONFIG_BACKLIGHT_LM3639 is not set -# CONFIG_BACKLIGHT_LP855X is not set -# CONFIG_BACKLIGHT_LV5207LP is not set -# CONFIG_BACKLIGHT_PANDORA is not set -# CONFIG_BACKLIGHT_PM8941_WLED is not set -# CONFIG_BACKLIGHT_PWM is not set -# CONFIG_BACKLIGHT_QCOM_WLED is not set -# CONFIG_BACKLIGHT_RPI is not set -# CONFIG_BACKLIGHT_SAHARA is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_BAREUDP is not set -CONFIG_BASE_FULL=y -CONFIG_BASE_SMALL=0 -# CONFIG_BATMAN_ADV is not set -# CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_BQ27XXX_HDQ is not set -# CONFIG_BATTERY_CW2015 is not set -# CONFIG_BATTERY_DS2760 is not set -# CONFIG_BATTERY_DS2780 is not set -# CONFIG_BATTERY_DS2781 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_GAUGE_LTC2941 is not set -# CONFIG_BATTERY_GOLDFISH is not set -# CONFIG_BATTERY_LEGO_EV3 is not set -# CONFIG_BATTERY_MAX17040 is not set -# CONFIG_BATTERY_MAX17042 is not set -# CONFIG_BATTERY_MAX1721X is not set -# CONFIG_BATTERY_RT5033 is not set -# CONFIG_BATTERY_SBS is not set -# CONFIG_BAYCOM_EPP is not set -# CONFIG_BAYCOM_PAR is not set -# CONFIG_BAYCOM_SER_FDX is not set -# CONFIG_BAYCOM_SER_HDX is not set -# CONFIG_BCACHE is not set -# CONFIG_BCM47XX is not set -# CONFIG_BCM54140_PHY is not set -# CONFIG_BCM63XX is not set -# CONFIG_BCM63XX_PHY is not set -# CONFIG_BCM7038_WDT is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM84881_PHY is not set -# CONFIG_BCM87XX_PHY is not set -# CONFIG_BCMA is not set -# CONFIG_BCMA_DRIVER_GPIO is not set -CONFIG_BCMA_POSSIBLE=y -# CONFIG_BCMGENET is not set -# CONFIG_BCM_IPROC_ADC is not set -# CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_BCM_SBA_RAID is not set -# CONFIG_BDI_SWITCH is not set -# CONFIG_BE2ISCSI is not set -# CONFIG_BE2NET is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_BGMAC is not set -# CONFIG_BH1750 is not set -# CONFIG_BH1780 is not set -# CONFIG_BIG_KEYS is not set -# CONFIG_BIG_LITTLE is not set -# CONFIG_BINARY_PRINTF is not set -# CONFIG_BINFMT_AOUT is not set -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_ELF_FDPIC is not set -# CONFIG_BINFMT_FLAT is not set -# CONFIG_BINFMT_MISC is not set -CONFIG_BINFMT_SCRIPT=y -CONFIG_BITREVERSE=y -# CONFIG_BLK_CGROUP_IOCOST is not set -# CONFIG_BLK_CGROUP_IOLATENCY is not set -# CONFIG_BLK_CMDLINE_PARSER is not set -# CONFIG_BLK_DEBUG_FS is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_BLK_DEV_4DRIVES is not set -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI14XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_BLK_DEV_ATIIXP is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_BSGLIB is not set -# CONFIG_BLK_DEV_CMD640 is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_CS5535 is not set -# CONFIG_BLK_DEV_CS5536 is not set -# CONFIG_BLK_DEV_CY82C693 is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_DELKIN is not set -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_DTC2278 is not set -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_GENERIC is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_HT6560B is not set -# CONFIG_BLK_DEV_IDEACPI is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDECS is not set -# CONFIG_BLK_DEV_IDEPCI is not set -# CONFIG_BLK_DEV_IDEPNP is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDE_AU1XXX is not set -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_INITRD=y -# CONFIG_BLK_DEV_INTEGRITY is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_BLK_DEV_IT8172 is not set -# CONFIG_BLK_DEV_IT8213 is not set -# CONFIG_BLK_DEV_IT821X is not set -# CONFIG_BLK_DEV_JMICRON is not set -# CONFIG_BLK_DEV_LOOP is not set -CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_NULL_BLK is not set -# CONFIG_BLK_DEV_NVME is not set -# CONFIG_BLK_DEV_OFFBOARD is not set -# CONFIG_BLK_DEV_OPTI621 is not set -# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_PLATFORM is not set -# CONFIG_BLK_DEV_PMEM is not set -# CONFIG_BLK_DEV_QD65XX is not set -# CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set -# CONFIG_BLK_DEV_RZ1000 is not set -# CONFIG_BLK_DEV_SC1200 is not set -# CONFIG_BLK_DEV_SD is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SIS5513 is not set -# CONFIG_BLK_DEV_SKD is not set -# CONFIG_BLK_DEV_SL82C105 is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_TC86C001 is not set -# CONFIG_BLK_DEV_THROTTLING is not set -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_UMC8672 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_BLK_DEV_ZONED is not set -# CONFIG_BLK_INLINE_ENCRYPTION is not set -# CONFIG_BLK_SED_OPAL is not set -# CONFIG_BLK_WBT is not set -CONFIG_BLOCK=y -# CONFIG_BMA180 is not set -# CONFIG_BMA220 is not set -# CONFIG_BMA400 is not set -# CONFIG_BMC150_ACCEL is not set -# CONFIG_BMC150_MAGN is not set -# CONFIG_BMC150_MAGN_I2C is not set -# CONFIG_BMC150_MAGN_SPI is not set -# CONFIG_BME680 is not set -# CONFIG_BMG160 is not set -# CONFIG_BMI160_I2C is not set -# CONFIG_BMI160_SPI is not set -# CONFIG_BMIPS_GENERIC is not set -# CONFIG_BMP280 is not set -# CONFIG_BNA is not set -# CONFIG_BNX2 is not set -# CONFIG_BNX2X is not set -# CONFIG_BNX2X_SRIOV is not set -# CONFIG_BNXT is not set -# CONFIG_BONDING is not set -# CONFIG_BOOKE_WDT is not set -CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT=3 -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -# CONFIG_BOOTTIME_TRACING is not set -# CONFIG_BOOT_CONFIG is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -CONFIG_BOOT_RAW=y -# CONFIG_BOUNCE is not set -CONFIG_BPF=y -# CONFIG_BPFILTER is not set -CONFIG_BPF_JIT=y -# CONFIG_BPF_JIT_ALWAYS_ON is not set -CONFIG_BPF_JIT_DEFAULT_ON=y -# CONFIG_BPF_PRELOAD is not set -# CONFIG_BPF_STREAM_PARSER is not set -CONFIG_BPF_SYSCALL=y -CONFIG_BPF_UNPRIV_DEFAULT_OFF=y -# CONFIG_BPQETHER is not set -CONFIG_BQL=y -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_BRCMFMAC is not set -# CONFIG_BRCMSMAC is not set -# CONFIG_BRCMSTB_GISB_ARB is not set -CONFIG_BRIDGE=y -# CONFIG_BRIDGE_EBT_802_3 is not set -# CONFIG_BRIDGE_EBT_AMONG is not set -# CONFIG_BRIDGE_EBT_ARP is not set -# CONFIG_BRIDGE_EBT_ARPREPLY is not set -# CONFIG_BRIDGE_EBT_BROUTE is not set -# CONFIG_BRIDGE_EBT_DNAT is not set -# CONFIG_BRIDGE_EBT_IP is not set -# CONFIG_BRIDGE_EBT_IP6 is not set -# CONFIG_BRIDGE_EBT_LIMIT is not set -# CONFIG_BRIDGE_EBT_LOG is not set -# CONFIG_BRIDGE_EBT_MARK is not set -# CONFIG_BRIDGE_EBT_MARK_T is not set -# CONFIG_BRIDGE_EBT_NFLOG is not set -# CONFIG_BRIDGE_EBT_PKTTYPE is not set -# CONFIG_BRIDGE_EBT_REDIRECT is not set -# CONFIG_BRIDGE_EBT_SNAT is not set -# CONFIG_BRIDGE_EBT_STP is not set -# CONFIG_BRIDGE_EBT_T_FILTER is not set -# CONFIG_BRIDGE_EBT_T_NAT is not set -# CONFIG_BRIDGE_EBT_VLAN is not set -CONFIG_BRIDGE_IGMP_SNOOPING=y -# CONFIG_BRIDGE_MRP is not set -# CONFIG_BRIDGE_NETFILTER is not set -# CONFIG_BRIDGE_NF_EBTABLES is not set -CONFIG_BRIDGE_VLAN_FILTERING=y -# CONFIG_BROADCOM_PHY is not set -CONFIG_BROKEN_ON_SMP=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_BT is not set -# CONFIG_BTRFS_ASSERT is not set -# CONFIG_BTRFS_DEBUG is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_BTRFS_FS_POSIX_ACL is not set -# CONFIG_BTRFS_FS_REF_VERIFY is not set -# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set -# CONFIG_BT_ATH3K is not set -# CONFIG_BT_BNEP is not set -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -# CONFIG_BT_BREDR is not set -# CONFIG_BT_CMTP is not set -# CONFIG_BT_FEATURE_DEBUG is not set -# CONFIG_BT_HCIBCM203X is not set -# CONFIG_BT_HCIBFUSB is not set -# CONFIG_BT_HCIBLUECARD is not set -# CONFIG_BT_HCIBPA10X is not set -# CONFIG_BT_HCIBT3C is not set -# CONFIG_BT_HCIBTSDIO is not set -# CONFIG_BT_HCIBTUSB is not set -# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set -# CONFIG_BT_HCIBTUSB_MTK is not set -# CONFIG_BT_HCIBTUSB_RTL is not set -# CONFIG_BT_HCIDTL1 is not set -# CONFIG_BT_HCIUART is not set -# CONFIG_BT_HCIUART_3WIRE is not set -# CONFIG_BT_HCIUART_AG6XX is not set -# CONFIG_BT_HCIUART_ATH3K is not set -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_H4=y -# CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIUART_MRVL is not set -# CONFIG_BT_HCIUART_QCA is not set -# CONFIG_BT_HCIUART_RTL is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_HIDP is not set -# CONFIG_BT_HS is not set -# CONFIG_BT_LE is not set -# CONFIG_BT_LEDS is not set -# CONFIG_BT_MRVL is not set -# CONFIG_BT_MSFTEXT is not set -# CONFIG_BT_MTKSDIO is not set -# CONFIG_BT_MTKUART is not set -# CONFIG_BT_RFCOMM is not set -CONFIG_BT_RFCOMM_TTY=y -# CONFIG_BT_SELFTEST is not set -CONFIG_BUG=y -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -CONFIG_BUILDTIME_EXTABLE_SORT=y -CONFIG_BUILDTIME_TABLE_SORT=y -# CONFIG_BUILD_BIN2C is not set -CONFIG_BUILD_SALT="" -# CONFIG_C2PORT is not set -CONFIG_CACHE_L2X0_PMU=y -# CONFIG_CADENCE_WATCHDOG is not set -# CONFIG_CAIF is not set -# CONFIG_CAN is not set -# CONFIG_CAN_BCM is not set -# CONFIG_CAN_DEBUG_DEVICES is not set -# CONFIG_CAN_DEV is not set -# CONFIG_CAN_GS_USB is not set -# CONFIG_CAN_GW is not set -# CONFIG_CAN_HI311X is not set -# CONFIG_CAN_IFI_CANFD is not set -# CONFIG_CAN_ISOTP is not set -# CONFIG_CAN_J1939 is not set -# CONFIG_CAN_KVASER_PCIEFD is not set -# CONFIG_CAN_MCBA_USB is not set -# CONFIG_CAN_MCP251XFD is not set -# CONFIG_CAN_M_CAN is not set -# CONFIG_CAN_PEAK_PCIEFD is not set -# CONFIG_CAN_RAW is not set -# CONFIG_CAN_RCAR is not set -# CONFIG_CAN_RCAR_CANFD is not set -# CONFIG_CAN_SLCAN is not set -# CONFIG_CAN_SUN4I is not set -# CONFIG_CAN_UCAN is not set -# CONFIG_CAN_VCAN is not set -# CONFIG_CAN_VXCAN is not set -# CONFIG_CAPI_AVM is not set -# CONFIG_CAPI_EICON is not set -# CONFIG_CAPI_TRACE is not set -CONFIG_CARDBUS=y -# CONFIG_CARDMAN_4000 is not set -# CONFIG_CARDMAN_4040 is not set -# CONFIG_CARL9170 is not set -# CONFIG_CASSINI is not set -# CONFIG_CAVIUM_CPT is not set -# CONFIG_CAVIUM_ERRATUM_22375 is not set -# CONFIG_CAVIUM_ERRATUM_23144 is not set -# CONFIG_CAVIUM_ERRATUM_23154 is not set -# CONFIG_CAVIUM_ERRATUM_27456 is not set -# CONFIG_CAVIUM_ERRATUM_30115 is not set -# CONFIG_CAVIUM_OCTEON_SOC is not set -# CONFIG_CAVIUM_PTP is not set -# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set -# CONFIG_CB710_CORE is not set -# CONFIG_CC10001_ADC is not set -# CONFIG_CCS811 is not set -CONFIG_CC_CAN_LINK=y -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_CEPH_FS is not set -# CONFIG_CEPH_LIB is not set -# CONFIG_CFG80211 is not set -# CONFIG_CFG80211_CERTIFICATION_ONUS is not set -# CONFIG_CGROUPS is not set -# CONFIG_CHARGER_ADP5061 is not set -# CONFIG_CHARGER_BD99954 is not set -# CONFIG_CHARGER_BQ2415X is not set -# CONFIG_CHARGER_BQ24190 is not set -# CONFIG_CHARGER_BQ24257 is not set -# CONFIG_CHARGER_BQ24735 is not set -# CONFIG_CHARGER_BQ2515X is not set -# CONFIG_CHARGER_BQ25890 is not set -# CONFIG_CHARGER_BQ25980 is not set -# CONFIG_CHARGER_DETECTOR_MAX14656 is not set -# CONFIG_CHARGER_GPIO is not set -# CONFIG_CHARGER_ISP1704 is not set -# CONFIG_CHARGER_LP8727 is not set -# CONFIG_CHARGER_LT3651 is not set -# CONFIG_CHARGER_LTC3651 is not set -# CONFIG_CHARGER_MANAGER is not set -# CONFIG_CHARGER_MAX8903 is not set -# CONFIG_CHARGER_RT9455 is not set -# CONFIG_CHARGER_SBS is not set -# CONFIG_CHARGER_SMB347 is not set -# CONFIG_CHARGER_TWL4030 is not set -# CONFIG_CHARGER_UCS1002 is not set -# CONFIG_CHASH_SELFTEST is not set -# CONFIG_CHASH_STATS is not set -# CONFIG_CHECKPOINT_RESTORE is not set -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_CHELSIO_T4 is not set -# CONFIG_CHELSIO_T4VF is not set -# CONFIG_CHROME_PLATFORMS is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_CIFS is not set -# CONFIG_CIFS_ACL is not set -CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_DEBUG is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_FSCACHE is not set -# CONFIG_CIFS_NFSD_EXPORT is not set -CONFIG_CIFS_POSIX=y -# CONFIG_CIFS_SMB2 is not set -# CONFIG_CIFS_STATS is not set -# CONFIG_CIFS_STATS2 is not set -# CONFIG_CIFS_WEAK_PW_HASH is not set -CONFIG_CIFS_XATTR=y -# CONFIG_CIO_DAC is not set -# CONFIG_CLEANCACHE is not set -# CONFIG_CLKSRC_VERSATILE is not set -# CONFIG_CLK_HSDK is not set -# CONFIG_CLK_QORIQ is not set -# CONFIG_CLOCK_THERMAL is not set -CONFIG_CLS_U32_MARK=y -# CONFIG_CLS_U32_PERF is not set -# CONFIG_CM32181 is not set -# CONFIG_CM3232 is not set -# CONFIG_CM3323 is not set -# CONFIG_CM3605 is not set -# CONFIG_CM36651 is not set -# CONFIG_CMA is not set -CONFIG_CMDLINE="" -# CONFIG_CMDLINE_BOOL is not set -# CONFIG_CMDLINE_EXTEND is not set -# CONFIG_CMDLINE_FORCE is not set -# CONFIG_CMDLINE_FROM_BOOTLOADER is not set -# CONFIG_CMDLINE_PARTITION is not set -# CONFIG_CNIC is not set -# CONFIG_CODA_FS is not set -# CONFIG_CODE_PATCHING_SELFTEST is not set -# CONFIG_COMEDI is not set -# CONFIG_COMMON_CLK_CDCE706 is not set -# CONFIG_COMMON_CLK_CDCE925 is not set -# CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_COMMON_CLK_FIXED_MMIO is not set -# CONFIG_COMMON_CLK_IPROC is not set -# CONFIG_COMMON_CLK_MAX9485 is not set -# CONFIG_COMMON_CLK_MT6765 is not set -# CONFIG_COMMON_CLK_MT8167 is not set -# CONFIG_COMMON_CLK_MT8167_AUDSYS is not set -# CONFIG_COMMON_CLK_MT8167_IMGSYS is not set -# CONFIG_COMMON_CLK_MT8167_MFGCFG is not set -# CONFIG_COMMON_CLK_MT8167_MMSYS is not set -# CONFIG_COMMON_CLK_MT8167_VDECSYS is not set -# CONFIG_COMMON_CLK_NXP is not set -# CONFIG_COMMON_CLK_PIC32 is not set -# CONFIG_COMMON_CLK_PWM is not set -# CONFIG_COMMON_CLK_PXA is not set -# CONFIG_COMMON_CLK_QCOM is not set -# CONFIG_COMMON_CLK_SI514 is not set -# CONFIG_COMMON_CLK_SI5341 is not set -# CONFIG_COMMON_CLK_SI5351 is not set -# CONFIG_COMMON_CLK_SI544 is not set -# CONFIG_COMMON_CLK_SI570 is not set -# CONFIG_COMMON_CLK_VC5 is not set -# CONFIG_COMMON_CLK_XGENE is not set -# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set -CONFIG_COMPACTION=y -# CONFIG_COMPAL_LAPTOP is not set -# CONFIG_COMPAT is not set -# CONFIG_COMPAT_BRK is not set -# CONFIG_COMPILE_TEST is not set -# CONFIG_CONFIGFS_FS is not set -# CONFIG_CONNECTOR is not set -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -CONFIG_CONSTRUCTORS=y -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_COPS is not set -# CONFIG_CORDIC is not set -# CONFIG_COREDUMP is not set -# CONFIG_CORESIGHT is not set -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_CORTINA_PHY is not set -# CONFIG_COUNTER is not set -# CONFIG_CPA_DEBUG is not set -# CONFIG_CPU_BIG_ENDIAN is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_FREQ is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set -# CONFIG_CPU_FREQ_STAT_DETAILS is not set -# CONFIG_CPU_FREQ_THERMAL is not set -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set -# CONFIG_CPU_IDLE is not set -# CONFIG_CPU_IDLE_GOV_LADDER is not set -# CONFIG_CPU_IDLE_GOV_MENU is not set -# CONFIG_CPU_IDLE_GOV_TEO is not set -# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set -# CONFIG_CPU_ISOLATION is not set -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_NO_EFFICIENT_FFS is not set -CONFIG_CPU_SW_DOMAIN_PAN=y -# CONFIG_CPU_THERMAL is not set -# CONFIG_CRAMFS is not set -CONFIG_CRAMFS_BLOCKDEV=y -# CONFIG_CRAMFS_MTD is not set -# CONFIG_CRASH_DUMP is not set -# CONFIG_CRC16 is not set -CONFIG_CRC32=y -# CONFIG_CRC32_BIT is not set -CONFIG_CRC32_SARWATE=y -# CONFIG_CRC32_SELFTEST is not set -# CONFIG_CRC32_SLICEBY4 is not set -# CONFIG_CRC32_SLICEBY8 is not set -# CONFIG_CRC4 is not set -# CONFIG_CRC64 is not set -# CONFIG_CRC7 is not set -# CONFIG_CRC8 is not set -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC_ITU_T is not set -# CONFIG_CRC_T10DIF is not set -CONFIG_CROSS_COMPILE="" -# CONFIG_CROSS_MEMORY_ATTACH is not set -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_842 is not set -CONFIG_CRYPTO_ACOMP2=y -# CONFIG_CRYPTO_ADIANTUM is not set -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -# CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128L is not set -# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set -# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set -# CONFIG_CRYPTO_AEGIS256 is not set -# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set -CONFIG_CRYPTO_AES=y -# CONFIG_CRYPTO_AES_586 is not set -# CONFIG_CRYPTO_AES_ARM is not set -# CONFIG_CRYPTO_AES_ARM64 is not set -# CONFIG_CRYPTO_AES_ARM64_BS is not set -# CONFIG_CRYPTO_AES_ARM64_CE is not set -# CONFIG_CRYPTO_AES_ARM64_CE_BLK is not set -# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set -# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set -# CONFIG_CRYPTO_AES_ARM_BS is not set -# CONFIG_CRYPTO_AES_ARM_CE is not set -# CONFIG_CRYPTO_AES_NI_INTEL is not set -# CONFIG_CRYPTO_AES_TI is not set -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_BLAKE2B is not set -# CONFIG_CRYPTO_BLAKE2S is not set -# CONFIG_CRYPTO_BLAKE2S_ARM is not set -# CONFIG_CRYPTO_BLAKE2S_X86 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_CBC is not set -CONFIG_CRYPTO_CCM=y -# CONFIG_CRYPTO_CFB is not set -# CONFIG_CRYPTO_CHACHA20 is not set -# CONFIG_CRYPTO_CHACHA20POLY1305 is not set -# CONFIG_CRYPTO_CHACHA20_NEON is not set -# CONFIG_CRYPTO_CHACHA20_X86_64 is not set -# CONFIG_CRYPTO_CHACHA_MIPS is not set -# CONFIG_CRYPTO_CMAC is not set -# CONFIG_CRYPTO_CRC32 is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CRC32C_INTEL is not set -# CONFIG_CRYPTO_CRC32_ARM_CE is not set -# CONFIG_CRYPTO_CRCT10DIF is not set -# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set -# CONFIG_CRYPTO_CRCT10DIF_ARM_CE is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_CTR=y -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_CURVE25519 is not set -# CONFIG_CRYPTO_CURVE25519_NEON is not set -# CONFIG_CRYPTO_CURVE25519_X86 is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set -# CONFIG_CRYPTO_DEV_ATMEL_AES is not set -# CONFIG_CRYPTO_DEV_ATMEL_AUTHENC is not set -# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set -# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set -# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set -# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set -# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set -# CONFIG_CRYPTO_DEV_CCP is not set -# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set -# CONFIG_CRYPTO_DEV_CCREE is not set -# CONFIG_CRYPTO_DEV_FSL_CAAM is not set -# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set -# CONFIG_CRYPTO_DEV_HIFN_795X is not set -# CONFIG_CRYPTO_DEV_HISI_SEC is not set -# CONFIG_CRYPTO_DEV_HISI_ZIP is not set -# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set -# CONFIG_CRYPTO_DEV_MARVELL_CESA is not set -# CONFIG_CRYPTO_DEV_MEDIATEK is not set -# CONFIG_CRYPTO_DEV_MV_CESA is not set -# CONFIG_CRYPTO_DEV_MXC_SCC is not set -# CONFIG_CRYPTO_DEV_MXS_DCP is not set -# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set -# CONFIG_CRYPTO_DEV_OCTEONTX_CPT is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set -# CONFIG_CRYPTO_DEV_QAT_C62X is not set -# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set -# CONFIG_CRYPTO_DEV_QCE is not set -# CONFIG_CRYPTO_DEV_S5P is not set -# CONFIG_CRYPTO_DEV_SAFEXCEL is not set -# CONFIG_CRYPTO_DEV_SAHARA is not set -# CONFIG_CRYPTO_DEV_SP_PSP is not set -# CONFIG_CRYPTO_DEV_TALITOS is not set -# CONFIG_CRYPTO_DEV_VIRTIO is not set -# CONFIG_CRYPTO_DH is not set -# CONFIG_CRYPTO_DRBG_CTR is not set -# CONFIG_CRYPTO_DRBG_HASH is not set -# CONFIG_CRYPTO_DRBG_MENU is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_ECDH is not set -# CONFIG_CRYPTO_ECHAINIV is not set -# CONFIG_CRYPTO_ECRDSA is not set -# CONFIG_CRYPTO_ESSIV is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_FIPS is not set -CONFIG_CRYPTO_GCM=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_GHASH=y -# CONFIG_CRYPTO_GHASH_ARM64_CE is not set -# CONFIG_CRYPTO_GHASH_ARM_CE is not set -# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_HW is not set -# CONFIG_CRYPTO_JITTERENTROPY is not set -# CONFIG_CRYPTO_KEYWRAP is not set -# CONFIG_CRYPTO_KHAZAD is not set -CONFIG_CRYPTO_KPP=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y -# CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC is not set -# CONFIG_CRYPTO_LIB_CHACHA is not set -# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set -# CONFIG_CRYPTO_LIB_CURVE25519 is not set -# CONFIG_CRYPTO_LIB_POLY1305 is not set -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_LZ4 is not set -# CONFIG_CRYPTO_LZ4HC is not set -# CONFIG_CRYPTO_LZO is not set -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -# CONFIG_CRYPTO_MCRYPTD is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_MORUS1280 is not set -# CONFIG_CRYPTO_MORUS1280_AVX2 is not set -# CONFIG_CRYPTO_MORUS1280_SSE2 is not set -# CONFIG_CRYPTO_MORUS640 is not set -# CONFIG_CRYPTO_MORUS640_SSE2 is not set -# CONFIG_CRYPTO_NHPOLY1305_NEON is not set -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -# CONFIG_CRYPTO_OFB is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_PCOMP is not set -# CONFIG_CRYPTO_PCOMP2 is not set -CONFIG_CRYPTO_PCRYPT=y -# CONFIG_CRYPTO_POLY1305 is not set -# CONFIG_CRYPTO_POLY1305_ARM is not set -# CONFIG_CRYPTO_POLY1305_MIPS is not set -# CONFIG_CRYPTO_POLY1305_NEON is not set -# CONFIG_CRYPTO_POLY1305_X86_64 is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_RNG is not set -# CONFIG_CRYPTO_RSA is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SALSA20_586 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SEQIV is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA1_ARM is not set -# CONFIG_CRYPTO_SHA1_ARM64_CE is not set -# CONFIG_CRYPTO_SHA1_ARM_CE is not set -# CONFIG_CRYPTO_SHA1_ARM_NEON is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA256_ARM is not set -# CONFIG_CRYPTO_SHA256_ARM64 is not set -# CONFIG_CRYPTO_SHA2_ARM64_CE is not set -# CONFIG_CRYPTO_SHA2_ARM_CE is not set -# CONFIG_CRYPTO_SHA3 is not set -# CONFIG_CRYPTO_SHA3_ARM64 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_SHA512_ARM is not set -# CONFIG_CRYPTO_SHA512_ARM64 is not set -# CONFIG_CRYPTO_SHA512_ARM64_CE is not set -# CONFIG_CRYPTO_SIMD is not set -CONFIG_CRYPTO_SKCIPHER=y -CONFIG_CRYPTO_SKCIPHER2=y -# CONFIG_CRYPTO_SM2 is not set -# CONFIG_CRYPTO_SM3 is not set -# CONFIG_CRYPTO_SM3_ARM64_CE is not set -# CONFIG_CRYPTO_SM4 is not set -# CONFIG_CRYPTO_SM4_ARM64_CE is not set -# CONFIG_CRYPTO_SPECK is not set -# CONFIG_CRYPTO_STATS is not set -# CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_TWOFISH_586 is not set -# CONFIG_CRYPTO_TWOFISH_COMMON is not set -# CONFIG_CRYPTO_USER is not set -# CONFIG_CRYPTO_USER_API_AEAD is not set -# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set -# CONFIG_CRYPTO_USER_API_HASH is not set -# CONFIG_CRYPTO_USER_API_RNG is not set -# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set -# CONFIG_CRYPTO_USER_API_SKCIPHER is not set -# CONFIG_CRYPTO_VMAC is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_XXHASH is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_ZSTD is not set -# CONFIG_CS5535_MFGPT is not set -# CONFIG_CS89x0 is not set -# CONFIG_CSD_LOCK_WAIT_DEBUG is not set -# CONFIG_CUSE is not set -# CONFIG_CW1200 is not set -# CONFIG_CXD2880_SPI_DRV is not set -# CONFIG_CXL_AFU_DRIVER_OPS is not set -# CONFIG_CXL_BASE is not set -# CONFIG_CXL_EEH is not set -# CONFIG_CXL_KERNEL_API is not set -# CONFIG_CXL_LIB is not set -# CONFIG_CYPRESS_FIRMWARE is not set -# CONFIG_DA280 is not set -# CONFIG_DA311 is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_DAX is not set -# CONFIG_DCB is not set -# CONFIG_DDR is not set -# CONFIG_DEBUG_ALIGN_RODATA is not set -# CONFIG_DEBUG_ATOMIC_SLEEP is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_EFI is not set -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ALLOW_ALL=y -# CONFIG_DEBUG_FS_ALLOW_NONE is not set -# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set -# CONFIG_DEBUG_GPIO is not set -# CONFIG_DEBUG_HIGHMEM is not set -# CONFIG_DEBUG_ICEDCC is not set -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_INFO_BTF is not set -# CONFIG_DEBUG_INFO_COMPRESSED is not set -# CONFIG_DEBUG_INFO_DWARF4 is not set -# CONFIG_DEBUG_INFO_SPLIT is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_KOBJECT_RELEASE is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_LL is not set -# CONFIG_DEBUG_LL_UART_8250 is not set -# CONFIG_DEBUG_LL_UART_PL01X is not set -# CONFIG_DEBUG_LOCKDEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_MISC is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_NX_TEST is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_DEBUG_PAGE_REF is not set -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -# CONFIG_DEBUG_PER_CPU_MAPS is not set -# CONFIG_DEBUG_PINCTRL is not set -# CONFIG_DEBUG_PI_LIST is not set -# CONFIG_DEBUG_PLIST is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RODATA_TEST is not set -# CONFIG_DEBUG_RSEQ is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_RWSEMS is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -# CONFIG_DEBUG_SEMIHOSTING is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_SHIRQ is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_STACKOVERFLOW is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set -# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set -# CONFIG_DEBUG_TIMEKEEPING is not set -# CONFIG_DEBUG_UART_8250_PALMCHIP is not set -# CONFIG_DEBUG_UART_8250_WORD is not set -# CONFIG_DEBUG_UART_BCM63XX is not set -# CONFIG_DEBUG_UART_FLOW_CONTROL is not set -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_VIRTUAL is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_VM_PGTABLE is not set -# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set -# CONFIG_DEBUG_WX is not set -# CONFIG_DEBUG_ZBOOT is not set -# CONFIG_DECNET is not set -# CONFIG_DEFAULT_CODEL is not set -CONFIG_DEFAULT_CUBIC=y -CONFIG_DEFAULT_DEADLINE=y -# CONFIG_DEFAULT_FQ is not set -CONFIG_DEFAULT_FQ_CODEL=y -# CONFIG_DEFAULT_FQ_PIE is not set -CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 -CONFIG_DEFAULT_INIT="" -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_DEFAULT_NET_SCH="fq_codel" -# CONFIG_DEFAULT_NOOP is not set -# CONFIG_DEFAULT_PFIFO_FAST is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_SECURITY="" -CONFIG_DEFAULT_SECURITY_DAC=y -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SFQ is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set -# CONFIG_DELL_LAPTOP is not set -# CONFIG_DELL_RBTN is not set -# CONFIG_DELL_SMBIOS is not set -# CONFIG_DELL_SMO8800 is not set -# CONFIG_DEPRECATED_PARAM_STRUCT is not set -# CONFIG_DETECT_HUNG_TASK is not set -# CONFIG_DEVKMEM is not set -# CONFIG_DEVMEM is not set -CONFIG_DEVPORT=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_DEVTMPFS is not set -# CONFIG_DEVTMPFS_MOUNT is not set -# CONFIG_DEV_DAX is not set -# CONFIG_DGAP is not set -# CONFIG_DGNC is not set -# CONFIG_DHT11 is not set -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_DISPLAY_CONNECTOR_ANALOG_TV is not set -# CONFIG_DISPLAY_CONNECTOR_DVI is not set -# CONFIG_DISPLAY_CONNECTOR_HDMI is not set -# CONFIG_DISPLAY_ENCODER_TFP410 is not set -# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set -# CONFIG_DISPLAY_PANEL_DPI is not set -# CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02 is not set -# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set -# CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1 is not set -# CONFIG_DL2K is not set -# CONFIG_DLHL60D is not set -# CONFIG_DLM is not set -# CONFIG_DM9000 is not set -# CONFIG_DMABUF_HEAPS is not set -# CONFIG_DMABUF_MOVE_NOTIFY is not set -# CONFIG_DMABUF_SELFTESTS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_DMADEVICES_DEBUG is not set -# CONFIG_DMARD06 is not set -# CONFIG_DMARD09 is not set -# CONFIG_DMARD10 is not set -# CONFIG_DMASCC is not set -# CONFIG_DMATEST is not set -# CONFIG_DMA_API_DEBUG is not set -CONFIG_DMA_COHERENT_POOL=y -CONFIG_DMA_DECLARE_COHERENT=y -# CONFIG_DMA_ENGINE is not set -# CONFIG_DMA_FENCE_TRACE is not set -# CONFIG_DMA_JZ4780 is not set -CONFIG_DMA_NONCOHERENT_MMAP=y -# CONFIG_DMA_NOOP_OPS is not set -# CONFIG_DMA_PERNUMA_CMA is not set -# CONFIG_DMA_SHARED_BUFFER is not set -# CONFIG_DMA_VIRT_OPS is not set -# CONFIG_DM_CACHE is not set -# CONFIG_DM_CLONE is not set -# CONFIG_DM_DEBUG is not set -# CONFIG_DM_DELAY is not set -# CONFIG_DM_DUST is not set -# CONFIG_DM_EBS is not set -# CONFIG_DM_ERA is not set -# CONFIG_DM_FLAKEY is not set -# CONFIG_DM_INTEGRITY is not set -# CONFIG_DM_LOG_USERSPACE is not set -# CONFIG_DM_LOG_WRITES is not set -# CONFIG_DM_MQ_DEFAULT is not set -# CONFIG_DM_MULTIPATH is not set -# CONFIG_DM_RAID is not set -# CONFIG_DM_SWITCH is not set -# CONFIG_DM_THIN_PROVISIONING is not set -# CONFIG_DM_UEVENT is not set -# CONFIG_DM_UNSTRIPED is not set -# CONFIG_DM_VERITY is not set -# CONFIG_DM_WRITECACHE is not set -# CONFIG_DM_ZERO is not set -# CONFIG_DNET is not set -# CONFIG_DNOTIFY is not set -# CONFIG_DNS_RESOLVER is not set -CONFIG_DOUBLEFAULT=y -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_DP83869_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DPOT_DAC is not set -# CONFIG_DPS310 is not set -CONFIG_DQL=y -# CONFIG_DRAGONRISE_FF is not set -# CONFIG_DRM is not set -# CONFIG_DRM_AMDGPU is not set -# CONFIG_DRM_AMDGPU_CIK is not set -# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set -# CONFIG_DRM_AMDGPU_SI is not set -# CONFIG_DRM_AMDGPU_USERPTR is not set -# CONFIG_DRM_AMD_ACP is not set -# CONFIG_DRM_AMD_DC_DCN2_0 is not set -# CONFIG_DRM_AMD_DC_DCN3_0 is not set -# CONFIG_DRM_AMD_DC_HDCP is not set -# CONFIG_DRM_AMD_DC_SI is not set -# CONFIG_DRM_ANALOGIX_ANX6345 is not set -# CONFIG_DRM_ANALOGIX_ANX78XX is not set -# CONFIG_DRM_ARCPGU is not set -# CONFIG_DRM_ARMADA is not set -# CONFIG_DRM_AST is not set -# CONFIG_DRM_BOCHS is not set -# CONFIG_DRM_CDNS_DSI is not set -# CONFIG_DRM_CDNS_MHDP8546 is not set -# CONFIG_DRM_CHRONTEL_CH7033 is not set -# CONFIG_DRM_CIRRUS_QEMU is not set -# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -# CONFIG_DRM_DEBUG_MM is not set -# CONFIG_DRM_DEBUG_SELFTEST is not set -# CONFIG_DRM_DISPLAY_CONNECTOR is not set -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DP_CEC is not set -# CONFIG_DRM_DUMB_VGA_DAC is not set -# CONFIG_DRM_DW_HDMI_CEC is not set -# CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_EXYNOS is not set -# CONFIG_DRM_FBDEV_EMULATION is not set -# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set -# CONFIG_DRM_FSL_DCU is not set -# CONFIG_DRM_GM12U320 is not set -# CONFIG_DRM_GMA500 is not set -# CONFIG_DRM_HDLCD is not set -# CONFIG_DRM_HISI_HIBMC is not set -# CONFIG_DRM_HISI_KIRIN is not set -# CONFIG_DRM_I2C_ADV7511 is not set -# CONFIG_DRM_I2C_CH7006 is not set -# CONFIG_DRM_I2C_NXP_TDA9950 is not set -# CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_I2C_SIL164 is not set -# CONFIG_DRM_I915 is not set -# CONFIG_DRM_KOMEDA is not set -# CONFIG_DRM_LEGACY is not set -# CONFIG_DRM_LIB_RANDOM is not set -# CONFIG_DRM_LIMA is not set -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set -# CONFIG_DRM_LONTIUM_LT9611 is not set -# CONFIG_DRM_LVDS_CODEC is not set -# CONFIG_DRM_LVDS_ENCODER is not set -# CONFIG_DRM_MALI_DISPLAY is not set -# CONFIG_DRM_MCDE is not set -# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set -# CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_MXSFB is not set -# CONFIG_DRM_NOUVEAU is not set -# CONFIG_DRM_NWL_MIPI_DSI is not set -# CONFIG_DRM_NXP_PTN3460 is not set -# CONFIG_DRM_OMAP is not set -# CONFIG_DRM_PANEL_ARM_VERSATILE is not set -# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set -# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set -# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set -# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set -# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set -# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set -# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set -# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set -# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set -# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set -# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set -# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set -# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set -# CONFIG_DRM_PANEL_LG_LB035Q02 is not set -# CONFIG_DRM_PANEL_LG_LG4573 is not set -# CONFIG_DRM_PANEL_LVDS is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set -# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set -# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set -# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set -# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set -# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set -# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set -# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set -# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set -# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set -# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set -# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set -# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set -# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set -# CONFIG_DRM_PANEL_SIMPLE is not set -# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set -# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set -# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set -# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set -# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set -# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set -# CONFIG_DRM_PANEL_TPO_TPG110 is not set -# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set -# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set -# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set -# CONFIG_DRM_PANFROST is not set -# CONFIG_DRM_PARADE_PS8622 is not set -# CONFIG_DRM_PARADE_PS8640 is not set -# CONFIG_DRM_PL111 is not set -# CONFIG_DRM_QXL is not set -# CONFIG_DRM_RADEON is not set -# CONFIG_DRM_RADEON_USERPTR is not set -# CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set -# CONFIG_DRM_SII902X is not set -# CONFIG_DRM_SII9234 is not set -# CONFIG_DRM_SIL_SII8620 is not set -# CONFIG_DRM_SIMPLE_BRIDGE is not set -# CONFIG_DRM_STI is not set -# CONFIG_DRM_STM is not set -# CONFIG_DRM_SUN4I is not set -# CONFIG_DRM_THINE_THC63LVD1024 is not set -# CONFIG_DRM_TIDSS is not set -# CONFIG_DRM_TILCDC is not set -# CONFIG_DRM_TINYDRM is not set -# CONFIG_DRM_TI_SN65DSI86 is not set -# CONFIG_DRM_TI_TFP410 is not set -# CONFIG_DRM_TI_TPD12S015 is not set -# CONFIG_DRM_TOSHIBA_TC358762 is not set -# CONFIG_DRM_TOSHIBA_TC358764 is not set -# CONFIG_DRM_TOSHIBA_TC358767 is not set -# CONFIG_DRM_TOSHIBA_TC358768 is not set -# CONFIG_DRM_TOSHIBA_TC358775 is not set -# CONFIG_DRM_TVE200 is not set -# CONFIG_DRM_UDL is not set -# CONFIG_DRM_VBOXVIDEO is not set -# CONFIG_DRM_VC4_HDMI_CEC is not set -# CONFIG_DRM_VGEM is not set -# CONFIG_DRM_VIRTIO_GPU is not set -# CONFIG_DRM_VKMS is not set -# CONFIG_DRM_VMWGFX is not set -# CONFIG_DRM_XEN is not set -# CONFIG_DS1682 is not set -# CONFIG_DS1803 is not set -# CONFIG_DS4424 is not set -# CONFIG_DST_CACHE is not set -# CONFIG_DTLK is not set -# CONFIG_DUMMY is not set -CONFIG_DUMMY_CONSOLE_COLUMNS=80 -CONFIG_DUMMY_CONSOLE_ROWS=25 -# CONFIG_DUMMY_IRQ is not set -# CONFIG_DVB_A8293 is not set -# CONFIG_DVB_AF9013 is not set -# CONFIG_DVB_AF9033 is not set -# CONFIG_DVB_AS102 is not set -# CONFIG_DVB_ASCOT2E is not set -# CONFIG_DVB_ATBM8830 is not set -# CONFIG_DVB_AU8522_DTV is not set -# CONFIG_DVB_AU8522_V4L is not set -# CONFIG_DVB_B2C2_FLEXCOP_USB is not set -# CONFIG_DVB_BCM3510 is not set -# CONFIG_DVB_CORE is not set -# CONFIG_DVB_CX22700 is not set -# CONFIG_DVB_CX22702 is not set -# CONFIG_DVB_CX24110 is not set -# CONFIG_DVB_CX24116 is not set -# CONFIG_DVB_CX24117 is not set -# CONFIG_DVB_CX24120 is not set -# CONFIG_DVB_CX24123 is not set -# CONFIG_DVB_CXD2099 is not set -# CONFIG_DVB_CXD2820R is not set -# CONFIG_DVB_CXD2841ER is not set -# CONFIG_DVB_CXD2880 is not set -# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set -# CONFIG_DVB_DIB3000MB is not set -# CONFIG_DVB_DIB3000MC is not set -# CONFIG_DVB_DIB7000M is not set -# CONFIG_DVB_DIB7000P is not set -# CONFIG_DVB_DIB8000 is not set -# CONFIG_DVB_DIB9000 is not set -# CONFIG_DVB_DRX39XYJ is not set -# CONFIG_DVB_DRXD is not set -# CONFIG_DVB_DRXK is not set -# CONFIG_DVB_DS3000 is not set -# CONFIG_DVB_DUMMY_FE is not set -# CONFIG_DVB_DYNAMIC_MINORS is not set -# CONFIG_DVB_EC100 is not set -# CONFIG_DVB_FIREDTV is not set -# CONFIG_DVB_HELENE is not set -# CONFIG_DVB_HORUS3A is not set -# CONFIG_DVB_ISL6405 is not set -# CONFIG_DVB_ISL6421 is not set -# CONFIG_DVB_ISL6423 is not set -# CONFIG_DVB_IX2505V is not set -# CONFIG_DVB_L64781 is not set -# CONFIG_DVB_LG2160 is not set -# CONFIG_DVB_LGDT3305 is not set -# CONFIG_DVB_LGDT3306A is not set -# CONFIG_DVB_LGDT330X is not set -# CONFIG_DVB_LGS8GL5 is not set -# CONFIG_DVB_LGS8GXX is not set -# CONFIG_DVB_LNBH25 is not set -# CONFIG_DVB_LNBH29 is not set -# CONFIG_DVB_LNBP21 is not set -# CONFIG_DVB_LNBP22 is not set -# CONFIG_DVB_M88DS3103 is not set -# CONFIG_DVB_M88RS2000 is not set -CONFIG_DVB_MAX_ADAPTERS=16 -# CONFIG_DVB_MB86A16 is not set -# CONFIG_DVB_MB86A20S is not set -# CONFIG_DVB_MMAP is not set -# CONFIG_DVB_MN88443X is not set -# CONFIG_DVB_MN88472 is not set -# CONFIG_DVB_MN88473 is not set -# CONFIG_DVB_MT312 is not set -# CONFIG_DVB_MT352 is not set -# CONFIG_DVB_MXL5XX is not set -# CONFIG_DVB_NET is not set -# CONFIG_DVB_NXT200X is not set -# CONFIG_DVB_NXT6000 is not set -# CONFIG_DVB_OR51132 is not set -# CONFIG_DVB_OR51211 is not set -# CONFIG_DVB_PLATFORM_DRIVERS is not set -# CONFIG_DVB_PLL is not set -# CONFIG_DVB_RTL2830 is not set -# CONFIG_DVB_RTL2832 is not set -# CONFIG_DVB_RTL2832_SDR is not set -# CONFIG_DVB_S5H1409 is not set -# CONFIG_DVB_S5H1411 is not set -# CONFIG_DVB_S5H1420 is not set -# CONFIG_DVB_S5H1432 is not set -# CONFIG_DVB_S921 is not set -# CONFIG_DVB_SI2165 is not set -# CONFIG_DVB_SI2168 is not set -# CONFIG_DVB_SI21XX is not set -# CONFIG_DVB_SP2 is not set -# CONFIG_DVB_SP8870 is not set -# CONFIG_DVB_SP887X is not set -# CONFIG_DVB_STB0899 is not set -# CONFIG_DVB_STB6000 is not set -# CONFIG_DVB_STB6100 is not set -# CONFIG_DVB_STV0288 is not set -# CONFIG_DVB_STV0297 is not set -# CONFIG_DVB_STV0299 is not set -# CONFIG_DVB_STV0367 is not set -# CONFIG_DVB_STV0900 is not set -# CONFIG_DVB_STV090x is not set -# CONFIG_DVB_STV0910 is not set -# CONFIG_DVB_STV6110 is not set -# CONFIG_DVB_STV6110x is not set -# CONFIG_DVB_STV6111 is not set -# CONFIG_DVB_TC90522 is not set -# CONFIG_DVB_TDA10021 is not set -# CONFIG_DVB_TDA10023 is not set -# CONFIG_DVB_TDA10048 is not set -# CONFIG_DVB_TDA1004X is not set -# CONFIG_DVB_TDA10071 is not set -# CONFIG_DVB_TDA10086 is not set -# CONFIG_DVB_TDA18271C2DD is not set -# CONFIG_DVB_TDA665x is not set -# CONFIG_DVB_TDA8083 is not set -# CONFIG_DVB_TDA8261 is not set -# CONFIG_DVB_TDA826X is not set -# CONFIG_DVB_TEST_DRIVERS is not set -# CONFIG_DVB_TS2020 is not set -# CONFIG_DVB_TTUSB_BUDGET is not set -# CONFIG_DVB_TTUSB_DEC is not set -# CONFIG_DVB_TUA6100 is not set -# CONFIG_DVB_TUNER_CX24113 is not set -# CONFIG_DVB_TUNER_DIB0070 is not set -# CONFIG_DVB_TUNER_DIB0090 is not set -# CONFIG_DVB_TUNER_ITD1000 is not set -# CONFIG_DVB_ULE_DEBUG is not set -# CONFIG_DVB_USB is not set -# CONFIG_DVB_USB_V2 is not set -# CONFIG_DVB_VES1820 is not set -# CONFIG_DVB_VES1X93 is not set -# CONFIG_DVB_ZD1301_DEMOD is not set -# CONFIG_DVB_ZL10036 is not set -# CONFIG_DVB_ZL10039 is not set -# CONFIG_DVB_ZL10353 is not set -# CONFIG_DWC_XLGMAC is not set -# CONFIG_DWMAC_DWC_QOS_ETH is not set -# CONFIG_DWMAC_INTEL_PLAT is not set -# CONFIG_DWMAC_IPQ806X is not set -# CONFIG_DWMAC_LPC18XX is not set -# CONFIG_DWMAC_MESON is not set -# CONFIG_DWMAC_ROCKCHIP is not set -# CONFIG_DWMAC_SOCFPGA is not set -# CONFIG_DWMAC_STI is not set -# CONFIG_DW_AXI_DMAC is not set -# CONFIG_DW_DMAC is not set -# CONFIG_DW_DMAC_PCI is not set -# CONFIG_DW_EDMA is not set -# CONFIG_DW_EDMA_PCIE is not set -# CONFIG_DW_WATCHDOG is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_DYNAMIC_DEBUG_CORE is not set -# CONFIG_E100 is not set -# CONFIG_E1000 is not set -# CONFIG_E1000E is not set -# CONFIG_E1000E_HWTS is not set -# CONFIG_EARLY_PRINTK_8250 is not set -# CONFIG_EARLY_PRINTK_USB_XDBC is not set -# CONFIG_EBC_C384_WDT is not set -# CONFIG_ECHO is not set -# CONFIG_ECRYPT_FS is not set -# CONFIG_EDAC is not set -# CONFIG_EEEPC_LAPTOP is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_EEPROM_93XX46 is not set -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_DIGSY_MTC_CFG is not set -# CONFIG_EEPROM_EE1004 is not set -# CONFIG_EEPROM_IDT_89HPESX is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EFI is not set -CONFIG_EFI_PARTITION=y -# CONFIG_EFI_VARS_PSTORE is not set -# CONFIG_EFS_FS is not set -CONFIG_ELFCORE=y -# CONFIG_ELF_CORE is not set -# CONFIG_EMAC_ROCKCHIP is not set -CONFIG_EMBEDDED=y -# CONFIG_EM_TIMER_STI is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -# CONFIG_ENA_ETHERNET is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_ENCRYPTED_KEYS is not set -# CONFIG_ENCX24J600 is not set -# CONFIG_ENERGY_MODEL is not set -# CONFIG_ENIC is not set -# CONFIG_ENVELOPE_DETECTOR is not set -# CONFIG_EPAPR_PARAVIRT is not set -# CONFIG_EPIC100 is not set -CONFIG_EPOLL=y -# CONFIG_EQUALIZER is not set -# CONFIG_EROFS_FS is not set -# CONFIG_ET131X is not set -CONFIG_ETHERNET=y -# CONFIG_ETHOC is not set -CONFIG_ETHTOOL_NETLINK=y -CONFIG_EVENTFD=y -# CONFIG_EVM is not set -# CONFIG_EXFAT_FS is not set -CONFIG_EXPERT=y -CONFIG_EXPORTFS=y -# CONFIG_EXPORTFS_BLOCK_OPS is not set -# CONFIG_EXT2_FS is not set -CONFIG_EXT2_FS_XATTR=y -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4_DEBUG is not set -# CONFIG_EXT4_ENCRYPTION is not set -# CONFIG_EXT4_FS is not set -# CONFIG_EXT4_FS_POSIX_ACL is not set -# CONFIG_EXT4_FS_SECURITY is not set -CONFIG_EXT4_USE_FOR_EXT2=y -# CONFIG_EXTCON is not set -# CONFIG_EXTCON_ADC_JACK is not set -# CONFIG_EXTCON_ARIZONA is not set -# CONFIG_EXTCON_AXP288 is not set -# CONFIG_EXTCON_FSA9480 is not set -# CONFIG_EXTCON_GPIO is not set -# CONFIG_EXTCON_INTEL_INT3496 is not set -# CONFIG_EXTCON_MAX3355 is not set -# CONFIG_EXTCON_PTN5150 is not set -# CONFIG_EXTCON_QCOM_SPMI_MISC is not set -# CONFIG_EXTCON_RT8973A is not set -# CONFIG_EXTCON_SM5502 is not set -# CONFIG_EXTCON_USB_GPIO is not set -CONFIG_EXTRA_FIRMWARE="" -CONFIG_EXTRA_TARGETS="" -# CONFIG_EXYNOS_ADC is not set -# CONFIG_EXYNOS_VIDEO is not set -# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_F2FS_CHECK_FS is not set -# CONFIG_F2FS_FAULT_INJECTION is not set -# CONFIG_F2FS_FS is not set -# CONFIG_F2FS_FS_COMPRESSION is not set -# CONFIG_F2FS_FS_ENCRYPTION is not set -# CONFIG_F2FS_FS_POSIX_ACL is not set -# CONFIG_F2FS_FS_SECURITY is not set -CONFIG_F2FS_FS_XATTR=y -# CONFIG_F2FS_IO_TRACE is not set -CONFIG_F2FS_STAT_FS=y -# CONFIG_FAILOVER is not set -# CONFIG_FAIR_GROUP_SCHED is not set -# CONFIG_FANOTIFY is not set -# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_FAT_DEFAULT_UTF8 is not set -# CONFIG_FAT_FS is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_FB is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_ARC is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_ARMCLCD is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_AUO_K190X is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_BIG_ENDIAN is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -# CONFIG_FB_BOTH_ENDIAN is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_CARMINE is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_DA8XX is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_FLEX is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_FSL_DIU is not set -# CONFIG_FB_GEODE is not set -# CONFIG_FB_GOLDFISH is not set -# CONFIG_FB_HGA is not set -# CONFIG_FB_I740 is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_IMX is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_LE80578 is not set -# CONFIG_FB_LITTLE_ENDIAN is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_MXS is not set -# CONFIG_FB_N411 is not set -# CONFIG_FB_NEOMAGIC is not set -CONFIG_FB_NOTIFY=y -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_OF is not set -# CONFIG_FB_OMAP2 is not set -# CONFIG_FB_OPENCORES is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_PS3 is not set -# CONFIG_FB_PXA is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIMPLE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_SM712 is not set -# CONFIG_FB_SM750 is not set -# CONFIG_FB_SMSCUFX is not set -# CONFIG_FB_SSD1307 is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_TFT is not set -# CONFIG_FB_TFT_AGM1264K_FL is not set -# CONFIG_FB_TFT_BD663474 is not set -# CONFIG_FB_TFT_FBTFT_DEVICE is not set -# CONFIG_FB_TFT_HX8340BN is not set -# CONFIG_FB_TFT_HX8347D is not set -# CONFIG_FB_TFT_HX8353D is not set -# CONFIG_FB_TFT_HX8357D is not set -# CONFIG_FB_TFT_ILI9163 is not set -# CONFIG_FB_TFT_ILI9320 is not set -# CONFIG_FB_TFT_ILI9325 is not set -# CONFIG_FB_TFT_ILI9340 is not set -# CONFIG_FB_TFT_ILI9341 is not set -# CONFIG_FB_TFT_ILI9481 is not set -# CONFIG_FB_TFT_ILI9486 is not set -# CONFIG_FB_TFT_PCD8544 is not set -# CONFIG_FB_TFT_RA8875 is not set -# CONFIG_FB_TFT_S6D02A1 is not set -# CONFIG_FB_TFT_S6D1121 is not set -# CONFIG_FB_TFT_SEPS525 is not set -# CONFIG_FB_TFT_SH1106 is not set -# CONFIG_FB_TFT_SSD1289 is not set -# CONFIG_FB_TFT_SSD1305 is not set -# CONFIG_FB_TFT_SSD1306 is not set -# CONFIG_FB_TFT_SSD1325 is not set -# CONFIG_FB_TFT_SSD1331 is not set -# CONFIG_FB_TFT_SSD1351 is not set -# CONFIG_FB_TFT_ST7735R is not set -# CONFIG_FB_TFT_ST7789V is not set -# CONFIG_FB_TFT_TINYLCD is not set -# CONFIG_FB_TFT_TLS8204 is not set -# CONFIG_FB_TFT_UC1611 is not set -# CONFIG_FB_TFT_UC1701 is not set -# CONFIG_FB_TFT_UPD161704 is not set -# CONFIG_FB_TFT_WATTEROTT is not set -# CONFIG_FB_TILEBLITTING is not set -# CONFIG_FB_TMIO is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_UDL is not set -# CONFIG_FB_UVESA is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_VIA is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_XGI is not set -# CONFIG_FCOE is not set -# CONFIG_FCOE_FNIC is not set -# CONFIG_FDDI is not set -# CONFIG_FEALNX is not set -# CONFIG_FENCE_TRACE is not set -# CONFIG_FHANDLE is not set -CONFIG_FIB_RULES=y -# CONFIG_FIELDBUS_DEV is not set -CONFIG_FILE_LOCKING=y -# CONFIG_FIND_BIT_BENCHMARK is not set -# CONFIG_FIREWIRE is not set -# CONFIG_FIREWIRE_NOSY is not set -# CONFIG_FIREWIRE_SERIAL is not set -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FIRMWARE_IN_KERNEL is not set -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_FIT_PARTITION is not set -# CONFIG_FIXED_PHY is not set -CONFIG_FLATMEM=y -CONFIG_FLATMEM_MANUAL=y -CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_FM10K is not set -# CONFIG_FMC is not set -# CONFIG_FONTS is not set -# CONFIG_FONT_6x8 is not set -# CONFIG_FONT_TER16x32 is not set -# CONFIG_FORCEDETH is not set -CONFIG_FORCE_MAX_ZONEORDER=11 -CONFIG_FORTIFY_SOURCE=y -# CONFIG_FPGA is not set -# CONFIG_FRAMEBUFFER_CONSOLE is not set -# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set -# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set -# CONFIG_FRAME_POINTER is not set -CONFIG_FRAME_WARN=1024 -# CONFIG_FREEZER is not set -# CONFIG_FRONTSWAP is not set -# CONFIG_FSCACHE is not set -# CONFIG_FSI is not set -# CONFIG_FSL_EDMA is not set -# CONFIG_FSL_ENETC is not set -# CONFIG_FSL_ENETC_MDIO is not set -# CONFIG_FSL_ENETC_VF is not set -# CONFIG_FSL_ERRATUM_A008585 is not set -# CONFIG_FSL_MC_BUS is not set -# CONFIG_FSL_PQ_MDIO is not set -# CONFIG_FSL_QDMA is not set -# CONFIG_FSL_RCPM is not set -# CONFIG_FSL_XGMAC_MDIO is not set -CONFIG_FSNOTIFY=y -# CONFIG_FS_DAX is not set -# CONFIG_FS_ENCRYPTION is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_FS_VERITY is not set -# CONFIG_FTGMAC100 is not set -# CONFIG_FTL is not set -# CONFIG_FTMAC100 is not set -# CONFIG_FTRACE is not set -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_FTR_FIXUP_SELFTEST is not set -# CONFIG_FTWDT010_WATCHDOG is not set -# CONFIG_FUJITSU_ERRATUM_010001 is not set -# CONFIG_FUJITSU_ES is not set -# CONFIG_FUJITSU_LAPTOP is not set -# CONFIG_FUJITSU_TABLET is not set -# CONFIG_FUNCTION_ERROR_INJECTION is not set -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_FUSE_FS is not set -# CONFIG_FUSION is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set -# CONFIG_FUSION_SPI is not set -CONFIG_FUTEX=y -CONFIG_FUTEX_PI=y -# CONFIG_FW_CFG_SYSFS is not set -CONFIG_FW_LOADER=y -# CONFIG_FW_LOADER_COMPRESS is not set -CONFIG_FW_LOADER_USER_HELPER=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -# CONFIG_FXAS21002C is not set -# CONFIG_FXOS8700_I2C is not set -# CONFIG_FXOS8700_SPI is not set -CONFIG_GACT_PROB=y -# CONFIG_GADGET_UAC1 is not set -# CONFIG_GAMEPORT is not set -# CONFIG_GATEWORKS_GW16083 is not set -# CONFIG_GCC_PLUGINS is not set -# CONFIG_GCOV is not set -# CONFIG_GCOV_KERNEL is not set -# CONFIG_GDB_SCRIPTS is not set -# CONFIG_GEMINI_ETHERNET is not set -# CONFIG_GENERIC_ADC_BATTERY is not set -# CONFIG_GENERIC_ADC_THERMAL is not set -CONFIG_GENERIC_CALIBRATE_DELAY=y -# CONFIG_GENERIC_CPU_DEVICES is not set -CONFIG_GENERIC_HWEIGHT=y -# CONFIG_GENERIC_IRQ_DEBUGFS is not set -CONFIG_GENERIC_IRQ_IPI=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_NET_UTILS=y -# CONFIG_GENERIC_PHY is not set -CONFIG_GENERIC_PTDUMP=y -CONFIG_GENERIC_VDSO_TIME_NS=y -# CONFIG_GENEVE is not set -# CONFIG_GENWQE is not set -# CONFIG_GFS2_FS is not set -# CONFIG_GIGASET_CAPI is not set -# CONFIG_GIGASET_DEBUG is not set -# CONFIG_GIGASET_DUMMYLL is not set -# CONFIG_GLOB_SELFTEST is not set -# CONFIG_GNSS is not set -# CONFIG_GOLDFISH is not set -# CONFIG_GOOGLE_COREBOOT_TABLE is not set -# CONFIG_GOOGLE_FIRMWARE is not set -# CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT is not set -# CONFIG_GOOGLE_MEMCONSOLE_COREBOOT is not set -# CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY is not set -# CONFIG_GOOGLE_SMI is not set -# CONFIG_GOOGLE_VPD is not set -# CONFIG_GP2AP002 is not set -# CONFIG_GP2AP020A00F is not set -# CONFIG_GPD_POCKET_FAN is not set -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_FASTPATH_LIMIT=512 -# CONFIG_GPIO_104_DIO_48E is not set -# CONFIG_GPIO_104_IDIO_16 is not set -# CONFIG_GPIO_104_IDI_48 is not set -# CONFIG_GPIO_74X164 is not set -# CONFIG_GPIO_74XX_MMIO is not set -# CONFIG_GPIO_ADNP is not set -# CONFIG_GPIO_ADP5588 is not set -# CONFIG_GPIO_AGGREGATOR is not set -# CONFIG_GPIO_ALTERA is not set -# CONFIG_GPIO_AMD8111 is not set -# CONFIG_GPIO_AMDPT is not set -# CONFIG_GPIO_AMD_FCH is not set -# CONFIG_GPIO_BCM_KONA is not set -# CONFIG_GPIO_BT8XX is not set -# CONFIG_GPIO_CADENCE is not set -# CONFIG_GPIO_CASCADE is not set -# CONFIG_GPIO_CDEV is not set -# CONFIG_GPIO_CDEV_V1 is not set -# CONFIG_GPIO_CS5535 is not set -# CONFIG_GPIO_DWAPB is not set -# CONFIG_GPIO_EM is not set -# CONFIG_GPIO_EXAR is not set -# CONFIG_GPIO_F7188X is not set -# CONFIG_GPIO_FTGPIO010 is not set -# CONFIG_GPIO_GENERIC_PLATFORM is not set -# CONFIG_GPIO_GPIO_MM is not set -# CONFIG_GPIO_GRGPIO is not set -# CONFIG_GPIO_GW_PLD is not set -# CONFIG_GPIO_HLWD is not set -# CONFIG_GPIO_ICH is not set -# CONFIG_GPIO_IT87 is not set -# CONFIG_GPIO_LOGICVC is not set -# CONFIG_GPIO_LYNXPOINT is not set -# CONFIG_GPIO_MAX3191X is not set -# CONFIG_GPIO_MAX7300 is not set -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_MB86S7X is not set -# CONFIG_GPIO_MC33880 is not set -# CONFIG_GPIO_ML_IOH is not set -# CONFIG_GPIO_MOCKUP is not set -# CONFIG_GPIO_MPC8XXX is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCA953X_IRQ is not set -# CONFIG_GPIO_PCA9570 is not set -# CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_PCH is not set -# CONFIG_GPIO_PCIE_IDIO_24 is not set -# CONFIG_GPIO_PCI_IDIO_16 is not set -# CONFIG_GPIO_PISOSR is not set -# CONFIG_GPIO_PL061 is not set -# CONFIG_GPIO_RCAR is not set -# CONFIG_GPIO_RDC321X is not set -# CONFIG_GPIO_SAMA5D2_PIOBU is not set -# CONFIG_GPIO_SCH is not set -# CONFIG_GPIO_SCH311X is not set -# CONFIG_GPIO_SIFIVE is not set -# CONFIG_GPIO_SX150X is not set -# CONFIG_GPIO_SYSCON is not set -CONFIG_GPIO_SYSFS=y -# CONFIG_GPIO_TPIC2810 is not set -# CONFIG_GPIO_TS4900 is not set -# CONFIG_GPIO_TS5500 is not set -# CONFIG_GPIO_VX855 is not set -# CONFIG_GPIO_WATCHDOG is not set -# CONFIG_GPIO_WINBOND is not set -# CONFIG_GPIO_WS16C48 is not set -# CONFIG_GPIO_XGENE is not set -# CONFIG_GPIO_XILINX is not set -# CONFIG_GPIO_XRA1403 is not set -# CONFIG_GPIO_ZEVIO is not set -# CONFIG_GPIO_ZX is not set -# CONFIG_GREENASIA_FF is not set -# CONFIG_GREYBUS is not set -# CONFIG_GS_FPGABOOT is not set -# CONFIG_GTP is not set -# CONFIG_GUP_BENCHMARK is not set -# CONFIG_GVE is not set -# CONFIG_HABANA_AI is not set -# CONFIG_HAMACHI is not set -# CONFIG_HAMRADIO is not set -# CONFIG_HAPPYMEAL is not set -CONFIG_HARDENED_USERCOPY=y -# CONFIG_HARDENED_USERCOPY_FALLBACK is not set -# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set -CONFIG_HARDEN_BRANCH_HISTORY=y -CONFIG_HARDEN_EL2_VECTORS=y -# CONFIG_HARDLOCKUP_DETECTOR is not set -# CONFIG_HAVE_ARM_ARCH_TIMER is not set -# CONFIG_HCALL_STATS is not set -# CONFIG_HDC100X is not set -# CONFIG_HDC2010 is not set -# CONFIG_HDLC is not set -# CONFIG_HDLC_CISCO is not set -# CONFIG_HDLC_FR is not set -# CONFIG_HDLC_PPP is not set -# CONFIG_HDLC_RAW is not set -# CONFIG_HDLC_RAW_ETH is not set -# CONFIG_HDMI_LPE_AUDIO is not set -# CONFIG_HDQ_MASTER_OMAP is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_HEADERS_INSTALL is not set -# CONFIG_HEADER_TEST is not set -# CONFIG_HERMES is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_HFSPLUS_FS_POSIX_ACL is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFS_FS_POSIX_ACL is not set -# CONFIG_HI8435 is not set -# CONFIG_HIBERNATION is not set -# CONFIG_HID is not set -# CONFIG_HIDRAW is not set -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_ACCUTOUCH is not set -# CONFIG_HID_ACRUX is not set -# CONFIG_HID_ACRUX_FF is not set -# CONFIG_HID_ALPS is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_APPLEIR is not set -# CONFIG_HID_ASUS is not set -# CONFIG_HID_AUREAL is not set -# CONFIG_HID_BATTERY_STRENGTH is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_BETOP_FF is not set -# CONFIG_HID_BIGBEN_FF is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CMEDIA is not set -# CONFIG_HID_CORSAIR is not set -# CONFIG_HID_COUGAR is not set -# CONFIG_HID_CP2112 is not set -# CONFIG_HID_CREATIVE_SB0540 is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_ELAN is not set -# CONFIG_HID_ELECOM is not set -# CONFIG_HID_ELO is not set -# CONFIG_HID_EMS_FF is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_GEMBIRD is not set -# CONFIG_HID_GENERIC is not set -# CONFIG_HID_GFRM is not set -# CONFIG_HID_GLORIOUS is not set -# CONFIG_HID_GOOGLE_HAMMER is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_GT683R is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_HOLTEK is not set -# CONFIG_HID_ICADE is not set -# CONFIG_HID_ITE is not set -# CONFIG_HID_JABRA is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_KEYTOUCH is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_LCPOWER is not set -# CONFIG_HID_LED is not set -# CONFIG_HID_LENOVO is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_LOGITECH_DJ is not set -# CONFIG_HID_LOGITECH_HIDPP is not set -# CONFIG_HID_MACALLY is not set -# CONFIG_HID_MAGICMOUSE is not set -# CONFIG_HID_MALTRON is not set -# CONFIG_HID_MAYFLASH is not set -# CONFIG_HID_MCP2221 is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_MULTITOUCH is not set -# CONFIG_HID_NTI is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_ORTEK is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PENMOUNT is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_PICOLCD is not set -# CONFIG_HID_PID is not set -# CONFIG_HID_PLANTRONICS is not set -# CONFIG_HID_PRIMAX is not set -# CONFIG_HID_PRODIKEYS is not set -# CONFIG_HID_REDRAGON is not set -# CONFIG_HID_RETRODE is not set -# CONFIG_HID_RMI is not set -# CONFIG_HID_ROCCAT is not set -# CONFIG_HID_SAITEK is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SENSOR_HUB is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SPEEDLINK is not set -# CONFIG_HID_STEAM is not set -# CONFIG_HID_STEELSERIES is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_THINGM is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_TIVO is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_U2FZERO is not set -# CONFIG_HID_UCLOGIC is not set -# CONFIG_HID_UDRAW_PS3 is not set -# CONFIG_HID_VIEWSONIC is not set -# CONFIG_HID_VIVALDI is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_WALTOP is not set -# CONFIG_HID_WIIMOTE is not set -# CONFIG_HID_XINMO is not set -# CONFIG_HID_ZEROPLUS is not set -# CONFIG_HID_ZYDACRON is not set -# CONFIG_HIGHMEM is not set -CONFIG_HIGH_RES_TIMERS=y -# CONFIG_HINIC is not set -# CONFIG_HIP04_ETH is not set -# CONFIG_HIPPI is not set -# CONFIG_HISILICON_ERRATUM_161010101 is not set -# CONFIG_HISILICON_ERRATUM_161600802 is not set -# CONFIG_HISI_DMA is not set -# CONFIG_HISI_FEMAC is not set -# CONFIG_HISI_HIKEY_USB is not set -# CONFIG_HIX5HD2_GMAC is not set -# CONFIG_HMC425 is not set -# CONFIG_HMC6352 is not set -# CONFIG_HNS is not set -# CONFIG_HNS3 is not set -# CONFIG_HNS_DSAF is not set -# CONFIG_HNS_ENET is not set -# CONFIG_HOSTAP is not set -# CONFIG_HOSTAP_CS is not set -# CONFIG_HOSTAP_PCI is not set -# CONFIG_HOSTAP_PLX is not set -# CONFIG_HOTPLUG_CPU is not set -# CONFIG_HOTPLUG_PCI is not set -# CONFIG_HP03 is not set -# CONFIG_HP100 is not set -# CONFIG_HP206C is not set -CONFIG_HPET_MMAP_DEFAULT=y -# CONFIG_HPFS_FS is not set -# CONFIG_HP_ILO is not set -# CONFIG_HP_WIRELESS is not set -# CONFIG_HSA_AMD is not set -# CONFIG_HSI is not set -# CONFIG_HSR is not set -# CONFIG_HTC_EGPIO is not set -# CONFIG_HTC_I2CPLD is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_HTS221 is not set -# CONFIG_HTU21 is not set -# CONFIG_HUGETLBFS is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_HVC_DCC is not set -# CONFIG_HVC_UDBG is not set -# CONFIG_HWLAT_TRACER is not set -# CONFIG_HWMON is not set -# CONFIG_HWMON_DEBUG_CHIP is not set -# CONFIG_HWMON_VID is not set -# CONFIG_HWSPINLOCK is not set -# CONFIG_HWSPINLOCK_OMAP is not set -CONFIG_HW_PERF_EVENTS=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HW_RANDOM_AMD is not set -# CONFIG_HW_RANDOM_ATMEL is not set -# CONFIG_HW_RANDOM_BA431 is not set -# CONFIG_HW_RANDOM_CAVIUM is not set -# CONFIG_HW_RANDOM_CCTRNG is not set -# CONFIG_HW_RANDOM_EXYNOS is not set -# CONFIG_HW_RANDOM_GEODE is not set -# CONFIG_HW_RANDOM_INTEL is not set -# CONFIG_HW_RANDOM_IPROC_RNG200 is not set -# CONFIG_HW_RANDOM_MTK is not set -# CONFIG_HW_RANDOM_OMAP is not set -# CONFIG_HW_RANDOM_OMAP3_ROM is not set -# CONFIG_HW_RANDOM_PPC4XX is not set -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -CONFIG_HW_RANDOM_TPM=y -# CONFIG_HW_RANDOM_VIA is not set -# CONFIG_HW_RANDOM_VIRTIO is not set -# CONFIG_HW_RANDOM_XIPHERA is not set -# CONFIG_HX711 is not set -# CONFIG_HYPERV is not set -# CONFIG_HYPERV_TSCPAGE is not set -# CONFIG_HYSDN is not set -CONFIG_HZ=100 -CONFIG_HZ_100=y -# CONFIG_HZ_1000 is not set -# CONFIG_HZ_1024 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_200 is not set -# CONFIG_HZ_24 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -# CONFIG_HZ_300 is not set -# CONFIG_HZ_48 is not set -# CONFIG_HZ_500 is not set -# CONFIG_HZ_PERIODIC is not set -# CONFIG_I2C is not set -# CONFIG_I2C_ALGOBIT is not set -# CONFIG_I2C_ALGOPCA is not set -# CONFIG_I2C_ALGOPCF is not set -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set -# CONFIG_I2C_AU1550 is not set -# CONFIG_I2C_BCM2835 is not set -# CONFIG_I2C_BCM_IPROC is not set -# CONFIG_I2C_BRCMSTB is not set -# CONFIG_I2C_CADENCE is not set -# CONFIG_I2C_CBUS_GPIO is not set -# CONFIG_I2C_CHARDEV is not set -# CONFIG_I2C_COMPAT is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEMUX_PINCTRL is not set -# CONFIG_I2C_DESIGNWARE_PCI is not set -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -# CONFIG_I2C_DESIGNWARE_SLAVE is not set -# CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_EG20T is not set -# CONFIG_I2C_ELEKTOR is not set -# CONFIG_I2C_EMEV2 is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set -# CONFIG_I2C_HELPER_AUTO is not set -# CONFIG_I2C_HID is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_IBM_IIC is not set -# CONFIG_I2C_IMG is not set -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_ISMT is not set -# CONFIG_I2C_JZ4780 is not set -# CONFIG_I2C_MLXCPLD is not set -# CONFIG_I2C_MPC is not set -# CONFIG_I2C_MT65XX is not set -# CONFIG_I2C_MUX is not set -# CONFIG_I2C_MUX_GPIO is not set -# CONFIG_I2C_MUX_GPMUX is not set -# CONFIG_I2C_MUX_LTC4306 is not set -# CONFIG_I2C_MUX_MLXCPLD is not set -# CONFIG_I2C_MUX_PCA9541 is not set -# CONFIG_I2C_MUX_PCA954x is not set -# CONFIG_I2C_MUX_PINCTRL is not set -# CONFIG_I2C_MUX_REG is not set -# CONFIG_I2C_MV64XXX is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_NOMADIK is not set -# CONFIG_I2C_NVIDIA_GPU is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_OCTEON is not set -# CONFIG_I2C_PARPORT is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_PXA_PCI is not set -# CONFIG_I2C_PXA_SLAVE is not set -# CONFIG_I2C_RCAR is not set -# CONFIG_I2C_RK3X is not set -# CONFIG_I2C_ROBOTFUZZ_OSIF is not set -# CONFIG_I2C_S3C2410 is not set -# CONFIG_I2C_SCMI is not set -# CONFIG_I2C_SH_MOBILE is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_SLAVE is not set -# CONFIG_I2C_SLAVE_EEPROM is not set -# CONFIG_I2C_SMBUS is not set -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_THUNDERX is not set -# CONFIG_I2C_TINY_USB is not set -# CONFIG_I2C_VERSATILE is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set -# CONFIG_I2C_XILINX is not set -# CONFIG_I3C is not set -# CONFIG_I40E is not set -# CONFIG_I40EVF is not set -# CONFIG_I6300ESB_WDT is not set -# CONFIG_I82092 is not set -# CONFIG_I82365 is not set -# CONFIG_IAQCORE is not set -# CONFIG_IBM_ASM is not set -# CONFIG_IBM_EMAC_DEBUG is not set -# CONFIG_IBM_EMAC_EMAC4 is not set -# CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_EMAC_MAL_COMMON_ERR is not set -# CONFIG_IBM_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_EMAC_RGMII is not set -# CONFIG_IBM_EMAC_TAH is not set -# CONFIG_IBM_EMAC_ZMII is not set -# CONFIG_ICE is not set -# CONFIG_ICP10100 is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_ICS932S401 is not set -# CONFIG_IDE is not set -# CONFIG_IDEAPAD_LAPTOP is not set -# CONFIG_IDE_GD is not set -# CONFIG_IDE_PROC_FS is not set -# CONFIG_IDE_TASK_IOCTL is not set -# CONFIG_IDLE_PAGE_TRACKING is not set -# CONFIG_IEEE802154 is not set -# CONFIG_IEEE802154_ADF7242 is not set -# CONFIG_IEEE802154_ATUSB is not set -# CONFIG_IEEE802154_CA8210 is not set -# CONFIG_IEEE802154_HWSIM is not set -# CONFIG_IEEE802154_MCR20A is not set -# CONFIG_IFB is not set -# CONFIG_IGB is not set -# CONFIG_IGBVF is not set -# CONFIG_IGC is not set -# CONFIG_IIO is not set -# CONFIG_IIO_BUFFER is not set -# CONFIG_IIO_BUFFER_CB is not set -# CONFIG_IIO_BUFFER_DMA is not set -# CONFIG_IIO_BUFFER_DMAENGINE is not set -# CONFIG_IIO_BUFFER_HDC2010 is not set -# CONFIG_IIO_BUFFER_HW_CONSUMER is not set -# CONFIG_IIO_CONFIGFS is not set -CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 -# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set -# CONFIG_IIO_INTERRUPT_TRIGGER is not set -# CONFIG_IIO_MUX is not set -# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set -# CONFIG_IIO_RESCALE is not set -# CONFIG_IIO_SIMPLE_DUMMY is not set -# CONFIG_IIO_SSP_SENSORHUB is not set -# CONFIG_IIO_ST_ACCEL_3AXIS is not set -# CONFIG_IIO_ST_GYRO_3AXIS is not set -# CONFIG_IIO_ST_LSM6DSX is not set -# CONFIG_IIO_ST_MAGN_3AXIS is not set -# CONFIG_IIO_ST_PRESS is not set -# CONFIG_IIO_SW_DEVICE is not set -# CONFIG_IIO_SW_TRIGGER is not set -# CONFIG_IIO_SYSFS_TRIGGER is not set -# CONFIG_IIO_TRIGGER is not set -# CONFIG_IIO_TRIGGERED_EVENT is not set -# CONFIG_IKCONFIG is not set -# CONFIG_IKCONFIG_PROC is not set -# CONFIG_IKHEADERS is not set -# CONFIG_IMA is not set -# CONFIG_IMGPDC_WDT is not set -# CONFIG_IMG_MDC_DMA is not set -# CONFIG_IMX7D_ADC is not set -# CONFIG_IMX_IPUV3_CORE is not set -# CONFIG_IMX_THERMAL is not set -# CONFIG_INA2XX_ADC is not set -# CONFIG_INDIRECT_PIO is not set -CONFIG_INET=y -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_ESPINTCP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_INET6_TUNNEL is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_DIAG is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_ESPINTCP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_LRO is not set -CONFIG_INET_TABLE_PERTURB_ORDER=16 -# CONFIG_INET_TCP_DIAG is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_UDP_DIAG is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INFINIBAND is not set -# CONFIG_INFTL is not set -# CONFIG_INGENIC_ADC is not set -# CONFIG_INGENIC_CGU_JZ4725B is not set -# CONFIG_INGENIC_CGU_JZ4740 is not set -# CONFIG_INGENIC_CGU_JZ4770 is not set -# CONFIG_INGENIC_CGU_JZ4780 is not set -# CONFIG_INGENIC_CGU_X1000 is not set -# CONFIG_INGENIC_CGU_X1830 is not set -# CONFIG_INGENIC_OST is not set -# CONFIG_INGENIC_SYSOST is not set -# CONFIG_INGENIC_TCU_CLK is not set -# CONFIG_INGENIC_TCU_IRQ is not set -# CONFIG_INGENIC_TIMER is not set -CONFIG_INIT_ENV_ARG_LIMIT=32 -# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set -# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set -# CONFIG_INIT_STACK_ALL_PATTERN is not set -# CONFIG_INIT_STACK_ALL_ZERO is not set -CONFIG_INIT_STACK_NONE=y -CONFIG_INOTIFY_USER=y -# CONFIG_INPUT is not set -# CONFIG_INPUT_AD714X is not set -# CONFIG_INPUT_ADXL34X is not set -# CONFIG_INPUT_APANEL is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_ATLAS_BTNS is not set -# CONFIG_INPUT_ATMEL_CAPTOUCH is not set -# CONFIG_INPUT_AXP20X_PEK is not set -# CONFIG_INPUT_BMA150 is not set -# CONFIG_INPUT_CM109 is not set -# CONFIG_INPUT_CMA3000 is not set -# CONFIG_INPUT_DRV260X_HAPTICS is not set -# CONFIG_INPUT_DRV2665_HAPTICS is not set -# CONFIG_INPUT_DRV2667_HAPTICS is not set -# CONFIG_INPUT_E3X0_BUTTON is not set -# CONFIG_INPUT_EVBUG is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_GP2A is not set -# CONFIG_INPUT_GPIO_BEEPER is not set -# CONFIG_INPUT_GPIO_DECODER is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_INPUT_GPIO_TILT_POLLED is not set -# CONFIG_INPUT_GPIO_VIBRA is not set -# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set -# CONFIG_INPUT_IMS_PCU is not set -# CONFIG_INPUT_IQS269A is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_KXTJ9 is not set -# CONFIG_INPUT_LEDS is not set -# CONFIG_INPUT_MATRIXKMAP is not set -# CONFIG_INPUT_MAX8997_HAPTIC is not set -CONFIG_INPUT_MISC=y -# CONFIG_INPUT_MMA8450 is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_MPU3050 is not set -# CONFIG_INPUT_MSM_VIBRATOR is not set -# CONFIG_INPUT_PALMAS_PWRBUTTON is not set -# CONFIG_INPUT_PCF8574 is not set -# CONFIG_INPUT_PCSPKR is not set -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_PWM_BEEPER is not set -# CONFIG_INPUT_PWM_VIBRA is not set -# CONFIG_INPUT_REGULATOR_HAPTIC is not set -# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set -# CONFIG_INPUT_SPARSEKMAP is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_TPS65218_PWRBUTTON is not set -# CONFIG_INPUT_TWL4030_PWRBUTTON is not set -# CONFIG_INPUT_TWL4030_VIBRA is not set -# CONFIG_INPUT_TWL6040_VIBRA is not set -# CONFIG_INPUT_UINPUT is not set -# CONFIG_INPUT_WISTRON_BTNS is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INT340X_THERMAL is not set -# CONFIG_INTEGRITY is not set -# CONFIG_INTEGRITY_AUDIT is not set -# CONFIG_INTEGRITY_SIGNATURE is not set -# CONFIG_INTEL_ATOMISP2_LED is not set -# CONFIG_INTEL_ATOMISP2_PM is not set -# CONFIG_INTEL_CHT_INT33FE is not set -# CONFIG_INTEL_HID_EVENT is not set -# CONFIG_INTEL_IDLE is not set -# CONFIG_INTEL_IDMA64 is not set -# CONFIG_INTEL_IDXD is not set -# CONFIG_INTEL_INT0002_VGPIO is not set -# CONFIG_INTEL_IOATDMA is not set -# CONFIG_INTEL_ISH_HID is not set -# CONFIG_INTEL_MEI is not set -# CONFIG_INTEL_MEI_ME is not set -# CONFIG_INTEL_MEI_TXE is not set -# CONFIG_INTEL_MIC_CARD is not set -# CONFIG_INTEL_MIC_HOST is not set -# CONFIG_INTEL_MID_PTI is not set -# CONFIG_INTEL_OAKTRAIL is not set -# CONFIG_INTEL_PMC_CORE is not set -# CONFIG_INTEL_PUNIT_IPC is not set -# CONFIG_INTEL_RST is not set -# CONFIG_INTEL_SMARTCONNECT is not set -# CONFIG_INTEL_SOC_PMIC is not set -# CONFIG_INTEL_SOC_PMIC_CHTDC_TI is not set -# CONFIG_INTEL_SOC_PMIC_CHTWC is not set -# CONFIG_INTEL_TH is not set -# CONFIG_INTEL_VBTN is not set -# CONFIG_INTEL_XWAY_PHY is not set -# CONFIG_INTERCONNECT is not set -# CONFIG_INTERVAL_TREE_TEST is not set -# CONFIG_INV_ICM42600_I2C is not set -# CONFIG_INV_ICM42600_SPI is not set -# CONFIG_INV_MPU6050_I2C is not set -# CONFIG_INV_MPU6050_IIO is not set -# CONFIG_INV_MPU6050_SPI is not set -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -# CONFIG_IOMMU_SUPPORT is not set -# CONFIG_IONIC is not set -# CONFIG_IOSCHED_BFQ is not set -CONFIG_IO_STRICT_DEVMEM=y -# CONFIG_IO_URING is not set -CONFIG_IO_WQ=y -# CONFIG_IP17XX_PHY is not set -# CONFIG_IP6_NF_FILTER is not set -# CONFIG_IP6_NF_IPTABLES is not set -# CONFIG_IP6_NF_MANGLE is not set -# CONFIG_IP6_NF_MATCH_AH is not set -# CONFIG_IP6_NF_MATCH_EUI64 is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_MH is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_RPFILTER is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_MATCH_SRH is not set -# CONFIG_IP6_NF_NAT is not set -# CONFIG_IP6_NF_RAW is not set -# CONFIG_IP6_NF_SECURITY is not set -# CONFIG_IP6_NF_TARGET_HL is not set -# CONFIG_IP6_NF_TARGET_MASQUERADE is not set -# CONFIG_IP6_NF_TARGET_REJECT is not set -# CONFIG_IP6_NF_TARGET_SYNPROXY is not set -# CONFIG_IPACK_BUS is not set -# CONFIG_IPC_NS is not set -# CONFIG_IPMB_DEVICE_INTERFACE is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_IPV6 is not set -# CONFIG_IPV6_FOU is not set -# CONFIG_IPV6_FOU_TUNNEL is not set -# CONFIG_IPV6_ILA is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_IPV6_MROUTE is not set -# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_ROUTE_INFO is not set -# CONFIG_IPV6_RPL_LWTUNNEL is not set -# CONFIG_IPV6_SEG6_HMAC is not set -# CONFIG_IPV6_SEG6_LWTUNNEL is not set -# CONFIG_IPV6_SIT is not set -# CONFIG_IPV6_SIT_6RD is not set -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_VTI is not set -# CONFIG_IPVLAN is not set -# CONFIG_IPVTAP is not set -# CONFIG_IPW2100 is not set -# CONFIG_IPW2100_DEBUG is not set -CONFIG_IPW2100_MONITOR=y -# CONFIG_IPW2200 is not set -# CONFIG_IPW2200_DEBUG is not set -CONFIG_IPW2200_MONITOR=y -# CONFIG_IPW2200_PROMISCUOUS is not set -# CONFIG_IPW2200_QOS is not set -# CONFIG_IPW2200_RADIOTAP is not set -# CONFIG_IPWIRELESS is not set -# CONFIG_IPX is not set -CONFIG_IP_ADVANCED_ROUTER=y -# CONFIG_IP_DCCP is not set -# CONFIG_IP_FIB_TRIE_STATS is not set -# CONFIG_IP_MROUTE is not set -CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_MULTIPLE_TABLES=y -# CONFIG_IP_NF_ARPFILTER is not set -# CONFIG_IP_NF_ARPTABLES is not set -# CONFIG_IP_NF_ARP_MANGLE is not set -# CONFIG_IP_NF_FILTER is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_MANGLE is not set -# CONFIG_IP_NF_MATCH_AH is not set -# CONFIG_IP_NF_MATCH_ECN is not set -# CONFIG_IP_NF_MATCH_RPFILTER is not set -# CONFIG_IP_NF_MATCH_TTL is not set -# CONFIG_IP_NF_RAW is not set -# CONFIG_IP_NF_SECURITY is not set -# CONFIG_IP_NF_TARGET_CLUSTERIP is not set -# CONFIG_IP_NF_TARGET_ECN is not set -# CONFIG_IP_NF_TARGET_MASQUERADE is not set -# CONFIG_IP_NF_TARGET_NETMAP is not set -# CONFIG_IP_NF_TARGET_REDIRECT is not set -# CONFIG_IP_NF_TARGET_REJECT is not set -# CONFIG_IP_NF_TARGET_SYNPROXY is not set -# CONFIG_IP_NF_TARGET_TTL is not set -# CONFIG_IP_PIMSM_V1 is not set -# CONFIG_IP_PIMSM_V2 is not set -# CONFIG_IP_PNP is not set -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -# CONFIG_IP_SCTP is not set -# CONFIG_IP_SET is not set -# CONFIG_IP_SET_HASH_IPMAC is not set -# CONFIG_IP_VS is not set -# CONFIG_IP_VS_MH is not set -CONFIG_IP_VS_MH_TAB_INDEX=10 -# CONFIG_IRDA is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_IRQ_ALL_CPUS is not set -# CONFIG_IRQ_DOMAIN_DEBUG is not set -# CONFIG_IRQ_POLL is not set -# CONFIG_IRQ_TIME_ACCOUNTING is not set -# CONFIG_IR_GPIO_CIR is not set -# CONFIG_IR_HIX5HD2 is not set -# CONFIG_IR_IGORPLUGUSB is not set -# CONFIG_IR_IGUANA is not set -# CONFIG_IR_IMG is not set -# CONFIG_IR_IMON is not set -# CONFIG_IR_IMON_RAW is not set -# CONFIG_IR_JVC_DECODER is not set -# CONFIG_IR_LIRC_CODEC is not set -# CONFIG_IR_MCEUSB is not set -# CONFIG_IR_NEC_DECODER is not set -# CONFIG_IR_RC5_DECODER is not set -# CONFIG_IR_RC6_DECODER is not set -# CONFIG_IR_REDRAT3 is not set -# CONFIG_IR_SERIAL is not set -# CONFIG_IR_SIR is not set -# CONFIG_IR_SONY_DECODER is not set -# CONFIG_IR_STREAMZAP is not set -# CONFIG_IR_TOY is not set -# CONFIG_IR_TTUSBIR is not set -# CONFIG_ISA_BUS is not set -# CONFIG_ISA_BUS_API is not set -# CONFIG_ISCSI_BOOT_SYSFS is not set -# CONFIG_ISCSI_TCP is not set -CONFIG_ISDN=y -# CONFIG_ISDN_AUDIO is not set -# CONFIG_ISDN_CAPI is not set -# CONFIG_ISDN_CAPI_CAPIDRV is not set -# CONFIG_ISDN_DIVERSION is not set -# CONFIG_ISDN_DRV_ACT2000 is not set -# CONFIG_ISDN_DRV_GIGASET is not set -# CONFIG_ISDN_DRV_HISAX is not set -# CONFIG_ISDN_DRV_ICN is not set -# CONFIG_ISDN_DRV_LOOP is not set -# CONFIG_ISDN_DRV_PCBIT is not set -# CONFIG_ISDN_DRV_SC is not set -# CONFIG_ISDN_I4L is not set -# CONFIG_ISL29003 is not set -# CONFIG_ISL29020 is not set -# CONFIG_ISL29125 is not set -# CONFIG_ISL29501 is not set -# CONFIG_ISO9660_FS is not set -# CONFIG_ISS4xx is not set -# CONFIG_ITG3200 is not set -# CONFIG_IWL3945 is not set -# CONFIG_IWLWIFI is not set -# CONFIG_IXGB is not set -# CONFIG_IXGBE is not set -# CONFIG_IXGBEVF is not set -# CONFIG_JAILHOUSE_GUEST is not set -# CONFIG_JBD2_DEBUG is not set -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set -# CONFIG_JFFS2_CMODE_NONE is not set -CONFIG_JFFS2_CMODE_PRIORITY=y -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFFS2_FS_POSIX_ACL is not set -# CONFIG_JFFS2_FS_SECURITY is not set -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -CONFIG_JFFS2_FS_WRITEBUFFER=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_LZMA=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -CONFIG_JFFS2_SUMMARY=y -# CONFIG_JFFS2_ZLIB is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_FS is not set -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_STATISTICS is not set -# CONFIG_JME is not set -CONFIG_JOLIET=y -# CONFIG_JSA1212 is not set -# CONFIG_JUMP_LABEL is not set -# CONFIG_JZ4740_WDT is not set -# CONFIG_JZ4770_PHY is not set -# CONFIG_KALLSYMS is not set -# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_KALLSYMS_UNCOMPRESSED is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_KASAN is not set -CONFIG_KASAN_STACK=1 -# CONFIG_KCMP is not set -# CONFIG_KCOV is not set -# CONFIG_KCSAN is not set -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_CAT is not set -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_LZ4 is not set -# CONFIG_KERNEL_LZMA is not set -# CONFIG_KERNEL_LZO is not set -CONFIG_KERNEL_MODE_NEON=y -CONFIG_KERNEL_XZ=y -# CONFIG_KERNEL_ZSTD is not set -CONFIG_KERNFS=y -# CONFIG_KEXEC is not set -# CONFIG_KEXEC_FILE is not set -# CONFIG_KEXEC_SIG is not set -# CONFIG_KEYBOARD_ADC is not set -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set -# CONFIG_KEYBOARD_APPLESPI is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_KEYBOARD_BCM is not set -# CONFIG_KEYBOARD_CAP11XX is not set -# CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_GPIO_POLLED is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_LM8333 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set -# CONFIG_KEYBOARD_MPR121 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OMAP4 is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_PXA27x is not set -# CONFIG_KEYBOARD_QT1050 is not set -# CONFIG_KEYBOARD_QT1070 is not set -# CONFIG_KEYBOARD_QT2160 is not set -# CONFIG_KEYBOARD_SAMSUNG is not set -# CONFIG_KEYBOARD_SH_KEYSC is not set -# CONFIG_KEYBOARD_SNVS_PWRKEY is not set -# CONFIG_KEYBOARD_STMPE is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_TCA8418 is not set -# CONFIG_KEYBOARD_TEGRA is not set -# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set -# CONFIG_KEYBOARD_TWL4030 is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYS is not set -# CONFIG_KEYS_REQUEST_CACHE is not set -# CONFIG_KEY_DH_OPERATIONS is not set -# CONFIG_KGDB is not set -# CONFIG_KMEMCHECK is not set -# CONFIG_KMX61 is not set -# CONFIG_KPC2000 is not set -# CONFIG_KPROBES is not set -# CONFIG_KPROBES_SANITY_TEST is not set -# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set -# CONFIG_KPROBE_EVENT_GEN_TEST is not set -# CONFIG_KS7010 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_KSM is not set -# CONFIG_KSZ884X_PCI is not set -# CONFIG_KUNIT is not set -CONFIG_KUSER_HELPERS=y -# CONFIG_KVM_AMD is not set -# CONFIG_KVM_AMD_SEV is not set -# CONFIG_KVM_GUEST is not set -# CONFIG_KVM_INTEL is not set -# CONFIG_KVM_WERROR is not set -# CONFIG_KXCJK1013 is not set -# CONFIG_KXSD9 is not set -# CONFIG_L2TP is not set -# CONFIG_L2TP_ETH is not set -# CONFIG_L2TP_IP is not set -# CONFIG_L2TP_V3 is not set -# CONFIG_LAN743X is not set -# CONFIG_LANMEDIA is not set -# CONFIG_LANTIQ is not set -# CONFIG_LAPB is not set -# CONFIG_LASAT is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_LATTICE_ECP3_CONFIG is not set -CONFIG_LBDAF=y -# CONFIG_LCD_AMS369FG06 is not set -# CONFIG_LCD_CLASS_DEVICE is not set -# CONFIG_LCD_HX8357 is not set -# CONFIG_LCD_ILI922X is not set -# CONFIG_LCD_ILI9320 is not set -# CONFIG_LCD_L4F00242T03 is not set -# CONFIG_LCD_LD9040 is not set -# CONFIG_LCD_LMS283GF05 is not set -# CONFIG_LCD_LMS501KF03 is not set -# CONFIG_LCD_LTV350QV is not set -# CONFIG_LCD_OTM3225A is not set -# CONFIG_LCD_S6E63M0 is not set -# CONFIG_LCD_TDO24M is not set -# CONFIG_LCD_VGG2432A4 is not set -CONFIG_LDISC_AUTOLOAD=y -# CONFIG_LDM_PARTITION is not set -CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y -# CONFIG_LD_HEAD_STUB_CATCH is not set -# CONFIG_LEDS_AN30259A is not set -# CONFIG_LEDS_APU is not set -# CONFIG_LEDS_AW2013 is not set -# CONFIG_LEDS_BCM6328 is not set -# CONFIG_LEDS_BCM6358 is not set -# CONFIG_LEDS_BD2802 is not set -# CONFIG_LEDS_BLINKM is not set -CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y -CONFIG_LEDS_CLASS=y -# CONFIG_LEDS_CLASS_FLASH is not set -CONFIG_LEDS_CLASS_MULTICOLOR=y -# CONFIG_LEDS_CR0014114 is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_EL15203000 is not set -# CONFIG_LEDS_GPIO is not set -# CONFIG_LEDS_INTEL_SS4200 is not set -# CONFIG_LEDS_IS31FL319X is not set -# CONFIG_LEDS_IS31FL32XX is not set -# CONFIG_LEDS_LM3530 is not set -# CONFIG_LEDS_LM3532 is not set -# CONFIG_LEDS_LM355x is not set -# CONFIG_LEDS_LM3642 is not set -# CONFIG_LEDS_LM3692X is not set -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP50XX is not set -# CONFIG_LEDS_LP5521 is not set -# CONFIG_LEDS_LP5523 is not set -# CONFIG_LEDS_LP5562 is not set -# CONFIG_LEDS_LP55XX_COMMON is not set -# CONFIG_LEDS_LP8501 is not set -# CONFIG_LEDS_LP8860 is not set -# CONFIG_LEDS_LT3593 is not set -# CONFIG_LEDS_MLXCPLD is not set -# CONFIG_LEDS_MLXREG is not set -# CONFIG_LEDS_NIC78BX is not set -# CONFIG_LEDS_NS2 is not set -# CONFIG_LEDS_OT200 is not set -# CONFIG_LEDS_PCA9532 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_PCA963X is not set -# CONFIG_LEDS_PWM is not set -# CONFIG_LEDS_REGULATOR is not set -# CONFIG_LEDS_SPI_BYTE is not set -# CONFIG_LEDS_SYSCON is not set -# CONFIG_LEDS_TCA6507 is not set -# CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_TLC591XX is not set -CONFIG_LEDS_TRIGGERS=y -# CONFIG_LEDS_TRIGGER_ACTIVITY is not set -# CONFIG_LEDS_TRIGGER_AUDIO is not set -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set -# CONFIG_LEDS_TRIGGER_CAMERA is not set -# CONFIG_LEDS_TRIGGER_CPU is not set -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -# CONFIG_LEDS_TRIGGER_DISK is not set -# CONFIG_LEDS_TRIGGER_GPIO is not set -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -# CONFIG_LEDS_TRIGGER_MTD is not set -CONFIG_LEDS_TRIGGER_NETDEV=y -# CONFIG_LEDS_TRIGGER_ONESHOT is not set -# CONFIG_LEDS_TRIGGER_PANIC is not set -# CONFIG_LEDS_TRIGGER_PATTERN is not set -CONFIG_LEDS_TRIGGER_TIMER=y -# CONFIG_LEDS_TRIGGER_TRANSIENT is not set -# CONFIG_LEDS_TURRIS_OMNIA is not set -# CONFIG_LEDS_USER is not set -# CONFIG_LED_TRIGGER_PHY is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_LGUEST is not set -# CONFIG_LIB80211 is not set -# CONFIG_LIB80211_CRYPT_CCMP is not set -# CONFIG_LIB80211_CRYPT_TKIP is not set -# CONFIG_LIB80211_CRYPT_WEP is not set -# CONFIG_LIB80211_DEBUG is not set -# CONFIG_LIBCRC32C is not set -# CONFIG_LIBERTAS is not set -# CONFIG_LIBERTAS_THINFIRM is not set -# CONFIG_LIBERTAS_USB is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_LIBIPW_DEBUG is not set -# CONFIG_LIBNVDIMM is not set -CONFIG_LIB_MEMNEQ=y -# CONFIG_LIDAR_LITE_V2 is not set -CONFIG_LINEAR_RANGES=y -# CONFIG_LIQUIDIO is not set -# CONFIG_LIQUIDIO_VF is not set -# CONFIG_LIRC is not set -# CONFIG_LIS3L02DQ is not set -# CONFIG_LKDTM is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_LMP91000 is not set -# CONFIG_LNET is not set -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_LOCKD is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_LOCKD_V4=y -# CONFIG_LOCKUP_DETECTOR is not set -# CONFIG_LOCK_EVENT_COUNTS is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_LOCK_TORTURE_TEST is not set -# CONFIG_LOGFS is not set -# CONFIG_LOGIG940_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIWHEELS_FF is not set -# CONFIG_LOGO is not set -CONFIG_LOG_BUF_SHIFT=17 -CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 -# CONFIG_LOONGSON_MC146818 is not set -# CONFIG_LPC_ICH is not set -# CONFIG_LPC_SCH is not set -# CONFIG_LP_CONSOLE is not set -# CONFIG_LSI_ET1011C_PHY is not set -CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" -CONFIG_LSM_MMAP_MIN_ADDR=65536 -# CONFIG_LTC1660 is not set -# CONFIG_LTC2471 is not set -# CONFIG_LTC2485 is not set -# CONFIG_LTC2496 is not set -# CONFIG_LTC2497 is not set -# CONFIG_LTC2632 is not set -# CONFIG_LTC2983 is not set -# CONFIG_LTE_GDM724X is not set -# CONFIG_LTPC is not set -# CONFIG_LTR501 is not set -# CONFIG_LUSTRE_FS is not set -# CONFIG_LV0104CS is not set -# CONFIG_LWTUNNEL is not set -# CONFIG_LXT_PHY is not set -# CONFIG_LZ4HC_COMPRESS is not set -# CONFIG_LZ4_COMPRESS is not set -# CONFIG_LZ4_DECOMPRESS is not set -CONFIG_LZMA_COMPRESS=y -CONFIG_LZMA_DECOMPRESS=y -# CONFIG_LZO_COMPRESS is not set -# CONFIG_LZO_DECOMPRESS is not set -# CONFIG_M62332 is not set -# CONFIG_MAC80211 is not set -# CONFIG_MAC80211_MESSAGE_TRACING is not set -CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_MACB is not set -# CONFIG_MACB_USE_HWSTAMP is not set -# CONFIG_MACH_ASM9260 is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_INGENIC is not set -# CONFIG_MACH_INGENIC_SOC is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_JZ4740 is not set -# CONFIG_MACH_LOONGSON2EF is not set -# CONFIG_MACH_LOONGSON32 is not set -# CONFIG_MACH_LOONGSON64 is not set -# CONFIG_MACH_PIC32 is not set -# CONFIG_MACH_PISTACHIO is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_MACH_XILFPGA is not set -# CONFIG_MACINTOSH_DRIVERS is not set -# CONFIG_MACSEC is not set -# CONFIG_MACVLAN is not set -# CONFIG_MACVTAP is not set -# CONFIG_MAC_EMUMOUSEBTN is not set -# CONFIG_MAC_PARTITION is not set -# CONFIG_MAG3110 is not set -# CONFIG_MAGIC_SYSRQ is not set -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -# CONFIG_MAGIC_SYSRQ_SERIAL is not set -CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" -# CONFIG_MAILBOX is not set -# CONFIG_MANAGER_SBS is not set -# CONFIG_MANDATORY_FILE_LOCKING is not set -# CONFIG_MANGLE_BOOTARGS is not set -# CONFIG_MARVELL_10G_PHY is not set -# CONFIG_MARVELL_PHY is not set -# CONFIG_MAX1027 is not set -# CONFIG_MAX11100 is not set -# CONFIG_MAX1118 is not set -# CONFIG_MAX1241 is not set -# CONFIG_MAX1363 is not set -# CONFIG_MAX30100 is not set -# CONFIG_MAX30102 is not set -# CONFIG_MAX31856 is not set -# CONFIG_MAX44000 is not set -# CONFIG_MAX44009 is not set -# CONFIG_MAX517 is not set -# CONFIG_MAX5432 is not set -# CONFIG_MAX5481 is not set -# CONFIG_MAX5487 is not set -# CONFIG_MAX5821 is not set -# CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_MAX9611 is not set -# CONFIG_MAXIM_THERMOCOUPLE is not set -CONFIG_MAY_USE_DEVLINK=y -# CONFIG_MB1232 is not set -# CONFIG_MC3230 is not set -# CONFIG_MCB is not set -# CONFIG_MCP320X is not set -# CONFIG_MCP3422 is not set -# CONFIG_MCP3911 is not set -# CONFIG_MCP4018 is not set -# CONFIG_MCP41010 is not set -# CONFIG_MCP4131 is not set -# CONFIG_MCP4531 is not set -# CONFIG_MCP4725 is not set -# CONFIG_MCP4922 is not set -# CONFIG_MCPM is not set -# CONFIG_MD is not set -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_BUS_MUX_GPIO is not set -# CONFIG_MDIO_BUS_MUX_MMIOREG is not set -# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set -# CONFIG_MDIO_DEVICE is not set -# CONFIG_MDIO_DEVRES is not set -# CONFIG_MDIO_HISI_FEMAC is not set -# CONFIG_MDIO_IPQ4019 is not set -# CONFIG_MDIO_IPQ8064 is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_MVUSB is not set -# CONFIG_MDIO_OCTEON is not set -# CONFIG_MDIO_THUNDER is not set -# CONFIG_MDIO_XPCS is not set -# CONFIG_MD_FAULTY is not set -# CONFIG_MEDIATEK_GE_PHY is not set -# CONFIG_MEDIATEK_MT6577_AUXADC is not set -# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set -# CONFIG_MEDIA_ATTACH is not set -# CONFIG_MEDIA_CAMERA_SUPPORT is not set -# CONFIG_MEDIA_CEC_SUPPORT is not set -# CONFIG_MEDIA_CONTROLLER is not set -# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set -# CONFIG_MEDIA_PCI_SUPPORT is not set -# CONFIG_MEDIA_PLATFORM_SUPPORT is not set -# CONFIG_MEDIA_RADIO_SUPPORT is not set -# CONFIG_MEDIA_RC_SUPPORT is not set -# CONFIG_MEDIA_SDR_SUPPORT is not set -# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -# CONFIG_MEDIA_SUPPORT is not set -# CONFIG_MEDIA_SUPPORT_FILTER is not set -# CONFIG_MEDIA_TEST_SUPPORT is not set -# CONFIG_MEDIA_TUNER_E4000 is not set -# CONFIG_MEDIA_TUNER_FC0011 is not set -# CONFIG_MEDIA_TUNER_FC0012 is not set -# CONFIG_MEDIA_TUNER_FC0013 is not set -# CONFIG_MEDIA_TUNER_FC2580 is not set -# CONFIG_MEDIA_TUNER_IT913X is not set -# CONFIG_MEDIA_TUNER_M88RS6000T is not set -# CONFIG_MEDIA_TUNER_MAX2165 is not set -# CONFIG_MEDIA_TUNER_MC44S803 is not set -# CONFIG_MEDIA_TUNER_MSI001 is not set -# CONFIG_MEDIA_TUNER_MT2060 is not set -# CONFIG_MEDIA_TUNER_MT2063 is not set -# CONFIG_MEDIA_TUNER_MT20XX is not set -# CONFIG_MEDIA_TUNER_MT2131 is not set -# CONFIG_MEDIA_TUNER_MT2266 is not set -# CONFIG_MEDIA_TUNER_MXL301RF is not set -# CONFIG_MEDIA_TUNER_MXL5005S is not set -# CONFIG_MEDIA_TUNER_MXL5007T is not set -# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set -# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set -# CONFIG_MEDIA_TUNER_QT1010 is not set -# CONFIG_MEDIA_TUNER_R820T is not set -# CONFIG_MEDIA_TUNER_SI2157 is not set -# CONFIG_MEDIA_TUNER_SIMPLE is not set -# CONFIG_MEDIA_TUNER_TDA18212 is not set -# CONFIG_MEDIA_TUNER_TDA18218 is not set -# CONFIG_MEDIA_TUNER_TDA18250 is not set -# CONFIG_MEDIA_TUNER_TDA18271 is not set -# CONFIG_MEDIA_TUNER_TDA827X is not set -# CONFIG_MEDIA_TUNER_TDA8290 is not set -# CONFIG_MEDIA_TUNER_TDA9887 is not set -# CONFIG_MEDIA_TUNER_TEA5761 is not set -# CONFIG_MEDIA_TUNER_TEA5767 is not set -# CONFIG_MEDIA_TUNER_TUA9001 is not set -# CONFIG_MEDIA_TUNER_XC2028 is not set -# CONFIG_MEDIA_TUNER_XC4000 is not set -# CONFIG_MEDIA_TUNER_XC5000 is not set -# CONFIG_MEDIA_USB_SUPPORT is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_MELLANOX_PLATFORM is not set -CONFIG_MEMBARRIER=y -# CONFIG_MEMORY is not set -# CONFIG_MEMORY_FAILURE is not set -# CONFIG_MEMORY_HOTPLUG is not set -# CONFIG_MEMSTICK is not set -# CONFIG_MEMTEST is not set -# CONFIG_MEN_A21_WDT is not set -# CONFIG_MESON_SM is not set -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_MFD_88PM800 is not set -# CONFIG_MFD_88PM805 is not set -# CONFIG_MFD_88PM860X is not set -# CONFIG_MFD_AAT2870_CORE is not set -# CONFIG_MFD_AC100 is not set -# CONFIG_MFD_ACT8945A is not set -# CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_ARIZONA_SPI is not set -# CONFIG_MFD_AS3711 is not set -# CONFIG_MFD_AS3722 is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_MFD_ATMEL_FLEXCOM is not set -# CONFIG_MFD_ATMEL_HLCDC is not set -# CONFIG_MFD_AXP20X is not set -# CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_BCM590XX is not set -# CONFIG_MFD_BD9571MWV is not set -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_CPCAP is not set -# CONFIG_MFD_CROS_EC is not set -# CONFIG_MFD_CS5535 is not set -# CONFIG_MFD_DA9052_I2C is not set -# CONFIG_MFD_DA9052_SPI is not set -# CONFIG_MFD_DA9055 is not set -# CONFIG_MFD_DA9062 is not set -# CONFIG_MFD_DA9063 is not set -# CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_DLN2 is not set -# CONFIG_MFD_EXYNOS_LPASS is not set -# CONFIG_MFD_GATEWORKS_GSC is not set -# CONFIG_MFD_HI6421_PMIC is not set -# CONFIG_MFD_INTEL_M10_BMC is not set -# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set -# CONFIG_MFD_IQS62X is not set -# CONFIG_MFD_JANZ_CMODIO is not set -# CONFIG_MFD_KEMPLD is not set -# CONFIG_MFD_LM3533 is not set -# CONFIG_MFD_LOCHNAGAR is not set -# CONFIG_MFD_LP3943 is not set -# CONFIG_MFD_LP8788 is not set -# CONFIG_MFD_MADERA is not set -# CONFIG_MFD_MAX14577 is not set -# CONFIG_MFD_MAX77620 is not set -# CONFIG_MFD_MAX77650 is not set -# CONFIG_MFD_MAX77686 is not set -# CONFIG_MFD_MAX77693 is not set -# CONFIG_MFD_MAX77843 is not set -# CONFIG_MFD_MAX8907 is not set -# CONFIG_MFD_MAX8925 is not set -# CONFIG_MFD_MAX8997 is not set -# CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_MC13XXX is not set -# CONFIG_MFD_MC13XXX_I2C is not set -# CONFIG_MFD_MC13XXX_SPI is not set -# CONFIG_MFD_MENF21BMC is not set -# CONFIG_MFD_MP2629 is not set -# CONFIG_MFD_MT6360 is not set -# CONFIG_MFD_MT6397 is not set -# CONFIG_MFD_OMAP_USB_HOST is not set -# CONFIG_MFD_PALMAS is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_PM8921_CORE is not set -# CONFIG_MFD_PM8XXX is not set -# CONFIG_MFD_RC5T583 is not set -# CONFIG_MFD_RDC321X is not set -# CONFIG_MFD_RETU is not set -# CONFIG_MFD_RK808 is not set -# CONFIG_MFD_RN5T618 is not set -# CONFIG_MFD_ROHM_BD70528 is not set -# CONFIG_MFD_ROHM_BD71828 is not set -# CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RTSX_PCI is not set -# CONFIG_MFD_RTSX_USB is not set -# CONFIG_MFD_SEC_CORE is not set -# CONFIG_MFD_SI476X_CORE is not set -# CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SL28CPLD is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SMSC is not set -# CONFIG_MFD_STMFX is not set -# CONFIG_MFD_STMPE is not set -# CONFIG_MFD_STPMIC1 is not set -# CONFIG_MFD_SYSCON is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC3589X is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_MFD_TIMBERDALE is not set -# CONFIG_MFD_TI_AM335X_TSCADC is not set -# CONFIG_MFD_TI_LMU is not set -# CONFIG_MFD_TI_LP873X is not set -# CONFIG_MFD_TI_LP87565 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_TPS65086 is not set -# CONFIG_MFD_TPS65090 is not set -# CONFIG_MFD_TPS65217 is not set -# CONFIG_MFD_TPS65218 is not set -# CONFIG_MFD_TPS6586X is not set -# CONFIG_MFD_TPS65910 is not set -# CONFIG_MFD_TPS65912 is not set -# CONFIG_MFD_TPS65912_I2C is not set -# CONFIG_MFD_TPS65912_SPI is not set -# CONFIG_MFD_TPS68470 is not set -# CONFIG_MFD_TPS80031 is not set -# CONFIG_MFD_TQMX86 is not set -# CONFIG_MFD_VIPERBOARD is not set -# CONFIG_MFD_VX855 is not set -# CONFIG_MFD_WL1273_CORE is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM831X_I2C is not set -# CONFIG_MFD_WM831X_SPI is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM8994 is not set -# CONFIG_MG_DISK is not set -# CONFIG_MHI_BUS is not set -# CONFIG_MICREL_KS8995MA is not set -# CONFIG_MICREL_PHY is not set -# CONFIG_MICROCHIP_KSZ is not set -# CONFIG_MICROCHIP_PHY is not set -# CONFIG_MICROCHIP_PIT64B is not set -# CONFIG_MICROCHIP_T1_PHY is not set -# CONFIG_MICROSEMI_PHY is not set -# CONFIG_MIGRATION is not set -CONFIG_MII=y -# CONFIG_MIKROTIK is not set -# CONFIG_MIKROTIK_RB532 is not set -# CONFIG_MINIX_FS is not set -# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_MIPS_ALCHEMY is not set -# CONFIG_MIPS_CDMM is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MIPS_FPU_EMULATOR is not set -# CONFIG_MIPS_FP_SUPPORT is not set -# CONFIG_MIPS_GENERIC is not set -# CONFIG_MIPS_GENERIC_KERNEL is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_O32_FP64_SUPPORT is not set -# CONFIG_MIPS_PARAVIRT is not set -# CONFIG_MIPS_PLATFORM_DEVICES is not set -# CONFIG_MIPS_SEAD3 is not set -# CONFIG_MISC_ALCOR_PCI is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_MISC_RTSX_PCI is not set -# CONFIG_MISC_RTSX_USB is not set -# CONFIG_MISDN is not set -# CONFIG_MISDN_AVMFRITZ is not set -# CONFIG_MISDN_HFCPCI is not set -# CONFIG_MISDN_HFCUSB is not set -# CONFIG_MISDN_INFINEON is not set -# CONFIG_MISDN_NETJET is not set -# CONFIG_MISDN_SPEEDFAX is not set -# CONFIG_MISDN_W6692 is not set -CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y -# CONFIG_MKISS is not set -# CONFIG_MLX4_CORE is not set -# CONFIG_MLX4_EN is not set -# CONFIG_MLX5_CORE is not set -# CONFIG_MLX90614 is not set -# CONFIG_MLX90632 is not set -# CONFIG_MLXFW is not set -# CONFIG_MLXSW_CORE is not set -# CONFIG_MLX_CPLD_PLATFORM is not set -# CONFIG_MLX_PLATFORM is not set -# CONFIG_MMA7455_I2C is not set -# CONFIG_MMA7455_SPI is not set -# CONFIG_MMA7660 is not set -# CONFIG_MMA8452 is not set -# CONFIG_MMA9551 is not set -# CONFIG_MMA9553 is not set -# CONFIG_MMC is not set -# CONFIG_MMC35240 is not set -# CONFIG_MMC_ARMMMCI is not set -# CONFIG_MMC_AU1X is not set -# CONFIG_MMC_BLOCK is not set -CONFIG_MMC_BLOCK_MINORS=8 -# CONFIG_MMC_CAVIUM_THUNDERX is not set -# CONFIG_MMC_CB710 is not set -# CONFIG_MMC_CQHCI is not set -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_DW is not set -# CONFIG_MMC_HSQ is not set -# CONFIG_MMC_JZ4740 is not set -# CONFIG_MMC_MTK is not set -# CONFIG_MMC_MVSDIO is not set -# CONFIG_MMC_S3C is not set -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_SDHCI_ACPI is not set -# CONFIG_MMC_SDHCI_AM654 is not set -# CONFIG_MMC_SDHCI_BCM_KONA is not set -# CONFIG_MMC_SDHCI_BRCMSTB is not set -# CONFIG_MMC_SDHCI_CADENCE is not set -# CONFIG_MMC_SDHCI_F_SDH30 is not set -# CONFIG_MMC_SDHCI_IPROC is not set -# CONFIG_MMC_SDHCI_MILBEAUT is not set -# CONFIG_MMC_SDHCI_MSM is not set -# CONFIG_MMC_SDHCI_OF_ARASAN is not set -# CONFIG_MMC_SDHCI_OF_ASPEED is not set -# CONFIG_MMC_SDHCI_OF_AT91 is not set -# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set -# CONFIG_MMC_SDHCI_OF_ESDHC is not set -# CONFIG_MMC_SDHCI_OF_HLWD is not set -# CONFIG_MMC_SDHCI_OMAP is not set -# CONFIG_MMC_SDHCI_PXAV2 is not set -# CONFIG_MMC_SDHCI_PXAV3 is not set -# CONFIG_MMC_SDHCI_S3C is not set -# CONFIG_MMC_SDHCI_XENON is not set -# CONFIG_MMC_SDRICOH_CS is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MMC_STM32_SDMMC is not set -# CONFIG_MMC_TEST is not set -# CONFIG_MMC_TIFM_SD is not set -# CONFIG_MMC_TOSHIBA_PCI is not set -# CONFIG_MMC_USDHI6ROL0 is not set -# CONFIG_MMC_USHC is not set -# CONFIG_MMC_VIA_SDMMC is not set -# CONFIG_MMC_VUB300 is not set -# CONFIG_MMIOTRACE is not set -CONFIG_MMU=y -CONFIG_MMU_GATHER_RCU_TABLE_FREE=y -CONFIG_MMU_GATHER_TABLE_FREE=y -CONFIG_MODULES=y -# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_MODULE_COMPRESS is not set -# CONFIG_MODULE_FORCE_LOAD is not set -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODULE_SIG is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_MODULE_STRIPPED=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MOST is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_ELAN_I2C is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_INPORT is not set -# CONFIG_MOUSE_LOGIBM is not set -# CONFIG_MOUSE_PC110PAD is not set -# CONFIG_MOUSE_PS2_FOCALTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_MOUSE_SYNAPTICS_USB is not set -# CONFIG_MOXTET is not set -# CONFIG_MPL115 is not set -# CONFIG_MPL115_I2C is not set -# CONFIG_MPL115_SPI is not set -# CONFIG_MPL3115 is not set -# CONFIG_MPLS is not set -# CONFIG_MPLS_IPTUNNEL is not set -# CONFIG_MPLS_ROUTING is not set -# CONFIG_MPTCP is not set -# CONFIG_MPU3050_I2C is not set -# CONFIG_MQ_IOSCHED_DEADLINE is not set -# CONFIG_MQ_IOSCHED_KYBER is not set -# CONFIG_MS5611 is not set -# CONFIG_MS5637 is not set -# CONFIG_MSCC_OCELOT_SWITCH is not set -# CONFIG_MSDOS_FS is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_MSI_BITMAP_SELFTEST is not set -# CONFIG_MSI_LAPTOP is not set -# CONFIG_MST_IRQ is not set -CONFIG_MTD=y -# CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_AR7_PARTS is not set -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_MTD_BLOCK2MTD is not set -CONFIG_MTD_CFI=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set -CONFIG_MTD_CFI_AMDSTD=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_STAA is not set -CONFIG_MTD_CFI_UTIL=y -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_DOCG3 is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_GPIO_ADDR is not set -# CONFIG_MTD_HYPERBUS is not set -# CONFIG_MTD_IMPA7 is not set -# CONFIG_MTD_INTEL_VR_NOR is not set -# CONFIG_MTD_JEDECPROBE is not set -# CONFIG_MTD_LATCH_ADDR is not set -# CONFIG_MTD_LPDDR is not set -# CONFIG_MTD_LPDDR2_NVM is not set -# CONFIG_MTD_M25P80 is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -CONFIG_MTD_MAP_BANK_WIDTH_2=y -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MCHP23K256 is not set -# CONFIG_MTD_MT81xx_NOR is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_MYLOADER_PARTS is not set -# CONFIG_MTD_NAND is not set -# CONFIG_MTD_NAND_AMS_DELTA is not set -# CONFIG_MTD_NAND_AR934X is not set -# CONFIG_MTD_NAND_AR934X_HW_ECC is not set -# CONFIG_MTD_NAND_ARASAN is not set -# CONFIG_MTD_NAND_ATMEL is not set -# CONFIG_MTD_NAND_AU1550 is not set -# CONFIG_MTD_NAND_BCH is not set -# CONFIG_MTD_NAND_BF5XX is not set -# CONFIG_MTD_NAND_BRCMNAND is not set -# CONFIG_MTD_NAND_CADENCE is not set -# CONFIG_MTD_NAND_CAFE is not set -# CONFIG_MTD_NAND_CM_X270 is not set -# CONFIG_MTD_NAND_CS553X is not set -# CONFIG_MTD_NAND_DAVINCI is not set -# CONFIG_MTD_NAND_DENALI is not set -# CONFIG_MTD_NAND_DENALI_DT is not set -# CONFIG_MTD_NAND_DENALI_PCI is not set -CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018 -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_DOCG4 is not set -# CONFIG_MTD_NAND_ECC is not set -# CONFIG_MTD_NAND_ECC_BCH is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_ECC_SW_BCH is not set -# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set -# CONFIG_MTD_NAND_FSL_ELBC is not set -# CONFIG_MTD_NAND_FSL_IFC is not set -# CONFIG_MTD_NAND_FSL_UPM is not set -# CONFIG_MTD_NAND_FSMC is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_GPMI_NAND is not set -# CONFIG_MTD_NAND_HISI504 is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_JZ4740 is not set -# CONFIG_MTD_NAND_MPC5121_NFC is not set -# CONFIG_MTD_NAND_MTK is not set -# CONFIG_MTD_NAND_MTK_BMT is not set -# CONFIG_MTD_NAND_MXC is not set -# CONFIG_MTD_NAND_MXIC is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_NDFC is not set -# CONFIG_MTD_NAND_NUC900 is not set -# CONFIG_MTD_NAND_OMAP2 is not set -# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set -# CONFIG_MTD_NAND_ORION is not set -# CONFIG_MTD_NAND_PASEMI is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_NAND_PXA3xx is not set -# CONFIG_MTD_NAND_RB4XX is not set -# CONFIG_MTD_NAND_RB750 is not set -# CONFIG_MTD_NAND_RB91X is not set -# CONFIG_MTD_NAND_RICOH is not set -# CONFIG_MTD_NAND_S3C2410 is not set -# CONFIG_MTD_NAND_SHARPSL is not set -# CONFIG_MTD_NAND_SH_FLCTL is not set -# CONFIG_MTD_NAND_SOCRATES is not set -# CONFIG_MTD_NAND_TMIO is not set -# CONFIG_MTD_NAND_TXX9NDFMC is not set -CONFIG_MTD_OF_PARTS=y -# CONFIG_MTD_ONENAND is not set -# CONFIG_MTD_OOPS is not set -# CONFIG_MTD_OTP is not set -# CONFIG_MTD_PARSER_TRX is not set -# CONFIG_MTD_PARTITIONED_MASTER is not set -# CONFIG_MTD_PCI is not set -# CONFIG_MTD_PCMCIA is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_PHYSMAP is not set -# CONFIG_MTD_PHYSMAP_COMPAT is not set -# CONFIG_MTD_PHYSMAP_GEMINI is not set -# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set -# CONFIG_MTD_PHYSMAP_IXP4XX is not set -CONFIG_MTD_PHYSMAP_OF=y -# CONFIG_MTD_PHYSMAP_OF_GEMINI is not set -# CONFIG_MTD_PHYSMAP_OF_VERSATILE is not set -# CONFIG_MTD_PHYSMAP_VERSATILE is not set -# CONFIG_MTD_PLATRAM is not set -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_RAW_NAND is not set -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set -# CONFIG_MTD_ROM is not set -CONFIG_MTD_ROOTFS_ROOT_DEV=y -# CONFIG_MTD_ROUTERBOOT_PARTS is not set -# CONFIG_MTD_SERCOMM_PARTS is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_SM_COMMON is not set -# CONFIG_MTD_SPINAND_MT29F is not set -# CONFIG_MTD_SPI_NAND is not set -# CONFIG_MTD_SPI_NOR is not set -# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set -# CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE is not set -CONFIG_MTD_SPLIT=y -# CONFIG_MTD_SPLIT_BCM63XX_FW is not set -# CONFIG_MTD_SPLIT_BCM_WFI_FW is not set -# CONFIG_MTD_SPLIT_BRNIMAGE_FW is not set -# CONFIG_MTD_SPLIT_ELF_FW is not set -# CONFIG_MTD_SPLIT_EVA_FW is not set -# CONFIG_MTD_SPLIT_FIRMWARE is not set -CONFIG_MTD_SPLIT_FIRMWARE_NAME="firmware" -# CONFIG_MTD_SPLIT_FIT_FW is not set -# CONFIG_MTD_SPLIT_H3C_VFS is not set -# CONFIG_MTD_SPLIT_JIMAGE_FW is not set -# CONFIG_MTD_SPLIT_LZMA_FW is not set -# CONFIG_MTD_SPLIT_MINOR_FW is not set -# CONFIG_MTD_SPLIT_SEAMA_FW is not set -CONFIG_MTD_SPLIT_SQUASHFS_ROOT=y -CONFIG_MTD_SPLIT_SUPPORT=y -# CONFIG_MTD_SPLIT_TPLINK_FW is not set -# CONFIG_MTD_SPLIT_TRX_FW is not set -# CONFIG_MTD_SPLIT_UIMAGE_FW is not set -# CONFIG_MTD_SPLIT_WRGG_FW is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SWAP is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_UBI is not set -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -# CONFIG_MTD_UIMAGE_SPLIT is not set -# CONFIG_MTD_VIRT_CONCAT is not set -# CONFIG_MTK_MMC is not set -# CONFIG_MTK_MMSYS is not set -# CONFIG_MTK_THERMAL is not set -# CONFIG_MULTIPLEXER is not set -CONFIG_MULTIUSER=y -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -# CONFIG_MUX_ADG792A is not set -# CONFIG_MUX_ADGS1408 is not set -# CONFIG_MUX_GPIO is not set -# CONFIG_MUX_MMIO is not set -# CONFIG_MV643XX_ETH is not set -# CONFIG_MVMDIO is not set -# CONFIG_MVNETA_BM is not set -# CONFIG_MVSW61XX_PHY is not set -# CONFIG_MV_XOR_V2 is not set -# CONFIG_MWAVE is not set -# CONFIG_MWL8K is not set -# CONFIG_MXC4005 is not set -# CONFIG_MXC6255 is not set -# CONFIG_MYRI10GE is not set -# CONFIG_NAMESPACES is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_NATSEMI is not set -# CONFIG_NAU7802 is not set -# CONFIG_NBPFAXI_DMA is not set -# CONFIG_NCP_FS is not set -# CONFIG_NE2000 is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NEC_MARKEINS is not set -CONFIG_NET=y -# CONFIG_NETCONSOLE is not set -CONFIG_NETDEVICES=y -# CONFIG_NETDEVSIM is not set -# CONFIG_NETFILTER is not set -# CONFIG_NETFILTER_ADVANCED is not set -# CONFIG_NETFILTER_DEBUG is not set -# CONFIG_NETFILTER_INGRESS is not set -# CONFIG_NETFILTER_NETLINK is not set -# CONFIG_NETFILTER_NETLINK_ACCT is not set -# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set -# CONFIG_NETFILTER_NETLINK_LOG is not set -# CONFIG_NETFILTER_NETLINK_OSF is not set -# CONFIG_NETFILTER_NETLINK_QUEUE is not set -# CONFIG_NETFILTER_XTABLES is not set -# CONFIG_NETFILTER_XT_CONNMARK is not set -# CONFIG_NETFILTER_XT_MARK is not set -# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set -# CONFIG_NETFILTER_XT_MATCH_BPF is not set -# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set -# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set -# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set -# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set -# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set -# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set -# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set -# CONFIG_NETFILTER_XT_MATCH_CPU is not set -# CONFIG_NETFILTER_XT_MATCH_DCCP is not set -# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set -# CONFIG_NETFILTER_XT_MATCH_DSCP is not set -# CONFIG_NETFILTER_XT_MATCH_ECN is not set -# CONFIG_NETFILTER_XT_MATCH_ESP is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set -# CONFIG_NETFILTER_XT_MATCH_HELPER is not set -# CONFIG_NETFILTER_XT_MATCH_HL is not set -# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set -# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set -# CONFIG_NETFILTER_XT_MATCH_L2TP is not set -# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set -# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set -# CONFIG_NETFILTER_XT_MATCH_MAC is not set -# CONFIG_NETFILTER_XT_MATCH_MARK is not set -# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set -# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set -# CONFIG_NETFILTER_XT_MATCH_OSF is not set -# CONFIG_NETFILTER_XT_MATCH_OWNER is not set -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set -# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set -# CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set -# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set -# CONFIG_NETFILTER_XT_MATCH_REALM is not set -# CONFIG_NETFILTER_XT_MATCH_RECENT is not set -# CONFIG_NETFILTER_XT_MATCH_SCTP is not set -# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set -# CONFIG_NETFILTER_XT_MATCH_STATE is not set -# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set -# CONFIG_NETFILTER_XT_MATCH_STRING is not set -# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set -# CONFIG_NETFILTER_XT_MATCH_TIME is not set -# CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set -# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set -# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set -# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set -# CONFIG_NETFILTER_XT_TARGET_CT is not set -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -# CONFIG_NETFILTER_XT_TARGET_HL is not set -# CONFIG_NETFILTER_XT_TARGET_HMARK is not set -# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set -# CONFIG_NETFILTER_XT_TARGET_LED is not set -# CONFIG_NETFILTER_XT_TARGET_LOG is not set -# CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set -# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set -# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set -# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set -# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set -# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set -# CONFIG_NETFILTER_XT_TARGET_TEE is not set -# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set -# CONFIG_NETLABEL is not set -# CONFIG_NETLINK_DIAG is not set -# CONFIG_NETLINK_MMAP is not set -# CONFIG_NETPOLL is not set -# CONFIG_NETROM is not set -CONFIG_NETWORK_FILESYSTEMS=y -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_NET_9P is not set -# CONFIG_NET_ACT_BPF is not set -# CONFIG_NET_ACT_CSUM is not set -# CONFIG_NET_ACT_CT is not set -# CONFIG_NET_ACT_GACT is not set -# CONFIG_NET_ACT_GATE is not set -# CONFIG_NET_ACT_IFE is not set -# CONFIG_NET_ACT_IPT is not set -# CONFIG_NET_ACT_MIRRED is not set -# CONFIG_NET_ACT_MPLS is not set -# CONFIG_NET_ACT_NAT is not set -# CONFIG_NET_ACT_PEDIT is not set -# CONFIG_NET_ACT_POLICE is not set -# CONFIG_NET_ACT_SAMPLE is not set -# CONFIG_NET_ACT_SIMP is not set -# CONFIG_NET_ACT_SKBEDIT is not set -# CONFIG_NET_ACT_SKBMOD is not set -# CONFIG_NET_ACT_TUNNEL_KEY is not set -# CONFIG_NET_ACT_VLAN is not set -CONFIG_NET_CADENCE=y -# CONFIG_NET_CALXEDA_XGMAC is not set -CONFIG_NET_CLS=y -# CONFIG_NET_CLS_ACT is not set -# CONFIG_NET_CLS_BASIC is not set -# CONFIG_NET_CLS_BPF is not set -# CONFIG_NET_CLS_FLOW is not set -# CONFIG_NET_CLS_FLOWER is not set -# CONFIG_NET_CLS_FW is not set -CONFIG_NET_CLS_IND=y -# CONFIG_NET_CLS_MATCHALL is not set -# CONFIG_NET_CLS_ROUTE4 is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set -# CONFIG_NET_CLS_U32 is not set -CONFIG_NET_CORE=y -# CONFIG_NET_DEVLINK is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_NET_DSA is not set -# CONFIG_NET_DSA_AR9331 is not set -# CONFIG_NET_DSA_BCM_SF2 is not set -# CONFIG_NET_DSA_LANTIQ_GSWIP is not set -# CONFIG_NET_DSA_LEGACY is not set -# CONFIG_NET_DSA_LOOP is not set -# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set -# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set -# CONFIG_NET_DSA_MSCC_FELIX is not set -# CONFIG_NET_DSA_MSCC_SEVILLE is not set -# CONFIG_NET_DSA_MT7530 is not set -# CONFIG_NET_DSA_MV88E6060 is not set -# CONFIG_NET_DSA_MV88E6123_61_65 is not set -# CONFIG_NET_DSA_MV88E6131 is not set -# CONFIG_NET_DSA_MV88E6171 is not set -# CONFIG_NET_DSA_MV88E6352 is not set -# CONFIG_NET_DSA_MV88E6XXX is not set -# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set -# CONFIG_NET_DSA_MV88E6XXX_PTP is not set -# CONFIG_NET_DSA_QCA8K is not set -# CONFIG_NET_DSA_REALTEK_SMI is not set -# CONFIG_NET_DSA_SJA1105 is not set -# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set -# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set -# CONFIG_NET_DSA_TAG_8021Q is not set -# CONFIG_NET_DSA_TAG_AR9331 is not set -# CONFIG_NET_DSA_TAG_BRCM is not set -# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set -# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set -# CONFIG_NET_DSA_TAG_DSA is not set -# CONFIG_NET_DSA_TAG_EDSA is not set -# CONFIG_NET_DSA_TAG_GSWIP is not set -# CONFIG_NET_DSA_TAG_KSZ is not set -# CONFIG_NET_DSA_TAG_LAN9303 is not set -# CONFIG_NET_DSA_TAG_MTK is not set -# CONFIG_NET_DSA_TAG_OCELOT is not set -# CONFIG_NET_DSA_TAG_QCA is not set -# CONFIG_NET_DSA_TAG_RTL4_A is not set -# CONFIG_NET_DSA_TAG_SJA1105 is not set -# CONFIG_NET_DSA_TAG_TRAILER is not set -# CONFIG_NET_DSA_VITESSE_VSC73XX is not set -# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set -# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_EMATCH_CANID is not set -# CONFIG_NET_EMATCH_CMP is not set -# CONFIG_NET_EMATCH_IPT is not set -# CONFIG_NET_EMATCH_META is not set -# CONFIG_NET_EMATCH_NBYTE is not set -CONFIG_NET_EMATCH_STACK=32 -# CONFIG_NET_EMATCH_TEXT is not set -# CONFIG_NET_EMATCH_U32 is not set -# CONFIG_NET_FAILOVER is not set -# CONFIG_NET_FC is not set -# CONFIG_NET_FOU is not set -# CONFIG_NET_FOU_IP_TUNNELS is not set -# CONFIG_NET_IFE is not set -# CONFIG_NET_IPGRE is not set -CONFIG_NET_IPGRE_BROADCAST=y -# CONFIG_NET_IPGRE_DEMUX is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPVTI is not set -# CONFIG_NET_IP_TUNNEL is not set -# CONFIG_NET_KEY is not set -# CONFIG_NET_KEY_MIGRATE is not set -# CONFIG_NET_L3_MASTER_DEV is not set -# CONFIG_NET_MEDIATEK_STAR_EMAC is not set -# CONFIG_NET_MPLS_GSO is not set -# CONFIG_NET_NCSI is not set -# CONFIG_NET_NSH is not set -# CONFIG_NET_PACKET_ENGINE is not set -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_NET_PTP_CLASSIFY is not set -CONFIG_NET_RX_BUSY_POLL=y -# CONFIG_NET_SB1000 is not set -CONFIG_NET_SCHED=y -# CONFIG_NET_SCH_ATM is not set -# CONFIG_NET_SCH_CAKE is not set -# CONFIG_NET_SCH_CBQ is not set -# CONFIG_NET_SCH_CBS is not set -# CONFIG_NET_SCH_CHOKE is not set -# CONFIG_NET_SCH_CODEL is not set -CONFIG_NET_SCH_DEFAULT=y -# CONFIG_NET_SCH_DRR is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_ETF is not set -# CONFIG_NET_SCH_ETS is not set -CONFIG_NET_SCH_FIFO=y -# CONFIG_NET_SCH_FQ is not set -CONFIG_NET_SCH_FQ_CODEL=y -# CONFIG_NET_SCH_FQ_PIE is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_HHF is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_INGRESS is not set -# CONFIG_NET_SCH_MQPRIO is not set -# CONFIG_NET_SCH_MULTIQ is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_SCH_PIE is not set -# CONFIG_NET_SCH_PLUG is not set -# CONFIG_NET_SCH_PRIO is not set -# CONFIG_NET_SCH_QFQ is not set -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_SFB is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_SKBPRIO is not set -# CONFIG_NET_SCH_TAPRIO is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_SCTPPROBE is not set -# CONFIG_NET_SWITCHDEV is not set -# CONFIG_NET_TCPPROBE is not set -# CONFIG_NET_TC_SKB_EXT is not set -# CONFIG_NET_TEAM is not set -# CONFIG_NET_TULIP is not set -# CONFIG_NET_UDP_TUNNEL is not set -CONFIG_NET_VENDOR_3COM=y -CONFIG_NET_VENDOR_8390=y -CONFIG_NET_VENDOR_ADAPTEC=y -CONFIG_NET_VENDOR_AGERE=y -CONFIG_NET_VENDOR_ALACRITECH=y -CONFIG_NET_VENDOR_ALTEON=y -CONFIG_NET_VENDOR_AMAZON=y -CONFIG_NET_VENDOR_AMD=y -CONFIG_NET_VENDOR_AQUANTIA=y -CONFIG_NET_VENDOR_ARC=y -CONFIG_NET_VENDOR_ATHEROS=y -CONFIG_NET_VENDOR_AURORA=y -CONFIG_NET_VENDOR_BROADCOM=y -CONFIG_NET_VENDOR_BROCADE=y -CONFIG_NET_VENDOR_CADENCE=y -CONFIG_NET_VENDOR_CAVIUM=y -CONFIG_NET_VENDOR_CHELSIO=y -CONFIG_NET_VENDOR_CIRRUS=y -CONFIG_NET_VENDOR_CISCO=y -CONFIG_NET_VENDOR_CORTINA=y -CONFIG_NET_VENDOR_DEC=y -CONFIG_NET_VENDOR_DLINK=y -CONFIG_NET_VENDOR_EMULEX=y -CONFIG_NET_VENDOR_EXAR=y -CONFIG_NET_VENDOR_EZCHIP=y -CONFIG_NET_VENDOR_FARADAY=y -CONFIG_NET_VENDOR_FREESCALE=y -CONFIG_NET_VENDOR_FUJITSU=y -CONFIG_NET_VENDOR_GOOGLE=y -CONFIG_NET_VENDOR_HISILICON=y -CONFIG_NET_VENDOR_HP=y -CONFIG_NET_VENDOR_HUAWEI=y -CONFIG_NET_VENDOR_I825XX=y -CONFIG_NET_VENDOR_IBM=y -CONFIG_NET_VENDOR_INTEL=y -CONFIG_NET_VENDOR_MARVELL=y -CONFIG_NET_VENDOR_MELLANOX=y -CONFIG_NET_VENDOR_MICREL=y -CONFIG_NET_VENDOR_MICROCHIP=y -CONFIG_NET_VENDOR_MICROSEMI=y -CONFIG_NET_VENDOR_MYRI=y -CONFIG_NET_VENDOR_NATSEMI=y -CONFIG_NET_VENDOR_NETERION=y -CONFIG_NET_VENDOR_NETRONOME=y -CONFIG_NET_VENDOR_NI=y -CONFIG_NET_VENDOR_NVIDIA=y -CONFIG_NET_VENDOR_OKI=y -CONFIG_NET_VENDOR_PACKET_ENGINES=y -CONFIG_NET_VENDOR_PENSANDO=y -CONFIG_NET_VENDOR_QLOGIC=y -CONFIG_NET_VENDOR_QUALCOMM=y -CONFIG_NET_VENDOR_RDC=y -CONFIG_NET_VENDOR_REALTEK=y -CONFIG_NET_VENDOR_RENESAS=y -CONFIG_NET_VENDOR_ROCKER=y -CONFIG_NET_VENDOR_SAMSUNG=y -CONFIG_NET_VENDOR_SEEQ=y -CONFIG_NET_VENDOR_SILAN=y -CONFIG_NET_VENDOR_SIS=y -CONFIG_NET_VENDOR_SMSC=y -CONFIG_NET_VENDOR_SOCIONEXT=y -CONFIG_NET_VENDOR_SOLARFLARE=y -CONFIG_NET_VENDOR_STMICRO=y -CONFIG_NET_VENDOR_SUN=y -CONFIG_NET_VENDOR_SYNOPSYS=y -CONFIG_NET_VENDOR_TEHUTI=y -CONFIG_NET_VENDOR_TI=y -CONFIG_NET_VENDOR_TOSHIBA=y -CONFIG_NET_VENDOR_VIA=y -CONFIG_NET_VENDOR_WIZNET=y -CONFIG_NET_VENDOR_XILINX=y -CONFIG_NET_VENDOR_XIRCOM=y -# CONFIG_NET_VRF is not set -# CONFIG_NET_XGENE is not set -CONFIG_NEW_LEDS=y -# CONFIG_NFC is not set -# CONFIG_NFP is not set -# CONFIG_NFSD is not set -# CONFIG_NFSD_V2_ACL is not set -CONFIG_NFSD_V3=y -# CONFIG_NFSD_V3_ACL is not set -# CONFIG_NFSD_V4 is not set -# CONFIG_NFS_ACL_SUPPORT is not set -CONFIG_NFS_COMMON=y -# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set -# CONFIG_NFS_FS is not set -# CONFIG_NFS_FSCACHE is not set -# CONFIG_NFS_SWAP is not set -# CONFIG_NFS_V2 is not set -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_V4_1 is not set -# CONFIG_NFTL is not set -# CONFIG_NFT_BRIDGE_META is not set -# CONFIG_NFT_BRIDGE_REJECT is not set -# CONFIG_NFT_CONNLIMIT is not set -# CONFIG_NFT_DUP_IPV4 is not set -# CONFIG_NFT_DUP_IPV6 is not set -# CONFIG_NFT_FIB_IPV4 is not set -# CONFIG_NFT_FIB_IPV6 is not set -# CONFIG_NFT_FIB_NETDEV is not set -# CONFIG_NFT_FLOW_OFFLOAD is not set -# CONFIG_NFT_OBJREF is not set -# CONFIG_NFT_OSF is not set -# CONFIG_NFT_RT is not set -# CONFIG_NFT_SET_BITMAP is not set -# CONFIG_NFT_SOCKET is not set -# CONFIG_NFT_SYNPROXY is not set -# CONFIG_NFT_TPROXY is not set -# CONFIG_NFT_TUNNEL is not set -# CONFIG_NFT_XFRM is not set -# CONFIG_NF_CONNTRACK is not set -# CONFIG_NF_CONNTRACK_AMANDA is not set -# CONFIG_NF_CONNTRACK_BRIDGE is not set -# CONFIG_NF_CONNTRACK_EVENTS is not set -# CONFIG_NF_CONNTRACK_FTP is not set -# CONFIG_NF_CONNTRACK_H323 is not set -# CONFIG_NF_CONNTRACK_IRC is not set -# CONFIG_NF_CONNTRACK_LABELS is not set -# CONFIG_NF_CONNTRACK_MARK is not set -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -# CONFIG_NF_CONNTRACK_PPTP is not set -CONFIG_NF_CONNTRACK_PROCFS=y -# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set -# CONFIG_NF_CONNTRACK_SANE is not set -# CONFIG_NF_CONNTRACK_SECMARK is not set -# CONFIG_NF_CONNTRACK_SIP is not set -# CONFIG_NF_CONNTRACK_SNMP is not set -# CONFIG_NF_CONNTRACK_TFTP is not set -# CONFIG_NF_CONNTRACK_TIMEOUT is not set -# CONFIG_NF_CONNTRACK_TIMESTAMP is not set -# CONFIG_NF_CONNTRACK_ZONES is not set -# CONFIG_NF_CT_NETLINK is not set -# CONFIG_NF_CT_NETLINK_HELPER is not set -# CONFIG_NF_CT_NETLINK_TIMEOUT is not set -# CONFIG_NF_CT_PROTO_DCCP is not set -# CONFIG_NF_CT_PROTO_GRE is not set -# CONFIG_NF_CT_PROTO_SCTP is not set -# CONFIG_NF_CT_PROTO_UDPLITE is not set -# CONFIG_NF_DEFRAG_IPV4 is not set -# CONFIG_NF_DUP_IPV4 is not set -# CONFIG_NF_DUP_IPV6 is not set -# CONFIG_NF_FLOW_TABLE is not set -# CONFIG_NF_LOG_ARP is not set -# CONFIG_NF_LOG_BRIDGE is not set -# CONFIG_NF_LOG_IPV4 is not set -# CONFIG_NF_LOG_NETDEV is not set -# CONFIG_NF_NAT is not set -# CONFIG_NF_NAT_AMANDA is not set -# CONFIG_NF_NAT_FTP is not set -# CONFIG_NF_NAT_H323 is not set -# CONFIG_NF_NAT_IRC is not set -# CONFIG_NF_NAT_NEEDED is not set -# CONFIG_NF_NAT_PPTP is not set -# CONFIG_NF_NAT_PROTO_GRE is not set -# CONFIG_NF_NAT_SIP is not set -# CONFIG_NF_NAT_SNMP_BASIC is not set -# CONFIG_NF_NAT_TFTP is not set -# CONFIG_NF_REJECT_IPV4 is not set -# CONFIG_NF_REJECT_IPV6 is not set -# CONFIG_NF_SOCKET_IPV4 is not set -# CONFIG_NF_SOCKET_IPV6 is not set -# CONFIG_NF_TABLES is not set -CONFIG_NF_TABLES_ARP=y -CONFIG_NF_TABLES_BRIDGE=y -CONFIG_NF_TABLES_INET=y -CONFIG_NF_TABLES_IPV4=y -CONFIG_NF_TABLES_IPV6=y -CONFIG_NF_TABLES_NETDEV=y -# CONFIG_NF_TABLES_SET is not set -# CONFIG_NF_TPROXY_IPV4 is not set -# CONFIG_NF_TPROXY_IPV6 is not set -# CONFIG_NI65 is not set -# CONFIG_NI903X_WDT is not set -# CONFIG_NIC7018_WDT is not set -# CONFIG_NILFS2_FS is not set -# CONFIG_NIU is not set -# CONFIG_NI_XGE_MANAGEMENT_ENET is not set -CONFIG_NLATTR=y -# CONFIG_NLMON is not set -# CONFIG_NLM_XLP_BOARD is not set -# CONFIG_NLM_XLR_BOARD is not set -# CONFIG_NLS is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_MAC_CELTIC is not set -# CONFIG_NLS_MAC_CENTEURO is not set -# CONFIG_NLS_MAC_CROATIAN is not set -# CONFIG_NLS_MAC_CYRILLIC is not set -# CONFIG_NLS_MAC_GAELIC is not set -# CONFIG_NLS_MAC_GREEK is not set -# CONFIG_NLS_MAC_ICELAND is not set -# CONFIG_NLS_MAC_INUIT is not set -# CONFIG_NLS_MAC_ROMAN is not set -# CONFIG_NLS_MAC_ROMANIAN is not set -# CONFIG_NLS_MAC_TURKISH is not set -# CONFIG_NLS_UTF8 is not set -CONFIG_NMI_LOG_BUF_SHIFT=13 -# CONFIG_NOA1305 is not set -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_NORTEL_HERMES is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set -# CONFIG_NOZOMI is not set -# CONFIG_NO_BOOTMEM is not set -# CONFIG_NO_HZ is not set -# CONFIG_NO_HZ_FULL is not set -# CONFIG_NO_HZ_IDLE is not set -# CONFIG_NS83820 is not set -# CONFIG_NTB is not set -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_FS is not set -# CONFIG_NTFS_RW is not set -# CONFIG_NTP_PPS is not set -# CONFIG_NULL_TTY is not set -# CONFIG_NUMA is not set -# CONFIG_NVM is not set -# CONFIG_NVMEM is not set -# CONFIG_NVMEM_BCM_OCOTP is not set -# CONFIG_NVMEM_IMX_OCOTP is not set -# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set -# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set -# CONFIG_NVMEM_REBOOT_MODE is not set -# CONFIG_NVMEM_RMEM is not set -# CONFIG_NVMEM_SYSFS is not set -# CONFIG_NVMEM_U_BOOT_ENV is not set -# CONFIG_NVME_FC is not set -# CONFIG_NVME_TARGET is not set -# CONFIG_NVME_TCP is not set -# CONFIG_NVRAM is not set -# CONFIG_NV_TCO is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -# CONFIG_NXP_TJA11XX_PHY is not set -# CONFIG_N_GSM is not set -# CONFIG_OABI_COMPAT is not set -# CONFIG_OBS600 is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_OCTEONTX2_AF is not set -# CONFIG_OCTEONTX2_PF is not set -# CONFIG_OF_OVERLAY is not set -CONFIG_OF_RESERVED_MEM=y -# CONFIG_OF_UNITTEST is not set -# CONFIG_OID_REGISTRY is not set -# CONFIG_OMAP2_DSS_DEBUG is not set -# CONFIG_OMAP2_DSS_DEBUGFS is not set -# CONFIG_OMAP2_DSS_SDI is not set -# CONFIG_OMAP_OCP2SCP is not set -# CONFIG_OMAP_USB2 is not set -# CONFIG_OMFS_FS is not set -# CONFIG_OPENVSWITCH is not set -# CONFIG_OPROFILE is not set -# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set -# CONFIG_OPT3001 is not set -CONFIG_OPTIMIZE_INLINING=y -# CONFIG_ORANGEFS_FS is not set -# CONFIG_ORION_WATCHDOG is not set -# CONFIG_OSF_PARTITION is not set -CONFIG_OVERLAY_FS=y -# CONFIG_OVERLAY_FS_INDEX is not set -# CONFIG_OVERLAY_FS_METACOPY is not set -CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y -# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set -CONFIG_OVERLAY_FS_XINO_AUTO=y -# CONFIG_OWL_LOADER is not set -# CONFIG_P54_COMMON is not set -# CONFIG_PA12203001 is not set -CONFIG_PACKET=y -# CONFIG_PACKET_DIAG is not set -# CONFIG_PACKING is not set -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_PAGE_OWNER is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_PAGE_POOL is not set -# CONFIG_PAGE_REPORTING is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_32KB is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_64KB is not set -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PALMAS_GPADC is not set -# CONFIG_PANASONIC_LAPTOP is not set -# CONFIG_PANEL is not set -CONFIG_PANIC_ON_OOPS=y -CONFIG_PANIC_ON_OOPS_VALUE=1 -CONFIG_PANIC_TIMEOUT=1 -# CONFIG_PANTHERLORD_FF is not set -# CONFIG_PARAVIRT is not set -# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set -# CONFIG_PARPORT is not set -# CONFIG_PARPORT_1284 is not set -# CONFIG_PARPORT_AX88796 is not set -# CONFIG_PARPORT_GSC is not set -# CONFIG_PARPORT_PC is not set -CONFIG_PARTITION_ADVANCED=y -# CONFIG_PATA_ALI is not set -# CONFIG_PATA_AMD is not set -# CONFIG_PATA_ARASAN_CF is not set -# CONFIG_PATA_ARTOP is not set -# CONFIG_PATA_ATIIXP is not set -# CONFIG_PATA_ATP867X is not set -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CS5520 is not set -# CONFIG_PATA_CS5530 is not set -# CONFIG_PATA_CS5535 is not set -# CONFIG_PATA_CS5536 is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IMX is not set -# CONFIG_PATA_ISAPNP is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_LEGACY is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_NS87415 is not set -# CONFIG_PATA_OCTEON_CF is not set -# CONFIG_PATA_OF_PLATFORM is not set -# CONFIG_PATA_OLDPIIX is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_OPTIDMA is not set -# CONFIG_PATA_PCMCIA is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_PLATFORM is not set -# CONFIG_PATA_QDI is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RDC is not set -# CONFIG_PATA_RZ1000 is not set -# CONFIG_PATA_SC1200 is not set -# CONFIG_PATA_SCH is not set -# CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_TOSHIBA is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set -# CONFIG_PATA_WINBOND_VLB is not set -# CONFIG_PC104 is not set -# CONFIG_PC300TOO is not set -# CONFIG_PCCARD is not set -# CONFIG_PCH_DMA is not set -# CONFIG_PCH_GBE is not set -# CONFIG_PCH_PHUB is not set -# CONFIG_PCI is not set -# CONFIG_PCI200SYN is not set -# CONFIG_PCIEAER is not set -# CONFIG_PCIEAER_INJECT is not set -# CONFIG_PCIEASPM is not set -# CONFIG_PCIEPORTBUS is not set -# CONFIG_PCIE_AL is not set -# CONFIG_PCIE_ALTERA is not set -# CONFIG_PCIE_ARMADA_8K is not set -CONFIG_PCIE_BUS_DEFAULT=y -# CONFIG_PCIE_BUS_PEER2PEER is not set -# CONFIG_PCIE_BUS_PERFORMANCE is not set -# CONFIG_PCIE_BUS_SAFE is not set -# CONFIG_PCIE_BUS_TUNE_OFF is not set -# CONFIG_PCIE_BW is not set -# CONFIG_PCIE_CADENCE_HOST is not set -# CONFIG_PCIE_CADENCE_PLAT_HOST is not set -# CONFIG_PCIE_DPC is not set -# CONFIG_PCIE_DW_PLAT is not set -# CONFIG_PCIE_DW_PLAT_HOST is not set -# CONFIG_PCIE_ECRC is not set -# CONFIG_PCIE_IPROC is not set -# CONFIG_PCIE_KIRIN is not set -# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set -# CONFIG_PCIE_PTM is not set -# CONFIG_PCIE_XILINX is not set -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_PCI_ATMEL is not set -# CONFIG_PCI_CNB20LE_QUIRK is not set -# CONFIG_PCI_DEBUG is not set -# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set -# CONFIG_PCI_ENDPOINT is not set -# CONFIG_PCI_ENDPOINT_TEST is not set -# CONFIG_PCI_FTPCI100 is not set -# CONFIG_PCI_HERMES is not set -# CONFIG_PCI_HISI is not set -# CONFIG_PCI_HOST_GENERIC is not set -# CONFIG_PCI_HOST_THUNDER_ECAM is not set -# CONFIG_PCI_HOST_THUNDER_PEM is not set -# CONFIG_PCI_IOV is not set -# CONFIG_PCI_J721E_HOST is not set -# CONFIG_PCI_LAYERSCAPE is not set -# CONFIG_PCI_MESON is not set -# CONFIG_PCI_MSI is not set -# CONFIG_PCI_PASID is not set -# CONFIG_PCI_PF_STUB is not set -# CONFIG_PCI_PRI is not set -CONFIG_PCI_QUIRKS=y -# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set -# CONFIG_PCI_STUB is not set -# CONFIG_PCI_SW_SWITCHTEC is not set -CONFIG_PCI_SYSCALL=y -# CONFIG_PCI_V3_SEMI is not set -# CONFIG_PCI_XGENE is not set -# CONFIG_PCMCIA is not set -# CONFIG_PCMCIA_3C574 is not set -# CONFIG_PCMCIA_3C589 is not set -# CONFIG_PCMCIA_AHA152X is not set -# CONFIG_PCMCIA_ATMEL is not set -# CONFIG_PCMCIA_AXNET is not set -# CONFIG_PCMCIA_DEBUG is not set -# CONFIG_PCMCIA_FDOMAIN is not set -# CONFIG_PCMCIA_FMVJ18X is not set -# CONFIG_PCMCIA_HERMES is not set -# CONFIG_PCMCIA_LOAD_CIS is not set -# CONFIG_PCMCIA_NINJA_SCSI is not set -# CONFIG_PCMCIA_NMCLAN is not set -# CONFIG_PCMCIA_PCNET is not set -# CONFIG_PCMCIA_QLOGIC is not set -# CONFIG_PCMCIA_RAYCS is not set -# CONFIG_PCMCIA_SMC91C92 is not set -# CONFIG_PCMCIA_SPECTRUM is not set -# CONFIG_PCMCIA_SYM53C500 is not set -# CONFIG_PCMCIA_WL3501 is not set -# CONFIG_PCMCIA_XIRC2PS is not set -# CONFIG_PCMCIA_XIRCOM is not set -# CONFIG_PCNET32 is not set -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_PCS_XPCS is not set -# CONFIG_PD6729 is not set -# CONFIG_PDA_POWER is not set -# CONFIG_PDC_ADMA is not set -# CONFIG_PERCPU_STATS is not set -# CONFIG_PERCPU_TEST is not set -# CONFIG_PERF_EVENTS is not set -# CONFIG_PERF_EVENTS_AMD_POWER is not set -# CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_PHANTOM is not set -# CONFIG_PHONET is not set -# CONFIG_PHYLIB is not set -# CONFIG_PHYS_ADDR_T_64BIT is not set -# CONFIG_PHY_CADENCE_DP is not set -# CONFIG_PHY_CADENCE_DPHY is not set -# CONFIG_PHY_CADENCE_SALVO is not set -# CONFIG_PHY_CADENCE_SIERRA is not set -# CONFIG_PHY_CADENCE_TORRENT is not set -# CONFIG_PHY_CPCAP_USB is not set -# CONFIG_PHY_EXYNOS_DP_VIDEO is not set -# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set -# CONFIG_PHY_FSL_IMX8MQ_USB is not set -# CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set -# CONFIG_PHY_MAPPHONE_MDM6600 is not set -# CONFIG_PHY_MIXEL_MIPI_DPHY is not set -# CONFIG_PHY_MTK_HDMI is not set -# CONFIG_PHY_OCELOT_SERDES is not set -# CONFIG_PHY_PXA_28NM_HSIC is not set -# CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_QCOM_DWC3 is not set -# CONFIG_PHY_QCOM_USB_HS is not set -# CONFIG_PHY_QCOM_USB_HSIC is not set -# CONFIG_PHY_SAMSUNG_USB2 is not set -# CONFIG_PHY_TUSB1210 is not set -# CONFIG_PHY_XGENE is not set -# CONFIG_PI433 is not set -# CONFIG_PID_IN_CONTEXTIDR is not set -# CONFIG_PID_NS is not set -CONFIG_PINCONF=y -# CONFIG_PINCTRL is not set -# CONFIG_PINCTRL_AMD is not set -# CONFIG_PINCTRL_AXP209 is not set -# CONFIG_PINCTRL_CEDARFORK is not set -# CONFIG_PINCTRL_EXYNOS is not set -# CONFIG_PINCTRL_EXYNOS5440 is not set -# CONFIG_PINCTRL_ICELAKE is not set -# CONFIG_PINCTRL_INGENIC is not set -# CONFIG_PINCTRL_MCP23S08 is not set -# CONFIG_PINCTRL_MSM8X74 is not set -# CONFIG_PINCTRL_MT6779 is not set -# CONFIG_PINCTRL_MT8167 is not set -# CONFIG_PINCTRL_MT8192 is not set -# CONFIG_PINCTRL_MTK_V2 is not set -# CONFIG_PINCTRL_OCELOT is not set -CONFIG_PINCTRL_SINGLE=y -# CONFIG_PINCTRL_STMFX is not set -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PING is not set -CONFIG_PINMUX=y -# CONFIG_PKCS7_MESSAGE_PARSER is not set -# CONFIG_PL310_ERRATA_588369 is not set -# CONFIG_PL310_ERRATA_727915 is not set -# CONFIG_PL310_ERRATA_753970 is not set -# CONFIG_PL310_ERRATA_769419 is not set -# CONFIG_PL320_MBOX is not set -# CONFIG_PL330_DMA is not set -# CONFIG_PLATFORM_MHU is not set -# CONFIG_PLAT_SPEAR is not set -# CONFIG_PLIP is not set -# CONFIG_PLX_DMA is not set -# CONFIG_PLX_HERMES is not set -# CONFIG_PM is not set -# CONFIG_PMBUS is not set -# CONFIG_PMC_MSP is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMS7003 is not set -# CONFIG_PM_AUTOSLEEP is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_DEVFREQ is not set -# CONFIG_PM_WAKELOCKS is not set -# CONFIG_POSIX_MQUEUE is not set -CONFIG_POSIX_TIMERS=y -# CONFIG_POWERCAP is not set -# CONFIG_POWER_AVS is not set -# CONFIG_POWER_RESET is not set -# CONFIG_POWER_RESET_BRCMKONA is not set -# CONFIG_POWER_RESET_BRCMSTB is not set -# CONFIG_POWER_RESET_GPIO is not set -# CONFIG_POWER_RESET_GPIO_RESTART is not set -# CONFIG_POWER_RESET_LINKSTATION is not set -# CONFIG_POWER_RESET_LTC2952 is not set -# CONFIG_POWER_RESET_PIIX4_POWEROFF is not set -# CONFIG_POWER_RESET_QNAP is not set -# CONFIG_POWER_RESET_RESTART is not set -# CONFIG_POWER_RESET_SYSCON is not set -# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set -# CONFIG_POWER_RESET_VERSATILE is not set -# CONFIG_POWER_RESET_XGENE is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_POWER_SUPPLY_HWMON is not set -# CONFIG_PPC4xx_GPIO is not set -# CONFIG_PPC_16K_PAGES is not set -# CONFIG_PPC_256K_PAGES is not set -CONFIG_PPC_4K_PAGES=y -# CONFIG_PPC_64K_PAGES is not set -# CONFIG_PPC_DISABLE_WERROR is not set -# CONFIG_PPC_EMULATED_STATS is not set -# CONFIG_PPC_EPAPR_HV_BYTECHAN is not set -# CONFIG_PPC_QUEUED_SPINLOCKS is not set -# CONFIG_PPP is not set -# CONFIG_PPPOATM is not set -# CONFIG_PPPOE is not set -# CONFIG_PPPOL2TP is not set -# CONFIG_PPP_ASYNC is not set -# CONFIG_PPP_BSDCOMP is not set -# CONFIG_PPP_DEFLATE is not set -CONFIG_PPP_FILTER=y -# CONFIG_PPP_MPPE is not set -CONFIG_PPP_MULTILINK=y -# CONFIG_PPP_SYNC_TTY is not set -# CONFIG_PPS is not set -# CONFIG_PPS_CLIENT_GPIO is not set -# CONFIG_PPS_CLIENT_KTIMER is not set -# CONFIG_PPS_CLIENT_LDISC is not set -# CONFIG_PPS_CLIENT_PARPORT is not set -# CONFIG_PPS_DEBUG is not set -# CONFIG_PPTP is not set -# CONFIG_PREEMPT is not set -# CONFIG_PREEMPTIRQ_DELAY_TEST is not set -# CONFIG_PREEMPTIRQ_EVENTS is not set -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PRESTERA is not set -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_PRIME_NUMBERS is not set -CONFIG_PRINTK=y -# CONFIG_PRINTK_CALLER is not set -CONFIG_PRINTK_NMI=y -CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 -# CONFIG_PRINTK_TIME is not set -CONFIG_PRINT_STACK_DEPTH=64 -# CONFIG_PRISM2_USB is not set -# CONFIG_PRISM54 is not set -# CONFIG_PROC_CHILDREN is not set -CONFIG_PROC_FS=y -# CONFIG_PROC_KCORE is not set -# CONFIG_PROC_PAGE_MONITOR is not set -# CONFIG_PROC_STRIPPED is not set -CONFIG_PROC_SYSCTL=y -# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILING is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_PROVE_RAW_LOCK_NESTING is not set -# CONFIG_PROVE_RCU is not set -# CONFIG_PROVE_RCU_LIST is not set -# CONFIG_PROVE_RCU_REPEATEDLY is not set -# CONFIG_PSAMPLE is not set -# CONFIG_PSB6970_PHY is not set -# CONFIG_PSI is not set -# CONFIG_PSTORE is not set -# CONFIG_PSTORE_842_COMPRESS is not set -# CONFIG_PSTORE_COMPRESS is not set -# CONFIG_PSTORE_COMPRESS_DEFAULT is not set -# CONFIG_PSTORE_CONSOLE is not set -# CONFIG_PSTORE_DEFLATE_COMPRESS is not set -# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set -# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -# CONFIG_PSTORE_LZO_COMPRESS is not set -# CONFIG_PSTORE_PMSG is not set -# CONFIG_PSTORE_RAM is not set -# CONFIG_PSTORE_ZSTD_COMPRESS is not set -# CONFIG_PTDUMP_DEBUGFS is not set -# CONFIG_PTP_1588_CLOCK is not set -# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set -# CONFIG_PTP_1588_CLOCK_IDTCM is not set -# CONFIG_PTP_1588_CLOCK_IXP46X is not set -# CONFIG_PTP_1588_CLOCK_KVM is not set -# CONFIG_PTP_1588_CLOCK_PCH is not set -# CONFIG_PTP_1588_CLOCK_VMW is not set -# CONFIG_PUBLIC_KEY_ALGO_RSA is not set -# CONFIG_PVPANIC is not set -# CONFIG_PWM is not set -# CONFIG_PWM_DEBUG is not set -# CONFIG_PWM_FSL_FTM is not set -# CONFIG_PWM_IMG is not set -# CONFIG_PWM_JZ4740 is not set -# CONFIG_PWM_MEDIATEK is not set -# CONFIG_PWM_PCA9685 is not set -CONFIG_PWRSEQ_EMMC=y -# CONFIG_PWRSEQ_SD8787 is not set -CONFIG_PWRSEQ_SIMPLE=y -# CONFIG_QCA7000 is not set -# CONFIG_QCA7000_SPI is not set -# CONFIG_QCA7000_UART is not set -# CONFIG_QCOM_EMAC is not set -# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set -# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set -# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set -# CONFIG_QCOM_HIDMA is not set -# CONFIG_QCOM_HIDMA_MGMT is not set -# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set -# CONFIG_QCOM_SPMI_ADC5 is not set -# CONFIG_QCOM_SPMI_IADC is not set -# CONFIG_QCOM_SPMI_TEMP_ALARM is not set -# CONFIG_QCOM_SPMI_VADC is not set -# CONFIG_QED is not set -# CONFIG_QLA3XXX is not set -# CONFIG_QLCNIC is not set -# CONFIG_QLGE is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX6FS_FS is not set -# CONFIG_QORIQ_CPUFREQ is not set -# CONFIG_QORIQ_THERMAL is not set -# CONFIG_QRTR is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_QUEUED_LOCK_STAT is not set -# CONFIG_QUICC_ENGINE is not set -# CONFIG_QUOTA is not set -# CONFIG_QUOTACTL is not set -# CONFIG_QUOTA_DEBUG is not set -# CONFIG_R3964 is not set -# CONFIG_R6040 is not set -# CONFIG_R8169 is not set -# CONFIG_R8188EU is not set -# CONFIG_R8712U is not set -# CONFIG_R8723AU is not set -# CONFIG_RADIO_ADAPTERS is not set -# CONFIG_RADIO_AZTECH is not set -# CONFIG_RADIO_CADET is not set -# CONFIG_RADIO_GEMTEK is not set -# CONFIG_RADIO_MAXIRADIO is not set -# CONFIG_RADIO_RTRACK is not set -# CONFIG_RADIO_RTRACK2 is not set -# CONFIG_RADIO_SF16FMI is not set -# CONFIG_RADIO_SF16FMR2 is not set -# CONFIG_RADIO_TERRATEC is not set -# CONFIG_RADIO_TRUST is not set -# CONFIG_RADIO_TYPHOON is not set -# CONFIG_RADIO_ZOLTRIX is not set -# CONFIG_RAID6_PQ_BENCHMARK is not set -# CONFIG_RAID_ATTRS is not set -# CONFIG_RALINK is not set -# CONFIG_RANDOM32_SELFTEST is not set -# CONFIG_RANDOMIZE_BASE is not set -CONFIG_RANDOM_TRUST_BOOTLOADER=y -CONFIG_RANDOM_TRUST_CPU=y -# CONFIG_RAPIDIO is not set -# CONFIG_RAS is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_RBTREE_TEST is not set -# CONFIG_RCU_BOOST is not set -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -# CONFIG_RCU_EQS_DEBUG is not set -# CONFIG_RCU_EXPEDITE_BOOT is not set -# CONFIG_RCU_EXPERT is not set -CONFIG_RCU_KTHREAD_PRIO=0 -CONFIG_RCU_NEED_SEGCBLIST=y -# CONFIG_RCU_PERF_TEST is not set -# CONFIG_RCU_REF_SCALE_TEST is not set -# CONFIG_RCU_SCALE_TEST is not set -CONFIG_RCU_STALL_COMMON=y -# CONFIG_RCU_STRICT_GRACE_PERIOD is not set -# CONFIG_RCU_TORTURE_TEST is not set -CONFIG_RCU_TORTURE_TEST_SLOW_INIT_DELAY=3 -# CONFIG_RCU_TRACE is not set -# CONFIG_RC_ATI_REMOTE is not set -# CONFIG_RC_CORE is not set -# CONFIG_RC_DECODERS is not set -# CONFIG_RC_LOOPBACK is not set -# CONFIG_RC_MAP is not set -# CONFIG_RC_XBOX_DVD is not set -# CONFIG_RDS is not set -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_GZIP is not set -# CONFIG_RD_LZ4 is not set -# CONFIG_RD_LZMA is not set -# CONFIG_RD_LZO is not set -# CONFIG_RD_XZ is not set -# CONFIG_RD_ZSTD is not set -# CONFIG_READABLE_ASM is not set -# CONFIG_READ_ONLY_THP_FOR_FS is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_REDWOOD is not set -# CONFIG_REED_SOLOMON is not set -# CONFIG_REED_SOLOMON_DEC8 is not set -# CONFIG_REED_SOLOMON_ENC8 is not set -# CONFIG_REED_SOLOMON_TEST is not set -# CONFIG_REGMAP is not set -# CONFIG_REGMAP_I2C is not set -# CONFIG_REGMAP_MMIO is not set -# CONFIG_REGMAP_SPI is not set -# CONFIG_REGULATOR is not set -# CONFIG_REGULATOR_88PG86X is not set -# CONFIG_REGULATOR_ACT8865 is not set -# CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_ANATOP is not set -# CONFIG_REGULATOR_DA9210 is not set -# CONFIG_REGULATOR_DA9211 is not set -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FAN53555 is not set -# CONFIG_REGULATOR_FAN53880 is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_GPIO is not set -# CONFIG_REGULATOR_ISL6271A is not set -# CONFIG_REGULATOR_ISL9305 is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_LP3972 is not set -# CONFIG_REGULATOR_LP872X is not set -# CONFIG_REGULATOR_LP8755 is not set -# CONFIG_REGULATOR_LTC3589 is not set -# CONFIG_REGULATOR_LTC3676 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_MAX77620 is not set -# CONFIG_REGULATOR_MAX77826 is not set -# CONFIG_REGULATOR_MAX8649 is not set -# CONFIG_REGULATOR_MAX8660 is not set -# CONFIG_REGULATOR_MAX8952 is not set -# CONFIG_REGULATOR_MAX8973 is not set -# CONFIG_REGULATOR_MCP16502 is not set -# CONFIG_REGULATOR_MP5416 is not set -# CONFIG_REGULATOR_MP8859 is not set -# CONFIG_REGULATOR_MP886X is not set -# CONFIG_REGULATOR_MPQ7920 is not set -# CONFIG_REGULATOR_MT6311 is not set -# CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PFUZE100 is not set -# CONFIG_REGULATOR_PV88060 is not set -# CONFIG_REGULATOR_PV88080 is not set -# CONFIG_REGULATOR_PV88090 is not set -# CONFIG_REGULATOR_PWM is not set -# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set -# CONFIG_REGULATOR_RT4801 is not set -# CONFIG_REGULATOR_RTMV20 is not set -# CONFIG_REGULATOR_SLG51000 is not set -# CONFIG_REGULATOR_SY8106A is not set -# CONFIG_REGULATOR_SY8824X is not set -# CONFIG_REGULATOR_SY8827N is not set -# CONFIG_REGULATOR_TI_ABB is not set -# CONFIG_REGULATOR_TPS51632 is not set -# CONFIG_REGULATOR_TPS62360 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -# CONFIG_REGULATOR_TPS65132 is not set -# CONFIG_REGULATOR_TPS6524X is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_VCTRL is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_REISERFS_FS_POSIX_ACL is not set -# CONFIG_REISERFS_FS_SECURITY is not set -CONFIG_REISERFS_FS_XATTR=y -# CONFIG_REISERFS_PROC_INFO is not set -# CONFIG_RELAY is not set -# CONFIG_RELOCATABLE is not set -# CONFIG_REMOTEPROC is not set -# CONFIG_RENESAS_PHY is not set -# CONFIG_RESET_ATH79 is not set -# CONFIG_RESET_BERLIN is not set -# CONFIG_RESET_BRCMSTB_RESCAL is not set -# CONFIG_RESET_CONTROLLER is not set -# CONFIG_RESET_IMX7 is not set -# CONFIG_RESET_INTEL_GW is not set -# CONFIG_RESET_LANTIQ is not set -# CONFIG_RESET_LPC18XX is not set -# CONFIG_RESET_MESON is not set -# CONFIG_RESET_PISTACHIO is not set -# CONFIG_RESET_SOCFPGA is not set -# CONFIG_RESET_STM32 is not set -# CONFIG_RESET_SUNXI is not set -# CONFIG_RESET_TEGRA_BPMP is not set -# CONFIG_RESET_TI_SYSCON is not set -# CONFIG_RESET_ZYNQ is not set -# CONFIG_RFD77402 is not set -# CONFIG_RFD_FTL is not set -CONFIG_RFKILL=y -# CONFIG_RFKILL_FULL is not set -# CONFIG_RFKILL_GPIO is not set -# CONFIG_RFKILL_INPUT is not set -# CONFIG_RFKILL_LEDS is not set -# CONFIG_RFKILL_REGULATOR is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_RING_BUFFER_STARTUP_TEST is not set -# CONFIG_RMI4_CORE is not set -# CONFIG_RMNET is not set -# CONFIG_ROCKCHIP_PHY is not set -# CONFIG_ROCKER is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_ROSE is not set -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPMSG_QCOM_GLINK_RPM is not set -# CONFIG_RPMSG_VIRTIO is not set -# CONFIG_RPR0521 is not set -# CONFIG_RSEQ is not set -# CONFIG_RT2X00 is not set -# CONFIG_RTC_CLASS is not set -# CONFIG_RTC_DEBUG is not set -# CONFIG_RTC_DRV_ABB5ZES3 is not set -# CONFIG_RTC_DRV_ABEOZ9 is not set -# CONFIG_RTC_DRV_ABX80X is not set -# CONFIG_RTC_DRV_ARMADA38X is not set -# CONFIG_RTC_DRV_AU1XXX is not set -# CONFIG_RTC_DRV_BQ32K is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_CADENCE is not set -CONFIG_RTC_DRV_CMOS=y -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1302 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1307_CENTURY is not set -# CONFIG_RTC_DRV_DS1307_HWMON is not set -# CONFIG_RTC_DRV_DS1343 is not set -# CONFIG_RTC_DRV_DS1347 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_DS1685_FAMILY is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_DS2404 is not set -# CONFIG_RTC_DRV_DS3232 is not set -# CONFIG_RTC_DRV_DS3234 is not set -# CONFIG_RTC_DRV_EM3027 is not set -# CONFIG_RTC_DRV_EP93XX is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_FTRTC010 is not set -# CONFIG_RTC_DRV_GENERIC is not set -# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -# CONFIG_RTC_DRV_HYM8563 is not set -# CONFIG_RTC_DRV_ISL12022 is not set -# CONFIG_RTC_DRV_ISL12026 is not set -# CONFIG_RTC_DRV_ISL12057 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_JZ4740 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_M41T93 is not set -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_MAX6916 is not set -# CONFIG_RTC_DRV_MCP795 is not set -# CONFIG_RTC_DRV_MOXART is not set -# CONFIG_RTC_DRV_MPC5121 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_MT2712 is not set -# CONFIG_RTC_DRV_OMAP is not set -# CONFIG_RTC_DRV_PCF2123 is not set -# CONFIG_RTC_DRV_PCF2127 is not set -# CONFIG_RTC_DRV_PCF85063 is not set -# CONFIG_RTC_DRV_PCF8523 is not set -# CONFIG_RTC_DRV_PCF85363 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_PL030 is not set -# CONFIG_RTC_DRV_PL031 is not set -# CONFIG_RTC_DRV_PS3 is not set -# CONFIG_RTC_DRV_PT7C4338 is not set -# CONFIG_RTC_DRV_R7301 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_RTC7301 is not set -# CONFIG_RTC_DRV_RV3028 is not set -# CONFIG_RTC_DRV_RV3029C2 is not set -# CONFIG_RTC_DRV_RV3032 is not set -# CONFIG_RTC_DRV_RV8803 is not set -# CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set -# CONFIG_RTC_DRV_RX8010 is not set -# CONFIG_RTC_DRV_RX8025 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_SD3078 is not set -# CONFIG_RTC_DRV_SNVS is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_SUN6I is not set -# CONFIG_RTC_DRV_TEST is not set -# CONFIG_RTC_DRV_V3020 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_XGENE is not set -# CONFIG_RTC_DRV_ZYNQMP is not set -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_LIB=y -# CONFIG_RTC_NVMEM is not set -CONFIG_RTC_SYSTOHC=y -CONFIG_RTC_SYSTOHC_DEVICE="rtc0" -# CONFIG_RTL8180 is not set -# CONFIG_RTL8187 is not set -# CONFIG_RTL8192E is not set -# CONFIG_RTL8192U is not set -# CONFIG_RTL8306_PHY is not set -# CONFIG_RTL8366RB_PHY is not set -# CONFIG_RTL8366S_PHY is not set -# CONFIG_RTL8366_SMI is not set -# CONFIG_RTL8366_SMI_DEBUG_FS is not set -# CONFIG_RTL8367B_PHY is not set -# CONFIG_RTL8367_PHY is not set -# CONFIG_RTLLIB is not set -# CONFIG_RTL_CARDS is not set -# CONFIG_RTS5208 is not set -CONFIG_RT_MUTEXES=y -# CONFIG_RUNTIME_DEBUG is not set -CONFIG_RUNTIME_TESTING_MENU=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_RXKAD=y -# CONFIG_S2IO is not set -# CONFIG_SAMPLES is not set -# CONFIG_SAMSUNG_LAPTOP is not set -# CONFIG_SATA_ACARD_AHCI is not set -# CONFIG_SATA_AHCI is not set -# CONFIG_SATA_AHCI_PLATFORM is not set -# CONFIG_SATA_DWC is not set -# CONFIG_SATA_FSL is not set -# CONFIG_SATA_HIGHBANK is not set -# CONFIG_SATA_HOST is not set -# CONFIG_SATA_INIC162X is not set -CONFIG_SATA_MOBILE_LPM_POLICY=0 -# CONFIG_SATA_MV is not set -# CONFIG_SATA_NV is not set -# CONFIG_SATA_PMP is not set -# CONFIG_SATA_PROMISE is not set -# CONFIG_SATA_QSTOR is not set -# CONFIG_SATA_RCAR is not set -# CONFIG_SATA_SIL is not set -# CONFIG_SATA_SIL24 is not set -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_SVW is not set -# CONFIG_SATA_SX4 is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set -# CONFIG_SBC_FITPC2_WATCHDOG is not set -CONFIG_SBITMAP=y -# CONFIG_SC92031 is not set -# CONFIG_SCA3000 is not set -# CONFIG_SCACHE_DEBUGFS is not set -# CONFIG_SCC is not set -# CONFIG_SCD30_CORE is not set -# CONFIG_SCF_TORTURE_TEST is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_SCHED_AUTOGROUP is not set -# CONFIG_SCHED_DEBUG is not set -CONFIG_SCHED_HRTICK=y -# CONFIG_SCHED_MC is not set -CONFIG_SCHED_OMIT_FRAME_POINTER=y -# CONFIG_SCHED_SMT is not set -CONFIG_SCHED_STACK_END_CHECK=y -# CONFIG_SCHED_TRACER is not set -# CONFIG_SCR24X is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_3W_SAS is not set -# CONFIG_SCSI_7000FASST is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_AHA152X is not set -# CONFIG_SCSI_AHA1542 is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC94XX is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_SCSI_BFA_FC is not set -# CONFIG_SCSI_BNX2X_FCOE is not set -# CONFIG_SCSI_BNX2_ISCSI is not set -# CONFIG_SCSI_BUSLOGIC is not set -# CONFIG_SCSI_CHELSIO_FCOE is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_CXGB3_ISCSI is not set -# CONFIG_SCSI_CXGB4_ISCSI is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_DPT_I2O is not set -# CONFIG_SCSI_DTC3280 is not set -# CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_ESAS2R is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_FDOMAIN_PCI is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_GENERIC_NCR5380 is not set -# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set -# CONFIG_SCSI_HISI_SAS is not set -# CONFIG_SCSI_HPSA is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_IN2000 is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_ISCI is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_LOGGING is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set -# CONFIG_SCSI_LPFC is not set -CONFIG_SCSI_MOD=y -# CONFIG_SCSI_MPT2SAS is not set -# CONFIG_SCSI_MPT3SAS is not set -# CONFIG_SCSI_MQ_DEFAULT is not set -# CONFIG_SCSI_MVSAS is not set -# CONFIG_SCSI_MVSAS_DEBUG is not set -# CONFIG_SCSI_MVUMI is not set -# CONFIG_SCSI_MYRB is not set -# CONFIG_SCSI_MYRS is not set -# CONFIG_SCSI_NCR53C406A is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_SCSI_PAS16 is not set -# CONFIG_SCSI_PM8001 is not set -# CONFIG_SCSI_PMCRAID is not set -CONFIG_SCSI_PROC_FS=y -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLOGIC_FAS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -# CONFIG_SCSI_SMARTPQI is not set -# CONFIG_SCSI_SNIC is not set -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_STEX is not set -# CONFIG_SCSI_SYM53C416 is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_T128 is not set -# CONFIG_SCSI_U14_34F is not set -# CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_ULTRASTOR is not set -# CONFIG_SCSI_VIRTIO is not set -# CONFIG_SCSI_WD719X is not set -# CONFIG_SCx200_ACB is not set -# CONFIG_SDIO_UART is not set -# CONFIG_SDR_MAX2175 is not set -# CONFIG_SDR_PLATFORM_DRIVERS is not set -# CONFIG_SD_ADC_MODULATOR is not set -# CONFIG_SECCOMP is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_APPARMOR is not set -CONFIG_SECURITY_DMESG_RESTRICT=y -# CONFIG_SECURITY_LOADPIN is not set -# CONFIG_SECURITY_LOCKDOWN_LSM is not set -# CONFIG_SECURITY_NETWORK_XFRM is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_SAFESETID is not set -# CONFIG_SECURITY_SELINUX_AVC_STATS is not set -# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set -CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0 -# CONFIG_SECURITY_SELINUX_DEVELOP is not set -# CONFIG_SECURITY_SELINUX_DISABLE is not set -# CONFIG_SECURITY_SMACK is not set -# CONFIG_SECURITY_TOMOYO is not set -# CONFIG_SECURITY_YAMA is not set -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SENSORS_ABITUGURU is not set -# CONFIG_SENSORS_ABITUGURU3 is not set -# CONFIG_SENSORS_ACPI_POWER is not set -# CONFIG_SENSORS_AD7314 is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM1177 is not set -# CONFIG_SENSORS_ADM1266 is not set -# CONFIG_SENSORS_ADM1275 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADS1015 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_ADS7871 is not set -# CONFIG_SENSORS_ADT7310 is not set -# CONFIG_SENSORS_ADT7410 is not set -# CONFIG_SENSORS_ADT7411 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_AMC6821 is not set -# CONFIG_SENSORS_APDS990X is not set -# CONFIG_SENSORS_APPLESMC is not set -# CONFIG_SENSORS_AS370 is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ASC7621 is not set -# CONFIG_SENSORS_ASPEED is not set -# CONFIG_SENSORS_ATK0110 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_AXI_FAN_CONTROL is not set -# CONFIG_SENSORS_BEL_PFE is not set -# CONFIG_SENSORS_BH1770 is not set -# CONFIG_SENSORS_BH1780 is not set -# CONFIG_SENSORS_CORETEMP is not set -# CONFIG_SENSORS_CORSAIR_CPRO is not set -# CONFIG_SENSORS_DELL_SMM is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_DRIVETEMP is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_DS620 is not set -# CONFIG_SENSORS_EMC1403 is not set -# CONFIG_SENSORS_EMC2103 is not set -# CONFIG_SENSORS_EMC6W201 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_FAM15H_POWER is not set -# CONFIG_SENSORS_FSCHMD is not set -# CONFIG_SENSORS_FTSTEUTATES is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_G762 is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_GPIO_FAN is not set -# CONFIG_SENSORS_GSC is not set -# CONFIG_SENSORS_HDAPS is not set -# CONFIG_SENSORS_HIH6130 is not set -# CONFIG_SENSORS_HMC5843 is not set -# CONFIG_SENSORS_HMC5843_I2C is not set -# CONFIG_SENSORS_HMC5843_SPI is not set -# CONFIG_SENSORS_HTU21 is not set -# CONFIG_SENSORS_I5500 is not set -# CONFIG_SENSORS_I5K_AMB is not set -# CONFIG_SENSORS_IBM_CFFPS is not set -# CONFIG_SENSORS_IIO_HWMON is not set -# CONFIG_SENSORS_INA209 is not set -# CONFIG_SENSORS_INA2XX is not set -# CONFIG_SENSORS_INA3221 is not set -# CONFIG_SENSORS_INSPUR_IPSPS is not set -# CONFIG_SENSORS_IR35221 is not set -# CONFIG_SENSORS_IR38064 is not set -# CONFIG_SENSORS_IRPS5401 is not set -# CONFIG_SENSORS_ISL29018 is not set -# CONFIG_SENSORS_ISL29028 is not set -# CONFIG_SENSORS_ISL68137 is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_JC42 is not set -# CONFIG_SENSORS_K10TEMP is not set -# CONFIG_SENSORS_K8TEMP is not set -# CONFIG_SENSORS_LINEAGE is not set -# CONFIG_SENSORS_LIS3LV02D is not set -# CONFIG_SENSORS_LIS3_I2C is not set -# CONFIG_SENSORS_LIS3_SPI is not set -# CONFIG_SENSORS_LM25066 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LM95234 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_LM95245 is not set -# CONFIG_SENSORS_LTC2945 is not set -# CONFIG_SENSORS_LTC2947_I2C is not set -# CONFIG_SENSORS_LTC2947_SPI is not set -# CONFIG_SENSORS_LTC2978 is not set -# CONFIG_SENSORS_LTC2990 is not set -# CONFIG_SENSORS_LTC3815 is not set -# CONFIG_SENSORS_LTC4151 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4222 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LTC4260 is not set -# CONFIG_SENSORS_LTC4261 is not set -# CONFIG_SENSORS_LTQ_CPUTEMP is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX16064 is not set -# CONFIG_SENSORS_MAX16065 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX16601 is not set -# CONFIG_SENSORS_MAX1668 is not set -# CONFIG_SENSORS_MAX197 is not set -# CONFIG_SENSORS_MAX20730 is not set -# CONFIG_SENSORS_MAX20751 is not set -# CONFIG_SENSORS_MAX31722 is not set -# CONFIG_SENSORS_MAX31730 is not set -# CONFIG_SENSORS_MAX31785 is not set -# CONFIG_SENSORS_MAX31790 is not set -# CONFIG_SENSORS_MAX34440 is not set -# CONFIG_SENSORS_MAX6621 is not set -# CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_MAX6697 is not set -# CONFIG_SENSORS_MAX8688 is not set -# CONFIG_SENSORS_MCP3021 is not set -# CONFIG_SENSORS_MP2975 is not set -# CONFIG_SENSORS_MR75203 is not set -# CONFIG_SENSORS_NCT6683 is not set -# CONFIG_SENSORS_NCT6775 is not set -# CONFIG_SENSORS_NCT7802 is not set -# CONFIG_SENSORS_NCT7904 is not set -# CONFIG_SENSORS_NPCM7XX is not set -# CONFIG_SENSORS_NSA320 is not set -# CONFIG_SENSORS_NTC_THERMISTOR is not set -# CONFIG_SENSORS_OCC_P8_I2C is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_PMBUS is not set -# CONFIG_SENSORS_POWR1220 is not set -# CONFIG_SENSORS_PWM_FAN is not set -# CONFIG_SENSORS_PXE1610 is not set -# CONFIG_SENSORS_RM3100_I2C is not set -# CONFIG_SENSORS_RM3100_SPI is not set -# CONFIG_SENSORS_SCH5627 is not set -# CONFIG_SENSORS_SCH5636 is not set -# CONFIG_SENSORS_SCH56XX_COMMON is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_SHT21 is not set -# CONFIG_SENSORS_SHT3x is not set -# CONFIG_SENSORS_SHTC1 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_SMM665 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_STTS751 is not set -# CONFIG_SENSORS_TC654 is not set -# CONFIG_SENSORS_TC74 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP102 is not set -# CONFIG_SENSORS_TMP103 is not set -# CONFIG_SENSORS_TMP108 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_TMP513 is not set -# CONFIG_SENSORS_TPS23861 is not set -# CONFIG_SENSORS_TPS40422 is not set -# CONFIG_SENSORS_TPS53679 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_TSL2563 is not set -# CONFIG_SENSORS_UCD9000 is not set -# CONFIG_SENSORS_UCD9200 is not set -# CONFIG_SENSORS_VEXPRESS is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VIA_CPUTEMP is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83773G is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83795 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_XDPE122 is not set -# CONFIG_SENSORS_XGENE is not set -# CONFIG_SENSORS_ZL6100 is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_16550A_VARIANTS=y -# CONFIG_SERIAL_8250_ACCENT is not set -# CONFIG_SERIAL_8250_ASPEED_VUART is not set -# CONFIG_SERIAL_8250_BOCA is not set -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_CS is not set -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -# CONFIG_SERIAL_8250_DETECT_IRQ is not set -CONFIG_SERIAL_8250_DMA=y -# CONFIG_SERIAL_8250_DW is not set -# CONFIG_SERIAL_8250_EM is not set -# CONFIG_SERIAL_8250_EXAR is not set -# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set -# CONFIG_SERIAL_8250_EXTENDED is not set -# CONFIG_SERIAL_8250_FINTEK is not set -# CONFIG_SERIAL_8250_FOURPORT is not set -# CONFIG_SERIAL_8250_HUB6 is not set -# CONFIG_SERIAL_8250_INGENIC is not set -# CONFIG_SERIAL_8250_LPSS is not set -# CONFIG_SERIAL_8250_MANY_PORTS is not set -# CONFIG_SERIAL_8250_MID is not set -# CONFIG_SERIAL_8250_MOXA is not set -CONFIG_SERIAL_8250_NR_UARTS=2 -# CONFIG_SERIAL_8250_PCI is not set -# CONFIG_SERIAL_8250_RSA is not set -# CONFIG_SERIAL_8250_RT288X is not set -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_SERIAL_ALTERA_JTAGUART is not set -# CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_AMBA_PL010 is not set -# CONFIG_SERIAL_AMBA_PL011 is not set -# CONFIG_SERIAL_ARC is not set -# CONFIG_SERIAL_BCM63XX is not set -# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_DEV_BUS is not set -CONFIG_SERIAL_EARLYCON=y -# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set -# CONFIG_SERIAL_FSL_LINFLEXUART is not set -# CONFIG_SERIAL_FSL_LPUART is not set -# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set -# CONFIG_SERIAL_IFX6X60 is not set -# CONFIG_SERIAL_JSM is not set -# CONFIG_SERIAL_MAX3100 is not set -# CONFIG_SERIAL_MAX310X is not set -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_SERIAL_OF_PLATFORM is not set -# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set -# CONFIG_SERIAL_PCH_UART is not set -# CONFIG_SERIAL_RP2 is not set -# CONFIG_SERIAL_SC16IS7XX is not set -# CONFIG_SERIAL_SCCNXP is not set -# CONFIG_SERIAL_SH_SCI is not set -# CONFIG_SERIAL_SIFIVE is not set -# CONFIG_SERIAL_SPRD is not set -# CONFIG_SERIAL_STM32 is not set -# CONFIG_SERIAL_ST_ASC is not set -# CONFIG_SERIAL_TIMBERDALE is not set -# CONFIG_SERIAL_UARTLITE is not set -# CONFIG_SERIAL_XILINX_PS_UART is not set -# CONFIG_SERIO is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_SERIO_AMBAKMI is not set -# CONFIG_SERIO_APBPS2 is not set -# CONFIG_SERIO_ARC_PS2 is not set -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_GPIO_PS2 is not set -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_PARKBD is not set -# CONFIG_SERIO_PCIPS2 is not set -# CONFIG_SERIO_PS2MULT is not set -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_SUN4I_PS2 is not set -# CONFIG_SFC is not set -# CONFIG_SFC_FALCON is not set -# CONFIG_SFI is not set -# CONFIG_SFP is not set -# CONFIG_SF_PDMA is not set -# CONFIG_SGETMASK_SYSCALL is not set -# CONFIG_SGI_IOC4 is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP30 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SGI_MFD_IOC3 is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_SG_POOL is not set -# CONFIG_SG_SPLIT is not set -CONFIG_SHMEM=y -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -# CONFIG_SH_ETH is not set -# CONFIG_SH_TIMER_CMT is not set -# CONFIG_SH_TIMER_MTU2 is not set -# CONFIG_SH_TIMER_TMU is not set -# CONFIG_SI1133 is not set -# CONFIG_SI1145 is not set -# CONFIG_SI7005 is not set -# CONFIG_SI7020 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -CONFIG_SIGNALFD=y -# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set -# CONFIG_SIMPLE_GPIO is not set -# CONFIG_SIMPLE_PM_BUS is not set -# CONFIG_SIOX is not set -# CONFIG_SIS190 is not set -# CONFIG_SIS900 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_SKY2_DEBUG is not set -# CONFIG_SLAB is not set -CONFIG_SLABINFO=y -CONFIG_SLAB_FREELIST_HARDENED=y -CONFIG_SLAB_FREELIST_RANDOM=y -CONFIG_SLAB_MERGE_DEFAULT=y -# CONFIG_SLHC is not set -# CONFIG_SLICOSS is not set -# CONFIG_SLIMBUS is not set -# CONFIG_SLIP is not set -# CONFIG_SLOB is not set -CONFIG_SLUB=y -CONFIG_SLUB_CPU_PARTIAL=y -# CONFIG_SLUB_DEBUG is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_MEMCG_SYSFS_ON is not set -# CONFIG_SLUB_STATS is not set -# CONFIG_SMARTJOYPLUS_FF is not set -# CONFIG_SMC911X is not set -# CONFIG_SMC9194 is not set -# CONFIG_SMC91X is not set -# CONFIG_SMP is not set -# CONFIG_SMSC911X is not set -# CONFIG_SMSC9420 is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_SMS_SDIO_DRV is not set -# CONFIG_SMS_USB_DRV is not set -# CONFIG_SM_FTL is not set -# CONFIG_SND is not set -# CONFIG_SND_AC97_POWER_SAVE is not set -# CONFIG_SND_AD1816A is not set -# CONFIG_SND_AD1848 is not set -# CONFIG_SND_AD1889 is not set -# CONFIG_SND_ADLIB is not set -# CONFIG_SND_ALI5451 is not set -# CONFIG_SND_ALOOP is not set -# CONFIG_SND_ALS100 is not set -# CONFIG_SND_ALS300 is not set -# CONFIG_SND_ALS4000 is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_ASIHPI is not set -# CONFIG_SND_ATIIXP is not set -# CONFIG_SND_ATIIXP_MODEM is not set -# CONFIG_SND_ATMEL_AC97C is not set -# CONFIG_SND_ATMEL_SOC is not set -# CONFIG_SND_AU8810 is not set -# CONFIG_SND_AU8820 is not set -# CONFIG_SND_AU8830 is not set -# CONFIG_SND_AUDIO_GRAPH_CARD is not set -# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set -# CONFIG_SND_AW2 is not set -# CONFIG_SND_AZT2320 is not set -# CONFIG_SND_AZT3328 is not set -# CONFIG_SND_BCD2000 is not set -# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set -# CONFIG_SND_BT87X is not set -# CONFIG_SND_CA0106 is not set -# CONFIG_SND_CMI8330 is not set -# CONFIG_SND_CMIPCI is not set -# CONFIG_SND_CS4231 is not set -# CONFIG_SND_CS4236 is not set -# CONFIG_SND_CS4281 is not set -# CONFIG_SND_CS46XX is not set -# CONFIG_SND_CS5530 is not set -# CONFIG_SND_CS5535AUDIO is not set -# CONFIG_SND_CTXFI is not set -# CONFIG_SND_DARLA20 is not set -# CONFIG_SND_DARLA24 is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_DESIGNWARE_I2S is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_ECHO3G is not set -# CONFIG_SND_EDMA_SOC is not set -# CONFIG_SND_EMU10K1 is not set -# CONFIG_SND_EMU10K1X is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_ENS1370 is not set -# CONFIG_SND_ENS1371 is not set -# CONFIG_SND_ES1688 is not set -# CONFIG_SND_ES18XX is not set -# CONFIG_SND_ES1938 is not set -# CONFIG_SND_ES1968 is not set -# CONFIG_SND_FIREWIRE is not set -# CONFIG_SND_FM801 is not set -# CONFIG_SND_GINA20 is not set -# CONFIG_SND_GINA24 is not set -# CONFIG_SND_GUSCLASSIC is not set -# CONFIG_SND_GUSEXTREME is not set -# CONFIG_SND_GUSMAX is not set -# CONFIG_SND_HDA_INTEL is not set -# CONFIG_SND_HDA_INTEL_DETECT_DMIC is not set -# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set -CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 -CONFIG_SND_HDA_PREALLOC_SIZE=64 -# CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_HWDEP is not set -# CONFIG_SND_I2S_HI6210_I2S is not set -# CONFIG_SND_ICE1712 is not set -# CONFIG_SND_ICE1724 is not set -# CONFIG_SND_INDIGO is not set -# CONFIG_SND_INDIGODJ is not set -# CONFIG_SND_INDIGODJX is not set -# CONFIG_SND_INDIGOIO is not set -# CONFIG_SND_INDIGOIOX is not set -# CONFIG_SND_INTEL8X0 is not set -# CONFIG_SND_INTEL8X0M is not set -# CONFIG_SND_INTERWAVE is not set -# CONFIG_SND_INTERWAVE_STB is not set -# CONFIG_SND_ISA is not set -# CONFIG_SND_JZ4740_SOC_I2S is not set -# CONFIG_SND_KIRKWOOD_SOC is not set -# CONFIG_SND_KORG1212 is not set -# CONFIG_SND_LAYLA20 is not set -# CONFIG_SND_LAYLA24 is not set -# CONFIG_SND_LOLA is not set -# CONFIG_SND_LX6464ES is not set -# CONFIG_SND_MAESTRO3 is not set -CONFIG_SND_MAX_CARDS=16 -# CONFIG_SND_MIA is not set -# CONFIG_SND_MIPS is not set -# CONFIG_SND_MIRO is not set -# CONFIG_SND_MIXART is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_MONA is not set -# CONFIG_SND_MPC52xx_SOC_EFIKA is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_MTS64 is not set -# CONFIG_SND_MXS_SOC is not set -# CONFIG_SND_NM256 is not set -# CONFIG_SND_OPL3SA2 is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_OPTI92X_AD1848 is not set -# CONFIG_SND_OPTI92X_CS4231 is not set -# CONFIG_SND_OPTI93X is not set -CONFIG_SND_OSSEMUL=y -# CONFIG_SND_OXYGEN is not set -CONFIG_SND_PCI=y -# CONFIG_SND_PCM is not set -# CONFIG_SND_PCMCIA is not set -# CONFIG_SND_PCM_OSS is not set -CONFIG_SND_PCM_OSS_PLUGINS=y -# CONFIG_SND_PCM_TIMER is not set -# CONFIG_SND_PCM_XRUN_DEBUG is not set -# CONFIG_SND_PCXHR is not set -# CONFIG_SND_PDAUDIOCF is not set -# CONFIG_SND_PORTMAN2X4 is not set -# CONFIG_SND_POWERPC_SOC is not set -# CONFIG_SND_PPC is not set -CONFIG_SND_PROC_FS=y -# CONFIG_SND_RAWMIDI is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_RIPTIDE is not set -# CONFIG_SND_RME32 is not set -# CONFIG_SND_RME96 is not set -# CONFIG_SND_RME9652 is not set -# CONFIG_SND_RTCTIMER is not set -# CONFIG_SND_SB16 is not set -# CONFIG_SND_SB8 is not set -# CONFIG_SND_SBAWE is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_SE6X is not set -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_SIMPLE_CARD is not set -# CONFIG_SND_SIMPLE_SCU_CARD is not set -# CONFIG_SND_SIS7019 is not set -# CONFIG_SND_SOC is not set -# CONFIG_SND_SOC_AC97_CODEC is not set -# CONFIG_SND_SOC_ADAU1701 is not set -# CONFIG_SND_SOC_ADAU1761_I2C is not set -# CONFIG_SND_SOC_ADAU1761_SPI is not set -# CONFIG_SND_SOC_ADAU7002 is not set -# CONFIG_SND_SOC_ADAU7118_HW is not set -# CONFIG_SND_SOC_ADAU7118_I2C is not set -# CONFIG_SND_SOC_AK4104 is not set -# CONFIG_SND_SOC_AK4118 is not set -# CONFIG_SND_SOC_AK4458 is not set -# CONFIG_SND_SOC_AK4554 is not set -# CONFIG_SND_SOC_AK4613 is not set -# CONFIG_SND_SOC_AK4642 is not set -# CONFIG_SND_SOC_AK5386 is not set -# CONFIG_SND_SOC_AK5558 is not set -# CONFIG_SND_SOC_ALC5623 is not set -# CONFIG_SND_SOC_AMD_ACP is not set -# CONFIG_SND_SOC_AMD_ACP3x is not set -# CONFIG_SND_SOC_AMD_RENOIR is not set -# CONFIG_SND_SOC_AU1XAUDIO is not set -# CONFIG_SND_SOC_AU1XPSC is not set -# CONFIG_SND_SOC_BD28623 is not set -# CONFIG_SND_SOC_BT_SCO is not set -# CONFIG_SND_SOC_CS35L32 is not set -# CONFIG_SND_SOC_CS35L33 is not set -# CONFIG_SND_SOC_CS35L34 is not set -# CONFIG_SND_SOC_CS35L35 is not set -# CONFIG_SND_SOC_CS35L36 is not set -# CONFIG_SND_SOC_CS4234 is not set -# CONFIG_SND_SOC_CS4265 is not set -# CONFIG_SND_SOC_CS4270 is not set -# CONFIG_SND_SOC_CS4271 is not set -# CONFIG_SND_SOC_CS4271_I2C is not set -# CONFIG_SND_SOC_CS4271_SPI is not set -# CONFIG_SND_SOC_CS42L42 is not set -# CONFIG_SND_SOC_CS42L51_I2C is not set -# CONFIG_SND_SOC_CS42L52 is not set -# CONFIG_SND_SOC_CS42L56 is not set -# CONFIG_SND_SOC_CS42L73 is not set -# CONFIG_SND_SOC_CS42XX8_I2C is not set -# CONFIG_SND_SOC_CS43130 is not set -# CONFIG_SND_SOC_CS4341 is not set -# CONFIG_SND_SOC_CS4349 is not set -# CONFIG_SND_SOC_CS53L30 is not set -# CONFIG_SND_SOC_CX2072X is not set -# CONFIG_SND_SOC_DA7213 is not set -# CONFIG_SND_SOC_DIO2125 is not set -# CONFIG_SND_SOC_DMIC is not set -# CONFIG_SND_SOC_ES7134 is not set -# CONFIG_SND_SOC_ES7241 is not set -# CONFIG_SND_SOC_ES8316 is not set -# CONFIG_SND_SOC_ES8328 is not set -# CONFIG_SND_SOC_ES8328_I2C is not set -# CONFIG_SND_SOC_ES8328_SPI is not set -# CONFIG_SND_SOC_EUKREA_TLV320 is not set -# CONFIG_SND_SOC_FSL_ASOC_CARD is not set -# CONFIG_SND_SOC_FSL_ASRC is not set -# CONFIG_SND_SOC_FSL_AUDMIX is not set -# CONFIG_SND_SOC_FSL_ESAI is not set -# CONFIG_SND_SOC_FSL_MICFIL is not set -# CONFIG_SND_SOC_FSL_SAI is not set -# CONFIG_SND_SOC_FSL_SPDIF is not set -# CONFIG_SND_SOC_FSL_SSI is not set -# CONFIG_SND_SOC_GTM601 is not set -# CONFIG_SND_SOC_ICS43432 is not set -# CONFIG_SND_SOC_IMG is not set -# CONFIG_SND_SOC_IMX_AUDMIX is not set -# CONFIG_SND_SOC_IMX_AUDMUX is not set -# CONFIG_SND_SOC_IMX_ES8328 is not set -# CONFIG_SND_SOC_IMX_SPDIF is not set -# CONFIG_SND_SOC_IMX_WM8962 is not set -# CONFIG_SND_SOC_INNO_RK3036 is not set -# CONFIG_SND_SOC_INTEL_APL is not set -# CONFIG_SND_SOC_INTEL_BAYTRAIL is not set -# CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH is not set -# CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH is not set -# CONFIG_SND_SOC_INTEL_BXT_RT298_MACH is not set -# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set -# CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH is not set -# CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH is not set -# CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH is not set -# CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH is not set -# CONFIG_SND_SOC_INTEL_BYT_MAX98090_MACH is not set -# CONFIG_SND_SOC_INTEL_BYT_RT5640_MACH is not set -# CONFIG_SND_SOC_INTEL_CATPT is not set -# CONFIG_SND_SOC_INTEL_CFL is not set -# CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH is not set -# CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH is not set -# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH is not set -# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH is not set -# CONFIG_SND_SOC_INTEL_CML_H is not set -# CONFIG_SND_SOC_INTEL_CML_LP is not set -# CONFIG_SND_SOC_INTEL_CNL is not set -# CONFIG_SND_SOC_INTEL_GLK is not set -# CONFIG_SND_SOC_INTEL_HASWELL is not set -# CONFIG_SND_SOC_INTEL_KBL is not set -# CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH is not set -# CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH is not set -# CONFIG_SND_SOC_INTEL_KEEMBAY is not set -# CONFIG_SND_SOC_INTEL_SKL is not set -# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH is not set -# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH is not set -# CONFIG_SND_SOC_INTEL_SKL_RT286_MACH is not set -# CONFIG_SND_SOC_INTEL_SKYLAKE is not set -# CONFIG_SND_SOC_INTEL_SST is not set -CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y -# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set -# CONFIG_SND_SOC_JZ4725B_CODEC is not set -# CONFIG_SND_SOC_JZ4740_CODEC is not set -# CONFIG_SND_SOC_JZ4770_CODEC is not set -# CONFIG_SND_SOC_MA120X0P is not set -# CONFIG_SND_SOC_MAX9759 is not set -# CONFIG_SND_SOC_MAX98088 is not set -# CONFIG_SND_SOC_MAX98357A is not set -# CONFIG_SND_SOC_MAX98373 is not set -# CONFIG_SND_SOC_MAX98373_I2C is not set -# CONFIG_SND_SOC_MAX98390 is not set -# CONFIG_SND_SOC_MAX98504 is not set -# CONFIG_SND_SOC_MAX9860 is not set -# CONFIG_SND_SOC_MAX9867 is not set -# CONFIG_SND_SOC_MAX98927 is not set -# CONFIG_SND_SOC_MEDIATEK is not set -# CONFIG_SND_SOC_MPC5200_AC97 is not set -# CONFIG_SND_SOC_MPC5200_I2S is not set -# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set -# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set -# CONFIG_SND_SOC_MT2701 is not set -# CONFIG_SND_SOC_MT6351 is not set -# CONFIG_SND_SOC_MT6358 is not set -# CONFIG_SND_SOC_MT6660 is not set -# CONFIG_SND_SOC_MT6797 is not set -# CONFIG_SND_SOC_MT8173 is not set -# CONFIG_SND_SOC_MT8183 is not set -# CONFIG_SND_SOC_MTK_BTCVSD is not set -# CONFIG_SND_SOC_NAU8540 is not set -# CONFIG_SND_SOC_NAU8810 is not set -# CONFIG_SND_SOC_NAU8822 is not set -# CONFIG_SND_SOC_NAU8824 is not set -# CONFIG_SND_SOC_PCM1681 is not set -# CONFIG_SND_SOC_PCM1789_I2C is not set -# CONFIG_SND_SOC_PCM1792A is not set -# CONFIG_SND_SOC_PCM179X_I2C is not set -# CONFIG_SND_SOC_PCM179X_SPI is not set -# CONFIG_SND_SOC_PCM186X_I2C is not set -# CONFIG_SND_SOC_PCM186X_SPI is not set -# CONFIG_SND_SOC_PCM3060_I2C is not set -# CONFIG_SND_SOC_PCM3060_SPI is not set -# CONFIG_SND_SOC_PCM3168A_I2C is not set -# CONFIG_SND_SOC_PCM3168A_SPI is not set -# CONFIG_SND_SOC_PCM512x_I2C is not set -# CONFIG_SND_SOC_PCM512x_SPI is not set -# CONFIG_SND_SOC_QCOM is not set -# CONFIG_SND_SOC_RK3328 is not set -# CONFIG_SND_SOC_RT5616 is not set -# CONFIG_SND_SOC_RT5631 is not set -# CONFIG_SND_SOC_RT5677_SPI is not set -# CONFIG_SND_SOC_SGTL5000 is not set -# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set -# CONFIG_SND_SOC_SOF_TOPLEVEL is not set -# CONFIG_SND_SOC_SPDIF is not set -# CONFIG_SND_SOC_SSM2305 is not set -# CONFIG_SND_SOC_SSM2602_I2C is not set -# CONFIG_SND_SOC_SSM2602_SPI is not set -# CONFIG_SND_SOC_SSM4567 is not set -# CONFIG_SND_SOC_STA32X is not set -# CONFIG_SND_SOC_STA350 is not set -# CONFIG_SND_SOC_STI_SAS is not set -# CONFIG_SND_SOC_TAS2552 is not set -# CONFIG_SND_SOC_TAS2562 is not set -# CONFIG_SND_SOC_TAS2764 is not set -# CONFIG_SND_SOC_TAS2770 is not set -# CONFIG_SND_SOC_TAS5086 is not set -# CONFIG_SND_SOC_TAS571X is not set -# CONFIG_SND_SOC_TAS5720 is not set -# CONFIG_SND_SOC_TAS6424 is not set -# CONFIG_SND_SOC_TDA7419 is not set -# CONFIG_SND_SOC_TFA9879 is not set -# CONFIG_SND_SOC_TLV320ADCX140 is not set -# CONFIG_SND_SOC_TLV320AIC23_I2C is not set -# CONFIG_SND_SOC_TLV320AIC23_SPI is not set -# CONFIG_SND_SOC_TLV320AIC31XX is not set -# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set -# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set -# CONFIG_SND_SOC_TPA6130A2 is not set -# CONFIG_SND_SOC_TS3A227E is not set -# CONFIG_SND_SOC_TSCS42XX is not set -# CONFIG_SND_SOC_TSCS454 is not set -# CONFIG_SND_SOC_UDA1334 is not set -# CONFIG_SND_SOC_WM8510 is not set -# CONFIG_SND_SOC_WM8523 is not set -# CONFIG_SND_SOC_WM8524 is not set -# CONFIG_SND_SOC_WM8580 is not set -# CONFIG_SND_SOC_WM8711 is not set -# CONFIG_SND_SOC_WM8728 is not set -# CONFIG_SND_SOC_WM8731 is not set -# CONFIG_SND_SOC_WM8737 is not set -# CONFIG_SND_SOC_WM8741 is not set -# CONFIG_SND_SOC_WM8750 is not set -# CONFIG_SND_SOC_WM8753 is not set -# CONFIG_SND_SOC_WM8770 is not set -# CONFIG_SND_SOC_WM8776 is not set -# CONFIG_SND_SOC_WM8782 is not set -# CONFIG_SND_SOC_WM8804_I2C is not set -# CONFIG_SND_SOC_WM8804_SPI is not set -# CONFIG_SND_SOC_WM8903 is not set -# CONFIG_SND_SOC_WM8904 is not set -# CONFIG_SND_SOC_WM8960 is not set -# CONFIG_SND_SOC_WM8962 is not set -# CONFIG_SND_SOC_WM8974 is not set -# CONFIG_SND_SOC_WM8978 is not set -# CONFIG_SND_SOC_WM8985 is not set -# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set -# CONFIG_SND_SOC_XILINX_I2S is not set -# CONFIG_SND_SOC_XILINX_SPDIF is not set -# CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set -# CONFIG_SND_SONICVIBES is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_SSCAPE is not set -# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI is not set -# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI is not set -# CONFIG_SND_SUN4I_CODEC is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_TIMER is not set -# CONFIG_SND_TRIDENT is not set -CONFIG_SND_USB=y -# CONFIG_SND_USB_6FIRE is not set -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_CAIAQ is not set -# CONFIG_SND_USB_HIFACE is not set -# CONFIG_SND_USB_POD is not set -# CONFIG_SND_USB_PODHD is not set -# CONFIG_SND_USB_TONEPORT is not set -# CONFIG_SND_USB_UA101 is not set -# CONFIG_SND_USB_US122L is not set -# CONFIG_SND_USB_USX2Y is not set -# CONFIG_SND_USB_VARIAX is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VIA82XX is not set -# CONFIG_SND_VIA82XX_MODEM is not set -# CONFIG_SND_VIRTUOSO is not set -# CONFIG_SND_VX222 is not set -# CONFIG_SND_VXPOCKET is not set -# CONFIG_SND_WAVEFRONT is not set -CONFIG_SND_X86=y -# CONFIG_SND_XEN_FRONTEND is not set -# CONFIG_SND_YMFPCI is not set -# CONFIG_SNI_RM is not set -# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set -# CONFIG_SOCK_CGROUP_DATA is not set -# CONFIG_SOC_AM33XX is not set -# CONFIG_SOC_AM43XX is not set -# CONFIG_SOC_BRCMSTB is not set -# CONFIG_SOC_CAMERA is not set -# CONFIG_SOC_DRA7XX is not set -# CONFIG_SOC_HAS_OMAP2_SDRC is not set -# CONFIG_SOC_OMAP5 is not set -# CONFIG_SOC_TI is not set -# CONFIG_SOFTLOCKUP_DETECTOR is not set -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_SONYPI is not set -# CONFIG_SONY_LAPTOP is not set -# CONFIG_SOUND is not set -# CONFIG_SOUNDWIRE is not set -# CONFIG_SOUND_OSS_CORE is not set -# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set -# CONFIG_SOUND_PRIME is not set -# CONFIG_SP5100_TCO is not set -# CONFIG_SPARSEMEM_MANUAL is not set -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set -# CONFIG_SPARSE_IRQ is not set -# CONFIG_SPARSE_RCU_POINTER is not set -# CONFIG_SPEAKUP is not set -# CONFIG_SPI is not set -# CONFIG_SPINLOCK_TEST is not set -# CONFIG_SPI_ALTERA is not set -# CONFIG_SPI_AMD is not set -# CONFIG_SPI_AU1550 is not set -# CONFIG_SPI_AXI_SPI_ENGINE is not set -# CONFIG_SPI_BCM2835 is not set -# CONFIG_SPI_BCM_QSPI is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_BUTTERFLY is not set -# CONFIG_SPI_CADENCE is not set -# CONFIG_SPI_CADENCE_QUADSPI is not set -# CONFIG_SPI_DEBUG is not set -# CONFIG_SPI_DESIGNWARE is not set -# CONFIG_SPI_FSL_DSPI is not set -# CONFIG_SPI_FSL_ESPI is not set -# CONFIG_SPI_FSL_SPI is not set -# CONFIG_SPI_GPIO is not set -# CONFIG_SPI_GPIO_OLD is not set -# CONFIG_SPI_IMG_SPFI is not set -# CONFIG_SPI_LANTIQ_SSC is not set -# CONFIG_SPI_LM70_LLP is not set -# CONFIG_SPI_LOOPBACK_TEST is not set -# CONFIG_SPI_MASTER is not set -# CONFIG_SPI_MEM is not set -# CONFIG_SPI_MPC52xx is not set -# CONFIG_SPI_MPC52xx_PSC is not set -# CONFIG_SPI_MTK_QUADSPI is not set -# CONFIG_SPI_MUX is not set -# CONFIG_SPI_MXIC is not set -# CONFIG_SPI_NXP_FLEXSPI is not set -# CONFIG_SPI_OCTEON is not set -# CONFIG_SPI_OC_TINY is not set -# CONFIG_SPI_ORION is not set -# CONFIG_SPI_PL022 is not set -# CONFIG_SPI_PPC4xx is not set -# CONFIG_SPI_PXA2XX is not set -# CONFIG_SPI_PXA2XX_PCI is not set -# CONFIG_SPI_QCOM_QSPI is not set -# CONFIG_SPI_ROCKCHIP is not set -# CONFIG_SPI_S3C64XX is not set -# CONFIG_SPI_SC18IS602 is not set -# CONFIG_SPI_SIFIVE is not set -# CONFIG_SPI_SLAVE is not set -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_THUNDERX is not set -# CONFIG_SPI_TI_QSPI is not set -# CONFIG_SPI_TLE62X0 is not set -# CONFIG_SPI_TOPCLIFF_PCH is not set -# CONFIG_SPI_XCOMM is not set -# CONFIG_SPI_XILINX is not set -# CONFIG_SPI_XWAY is not set -# CONFIG_SPI_ZYNQMP_GQSPI is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_SPMI is not set -# CONFIG_SPS30 is not set -CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set -# CONFIG_SQUASHFS_DECOMP_MULTI is not set -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -# CONFIG_SQUASHFS_DECOMP_SINGLE is not set -CONFIG_SQUASHFS_EMBEDDED=y -# CONFIG_SQUASHFS_FILE_CACHE is not set -CONFIG_SQUASHFS_FILE_DIRECT=y -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -# CONFIG_SQUASHFS_LZ4 is not set -# CONFIG_SQUASHFS_LZO is not set -# CONFIG_SQUASHFS_XATTR is not set -CONFIG_SQUASHFS_XZ=y -# CONFIG_SQUASHFS_ZLIB is not set -# CONFIG_SQUASHFS_ZSTD is not set -# CONFIG_SRAM is not set -# CONFIG_SRF04 is not set -# CONFIG_SRF08 is not set -# CONFIG_SSB is not set -# CONFIG_SSB_DEBUG is not set -# CONFIG_SSB_DRIVER_GPIO is not set -# CONFIG_SSB_HOST_SOC is not set -# CONFIG_SSB_PCMCIAHOST is not set -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB_SDIOHOST is not set -# CONFIG_SSB_SILENT is not set -# CONFIG_SSFDC is not set -# CONFIG_STACKPROTECTOR is not set -# CONFIG_STACKPROTECTOR_STRONG is not set -# CONFIG_STACKTRACE is not set -CONFIG_STACKTRACE_SUPPORT=y -# CONFIG_STACK_TRACER is not set -# CONFIG_STACK_VALIDATION is not set -CONFIG_STAGING=y -# CONFIG_STAGING_BOARD is not set -# CONFIG_STAGING_GASKET_FRAMEWORK is not set -# CONFIG_STAGING_MEDIA is not set -CONFIG_STANDALONE=y -# CONFIG_STATIC_KEYS_SELFTEST is not set -# CONFIG_STATIC_USERMODEHELPER is not set -CONFIG_STDBINUTILS=y -# CONFIG_STE10XP is not set -# CONFIG_STE_MODEM_RPROC is not set -# CONFIG_STK3310 is not set -# CONFIG_STK8312 is not set -# CONFIG_STK8BA50 is not set -# CONFIG_STM is not set -# CONFIG_STMMAC_ETH is not set -# CONFIG_STMMAC_PCI is not set -# CONFIG_STMMAC_PLATFORM is not set -# CONFIG_STM_DUMMY is not set -# CONFIG_STM_SOURCE_CONSOLE is not set -CONFIG_STP=y -# CONFIG_STREAM_PARSER is not set -# CONFIG_STRICT_DEVMEM is not set -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_STRICT_MODULE_RWX=y -# CONFIG_STRING_SELFTEST is not set -CONFIG_STRIP_ASM_SYMS=y -# CONFIG_STX104 is not set -# CONFIG_ST_UVIS25 is not set -# CONFIG_SUN4I_GPADC is not set -# CONFIG_SUN50I_DE2_BUS is not set -# CONFIG_SUN50I_ERRATUM_UNKNOWN1 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_SUNGEM is not set -# CONFIG_SUNRPC is not set -# CONFIG_SUNRPC_DEBUG is not set -CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y -# CONFIG_SUNRPC_GSS is not set -# CONFIG_SUNXI_SRAM is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_SURFACE_3_BUTTON is not set -# CONFIG_SUSPEND is not set -# CONFIG_SUSPEND_SKIP_SYNC is not set -CONFIG_SWAP=y -# CONFIG_SWCONFIG is not set -# CONFIG_SWCONFIG_B53 is not set -# CONFIG_SWCONFIG_B53_MDIO_DRIVER is not set -# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set -# CONFIG_SWCONFIG_B53_SPI_DRIVER is not set -# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set -# CONFIG_SWCONFIG_LEDS is not set -# CONFIG_SW_SYNC is not set -# CONFIG_SX9310 is not set -# CONFIG_SX9500 is not set -# CONFIG_SXGBE_ETH is not set -CONFIG_SYMBOLIC_ERRNAME=y -# CONFIG_SYNCLINK_CS is not set -# CONFIG_SYNC_FILE is not set -# CONFIG_SYNOPSYS_DWC_ETH_QOS is not set -# CONFIG_SYNTH_EVENTS is not set -CONFIG_SYN_COOKIES=y -# CONFIG_SYSCON_REBOOT_MODE is not set -CONFIG_SYSCTL=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_SYSFS=y -# CONFIG_SYSFS_DEPRECATED is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_SYSFS_SYSCALL is not set -# CONFIG_SYSTEMPORT is not set -# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set -# CONFIG_SYSTEM_DATA_VERIFICATION is not set -# CONFIG_SYSTEM_TRUSTED_KEYRING is not set -CONFIG_SYSTEM_TRUSTED_KEYS="" -# CONFIG_SYSV68_PARTITION is not set -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_SYSV_FS is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_T5403 is not set -# CONFIG_TARGET_CORE is not set -# CONFIG_TASKSTATS is not set -# CONFIG_TASKS_RCU is not set -# CONFIG_TASK_XACCT is not set -# CONFIG_TC35815 is not set -# CONFIG_TCG_ATMEL is not set -# CONFIG_TCG_CRB is not set -# CONFIG_TCG_FTPM_TEE is not set -# CONFIG_TCG_INFINEON is not set -# CONFIG_TCG_NSC is not set -# CONFIG_TCG_ST33_I2C is not set -# CONFIG_TCG_TIS is not set -# CONFIG_TCG_TIS_I2C_ATMEL is not set -# CONFIG_TCG_TIS_I2C_INFINEON is not set -# CONFIG_TCG_TIS_I2C_NUVOTON is not set -# CONFIG_TCG_TIS_SPI is not set -# CONFIG_TCG_TIS_ST33ZP24_I2C is not set -# CONFIG_TCG_TIS_ST33ZP24_SPI is not set -# CONFIG_TCG_TPM is not set -# CONFIG_TCG_VTPM_PROXY is not set -# CONFIG_TCG_XEN is not set -# CONFIG_TCIC is not set -CONFIG_TCP_CONG_ADVANCED=y -# CONFIG_TCP_CONG_BBR is not set -# CONFIG_TCP_CONG_BIC is not set -# CONFIG_TCP_CONG_CDG is not set -CONFIG_TCP_CONG_CUBIC=y -# CONFIG_TCP_CONG_DCTCP is not set -# CONFIG_TCP_CONG_HSTCP is not set -# CONFIG_TCP_CONG_HTCP is not set -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_ILLINOIS is not set -# CONFIG_TCP_CONG_LP is not set -# CONFIG_TCP_CONG_NV is not set -# CONFIG_TCP_CONG_SCALABLE is not set -# CONFIG_TCP_CONG_VEGAS is not set -# CONFIG_TCP_CONG_VENO is not set -# CONFIG_TCP_CONG_WESTWOOD is not set -# CONFIG_TCP_CONG_YEAH is not set -# CONFIG_TCP_MD5SIG is not set -# CONFIG_TCS3414 is not set -# CONFIG_TCS3472 is not set -# CONFIG_TEE is not set -# CONFIG_TEGRA_AHB is not set -# CONFIG_TEGRA_HOST1X is not set -# CONFIG_TEHUTI is not set -# CONFIG_TERANETICS_PHY is not set -# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set -# CONFIG_TEST_BITFIELD is not set -# CONFIG_TEST_BITMAP is not set -# CONFIG_TEST_BITOPS is not set -# CONFIG_TEST_BLACKHOLE_DEV is not set -# CONFIG_TEST_BPF is not set -# CONFIG_TEST_FIRMWARE is not set -# CONFIG_TEST_FREE_PAGES is not set -# CONFIG_TEST_HASH is not set -# CONFIG_TEST_HEXDUMP is not set -# CONFIG_TEST_IDA is not set -# CONFIG_TEST_KASAN_MODULE is not set -# CONFIG_TEST_KMOD is not set -# CONFIG_TEST_KSTRTOX is not set -# CONFIG_TEST_LIST_SORT is not set -# CONFIG_TEST_LKM is not set -# CONFIG_TEST_LOCKUP is not set -# CONFIG_TEST_MEMCAT_P is not set -# CONFIG_TEST_MEMINIT is not set -# CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_OVERFLOW is not set -# CONFIG_TEST_POWER is not set -# CONFIG_TEST_PRINTF is not set -# CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_SORT is not set -# CONFIG_TEST_STACKINIT is not set -# CONFIG_TEST_STATIC_KEYS is not set -# CONFIG_TEST_STRING_HELPERS is not set -# CONFIG_TEST_STRSCPY is not set -# CONFIG_TEST_SYSCTL is not set -# CONFIG_TEST_UBSAN is not set -# CONFIG_TEST_UDELAY is not set -# CONFIG_TEST_USER_COPY is not set -# CONFIG_TEST_UUID is not set -# CONFIG_TEST_VMALLOC is not set -# CONFIG_TEST_XARRAY is not set -CONFIG_TEXTSEARCH=y -# CONFIG_TEXTSEARCH_BM is not set -# CONFIG_TEXTSEARCH_FSM is not set -# CONFIG_TEXTSEARCH_KMP is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set -# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_EMULATION is not set -# CONFIG_THERMAL_GOV_BANG_BANG is not set -# CONFIG_THERMAL_GOV_FAIR_SHARE is not set -# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set -# CONFIG_THERMAL_GOV_USER_SPACE is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_THERMAL_MMIO is not set -# CONFIG_THERMAL_NETLINK is not set -# CONFIG_THERMAL_STATISTICS is not set -# CONFIG_THERMAL_WRITABLE_TRIPS is not set -# CONFIG_THINKPAD_ACPI is not set -CONFIG_THIN_ARCHIVES=y -# CONFIG_THRUSTMASTER_FF is not set -# CONFIG_THUMB2_KERNEL is not set -# CONFIG_THUNDERBOLT is not set -# CONFIG_THUNDER_NIC_BGX is not set -# CONFIG_THUNDER_NIC_PF is not set -# CONFIG_THUNDER_NIC_RGX is not set -# CONFIG_THUNDER_NIC_VF is not set -# CONFIG_TICK_CPU_ACCOUNTING is not set -CONFIG_TICK_ONESHOT=y -# CONFIG_TIFM_CORE is not set -# CONFIG_TIGON3 is not set -# CONFIG_TIMB_DMA is not set -CONFIG_TIMERFD=y -# CONFIG_TIMER_STATS is not set -# CONFIG_TIME_NS is not set -# CONFIG_TINYDRM_HX8357D is not set -# CONFIG_TINYDRM_ILI9225 is not set -# CONFIG_TINYDRM_ILI9341 is not set -# CONFIG_TINYDRM_ILI9486 is not set -# CONFIG_TINYDRM_MI0283QT is not set -# CONFIG_TINYDRM_REPAPER is not set -# CONFIG_TINYDRM_ST7586 is not set -# CONFIG_TINYDRM_ST7735R is not set -CONFIG_TINY_RCU=y -# CONFIG_TIPC is not set -# CONFIG_TI_ADC081C is not set -# CONFIG_TI_ADC0832 is not set -# CONFIG_TI_ADC084S021 is not set -# CONFIG_TI_ADC108S102 is not set -# CONFIG_TI_ADC12138 is not set -# CONFIG_TI_ADC128S052 is not set -# CONFIG_TI_ADC161S626 is not set -# CONFIG_TI_ADS1015 is not set -# CONFIG_TI_ADS124S08 is not set -# CONFIG_TI_ADS7950 is not set -# CONFIG_TI_ADS8344 is not set -# CONFIG_TI_ADS8688 is not set -# CONFIG_TI_AM335X_ADC is not set -# CONFIG_TI_CPSW is not set -# CONFIG_TI_CPSW_ALE is not set -# CONFIG_TI_CPSW_PHY_SEL is not set -# CONFIG_TI_CPTS is not set -# CONFIG_TI_DAC082S085 is not set -# CONFIG_TI_DAC5571 is not set -# CONFIG_TI_DAC7311 is not set -# CONFIG_TI_DAC7512 is not set -# CONFIG_TI_DAC7612 is not set -# CONFIG_TI_DAVINCI_CPDMA is not set -# CONFIG_TI_DAVINCI_MDIO is not set -# CONFIG_TI_ST is not set -# CONFIG_TI_SYSCON_RESET is not set -# CONFIG_TI_TLC4541 is not set -# CONFIG_TLAN is not set -# CONFIG_TLS is not set -# CONFIG_TMD_HERMES is not set -# CONFIG_TMP006 is not set -# CONFIG_TMP007 is not set -CONFIG_TMPFS=y -# CONFIG_TMPFS_INODE64 is not set -# CONFIG_TMPFS_POSIX_ACL is not set -CONFIG_TMPFS_XATTR=y -# CONFIG_TOPSTAR_LAPTOP is not set -# CONFIG_TORTURE_TEST is not set -# CONFIG_TOSHIBA_HAPS is not set -# CONFIG_TOUCHSCREEN_88PM860X is not set -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set -# CONFIG_TOUCHSCREEN_ADC is not set -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_AR1021_I2C is not set -# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set -# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set -# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set -# CONFIG_TOUCHSCREEN_BU21013 is not set -# CONFIG_TOUCHSCREEN_BU21029 is not set -# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set -# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set -# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set -# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set -# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_I2C is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set -# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -# CONFIG_TOUCHSCREEN_CYTTSP_I2C is not set -# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set -# CONFIG_TOUCHSCREEN_DA9034 is not set -# CONFIG_TOUCHSCREEN_DA9052 is not set -# CONFIG_TOUCHSCREEN_DYNAPRO is not set -# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_EGALAX is not set -# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set -# CONFIG_TOUCHSCREEN_EKTF2127 is not set -# CONFIG_TOUCHSCREEN_ELAN is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_EXC3000 is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GOODIX is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set -# CONFIG_TOUCHSCREEN_HIDEEP is not set -# CONFIG_TOUCHSCREEN_HP600 is not set -# CONFIG_TOUCHSCREEN_HP7XX is not set -# CONFIG_TOUCHSCREEN_HTCPEN is not set -# CONFIG_TOUCHSCREEN_ILI210X is not set -# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_IPAQ_MICRO is not set -# CONFIG_TOUCHSCREEN_IPROC is not set -# CONFIG_TOUCHSCREEN_IQS5XX is not set -# CONFIG_TOUCHSCREEN_LPC32XX is not set -# CONFIG_TOUCHSCREEN_MAX11801 is not set -# CONFIG_TOUCHSCREEN_MC13783 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set -# CONFIG_TOUCHSCREEN_MIGOR is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_MMS114 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_MX25 is not set -# CONFIG_TOUCHSCREEN_MXS_LRADC is not set -# CONFIG_TOUCHSCREEN_PCAP is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_PIXCIR is not set -# CONFIG_TOUCHSCREEN_PROPERTIES is not set -# CONFIG_TOUCHSCREEN_RASPBERRYPI_FW is not set -# CONFIG_TOUCHSCREEN_RM_TS is not set -# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set -# CONFIG_TOUCHSCREEN_RPI_FT5406 is not set -# CONFIG_TOUCHSCREEN_S3C2410 is not set -# CONFIG_TOUCHSCREEN_S6SY761 is not set -# CONFIG_TOUCHSCREEN_SILEAD is not set -# CONFIG_TOUCHSCREEN_SIS_I2C is not set -# CONFIG_TOUCHSCREEN_ST1232 is not set -# CONFIG_TOUCHSCREEN_STMFTS is not set -# CONFIG_TOUCHSCREEN_STMPE is not set -# CONFIG_TOUCHSCREEN_SUN4I is not set -# CONFIG_TOUCHSCREEN_SUR40 is not set -# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set -# CONFIG_TOUCHSCREEN_SX8654 is not set -# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_TPS6507X is not set -# CONFIG_TOUCHSCREEN_TS4800 is not set -# CONFIG_TOUCHSCREEN_TSC2004 is not set -# CONFIG_TOUCHSCREEN_TSC2005 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set -# CONFIG_TOUCHSCREEN_TSC200X_CORE is not set -# CONFIG_TOUCHSCREEN_TSC_SERIO is not set -# CONFIG_TOUCHSCREEN_UCB1400 is not set -# CONFIG_TOUCHSCREEN_USB_3M is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_USB_DMC_TSC10 is not set -# CONFIG_TOUCHSCREEN_USB_E2I is not set -# CONFIG_TOUCHSCREEN_USB_EASYTOUCH is not set -# CONFIG_TOUCHSCREEN_USB_EGALAX is not set -# CONFIG_TOUCHSCREEN_USB_ELO is not set -# CONFIG_TOUCHSCREEN_USB_ETT_TC45USB is not set -# CONFIG_TOUCHSCREEN_USB_ETURBO is not set -# CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH is not set -# CONFIG_TOUCHSCREEN_USB_GOTOP is not set -# CONFIG_TOUCHSCREEN_USB_GUNZE is not set -# CONFIG_TOUCHSCREEN_USB_IDEALTEK is not set -# CONFIG_TOUCHSCREEN_USB_IRTOUCH is not set -# CONFIG_TOUCHSCREEN_USB_ITM is not set -# CONFIG_TOUCHSCREEN_USB_JASTEC is not set -# CONFIG_TOUCHSCREEN_USB_NEXIO is not set -# CONFIG_TOUCHSCREEN_USB_PANJIT is not set -# CONFIG_TOUCHSCREEN_USB_ZYTRONIC is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set -# CONFIG_TOUCHSCREEN_WACOM_I2C is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set -# CONFIG_TOUCHSCREEN_WM831X is not set -# CONFIG_TOUCHSCREEN_WM9705 is not set -# CONFIG_TOUCHSCREEN_WM9712 is not set -# CONFIG_TOUCHSCREEN_WM9713 is not set -# CONFIG_TOUCHSCREEN_WM97XX is not set -# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set -# CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE is not set -# CONFIG_TOUCHSCREEN_ZET6223 is not set -# CONFIG_TOUCHSCREEN_ZFORCE is not set -# CONFIG_TOUCHSCREEN_ZINITIX is not set -# CONFIG_TPL0102 is not set -# CONFIG_TPS6105X is not set -# CONFIG_TPS65010 is not set -# CONFIG_TPS6507X is not set -# CONFIG_TRACEPOINT_BENCHMARK is not set -# CONFIG_TRACER_SNAPSHOT is not set -# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set -# CONFIG_TRACE_EVENT_INJECT is not set -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_TRACE_SINK is not set -# CONFIG_TRACING_EVENTS_GPIO is not set -CONFIG_TRACING_SUPPORT=y -CONFIG_TRAD_SIGNALS=y -# CONFIG_TRANSPARENT_HUGEPAGE is not set -# CONFIG_TREE_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set -# CONFIG_TRUSTED_FOUNDATIONS is not set -# CONFIG_TRUSTED_KEYS is not set -# CONFIG_TSL2583 is not set -# CONFIG_TSL2772 is not set -# CONFIG_TSL2x7x is not set -# CONFIG_TSL4531 is not set -# CONFIG_TSYS01 is not set -# CONFIG_TSYS02D is not set -# CONFIG_TTPCI_EEPROM is not set -CONFIG_TTY=y -# CONFIG_TTY_PRINTK is not set -# CONFIG_TUN is not set -# CONFIG_TUN_VNET_CROSS_LE is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TWL4030_MADC is not set -# CONFIG_TWL6030_GPADC is not set -# CONFIG_TWL6040_CORE is not set -# CONFIG_TYPEC is not set -# CONFIG_TYPEC_TCPM is not set -# CONFIG_TYPEC_UCSI is not set -# CONFIG_TYPHOON is not set -# CONFIG_UACCESS_WITH_MEMCPY is not set -# CONFIG_UBIFS_ATIME_SUPPORT is not set -# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -# CONFIG_UBIFS_FS_AUTHENTICATION is not set -# CONFIG_UBIFS_FS_ENCRYPTION is not set -CONFIG_UBIFS_FS_LZO=y -# CONFIG_UBIFS_FS_SECURITY is not set -CONFIG_UBIFS_FS_XATTR=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UBIFS_FS_ZSTD=y -# CONFIG_UBSAN is not set -CONFIG_UBSAN_ALIGNMENT=y -# CONFIG_UBSAN_MISC is not set -# CONFIG_UCB1400_CORE is not set -# CONFIG_UCSI is not set -# CONFIG_UDF_FS is not set -# CONFIG_UDMABUF is not set -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_UFS_FS is not set -# CONFIG_UHID is not set -CONFIG_UID16=y -# CONFIG_UIO is not set -# CONFIG_ULTRA is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_UNICODE is not set -# CONFIG_UNISYSSPAR is not set -# CONFIG_UNISYS_VISORBUS is not set -CONFIG_UNIX=y -CONFIG_UNIX98_PTYS=y -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_UNIX_DIAG is not set -CONFIG_UNIX_SCM=y -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_UNWINDER_FRAME_POINTER is not set -# CONFIG_UPROBES is not set -# CONFIG_UPROBE_EVENTS is not set -# CONFIG_US5182D is not set -# CONFIG_USB is not set -# CONFIG_USB4 is not set -# CONFIG_USBIP_CORE is not set -CONFIG_USBIP_VHCI_HC_PORTS=8 -CONFIG_USBIP_VHCI_NR_HCS=1 -# CONFIG_USBIP_VUDC is not set -# CONFIG_USBPCWATCHDOG is not set -# CONFIG_USB_ACM is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AIRSPY is not set -CONFIG_USB_ALI_M5632=y -# CONFIG_USB_AMD5536UDC is not set -CONFIG_USB_AN2720=y -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set -# CONFIG_USB_APPLEDISPLAY is not set -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARMLINUX=y -# CONFIG_USB_ATM is not set -CONFIG_USB_AUTOSUSPEND_DELAY=2 -# CONFIG_USB_BDC_UDC is not set -CONFIG_USB_BELKIN=y -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_CATC is not set -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_CDNS3 is not set -# CONFIG_USB_CHAOSKEY is not set -# CONFIG_USB_CHIPIDEA is not set -# CONFIG_USB_CHIPIDEA_GENERIC is not set -# CONFIG_USB_CHIPIDEA_IMX is not set -# CONFIG_USB_CHIPIDEA_MSM is not set -# CONFIG_USB_CHIPIDEA_PCI is not set -# CONFIG_USB_CHIPIDEA_TEGRA is not set -# CONFIG_USB_CONFIGFS is not set -# CONFIG_USB_CONN_GPIO is not set -# CONFIG_USB_CXACRU is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -CONFIG_USB_DEFAULT_PERSIST=y -# CONFIG_USB_DSBR is not set -# CONFIG_USB_DUMMY_HCD is not set -# CONFIG_USB_DWC2 is not set -# CONFIG_USB_DWC2_DEBUG is not set -# CONFIG_USB_DWC2_DUAL_ROLE is not set -# CONFIG_USB_DWC2_HOST is not set -# CONFIG_USB_DWC2_PERIPHERAL is not set -# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set -# CONFIG_USB_DWC3 is not set -# CONFIG_USB_DWC3_EXYNOS is not set -# CONFIG_USB_DWC3_HAPS is not set -# CONFIG_USB_DWC3_KEYSTONE is not set -# CONFIG_USB_DWC3_OF_SIMPLE is not set -# CONFIG_USB_DWC3_PCI is not set -# CONFIG_USB_DWC3_QCOM is not set -# CONFIG_USB_DWC3_ULPI is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_EG20T is not set -# CONFIG_USB_EHCI_ATH79 is not set -# CONFIG_USB_EHCI_FSL is not set -# CONFIG_USB_EHCI_HCD is not set -# CONFIG_USB_EHCI_HCD_AT91 is not set -# CONFIG_USB_EHCI_HCD_OMAP is not set -# CONFIG_USB_EHCI_HCD_PPC_OF is not set -# CONFIG_USB_EHCI_MSM is not set -# CONFIG_USB_EHCI_MV is not set -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_EHSET_TEST_FIXTURE is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EPSON2888 is not set -# CONFIG_USB_ETH is not set -# CONFIG_USB_EZUSB_FX2 is not set -# CONFIG_USB_FEW_INIT_RETRIES is not set -# CONFIG_USB_FOTG210_HCD is not set -# CONFIG_USB_FOTG210_UDC is not set -# CONFIG_USB_FSL_USB2 is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_FUNCTIONFS is not set -# CONFIG_USB_FUSB300 is not set -# CONFIG_USB_GADGET is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 -CONFIG_USB_GADGET_VBUS_DRAW=2 -# CONFIG_USB_GADGET_XILINX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GOKU is not set -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_USB_GR_UDC is not set -# CONFIG_USB_GSPCA is not set -# CONFIG_USB_GSPCA_BENQ is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_CPIA1 is not set -# CONFIG_USB_GSPCA_DTCS033 is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_JL2005BCD is not set -# CONFIG_USB_GSPCA_KINECT is not set -# CONFIG_USB_GSPCA_KONICA is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_NW80X is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_OV534_9 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7302 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SE401 is not set -# CONFIG_USB_GSPCA_SN9C2028 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA1528 is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_SQ930X is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_STK1135 is not set -# CONFIG_USB_GSPCA_STV0680 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TOPRO is not set -# CONFIG_USB_GSPCA_TOUPTEK is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_VICAM is not set -# CONFIG_USB_GSPCA_XIRLINK_CIT is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_USB_G_ACM_MS is not set -# CONFIG_USB_G_DBGP is not set -# CONFIG_USB_G_HID is not set -# CONFIG_USB_G_MULTI is not set -# CONFIG_USB_G_NCM is not set -# CONFIG_USB_G_NOKIA is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_G_WEBCAM is not set -# CONFIG_USB_HACKRF is not set -# CONFIG_USB_HCD_TEST_MODE is not set -# CONFIG_USB_HID is not set -# CONFIG_USB_HIDDEV is not set -# CONFIG_USB_HSIC_USB3503 is not set -# CONFIG_USB_HSIC_USB4604 is not set -# CONFIG_USB_HSO is not set -# CONFIG_USB_HUB_USB251XB is not set -# CONFIG_USB_HWA_HCD is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_IMX21_HCD is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_IPHETH is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1301 is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_ISP1760 is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_KBD is not set -# CONFIG_USB_KC2190 is not set -# CONFIG_USB_LAN78XX is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LGM_PHY is not set -# CONFIG_USB_LINK_LAYER_TEST is not set -# CONFIG_USB_M5602 is not set -# CONFIG_USB_M66592 is not set -# CONFIG_USB_MASS_STORAGE is not set -# CONFIG_USB_MAX3420_UDC is not set -# CONFIG_USB_MAX3421_HCD is not set -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_MOUSE is not set -# CONFIG_USB_MSI2500 is not set -# CONFIG_USB_MSM_OTG is not set -# CONFIG_USB_MTU3 is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_MV_U3D is not set -# CONFIG_USB_MV_UDC is not set -# CONFIG_USB_MXS_PHY is not set -# CONFIG_USB_NET2272 is not set -# CONFIG_USB_NET2280 is not set -# CONFIG_USB_NET_AQC111 is not set -# CONFIG_USB_NET_AX88179_178A is not set -# CONFIG_USB_NET_AX8817X is not set -# CONFIG_USB_NET_CDCETHER is not set -# CONFIG_USB_NET_CDC_EEM is not set -# CONFIG_USB_NET_CDC_MBIM is not set -# CONFIG_USB_NET_CDC_NCM is not set -# CONFIG_USB_NET_CDC_SUBSET is not set -# CONFIG_USB_NET_CH9200 is not set -# CONFIG_USB_NET_CX82310_ETH is not set -# CONFIG_USB_NET_DM9601 is not set -# CONFIG_USB_NET_DRIVERS is not set -# CONFIG_USB_NET_GL620A is not set -# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_USB_NET_KALMIA is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_NET1080 is not set -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_QMI_WWAN is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set -# CONFIG_USB_NET_SMSC75XX is not set -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_SR9700 is not set -# CONFIG_USB_NET_SR9800 is not set -# CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_OHCI_HCD is not set -# CONFIG_USB_OHCI_HCD_PCI is not set -# CONFIG_USB_OHCI_HCD_PPC_OF is not set -# CONFIG_USB_OHCI_HCD_PPC_OF_BE is not set -# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set -# CONFIG_USB_OHCI_HCD_SSB is not set -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set -# CONFIG_USB_OTG_FSM is not set -# CONFIG_USB_OTG_PRODUCTLIST is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_PCI is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_PHY is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_PWC_INPUT_EVDEV is not set -# CONFIG_USB_PXA27X is not set -# CONFIG_USB_R8A66597 is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_RAW_GADGET is not set -# CONFIG_USB_RCAR_PHY is not set -# CONFIG_USB_RENESAS_USBHS is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_ROLES_INTEL_XHCI is not set -# CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_RTL8152 is not set -# CONFIG_USB_S2255 is not set -# CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_CP210X is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_DEBUG is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_F81232 is not set -# CONFIG_USB_SERIAL_F8153X is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_GARMIN is not set -CONFIG_USB_SERIAL_GENERIC=y -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -CONFIG_USB_SERIAL_KEYSPAN_MPR=y -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -CONFIG_USB_SERIAL_KEYSPAN_USA19=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -CONFIG_USB_SERIAL_KEYSPAN_USA28=y -CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_METRO is not set -# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MXUPORT is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_QCAUX is not set -# CONFIG_USB_SERIAL_QT2 is not set -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_SAFE is not set -CONFIG_USB_SERIAL_SAFE_PADDED=y -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SIMPLE is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_SSU100 is not set -# CONFIG_USB_SERIAL_SYMBOL is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_UPD78F0730 is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_WISHBONE is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_XSENS_MT is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_SIERRA_NET is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_SNP_UDC_PLAT is not set -# CONFIG_USB_SPEEDTOUCH is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_ENE_UB6250 is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_REALTEK is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_USB_SWITCH_FSA9480 is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_TMC is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_UAS is not set -# CONFIG_USB_UEAGLEATM is not set -# CONFIG_USB_ULPI is not set -# CONFIG_USB_ULPI_BUS is not set -# CONFIG_USB_USBNET is not set -# CONFIG_USB_USS720 is not set -# CONFIG_USB_VIDEO_CLASS is not set -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -# CONFIG_USB_VL600 is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_WHCI_HCD is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set -# CONFIG_USB_XHCI_DBGCAP is not set -# CONFIG_USB_XHCI_HCD is not set -# CONFIG_USB_XHCI_MVEBU is not set -# CONFIG_USB_XHCI_PCI_RENESAS is not set -# CONFIG_USB_XUSBATM is not set -# CONFIG_USB_YUREX is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_ZERO is not set -# CONFIG_USB_ZR364XX is not set -# CONFIG_USELIB is not set -# CONFIG_USERFAULTFD is not set -# CONFIG_USERIO is not set -# CONFIG_USE_OF is not set -# CONFIG_UTS_NS is not set -# CONFIG_UWB is not set -# CONFIG_U_SERIAL_CONSOLE is not set -# CONFIG_V4L_MEM2MEM_DRIVERS is not set -# CONFIG_V4L_PLATFORM_DRIVERS is not set -# CONFIG_V4L_TEST_DRIVERS is not set -# CONFIG_VALIDATE_FS_PARSER is not set -# CONFIG_VBOXGUEST is not set -# CONFIG_VCNL3020 is not set -# CONFIG_VCNL4000 is not set -# CONFIG_VCNL4035 is not set -# CONFIG_VDPA is not set -CONFIG_VDSO=y -# CONFIG_VEML6030 is not set -# CONFIG_VEML6070 is not set -# CONFIG_VETH is not set -# CONFIG_VEXPRESS_CONFIG is not set -# CONFIG_VF610_ADC is not set -# CONFIG_VF610_DAC is not set -# CONFIG_VFAT_FS is not set -# CONFIG_VFIO is not set -# CONFIG_VGASTATE is not set -# CONFIG_VGA_ARB is not set -# CONFIG_VGA_SWITCHEROO is not set -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set -CONFIG_VHOST_MENU=y -# CONFIG_VHOST_NET is not set -# CONFIG_VHOST_VSOCK is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_VIDEO_AD5820 is not set -# CONFIG_VIDEO_AD9389B is not set -# CONFIG_VIDEO_ADP1653 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_ADV7183 is not set -# CONFIG_VIDEO_ADV7343 is not set -# CONFIG_VIDEO_ADV7393 is not set -# CONFIG_VIDEO_ADV748X is not set -# CONFIG_VIDEO_ADV7511 is not set -# CONFIG_VIDEO_ADV7604 is not set -# CONFIG_VIDEO_ADV7842 is not set -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_AK7375 is not set -# CONFIG_VIDEO_AK881X is not set -# CONFIG_VIDEO_AM437X_VPFE is not set -# CONFIG_VIDEO_ASPEED is not set -# CONFIG_VIDEO_ATMEL_ISC is not set -# CONFIG_VIDEO_ATMEL_ISI is not set -# CONFIG_VIDEO_AU0828 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT848 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_CADENCE is not set -# CONFIG_VIDEO_CAFE_CCIC is not set -# CONFIG_VIDEO_CS3308 is not set -# CONFIG_VIDEO_CS5345 is not set -# CONFIG_VIDEO_CS53L32A is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_CX2341X is not set -# CONFIG_VIDEO_CX25840 is not set -# CONFIG_VIDEO_CX88 is not set -# CONFIG_VIDEO_DEV is not set -# CONFIG_VIDEO_DM6446_CCDC is not set -# CONFIG_VIDEO_DT3155 is not set -# CONFIG_VIDEO_DW9714 is not set -# CONFIG_VIDEO_DW9768 is not set -# CONFIG_VIDEO_DW9807_VCM is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_ET8EK8 is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -# CONFIG_VIDEO_GO7007 is not set -# CONFIG_VIDEO_GS1662 is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_HEXIUM_GEMINI is not set -# CONFIG_VIDEO_HEXIUM_ORION is not set -# CONFIG_VIDEO_HI556 is not set -# CONFIG_VIDEO_I2C is not set -# CONFIG_VIDEO_IMX214 is not set -# CONFIG_VIDEO_IMX219 is not set -# CONFIG_VIDEO_IMX258 is not set -# CONFIG_VIDEO_IMX274 is not set -# CONFIG_VIDEO_IMX290 is not set -# CONFIG_VIDEO_IMX319 is not set -# CONFIG_VIDEO_IMX355 is not set -# CONFIG_VIDEO_IMX477 is not set -# CONFIG_VIDEO_IRS1125 is not set -# CONFIG_VIDEO_IR_I2C is not set -# CONFIG_VIDEO_IVTV is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_LM3560 is not set -# CONFIG_VIDEO_LM3646 is not set -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_M5MOLS is not set -# CONFIG_VIDEO_MAX9286 is not set -# CONFIG_VIDEO_ML86V7667 is not set -# CONFIG_VIDEO_MSP3400 is not set -# CONFIG_VIDEO_MT9M001 is not set -# CONFIG_VIDEO_MT9M032 is not set -# CONFIG_VIDEO_MT9M111 is not set -# CONFIG_VIDEO_MT9P031 is not set -# CONFIG_VIDEO_MT9T001 is not set -# CONFIG_VIDEO_MT9T112 is not set -# CONFIG_VIDEO_MT9V011 is not set -# CONFIG_VIDEO_MT9V032 is not set -# CONFIG_VIDEO_MT9V111 is not set -# CONFIG_VIDEO_MUX is not set -# CONFIG_VIDEO_MXB is not set -# CONFIG_VIDEO_NOON010PC30 is not set -# CONFIG_VIDEO_OMAP2_VOUT is not set -# CONFIG_VIDEO_OV13858 is not set -# CONFIG_VIDEO_OV2640 is not set -# CONFIG_VIDEO_OV2659 is not set -# CONFIG_VIDEO_OV2680 is not set -# CONFIG_VIDEO_OV2685 is not set -# CONFIG_VIDEO_OV2740 is not set -# CONFIG_VIDEO_OV5640 is not set -# CONFIG_VIDEO_OV5645 is not set -# CONFIG_VIDEO_OV5647 is not set -# CONFIG_VIDEO_OV5670 is not set -# CONFIG_VIDEO_OV5675 is not set -# CONFIG_VIDEO_OV5695 is not set -# CONFIG_VIDEO_OV6650 is not set -# CONFIG_VIDEO_OV7251 is not set -# CONFIG_VIDEO_OV7640 is not set -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_OV772X is not set -# CONFIG_VIDEO_OV7740 is not set -# CONFIG_VIDEO_OV8856 is not set -# CONFIG_VIDEO_OV9281 is not set -# CONFIG_VIDEO_OV9640 is not set -# CONFIG_VIDEO_OV9650 is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_RDACM20 is not set -# CONFIG_VIDEO_RJ54N1 is not set -# CONFIG_VIDEO_S5C73M3 is not set -# CONFIG_VIDEO_S5K4ECGX is not set -# CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_S5K6A3 is not set -# CONFIG_VIDEO_S5K6AA is not set -# CONFIG_VIDEO_SAA6588 is not set -# CONFIG_VIDEO_SAA6752HS is not set -# CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA711X is not set -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7134 is not set -# CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_SH_MOBILE_CEU is not set -# CONFIG_VIDEO_SMIAPP is not set -# CONFIG_VIDEO_SONY_BTF_MPX is not set -# CONFIG_VIDEO_SR030PC30 is not set -# CONFIG_VIDEO_STK1160_COMMON is not set -# CONFIG_VIDEO_ST_MIPID02 is not set -# CONFIG_VIDEO_TC358743 is not set -# CONFIG_VIDEO_TDA1997X is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_THS8200 is not set -# CONFIG_VIDEO_TIMBERDALE is not set -# CONFIG_VIDEO_TLV320AIC23B is not set -# CONFIG_VIDEO_TM6000 is not set -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TVP514X is not set -# CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_TVP7002 is not set -# CONFIG_VIDEO_TW2804 is not set -# CONFIG_VIDEO_TW9903 is not set -# CONFIG_VIDEO_TW9906 is not set -# CONFIG_VIDEO_TW9910 is not set -# CONFIG_VIDEO_UDA1342 is not set -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -# CONFIG_VIDEO_USBTV is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_VIDEO_V4L2 is not set -# CONFIG_VIDEO_VP27SMPX is not set -# CONFIG_VIDEO_VPX3220 is not set -# CONFIG_VIDEO_VS6624 is not set -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_WM8775 is not set -# CONFIG_VIDEO_XILINX is not set -# CONFIG_VIDEO_ZORAN is not set -# CONFIG_VIRTIO_BALLOON is not set -# CONFIG_VIRTIO_BLK_SCSI is not set -# CONFIG_VIRTIO_CONSOLE is not set -# CONFIG_VIRTIO_FS is not set -# CONFIG_VIRTIO_INPUT is not set -# CONFIG_VIRTIO_IOMMU is not set -CONFIG_VIRTIO_MENU=y -# CONFIG_VIRTIO_MMIO is not set -# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set -# CONFIG_VIRTIO_PCI is not set -# CONFIG_VIRTUALIZATION is not set -# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set -# CONFIG_VIRT_DRIVERS is not set -CONFIG_VIRT_TO_BUS=y -# CONFIG_VITESSE_PHY is not set -# CONFIG_VL53L0X_I2C is not set -# CONFIG_VL6180 is not set -CONFIG_VLAN_8021Q=y -# CONFIG_VLAN_8021Q_GVRP is not set -# CONFIG_VLAN_8021Q_MVRP is not set -# CONFIG_VME_BUS is not set -# CONFIG_VMSPLIT_1G is not set -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_2G_OPT is not set -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_3G_OPT is not set -# CONFIG_VMWARE_PVSCSI is not set -# CONFIG_VMXNET3 is not set -# CONFIG_VM_EVENT_COUNTERS is not set -# CONFIG_VOP_BUS is not set -# CONFIG_VORTEX is not set -# CONFIG_VSOCKETS is not set -# CONFIG_VSOCKETS_DIAG is not set -# CONFIG_VT is not set -# CONFIG_VT6655 is not set -# CONFIG_VT6656 is not set -# CONFIG_VXFS_FS is not set -# CONFIG_VXGE is not set -# CONFIG_VXLAN is not set -# CONFIG_VZ89X is not set -# CONFIG_W1 is not set -# CONFIG_W1_CON is not set -# CONFIG_W1_MASTER_DS1WM is not set -# CONFIG_W1_MASTER_DS2482 is not set -# CONFIG_W1_MASTER_DS2490 is not set -# CONFIG_W1_MASTER_GPIO is not set -# CONFIG_W1_MASTER_MATROX is not set -# CONFIG_W1_MASTER_SGI is not set -# CONFIG_W1_SLAVE_DS2405 is not set -# CONFIG_W1_SLAVE_DS2406 is not set -# CONFIG_W1_SLAVE_DS2408 is not set -# CONFIG_W1_SLAVE_DS2413 is not set -# CONFIG_W1_SLAVE_DS2423 is not set -# CONFIG_W1_SLAVE_DS2430 is not set -# CONFIG_W1_SLAVE_DS2431 is not set -# CONFIG_W1_SLAVE_DS2433 is not set -# CONFIG_W1_SLAVE_DS2438 is not set -# CONFIG_W1_SLAVE_DS250X is not set -# CONFIG_W1_SLAVE_DS2780 is not set -# CONFIG_W1_SLAVE_DS2781 is not set -# CONFIG_W1_SLAVE_DS2805 is not set -# CONFIG_W1_SLAVE_DS28E04 is not set -# CONFIG_W1_SLAVE_DS28E17 is not set -# CONFIG_W1_SLAVE_SMEM is not set -# CONFIG_W1_SLAVE_THERM is not set -# CONFIG_W83627HF_WDT is not set -# CONFIG_W83877F_WDT is not set -# CONFIG_W83977F_WDT is not set -# CONFIG_WAN is not set -# CONFIG_WANXL is not set -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_CORE is not set -CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y -# CONFIG_WATCHDOG_NOWAYOUT is not set -CONFIG_WATCHDOG_OPEN_TIMEOUT=0 -# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set -# CONFIG_WATCHDOG_SYSFS is not set -# CONFIG_WATCH_QUEUE is not set -# CONFIG_WD80x3 is not set -# CONFIG_WDAT_WDT is not set -# CONFIG_WDTPCI is not set -# CONFIG_WEXT_CORE is not set -# CONFIG_WEXT_PRIV is not set -# CONFIG_WEXT_PROC is not set -# CONFIG_WEXT_SPY is not set -CONFIG_WILINK_PLATFORM_DATA=y -# CONFIG_WIMAX is not set -# CONFIG_WIREGUARD is not set -CONFIG_WIRELESS=y -# CONFIG_WIRELESS_EXT is not set -# CONFIG_WIRELESS_WDS is not set -# CONFIG_WIZNET_W5100 is not set -# CONFIG_WIZNET_W5300 is not set -# CONFIG_WL1251 is not set -# CONFIG_WL12XX is not set -# CONFIG_WL18XX is not set -CONFIG_WLAN=y -# CONFIG_WLAN_VENDOR_ADMTEK is not set -# CONFIG_WLAN_VENDOR_ATH is not set -# CONFIG_WLAN_VENDOR_ATMEL is not set -# CONFIG_WLAN_VENDOR_BROADCOM is not set -# CONFIG_WLAN_VENDOR_CISCO is not set -# CONFIG_WLAN_VENDOR_INTEL is not set -# CONFIG_WLAN_VENDOR_INTERSIL is not set -# CONFIG_WLAN_VENDOR_MARVELL is not set -# CONFIG_WLAN_VENDOR_MEDIATEK is not set -# CONFIG_WLAN_VENDOR_MICROCHIP is not set -# CONFIG_WLAN_VENDOR_QUANTENNA is not set -# CONFIG_WLAN_VENDOR_RALINK is not set -# CONFIG_WLAN_VENDOR_REALTEK is not set -# CONFIG_WLAN_VENDOR_RSI is not set -# CONFIG_WLAN_VENDOR_ST is not set -# CONFIG_WLAN_VENDOR_TI is not set -# CONFIG_WLAN_VENDOR_ZYDAS is not set -# CONFIG_WLCORE is not set -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -# CONFIG_WQ_WATCHDOG is not set -# CONFIG_WW_MUTEX_SELFTEST is not set -# CONFIG_X25 is not set -# CONFIG_X509_CERTIFICATE_PARSER is not set -# CONFIG_X86_PKG_TEMP_THERMAL is not set -CONFIG_X86_SYSFB=y -# CONFIG_XDP_SOCKETS is not set -# CONFIG_XEN is not set -# CONFIG_XEN_GRANT_DMA_ALLOC is not set -# CONFIG_XEN_PVCALLS_FRONTEND is not set -CONFIG_XEN_SCRUB_PAGES_DEFAULT=y -CONFIG_XFRM=y -# CONFIG_XFRM_INTERFACE is not set -# CONFIG_XFRM_IPCOMP is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_USER is not set -# CONFIG_XFS_DEBUG is not set -# CONFIG_XFS_FS is not set -# CONFIG_XFS_ONLINE_SCRUB is not set -# CONFIG_XFS_POSIX_ACL is not set -# CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_RT is not set -# CONFIG_XFS_SUPPORT_V4 is not set -# CONFIG_XFS_WARN is not set -# CONFIG_XILINX_AXI_EMAC is not set -# CONFIG_XILINX_DMA is not set -# CONFIG_XILINX_EMACLITE is not set -# CONFIG_XILINX_GMII2RGMII is not set -# CONFIG_XILINX_LL_TEMAC is not set -# CONFIG_XILINX_SDFEC is not set -# CONFIG_XILINX_VCU is not set -# CONFIG_XILINX_WATCHDOG is not set -# CONFIG_XILINX_XADC is not set -# CONFIG_XILINX_ZYNQMP_DMA is not set -# CONFIG_XILINX_ZYNQMP_DPDMA is not set -# CONFIG_XILLYBUS is not set -# CONFIG_XIL_AXIS_FIFO is not set -# CONFIG_XIP_KERNEL is not set -# CONFIG_XMON is not set -CONFIG_XZ_DEC=y -# CONFIG_XZ_DEC_ARM is not set -# CONFIG_XZ_DEC_ARMTHUMB is not set -# CONFIG_XZ_DEC_BCJ is not set -# CONFIG_XZ_DEC_IA64 is not set -# CONFIG_XZ_DEC_POWERPC is not set -# CONFIG_XZ_DEC_SPARC is not set -# CONFIG_XZ_DEC_TEST is not set -# CONFIG_XZ_DEC_X86 is not set -# CONFIG_YAM is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_YENTA is not set -# CONFIG_YENTA_O2 is not set -# CONFIG_YENTA_RICOH is not set -# CONFIG_YENTA_TI is not set -# CONFIG_YENTA_TOSHIBA is not set -# CONFIG_ZBUD is not set -# CONFIG_ZD1211RW is not set -# CONFIG_ZD1211RW_DEBUG is not set -# CONFIG_ZEROPLUS_FF is not set -# CONFIG_ZIIRAVE_WATCHDOG is not set -# CONFIG_ZISOFS is not set -# CONFIG_ZLIB_DEFLATE is not set -# CONFIG_ZLIB_INFLATE is not set -CONFIG_ZONE_DMA=y -# CONFIG_ZOPT2201 is not set -# CONFIG_ZPA2326 is not set -# CONFIG_ZPOOL is not set -# CONFIG_ZRAM is not set -# CONFIG_ZRAM_MEMORY_TRACKING is not set -# CONFIG_ZSMALLOC is not set -# CONFIG_ZX_TDM is not set diff --git a/target/linux/generic/hack-5.10/100-update-mtk_wed_h.patch b/target/linux/generic/hack-5.10/100-update-mtk_wed_h.patch deleted file mode 100644 index 5f05179a36..0000000000 --- a/target/linux/generic/hack-5.10/100-update-mtk_wed_h.patch +++ /dev/null @@ -1,248 +0,0 @@ ---- a/include/linux/soc/mediatek/mtk_wed.h -+++ b/include/linux/soc/mediatek/mtk_wed.h -@@ -5,21 +5,77 @@ - #include - #include - #include -+#include -+#include - - #define MTK_WED_TX_QUEUES 2 -+#define MTK_WED_RX_QUEUES 2 -+ -+#define WED_WO_STA_REC 0x6 - - struct mtk_wed_hw; - struct mtk_wdma_desc; - -+enum mtk_wed_wo_cmd { -+ MTK_WED_WO_CMD_WED_CFG, -+ MTK_WED_WO_CMD_WED_RX_STAT, -+ MTK_WED_WO_CMD_RRO_SER, -+ MTK_WED_WO_CMD_DBG_INFO, -+ MTK_WED_WO_CMD_DEV_INFO, -+ MTK_WED_WO_CMD_BSS_INFO, -+ MTK_WED_WO_CMD_STA_REC, -+ MTK_WED_WO_CMD_DEV_INFO_DUMP, -+ MTK_WED_WO_CMD_BSS_INFO_DUMP, -+ MTK_WED_WO_CMD_STA_REC_DUMP, -+ MTK_WED_WO_CMD_BA_INFO_DUMP, -+ MTK_WED_WO_CMD_FBCMD_Q_DUMP, -+ MTK_WED_WO_CMD_FW_LOG_CTRL, -+ MTK_WED_WO_CMD_LOG_FLUSH, -+ MTK_WED_WO_CMD_CHANGE_STATE, -+ MTK_WED_WO_CMD_CPU_STATS_ENABLE, -+ MTK_WED_WO_CMD_CPU_STATS_DUMP, -+ MTK_WED_WO_CMD_EXCEPTION_INIT, -+ MTK_WED_WO_CMD_PROF_CTRL, -+ MTK_WED_WO_CMD_STA_BA_DUMP, -+ MTK_WED_WO_CMD_BA_CTRL_DUMP, -+ MTK_WED_WO_CMD_RXCNT_CTRL, -+ MTK_WED_WO_CMD_RXCNT_INFO, -+ MTK_WED_WO_CMD_SET_CAP, -+ MTK_WED_WO_CMD_CCIF_RING_DUMP, -+ MTK_WED_WO_CMD_WED_END -+}; -+ -+struct mtk_rxbm_desc { -+ __le32 buf0; -+ __le32 token; -+} __packed __aligned(4); -+ -+enum mtk_wed_bus_tye { -+ MTK_WED_BUS_PCIE, -+ MTK_WED_BUS_AXI, -+}; -+ -+#define MTK_WED_RING_CONFIGURED BIT(0) - struct mtk_wed_ring { - struct mtk_wdma_desc *desc; - dma_addr_t desc_phys; -+ u32 desc_size; - int size; -+ u32 flags; - - u32 reg_base; - void __iomem *wpdma; - }; - -+struct mtk_wed_wo_rx_stats { -+ __le16 wlan_idx; -+ __le16 tid; -+ __le32 rx_pkt_cnt; -+ __le32 rx_byte_cnt; -+ __le32 rx_err_cnt; -+ __le32 rx_drop_cnt; -+}; -+ - struct mtk_wed_device { - #ifdef CONFIG_NET_MEDIATEK_SOC_WED - const struct mtk_wed_ops *ops; -@@ -28,30 +84,76 @@ struct mtk_wed_device { - bool init_done, running; - int wdma_idx; - int irq; -+ u8 version; -+ -+ /* used by wlan driver */ -+ u32 rev_id; - - struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES]; -+ struct mtk_wed_ring rx_ring[MTK_WED_RX_QUEUES]; - struct mtk_wed_ring txfree_ring; - struct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES]; -+ struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES]; - - struct { - int size; - void **pages; - struct mtk_wdma_desc *desc; - dma_addr_t desc_phys; -- } buf_ring; -+ } tx_buf_ring; -+ -+ struct { -+ int size; -+ struct page_frag_cache rx_page; -+ struct mtk_rxbm_desc *desc; -+ dma_addr_t desc_phys; -+ } rx_buf_ring; -+ -+ struct { -+ struct mtk_wed_ring ring; -+ dma_addr_t miod_phys; -+ dma_addr_t fdbk_phys; -+ } rro; - - /* filled by driver: */ - struct { -- struct pci_dev *pci_dev; -+ union { -+ struct platform_device *platform_dev; -+ struct pci_dev *pci_dev; -+ }; -+ enum mtk_wed_bus_tye bus_type; -+ void __iomem *base; -+ u32 phy_base; - - u32 wpdma_phys; -+ u32 wpdma_int; -+ u32 wpdma_mask; -+ u32 wpdma_tx; -+ u32 wpdma_txfree; -+ u32 wpdma_rx_glo; -+ u32 wpdma_rx; -+ -+ bool wcid_512; - - u16 token_start; - unsigned int nbuf; -+ unsigned int rx_nbuf; -+ unsigned int rx_npkt; -+ unsigned int rx_size; -+ -+ u8 tx_tbit[MTK_WED_TX_QUEUES]; -+ u8 rx_tbit[MTK_WED_RX_QUEUES]; -+ u8 txfree_tbit; - - u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id); - int (*offload_enable)(struct mtk_wed_device *wed); - void (*offload_disable)(struct mtk_wed_device *wed); -+ u32 (*init_rx_buf)(struct mtk_wed_device *wed, int size); -+ void (*release_rx_buf)(struct mtk_wed_device *wed); -+ void (*update_wo_rx_stats)(struct mtk_wed_device *wed, -+ struct mtk_wed_wo_rx_stats *stats); -+ int (*reset)(struct mtk_wed_device *wed); -+ void (*reset_complete)(struct mtk_wed_device *wed); - } wlan; - #endif - }; -@@ -59,10 +161,16 @@ struct mtk_wed_device { - struct mtk_wed_ops { - int (*attach)(struct mtk_wed_device *dev); - int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring, -- void __iomem *regs); -+ void __iomem *regs, bool reset); -+ int (*rx_ring_setup)(struct mtk_wed_device *dev, int ring, -+ void __iomem *regs, bool reset); - int (*txfree_ring_setup)(struct mtk_wed_device *dev, - void __iomem *regs); -+ int (*msg_update)(struct mtk_wed_device *dev, int cmd_id, -+ void *data, int len); - void (*detach)(struct mtk_wed_device *dev); -+ void (*ppe_check)(struct mtk_wed_device *dev, struct sk_buff *skb, -+ u32 reason, u32 hash); - - void (*stop)(struct mtk_wed_device *dev); - void (*start)(struct mtk_wed_device *dev, u32 irq_mask); -@@ -73,6 +181,8 @@ struct mtk_wed_ops { - - u32 (*irq_get)(struct mtk_wed_device *dev, u32 mask); - void (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask); -+ int (*setup_tc)(struct mtk_wed_device *wed, struct net_device *dev, -+ enum tc_setup_type type, void *type_data); - }; - - extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops; -@@ -97,12 +207,22 @@ mtk_wed_device_attach(struct mtk_wed_dev - return ret; - } - -+static inline bool -+mtk_wed_get_rx_capa(struct mtk_wed_device *dev) -+{ -+#ifdef CONFIG_NET_MEDIATEK_SOC_WED -+ return dev->version != 1; -+#else -+ return false; -+#endif -+} -+ - #ifdef CONFIG_NET_MEDIATEK_SOC_WED - #define mtk_wed_device_active(_dev) !!(_dev)->ops - #define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev) - #define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask) --#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) \ -- (_dev)->ops->tx_ring_setup(_dev, _ring, _regs) -+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) \ -+ (_dev)->ops->tx_ring_setup(_dev, _ring, _regs, _reset) - #define mtk_wed_device_txfree_ring_setup(_dev, _regs) \ - (_dev)->ops->txfree_ring_setup(_dev, _regs) - #define mtk_wed_device_reg_read(_dev, _reg) \ -@@ -113,6 +233,16 @@ mtk_wed_device_attach(struct mtk_wed_dev - (_dev)->ops->irq_get(_dev, _mask) - #define mtk_wed_device_irq_set_mask(_dev, _mask) \ - (_dev)->ops->irq_set_mask(_dev, _mask) -+#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) \ -+ (_dev)->ops->rx_ring_setup(_dev, _ring, _regs, _reset) -+#define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) \ -+ (_dev)->ops->ppe_check(_dev, _skb, _reason, _hash) -+#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) \ -+ (_dev)->ops->msg_update(_dev, _id, _msg, _len) -+#define mtk_wed_device_stop(_dev) (_dev)->ops->stop(_dev) -+#define mtk_wed_device_dma_reset(_dev) (_dev)->ops->reset_dma(_dev) -+#define mtk_wed_device_setup_tc(_dev, _netdev, _type, _type_data) \ -+ (_dev)->ops->setup_tc(_dev, _netdev, _type, _type_data) - #else - static inline bool mtk_wed_device_active(struct mtk_wed_device *dev) - { -@@ -120,12 +250,18 @@ static inline bool mtk_wed_device_active - } - #define mtk_wed_device_detach(_dev) do {} while (0) - #define mtk_wed_device_start(_dev, _mask) do {} while (0) --#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) -ENODEV -+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV - #define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV - #define mtk_wed_device_reg_read(_dev, _reg) 0 - #define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0) - #define mtk_wed_device_irq_get(_dev, _mask) 0 - #define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0) -+#define mtk_wed_device_rx_ring_setup(_dev, _ring, _regs, _reset) -ENODEV -+#define mtk_wed_device_ppe_check(_dev, _skb, _reason, _hash) do {} while (0) -+#define mtk_wed_device_update_msg(_dev, _id, _msg, _len) -ENODEV -+#define mtk_wed_device_stop(_dev) do {} while (0) -+#define mtk_wed_device_dma_reset(_dev) do {} while (0) -+#define mtk_wed_device_setup_tc(_dev, _netdev, _type, _type_data) -EOPNOTSUPP - #endif - - #endif diff --git a/target/linux/generic/hack-5.10/204-module_strip.patch b/target/linux/generic/hack-5.10/204-module_strip.patch deleted file mode 100644 index 1dc3eb2752..0000000000 --- a/target/linux/generic/hack-5.10/204-module_strip.patch +++ /dev/null @@ -1,212 +0,0 @@ -From a779a482fb9b9f8fcdf8b2519c789b4b9bb5dd05 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Fri, 7 Jul 2017 16:56:48 +0200 -Subject: build: add a hack for removing non-essential module info - -Signed-off-by: Felix Fietkau ---- - include/linux/module.h | 13 ++++++++----- - include/linux/moduleparam.h | 15 ++++++++++++--- - init/Kconfig | 7 +++++++ - kernel/module.c | 5 ++++- - scripts/mod/modpost.c | 12 ++++++++++++ - 5 files changed, 43 insertions(+), 9 deletions(-) - ---- a/include/linux/module.h -+++ b/include/linux/module.h -@@ -161,6 +161,7 @@ extern void cleanup_module(void); - - /* Generic info of form tag = "info" */ - #define MODULE_INFO(tag, info) __MODULE_INFO(tag, tag, info) -+#define MODULE_INFO_STRIP(tag, info) __MODULE_INFO_STRIP(tag, tag, info) - - /* For userspace: you can also call me... */ - #define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias) -@@ -230,12 +231,12 @@ extern void cleanup_module(void); - * Author(s), use "Name " or just "Name", for multiple - * authors use multiple MODULE_AUTHOR() statements/lines. - */ --#define MODULE_AUTHOR(_author) MODULE_INFO(author, _author) -+#define MODULE_AUTHOR(_author) MODULE_INFO_STRIP(author, _author) - - /* What your module does. */ --#define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description) -+#define MODULE_DESCRIPTION(_description) MODULE_INFO_STRIP(description, _description) - --#ifdef MODULE -+#if defined(MODULE) && !defined(CONFIG_MODULE_STRIPPED) - /* Creates an alias so file2alias.c can find device table. */ - #define MODULE_DEVICE_TABLE(type, name) \ - extern typeof(name) __mod_##type##__##name##_device_table \ -@@ -262,7 +263,9 @@ extern typeof(name) __mod_##type##__##na - */ - - #if defined(MODULE) || !defined(CONFIG_SYSFS) --#define MODULE_VERSION(_version) MODULE_INFO(version, _version) -+#define MODULE_VERSION(_version) MODULE_INFO_STRIP(version, _version) -+#elif defined(CONFIG_MODULE_STRIPPED) -+#define MODULE_VERSION(_version) __MODULE_INFO_DISABLED(version) - #else - #define MODULE_VERSION(_version) \ - MODULE_INFO(version, _version); \ -@@ -285,7 +288,7 @@ extern typeof(name) __mod_##type##__##na - /* Optional firmware file (or files) needed by the module - * format is simply firmware file name. Multiple firmware - * files require multiple MODULE_FIRMWARE() specifiers */ --#define MODULE_FIRMWARE(_firmware) MODULE_INFO(firmware, _firmware) -+#define MODULE_FIRMWARE(_firmware) MODULE_INFO_STRIP(firmware, _firmware) - - #define MODULE_IMPORT_NS(ns) MODULE_INFO(import_ns, #ns) - ---- a/include/linux/moduleparam.h -+++ b/include/linux/moduleparam.h -@@ -20,6 +20,16 @@ - /* Chosen so that structs with an unsigned long line up. */ - #define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long)) - -+/* This struct is here for syntactic coherency, it is not used */ -+#define __MODULE_INFO_DISABLED(name) \ -+ struct __UNIQUE_ID(name) {} -+ -+#ifdef CONFIG_MODULE_STRIPPED -+#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO_DISABLED(name) -+#else -+#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO(tag, name, info) -+#endif -+ - #define __MODULE_INFO(tag, name, info) \ - static const char __UNIQUE_ID(name)[] \ - __used __section(".modinfo") __attribute__((unused, aligned(1))) \ -@@ -31,7 +41,7 @@ static const char __UNIQUE_ID(name)[] - /* One for each parameter, describing how to use it. Some files do - multiple of these per line, so can't just use MODULE_INFO. */ - #define MODULE_PARM_DESC(_parm, desc) \ -- __MODULE_INFO(parm, _parm, #_parm ":" desc) -+ __MODULE_INFO_STRIP(parm, _parm, #_parm ":" desc) - - struct kernel_param; - ---- a/init/Kconfig -+++ b/init/Kconfig -@@ -2364,6 +2364,13 @@ config UNUSED_KSYMS_WHITELIST - one per line. The path can be absolute, or relative to the kernel - source tree. - -+config MODULE_STRIPPED -+ bool "Reduce module size" -+ depends on MODULES -+ help -+ Remove module parameter descriptions, author info, version, aliases, -+ device tables, etc. -+ - endif # MODULES - - config MODULES_TREE_LOOKUP ---- a/kernel/module.c -+++ b/kernel/module.c -@@ -1285,6 +1285,7 @@ static struct module_attribute *modinfo_ - - static const char vermagic[] = VERMAGIC_STRING; - -+#if defined(CONFIG_MODVERSIONS) || !defined(CONFIG_MODULE_STRIPPED) - static int try_to_force_load(struct module *mod, const char *reason) - { - #ifdef CONFIG_MODULE_FORCE_LOAD -@@ -1296,6 +1297,7 @@ static int try_to_force_load(struct modu - return -ENOEXEC; - #endif - } -+#endif - - #ifdef CONFIG_MODVERSIONS - -@@ -3251,9 +3253,11 @@ static int setup_load_info(struct load_i - - static int check_modinfo(struct module *mod, struct load_info *info, int flags) - { -- const char *modmagic = get_modinfo(info, "vermagic"); - int err; - -+#ifndef CONFIG_MODULE_STRIPPED -+ const char *modmagic = get_modinfo(info, "vermagic"); -+ - if (flags & MODULE_INIT_IGNORE_VERMAGIC) - modmagic = NULL; - -@@ -3274,6 +3278,7 @@ static int check_modinfo(struct module * - mod->name); - add_taint_module(mod, TAINT_OOT_MODULE, LOCKDEP_STILL_OK); - } -+#endif - - check_modinfo_retpoline(mod, info); - ---- a/scripts/mod/modpost.c -+++ b/scripts/mod/modpost.c -@@ -2040,7 +2040,9 @@ static void read_symbols(const char *mod - symname = remove_dot(info.strtab + sym->st_name); - - handle_symbol(mod, &info, sym, symname); -+#ifndef CONFIG_MODULE_STRIPPED - handle_moddevtable(mod, &info, sym, symname); -+#endif - } - - for (sym = info.symtab_start; sym < info.symtab_stop; sym++) { -@@ -2253,8 +2255,10 @@ static void add_header(struct buffer *b, - buf_printf(b, "\n"); - buf_printf(b, "BUILD_SALT;\n"); - buf_printf(b, "\n"); -+#ifndef CONFIG_MODULE_STRIPPED - buf_printf(b, "MODULE_INFO(vermagic, VERMAGIC_STRING);\n"); - buf_printf(b, "MODULE_INFO(name, KBUILD_MODNAME);\n"); -+#endif - buf_printf(b, "\n"); - buf_printf(b, "__visible struct module __this_module\n"); - buf_printf(b, "__section(\".gnu.linkonce.this_module\") = {\n"); -@@ -2271,8 +2275,10 @@ static void add_header(struct buffer *b, - - static void add_intree_flag(struct buffer *b, int is_intree) - { -+#ifndef CONFIG_MODULE_STRIPPED - if (is_intree) - buf_printf(b, "\nMODULE_INFO(intree, \"Y\");\n"); -+#endif - } - - /* Cannot check for assembler */ -@@ -2285,8 +2291,10 @@ static void add_retpoline(struct buffer - - static void add_staging_flag(struct buffer *b, const char *name) - { -+#ifndef CONFIG_MODULE_STRIPPED - if (strstarts(name, "drivers/staging")) - buf_printf(b, "\nMODULE_INFO(staging, \"Y\");\n"); -+#endif - } - - /** -@@ -2370,11 +2378,13 @@ static void add_depends(struct buffer *b - - static void add_srcversion(struct buffer *b, struct module *mod) - { -+#ifndef CONFIG_MODULE_STRIPPED - if (mod->srcversion[0]) { - buf_printf(b, "\n"); - buf_printf(b, "MODULE_INFO(srcversion, \"%s\");\n", - mod->srcversion); - } -+#endif - } - - static void write_buf(struct buffer *b, const char *fname) -@@ -2633,7 +2643,9 @@ int main(int argc, char **argv) - add_staging_flag(&buf, mod->name); - err |= add_versions(&buf, mod); - add_depends(&buf, mod); -+#ifndef CONFIG_MODULE_STRIPPED - add_moddevtable(&buf, mod); -+#endif - add_srcversion(&buf, mod); - - sprintf(fname, "%s.mod.c", mod->name); diff --git a/target/linux/generic/hack-5.10/205-kconfig-abort-configuration-on-unset-symbol.patch b/target/linux/generic/hack-5.10/205-kconfig-abort-configuration-on-unset-symbol.patch deleted file mode 100644 index bd5c54d4b8..0000000000 --- a/target/linux/generic/hack-5.10/205-kconfig-abort-configuration-on-unset-symbol.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 310e8e04a05d9eb43fa9dd7f00143300afcaa37a Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Fri, 11 Nov 2022 13:33:44 +0100 -Subject: [PATCH] kconfig: abort configuration on unset symbol - -When a target configuration has unset Kconfig symbols, the build will -fail when OpenWrt is compiled with V=s and stdin is connected to a tty. - -In case OpenWrt is compiled without either of these preconditions, the -build will succeed with the symbols in question being unset. - -Modify the kernel configuration in a way it fails on unset symbols -regardless of the aforementioned preconditions. - -Signed-off-by: David Bauer ---- - scripts/kconfig/conf.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/scripts/kconfig/conf.c -+++ b/scripts/kconfig/conf.c -@@ -109,6 +109,9 @@ static int conf_askvalue(struct symbol * - } - /* fall through */ - case oldaskconfig: -+ if (!tty_stdio && getenv("FAIL_ON_UNCONFIGURED")) { -+ exit(1); -+ } - fflush(stdout); - xfgets(line, sizeof(line), stdin); - return 1; -@@ -303,6 +306,9 @@ static int conf_choice(struct menu *menu - } - /* fall through */ - case oldaskconfig: -+ if (!tty_stdio && getenv("FAIL_ON_UNCONFIGURED")) { -+ exit(1); -+ } - fflush(stdout); - xfgets(line, sizeof(line), stdin); - strip(line); diff --git a/target/linux/generic/hack-5.10/210-darwin_scripts_include.patch b/target/linux/generic/hack-5.10/210-darwin_scripts_include.patch deleted file mode 100644 index be6adc0d11..0000000000 --- a/target/linux/generic/hack-5.10/210-darwin_scripts_include.patch +++ /dev/null @@ -1,3053 +0,0 @@ -From db7c30dcd9a0391bf13b62c9f91e144d762ef43a Mon Sep 17 00:00:00 2001 -From: Florian Fainelli -Date: Fri, 7 Jul 2017 17:00:49 +0200 -Subject: Add an OSX specific patch to make the kernel be compiled - -lede-commit: 3fc2a24f0422b2f55f9ed43f116db3111f700526 -Signed-off-by: Florian Fainelli ---- - scripts/kconfig/Makefile | 3 + - scripts/mod/elf.h | 3007 ++++++++++++++++++++++++++++++++++++++++++++ - scripts/mod/mk_elfconfig.c | 4 + - scripts/mod/modpost.h | 4 + - 4 files changed, 3018 insertions(+) - create mode 100644 scripts/mod/elf.h - ---- /dev/null -+++ b/scripts/mod/elf.h -@@ -0,0 +1,3007 @@ -+/* This file defines standard ELF types, structures, and macros. -+ Copyright (C) 1995-2012 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, see -+ . */ -+ -+#ifndef _ELF_H -+#define _ELF_H 1 -+ -+/* Standard ELF types. */ -+ -+#include -+ -+/* Type for a 16-bit quantity. */ -+typedef uint16_t Elf32_Half; -+typedef uint16_t Elf64_Half; -+ -+/* Types for signed and unsigned 32-bit quantities. */ -+typedef uint32_t Elf32_Word; -+typedef int32_t Elf32_Sword; -+typedef uint32_t Elf64_Word; -+typedef int32_t Elf64_Sword; -+ -+/* Types for signed and unsigned 64-bit quantities. */ -+typedef uint64_t Elf32_Xword; -+typedef int64_t Elf32_Sxword; -+typedef uint64_t Elf64_Xword; -+typedef int64_t Elf64_Sxword; -+ -+/* Type of addresses. */ -+typedef uint32_t Elf32_Addr; -+typedef uint64_t Elf64_Addr; -+ -+/* Type of file offsets. */ -+typedef uint32_t Elf32_Off; -+typedef uint64_t Elf64_Off; -+ -+/* Type for section indices, which are 16-bit quantities. */ -+typedef uint16_t Elf32_Section; -+typedef uint16_t Elf64_Section; -+ -+/* Type for version symbol information. */ -+typedef Elf32_Half Elf32_Versym; -+typedef Elf64_Half Elf64_Versym; -+ -+ -+/* The ELF file header. This appears at the start of every ELF file. */ -+ -+#define EI_NIDENT (16) -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf32_Half e_type; /* Object file type */ -+ Elf32_Half e_machine; /* Architecture */ -+ Elf32_Word e_version; /* Object file version */ -+ Elf32_Addr e_entry; /* Entry point virtual address */ -+ Elf32_Off e_phoff; /* Program header table file offset */ -+ Elf32_Off e_shoff; /* Section header table file offset */ -+ Elf32_Word e_flags; /* Processor-specific flags */ -+ Elf32_Half e_ehsize; /* ELF header size in bytes */ -+ Elf32_Half e_phentsize; /* Program header table entry size */ -+ Elf32_Half e_phnum; /* Program header table entry count */ -+ Elf32_Half e_shentsize; /* Section header table entry size */ -+ Elf32_Half e_shnum; /* Section header table entry count */ -+ Elf32_Half e_shstrndx; /* Section header string table index */ -+} Elf32_Ehdr; -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf64_Half e_type; /* Object file type */ -+ Elf64_Half e_machine; /* Architecture */ -+ Elf64_Word e_version; /* Object file version */ -+ Elf64_Addr e_entry; /* Entry point virtual address */ -+ Elf64_Off e_phoff; /* Program header table file offset */ -+ Elf64_Off e_shoff; /* Section header table file offset */ -+ Elf64_Word e_flags; /* Processor-specific flags */ -+ Elf64_Half e_ehsize; /* ELF header size in bytes */ -+ Elf64_Half e_phentsize; /* Program header table entry size */ -+ Elf64_Half e_phnum; /* Program header table entry count */ -+ Elf64_Half e_shentsize; /* Section header table entry size */ -+ Elf64_Half e_shnum; /* Section header table entry count */ -+ Elf64_Half e_shstrndx; /* Section header string table index */ -+} Elf64_Ehdr; -+ -+/* Fields in the e_ident array. The EI_* macros are indices into the -+ array. The macros under each EI_* macro are the values the byte -+ may have. */ -+ -+#define EI_MAG0 0 /* File identification byte 0 index */ -+#define ELFMAG0 0x7f /* Magic number byte 0 */ -+ -+#define EI_MAG1 1 /* File identification byte 1 index */ -+#define ELFMAG1 'E' /* Magic number byte 1 */ -+ -+#define EI_MAG2 2 /* File identification byte 2 index */ -+#define ELFMAG2 'L' /* Magic number byte 2 */ -+ -+#define EI_MAG3 3 /* File identification byte 3 index */ -+#define ELFMAG3 'F' /* Magic number byte 3 */ -+ -+/* Conglomeration of the identification bytes, for easy testing as a word. */ -+#define ELFMAG "\177ELF" -+#define SELFMAG 4 -+ -+#define EI_CLASS 4 /* File class byte index */ -+#define ELFCLASSNONE 0 /* Invalid class */ -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+#define ELFCLASSNUM 3 -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATANONE 0 /* Invalid data encoding */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ -+#define ELFDATANUM 3 -+ -+#define EI_VERSION 6 /* File version byte index */ -+ /* Value must be EV_CURRENT */ -+ -+#define EI_OSABI 7 /* OS ABI identification */ -+#define ELFOSABI_NONE 0 /* UNIX System V ABI */ -+#define ELFOSABI_SYSV 0 /* Alias. */ -+#define ELFOSABI_HPUX 1 /* HP-UX */ -+#define ELFOSABI_NETBSD 2 /* NetBSD. */ -+#define ELFOSABI_GNU 3 /* Object uses GNU ELF extensions. */ -+#define ELFOSABI_LINUX ELFOSABI_GNU /* Compatibility alias. */ -+#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ -+#define ELFOSABI_AIX 7 /* IBM AIX. */ -+#define ELFOSABI_IRIX 8 /* SGI Irix. */ -+#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ -+#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ -+#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ -+#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ -+#define ELFOSABI_ARM_AEABI 64 /* ARM EABI */ -+#define ELFOSABI_ARM 97 /* ARM */ -+#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ -+ -+#define EI_ABIVERSION 8 /* ABI version */ -+ -+#define EI_PAD 9 /* Byte index of padding bytes */ -+ -+/* Legal values for e_type (object file type). */ -+ -+#define ET_NONE 0 /* No file type */ -+#define ET_REL 1 /* Relocatable file */ -+#define ET_EXEC 2 /* Executable file */ -+#define ET_DYN 3 /* Shared object file */ -+#define ET_CORE 4 /* Core file */ -+#define ET_NUM 5 /* Number of defined types */ -+#define ET_LOOS 0xfe00 /* OS-specific range start */ -+#define ET_HIOS 0xfeff /* OS-specific range end */ -+#define ET_LOPROC 0xff00 /* Processor-specific range start */ -+#define ET_HIPROC 0xffff /* Processor-specific range end */ -+ -+/* Legal values for e_machine (architecture). */ -+ -+#define EM_NONE 0 /* No machine */ -+#define EM_M32 1 /* AT&T WE 32100 */ -+#define EM_SPARC 2 /* SUN SPARC */ -+#define EM_386 3 /* Intel 80386 */ -+#define EM_68K 4 /* Motorola m68k family */ -+#define EM_88K 5 /* Motorola m88k family */ -+#define EM_860 7 /* Intel 80860 */ -+#define EM_MIPS 8 /* MIPS R3000 big-endian */ -+#define EM_S370 9 /* IBM System/370 */ -+#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ -+ -+#define EM_PARISC 15 /* HPPA */ -+#define EM_VPP500 17 /* Fujitsu VPP500 */ -+#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ -+#define EM_960 19 /* Intel 80960 */ -+#define EM_PPC 20 /* PowerPC */ -+#define EM_PPC64 21 /* PowerPC 64-bit */ -+#define EM_S390 22 /* IBM S390 */ -+ -+#define EM_V800 36 /* NEC V800 series */ -+#define EM_FR20 37 /* Fujitsu FR20 */ -+#define EM_RH32 38 /* TRW RH-32 */ -+#define EM_RCE 39 /* Motorola RCE */ -+#define EM_ARM 40 /* ARM */ -+#define EM_FAKE_ALPHA 41 /* Digital Alpha */ -+#define EM_SH 42 /* Hitachi SH */ -+#define EM_SPARCV9 43 /* SPARC v9 64-bit */ -+#define EM_TRICORE 44 /* Siemens Tricore */ -+#define EM_ARC 45 /* Argonaut RISC Core */ -+#define EM_H8_300 46 /* Hitachi H8/300 */ -+#define EM_H8_300H 47 /* Hitachi H8/300H */ -+#define EM_H8S 48 /* Hitachi H8S */ -+#define EM_H8_500 49 /* Hitachi H8/500 */ -+#define EM_IA_64 50 /* Intel Merced */ -+#define EM_MIPS_X 51 /* Stanford MIPS-X */ -+#define EM_COLDFIRE 52 /* Motorola Coldfire */ -+#define EM_68HC12 53 /* Motorola M68HC12 */ -+#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ -+#define EM_PCP 55 /* Siemens PCP */ -+#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ -+#define EM_NDR1 57 /* Denso NDR1 microprocessor */ -+#define EM_STARCORE 58 /* Motorola Start*Core processor */ -+#define EM_ME16 59 /* Toyota ME16 processor */ -+#define EM_ST100 60 /* STMicroelectronic ST100 processor */ -+#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ -+#define EM_X86_64 62 /* AMD x86-64 architecture */ -+#define EM_PDSP 63 /* Sony DSP Processor */ -+ -+#define EM_FX66 66 /* Siemens FX66 microcontroller */ -+#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ -+#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ -+#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ -+#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ -+#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ -+#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ -+#define EM_SVX 73 /* Silicon Graphics SVx */ -+#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ -+#define EM_VAX 75 /* Digital VAX */ -+#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ -+#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ -+#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ -+#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ -+#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ -+#define EM_HUANY 81 /* Harvard University machine-independent object files */ -+#define EM_PRISM 82 /* SiTera Prism */ -+#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ -+#define EM_FR30 84 /* Fujitsu FR30 */ -+#define EM_D10V 85 /* Mitsubishi D10V */ -+#define EM_D30V 86 /* Mitsubishi D30V */ -+#define EM_V850 87 /* NEC v850 */ -+#define EM_M32R 88 /* Mitsubishi M32R */ -+#define EM_MN10300 89 /* Matsushita MN10300 */ -+#define EM_MN10200 90 /* Matsushita MN10200 */ -+#define EM_PJ 91 /* picoJava */ -+#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ -+#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ -+#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ -+#define EM_TILEPRO 188 /* Tilera TILEPro */ -+#define EM_TILEGX 191 /* Tilera TILE-Gx */ -+#define EM_NUM 192 -+ -+/* If it is necessary to assign new unofficial EM_* values, please -+ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the -+ chances of collision with official or non-GNU unofficial values. */ -+ -+#define EM_ALPHA 0x9026 -+ -+/* Legal values for e_version (version). */ -+ -+#define EV_NONE 0 /* Invalid ELF version */ -+#define EV_CURRENT 1 /* Current version */ -+#define EV_NUM 2 -+ -+/* Section header. */ -+ -+typedef struct -+{ -+ Elf32_Word sh_name; /* Section name (string tbl index) */ -+ Elf32_Word sh_type; /* Section type */ -+ Elf32_Word sh_flags; /* Section flags */ -+ Elf32_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf32_Off sh_offset; /* Section file offset */ -+ Elf32_Word sh_size; /* Section size in bytes */ -+ Elf32_Word sh_link; /* Link to another section */ -+ Elf32_Word sh_info; /* Additional section information */ -+ Elf32_Word sh_addralign; /* Section alignment */ -+ Elf32_Word sh_entsize; /* Entry size if section holds table */ -+} Elf32_Shdr; -+ -+typedef struct -+{ -+ Elf64_Word sh_name; /* Section name (string tbl index) */ -+ Elf64_Word sh_type; /* Section type */ -+ Elf64_Xword sh_flags; /* Section flags */ -+ Elf64_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf64_Off sh_offset; /* Section file offset */ -+ Elf64_Xword sh_size; /* Section size in bytes */ -+ Elf64_Word sh_link; /* Link to another section */ -+ Elf64_Word sh_info; /* Additional section information */ -+ Elf64_Xword sh_addralign; /* Section alignment */ -+ Elf64_Xword sh_entsize; /* Entry size if section holds table */ -+} Elf64_Shdr; -+ -+/* Special section indices. */ -+ -+#define SHN_UNDEF 0 /* Undefined section */ -+#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ -+#define SHN_LOPROC 0xff00 /* Start of processor-specific */ -+#define SHN_BEFORE 0xff00 /* Order section before all others -+ (Solaris). */ -+#define SHN_AFTER 0xff01 /* Order section after all others -+ (Solaris). */ -+#define SHN_HIPROC 0xff1f /* End of processor-specific */ -+#define SHN_LOOS 0xff20 /* Start of OS-specific */ -+#define SHN_HIOS 0xff3f /* End of OS-specific */ -+#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ -+#define SHN_COMMON 0xfff2 /* Associated symbol is common */ -+#define SHN_XINDEX 0xffff /* Index is in extra table. */ -+#define SHN_HIRESERVE 0xffff /* End of reserved indices */ -+ -+/* Legal values for sh_type (section type). */ -+ -+#define SHT_NULL 0 /* Section header table entry unused */ -+#define SHT_PROGBITS 1 /* Program data */ -+#define SHT_SYMTAB 2 /* Symbol table */ -+#define SHT_STRTAB 3 /* String table */ -+#define SHT_RELA 4 /* Relocation entries with addends */ -+#define SHT_HASH 5 /* Symbol hash table */ -+#define SHT_DYNAMIC 6 /* Dynamic linking information */ -+#define SHT_NOTE 7 /* Notes */ -+#define SHT_NOBITS 8 /* Program space with no data (bss) */ -+#define SHT_REL 9 /* Relocation entries, no addends */ -+#define SHT_SHLIB 10 /* Reserved */ -+#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ -+#define SHT_INIT_ARRAY 14 /* Array of constructors */ -+#define SHT_FINI_ARRAY 15 /* Array of destructors */ -+#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ -+#define SHT_GROUP 17 /* Section group */ -+#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ -+#define SHT_NUM 19 /* Number of defined types. */ -+#define SHT_LOOS 0x60000000 /* Start OS-specific. */ -+#define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes. */ -+#define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ -+#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ -+#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ -+#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ -+#define SHT_SUNW_move 0x6ffffffa -+#define SHT_SUNW_COMDAT 0x6ffffffb -+#define SHT_SUNW_syminfo 0x6ffffffc -+#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ -+#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ -+#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ -+#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ -+#define SHT_HIOS 0x6fffffff /* End OS-specific type */ -+#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define SHT_LOUSER 0x80000000 /* Start of application-specific */ -+#define SHT_HIUSER 0x8fffffff /* End of application-specific */ -+ -+/* Legal values for sh_flags (section flags). */ -+ -+#define SHF_WRITE (1 << 0) /* Writable */ -+#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ -+#define SHF_EXECINSTR (1 << 2) /* Executable */ -+#define SHF_MERGE (1 << 4) /* Might be merged */ -+#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ -+#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ -+#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ -+#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling -+ required */ -+#define SHF_GROUP (1 << 9) /* Section is member of a group. */ -+#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ -+#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ -+#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ -+#define SHF_ORDERED (1 << 30) /* Special ordering requirement -+ (Solaris). */ -+#define SHF_EXCLUDE (1 << 31) /* Section is excluded unless -+ referenced or allocated (Solaris).*/ -+ -+/* Section group handling. */ -+#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ -+ -+/* Symbol table entry. */ -+ -+typedef struct -+{ -+ Elf32_Word st_name; /* Symbol name (string tbl index) */ -+ Elf32_Addr st_value; /* Symbol value */ -+ Elf32_Word st_size; /* Symbol size */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf32_Section st_shndx; /* Section index */ -+} Elf32_Sym; -+ -+typedef struct -+{ -+ Elf64_Word st_name; /* Symbol name (string tbl index) */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf64_Section st_shndx; /* Section index */ -+ Elf64_Addr st_value; /* Symbol value */ -+ Elf64_Xword st_size; /* Symbol size */ -+} Elf64_Sym; -+ -+/* The syminfo section if available contains additional information about -+ every dynamic symbol. */ -+ -+typedef struct -+{ -+ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf32_Half si_flags; /* Per symbol flags */ -+} Elf32_Syminfo; -+ -+typedef struct -+{ -+ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf64_Half si_flags; /* Per symbol flags */ -+} Elf64_Syminfo; -+ -+/* Possible values for si_boundto. */ -+#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ -+#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ -+#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ -+ -+/* Possible bitmasks for si_flags. */ -+#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ -+#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ -+#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ -+#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy -+ loaded */ -+/* Syminfo version values. */ -+#define SYMINFO_NONE 0 -+#define SYMINFO_CURRENT 1 -+#define SYMINFO_NUM 2 -+ -+ -+/* How to extract and insert information held in the st_info field. */ -+ -+#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) -+#define ELF32_ST_TYPE(val) ((val) & 0xf) -+#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) -+ -+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ -+#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) -+#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) -+#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) -+ -+/* Legal values for ST_BIND subfield of st_info (symbol binding). */ -+ -+#define STB_LOCAL 0 /* Local symbol */ -+#define STB_GLOBAL 1 /* Global symbol */ -+#define STB_WEAK 2 /* Weak symbol */ -+#define STB_NUM 3 /* Number of defined types. */ -+#define STB_LOOS 10 /* Start of OS-specific */ -+#define STB_GNU_UNIQUE 10 /* Unique symbol. */ -+#define STB_HIOS 12 /* End of OS-specific */ -+#define STB_LOPROC 13 /* Start of processor-specific */ -+#define STB_HIPROC 15 /* End of processor-specific */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_NOTYPE 0 /* Symbol type is unspecified */ -+#define STT_OBJECT 1 /* Symbol is a data object */ -+#define STT_FUNC 2 /* Symbol is a code object */ -+#define STT_SECTION 3 /* Symbol associated with a section */ -+#define STT_FILE 4 /* Symbol's name is file name */ -+#define STT_COMMON 5 /* Symbol is a common data object */ -+#define STT_TLS 6 /* Symbol is thread-local data object*/ -+#define STT_NUM 7 /* Number of defined types. */ -+#define STT_LOOS 10 /* Start of OS-specific */ -+#define STT_GNU_IFUNC 10 /* Symbol is indirect code object */ -+#define STT_HIOS 12 /* End of OS-specific */ -+#define STT_LOPROC 13 /* Start of processor-specific */ -+#define STT_HIPROC 15 /* End of processor-specific */ -+ -+ -+/* Symbol table indices are found in the hash buckets and chain table -+ of a symbol hash table section. This special index value indicates -+ the end of a chain, meaning no further symbols are found in that bucket. */ -+ -+#define STN_UNDEF 0 /* End of a chain. */ -+ -+ -+/* How to extract and insert information held in the st_other field. */ -+ -+#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) -+ -+/* For ELF64 the definitions are the same. */ -+#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) -+ -+/* Symbol visibility specification encoded in the st_other field. */ -+#define STV_DEFAULT 0 /* Default symbol visibility rules */ -+#define STV_INTERNAL 1 /* Processor specific hidden class */ -+#define STV_HIDDEN 2 /* Sym unavailable in other modules */ -+#define STV_PROTECTED 3 /* Not preemptible, not exported */ -+ -+ -+/* Relocation table entry without addend (in section of type SHT_REL). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+} Elf32_Rel; -+ -+/* I have seen two different definitions of the Elf64_Rel and -+ Elf64_Rela structures, so we'll leave them out until Novell (or -+ whoever) gets their act together. */ -+/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+} Elf64_Rel; -+ -+/* Relocation table entry with addend (in section of type SHT_RELA). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+ Elf32_Sword r_addend; /* Addend */ -+} Elf32_Rela; -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+ Elf64_Sxword r_addend; /* Addend */ -+} Elf64_Rela; -+ -+/* How to extract and insert information held in the r_info field. */ -+ -+#define ELF32_R_SYM(val) ((val) >> 8) -+#define ELF32_R_TYPE(val) ((val) & 0xff) -+#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) -+ -+#define ELF64_R_SYM(i) ((i) >> 32) -+#define ELF64_R_TYPE(i) ((i) & 0xffffffff) -+#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) -+ -+/* Program segment header. */ -+ -+typedef struct -+{ -+ Elf32_Word p_type; /* Segment type */ -+ Elf32_Off p_offset; /* Segment file offset */ -+ Elf32_Addr p_vaddr; /* Segment virtual address */ -+ Elf32_Addr p_paddr; /* Segment physical address */ -+ Elf32_Word p_filesz; /* Segment size in file */ -+ Elf32_Word p_memsz; /* Segment size in memory */ -+ Elf32_Word p_flags; /* Segment flags */ -+ Elf32_Word p_align; /* Segment alignment */ -+} Elf32_Phdr; -+ -+typedef struct -+{ -+ Elf64_Word p_type; /* Segment type */ -+ Elf64_Word p_flags; /* Segment flags */ -+ Elf64_Off p_offset; /* Segment file offset */ -+ Elf64_Addr p_vaddr; /* Segment virtual address */ -+ Elf64_Addr p_paddr; /* Segment physical address */ -+ Elf64_Xword p_filesz; /* Segment size in file */ -+ Elf64_Xword p_memsz; /* Segment size in memory */ -+ Elf64_Xword p_align; /* Segment alignment */ -+} Elf64_Phdr; -+ -+/* Special value for e_phnum. This indicates that the real number of -+ program headers is too large to fit into e_phnum. Instead the real -+ value is in the field sh_info of section 0. */ -+ -+#define PN_XNUM 0xffff -+ -+/* Legal values for p_type (segment type). */ -+ -+#define PT_NULL 0 /* Program header table entry unused */ -+#define PT_LOAD 1 /* Loadable program segment */ -+#define PT_DYNAMIC 2 /* Dynamic linking information */ -+#define PT_INTERP 3 /* Program interpreter */ -+#define PT_NOTE 4 /* Auxiliary information */ -+#define PT_SHLIB 5 /* Reserved */ -+#define PT_PHDR 6 /* Entry for header table itself */ -+#define PT_TLS 7 /* Thread-local storage segment */ -+#define PT_NUM 8 /* Number of defined types */ -+#define PT_LOOS 0x60000000 /* Start of OS-specific */ -+#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ -+#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ -+#define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ -+#define PT_LOSUNW 0x6ffffffa -+#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ -+#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ -+#define PT_HISUNW 0x6fffffff -+#define PT_HIOS 0x6fffffff /* End of OS-specific */ -+#define PT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define PT_HIPROC 0x7fffffff /* End of processor-specific */ -+ -+/* Legal values for p_flags (segment flags). */ -+ -+#define PF_X (1 << 0) /* Segment is executable */ -+#define PF_W (1 << 1) /* Segment is writable */ -+#define PF_R (1 << 2) /* Segment is readable */ -+#define PF_MASKOS 0x0ff00000 /* OS-specific */ -+#define PF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Legal values for note segment descriptor types for core files. */ -+ -+#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ -+#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ -+#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ -+#define NT_PRXREG 4 /* Contains copy of prxregset struct */ -+#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ -+#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ -+#define NT_AUXV 6 /* Contains copy of auxv array */ -+#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ -+#define NT_ASRS 8 /* Contains copy of asrset struct */ -+#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ -+#define NT_PSINFO 13 /* Contains copy of psinfo struct */ -+#define NT_PRCRED 14 /* Contains copy of prcred struct */ -+#define NT_UTSNAME 15 /* Contains copy of utsname struct */ -+#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ -+#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ -+#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */ -+#define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */ -+#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ -+#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ -+#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ -+#define NT_386_TLS 0x200 /* i386 TLS slots (struct user_desc) */ -+#define NT_386_IOPERM 0x201 /* x86 io permission bitmap (1=deny) */ -+#define NT_X86_XSTATE 0x202 /* x86 extended state using xsave */ -+ -+/* Legal values for the note segment descriptor types for object files. */ -+ -+#define NT_VERSION 1 /* Contains a version string. */ -+ -+ -+/* Dynamic section entry. */ -+ -+typedef struct -+{ -+ Elf32_Sword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf32_Word d_val; /* Integer value */ -+ Elf32_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf32_Dyn; -+ -+typedef struct -+{ -+ Elf64_Sxword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf64_Xword d_val; /* Integer value */ -+ Elf64_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf64_Dyn; -+ -+/* Legal values for d_tag (dynamic entry type). */ -+ -+#define DT_NULL 0 /* Marks end of dynamic section */ -+#define DT_NEEDED 1 /* Name of needed library */ -+#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ -+#define DT_PLTGOT 3 /* Processor defined value */ -+#define DT_HASH 4 /* Address of symbol hash table */ -+#define DT_STRTAB 5 /* Address of string table */ -+#define DT_SYMTAB 6 /* Address of symbol table */ -+#define DT_RELA 7 /* Address of Rela relocs */ -+#define DT_RELASZ 8 /* Total size of Rela relocs */ -+#define DT_RELAENT 9 /* Size of one Rela reloc */ -+#define DT_STRSZ 10 /* Size of string table */ -+#define DT_SYMENT 11 /* Size of one symbol table entry */ -+#define DT_INIT 12 /* Address of init function */ -+#define DT_FINI 13 /* Address of termination function */ -+#define DT_SONAME 14 /* Name of shared object */ -+#define DT_RPATH 15 /* Library search path (deprecated) */ -+#define DT_SYMBOLIC 16 /* Start symbol search here */ -+#define DT_REL 17 /* Address of Rel relocs */ -+#define DT_RELSZ 18 /* Total size of Rel relocs */ -+#define DT_RELENT 19 /* Size of one Rel reloc */ -+#define DT_PLTREL 20 /* Type of reloc in PLT */ -+#define DT_DEBUG 21 /* For debugging; unspecified */ -+#define DT_TEXTREL 22 /* Reloc might modify .text */ -+#define DT_JMPREL 23 /* Address of PLT relocs */ -+#define DT_BIND_NOW 24 /* Process relocations of object */ -+#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ -+#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ -+#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ -+#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ -+#define DT_RUNPATH 29 /* Library search path */ -+#define DT_FLAGS 30 /* Flags for the object being loaded */ -+#define DT_ENCODING 32 /* Start of encoded range */ -+#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ -+#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ -+#define DT_NUM 34 /* Number used */ -+#define DT_LOOS 0x6000000d /* Start of OS-specific */ -+#define DT_HIOS 0x6ffff000 /* End of OS-specific */ -+#define DT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define DT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ -+ -+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the -+ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's -+ approach. */ -+#define DT_VALRNGLO 0x6ffffd00 -+#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ -+#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ -+#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ -+#define DT_CHECKSUM 0x6ffffdf8 -+#define DT_PLTPADSZ 0x6ffffdf9 -+#define DT_MOVEENT 0x6ffffdfa -+#define DT_MOVESZ 0x6ffffdfb -+#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ -+#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting -+ the following DT_* entry. */ -+#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ -+#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ -+#define DT_VALRNGHI 0x6ffffdff -+#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ -+#define DT_VALNUM 12 -+ -+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the -+ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. -+ -+ If any adjustment is made to the ELF object after it has been -+ built these entries will need to be adjusted. */ -+#define DT_ADDRRNGLO 0x6ffffe00 -+#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table. */ -+#define DT_TLSDESC_PLT 0x6ffffef6 -+#define DT_TLSDESC_GOT 0x6ffffef7 -+#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ -+#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ -+#define DT_CONFIG 0x6ffffefa /* Configuration information. */ -+#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ -+#define DT_AUDIT 0x6ffffefc /* Object auditing. */ -+#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ -+#define DT_MOVETAB 0x6ffffefe /* Move table. */ -+#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ -+#define DT_ADDRRNGHI 0x6ffffeff -+#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ -+#define DT_ADDRNUM 11 -+ -+/* The versioning entry types. The next are defined as part of the -+ GNU extension. */ -+#define DT_VERSYM 0x6ffffff0 -+ -+#define DT_RELACOUNT 0x6ffffff9 -+#define DT_RELCOUNT 0x6ffffffa -+ -+/* These were chosen by Sun. */ -+#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ -+#define DT_VERDEF 0x6ffffffc /* Address of version definition -+ table */ -+#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ -+#define DT_VERNEED 0x6ffffffe /* Address of table with needed -+ versions */ -+#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ -+#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ -+#define DT_VERSIONTAGNUM 16 -+ -+/* Sun added these machine-independent extensions in the "processor-specific" -+ range. Be compatible. */ -+#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ -+#define DT_FILTER 0x7fffffff /* Shared object to get values from */ -+#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) -+#define DT_EXTRANUM 3 -+ -+/* Values of `d_un.d_val' in the DT_FLAGS entry. */ -+#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ -+#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ -+#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ -+#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ -+#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ -+ -+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 -+ entry in the dynamic section. */ -+#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ -+#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ -+#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ -+#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ -+#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ -+#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ -+#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ -+#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ -+#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ -+#define DF_1_TRANS 0x00000200 -+#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ -+#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ -+#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ -+#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ -+#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ -+#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ -+#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ -+ -+/* Flags for the feature selection in DT_FEATURE_1. */ -+#define DTF_1_PARINIT 0x00000001 -+#define DTF_1_CONFEXP 0x00000002 -+ -+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ -+#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ -+#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not -+ generally available. */ -+ -+/* Version definition sections. */ -+ -+typedef struct -+{ -+ Elf32_Half vd_version; /* Version revision */ -+ Elf32_Half vd_flags; /* Version information */ -+ Elf32_Half vd_ndx; /* Version Index */ -+ Elf32_Half vd_cnt; /* Number of associated aux entries */ -+ Elf32_Word vd_hash; /* Version name hash value */ -+ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf32_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf32_Verdef; -+ -+typedef struct -+{ -+ Elf64_Half vd_version; /* Version revision */ -+ Elf64_Half vd_flags; /* Version information */ -+ Elf64_Half vd_ndx; /* Version Index */ -+ Elf64_Half vd_cnt; /* Number of associated aux entries */ -+ Elf64_Word vd_hash; /* Version name hash value */ -+ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf64_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf64_Verdef; -+ -+ -+/* Legal values for vd_version (version revision). */ -+#define VER_DEF_NONE 0 /* No version */ -+#define VER_DEF_CURRENT 1 /* Current version */ -+#define VER_DEF_NUM 2 /* Given version number */ -+ -+/* Legal values for vd_flags (version information flags). */ -+#define VER_FLG_BASE 0x1 /* Version definition of file itself */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+/* Versym symbol index values. */ -+#define VER_NDX_LOCAL 0 /* Symbol is local. */ -+#define VER_NDX_GLOBAL 1 /* Symbol is global. */ -+#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ -+#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ -+ -+/* Auxialiary version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vda_name; /* Version or dependency names */ -+ Elf32_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf32_Verdaux; -+ -+typedef struct -+{ -+ Elf64_Word vda_name; /* Version or dependency names */ -+ Elf64_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf64_Verdaux; -+ -+ -+/* Version dependency section. */ -+ -+typedef struct -+{ -+ Elf32_Half vn_version; /* Version of structure */ -+ Elf32_Half vn_cnt; /* Number of associated aux entries */ -+ Elf32_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf32_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf32_Verneed; -+ -+typedef struct -+{ -+ Elf64_Half vn_version; /* Version of structure */ -+ Elf64_Half vn_cnt; /* Number of associated aux entries */ -+ Elf64_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf64_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf64_Verneed; -+ -+ -+/* Legal values for vn_version (version revision). */ -+#define VER_NEED_NONE 0 /* No version */ -+#define VER_NEED_CURRENT 1 /* Current version */ -+#define VER_NEED_NUM 2 /* Given version number */ -+ -+/* Auxiliary needed version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vna_hash; /* Hash value of dependency name */ -+ Elf32_Half vna_flags; /* Dependency specific information */ -+ Elf32_Half vna_other; /* Unused */ -+ Elf32_Word vna_name; /* Dependency name string offset */ -+ Elf32_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf32_Vernaux; -+ -+typedef struct -+{ -+ Elf64_Word vna_hash; /* Hash value of dependency name */ -+ Elf64_Half vna_flags; /* Dependency specific information */ -+ Elf64_Half vna_other; /* Unused */ -+ Elf64_Word vna_name; /* Dependency name string offset */ -+ Elf64_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf64_Vernaux; -+ -+ -+/* Legal values for vna_flags. */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+ -+/* Auxiliary vector. */ -+ -+/* This vector is normally only used by the program interpreter. The -+ usual definition in an ABI supplement uses the name auxv_t. The -+ vector is not usually defined in a standard file, but it -+ can't hurt. We rename it to avoid conflicts. The sizes of these -+ types are an arrangement between the exec server and the program -+ interpreter, so we don't fully specify them here. */ -+ -+typedef struct -+{ -+ uint32_t a_type; /* Entry type */ -+ union -+ { -+ uint32_t a_val; /* Integer value */ -+ /* We use to have pointer elements added here. We cannot do that, -+ though, since it does not work when using 32-bit definitions -+ on 64-bit platforms and vice versa. */ -+ } a_un; -+} Elf32_auxv_t; -+ -+typedef struct -+{ -+ uint64_t a_type; /* Entry type */ -+ union -+ { -+ uint64_t a_val; /* Integer value */ -+ /* We use to have pointer elements added here. We cannot do that, -+ though, since it does not work when using 32-bit definitions -+ on 64-bit platforms and vice versa. */ -+ } a_un; -+} Elf64_auxv_t; -+ -+/* Legal values for a_type (entry type). */ -+ -+#define AT_NULL 0 /* End of vector */ -+#define AT_IGNORE 1 /* Entry should be ignored */ -+#define AT_EXECFD 2 /* File descriptor of program */ -+#define AT_PHDR 3 /* Program headers for program */ -+#define AT_PHENT 4 /* Size of program header entry */ -+#define AT_PHNUM 5 /* Number of program headers */ -+#define AT_PAGESZ 6 /* System page size */ -+#define AT_BASE 7 /* Base address of interpreter */ -+#define AT_FLAGS 8 /* Flags */ -+#define AT_ENTRY 9 /* Entry point of program */ -+#define AT_NOTELF 10 /* Program is not ELF */ -+#define AT_UID 11 /* Real uid */ -+#define AT_EUID 12 /* Effective uid */ -+#define AT_GID 13 /* Real gid */ -+#define AT_EGID 14 /* Effective gid */ -+#define AT_CLKTCK 17 /* Frequency of times() */ -+ -+/* Some more special a_type values describing the hardware. */ -+#define AT_PLATFORM 15 /* String identifying platform. */ -+#define AT_HWCAP 16 /* Machine dependent hints about -+ processor capabilities. */ -+ -+/* This entry gives some information about the FPU initialization -+ performed by the kernel. */ -+#define AT_FPUCW 18 /* Used FPU control word. */ -+ -+/* Cache block sizes. */ -+#define AT_DCACHEBSIZE 19 /* Data cache block size. */ -+#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ -+#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ -+ -+/* A special ignored value for PPC, used by the kernel to control the -+ interpretation of the AUXV. Must be > 16. */ -+#define AT_IGNOREPPC 22 /* Entry should be ignored. */ -+ -+#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ -+ -+#define AT_BASE_PLATFORM 24 /* String identifying real platforms.*/ -+ -+#define AT_RANDOM 25 /* Address of 16 random bytes. */ -+ -+#define AT_EXECFN 31 /* Filename of executable. */ -+ -+/* Pointer to the global system page used for system calls and other -+ nice things. */ -+#define AT_SYSINFO 32 -+#define AT_SYSINFO_EHDR 33 -+ -+/* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains -+ log2 of line size; mask those to get cache size. */ -+#define AT_L1I_CACHESHAPE 34 -+#define AT_L1D_CACHESHAPE 35 -+#define AT_L2_CACHESHAPE 36 -+#define AT_L3_CACHESHAPE 37 -+ -+/* Note section contents. Each entry in the note section begins with -+ a header of a fixed form. */ -+ -+typedef struct -+{ -+ Elf32_Word n_namesz; /* Length of the note's name. */ -+ Elf32_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf32_Word n_type; /* Type of the note. */ -+} Elf32_Nhdr; -+ -+typedef struct -+{ -+ Elf64_Word n_namesz; /* Length of the note's name. */ -+ Elf64_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf64_Word n_type; /* Type of the note. */ -+} Elf64_Nhdr; -+ -+/* Known names of notes. */ -+ -+/* Solaris entries in the note section have this name. */ -+#define ELF_NOTE_SOLARIS "SUNW Solaris" -+ -+/* Note entries for GNU systems have this name. */ -+#define ELF_NOTE_GNU "GNU" -+ -+ -+/* Defined types of notes for Solaris. */ -+ -+/* Value of descriptor (one word) is desired pagesize for the binary. */ -+#define ELF_NOTE_PAGESIZE_HINT 1 -+ -+ -+/* Defined note types for GNU systems. */ -+ -+/* ABI information. The descriptor consists of words: -+ word 0: OS descriptor -+ word 1: major version of the ABI -+ word 2: minor version of the ABI -+ word 3: subminor version of the ABI -+*/ -+#define NT_GNU_ABI_TAG 1 -+#define ELF_NOTE_ABI NT_GNU_ABI_TAG /* Old name. */ -+ -+/* Known OSes. These values can appear in word 0 of an -+ NT_GNU_ABI_TAG note section entry. */ -+#define ELF_NOTE_OS_LINUX 0 -+#define ELF_NOTE_OS_GNU 1 -+#define ELF_NOTE_OS_SOLARIS2 2 -+#define ELF_NOTE_OS_FREEBSD 3 -+ -+/* Synthetic hwcap information. The descriptor begins with two words: -+ word 0: number of entries -+ word 1: bitmask of enabled entries -+ Then follow variable-length entries, one byte followed by a -+ '\0'-terminated hwcap name string. The byte gives the bit -+ number to test if enabled, (1U << bit) & bitmask. */ -+#define NT_GNU_HWCAP 2 -+ -+/* Build ID bits as generated by ld --build-id. -+ The descriptor consists of any nonzero number of bytes. */ -+#define NT_GNU_BUILD_ID 3 -+ -+/* Version note generated by GNU gold containing a version string. */ -+#define NT_GNU_GOLD_VERSION 4 -+ -+ -+/* Move records. */ -+typedef struct -+{ -+ Elf32_Xword m_value; /* Symbol value. */ -+ Elf32_Word m_info; /* Size and index. */ -+ Elf32_Word m_poffset; /* Symbol offset. */ -+ Elf32_Half m_repeat; /* Repeat count. */ -+ Elf32_Half m_stride; /* Stride info. */ -+} Elf32_Move; -+ -+typedef struct -+{ -+ Elf64_Xword m_value; /* Symbol value. */ -+ Elf64_Xword m_info; /* Size and index. */ -+ Elf64_Xword m_poffset; /* Symbol offset. */ -+ Elf64_Half m_repeat; /* Repeat count. */ -+ Elf64_Half m_stride; /* Stride info. */ -+} Elf64_Move; -+ -+/* Macro to construct move records. */ -+#define ELF32_M_SYM(info) ((info) >> 8) -+#define ELF32_M_SIZE(info) ((unsigned char) (info)) -+#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) -+ -+#define ELF64_M_SYM(info) ELF32_M_SYM (info) -+#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) -+#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) -+ -+ -+/* Motorola 68k specific definitions. */ -+ -+/* Values for Elf32_Ehdr.e_flags. */ -+#define EF_CPU32 0x00810000 -+ -+/* m68k relocs. */ -+ -+#define R_68K_NONE 0 /* No reloc */ -+#define R_68K_32 1 /* Direct 32 bit */ -+#define R_68K_16 2 /* Direct 16 bit */ -+#define R_68K_8 3 /* Direct 8 bit */ -+#define R_68K_PC32 4 /* PC relative 32 bit */ -+#define R_68K_PC16 5 /* PC relative 16 bit */ -+#define R_68K_PC8 6 /* PC relative 8 bit */ -+#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ -+#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ -+#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ -+#define R_68K_GOT32O 10 /* 32 bit GOT offset */ -+#define R_68K_GOT16O 11 /* 16 bit GOT offset */ -+#define R_68K_GOT8O 12 /* 8 bit GOT offset */ -+#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ -+#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ -+#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ -+#define R_68K_PLT32O 16 /* 32 bit PLT offset */ -+#define R_68K_PLT16O 17 /* 16 bit PLT offset */ -+#define R_68K_PLT8O 18 /* 8 bit PLT offset */ -+#define R_68K_COPY 19 /* Copy symbol at runtime */ -+#define R_68K_GLOB_DAT 20 /* Create GOT entry */ -+#define R_68K_JMP_SLOT 21 /* Create PLT entry */ -+#define R_68K_RELATIVE 22 /* Adjust by program base */ -+#define R_68K_TLS_GD32 25 /* 32 bit GOT offset for GD */ -+#define R_68K_TLS_GD16 26 /* 16 bit GOT offset for GD */ -+#define R_68K_TLS_GD8 27 /* 8 bit GOT offset for GD */ -+#define R_68K_TLS_LDM32 28 /* 32 bit GOT offset for LDM */ -+#define R_68K_TLS_LDM16 29 /* 16 bit GOT offset for LDM */ -+#define R_68K_TLS_LDM8 30 /* 8 bit GOT offset for LDM */ -+#define R_68K_TLS_LDO32 31 /* 32 bit module-relative offset */ -+#define R_68K_TLS_LDO16 32 /* 16 bit module-relative offset */ -+#define R_68K_TLS_LDO8 33 /* 8 bit module-relative offset */ -+#define R_68K_TLS_IE32 34 /* 32 bit GOT offset for IE */ -+#define R_68K_TLS_IE16 35 /* 16 bit GOT offset for IE */ -+#define R_68K_TLS_IE8 36 /* 8 bit GOT offset for IE */ -+#define R_68K_TLS_LE32 37 /* 32 bit offset relative to -+ static TLS block */ -+#define R_68K_TLS_LE16 38 /* 16 bit offset relative to -+ static TLS block */ -+#define R_68K_TLS_LE8 39 /* 8 bit offset relative to -+ static TLS block */ -+#define R_68K_TLS_DTPMOD32 40 /* 32 bit module number */ -+#define R_68K_TLS_DTPREL32 41 /* 32 bit module-relative offset */ -+#define R_68K_TLS_TPREL32 42 /* 32 bit TP-relative offset */ -+/* Keep this the last entry. */ -+#define R_68K_NUM 43 -+ -+/* Intel 80386 specific definitions. */ -+ -+/* i386 relocs. */ -+ -+#define R_386_NONE 0 /* No reloc */ -+#define R_386_32 1 /* Direct 32 bit */ -+#define R_386_PC32 2 /* PC relative 32 bit */ -+#define R_386_GOT32 3 /* 32 bit GOT entry */ -+#define R_386_PLT32 4 /* 32 bit PLT address */ -+#define R_386_COPY 5 /* Copy symbol at runtime */ -+#define R_386_GLOB_DAT 6 /* Create GOT entry */ -+#define R_386_JMP_SLOT 7 /* Create PLT entry */ -+#define R_386_RELATIVE 8 /* Adjust by program base */ -+#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ -+#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ -+#define R_386_32PLT 11 -+#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ -+#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS -+ block offset */ -+#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block -+ offset */ -+#define R_386_TLS_LE 17 /* Offset relative to static TLS -+ block */ -+#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of -+ general dynamic thread local data */ -+#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of -+ local dynamic thread local data -+ in LE code */ -+#define R_386_16 20 -+#define R_386_PC16 21 -+#define R_386_8 22 -+#define R_386_PC8 23 -+#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic -+ thread local data */ -+#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ -+#define R_386_TLS_GD_CALL 26 /* Relocation for call to -+ __tls_get_addr() */ -+#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ -+#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic -+ thread local data in LE code */ -+#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ -+#define R_386_TLS_LDM_CALL 30 /* Relocation for call to -+ __tls_get_addr() in LDM code */ -+#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ -+#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ -+#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS -+ block offset */ -+#define R_386_TLS_LE_32 34 /* Negated offset relative to static -+ TLS block */ -+#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ -+#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ -+#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ -+/* 38? */ -+#define R_386_TLS_GOTDESC 39 /* GOT offset for TLS descriptor. */ -+#define R_386_TLS_DESC_CALL 40 /* Marker of call through TLS -+ descriptor for -+ relaxation. */ -+#define R_386_TLS_DESC 41 /* TLS descriptor containing -+ pointer to code and to -+ argument, returning the TLS -+ offset for the symbol. */ -+#define R_386_IRELATIVE 42 /* Adjust indirectly by program base */ -+/* Keep this the last entry. */ -+#define R_386_NUM 43 -+ -+/* SUN SPARC specific definitions. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_SPARC_REGISTER 13 /* Global register reserved to app. */ -+ -+/* Values for Elf64_Ehdr.e_flags. */ -+ -+#define EF_SPARCV9_MM 3 -+#define EF_SPARCV9_TSO 0 -+#define EF_SPARCV9_PSO 1 -+#define EF_SPARCV9_RMO 2 -+#define EF_SPARC_LEDATA 0x800000 /* little endian data */ -+#define EF_SPARC_EXT_MASK 0xFFFF00 -+#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ -+#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ -+#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ -+#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ -+ -+/* SPARC relocs. */ -+ -+#define R_SPARC_NONE 0 /* No reloc */ -+#define R_SPARC_8 1 /* Direct 8 bit */ -+#define R_SPARC_16 2 /* Direct 16 bit */ -+#define R_SPARC_32 3 /* Direct 32 bit */ -+#define R_SPARC_DISP8 4 /* PC relative 8 bit */ -+#define R_SPARC_DISP16 5 /* PC relative 16 bit */ -+#define R_SPARC_DISP32 6 /* PC relative 32 bit */ -+#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ -+#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ -+#define R_SPARC_HI22 9 /* High 22 bit */ -+#define R_SPARC_22 10 /* Direct 22 bit */ -+#define R_SPARC_13 11 /* Direct 13 bit */ -+#define R_SPARC_LO10 12 /* Truncated 10 bit */ -+#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ -+#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ -+#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ -+#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ -+#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ -+#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ -+#define R_SPARC_COPY 19 /* Copy symbol at runtime */ -+#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ -+#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ -+#define R_SPARC_RELATIVE 22 /* Adjust by program base */ -+#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ -+ -+/* Additional Sparc64 relocs. */ -+ -+#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ -+#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ -+#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ -+#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ -+#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ -+#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ -+#define R_SPARC_10 30 /* Direct 10 bit */ -+#define R_SPARC_11 31 /* Direct 11 bit */ -+#define R_SPARC_64 32 /* Direct 64 bit */ -+#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ -+#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ -+#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ -+#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ -+#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ -+#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ -+#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ -+#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ -+#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ -+#define R_SPARC_GLOB_JMP 42 /* was part of v9 ABI but was removed */ -+#define R_SPARC_7 43 /* Direct 7 bit */ -+#define R_SPARC_5 44 /* Direct 5 bit */ -+#define R_SPARC_6 45 /* Direct 6 bit */ -+#define R_SPARC_DISP64 46 /* PC relative 64 bit */ -+#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ -+#define R_SPARC_HIX22 48 /* High 22 bit complemented */ -+#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ -+#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ -+#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ -+#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ -+#define R_SPARC_REGISTER 53 /* Global register usage */ -+#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ -+#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ -+#define R_SPARC_TLS_GD_HI22 56 -+#define R_SPARC_TLS_GD_LO10 57 -+#define R_SPARC_TLS_GD_ADD 58 -+#define R_SPARC_TLS_GD_CALL 59 -+#define R_SPARC_TLS_LDM_HI22 60 -+#define R_SPARC_TLS_LDM_LO10 61 -+#define R_SPARC_TLS_LDM_ADD 62 -+#define R_SPARC_TLS_LDM_CALL 63 -+#define R_SPARC_TLS_LDO_HIX22 64 -+#define R_SPARC_TLS_LDO_LOX10 65 -+#define R_SPARC_TLS_LDO_ADD 66 -+#define R_SPARC_TLS_IE_HI22 67 -+#define R_SPARC_TLS_IE_LO10 68 -+#define R_SPARC_TLS_IE_LD 69 -+#define R_SPARC_TLS_IE_LDX 70 -+#define R_SPARC_TLS_IE_ADD 71 -+#define R_SPARC_TLS_LE_HIX22 72 -+#define R_SPARC_TLS_LE_LOX10 73 -+#define R_SPARC_TLS_DTPMOD32 74 -+#define R_SPARC_TLS_DTPMOD64 75 -+#define R_SPARC_TLS_DTPOFF32 76 -+#define R_SPARC_TLS_DTPOFF64 77 -+#define R_SPARC_TLS_TPOFF32 78 -+#define R_SPARC_TLS_TPOFF64 79 -+#define R_SPARC_GOTDATA_HIX22 80 -+#define R_SPARC_GOTDATA_LOX10 81 -+#define R_SPARC_GOTDATA_OP_HIX22 82 -+#define R_SPARC_GOTDATA_OP_LOX10 83 -+#define R_SPARC_GOTDATA_OP 84 -+#define R_SPARC_H34 85 -+#define R_SPARC_SIZE32 86 -+#define R_SPARC_SIZE64 87 -+#define R_SPARC_WDISP10 88 -+#define R_SPARC_JMP_IREL 248 -+#define R_SPARC_IRELATIVE 249 -+#define R_SPARC_GNU_VTINHERIT 250 -+#define R_SPARC_GNU_VTENTRY 251 -+#define R_SPARC_REV32 252 -+/* Keep this the last entry. */ -+#define R_SPARC_NUM 253 -+ -+/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ -+ -+#define DT_SPARC_REGISTER 0x70000001 -+#define DT_SPARC_NUM 2 -+ -+/* MIPS R3000 specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ -+#define EF_MIPS_PIC 2 /* Contains PIC code */ -+#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ -+#define EF_MIPS_XGOT 8 -+#define EF_MIPS_64BIT_WHIRL 16 -+#define EF_MIPS_ABI2 32 -+#define EF_MIPS_ABI_ON32 64 -+#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ -+ -+/* Legal values for MIPS architecture level. */ -+ -+#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* The following are non-official names and should not be used. */ -+ -+#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* Special section indices. */ -+ -+#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ -+#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ -+#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ -+#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ -+#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ -+#define SHT_MIPS_MSYM 0x70000001 -+#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ -+#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ -+#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ -+#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ -+#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ -+#define SHT_MIPS_PACKAGE 0x70000007 -+#define SHT_MIPS_PACKSYM 0x70000008 -+#define SHT_MIPS_RELD 0x70000009 -+#define SHT_MIPS_IFACE 0x7000000b -+#define SHT_MIPS_CONTENT 0x7000000c -+#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ -+#define SHT_MIPS_SHDR 0x70000010 -+#define SHT_MIPS_FDESC 0x70000011 -+#define SHT_MIPS_EXTSYM 0x70000012 -+#define SHT_MIPS_DENSE 0x70000013 -+#define SHT_MIPS_PDESC 0x70000014 -+#define SHT_MIPS_LOCSYM 0x70000015 -+#define SHT_MIPS_AUXSYM 0x70000016 -+#define SHT_MIPS_OPTSYM 0x70000017 -+#define SHT_MIPS_LOCSTR 0x70000018 -+#define SHT_MIPS_LINE 0x70000019 -+#define SHT_MIPS_RFDESC 0x7000001a -+#define SHT_MIPS_DELTASYM 0x7000001b -+#define SHT_MIPS_DELTAINST 0x7000001c -+#define SHT_MIPS_DELTACLASS 0x7000001d -+#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ -+#define SHT_MIPS_DELTADECL 0x7000001f -+#define SHT_MIPS_SYMBOL_LIB 0x70000020 -+#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ -+#define SHT_MIPS_TRANSLATE 0x70000022 -+#define SHT_MIPS_PIXIE 0x70000023 -+#define SHT_MIPS_XLATE 0x70000024 -+#define SHT_MIPS_XLATE_DEBUG 0x70000025 -+#define SHT_MIPS_WHIRL 0x70000026 -+#define SHT_MIPS_EH_REGION 0x70000027 -+#define SHT_MIPS_XLATE_OLD 0x70000028 -+#define SHT_MIPS_PDR_EXCEPTION 0x70000029 -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ -+#define SHF_MIPS_MERGE 0x20000000 -+#define SHF_MIPS_ADDR 0x40000000 -+#define SHF_MIPS_STRINGS 0x80000000 -+#define SHF_MIPS_NOSTRIP 0x08000000 -+#define SHF_MIPS_LOCAL 0x04000000 -+#define SHF_MIPS_NAMES 0x02000000 -+#define SHF_MIPS_NODUPE 0x01000000 -+ -+ -+/* Symbol tables. */ -+ -+/* MIPS specific values for `st_other'. */ -+#define STO_MIPS_DEFAULT 0x0 -+#define STO_MIPS_INTERNAL 0x1 -+#define STO_MIPS_HIDDEN 0x2 -+#define STO_MIPS_PROTECTED 0x3 -+#define STO_MIPS_PLT 0x8 -+#define STO_MIPS_SC_ALIGN_UNUSED 0xff -+ -+/* MIPS specific values for `st_info'. */ -+#define STB_MIPS_SPLIT_COMMON 13 -+ -+/* Entries found in sections of type SHT_MIPS_GPTAB. */ -+ -+typedef union -+{ -+ struct -+ { -+ Elf32_Word gt_current_g_value; /* -G value used for compilation */ -+ Elf32_Word gt_unused; /* Not used */ -+ } gt_header; /* First entry in section */ -+ struct -+ { -+ Elf32_Word gt_g_value; /* If this value were used for -G */ -+ Elf32_Word gt_bytes; /* This many bytes would be used */ -+ } gt_entry; /* Subsequent entries in section */ -+} Elf32_gptab; -+ -+/* Entry found in sections of type SHT_MIPS_REGINFO. */ -+ -+typedef struct -+{ -+ Elf32_Word ri_gprmask; /* General registers used */ -+ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ -+ Elf32_Sword ri_gp_value; /* $gp register value */ -+} Elf32_RegInfo; -+ -+/* Entries found in sections of type SHT_MIPS_OPTIONS. */ -+ -+typedef struct -+{ -+ unsigned char kind; /* Determines interpretation of the -+ variable part of descriptor. */ -+ unsigned char size; /* Size of descriptor, including header. */ -+ Elf32_Section section; /* Section header index of section affected, -+ 0 for global options. */ -+ Elf32_Word info; /* Kind-specific information. */ -+} Elf_Options; -+ -+/* Values for `kind' field in Elf_Options. */ -+ -+#define ODK_NULL 0 /* Undefined. */ -+#define ODK_REGINFO 1 /* Register usage information. */ -+#define ODK_EXCEPTIONS 2 /* Exception processing options. */ -+#define ODK_PAD 3 /* Section padding options. */ -+#define ODK_HWPATCH 4 /* Hardware workarounds performed */ -+#define ODK_FILL 5 /* record the fill value used by the linker. */ -+#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ -+#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ -+#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ -+ -+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ -+ -+#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ -+#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ -+#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ -+#define OEX_SMM 0x20000 /* Force sequential memory mode? */ -+#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ -+#define OEX_PRECISEFP OEX_FPDBUG -+#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ -+ -+#define OEX_FPU_INVAL 0x10 -+#define OEX_FPU_DIV0 0x08 -+#define OEX_FPU_OFLO 0x04 -+#define OEX_FPU_UFLO 0x02 -+#define OEX_FPU_INEX 0x01 -+ -+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ -+ -+#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ -+#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ -+#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ -+#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ -+ -+#define OPAD_PREFIX 0x1 -+#define OPAD_POSTFIX 0x2 -+#define OPAD_SYMBOL 0x4 -+ -+/* Entry found in `.options' section. */ -+ -+typedef struct -+{ -+ Elf32_Word hwp_flags1; /* Extra flags. */ -+ Elf32_Word hwp_flags2; /* Extra flags. */ -+} Elf_Options_Hw; -+ -+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ -+ -+#define OHWA0_R4KEOP_CHECKED 0x00000001 -+#define OHWA1_R4KEOP_CLEAN 0x00000002 -+ -+/* MIPS relocs. */ -+ -+#define R_MIPS_NONE 0 /* No reloc */ -+#define R_MIPS_16 1 /* Direct 16 bit */ -+#define R_MIPS_32 2 /* Direct 32 bit */ -+#define R_MIPS_REL32 3 /* PC relative 32 bit */ -+#define R_MIPS_26 4 /* Direct 26 bit shifted */ -+#define R_MIPS_HI16 5 /* High 16 bit */ -+#define R_MIPS_LO16 6 /* Low 16 bit */ -+#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ -+#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ -+#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ -+#define R_MIPS_PC16 10 /* PC relative 16 bit */ -+#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ -+#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ -+ -+#define R_MIPS_SHIFT5 16 -+#define R_MIPS_SHIFT6 17 -+#define R_MIPS_64 18 -+#define R_MIPS_GOT_DISP 19 -+#define R_MIPS_GOT_PAGE 20 -+#define R_MIPS_GOT_OFST 21 -+#define R_MIPS_GOT_HI16 22 -+#define R_MIPS_GOT_LO16 23 -+#define R_MIPS_SUB 24 -+#define R_MIPS_INSERT_A 25 -+#define R_MIPS_INSERT_B 26 -+#define R_MIPS_DELETE 27 -+#define R_MIPS_HIGHER 28 -+#define R_MIPS_HIGHEST 29 -+#define R_MIPS_CALL_HI16 30 -+#define R_MIPS_CALL_LO16 31 -+#define R_MIPS_SCN_DISP 32 -+#define R_MIPS_REL16 33 -+#define R_MIPS_ADD_IMMEDIATE 34 -+#define R_MIPS_PJUMP 35 -+#define R_MIPS_RELGOT 36 -+#define R_MIPS_JALR 37 -+#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ -+#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ -+#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ -+#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ -+#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ -+#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ -+#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ -+#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ -+#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ -+#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ -+#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ -+#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ -+#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ -+#define R_MIPS_GLOB_DAT 51 -+#define R_MIPS_COPY 126 -+#define R_MIPS_JUMP_SLOT 127 -+/* Keep this the last entry. */ -+#define R_MIPS_NUM 128 -+ -+/* Legal values for p_type field of Elf32_Phdr. */ -+ -+#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ -+#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ -+#define PT_MIPS_OPTIONS 0x70000002 -+ -+/* Special program header types. */ -+ -+#define PF_MIPS_LOCAL 0x10000000 -+ -+/* Legal values for d_tag field of Elf32_Dyn. */ -+ -+#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ -+#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ -+#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ -+#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ -+#define DT_MIPS_FLAGS 0x70000005 /* Flags */ -+#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ -+#define DT_MIPS_MSYM 0x70000007 -+#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ -+#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ -+#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ -+#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ -+#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ -+#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ -+#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ -+#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ -+#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ -+#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ -+#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ -+#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in -+ DT_MIPS_DELTA_CLASS. */ -+#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ -+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in -+ DT_MIPS_DELTA_INSTANCE. */ -+#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ -+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in -+ DT_MIPS_DELTA_RELOC. */ -+#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta -+ relocations refer to. */ -+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in -+ DT_MIPS_DELTA_SYM. */ -+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the -+ class declaration. */ -+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in -+ DT_MIPS_DELTA_CLASSSYM. */ -+#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ -+#define DT_MIPS_PIXIE_INIT 0x70000023 -+#define DT_MIPS_SYMBOL_LIB 0x70000024 -+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 -+#define DT_MIPS_LOCAL_GOTIDX 0x70000026 -+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 -+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 -+#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ -+#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ -+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b -+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ -+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve -+ function stored in GOT. */ -+#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added -+ by rld on dlopen() calls. */ -+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ -+#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ -+#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ -+/* The address of .got.plt in an executable using the new non-PIC ABI. */ -+#define DT_MIPS_PLTGOT 0x70000032 -+/* The base of the PLT in an executable using the new non-PIC ABI if that -+ PLT is writable. For a non-writable PLT, this is omitted or has a zero -+ value. */ -+#define DT_MIPS_RWPLT 0x70000034 -+#define DT_MIPS_NUM 0x35 -+ -+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ -+ -+#define RHF_NONE 0 /* No flags */ -+#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ -+#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ -+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ -+#define RHF_NO_MOVE (1 << 3) -+#define RHF_SGI_ONLY (1 << 4) -+#define RHF_GUARANTEE_INIT (1 << 5) -+#define RHF_DELTA_C_PLUS_PLUS (1 << 6) -+#define RHF_GUARANTEE_START_INIT (1 << 7) -+#define RHF_PIXIE (1 << 8) -+#define RHF_DEFAULT_DELAY_LOAD (1 << 9) -+#define RHF_REQUICKSTART (1 << 10) -+#define RHF_REQUICKSTARTED (1 << 11) -+#define RHF_CORD (1 << 12) -+#define RHF_NO_UNRES_UNDEF (1 << 13) -+#define RHF_RLD_ORDER_SAFE (1 << 14) -+ -+/* Entries found in sections of type SHT_MIPS_LIBLIST. */ -+ -+typedef struct -+{ -+ Elf32_Word l_name; /* Name (string table index) */ -+ Elf32_Word l_time_stamp; /* Timestamp */ -+ Elf32_Word l_checksum; /* Checksum */ -+ Elf32_Word l_version; /* Interface version */ -+ Elf32_Word l_flags; /* Flags */ -+} Elf32_Lib; -+ -+typedef struct -+{ -+ Elf64_Word l_name; /* Name (string table index) */ -+ Elf64_Word l_time_stamp; /* Timestamp */ -+ Elf64_Word l_checksum; /* Checksum */ -+ Elf64_Word l_version; /* Interface version */ -+ Elf64_Word l_flags; /* Flags */ -+} Elf64_Lib; -+ -+ -+/* Legal values for l_flags. */ -+ -+#define LL_NONE 0 -+#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ -+#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ -+#define LL_REQUIRE_MINOR (1 << 2) -+#define LL_EXPORTS (1 << 3) -+#define LL_DELAY_LOAD (1 << 4) -+#define LL_DELTA (1 << 5) -+ -+/* Entries found in sections of type SHT_MIPS_CONFLICT. */ -+ -+typedef Elf32_Addr Elf32_Conflict; -+ -+ -+/* HPPA specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ -+#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ -+#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ -+#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ -+#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch -+ prediction. */ -+#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ -+#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ -+ -+/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ -+ -+#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ -+#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ -+#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ -+ -+/* Additional section indeces. */ -+ -+#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared -+ symbols in ANSI C. */ -+#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ -+#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ -+#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ -+#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ -+#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ -+ -+#define STT_HP_OPAQUE (STT_LOOS + 0x1) -+#define STT_HP_STUB (STT_LOOS + 0x2) -+ -+/* HPPA relocs. */ -+ -+#define R_PARISC_NONE 0 /* No reloc. */ -+#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ -+#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ -+#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ -+#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ -+#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ -+#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ -+#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ -+#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ -+#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ -+#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ -+#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ -+#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ -+#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ -+#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ -+#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ -+#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ -+#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ -+#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ -+#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ -+#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ -+#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ -+#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ -+#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ -+#define R_PARISC_FPTR64 64 /* 64 bits function address. */ -+#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ -+#define R_PARISC_PLABEL21L 66 /* Left 21 bits of fdesc address. */ -+#define R_PARISC_PLABEL14R 70 /* Right 14 bits of fdesc address. */ -+#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ -+#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ -+#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ -+#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ -+#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ -+#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ -+#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ -+#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ -+#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ -+#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ -+#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ -+#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ -+#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ -+#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ -+#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LORESERVE 128 -+#define R_PARISC_COPY 128 /* Copy relocation. */ -+#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ -+#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ -+#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ -+#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ -+#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ -+#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ -+#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ -+#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ -+#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_GNU_VTENTRY 232 -+#define R_PARISC_GNU_VTINHERIT 233 -+#define R_PARISC_TLS_GD21L 234 /* GD 21-bit left. */ -+#define R_PARISC_TLS_GD14R 235 /* GD 14-bit right. */ -+#define R_PARISC_TLS_GDCALL 236 /* GD call to __t_g_a. */ -+#define R_PARISC_TLS_LDM21L 237 /* LD module 21-bit left. */ -+#define R_PARISC_TLS_LDM14R 238 /* LD module 14-bit right. */ -+#define R_PARISC_TLS_LDMCALL 239 /* LD module call to __t_g_a. */ -+#define R_PARISC_TLS_LDO21L 240 /* LD offset 21-bit left. */ -+#define R_PARISC_TLS_LDO14R 241 /* LD offset 14-bit right. */ -+#define R_PARISC_TLS_DTPMOD32 242 /* DTP module 32-bit. */ -+#define R_PARISC_TLS_DTPMOD64 243 /* DTP module 64-bit. */ -+#define R_PARISC_TLS_DTPOFF32 244 /* DTP offset 32-bit. */ -+#define R_PARISC_TLS_DTPOFF64 245 /* DTP offset 32-bit. */ -+#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L -+#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R -+#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L -+#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R -+#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 -+#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 -+#define R_PARISC_HIRESERVE 255 -+ -+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PT_HP_TLS (PT_LOOS + 0x0) -+#define PT_HP_CORE_NONE (PT_LOOS + 0x1) -+#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) -+#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) -+#define PT_HP_CORE_COMM (PT_LOOS + 0x4) -+#define PT_HP_CORE_PROC (PT_LOOS + 0x5) -+#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) -+#define PT_HP_CORE_STACK (PT_LOOS + 0x7) -+#define PT_HP_CORE_SHM (PT_LOOS + 0x8) -+#define PT_HP_CORE_MMF (PT_LOOS + 0x9) -+#define PT_HP_PARALLEL (PT_LOOS + 0x10) -+#define PT_HP_FASTBIND (PT_LOOS + 0x11) -+#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) -+#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) -+#define PT_HP_STACK (PT_LOOS + 0x14) -+ -+#define PT_PARISC_ARCHEXT 0x70000000 -+#define PT_PARISC_UNWIND 0x70000001 -+ -+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PF_PARISC_SBP 0x08000000 -+ -+#define PF_HP_PAGE_SIZE 0x00100000 -+#define PF_HP_FAR_SHARED 0x00200000 -+#define PF_HP_NEAR_SHARED 0x00400000 -+#define PF_HP_CODE 0x01000000 -+#define PF_HP_MODIFY 0x02000000 -+#define PF_HP_LAZYSWAP 0x04000000 -+#define PF_HP_SBP 0x08000000 -+ -+ -+/* Alpha specific definitions. */ -+ -+/* Legal values for e_flags field of Elf64_Ehdr. */ -+ -+#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ -+#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ -+ -+/* Legal values for sh_type field of Elf64_Shdr. */ -+ -+/* These two are primerily concerned with ECOFF debugging info. */ -+#define SHT_ALPHA_DEBUG 0x70000001 -+#define SHT_ALPHA_REGINFO 0x70000002 -+ -+/* Legal values for sh_flags field of Elf64_Shdr. */ -+ -+#define SHF_ALPHA_GPREL 0x10000000 -+ -+/* Legal values for st_other field of Elf64_Sym. */ -+#define STO_ALPHA_NOPV 0x80 /* No PV required. */ -+#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ -+ -+/* Alpha relocs. */ -+ -+#define R_ALPHA_NONE 0 /* No reloc */ -+#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ -+#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ -+#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ -+#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ -+#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ -+#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ -+#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ -+#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ -+#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ -+#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ -+#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ -+#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ -+#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ -+#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ -+#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ -+#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ -+#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ -+#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ -+#define R_ALPHA_TLS_GD_HI 28 -+#define R_ALPHA_TLSGD 29 -+#define R_ALPHA_TLS_LDM 30 -+#define R_ALPHA_DTPMOD64 31 -+#define R_ALPHA_GOTDTPREL 32 -+#define R_ALPHA_DTPREL64 33 -+#define R_ALPHA_DTPRELHI 34 -+#define R_ALPHA_DTPRELLO 35 -+#define R_ALPHA_DTPREL16 36 -+#define R_ALPHA_GOTTPREL 37 -+#define R_ALPHA_TPREL64 38 -+#define R_ALPHA_TPRELHI 39 -+#define R_ALPHA_TPRELLO 40 -+#define R_ALPHA_TPREL16 41 -+/* Keep this the last entry. */ -+#define R_ALPHA_NUM 46 -+ -+/* Magic values of the LITUSE relocation addend. */ -+#define LITUSE_ALPHA_ADDR 0 -+#define LITUSE_ALPHA_BASE 1 -+#define LITUSE_ALPHA_BYTOFF 2 -+#define LITUSE_ALPHA_JSR 3 -+#define LITUSE_ALPHA_TLS_GD 4 -+#define LITUSE_ALPHA_TLS_LDM 5 -+ -+/* Legal values for d_tag of Elf64_Dyn. */ -+#define DT_ALPHA_PLTRO (DT_LOPROC + 0) -+#define DT_ALPHA_NUM 1 -+ -+/* PowerPC specific declarations */ -+ -+/* Values for Elf32/64_Ehdr.e_flags. */ -+#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ -+ -+/* Cygnus local bits below */ -+#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ -+#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib -+ flag */ -+ -+/* PowerPC relocations defined by the ABIs */ -+#define R_PPC_NONE 0 -+#define R_PPC_ADDR32 1 /* 32bit absolute address */ -+#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ -+#define R_PPC_ADDR16 3 /* 16bit absolute address */ -+#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ -+#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ -+#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ -+#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ -+#define R_PPC_ADDR14_BRTAKEN 8 -+#define R_PPC_ADDR14_BRNTAKEN 9 -+#define R_PPC_REL24 10 /* PC relative 26 bit */ -+#define R_PPC_REL14 11 /* PC relative 16 bit */ -+#define R_PPC_REL14_BRTAKEN 12 -+#define R_PPC_REL14_BRNTAKEN 13 -+#define R_PPC_GOT16 14 -+#define R_PPC_GOT16_LO 15 -+#define R_PPC_GOT16_HI 16 -+#define R_PPC_GOT16_HA 17 -+#define R_PPC_PLTREL24 18 -+#define R_PPC_COPY 19 -+#define R_PPC_GLOB_DAT 20 -+#define R_PPC_JMP_SLOT 21 -+#define R_PPC_RELATIVE 22 -+#define R_PPC_LOCAL24PC 23 -+#define R_PPC_UADDR32 24 -+#define R_PPC_UADDR16 25 -+#define R_PPC_REL32 26 -+#define R_PPC_PLT32 27 -+#define R_PPC_PLTREL32 28 -+#define R_PPC_PLT16_LO 29 -+#define R_PPC_PLT16_HI 30 -+#define R_PPC_PLT16_HA 31 -+#define R_PPC_SDAREL16 32 -+#define R_PPC_SECTOFF 33 -+#define R_PPC_SECTOFF_LO 34 -+#define R_PPC_SECTOFF_HI 35 -+#define R_PPC_SECTOFF_HA 36 -+ -+/* PowerPC relocations defined for the TLS access ABI. */ -+#define R_PPC_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ -+#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ -+#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ -+#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ -+#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ -+#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ -+#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ -+#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ -+#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ -+ -+/* The remaining relocs are from the Embedded ELF ABI, and are not -+ in the SVR4 ELF ABI. */ -+#define R_PPC_EMB_NADDR32 101 -+#define R_PPC_EMB_NADDR16 102 -+#define R_PPC_EMB_NADDR16_LO 103 -+#define R_PPC_EMB_NADDR16_HI 104 -+#define R_PPC_EMB_NADDR16_HA 105 -+#define R_PPC_EMB_SDAI16 106 -+#define R_PPC_EMB_SDA2I16 107 -+#define R_PPC_EMB_SDA2REL 108 -+#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ -+#define R_PPC_EMB_MRKREF 110 -+#define R_PPC_EMB_RELSEC16 111 -+#define R_PPC_EMB_RELST_LO 112 -+#define R_PPC_EMB_RELST_HI 113 -+#define R_PPC_EMB_RELST_HA 114 -+#define R_PPC_EMB_BIT_FLD 115 -+#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ -+ -+/* Diab tool relocations. */ -+#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ -+#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ -+#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ -+#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ -+#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ -+#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ -+ -+/* GNU extension to support local ifunc. */ -+#define R_PPC_IRELATIVE 248 -+ -+/* GNU relocs used in PIC code sequences. */ -+#define R_PPC_REL16 249 /* half16 (sym+add-.) */ -+#define R_PPC_REL16_LO 250 /* half16 (sym+add-.)@l */ -+#define R_PPC_REL16_HI 251 /* half16 (sym+add-.)@h */ -+#define R_PPC_REL16_HA 252 /* half16 (sym+add-.)@ha */ -+ -+/* This is a phony reloc to handle any old fashioned TOC16 references -+ that may still be in object files. */ -+#define R_PPC_TOC16 255 -+ -+/* PowerPC specific values for the Dyn d_tag field. */ -+#define DT_PPC_GOT (DT_LOPROC + 0) -+#define DT_PPC_NUM 1 -+ -+/* PowerPC64 relocations defined by the ABIs */ -+#define R_PPC64_NONE R_PPC_NONE -+#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ -+#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ -+#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ -+#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ -+#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ -+#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ -+#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ -+#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN -+#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN -+#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ -+#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ -+#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN -+#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN -+#define R_PPC64_GOT16 R_PPC_GOT16 -+#define R_PPC64_GOT16_LO R_PPC_GOT16_LO -+#define R_PPC64_GOT16_HI R_PPC_GOT16_HI -+#define R_PPC64_GOT16_HA R_PPC_GOT16_HA -+ -+#define R_PPC64_COPY R_PPC_COPY -+#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT -+#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT -+#define R_PPC64_RELATIVE R_PPC_RELATIVE -+ -+#define R_PPC64_UADDR32 R_PPC_UADDR32 -+#define R_PPC64_UADDR16 R_PPC_UADDR16 -+#define R_PPC64_REL32 R_PPC_REL32 -+#define R_PPC64_PLT32 R_PPC_PLT32 -+#define R_PPC64_PLTREL32 R_PPC_PLTREL32 -+#define R_PPC64_PLT16_LO R_PPC_PLT16_LO -+#define R_PPC64_PLT16_HI R_PPC_PLT16_HI -+#define R_PPC64_PLT16_HA R_PPC_PLT16_HA -+ -+#define R_PPC64_SECTOFF R_PPC_SECTOFF -+#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO -+#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI -+#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA -+#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ -+#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ -+#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ -+#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ -+#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ -+#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ -+#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ -+#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ -+#define R_PPC64_PLT64 45 /* doubleword64 L + A */ -+#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ -+#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ -+#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ -+#define R_PPC64_TOC 51 /* doubleword64 .TOC */ -+#define R_PPC64_PLTGOT16 52 /* half16* M + A */ -+#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ -+#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ -+#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ -+ -+#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ -+#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ -+#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ -+#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ -+#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ -+#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ -+#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ -+#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ -+#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ -+#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ -+#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ -+ -+/* PowerPC64 relocations defined for the TLS access ABI. */ -+#define R_PPC64_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ -+#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ -+#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ -+#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ -+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ -+#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ -+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ -+#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ -+#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ -+#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ -+#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ -+#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ -+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ -+#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ -+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ -+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ -+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ -+ -+/* GNU extension to support local ifunc. */ -+#define R_PPC64_JMP_IREL 247 -+#define R_PPC64_IRELATIVE 248 -+#define R_PPC64_REL16 249 /* half16 (sym+add-.) */ -+#define R_PPC64_REL16_LO 250 /* half16 (sym+add-.)@l */ -+#define R_PPC64_REL16_HI 251 /* half16 (sym+add-.)@h */ -+#define R_PPC64_REL16_HA 252 /* half16 (sym+add-.)@ha */ -+ -+/* PowerPC64 specific values for the Dyn d_tag field. */ -+#define DT_PPC64_GLINK (DT_LOPROC + 0) -+#define DT_PPC64_OPD (DT_LOPROC + 1) -+#define DT_PPC64_OPDSZ (DT_LOPROC + 2) -+#define DT_PPC64_NUM 3 -+ -+ -+/* ARM specific declarations */ -+ -+/* Processor specific flags for the ELF header e_flags field. */ -+#define EF_ARM_RELEXEC 0x01 -+#define EF_ARM_HASENTRY 0x02 -+#define EF_ARM_INTERWORK 0x04 -+#define EF_ARM_APCS_26 0x08 -+#define EF_ARM_APCS_FLOAT 0x10 -+#define EF_ARM_PIC 0x20 -+#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ -+#define EF_ARM_NEW_ABI 0x80 -+#define EF_ARM_OLD_ABI 0x100 -+#define EF_ARM_SOFT_FLOAT 0x200 -+#define EF_ARM_VFP_FLOAT 0x400 -+#define EF_ARM_MAVERICK_FLOAT 0x800 -+ -+ -+/* Other constants defined in the ARM ELF spec. version B-01. */ -+/* NB. These conflict with values defined above. */ -+#define EF_ARM_SYMSARESORTED 0x04 -+#define EF_ARM_DYNSYMSUSESEGIDX 0x08 -+#define EF_ARM_MAPSYMSFIRST 0x10 -+#define EF_ARM_EABIMASK 0XFF000000 -+ -+/* Constants defined in AAELF. */ -+#define EF_ARM_BE8 0x00800000 -+#define EF_ARM_LE8 0x00400000 -+ -+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) -+#define EF_ARM_EABI_UNKNOWN 0x00000000 -+#define EF_ARM_EABI_VER1 0x01000000 -+#define EF_ARM_EABI_VER2 0x02000000 -+#define EF_ARM_EABI_VER3 0x03000000 -+#define EF_ARM_EABI_VER4 0x04000000 -+#define EF_ARM_EABI_VER5 0x05000000 -+ -+/* Additional symbol types for Thumb. */ -+#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ -+#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ -+ -+/* ARM-specific values for sh_flags */ -+#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ -+#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined -+ in the input to a link step. */ -+ -+/* ARM-specific program header flags */ -+#define PF_ARM_SB 0x10000000 /* Segment contains the location -+ addressed by the static base. */ -+#define PF_ARM_PI 0x20000000 /* Position-independent segment. */ -+#define PF_ARM_ABS 0x40000000 /* Absolute segment. */ -+ -+/* Processor specific values for the Phdr p_type field. */ -+#define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */ -+ -+/* Processor specific values for the Shdr sh_type field. */ -+#define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */ -+#define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */ -+#define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */ -+ -+ -+/* ARM relocs. */ -+ -+#define R_ARM_NONE 0 /* No reloc */ -+#define R_ARM_PC24 1 /* PC relative 26 bit branch */ -+#define R_ARM_ABS32 2 /* Direct 32 bit */ -+#define R_ARM_REL32 3 /* PC relative 32 bit */ -+#define R_ARM_PC13 4 -+#define R_ARM_ABS16 5 /* Direct 16 bit */ -+#define R_ARM_ABS12 6 /* Direct 12 bit */ -+#define R_ARM_THM_ABS5 7 -+#define R_ARM_ABS8 8 /* Direct 8 bit */ -+#define R_ARM_SBREL32 9 -+#define R_ARM_THM_PC22 10 -+#define R_ARM_THM_PC8 11 -+#define R_ARM_AMP_VCALL9 12 -+#define R_ARM_SWI24 13 /* Obsolete static relocation. */ -+#define R_ARM_TLS_DESC 13 /* Dynamic relocation. */ -+#define R_ARM_THM_SWI8 14 -+#define R_ARM_XPC25 15 -+#define R_ARM_THM_XPC22 16 -+#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ -+#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ -+#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ -+#define R_ARM_COPY 20 /* Copy symbol at runtime */ -+#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ -+#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ -+#define R_ARM_RELATIVE 23 /* Adjust by program base */ -+#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ -+#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ -+#define R_ARM_GOT32 26 /* 32 bit GOT entry */ -+#define R_ARM_PLT32 27 /* 32 bit PLT address */ -+#define R_ARM_ALU_PCREL_7_0 32 -+#define R_ARM_ALU_PCREL_15_8 33 -+#define R_ARM_ALU_PCREL_23_15 34 -+#define R_ARM_LDR_SBREL_11_0 35 -+#define R_ARM_ALU_SBREL_19_12 36 -+#define R_ARM_ALU_SBREL_27_20 37 -+#define R_ARM_TLS_GOTDESC 90 -+#define R_ARM_TLS_CALL 91 -+#define R_ARM_TLS_DESCSEQ 92 -+#define R_ARM_THM_TLS_CALL 93 -+#define R_ARM_GNU_VTENTRY 100 -+#define R_ARM_GNU_VTINHERIT 101 -+#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ -+#define R_ARM_THM_PC9 103 /* thumb conditional branch */ -+#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic -+ thread local data */ -+#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic -+ thread local data */ -+#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS -+ block */ -+#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of -+ static TLS block offset */ -+#define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static -+ TLS block */ -+#define R_ARM_THM_TLS_DESCSEQ 129 -+#define R_ARM_IRELATIVE 160 -+#define R_ARM_RXPC25 249 -+#define R_ARM_RSBREL32 250 -+#define R_ARM_THM_RPC22 251 -+#define R_ARM_RREL32 252 -+#define R_ARM_RABS22 253 -+#define R_ARM_RPC24 254 -+#define R_ARM_RBASE 255 -+/* Keep this the last entry. */ -+#define R_ARM_NUM 256 -+ -+/* IA-64 specific declarations. */ -+ -+/* Processor specific flags for the Ehdr e_flags field. */ -+#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ -+#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ -+#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ -+ -+/* Processor specific values for the Phdr p_type field. */ -+#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ -+#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ -+#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) -+#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) -+#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) -+ -+/* Processor specific flags for the Phdr p_flags field. */ -+#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Shdr sh_type field. */ -+#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ -+#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ -+ -+/* Processor specific flags for the Shdr sh_flags field. */ -+#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ -+#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Dyn d_tag field. */ -+#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) -+#define DT_IA_64_NUM 1 -+ -+/* IA-64 relocations. */ -+#define R_IA64_NONE 0x00 /* none */ -+#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ -+#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ -+#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ -+#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ -+#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ -+#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ -+#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ -+#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ -+#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ -+#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ -+#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ -+#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ -+#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ -+#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ -+#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ -+#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ -+#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ -+#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ -+#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ -+#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ -+#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ -+#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ -+#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ -+#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ -+#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ -+#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ -+#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ -+#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ -+#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ -+#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ -+#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ -+#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ -+#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ -+#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ -+#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ -+#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ -+#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ -+#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ -+#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ -+#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ -+#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ -+#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ -+#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ -+#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ -+#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ -+#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ -+#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ -+#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ -+#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ -+#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ -+#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ -+#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ -+#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ -+#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ -+#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ -+#define R_IA64_COPY 0x84 /* copy relocation */ -+#define R_IA64_SUB 0x85 /* Addend and symbol difference */ -+#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ -+#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ -+#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ -+#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ -+#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ -+#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ -+#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ -+#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ -+#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ -+#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ -+#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ -+#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ -+#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ -+#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ -+#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ -+#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ -+ -+/* SH specific declarations */ -+ -+/* Processor specific flags for the ELF header e_flags field. */ -+#define EF_SH_MACH_MASK 0x1f -+#define EF_SH_UNKNOWN 0x0 -+#define EF_SH1 0x1 -+#define EF_SH2 0x2 -+#define EF_SH3 0x3 -+#define EF_SH_DSP 0x4 -+#define EF_SH3_DSP 0x5 -+#define EF_SH4AL_DSP 0x6 -+#define EF_SH3E 0x8 -+#define EF_SH4 0x9 -+#define EF_SH2E 0xb -+#define EF_SH4A 0xc -+#define EF_SH2A 0xd -+#define EF_SH4_NOFPU 0x10 -+#define EF_SH4A_NOFPU 0x11 -+#define EF_SH4_NOMMU_NOFPU 0x12 -+#define EF_SH2A_NOFPU 0x13 -+#define EF_SH3_NOMMU 0x14 -+#define EF_SH2A_SH4_NOFPU 0x15 -+#define EF_SH2A_SH3_NOFPU 0x16 -+#define EF_SH2A_SH4 0x17 -+#define EF_SH2A_SH3E 0x18 -+ -+/* SH relocs. */ -+#define R_SH_NONE 0 -+#define R_SH_DIR32 1 -+#define R_SH_REL32 2 -+#define R_SH_DIR8WPN 3 -+#define R_SH_IND12W 4 -+#define R_SH_DIR8WPL 5 -+#define R_SH_DIR8WPZ 6 -+#define R_SH_DIR8BP 7 -+#define R_SH_DIR8W 8 -+#define R_SH_DIR8L 9 -+#define R_SH_SWITCH16 25 -+#define R_SH_SWITCH32 26 -+#define R_SH_USES 27 -+#define R_SH_COUNT 28 -+#define R_SH_ALIGN 29 -+#define R_SH_CODE 30 -+#define R_SH_DATA 31 -+#define R_SH_LABEL 32 -+#define R_SH_SWITCH8 33 -+#define R_SH_GNU_VTINHERIT 34 -+#define R_SH_GNU_VTENTRY 35 -+#define R_SH_TLS_GD_32 144 -+#define R_SH_TLS_LD_32 145 -+#define R_SH_TLS_LDO_32 146 -+#define R_SH_TLS_IE_32 147 -+#define R_SH_TLS_LE_32 148 -+#define R_SH_TLS_DTPMOD32 149 -+#define R_SH_TLS_DTPOFF32 150 -+#define R_SH_TLS_TPOFF32 151 -+#define R_SH_GOT32 160 -+#define R_SH_PLT32 161 -+#define R_SH_COPY 162 -+#define R_SH_GLOB_DAT 163 -+#define R_SH_JMP_SLOT 164 -+#define R_SH_RELATIVE 165 -+#define R_SH_GOTOFF 166 -+#define R_SH_GOTPC 167 -+/* Keep this the last entry. */ -+#define R_SH_NUM 256 -+ -+/* S/390 specific definitions. */ -+ -+/* Valid values for the e_flags field. */ -+ -+#define EF_S390_HIGH_GPRS 0x00000001 /* High GPRs kernel facility needed. */ -+ -+/* Additional s390 relocs */ -+ -+#define R_390_NONE 0 /* No reloc. */ -+#define R_390_8 1 /* Direct 8 bit. */ -+#define R_390_12 2 /* Direct 12 bit. */ -+#define R_390_16 3 /* Direct 16 bit. */ -+#define R_390_32 4 /* Direct 32 bit. */ -+#define R_390_PC32 5 /* PC relative 32 bit. */ -+#define R_390_GOT12 6 /* 12 bit GOT offset. */ -+#define R_390_GOT32 7 /* 32 bit GOT offset. */ -+#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ -+#define R_390_COPY 9 /* Copy symbol at runtime. */ -+#define R_390_GLOB_DAT 10 /* Create GOT entry. */ -+#define R_390_JMP_SLOT 11 /* Create PLT entry. */ -+#define R_390_RELATIVE 12 /* Adjust by program base. */ -+#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ -+#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ -+#define R_390_GOT16 15 /* 16 bit GOT offset. */ -+#define R_390_PC16 16 /* PC relative 16 bit. */ -+#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ -+#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ -+#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ -+#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ -+#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ -+#define R_390_64 22 /* Direct 64 bit. */ -+#define R_390_PC64 23 /* PC relative 64 bit. */ -+#define R_390_GOT64 24 /* 64 bit GOT offset. */ -+#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ -+#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ -+#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ -+#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ -+#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ -+#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ -+#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ -+#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ -+#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ -+#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ -+#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ -+#define R_390_TLS_GDCALL 38 /* Tag for function call in general -+ dynamic TLS code. */ -+#define R_390_TLS_LDCALL 39 /* Tag for function call in local -+ dynamic TLS code. */ -+#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ -+#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ -+#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS -+ block. */ -+#define R_390_20 57 /* Direct 20 bit. */ -+#define R_390_GOT20 58 /* 20 bit GOT offset. */ -+#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */ -+#define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_IRELATIVE 61 /* STT_GNU_IFUNC relocation. */ -+/* Keep this the last entry. */ -+#define R_390_NUM 62 -+ -+ -+/* CRIS relocations. */ -+#define R_CRIS_NONE 0 -+#define R_CRIS_8 1 -+#define R_CRIS_16 2 -+#define R_CRIS_32 3 -+#define R_CRIS_8_PCREL 4 -+#define R_CRIS_16_PCREL 5 -+#define R_CRIS_32_PCREL 6 -+#define R_CRIS_GNU_VTINHERIT 7 -+#define R_CRIS_GNU_VTENTRY 8 -+#define R_CRIS_COPY 9 -+#define R_CRIS_GLOB_DAT 10 -+#define R_CRIS_JUMP_SLOT 11 -+#define R_CRIS_RELATIVE 12 -+#define R_CRIS_16_GOT 13 -+#define R_CRIS_32_GOT 14 -+#define R_CRIS_16_GOTPLT 15 -+#define R_CRIS_32_GOTPLT 16 -+#define R_CRIS_32_GOTREL 17 -+#define R_CRIS_32_PLT_GOTREL 18 -+#define R_CRIS_32_PLT_PCREL 19 -+ -+#define R_CRIS_NUM 20 -+ -+ -+/* AMD x86-64 relocations. */ -+#define R_X86_64_NONE 0 /* No reloc */ -+#define R_X86_64_64 1 /* Direct 64 bit */ -+#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ -+#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ -+#define R_X86_64_PLT32 4 /* 32 bit PLT address */ -+#define R_X86_64_COPY 5 /* Copy symbol at runtime */ -+#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ -+#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ -+#define R_X86_64_RELATIVE 8 /* Adjust by program base */ -+#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative -+ offset to GOT */ -+#define R_X86_64_32 10 /* Direct 32 bit zero extended */ -+#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ -+#define R_X86_64_16 12 /* Direct 16 bit zero extended */ -+#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ -+#define R_X86_64_8 14 /* Direct 8 bit sign extended */ -+#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ -+#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ -+#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ -+#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ -+#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset -+ to two GOT entries for GD symbol */ -+#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset -+ to two GOT entries for LD symbol */ -+#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ -+#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset -+ to GOT entry for IE symbol */ -+#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ -+#define R_X86_64_PC64 24 /* PC relative 64 bit */ -+#define R_X86_64_GOTOFF64 25 /* 64 bit offset to GOT */ -+#define R_X86_64_GOTPC32 26 /* 32 bit signed pc relative -+ offset to GOT */ -+#define R_X86_64_GOT64 27 /* 64-bit GOT entry offset */ -+#define R_X86_64_GOTPCREL64 28 /* 64-bit PC relative offset -+ to GOT entry */ -+#define R_X86_64_GOTPC64 29 /* 64-bit PC relative offset to GOT */ -+#define R_X86_64_GOTPLT64 30 /* like GOT64, says PLT entry needed */ -+#define R_X86_64_PLTOFF64 31 /* 64-bit GOT relative offset -+ to PLT entry */ -+#define R_X86_64_SIZE32 32 /* Size of symbol plus 32-bit addend */ -+#define R_X86_64_SIZE64 33 /* Size of symbol plus 64-bit addend */ -+#define R_X86_64_GOTPC32_TLSDESC 34 /* GOT offset for TLS descriptor. */ -+#define R_X86_64_TLSDESC_CALL 35 /* Marker for call through TLS -+ descriptor. */ -+#define R_X86_64_TLSDESC 36 /* TLS descriptor. */ -+#define R_X86_64_IRELATIVE 37 /* Adjust indirectly by program base */ -+#define R_X86_64_RELATIVE64 38 /* 64-bit adjust by program base */ -+ -+#define R_X86_64_NUM 39 -+ -+ -+/* AM33 relocations. */ -+#define R_MN10300_NONE 0 /* No reloc. */ -+#define R_MN10300_32 1 /* Direct 32 bit. */ -+#define R_MN10300_16 2 /* Direct 16 bit. */ -+#define R_MN10300_8 3 /* Direct 8 bit. */ -+#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ -+#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ -+#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ -+#define R_MN10300_GNU_VTINHERIT 7 /* Ancient C++ vtable garbage... */ -+#define R_MN10300_GNU_VTENTRY 8 /* ... collection annotation. */ -+#define R_MN10300_24 9 /* Direct 24 bit. */ -+#define R_MN10300_GOTPC32 10 /* 32-bit PCrel offset to GOT. */ -+#define R_MN10300_GOTPC16 11 /* 16-bit PCrel offset to GOT. */ -+#define R_MN10300_GOTOFF32 12 /* 32-bit offset from GOT. */ -+#define R_MN10300_GOTOFF24 13 /* 24-bit offset from GOT. */ -+#define R_MN10300_GOTOFF16 14 /* 16-bit offset from GOT. */ -+#define R_MN10300_PLT32 15 /* 32-bit PCrel to PLT entry. */ -+#define R_MN10300_PLT16 16 /* 16-bit PCrel to PLT entry. */ -+#define R_MN10300_GOT32 17 /* 32-bit offset to GOT entry. */ -+#define R_MN10300_GOT24 18 /* 24-bit offset to GOT entry. */ -+#define R_MN10300_GOT16 19 /* 16-bit offset to GOT entry. */ -+#define R_MN10300_COPY 20 /* Copy symbol at runtime. */ -+#define R_MN10300_GLOB_DAT 21 /* Create GOT entry. */ -+#define R_MN10300_JMP_SLOT 22 /* Create PLT entry. */ -+#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ -+ -+#define R_MN10300_NUM 24 -+ -+ -+/* M32R relocs. */ -+#define R_M32R_NONE 0 /* No reloc. */ -+#define R_M32R_16 1 /* Direct 16 bit. */ -+#define R_M32R_32 2 /* Direct 32 bit. */ -+#define R_M32R_24 3 /* Direct 24 bit. */ -+#define R_M32R_10_PCREL 4 /* PC relative 10 bit shifted. */ -+#define R_M32R_18_PCREL 5 /* PC relative 18 bit shifted. */ -+#define R_M32R_26_PCREL 6 /* PC relative 26 bit shifted. */ -+#define R_M32R_HI16_ULO 7 /* High 16 bit with unsigned low. */ -+#define R_M32R_HI16_SLO 8 /* High 16 bit with signed low. */ -+#define R_M32R_LO16 9 /* Low 16 bit. */ -+#define R_M32R_SDA16 10 /* 16 bit offset in SDA. */ -+#define R_M32R_GNU_VTINHERIT 11 -+#define R_M32R_GNU_VTENTRY 12 -+/* M32R relocs use SHT_RELA. */ -+#define R_M32R_16_RELA 33 /* Direct 16 bit. */ -+#define R_M32R_32_RELA 34 /* Direct 32 bit. */ -+#define R_M32R_24_RELA 35 /* Direct 24 bit. */ -+#define R_M32R_10_PCREL_RELA 36 /* PC relative 10 bit shifted. */ -+#define R_M32R_18_PCREL_RELA 37 /* PC relative 18 bit shifted. */ -+#define R_M32R_26_PCREL_RELA 38 /* PC relative 26 bit shifted. */ -+#define R_M32R_HI16_ULO_RELA 39 /* High 16 bit with unsigned low */ -+#define R_M32R_HI16_SLO_RELA 40 /* High 16 bit with signed low */ -+#define R_M32R_LO16_RELA 41 /* Low 16 bit */ -+#define R_M32R_SDA16_RELA 42 /* 16 bit offset in SDA */ -+#define R_M32R_RELA_GNU_VTINHERIT 43 -+#define R_M32R_RELA_GNU_VTENTRY 44 -+#define R_M32R_REL32 45 /* PC relative 32 bit. */ -+ -+#define R_M32R_GOT24 48 /* 24 bit GOT entry */ -+#define R_M32R_26_PLTREL 49 /* 26 bit PC relative to PLT shifted */ -+#define R_M32R_COPY 50 /* Copy symbol at runtime */ -+#define R_M32R_GLOB_DAT 51 /* Create GOT entry */ -+#define R_M32R_JMP_SLOT 52 /* Create PLT entry */ -+#define R_M32R_RELATIVE 53 /* Adjust by program base */ -+#define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */ -+#define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */ -+#define R_M32R_GOT16_HI_ULO 56 /* High 16 bit GOT entry with unsigned -+ low */ -+#define R_M32R_GOT16_HI_SLO 57 /* High 16 bit GOT entry with signed -+ low */ -+#define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */ -+#define R_M32R_GOTPC_HI_ULO 59 /* High 16 bit PC relative offset to -+ GOT with unsigned low */ -+#define R_M32R_GOTPC_HI_SLO 60 /* High 16 bit PC relative offset to -+ GOT with signed low */ -+#define R_M32R_GOTPC_LO 61 /* Low 16 bit PC relative offset to -+ GOT */ -+#define R_M32R_GOTOFF_HI_ULO 62 /* High 16 bit offset to GOT -+ with unsigned low */ -+#define R_M32R_GOTOFF_HI_SLO 63 /* High 16 bit offset to GOT -+ with signed low */ -+#define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */ -+#define R_M32R_NUM 256 /* Keep this the last entry. */ -+ -+ -+/* TILEPro relocations. */ -+#define R_TILEPRO_NONE 0 /* No reloc */ -+#define R_TILEPRO_32 1 /* Direct 32 bit */ -+#define R_TILEPRO_16 2 /* Direct 16 bit */ -+#define R_TILEPRO_8 3 /* Direct 8 bit */ -+#define R_TILEPRO_32_PCREL 4 /* PC relative 32 bit */ -+#define R_TILEPRO_16_PCREL 5 /* PC relative 16 bit */ -+#define R_TILEPRO_8_PCREL 6 /* PC relative 8 bit */ -+#define R_TILEPRO_LO16 7 /* Low 16 bit */ -+#define R_TILEPRO_HI16 8 /* High 16 bit */ -+#define R_TILEPRO_HA16 9 /* High 16 bit, adjusted */ -+#define R_TILEPRO_COPY 10 /* Copy relocation */ -+#define R_TILEPRO_GLOB_DAT 11 /* Create GOT entry */ -+#define R_TILEPRO_JMP_SLOT 12 /* Create PLT entry */ -+#define R_TILEPRO_RELATIVE 13 /* Adjust by program base */ -+#define R_TILEPRO_BROFF_X1 14 /* X1 pipe branch offset */ -+#define R_TILEPRO_JOFFLONG_X1 15 /* X1 pipe jump offset */ -+#define R_TILEPRO_JOFFLONG_X1_PLT 16 /* X1 pipe jump offset to PLT */ -+#define R_TILEPRO_IMM8_X0 17 /* X0 pipe 8-bit */ -+#define R_TILEPRO_IMM8_Y0 18 /* Y0 pipe 8-bit */ -+#define R_TILEPRO_IMM8_X1 19 /* X1 pipe 8-bit */ -+#define R_TILEPRO_IMM8_Y1 20 /* Y1 pipe 8-bit */ -+#define R_TILEPRO_MT_IMM15_X1 21 /* X1 pipe mtspr */ -+#define R_TILEPRO_MF_IMM15_X1 22 /* X1 pipe mfspr */ -+#define R_TILEPRO_IMM16_X0 23 /* X0 pipe 16-bit */ -+#define R_TILEPRO_IMM16_X1 24 /* X1 pipe 16-bit */ -+#define R_TILEPRO_IMM16_X0_LO 25 /* X0 pipe low 16-bit */ -+#define R_TILEPRO_IMM16_X1_LO 26 /* X1 pipe low 16-bit */ -+#define R_TILEPRO_IMM16_X0_HI 27 /* X0 pipe high 16-bit */ -+#define R_TILEPRO_IMM16_X1_HI 28 /* X1 pipe high 16-bit */ -+#define R_TILEPRO_IMM16_X0_HA 29 /* X0 pipe high 16-bit, adjusted */ -+#define R_TILEPRO_IMM16_X1_HA 30 /* X1 pipe high 16-bit, adjusted */ -+#define R_TILEPRO_IMM16_X0_PCREL 31 /* X0 pipe PC relative 16 bit */ -+#define R_TILEPRO_IMM16_X1_PCREL 32 /* X1 pipe PC relative 16 bit */ -+#define R_TILEPRO_IMM16_X0_LO_PCREL 33 /* X0 pipe PC relative low 16 bit */ -+#define R_TILEPRO_IMM16_X1_LO_PCREL 34 /* X1 pipe PC relative low 16 bit */ -+#define R_TILEPRO_IMM16_X0_HI_PCREL 35 /* X0 pipe PC relative high 16 bit */ -+#define R_TILEPRO_IMM16_X1_HI_PCREL 36 /* X1 pipe PC relative high 16 bit */ -+#define R_TILEPRO_IMM16_X0_HA_PCREL 37 /* X0 pipe PC relative ha() 16 bit */ -+#define R_TILEPRO_IMM16_X1_HA_PCREL 38 /* X1 pipe PC relative ha() 16 bit */ -+#define R_TILEPRO_IMM16_X0_GOT 39 /* X0 pipe 16-bit GOT offset */ -+#define R_TILEPRO_IMM16_X1_GOT 40 /* X1 pipe 16-bit GOT offset */ -+#define R_TILEPRO_IMM16_X0_GOT_LO 41 /* X0 pipe low 16-bit GOT offset */ -+#define R_TILEPRO_IMM16_X1_GOT_LO 42 /* X1 pipe low 16-bit GOT offset */ -+#define R_TILEPRO_IMM16_X0_GOT_HI 43 /* X0 pipe high 16-bit GOT offset */ -+#define R_TILEPRO_IMM16_X1_GOT_HI 44 /* X1 pipe high 16-bit GOT offset */ -+#define R_TILEPRO_IMM16_X0_GOT_HA 45 /* X0 pipe ha() 16-bit GOT offset */ -+#define R_TILEPRO_IMM16_X1_GOT_HA 46 /* X1 pipe ha() 16-bit GOT offset */ -+#define R_TILEPRO_MMSTART_X0 47 /* X0 pipe mm "start" */ -+#define R_TILEPRO_MMEND_X0 48 /* X0 pipe mm "end" */ -+#define R_TILEPRO_MMSTART_X1 49 /* X1 pipe mm "start" */ -+#define R_TILEPRO_MMEND_X1 50 /* X1 pipe mm "end" */ -+#define R_TILEPRO_SHAMT_X0 51 /* X0 pipe shift amount */ -+#define R_TILEPRO_SHAMT_X1 52 /* X1 pipe shift amount */ -+#define R_TILEPRO_SHAMT_Y0 53 /* Y0 pipe shift amount */ -+#define R_TILEPRO_SHAMT_Y1 54 /* Y1 pipe shift amount */ -+#define R_TILEPRO_DEST_IMM8_X1 55 /* X1 pipe destination 8-bit */ -+/* Relocs 56-59 are currently not defined. */ -+#define R_TILEPRO_TLS_GD_CALL 60 /* "jal" for TLS GD */ -+#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61 /* X0 pipe "addi" for TLS GD */ -+#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62 /* X1 pipe "addi" for TLS GD */ -+#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63 /* Y0 pipe "addi" for TLS GD */ -+#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64 /* Y1 pipe "addi" for TLS GD */ -+#define R_TILEPRO_TLS_IE_LOAD 65 /* "lw_tls" for TLS IE */ -+#define R_TILEPRO_IMM16_X0_TLS_GD 66 /* X0 pipe 16-bit TLS GD offset */ -+#define R_TILEPRO_IMM16_X1_TLS_GD 67 /* X1 pipe 16-bit TLS GD offset */ -+#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68 /* X0 pipe low 16-bit TLS GD offset */ -+#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69 /* X1 pipe low 16-bit TLS GD offset */ -+#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70 /* X0 pipe high 16-bit TLS GD offset */ -+#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71 /* X1 pipe high 16-bit TLS GD offset */ -+#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72 /* X0 pipe ha() 16-bit TLS GD offset */ -+#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73 /* X1 pipe ha() 16-bit TLS GD offset */ -+#define R_TILEPRO_IMM16_X0_TLS_IE 74 /* X0 pipe 16-bit TLS IE offset */ -+#define R_TILEPRO_IMM16_X1_TLS_IE 75 /* X1 pipe 16-bit TLS IE offset */ -+#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76 /* X0 pipe low 16-bit TLS IE offset */ -+#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77 /* X1 pipe low 16-bit TLS IE offset */ -+#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78 /* X0 pipe high 16-bit TLS IE offset */ -+#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79 /* X1 pipe high 16-bit TLS IE offset */ -+#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80 /* X0 pipe ha() 16-bit TLS IE offset */ -+#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81 /* X1 pipe ha() 16-bit TLS IE offset */ -+#define R_TILEPRO_TLS_DTPMOD32 82 /* ID of module containing symbol */ -+#define R_TILEPRO_TLS_DTPOFF32 83 /* Offset in TLS block */ -+#define R_TILEPRO_TLS_TPOFF32 84 /* Offset in static TLS block */ -+#define R_TILEPRO_IMM16_X0_TLS_LE 85 /* X0 pipe 16-bit TLS LE offset */ -+#define R_TILEPRO_IMM16_X1_TLS_LE 86 /* X1 pipe 16-bit TLS LE offset */ -+#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87 /* X0 pipe low 16-bit TLS LE offset */ -+#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88 /* X1 pipe low 16-bit TLS LE offset */ -+#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89 /* X0 pipe high 16-bit TLS LE offset */ -+#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90 /* X1 pipe high 16-bit TLS LE offset */ -+#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91 /* X0 pipe ha() 16-bit TLS LE offset */ -+#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92 /* X1 pipe ha() 16-bit TLS LE offset */ -+ -+#define R_TILEPRO_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ -+#define R_TILEPRO_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ -+ -+#define R_TILEPRO_NUM 130 -+ -+ -+/* TILE-Gx relocations. */ -+#define R_TILEGX_NONE 0 /* No reloc */ -+#define R_TILEGX_64 1 /* Direct 64 bit */ -+#define R_TILEGX_32 2 /* Direct 32 bit */ -+#define R_TILEGX_16 3 /* Direct 16 bit */ -+#define R_TILEGX_8 4 /* Direct 8 bit */ -+#define R_TILEGX_64_PCREL 5 /* PC relative 64 bit */ -+#define R_TILEGX_32_PCREL 6 /* PC relative 32 bit */ -+#define R_TILEGX_16_PCREL 7 /* PC relative 16 bit */ -+#define R_TILEGX_8_PCREL 8 /* PC relative 8 bit */ -+#define R_TILEGX_HW0 9 /* hword 0 16-bit */ -+#define R_TILEGX_HW1 10 /* hword 1 16-bit */ -+#define R_TILEGX_HW2 11 /* hword 2 16-bit */ -+#define R_TILEGX_HW3 12 /* hword 3 16-bit */ -+#define R_TILEGX_HW0_LAST 13 /* last hword 0 16-bit */ -+#define R_TILEGX_HW1_LAST 14 /* last hword 1 16-bit */ -+#define R_TILEGX_HW2_LAST 15 /* last hword 2 16-bit */ -+#define R_TILEGX_COPY 16 /* Copy relocation */ -+#define R_TILEGX_GLOB_DAT 17 /* Create GOT entry */ -+#define R_TILEGX_JMP_SLOT 18 /* Create PLT entry */ -+#define R_TILEGX_RELATIVE 19 /* Adjust by program base */ -+#define R_TILEGX_BROFF_X1 20 /* X1 pipe branch offset */ -+#define R_TILEGX_JUMPOFF_X1 21 /* X1 pipe jump offset */ -+#define R_TILEGX_JUMPOFF_X1_PLT 22 /* X1 pipe jump offset to PLT */ -+#define R_TILEGX_IMM8_X0 23 /* X0 pipe 8-bit */ -+#define R_TILEGX_IMM8_Y0 24 /* Y0 pipe 8-bit */ -+#define R_TILEGX_IMM8_X1 25 /* X1 pipe 8-bit */ -+#define R_TILEGX_IMM8_Y1 26 /* Y1 pipe 8-bit */ -+#define R_TILEGX_DEST_IMM8_X1 27 /* X1 pipe destination 8-bit */ -+#define R_TILEGX_MT_IMM14_X1 28 /* X1 pipe mtspr */ -+#define R_TILEGX_MF_IMM14_X1 29 /* X1 pipe mfspr */ -+#define R_TILEGX_MMSTART_X0 30 /* X0 pipe mm "start" */ -+#define R_TILEGX_MMEND_X0 31 /* X0 pipe mm "end" */ -+#define R_TILEGX_SHAMT_X0 32 /* X0 pipe shift amount */ -+#define R_TILEGX_SHAMT_X1 33 /* X1 pipe shift amount */ -+#define R_TILEGX_SHAMT_Y0 34 /* Y0 pipe shift amount */ -+#define R_TILEGX_SHAMT_Y1 35 /* Y1 pipe shift amount */ -+#define R_TILEGX_IMM16_X0_HW0 36 /* X0 pipe hword 0 */ -+#define R_TILEGX_IMM16_X1_HW0 37 /* X1 pipe hword 0 */ -+#define R_TILEGX_IMM16_X0_HW1 38 /* X0 pipe hword 1 */ -+#define R_TILEGX_IMM16_X1_HW1 39 /* X1 pipe hword 1 */ -+#define R_TILEGX_IMM16_X0_HW2 40 /* X0 pipe hword 2 */ -+#define R_TILEGX_IMM16_X1_HW2 41 /* X1 pipe hword 2 */ -+#define R_TILEGX_IMM16_X0_HW3 42 /* X0 pipe hword 3 */ -+#define R_TILEGX_IMM16_X1_HW3 43 /* X1 pipe hword 3 */ -+#define R_TILEGX_IMM16_X0_HW0_LAST 44 /* X0 pipe last hword 0 */ -+#define R_TILEGX_IMM16_X1_HW0_LAST 45 /* X1 pipe last hword 0 */ -+#define R_TILEGX_IMM16_X0_HW1_LAST 46 /* X0 pipe last hword 1 */ -+#define R_TILEGX_IMM16_X1_HW1_LAST 47 /* X1 pipe last hword 1 */ -+#define R_TILEGX_IMM16_X0_HW2_LAST 48 /* X0 pipe last hword 2 */ -+#define R_TILEGX_IMM16_X1_HW2_LAST 49 /* X1 pipe last hword 2 */ -+#define R_TILEGX_IMM16_X0_HW0_PCREL 50 /* X0 pipe PC relative hword 0 */ -+#define R_TILEGX_IMM16_X1_HW0_PCREL 51 /* X1 pipe PC relative hword 0 */ -+#define R_TILEGX_IMM16_X0_HW1_PCREL 52 /* X0 pipe PC relative hword 1 */ -+#define R_TILEGX_IMM16_X1_HW1_PCREL 53 /* X1 pipe PC relative hword 1 */ -+#define R_TILEGX_IMM16_X0_HW2_PCREL 54 /* X0 pipe PC relative hword 2 */ -+#define R_TILEGX_IMM16_X1_HW2_PCREL 55 /* X1 pipe PC relative hword 2 */ -+#define R_TILEGX_IMM16_X0_HW3_PCREL 56 /* X0 pipe PC relative hword 3 */ -+#define R_TILEGX_IMM16_X1_HW3_PCREL 57 /* X1 pipe PC relative hword 3 */ -+#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */ -+#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */ -+#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */ -+#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */ -+#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */ -+#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */ -+#define R_TILEGX_IMM16_X0_HW0_GOT 64 /* X0 pipe hword 0 GOT offset */ -+#define R_TILEGX_IMM16_X1_HW0_GOT 65 /* X1 pipe hword 0 GOT offset */ -+/* Relocs 66-71 are currently not defined. */ -+#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */ -+#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */ -+#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */ -+#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */ -+/* Relocs 76-77 are currently not defined. */ -+#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78 /* X0 pipe hword 0 TLS GD offset */ -+#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79 /* X1 pipe hword 0 TLS GD offset */ -+#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80 /* X0 pipe hword 0 TLS LE offset */ -+#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81 /* X1 pipe hword 0 TLS LE offset */ -+#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */ -+#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */ -+#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */ -+#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */ -+#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */ -+#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */ -+#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */ -+#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */ -+/* Relocs 90-91 are currently not defined. */ -+#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92 /* X0 pipe hword 0 TLS IE offset */ -+#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93 /* X1 pipe hword 0 TLS IE offset */ -+/* Relocs 94-99 are currently not defined. */ -+#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */ -+#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */ -+#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */ -+#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */ -+/* Relocs 104-105 are currently not defined. */ -+#define R_TILEGX_TLS_DTPMOD64 106 /* 64-bit ID of symbol's module */ -+#define R_TILEGX_TLS_DTPOFF64 107 /* 64-bit offset in TLS block */ -+#define R_TILEGX_TLS_TPOFF64 108 /* 64-bit offset in static TLS block */ -+#define R_TILEGX_TLS_DTPMOD32 109 /* 32-bit ID of symbol's module */ -+#define R_TILEGX_TLS_DTPOFF32 110 /* 32-bit offset in TLS block */ -+#define R_TILEGX_TLS_TPOFF32 111 /* 32-bit offset in static TLS block */ -+#define R_TILEGX_TLS_GD_CALL 112 /* "jal" for TLS GD */ -+#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113 /* X0 pipe "addi" for TLS GD */ -+#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114 /* X1 pipe "addi" for TLS GD */ -+#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115 /* Y0 pipe "addi" for TLS GD */ -+#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116 /* Y1 pipe "addi" for TLS GD */ -+#define R_TILEGX_TLS_IE_LOAD 117 /* "ld_tls" for TLS IE */ -+#define R_TILEGX_IMM8_X0_TLS_ADD 118 /* X0 pipe "addi" for TLS GD/IE */ -+#define R_TILEGX_IMM8_X1_TLS_ADD 119 /* X1 pipe "addi" for TLS GD/IE */ -+#define R_TILEGX_IMM8_Y0_TLS_ADD 120 /* Y0 pipe "addi" for TLS GD/IE */ -+#define R_TILEGX_IMM8_Y1_TLS_ADD 121 /* Y1 pipe "addi" for TLS GD/IE */ -+ -+#define R_TILEGX_GNU_VTINHERIT 128 /* GNU C++ vtable hierarchy */ -+#define R_TILEGX_GNU_VTENTRY 129 /* GNU C++ vtable member usage */ -+ -+#define R_TILEGX_NUM 130 -+ -+#endif /* elf.h */ ---- a/scripts/mod/mk_elfconfig.c -+++ b/scripts/mod/mk_elfconfig.c -@@ -2,7 +2,11 @@ - #include - #include - #include -+#ifndef __APPLE__ - #include -+#else -+#include "elf.h" -+#endif - - int - main(int argc, char **argv) ---- a/scripts/mod/modpost.h -+++ b/scripts/mod/modpost.h -@@ -8,7 +8,11 @@ - #include - #include - #include -+#if !(defined(__APPLE__) || defined(__CYGWIN__)) - #include -+#else -+#include "elf.h" -+#endif - - #include "elfconfig.h" - diff --git a/target/linux/generic/hack-5.10/211-darwin-uuid-typedef-clash.patch b/target/linux/generic/hack-5.10/211-darwin-uuid-typedef-clash.patch deleted file mode 100644 index 50a6227148..0000000000 --- a/target/linux/generic/hack-5.10/211-darwin-uuid-typedef-clash.patch +++ /dev/null @@ -1,22 +0,0 @@ -From e44fc2af1ddc452b6659d08c16973d65c73b7d0a Mon Sep 17 00:00:00 2001 -From: Kevin Darbyshire-Bryant -Date: Wed, 5 Feb 2020 18:36:43 +0000 -Subject: [PATCH] file2alias: build on macos - -Signed-off-by: Kevin Darbyshire-Bryant ---- - scripts/mod/file2alias.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/scripts/mod/file2alias.c -+++ b/scripts/mod/file2alias.c -@@ -38,6 +38,9 @@ typedef struct { - __u8 b[16]; - } guid_t; - -+#ifdef __APPLE__ -+#define uuid_t compat_uuid_t -+#endif - /* backwards compatibility, don't use in new code */ - typedef struct { - __u8 b[16]; diff --git a/target/linux/generic/hack-5.10/212-tools_portability.patch b/target/linux/generic/hack-5.10/212-tools_portability.patch deleted file mode 100644 index 0d8eb6fb9d..0000000000 --- a/target/linux/generic/hack-5.10/212-tools_portability.patch +++ /dev/null @@ -1,110 +0,0 @@ -From 48232d3d931c95953ce2ddfe7da7bb164aef6a73 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Fri, 7 Jul 2017 17:03:16 +0200 -Subject: fix portability of some includes files in tools/ used on the host - -Signed-off-by: Felix Fietkau ---- - tools/include/tools/be_byteshift.h | 4 ++++ - tools/include/tools/le_byteshift.h | 4 ++++ - tools/include/tools/linux_types.h | 22 ++++++++++++++++++++++ - 3 files changed, 30 insertions(+) - create mode 100644 tools/include/tools/linux_types.h - ---- a/tools/include/tools/be_byteshift.h -+++ b/tools/include/tools/be_byteshift.h -@@ -2,6 +2,10 @@ - #ifndef _TOOLS_BE_BYTESHIFT_H - #define _TOOLS_BE_BYTESHIFT_H - -+#ifndef __linux__ -+#include "linux_types.h" -+#endif -+ - #include - - static inline uint16_t __get_unaligned_be16(const uint8_t *p) ---- a/tools/include/tools/le_byteshift.h -+++ b/tools/include/tools/le_byteshift.h -@@ -2,6 +2,10 @@ - #ifndef _TOOLS_LE_BYTESHIFT_H - #define _TOOLS_LE_BYTESHIFT_H - -+#ifndef __linux__ -+#include "linux_types.h" -+#endif -+ - #include - - static inline uint16_t __get_unaligned_le16(const uint8_t *p) ---- /dev/null -+++ b/tools/include/tools/linux_types.h -@@ -0,0 +1,26 @@ -+#ifndef __LINUX_TYPES_H -+#define __LINUX_TYPES_H -+ -+#include -+ -+typedef int8_t __s8; -+typedef uint8_t __u8; -+typedef uint8_t __be8; -+typedef uint8_t __le8; -+ -+typedef int16_t __s16; -+typedef uint16_t __u16; -+typedef uint16_t __be16; -+typedef uint16_t __le16; -+ -+typedef int32_t __s32; -+typedef uint32_t __u32; -+typedef uint32_t __be32; -+typedef uint32_t __le32; -+ -+typedef int64_t __s64; -+typedef uint64_t __u64; -+typedef uint64_t __be64; -+typedef uint64_t __le64; -+ -+#endif ---- a/tools/include/linux/types.h -+++ b/tools/include/linux/types.h -@@ -7,8 +7,12 @@ - #include - - #define __SANE_USERSPACE_TYPES__ /* For PPC64, to get LL64 types */ -+#ifndef __linux__ -+#include -+#else - #include - #include -+#endif - - struct page; - struct kmem_cache; ---- a/tools/perf/pmu-events/jevents.c -+++ b/tools/perf/pmu-events/jevents.c -@@ -1,4 +1,6 @@ -+#ifdef __linux__ - #define _XOPEN_SOURCE 500 /* needed for nftw() */ -+#endif - #define _GNU_SOURCE /* needed for asprintf() */ - - /* Parse event JSON files */ -@@ -35,6 +37,7 @@ - #include - #include - #include -+#include - #include - #include - #include ---- a/tools/perf/pmu-events/json.c -+++ b/tools/perf/pmu-events/json.c -@@ -38,7 +38,6 @@ - #include - #include "jsmn.h" - #include "json.h" --#include - - - static char *mapfile(const char *fn, size_t *size) diff --git a/target/linux/generic/hack-5.10/214-spidev_h_portability.patch b/target/linux/generic/hack-5.10/214-spidev_h_portability.patch deleted file mode 100644 index 506d50ad4d..0000000000 --- a/target/linux/generic/hack-5.10/214-spidev_h_portability.patch +++ /dev/null @@ -1,24 +0,0 @@ -From be9be95ff10e16a5b4ad36f903978d0cc5747024 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Fri, 7 Jul 2017 17:04:08 +0200 -Subject: kernel: fix linux/spi/spidev.h portability issues with musl - -Felix will try to get this define included into musl - -lede-commit: 795e7cf60de19e7a076a46874fab7bb88b43bbff -Signed-off-by: Felix Fietkau ---- - include/uapi/linux/spi/spidev.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/include/uapi/linux/spi/spidev.h -+++ b/include/uapi/linux/spi/spidev.h -@@ -121,7 +121,7 @@ struct spi_ioc_transfer { - - /* not all platforms use or _IOC_TYPECHECK() ... */ - #define SPI_MSGSIZE(N) \ -- ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ -+ ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << 13)) \ - ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0) - #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) - diff --git a/target/linux/generic/hack-5.10/220-arm-gc_sections.patch b/target/linux/generic/hack-5.10/220-arm-gc_sections.patch deleted file mode 100644 index 5b36c5ebae..0000000000 --- a/target/linux/generic/hack-5.10/220-arm-gc_sections.patch +++ /dev/null @@ -1,123 +0,0 @@ -From e3d8676f5722b7622685581e06e8f53e6138e3ab Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 15 Jul 2017 23:42:36 +0200 -Subject: use -ffunction-sections, -fdata-sections and --gc-sections - -In combination with kernel symbol export stripping this significantly reduces -the kernel image size. Used on both ARM and MIPS architectures. - -Signed-off-by: Felix Fietkau -Signed-off-by: Jonas Gorski -Signed-off-by: Gabor Juhos ---- ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -114,6 +114,7 @@ config ARM - select HAVE_UID16 - select HAVE_VIRT_CPU_ACCOUNTING_GEN - select IRQ_FORCED_THREADING -+ select HAVE_LD_DEAD_CODE_DATA_ELIMINATION - select MODULES_USE_ELF_REL - select NEED_DMA_MAP_STATE - select OF_EARLY_FLATTREE if OF ---- a/arch/arm/boot/compressed/Makefile -+++ b/arch/arm/boot/compressed/Makefile -@@ -100,6 +100,7 @@ $(foreach o, $(libfdt_objs) atags_to_fdt - ifdef building_out_of_srctree - $(shell rm -f $(addprefix $(obj)/, fdt_rw.c fdt_ro.c fdt_wip.c fdt.c)) - endif -+KBUILD_CFLAGS_KERNEL := $(patsubst -f%-sections,,$(KBUILD_CFLAGS_KERNEL)) - - targets := vmlinux vmlinux.lds piggy_data piggy.o \ - lib1funcs.o ashldi3.o bswapsdi2.o \ ---- a/arch/arm/kernel/vmlinux.lds.S -+++ b/arch/arm/kernel/vmlinux.lds.S -@@ -75,7 +75,7 @@ SECTIONS - . = ALIGN(4); - __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { - __start___ex_table = .; -- ARM_MMU_KEEP(*(__ex_table)) -+ KEEP(*(__ex_table)) - __stop___ex_table = .; - } - -@@ -100,24 +100,24 @@ SECTIONS - } - .init.arch.info : { - __arch_info_begin = .; -- *(.arch.info.init) -+ KEEP(*(.arch.info.init)) - __arch_info_end = .; - } - .init.tagtable : { - __tagtable_begin = .; -- *(.taglist.init) -+ KEEP(*(.taglist.init)) - __tagtable_end = .; - } - #ifdef CONFIG_SMP_ON_UP - .init.smpalt : { - __smpalt_begin = .; -- *(.alt.smp.init) -+ KEEP(*(.alt.smp.init)) - __smpalt_end = .; - } - #endif - .init.pv_table : { - __pv_table_begin = .; -- *(.pv_table) -+ KEEP(*(.pv_table)) - __pv_table_end = .; - } - ---- a/arch/arm/include/asm/vmlinux.lds.h -+++ b/arch/arm/include/asm/vmlinux.lds.h -@@ -42,13 +42,13 @@ - #define PROC_INFO \ - . = ALIGN(4); \ - __proc_info_begin = .; \ -- *(.proc.info.init) \ -+ KEEP(*(.proc.info.init)) \ - __proc_info_end = .; - - #define IDMAP_TEXT \ - ALIGN_FUNCTION(); \ - __idmap_text_start = .; \ -- *(.idmap.text) \ -+ KEEP(*(.idmap.text)) \ - __idmap_text_end = .; \ - - #define ARM_DISCARD \ -@@ -109,12 +109,12 @@ - . = ALIGN(8); \ - .ARM.unwind_idx : { \ - __start_unwind_idx = .; \ -- *(.ARM.exidx*) \ -+ KEEP(*(.ARM.exidx*)) \ - __stop_unwind_idx = .; \ - } \ - .ARM.unwind_tab : { \ - __start_unwind_tab = .; \ -- *(.ARM.extab*) \ -+ KEEP(*(.ARM.extab*)) \ - __stop_unwind_tab = .; \ - } - -@@ -126,7 +126,7 @@ - __vectors_lma = .; \ - OVERLAY 0xffff0000 : NOCROSSREFS AT(__vectors_lma) { \ - .vectors { \ -- *(.vectors) \ -+ KEEP(*(.vectors)) \ - } \ - .vectors.bhb.loop8 { \ - *(.vectors.bhb.loop8) \ -@@ -144,7 +144,7 @@ - \ - __stubs_lma = .; \ - .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_lma) { \ -- *(.stubs) \ -+ KEEP(*(.stubs)) \ - } \ - ARM_LMA(__stubs, .stubs); \ - . = __stubs_lma + SIZEOF(.stubs); \ diff --git a/target/linux/generic/hack-5.10/221-module_exports.patch b/target/linux/generic/hack-5.10/221-module_exports.patch deleted file mode 100644 index 8525e76486..0000000000 --- a/target/linux/generic/hack-5.10/221-module_exports.patch +++ /dev/null @@ -1,126 +0,0 @@ -From b14784e7883390c20ed3ff904892255404a5914b Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Fri, 7 Jul 2017 17:05:53 +0200 -Subject: add an optional config option for stripping all unnecessary symbol exports from the kernel image - -lede-commit: bb5a40c64b7c4f4848509fa0a6625055fc9e66cc -Signed-off-by: Felix Fietkau ---- - include/asm-generic/vmlinux.lds.h | 18 +++++++++++++++--- - include/linux/export.h | 9 ++++++++- - scripts/Makefile.build | 2 +- - 3 files changed, 24 insertions(+), 5 deletions(-) - ---- a/include/asm-generic/vmlinux.lds.h -+++ b/include/asm-generic/vmlinux.lds.h -@@ -81,6 +81,16 @@ - #define RO_EXCEPTION_TABLE - #endif - -+#ifndef SYMTAB_KEEP -+#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*))) -+#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*))) -+#endif -+ -+#ifndef SYMTAB_DISCARD -+#define SYMTAB_DISCARD -+#define SYMTAB_DISCARD_GPL -+#endif -+ - /* Align . to a 8 byte boundary equals to maximum function alignment. */ - #define ALIGN_FUNCTION() . = ALIGN(8) - -@@ -474,14 +484,14 @@ - /* Kernel symbol table: Normal symbols */ \ - __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ - __start___ksymtab = .; \ -- KEEP(*(SORT(___ksymtab+*))) \ -+ SYMTAB_KEEP \ - __stop___ksymtab = .; \ - } \ - \ - /* Kernel symbol table: GPL-only symbols */ \ - __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \ - __start___ksymtab_gpl = .; \ -- KEEP(*(SORT(___ksymtab_gpl+*))) \ -+ SYMTAB_KEEP_GPL \ - __stop___ksymtab_gpl = .; \ - } \ - \ -@@ -543,7 +553,7 @@ - \ - /* Kernel symbol table: strings */ \ - __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) { \ -- *(__ksymtab_strings) \ -+ *(__ksymtab_strings+*) \ - } \ - \ - /* __*init sections */ \ -@@ -1024,6 +1034,8 @@ - - #define COMMON_DISCARDS \ - SANITIZER_DISCARDS \ -+ SYMTAB_DISCARD \ -+ SYMTAB_DISCARD_GPL \ - *(.discard) \ - *(.discard.*) \ - *(.modinfo) \ ---- a/include/linux/export.h -+++ b/include/linux/export.h -@@ -82,6 +82,12 @@ struct kernel_symbol { - - #else - -+#ifdef MODULE -+#define __EXPORT_SUFFIX(sym) -+#else -+#define __EXPORT_SUFFIX(sym) "+" #sym -+#endif -+ - /* - * For every exported symbol, do the following: - * -@@ -99,7 +105,7 @@ struct kernel_symbol { - extern const char __kstrtab_##sym[]; \ - extern const char __kstrtabns_##sym[]; \ - __CRC_SYMBOL(sym, sec); \ -- asm(" .section \"__ksymtab_strings\",\"aMS\",%progbits,1 \n" \ -+ asm(" .section \"__ksymtab_strings" __EXPORT_SUFFIX(sym) "\",\"aMS\",%progbits,1 \n" \ - "__kstrtab_" #sym ": \n" \ - " .asciz \"" #sym "\" \n" \ - "__kstrtabns_" #sym ": \n" \ ---- a/include/asm-generic/export.h -+++ b/include/asm-generic/export.h -@@ -26,6 +26,12 @@ - #endif - .endm - -+#ifdef MODULE -+#define __EXPORT_SUFFIX(name) -+#else -+#define __EXPORT_SUFFIX(name) + #name -+#endif -+ - /* - * note on .section use: we specify progbits since usage of the "M" (SHF_MERGE) - * section flag requires it. Use '%progbits' instead of '@progbits' since the -@@ -39,7 +45,7 @@ - __ksymtab_\name: - __put \val, __kstrtab_\name - .previous -- .section __ksymtab_strings,"aMS",%progbits,1 -+ .section __ksymtab_strings __EXPORT_SUFFIX(name),"aMS",%progbits,1 - __kstrtab_\name: - .asciz "\name" - .previous ---- a/scripts/Makefile.build -+++ b/scripts/Makefile.build -@@ -373,7 +373,7 @@ targets += $(lib-y) $(always-y) $(MAKECM - # Linker scripts preprocessor (.lds.S -> .lds) - # --------------------------------------------------------------------------- - quiet_cmd_cpp_lds_S = LDS $@ -- cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \ -+ cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -U$(ARCH) \ - -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $< - - $(obj)/%.lds: $(src)/%.lds.S FORCE diff --git a/target/linux/generic/hack-5.10/230-openwrt_lzma_options.patch b/target/linux/generic/hack-5.10/230-openwrt_lzma_options.patch deleted file mode 100644 index 906527faf9..0000000000 --- a/target/linux/generic/hack-5.10/230-openwrt_lzma_options.patch +++ /dev/null @@ -1,34 +0,0 @@ -From b3d00b452467f621317953d9e4c6f9ae8dcfd271 Mon Sep 17 00:00:00 2001 -From: Imre Kaloz -Date: Fri, 7 Jul 2017 17:06:55 +0200 -Subject: use the openwrt lzma options for now - -lede-commit: 548de949f392049420a6a1feeef118b30ab8ea8c -Signed-off-by: Imre Kaloz ---- - lib/decompress.c | 1 + - scripts/Makefile.lib | 2 +- - usr/gen_initramfs_list.sh | 10 +++++----- - 3 files changed, 7 insertions(+), 6 deletions(-) - ---- a/lib/decompress.c -+++ b/lib/decompress.c -@@ -53,6 +53,7 @@ static const struct compress_format comp - { {0x1f, 0x9e}, "gzip", gunzip }, - { {0x42, 0x5a}, "bzip2", bunzip2 }, - { {0x5d, 0x00}, "lzma", unlzma }, -+ { {0x6d, 0x00}, "lzma-openwrt", unlzma }, - { {0xfd, 0x37}, "xz", unxz }, - { {0x89, 0x4c}, "lzo", unlzo }, - { {0x02, 0x21}, "lz4", unlz4 }, ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -370,7 +370,7 @@ quiet_cmd_bzip2 = BZIP2 $@ - # --------------------------------------------------------------------------- - - quiet_cmd_lzma = LZMA $@ -- cmd_lzma = { cat $(real-prereqs) | $(LZMA) -9; $(size_append); } > $@ -+ cmd_lzma = { cat $(real-prereqs) | $(LZMA) e -d20 -lc1 -lp2 -pb2 -eos -si -so; $(size_append); } > $@ - - quiet_cmd_lzo = LZO $@ - cmd_lzo = { cat $(real-prereqs) | $(KLZOP) -9; $(size_append); } > $@ diff --git a/target/linux/generic/hack-5.10/250-netfilter_depends.patch b/target/linux/generic/hack-5.10/250-netfilter_depends.patch deleted file mode 100644 index ec01854958..0000000000 --- a/target/linux/generic/hack-5.10/250-netfilter_depends.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Felix Fietkau -Subject: hack: net: remove bogus netfilter dependencies - -lede-commit: 589d2a377dee27d206fc3725325309cf649e4df6 -Signed-off-by: Felix Fietkau ---- - net/netfilter/Kconfig | 2 -- - 1 file changed, 2 deletions(-) - ---- a/net/netfilter/Kconfig -+++ b/net/netfilter/Kconfig -@@ -227,7 +227,6 @@ config NF_CONNTRACK_FTP - - config NF_CONNTRACK_H323 - tristate "H.323 protocol support" -- depends on IPV6 || IPV6=n - depends on NETFILTER_ADVANCED - help - H.323 is a VoIP signalling protocol from ITU-T. As one of the most -@@ -1071,7 +1070,6 @@ config NETFILTER_XT_TARGET_SECMARK - - config NETFILTER_XT_TARGET_TCPMSS - tristate '"TCPMSS" target support' -- depends on IPV6 || IPV6=n - default m if NETFILTER_ADVANCED=n - help - This option adds a `TCPMSS' target, which allows you to alter the diff --git a/target/linux/generic/hack-5.10/251-kconfig.patch b/target/linux/generic/hack-5.10/251-kconfig.patch deleted file mode 100644 index d692d137f1..0000000000 --- a/target/linux/generic/hack-5.10/251-kconfig.patch +++ /dev/null @@ -1,210 +0,0 @@ -From da3c50704f14132f4adf80d48e9a4cd5d46e54c9 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 7 Jul 2017 17:09:21 +0200 -Subject: kconfig: owrt specifc dependencies - -Signed-off-by: John Crispin ---- - crypto/Kconfig | 10 +++++----- - drivers/bcma/Kconfig | 1 + - drivers/ssb/Kconfig | 3 ++- - lib/Kconfig | 8 ++++---- - net/netfilter/Kconfig | 2 +- - net/wireless/Kconfig | 17 ++++++++++------- - sound/core/Kconfig | 4 ++-- - 7 files changed, 25 insertions(+), 20 deletions(-) - ---- a/crypto/Kconfig -+++ b/crypto/Kconfig -@@ -34,7 +34,7 @@ config CRYPTO_FIPS - this is. - - config CRYPTO_ALGAPI -- tristate -+ tristate "ALGAPI" - select CRYPTO_ALGAPI2 - help - This option provides the API for cryptographic algorithms. -@@ -43,7 +43,7 @@ config CRYPTO_ALGAPI2 - tristate - - config CRYPTO_AEAD -- tristate -+ tristate "AEAD" - select CRYPTO_AEAD2 - select CRYPTO_ALGAPI - -@@ -54,7 +54,7 @@ config CRYPTO_AEAD2 - select CRYPTO_RNG2 - - config CRYPTO_SKCIPHER -- tristate -+ tristate "SKCIPHER" - select CRYPTO_SKCIPHER2 - select CRYPTO_ALGAPI - -@@ -64,7 +64,7 @@ config CRYPTO_SKCIPHER2 - select CRYPTO_RNG2 - - config CRYPTO_HASH -- tristate -+ tristate "HASH" - select CRYPTO_HASH2 - select CRYPTO_ALGAPI - -@@ -73,7 +73,7 @@ config CRYPTO_HASH2 - select CRYPTO_ALGAPI2 - - config CRYPTO_RNG -- tristate -+ tristate "RNG" - select CRYPTO_RNG2 - select CRYPTO_ALGAPI - ---- a/drivers/bcma/Kconfig -+++ b/drivers/bcma/Kconfig -@@ -16,6 +16,7 @@ if BCMA - # Support for Block-I/O. SELECT this from the driver that needs it. - config BCMA_BLOCKIO - bool -+ default y - - config BCMA_HOST_PCI_POSSIBLE - bool ---- a/drivers/ssb/Kconfig -+++ b/drivers/ssb/Kconfig -@@ -29,6 +29,7 @@ config SSB_SPROM - config SSB_BLOCKIO - bool - depends on SSB -+ default y - - config SSB_PCIHOST_POSSIBLE - bool -@@ -49,7 +50,7 @@ config SSB_PCIHOST - config SSB_B43_PCI_BRIDGE - bool - depends on SSB_PCIHOST -- default n -+ default y - - config SSB_PCMCIAHOST_POSSIBLE - bool ---- a/lib/Kconfig -+++ b/lib/Kconfig -@@ -423,16 +423,16 @@ config BCH_CONST_T - # Textsearch support is select'ed if needed - # - config TEXTSEARCH -- bool -+ bool "Textsearch support" - - config TEXTSEARCH_KMP -- tristate -+ tristate "Textsearch KMP" - - config TEXTSEARCH_BM -- tristate -+ tristate "Textsearch BM" - - config TEXTSEARCH_FSM -- tristate -+ tristate "Textsearch FSM" - - config BTREE - bool ---- a/net/netfilter/Kconfig -+++ b/net/netfilter/Kconfig -@@ -11,7 +11,7 @@ config NETFILTER_INGRESS - infrastructure. - - config NETFILTER_NETLINK -- tristate -+ tristate "Netfilter NFNETLINK interface" - - config NETFILTER_FAMILY_BRIDGE - bool ---- a/net/wireless/Kconfig -+++ b/net/wireless/Kconfig -@@ -1,6 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0-only - config WIRELESS_EXT -- bool -+ bool "Wireless extensions" - - config WEXT_CORE - def_bool y -@@ -12,10 +12,10 @@ config WEXT_PROC - depends on WEXT_CORE - - config WEXT_SPY -- bool -+ bool "WEXT_SPY" - - config WEXT_PRIV -- bool -+ bool "WEXT_PRIV" - - config CFG80211 - tristate "cfg80211 - wireless configuration API" -@@ -204,7 +204,7 @@ config CFG80211_WEXT_EXPORT - endif # CFG80211 - - config LIB80211 -- tristate -+ tristate "LIB80211" - default n - help - This options enables a library of common routines used -@@ -213,17 +213,17 @@ config LIB80211 - Drivers should select this themselves if needed. - - config LIB80211_CRYPT_WEP -- tristate -+ tristate "LIB80211_CRYPT_WEP" - select CRYPTO_LIB_ARC4 - - config LIB80211_CRYPT_CCMP -- tristate -+ tristate "LIB80211_CRYPT_CCMP" - select CRYPTO - select CRYPTO_AES - select CRYPTO_CCM - - config LIB80211_CRYPT_TKIP -- tristate -+ tristate "LIB80211_CRYPT_TKIP" - select CRYPTO_LIB_ARC4 - - config LIB80211_DEBUG ---- a/sound/core/Kconfig -+++ b/sound/core/Kconfig -@@ -17,7 +17,7 @@ config SND_DMAENGINE_PCM - tristate - - config SND_HWDEP -- tristate -+ tristate "Sound hardware support" - - config SND_SEQ_DEVICE - tristate -@@ -27,7 +27,7 @@ config SND_RAWMIDI - select SND_SEQ_DEVICE if SND_SEQUENCER != n - - config SND_COMPRESS_OFFLOAD -- tristate -+ tristate "Compression offloading support" - - config SND_JACK - bool ---- a/net/Kconfig -+++ b/net/Kconfig -@@ -436,7 +436,7 @@ config NET_DEVLINK - default n - - config PAGE_POOL -- bool -+ bool "Page pool support" - - config FAILOVER - tristate "Generic failover module" diff --git a/target/linux/generic/hack-5.10/253-ksmbd-config.patch b/target/linux/generic/hack-5.10/253-ksmbd-config.patch deleted file mode 100644 index 6fb9de3b05..0000000000 --- a/target/linux/generic/hack-5.10/253-ksmbd-config.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: Rosen Penev -Subject: Kconfig: add help text to kernel config - -These options will be used for ksmbd. Once kernel 5.15 -makes it in, this patch can go away. - -Submitted-by: Rosen Penev ---- - init/Kconfig | 2 +- - lib/Kconfig | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/init/Kconfig -+++ b/init/Kconfig -@@ -2396,7 +2396,7 @@ config PADATA - bool - - config ASN1 -- tristate -+ tristate "ASN1" - help - Build a simple ASN.1 grammar compiler that produces a bytecode output - that can be interpreted by the ASN.1 stream decoder and used to ---- a/lib/Kconfig -+++ b/lib/Kconfig -@@ -594,7 +594,7 @@ config LIBFDT - bool - - config OID_REGISTRY -- tristate -+ tristate "OID" - help - Enable fast lookup object identifier registry. - diff --git a/target/linux/generic/hack-5.10/259-regmap_dynamic.patch b/target/linux/generic/hack-5.10/259-regmap_dynamic.patch deleted file mode 100644 index bc81a7285c..0000000000 --- a/target/linux/generic/hack-5.10/259-regmap_dynamic.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 811d9e2268a62b830cfe93cd8bc929afcb8b198b Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 15 Jul 2017 21:12:38 +0200 -Subject: kernel: move regmap bloat out of the kernel image if it is only being used in modules - -lede-commit: 96f39119815028073583e4fca3a9c5fe9141e998 -Signed-off-by: Felix Fietkau ---- - drivers/base/regmap/Kconfig | 15 ++++++++++----- - drivers/base/regmap/Makefile | 12 ++++++++---- - drivers/base/regmap/regmap.c | 3 +++ - include/linux/regmap.h | 2 +- - 4 files changed, 22 insertions(+), 10 deletions(-) - ---- a/drivers/base/regmap/Kconfig -+++ b/drivers/base/regmap/Kconfig -@@ -4,9 +4,8 @@ - # subsystems should select the appropriate symbols. - - config REGMAP -- default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_W1 || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ || REGMAP_SOUNDWIRE || REGMAP_SCCB || REGMAP_I3C || REGMAP_SPI_AVMM) - select IRQ_DOMAIN if REGMAP_IRQ -- bool -+ tristate - - config REGCACHE_COMPRESSED - select LZO_COMPRESS -@@ -14,46 +13,59 @@ config REGCACHE_COMPRESSED - bool - - config REGMAP_AC97 -+ select REGMAP - tristate - - config REGMAP_I2C - tristate -+ select REGMAP - depends on I2C - - config REGMAP_SLIMBUS - tristate -+ select REGMAP - depends on SLIMBUS - - config REGMAP_SPI - tristate -+ select REGMAP -+ depends on SPI_MASTER - depends on SPI - - config REGMAP_SPMI - tristate -+ select REGMAP - depends on SPMI - - config REGMAP_W1 - tristate -+ select REGMAP - depends on W1 - - config REGMAP_MMIO - tristate -+ select REGMAP - - config REGMAP_IRQ - bool -+ select REGMAP - - config REGMAP_SOUNDWIRE - tristate -+ select REGMAP - depends on SOUNDWIRE - - config REGMAP_SCCB - tristate -+ select REGMAP - depends on I2C - - config REGMAP_I3C - tristate -+ select REGMAP - depends on I3C - - config REGMAP_SPI_AVMM - tristate -+ select REGMAP - depends on SPI ---- a/drivers/base/regmap/Makefile -+++ b/drivers/base/regmap/Makefile -@@ -2,10 +2,14 @@ - # For include/trace/define_trace.h to include trace.h - CFLAGS_regmap.o := -I$(src) - --obj-$(CONFIG_REGMAP) += regmap.o regcache.o --obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-flat.o --obj-$(CONFIG_REGCACHE_COMPRESSED) += regcache-lzo.o --obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o -+regmap-core-objs = regmap.o regcache.o regcache-rbtree.o regcache-flat.o -+ifdef CONFIG_DEBUG_FS -+regmap-core-objs += regmap-debugfs.o -+endif -+ifdef CONFIG_REGCACHE_COMPRESSED -+regmap-core-objs += regcache-lzo.o -+endif -+obj-$(CONFIG_REGMAP) += regmap-core.o - obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o - obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o - obj-$(CONFIG_REGMAP_SLIMBUS) += regmap-slimbus.o ---- a/drivers/base/regmap/regmap.c -+++ b/drivers/base/regmap/regmap.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -3298,3 +3299,5 @@ static int __init regmap_initcall(void) - return 0; - } - postcore_initcall(regmap_initcall); -+ -+MODULE_LICENSE("GPL"); ---- a/include/linux/regmap.h -+++ b/include/linux/regmap.h -@@ -179,7 +179,7 @@ struct reg_sequence { - __ret ?: __tmp; \ - }) - --#ifdef CONFIG_REGMAP -+#if IS_REACHABLE(CONFIG_REGMAP) - - enum regmap_endian { - /* Unspecified -> 0 -> Backwards compatible default */ diff --git a/target/linux/generic/hack-5.10/260-crypto_test_dependencies.patch b/target/linux/generic/hack-5.10/260-crypto_test_dependencies.patch deleted file mode 100644 index 3ccf67b23e..0000000000 --- a/target/linux/generic/hack-5.10/260-crypto_test_dependencies.patch +++ /dev/null @@ -1,52 +0,0 @@ -From fd1799b0bf5efa46dd3e6dfbbf3955564807e508 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Fri, 7 Jul 2017 17:12:51 +0200 -Subject: kernel: prevent cryptomgr from pulling in useless extra dependencies for tests that are not run - -Reduces kernel size after LZMA by about 5k on MIPS - -lede-commit: 044c316167e076479a344c59905e5b435b84a77f -Signed-off-by: Felix Fietkau ---- - crypto/Kconfig | 13 ++++++------- - crypto/algboss.c | 4 ++++ - 2 files changed, 10 insertions(+), 7 deletions(-) - ---- a/crypto/Kconfig -+++ b/crypto/Kconfig -@@ -121,13 +121,13 @@ config CRYPTO_MANAGER - cbc(aes). - - config CRYPTO_MANAGER2 -- def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) -- select CRYPTO_AEAD2 -- select CRYPTO_HASH2 -- select CRYPTO_SKCIPHER2 -- select CRYPTO_AKCIPHER2 -- select CRYPTO_KPP2 -- select CRYPTO_ACOMP2 -+ def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y && !CRYPTO_MANAGER_DISABLE_TESTS) -+ select CRYPTO_AEAD2 if !CRYPTO_MANAGER_DISABLE_TESTS -+ select CRYPTO_HASH2 if !CRYPTO_MANAGER_DISABLE_TESTS -+ select CRYPTO_SKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS -+ select CRYPTO_AKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS -+ select CRYPTO_KPP2 if !CRYPTO_MANAGER_DISABLE_TESTS -+ select CRYPTO_ACOMP2 if !CRYPTO_MANAGER_DISABLE_TESTS - - config CRYPTO_USER - tristate "Userspace cryptographic algorithm configuration" ---- a/crypto/algboss.c -+++ b/crypto/algboss.c -@@ -230,8 +230,12 @@ static int cryptomgr_schedule_test(struc - type = alg->cra_flags; - - /* Do not test internal algorithms. */ -+#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS -+ type |= CRYPTO_ALG_TESTED; -+#else - if (type & CRYPTO_ALG_INTERNAL) - type |= CRYPTO_ALG_TESTED; -+#endif - - param->type = type; - diff --git a/target/linux/generic/hack-5.10/261-lib-arc4-unhide.patch b/target/linux/generic/hack-5.10/261-lib-arc4-unhide.patch deleted file mode 100644 index b61dd269a4..0000000000 --- a/target/linux/generic/hack-5.10/261-lib-arc4-unhide.patch +++ /dev/null @@ -1,28 +0,0 @@ -From: Koen Vandeputte -Subject: crypto: arc4 unhide - -This makes it possible to select CONFIG_CRYPTO_LIB_ARC4 directly. We -need this to be able to compile this into the kernel and make use of it -from backports. - -Submitted-by: Koen Vandeputte -Submitted-by: David Bauer -Submitted-by: Christian Lamparter -Submitted-by: Ansuel Smith -Submitted-by: Robert Marko -Submitted-by: Hauke Mehrtens ---- - lib/crypto/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/lib/crypto/Kconfig -+++ b/lib/crypto/Kconfig -@@ -6,7 +6,7 @@ config CRYPTO_LIB_AES - tristate - - config CRYPTO_LIB_ARC4 -- tristate -+ tristate "ARC4 cipher library" - - config CRYPTO_ARCH_HAVE_LIB_BLAKE2S - bool diff --git a/target/linux/generic/hack-5.10/280-rfkill-stubs.patch b/target/linux/generic/hack-5.10/280-rfkill-stubs.patch deleted file mode 100644 index 2e48aea1cf..0000000000 --- a/target/linux/generic/hack-5.10/280-rfkill-stubs.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 236c1acdfef5958010ac9814a9872e0a46fd78ee Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 7 Jul 2017 17:13:44 +0200 -Subject: rfkill: add fake rfkill support - -allow building of modules depending on RFKILL even if RFKILL is not enabled. - -Signed-off-by: John Crispin ---- - include/linux/rfkill.h | 2 +- - net/Makefile | 2 +- - net/rfkill/Kconfig | 14 +++++++++----- - net/rfkill/Makefile | 2 +- - 4 files changed, 12 insertions(+), 8 deletions(-) - ---- a/include/linux/rfkill.h -+++ b/include/linux/rfkill.h -@@ -64,7 +64,7 @@ struct rfkill_ops { - int (*set_block)(void *data, bool blocked); - }; - --#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) -+#if defined(CONFIG_RFKILL_FULL) || defined(CONFIG_RFKILL_FULL_MODULE) - /** - * rfkill_alloc - Allocate rfkill structure - * @name: name of the struct -- the string is not copied internally ---- a/net/Makefile -+++ b/net/Makefile -@@ -53,7 +53,7 @@ obj-$(CONFIG_TIPC) += tipc/ - obj-$(CONFIG_NETLABEL) += netlabel/ - obj-$(CONFIG_IUCV) += iucv/ - obj-$(CONFIG_SMC) += smc/ --obj-$(CONFIG_RFKILL) += rfkill/ -+obj-$(CONFIG_RFKILL_FULL) += rfkill/ - obj-$(CONFIG_NET_9P) += 9p/ - obj-$(CONFIG_CAIF) += caif/ - ifneq ($(CONFIG_DCB),) ---- a/net/rfkill/Kconfig -+++ b/net/rfkill/Kconfig -@@ -2,7 +2,11 @@ - # - # RF switch subsystem configuration - # --menuconfig RFKILL -+config RFKILL -+ bool -+ default y -+ -+menuconfig RFKILL_FULL - tristate "RF switch subsystem support" - help - Say Y here if you want to have control over RF switches -@@ -14,19 +18,19 @@ menuconfig RFKILL - # LED trigger support - config RFKILL_LEDS - bool -- depends on RFKILL -+ depends on RFKILL_FULL - depends on LEDS_TRIGGERS = y || RFKILL = LEDS_TRIGGERS - default y - - config RFKILL_INPUT - bool "RF switch input support" if EXPERT -- depends on RFKILL -+ depends on RFKILL_FULL - depends on INPUT = y || RFKILL = INPUT - default y if !EXPERT - - config RFKILL_GPIO - tristate "GPIO RFKILL driver" -- depends on RFKILL -+ depends on RFKILL_FULL - depends on GPIOLIB || COMPILE_TEST - default n - help ---- a/net/rfkill/Makefile -+++ b/net/rfkill/Makefile -@@ -5,5 +5,5 @@ - - rfkill-y += core.o - rfkill-$(CONFIG_RFKILL_INPUT) += input.o --obj-$(CONFIG_RFKILL) += rfkill.o -+obj-$(CONFIG_RFKILL_FULL) += rfkill.o - obj-$(CONFIG_RFKILL_GPIO) += rfkill-gpio.o diff --git a/target/linux/generic/hack-5.10/300-MIPS-r4k_cache-use-more-efficient-cache-blast.patch b/target/linux/generic/hack-5.10/300-MIPS-r4k_cache-use-more-efficient-cache-blast.patch deleted file mode 100644 index fe89de7e08..0000000000 --- a/target/linux/generic/hack-5.10/300-MIPS-r4k_cache-use-more-efficient-cache-blast.patch +++ /dev/null @@ -1,64 +0,0 @@ -From: Ben Menchaca -Date: Fri, 7 Jun 2013 18:35:22 -0500 -Subject: MIPS: r4k_cache: use more efficient cache blast - -Optimize the compiler output for larger cache blast cases that are -common for DMA-based networking. - -Signed-off-by: Ben Menchaca -Signed-off-by: Felix Fietkau ---- ---- a/arch/mips/include/asm/r4kcache.h -+++ b/arch/mips/include/asm/r4kcache.h -@@ -296,14 +296,46 @@ static inline void prot##extra##blast_## - unsigned long end) \ - { \ - unsigned long lsize = cpu_##desc##_line_size(); \ -+ unsigned long lsize_2 = lsize * 2; \ -+ unsigned long lsize_3 = lsize * 3; \ -+ unsigned long lsize_4 = lsize * 4; \ -+ unsigned long lsize_5 = lsize * 5; \ -+ unsigned long lsize_6 = lsize * 6; \ -+ unsigned long lsize_7 = lsize * 7; \ -+ unsigned long lsize_8 = lsize * 8; \ - unsigned long addr = start & ~(lsize - 1); \ -- unsigned long aend = (end - 1) & ~(lsize - 1); \ -+ unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \ -+ int lines = (aend - addr) / lsize; \ - \ -- while (1) { \ -+ while (lines >= 8) { \ -+ prot##cache_op(hitop, addr); \ -+ prot##cache_op(hitop, addr + lsize); \ -+ prot##cache_op(hitop, addr + lsize_2); \ -+ prot##cache_op(hitop, addr + lsize_3); \ -+ prot##cache_op(hitop, addr + lsize_4); \ -+ prot##cache_op(hitop, addr + lsize_5); \ -+ prot##cache_op(hitop, addr + lsize_6); \ -+ prot##cache_op(hitop, addr + lsize_7); \ -+ addr += lsize_8; \ -+ lines -= 8; \ -+ } \ -+ \ -+ if (lines & 0x4) { \ -+ prot##cache_op(hitop, addr); \ -+ prot##cache_op(hitop, addr + lsize); \ -+ prot##cache_op(hitop, addr + lsize_2); \ -+ prot##cache_op(hitop, addr + lsize_3); \ -+ addr += lsize_4; \ -+ } \ -+ \ -+ if (lines & 0x2) { \ -+ prot##cache_op(hitop, addr); \ -+ prot##cache_op(hitop, addr + lsize); \ -+ addr += lsize_2; \ -+ } \ -+ \ -+ if (lines & 0x1) { \ - prot##cache_op(hitop, addr); \ -- if (addr == aend) \ -- break; \ -- addr += lsize; \ - } \ - } - diff --git a/target/linux/generic/hack-5.10/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/hack-5.10/321-powerpc_crtsavres_prereq.patch deleted file mode 100644 index c4fd475b1f..0000000000 --- a/target/linux/generic/hack-5.10/321-powerpc_crtsavres_prereq.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001 -From: "Alexandros C. Couloumbis" -Date: Fri, 7 Jul 2017 17:14:51 +0200 -Subject: hack: arch: powerpc: drop register save/restore library from modules - -Upstream GCC uses a libgcc function for saving/restoring registers. This -makes the code bigger, and upstream kernels need to carry that function -for every single kernel module. Our GCC is patched to avoid those -references, so we can drop the extra bloat for modules. - -lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec -Signed-off-by: Alexandros C. Couloumbis ---- - arch/powerpc/Makefile | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/powerpc/Makefile -+++ b/arch/powerpc/Makefile -@@ -44,19 +44,6 @@ machine-$(CONFIG_PPC64) += 64 - machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le - UTS_MACHINE := $(subst $(space),,$(machine-y)) - --# XXX This needs to be before we override LD below --ifdef CONFIG_PPC32 --KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o --else --ifeq ($(call ld-ifversion, -ge, 225000000, y),y) --# Have the linker provide sfpr if possible. --# There is a corresponding test in arch/powerpc/lib/Makefile --KBUILD_LDFLAGS_MODULE += --save-restore-funcs --else --KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o --endif --endif -- - ifdef CONFIG_CPU_LITTLE_ENDIAN - KBUILD_CFLAGS += -mlittle-endian - KBUILD_LDFLAGS += -EL diff --git a/target/linux/generic/hack-5.10/401-mtd-super-don-t-reply-on-mtdblock-device-minor.patch b/target/linux/generic/hack-5.10/401-mtd-super-don-t-reply-on-mtdblock-device-minor.patch deleted file mode 100644 index 04cf52b096..0000000000 --- a/target/linux/generic/hack-5.10/401-mtd-super-don-t-reply-on-mtdblock-device-minor.patch +++ /dev/null @@ -1,85 +0,0 @@ -From f9760b158f610b1792a222cc924073724c061bfb Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 7 Apr 2021 22:37:57 +0100 -Subject: [PATCH 1/2] mtd: super: don't reply on mtdblock device minor -To: linux-mtd@lists.infradead.org -Cc: Vignesh Raghavendra , - Richard Weinberger , - Miquel Raynal , - David Woodhouse - -For blktrans devices with partitions (ie. part_bits != 0) the -assumption that the minor number of the mtdblock device matches -the mtdnum doesn't hold true. -Properly resolve mtd device from blktrans layer instead. - -Signed-off-by: Daniel Golle ---- - drivers/mtd/mtdsuper.c | 33 ++++++++++++++++++++++++++------- - 1 file changed, 26 insertions(+), 7 deletions(-) - ---- a/drivers/mtd/mtdsuper.c -+++ b/drivers/mtd/mtdsuper.c -@@ -9,6 +9,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -121,7 +122,8 @@ int get_tree_mtd(struct fs_context *fc, - { - #ifdef CONFIG_BLOCK - struct block_device *bdev; -- int ret, major; -+ struct mtd_blktrans_dev *blktrans_dev; -+ int ret, major, part_bits; - #endif - int mtdnr; - -@@ -169,21 +171,38 @@ int get_tree_mtd(struct fs_context *fc, - /* try the old way - the hack where we allowed users to mount - * /dev/mtdblock$(n) but didn't actually _use_ the blockdev - */ -- bdev = lookup_bdev(fc->source); -+ bdev = blkdev_get_by_path(fc->source, FMODE_READ, NULL); - if (IS_ERR(bdev)) { - ret = PTR_ERR(bdev); - errorf(fc, "MTD: Couldn't look up '%s': %d", fc->source, ret); - return ret; - } -- pr_debug("MTDSB: lookup_bdev() returned 0\n"); -+ pr_debug("MTDSB: blkdev_get_by_path() returned 0\n"); - - major = MAJOR(bdev->bd_dev); -- mtdnr = MINOR(bdev->bd_dev); -- bdput(bdev); - -- if (major == MTD_BLOCK_MAJOR) -- return mtd_get_sb_by_nr(fc, mtdnr, fill_super); -+ if (major == MTD_BLOCK_MAJOR) { -+ if (!bdev->bd_disk) { -+ blkdev_put(bdev, FMODE_READ); -+ BUG(); -+ return -EINVAL; -+ } -+ -+ blktrans_dev = (struct mtd_blktrans_dev *)(bdev->bd_disk->private_data); -+ if (!blktrans_dev || !blktrans_dev->tr) { -+ blkdev_put(bdev, FMODE_READ); -+ BUG(); -+ return -EINVAL; -+ } -+ mtdnr = blktrans_dev->devnum; -+ part_bits = blktrans_dev->tr->part_bits; -+ blkdev_put(bdev, FMODE_READ); -+ if (MINOR(bdev->bd_dev) != (mtdnr << part_bits)) -+ return -EINVAL; - -+ return mtd_get_sb_by_nr(fc, mtdnr, fill_super); -+ } -+ blkdev_put(bdev, FMODE_READ); - #endif /* CONFIG_BLOCK */ - - if (!(fc->sb_flags & SB_SILENT)) diff --git a/target/linux/generic/hack-5.10/402-mtd-blktrans-call-add-disks-after-mtd-device.patch b/target/linux/generic/hack-5.10/402-mtd-blktrans-call-add-disks-after-mtd-device.patch deleted file mode 100644 index 957c6305d1..0000000000 --- a/target/linux/generic/hack-5.10/402-mtd-blktrans-call-add-disks-after-mtd-device.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 0bccc3722bdd88e8ae995e77ef9f7b77ee4cbdee Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 7 Apr 2021 22:45:54 +0100 -Subject: [PATCH 2/2] mtd: blktrans: call add disks after mtd device -To: linux-mtd@lists.infradead.org -Cc: Vignesh Raghavendra , - Richard Weinberger , - Miquel Raynal , - David Woodhouse - -Calling device_add_disk while holding mtd_table_mutex leads -to deadlock in case part_bits!=0 as block partition parsers -will try to open the newly created disks, trying to acquire -mutex once again. -Move device_add_disk to additional function called after -add partitions of an MTD device have been added and locks -have been released. - -Signed-off-by: Daniel Golle ---- - drivers/mtd/mtd_blkdevs.c | 33 ++++++++++++++++++++++++++------- - drivers/mtd/mtdcore.c | 3 +++ - include/linux/mtd/blktrans.h | 1 + - 3 files changed, 30 insertions(+), 7 deletions(-) - ---- a/drivers/mtd/mtd_blkdevs.c -+++ b/drivers/mtd/mtd_blkdevs.c -@@ -457,13 +457,6 @@ int add_mtd_blktrans_dev(struct mtd_blkt - if (new->readonly) - set_disk_ro(gd, 1); - -- device_add_disk(&new->mtd->dev, gd, NULL); -- -- if (new->disk_attributes) { -- ret = sysfs_create_group(&disk_to_dev(gd)->kobj, -- new->disk_attributes); -- WARN_ON(ret); -- } - return 0; - error4: - kfree(new->tag_set); -@@ -475,6 +468,27 @@ error1: - return ret; - } - -+void register_mtd_blktrans_devs(void) -+{ -+ struct mtd_blktrans_ops *tr; -+ struct mtd_blktrans_dev *dev, *next; -+ int ret; -+ -+ list_for_each_entry(tr, &blktrans_majors, list) { -+ list_for_each_entry_safe(dev, next, &tr->devs, list) { -+ if (dev->disk->flags & GENHD_FL_UP) -+ continue; -+ -+ device_add_disk(&dev->mtd->dev, dev->disk, NULL); -+ if (dev->disk_attributes) { -+ ret = sysfs_create_group(&disk_to_dev(dev->disk)->kobj, -+ dev->disk_attributes); -+ WARN_ON(ret); -+ } -+ } -+ } -+} -+ - int del_mtd_blktrans_dev(struct mtd_blktrans_dev *old) - { - unsigned long flags; ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -32,6 +32,7 @@ - - #include - #include -+#include - - #include "mtdcore.h" - -@@ -930,6 +931,8 @@ int mtd_device_parse_register(struct mtd - register_reboot_notifier(&mtd->reboot_notifier); - } - -+ register_mtd_blktrans_devs(); -+ - out: - if (ret && device_is_registered(&mtd->dev)) - del_mtd_device(mtd); ---- a/include/linux/mtd/blktrans.h -+++ b/include/linux/mtd/blktrans.h -@@ -76,6 +76,6 @@ extern int deregister_mtd_blktrans(struc - extern int add_mtd_blktrans_dev(struct mtd_blktrans_dev *dev); - extern int del_mtd_blktrans_dev(struct mtd_blktrans_dev *dev); - extern int mtd_blktrans_cease_background(struct mtd_blktrans_dev *dev); -- -+extern void register_mtd_blktrans_devs(void); - - #endif /* __MTD_TRANS_H__ */ diff --git a/target/linux/generic/hack-5.10/410-block-fit-partition-parser.patch b/target/linux/generic/hack-5.10/410-block-fit-partition-parser.patch deleted file mode 100644 index 52d8e24d0f..0000000000 --- a/target/linux/generic/hack-5.10/410-block-fit-partition-parser.patch +++ /dev/null @@ -1,251 +0,0 @@ -From: Daniel Golle -Subject: [PATCH] kernel: fix FIT partition parser compatibility issues - -The uImage.FIT partition parser used to squeeze in FIT partitions in -the range where partition editor tools (fdisk and such) expect the -regular partition. This is confusing people and tools when adding -additional partitions on top of the partition used for OpenWrt's -uImage.FIT. -Instead of squeezing in the additional partitions, rather start with -all uImage.FIT partitions at offset 64. - -Submitted-by: Daniel Golle ---- - block/blk.h | 2 ++ - block/partitions/Kconfig | 7 +++ - block/partitions/Makefile | 1 + - block/partitions/check.h | 3 ++ - block/partitions/core.c | 15 +++++++ - drivers/mtd/ubi/block.c | 7 +++ - block/partitions/efi.c | 8 +++++++ - block/partitions/efi.h | 3 ++ - drivers/mtd/mtdblock.c | 4 +++ - drivers/mtd/mtd_blkdevs.c | 14 +------ - block/partitions/msdos.c | 10 ++++++ - include/linux/msdos_partition.h | 1 + - 12 files changed, 52 insertions(+), 13 deletions(-) - ---- a/block/blk.h -+++ b/block/blk.h -@@ -361,6 +361,8 @@ char *disk_name(struct gendisk *hd, int - #define ADDPART_FLAG_NONE 0 - #define ADDPART_FLAG_RAID 1 - #define ADDPART_FLAG_WHOLEDISK 2 -+#define ADDPART_FLAG_READONLY 4 -+#define ADDPART_FLAG_ROOTDEV 8 - void delete_partition(struct hd_struct *part); - int bdev_add_partition(struct block_device *bdev, int partno, - sector_t start, sector_t length); ---- a/block/partitions/Kconfig -+++ b/block/partitions/Kconfig -@@ -101,6 +101,13 @@ config ATARI_PARTITION - Say Y here if you would like to use hard disks under Linux which - were partitioned under the Atari OS. - -+config FIT_PARTITION -+ bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED -+ default n -+ help -+ Say Y here if your system needs to mount the filesystem part of -+ a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot. -+ - config IBM_PARTITION - bool "IBM disk label and partition support" - depends on PARTITION_ADVANCED && S390 ---- a/block/partitions/Makefile -+++ b/block/partitions/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o - obj-$(CONFIG_AMIGA_PARTITION) += amiga.o - obj-$(CONFIG_ATARI_PARTITION) += atari.o - obj-$(CONFIG_AIX_PARTITION) += aix.o -+obj-$(CONFIG_FIT_PARTITION) += fit.o - obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o - obj-$(CONFIG_MAC_PARTITION) += mac.o - obj-$(CONFIG_LDM_PARTITION) += ldm.o ---- a/block/partitions/check.h -+++ b/block/partitions/check.h -@@ -58,6 +58,7 @@ int amiga_partition(struct parsed_partit - int atari_partition(struct parsed_partitions *state); - int cmdline_partition(struct parsed_partitions *state); - int efi_partition(struct parsed_partitions *state); -+int fit_partition(struct parsed_partitions *state); - int ibm_partition(struct parsed_partitions *); - int karma_partition(struct parsed_partitions *state); - int ldm_partition(struct parsed_partitions *state); -@@ -68,3 +69,5 @@ int sgi_partition(struct parsed_partitio - int sun_partition(struct parsed_partitions *state); - int sysv68_partition(struct parsed_partitions *state); - int ultrix_partition(struct parsed_partitions *state); -+ -+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain); ---- a/block/partitions/core.c -+++ b/block/partitions/core.c -@@ -10,6 +10,10 @@ - #include - #include - #include -+#ifdef CONFIG_FIT_PARTITION -+#include -+#endif -+ - #include "check.h" - - static int (*check_part[])(struct parsed_partitions *) = { -@@ -46,6 +50,9 @@ static int (*check_part[])(struct parsed - #ifdef CONFIG_EFI_PARTITION - efi_partition, /* this must come before msdos */ - #endif -+#ifdef CONFIG_FIT_PARTITION -+ fit_partition, -+#endif - #ifdef CONFIG_SGI_PARTITION - sgi_partition, - #endif -@@ -701,6 +708,14 @@ static bool blk_add_partition(struct gen - (state->parts[p].flags & ADDPART_FLAG_RAID)) - md_autodetect_dev(part_to_dev(part)->devt); - -+#ifdef CONFIG_FIT_PARTITION -+ if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0) -+ ROOT_DEV = part_to_dev(part)->devt; -+ -+ if (state->parts[p].flags & ADDPART_FLAG_READONLY) -+ part->policy = true; -+#endif -+ - return true; - } - ---- a/drivers/mtd/ubi/block.c -+++ b/drivers/mtd/ubi/block.c -@@ -396,7 +396,11 @@ int ubiblock_create(struct ubi_volume_in - dev->leb_size = vi->usable_leb_size; - - /* Initialize the gendisk of this ubiblock device */ -+#ifdef CONFIG_FIT_PARTITION -+ gd = alloc_disk(0); -+#else - gd = alloc_disk(1); -+#endif - if (!gd) { - pr_err("UBI: block: alloc_disk failed\n"); - ret = -ENODEV; -@@ -413,6 +417,9 @@ int ubiblock_create(struct ubi_volume_in - goto out_put_disk; - } - gd->private_data = dev; -+#ifdef CONFIG_FIT_PARTITION -+ gd->flags |= GENHD_FL_EXT_DEVT; -+#endif - sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id); - set_capacity(gd, disk_capacity); - dev->gd = gd; ---- a/block/partitions/efi.c -+++ b/block/partitions/efi.c -@@ -706,6 +706,9 @@ int efi_partition(struct parsed_partitio - gpt_entry *ptes = NULL; - u32 i; - unsigned ssz = bdev_logical_block_size(state->bdev) / 512; -+#ifdef CONFIG_FIT_PARTITION -+ u32 extra_slot = 64; -+#endif - - if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) { - kfree(gpt); -@@ -739,6 +742,11 @@ int efi_partition(struct parsed_partitio - ARRAY_SIZE(ptes[i].partition_name)); - utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname); - state->parts[i + 1].has_info = true; -+#ifdef CONFIG_FIT_PARTITION -+ /* If this is a U-Boot FIT volume it may have subpartitions */ -+ if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID)) -+ (void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1); -+#endif - } - kfree(ptes); - kfree(gpt); ---- a/block/partitions/efi.h -+++ b/block/partitions/efi.h -@@ -52,6 +52,9 @@ - #define PARTITION_LINUX_LVM_GUID \ - EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \ - 0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28) -+#define PARTITION_LINUX_FIT_GUID \ -+ EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \ -+ 0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93) - - typedef struct _gpt_header { - __le64 signature; ---- a/drivers/mtd/mtdblock.c -+++ b/drivers/mtd/mtdblock.c -@@ -338,7 +338,11 @@ static void mtdblock_remove_dev(struct m - static struct mtd_blktrans_ops mtdblock_tr = { - .name = "mtdblock", - .major = MTD_BLOCK_MAJOR, -+#ifdef CONFIG_FIT_PARTITION -+ .part_bits = 2, -+#else - .part_bits = 0, -+#endif - .blksize = 512, - .open = mtdblock_open, - .flush = mtdblock_flush, ---- a/drivers/mtd/mtd_blkdevs.c -+++ b/drivers/mtd/mtd_blkdevs.c -@@ -407,18 +407,8 @@ int add_mtd_blktrans_dev(struct mtd_blkt - gd->first_minor = (new->devnum) << tr->part_bits; - gd->fops = &mtd_block_ops; - -- if (tr->part_bits) -- if (new->devnum < 26) -- snprintf(gd->disk_name, sizeof(gd->disk_name), -- "%s%c", tr->name, 'a' + new->devnum); -- else -- snprintf(gd->disk_name, sizeof(gd->disk_name), -- "%s%c%c", tr->name, -- 'a' - 1 + new->devnum / 26, -- 'a' + new->devnum % 26); -- else -- snprintf(gd->disk_name, sizeof(gd->disk_name), -- "%s%d", tr->name, new->devnum); -+ snprintf(gd->disk_name, sizeof(gd->disk_name), -+ "%s%d", tr->name, new->devnum); - - set_capacity(gd, ((u64)new->size * tr->blksize) >> 9); - ---- a/block/partitions/msdos.c -+++ b/block/partitions/msdos.c -@@ -563,6 +563,15 @@ static void parse_minix(struct parsed_pa - #endif /* CONFIG_MINIX_SUBPARTITION */ - } - -+static void parse_fit_mbr(struct parsed_partitions *state, -+ sector_t offset, sector_t size, int origin) -+{ -+#ifdef CONFIG_FIT_PARTITION -+ u32 extra_slot = 64; -+ (void) parse_fit_partitions(state, offset, size, &extra_slot, 1); -+#endif /* CONFIG_FIT_PARTITION */ -+} -+ - static struct { - unsigned char id; - void (*parse)(struct parsed_partitions *, sector_t, sector_t, int); -@@ -574,6 +583,7 @@ static struct { - {UNIXWARE_PARTITION, parse_unixware}, - {SOLARIS_X86_PARTITION, parse_solaris_x86}, - {NEW_SOLARIS_X86_PARTITION, parse_solaris_x86}, -+ {FIT_PARTITION, parse_fit_mbr}, - {0, NULL}, - }; - ---- a/include/linux/msdos_partition.h -+++ b/include/linux/msdos_partition.h -@@ -31,6 +31,7 @@ enum msdos_sys_ind { - LINUX_LVM_PARTITION = 0x8e, - LINUX_RAID_PARTITION = 0xfd, /* autodetect RAID partition */ - -+ FIT_PARTITION = 0x2e, /* U-Boot uImage.FIT */ - SOLARIS_X86_PARTITION = 0x82, /* also Linux swap partitions */ - NEW_SOLARIS_X86_PARTITION = 0xbf, - diff --git a/target/linux/generic/hack-5.10/420-mtd-support-OpenWrt-s-MTD_ROOTFS_ROOT_DEV.patch b/target/linux/generic/hack-5.10/420-mtd-support-OpenWrt-s-MTD_ROOTFS_ROOT_DEV.patch deleted file mode 100644 index 08e4193c60..0000000000 --- a/target/linux/generic/hack-5.10/420-mtd-support-OpenWrt-s-MTD_ROOTFS_ROOT_DEV.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 7 Nov 2022 23:48:24 +0100 -Subject: [PATCH] mtd: support OpenWrt's MTD_ROOTFS_ROOT_DEV -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This allows setting ROOT_DEV to MTD partition named "rootfs". - -Signed-off-by: Rafał Miłecki ---- - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -758,7 +758,8 @@ int add_mtd_device(struct mtd_info *mtd) - - mutex_unlock(&mtd_table_mutex); - -- if (of_find_property(mtd_get_of_node(mtd), "linux,rootfs", NULL)) { -+ if (of_find_property(mtd_get_of_node(mtd), "linux,rootfs", NULL) || -+ (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) && !strcmp(mtd->name, "rootfs") && ROOT_DEV == 0)) { - if (IS_BUILTIN(CONFIG_MTD)) { - pr_info("mtd: setting mtd%d (%s) as root device\n", mtd->index, mtd->name); - ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, mtd->index); diff --git a/target/linux/generic/hack-5.10/421-mtd-fix-squashfs-root-on-targets-with-CONFIG_FIT_PAR.patch b/target/linux/generic/hack-5.10/421-mtd-fix-squashfs-root-on-targets-with-CONFIG_FIT_PAR.patch deleted file mode 100644 index df93c6be62..0000000000 --- a/target/linux/generic/hack-5.10/421-mtd-fix-squashfs-root-on-targets-with-CONFIG_FIT_PAR.patch +++ /dev/null @@ -1,31 +0,0 @@ -From: Felix Fietkau -Date: Sat Apr 10 17:00:57 2021 +0200 -Subject: [PATCH] mtd: fix squashfs root on targets with CONFIG_FIT_PARTITION - -Fix assumption about the block device index ---- - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -760,12 +760,18 @@ int add_mtd_device(struct mtd_info *mtd) - - if (of_find_property(mtd_get_of_node(mtd), "linux,rootfs", NULL) || - (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) && !strcmp(mtd->name, "rootfs") && ROOT_DEV == 0)) { -+ unsigned int index = mtd->index; -+ -+#ifdef CONFIG_FIT_PARTITION -+ index <<= 2; -+#endif -+ - if (IS_BUILTIN(CONFIG_MTD)) { -- pr_info("mtd: setting mtd%d (%s) as root device\n", mtd->index, mtd->name); -- ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, mtd->index); -+ pr_info("mtd: setting mtd%d (%s) as root device\n", index, mtd->name); -+ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, index); - } else { - pr_warn("mtd: can't set mtd%d (%s) as root device - mtd must be builtin\n", -- mtd->index, mtd->name); -+ index, mtd->name); - } - } - diff --git a/target/linux/generic/hack-5.10/422-drivers-mtd-parsers-add-nvmem-support-to-cmdlinepart.patch b/target/linux/generic/hack-5.10/422-drivers-mtd-parsers-add-nvmem-support-to-cmdlinepart.patch deleted file mode 100644 index 965a331a19..0000000000 --- a/target/linux/generic/hack-5.10/422-drivers-mtd-parsers-add-nvmem-support-to-cmdlinepart.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 6fa9e3678eb002246df1280322b6a024853950a5 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 11 Oct 2021 00:53:14 +0200 -Subject: [PATCH] drivers: mtd: parsers: add nvmem support to cmdlinepart - -Assuming cmdlinepart is only one level deep partition scheme and that -static partition are also defined in DTS, we can assign an of_node for -partition declared from bootargs. cmdlinepart have priority than -fiexed-partition parser so in this specific case the parser doesn't -assign an of_node. Fix this by searching a defined of_node using a -similar fixed_partition parser and if a partition is found with the same -label, check that it has the same offset and size and return the DT -of_node to correctly use NVMEM cells. - -Signed-off-by: Ansuel Smith ---- - drivers/mtd/parsers/cmdlinepart.c | 71 +++++++++++++++++++++++++++++++ - 1 file changed, 71 insertions(+) - ---- a/drivers/mtd/parsers/cmdlinepart.c -+++ b/drivers/mtd/parsers/cmdlinepart.c -@@ -43,6 +43,7 @@ - #include - #include - #include -+#include - - /* debug macro */ - #if 0 -@@ -323,6 +324,68 @@ static int mtdpart_setup_real(char *s) - return 0; - } - -+static int search_fixed_partition(struct mtd_info *master, -+ struct mtd_partition *target_part, -+ struct mtd_partition *fixed_part) -+{ -+ struct device_node *mtd_node; -+ struct device_node *ofpart_node; -+ struct device_node *pp; -+ struct mtd_partition part; -+ const char *partname; -+ -+ mtd_node = mtd_get_of_node(master); -+ if (!mtd_node) -+ return -EINVAL; -+ -+ ofpart_node = of_get_child_by_name(mtd_node, "partitions"); -+ -+ for_each_child_of_node(ofpart_node, pp) { -+ const __be32 *reg; -+ int len; -+ int a_cells, s_cells; -+ -+ reg = of_get_property(pp, "reg", &len); -+ if (!reg) { -+ pr_debug("%s: ofpart partition %pOF (%pOF) missing reg property.\n", -+ master->name, pp, -+ mtd_node); -+ continue; -+ } -+ -+ a_cells = of_n_addr_cells(pp); -+ s_cells = of_n_size_cells(pp); -+ if (len / 4 != a_cells + s_cells) { -+ pr_debug("%s: ofpart partition %pOF (%pOF) error parsing reg property.\n", -+ master->name, pp, -+ mtd_node); -+ continue; -+ } -+ -+ part.offset = of_read_number(reg, a_cells); -+ part.size = of_read_number(reg + a_cells, s_cells); -+ part.of_node = pp; -+ -+ partname = of_get_property(pp, "label", &len); -+ if (!partname) -+ partname = of_get_property(pp, "name", &len); -+ part.name = partname; -+ -+ if (!strncmp(target_part->name, part.name, len)) { -+ if (part.offset != target_part->offset) -+ return -EINVAL; -+ -+ if (part.size != target_part->size) -+ return -EINVAL; -+ -+ memcpy(fixed_part, &part, sizeof(struct mtd_partition)); -+ return 0; -+ } -+ } -+ -+ return -EINVAL; -+} -+ - /* - * Main function to be called from the MTD mapping driver/device to - * obtain the partitioning information. At this point the command line -@@ -338,6 +401,7 @@ static int parse_cmdline_partitions(stru - int i, err; - struct cmdline_mtd_partition *part; - const char *mtd_id = master->name; -+ struct mtd_partition fixed_part; - - /* parse command line */ - if (!cmdline_parsed) { -@@ -382,6 +446,13 @@ static int parse_cmdline_partitions(stru - sizeof(*part->parts) * (part->num_parts - i)); - i--; - } -+ -+ err = search_fixed_partition(master, &part->parts[i], &fixed_part); -+ if (!err) { -+ part->parts[i].of_node = fixed_part.of_node; -+ pr_info("Found partition defined in DT for %s. Assigning OF node to support nvmem.", -+ part->parts[i].name); -+ } - } - - *pparts = kmemdup(part->parts, sizeof(*part->parts) * part->num_parts, diff --git a/target/linux/generic/hack-5.10/430-mtk-bmt-support.patch b/target/linux/generic/hack-5.10/430-mtk-bmt-support.patch deleted file mode 100644 index b18df7584d..0000000000 --- a/target/linux/generic/hack-5.10/430-mtk-bmt-support.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 11425c9de29c8b9c5e4d7eec163a6afbb7fbdce2 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Thu, 9 Apr 2020 09:53:24 +0200 -Subject: mediatek: Implement bad-block management table support - -Submitted-by: Felix Fietkau ---- - drivers/mtd/nand/Kconfig | 4 ++++ - drivers/mtd/nand/Makefile | 1 + - 2 files changed, 5 insertions(+) - ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -15,6 +15,10 @@ config MTD_NAND_ECC - bool - depends on MTD_NAND_CORE - -+config MTD_NAND_MTK_BMT -+ bool "Support MediaTek NAND Bad-block Management Table" -+ default n -+ - endmenu - - endmenu ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -2,6 +2,7 @@ - - nandcore-objs := core.o bbt.o - obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o -+obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o - - obj-y += onenand/ - obj-y += raw/ diff --git a/target/linux/generic/hack-5.10/600-bridge_offload.patch b/target/linux/generic/hack-5.10/600-bridge_offload.patch deleted file mode 100644 index 82282627ea..0000000000 --- a/target/linux/generic/hack-5.10/600-bridge_offload.patch +++ /dev/null @@ -1,845 +0,0 @@ -From: Felix Fietkau -Subject: bridge: Add a fast path for the bridge code - -This caches flows between MAC addresses on separate ports, including their VLAN -in order to bypass the normal bridge forwarding code. -In my test on MT7622, this reduces LAN->WLAN bridging CPU usage by 6-10%, -potentially even more on weaker platforms - -Submitted-by: Felix Fietkau ---- - include/linux/if_bridge.h | 1 + - net/bridge/Makefile | 2 +- - net/bridge/br.c | 8 +++ - net/bridge/br_device.c | 7 +++ - net/bridge/br_forward.c | 3 ++ - net/bridge/br_if.c | 7 ++- - net/bridge/br_input.c | 5 ++ - net/bridge/br_offload.c | 436 +++++++++++++++ - net/bridge/br_private.h | 22 ++++- - net/bridge/br_private_offload.h | 21 +++++ - net/bridge/br_stp.c | 3 + - net/bridge/br_sysfs_br.c | 35 ++++++ - net/bridge/br_sysfs_if.c | 2 + - net/bridge/br_vlan_tunnel.c | 3 ++ - 14 files changed, 552 insertions(+), 3 deletions(-) - create mode 100644 net/bridge/br_offload.c - create mode 100644 net/bridge/br_private_offload.h - ---- a/include/linux/if_bridge.h -+++ b/include/linux/if_bridge.h -@@ -57,6 +57,7 @@ struct br_ip_list { - #define BR_MRP_LOST_CONT BIT(18) - #define BR_MRP_LOST_IN_CONT BIT(19) - #define BR_BPDU_FILTER BIT(20) -+#define BR_OFFLOAD BIT(21) - - #define BR_DEFAULT_AGEING_TIME (300 * HZ) - ---- a/net/bridge/Makefile -+++ b/net/bridge/Makefile -@@ -5,7 +5,7 @@ - - obj-$(CONFIG_BRIDGE) += bridge.o - --bridge-y := br.o br_device.o br_fdb.o br_forward.o br_if.o br_input.o \ -+bridge-y := br.o br_device.o br_fdb.o br_forward.o br_if.o br_input.o br_offload.o \ - br_ioctl.o br_stp.o br_stp_bpdu.o \ - br_stp_if.o br_stp_timer.o br_netlink.o \ - br_netlink_tunnel.o br_arp_nd_proxy.o ---- a/net/bridge/br.c -+++ b/net/bridge/br.c -@@ -18,6 +18,7 @@ - #include - - #include "br_private.h" -+#include "br_private_offload.h" - - /* - * Handle changes in state of network devices enslaved to a bridge. -@@ -332,6 +333,10 @@ static int __init br_init(void) - if (err) - goto err_out; - -+ err = br_offload_init(); -+ if (err) -+ goto err_out0; -+ - err = register_pernet_subsys(&br_net_ops); - if (err) - goto err_out1; -@@ -375,6 +380,8 @@ err_out3: - err_out2: - unregister_pernet_subsys(&br_net_ops); - err_out1: -+ br_offload_fini(); -+err_out0: - br_fdb_fini(); - err_out: - stp_proto_unregister(&br_stp_proto); -@@ -396,6 +403,7 @@ static void __exit br_deinit(void) - #if IS_ENABLED(CONFIG_ATM_LANE) - br_fdb_test_addr_hook = NULL; - #endif -+ br_offload_fini(); - br_fdb_fini(); - } - ---- a/net/bridge/br_device.c -+++ b/net/bridge/br_device.c -@@ -529,6 +529,8 @@ void br_dev_setup(struct net_device *dev - br->bridge_hello_time = br->hello_time = 2 * HZ; - br->bridge_forward_delay = br->forward_delay = 15 * HZ; - br->bridge_ageing_time = br->ageing_time = BR_DEFAULT_AGEING_TIME; -+ br->offload_cache_size = 128; -+ br->offload_cache_reserved = 8; - dev->max_mtu = ETH_MAX_MTU; - - br_netfilter_rtable_init(br); ---- a/net/bridge/br_fdb.c -+++ b/net/bridge/br_fdb.c -@@ -23,6 +23,7 @@ - #include - #include - #include "br_private.h" -+#include "br_private_offload.h" - - static const struct rhashtable_params br_fdb_rht_params = { - .head_offset = offsetof(struct net_bridge_fdb_entry, rhnode), -@@ -513,6 +514,8 @@ static struct net_bridge_fdb_entry *fdb_ - fdb->key.vlan_id = vid; - fdb->flags = flags; - fdb->updated = fdb->used = jiffies; -+ INIT_HLIST_HEAD(&fdb->offload_in); -+ INIT_HLIST_HEAD(&fdb->offload_out); - if (rhashtable_lookup_insert_fast(&br->fdb_hash_tbl, - &fdb->rhnode, - br_fdb_rht_params)) { -@@ -734,6 +737,8 @@ static void fdb_notify(struct net_bridge - struct sk_buff *skb; - int err = -ENOBUFS; - -+ br_offload_fdb_update(fdb); -+ - if (swdev_notify) - br_switchdev_fdb_notify(br, fdb, type); - ---- a/net/bridge/br_forward.c -+++ b/net/bridge/br_forward.c -@@ -16,6 +16,7 @@ - #include - #include - #include "br_private.h" -+#include "br_private_offload.h" - - /* Don't forward packets to originating port or forwarding disabled */ - static inline int should_deliver(const struct net_bridge_port *p, -@@ -32,6 +33,8 @@ static inline int should_deliver(const s - - int br_dev_queue_push_xmit(struct net *net, struct sock *sk, struct sk_buff *skb) - { -+ br_offload_output(skb); -+ - skb_push(skb, ETH_HLEN); - if (!is_skb_forwardable(skb->dev, skb)) - goto drop; ---- a/net/bridge/br_if.c -+++ b/net/bridge/br_if.c -@@ -25,6 +25,7 @@ - #include - - #include "br_private.h" -+#include "br_private_offload.h" - - /* - * Determine initial path cost based on speed. -@@ -427,7 +428,7 @@ static struct net_bridge_port *new_nbp(s - p->path_cost = port_cost(dev); - p->priority = 0x8000 >> BR_PORT_BITS; - p->port_no = index; -- p->flags = BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD; -+ p->flags = BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD | BR_OFFLOAD; - br_init_port(p); - br_set_state(p, BR_STATE_DISABLED); - br_stp_port_timer_init(p); -@@ -777,6 +778,9 @@ void br_port_flags_change(struct net_bri - - if (mask & BR_NEIGH_SUPPRESS) - br_recalculate_neigh_suppress_enabled(br); -+ -+ if (mask & BR_OFFLOAD) -+ br_offload_port_state(p); - } - - bool br_port_flag_is_set(const struct net_device *dev, unsigned long flag) ---- a/net/bridge/br_input.c -+++ b/net/bridge/br_input.c -@@ -22,6 +22,7 @@ - #include - #include "br_private.h" - #include "br_private_tunnel.h" -+#include "br_private_offload.h" - - static int - br_netif_receive_skb(struct net *net, struct sock *sk, struct sk_buff *skb) -@@ -169,6 +170,7 @@ int br_handle_frame_finish(struct net *n - dst->used = now; - br_forward(dst->dst, skb, local_rcv, false); - } else { -+ br_offload_skb_disable(skb); - if (!mcast_hit) - br_flood(br, skb, pkt_type, local_rcv, false); - else -@@ -287,6 +289,9 @@ static rx_handler_result_t br_handle_fra - memset(skb->cb, 0, sizeof(struct br_input_skb_cb)); - - p = br_port_get_rcu(skb->dev); -+ if (br_offload_input(p, skb)) -+ return RX_HANDLER_CONSUMED; -+ - if (p->flags & BR_VLAN_TUNNEL) { - if (br_handle_ingress_vlan_tunnel(skb, p, - nbp_vlan_group_rcu(p))) ---- /dev/null -+++ b/net/bridge/br_offload.c -@@ -0,0 +1,436 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+#include -+#include -+#include "br_private.h" -+#include "br_private_offload.h" -+ -+static DEFINE_SPINLOCK(offload_lock); -+ -+struct bridge_flow_key { -+ u8 dest[ETH_ALEN]; -+ u8 src[ETH_ALEN]; -+#ifdef CONFIG_BRIDGE_VLAN_FILTERING -+ u16 vlan_tag; -+ bool vlan_present; -+#endif -+}; -+ -+struct bridge_flow { -+ struct net_bridge_port *port; -+ struct rhash_head node; -+ struct bridge_flow_key key; -+#ifdef CONFIG_BRIDGE_VLAN_FILTERING -+ bool vlan_out_present; -+ u16 vlan_out; -+#endif -+ -+ unsigned long used; -+ struct net_bridge_fdb_entry *fdb_in, *fdb_out; -+ struct hlist_node fdb_list_in, fdb_list_out; -+ -+ struct rcu_head rcu; -+}; -+ -+static const struct rhashtable_params flow_params = { -+ .automatic_shrinking = true, -+ .head_offset = offsetof(struct bridge_flow, node), -+ .key_len = sizeof(struct bridge_flow_key), -+ .key_offset = offsetof(struct bridge_flow, key), -+}; -+ -+static struct kmem_cache *offload_cache __read_mostly; -+ -+static void -+flow_rcu_free(struct rcu_head *head) -+{ -+ struct bridge_flow *flow; -+ -+ flow = container_of(head, struct bridge_flow, rcu); -+ kmem_cache_free(offload_cache, flow); -+} -+ -+static void -+__br_offload_flow_free(struct bridge_flow *flow) -+{ -+ flow->used = 0; -+ hlist_del(&flow->fdb_list_in); -+ hlist_del(&flow->fdb_list_out); -+ -+ call_rcu(&flow->rcu, flow_rcu_free); -+} -+ -+static void -+br_offload_flow_free(struct bridge_flow *flow) -+{ -+ if (rhashtable_remove_fast(&flow->port->offload.rht, &flow->node, -+ flow_params) != 0) -+ return; -+ -+ __br_offload_flow_free(flow); -+} -+ -+static bool -+br_offload_flow_fdb_refresh_time(struct bridge_flow *flow, -+ struct net_bridge_fdb_entry *fdb) -+{ -+ if (!time_after(flow->used, fdb->updated)) -+ return false; -+ -+ fdb->updated = flow->used; -+ -+ return true; -+} -+ -+ -+static void -+br_offload_flow_refresh_time(struct bridge_flow *flow) -+{ -+ br_offload_flow_fdb_refresh_time(flow, flow->fdb_in); -+ br_offload_flow_fdb_refresh_time(flow, flow->fdb_out); -+} -+ -+static void -+br_offload_destroy_cb(void *ptr, void *arg) -+{ -+ struct bridge_flow *flow = ptr; -+ -+ __br_offload_flow_free(flow); -+} -+ -+static bool -+br_offload_need_gc(struct net_bridge_port *p) -+{ -+ return (atomic_read(&p->offload.rht.nelems) + -+ p->br->offload_cache_reserved) >= p->br->offload_cache_size; -+} -+ -+static void -+br_offload_gc_work(struct work_struct *work) -+{ -+ struct rhashtable_iter hti; -+ struct net_bridge_port *p; -+ struct bridge_flow *gc_flow = NULL; -+ struct bridge_flow *flow; -+ unsigned long gc_used; -+ -+ p = container_of(work, struct net_bridge_port, offload.gc_work); -+ -+ if (!br_offload_need_gc(p)) -+ return; -+ -+ rhashtable_walk_enter(&p->offload.rht, &hti); -+ rhashtable_walk_start(&hti); -+ while ((flow = rhashtable_walk_next(&hti)) != NULL) { -+ unsigned long used; -+ -+ if (IS_ERR(flow)) -+ continue; -+ -+ used = READ_ONCE(flow->used); -+ if (!used) -+ continue; -+ -+ if (gc_flow && !time_before(used, gc_used)) -+ continue; -+ -+ gc_flow = flow; -+ gc_used = used; -+ } -+ rhashtable_walk_stop(&hti); -+ rhashtable_walk_exit(&hti); -+ -+ if (!gc_flow) -+ return; -+ -+ spin_lock_bh(&offload_lock); -+ if (br_offload_need_gc(p) && gc_flow && -+ gc_flow->used == gc_used) -+ br_offload_flow_free(gc_flow); -+ if (p->offload.enabled && br_offload_need_gc(p)) -+ queue_work(system_long_wq, work); -+ spin_unlock_bh(&offload_lock); -+ -+} -+ -+void br_offload_port_state(struct net_bridge_port *p) -+{ -+ struct net_bridge_port_offload *o = &p->offload; -+ bool enabled = true; -+ bool flush = false; -+ -+ if (p->state != BR_STATE_FORWARDING || -+ !(p->flags & BR_OFFLOAD)) -+ enabled = false; -+ -+ spin_lock_bh(&offload_lock); -+ if (o->enabled == enabled) -+ goto out; -+ -+ if (enabled) { -+ if (!o->gc_work.func) -+ INIT_WORK(&o->gc_work, br_offload_gc_work); -+ rhashtable_init(&o->rht, &flow_params); -+ } else { -+ flush = true; -+ rhashtable_free_and_destroy(&o->rht, br_offload_destroy_cb, o); -+ } -+ -+ o->enabled = enabled; -+ -+out: -+ spin_unlock_bh(&offload_lock); -+ -+ if (flush) -+ flush_work(&o->gc_work); -+} -+ -+void br_offload_fdb_update(const struct net_bridge_fdb_entry *fdb) -+{ -+ struct bridge_flow *f; -+ struct hlist_node *tmp; -+ -+ spin_lock_bh(&offload_lock); -+ -+ hlist_for_each_entry_safe(f, tmp, &fdb->offload_in, fdb_list_in) -+ br_offload_flow_free(f); -+ -+ hlist_for_each_entry_safe(f, tmp, &fdb->offload_out, fdb_list_out) -+ br_offload_flow_free(f); -+ -+ spin_unlock_bh(&offload_lock); -+} -+ -+static void -+br_offload_prepare_key(struct net_bridge_port *p, struct bridge_flow_key *key, -+ struct sk_buff *skb) -+{ -+ memset(key, 0, sizeof(*key)); -+ memcpy(key, eth_hdr(skb), 2 * ETH_ALEN); -+#ifdef CONFIG_BRIDGE_VLAN_FILTERING -+ if (!br_opt_get(p->br, BROPT_VLAN_ENABLED)) -+ return; -+ -+ if (!skb_vlan_tag_present(skb) || skb->vlan_proto != p->br->vlan_proto) -+ return; -+ -+ key->vlan_present = true; -+ key->vlan_tag = skb_vlan_tag_get_id(skb); -+#endif -+} -+ -+void br_offload_output(struct sk_buff *skb) -+{ -+ struct net_bridge_port_offload *o; -+ struct br_input_skb_cb *cb = (struct br_input_skb_cb *)skb->cb; -+ struct net_bridge_port *p, *inp; -+ struct net_device *dev; -+ struct net_bridge_fdb_entry *fdb_in, *fdb_out; -+ struct net_bridge_vlan_group *vg; -+ struct bridge_flow_key key; -+ struct bridge_flow *flow; -+ u16 vlan; -+ -+ if (!cb->offload) -+ return; -+ -+ rcu_read_lock(); -+ -+ p = br_port_get_rcu(skb->dev); -+ if (!p) -+ goto out; -+ -+ o = &p->offload; -+ if (!o->enabled) -+ goto out; -+ -+ if (atomic_read(&p->offload.rht.nelems) >= p->br->offload_cache_size) -+ goto out; -+ -+ dev = dev_get_by_index_rcu(dev_net(p->br->dev), cb->input_ifindex); -+ if (!dev) -+ goto out; -+ -+ inp = br_port_get_rcu(dev); -+ if (!inp) -+ goto out; -+ -+ vg = nbp_vlan_group_rcu(inp); -+ vlan = cb->input_vlan_present ? cb->input_vlan_tag : br_get_pvid(vg); -+ fdb_in = br_fdb_find_rcu(p->br, eth_hdr(skb)->h_source, vlan); -+ if (!fdb_in || !fdb_in->dst) -+ goto out; -+ -+ vg = nbp_vlan_group_rcu(p); -+ vlan = skb_vlan_tag_present(skb) ? skb_vlan_tag_get_id(skb) : br_get_pvid(vg); -+ fdb_out = br_fdb_find_rcu(p->br, eth_hdr(skb)->h_dest, vlan); -+ if (!fdb_out || !fdb_out->dst) -+ goto out; -+ -+ br_offload_prepare_key(p, &key, skb); -+#ifdef CONFIG_BRIDGE_VLAN_FILTERING -+ key.vlan_present = cb->input_vlan_present; -+ key.vlan_tag = cb->input_vlan_tag; -+#endif -+ -+ flow = kmem_cache_alloc(offload_cache, GFP_ATOMIC); -+ flow->port = inp; -+ memcpy(&flow->key, &key, sizeof(key)); -+ -+#ifdef CONFIG_BRIDGE_VLAN_FILTERING -+ flow->vlan_out_present = skb_vlan_tag_present(skb); -+ flow->vlan_out = skb_vlan_tag_get(skb); -+#endif -+ -+ flow->fdb_in = fdb_in; -+ flow->fdb_out = fdb_out; -+ flow->used = jiffies; -+ -+ spin_lock_bh(&offload_lock); -+ if (!o->enabled || -+ atomic_read(&p->offload.rht.nelems) >= p->br->offload_cache_size || -+ rhashtable_insert_fast(&inp->offload.rht, &flow->node, flow_params)) { -+ kmem_cache_free(offload_cache, flow); -+ goto out_unlock; -+ } -+ -+ hlist_add_head(&flow->fdb_list_in, &fdb_in->offload_in); -+ hlist_add_head(&flow->fdb_list_out, &fdb_out->offload_out); -+ -+ if (br_offload_need_gc(p)) -+ queue_work(system_long_wq, &p->offload.gc_work); -+ -+out_unlock: -+ spin_unlock_bh(&offload_lock); -+ -+out: -+ rcu_read_unlock(); -+} -+ -+bool br_offload_input(struct net_bridge_port *p, struct sk_buff *skb) -+{ -+ struct net_bridge_port_offload *o = &p->offload; -+ struct br_input_skb_cb *cb = (struct br_input_skb_cb *)skb->cb; -+ struct bridge_flow_key key; -+ struct net_bridge_port *dst; -+ struct bridge_flow *flow; -+ unsigned long now = jiffies; -+ bool ret = false; -+ -+ if (skb->len < sizeof(key)) -+ return false; -+ -+ if (!o->enabled) -+ return false; -+ -+ if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) -+ return false; -+ -+ br_offload_prepare_key(p, &key, skb); -+ -+ rcu_read_lock(); -+ flow = rhashtable_lookup(&o->rht, &key, flow_params); -+ if (!flow) { -+ cb->offload = 1; -+#ifdef CONFIG_BRIDGE_VLAN_FILTERING -+ cb->input_vlan_present = key.vlan_present != 0; -+ cb->input_vlan_tag = key.vlan_tag; -+#endif -+ cb->input_ifindex = p->dev->ifindex; -+ goto out; -+ } -+ -+ if (flow->fdb_in->dst != p) -+ goto out; -+ -+ dst = flow->fdb_out->dst; -+ if (!dst) -+ goto out; -+ -+ ret = true; -+#ifdef CONFIG_BRIDGE_VLAN_FILTERING -+ if (!flow->vlan_out_present && key.vlan_present) { -+ __vlan_hwaccel_clear_tag(skb); -+ } else if (flow->vlan_out_present) { -+ if (skb_vlan_tag_present(skb) && -+ skb->vlan_proto != p->br->vlan_proto) { -+ /* Protocol-mismatch, empty out vlan_tci for new tag */ -+ skb_push(skb, ETH_HLEN); -+ skb = vlan_insert_tag_set_proto(skb, skb->vlan_proto, -+ skb_vlan_tag_get(skb)); -+ if (unlikely(!skb)) -+ goto out; -+ -+ skb_pull(skb, ETH_HLEN); -+ skb_reset_mac_len(skb); -+ } -+ -+ __vlan_hwaccel_put_tag(skb, p->br->vlan_proto, -+ flow->vlan_out); -+ } -+#endif -+ -+ skb->dev = dst->dev; -+ skb_push(skb, ETH_HLEN); -+ -+ if (skb_warn_if_lro(skb) || !is_skb_forwardable(skb->dev, skb)) { -+ kfree_skb(skb); -+ goto out; -+ } -+ -+ if (now - flow->used >= HZ) { -+ flow->used = now; -+ br_offload_flow_refresh_time(flow); -+ } -+ -+ skb_forward_csum(skb); -+ dev_queue_xmit(skb); -+ -+out: -+ rcu_read_unlock(); -+ return ret; -+} -+ -+static void -+br_offload_check_gc(struct net_bridge *br) -+{ -+ struct net_bridge_port *p; -+ -+ spin_lock_bh(&br->lock); -+ list_for_each_entry(p, &br->port_list, list) -+ if (br_offload_need_gc(p)) -+ queue_work(system_long_wq, &p->offload.gc_work); -+ spin_unlock_bh(&br->lock); -+} -+ -+ -+int br_offload_set_cache_size(struct net_bridge *br, unsigned long val) -+{ -+ br->offload_cache_size = val; -+ br_offload_check_gc(br); -+ -+ return 0; -+} -+ -+int br_offload_set_cache_reserved(struct net_bridge *br, unsigned long val) -+{ -+ br->offload_cache_reserved = val; -+ br_offload_check_gc(br); -+ -+ return 0; -+} -+ -+int __init br_offload_init(void) -+{ -+ offload_cache = kmem_cache_create("bridge_offload_cache", -+ sizeof(struct bridge_flow), -+ 0, SLAB_HWCACHE_ALIGN, NULL); -+ if (!offload_cache) -+ return -ENOMEM; -+ -+ return 0; -+} -+ -+void br_offload_fini(void) -+{ -+ kmem_cache_destroy(offload_cache); -+} ---- a/net/bridge/br_private.h -+++ b/net/bridge/br_private.h -@@ -207,7 +207,13 @@ struct net_bridge_fdb_entry { - unsigned long updated ____cacheline_aligned_in_smp; - unsigned long used; - -- struct rcu_head rcu; -+ union { -+ struct { -+ struct hlist_head offload_in; -+ struct hlist_head offload_out; -+ }; -+ struct rcu_head rcu; -+ }; - }; - - #define MDB_PG_FLAGS_PERMANENT BIT(0) -@@ -280,6 +286,12 @@ struct net_bridge_mdb_entry { - struct rcu_head rcu; - }; - -+struct net_bridge_port_offload { -+ struct rhashtable rht; -+ struct work_struct gc_work; -+ bool enabled; -+}; -+ - struct net_bridge_port { - struct net_bridge *br; - struct net_device *dev; -@@ -337,6 +349,7 @@ struct net_bridge_port { - u16 backup_redirected_cnt; - - struct bridge_stp_xstats stp_xstats; -+ struct net_bridge_port_offload offload; - }; - - #define kobj_to_brport(obj) container_of(obj, struct net_bridge_port, kobj) -@@ -475,6 +488,9 @@ struct net_bridge { - struct kobject *ifobj; - u32 auto_cnt; - -+ u32 offload_cache_size; -+ u32 offload_cache_reserved; -+ - #ifdef CONFIG_NET_SWITCHDEV - int offload_fwd_mark; - #endif -@@ -501,6 +517,10 @@ struct br_input_skb_cb { - #ifdef CONFIG_NETFILTER_FAMILY_BRIDGE - u8 br_netfilter_broute:1; - #endif -+ u8 offload:1; -+ u8 input_vlan_present:1; -+ u16 input_vlan_tag; -+ int input_ifindex; - - #ifdef CONFIG_NET_SWITCHDEV - int offload_fwd_mark; ---- /dev/null -+++ b/net/bridge/br_private_offload.h -@@ -0,0 +1,21 @@ -+#ifndef __BR_OFFLOAD_H -+#define __BR_OFFLOAD_H -+ -+bool br_offload_input(struct net_bridge_port *p, struct sk_buff *skb); -+void br_offload_output(struct sk_buff *skb); -+void br_offload_port_state(struct net_bridge_port *p); -+void br_offload_fdb_update(const struct net_bridge_fdb_entry *fdb); -+int br_offload_init(void); -+void br_offload_fini(void); -+int br_offload_set_cache_size(struct net_bridge *br, unsigned long val); -+int br_offload_set_cache_reserved(struct net_bridge *br, unsigned long val); -+ -+static inline void br_offload_skb_disable(struct sk_buff *skb) -+{ -+ struct br_input_skb_cb *cb = (struct br_input_skb_cb *)skb->cb; -+ -+ if (cb->offload) -+ cb->offload = 0; -+} -+ -+#endif ---- a/net/bridge/br_stp.c -+++ b/net/bridge/br_stp.c -@@ -12,6 +12,7 @@ - - #include "br_private.h" - #include "br_private_stp.h" -+#include "br_private_offload.h" - - /* since time values in bpdu are in jiffies and then scaled (1/256) - * before sending, make sure that is at least one STP tick. -@@ -52,6 +53,8 @@ void br_set_state(struct net_bridge_port - (unsigned int) p->port_no, p->dev->name, - br_port_state_names[p->state]); - -+ br_offload_port_state(p); -+ - if (p->br->stp_enabled == BR_KERNEL_STP) { - switch (p->state) { - case BR_STATE_BLOCKING: ---- a/net/bridge/br_sysfs_br.c -+++ b/net/bridge/br_sysfs_br.c -@@ -18,6 +18,7 @@ - #include - - #include "br_private.h" -+#include "br_private_offload.h" - - #define to_bridge(cd) ((struct net_bridge *)netdev_priv(to_net_dev(cd))) - -@@ -842,6 +843,38 @@ static ssize_t vlan_stats_per_port_store - static DEVICE_ATTR_RW(vlan_stats_per_port); - #endif - -+static ssize_t offload_cache_size_show(struct device *d, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct net_bridge *br = to_bridge(d); -+ return sprintf(buf, "%u\n", br->offload_cache_size); -+} -+ -+static ssize_t offload_cache_size_store(struct device *d, -+ struct device_attribute *attr, -+ const char *buf, size_t len) -+{ -+ return store_bridge_parm(d, buf, len, br_offload_set_cache_size); -+} -+static DEVICE_ATTR_RW(offload_cache_size); -+ -+static ssize_t offload_cache_reserved_show(struct device *d, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct net_bridge *br = to_bridge(d); -+ return sprintf(buf, "%u\n", br->offload_cache_reserved); -+} -+ -+static ssize_t offload_cache_reserved_store(struct device *d, -+ struct device_attribute *attr, -+ const char *buf, size_t len) -+{ -+ return store_bridge_parm(d, buf, len, br_offload_set_cache_reserved); -+} -+static DEVICE_ATTR_RW(offload_cache_reserved); -+ - static struct attribute *bridge_attrs[] = { - &dev_attr_forward_delay.attr, - &dev_attr_hello_time.attr, -@@ -896,6 +929,8 @@ static struct attribute *bridge_attrs[] - &dev_attr_vlan_stats_enabled.attr, - &dev_attr_vlan_stats_per_port.attr, - #endif -+ &dev_attr_offload_cache_size.attr, -+ &dev_attr_offload_cache_reserved.attr, - NULL - }; - ---- a/net/bridge/br_sysfs_if.c -+++ b/net/bridge/br_sysfs_if.c -@@ -234,6 +234,7 @@ BRPORT_ATTR_FLAG(broadcast_flood, BR_BCA - BRPORT_ATTR_FLAG(neigh_suppress, BR_NEIGH_SUPPRESS); - BRPORT_ATTR_FLAG(isolated, BR_ISOLATED); - BRPORT_ATTR_FLAG(bpdu_filter, BR_BPDU_FILTER); -+BRPORT_ATTR_FLAG(offload, BR_OFFLOAD); - - #ifdef CONFIG_BRIDGE_IGMP_SNOOPING - static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf) -@@ -288,6 +289,7 @@ static const struct brport_attribute *br - &brport_attr_isolated, - &brport_attr_bpdu_filter, - &brport_attr_backup_port, -+ &brport_attr_offload, - NULL - }; - ---- a/net/bridge/br_vlan_tunnel.c -+++ b/net/bridge/br_vlan_tunnel.c -@@ -15,6 +15,7 @@ - - #include "br_private.h" - #include "br_private_tunnel.h" -+#include "br_private_offload.h" - - static inline int br_vlan_tunid_cmp(struct rhashtable_compare_arg *arg, - const void *ptr) -@@ -180,6 +181,7 @@ int br_handle_ingress_vlan_tunnel(struct - skb_dst_drop(skb); - - __vlan_hwaccel_put_tag(skb, p->br->vlan_proto, vlan->vid); -+ br_offload_skb_disable(skb); - - return 0; - } -@@ -203,6 +205,7 @@ int br_handle_egress_vlan_tunnel(struct - if (err) - return err; - -+ br_offload_skb_disable(skb); - tunnel_dst = rcu_dereference(vlan->tinfo.tunnel_dst); - if (tunnel_dst && dst_hold_safe(&tunnel_dst->dst)) - skb_dst_set(skb, &tunnel_dst->dst); diff --git a/target/linux/generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch b/target/linux/generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch deleted file mode 100644 index 517d5cbe52..0000000000 --- a/target/linux/generic/hack-5.10/601-of_net-add-mac-address-ascii-support.patch +++ /dev/null @@ -1,116 +0,0 @@ -From: Yousong Zhou -Subject: [PATCH] of: net: add nvmem cell mac-address-ascii support - -This is needed for devices with mac address stored in ascii format, -e.g. HiWiFi HC6361 to be ported in the following patch. - -Submitted-by: Yousong Zhou ---- - net/core/of_net.c | 83 ++++++++++++------ - 1 files changed, 72 insertions(+), 11 deletions(-) - ---- a/drivers/of/of_net.c -+++ b/drivers/of/of_net.c -@@ -57,13 +57,70 @@ static int of_get_mac_addr(struct device - return -ENODEV; - } - -+static void *nvmem_cell_get_mac_address(struct nvmem_cell *cell) -+{ -+ size_t len; -+ void *mac; -+ -+ mac = nvmem_cell_read(cell, &len); -+ if (IS_ERR(mac)) -+ return mac; -+ if (len != ETH_ALEN) { -+ kfree(mac); -+ return ERR_PTR(-EINVAL); -+ } -+ return mac; -+} -+ -+static void *nvmem_cell_get_mac_address_ascii(struct nvmem_cell *cell) -+{ -+ size_t len; -+ int ret; -+ void *mac_ascii; -+ u8 *mac; -+ -+ mac_ascii = nvmem_cell_read(cell, &len); -+ if (IS_ERR(mac_ascii)) -+ return mac_ascii; -+ if (len != ETH_ALEN*2+5) { -+ kfree(mac_ascii); -+ return ERR_PTR(-EINVAL); -+ } -+ mac = kmalloc(ETH_ALEN, GFP_KERNEL); -+ if (!mac) { -+ kfree(mac_ascii); -+ return ERR_PTR(-ENOMEM); -+ } -+ ret = sscanf(mac_ascii, "%2hhx:%2hhx:%2hhx:%2hhx:%2hhx:%2hhx", -+ &mac[0], &mac[1], &mac[2], -+ &mac[3], &mac[4], &mac[5]); -+ kfree(mac_ascii); -+ if (ret == ETH_ALEN) -+ return mac; -+ kfree(mac); -+ return ERR_PTR(-EINVAL); -+} -+ -+static struct nvmem_cell_mac_address_property { -+ char *name; -+ void *(*read)(struct nvmem_cell *); -+} nvmem_cell_mac_address_properties[] = { -+ { -+ .name = "mac-address", -+ .read = nvmem_cell_get_mac_address, -+ }, { -+ .name = "mac-address-ascii", -+ .read = nvmem_cell_get_mac_address_ascii, -+ }, -+}; -+ - static int of_get_mac_addr_nvmem(struct device_node *np, u8 *addr) - { - struct platform_device *pdev = of_find_device_by_node(np); -+ struct nvmem_cell_mac_address_property *property; - struct nvmem_cell *cell; - const void *mac; -- size_t len; -- int ret; -+ int ret, i; - - /* Try lookup by device first, there might be a nvmem_cell_lookup - * associated with a given device. -@@ -74,17 +131,26 @@ static int of_get_mac_addr_nvmem(struct - return ret; - } - -- cell = of_nvmem_cell_get(np, "mac-address"); -+ for (i = 0; i < ARRAY_SIZE(nvmem_cell_mac_address_properties); i++) { -+ property = &nvmem_cell_mac_address_properties[i]; -+ cell = of_nvmem_cell_get(np, property->name); -+ /* For -EPROBE_DEFER don't try other properties. -+ * We'll get back to this one. -+ */ -+ if (!IS_ERR(cell) || PTR_ERR(cell) == -EPROBE_DEFER) -+ break; -+ } -+ - if (IS_ERR(cell)) - return PTR_ERR(cell); - -- mac = nvmem_cell_read(cell, &len); -+ mac = property->read(cell); - nvmem_cell_put(cell); - - if (IS_ERR(mac)) - return PTR_ERR(mac); - -- if (len != ETH_ALEN || !is_valid_ether_addr(mac)) { -+ if (!is_valid_ether_addr(mac)) { - kfree(mac); - return -EINVAL; - } diff --git a/target/linux/generic/hack-5.10/645-netfilter-connmark-introduce-set-dscpmark.patch b/target/linux/generic/hack-5.10/645-netfilter-connmark-introduce-set-dscpmark.patch deleted file mode 100644 index c368c4ae3b..0000000000 --- a/target/linux/generic/hack-5.10/645-netfilter-connmark-introduce-set-dscpmark.patch +++ /dev/null @@ -1,214 +0,0 @@ -From eda40b8c8c82e0f2789d6bc8bf63846dce2e8f32 Mon Sep 17 00:00:00 2001 -From: Kevin Darbyshire-Bryant -Date: Sat, 23 Mar 2019 09:29:49 +0000 -Subject: [PATCH] netfilter: connmark: introduce set-dscpmark - -set-dscpmark is a method of storing the DSCP of an ip packet into -conntrack mark. In combination with a suitable tc filter action -(act_ctinfo) DSCP values are able to be stored in the mark on egress and -restored on ingress across links that otherwise alter or bleach DSCP. - -This is useful for qdiscs such as CAKE which are able to shape according -to policies based on DSCP. - -Ingress classification is traditionally a challenging task since -iptables rules haven't yet run and tc filter/eBPF programs are pre-NAT -lookups, hence are unable to see internal IPv4 addresses as used on the -typical home masquerading gateway. - -x_tables CONNMARK set-dscpmark target solves the problem of storing the -DSCP to the conntrack mark in a way suitable for the new act_ctinfo tc -action to restore. - -The set-dscpmark option accepts 2 parameters, a 32bit 'dscpmask' and a -32bit 'statemask'. The dscp mask must be 6 contiguous bits and -represents the area where the DSCP will be stored in the connmark. The -state mask is a minimum 1 bit length mask that must not overlap with the -dscpmask. It represents a flag which is set when the DSCP has been -stored in the conntrack mark. This is useful to implement a 'one shot' -iptables based classification where the 'complicated' iptables rules are -only run once to classify the connection on initial (egress) packet and -subsequent packets are all marked/restored with the same DSCP. A state -mask of zero disables the setting of a status bit/s. - -example syntax with a suitably modified iptables user space application: - -iptables -A QOS_MARK_eth0 -t mangle -j CONNMARK --set-dscpmark 0xfc000000/0x01000000 - -Would store the DSCP in the top 6 bits of the 32bit mark field, and use -the LSB of the top byte as the 'DSCP has been stored' marker. - -|----0xFC----conntrack mark----000000---| -| Bits 31-26 | bit 25 | bit24 |~~~ Bit 0| -| DSCP | unused | flag |unused | -|-----------------------0x01---000000---| - ^ ^ - | | - ---| Conditional flag - | set this when dscp -|-ip diffserv-| stored in mark -| 6 bits | -|-------------| - -an identically configured tc action to restore looks like: - -tc filter show dev eth0 ingress -filter parent ffff: protocol all pref 10 u32 chain 0 -filter parent ffff: protocol all pref 10 u32 chain 0 fh 800: ht divisor 1 -filter parent ffff: protocol all pref 10 u32 chain 0 fh 800::800 order 2048 key ht 800 bkt 0 flowid 1: not_in_hw - match 00000000/00000000 at 0 - action order 1: ctinfo zone 0 pipe - index 2 ref 1 bind 1 dscp 0xfc000000/0x1000000 - - action order 2: mirred (Egress Redirect to device ifb4eth0) stolen - index 1 ref 1 bind 1 - -|----0xFC----conntrack mark----000000---| -| Bits 31-26 | bit 25 | bit24 |~~~ Bit 0| -| DSCP | unused | flag |unused | -|-----------------------0x01---000000---| - | | - | | - ---| Conditional flag - v only restore if set -|-ip diffserv-| -| 6 bits | -|-------------| - -Signed-off-by: Kevin Darbyshire-Bryant ---- - include/uapi/linux/netfilter/xt_connmark.h | 10 ++++ - net/netfilter/xt_connmark.c | 55 ++++++++++++++++++---- - 2 files changed, 57 insertions(+), 8 deletions(-) - ---- a/include/uapi/linux/netfilter/xt_connmark.h -+++ b/include/uapi/linux/netfilter/xt_connmark.h -@@ -20,6 +20,11 @@ enum { - }; - - enum { -+ XT_CONNMARK_VALUE = (1 << 0), -+ XT_CONNMARK_DSCP = (1 << 1) -+}; -+ -+enum { - D_SHIFT_LEFT = 0, - D_SHIFT_RIGHT, - }; -@@ -34,6 +39,11 @@ struct xt_connmark_tginfo2 { - __u8 shift_dir, shift_bits, mode; - }; - -+struct xt_connmark_tginfo3 { -+ __u32 ctmark, ctmask, nfmask; -+ __u8 shift_dir, shift_bits, mode, func; -+}; -+ - struct xt_connmark_mtinfo1 { - __u32 mark, mask; - __u8 invert; ---- a/net/netfilter/xt_connmark.c -+++ b/net/netfilter/xt_connmark.c -@@ -24,13 +24,13 @@ MODULE_ALIAS("ipt_connmark"); - MODULE_ALIAS("ip6t_connmark"); - - static unsigned int --connmark_tg_shift(struct sk_buff *skb, const struct xt_connmark_tginfo2 *info) -+connmark_tg_shift(struct sk_buff *skb, const struct xt_connmark_tginfo3 *info) - { - enum ip_conntrack_info ctinfo; - u_int32_t new_targetmark; - struct nf_conn *ct; - u_int32_t newmark; -- u_int32_t oldmark; -+ u_int8_t dscp; - - ct = nf_ct_get(skb, &ctinfo); - if (ct == NULL) -@@ -38,13 +38,24 @@ connmark_tg_shift(struct sk_buff *skb, c - - switch (info->mode) { - case XT_CONNMARK_SET: -- oldmark = READ_ONCE(ct->mark); -- newmark = (oldmark & ~info->ctmask) ^ info->ctmark; -- if (info->shift_dir == D_SHIFT_RIGHT) -- newmark >>= info->shift_bits; -- else -- newmark <<= info->shift_bits; -+ newmark = READ_ONCE(ct->mark); -+ if (info->func & XT_CONNMARK_VALUE) { -+ newmark = (newmark & ~info->ctmask) ^ info->ctmark; -+ if (info->shift_dir == D_SHIFT_RIGHT) -+ newmark >>= info->shift_bits; -+ else -+ newmark <<= info->shift_bits; -+ } else if (info->func & XT_CONNMARK_DSCP) { -+ if (skb->protocol == htons(ETH_P_IP)) -+ dscp = ipv4_get_dsfield(ip_hdr(skb)) >> 2; -+ else if (skb->protocol == htons(ETH_P_IPV6)) -+ dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2; -+ else /* protocol doesn't have diffserv */ -+ break; - -+ newmark = (newmark & ~info->ctmark) | -+ (info->ctmask | (dscp << info->shift_bits)); -+ } - if (READ_ONCE(ct->mark) != newmark) { - WRITE_ONCE(ct->mark, newmark); - nf_conntrack_event_cache(IPCT_MARK, ct); -@@ -83,20 +94,36 @@ static unsigned int - connmark_tg(struct sk_buff *skb, const struct xt_action_param *par) - { - const struct xt_connmark_tginfo1 *info = par->targinfo; -- const struct xt_connmark_tginfo2 info2 = { -+ const struct xt_connmark_tginfo3 info3 = { - .ctmark = info->ctmark, - .ctmask = info->ctmask, - .nfmask = info->nfmask, - .mode = info->mode, -+ .func = XT_CONNMARK_VALUE - }; - -- return connmark_tg_shift(skb, &info2); -+ return connmark_tg_shift(skb, &info3); - } - - static unsigned int - connmark_tg_v2(struct sk_buff *skb, const struct xt_action_param *par) - { - const struct xt_connmark_tginfo2 *info = par->targinfo; -+ const struct xt_connmark_tginfo3 info3 = { -+ .ctmark = info->ctmark, -+ .ctmask = info->ctmask, -+ .nfmask = info->nfmask, -+ .mode = info->mode, -+ .func = XT_CONNMARK_VALUE -+ }; -+ -+ return connmark_tg_shift(skb, &info3); -+} -+ -+static unsigned int -+connmark_tg_v3(struct sk_buff *skb, const struct xt_action_param *par) -+{ -+ const struct xt_connmark_tginfo3 *info = par->targinfo; - - return connmark_tg_shift(skb, info); - } -@@ -167,6 +194,16 @@ static struct xt_target connmark_tg_reg[ - .targetsize = sizeof(struct xt_connmark_tginfo2), - .destroy = connmark_tg_destroy, - .me = THIS_MODULE, -+ }, -+ { -+ .name = "CONNMARK", -+ .revision = 3, -+ .family = NFPROTO_UNSPEC, -+ .checkentry = connmark_tg_check, -+ .target = connmark_tg_v3, -+ .targetsize = sizeof(struct xt_connmark_tginfo3), -+ .destroy = connmark_tg_destroy, -+ .me = THIS_MODULE, - } - }; - diff --git a/target/linux/generic/hack-5.10/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-5.10/650-netfilter-add-xt_FLOWOFFLOAD-target.patch deleted file mode 100644 index b83a185aeb..0000000000 --- a/target/linux/generic/hack-5.10/650-netfilter-add-xt_FLOWOFFLOAD-target.patch +++ /dev/null @@ -1,874 +0,0 @@ -From: Felix Fietkau -Date: Tue, 20 Feb 2018 15:56:02 +0100 -Subject: [PATCH] netfilter: add xt_FLOWOFFLOAD target - -Signed-off-by: Felix Fietkau ---- - create mode 100644 net/netfilter/xt_OFFLOAD.c - ---- a/net/ipv4/netfilter/Kconfig -+++ b/net/ipv4/netfilter/Kconfig -@@ -56,8 +56,6 @@ config NF_TABLES_ARP - help - This option enables the ARP support for nf_tables. - --endif # NF_TABLES -- - config NF_FLOW_TABLE_IPV4 - tristate "Netfilter flow table IPv4 module" - depends on NF_FLOW_TABLE -@@ -66,6 +64,8 @@ config NF_FLOW_TABLE_IPV4 - - To compile it as a module, choose M here. - -+endif # NF_TABLES -+ - config NF_DUP_IPV4 - tristate "Netfilter IPv4 packet duplication to alternate destination" - depends on !NF_CONNTRACK || NF_CONNTRACK ---- a/net/ipv6/netfilter/Kconfig -+++ b/net/ipv6/netfilter/Kconfig -@@ -45,7 +45,6 @@ config NFT_FIB_IPV6 - multicast or blackhole. - - endif # NF_TABLES_IPV6 --endif # NF_TABLES - - config NF_FLOW_TABLE_IPV6 - tristate "Netfilter flow table IPv6 module" -@@ -55,6 +54,8 @@ config NF_FLOW_TABLE_IPV6 - - To compile it as a module, choose M here. - -+endif # NF_TABLES -+ - config NF_DUP_IPV6 - tristate "Netfilter IPv6 packet duplication to alternate destination" - depends on !NF_CONNTRACK || NF_CONNTRACK ---- a/net/netfilter/Kconfig -+++ b/net/netfilter/Kconfig -@@ -682,8 +682,6 @@ config NFT_FIB_NETDEV - - endif # NF_TABLES_NETDEV - --endif # NF_TABLES -- - config NF_FLOW_TABLE_INET - tristate "Netfilter flow table mixed IPv4/IPv6 module" - depends on NF_FLOW_TABLE -@@ -692,11 +690,12 @@ config NF_FLOW_TABLE_INET - - To compile it as a module, choose M here. - -+endif # NF_TABLES -+ - config NF_FLOW_TABLE - tristate "Netfilter flow table module" - depends on NETFILTER_INGRESS - depends on NF_CONNTRACK -- depends on NF_TABLES - help - This option adds the flow table core infrastructure. - -@@ -976,6 +975,15 @@ config NETFILTER_XT_TARGET_NOTRACK - depends on NETFILTER_ADVANCED - select NETFILTER_XT_TARGET_CT - -+config NETFILTER_XT_TARGET_FLOWOFFLOAD -+ tristate '"FLOWOFFLOAD" target support' -+ depends on NF_FLOW_TABLE -+ depends on NETFILTER_INGRESS -+ help -+ This option adds a `FLOWOFFLOAD' target, which uses the nf_flow_offload -+ module to speed up processing of packets by bypassing the usual -+ netfilter chains -+ - config NETFILTER_XT_TARGET_RATEEST - tristate '"RATEEST" target support' - depends on NETFILTER_ADVANCED ---- a/net/netfilter/Makefile -+++ b/net/netfilter/Makefile -@@ -145,6 +145,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF - obj-$(CONFIG_NETFILTER_XT_TARGET_CONNSECMARK) += xt_CONNSECMARK.o - obj-$(CONFIG_NETFILTER_XT_TARGET_CT) += xt_CT.o - obj-$(CONFIG_NETFILTER_XT_TARGET_DSCP) += xt_DSCP.o -+obj-$(CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD) += xt_FLOWOFFLOAD.o - obj-$(CONFIG_NETFILTER_XT_TARGET_HL) += xt_HL.o - obj-$(CONFIG_NETFILTER_XT_TARGET_HMARK) += xt_HMARK.o - obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o ---- /dev/null -+++ b/net/netfilter/xt_FLOWOFFLOAD.c -@@ -0,0 +1,712 @@ -+/* -+ * Copyright (C) 2018-2021 Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct xt_flowoffload_hook { -+ struct hlist_node list; -+ struct nf_hook_ops ops; -+ struct net *net; -+ bool registered; -+ bool used; -+}; -+ -+struct xt_flowoffload_table { -+ struct nf_flowtable ft; -+ struct hlist_head hooks; -+ struct delayed_work work; -+}; -+ -+struct nf_forward_info { -+ const struct net_device *indev; -+ const struct net_device *outdev; -+ const struct net_device *hw_outdev; -+ struct id { -+ __u16 id; -+ __be16 proto; -+ } encap[NF_FLOW_TABLE_ENCAP_MAX]; -+ u8 num_encaps; -+ u8 ingress_vlans; -+ u8 h_source[ETH_ALEN]; -+ u8 h_dest[ETH_ALEN]; -+ enum flow_offload_xmit_type xmit_type; -+}; -+ -+static DEFINE_SPINLOCK(hooks_lock); -+ -+struct xt_flowoffload_table flowtable[2]; -+ -+static inline __be16 nf_flow_pppoe_proto(const struct sk_buff *skb) -+{ -+ __be16 proto; -+ -+ proto = *((__be16 *)(skb_mac_header(skb) + ETH_HLEN + -+ sizeof(struct pppoe_hdr))); -+ switch (proto) { -+ case htons(PPP_IP): -+ return htons(ETH_P_IP); -+ case htons(PPP_IPV6): -+ return htons(ETH_P_IPV6); -+ } -+ -+ return 0; -+} -+ -+static unsigned int -+xt_flowoffload_net_hook(void *priv, struct sk_buff *skb, -+ const struct nf_hook_state *state) -+{ -+ struct vlan_ethhdr *veth; -+ __be16 proto; -+ -+ switch (skb->protocol) { -+ case htons(ETH_P_8021Q): -+ veth = (struct vlan_ethhdr *)skb_mac_header(skb); -+ proto = veth->h_vlan_encapsulated_proto; -+ break; -+ case htons(ETH_P_PPP_SES): -+ proto = nf_flow_pppoe_proto(skb); -+ break; -+ default: -+ proto = skb->protocol; -+ break; -+ } -+ -+ switch (proto) { -+ case htons(ETH_P_IP): -+ return nf_flow_offload_ip_hook(priv, skb, state); -+ case htons(ETH_P_IPV6): -+ return nf_flow_offload_ipv6_hook(priv, skb, state); -+ } -+ -+ return NF_ACCEPT; -+} -+ -+static int -+xt_flowoffload_create_hook(struct xt_flowoffload_table *table, -+ struct net_device *dev) -+{ -+ struct xt_flowoffload_hook *hook; -+ struct nf_hook_ops *ops; -+ -+ hook = kzalloc(sizeof(*hook), GFP_ATOMIC); -+ if (!hook) -+ return -ENOMEM; -+ -+ ops = &hook->ops; -+ ops->pf = NFPROTO_NETDEV; -+ ops->hooknum = NF_NETDEV_INGRESS; -+ ops->priority = 10; -+ ops->priv = &table->ft; -+ ops->hook = xt_flowoffload_net_hook; -+ ops->dev = dev; -+ -+ hlist_add_head(&hook->list, &table->hooks); -+ mod_delayed_work(system_power_efficient_wq, &table->work, 0); -+ -+ return 0; -+} -+ -+static struct xt_flowoffload_hook * -+flow_offload_lookup_hook(struct xt_flowoffload_table *table, -+ struct net_device *dev) -+{ -+ struct xt_flowoffload_hook *hook; -+ -+ hlist_for_each_entry(hook, &table->hooks, list) { -+ if (hook->ops.dev == dev) -+ return hook; -+ } -+ -+ return NULL; -+} -+ -+static void -+xt_flowoffload_check_device(struct xt_flowoffload_table *table, -+ struct net_device *dev) -+{ -+ struct xt_flowoffload_hook *hook; -+ -+ if (!dev) -+ return; -+ -+ spin_lock_bh(&hooks_lock); -+ hook = flow_offload_lookup_hook(table, dev); -+ if (hook) -+ hook->used = true; -+ else -+ xt_flowoffload_create_hook(table, dev); -+ spin_unlock_bh(&hooks_lock); -+} -+ -+static void -+xt_flowoffload_register_hooks(struct xt_flowoffload_table *table) -+{ -+ struct xt_flowoffload_hook *hook; -+ -+restart: -+ hlist_for_each_entry(hook, &table->hooks, list) { -+ if (hook->registered) -+ continue; -+ -+ hook->registered = true; -+ hook->net = dev_net(hook->ops.dev); -+ spin_unlock_bh(&hooks_lock); -+ nf_register_net_hook(hook->net, &hook->ops); -+ if (table->ft.flags & NF_FLOWTABLE_HW_OFFLOAD) -+ table->ft.type->setup(&table->ft, hook->ops.dev, -+ FLOW_BLOCK_BIND); -+ spin_lock_bh(&hooks_lock); -+ goto restart; -+ } -+ -+} -+ -+static bool -+xt_flowoffload_cleanup_hooks(struct xt_flowoffload_table *table) -+{ -+ struct xt_flowoffload_hook *hook; -+ bool active = false; -+ -+restart: -+ spin_lock_bh(&hooks_lock); -+ hlist_for_each_entry(hook, &table->hooks, list) { -+ if (hook->used || !hook->registered) { -+ active = true; -+ continue; -+ } -+ -+ hlist_del(&hook->list); -+ spin_unlock_bh(&hooks_lock); -+ if (table->ft.flags & NF_FLOWTABLE_HW_OFFLOAD) -+ table->ft.type->setup(&table->ft, hook->ops.dev, -+ FLOW_BLOCK_UNBIND); -+ nf_unregister_net_hook(hook->net, &hook->ops); -+ kfree(hook); -+ goto restart; -+ } -+ spin_unlock_bh(&hooks_lock); -+ -+ return active; -+} -+ -+static void -+xt_flowoffload_check_hook(struct flow_offload *flow, void *data) -+{ -+ struct xt_flowoffload_table *table = data; -+ struct flow_offload_tuple *tuple0 = &flow->tuplehash[0].tuple; -+ struct flow_offload_tuple *tuple1 = &flow->tuplehash[1].tuple; -+ struct xt_flowoffload_hook *hook; -+ -+ spin_lock_bh(&hooks_lock); -+ hlist_for_each_entry(hook, &table->hooks, list) { -+ if (hook->ops.dev->ifindex != tuple0->iifidx && -+ hook->ops.dev->ifindex != tuple1->iifidx) -+ continue; -+ -+ hook->used = true; -+ } -+ spin_unlock_bh(&hooks_lock); -+} -+ -+static void -+xt_flowoffload_hook_work(struct work_struct *work) -+{ -+ struct xt_flowoffload_table *table; -+ struct xt_flowoffload_hook *hook; -+ int err; -+ -+ table = container_of(work, struct xt_flowoffload_table, work.work); -+ -+ spin_lock_bh(&hooks_lock); -+ xt_flowoffload_register_hooks(table); -+ hlist_for_each_entry(hook, &table->hooks, list) -+ hook->used = false; -+ spin_unlock_bh(&hooks_lock); -+ -+ err = nf_flow_table_iterate(&table->ft, xt_flowoffload_check_hook, -+ table); -+ if (err && err != -EAGAIN) -+ goto out; -+ -+ if (!xt_flowoffload_cleanup_hooks(table)) -+ return; -+ -+out: -+ queue_delayed_work(system_power_efficient_wq, &table->work, HZ); -+} -+ -+static bool -+xt_flowoffload_skip(struct sk_buff *skb, int family) -+{ -+ if (skb_sec_path(skb)) -+ return true; -+ -+ if (family == NFPROTO_IPV4) { -+ const struct ip_options *opt = &(IPCB(skb)->opt); -+ -+ if (unlikely(opt->optlen)) -+ return true; -+ } -+ -+ return false; -+} -+ -+static enum flow_offload_xmit_type nf_xmit_type(struct dst_entry *dst) -+{ -+ if (dst_xfrm(dst)) -+ return FLOW_OFFLOAD_XMIT_XFRM; -+ -+ return FLOW_OFFLOAD_XMIT_NEIGH; -+} -+ -+static void nf_default_forward_path(struct nf_flow_route *route, -+ struct dst_entry *dst_cache, -+ enum ip_conntrack_dir dir, -+ struct net_device **dev) -+{ -+ dev[!dir] = dst_cache->dev; -+ route->tuple[!dir].in.ifindex = dst_cache->dev->ifindex; -+ route->tuple[dir].dst = dst_cache; -+ route->tuple[dir].xmit_type = nf_xmit_type(dst_cache); -+} -+ -+static bool nf_is_valid_ether_device(const struct net_device *dev) -+{ -+ if (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER || -+ dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr)) -+ return false; -+ -+ return true; -+} -+ -+static void nf_dev_path_info(const struct net_device_path_stack *stack, -+ struct nf_forward_info *info, -+ unsigned char *ha) -+{ -+ const struct net_device_path *path; -+ int i; -+ -+ memcpy(info->h_dest, ha, ETH_ALEN); -+ -+ for (i = 0; i < stack->num_paths; i++) { -+ path = &stack->path[i]; -+ switch (path->type) { -+ case DEV_PATH_ETHERNET: -+ case DEV_PATH_DSA: -+ case DEV_PATH_VLAN: -+ case DEV_PATH_PPPOE: -+ info->indev = path->dev; -+ if (is_zero_ether_addr(info->h_source)) -+ memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN); -+ -+ if (path->type == DEV_PATH_ETHERNET) -+ break; -+ if (path->type == DEV_PATH_DSA) { -+ i = stack->num_paths; -+ break; -+ } -+ -+ /* DEV_PATH_VLAN and DEV_PATH_PPPOE */ -+ if (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) { -+ info->indev = NULL; -+ break; -+ } -+ if (!info->outdev) -+ info->outdev = path->dev; -+ info->encap[info->num_encaps].id = path->encap.id; -+ info->encap[info->num_encaps].proto = path->encap.proto; -+ info->num_encaps++; -+ if (path->type == DEV_PATH_PPPOE) -+ memcpy(info->h_dest, path->encap.h_dest, ETH_ALEN); -+ break; -+ case DEV_PATH_BRIDGE: -+ if (is_zero_ether_addr(info->h_source)) -+ memcpy(info->h_source, path->dev->dev_addr, ETH_ALEN); -+ -+ switch (path->bridge.vlan_mode) { -+ case DEV_PATH_BR_VLAN_UNTAG_HW: -+ info->ingress_vlans |= BIT(info->num_encaps - 1); -+ break; -+ case DEV_PATH_BR_VLAN_TAG: -+ info->encap[info->num_encaps].id = path->bridge.vlan_id; -+ info->encap[info->num_encaps].proto = path->bridge.vlan_proto; -+ info->num_encaps++; -+ break; -+ case DEV_PATH_BR_VLAN_UNTAG: -+ info->num_encaps--; -+ break; -+ case DEV_PATH_BR_VLAN_KEEP: -+ break; -+ } -+ break; -+ default: -+ info->indev = NULL; -+ break; -+ } -+ } -+ if (!info->outdev) -+ info->outdev = info->indev; -+ -+ info->hw_outdev = info->indev; -+ -+ if (nf_is_valid_ether_device(info->indev)) -+ info->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT; -+} -+ -+static int nf_dev_fill_forward_path(const struct nf_flow_route *route, -+ const struct dst_entry *dst_cache, -+ const struct nf_conn *ct, -+ enum ip_conntrack_dir dir, u8 *ha, -+ struct net_device_path_stack *stack) -+{ -+ const void *daddr = &ct->tuplehash[!dir].tuple.src.u3; -+ struct net_device *dev = dst_cache->dev; -+ struct neighbour *n; -+ u8 nud_state; -+ -+ if (!nf_is_valid_ether_device(dev)) -+ goto out; -+ -+ n = dst_neigh_lookup(dst_cache, daddr); -+ if (!n) -+ return -1; -+ -+ read_lock_bh(&n->lock); -+ nud_state = n->nud_state; -+ ether_addr_copy(ha, n->ha); -+ read_unlock_bh(&n->lock); -+ neigh_release(n); -+ -+ if (!(nud_state & NUD_VALID)) -+ return -1; -+ -+out: -+ return dev_fill_forward_path(dev, ha, stack); -+} -+ -+static void nf_dev_forward_path(struct nf_flow_route *route, -+ const struct nf_conn *ct, -+ enum ip_conntrack_dir dir, -+ struct net_device **devs) -+{ -+ const struct dst_entry *dst = route->tuple[dir].dst; -+ struct net_device_path_stack stack; -+ struct nf_forward_info info = {}; -+ unsigned char ha[ETH_ALEN]; -+ int i; -+ -+ if (nf_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0) -+ nf_dev_path_info(&stack, &info, ha); -+ -+ devs[!dir] = (struct net_device *)info.indev; -+ if (!info.indev) -+ return; -+ -+ route->tuple[!dir].in.ifindex = info.indev->ifindex; -+ for (i = 0; i < info.num_encaps; i++) { -+ route->tuple[!dir].in.encap[i].id = info.encap[i].id; -+ route->tuple[!dir].in.encap[i].proto = info.encap[i].proto; -+ } -+ route->tuple[!dir].in.num_encaps = info.num_encaps; -+ route->tuple[!dir].in.ingress_vlans = info.ingress_vlans; -+ -+ if (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) { -+ memcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN); -+ memcpy(route->tuple[dir].out.h_dest, info.h_dest, ETH_ALEN); -+ route->tuple[dir].out.ifindex = info.outdev->ifindex; -+ route->tuple[dir].out.hw_ifindex = info.hw_outdev->ifindex; -+ route->tuple[dir].xmit_type = info.xmit_type; -+ } -+} -+ -+static int -+xt_flowoffload_route(struct sk_buff *skb, const struct nf_conn *ct, -+ const struct xt_action_param *par, -+ struct nf_flow_route *route, enum ip_conntrack_dir dir, -+ struct net_device **devs) -+{ -+ struct dst_entry *this_dst = skb_dst(skb); -+ struct dst_entry *other_dst = NULL; -+ struct flowi fl; -+ -+ memset(&fl, 0, sizeof(fl)); -+ switch (xt_family(par)) { -+ case NFPROTO_IPV4: -+ fl.u.ip4.daddr = ct->tuplehash[dir].tuple.src.u3.ip; -+ fl.u.ip4.flowi4_oif = xt_in(par)->ifindex; -+ break; -+ case NFPROTO_IPV6: -+ fl.u.ip6.saddr = ct->tuplehash[!dir].tuple.dst.u3.in6; -+ fl.u.ip6.daddr = ct->tuplehash[dir].tuple.src.u3.in6; -+ fl.u.ip6.flowi6_oif = xt_in(par)->ifindex; -+ break; -+ } -+ -+ nf_route(xt_net(par), &other_dst, &fl, false, xt_family(par)); -+ if (!other_dst) -+ return -ENOENT; -+ -+ nf_default_forward_path(route, this_dst, dir, devs); -+ nf_default_forward_path(route, other_dst, !dir, devs); -+ -+ if (route->tuple[dir].xmit_type == FLOW_OFFLOAD_XMIT_NEIGH && -+ route->tuple[!dir].xmit_type == FLOW_OFFLOAD_XMIT_NEIGH) { -+ nf_dev_forward_path(route, ct, dir, devs); -+ nf_dev_forward_path(route, ct, !dir, devs); -+ } -+ -+ return 0; -+} -+ -+static unsigned int -+flowoffload_tg(struct sk_buff *skb, const struct xt_action_param *par) -+{ -+ struct xt_flowoffload_table *table; -+ const struct xt_flowoffload_target_info *info = par->targinfo; -+ struct tcphdr _tcph, *tcph = NULL; -+ enum ip_conntrack_info ctinfo; -+ enum ip_conntrack_dir dir; -+ struct nf_flow_route route = {}; -+ struct flow_offload *flow = NULL; -+ struct net_device *devs[2] = {}; -+ struct nf_conn *ct; -+ struct net *net; -+ -+ if (xt_flowoffload_skip(skb, xt_family(par))) -+ return XT_CONTINUE; -+ -+ ct = nf_ct_get(skb, &ctinfo); -+ if (ct == NULL) -+ return XT_CONTINUE; -+ -+ switch (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum) { -+ case IPPROTO_TCP: -+ if (ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) -+ return XT_CONTINUE; -+ -+ tcph = skb_header_pointer(skb, par->thoff, -+ sizeof(_tcph), &_tcph); -+ if (unlikely(!tcph || tcph->fin || tcph->rst)) -+ return XT_CONTINUE; -+ break; -+ case IPPROTO_UDP: -+ break; -+ default: -+ return XT_CONTINUE; -+ } -+ -+ if (nf_ct_ext_exist(ct, NF_CT_EXT_HELPER) || -+ ct->status & (IPS_SEQ_ADJUST | IPS_NAT_CLASH)) -+ return XT_CONTINUE; -+ -+ if (!nf_ct_is_confirmed(ct)) -+ return XT_CONTINUE; -+ -+ devs[dir] = xt_out(par); -+ devs[!dir] = xt_in(par); -+ -+ if (!devs[dir] || !devs[!dir]) -+ return XT_CONTINUE; -+ -+ if (test_and_set_bit(IPS_OFFLOAD_BIT, &ct->status)) -+ return XT_CONTINUE; -+ -+ dir = CTINFO2DIR(ctinfo); -+ -+ if (xt_flowoffload_route(skb, ct, par, &route, dir, devs) < 0) -+ goto err_flow_route; -+ -+ flow = flow_offload_alloc(ct); -+ if (!flow) -+ goto err_flow_alloc; -+ -+ if (flow_offload_route_init(flow, &route) < 0) -+ goto err_flow_add; -+ -+ if (tcph) { -+ ct->proto.tcp.seen[0].flags |= IP_CT_TCP_FLAG_BE_LIBERAL; -+ ct->proto.tcp.seen[1].flags |= IP_CT_TCP_FLAG_BE_LIBERAL; -+ } -+ -+ table = &flowtable[!!(info->flags & XT_FLOWOFFLOAD_HW)]; -+ -+ net = read_pnet(&table->ft.net); -+ if (!net) -+ write_pnet(&table->ft.net, xt_net(par)); -+ -+ if (flow_offload_add(&table->ft, flow) < 0) -+ goto err_flow_add; -+ -+ xt_flowoffload_check_device(table, devs[0]); -+ xt_flowoffload_check_device(table, devs[1]); -+ -+ dst_release(route.tuple[!dir].dst); -+ -+ return XT_CONTINUE; -+ -+err_flow_add: -+ flow_offload_free(flow); -+err_flow_alloc: -+ dst_release(route.tuple[!dir].dst); -+err_flow_route: -+ clear_bit(IPS_OFFLOAD_BIT, &ct->status); -+ -+ return XT_CONTINUE; -+} -+ -+static int flowoffload_chk(const struct xt_tgchk_param *par) -+{ -+ struct xt_flowoffload_target_info *info = par->targinfo; -+ -+ if (info->flags & ~XT_FLOWOFFLOAD_MASK) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static struct xt_target offload_tg_reg __read_mostly = { -+ .family = NFPROTO_UNSPEC, -+ .name = "FLOWOFFLOAD", -+ .revision = 0, -+ .targetsize = sizeof(struct xt_flowoffload_target_info), -+ .usersize = sizeof(struct xt_flowoffload_target_info), -+ .checkentry = flowoffload_chk, -+ .target = flowoffload_tg, -+ .me = THIS_MODULE, -+}; -+ -+static int flow_offload_netdev_event(struct notifier_block *this, -+ unsigned long event, void *ptr) -+{ -+ struct xt_flowoffload_hook *hook0, *hook1; -+ struct net_device *dev = netdev_notifier_info_to_dev(ptr); -+ -+ if (event != NETDEV_UNREGISTER) -+ return NOTIFY_DONE; -+ -+ spin_lock_bh(&hooks_lock); -+ hook0 = flow_offload_lookup_hook(&flowtable[0], dev); -+ if (hook0) -+ hlist_del(&hook0->list); -+ -+ hook1 = flow_offload_lookup_hook(&flowtable[1], dev); -+ if (hook1) -+ hlist_del(&hook1->list); -+ spin_unlock_bh(&hooks_lock); -+ -+ if (hook0) { -+ nf_unregister_net_hook(hook0->net, &hook0->ops); -+ kfree(hook0); -+ } -+ -+ if (hook1) { -+ nf_unregister_net_hook(hook1->net, &hook1->ops); -+ kfree(hook1); -+ } -+ -+ nf_flow_table_cleanup(dev); -+ -+ return NOTIFY_DONE; -+} -+ -+static struct notifier_block flow_offload_netdev_notifier = { -+ .notifier_call = flow_offload_netdev_event, -+}; -+ -+static int nf_flow_rule_route_inet(struct net *net, -+ const struct flow_offload *flow, -+ enum flow_offload_tuple_dir dir, -+ struct nf_flow_rule *flow_rule) -+{ -+ const struct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple; -+ int err; -+ -+ switch (flow_tuple->l3proto) { -+ case NFPROTO_IPV4: -+ err = nf_flow_rule_route_ipv4(net, flow, dir, flow_rule); -+ break; -+ case NFPROTO_IPV6: -+ err = nf_flow_rule_route_ipv6(net, flow, dir, flow_rule); -+ break; -+ default: -+ err = -1; -+ break; -+ } -+ -+ return err; -+} -+ -+static struct nf_flowtable_type flowtable_inet = { -+ .family = NFPROTO_INET, -+ .init = nf_flow_table_init, -+ .setup = nf_flow_table_offload_setup, -+ .action = nf_flow_rule_route_inet, -+ .free = nf_flow_table_free, -+ .hook = xt_flowoffload_net_hook, -+ .owner = THIS_MODULE, -+}; -+ -+static int init_flowtable(struct xt_flowoffload_table *tbl) -+{ -+ INIT_DELAYED_WORK(&tbl->work, xt_flowoffload_hook_work); -+ tbl->ft.type = &flowtable_inet; -+ -+ return nf_flow_table_init(&tbl->ft); -+} -+ -+static int __init xt_flowoffload_tg_init(void) -+{ -+ int ret; -+ -+ register_netdevice_notifier(&flow_offload_netdev_notifier); -+ -+ ret = init_flowtable(&flowtable[0]); -+ if (ret) -+ return ret; -+ -+ ret = init_flowtable(&flowtable[1]); -+ if (ret) -+ goto cleanup; -+ -+ flowtable[1].ft.flags = NF_FLOWTABLE_HW_OFFLOAD; -+ -+ ret = xt_register_target(&offload_tg_reg); -+ if (ret) -+ goto cleanup2; -+ -+ return 0; -+ -+cleanup2: -+ nf_flow_table_free(&flowtable[1].ft); -+cleanup: -+ nf_flow_table_free(&flowtable[0].ft); -+ return ret; -+} -+ -+static void __exit xt_flowoffload_tg_exit(void) -+{ -+ xt_unregister_target(&offload_tg_reg); -+ unregister_netdevice_notifier(&flow_offload_netdev_notifier); -+ nf_flow_table_free(&flowtable[0].ft); -+ nf_flow_table_free(&flowtable[1].ft); -+} -+ -+MODULE_LICENSE("GPL"); -+module_init(xt_flowoffload_tg_init); -+module_exit(xt_flowoffload_tg_exit); ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -7,7 +7,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -380,8 +379,7 @@ flow_offload_lookup(struct nf_flowtable - } - EXPORT_SYMBOL_GPL(flow_offload_lookup); - --static int --nf_flow_table_iterate(struct nf_flowtable *flow_table, -+int nf_flow_table_iterate(struct nf_flowtable *flow_table, - void (*iter)(struct flow_offload *flow, void *data), - void *data) - { -@@ -413,6 +411,7 @@ nf_flow_table_iterate(struct nf_flowtabl - - return err; - } -+EXPORT_SYMBOL_GPL(nf_flow_table_iterate); - - static void nf_flow_offload_gc_step(struct flow_offload *flow, void *data) - { ---- /dev/null -+++ b/include/uapi/linux/netfilter/xt_FLOWOFFLOAD.h -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -+#ifndef _XT_FLOWOFFLOAD_H -+#define _XT_FLOWOFFLOAD_H -+ -+#include -+ -+enum { -+ XT_FLOWOFFLOAD_HW = 1 << 0, -+ -+ XT_FLOWOFFLOAD_MASK = XT_FLOWOFFLOAD_HW -+}; -+ -+struct xt_flowoffload_target_info { -+ __u32 flags; -+}; -+ -+#endif /* _XT_FLOWOFFLOAD_H */ ---- a/include/net/netfilter/nf_flow_table.h -+++ b/include/net/netfilter/nf_flow_table.h -@@ -271,6 +271,10 @@ void nf_flow_table_free(struct nf_flowta - - void flow_offload_teardown(struct flow_offload *flow); - -+int nf_flow_table_iterate(struct nf_flowtable *flow_table, -+ void (*iter)(struct flow_offload *flow, void *data), -+ void *data); -+ - void nf_flow_snat_port(const struct flow_offload *flow, - struct sk_buff *skb, unsigned int thoff, - u8 protocol, enum flow_offload_tuple_dir dir); diff --git a/target/linux/generic/hack-5.10/651-wireless_mesh_header.patch b/target/linux/generic/hack-5.10/651-wireless_mesh_header.patch deleted file mode 100644 index 0639ad4e48..0000000000 --- a/target/linux/generic/hack-5.10/651-wireless_mesh_header.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 6d3bc769657b0ee7c7506dad9911111c4226a7ea Mon Sep 17 00:00:00 2001 -From: Imre Kaloz -Date: Fri, 7 Jul 2017 17:21:05 +0200 -Subject: mac80211: increase wireless mesh header size - -lede-commit 3d4466cfd8f75f717efdb1f96fdde3c70d865fc1 -Signed-off-by: Imre Kaloz ---- - include/linux/netdevice.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -144,8 +144,8 @@ static inline bool dev_xmit_complete(int - - #if defined(CONFIG_HYPERV_NET) - # define LL_MAX_HEADER 128 --#elif defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) --# if defined(CONFIG_MAC80211_MESH) -+#elif defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) || 1 -+# if defined(CONFIG_MAC80211_MESH) || 1 - # define LL_MAX_HEADER 128 - # else - # define LL_MAX_HEADER 96 diff --git a/target/linux/generic/hack-5.10/660-fq_codel_defaults.patch b/target/linux/generic/hack-5.10/660-fq_codel_defaults.patch deleted file mode 100644 index a57a045f4a..0000000000 --- a/target/linux/generic/hack-5.10/660-fq_codel_defaults.patch +++ /dev/null @@ -1,27 +0,0 @@ -From a6ccb238939b25851474a279b20367fd24a0e816 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Fri, 7 Jul 2017 17:21:53 +0200 -Subject: hack: net: fq_codel: tune defaults for small devices - -Assume that x86_64 devices always have a big memory and do not need this -optimization compared to devices with only 32 MB or 64 MB RAM. - -Signed-off-by: Felix Fietkau ---- - net/sched/sch_fq_codel.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/net/sched/sch_fq_codel.c -+++ b/net/sched/sch_fq_codel.c -@@ -467,7 +467,11 @@ static int fq_codel_init(struct Qdisc *s - - sch->limit = 10*1024; - q->flows_cnt = 1024; -+#ifdef CONFIG_X86_64 - q->memory_limit = 32 << 20; /* 32 MBytes */ -+#else -+ q->memory_limit = 4 << 20; /* 4 MBytes */ -+#endif - q->drop_batch_size = 64; - q->quantum = psched_mtu(qdisc_dev(sch)); - INIT_LIST_HEAD(&q->new_flows); diff --git a/target/linux/generic/hack-5.10/661-kernel-ct-size-the-hashtable-more-adequately.patch b/target/linux/generic/hack-5.10/661-kernel-ct-size-the-hashtable-more-adequately.patch deleted file mode 100644 index dd67c76b13..0000000000 --- a/target/linux/generic/hack-5.10/661-kernel-ct-size-the-hashtable-more-adequately.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 804fbb3f2ec9283f7b778e057a68bfff440a0be6 Mon Sep 17 00:00:00 2001 -From: Rui Salvaterra -Date: Wed, 30 Mar 2022 22:51:55 +0100 -Subject: [PATCH] kernel: ct: size the hashtable more adequately - -To set the default size of the connection tracking hash table, a divider of -16384 becomes inadequate for a router handling lots of connections. Divide by -2048 instead, making the default size scale better with the available RAM. - -Signed-off-by: Rui Salvaterra ---- - net/netfilter/nf_conntrack_core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/net/netfilter/nf_conntrack_core.c -+++ b/net/netfilter/nf_conntrack_core.c -@@ -2576,7 +2576,7 @@ int nf_conntrack_init_start(void) - - if (!nf_conntrack_htable_size) { - nf_conntrack_htable_size -- = (((nr_pages << PAGE_SHIFT) / 16384) -+ = (((nr_pages << PAGE_SHIFT) / 2048) - / sizeof(struct hlist_head)); - if (BITS_PER_LONG >= 64 && - nr_pages > (4 * (1024 * 1024 * 1024 / PAGE_SIZE))) diff --git a/target/linux/generic/hack-5.10/700-swconfig_switch_drivers.patch b/target/linux/generic/hack-5.10/700-swconfig_switch_drivers.patch deleted file mode 100644 index 48be440025..0000000000 --- a/target/linux/generic/hack-5.10/700-swconfig_switch_drivers.patch +++ /dev/null @@ -1,131 +0,0 @@ -From 36e516290611e613aa92996cb4339561452695b4 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Fri, 7 Jul 2017 17:24:23 +0200 -Subject: net: swconfig: adds openwrt switch layer - -Signed-off-by: Felix Fietkau ---- - drivers/net/phy/Kconfig | 83 +++++++++++++++++++++++++++++++++++++++++++++++ - drivers/net/phy/Makefile | 15 +++++++++ - include/uapi/linux/Kbuild | 1 + - 3 files changed, 99 insertions(+) - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -61,6 +61,80 @@ config SFP - depends on HWMON || HWMON=n - select MDIO_I2C - -+comment "Switch configuration API + drivers" -+ -+config SWCONFIG -+ tristate "Switch configuration API" -+ help -+ Switch configuration API using netlink. This allows -+ you to configure the VLAN features of certain switches. -+ -+config SWCONFIG_LEDS -+ bool "Switch LED trigger support" -+ depends on (SWCONFIG && LEDS_TRIGGERS) -+ -+config ADM6996_PHY -+ tristate "Driver for ADM6996 switches" -+ select SWCONFIG -+ help -+ Currently supports the ADM6996FC and ADM6996M switches. -+ Support for FC is very limited. -+ -+config AR8216_PHY -+ tristate "Driver for Atheros AR8216/8327 switches" -+ select SWCONFIG -+ select ETHERNET_PACKET_MANGLE -+ -+config AR8216_PHY_LEDS -+ bool "Atheros AR8216 switch LED support" -+ depends on (AR8216_PHY && LEDS_CLASS) -+ -+source "drivers/net/phy/b53/Kconfig" -+ -+config IP17XX_PHY -+ tristate "Driver for IC+ IP17xx switches" -+ select SWCONFIG -+ -+config PSB6970_PHY -+ tristate "Lantiq XWAY Tantos (PSB6970) Ethernet switch" -+ select SWCONFIG -+ -+config RTL8306_PHY -+ tristate "Driver for Realtek RTL8306S switches" -+ select SWCONFIG -+ -+config RTL8366_SMI -+ tristate "Driver for the RTL8366 SMI interface" -+ depends on GPIOLIB -+ help -+ This module implements the SMI interface protocol which is used -+ by some RTL8366 ethernet switch devices via the generic GPIO API. -+ -+if RTL8366_SMI -+ -+config RTL8366_SMI_DEBUG_FS -+ bool "RTL8366 SMI interface debugfs support" -+ depends on DEBUG_FS -+ default n -+ -+config RTL8366S_PHY -+ tristate "Driver for the Realtek RTL8366S switch" -+ select SWCONFIG -+ -+config RTL8366RB_PHY -+ tristate "Driver for the Realtek RTL8366RB switch" -+ select SWCONFIG -+ -+config RTL8367_PHY -+ tristate "Driver for the Realtek RTL8367R/M switches" -+ select SWCONFIG -+ -+config RTL8367B_PHY -+ tristate "Driver fot the Realtek RTL8367R-VB switch" -+ select SWCONFIG -+ -+endif # RTL8366_SMI -+ - comment "MII PHY device drivers" - - config AMD_PHY ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -24,6 +24,21 @@ libphy-$(CONFIG_LED_TRIGGER_PHY) += phy_ - obj-$(CONFIG_PHYLINK) += phylink.o - obj-$(CONFIG_PHYLIB) += libphy.o - -+obj-$(CONFIG_SWCONFIG) += swconfig.o -+obj-$(CONFIG_ADM6996_PHY) += adm6996.o -+obj-$(CONFIG_AR8216_PHY) += ar8xxx.o -+ar8xxx-y += ar8216.o -+ar8xxx-y += ar8327.o -+obj-$(CONFIG_SWCONFIG_B53) += b53/ -+obj-$(CONFIG_IP17XX_PHY) += ip17xx.o -+obj-$(CONFIG_PSB6970_PHY) += psb6970.o -+obj-$(CONFIG_RTL8306_PHY) += rtl8306.o -+obj-$(CONFIG_RTL8366_SMI) += rtl8366_smi.o -+obj-$(CONFIG_RTL8366S_PHY) += rtl8366s.o -+obj-$(CONFIG_RTL8366RB_PHY) += rtl8366rb.o -+obj-$(CONFIG_RTL8367_PHY) += rtl8367.o -+obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o -+ - obj-$(CONFIG_NETWORK_PHY_TIMESTAMPING) += mii_timestamper.o - - obj-$(CONFIG_SFP) += sfp.o ---- a/include/linux/platform_data/b53.h -+++ b/include/linux/platform_data/b53.h -@@ -29,6 +29,9 @@ struct b53_platform_data { - u32 chip_id; - u16 enabled_ports; - -+ /* allow to specify an ethX alias */ -+ const char *alias; -+ - /* only used by MMAP'd driver */ - unsigned big_endian:1; - void __iomem *regs; diff --git a/target/linux/generic/hack-5.10/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch b/target/linux/generic/hack-5.10/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch deleted file mode 100644 index ef4635065d..0000000000 --- a/target/linux/generic/hack-5.10/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: DENG Qingfang -Subject: DSA: roaming fix for Marvell mv88e6xxx - -Marvell mv88e6xxx switch series cannot perform MAC learning from -CPU-injected (FROM_CPU) DSA frames, which results in 2 issues. -- excessive flooding, due to the fact that DSA treats those addresses -as unknown -- the risk of stale routes, which can lead to temporary packet loss - -Backport those patch series from netdev mailing list, which solve these -issues by adding and clearing static entries to the switch's FDB. - -Add a hack patch to set default VID to 1 in port_fdb_{add,del}. Otherwise -the static entries will be added to the switch's private FDB if VLAN -filtering disabled, which will not work. - -The switch may generate an "ATU violation" warning when a client moves -from the CPU port to a switch port because the static ATU entry added by -DSA core still points to the CPU port. DSA core will then clear the static -entry so it is not fatal. Disable the warning so it will not confuse users. - -Link: https://lore.kernel.org/netdev/20210106095136.224739-1-olteanv@gmail.com/ -Link: https://lore.kernel.org/netdev/20210116012515.3152-1-tobias@waldekranz.com/ -Ref: https://gitlab.nic.cz/turris/turris-build/-/issues/165 -Submitted-by: DENG Qingfang ---- - drivers/net/dsa/mv88e6xxx/chip.c | 3 +++ - 3 files changed, 3 insertions(+) - ---- a/drivers/net/dsa/mv88e6xxx/chip.c -+++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -2714,6 +2714,9 @@ static int mv88e6xxx_setup_port(struct m - if (dsa_is_cpu_port(ds, port)) - reg = 0; - -+ /* Disable ATU member violation interrupt */ -+ reg |= MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG; -+ - err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, - reg); - if (err) diff --git a/target/linux/generic/hack-5.10/720-net-phy-add-aqr-phys.patch b/target/linux/generic/hack-5.10/720-net-phy-add-aqr-phys.patch deleted file mode 100644 index e90447e0cb..0000000000 --- a/target/linux/generic/hack-5.10/720-net-phy-add-aqr-phys.patch +++ /dev/null @@ -1,142 +0,0 @@ -From: Birger Koblitz -Date: Sun, 5 Sep 2021 15:13:10 +0200 -Subject: [PATCH] kernel: Add AQR113C and AQR813 support - -This hack adds support for the Aquantia 4th generation, 10GBit -PHYs AQR113C and AQR813. - -Signed-off-by: Birger Koblitz - ---- a/drivers/net/phy/aquantia_main.c -+++ b/drivers/net/phy/aquantia_main.c -@@ -20,8 +20,10 @@ - #define PHY_ID_AQR105 0x03a1b4a2 - #define PHY_ID_AQR106 0x03a1b4d0 - #define PHY_ID_AQR107 0x03a1b4e0 -+#define PHY_ID_AQR113C 0x31c31c12 - #define PHY_ID_AQCS109 0x03a1b5c2 - #define PHY_ID_AQR405 0x03a1b4b0 -+#define PHY_ID_AQR813 0x31c31cb2 - - #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 - #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) -@@ -352,6 +354,49 @@ static int aqr107_read_rate(struct phy_d - return 0; - } - -+static int aqr113c_read_status(struct phy_device *phydev) -+{ -+ int val, ret; -+ -+ ret = aqr_read_status(phydev); -+ if (ret) -+ return ret; -+ -+ if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) -+ return 0; -+ -+ // On AQR113C, the speed returned by aqr_read_status is wrong -+ aqr107_read_rate(phydev); -+ -+ val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); -+ if (val < 0) -+ return val; -+ -+ switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: -+ phydev->interface = PHY_INTERFACE_MODE_10GKR; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: -+ phydev->interface = PHY_INTERFACE_MODE_10GBASER; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: -+ phydev->interface = PHY_INTERFACE_MODE_USXGMII; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: -+ phydev->interface = PHY_INTERFACE_MODE_SGMII; -+ break; -+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: -+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -+ break; -+ default: -+ phydev->interface = PHY_INTERFACE_MODE_NA; -+ break; -+ } -+ -+ /* Read downshifted rate from vendor register */ -+ return aqr107_read_rate(phydev); -+} -+ - static int aqr107_read_status(struct phy_device *phydev) - { - int val, ret; -@@ -482,7 +527,7 @@ static void aqr107_chip_info(struct phy_ - build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); - prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); - -- phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", -+ phydev_info(phydev, "FW %u.%u, Build %u, Provisioning %u\n", - fw_major, fw_minor, build_id, prov_id); - } - -@@ -690,6 +735,24 @@ static struct phy_driver aqr_driver[] = - .link_change_notify = aqr107_link_change_notify, - }, - { -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), -+ .name = "Aquantia AQR113C", -+ .probe = aqr107_probe, -+ .config_init = aqr107_config_init, -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .ack_interrupt = aqr_ack_interrupt, -+ .read_status = aqr113c_read_status, -+ .get_tunable = aqr107_get_tunable, -+ .set_tunable = aqr107_set_tunable, -+ .suspend = aqr107_suspend, -+ .resume = aqr107_resume, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+ .link_change_notify = aqr107_link_change_notify, -+}, -+{ - PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), - .name = "Aquantia AQCS109", - .probe = aqr107_probe, -@@ -715,6 +778,24 @@ static struct phy_driver aqr_driver[] = - .ack_interrupt = aqr_ack_interrupt, - .read_status = aqr_read_status, - }, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR813), -+ .name = "Aquantia AQR813", -+ .probe = aqr107_probe, -+ .config_init = aqr107_config_init, -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .ack_interrupt = aqr_ack_interrupt, -+ .read_status = aqr113c_read_status, -+ .get_tunable = aqr107_get_tunable, -+ .set_tunable = aqr107_set_tunable, -+ .suspend = aqr107_suspend, -+ .resume = aqr107_resume, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+ .link_change_notify = aqr107_link_change_notify, -+}, - }; - - module_phy_driver(aqr_driver); -@@ -725,8 +806,10 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, - { } - }; - diff --git a/target/linux/generic/hack-5.10/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-5.10/721-net-add-packet-mangeling.patch deleted file mode 100644 index fed3848a9c..0000000000 --- a/target/linux/generic/hack-5.10/721-net-add-packet-mangeling.patch +++ /dev/null @@ -1,167 +0,0 @@ -From ffe387740bbe88dd88bbe04d6375902708003d6e Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Fri, 7 Jul 2017 17:25:00 +0200 -Subject: net: add packet mangeling - -ar8216 switches have a hardware bug, which renders normal 802.1q support -unusable. Packet mangling is required to fix up the vlan for incoming -packets. - -Signed-off-by: Felix Fietkau ---- - include/linux/netdevice.h | 11 +++++++++++ - include/linux/skbuff.h | 14 ++++---------- - net/Kconfig | 6 ++++++ - net/core/dev.c | 20 +++++++++++++++----- - net/core/skbuff.c | 17 +++++++++++++++++ - net/ethernet/eth.c | 6 ++++++ - 6 files changed, 59 insertions(+), 15 deletions(-) - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -1648,6 +1648,7 @@ enum netdev_priv_flags { - IFF_FAILOVER_SLAVE = 1<<28, - IFF_L3MDEV_RX_HANDLER = 1<<29, - IFF_LIVE_RENAME_OK = 1<<30, -+ IFF_NO_IP_ALIGN = 1<<31, - }; - - #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN -@@ -1680,6 +1681,7 @@ enum netdev_priv_flags { - #define IFF_FAILOVER_SLAVE IFF_FAILOVER_SLAVE - #define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER - #define IFF_LIVE_RENAME_OK IFF_LIVE_RENAME_OK -+#define IFF_NO_IP_ALIGN IFF_NO_IP_ALIGN - - /* Specifies the type of the struct net_device::ml_priv pointer */ - enum netdev_ml_priv_type { -@@ -2020,6 +2022,11 @@ struct net_device { - const struct tlsdev_ops *tlsdev_ops; - #endif - -+#ifdef CONFIG_ETHERNET_PACKET_MANGLE -+ void (*eth_mangle_rx)(struct net_device *dev, struct sk_buff *skb); -+ struct sk_buff *(*eth_mangle_tx)(struct net_device *dev, struct sk_buff *skb); -+#endif -+ - const struct header_ops *header_ops; - - unsigned int flags; -@@ -2110,6 +2117,10 @@ struct net_device { - struct mpls_dev __rcu *mpls_ptr; - #endif - -+#ifdef CONFIG_ETHERNET_PACKET_MANGLE -+ void *phy_ptr; /* PHY device specific data */ -+#endif -+ - /* - * Cache lines mostly used on receive path (including eth_type_trans()) - */ ---- a/include/linux/skbuff.h -+++ b/include/linux/skbuff.h -@@ -2728,6 +2728,10 @@ static inline int pskb_trim(struct sk_bu - return (len < skb->len) ? __pskb_trim(skb, len) : 0; - } - -+extern struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, -+ unsigned int length, gfp_t gfp); -+ -+ - /** - * pskb_trim_unique - remove end from a paged unique (not cloned) buffer - * @skb: buffer to alter -@@ -2859,16 +2863,6 @@ static inline struct sk_buff *dev_alloc_ - } - - --static inline struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, -- unsigned int length, gfp_t gfp) --{ -- struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); -- -- if (NET_IP_ALIGN && skb) -- skb_reserve(skb, NET_IP_ALIGN); -- return skb; --} -- - static inline struct sk_buff *netdev_alloc_skb_ip_align(struct net_device *dev, - unsigned int length) - { ---- a/net/Kconfig -+++ b/net/Kconfig -@@ -26,6 +26,12 @@ menuconfig NET - - if NET - -+config ETHERNET_PACKET_MANGLE -+ bool -+ help -+ This option can be selected by phy drivers that need to mangle -+ packets going in or out of an ethernet device. -+ - config WANT_COMPAT_NETLINK_MESSAGES - bool - help ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -3656,6 +3656,11 @@ static int xmit_one(struct sk_buff *skb, - if (dev_nit_active(dev)) - dev_queue_xmit_nit(skb, dev); - -+#ifdef CONFIG_ETHERNET_PACKET_MANGLE -+ if (dev->eth_mangle_tx && !(skb = dev->eth_mangle_tx(dev, skb))) -+ return NETDEV_TX_OK; -+#endif -+ - len = skb->len; - PRANDOM_ADD_NOISE(skb, dev, txq, len + jiffies); - trace_net_dev_start_xmit(skb, dev); ---- a/net/core/skbuff.c -+++ b/net/core/skbuff.c -@@ -60,6 +60,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -553,6 +554,22 @@ skb_fail: - } - EXPORT_SYMBOL(__napi_alloc_skb); - -+struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev, -+ unsigned int length, gfp_t gfp) -+{ -+ struct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp); -+ -+#ifdef CONFIG_ETHERNET_PACKET_MANGLE -+ if (dev && (dev->priv_flags & IFF_NO_IP_ALIGN)) -+ return skb; -+#endif -+ -+ if (NET_IP_ALIGN && skb) -+ skb_reserve(skb, NET_IP_ALIGN); -+ return skb; -+} -+EXPORT_SYMBOL(__netdev_alloc_skb_ip_align); -+ - void skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page, int off, - int size, unsigned int truesize) - { ---- a/net/ethernet/eth.c -+++ b/net/ethernet/eth.c -@@ -171,6 +171,12 @@ __be16 eth_type_trans(struct sk_buff *sk - const struct ethhdr *eth; - - skb->dev = dev; -+ -+#ifdef CONFIG_ETHERNET_PACKET_MANGLE -+ if (dev->eth_mangle_rx) -+ dev->eth_mangle_rx(dev, skb); -+#endif -+ - skb_reset_mac_header(skb); - - eth = (struct ethhdr *)skb->data; diff --git a/target/linux/generic/hack-5.10/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch b/target/linux/generic/hack-5.10/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch deleted file mode 100644 index 42bf8951d6..0000000000 --- a/target/linux/generic/hack-5.10/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch +++ /dev/null @@ -1,154 +0,0 @@ -From 5f62951fba63a9f9cfff564209426bdea5fcc371 Mon Sep 17 00:00:00 2001 -From: Alex Marginean -Date: Tue, 27 Aug 2019 15:16:56 +0300 -Subject: [PATCH] drivers: net: phy: aquantia: enable AQR112 and AQR412 - -Adds support for AQR112 and AQR412 which is mostly based on existing code -with the addition of code configuring the protocol on system side. -This allows changing the system side protocol without having to deploy a -different firmware on the PHY. - -Signed-off-by: Alex Marginean ---- - drivers/net/phy/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 88 insertions(+) - ---- a/drivers/net/phy/aquantia_main.c -+++ b/drivers/net/phy/aquantia_main.c -@@ -20,9 +20,11 @@ - #define PHY_ID_AQR105 0x03a1b4a2 - #define PHY_ID_AQR106 0x03a1b4d0 - #define PHY_ID_AQR107 0x03a1b4e0 -+#define PHY_ID_AQR112 0x03a1b662 - #define PHY_ID_AQR113C 0x31c31c12 - #define PHY_ID_AQCS109 0x03a1b5c2 - #define PHY_ID_AQR405 0x03a1b4b0 -+#define PHY_ID_AQR412 0x03a1b712 - #define PHY_ID_AQR813 0x31c31cb2 - - #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 -@@ -134,6 +136,29 @@ - #define AQR107_OP_IN_PROG_SLEEP 1000 - #define AQR107_OP_IN_PROG_TIMEOUT 100000 - -+/* registers in MDIO_MMD_VEND1 region */ -+#define AQUANTIA_VND1_GLOBAL_SC 0x000 -+#define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb) -+ -+/* global start rate, the protocol associated with this speed is used by default -+ * on SI. -+ */ -+#define AQUANTIA_VND1_GSTART_RATE 0x31a -+#define AQUANTIA_VND1_GSTART_RATE_OFF 0 -+#define AQUANTIA_VND1_GSTART_RATE_100M 1 -+#define AQUANTIA_VND1_GSTART_RATE_1G 2 -+#define AQUANTIA_VND1_GSTART_RATE_10G 3 -+#define AQUANTIA_VND1_GSTART_RATE_2_5G 4 -+#define AQUANTIA_VND1_GSTART_RATE_5G 5 -+ -+/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */ -+#define AQUANTIA_VND1_GSYSCFG_BASE 0x31b -+#define AQUANTIA_VND1_GSYSCFG_100M 0 -+#define AQUANTIA_VND1_GSYSCFG_1G 1 -+#define AQUANTIA_VND1_GSYSCFG_2_5G 2 -+#define AQUANTIA_VND1_GSYSCFG_5G 3 -+#define AQUANTIA_VND1_GSYSCFG_10G 4 -+ - struct aqr107_hw_stat { - const char *name; - int reg; -@@ -265,6 +290,51 @@ static int aqr_config_aneg(struct phy_de - return genphy_c45_check_and_restart_aneg(phydev, changed); - } - -+static struct { -+ u16 syscfg; -+ int cnt; -+ u16 start_rate; -+} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = { -+ [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G, -+ AQUANTIA_VND1_GSTART_RATE_1G}, -+ [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, -+ AQUANTIA_VND1_GSTART_RATE_2_5G}, -+ [PHY_INTERFACE_MODE_XGMII] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, -+ AQUANTIA_VND1_GSTART_RATE_10G}, -+ [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G, -+ AQUANTIA_VND1_GSTART_RATE_10G}, -+}; -+ -+/* Sets up protocol on system side before calling aqr_config_aneg */ -+static int aqr_config_aneg_set_prot(struct phy_device *phydev) -+{ -+ int if_type = phydev->interface; -+ int i; -+ -+ if (!aquantia_syscfg[if_type].cnt) -+ return 0; -+ -+ /* set PHY in low power mode so we can configure protocols */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, -+ AQUANTIA_VND1_GLOBAL_SC_LP); -+ mdelay(10); -+ -+ /* set the default rate to enable the SI link */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE, -+ aquantia_syscfg[if_type].start_rate); -+ -+ for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++) -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, -+ AQUANTIA_VND1_GSYSCFG_BASE + i, -+ aquantia_syscfg[if_type].syscfg); -+ -+ /* wake PHY back up */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0); -+ mdelay(10); -+ -+ return aqr_config_aneg(phydev); -+} -+ - static int aqr_config_intr(struct phy_device *phydev) - { - bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; -@@ -796,6 +866,30 @@ static struct phy_driver aqr_driver[] = - .get_stats = aqr107_get_stats, - .link_change_notify = aqr107_link_change_notify, - }, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112), -+ .name = "Aquantia AQR112", -+ .probe = aqr107_probe, -+ .config_aneg = aqr_config_aneg_set_prot, -+ .config_intr = aqr_config_intr, -+ .ack_interrupt = aqr_ack_interrupt, -+ .read_status = aqr107_read_status, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR412), -+ .name = "Aquantia AQR412", -+ .probe = aqr107_probe, -+ .config_aneg = aqr_config_aneg_set_prot, -+ .config_intr = aqr_config_intr, -+ .ack_interrupt = aqr_ack_interrupt, -+ .read_status = aqr107_read_status, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+}, - }; - - module_phy_driver(aqr_driver); -@@ -806,9 +900,11 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, - { } - }; diff --git a/target/linux/generic/hack-5.10/723-net-phy-aquantia-fix-system-side-protocol-mi.patch b/target/linux/generic/hack-5.10/723-net-phy-aquantia-fix-system-side-protocol-mi.patch deleted file mode 100644 index c65f273a8a..0000000000 --- a/target/linux/generic/hack-5.10/723-net-phy-aquantia-fix-system-side-protocol-mi.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 5f008cb22f60da4e10375f22266c1a4e20b1252e Mon Sep 17 00:00:00 2001 -From: Alex Marginean -Date: Fri, 20 Sep 2019 18:22:52 +0300 -Subject: [PATCH] drivers: net: phy: aquantia: fix system side protocol - misconfiguration - -Do not set up protocols for speeds that are not supported by FW. Enabling -these protocols leads to link issues on system side. - -Signed-off-by: Alex Marginean ---- - drivers/net/phy/aquantia_main.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - ---- a/drivers/net/phy/aquantia_main.c -+++ b/drivers/net/phy/aquantia_main.c -@@ -323,10 +323,16 @@ static int aqr_config_aneg_set_prot(stru - phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE, - aquantia_syscfg[if_type].start_rate); - -- for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++) -+ for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++) { -+ u16 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, -+ AQUANTIA_VND1_GSYSCFG_BASE + i); -+ if (!reg) -+ continue; -+ - phy_write_mmd(phydev, MDIO_MMD_VEND1, - AQUANTIA_VND1_GSYSCFG_BASE + i, - aquantia_syscfg[if_type].syscfg); -+ } - - /* wake PHY back up */ - phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0); diff --git a/target/linux/generic/hack-5.10/724-net-phy-aquantia-Add-AQR113-driver-support.patch b/target/linux/generic/hack-5.10/724-net-phy-aquantia-Add-AQR113-driver-support.patch deleted file mode 100644 index 8fd3b018b4..0000000000 --- a/target/linux/generic/hack-5.10/724-net-phy-aquantia-Add-AQR113-driver-support.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 2e677e4ae8f8330f68013163b060d0fda3a43095 Mon Sep 17 00:00:00 2001 -From: "Langer, Thomas" -Date: Fri, 9 Jul 2021 17:36:46 +0200 -Subject: [PATCH] PONRTSYS-8842: aquantia: Add AQR113 driver support - -Add a new entry for AQR113 PHY_ID ---- - drivers/net/phy/aquantia_main.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/net/phy/aquantia_main.c -+++ b/drivers/net/phy/aquantia_main.c -@@ -21,6 +21,7 @@ - #define PHY_ID_AQR106 0x03a1b4d0 - #define PHY_ID_AQR107 0x03a1b4e0 - #define PHY_ID_AQR112 0x03a1b662 -+#define PHY_ID_AQR113 0x31c31c40 - #define PHY_ID_AQR113C 0x31c31c12 - #define PHY_ID_AQCS109 0x03a1b5c2 - #define PHY_ID_AQR405 0x03a1b4b0 -@@ -885,6 +886,14 @@ static struct phy_driver aqr_driver[] = - .get_stats = aqr107_get_stats, - }, - { -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR113), -+ .name = "Aquantia AQR113", -+ .config_aneg = aqr_config_aneg, -+ .config_intr = aqr_config_intr, -+ .ack_interrupt = aqr_ack_interrupt, -+ .read_status = aqr107_read_status, -+}, -+{ - PHY_ID_MATCH_MODEL(PHY_ID_AQR412), - .name = "Aquantia AQR412", - .probe = aqr107_probe, -@@ -907,6 +916,7 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, diff --git a/target/linux/generic/hack-5.10/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-5.10/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch deleted file mode 100644 index f2db552a1e..0000000000 --- a/target/linux/generic/hack-5.10/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 3b92ee7b7899b6beffb2b484c58326e36612a873 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 23 Dec 2021 14:52:56 +0000 -Subject: [PATCH] net: phy: aquantia: add PHY_ID for AQR112R - -As advised by Ian Chang this PHY is used in Puzzle devices. - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/aquantia_main.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/net/phy/aquantia_main.c -+++ b/drivers/net/phy/aquantia_main.c -@@ -21,6 +21,8 @@ - #define PHY_ID_AQR106 0x03a1b4d0 - #define PHY_ID_AQR107 0x03a1b4e0 - #define PHY_ID_AQR112 0x03a1b662 -+#define PHY_ID_AQR112C 0x03a1b790 -+#define PHY_ID_AQR112R 0x31c31d12 - #define PHY_ID_AQR113 0x31c31c40 - #define PHY_ID_AQR113C 0x31c31c12 - #define PHY_ID_AQCS109 0x03a1b5c2 -@@ -886,6 +888,30 @@ static struct phy_driver aqr_driver[] = - .get_stats = aqr107_get_stats, - }, - { -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C), -+ .name = "Aquantia AQR112C", -+ .probe = aqr107_probe, -+ .config_aneg = aqr_config_aneg_set_prot, -+ .config_intr = aqr_config_intr, -+ .ack_interrupt = aqr_ack_interrupt, -+ .read_status = aqr107_read_status, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+}, -+{ -+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R), -+ .name = "Aquantia AQR112R", -+ .probe = aqr107_probe, -+ .config_aneg = aqr_config_aneg_set_prot, -+ .config_intr = aqr_config_intr, -+ .ack_interrupt = aqr_ack_interrupt, -+ .read_status = aqr107_read_status, -+ .get_sset_count = aqr107_get_sset_count, -+ .get_strings = aqr107_get_strings, -+ .get_stats = aqr107_get_stats, -+}, -+{ - PHY_ID_MATCH_MODEL(PHY_ID_AQR113), - .name = "Aquantia AQR113", - .config_aneg = aqr_config_aneg, -@@ -916,6 +942,8 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) }, -+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, - { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, diff --git a/target/linux/generic/hack-5.10/760-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/generic/hack-5.10/760-net-usb-r8152-add-LED-configuration-from-OF.patch deleted file mode 100644 index 51b4d87e6c..0000000000 --- a/target/linux/generic/hack-5.10/760-net-usb-r8152-add-LED-configuration-from-OF.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 82985725e071f2a5735052f18e109a32aeac3a0b Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sun, 26 Jul 2020 02:38:31 +0200 -Subject: [PATCH] net: usb: r8152: add LED configuration from OF - -This adds the ability to configure the LED configuration register using -OF. This way, the correct value for board specific LED configuration can -be determined. - -Signed-off-by: David Bauer ---- - drivers/net/usb/r8152.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -6782,6 +6783,22 @@ static void rtl_tally_reset(struct r8152 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); - } - -+static int r8152_led_configuration(struct r8152 *tp) -+{ -+ u32 led_data; -+ int ret; -+ -+ ret = of_property_read_u32(tp->udev->dev.of_node, "realtek,led-data", -+ &led_data); -+ -+ if (ret) -+ return ret; -+ -+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data); -+ -+ return 0; -+} -+ - static void r8152b_init(struct r8152 *tp) - { - u32 ocp_data; -@@ -6823,6 +6840,8 @@ static void r8152b_init(struct r8152 *tp - ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); - ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); - ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); -+ -+ r8152_led_configuration(tp); - } - - static void r8153_init(struct r8152 *tp) -@@ -6963,6 +6982,8 @@ static void r8153_init(struct r8152 *tp) - tp->coalesce = COALESCE_SLOW; - break; - } -+ -+ r8152_led_configuration(tp); - } - - static void r8153b_init(struct r8152 *tp) -@@ -7045,6 +7066,8 @@ static void r8153b_init(struct r8152 *tp - rtl_tally_reset(tp); - - tp->coalesce = 15000; /* 15 us */ -+ -+ r8152_led_configuration(tp); - } - - static void r8153c_init(struct r8152 *tp) diff --git a/target/linux/generic/hack-5.10/761-dt-bindings-net-add-RTL8152-binding-documentation.patch b/target/linux/generic/hack-5.10/761-dt-bindings-net-add-RTL8152-binding-documentation.patch deleted file mode 100644 index be262b993c..0000000000 --- a/target/linux/generic/hack-5.10/761-dt-bindings-net-add-RTL8152-binding-documentation.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 3ee05f4aa64fc86af3be5bc176ba5808de9260a7 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sun, 26 Jul 2020 15:30:33 +0200 -Subject: [PATCH] dt-bindings: net: add RTL8152 binding documentation - -Add binding documentation for the Realtek RTL8152 / RTL8153 USB ethernet -adapters. - -Signed-off-by: David Bauer ---- - .../bindings/net/realtek,rtl8152.yaml | 36 +++++++++++++++++++ - 1 file changed, 36 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl8152.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/realtek,rtl8152.yaml -@@ -0,0 +1,36 @@ -+# SPDX-License-Identifier: GPL-2.0 -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/realtek,rtl8152.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Realtek RTL8152/RTL8153 series USB ethernet -+ -+maintainers: -+ - David Bauer -+ -+properties: -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - realtek,rtl8152 -+ - realtek,rtl8153 -+ -+ reg: -+ description: The device number on the USB bus -+ -+ realtek,led-data: -+ description: Value to be written to the LED configuration register. -+ -+required: -+ - compatible -+ - reg -+ -+examples: -+ - | -+ usb-eth@2 { -+ compatible = "realtek,rtl8153"; -+ reg = <2>; -+ realtek,led-data = <0x87>; -+ }; -\ No newline at end of file diff --git a/target/linux/generic/hack-5.10/773-bgmac-add-srab-switch.patch b/target/linux/generic/hack-5.10/773-bgmac-add-srab-switch.patch deleted file mode 100644 index fcd9678d05..0000000000 --- a/target/linux/generic/hack-5.10/773-bgmac-add-srab-switch.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 3cb240533ab787899dc7f17aa7d6c5b4810e2e58 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Fri, 7 Jul 2017 17:26:01 +0200 -Subject: bcm53xx: bgmac: use srab switch driver - -use the srab switch driver on these SoCs. - -Signed-off-by: Hauke Mehrtens ---- - drivers/net/ethernet/broadcom/bgmac-bcma.c | 1 + - drivers/net/ethernet/broadcom/bgmac.c | 24 ++++++++++++++++++++++++ - drivers/net/ethernet/broadcom/bgmac.h | 4 ++++ - 3 files changed, 29 insertions(+) - ---- a/drivers/net/ethernet/broadcom/bgmac-bcma.c -+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c -@@ -280,6 +280,7 @@ static int bgmac_probe(struct bcma_devic - bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST; - bgmac->feature_flags |= BGMAC_FEAT_NO_RESET; - bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500; -+ bgmac->feature_flags |= BGMAC_FEAT_SRAB; - break; - default: - bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST; ---- a/drivers/net/ethernet/broadcom/bgmac.c -+++ b/drivers/net/ethernet/broadcom/bgmac.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -1408,6 +1409,17 @@ static const struct ethtool_ops bgmac_et - .set_link_ksettings = phy_ethtool_set_link_ksettings, - }; - -+static struct b53_platform_data bgmac_b53_pdata = { -+}; -+ -+static struct platform_device bgmac_b53_dev = { -+ .name = "b53-srab-switch", -+ .id = -1, -+ .dev = { -+ .platform_data = &bgmac_b53_pdata, -+ }, -+}; -+ - /************************************************** - * MII - **************************************************/ -@@ -1546,6 +1558,14 @@ int bgmac_enet_probe(struct bgmac *bgmac - - bgmac->in_init = false; - -+ if ((bgmac->feature_flags & BGMAC_FEAT_SRAB) && !bgmac_b53_pdata.regs) { -+ bgmac_b53_pdata.regs = ioremap(0x18007000, 0x1000); -+ -+ err = platform_device_register(&bgmac_b53_dev); -+ if (!err) -+ bgmac->b53_device = &bgmac_b53_dev; -+ } -+ - err = register_netdev(bgmac->net_dev); - if (err) { - dev_err(bgmac->dev, "Cannot register net device\n"); -@@ -1568,6 +1588,10 @@ EXPORT_SYMBOL_GPL(bgmac_enet_probe); - - void bgmac_enet_remove(struct bgmac *bgmac) - { -+ if (bgmac->b53_device) -+ platform_device_unregister(&bgmac_b53_dev); -+ bgmac->b53_device = NULL; -+ - unregister_netdev(bgmac->net_dev); - phy_disconnect(bgmac->net_dev->phydev); - netif_napi_del(&bgmac->napi); ---- a/drivers/net/ethernet/broadcom/bgmac.h -+++ b/drivers/net/ethernet/broadcom/bgmac.h -@@ -428,6 +428,7 @@ - #define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII BIT(18) - #define BGMAC_FEAT_CC7_IF_TYPE_RGMII BIT(19) - #define BGMAC_FEAT_IDM_MASK BIT(20) -+#define BGMAC_FEAT_SRAB BIT(21) - - struct bgmac_slot_info { - union { -@@ -535,6 +536,9 @@ struct bgmac { - void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask, - u32 set); - int (*phy_connect)(struct bgmac *bgmac); -+ -+ /* platform device for associated switch */ -+ struct platform_device *b53_device; - }; - - struct bgmac *bgmac_alloc(struct device *dev); diff --git a/target/linux/generic/hack-5.10/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-5.10/780-usb-net-MeigLink_modem_support.patch deleted file mode 100644 index 3b8655fa6e..0000000000 --- a/target/linux/generic/hack-5.10/780-usb-net-MeigLink_modem_support.patch +++ /dev/null @@ -1,47 +0,0 @@ -From: Daniel Golle -Subject: wwan: Add MeigLink SLM750 modem support - -Add patch found in Teltonika RUT9_R_00.07.01.4 GPL SDK download[1] -adding USB IDs of the MeigLink SLM750 to the relevant kernel drivers. -Newer versions of Teltonika's 2G/3G/4G RUT9XX WWAN router series come -with this kind of modem. - -[1]: https://wiki.teltonika-networks.com/view/GPL -Submitted-by: Daniel Golle ---- - drivers/net/usb/qmi_wwan.c | 8 ++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/net/usb/qmi_wwan.c -+++ b/drivers/net/usb/qmi_wwan.c -@@ -1025,6 +1025,7 @@ static const struct usb_device_id produc - {QMI_MATCH_FF_FF_FF(0x2c7c, 0x0620)}, /* Quectel EM160R-GL */ - {QMI_MATCH_FF_FF_FF(0x2c7c, 0x0800)}, /* Quectel RM500Q-GL */ - {QMI_MATCH_FF_FF_FF(0x2c7c, 0x0801)}, /* Quectel RM520N */ -+ {QMI_MATCH_FF_FF_FF(0x05c6, 0xf601)}, /* MeigLink SLM750 */ - - /* 3. Combined interface devices matching on interface number */ - {QMI_FIXED_INTF(0x0408, 0xea42, 4)}, /* Yota / Megafon M100-1 */ ---- a/drivers/usb/serial/option.c -+++ b/drivers/usb/serial/option.c -@@ -244,6 +244,8 @@ static void option_instat_callback(struc - #define UBLOX_PRODUCT_R410M 0x90b2 - /* These Yuga products use Qualcomm's vendor ID */ - #define YUGA_PRODUCT_CLM920_NC5 0x9625 -+/* These MeigLink products use Qualcomm's vendor ID */ -+#define MEIGLINK_PRODUCT_SLM750 0xf601 - - #define QUECTEL_VENDOR_ID 0x2c7c - /* These Quectel products use Quectel's vendor ID */ -@@ -1164,6 +1166,11 @@ static const struct usb_device_id option - .driver_info = ZLP }, - { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), - .driver_info = RSVD(4) }, -+ /* Meiglink products using Qualcomm vendor ID */ -+ // Works OK. In case of some issues check macros that are used by Quectel Products -+ { USB_DEVICE_AND_INTERFACE_INFO(QUALCOMM_VENDOR_ID, MEIGLINK_PRODUCT_SLM750, 0xff, 0xff, 0xff), -+ .driver_info = NUMEP2 }, -+ { USB_DEVICE_AND_INTERFACE_INFO(QUALCOMM_VENDOR_ID, MEIGLINK_PRODUCT_SLM750, 0xff, 0, 0) }, - { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0xff, 0xff), - .driver_info = RSVD(1) | RSVD(2) | RSVD(3) | RSVD(4) | NUMEP2 }, - { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0, 0) }, diff --git a/target/linux/generic/hack-5.10/800-GPIO-add-named-gpio-exports.patch b/target/linux/generic/hack-5.10/800-GPIO-add-named-gpio-exports.patch deleted file mode 100644 index 6367ee9a0b..0000000000 --- a/target/linux/generic/hack-5.10/800-GPIO-add-named-gpio-exports.patch +++ /dev/null @@ -1,162 +0,0 @@ -From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 12 Aug 2014 20:49:27 +0200 -Subject: [PATCH 30/36] GPIO: add named gpio exports - -Signed-off-by: John Crispin ---- a/drivers/gpio/gpiolib-of.c -+++ b/drivers/gpio/gpiolib-of.c -@@ -19,6 +19,8 @@ - #include - #include - #include -+#include -+#include - - #include "gpiolib.h" - #include "gpiolib-of.h" -@@ -1046,3 +1048,72 @@ void of_gpiochip_remove(struct gpio_chip - { - of_node_put(chip->of_node); - } -+ -+#ifdef CONFIG_GPIO_SYSFS -+ -+static struct of_device_id gpio_export_ids[] = { -+ { .compatible = "gpio-export" }, -+ { /* sentinel */ } -+}; -+ -+static int of_gpio_export_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct device_node *cnp; -+ u32 val; -+ int nb = 0; -+ -+ for_each_child_of_node(np, cnp) { -+ const char *name = NULL; -+ int gpio; -+ bool dmc; -+ int max_gpio = 1; -+ int i; -+ -+ of_property_read_string(cnp, "gpio-export,name", &name); -+ -+ if (!name) -+ max_gpio = of_gpio_count(cnp); -+ -+ for (i = 0; i < max_gpio; i++) { -+ unsigned flags = 0; -+ enum of_gpio_flags of_flags; -+ -+ gpio = of_get_gpio_flags(cnp, i, &of_flags); -+ if (!gpio_is_valid(gpio)) -+ return gpio; -+ -+ if (of_flags == OF_GPIO_ACTIVE_LOW) -+ flags |= GPIOF_ACTIVE_LOW; -+ -+ if (!of_property_read_u32(cnp, "gpio-export,output", &val)) -+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; -+ else -+ flags |= GPIOF_IN; -+ -+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np))) -+ continue; -+ -+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change"); -+ gpio_export_with_name(gpio, dmc, name); -+ nb++; -+ } -+ } -+ -+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb); -+ -+ return 0; -+} -+ -+static struct platform_driver gpio_export_driver = { -+ .driver = { -+ .name = "gpio-export", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(gpio_export_ids), -+ }, -+ .probe = of_gpio_export_probe, -+}; -+ -+module_platform_driver(gpio_export_driver); -+ -+#endif ---- a/include/asm-generic/gpio.h -+++ b/include/asm-generic/gpio.h -@@ -125,6 +125,12 @@ static inline int gpio_export(unsigned g - return gpiod_export(gpio_to_desc(gpio), direction_may_change); - } - -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); -+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name) -+{ -+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name); -+} -+ - static inline int gpio_export_link(struct device *dev, const char *name, - unsigned gpio) - { ---- a/include/linux/gpio/consumer.h -+++ b/include/linux/gpio/consumer.h -@@ -715,6 +715,7 @@ static inline void devm_acpi_dev_remove_ - - #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) - -+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); - int gpiod_export(struct gpio_desc *desc, bool direction_may_change); - int gpiod_export_link(struct device *dev, const char *name, - struct gpio_desc *desc); -@@ -722,6 +723,13 @@ void gpiod_unexport(struct gpio_desc *de - - #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ - -+static inline int _gpiod_export(struct gpio_desc *desc, -+ bool direction_may_change, -+ const char *name) -+{ -+ return -ENOSYS; -+} -+ - static inline int gpiod_export(struct gpio_desc *desc, - bool direction_may_change) - { ---- a/drivers/gpio/gpiolib-sysfs.c -+++ b/drivers/gpio/gpiolib-sysfs.c -@@ -572,7 +572,7 @@ static struct class gpio_class = { - * - * Returns zero on success, else an error. - */ --int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) - { - struct gpio_chip *chip; - struct gpio_device *gdev; -@@ -634,6 +634,8 @@ int gpiod_export(struct gpio_desc *desc, - offset = gpio_chip_hwgpio(desc); - if (chip->names && chip->names[offset]) - ioname = chip->names[offset]; -+ if (name) -+ ioname = name; - - dev = device_create_with_groups(&gpio_class, &gdev->dev, - MKDEV(0, 0), data, gpio_groups, -@@ -655,6 +657,12 @@ err_unlock: - gpiod_dbg(desc, "%s: status %d\n", __func__, status); - return status; - } -+EXPORT_SYMBOL_GPL(__gpiod_export); -+ -+int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+{ -+ return __gpiod_export(desc, direction_may_change, NULL); -+} - EXPORT_SYMBOL_GPL(gpiod_export); - - static int match_export(struct device *dev, const void *desc) diff --git a/target/linux/generic/hack-5.10/810-bcma-ssb-fallback-sprom.patch b/target/linux/generic/hack-5.10/810-bcma-ssb-fallback-sprom.patch deleted file mode 100644 index eea7270211..0000000000 --- a/target/linux/generic/hack-5.10/810-bcma-ssb-fallback-sprom.patch +++ /dev/null @@ -1,169 +0,0 @@ ---- a/drivers/bcma/bcma_private.h -+++ b/drivers/bcma/bcma_private.h -@@ -38,6 +38,10 @@ int bcma_bus_resume(struct bcma_bus *bus - void bcma_detect_chip(struct bcma_bus *bus); - int bcma_bus_scan(struct bcma_bus *bus); - -+/* fallback-sprom.c */ -+int __init bcma_fbs_register(void); -+int bcma_get_fallback_sprom(struct bcma_bus *dev, struct ssb_sprom *out); -+ - /* sprom.c */ - int bcma_sprom_get(struct bcma_bus *bus); - ---- a/drivers/bcma/Kconfig -+++ b/drivers/bcma/Kconfig -@@ -18,6 +18,10 @@ config BCMA_BLOCKIO - bool - default y - -+config BCMA_FALLBACK_SPROM -+ bool -+ default y -+ - config BCMA_HOST_PCI_POSSIBLE - bool - depends on PCI = y ---- a/drivers/bcma/Makefile -+++ b/drivers/bcma/Makefile -@@ -11,6 +11,7 @@ bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) - bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o - bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o - bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o -+bcma-$(CONFIG_BCMA_FALLBACK_SPROM) += fallback-sprom.o - bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o - bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o - obj-$(CONFIG_BCMA) += bcma.o ---- a/drivers/bcma/sprom.c -+++ b/drivers/bcma/sprom.c -@@ -51,21 +51,26 @@ static int bcma_fill_sprom_with_fallback - { - int err; - -- if (!get_fallback_sprom) { -+ if (get_fallback_sprom) -+ err = get_fallback_sprom(bus, out); -+ -+#ifdef CONFIG_BCMA_FALLBACK_SPROM -+ if (!get_fallback_sprom || err) -+ err = bcma_get_fallback_sprom(bus, out); -+#else -+ if (!get_fallback_sprom) - err = -ENOENT; -- goto fail; -- } -+#endif /* CONFIG_BCMA_FALLBACK_SPROM */ - -- err = get_fallback_sprom(bus, out); -- if (err) -- goto fail; -+ if (err) { -+ bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err); -+ return err; -+ } - - bcma_debug(bus, "Using SPROM revision %d provided by platform.\n", - bus->sprom.revision); -+ - return 0; --fail: -- bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err); -- return err; - } - - /************************************************** ---- a/drivers/ssb/Kconfig -+++ b/drivers/ssb/Kconfig -@@ -25,6 +25,11 @@ if SSB - config SSB_SPROM - bool - -+config SSB_FALLBACK_SPROM -+ bool -+ depends on SSB_PCIHOST -+ default y -+ - # Support for Block-I/O. SELECT this from the driver that needs it. - config SSB_BLOCKIO - bool ---- a/drivers/ssb/Makefile -+++ b/drivers/ssb/Makefile -@@ -2,6 +2,7 @@ - # core - ssb-y += main.o scan.o - ssb-$(CONFIG_SSB_EMBEDDED) += embedded.o -+ssb-$(CONFIG_SSB_FALLBACK_SPROM) += fallback-sprom.o - ssb-$(CONFIG_SSB_SPROM) += sprom.o - - # host support ---- a/drivers/ssb/sprom.c -+++ b/drivers/ssb/sprom.c -@@ -180,10 +180,20 @@ int ssb_arch_register_fallback_sprom(int - - int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out) - { -+ int err; -+ -+ if (get_fallback_sprom) -+ err = get_fallback_sprom(bus, out); -+ -+#ifdef CONFIG_SSB_FALLBACK_SPROM -+ if (!get_fallback_sprom || err) -+ err = ssb_get_fallback_sprom(bus, out); -+#else - if (!get_fallback_sprom) - return -ENOENT; -+#endif /* CONFIG_SSB_FALLBACK_SPROM */ - -- return get_fallback_sprom(bus, out); -+ return err; - } - - /* https://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */ ---- a/drivers/ssb/ssb_private.h -+++ b/drivers/ssb/ssb_private.h -@@ -143,6 +143,10 @@ extern int ssb_bus_scan(struct ssb_bus * - extern void ssb_iounmap(struct ssb_bus *ssb); - - -+/* fallback-sprom.c */ -+int __init ssb_fbs_register(void); -+int ssb_get_fallback_sprom(struct ssb_bus *dev, struct ssb_sprom *out); -+ - /* sprom.c */ - extern - ssize_t ssb_attr_sprom_show(struct ssb_bus *bus, char *buf, ---- a/drivers/bcma/main.c -+++ b/drivers/bcma/main.c -@@ -668,6 +668,14 @@ static int __init bcma_modinit(void) - { - int err; - -+#ifdef CONFIG_BCMA_FALLBACK_SPROM -+ err = bcma_fbs_register(); -+ if (err) { -+ pr_err("Fallback SPROM initialization failed\n"); -+ err = 0; -+ } -+#endif /* CONFIG_BCMA_FALLBACK_SPROM */ -+ - err = bcma_init_bus_register(); - if (err) - return err; ---- a/drivers/ssb/main.c -+++ b/drivers/ssb/main.c -@@ -1282,6 +1282,14 @@ static int __init ssb_modinit(void) - { - int err; - -+#ifdef CONFIG_SSB_FALLBACK_SPROM -+ err = ssb_fbs_register(); -+ if (err) { -+ pr_err("Fallback SPROM initialization failed\n"); -+ err = 0; -+ } -+#endif /* CONFIG_SSB_FALLBACK_SPROM */ -+ - /* See the comment at the ssb_is_early_boot definition */ - ssb_is_early_boot = 0; - err = bus_register(&ssb_bustype); diff --git a/target/linux/generic/hack-5.10/901-debloat_sock_diag.patch b/target/linux/generic/hack-5.10/901-debloat_sock_diag.patch deleted file mode 100644 index 1ff1bcabb4..0000000000 --- a/target/linux/generic/hack-5.10/901-debloat_sock_diag.patch +++ /dev/null @@ -1,162 +0,0 @@ -From 3b6115d6b57a263bdc8c9b1df273bd4a7955eead Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 8 Jul 2017 08:16:31 +0200 -Subject: debloat: add some debloat patches, strip down procfs and make O_DIRECT support optional, saves ~15K after lzma on MIPS - -Signed-off-by: Felix Fietkau ---- - net/Kconfig | 3 +++ - net/core/Makefile | 3 ++- - net/core/sock.c | 2 ++ - net/ipv4/Kconfig | 1 + - net/netlink/Kconfig | 1 + - net/packet/Kconfig | 1 + - net/unix/Kconfig | 1 + - 7 files changed, 11 insertions(+), 1 deletion(-) - ---- a/net/Kconfig -+++ b/net/Kconfig -@@ -104,6 +104,9 @@ source "net/mptcp/Kconfig" - - endif # if INET - -+config SOCK_DIAG -+ bool -+ - config NETWORK_SECMARK - bool "Security Marking" - help ---- a/net/core/Makefile -+++ b/net/core/Makefile -@@ -10,9 +10,10 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_core. - - obj-y += dev.o dev_addr_lists.o dst.o netevent.o \ - neighbour.o rtnetlink.o utils.o link_watch.o filter.o \ -- sock_diag.o dev_ioctl.o tso.o sock_reuseport.o \ -+ dev_ioctl.o tso.o sock_reuseport.o \ - fib_notifier.o xdp.o flow_offload.o - -+obj-$(CONFIG_SOCK_DIAG) += sock_diag.o - obj-y += net-sysfs.o - obj-$(CONFIG_PAGE_POOL) += page_pool.o - obj-$(CONFIG_PROC_FS) += net-procfs.o ---- a/net/core/sock.c -+++ b/net/core/sock.c -@@ -114,6 +114,7 @@ - #include - #include - #include -+#include - - #include - -@@ -141,6 +142,7 @@ - - static DEFINE_MUTEX(proto_list_mutex); - static LIST_HEAD(proto_list); -+DEFINE_COOKIE(sock_cookie); - - static void sock_inuse_add(struct net *net, int val); - -@@ -526,6 +528,18 @@ discard_and_relse: - } - EXPORT_SYMBOL(__sk_receive_skb); - -+u64 __sock_gen_cookie(struct sock *sk) -+{ -+ while (1) { -+ u64 res = atomic64_read(&sk->sk_cookie); -+ -+ if (res) -+ return res; -+ res = gen_cookie_next(&sock_cookie); -+ atomic64_cmpxchg(&sk->sk_cookie, 0, res); -+ } -+} -+ - struct dst_entry *__sk_dst_check(struct sock *sk, u32 cookie) - { - struct dst_entry *dst = __sk_dst_get(sk); -@@ -1834,9 +1848,11 @@ static void __sk_free(struct sock *sk) - if (likely(sk->sk_net_refcnt)) - sock_inuse_add(sock_net(sk), -1); - -+#ifdef CONFIG_SOCK_DIAG - if (unlikely(sk->sk_net_refcnt && sock_diag_has_destroy_listeners(sk))) - sock_diag_broadcast_destroy(sk); - else -+#endif - sk_destruct(sk); - } - ---- a/net/core/sock_diag.c -+++ b/net/core/sock_diag.c -@@ -11,7 +11,6 @@ - #include - #include - #include --#include - #include - #include - -@@ -20,20 +19,6 @@ static int (*inet_rcv_compat)(struct sk_ - static DEFINE_MUTEX(sock_diag_table_mutex); - static struct workqueue_struct *broadcast_wq; - --DEFINE_COOKIE(sock_cookie); -- --u64 __sock_gen_cookie(struct sock *sk) --{ -- while (1) { -- u64 res = atomic64_read(&sk->sk_cookie); -- -- if (res) -- return res; -- res = gen_cookie_next(&sock_cookie); -- atomic64_cmpxchg(&sk->sk_cookie, 0, res); -- } --} -- - int sock_diag_check_cookie(struct sock *sk, const __u32 *cookie) - { - u64 res; ---- a/net/ipv4/Kconfig -+++ b/net/ipv4/Kconfig -@@ -424,6 +424,7 @@ config INET_TUNNEL - - config INET_DIAG - tristate "INET: socket monitoring interface" -+ select SOCK_DIAG - default y - help - Support for INET (TCP, DCCP, etc) socket monitoring interface used by ---- a/net/netlink/Kconfig -+++ b/net/netlink/Kconfig -@@ -5,6 +5,7 @@ - - config NETLINK_DIAG - tristate "NETLINK: socket monitoring interface" -+ select SOCK_DIAG - default n - help - Support for NETLINK socket monitoring interface used by the ss tool. ---- a/net/packet/Kconfig -+++ b/net/packet/Kconfig -@@ -19,6 +19,7 @@ config PACKET - config PACKET_DIAG - tristate "Packet: sockets monitoring interface" - depends on PACKET -+ select SOCK_DIAG - default n - help - Support for PF_PACKET sockets monitoring interface used by the ss tool. ---- a/net/unix/Kconfig -+++ b/net/unix/Kconfig -@@ -28,6 +28,7 @@ config UNIX_SCM - config UNIX_DIAG - tristate "UNIX: socket monitoring interface" - depends on UNIX -+ select SOCK_DIAG - default n - help - Support for UNIX socket monitoring interface used by the ss tool. diff --git a/target/linux/generic/hack-5.10/902-debloat_proc.patch b/target/linux/generic/hack-5.10/902-debloat_proc.patch deleted file mode 100644 index d8c289ac1a..0000000000 --- a/target/linux/generic/hack-5.10/902-debloat_proc.patch +++ /dev/null @@ -1,408 +0,0 @@ -From 9e3f1d0805b2d919904dd9a4ff0d956314cc3cba Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 8 Jul 2017 08:20:09 +0200 -Subject: debloat: procfs - -Signed-off-by: Felix Fietkau ---- - fs/locks.c | 2 ++ - fs/proc/Kconfig | 5 +++++ - fs/proc/consoles.c | 3 +++ - fs/proc/proc_tty.c | 11 ++++++++++- - include/net/snmp.h | 18 +++++++++++++++++- - ipc/msg.c | 3 +++ - ipc/sem.c | 2 ++ - ipc/shm.c | 2 ++ - ipc/util.c | 3 +++ - kernel/exec_domain.c | 2 ++ - kernel/irq/proc.c | 9 +++++++++ - kernel/time/timer_list.c | 2 ++ - mm/vmalloc.c | 2 ++ - mm/vmstat.c | 8 +++++--- - net/8021q/vlanproc.c | 6 ++++++ - net/core/net-procfs.c | 18 ++++++++++++------ - net/core/sock.c | 2 ++ - net/ipv4/fib_trie.c | 18 ++++++++++++------ - net/ipv4/proc.c | 3 +++ - net/ipv4/route.c | 3 +++ - 20 files changed, 105 insertions(+), 17 deletions(-) - ---- a/fs/locks.c -+++ b/fs/locks.c -@@ -3016,6 +3016,8 @@ static const struct seq_operations locks - - static int __init proc_locks_init(void) - { -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return 0; - proc_create_seq_private("locks", 0, NULL, &locks_seq_operations, - sizeof(struct locks_iterator), NULL); - return 0; ---- a/fs/proc/Kconfig -+++ b/fs/proc/Kconfig -@@ -100,6 +100,11 @@ config PROC_CHILDREN - Say Y if you are running any user-space software which takes benefit from - this interface. For example, rkt is such a piece of software. - -+config PROC_STRIPPED -+ default n -+ depends on EXPERT -+ bool "Strip non-essential /proc functionality to reduce code size" -+ - config PROC_PID_ARCH_STATUS - def_bool n - depends on PROC_FS ---- a/fs/proc/consoles.c -+++ b/fs/proc/consoles.c -@@ -92,6 +92,9 @@ static const struct seq_operations conso - - static int __init proc_consoles_init(void) - { -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return 0; -+ - proc_create_seq("consoles", 0, NULL, &consoles_op); - return 0; - } ---- a/fs/proc/proc_tty.c -+++ b/fs/proc/proc_tty.c -@@ -133,7 +133,10 @@ static const struct seq_operations tty_d - void proc_tty_register_driver(struct tty_driver *driver) - { - struct proc_dir_entry *ent; -- -+ -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return; -+ - if (!driver->driver_name || driver->proc_entry || - !driver->ops->proc_show) - return; -@@ -150,6 +153,9 @@ void proc_tty_unregister_driver(struct t - { - struct proc_dir_entry *ent; - -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return; -+ - ent = driver->proc_entry; - if (!ent) - return; -@@ -164,6 +170,9 @@ void proc_tty_unregister_driver(struct t - */ - void __init proc_tty_init(void) - { -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return; -+ - if (!proc_mkdir("tty", NULL)) - return; - proc_mkdir("tty/ldisc", NULL); /* Preserved: it's userspace visible */ ---- a/include/net/snmp.h -+++ b/include/net/snmp.h -@@ -124,6 +124,21 @@ struct linux_tls_mib { - #define DECLARE_SNMP_STAT(type, name) \ - extern __typeof__(type) __percpu *name - -+#ifdef CONFIG_PROC_STRIPPED -+#define __SNMP_STATS_DUMMY(mib) \ -+ do { (void) mib->mibs[0]; } while(0) -+ -+#define __SNMP_INC_STATS(mib, field) __SNMP_STATS_DUMMY(mib) -+#define SNMP_INC_STATS_ATOMIC_LONG(mib, field) __SNMP_STATS_DUMMY(mib) -+#define SNMP_INC_STATS(mib, field) __SNMP_STATS_DUMMY(mib) -+#define SNMP_DEC_STATS(mib, field) __SNMP_STATS_DUMMY(mib) -+#define __SNMP_ADD_STATS(mib, field, addend) __SNMP_STATS_DUMMY(mib) -+#define SNMP_ADD_STATS(mib, field, addend) __SNMP_STATS_DUMMY(mib) -+#define SNMP_UPD_PO_STATS(mib, basefield, addend) __SNMP_STATS_DUMMY(mib) -+#define __SNMP_UPD_PO_STATS(mib, basefield, addend) __SNMP_STATS_DUMMY(mib) -+ -+#else -+ - #define __SNMP_INC_STATS(mib, field) \ - __this_cpu_inc(mib->mibs[field]) - -@@ -154,8 +169,9 @@ struct linux_tls_mib { - __this_cpu_add(ptr[basefield##OCTETS], addend); \ - } while (0) - -+#endif - --#if BITS_PER_LONG==32 -+#if (BITS_PER_LONG==32) && !defined(CONFIG_PROC_STRIPPED) - - #define __SNMP_ADD_STATS64(mib, field, addend) \ - do { \ ---- a/ipc/msg.c -+++ b/ipc/msg.c -@@ -1350,6 +1350,9 @@ void __init msg_init(void) - { - msg_init_ns(&init_ipc_ns); - -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return; -+ - ipc_init_proc_interface("sysvipc/msg", - " key msqid perms cbytes qnum lspid lrpid uid gid cuid cgid stime rtime ctime\n", - IPC_MSG_IDS, sysvipc_msg_proc_show); ---- a/ipc/sem.c -+++ b/ipc/sem.c -@@ -266,6 +266,8 @@ void sem_exit_ns(struct ipc_namespace *n - void __init sem_init(void) - { - sem_init_ns(&init_ipc_ns); -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return; - ipc_init_proc_interface("sysvipc/sem", - " key semid perms nsems uid gid cuid cgid otime ctime\n", - IPC_SEM_IDS, sysvipc_sem_proc_show); ---- a/ipc/shm.c -+++ b/ipc/shm.c -@@ -154,6 +154,8 @@ pure_initcall(ipc_ns_init); - - void __init shm_init(void) - { -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return; - ipc_init_proc_interface("sysvipc/shm", - #if BITS_PER_LONG <= 32 - " key shmid perms size cpid lpid nattch uid gid cuid cgid atime dtime ctime rss swap\n", ---- a/ipc/util.c -+++ b/ipc/util.c -@@ -140,6 +140,9 @@ void __init ipc_init_proc_interface(cons - struct proc_dir_entry *pde; - struct ipc_proc_iface *iface; - -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return; -+ - iface = kmalloc(sizeof(*iface), GFP_KERNEL); - if (!iface) - return; ---- a/kernel/exec_domain.c -+++ b/kernel/exec_domain.c -@@ -29,6 +29,8 @@ static int execdomains_proc_show(struct - - static int __init proc_execdomains_init(void) - { -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return 0; - proc_create_single("execdomains", 0, NULL, execdomains_proc_show); - return 0; - } ---- a/kernel/irq/proc.c -+++ b/kernel/irq/proc.c -@@ -341,6 +341,9 @@ void register_irq_proc(unsigned int irq, - void __maybe_unused *irqp = (void *)(unsigned long) irq; - char name [MAX_NAMELEN]; - -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) -+ return; -+ - if (!root_irq_dir || (desc->irq_data.chip == &no_irq_chip)) - return; - -@@ -394,6 +397,9 @@ void unregister_irq_proc(unsigned int ir - { - char name [MAX_NAMELEN]; - -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) -+ return; -+ - if (!root_irq_dir || !desc->dir) - return; - #ifdef CONFIG_SMP -@@ -432,6 +438,9 @@ void init_irq_proc(void) - unsigned int irq; - struct irq_desc *desc; - -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP)) -+ return; -+ - /* create /proc/irq */ - root_irq_dir = proc_mkdir("irq", NULL); - if (!root_irq_dir) ---- a/kernel/time/timer_list.c -+++ b/kernel/time/timer_list.c -@@ -370,6 +370,8 @@ static int __init init_timer_list_procfs - { - struct proc_dir_entry *pe; - -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return 0; - pe = proc_create_seq_private("timer_list", 0400, NULL, &timer_list_sops, - sizeof(struct timer_list_iter), NULL); - if (!pe) ---- a/mm/vmalloc.c -+++ b/mm/vmalloc.c -@@ -3572,6 +3572,8 @@ static const struct seq_operations vmall - - static int __init proc_vmalloc_init(void) - { -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return 0; - if (IS_ENABLED(CONFIG_NUMA)) - proc_create_seq_private("vmallocinfo", 0400, NULL, - &vmalloc_op, ---- a/mm/vmstat.c -+++ b/mm/vmstat.c -@@ -2040,10 +2040,12 @@ void __init init_mm_internals(void) - start_shepherd_timer(); - #endif - #ifdef CONFIG_PROC_FS -- proc_create_seq("buddyinfo", 0444, NULL, &fragmentation_op); -- proc_create_seq("pagetypeinfo", 0400, NULL, &pagetypeinfo_op); -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { -+ proc_create_seq("buddyinfo", 0444, NULL, &fragmentation_op); -+ proc_create_seq("pagetypeinfo", 0400, NULL, &pagetypeinfo_op); -+ proc_create_seq("zoneinfo", 0444, NULL, &zoneinfo_op); -+ } - proc_create_seq("vmstat", 0444, NULL, &vmstat_op); -- proc_create_seq("zoneinfo", 0444, NULL, &zoneinfo_op); - #endif - } - ---- a/net/8021q/vlanproc.c -+++ b/net/8021q/vlanproc.c -@@ -93,6 +93,9 @@ void vlan_proc_cleanup(struct net *net) - { - struct vlan_net *vn = net_generic(net, vlan_net_id); - -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return; -+ - if (vn->proc_vlan_conf) - remove_proc_entry(name_conf, vn->proc_vlan_dir); - -@@ -112,6 +115,9 @@ int __net_init vlan_proc_init(struct net - { - struct vlan_net *vn = net_generic(net, vlan_net_id); - -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return 0; -+ - vn->proc_vlan_dir = proc_net_mkdir(net, name_root, net->proc_net); - if (!vn->proc_vlan_dir) - goto err; ---- a/net/core/net-procfs.c -+++ b/net/core/net-procfs.c -@@ -320,10 +320,12 @@ static int __net_init dev_proc_net_init( - if (!proc_create_net("dev", 0444, net->proc_net, &dev_seq_ops, - sizeof(struct seq_net_private))) - goto out; -- if (!proc_create_seq("softnet_stat", 0444, net->proc_net, -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && -+ !proc_create_seq("softnet_stat", 0444, net->proc_net, - &softnet_seq_ops)) - goto out_dev; -- if (!proc_create_net("ptype", 0444, net->proc_net, &ptype_seq_ops, -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && -+ !proc_create_net("ptype", 0444, net->proc_net, &ptype_seq_ops, - sizeof(struct seq_net_private))) - goto out_softnet; - -@@ -333,9 +335,11 @@ static int __net_init dev_proc_net_init( - out: - return rc; - out_ptype: -- remove_proc_entry("ptype", net->proc_net); -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ remove_proc_entry("ptype", net->proc_net); - out_softnet: -- remove_proc_entry("softnet_stat", net->proc_net); -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ remove_proc_entry("softnet_stat", net->proc_net); - out_dev: - remove_proc_entry("dev", net->proc_net); - goto out; -@@ -345,8 +349,10 @@ static void __net_exit dev_proc_net_exit - { - wext_proc_exit(net); - -- remove_proc_entry("ptype", net->proc_net); -- remove_proc_entry("softnet_stat", net->proc_net); -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { -+ remove_proc_entry("ptype", net->proc_net); -+ remove_proc_entry("softnet_stat", net->proc_net); -+ } - remove_proc_entry("dev", net->proc_net); - } - ---- a/net/core/sock.c -+++ b/net/core/sock.c -@@ -3710,6 +3710,8 @@ static __net_initdata struct pernet_oper - - static int __init proto_init(void) - { -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return 0; - return register_pernet_subsys(&proto_net_ops); - } - ---- a/net/ipv4/fib_trie.c -+++ b/net/ipv4/fib_trie.c -@@ -2988,11 +2988,13 @@ static const struct seq_operations fib_r - - int __net_init fib_proc_init(struct net *net) - { -- if (!proc_create_net("fib_trie", 0444, net->proc_net, &fib_trie_seq_ops, -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && -+ !proc_create_net("fib_trie", 0444, net->proc_net, &fib_trie_seq_ops, - sizeof(struct fib_trie_iter))) - goto out1; - -- if (!proc_create_net_single("fib_triestat", 0444, net->proc_net, -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED) && -+ !proc_create_net_single("fib_triestat", 0444, net->proc_net, - fib_triestat_seq_show, NULL)) - goto out2; - -@@ -3003,17 +3005,21 @@ int __net_init fib_proc_init(struct net - return 0; - - out3: -- remove_proc_entry("fib_triestat", net->proc_net); -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ remove_proc_entry("fib_triestat", net->proc_net); - out2: -- remove_proc_entry("fib_trie", net->proc_net); -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ remove_proc_entry("fib_trie", net->proc_net); - out1: - return -ENOMEM; - } - - void __net_exit fib_proc_exit(struct net *net) - { -- remove_proc_entry("fib_trie", net->proc_net); -- remove_proc_entry("fib_triestat", net->proc_net); -+ if (!IS_ENABLED(CONFIG_PROC_STRIPPED)) { -+ remove_proc_entry("fib_trie", net->proc_net); -+ remove_proc_entry("fib_triestat", net->proc_net); -+ } - remove_proc_entry("route", net->proc_net); - } - ---- a/net/ipv4/proc.c -+++ b/net/ipv4/proc.c -@@ -528,5 +528,8 @@ static __net_initdata struct pernet_oper - - int __init ip_misc_proc_init(void) - { -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return 0; -+ - return register_pernet_subsys(&ip_proc_ops); - } ---- a/net/ipv4/route.c -+++ b/net/ipv4/route.c -@@ -410,6 +410,9 @@ static struct pernet_operations ip_rt_pr - - static int __init ip_rt_proc_init(void) - { -+ if (IS_ENABLED(CONFIG_PROC_STRIPPED)) -+ return 0; -+ - return register_pernet_subsys(&ip_rt_proc_ops); - } - diff --git a/target/linux/generic/hack-5.10/904-debloat_dma_buf.patch b/target/linux/generic/hack-5.10/904-debloat_dma_buf.patch deleted file mode 100644 index 7bf15c1dd8..0000000000 --- a/target/linux/generic/hack-5.10/904-debloat_dma_buf.patch +++ /dev/null @@ -1,92 +0,0 @@ -From e3692cb2fcd5ba1244512a0f43b8118f65f1c375 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sat, 8 Jul 2017 08:20:43 +0200 -Subject: debloat: dmabuf - -Signed-off-by: Felix Fietkau ---- - drivers/base/Kconfig | 2 +- - drivers/dma-buf/Makefile | 10 +++++++--- - drivers/dma-buf/dma-buf.c | 4 +++- - kernel/sched/core.c | 1 + - 4 files changed, 12 insertions(+), 5 deletions(-) - ---- a/drivers/base/Kconfig -+++ b/drivers/base/Kconfig -@@ -184,7 +184,7 @@ config SOC_BUS - source "drivers/base/regmap/Kconfig" - - config DMA_SHARED_BUFFER -- bool -+ tristate - default n - select IRQ_WORK - help ---- a/drivers/dma-buf/heaps/Makefile -+++ b/drivers/dma-buf/heaps/Makefile -@@ -1,4 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0 --obj-y += heap-helpers.o --obj-$(CONFIG_DMABUF_HEAPS_SYSTEM) += system_heap.o --obj-$(CONFIG_DMABUF_HEAPS_CMA) += cma_heap.o -+dma-buf-objs-y += heap-helpers.o -+dma-buf-objs-$(CONFIG_DMABUF_HEAPS_SYSTEM) += system_heap.o -+dma-buf-objs-$(CONFIG_DMABUF_HEAPS_CMA) += cma_heap.o ---- a/drivers/dma-buf/Makefile -+++ b/drivers/dma-buf/Makefile -@@ -1,15 +1,19 @@ - # SPDX-License-Identifier: GPL-2.0-only --obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \ -+obj-$(CONFIG_DMA_SHARED_BUFFER) := dma-shared-buffer.o -+ -+dma-buf-objs-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \ - dma-resv.o seqno-fence.o --obj-$(CONFIG_DMABUF_HEAPS) += dma-heap.o --obj-$(CONFIG_DMABUF_HEAPS) += heaps/ --obj-$(CONFIG_SYNC_FILE) += sync_file.o --obj-$(CONFIG_SW_SYNC) += sw_sync.o sync_debug.o --obj-$(CONFIG_UDMABUF) += udmabuf.o -+dma-buf-objs-$(CONFIG_DMABUF_HEAPS) += dma-heap.o -+obj-$(CONFIG_DMABUF_HEAPS) += heaps/ -+dma-buf-objs-$(CONFIG_SYNC_FILE) += sync_file.o -+dma-buf-objs-$(CONFIG_SW_SYNC) += sw_sync.o sync_debug.o -+dma-buf-objs-$(CONFIG_UDMABUF) += udmabuf.o - - dmabuf_selftests-y := \ - selftest.o \ - st-dma-fence.o \ - st-dma-fence-chain.o - --obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o -+dma-buf-objs-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o -+ -+dma-shared-buffer-objs := $(dma-buf-objs-y) ---- a/drivers/dma-buf/dma-buf.c -+++ b/drivers/dma-buf/dma-buf.c -@@ -1419,4 +1419,5 @@ static void __exit dma_buf_deinit(void) - dma_buf_uninit_debugfs(); - kern_unmount(dma_buf_mnt); - } --__exitcall(dma_buf_deinit); -+module_exit(dma_buf_deinit); -+MODULE_LICENSE("GPL"); ---- a/kernel/sched/core.c -+++ b/kernel/sched/core.c -@@ -3074,6 +3074,7 @@ int wake_up_state(struct task_struct *p, - { - return try_to_wake_up(p, state, 0); - } -+EXPORT_SYMBOL_GPL(wake_up_state); - - /* - * Perform scheduler related setup for a newly forked process p. ---- a/fs/d_path.c -+++ b/fs/d_path.c -@@ -311,6 +311,7 @@ char *dynamic_dname(struct dentry *dentr - buffer += buflen - sz; - return memcpy(buffer, temp, sz); - } -+EXPORT_SYMBOL_GPL(dynamic_dname); - - char *simple_dname(struct dentry *dentry, char *buffer, int buflen) - { diff --git a/target/linux/generic/hack-5.10/910-kobject_uevent.patch b/target/linux/generic/hack-5.10/910-kobject_uevent.patch deleted file mode 100644 index c4c41ca400..0000000000 --- a/target/linux/generic/hack-5.10/910-kobject_uevent.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0d37e6edc09c99e683dd91ca0e83bbc0df8477b3 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sun, 16 Jul 2017 16:56:10 +0200 -Subject: lib: add uevent_next_seqnum() - -Signed-off-by: Felix Fietkau ---- - include/linux/kobject.h | 5 +++++ - lib/kobject_uevent.c | 37 +++++++++++++++++++++++++++++++++++++ - 2 files changed, 42 insertions(+) - ---- a/lib/kobject_uevent.c -+++ b/lib/kobject_uevent.c -@@ -179,6 +179,18 @@ out: - return r; - } - -+u64 uevent_next_seqnum(void) -+{ -+ u64 seq; -+ -+ mutex_lock(&uevent_sock_mutex); -+ seq = ++uevent_seqnum; -+ mutex_unlock(&uevent_sock_mutex); -+ -+ return seq; -+} -+EXPORT_SYMBOL_GPL(uevent_next_seqnum); -+ - /** - * kobject_synth_uevent - send synthetic uevent with arguments - * diff --git a/target/linux/generic/hack-5.10/911-kobject_add_broadcast_uevent.patch b/target/linux/generic/hack-5.10/911-kobject_add_broadcast_uevent.patch deleted file mode 100644 index a487d55193..0000000000 --- a/target/linux/generic/hack-5.10/911-kobject_add_broadcast_uevent.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 0d37e6edc09c99e683dd91ca0e83bbc0df8477b3 Mon Sep 17 00:00:00 2001 -From: Felix Fietkau -Date: Sun, 16 Jul 2017 16:56:10 +0200 -Subject: lib: add uevent_next_seqnum() - -Signed-off-by: Felix Fietkau ---- - include/linux/kobject.h | 5 +++++ - lib/kobject_uevent.c | 37 +++++++++++++++++++++++++++++++++++++ - 2 files changed, 42 insertions(+) - ---- a/include/linux/kobject.h -+++ b/include/linux/kobject.h -@@ -32,6 +32,8 @@ - #define UEVENT_NUM_ENVP 64 /* number of env pointers */ - #define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */ - -+struct sk_buff; -+ - #ifdef CONFIG_UEVENT_HELPER - /* path to the userspace helper executed on an event */ - extern char uevent_helper[]; -@@ -244,4 +246,7 @@ int kobject_synth_uevent(struct kobject - __printf(2, 3) - int add_uevent_var(struct kobj_uevent_env *env, const char *format, ...); - -+int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, -+ gfp_t allocation); -+ - #endif /* _KOBJECT_H_ */ ---- a/lib/kobject_uevent.c -+++ b/lib/kobject_uevent.c -@@ -691,6 +691,43 @@ int add_uevent_var(struct kobj_uevent_en - EXPORT_SYMBOL_GPL(add_uevent_var); - - #if defined(CONFIG_NET) -+int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, -+ gfp_t allocation) -+{ -+ struct uevent_sock *ue_sk; -+ int err = 0; -+ -+ /* send netlink message */ -+ mutex_lock(&uevent_sock_mutex); -+ list_for_each_entry(ue_sk, &uevent_sock_list, list) { -+ struct sock *uevent_sock = ue_sk->sk; -+ struct sk_buff *skb2; -+ -+ skb2 = skb_clone(skb, allocation); -+ if (!skb2) -+ break; -+ -+ err = netlink_broadcast(uevent_sock, skb2, pid, group, -+ allocation); -+ if (err) -+ break; -+ } -+ mutex_unlock(&uevent_sock_mutex); -+ -+ kfree_skb(skb); -+ return err; -+} -+#else -+int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group, -+ gfp_t allocation) -+{ -+ kfree_skb(skb); -+ return 0; -+} -+#endif -+EXPORT_SYMBOL_GPL(broadcast_uevent); -+ -+#if defined(CONFIG_NET) - static int uevent_net_broadcast(struct sock *usk, struct sk_buff *skb, - struct netlink_ext_ack *extack) - { diff --git a/target/linux/generic/hack-5.10/920-device_tree_cmdline.patch b/target/linux/generic/hack-5.10/920-device_tree_cmdline.patch deleted file mode 100644 index dbba45b41c..0000000000 --- a/target/linux/generic/hack-5.10/920-device_tree_cmdline.patch +++ /dev/null @@ -1,28 +0,0 @@ -From a9968d9cb8cb10030491fa05e24b00bd42f6d3a9 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 30 May 2013 16:00:42 +0000 -Subject: fdt: enable retrieving kernel args from bootloader - -This patch is a device tree enhancement that IMHO is worthy of mainline. -It allows the bootloader's commandline to be preserved even when the -device tree specifies one. - -Submitted-by: Daniel Gimpelevich - -SVN-Revision: 36780 ---- - drivers/of/fdt.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1054,6 +1054,9 @@ int __init early_init_dt_scan_chosen(uns - p = of_get_flat_dt_prop(node, "bootargs", &l); - if (p != NULL && l > 0) - strlcpy(data, p, min(l, COMMAND_LINE_SIZE)); -+ p = of_get_flat_dt_prop(node, "bootargs-append", &l); -+ if (p != NULL && l > 0) -+ strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); - - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else diff --git a/target/linux/generic/pending-5.10/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch b/target/linux/generic/pending-5.10/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch deleted file mode 100644 index 75f63728ec..0000000000 --- a/target/linux/generic/pending-5.10/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d8d1a9a77863a8c7031ae82a1d461aa78eb72a7b Mon Sep 17 00:00:00 2001 -From: Rob Herring -Date: Mon, 11 Oct 2021 14:12:43 -0500 -Subject: [PATCH] checks: Drop interrupt provider '#address-cells' check - -'#address-cells' is only needed when parsing 'interrupt-map' properties, so -remove it from the common interrupt-provider test. - -Cc: Andre Przywara -Reviewed-by: David Gibson -Signed-off-by: Rob Herring -Message-Id: <20211011191245.1009682-3-robh@kernel.org> -Signed-off-by: David Gibson ---- ---- a/scripts/dtc/checks.c -+++ b/scripts/dtc/checks.c -@@ -1569,11 +1569,6 @@ static void check_interrupt_provider(str - if (!prop) - FAIL(c, dti, node, - "Missing #interrupt-cells in interrupt provider"); -- -- prop = get_property(node, "#address-cells"); -- if (!prop) -- FAIL(c, dti, node, -- "Missing #address-cells in interrupt provider"); - } - WARNING(interrupt_provider, check_interrupt_provider, NULL); - diff --git a/target/linux/generic/pending-5.10/100-compiler.h-only-include-asm-rwonce.h-for-kernel-code.patch b/target/linux/generic/pending-5.10/100-compiler.h-only-include-asm-rwonce.h-for-kernel-code.patch deleted file mode 100644 index 282c8196e5..0000000000 --- a/target/linux/generic/pending-5.10/100-compiler.h-only-include-asm-rwonce.h-for-kernel-code.patch +++ /dev/null @@ -1,29 +0,0 @@ -From: Felix Fietkau -Date: Thu, 22 Oct 2020 22:00:03 +0200 -Subject: [PATCH] compiler.h: only include asm/rwonce.h for kernel code - -This header file is not in uapi, which makes any user space code that includes -linux/compiler.h to fail with the error 'asm/rwonce.h: No such file or directory' - -Fixes: e506ea451254 ("compiler.h: Split {READ,WRITE}_ONCE definitions out into rwonce.h") -Signed-off-by: Felix Fietkau ---- - ---- a/include/linux/compiler.h -+++ b/include/linux/compiler.h -@@ -213,6 +213,8 @@ void ftrace_likely_update(struct ftrace_ - __v; \ - }) - -+#include -+ - #endif /* __KERNEL__ */ - - /* -@@ -245,6 +247,4 @@ static inline void *offset_to_ptr(const - */ - #define prevent_tail_call_optimization() mb() - --#include -- - #endif /* __LINUX_COMPILER_H */ diff --git a/target/linux/generic/pending-5.10/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch b/target/linux/generic/pending-5.10/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch deleted file mode 100644 index cc9f99e8b0..0000000000 --- a/target/linux/generic/pending-5.10/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch +++ /dev/null @@ -1,57 +0,0 @@ -From: Felix Fietkau -Date: Wed, 18 Apr 2018 10:50:05 +0200 -Subject: [PATCH] MIPS: only process negative stack offsets on stack traces - -Fixes endless back traces in cases where the compiler emits a stack -pointer increase in a branch delay slot (probably for some form of -function return). - -[ 3.475442] BUG: MAX_STACK_TRACE_ENTRIES too low! -[ 3.480070] turning off the locking correctness validator. -[ 3.485521] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.14.34 #0 -[ 3.491475] Stack : 00000000 00000000 00000000 00000000 80e0fce2 00000034 00000000 00000000 -[ 3.499764] 87c3838c 80696377 8061047c 00000000 00000001 00000001 87c2d850 6534689f -[ 3.508059] 00000000 00000000 80e10000 00000000 00000000 000000cf 0000000f 00000000 -[ 3.516353] 00000000 806a0000 00076891 00000000 00000000 00000000 ffffffff 00000000 -[ 3.524648] 806c0000 00000004 80e10000 806a0000 00000003 80690000 00000000 80700000 -[ 3.532942] ... -[ 3.535362] Call Trace: -[ 3.537818] [<80010a48>] show_stack+0x58/0x100 -[ 3.542207] [<804c2f78>] dump_stack+0xe8/0x170 -[ 3.546613] [<80079f90>] save_trace+0xf0/0x110 -[ 3.551010] [<8007b1ec>] mark_lock+0x33c/0x78c -[ 3.555413] [<8007bf48>] __lock_acquire+0x2ac/0x1a08 -[ 3.560337] [<8007de60>] lock_acquire+0x64/0x8c -[ 3.564846] [<804e1570>] _raw_spin_lock_irqsave+0x54/0x78 -[ 3.570186] [<801b618c>] kernfs_notify+0x94/0xac -[ 3.574770] [<801b7b10>] sysfs_notify+0x74/0xa0 -[ 3.579257] [<801b618c>] kernfs_notify+0x94/0xac -[ 3.583839] [<801b7b10>] sysfs_notify+0x74/0xa0 -[ 3.588329] [<801b618c>] kernfs_notify+0x94/0xac -[ 3.592911] [<801b7b10>] sysfs_notify+0x74/0xa0 -[ 3.597401] [<801b618c>] kernfs_notify+0x94/0xac -[ 3.601983] [<801b7b10>] sysfs_notify+0x74/0xa0 -[ 3.606473] [<801b618c>] kernfs_notify+0x94/0xac -[ 3.611055] [<801b7b10>] sysfs_notify+0x74/0xa0 -[ 3.615545] [<801b618c>] kernfs_notify+0x94/0xac -[ 3.620125] [<801b7b10>] sysfs_notify+0x74/0xa0 -[ 3.624619] [<801b618c>] kernfs_notify+0x94/0xac -[ 3.629197] [<801b7b10>] sysfs_notify+0x74/0xa0 -[ 3.633691] [<801b618c>] kernfs_notify+0x94/0xac -[ 3.638269] [<801b7b10>] sysfs_notify+0x74/0xa0 -[ 3.642763] [<801b618c>] kernfs_notify+0x94/0xac - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/mips/kernel/process.c -+++ b/arch/mips/kernel/process.c -@@ -380,6 +380,8 @@ static inline int is_sp_move_ins(union m - - if (ip->i_format.opcode == addiu_op || - ip->i_format.opcode == daddiu_op) { -+ if (ip->i_format.simmediate > 0) -+ return 0; - *frame_size = -ip->i_format.simmediate; - return 1; - } diff --git a/target/linux/generic/pending-5.10/110-v6.3-0001-spidev-Add-Silicon-Labs-EM3581-device-compatible.patch b/target/linux/generic/pending-5.10/110-v6.3-0001-spidev-Add-Silicon-Labs-EM3581-device-compatible.patch deleted file mode 100644 index 6090bbb329..0000000000 --- a/target/linux/generic/pending-5.10/110-v6.3-0001-spidev-Add-Silicon-Labs-EM3581-device-compatible.patch +++ /dev/null @@ -1,21 +0,0 @@ -From f7982c726e02001afc19052fe48f642dfcbc00b2 Mon Sep 17 00:00:00 2001 -From: Vincent Tremblay -Date: Mon, 26 Dec 2022 21:10:37 -0500 -Subject: [PATCH 1/2] spidev: Add Silicon Labs EM3581 device compatible - -Add compatible string for Silicon Labs EM3581 device. - -Note: This patch is adapted from a patch submitted to the for-next branch (v6.3). - -Signed-off-by: Vincent Tremblay - ---- a/drivers/spi/spidev.c -+++ b/drivers/spi/spidev.c -@@ -691,6 +691,7 @@ static const struct of_device_id spidev_ - { .compatible = "lwn,bk4" }, - { .compatible = "dh,dhcom-board" }, - { .compatible = "menlo,m53cpld" }, -+ { .compatible = "silabs,em3581" }, - {}, - }; - MODULE_DEVICE_TABLE(of, spidev_dt_ids); diff --git a/target/linux/generic/pending-5.10/110-v6.3-0002-spidev-Add-Silicon-Labs-SI3210-device-compatible.patch b/target/linux/generic/pending-5.10/110-v6.3-0002-spidev-Add-Silicon-Labs-SI3210-device-compatible.patch deleted file mode 100644 index 19b7a0a4e5..0000000000 --- a/target/linux/generic/pending-5.10/110-v6.3-0002-spidev-Add-Silicon-Labs-SI3210-device-compatible.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 536581825219e97fa2ae0c4de35605d2f6311416 Mon Sep 17 00:00:00 2001 -From: Vincent Tremblay -Date: Tue, 27 Dec 2022 09:00:58 -0500 -Subject: [PATCH 2/2] spidev: Add Silicon Labs SI3210 device compatible - -Add compatible string for Silicon Labs SI3210 device. - -Note: This patch is adapted from a patch submitted to the for-next branch (v6.3). - -Signed-off-by: Vincent Tremblay ---- - ---- a/drivers/spi/spidev.c -+++ b/drivers/spi/spidev.c -@@ -692,6 +692,7 @@ static const struct of_device_id spidev_ - { .compatible = "dh,dhcom-board" }, - { .compatible = "menlo,m53cpld" }, - { .compatible = "silabs,em3581" }, -+ { .compatible = "silabs,si3210" }, - {}, - }; - MODULE_DEVICE_TABLE(of, spidev_dt_ids); diff --git a/target/linux/generic/pending-5.10/111-watchdog-max63xx_wdt-Add-support-for-specifying-WDI-.patch b/target/linux/generic/pending-5.10/111-watchdog-max63xx_wdt-Add-support-for-specifying-WDI-.patch deleted file mode 100644 index d2e134a132..0000000000 --- a/target/linux/generic/pending-5.10/111-watchdog-max63xx_wdt-Add-support-for-specifying-WDI-.patch +++ /dev/null @@ -1,75 +0,0 @@ -From bd1b9f66d5134e518419f4c4dacf1884c1616983 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 28 Apr 2022 11:13:23 +0200 -Subject: [PATCH] watchdog: max63xx_wdt: Add support for specifying WDI logic - via GPIO -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -On some boards is WDI logic of max6370 chip connected via GPIO. -So extend max63xx_wdt driver to allow specifying WDI logic via GPIO. - -Signed-off-by: Pali Rohár ---- - drivers/watchdog/max63xx_wdt.c | 24 ++++++++++++++++++++++++ - 1 file changed, 24 insertions(+) - ---- a/drivers/watchdog/max63xx_wdt.c -+++ b/drivers/watchdog/max63xx_wdt.c -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - - #define DEFAULT_HEARTBEAT 60 - #define MAX_HEARTBEAT 60 -@@ -52,6 +53,9 @@ struct max63xx_wdt { - void __iomem *base; - spinlock_t lock; - -+ /* GPIOs */ -+ struct gpio_desc *gpio_wdi; -+ - /* WDI and WSET bits write access routines */ - void (*ping)(struct max63xx_wdt *wdt); - void (*set)(struct max63xx_wdt *wdt, u8 set); -@@ -157,6 +161,17 @@ static const struct watchdog_info max63x - .identity = "max63xx Watchdog", - }; - -+static void max63xx_gpio_ping(struct max63xx_wdt *wdt) -+{ -+ spin_lock(&wdt->lock); -+ -+ gpiod_set_value(wdt->gpio_wdi, 1); -+ udelay(1); -+ gpiod_set_value(wdt->gpio_wdi, 0); -+ -+ spin_unlock(&wdt->lock); -+} -+ - static void max63xx_mmap_ping(struct max63xx_wdt *wdt) - { - u8 val; -@@ -221,10 +236,19 @@ static int max63xx_wdt_probe(struct plat - return -EINVAL; - } - -+ wdt->gpio_wdi = devm_gpiod_get(dev, NULL, GPIOD_FLAGS_BIT_DIR_OUT); -+ if (IS_ERR(wdt->gpio_wdi) && PTR_ERR(wdt->gpio_wdi) != -ENOENT) -+ return dev_err_probe(dev, PTR_ERR(wdt->gpio_wdi), -+ "unable to request gpio: %ld\n", -+ PTR_ERR(wdt->gpio_wdi)); -+ - err = max63xx_mmap_init(pdev, wdt); - if (err) - return err; - -+ if (!IS_ERR(wdt->gpio_wdi)) -+ wdt->ping = max63xx_gpio_ping; -+ - platform_set_drvdata(pdev, &wdt->wdd); - watchdog_set_drvdata(&wdt->wdd, wdt); - diff --git a/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch b/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch deleted file mode 100644 index 1adfd22e87..0000000000 --- a/target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch +++ /dev/null @@ -1,82 +0,0 @@ -From: Tobias Wolf -Subject: mm: Fix alloc_node_mem_map with ARCH_PFN_OFFSET calculation - -An rt288x (ralink) based router (Belkin F5D8235 v1) does not boot with any -kernel beyond version 4.3 resulting in: - -BUG: Bad page state in process swapper pfn:086ac - -bisect resulted in: - -a1c34a3bf00af2cede839879502e12dc68491ad5 is the first bad commit -commit a1c34a3bf00af2cede839879502e12dc68491ad5 -Author: Laura Abbott -Date: Thu Nov 5 18:48:46 2015 -0800 - - mm: Don't offset memmap for flatmem - - Srinivas Kandagatla reported bad page messages when trying to remove the - bottom 2MB on an ARM based IFC6410 board - - BUG: Bad page state in process swapper pfn:fffa8 - page:ef7fb500 count:0 mapcount:0 mapping: (null) index:0x0 - flags: 0x96640253(locked|error|dirty|active|arch_1|reclaim|mlocked) - page dumped because: PAGE_FLAGS_CHECK_AT_FREE flag(s) set - bad because of flags: - flags: 0x200041(locked|active|mlocked) - Modules linked in: - CPU: 0 PID: 0 Comm: swapper Not tainted 3.19.0-rc3-00007-g412f9ba-dirty -#816 - Hardware name: Qualcomm (Flattened Device Tree) - unwind_backtrace - show_stack - dump_stack - bad_page - free_pages_prepare - free_hot_cold_page - __free_pages - free_highmem_page - mem_init - start_kernel - Disabling lock debugging due to kernel taint - [...] -:040000 040000 2de013c372345fd471cd58f0553c9b38b0ef1cc4 -0a8156f848733dfa21e16c196dfb6c0a76290709 M mm - -This fix for ARM does not account ARCH_PFN_OFFSET for mem_map as later used by -page_to_pfn anymore. - -The following output was generated with two hacked in printk statements: - -printk("before %p vs. %p or %p\n", mem_map, mem_map - offset, mem_map - -(pgdat->node_start_pfn - ARCH_PFN_OFFSET)); - if (page_to_pfn(mem_map) != pgdat->node_start_pfn) - mem_map -= offset + (pgdat->node_start_pfn - ARCH_PFN_OFFSET); -printk("after %p\n", mem_map); - -Output: - -[ 0.000000] before 8861b280 vs. 8861b280 or 8851b280 -[ 0.000000] after 8851b280 - -As seen in the first line mem_map with subtraction of offset does not equal the -mem_map after subtraction of ARCH_PFN_OFFSET. - -After adding the offset of ARCH_PFN_OFFSET as well to mem_map as the -previously calculated offset is zero for the named platform it is able to boot -4.4 and 4.9-rc7 again. - -Signed-off-by: Tobias Wolf ---- - ---- a/mm/page_alloc.c -+++ b/mm/page_alloc.c -@@ -7107,7 +7107,7 @@ static void __ref alloc_node_mem_map(str - if (pgdat == NODE_DATA(0)) { - mem_map = NODE_DATA(0)->node_mem_map; - if (page_to_pfn(mem_map) != pgdat->node_start_pfn) -- mem_map -= offset; -+ mem_map -= offset + (pgdat->node_start_pfn - ARCH_PFN_OFFSET); - } - #endif - } diff --git a/target/linux/generic/pending-5.10/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch b/target/linux/generic/pending-5.10/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch deleted file mode 100644 index e48da41fae..0000000000 --- a/target/linux/generic/pending-5.10/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch +++ /dev/null @@ -1,78 +0,0 @@ -From: Felix Fietkau -Subject: jffs2: use .rename2 and add RENAME_WHITEOUT support - -It is required for renames on overlayfs - -Signed-off-by: Felix Fietkau ---- - ---- a/fs/jffs2/dir.c -+++ b/fs/jffs2/dir.c -@@ -609,7 +609,8 @@ static int jffs2_rmdir (struct inode *di - return ret; - } - --static int jffs2_mknod (struct inode *dir_i, struct dentry *dentry, umode_t mode, dev_t rdev) -+static int __jffs2_mknod (struct inode *dir_i, struct dentry *dentry, -+ umode_t mode, dev_t rdev, bool whiteout) - { - struct jffs2_inode_info *f, *dir_f; - struct jffs2_sb_info *c; -@@ -748,7 +749,11 @@ static int jffs2_mknod (struct inode *di - mutex_unlock(&dir_f->sem); - jffs2_complete_reservation(c); - -- d_instantiate_new(dentry, inode); -+ if (!whiteout) -+ d_instantiate_new(dentry, inode); -+ else -+ unlock_new_inode(inode); -+ - return 0; - - fail: -@@ -756,6 +761,17 @@ static int jffs2_mknod (struct inode *di - return ret; - } - -+static int jffs2_mknod (struct inode *dir_i, struct dentry *dentry, umode_t mode, dev_t rdev) -+{ -+ return __jffs2_mknod(dir_i, dentry, mode, rdev, false); -+} -+ -+static int jffs2_whiteout (struct inode *old_dir, struct dentry *old_dentry) -+{ -+ return __jffs2_mknod(old_dir, old_dentry, S_IFCHR | WHITEOUT_MODE, -+ WHITEOUT_DEV, true); -+} -+ - static int jffs2_rename (struct inode *old_dir_i, struct dentry *old_dentry, - struct inode *new_dir_i, struct dentry *new_dentry, - unsigned int flags) -@@ -766,7 +782,7 @@ static int jffs2_rename (struct inode *o - uint8_t type; - uint32_t now; - -- if (flags & ~RENAME_NOREPLACE) -+ if (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT)) - return -EINVAL; - - /* The VFS will check for us and prevent trying to rename a -@@ -832,9 +848,14 @@ static int jffs2_rename (struct inode *o - if (d_is_dir(old_dentry) && !victim_f) - inc_nlink(new_dir_i); - -- /* Unlink the original */ -- ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), -- old_dentry->d_name.name, old_dentry->d_name.len, NULL, now); -+ if (flags & RENAME_WHITEOUT) -+ /* Replace with whiteout */ -+ ret = jffs2_whiteout(old_dir_i, old_dentry); -+ else -+ /* Unlink the original */ -+ ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), -+ old_dentry->d_name.name, -+ old_dentry->d_name.len, NULL, now); - - /* We don't touch inode->i_nlink */ - diff --git a/target/linux/generic/pending-5.10/141-jffs2-add-RENAME_EXCHANGE-support.patch b/target/linux/generic/pending-5.10/141-jffs2-add-RENAME_EXCHANGE-support.patch deleted file mode 100644 index dbc72339c6..0000000000 --- a/target/linux/generic/pending-5.10/141-jffs2-add-RENAME_EXCHANGE-support.patch +++ /dev/null @@ -1,73 +0,0 @@ -From: Felix Fietkau -Subject: jffs2: add RENAME_EXCHANGE support - -Signed-off-by: Felix Fietkau ---- - ---- a/fs/jffs2/dir.c -+++ b/fs/jffs2/dir.c -@@ -779,18 +779,31 @@ static int jffs2_rename (struct inode *o - int ret; - struct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb); - struct jffs2_inode_info *victim_f = NULL; -+ struct inode *fst_inode = d_inode(old_dentry); -+ struct inode *snd_inode = d_inode(new_dentry); - uint8_t type; - uint32_t now; - -- if (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT)) -+ if (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT|RENAME_EXCHANGE)) - return -EINVAL; - -+ if ((flags & RENAME_EXCHANGE) && (old_dir_i != new_dir_i)) { -+ if (S_ISDIR(fst_inode->i_mode) && !S_ISDIR(snd_inode->i_mode)) { -+ inc_nlink(new_dir_i); -+ drop_nlink(old_dir_i); -+ } -+ else if (!S_ISDIR(fst_inode->i_mode) && S_ISDIR(snd_inode->i_mode)) { -+ drop_nlink(new_dir_i); -+ inc_nlink(old_dir_i); -+ } -+ } -+ - /* The VFS will check for us and prevent trying to rename a - * file over a directory and vice versa, but if it's a directory, - * the VFS can't check whether the victim is empty. The filesystem - * needs to do that for itself. - */ -- if (d_really_is_positive(new_dentry)) { -+ if (d_really_is_positive(new_dentry) && !(flags & RENAME_EXCHANGE)) { - victim_f = JFFS2_INODE_INFO(d_inode(new_dentry)); - if (d_is_dir(new_dentry)) { - struct jffs2_full_dirent *fd; -@@ -825,7 +838,7 @@ static int jffs2_rename (struct inode *o - if (ret) - return ret; - -- if (victim_f) { -+ if (victim_f && !(flags & RENAME_EXCHANGE)) { - /* There was a victim. Kill it off nicely */ - if (d_is_dir(new_dentry)) - clear_nlink(d_inode(new_dentry)); -@@ -851,6 +864,12 @@ static int jffs2_rename (struct inode *o - if (flags & RENAME_WHITEOUT) - /* Replace with whiteout */ - ret = jffs2_whiteout(old_dir_i, old_dentry); -+ else if (flags & RENAME_EXCHANGE) -+ /* Replace the original */ -+ ret = jffs2_do_link(c, JFFS2_INODE_INFO(old_dir_i), -+ d_inode(new_dentry)->i_ino, type, -+ old_dentry->d_name.name, old_dentry->d_name.len, -+ now); - else - /* Unlink the original */ - ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), -@@ -882,7 +901,7 @@ static int jffs2_rename (struct inode *o - return ret; - } - -- if (d_is_dir(old_dentry)) -+ if (d_is_dir(old_dentry) && !(flags & RENAME_EXCHANGE)) - drop_nlink(old_dir_i); - - new_dir_i->i_mtime = new_dir_i->i_ctime = old_dir_i->i_mtime = old_dir_i->i_ctime = ITIME(now); diff --git a/target/linux/generic/pending-5.10/142-jffs2-add-splice-ops.patch b/target/linux/generic/pending-5.10/142-jffs2-add-splice-ops.patch deleted file mode 100644 index de847a1f5c..0000000000 --- a/target/linux/generic/pending-5.10/142-jffs2-add-splice-ops.patch +++ /dev/null @@ -1,20 +0,0 @@ -From: Felix Fietkau -Subject: jffs2: add splice ops - -Add splice_read using generic_file_splice_read. -Add splice_write using iter_file_splice_write - -Signed-off-by: Felix Fietkau ---- - ---- a/fs/jffs2/file.c -+++ b/fs/jffs2/file.c -@@ -53,6 +53,8 @@ const struct file_operations jffs2_file_ - .open = generic_file_open, - .read_iter = generic_file_read_iter, - .write_iter = generic_file_write_iter, -+ .splice_read = generic_file_splice_read, -+ .splice_write = iter_file_splice_write, - .unlocked_ioctl=jffs2_ioctl, - .mmap = generic_file_readonly_mmap, - .fsync = jffs2_fsync, diff --git a/target/linux/generic/pending-5.10/150-bridge_allow_receiption_on_disabled_port.patch b/target/linux/generic/pending-5.10/150-bridge_allow_receiption_on_disabled_port.patch deleted file mode 100644 index 8ab4b361f0..0000000000 --- a/target/linux/generic/pending-5.10/150-bridge_allow_receiption_on_disabled_port.patch +++ /dev/null @@ -1,45 +0,0 @@ -From: Stephen Hemminger -Subject: bridge: allow receiption on disabled port - -When an ethernet device is enslaved to a bridge, and the bridge STP -detects loss of carrier (or operational state down), then normally -packet receiption is blocked. - -This breaks control applications like WPA which maybe expecting to -receive packets to negotiate to bring link up. The bridge needs to -block forwarding packets from these disabled ports, but there is no -hard requirement to not allow local packet delivery. - -Signed-off-by: Stephen Hemminger -Signed-off-by: Felix Fietkau - ---- a/net/bridge/br_input.c -+++ b/net/bridge/br_input.c -@@ -202,6 +202,9 @@ static void __br_handle_local_finish(str - /* note: already called with rcu_read_lock */ - static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb) - { -+ struct net_bridge_port *p = br_port_get_rcu(skb->dev); -+ -+ if (p->state != BR_STATE_DISABLED) - __br_handle_local_finish(skb); - - /* return 1 to signal the okfn() was called so it's ok to use the skb */ -@@ -355,6 +358,17 @@ static rx_handler_result_t br_handle_fra - - forward: - switch (p->state) { -+ case BR_STATE_DISABLED: -+ if (ether_addr_equal(p->br->dev->dev_addr, dest)) -+ skb->pkt_type = PACKET_HOST; -+ -+ if (NF_HOOK(NFPROTO_BRIDGE, NF_BR_PRE_ROUTING, -+ dev_net(skb->dev), NULL, skb, skb->dev, NULL, -+ br_handle_local_finish) == 1) { -+ return RX_HANDLER_PASS; -+ } -+ break; -+ - case BR_STATE_FORWARDING: - case BR_STATE_LEARNING: - if (ether_addr_equal(p->br->dev->dev_addr, dest)) diff --git a/target/linux/generic/pending-5.10/190-rtc-rs5c372-support_alarms_up_to_1_week.patch b/target/linux/generic/pending-5.10/190-rtc-rs5c372-support_alarms_up_to_1_week.patch deleted file mode 100644 index 13b79b5c09..0000000000 --- a/target/linux/generic/pending-5.10/190-rtc-rs5c372-support_alarms_up_to_1_week.patch +++ /dev/null @@ -1,94 +0,0 @@ -From: Daniel González Cabanelas -Subject: [PATCH 1/2] rtc: rs5c372: support alarms up to 1 week - -The Ricoh R2221x, R2223x, RS5C372, RV5C387A chips can handle 1 week -alarms. - -Read the "wday" alarm register and convert it to a date to support up 1 -week in our driver. - -Signed-off-by: Daniel González Cabanelas ---- - drivers/rtc/rtc-rs5c372.c | 48 ++++++++++++++++++++++++++++++++++----- - 1 file changed, 42 insertions(+), 6 deletions(-) - ---- a/drivers/rtc/rtc-rs5c372.c -+++ b/drivers/rtc/rtc-rs5c372.c -@@ -393,7 +393,9 @@ static int rs5c_read_alarm(struct device - { - struct i2c_client *client = to_i2c_client(dev); - struct rs5c372 *rs5c = i2c_get_clientdata(client); -- int status; -+ int status, wday_offs; -+ struct rtc_time rtc; -+ unsigned long alarm_secs; - - status = rs5c_get_regs(rs5c); - if (status < 0) -@@ -403,6 +405,30 @@ static int rs5c_read_alarm(struct device - t->time.tm_sec = 0; - t->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f); - t->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]); -+ t->time.tm_wday = ffs(rs5c->regs[RS5C_REG_ALARM_A_WDAY] & 0x7f) - 1; -+ -+ /* determine the day, month and year based on alarm wday, taking as a -+ * reference the current time from the rtc -+ */ -+ status = rs5c372_rtc_read_time(dev, &rtc); -+ if (status < 0) -+ return status; -+ -+ wday_offs = t->time.tm_wday - rtc.tm_wday; -+ alarm_secs = mktime64(rtc.tm_year + 1900, -+ rtc.tm_mon + 1, -+ rtc.tm_mday + wday_offs, -+ t->time.tm_hour, -+ t->time.tm_min, -+ t->time.tm_sec); -+ -+ if (wday_offs < 0 || (wday_offs == 0 && -+ (t->time.tm_hour < rtc.tm_hour || -+ (t->time.tm_hour == rtc.tm_hour && -+ t->time.tm_min <= rtc.tm_min)))) -+ alarm_secs += 7 * 86400; -+ -+ rtc_time64_to_tm(alarm_secs, &t->time); - - /* ... and status */ - t->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE); -@@ -417,12 +443,20 @@ static int rs5c_set_alarm(struct device - struct rs5c372 *rs5c = i2c_get_clientdata(client); - int status, addr, i; - unsigned char buf[3]; -+ struct rtc_time rtc_tm; -+ unsigned long rtc_secs, alarm_secs; - -- /* only handle up to 24 hours in the future, like RTC_ALM_SET */ -- if (t->time.tm_mday != -1 -- || t->time.tm_mon != -1 -- || t->time.tm_year != -1) -+ /* chip only can handle alarms up to one week in the future*/ -+ status = rs5c372_rtc_read_time(dev, &rtc_tm); -+ if (status) -+ return status; -+ rtc_secs = rtc_tm_to_time64(&rtc_tm); -+ alarm_secs = rtc_tm_to_time64(&t->time); -+ if (alarm_secs >= rtc_secs + 7 * 86400) { -+ dev_err(dev, "%s: alarm maximum is one week in the future (%d)\n", -+ __func__, status); - return -EINVAL; -+ } - - /* REVISIT: round up tm_sec */ - -@@ -443,7 +477,9 @@ static int rs5c_set_alarm(struct device - /* set alarm */ - buf[0] = bin2bcd(t->time.tm_min); - buf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour); -- buf[2] = 0x7f; /* any/all days */ -+ /* each bit is the day of the week, 0x7f means all days */ -+ buf[2] = (t->time.tm_wday >= 0 && t->time.tm_wday < 7) ? -+ BIT(t->time.tm_wday) : 0x7f; - - for (i = 0; i < sizeof(buf); i++) { - addr = RS5C_ADDR(RS5C_REG_ALARM_A_MIN + i); diff --git a/target/linux/generic/pending-5.10/191-rtc-rs5c372-let_the_alarm_to_be_used_as_wakeup_source.patch b/target/linux/generic/pending-5.10/191-rtc-rs5c372-let_the_alarm_to_be_used_as_wakeup_source.patch deleted file mode 100644 index 7e9d0e66c0..0000000000 --- a/target/linux/generic/pending-5.10/191-rtc-rs5c372-let_the_alarm_to_be_used_as_wakeup_source.patch +++ /dev/null @@ -1,70 +0,0 @@ -From: Daniel González Cabanelas -Subject: [PATCH 2/2] rtc: rs5c372: let the alarm to be used as wakeup source - -Currently there is no use for the interrupts on the rs5c372 RTC and the -wakealarm isn't enabled. There are some devices like NASes which use this -RTC to wake up from the power off state when the INTR pin is activated by -the alarm clock. - -Enable the alarm and let to be used as a wakeup source. - -Tested on a Buffalo LS421DE NAS. - -Signed-off-by: Daniel González Cabanelas ---- - drivers/rtc/rtc-rs5c372.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/rtc/rtc-rs5c372.c -+++ b/drivers/rtc/rtc-rs5c372.c -@@ -654,6 +654,7 @@ static int rs5c372_probe(struct i2c_clie - int err = 0; - int smbus_mode = 0; - struct rs5c372 *rs5c372; -+ bool rs5c372_can_wakeup_device = false; - - dev_dbg(&client->dev, "%s\n", __func__); - -@@ -689,6 +690,12 @@ static int rs5c372_probe(struct i2c_clie - else - rs5c372->type = id->driver_data; - -+#ifdef CONFIG_OF -+ if(of_property_read_bool(client->dev.of_node, -+ "wakeup-source")) -+ rs5c372_can_wakeup_device = true; -+#endif -+ - /* we read registers 0x0f then 0x00-0x0f; skip the first one */ - rs5c372->regs = &rs5c372->buf[1]; - rs5c372->smbus = smbus_mode; -@@ -722,6 +729,8 @@ static int rs5c372_probe(struct i2c_clie - goto exit; - } - -+ rs5c372->has_irq = 1; -+ - /* if the oscillator lost power and no other software (like - * the bootloader) set it up, do it here. - * -@@ -748,6 +757,10 @@ static int rs5c372_probe(struct i2c_clie - ); - - /* REVISIT use client->irq to register alarm irq ... */ -+ if (rs5c372_can_wakeup_device) { -+ device_init_wakeup(&client->dev, true); -+ } -+ - rs5c372->rtc = devm_rtc_device_register(&client->dev, - rs5c372_driver.driver.name, - &rs5c372_rtc_ops, THIS_MODULE); -@@ -761,6 +774,9 @@ static int rs5c372_probe(struct i2c_clie - if (err) - goto exit; - -+ /* the rs5c372 alarm only supports a minute accuracy */ -+ rs5c372->rtc->uie_unsupported = 1; -+ - return 0; - - exit: diff --git a/target/linux/generic/pending-5.10/203-kallsyms_uncompressed.patch b/target/linux/generic/pending-5.10/203-kallsyms_uncompressed.patch deleted file mode 100644 index 190ce0720d..0000000000 --- a/target/linux/generic/pending-5.10/203-kallsyms_uncompressed.patch +++ /dev/null @@ -1,119 +0,0 @@ -From: Felix Fietkau -Subject: kernel: add a config option for keeping the kallsyms table uncompressed, saving ~9kb kernel size after lzma on ar71xx - -[john@phrozen.org: added to my upstream queue 30.12.2016] -lede-commit: e0e3509b5ce2ccf93d4d67ea907613f5f7ec2eed -Signed-off-by: Felix Fietkau ---- - init/Kconfig | 11 +++++++++++ - kernel/kallsyms.c | 8 ++++++++ - scripts/kallsyms.c | 12 ++++++++++++ - scripts/link-vmlinux.sh | 4 ++++ - 4 files changed, 35 insertions(+) - ---- a/init/Kconfig -+++ b/init/Kconfig -@@ -1401,6 +1401,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW - the unaligned access emulation. - see arch/parisc/kernel/unaligned.c for reference - -+config KALLSYMS_UNCOMPRESSED -+ bool "Keep kallsyms uncompressed" -+ depends on KALLSYMS -+ help -+ Normally kallsyms contains compressed symbols (using a token table), -+ reducing the uncompressed kernel image size. Keeping the symbol table -+ uncompressed significantly improves the size of this part in compressed -+ kernel images. -+ -+ Say N unless you need compressed kernel images to be small. -+ - config HAVE_PCSPKR_PLATFORM - bool - ---- a/kernel/kallsyms.c -+++ b/kernel/kallsyms.c -@@ -77,6 +77,11 @@ static unsigned int kallsyms_expand_symb - * For every byte on the compressed symbol data, copy the table - * entry for that byte. - */ -+#ifdef CONFIG_KALLSYMS_UNCOMPRESSED -+ memcpy(result, data + 1, len - 1); -+ result += len - 1; -+ len = 0; -+#endif - while (len) { - tptr = &kallsyms_token_table[kallsyms_token_index[*data]]; - data++; -@@ -109,6 +114,9 @@ tail: - */ - static char kallsyms_get_symbol_type(unsigned int off) - { -+#ifdef CONFIG_KALLSYMS_UNCOMPRESSED -+ return kallsyms_names[off + 1]; -+#endif - /* - * Get just the first code, look it up in the token table, - * and return the first char from this token. ---- a/scripts/kallsyms.c -+++ b/scripts/kallsyms.c -@@ -58,6 +58,7 @@ static struct addr_range percpu_range = - static struct sym_entry **table; - static unsigned int table_size, table_cnt; - static int all_symbols; -+static int uncompressed; - static int absolute_percpu; - static int base_relative; - -@@ -486,6 +487,9 @@ static void write_src(void) - - free(markers); - -+ if (uncompressed) -+ return; -+ - output_label("kallsyms_token_table"); - off = 0; - for (i = 0; i < 256; i++) { -@@ -537,6 +541,9 @@ static unsigned char *find_token(unsigne - { - int i; - -+ if (uncompressed) -+ return NULL; -+ - for (i = 0; i < len - 1; i++) { - if (str[i] == token[0] && str[i+1] == token[1]) - return &str[i]; -@@ -609,6 +616,9 @@ static void optimize_result(void) - { - int i, best; - -+ if (uncompressed) -+ return; -+ - /* using the '\0' symbol last allows compress_symbols to use standard - * fast string functions */ - for (i = 255; i >= 0; i--) { -@@ -773,6 +783,8 @@ int main(int argc, char **argv) - absolute_percpu = 1; - else if (strcmp(argv[i], "--base-relative") == 0) - base_relative = 1; -+ else if (strcmp(argv[i], "--uncompressed") == 0) -+ uncompressed = 1; - else - usage(); - } ---- a/scripts/link-vmlinux.sh -+++ b/scripts/link-vmlinux.sh -@@ -192,6 +192,10 @@ kallsyms() - kallsymopt="${kallsymopt} --base-relative" - fi - -+ if [ -n "${CONFIG_KALLSYMS_UNCOMPRESSED}" ]; then -+ kallsymopt="${kallsymopt} --uncompressed" -+ fi -+ - info KSYMS ${2} - ${NM} -n ${1} | scripts/kallsyms ${kallsymopt} > ${2} - } diff --git a/target/linux/generic/pending-5.10/205-backtrace_module_info.patch b/target/linux/generic/pending-5.10/205-backtrace_module_info.patch deleted file mode 100644 index f1f35c9923..0000000000 --- a/target/linux/generic/pending-5.10/205-backtrace_module_info.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: Felix Fietkau -Subject: kernel: when KALLSYMS is disabled, print module address + size for matching backtrace entries - -[john@phrozen.org: felix will add this to his upstream queue] - -lede-commit 53827cdc824556cda910b23ce5030c363b8f1461 -Signed-off-by: Felix Fietkau ---- - lib/vsprintf.c | 15 +++++++++++---- - 1 file changed, 11 insertions(+), 4 deletions(-) - ---- a/lib/vsprintf.c -+++ b/lib/vsprintf.c -@@ -985,8 +985,10 @@ char *symbol_string(char *buf, char *end - struct printf_spec spec, const char *fmt) - { - unsigned long value; --#ifdef CONFIG_KALLSYMS - char sym[KSYM_SYMBOL_LEN]; -+#ifndef CONFIG_KALLSYMS -+ struct module *mod; -+ int len; - #endif - - if (fmt[1] == 'R') -@@ -1003,8 +1005,14 @@ char *symbol_string(char *buf, char *end - - return string_nocheck(buf, end, sym, spec); - #else -- return special_hex_number(buf, end, value, sizeof(void *)); -+ len = snprintf(sym, sizeof(sym), "0x%lx", value); -+ mod = __module_address(value); -+ if (mod) -+ snprintf(sym + len, sizeof(sym) - len, " [%s@%p+0x%x]", -+ mod->name, mod->core_layout.base, -+ mod->core_layout.size); - #endif -+ return string(buf, end, sym, spec); - } - - static const struct printf_spec default_str_spec = { diff --git a/target/linux/generic/pending-5.10/240-remove-unsane-filenames-from-deps_initramfs-list.patch b/target/linux/generic/pending-5.10/240-remove-unsane-filenames-from-deps_initramfs-list.patch deleted file mode 100644 index 29cfade716..0000000000 --- a/target/linux/generic/pending-5.10/240-remove-unsane-filenames-from-deps_initramfs-list.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: Gabor Juhos -Subject: usr: sanitize deps_initramfs list - -If any filename in the intramfs dependency -list contains a colon, that causes a kernel -build error like this: - -/devel/openwrt/build_dir/linux-ar71xx_generic/linux-3.6.6/usr/Makefile:58: *** multiple target patterns. Stop. -make[5]: *** [usr] Error 2 - -Fix it by removing such filenames from the -deps_initramfs list. - -Signed-off-by: Gabor Juhos -Signed-off-by: Felix Fietkau ---- - usr/Makefile | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - ---- a/usr/Makefile -+++ b/usr/Makefile -@@ -61,6 +61,8 @@ hostprogs := gen_init_cpio - # The dependency list is generated by gen_initramfs.sh -l - -include $(obj)/.initramfs_data.cpio.d - -+deps_initramfs := $(foreach v,$(deps_initramfs),$(if $(findstring :,$(v)),,$(v))) -+ - # do not try to update files included in initramfs - $(deps_initramfs): ; - diff --git a/target/linux/generic/pending-5.10/261-enable_wilink_platform_without_drivers.patch b/target/linux/generic/pending-5.10/261-enable_wilink_platform_without_drivers.patch deleted file mode 100644 index cd31f9d934..0000000000 --- a/target/linux/generic/pending-5.10/261-enable_wilink_platform_without_drivers.patch +++ /dev/null @@ -1,20 +0,0 @@ -From: Imre Kaloz -Subject: [PATCH] hack: net: wireless: make the wl12xx glue code available with - compat-wireless, too - -Signed-off-by: Imre Kaloz ---- - drivers/net/wireless/ti/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/wireless/ti/Kconfig -+++ b/drivers/net/wireless/ti/Kconfig -@@ -20,7 +20,7 @@ source "drivers/net/wireless/ti/wlcore/K - - config WILINK_PLATFORM_DATA - bool "TI WiLink platform data" -- depends on WLCORE_SDIO || WL1251_SDIO -+ depends on WLCORE_SDIO || WL1251_SDIO || ARCH_OMAP2PLUS - default y - help - Small platform data bit needed to pass data to the sdio modules. diff --git a/target/linux/generic/pending-5.10/270-platform-mikrotik-build-bits.patch b/target/linux/generic/pending-5.10/270-platform-mikrotik-build-bits.patch deleted file mode 100644 index df738ef97b..0000000000 --- a/target/linux/generic/pending-5.10/270-platform-mikrotik-build-bits.patch +++ /dev/null @@ -1,31 +0,0 @@ -From c2deb5ef01a0ef09088832744cbace9e239a6ee0 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= -Date: Sat, 28 Mar 2020 12:11:50 +0100 -Subject: [PATCH] generic: platform/mikrotik build bits (5.4) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This patch adds platform/mikrotik kernel build bits - -Signed-off-by: Thibaut VARÈNE ---- - drivers/platform/Kconfig | 2 ++ - drivers/platform/Makefile | 1 + - 2 files changed, 3 insertions(+) - ---- a/drivers/platform/Kconfig -+++ b/drivers/platform/Kconfig -@@ -13,3 +13,5 @@ source "drivers/platform/chrome/Kconfig" - source "drivers/platform/mellanox/Kconfig" - - source "drivers/platform/olpc/Kconfig" -+ -+source "drivers/platform/mikrotik/Kconfig" ---- a/drivers/platform/Makefile -+++ b/drivers/platform/Makefile -@@ -9,3 +9,4 @@ obj-$(CONFIG_MIPS) += mips/ - obj-$(CONFIG_OLPC_EC) += olpc/ - obj-$(CONFIG_GOLDFISH) += goldfish/ - obj-$(CONFIG_CHROME_PLATFORMS) += chrome/ -+obj-$(CONFIG_MIKROTIK) += mikrotik/ diff --git a/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch b/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch deleted file mode 100644 index 706c5dee22..0000000000 --- a/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch +++ /dev/null @@ -1,40 +0,0 @@ -From: Mark Miller -Subject: mips: expose CONFIG_BOOT_RAW - -This exposes the CONFIG_BOOT_RAW symbol in Kconfig. This is needed on -certain Broadcom chipsets running CFE in order to load the kernel. - -Signed-off-by: Mark Miller -Acked-by: Rob Landley ---- ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -1085,9 +1085,6 @@ config FW_ARC - config ARCH_MAY_HAVE_PC_FDC - bool - --config BOOT_RAW -- bool -- - config CEVT_BCM1480 - bool - -@@ -3182,6 +3179,18 @@ choice - bool "Extend builtin kernel arguments with bootloader arguments" - endchoice - -+config BOOT_RAW -+ bool "Enable the kernel to be executed from the load address" -+ default n -+ help -+ Allow the kernel to be executed from the load address for -+ bootloaders which cannot read the ELF format. This places -+ a jump to start_kernel at the load address. -+ -+ If unsure, say N. -+ -+ -+ - endmenu - - config LOCKDEP_SUPPORT diff --git a/target/linux/generic/pending-5.10/301-MIPS-Add-barriers-between-dcache-icache-flushes.patch b/target/linux/generic/pending-5.10/301-MIPS-Add-barriers-between-dcache-icache-flushes.patch deleted file mode 100644 index 726c884027..0000000000 --- a/target/linux/generic/pending-5.10/301-MIPS-Add-barriers-between-dcache-icache-flushes.patch +++ /dev/null @@ -1,71 +0,0 @@ -From e6e6ef4275978823ec3a84133fc91f4ffbef5c84 Mon Sep 17 00:00:00 2001 -From: Paul Burton -Date: Mon, 22 Feb 2016 18:09:44 +0000 -Subject: [PATCH] MIPS: Add barriers between dcache & icache flushes - -Index-based cache operations may be arbitrarily reordered by out of -order CPUs. Thus code which writes back the dcache & then invalidates -the icache using indexed cache ops must include a barrier between -operating on the 2 caches in order to prevent the scenario in which: - - - icache invalidation occurs. - - - icache fetch occurs, due to speculation. - - - dcache writeback occurs. - -If the above were allowed to happen then the icache would contain stale -data. Forcing the dcache writeback to complete before the icache -invalidation avoids this. - -Signed-off-by: Paul Burton -Cc: James Hogan ---- - arch/mips/mm/c-r4k.c | 13 +++++++++++-- - 1 file changed, 11 insertions(+), 2 deletions(-) - ---- a/arch/mips/mm/c-r4k.c -+++ b/arch/mips/mm/c-r4k.c -@@ -515,6 +515,7 @@ static inline void local_r4k___flush_cac - - default: - r4k_blast_dcache(); -+ mb(); /* cache instructions may be reordered */ - r4k_blast_icache(); - break; - } -@@ -595,8 +596,10 @@ static inline void local_r4k_flush_cache - if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) - r4k_blast_dcache(); - /* If executable, blast stale lines from icache */ -- if (exec) -+ if (exec) { -+ mb(); /* cache instructions may be reordered */ - r4k_blast_icache(); -+ } - } - - static void r4k_flush_cache_range(struct vm_area_struct *vma, -@@ -697,8 +700,13 @@ static inline void local_r4k_flush_cache - if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { - vaddr ? r4k_blast_dcache_page(addr) : - r4k_blast_dcache_user_page(addr); -- if (exec && !cpu_icache_snoops_remote_store) -+ if (exec) -+ mb(); /* cache instructions may be reordered */ -+ -+ if (exec && !cpu_icache_snoops_remote_store) { - r4k_blast_scache_page(addr); -+ mb(); /* cache instructions may be reordered */ -+ } - } - if (exec) { - if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { -@@ -765,6 +773,7 @@ static inline void __local_r4k_flush_ica - else - blast_dcache_range(start, end); - } -+ mb(); /* cache instructions may be reordered */ - } - - if (type == R4K_INDEX || diff --git a/target/linux/generic/pending-5.10/302-mips_no_branch_likely.patch b/target/linux/generic/pending-5.10/302-mips_no_branch_likely.patch deleted file mode 100644 index 271923fca8..0000000000 --- a/target/linux/generic/pending-5.10/302-mips_no_branch_likely.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Felix Fietkau -Subject: mips: use -mno-branch-likely for kernel and userspace - -saves ~11k kernel size after lzma and ~12k squashfs size in the - -lede-commit: 41a039f46450ffae9483d6216422098669da2900 -Signed-off-by: Felix Fietkau ---- - arch/mips/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -95,7 +95,7 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin - # machines may also. Since BFD is incredibly buggy with respect to - # crossformat linking we rely on the elf2ecoff tool for format conversion. - # --cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -+cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely - cflags-y += -msoft-float - LDFLAGS_vmlinux += -G 0 -static -n -nostdlib - KBUILD_AFLAGS_MODULE += -mlong-calls diff --git a/target/linux/generic/pending-5.10/305-mips_module_reloc.patch b/target/linux/generic/pending-5.10/305-mips_module_reloc.patch deleted file mode 100644 index 839ba24293..0000000000 --- a/target/linux/generic/pending-5.10/305-mips_module_reloc.patch +++ /dev/null @@ -1,371 +0,0 @@ -From: Felix Fietkau -Subject: mips: replace -mlong-calls with -mno-long-calls to make function calls faster in kernel modules to achieve this, try to - -lede-commit: 3b3d64743ba2a874df9d70cd19e242205b0a788c -Signed-off-by: Felix Fietkau ---- - arch/mips/Makefile | 5 + - arch/mips/include/asm/module.h | 5 + - arch/mips/kernel/module.c | 279 ++++++++++++++++++++++++++++++++++++++++- - 3 files changed, 284 insertions(+), 5 deletions(-) - ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -98,8 +98,18 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin - cflags-y += -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely - cflags-y += -msoft-float - LDFLAGS_vmlinux += -G 0 -static -n -nostdlib -+ifdef CONFIG_64BIT - KBUILD_AFLAGS_MODULE += -mlong-calls - KBUILD_CFLAGS_MODULE += -mlong-calls -+else -+ ifdef CONFIG_DYNAMIC_FTRACE -+ KBUILD_AFLAGS_MODULE += -mlong-calls -+ KBUILD_CFLAGS_MODULE += -mlong-calls -+ else -+ KBUILD_AFLAGS_MODULE += -mno-long-calls -+ KBUILD_CFLAGS_MODULE += -mno-long-calls -+ endif -+endif - - ifeq ($(CONFIG_RELOCATABLE),y) - LDFLAGS_vmlinux += --emit-relocs ---- a/arch/mips/include/asm/module.h -+++ b/arch/mips/include/asm/module.h -@@ -12,6 +12,11 @@ struct mod_arch_specific { - const struct exception_table_entry *dbe_start; - const struct exception_table_entry *dbe_end; - struct mips_hi16 *r_mips_hi16_list; -+ -+ void *phys_plt_tbl; -+ void *virt_plt_tbl; -+ unsigned int phys_plt_offset; -+ unsigned int virt_plt_offset; - }; - - typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ ---- a/arch/mips/kernel/module.c -+++ b/arch/mips/kernel/module.c -@@ -31,14 +31,221 @@ struct mips_hi16 { - static LIST_HEAD(dbe_list); - static DEFINE_SPINLOCK(dbe_lock); - --#ifdef MODULE_START -+/* -+ * Get the potential max trampolines size required of the init and -+ * non-init sections. Only used if we cannot find enough contiguous -+ * physically mapped memory to put the module into. -+ */ -+static unsigned int -+get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs, -+ const char *secstrings, unsigned int symindex, bool is_init) -+{ -+ unsigned long ret = 0; -+ unsigned int i, j; -+ Elf_Sym *syms; -+ -+ /* Everything marked ALLOC (this includes the exported symbols) */ -+ for (i = 1; i < hdr->e_shnum; ++i) { -+ unsigned int info = sechdrs[i].sh_info; -+ -+ if (sechdrs[i].sh_type != SHT_REL -+ && sechdrs[i].sh_type != SHT_RELA) -+ continue; -+ -+ /* Not a valid relocation section? */ -+ if (info >= hdr->e_shnum) -+ continue; -+ -+ /* Don't bother with non-allocated sections */ -+ if (!(sechdrs[info].sh_flags & SHF_ALLOC)) -+ continue; -+ -+ /* If it's called *.init*, and we're not init, we're -+ not interested */ -+ if ((strstr(secstrings + sechdrs[i].sh_name, ".init") != 0) -+ != is_init) -+ continue; -+ -+ syms = (Elf_Sym *) sechdrs[symindex].sh_addr; -+ if (sechdrs[i].sh_type == SHT_REL) { -+ Elf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr; -+ unsigned int size = sechdrs[i].sh_size / sizeof(*rel); -+ -+ for (j = 0; j < size; ++j) { -+ Elf_Sym *sym; -+ -+ if (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26) -+ continue; -+ -+ sym = syms + ELF_MIPS_R_SYM(rel[j]); -+ if (!is_init && sym->st_shndx != SHN_UNDEF) -+ continue; -+ -+ ret += 4 * sizeof(int); -+ } -+ } else { -+ Elf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr; -+ unsigned int size = sechdrs[i].sh_size / sizeof(*rela); -+ -+ for (j = 0; j < size; ++j) { -+ Elf_Sym *sym; -+ -+ if (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26) -+ continue; -+ -+ sym = syms + ELF_MIPS_R_SYM(rela[j]); -+ if (!is_init && sym->st_shndx != SHN_UNDEF) -+ continue; -+ -+ ret += 4 * sizeof(int); -+ } -+ } -+ } -+ -+ return ret; -+} -+ -+#ifndef MODULE_START -+static void *alloc_phys(unsigned long size) -+{ -+ unsigned order; -+ struct page *page; -+ struct page *p; -+ -+ size = PAGE_ALIGN(size); -+ order = get_order(size); -+ -+ page = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN | -+ __GFP_THISNODE, order); -+ if (!page) -+ return NULL; -+ -+ split_page(page, order); -+ -+ /* mark all pages except for the last one */ -+ for (p = page; p + 1 < page + (size >> PAGE_SHIFT); ++p) -+ set_bit(PG_owner_priv_1, &p->flags); -+ -+ for (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p) -+ __free_page(p); -+ -+ return page_address(page); -+} -+#endif -+ -+static void free_phys(void *ptr) -+{ -+ struct page *page; -+ bool free; -+ -+ page = virt_to_page(ptr); -+ do { -+ free = test_and_clear_bit(PG_owner_priv_1, &page->flags); -+ __free_page(page); -+ page++; -+ } while (free); -+} -+ -+ - void *module_alloc(unsigned long size) - { -+#ifdef MODULE_START - return __vmalloc_node_range(size, 1, MODULE_START, MODULE_END, - GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, - __builtin_return_address(0)); -+#else -+ void *ptr; -+ -+ if (size == 0) -+ return NULL; -+ -+ ptr = alloc_phys(size); -+ -+ /* If we failed to allocate physically contiguous memory, -+ * fall back to regular vmalloc. The module loader code will -+ * create jump tables to handle long jumps */ -+ if (!ptr) -+ return vmalloc(size); -+ -+ return ptr; -+#endif - } -+ -+static inline bool is_phys_addr(void *ptr) -+{ -+#ifdef CONFIG_64BIT -+ return (KSEGX((unsigned long)ptr) == CKSEG0); -+#else -+ return (KSEGX(ptr) == KSEG0); - #endif -+} -+ -+/* Free memory returned from module_alloc */ -+void module_memfree(void *module_region) -+{ -+ if (is_phys_addr(module_region)) -+ free_phys(module_region); -+ else -+ vfree(module_region); -+} -+ -+static void *__module_alloc(int size, bool phys) -+{ -+ void *ptr; -+ -+ if (phys) -+ ptr = kmalloc(size, GFP_KERNEL); -+ else -+ ptr = vmalloc(size); -+ return ptr; -+} -+ -+static void __module_free(void *ptr) -+{ -+ if (is_phys_addr(ptr)) -+ kfree(ptr); -+ else -+ vfree(ptr); -+} -+ -+int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, -+ char *secstrings, struct module *mod) -+{ -+ unsigned int symindex = 0; -+ unsigned int core_size, init_size; -+ int i; -+ -+ mod->arch.phys_plt_offset = 0; -+ mod->arch.virt_plt_offset = 0; -+ mod->arch.phys_plt_tbl = NULL; -+ mod->arch.virt_plt_tbl = NULL; -+ -+ if (IS_ENABLED(CONFIG_64BIT)) -+ return 0; -+ -+ for (i = 1; i < hdr->e_shnum; i++) -+ if (sechdrs[i].sh_type == SHT_SYMTAB) -+ symindex = i; -+ -+ core_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false); -+ init_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true); -+ -+ if ((core_size + init_size) == 0) -+ return 0; -+ -+ mod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1); -+ if (!mod->arch.phys_plt_tbl) -+ return -ENOMEM; -+ -+ mod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0); -+ if (!mod->arch.virt_plt_tbl) { -+ __module_free(mod->arch.phys_plt_tbl); -+ mod->arch.phys_plt_tbl = NULL; -+ return -ENOMEM; -+ } -+ -+ return 0; -+} - - static int apply_r_mips_none(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) -@@ -54,9 +261,40 @@ static int apply_r_mips_32(struct module - return 0; - } - -+static Elf_Addr add_plt_entry_to(unsigned *plt_offset, -+ void *start, Elf_Addr v) -+{ -+ unsigned *tramp = start + *plt_offset; -+ *plt_offset += 4 * sizeof(int); -+ -+ /* adjust carry for addiu */ -+ if (v & 0x00008000) -+ v += 0x10000; -+ -+ tramp[0] = 0x3c190000 | (v >> 16); /* lui t9, hi16 */ -+ tramp[1] = 0x27390000 | (v & 0xffff); /* addiu t9, t9, lo16 */ -+ tramp[2] = 0x03200008; /* jr t9 */ -+ tramp[3] = 0x00000000; /* nop */ -+ -+ return (Elf_Addr) tramp; -+} -+ -+static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v) -+{ -+ if (is_phys_addr(location)) -+ return add_plt_entry_to(&me->arch.phys_plt_offset, -+ me->arch.phys_plt_tbl, v); -+ else -+ return add_plt_entry_to(&me->arch.virt_plt_offset, -+ me->arch.virt_plt_tbl, v); -+ -+} -+ - static int apply_r_mips_26(struct module *me, u32 *location, - u32 base, Elf_Addr v, bool rela) - { -+ u32 ofs = base & 0x03ffffff; -+ - if (v % 4) { - pr_err("module %s: dangerous R_MIPS_26 relocation\n", - me->name); -@@ -64,13 +302,17 @@ static int apply_r_mips_26(struct module - } - - if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { -- pr_err("module %s: relocation overflow\n", -- me->name); -- return -ENOEXEC; -+ v = add_plt_entry(me, location, v + (ofs << 2)); -+ if (!v) { -+ pr_err("module %s: relocation overflow\n", -+ me->name); -+ return -ENOEXEC; -+ } -+ ofs = 0; - } - - *location = (*location & ~0x03ffffff) | -- ((base + (v >> 2)) & 0x03ffffff); -+ ((ofs + (v >> 2)) & 0x03ffffff); - - return 0; - } -@@ -446,9 +688,36 @@ int module_finalize(const Elf_Ehdr *hdr, - list_add(&me->arch.dbe_list, &dbe_list); - spin_unlock_irq(&dbe_lock); - } -+ -+ /* Get rid of the fixup trampoline if we're running the module -+ * from physically mapped address space */ -+ if (me->arch.phys_plt_offset == 0) { -+ __module_free(me->arch.phys_plt_tbl); -+ me->arch.phys_plt_tbl = NULL; -+ } -+ if (me->arch.virt_plt_offset == 0) { -+ __module_free(me->arch.virt_plt_tbl); -+ me->arch.virt_plt_tbl = NULL; -+ } -+ - return 0; - } - -+void module_arch_freeing_init(struct module *mod) -+{ -+ if (mod->state == MODULE_STATE_LIVE) -+ return; -+ -+ if (mod->arch.phys_plt_tbl) { -+ __module_free(mod->arch.phys_plt_tbl); -+ mod->arch.phys_plt_tbl = NULL; -+ } -+ if (mod->arch.virt_plt_tbl) { -+ __module_free(mod->arch.virt_plt_tbl); -+ mod->arch.virt_plt_tbl = NULL; -+ } -+} -+ - void module_arch_cleanup(struct module *mod) - { - spin_lock_irq(&dbe_lock); diff --git a/target/linux/generic/pending-5.10/307-mips_highmem_offset.patch b/target/linux/generic/pending-5.10/307-mips_highmem_offset.patch deleted file mode 100644 index e1ada22f34..0000000000 --- a/target/linux/generic/pending-5.10/307-mips_highmem_offset.patch +++ /dev/null @@ -1,19 +0,0 @@ -From: Felix Fietkau -Subject: kernel: adjust mips highmem offset to avoid the need for -mlong-calls on systems with >256M RAM - -Signed-off-by: Felix Fietkau ---- - arch/mips/include/asm/mach-generic/spaces.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/include/asm/mach-generic/spaces.h -+++ b/arch/mips/include/asm/mach-generic/spaces.h -@@ -54,7 +54,7 @@ - * Memory above this physical address will be considered highmem. - */ - #ifndef HIGHMEM_START --#define HIGHMEM_START _AC(0x20000000, UL) -+#define HIGHMEM_START _AC(0x10000000, UL) - #endif - - #endif /* CONFIG_32BIT */ diff --git a/target/linux/generic/pending-5.10/308-mips32r2_tune.patch b/target/linux/generic/pending-5.10/308-mips32r2_tune.patch deleted file mode 100644 index bbea947382..0000000000 --- a/target/linux/generic/pending-5.10/308-mips32r2_tune.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Felix Fietkau -Subject: kernel: add -mtune=34kc to MIPS CFLAGS when building for mips32r2 - -This provides a good tradeoff across at least 24Kc-74Kc, while also -producing smaller code. - -Signed-off-by: Felix Fietkau ---- - arch/mips/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/Makefile -+++ b/arch/mips/Makefile -@@ -174,7 +174,7 @@ cflags-$(CONFIG_CPU_VR41XX) += -march=r4 - cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap - cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap - cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap --cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap -+cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -mtune=34kc -Wa,--trap - cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg - cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap -modd-spreg - cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap diff --git a/target/linux/generic/pending-5.10/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch b/target/linux/generic/pending-5.10/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch deleted file mode 100644 index 794f027f18..0000000000 --- a/target/linux/generic/pending-5.10/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch +++ /dev/null @@ -1,140 +0,0 @@ -From 87ec87c2ad615c1a177cd08ef5fa29fc739f6e50 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sun, 23 Dec 2018 18:06:53 +0100 -Subject: [PATCH] MIPS: Add CPU option reporting to /proc/cpuinfo - -Many MIPS CPUs have optional CPU features which are not activates for -all CPU cores. Print the CPU options which are implemented in the core -in /proc/cpuinfo. This makes it possible to see what features are -supported and which are not supported. This should cover all standard -MIPS extensions, before it only printed information about the main MIPS -ASEs. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/kernel/proc.c | 116 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 116 insertions(+) - ---- a/arch/mips/kernel/proc.c -+++ b/arch/mips/kernel/proc.c -@@ -138,6 +138,120 @@ static int show_cpuinfo(struct seq_file - seq_printf(m, "micromips kernel\t: %s\n", - (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); - } -+ -+ seq_printf(m, "Options implemented\t:"); -+ if (cpu_has_tlb) -+ seq_printf(m, "%s", " tlb"); -+ if (cpu_has_ftlb) -+ seq_printf(m, "%s", " ftlb"); -+ if (cpu_has_tlbinv) -+ seq_printf(m, "%s", " tlbinv"); -+ if (cpu_has_segments) -+ seq_printf(m, "%s", " segments"); -+ if (cpu_has_rixiex) -+ seq_printf(m, "%s", " rixiex"); -+ if (cpu_has_ldpte) -+ seq_printf(m, "%s", " ldpte"); -+ if (cpu_has_maar) -+ seq_printf(m, "%s", " maar"); -+ if (cpu_has_rw_llb) -+ seq_printf(m, "%s", " rw_llb"); -+ if (cpu_has_4kex) -+ seq_printf(m, "%s", " 4kex"); -+ if (cpu_has_3k_cache) -+ seq_printf(m, "%s", " 3k_cache"); -+ if (cpu_has_4k_cache) -+ seq_printf(m, "%s", " 4k_cache"); -+ if (cpu_has_6k_cache) -+ seq_printf(m, "%s", " 6k_cache"); -+ if (cpu_has_8k_cache) -+ seq_printf(m, "%s", " 8k_cache"); -+ if (cpu_has_tx39_cache) -+ seq_printf(m, "%s", " tx39_cache"); -+ if (cpu_has_octeon_cache) -+ seq_printf(m, "%s", " octeon_cache"); -+ if (cpu_has_fpu) -+ seq_printf(m, "%s", " fpu"); -+ if (cpu_has_32fpr) -+ seq_printf(m, "%s", " 32fpr"); -+ if (cpu_has_cache_cdex_p) -+ seq_printf(m, "%s", " cache_cdex_p"); -+ if (cpu_has_cache_cdex_s) -+ seq_printf(m, "%s", " cache_cdex_s"); -+ if (cpu_has_prefetch) -+ seq_printf(m, "%s", " prefetch"); -+ if (cpu_has_mcheck) -+ seq_printf(m, "%s", " mcheck"); -+ if (cpu_has_ejtag) -+ seq_printf(m, "%s", " ejtag"); -+ if (cpu_has_llsc) -+ seq_printf(m, "%s", " llsc"); -+ if (cpu_has_guestctl0ext) -+ seq_printf(m, "%s", " guestctl0ext"); -+ if (cpu_has_guestctl1) -+ seq_printf(m, "%s", " guestctl1"); -+ if (cpu_has_guestctl2) -+ seq_printf(m, "%s", " guestctl2"); -+ if (cpu_has_guestid) -+ seq_printf(m, "%s", " guestid"); -+ if (cpu_has_drg) -+ seq_printf(m, "%s", " drg"); -+ if (cpu_has_rixi) -+ seq_printf(m, "%s", " rixi"); -+ if (cpu_has_lpa) -+ seq_printf(m, "%s", " lpa"); -+ if (cpu_has_mvh) -+ seq_printf(m, "%s", " mvh"); -+ if (cpu_has_vtag_icache) -+ seq_printf(m, "%s", " vtag_icache"); -+ if (cpu_has_dc_aliases) -+ seq_printf(m, "%s", " dc_aliases"); -+ if (cpu_has_ic_fills_f_dc) -+ seq_printf(m, "%s", " ic_fills_f_dc"); -+ if (cpu_has_pindexed_dcache) -+ seq_printf(m, "%s", " pindexed_dcache"); -+ if (cpu_has_userlocal) -+ seq_printf(m, "%s", " userlocal"); -+ if (cpu_has_nofpuex) -+ seq_printf(m, "%s", " nofpuex"); -+ if (cpu_has_vint) -+ seq_printf(m, "%s", " vint"); -+ if (cpu_has_veic) -+ seq_printf(m, "%s", " veic"); -+ if (cpu_has_inclusive_pcaches) -+ seq_printf(m, "%s", " inclusive_pcaches"); -+ if (cpu_has_perf_cntr_intr_bit) -+ seq_printf(m, "%s", " perf_cntr_intr_bit"); -+ if (cpu_has_ufr) -+ seq_printf(m, "%s", " ufr"); -+ if (cpu_has_fre) -+ seq_printf(m, "%s", " fre"); -+ if (cpu_has_cdmm) -+ seq_printf(m, "%s", " cdmm"); -+ if (cpu_has_small_pages) -+ seq_printf(m, "%s", " small_pages"); -+ if (cpu_has_nan_legacy) -+ seq_printf(m, "%s", " nan_legacy"); -+ if (cpu_has_nan_2008) -+ seq_printf(m, "%s", " nan_2008"); -+ if (cpu_has_ebase_wg) -+ seq_printf(m, "%s", " ebase_wg"); -+ if (cpu_has_badinstr) -+ seq_printf(m, "%s", " badinstr"); -+ if (cpu_has_badinstrp) -+ seq_printf(m, "%s", " badinstrp"); -+ if (cpu_has_contextconfig) -+ seq_printf(m, "%s", " contextconfig"); -+ if (cpu_has_perf) -+ seq_printf(m, "%s", " perf"); -+ if (cpu_has_shared_ftlb_ram) -+ seq_printf(m, "%s", " shared_ftlb_ram"); -+ if (cpu_has_shared_ftlb_entries) -+ seq_printf(m, "%s", " shared_ftlb_entries"); -+ if (cpu_has_mipsmt_pertccounters) -+ seq_printf(m, "%s", " mipsmt_pertccounters"); -+ seq_printf(m, "\n"); -+ - seq_printf(m, "shadow register sets\t: %d\n", - cpu_data[n].srsets); - seq_printf(m, "kscratch registers\t: %d\n", diff --git a/target/linux/generic/pending-5.10/310-arm_module_unresolved_weak_sym.patch b/target/linux/generic/pending-5.10/310-arm_module_unresolved_weak_sym.patch deleted file mode 100644 index 191dc6ac3c..0000000000 --- a/target/linux/generic/pending-5.10/310-arm_module_unresolved_weak_sym.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Felix Fietkau -Subject: fix errors in unresolved weak symbols on arm - -lede-commit: 570699d4838a907c3ef9f2819bf19eb72997b32f -Signed-off-by: Felix Fietkau ---- - arch/arm/kernel/module.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm/kernel/module.c -+++ b/arch/arm/kernel/module.c -@@ -105,6 +105,10 @@ apply_relocate(Elf32_Shdr *sechdrs, cons - return -ENOEXEC; - } - -+ if ((IS_ERR_VALUE(sym->st_value) || !sym->st_value) && -+ ELF_ST_BIND(sym->st_info) == STB_WEAK) -+ continue; -+ - loc = dstsec->sh_addr + rel->r_offset; - - switch (ELF32_R_TYPE(rel->r_info)) { diff --git a/target/linux/generic/pending-5.10/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch b/target/linux/generic/pending-5.10/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch deleted file mode 100644 index 2808c95322..0000000000 --- a/target/linux/generic/pending-5.10/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch +++ /dev/null @@ -1,281 +0,0 @@ -From: Yousong Zhou -Subject: MIPS: kexec: Accept command line parameters from userspace. - -Signed-off-by: Yousong Zhou ---- - arch/mips/kernel/machine_kexec.c | 153 +++++++++++++++++++++++++++++++----- - arch/mips/kernel/machine_kexec.h | 20 +++++ - arch/mips/kernel/relocate_kernel.S | 21 +++-- - 3 files changed, 167 insertions(+), 27 deletions(-) - create mode 100644 arch/mips/kernel/machine_kexec.h - ---- a/arch/mips/kernel/machine_kexec.c -+++ b/arch/mips/kernel/machine_kexec.c -@@ -9,14 +9,11 @@ - #include - #include - -+#include - #include - #include -- --extern const unsigned char relocate_new_kernel[]; --extern const size_t relocate_new_kernel_size; -- --extern unsigned long kexec_start_address; --extern unsigned long kexec_indirection_page; -+#include -+#include "machine_kexec.h" - - static unsigned long reboot_code_buffer; - -@@ -30,6 +27,101 @@ void (*_crash_smp_send_stop)(void) = NUL - void (*_machine_kexec_shutdown)(void) = NULL; - void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL; - -+static void machine_kexec_print_args(void) -+{ -+ unsigned long argc = (int)kexec_args[0]; -+ int i; -+ -+ pr_info("kexec_args[0] (argc): %lu\n", argc); -+ pr_info("kexec_args[1] (argv): %p\n", (void *)kexec_args[1]); -+ pr_info("kexec_args[2] (env ): %p\n", (void *)kexec_args[2]); -+ pr_info("kexec_args[3] (desc): %p\n", (void *)kexec_args[3]); -+ -+ for (i = 0; i < argc; i++) { -+ pr_info("kexec_argv[%d] = %p, %s\n", -+ i, kexec_argv[i], kexec_argv[i]); -+ } -+} -+ -+static void machine_kexec_init_argv(struct kimage *image) -+{ -+ void __user *buf = NULL; -+ size_t bufsz; -+ size_t size; -+ int i; -+ -+ bufsz = 0; -+ for (i = 0; i < image->nr_segments; i++) { -+ struct kexec_segment *seg; -+ -+ seg = &image->segment[i]; -+ if (seg->bufsz < 6) -+ continue; -+ -+ if (strncmp((char *) seg->buf, "kexec ", 6)) -+ continue; -+ -+ buf = seg->buf; -+ bufsz = seg->bufsz; -+ break; -+ } -+ -+ if (!buf) -+ return; -+ -+ size = KEXEC_COMMAND_LINE_SIZE; -+ size = min(size, bufsz); -+ if (size < bufsz) -+ pr_warn("kexec command line truncated to %zd bytes\n", size); -+ -+ /* Copy to kernel space */ -+ if (copy_from_user(kexec_argv_buf, buf, size)) -+ pr_warn("kexec command line copy to kernel space failed\n"); -+ -+ kexec_argv_buf[size - 1] = 0; -+} -+ -+static void machine_kexec_parse_argv(struct kimage *image) -+{ -+ char *reboot_code_buffer; -+ int reloc_delta; -+ char *ptr; -+ int argc; -+ int i; -+ -+ ptr = kexec_argv_buf; -+ argc = 0; -+ -+ /* -+ * convert command line string to array of parameters -+ * (as bootloader does). -+ */ -+ while (ptr && *ptr && (KEXEC_MAX_ARGC > argc)) { -+ if (*ptr == ' ') { -+ *ptr++ = '\0'; -+ continue; -+ } -+ -+ kexec_argv[argc++] = ptr; -+ ptr = strchr(ptr, ' '); -+ } -+ -+ if (!argc) -+ return; -+ -+ kexec_args[0] = argc; -+ kexec_args[1] = (unsigned long)kexec_argv; -+ kexec_args[2] = 0; -+ kexec_args[3] = 0; -+ -+ reboot_code_buffer = page_address(image->control_code_page); -+ reloc_delta = reboot_code_buffer - (char *)kexec_relocate_new_kernel; -+ -+ kexec_args[1] += reloc_delta; -+ for (i = 0; i < argc; i++) -+ kexec_argv[i] += reloc_delta; -+} -+ - static void kexec_image_info(const struct kimage *kimage) - { - unsigned long i; -@@ -99,6 +191,18 @@ machine_kexec_prepare(struct kimage *kim - #endif - - kexec_image_info(kimage); -+ /* -+ * Whenever arguments passed from kexec-tools, Init the arguments as -+ * the original ones to try avoiding booting failure. -+ */ -+ -+ kexec_args[0] = fw_arg0; -+ kexec_args[1] = fw_arg1; -+ kexec_args[2] = fw_arg2; -+ kexec_args[3] = fw_arg3; -+ -+ machine_kexec_init_argv(kimage); -+ machine_kexec_parse_argv(kimage); - - if (_machine_kexec_prepare) - return _machine_kexec_prepare(kimage); -@@ -161,7 +265,7 @@ machine_crash_shutdown(struct pt_regs *r - void kexec_nonboot_cpu_jump(void) - { - local_flush_icache_range((unsigned long)relocated_kexec_smp_wait, -- reboot_code_buffer + relocate_new_kernel_size); -+ reboot_code_buffer + KEXEC_RELOCATE_NEW_KERNEL_SIZE); - - relocated_kexec_smp_wait(NULL); - } -@@ -199,7 +303,7 @@ void kexec_reboot(void) - * machine_kexec() CPU. - */ - local_flush_icache_range(reboot_code_buffer, -- reboot_code_buffer + relocate_new_kernel_size); -+ reboot_code_buffer + KEXEC_RELOCATE_NEW_KERNEL_SIZE); - - do_kexec = (void *)reboot_code_buffer; - do_kexec(); -@@ -212,10 +316,12 @@ machine_kexec(struct kimage *image) - unsigned long *ptr; - - reboot_code_buffer = -- (unsigned long)page_address(image->control_code_page); -+ (unsigned long)page_address(image->control_code_page); -+ pr_info("reboot_code_buffer = %p\n", (void *)reboot_code_buffer); - - kexec_start_address = - (unsigned long) phys_to_virt(image->start); -+ pr_info("kexec_start_address = %p\n", (void *)kexec_start_address); - - if (image->type == KEXEC_TYPE_DEFAULT) { - kexec_indirection_page = -@@ -223,9 +329,19 @@ machine_kexec(struct kimage *image) - } else { - kexec_indirection_page = (unsigned long)&image->head; - } -+ pr_info("kexec_indirection_page = %p\n", (void *)kexec_indirection_page); - -- memcpy((void*)reboot_code_buffer, relocate_new_kernel, -- relocate_new_kernel_size); -+ pr_info("Where is memcpy: %p\n", memcpy); -+ pr_info("kexec_relocate_new_kernel = %p, kexec_relocate_new_kernel_end = %p\n", -+ (void *)kexec_relocate_new_kernel, &kexec_relocate_new_kernel_end); -+ pr_info("Copy %lu bytes from %p to %p\n", KEXEC_RELOCATE_NEW_KERNEL_SIZE, -+ (void *)kexec_relocate_new_kernel, (void *)reboot_code_buffer); -+ memcpy((void*)reboot_code_buffer, kexec_relocate_new_kernel, -+ KEXEC_RELOCATE_NEW_KERNEL_SIZE); -+ -+ pr_info("Before _print_args().\n"); -+ machine_kexec_print_args(); -+ pr_info("Before eval loop.\n"); - - /* - * The generic kexec code builds a page list with physical -@@ -256,7 +372,7 @@ machine_kexec(struct kimage *image) - #ifdef CONFIG_SMP - /* All secondary cpus now may jump to kexec_wait cycle */ - relocated_kexec_smp_wait = reboot_code_buffer + -- (void *)(kexec_smp_wait - relocate_new_kernel); -+ (void *)(kexec_smp_wait - kexec_relocate_new_kernel); - smp_wmb(); - atomic_set(&kexec_ready_to_reboot, 1); - #endif ---- /dev/null -+++ b/arch/mips/kernel/machine_kexec.h -@@ -0,0 +1,20 @@ -+#ifndef _MACHINE_KEXEC_H -+#define _MACHINE_KEXEC_H -+ -+#ifndef __ASSEMBLY__ -+extern const unsigned char kexec_relocate_new_kernel[]; -+extern unsigned long kexec_relocate_new_kernel_end; -+extern unsigned long kexec_start_address; -+extern unsigned long kexec_indirection_page; -+ -+extern char kexec_argv_buf[]; -+extern char *kexec_argv[]; -+ -+#define KEXEC_RELOCATE_NEW_KERNEL_SIZE ((unsigned long)&kexec_relocate_new_kernel_end - (unsigned long)kexec_relocate_new_kernel) -+#endif /* !__ASSEMBLY__ */ -+ -+#define KEXEC_COMMAND_LINE_SIZE 256 -+#define KEXEC_ARGV_SIZE (KEXEC_COMMAND_LINE_SIZE / 16) -+#define KEXEC_MAX_ARGC (KEXEC_ARGV_SIZE / sizeof(long)) -+ -+#endif ---- a/arch/mips/kernel/relocate_kernel.S -+++ b/arch/mips/kernel/relocate_kernel.S -@@ -10,8 +10,9 @@ - #include - #include - #include -+#include "machine_kexec.h" - --LEAF(relocate_new_kernel) -+LEAF(kexec_relocate_new_kernel) - PTR_L a0, arg0 - PTR_L a1, arg1 - PTR_L a2, arg2 -@@ -96,7 +97,7 @@ done: - #endif - /* jump to kexec_start_address */ - j s1 -- END(relocate_new_kernel) -+ END(kexec_relocate_new_kernel) - - #ifdef CONFIG_SMP - /* -@@ -182,9 +183,15 @@ kexec_indirection_page: - PTR 0 - .size kexec_indirection_page, PTRSIZE - --relocate_new_kernel_end: -+kexec_argv_buf: -+ EXPORT(kexec_argv_buf) -+ .skip KEXEC_COMMAND_LINE_SIZE -+ .size kexec_argv_buf, KEXEC_COMMAND_LINE_SIZE -+ -+kexec_argv: -+ EXPORT(kexec_argv) -+ .skip KEXEC_ARGV_SIZE -+ .size kexec_argv, KEXEC_ARGV_SIZE - --relocate_new_kernel_size: -- EXPORT(relocate_new_kernel_size) -- PTR relocate_new_kernel_end - relocate_new_kernel -- .size relocate_new_kernel_size, PTRSIZE -+kexec_relocate_new_kernel_end: -+ EXPORT(kexec_relocate_new_kernel_end) diff --git a/target/linux/generic/pending-5.10/332-arc-add-OWRTDTB-section.patch b/target/linux/generic/pending-5.10/332-arc-add-OWRTDTB-section.patch deleted file mode 100644 index 4a76e216d5..0000000000 --- a/target/linux/generic/pending-5.10/332-arc-add-OWRTDTB-section.patch +++ /dev/null @@ -1,84 +0,0 @@ -From bb0c3b0175240bf152fd7c644821a0cf9f77c37c Mon Sep 17 00:00:00 2001 -From: Evgeniy Didin -Date: Fri, 15 Mar 2019 18:53:38 +0300 -Subject: [PATCH] arc add OWRTDTB section - -This change allows OpenWRT to patch resulting kernel binary with -external .dtb. - -That allows us to re-use exactky the same vmlinux on different boards -given its ARC core configurations match (at least cache line sizes etc). - -""patch-dtb" searches for ASCII "OWRTDTB:" strign and copies external -.dtb right after it, keeping the string in place. - -Signed-off-by: Eugeniy Paltsev -Signed-off-by: Alexey Brodkin -Signed-off-by: Evgeniy Didin ---- - arch/arc/kernel/head.S | 10 ++++++++++ - arch/arc/kernel/setup.c | 4 +++- - arch/arc/kernel/vmlinux.lds.S | 13 +++++++++++++ - 3 files changed, 26 insertions(+), 1 deletion(-) - ---- a/arch/arc/kernel/head.S -+++ b/arch/arc/kernel/head.S -@@ -88,6 +88,16 @@ - DSP_EARLY_INIT - .endm - -+ ; Here "patch-dtb" will embed external .dtb -+ ; Note "patch-dtb" searches for ASCII "OWRTDTB:" string -+ ; and pastes .dtb right after it, hense the string precedes -+ ; __image_dtb symbol. -+ .section .owrt, "aw",@progbits -+ .ascii "OWRTDTB:" -+ENTRY(__image_dtb) -+ .fill 0x4000 -+END(__image_dtb) -+ - .section .init.text, "ax",@progbits - - ;---------------------------------------------------------------- ---- a/arch/arc/kernel/setup.c -+++ b/arch/arc/kernel/setup.c -@@ -495,6 +495,8 @@ static inline bool uboot_arg_invalid(uns - /* We always pass 0 as magic from U-boot */ - #define UBOOT_MAGIC_VALUE 0 - -+extern struct boot_param_header __image_dtb; -+ - void __init handle_uboot_args(void) - { - bool use_embedded_dtb = true; -@@ -533,7 +535,7 @@ void __init handle_uboot_args(void) - ignore_uboot_args: - - if (use_embedded_dtb) { -- machine_desc = setup_machine_fdt(__dtb_start); -+ machine_desc = setup_machine_fdt(&__image_dtb); - if (!machine_desc) - panic("Embedded DT invalid\n"); - } ---- a/arch/arc/kernel/vmlinux.lds.S -+++ b/arch/arc/kernel/vmlinux.lds.S -@@ -27,6 +27,19 @@ SECTIONS - - . = CONFIG_LINUX_LINK_BASE; - -+ /* -+ * In OpenWRT we want to patch built binary embedding .dtb of choice. -+ * This is implemented with "patch-dtb" utility which searches for -+ * "OWRTDTB:" string in first 16k of image and if it is found -+ * copies .dtb right after mentioned string. -+ * -+ * Note: "OWRTDTB:" won't be overwritten with .dtb, .dtb will follow it. -+ */ -+ .owrt : { -+ *(.owrt) -+ . = ALIGN(PAGE_SIZE); -+ } -+ - _int_vec_base_lds = .; - .vector : { - *(.vector) diff --git a/target/linux/generic/pending-5.10/333-arc-enable-unaligned-access-in-kernel-mode.patch b/target/linux/generic/pending-5.10/333-arc-enable-unaligned-access-in-kernel-mode.patch deleted file mode 100644 index 1848a84cc4..0000000000 --- a/target/linux/generic/pending-5.10/333-arc-enable-unaligned-access-in-kernel-mode.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: Alexey Brodkin -Subject: arc: enable unaligned access in kernel mode - -This enables misaligned access handling even in kernel mode. -Some wireless drivers (ath9k-htc and mt7601u) use misaligned accesses -here and there and to cope with that without fixing stuff in the drivers -we're just gracefully handling it on ARC. - -Signed-off-by: Alexey Brodkin ---- - arch/arc/kernel/unaligned.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arc/kernel/unaligned.c -+++ b/arch/arc/kernel/unaligned.c -@@ -202,7 +202,7 @@ int misaligned_fixup(unsigned long addre - char buf[TASK_COMM_LEN]; - - /* handle user mode only and only if enabled by sysadmin */ -- if (!user_mode(regs) || !unaligned_enabled) -+ if (!unaligned_enabled) - return 1; - - if (no_unaligned_warning) { diff --git a/target/linux/generic/pending-5.10/342-powerpc-Enable-kernel-XZ-compression-option-on-PPC_8.patch b/target/linux/generic/pending-5.10/342-powerpc-Enable-kernel-XZ-compression-option-on-PPC_8.patch deleted file mode 100644 index 6792a66f8a..0000000000 --- a/target/linux/generic/pending-5.10/342-powerpc-Enable-kernel-XZ-compression-option-on-PPC_8.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 66770a004afe10df11d3902e16eaa0c2c39436bb Mon Sep 17 00:00:00 2001 -From: Pawel Dembicki -Date: Fri, 24 May 2019 17:56:19 +0200 -Subject: [PATCH] powerpc: Enable kernel XZ compression option on PPC_85xx - -Enable kernel XZ compression option on PPC_85xx. Tested with -simpleImage on TP-Link TL-WDR4900 (Freescale P1014 processor). - -Suggested-by: Christian Lamparter -Signed-off-by: Pawel Dembicki ---- - arch/powerpc/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/powerpc/Kconfig -+++ b/arch/powerpc/Kconfig -@@ -214,7 +214,7 @@ config PPC - select HAVE_KERNEL_GZIP - select HAVE_KERNEL_LZMA if DEFAULT_UIMAGE - select HAVE_KERNEL_LZO if DEFAULT_UIMAGE -- select HAVE_KERNEL_XZ if PPC_BOOK3S || 44x -+ select HAVE_KERNEL_XZ if PPC_BOOK3S || 44x || PPC_85xx - select HAVE_KPROBES - select HAVE_KPROBES_ON_FTRACE - select HAVE_KRETPROBES diff --git a/target/linux/generic/pending-5.10/400-mtd-mtdsplit-support.patch b/target/linux/generic/pending-5.10/400-mtd-mtdsplit-support.patch deleted file mode 100644 index 89cac88717..0000000000 --- a/target/linux/generic/pending-5.10/400-mtd-mtdsplit-support.patch +++ /dev/null @@ -1,337 +0,0 @@ -From: Gabor Juhos -Subject: mtd: Add new Kconfig option for firmware partition split - -Add a new kernel config option for generic firmware partition -split support and change the uImage split support to depend on -the new option. Aslo rename the MTD_UIMAGE_SPLIT_NAME option to -MTD_SPLIT_FIRMWARE_NAME to make it more generic. - -The patch is in preparation for multiple firmware format -support. - -Submitted-by: Gabor Juhos - -SVN-Revision: 38002 ---- - drivers/mtd/Kconfig | 19 + - drivers/mtd/mtdpart.c | 144 +++++++++++++----- - include/linux/mtd/partitions.h | 7 + - drivers/mtd/Makefile | 2 + - include/linux/mtd/mtd.h | 25 + - 5 files changed, 171 insertions(+), 25 deletions(-) - ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -12,6 +12,25 @@ menuconfig MTD - - if MTD - -+menu "OpenWrt specific MTD options" -+ -+config MTD_ROOTFS_ROOT_DEV -+ bool "Automatically set 'rootfs' partition to be root filesystem" -+ default y -+ -+config MTD_SPLIT_FIRMWARE -+ bool "Automatically split firmware partition for kernel+rootfs" -+ default y -+ -+config MTD_SPLIT_FIRMWARE_NAME -+ string "Firmware partition name" -+ depends on MTD_SPLIT_FIRMWARE -+ default "firmware" -+ -+source "drivers/mtd/mtdsplit/Kconfig" -+ -+endmenu -+ - config MTD_TESTS - tristate "MTD tests support (DANGEROUS)" - depends on m ---- a/drivers/mtd/mtdpart.c -+++ b/drivers/mtd/mtdpart.c -@@ -15,11 +15,13 @@ - #include - #include - #include -+#include - #include - #include - #include - - #include "mtdcore.h" -+#include "mtdsplit/mtdsplit.h" - - /* - * MTD methods which simply translate the effective address and pass through -@@ -237,6 +239,147 @@ static int mtd_add_partition_attrs(struc - return ret; - } - -+static DEFINE_SPINLOCK(part_parser_lock); -+static LIST_HEAD(part_parsers); -+ -+static struct mtd_part_parser *mtd_part_parser_get(const char *name) -+{ -+ struct mtd_part_parser *p, *ret = NULL; -+ -+ spin_lock(&part_parser_lock); -+ -+ list_for_each_entry(p, &part_parsers, list) -+ if (!strcmp(p->name, name) && try_module_get(p->owner)) { -+ ret = p; -+ break; -+ } -+ -+ spin_unlock(&part_parser_lock); -+ -+ return ret; -+} -+ -+static inline void mtd_part_parser_put(const struct mtd_part_parser *p) -+{ -+ module_put(p->owner); -+} -+ -+static struct mtd_part_parser * -+get_partition_parser_by_type(enum mtd_parser_type type, -+ struct mtd_part_parser *start) -+{ -+ struct mtd_part_parser *p, *ret = NULL; -+ -+ spin_lock(&part_parser_lock); -+ -+ p = list_prepare_entry(start, &part_parsers, list); -+ if (start) -+ mtd_part_parser_put(start); -+ -+ list_for_each_entry_continue(p, &part_parsers, list) { -+ if (p->type == type && try_module_get(p->owner)) { -+ ret = p; -+ break; -+ } -+ } -+ -+ spin_unlock(&part_parser_lock); -+ -+ return ret; -+} -+ -+static int parse_mtd_partitions_by_type(struct mtd_info *master, -+ enum mtd_parser_type type, -+ const struct mtd_partition **pparts, -+ struct mtd_part_parser_data *data) -+{ -+ struct mtd_part_parser *prev = NULL; -+ int ret = 0; -+ -+ while (1) { -+ struct mtd_part_parser *parser; -+ -+ parser = get_partition_parser_by_type(type, prev); -+ if (!parser) -+ break; -+ -+ ret = (*parser->parse_fn)(master, pparts, data); -+ -+ if (ret > 0) { -+ mtd_part_parser_put(parser); -+ printk(KERN_NOTICE -+ "%d %s partitions found on MTD device %s\n", -+ ret, parser->name, master->name); -+ break; -+ } -+ -+ prev = parser; -+ } -+ -+ return ret; -+} -+ -+static int -+run_parsers_by_type(struct mtd_info *child, enum mtd_parser_type type) -+{ -+ struct mtd_partition *parts; -+ int nr_parts; -+ int i; -+ -+ nr_parts = parse_mtd_partitions_by_type(child, type, (const struct mtd_partition **)&parts, -+ NULL); -+ if (nr_parts <= 0) -+ return nr_parts; -+ -+ if (WARN_ON(!parts)) -+ return 0; -+ -+ for (i = 0; i < nr_parts; i++) { -+ /* adjust partition offsets */ -+ parts[i].offset += child->part.offset; -+ -+ mtd_add_partition(child->parent, -+ parts[i].name, -+ parts[i].offset, -+ parts[i].size); -+ } -+ -+ kfree(parts); -+ -+ return nr_parts; -+} -+ -+#ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME -+#define SPLIT_FIRMWARE_NAME CONFIG_MTD_SPLIT_FIRMWARE_NAME -+#else -+#define SPLIT_FIRMWARE_NAME "unused" -+#endif -+ -+static void split_firmware(struct mtd_info *master, struct mtd_info *part) -+{ -+ run_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE); -+} -+ -+static void mtd_partition_split(struct mtd_info *master, struct mtd_info *part) -+{ -+ static int rootfs_found = 0; -+ -+ if (rootfs_found) -+ return; -+ -+ if (of_find_property(mtd_get_of_node(part), "linux,rootfs", NULL) || -+ !strcmp(part->name, "rootfs")) { -+ run_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS); -+ -+ rootfs_found = 1; -+ } -+ -+ if (IS_ENABLED(CONFIG_MTD_SPLIT_FIRMWARE) && -+ !strcmp(part->name, SPLIT_FIRMWARE_NAME) && -+ !of_find_property(mtd_get_of_node(part), "compatible", NULL)) -+ split_firmware(master, part); -+} -+ - int mtd_add_partition(struct mtd_info *parent, const char *name, - long long offset, long long length) - { -@@ -275,6 +418,7 @@ int mtd_add_partition(struct mtd_info *p - if (ret) - goto err_remove_part; - -+ mtd_partition_split(parent, child); - mtd_add_partition_attrs(child); - - return 0; -@@ -423,6 +567,7 @@ int add_mtd_partitions(struct mtd_info * - goto err_del_partitions; - } - -+ mtd_partition_split(master, child); - mtd_add_partition_attrs(child); - - /* Look for subpartitions */ -@@ -439,31 +584,6 @@ err_del_partitions: - return ret; - } - --static DEFINE_SPINLOCK(part_parser_lock); --static LIST_HEAD(part_parsers); -- --static struct mtd_part_parser *mtd_part_parser_get(const char *name) --{ -- struct mtd_part_parser *p, *ret = NULL; -- -- spin_lock(&part_parser_lock); -- -- list_for_each_entry(p, &part_parsers, list) -- if (!strcmp(p->name, name) && try_module_get(p->owner)) { -- ret = p; -- break; -- } -- -- spin_unlock(&part_parser_lock); -- -- return ret; --} -- --static inline void mtd_part_parser_put(const struct mtd_part_parser *p) --{ -- module_put(p->owner); --} -- - /* - * Many partition parsers just expected the core to kfree() all their data in - * one chunk. Do that by default. ---- a/include/linux/mtd/partitions.h -+++ b/include/linux/mtd/partitions.h -@@ -75,6 +75,12 @@ struct mtd_part_parser_data { - * Functions dealing with the various ways of partitioning the space - */ - -+enum mtd_parser_type { -+ MTD_PARSER_TYPE_DEVICE = 0, -+ MTD_PARSER_TYPE_ROOTFS, -+ MTD_PARSER_TYPE_FIRMWARE, -+}; -+ - struct mtd_part_parser { - struct list_head list; - struct module *owner; -@@ -83,6 +89,7 @@ struct mtd_part_parser { - int (*parse_fn)(struct mtd_info *, const struct mtd_partition **, - struct mtd_part_parser_data *); - void (*cleanup)(const struct mtd_partition *pparts, int nr_parts); -+ enum mtd_parser_type type; - }; - - /* Container for passing around a set of parsed partitions */ ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -9,6 +9,8 @@ mtd-y := mtdcore.o mtdsuper.o mtdconc - - obj-y += parsers/ - -+obj-$(CONFIG_MTD_SPLIT) += mtdsplit/ -+ - # 'Users' - code which presents functionality to userspace. - obj-$(CONFIG_MTD_BLKDEVS) += mtd_blkdevs.o - obj-$(CONFIG_MTD_BLOCK) += mtdblock.o ---- a/include/linux/mtd/mtd.h -+++ b/include/linux/mtd/mtd.h -@@ -606,6 +606,24 @@ static inline void mtd_align_erase_req(s - req->len += mtd->erasesize - mod; - } - -+static inline uint64_t mtd_roundup_to_eb(uint64_t sz, struct mtd_info *mtd) -+{ -+ if (mtd_mod_by_eb(sz, mtd) == 0) -+ return sz; -+ -+ /* Round up to next erase block */ -+ return (mtd_div_by_eb(sz, mtd) + 1) * mtd->erasesize; -+} -+ -+static inline uint64_t mtd_rounddown_to_eb(uint64_t sz, struct mtd_info *mtd) -+{ -+ if (mtd_mod_by_eb(sz, mtd) == 0) -+ return sz; -+ -+ /* Round down to the start of the current erase block */ -+ return (mtd_div_by_eb(sz, mtd)) * mtd->erasesize; -+} -+ - static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd) - { - if (mtd->writesize_shift) -@@ -679,6 +697,13 @@ extern struct mtd_info *of_get_mtd_devic - extern struct mtd_info *get_mtd_device_nm(const char *name); - extern void put_mtd_device(struct mtd_info *mtd); - -+static inline uint64_t mtdpart_get_offset(const struct mtd_info *mtd) -+{ -+ if (!mtd_is_partition(mtd)) -+ return 0; -+ -+ return mtd->part.offset; -+} - - struct mtd_notifier { - void (*add)(struct mtd_info *mtd); diff --git a/target/linux/generic/pending-5.10/402-mtd-spi-nor-write-support-for-minor-aligned-partitions.patch b/target/linux/generic/pending-5.10/402-mtd-spi-nor-write-support-for-minor-aligned-partitions.patch deleted file mode 100644 index c9bb4a14a4..0000000000 --- a/target/linux/generic/pending-5.10/402-mtd-spi-nor-write-support-for-minor-aligned-partitions.patch +++ /dev/null @@ -1,245 +0,0 @@ -From cd13e2cd28bf7313b6ad6986bb8d63ea98b37a48 Mon Sep 17 00:00:00 2001 -From: John Thomson -Date: Fri, 25 Dec 2020 18:50:08 +1000 -Subject: [PATCH] mtd: spi-nor: write support for minor aligned partitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Do not prevent writing to mtd partitions where a partition boundary sits -on a minor erasesize boundary. -This addresses a FIXME that has been present since the start of the -linux git history: -/* Doesn't start on a boundary of major erase size */ -/* FIXME: Let it be writable if it is on a boundary of - * _minor_ erase size though */ - -Allow a uniform erase region spi-nor device to be configured -to use the non-uniform erase regions code path for an erase with: -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y - -On supporting hardware (SECT_4K: majority of current SPI-NOR device) -provide the facility for an erase to use the least number -of SPI-NOR operations, as well as access to 4K erase without -requiring CONFIG_MTD_SPI_NOR_USE_4K_SECTORS - -Introduce erasesize_minor to the mtd struct, -the smallest erasesize supported by the device - -On existing devices, this is useful where write support is wanted -for data on a 4K partition, such as some u-boot-env partitions, -or RouterBoot soft_config, while still netting the performance -benefits of using 64K sectors - -Performance: -time mtd erase firmware -OpenWrt 5.10 ramips MT7621 w25q128jv 0xfc0000 partition length - -Without this patch -MTD_SPI_NOR_USE_4K_SECTORS=y |n -real 2m 11.66s |0m 50.86s -user 0m 0.00s |0m 0.00s -sys 1m 56.20s |0m 50.80s - -With this patch -MTD_SPI_NOR_USE_VARIABLE_ERASE=n|y |4K_SECTORS=y -real 0m 51.68s |0m 50.85s |2m 12.89s -user 0m 0.00s |0m 0.00s |0m 0.01s -sys 0m 46.94s |0m 50.38s |2m 12.46s - -Signed-off-by: John Thomson -Signed-off-by: Thibaut VARÈNE - ---- - -checkpatch does not like the printk(KERN_WARNING -these should be changed separately beforehand? - -Changes v1 -> v2: -Added mtdcore sysfs for erasesize_minor -Removed finding minor erasesize for variable erase regions device, -as untested and no responses regarding it. -Moved IF_ENABLED for SPINOR variable erase to guard setting -erasesize_minor in spi-nor/core.c -Removed setting erasesize to minor where partition boundaries require -minor erase to be writable -Simplified minor boundary check by relying on minor being a factor of -major - -Changes RFC -> v1: -Fix uninitialized variable smatch warning -Reported-by: kernel test robot -Reported-by: Dan Carpenter ---- - drivers/mtd/mtdcore.c | 10 ++++++++++ - drivers/mtd/mtdpart.c | 35 +++++++++++++++++++++++++---------- - drivers/mtd/spi-nor/Kconfig | 10 ++++++++++ - drivers/mtd/spi-nor/core.c | 11 +++++++++-- - include/linux/mtd/mtd.h | 2 ++ - 5 files changed, 56 insertions(+), 12 deletions(-) - ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -164,6 +164,15 @@ static ssize_t mtd_erasesize_show(struct - } - static DEVICE_ATTR(erasesize, S_IRUGO, mtd_erasesize_show, NULL); - -+static ssize_t mtd_erasesize_minor_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct mtd_info *mtd = dev_get_drvdata(dev); -+ -+ return snprintf(buf, PAGE_SIZE, "%lu\n", (unsigned long)mtd->erasesize_minor); -+} -+static DEVICE_ATTR(erasesize_minor, S_IRUGO, mtd_erasesize_minor_show, NULL); -+ - static ssize_t mtd_writesize_show(struct device *dev, - struct device_attribute *attr, char *buf) - { -@@ -313,6 +322,7 @@ static struct attribute *mtd_attrs[] = { - &dev_attr_flags.attr, - &dev_attr_size.attr, - &dev_attr_erasesize.attr, -+ &dev_attr_erasesize_minor.attr, - &dev_attr_writesize.attr, - &dev_attr_subpagesize.attr, - &dev_attr_oobsize.attr, ---- a/drivers/mtd/mtdpart.c -+++ b/drivers/mtd/mtdpart.c -@@ -41,6 +41,7 @@ static struct mtd_info *allocate_partiti - struct mtd_info *master = mtd_get_master(parent); - int wr_alignment = (parent->flags & MTD_NO_ERASE) ? - master->writesize : master->erasesize; -+ int wr_alignment_minor = 0; - u64 parent_size = mtd_is_partition(parent) ? - parent->part.size : parent->size; - struct mtd_info *child; -@@ -165,6 +166,7 @@ static struct mtd_info *allocate_partiti - } else { - /* Single erase size */ - child->erasesize = master->erasesize; -+ child->erasesize_minor = master->erasesize_minor; - } - - /* -@@ -172,26 +174,39 @@ static struct mtd_info *allocate_partiti - * exposes several regions with different erasesize. Adjust - * wr_alignment accordingly. - */ -- if (!(child->flags & MTD_NO_ERASE)) -+ if (!(child->flags & MTD_NO_ERASE)) { - wr_alignment = child->erasesize; -+ wr_alignment_minor = child->erasesize_minor; -+ } - - tmp = mtd_get_master_ofs(child, 0); - remainder = do_div(tmp, wr_alignment); - if ((child->flags & MTD_WRITEABLE) && remainder) { -- /* Doesn't start on a boundary of major erase size */ -- /* FIXME: Let it be writable if it is on a boundary of -- * _minor_ erase size though */ -- child->flags &= ~MTD_WRITEABLE; -- printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase/write block boundary -- force read-only\n", -- part->name); -+ if (wr_alignment_minor) { -+ /* rely on minor being a factor of major erasesize */ -+ tmp = remainder; -+ remainder = do_div(tmp, wr_alignment_minor); -+ } -+ if (remainder) { -+ child->flags &= ~MTD_WRITEABLE; -+ printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase/write block boundary -- force read-only\n", -+ part->name); -+ } - } - - tmp = mtd_get_master_ofs(child, 0) + child->part.size; - remainder = do_div(tmp, wr_alignment); - if ((child->flags & MTD_WRITEABLE) && remainder) { -- child->flags &= ~MTD_WRITEABLE; -- printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase/write block -- force read-only\n", -- part->name); -+ if (wr_alignment_minor) { -+ tmp = remainder; -+ remainder = do_div(tmp, wr_alignment_minor); -+ } -+ -+ if (remainder) { -+ child->flags &= ~MTD_WRITEABLE; -+ printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase/write block -- force read-only\n", -+ part->name); -+ } - } - - child->size = child->part.size; ---- a/drivers/mtd/spi-nor/Kconfig -+++ b/drivers/mtd/spi-nor/Kconfig -@@ -10,6 +10,16 @@ menuconfig MTD_SPI_NOR - - if MTD_SPI_NOR - -+config MTD_SPI_NOR_USE_VARIABLE_ERASE -+ bool "Disable uniform_erase to allow use of all hardware supported erasesizes" -+ depends on !MTD_SPI_NOR_USE_4K_SECTORS -+ default n -+ help -+ Allow mixed use of all hardware supported erasesizes, -+ by forcing spi_nor to use the multiple eraseregions code path. -+ For example: A 68K erase will use one 64K erase, and one 4K erase -+ on supporting hardware. -+ - config MTD_SPI_NOR_USE_4K_SECTORS - bool "Use small 4096 B erase sectors" - default y ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -1084,6 +1084,8 @@ static u8 spi_nor_convert_3to4_erase(u8 - - static bool spi_nor_has_uniform_erase(const struct spi_nor *nor) - { -+ if (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE)) -+ return false; - return !!nor->params->erase_map.uniform_erase_type; - } - -@@ -2580,6 +2582,7 @@ static int spi_nor_select_erase(struct s - { - struct spi_nor_erase_map *map = &nor->params->erase_map; - const struct spi_nor_erase_type *erase = NULL; -+ const struct spi_nor_erase_type *erase_minor = NULL; - struct mtd_info *mtd = &nor->mtd; - u32 wanted_size = nor->info->sector_size; - int i; -@@ -2612,8 +2615,9 @@ static int spi_nor_select_erase(struct s - */ - for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) { - if (map->erase_type[i].size) { -- erase = &map->erase_type[i]; -- break; -+ if (!erase) -+ erase = &map->erase_type[i]; -+ erase_minor = &map->erase_type[i]; - } - } - -@@ -2621,6 +2625,9 @@ static int spi_nor_select_erase(struct s - return -EINVAL; - - mtd->erasesize = erase->size; -+ if (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE) && -+ erase_minor && erase_minor->size < erase->size) -+ mtd->erasesize_minor = erase_minor->size; - return 0; - } - ---- a/include/linux/mtd/mtd.h -+++ b/include/linux/mtd/mtd.h -@@ -242,6 +242,8 @@ struct mtd_info { - * information below if they desire - */ - uint32_t erasesize; -+ /* "Minor" (smallest) erase size supported by the whole device */ -+ uint32_t erasesize_minor; - /* Minimal writable flash unit size. In case of NOR flash it is 1 (even - * though individual bits can be cleared), in case of NAND flash it is - * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR diff --git a/target/linux/generic/pending-5.10/410-mtd-parsers-ofpart-fix-parsing-subpartitions.patch b/target/linux/generic/pending-5.10/410-mtd-parsers-ofpart-fix-parsing-subpartitions.patch deleted file mode 100644 index 353fa96748..0000000000 --- a/target/linux/generic/pending-5.10/410-mtd-parsers-ofpart-fix-parsing-subpartitions.patch +++ /dev/null @@ -1,76 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Thu, 6 May 2021 12:33:58 +0200 -Subject: [PATCH] mtd: parsers: ofpart: fix parsing subpartitions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -ofpart was recently patched to not scan random partition nodes as -subpartitions. That change unfortunately broke scanning valid -subpartitions like: - -partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - compatible = "fixed-partitions"; - label = "bootloader"; - reg = <0x0 0x100000>; - - partition@0 { - label = "config"; - reg = <0x80000 0x80000>; - }; - }; -}; - -Fix that regression by adding 1 more code path. We actually need 3 -conditional blocks to support 3 possible cases. This change also makes -code easier to understand & follow. - -Reported-by: David Bauer -Fixes: 2d751203aacf ("mtd: parsers: ofpart: limit parsing of deprecated DT syntax -Signed-off-by: Rafał Miłecki ---- - drivers/mtd/parsers/ofpart_core.c | 26 ++++++++++++++------------ - 1 file changed, 14 insertions(+), 12 deletions(-) - ---- a/drivers/mtd/parsers/ofpart_core.c -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -57,20 +57,22 @@ static int parse_fixed_partitions(struct - if (!mtd_node) - return 0; - -- ofpart_node = of_get_child_by_name(mtd_node, "partitions"); -- if (!ofpart_node && !master->parent) { -- /* -- * We might get here even when ofpart isn't used at all (e.g., -- * when using another parser), so don't be louder than -- * KERN_DEBUG -- */ -- pr_debug("%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\n", -- master->name, mtd_node); -+ if (!master->parent) { /* Master */ -+ ofpart_node = of_get_child_by_name(mtd_node, "partitions"); -+ if (!ofpart_node) { -+ /* -+ * We might get here even when ofpart isn't used at all (e.g., -+ * when using another parser), so don't be louder than -+ * KERN_DEBUG -+ */ -+ pr_debug("%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\n", -+ master->name, mtd_node); -+ ofpart_node = mtd_node; -+ dedicated = false; -+ } -+ } else { /* Partition */ - ofpart_node = mtd_node; -- dedicated = false; - } -- if (!ofpart_node) -- return 0; - - of_id = of_match_node(parse_ofpart_match_table, ofpart_node); - if (dedicated && !of_id) { diff --git a/target/linux/generic/pending-5.10/420-mtd-redboot_space.patch b/target/linux/generic/pending-5.10/420-mtd-redboot_space.patch deleted file mode 100644 index 5be2a2246e..0000000000 --- a/target/linux/generic/pending-5.10/420-mtd-redboot_space.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: Felix Fietkau -Subject: add patch for including unpartitioned space in the rootfs partition for redboot devices (if applicable) - -[john@phrozen.org: used by ixp and others] - -lede-commit: 394918851f84e4d00fa16eb900e7700e95091f00 -Signed-off-by: Felix Fietkau ---- - drivers/mtd/redboot.c | 19 +++++++++++++------ - 1 file changed, 13 insertions(+), 6 deletions(-) - ---- a/drivers/mtd/parsers/redboot.c -+++ b/drivers/mtd/parsers/redboot.c -@@ -280,14 +280,21 @@ static int parse_redboot_partitions(stru - #endif - names += strlen(names)+1; - --#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED - if(fl->next && fl->img->flash_base + fl->img->size + master->erasesize <= fl->next->img->flash_base) { -- i++; -- parts[i].offset = parts[i-1].size + parts[i-1].offset; -- parts[i].size = fl->next->img->flash_base - parts[i].offset; -- parts[i].name = nullname; -- } -+ if (!strcmp(parts[i].name, "rootfs")) { -+ parts[i].size = fl->next->img->flash_base; -+ parts[i].size &= ~(master->erasesize - 1); -+ parts[i].size -= parts[i].offset; -+#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED -+ nrparts--; -+ } else { -+ i++; -+ parts[i].offset = parts[i-1].size + parts[i-1].offset; -+ parts[i].size = fl->next->img->flash_base - parts[i].offset; -+ parts[i].name = nullname; - #endif -+ } -+ } - tmp_fl = fl; - fl = fl->next; - kfree(tmp_fl); diff --git a/target/linux/generic/pending-5.10/430-mtd-add-myloader-partition-parser.patch b/target/linux/generic/pending-5.10/430-mtd-add-myloader-partition-parser.patch deleted file mode 100644 index 8a6e630530..0000000000 --- a/target/linux/generic/pending-5.10/430-mtd-add-myloader-partition-parser.patch +++ /dev/null @@ -1,229 +0,0 @@ -From: Florian Fainelli -Subject: Add myloader partition table parser - -[john@phozen.org: shoud be upstreamable] - -lede-commit: d8bf22859b51faa09d22c056fe221a45d2f7a3b8 -Signed-off-by: Florian Fainelli -[adjust for kernel 5.4, add myloader.c to patch] -Signed-off-by: Adrian Schmutzler - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -57,6 +57,22 @@ config MTD_CMDLINE_PARTS - - If unsure, say 'N'. - -+config MTD_MYLOADER_PARTS -+ tristate "MyLoader partition parsing" -+ depends on ADM5120 || ATH25 || ATH79 -+ help -+ MyLoader is a bootloader which allows the user to define partitions -+ in flash devices, by putting a table in the second erase block -+ on the device, similar to a partition table. This table gives the -+ offsets and lengths of the user defined partitions. -+ -+ If you need code which can detect and parse these tables, and -+ register MTD 'partitions' corresponding to each image detected, -+ enable this option. -+ -+ You will still need the parsing functions to be called by the driver -+ for your particular device. It won't happen automatically. -+ - config MTD_OF_PARTS - tristate "OpenFirmware (device tree) partitioning parser" - default y ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -3,6 +3,7 @@ obj-$(CONFIG_MTD_AR7_PARTS) += ar7part. - obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o - obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o - obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o -+obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o - obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o - ofpart-y += ofpart_core.o - ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908) += ofpart_bcm4908.o ---- /dev/null -+++ b/drivers/mtd/parsers/myloader.c -@@ -0,0 +1,181 @@ -+/* -+ * Parse MyLoader-style flash partition tables and produce a Linux partition -+ * array to match. -+ * -+ * Copyright (C) 2007-2009 Gabor Juhos -+ * -+ * This file was based on drivers/mtd/redboot.c -+ * Author: Red Hat, Inc. - David Woodhouse -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BLOCK_LEN_MIN 0x10000 -+#define PART_NAME_LEN 32 -+ -+struct part_data { -+ struct mylo_partition_table tab; -+ char names[MYLO_MAX_PARTITIONS][PART_NAME_LEN]; -+}; -+ -+static int myloader_parse_partitions(struct mtd_info *master, -+ const struct mtd_partition **pparts, -+ struct mtd_part_parser_data *data) -+{ -+ struct part_data *buf; -+ struct mylo_partition_table *tab; -+ struct mylo_partition *part; -+ struct mtd_partition *mtd_parts; -+ struct mtd_partition *mtd_part; -+ int num_parts; -+ int ret, i; -+ size_t retlen; -+ char *names; -+ unsigned long offset; -+ unsigned long blocklen; -+ -+ buf = vmalloc(sizeof(*buf)); -+ if (!buf) { -+ return -ENOMEM; -+ goto out; -+ } -+ tab = &buf->tab; -+ -+ blocklen = master->erasesize; -+ if (blocklen < BLOCK_LEN_MIN) -+ blocklen = BLOCK_LEN_MIN; -+ -+ offset = blocklen; -+ -+ /* Find the partition table */ -+ for (i = 0; i < 4; i++, offset += blocklen) { -+ printk(KERN_DEBUG "%s: searching for MyLoader partition table" -+ " at offset 0x%lx\n", master->name, offset); -+ -+ ret = mtd_read(master, offset, sizeof(*buf), &retlen, -+ (void *)buf); -+ if (ret) -+ goto out_free_buf; -+ -+ if (retlen != sizeof(*buf)) { -+ ret = -EIO; -+ goto out_free_buf; -+ } -+ -+ /* Check for Partition Table magic number */ -+ if (tab->magic == le32_to_cpu(MYLO_MAGIC_PARTITIONS)) -+ break; -+ -+ } -+ -+ if (tab->magic != le32_to_cpu(MYLO_MAGIC_PARTITIONS)) { -+ printk(KERN_DEBUG "%s: no MyLoader partition table found\n", -+ master->name); -+ ret = 0; -+ goto out_free_buf; -+ } -+ -+ /* The MyLoader and the Partition Table is always present */ -+ num_parts = 2; -+ -+ /* Detect number of used partitions */ -+ for (i = 0; i < MYLO_MAX_PARTITIONS; i++) { -+ part = &tab->partitions[i]; -+ -+ if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE) -+ continue; -+ -+ num_parts++; -+ } -+ -+ mtd_parts = kzalloc((num_parts * sizeof(*mtd_part) + -+ num_parts * PART_NAME_LEN), GFP_KERNEL); -+ -+ if (!mtd_parts) { -+ ret = -ENOMEM; -+ goto out_free_buf; -+ } -+ -+ mtd_part = mtd_parts; -+ names = (char *)&mtd_parts[num_parts]; -+ -+ strncpy(names, "myloader", PART_NAME_LEN); -+ mtd_part->name = names; -+ mtd_part->offset = 0; -+ mtd_part->size = offset; -+ mtd_part->mask_flags = MTD_WRITEABLE; -+ mtd_part++; -+ names += PART_NAME_LEN; -+ -+ strncpy(names, "partition_table", PART_NAME_LEN); -+ mtd_part->name = names; -+ mtd_part->offset = offset; -+ mtd_part->size = blocklen; -+ mtd_part->mask_flags = MTD_WRITEABLE; -+ mtd_part++; -+ names += PART_NAME_LEN; -+ -+ for (i = 0; i < MYLO_MAX_PARTITIONS; i++) { -+ part = &tab->partitions[i]; -+ -+ if (le16_to_cpu(part->type) == PARTITION_TYPE_FREE) -+ continue; -+ -+ if ((buf->names[i][0]) && (buf->names[i][0] != '\xff')) -+ strncpy(names, buf->names[i], PART_NAME_LEN); -+ else -+ snprintf(names, PART_NAME_LEN, "partition%d", i); -+ -+ mtd_part->offset = le32_to_cpu(part->addr); -+ mtd_part->size = le32_to_cpu(part->size); -+ mtd_part->name = names; -+ mtd_part++; -+ names += PART_NAME_LEN; -+ } -+ -+ *pparts = mtd_parts; -+ ret = num_parts; -+ -+ out_free_buf: -+ vfree(buf); -+ out: -+ return ret; -+} -+ -+static struct mtd_part_parser myloader_mtd_parser = { -+ .owner = THIS_MODULE, -+ .parse_fn = myloader_parse_partitions, -+ .name = "MyLoader", -+}; -+ -+static int __init myloader_mtd_parser_init(void) -+{ -+ register_mtd_parser(&myloader_mtd_parser); -+ -+ return 0; -+} -+ -+static void __exit myloader_mtd_parser_exit(void) -+{ -+ deregister_mtd_parser(&myloader_mtd_parser); -+} -+ -+module_init(myloader_mtd_parser_init); -+module_exit(myloader_mtd_parser_exit); -+ -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_DESCRIPTION("Parsing code for MyLoader partition tables"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/generic/pending-5.10/431-mtd-bcm47xxpart-check-for-bad-blocks-when-calculatin.patch b/target/linux/generic/pending-5.10/431-mtd-bcm47xxpart-check-for-bad-blocks-when-calculatin.patch deleted file mode 100644 index bcea45d009..0000000000 --- a/target/linux/generic/pending-5.10/431-mtd-bcm47xxpart-check-for-bad-blocks-when-calculatin.patch +++ /dev/null @@ -1,68 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Subject: [PATCH] mtd: bcm47xxpart: check for bad blocks when calculating offsets - -Signed-off-by: Rafał Miłecki ---- - ---- a/drivers/mtd/parsers/parser_trx.c -+++ b/drivers/mtd/parsers/parser_trx.c -@@ -25,6 +25,33 @@ struct trx_header { - uint32_t offset[3]; - } __packed; - -+/* -+ * Calculate real end offset (address) for a given amount of data. It checks -+ * all blocks skipping bad ones. -+ */ -+static size_t parser_trx_real_offset(struct mtd_info *mtd, size_t bytes) -+{ -+ size_t real_offset = 0; -+ -+ if (mtd_block_isbad(mtd, real_offset)) -+ pr_warn("Base offset shouldn't be at bad block"); -+ -+ while (bytes >= mtd->erasesize) { -+ bytes -= mtd->erasesize; -+ real_offset += mtd->erasesize; -+ while (mtd_block_isbad(mtd, real_offset)) { -+ real_offset += mtd->erasesize; -+ -+ if (real_offset >= mtd->size) -+ return real_offset - mtd->erasesize; -+ } -+ } -+ -+ real_offset += bytes; -+ -+ return real_offset; -+} -+ - static const char *parser_trx_data_part_name(struct mtd_info *master, - size_t offset) - { -@@ -86,21 +113,21 @@ static int parser_trx_parse(struct mtd_i - if (trx.offset[2]) { - part = &parts[curr_part++]; - part->name = "loader"; -- part->offset = trx.offset[i]; -+ part->offset = parser_trx_real_offset(mtd, trx.offset[i]); - i++; - } - - if (trx.offset[i]) { - part = &parts[curr_part++]; - part->name = "linux"; -- part->offset = trx.offset[i]; -+ part->offset = parser_trx_real_offset(mtd, trx.offset[i]); - i++; - } - - if (trx.offset[i]) { - part = &parts[curr_part++]; -- part->name = parser_trx_data_part_name(mtd, trx.offset[i]); -- part->offset = trx.offset[i]; -+ part->offset = parser_trx_real_offset(mtd, trx.offset[i]); -+ part->name = parser_trx_data_part_name(mtd, part->offset); - i++; - } - diff --git a/target/linux/generic/pending-5.10/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch b/target/linux/generic/pending-5.10/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch deleted file mode 100644 index 852654d924..0000000000 --- a/target/linux/generic/pending-5.10/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch +++ /dev/null @@ -1,37 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Subject: mtd: bcm47xxpart: detect T_Meter partition - -It can be found on many Netgear devices. It consists of many 0x30 blocks -starting with 4D 54. - -Signed-off-by: Rafał Miłecki ---- - drivers/mtd/bcm47xxpart.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/mtd/parsers/bcm47xxpart.c -+++ b/drivers/mtd/parsers/bcm47xxpart.c -@@ -35,6 +35,7 @@ - #define NVRAM_HEADER 0x48534C46 /* FLSH */ - #define POT_MAGIC1 0x54544f50 /* POTT */ - #define POT_MAGIC2 0x504f /* OP */ -+#define T_METER_MAGIC 0x4D540000 /* MT */ - #define ML_MAGIC1 0x39685a42 - #define ML_MAGIC2 0x26594131 - #define TRX_MAGIC 0x30524448 -@@ -178,6 +179,15 @@ static int bcm47xxpart_parse(struct mtd_ - MTD_WRITEABLE); - continue; - } -+ -+ /* T_Meter */ -+ if ((le32_to_cpu(buf[0x000 / 4]) & 0xFFFF0000) == T_METER_MAGIC && -+ (le32_to_cpu(buf[0x030 / 4]) & 0xFFFF0000) == T_METER_MAGIC && -+ (le32_to_cpu(buf[0x060 / 4]) & 0xFFFF0000) == T_METER_MAGIC) { -+ bcm47xxpart_add_part(&parts[curr_part++], "T_Meter", offset, -+ MTD_WRITEABLE); -+ continue; -+ } - - /* TRX */ - if (buf[0x000 / 4] == TRX_MAGIC) { diff --git a/target/linux/generic/pending-5.10/435-mtd-add-routerbootpart-parser-config.patch b/target/linux/generic/pending-5.10/435-mtd-add-routerbootpart-parser-config.patch deleted file mode 100644 index 5c7b57b373..0000000000 --- a/target/linux/generic/pending-5.10/435-mtd-add-routerbootpart-parser-config.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 4437e01fb6bca63fccdba5d6c44888b0935885c2 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= -Date: Tue, 24 Mar 2020 11:45:07 +0100 -Subject: [PATCH] generic: routerboot partition build bits (5.4) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This patch adds routerbootpart kernel build bits - -Signed-off-by: Thibaut VARÈNE ---- - drivers/mtd/parsers/Kconfig | 9 +++++++++ - drivers/mtd/parsers/Makefile | 1 + - 2 files changed, 10 insertions(+) - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -219,3 +219,12 @@ config MTD_SERCOMM_PARTS - partition map. This partition table contains real partition - offsets, which may differ from device to device depending on the - number and location of bad blocks on NAND. -+ -+config MTD_ROUTERBOOT_PARTS -+ tristate "RouterBoot flash partition parser" -+ depends on MTD && OF -+ help -+ MikroTik RouterBoot is implemented as a multi segment system on the -+ flash, some of which are fixed and some of which are located at -+ variable offsets. This parser handles both cases via properly -+ formatted DTS. ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -15,3 +15,4 @@ obj-$(CONFIG_MTD_PARSER_TRX) += parser_ - obj-$(CONFIG_MTD_SERCOMM_PARTS) += scpart.o - obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o - obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o -+obj-$(CONFIG_MTD_ROUTERBOOT_PARTS) += routerbootpart.o diff --git a/target/linux/generic/pending-5.10/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch b/target/linux/generic/pending-5.10/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch deleted file mode 100644 index 2435133fa0..0000000000 --- a/target/linux/generic/pending-5.10/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch +++ /dev/null @@ -1,25 +0,0 @@ -From: Felix Fietkau -Subject: kernel: disable cfi cmdset 0002 erase suspend - -on some platforms, erase suspend leads to data corruption and lockups when write -ops collide with erase ops. this has been observed on the buffalo wzr-hp-g300nh. -rather than play whack-a-mole with a hard to reproduce issue on a variety of devices, -simply disable erase suspend, as it will usually not produce any useful gain on -the small filesystems used on embedded hardware. - -Signed-off-by: Felix Fietkau ---- - drivers/mtd/chips/cfi_cmdset_0002.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -906,7 +906,7 @@ static int get_chip(struct map_info *map - return 0; - - case FL_ERASING: -- if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) || -+ if (1 /* no suspend */ || !cfip || !(cfip->EraseSuspend & (0x1|0x2)) || - !(mode == FL_READY || mode == FL_POINT || - (mode == FL_WRITING && (cfip->EraseSuspend & 0x2)))) - goto sleep; diff --git a/target/linux/generic/pending-5.10/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch b/target/linux/generic/pending-5.10/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch deleted file mode 100644 index 059d9673dc..0000000000 --- a/target/linux/generic/pending-5.10/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch +++ /dev/null @@ -1,17 +0,0 @@ -From: George Kashperko -Subject: Issue map read after Write Buffer Load command to ensure chip is ready to receive data. - -Signed-off-by: George Kashperko ---- - drivers/mtd/chips/cfi_cmdset_0002.c | 1 + - 1 file changed, 1 insertion(+) ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -2050,6 +2050,7 @@ static int __xipram do_write_buffer(stru - - /* Write Buffer Load */ - map_write(map, CMD(0x25), cmd_adr); -+ (void) map_read(map, cmd_adr); - - chip->state = FL_WRITING_TO_BUFFER; - diff --git a/target/linux/generic/pending-5.10/465-m25p80-mx-disable-software-protection.patch b/target/linux/generic/pending-5.10/465-m25p80-mx-disable-software-protection.patch deleted file mode 100644 index f58d5452ab..0000000000 --- a/target/linux/generic/pending-5.10/465-m25p80-mx-disable-software-protection.patch +++ /dev/null @@ -1,18 +0,0 @@ -From: Felix Fietkau -Subject: Disable software protection bits for Macronix flashes. - -Signed-off-by: Felix Fietkau ---- - drivers/mtd/spi-nor/spi-nor.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mtd/spi-nor/macronix.c -+++ b/drivers/mtd/spi-nor/macronix.c -@@ -93,6 +93,7 @@ static void macronix_default_init(struct - { - nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; - nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode; -+ nor->flags |= SNOR_F_HAS_LOCK; - } - - static const struct spi_nor_fixups macronix_fixups = { diff --git a/target/linux/generic/pending-5.10/476-mtd-spi-nor-add-eon-en25q128.patch b/target/linux/generic/pending-5.10/476-mtd-spi-nor-add-eon-en25q128.patch deleted file mode 100644 index 9383e48856..0000000000 --- a/target/linux/generic/pending-5.10/476-mtd-spi-nor-add-eon-en25q128.patch +++ /dev/null @@ -1,18 +0,0 @@ -From: Piotr Dymacz -Subject: kernel/mtd: add support for EON EN25Q128 - -Signed-off-by: Piotr Dymacz ---- - drivers/mtd/spi-nor/spi-nor.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mtd/spi-nor/eon.c -+++ b/drivers/mtd/spi-nor/eon.c -@@ -25,6 +25,7 @@ static const struct flash_info eon_parts - { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, - { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, - { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, -+ { "en25q128", INFO(0x1c3018, 0, 64 * 1024, 256, SECT_4K) }, - { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16, - SECT_4K | SPI_NOR_DUAL_READ) }, - { "en25qh16", INFO(0x1c7015, 0, 64 * 1024, 32, diff --git a/target/linux/generic/pending-5.10/477-mtd-spi-nor-add-eon-en25qx128a.patch b/target/linux/generic/pending-5.10/477-mtd-spi-nor-add-eon-en25qx128a.patch deleted file mode 100644 index 3c579e55e3..0000000000 --- a/target/linux/generic/pending-5.10/477-mtd-spi-nor-add-eon-en25qx128a.patch +++ /dev/null @@ -1,21 +0,0 @@ -From: Christian Marangi -Subject: kernel/mtd: add support for EON EN25QX128A - -Add support for EON EN25QX128A with no flags as it does -support SFDP parsing. - -Signed-off-by: Christian Marangi ---- - drivers/mtd/spi-nor/spi-nor.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mtd/spi-nor/eon.c -+++ b/drivers/mtd/spi-nor/eon.c -@@ -26,6 +26,7 @@ static const struct flash_info eon_parts - { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, - { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, - { "en25q128", INFO(0x1c3018, 0, 64 * 1024, 256, SECT_4K) }, -+ { "en25qx128a", INFO(0x1c7118, 0, 64 * 1024, 256, 0) }, - { "en25q80a", INFO(0x1c3014, 0, 64 * 1024, 16, - SECT_4K | SPI_NOR_DUAL_READ) }, - { "en25qh16", INFO(0x1c7015, 0, 64 * 1024, 32, diff --git a/target/linux/generic/pending-5.10/479-mtd-spi-nor-add-xtx-xt25f128b.patch b/target/linux/generic/pending-5.10/479-mtd-spi-nor-add-xtx-xt25f128b.patch deleted file mode 100644 index 784392cd88..0000000000 --- a/target/linux/generic/pending-5.10/479-mtd-spi-nor-add-xtx-xt25f128b.patch +++ /dev/null @@ -1,79 +0,0 @@ -From patchwork Thu Feb 6 17:19:41 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 1234465 -Date: Thu, 6 Feb 2020 19:19:41 +0200 -From: Daniel Golle -To: linux-mtd@lists.infradead.org -Subject: [PATCH v2] mtd: spi-nor: Add support for xt25f128b chip -Message-ID: <20200206171941.GA2398@makrotopia.org> -MIME-Version: 1.0 -Content-Disposition: inline -List-Subscribe: , - -Cc: Eitan Cohen , Piotr Dymacz , - Tudor Ambarus -Sender: "linux-mtd" -Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org - -Add XT25F128B made by XTX Technology (Shenzhen) Limited. -This chip supports dual and quad read and uniform 4K-byte erase. -Verified on Teltonika RUT955 which comes with XT25F128B in recent -versions of the device. - -Signed-off-by: Daniel Golle -Signed-off-by: Felix Fietkau ---- - drivers/mtd/spi-nor/spi-nor.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/spi-nor/Makefile -+++ b/drivers/mtd/spi-nor/Makefile -@@ -17,6 +17,7 @@ spi-nor-objs += sst.o - spi-nor-objs += winbond.o - spi-nor-objs += xilinx.o - spi-nor-objs += xmc.o -+spi-nor-objs += xtx.o - obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o - - obj-$(CONFIG_MTD_SPI_NOR) += controllers/ ---- /dev/null -+++ b/drivers/mtd/spi-nor/xtx.c -@@ -0,0 +1,15 @@ -+// SPDX-License-Identifier: GPL-2.0 -+#include -+ -+#include "core.h" -+ -+static const struct flash_info xtx_parts[] = { -+ /* XTX Technology (Shenzhen) Limited */ -+ { "xt25f128b", INFO(0x0B4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+}; -+ -+const struct spi_nor_manufacturer spi_nor_xtx = { -+ .name = "xtx", -+ .parts = xtx_parts, -+ .nparts = ARRAY_SIZE(xtx_parts), -+}; ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -2039,6 +2039,7 @@ static const struct spi_nor_manufacturer - &spi_nor_winbond, - &spi_nor_xilinx, - &spi_nor_xmc, -+ &spi_nor_xtx, - }; - - static const struct flash_info * ---- a/drivers/mtd/spi-nor/core.h -+++ b/drivers/mtd/spi-nor/core.h -@@ -398,6 +398,7 @@ extern const struct spi_nor_manufacturer - extern const struct spi_nor_manufacturer spi_nor_winbond; - extern const struct spi_nor_manufacturer spi_nor_xilinx; - extern const struct spi_nor_manufacturer spi_nor_xmc; -+extern const struct spi_nor_manufacturer spi_nor_xtx; - - int spi_nor_write_enable(struct spi_nor *nor); - int spi_nor_write_disable(struct spi_nor *nor); diff --git a/target/linux/generic/pending-5.10/482-mtd-spi-nor-add-support-for-Gigadevice-GD25D05.patch b/target/linux/generic/pending-5.10/482-mtd-spi-nor-add-support-for-Gigadevice-GD25D05.patch deleted file mode 100644 index c32cde559d..0000000000 --- a/target/linux/generic/pending-5.10/482-mtd-spi-nor-add-support-for-Gigadevice-GD25D05.patch +++ /dev/null @@ -1,22 +0,0 @@ -From d68b4aa22e8c625685bfad642dd7337948dc0ad1 Mon Sep 17 00:00:00 2001 -From: Koen Vandeputte -Date: Mon, 6 Jan 2020 13:07:56 +0100 -Subject: [PATCH] mtd: spi-nor: add support for Gigadevice GD25D05 - -Signed-off-by: Koen Vandeputte ---- - drivers/mtd/spi-nor/spi-nor.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/mtd/spi-nor/gigadevice.c -+++ b/drivers/mtd/spi-nor/gigadevice.c -@@ -24,6 +24,9 @@ static struct spi_nor_fixups gd25q256_fi - }; - - static const struct flash_info gigadevice_parts[] = { -+ { "gd25q05", INFO(0xc84010, 0, 64 * 1024, 1, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, - { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, diff --git a/target/linux/generic/pending-5.10/483-mtd-spi-nor-add-gd25q512.patch b/target/linux/generic/pending-5.10/483-mtd-spi-nor-add-gd25q512.patch deleted file mode 100644 index b18ba15671..0000000000 --- a/target/linux/generic/pending-5.10/483-mtd-spi-nor-add-gd25q512.patch +++ /dev/null @@ -1,21 +0,0 @@ -From: Roman Yeryomin -Subject: mtd/spi-nor/gigadevice: Add gd25q512 SPI NOR flash - -Submitted-by: Roman Yeryomin -Submitted-by: John Crispin ---- - drivers/mtd/spi-nor/gigadevice.c | 3 +++ - 1 files changed, 3 insertions(+) - ---- a/drivers/mtd/spi-nor/gigadevice.c -+++ b/drivers/mtd/spi-nor/gigadevice.c -@@ -53,6 +53,9 @@ static const struct flash_info gigadevic - SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | - SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6) - .fixups = &gd25q256_fixups }, -+ { "gd25q512", INFO(0xc84020, 0, 64 * 1024, 1024, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES) }, - }; - - const struct spi_nor_manufacturer spi_nor_gigadevice = { diff --git a/target/linux/generic/pending-5.10/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch b/target/linux/generic/pending-5.10/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch deleted file mode 100644 index 3a8ba498bd..0000000000 --- a/target/linux/generic/pending-5.10/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch +++ /dev/null @@ -1,178 +0,0 @@ -From a07e31adf2753cad2fd9790db5bfc047c81e8152 Mon Sep 17 00:00:00 2001 -From: Felix Matouschek -Date: Fri, 2 Jul 2021 20:31:23 +0200 -Subject: [PATCH] mtd: spinand: Add support for XTX XT26G0xA - -Add support for XTX Technology XT26G01AXXXXX, XTX26G02AXXXXX and -XTX26G04AXXXXX SPI NAND. - -These are 3V, 1G/2G/4Gbit serial SLC NAND flash devices with on-die ECC -(8bit strength per 512bytes). - -Tested on Teltonika RUTX10 flashed with OpenWrt. - -Datasheets available at -http://www.xtxtech.com/download/?AId=225 -https://datasheet.lcsc.com/szlcsc/2005251034_XTX-XT26G01AWSEGA_C558841.pdf - -Signed-off-by: Felix Matouschek ---- - drivers/mtd/nand/spi/Makefile | 2 +- - drivers/mtd/nand/spi/core.c | 1 + - drivers/mtd/nand/spi/xtx.c | 122 ++++++++++++++++++++++++++++++++++ - include/linux/mtd/spinand.h | 1 + - 4 files changed, 125 insertions(+), 1 deletion(-) - create mode 100644 drivers/mtd/nand/spi/xtx.c - ---- a/drivers/mtd/nand/spi/Makefile -+++ b/drivers/mtd/nand/spi/Makefile -@@ -1,3 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o -+spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o - obj-$(CONFIG_MTD_SPI_NAND) += spinand.o ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -760,6 +760,7 @@ static const struct spinand_manufacturer - ¶gon_spinand_manufacturer, - &toshiba_spinand_manufacturer, - &winbond_spinand_manufacturer, -+ &xtx_spinand_manufacturer, - }; - - static int spinand_manufacturer_match(struct spinand_device *spinand, ---- /dev/null -+++ b/drivers/mtd/nand/spi/xtx.c -@@ -0,0 +1,122 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Author: -+ * Felix Matouschek -+ */ -+ -+#include -+#include -+#include -+ -+#define SPINAND_MFR_XTX 0x0B -+ -+#define XT26G0XA_STATUS_ECC_MASK GENMASK(5, 2) -+#define XT26G0XA_STATUS_ECC_NO_DETECTED (0 << 2) -+#define XT26G0XA_STATUS_ECC_8_CORRECTED (3 << 4) -+#define XT26G0XA_STATUS_ECC_UNCOR_ERROR (2 << 4) -+ -+static SPINAND_OP_VARIANTS(read_cache_variants, -+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(write_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(update_cache_variants, -+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), -+ SPINAND_PROG_LOAD(false, 0, NULL, 0)); -+ -+static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section) -+ return -ERANGE; -+ -+ region->offset = 48; -+ region->length = 16; -+ -+ return 0; -+} -+ -+static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section) -+ return -ERANGE; -+ -+ region->offset = 1; -+ region->length = 47; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = { -+ .ecc = xt26g0xa_ooblayout_ecc, -+ .free = xt26g0xa_ooblayout_free, -+}; -+ -+static int xt26g0xa_ecc_get_status(struct spinand_device *spinand, -+ u8 status) -+{ -+ switch (status & XT26G0XA_STATUS_ECC_MASK) { -+ case XT26G0XA_STATUS_ECC_NO_DETECTED: -+ return 0; -+ case XT26G0XA_STATUS_ECC_8_CORRECTED: -+ return 8; -+ case XT26G0XA_STATUS_ECC_UNCOR_ERROR: -+ return -EBADMSG; -+ default: /* (1 << 2) through (7 << 2) are 1-7 corrected errors */ -+ return (status & XT26G0XA_STATUS_ECC_MASK) >> 2; -+ } -+ -+ return -EINVAL; -+} -+ -+static const struct spinand_info xtx_spinand_table[] = { -+ SPINAND_INFO("XT26G01A", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&xt26g0xa_ooblayout, -+ xt26g0xa_ecc_get_status)), -+ SPINAND_INFO("XT26G02A", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE2), -+ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&xt26g0xa_ooblayout, -+ xt26g0xa_ecc_get_status)), -+ SPINAND_INFO("XT26G04A", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE3), -+ NAND_MEMORG(1, 2048, 64, 128, 2048, 40, 1, 1, 1), -+ NAND_ECCREQ(8, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&xt26g0xa_ooblayout, -+ xt26g0xa_ecc_get_status)), -+}; -+ -+static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { -+}; -+ -+const struct spinand_manufacturer xtx_spinand_manufacturer = { -+ .id = SPINAND_MFR_XTX, -+ .name = "XTX", -+ .chips = xtx_spinand_table, -+ .nchips = ARRAY_SIZE(xtx_spinand_table), -+ .ops = &xtx_spinand_manuf_ops, -+}; ---- a/include/linux/mtd/spinand.h -+++ b/include/linux/mtd/spinand.h -@@ -244,6 +244,7 @@ extern const struct spinand_manufacturer - extern const struct spinand_manufacturer paragon_spinand_manufacturer; - extern const struct spinand_manufacturer toshiba_spinand_manufacturer; - extern const struct spinand_manufacturer winbond_spinand_manufacturer; -+extern const struct spinand_manufacturer xtx_spinand_manufacturer; - - /** - * struct spinand_op_variants - SPI NAND operation variants diff --git a/target/linux/generic/pending-5.10/484-mtd-spi-nor-add-esmt-f25l16pa.patch b/target/linux/generic/pending-5.10/484-mtd-spi-nor-add-esmt-f25l16pa.patch deleted file mode 100644 index bf2f1e6aa6..0000000000 --- a/target/linux/generic/pending-5.10/484-mtd-spi-nor-add-esmt-f25l16pa.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: Jihoon Han -Subject: mtd/spi-nor/esmt: Add support for ESMT F25L16PA(2S) SPI-NOR - -This fixes support for Dongwon T&I DW02-412H which uses F25L16PA(2S) flash. - -Submitted-by: Jihoon Han -Reviewed-by: Sungbo Eo -[refresh patches] -Submitted-by: Adrian Schmutzler ---- - drivers/mtd/spi-nor/esmt.c | 2 ++ - 1 files changed, 2 insertions(+) - ---- a/drivers/mtd/spi-nor/esmt.c -+++ b/drivers/mtd/spi-nor/esmt.c -@@ -10,6 +10,8 @@ - - static const struct flash_info esmt_parts[] = { - /* ESMT */ -+ { "f25l16pa-2s", INFO(0x8c2115, 0, 64 * 1024, 32, -+ SECT_4K | SPI_NOR_HAS_LOCK) }, - { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, - SECT_4K | SPI_NOR_HAS_LOCK) }, - { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, diff --git a/target/linux/generic/pending-5.10/485-mtd-spi-nor-add-xmc-xm25qh128c.patch b/target/linux/generic/pending-5.10/485-mtd-spi-nor-add-xmc-xm25qh128c.patch deleted file mode 100644 index ba654ce4ca..0000000000 --- a/target/linux/generic/pending-5.10/485-mtd-spi-nor-add-xmc-xm25qh128c.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Langhua Ye -Subject: mtd/spi-nor/xmc: add support for XMC XM25QH128C - -The XMC XM25QH128C is a 16MB SPI NOR chip. The patch is verified on Ruijie RG-EW3200GX PRO. -Datasheet available at https://www.xmcwh.com/uploads/435/XM25QH128C.pdf - -Submitted-by: Langhua Ye ---- - drivers/mtd/spi-nor/xmc.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/mtd/spi-nor/xmc.c -+++ b/drivers/mtd/spi-nor/xmc.c -@@ -14,6 +14,8 @@ static const struct flash_info xmc_parts - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "XM25QH128C", INFO(0x204018, 0, 64 * 1024, 256, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - }; - - const struct spi_nor_manufacturer spi_nor_xmc = { diff --git a/target/linux/generic/pending-5.10/488-mtd-spi-nor-add-xmc-xm25qh64c.patch b/target/linux/generic/pending-5.10/488-mtd-spi-nor-add-xmc-xm25qh64c.patch deleted file mode 100644 index 236d1c2755..0000000000 --- a/target/linux/generic/pending-5.10/488-mtd-spi-nor-add-xmc-xm25qh64c.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Joe Mullally -Subject: mtd/spi-nor/xmc: add support for XMC XM25QH64C - -The XMC XM25QH64C is a 8MB SPI NOR chip. The patch is verified on TL-WPA8631P v3. -Datasheet available at https://www.xmcwh.com/uploads/442/XM25QH64C.pdf - -Signed-off-by: Joe Mullally ---- - drivers/mtd/spi-nor/xmc.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/mtd/spi-nor/xmc.c -+++ b/drivers/mtd/spi-nor/xmc.c -@@ -12,6 +12,8 @@ static const struct flash_info xmc_parts - /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ - { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "XM25QH64C", INFO(0x204017, 0, 64 * 1024, 128, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "XM25QH128C", INFO(0x204018, 0, 64 * 1024, 256, diff --git a/target/linux/generic/pending-5.10/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/target/linux/generic/pending-5.10/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch deleted file mode 100644 index 36bd2bb589..0000000000 --- a/target/linux/generic/pending-5.10/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch +++ /dev/null @@ -1,97 +0,0 @@ -From: Daniel Golle -Subject: ubi: auto-attach mtd device named "ubi" or "data" on boot - -Signed-off-by: Daniel Golle ---- - drivers/mtd/ubi/build.c | 36 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 36 insertions(+) - ---- a/drivers/mtd/ubi/build.c -+++ b/drivers/mtd/ubi/build.c -@@ -1201,6 +1201,73 @@ static struct mtd_info * __init open_mtd - return mtd; - } - -+/* -+ * This function tries attaching mtd partitions named either "ubi" or "data" -+ * during boot. -+ */ -+static void __init ubi_auto_attach(void) -+{ -+ int err; -+ struct mtd_info *mtd; -+ loff_t offset = 0; -+ size_t len; -+ char magic[4]; -+ -+ /* try attaching mtd device named "ubi" or "data" */ -+ mtd = open_mtd_device("ubi"); -+ if (IS_ERR(mtd)) -+ mtd = open_mtd_device("data"); -+ -+ if (IS_ERR(mtd)) -+ return; -+ -+ /* get the first not bad block */ -+ if (mtd_can_have_bb(mtd)) -+ while (mtd_block_isbad(mtd, offset)) { -+ offset += mtd->erasesize; -+ -+ if (offset > mtd->size) { -+ pr_err("UBI error: Failed to find a non-bad " -+ "block on mtd%d\n", mtd->index); -+ goto cleanup; -+ } -+ } -+ -+ /* check if the read from flash was successful */ -+ err = mtd_read(mtd, offset, 4, &len, (void *) magic); -+ if ((err && !mtd_is_bitflip(err)) || len != 4) { -+ pr_err("UBI error: unable to read from mtd%d\n", mtd->index); -+ goto cleanup; -+ } -+ -+ /* check for a valid ubi magic */ -+ if (strncmp(magic, "UBI#", 4)) { -+ pr_err("UBI error: no valid UBI magic found inside mtd%d\n", mtd->index); -+ goto cleanup; -+ } -+ -+ /* don't auto-add media types where UBI doesn't makes sense */ -+ if (mtd->type != MTD_NANDFLASH && -+ mtd->type != MTD_NORFLASH && -+ mtd->type != MTD_DATAFLASH && -+ mtd->type != MTD_MLCNANDFLASH) -+ goto cleanup; -+ -+ mutex_lock(&ubi_devices_mutex); -+ pr_notice("UBI: auto-attach mtd%d\n", mtd->index); -+ err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0); -+ mutex_unlock(&ubi_devices_mutex); -+ if (err < 0) { -+ pr_err("UBI error: cannot attach mtd%d\n", mtd->index); -+ goto cleanup; -+ } -+ -+ return; -+ -+cleanup: -+ put_mtd_device(mtd); -+} -+ - static int __init ubi_init(void) - { - int err, i, k; -@@ -1284,6 +1351,12 @@ static int __init ubi_init(void) - } - } - -+ /* auto-attach mtd devices only if built-in to the kernel and no ubi.mtd -+ * parameter was given */ -+ if (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) && -+ !ubi_is_module() && !mtd_devs) -+ ubi_auto_attach(); -+ - err = ubiblock_init(); - if (err) { - pr_err("UBI error: block: cannot initialize, error %d\n", err); diff --git a/target/linux/generic/pending-5.10/491-ubi-auto-create-ubiblock-device-for-rootfs.patch b/target/linux/generic/pending-5.10/491-ubi-auto-create-ubiblock-device-for-rootfs.patch deleted file mode 100644 index a2b48fd4fc..0000000000 --- a/target/linux/generic/pending-5.10/491-ubi-auto-create-ubiblock-device-for-rootfs.patch +++ /dev/null @@ -1,69 +0,0 @@ -From: Daniel Golle -Subject: ubi: auto-create ubiblock device for rootfs - -Signed-off-by: Daniel Golle ---- - drivers/mtd/ubi/block.c | 42 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 42 insertions(+) - ---- a/drivers/mtd/ubi/block.c -+++ b/drivers/mtd/ubi/block.c -@@ -652,6 +652,47 @@ static void __init ubiblock_create_from_ - } - } - -+#define UBIFS_NODE_MAGIC 0x06101831 -+static inline int ubi_vol_is_ubifs(struct ubi_volume_desc *desc) -+{ -+ int ret; -+ uint32_t magic_of, magic; -+ ret = ubi_read(desc, 0, (char *)&magic_of, 0, 4); -+ if (ret) -+ return 0; -+ magic = le32_to_cpu(magic_of); -+ return magic == UBIFS_NODE_MAGIC; -+} -+ -+static void __init ubiblock_create_auto_rootfs(void) -+{ -+ int ubi_num, ret, is_ubifs; -+ struct ubi_volume_desc *desc; -+ struct ubi_volume_info vi; -+ -+ for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) { -+ desc = ubi_open_volume_nm(ubi_num, "rootfs", UBI_READONLY); -+ if (IS_ERR(desc)) -+ desc = ubi_open_volume_nm(ubi_num, "fit", UBI_READONLY);; -+ -+ if (IS_ERR(desc)) -+ continue; -+ -+ ubi_get_volume_info(desc, &vi); -+ is_ubifs = ubi_vol_is_ubifs(desc); -+ ubi_close_volume(desc); -+ if (is_ubifs) -+ break; -+ -+ ret = ubiblock_create(&vi); -+ if (ret) -+ pr_err("UBI error: block: can't add '%s' volume, err=%d\n", -+ vi.name, ret); -+ /* always break if we get here */ -+ break; -+ } -+} -+ - static void ubiblock_remove_all(void) - { - struct ubiblock *next; -@@ -684,6 +725,10 @@ int __init ubiblock_init(void) - */ - ubiblock_create_from_param(); - -+ /* auto-attach "rootfs" volume if existing and non-ubifs */ -+ if (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV)) -+ ubiblock_create_auto_rootfs(); -+ - /* - * Block devices are only created upon user requests, so we ignore - * existing volumes. diff --git a/target/linux/generic/pending-5.10/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch b/target/linux/generic/pending-5.10/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch deleted file mode 100644 index e3c4dd2ef4..0000000000 --- a/target/linux/generic/pending-5.10/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch +++ /dev/null @@ -1,53 +0,0 @@ -From: Daniel Golle -Subject: try auto-mounting ubi0:rootfs in init/do_mounts.c - -Signed-off-by: Daniel Golle ---- - init/do_mounts.c | 26 +++++++++++++++++++++++++- - 1 file changed, 25 insertions(+), 1 deletion(-) - ---- a/init/do_mounts.c -+++ b/init/do_mounts.c -@@ -474,7 +474,30 @@ retry: - out: - put_page(page); - } -- -+ -+#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV -+static int __init mount_ubi_rootfs(void) -+{ -+ int flags = MS_SILENT; -+ int err, tried = 0; -+ -+ while (tried < 2) { -+ err = do_mount_root("ubi0:rootfs", "ubifs", flags, \ -+ root_mount_data); -+ switch (err) { -+ case -EACCES: -+ flags |= MS_RDONLY; -+ tried++; -+ break; -+ default: -+ return err; -+ } -+ } -+ -+ return -EINVAL; -+} -+#endif -+ - #ifdef CONFIG_ROOT_NFS - - #define NFSROOT_TIMEOUT_MIN 5 -@@ -567,6 +590,10 @@ void __init mount_root(void) - return; - } - #endif -+#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV -+ if (!mount_ubi_rootfs()) -+ return; -+#endif - #ifdef CONFIG_BLOCK - { - int err = create_dev("/dev/root", ROOT_DEV); diff --git a/target/linux/generic/pending-5.10/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch b/target/linux/generic/pending-5.10/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch deleted file mode 100644 index 2dff46807e..0000000000 --- a/target/linux/generic/pending-5.10/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: Daniel Golle -Subject: ubi: set ROOT_DEV to ubiblock "rootfs" if unset - -Signed-off-by: Daniel Golle ---- - drivers/mtd/ubi/block.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/drivers/mtd/ubi/block.c -+++ b/drivers/mtd/ubi/block.c -@@ -42,6 +42,7 @@ - #include - #include - #include -+#include - - #include "ubi-media.h" - #include "ubi.h" -@@ -458,6 +459,15 @@ int ubiblock_create(struct ubi_volume_in - dev_info(disk_to_dev(dev->gd), "created from ubi%d:%d(%s)", - dev->ubi_num, dev->vol_id, vi->name); - mutex_unlock(&devices_mutex); -+ -+ if (!strcmp(vi->name, "rootfs") && -+ IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) && -+ ROOT_DEV == 0) { -+ pr_notice("ubiblock: device ubiblock%d_%d (%s) set to be root filesystem\n", -+ dev->ubi_num, dev->vol_id, vi->name); -+ ROOT_DEV = MKDEV(gd->major, gd->first_minor); -+ } -+ - return 0; - - out_free_queue: diff --git a/target/linux/generic/pending-5.10/494-mtd-ubi-add-EOF-marker-support.patch b/target/linux/generic/pending-5.10/494-mtd-ubi-add-EOF-marker-support.patch deleted file mode 100644 index fc48146221..0000000000 --- a/target/linux/generic/pending-5.10/494-mtd-ubi-add-EOF-marker-support.patch +++ /dev/null @@ -1,60 +0,0 @@ -From: Gabor Juhos -Subject: mtd: add EOF marker support to the UBI layer - -Signed-off-by: Gabor Juhos ---- - drivers/mtd/ubi/attach.c | 25 ++++++++++++++++++++++--- - drivers/mtd/ubi/ubi.h | 1 + - 2 files changed, 23 insertions(+), 3 deletions(-) - ---- a/drivers/mtd/ubi/attach.c -+++ b/drivers/mtd/ubi/attach.c -@@ -926,6 +926,13 @@ static bool vol_ignored(int vol_id) - #endif - } - -+static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech) -+{ -+ return ech->padding1[0] == 'E' && -+ ech->padding1[1] == 'O' && -+ ech->padding1[2] == 'F'; -+} -+ - /** - * scan_peb - scan and process UBI headers of a PEB. - * @ubi: UBI device description object -@@ -958,9 +965,21 @@ static int scan_peb(struct ubi_device *u - return 0; - } - -- err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); -- if (err < 0) -- return err; -+ if (!ai->eof_found) { -+ err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); -+ if (err < 0) -+ return err; -+ -+ if (ec_hdr_has_eof(ech)) { -+ pr_notice("UBI: EOF marker found, PEBs from %d will be erased\n", -+ pnum); -+ ai->eof_found = true; -+ } -+ } -+ -+ if (ai->eof_found) -+ err = UBI_IO_FF_BITFLIPS; -+ - switch (err) { - case 0: - break; ---- a/drivers/mtd/ubi/ubi.h -+++ b/drivers/mtd/ubi/ubi.h -@@ -780,6 +780,7 @@ struct ubi_attach_info { - int mean_ec; - uint64_t ec_sum; - int ec_count; -+ bool eof_found; - struct kmem_cache *aeb_slab_cache; - struct ubi_ec_hdr *ech; - struct ubi_vid_io_buf *vidb; diff --git a/target/linux/generic/pending-5.10/496-dt-bindings-add-bindings-for-mtd-concat-devices.patch b/target/linux/generic/pending-5.10/496-dt-bindings-add-bindings-for-mtd-concat-devices.patch deleted file mode 100644 index 01f3b9ec2d..0000000000 --- a/target/linux/generic/pending-5.10/496-dt-bindings-add-bindings-for-mtd-concat-devices.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 5734c6669fba7ddb5ef491ccff7159d15dba0b59 Mon Sep 17 00:00:00 2001 -From: Bernhard Frauendienst -Date: Wed, 5 Sep 2018 01:32:51 +0200 -Subject: [PATCH 496/497] dt-bindings: add bindings for mtd-concat devices - -Document virtual mtd-concat device bindings. - -Signed-off-by: Bernhard Frauendienst ---- - .../devicetree/bindings/mtd/mtd-concat.txt | 36 +++++++++++++++++++ - 1 file changed, 36 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mtd/mtd-concat.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mtd/mtd-concat.txt -@@ -0,0 +1,36 @@ -+Virtual MTD concat device -+ -+Requires properties: -+- devices: list of phandles to mtd nodes that should be concatenated -+ -+Example: -+ -+&spi { -+ flash0: flash@0 { -+ ... -+ }; -+ flash1: flash@1 { -+ ... -+ }; -+}; -+ -+flash { -+ compatible = "mtd-concat"; -+ -+ devices = <&flash0 &flash1>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ -+ partition@0 { -+ label = "boot"; -+ reg = <0x0000000 0x0040000>; -+ read-only; -+ }; -+ -+ partition@40000 { -+ label = "firmware"; -+ reg = <0x0040000 0x1fc0000>; -+ }; -+ } -+} diff --git a/target/linux/generic/pending-5.10/497-mtd-mtdconcat-add-dt-driver-for-concat-devices.patch b/target/linux/generic/pending-5.10/497-mtd-mtdconcat-add-dt-driver-for-concat-devices.patch deleted file mode 100644 index 9b938a43f8..0000000000 --- a/target/linux/generic/pending-5.10/497-mtd-mtdconcat-add-dt-driver-for-concat-devices.patch +++ /dev/null @@ -1,216 +0,0 @@ -From e53f712d8eac71f54399b61038ccf87d2cee99d7 Mon Sep 17 00:00:00 2001 -From: Bernhard Frauendienst -Date: Sat, 25 Aug 2018 12:35:22 +0200 -Subject: [PATCH 497/497] mtd: mtdconcat: add dt driver for concat devices - -Some mtd drivers like physmap variants have support for concatenating -multiple mtd devices, but there is no generic way to define such a -concat device from within the device tree. - -This is useful for some SoC boards that use multiple flash chips as -memory banks of a single mtd device, with partitions spanning chip -borders. - -This commit adds a driver for creating virtual mtd-concat devices. They -must have a compatible = "mtd-concat" line, and define a list of devices -to concat in the 'devices' property, for example: - -flash { - compatible = "mtd-concat"; - - devices = <&flash0 &flash1>; - - partitions { - ... - }; -}; - -The driver is added to the very end of the mtd Makefile to increase the -likelyhood of all child devices already being loaded at the time of -probing, preventing unnecessary deferred probes. - -Signed-off-by: Bernhard Frauendienst ---- - drivers/mtd/Kconfig | 2 + - drivers/mtd/Makefile | 3 + - drivers/mtd/composite/Kconfig | 12 +++ - drivers/mtd/composite/Makefile | 6 ++ - drivers/mtd/composite/virt_concat.c | 128 ++++++++++++++++++++++++++++ - 5 files changed, 151 insertions(+) - create mode 100644 drivers/mtd/composite/Kconfig - create mode 100644 drivers/mtd/composite/Makefile - create mode 100644 drivers/mtd/composite/virt_concat.c - ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -238,4 +238,6 @@ source "drivers/mtd/ubi/Kconfig" - - source "drivers/mtd/hyperbus/Kconfig" - -+source "drivers/mtd/composite/Kconfig" -+ - endif # MTD ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -33,3 +33,6 @@ obj-y += chips/ lpddr/ maps/ devices/ n - obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ - obj-$(CONFIG_MTD_UBI) += ubi/ - obj-$(CONFIG_MTD_HYPERBUS) += hyperbus/ -+ -+# Composite drivers must be loaded last -+obj-y += composite/ ---- /dev/null -+++ b/drivers/mtd/composite/Kconfig -@@ -0,0 +1,12 @@ -+menu "Composite MTD device drivers" -+ depends on MTD!=n -+ -+config MTD_VIRT_CONCAT -+ tristate "Virtual concat MTD device" -+ help -+ This driver allows creation of a virtual MTD concat device, which -+ concatenates multiple underlying MTD devices to a single device. -+ This is required by some SoC boards where multiple memory banks are -+ used as one device with partitions spanning across device boundaries. -+ -+endmenu ---- /dev/null -+++ b/drivers/mtd/composite/Makefile -@@ -0,0 +1,6 @@ -+# SPDX-License-Identifier: GPL-2.0 -+# -+# linux/drivers/mtd/composite/Makefile -+# -+ -+obj-$(CONFIG_MTD_VIRT_CONCAT) += virt_concat.o ---- /dev/null -+++ b/drivers/mtd/composite/virt_concat.c -@@ -0,0 +1,128 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Virtual concat MTD device driver -+ * -+ * Copyright (C) 2018 Bernhard Frauendienst -+ * Author: Bernhard Frauendienst, kernel@nospam.obeliks.de -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * struct of_virt_concat - platform device driver data. -+ * @cmtd the final mtd_concat device -+ * @num_devices the number of devices in @devices -+ * @devices points to an array of devices already loaded -+ */ -+struct of_virt_concat { -+ struct mtd_info *cmtd; -+ int num_devices; -+ struct mtd_info **devices; -+}; -+ -+static int virt_concat_remove(struct platform_device *pdev) -+{ -+ struct of_virt_concat *info; -+ int i; -+ -+ info = platform_get_drvdata(pdev); -+ if (!info) -+ return 0; -+ -+ // unset data for when this is called after a probe error -+ platform_set_drvdata(pdev, NULL); -+ -+ if (info->cmtd) { -+ mtd_device_unregister(info->cmtd); -+ mtd_concat_destroy(info->cmtd); -+ } -+ -+ if (info->devices) { -+ for (i = 0; i < info->num_devices; i++) -+ put_mtd_device(info->devices[i]); -+ } -+ -+ return 0; -+} -+ -+static int virt_concat_probe(struct platform_device *pdev) -+{ -+ struct device_node *node = pdev->dev.of_node; -+ struct of_phandle_iterator it; -+ struct of_virt_concat *info; -+ struct mtd_info *mtd; -+ int err = 0, count; -+ -+ count = of_count_phandle_with_args(node, "devices", NULL); -+ if (count <= 0) -+ return -EINVAL; -+ -+ info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); -+ if (!info) -+ return -ENOMEM; -+ info->devices = devm_kcalloc(&pdev->dev, count, -+ sizeof(*(info->devices)), GFP_KERNEL); -+ if (!info->devices) { -+ err = -ENOMEM; -+ goto err_remove; -+ } -+ -+ platform_set_drvdata(pdev, info); -+ -+ of_for_each_phandle(&it, err, node, "devices", NULL, 0) { -+ mtd = of_get_mtd_device_by_node(it.node); -+ if (IS_ERR(mtd)) { -+ of_node_put(it.node); -+ err = -EPROBE_DEFER; -+ goto err_remove; -+ } -+ -+ info->devices[info->num_devices++] = mtd; -+ } -+ -+ info->cmtd = mtd_concat_create(info->devices, info->num_devices, -+ dev_name(&pdev->dev)); -+ if (!info->cmtd) { -+ err = -ENXIO; -+ goto err_remove; -+ } -+ -+ info->cmtd->dev.parent = &pdev->dev; -+ mtd_set_of_node(info->cmtd, node); -+ mtd_device_register(info->cmtd, NULL, 0); -+ -+ return 0; -+ -+err_remove: -+ virt_concat_remove(pdev); -+ -+ return err; -+} -+ -+static const struct of_device_id virt_concat_of_match[] = { -+ { .compatible = "mtd-concat", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, virt_concat_of_match); -+ -+static struct platform_driver virt_concat_driver = { -+ .probe = virt_concat_probe, -+ .remove = virt_concat_remove, -+ .driver = { -+ .name = "virt-mtdconcat", -+ .of_match_table = virt_concat_of_match, -+ }, -+}; -+ -+module_platform_driver(virt_concat_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Bernhard Frauendienst "); -+MODULE_DESCRIPTION("Virtual concat MTD device driver"); diff --git a/target/linux/generic/pending-5.10/498-mtd-spi-nor-locking-support-for-MX25L6405D.patch b/target/linux/generic/pending-5.10/498-mtd-spi-nor-locking-support-for-MX25L6405D.patch deleted file mode 100644 index 62e977c8d1..0000000000 --- a/target/linux/generic/pending-5.10/498-mtd-spi-nor-locking-support-for-MX25L6405D.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 8bf2ce6ea4ee840b70f55a27f80e1cd308051b13 Mon Sep 17 00:00:00 2001 -From: Nick Hainke -Date: Mon, 27 Dec 2021 00:38:13 +0100 -Subject: [PATCH 1/2] mtd: spi-nor: locking support for MX25L6405D - -Macronix MX25L6405D supports locking with four block-protection bits. -Currently, the driver only sets three bits. If the bootloader does not -sustain the flash chip in an unlocked state, the flash might be -non-writeable. Add the corresponding flag to enable locking support with -four bits in the status register. - -Tested on Nanostation M2 XM. - -Similar to commit 7ea40b54e83b ("mtd: spi-nor: enable locking support for -MX25L12805D") - -Signed-off-by: David Bauer -Signed-off-by: Nick Hainke ---- - drivers/mtd/spi-nor/macronix.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/macronix.c -+++ b/drivers/mtd/spi-nor/macronix.c -@@ -42,7 +42,8 @@ static const struct flash_info macronix_ - { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, - { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, - { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, -- { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, -+ { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K | -+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) }, - { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) }, - { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64, - SECT_4K | SPI_NOR_DUAL_READ | diff --git a/target/linux/generic/pending-5.10/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch b/target/linux/generic/pending-5.10/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch deleted file mode 100644 index ec14f6341c..0000000000 --- a/target/linux/generic/pending-5.10/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 245224608b5368c10407da07557e546743d3c489 Mon Sep 17 00:00:00 2001 -From: Nick Hainke -Date: Mon, 27 Dec 2021 09:33:13 +0100 -Subject: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix - -Macronix flash chips seem to consist of only one status register. -These chips will not work with the "16-bit Write Status (01h) Command". -Disable SNOR_F_HAS_16BIT_SR for all Macronix chips. - -Tested with MX25L6405D. - -Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on -lock()/unlock()") - -Signed-off-by: David Bauer -Signed-off-by: Nick Hainke ---- - drivers/mtd/spi-nor/macronix.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mtd/spi-nor/macronix.c -+++ b/drivers/mtd/spi-nor/macronix.c -@@ -94,6 +94,7 @@ static void macronix_default_init(struct - { - nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; - nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode; -+ nor->flags &= ~SNOR_F_HAS_16BIT_SR; - nor->flags |= SNOR_F_HAS_LOCK; - } - diff --git a/target/linux/generic/pending-5.10/500-fs_cdrom_dependencies.patch b/target/linux/generic/pending-5.10/500-fs_cdrom_dependencies.patch deleted file mode 100644 index 620bf72b4d..0000000000 --- a/target/linux/generic/pending-5.10/500-fs_cdrom_dependencies.patch +++ /dev/null @@ -1,51 +0,0 @@ -From: Felix Fietkau -Subject: fs: Add CDROM dependencies - -Submitted-by: Felix Fietkau ---- - fs/hfs/Kconfig | 1 + - fs/hfsplus/Kconfig | 1 + - fs/isofs/Kconfig | 1 + - fs/udf/Kconfig | 1 + - 4 files changed, 4 insertions(+) - ---- a/fs/hfs/Kconfig -+++ b/fs/hfs/Kconfig -@@ -2,6 +2,7 @@ - config HFS_FS - tristate "Apple Macintosh file system support" - depends on BLOCK -+ select CDROM - select NLS - help - If you say Y here, you will be able to mount Macintosh-formatted ---- a/fs/hfsplus/Kconfig -+++ b/fs/hfsplus/Kconfig -@@ -2,6 +2,7 @@ - config HFSPLUS_FS - tristate "Apple Extended HFS file system support" - depends on BLOCK -+ select CDROM - select NLS - select NLS_UTF8 - help ---- a/fs/isofs/Kconfig -+++ b/fs/isofs/Kconfig -@@ -1,6 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0-only - config ISO9660_FS - tristate "ISO 9660 CDROM file system support" -+ select CDROM - help - This is the standard file system used on CD-ROMs. It was previously - known as "High Sierra File System" and is called "hsfs" on other ---- a/fs/udf/Kconfig -+++ b/fs/udf/Kconfig -@@ -1,6 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0-only - config UDF_FS - tristate "UDF file system support" -+ select CDROM - select CRC_ITU_T - select NLS - help diff --git a/target/linux/generic/pending-5.10/530-jffs2_make_lzma_available.patch b/target/linux/generic/pending-5.10/530-jffs2_make_lzma_available.patch deleted file mode 100644 index 52071ca673..0000000000 --- a/target/linux/generic/pending-5.10/530-jffs2_make_lzma_available.patch +++ /dev/null @@ -1,4581 +0,0 @@ -From: Alexandros C. Couloumbis -Subject: fs: add jffs2/lzma support (not activated by default yet) - -lede-commit: c2c88d315fa0e881f8b19da07b62859b915b11b2 -Signed-off-by: Alexandros C. Couloumbis ---- - fs/jffs2/Kconfig | 9 + - fs/jffs2/Makefile | 3 + - fs/jffs2/compr.c | 6 + - fs/jffs2/compr.h | 10 +- - fs/jffs2/compr_lzma.c | 128 +++ - fs/jffs2/super.c | 33 +- - include/linux/lzma.h | 62 ++ - include/linux/lzma/LzFind.h | 115 +++ - include/linux/lzma/LzHash.h | 54 + - include/linux/lzma/LzmaDec.h | 231 +++++ - include/linux/lzma/LzmaEnc.h | 80 ++ - include/linux/lzma/Types.h | 226 +++++ - include/uapi/linux/jffs2.h | 1 + - lib/Kconfig | 6 + - lib/Makefile | 12 + - lib/lzma/LzFind.c | 761 ++++++++++++++ - lib/lzma/LzmaDec.c | 999 +++++++++++++++++++ - lib/lzma/LzmaEnc.c | 2271 ++++++++++++++++++++++++++++++++++++++++++ - lib/lzma/Makefile | 7 + - 19 files changed, 5008 insertions(+), 6 deletions(-) - create mode 100644 fs/jffs2/compr_lzma.c - create mode 100644 include/linux/lzma.h - create mode 100644 include/linux/lzma/LzFind.h - create mode 100644 include/linux/lzma/LzHash.h - create mode 100644 include/linux/lzma/LzmaDec.h - create mode 100644 include/linux/lzma/LzmaEnc.h - create mode 100644 include/linux/lzma/Types.h - create mode 100644 lib/lzma/LzFind.c - create mode 100644 lib/lzma/LzmaDec.c - create mode 100644 lib/lzma/LzmaEnc.c - create mode 100644 lib/lzma/Makefile - ---- a/fs/jffs2/Kconfig -+++ b/fs/jffs2/Kconfig -@@ -136,6 +136,15 @@ config JFFS2_LZO - This feature was added in July, 2007. Say 'N' if you need - compatibility with older bootloaders or kernels. - -+config JFFS2_LZMA -+ bool "JFFS2 LZMA compression support" if JFFS2_COMPRESSION_OPTIONS -+ select LZMA_COMPRESS -+ select LZMA_DECOMPRESS -+ depends on JFFS2_FS -+ default n -+ help -+ JFFS2 wrapper to the LZMA C SDK -+ - config JFFS2_RTIME - bool "JFFS2 RTIME compression support" if JFFS2_COMPRESSION_OPTIONS - depends on JFFS2_FS ---- a/fs/jffs2/Makefile -+++ b/fs/jffs2/Makefile -@@ -19,4 +19,7 @@ jffs2-$(CONFIG_JFFS2_RUBIN) += compr_rub - jffs2-$(CONFIG_JFFS2_RTIME) += compr_rtime.o - jffs2-$(CONFIG_JFFS2_ZLIB) += compr_zlib.o - jffs2-$(CONFIG_JFFS2_LZO) += compr_lzo.o -+jffs2-$(CONFIG_JFFS2_LZMA) += compr_lzma.o - jffs2-$(CONFIG_JFFS2_SUMMARY) += summary.o -+ -+CFLAGS_compr_lzma.o += -Iinclude/linux -Ilib/lzma ---- a/fs/jffs2/compr.c -+++ b/fs/jffs2/compr.c -@@ -378,6 +378,9 @@ int __init jffs2_compressors_init(void) - #ifdef CONFIG_JFFS2_LZO - jffs2_lzo_init(); - #endif -+#ifdef CONFIG_JFFS2_LZMA -+ jffs2_lzma_init(); -+#endif - /* Setting default compression mode */ - #ifdef CONFIG_JFFS2_CMODE_NONE - jffs2_compression_mode = JFFS2_COMPR_MODE_NONE; -@@ -401,6 +404,9 @@ int __init jffs2_compressors_init(void) - int jffs2_compressors_exit(void) - { - /* Unregistering compressors */ -+#ifdef CONFIG_JFFS2_LZMA -+ jffs2_lzma_exit(); -+#endif - #ifdef CONFIG_JFFS2_LZO - jffs2_lzo_exit(); - #endif ---- a/fs/jffs2/compr.h -+++ b/fs/jffs2/compr.h -@@ -29,9 +29,9 @@ - #define JFFS2_DYNRUBIN_PRIORITY 20 - #define JFFS2_LZARI_PRIORITY 30 - #define JFFS2_RTIME_PRIORITY 50 --#define JFFS2_ZLIB_PRIORITY 60 --#define JFFS2_LZO_PRIORITY 80 -- -+#define JFFS2_LZMA_PRIORITY 70 -+#define JFFS2_ZLIB_PRIORITY 80 -+#define JFFS2_LZO_PRIORITY 90 - - #define JFFS2_RUBINMIPS_DISABLED /* RUBINs will be used only */ - #define JFFS2_DYNRUBIN_DISABLED /* for decompression */ -@@ -101,5 +101,9 @@ void jffs2_zlib_exit(void); - int jffs2_lzo_init(void); - void jffs2_lzo_exit(void); - #endif -+#ifdef CONFIG_JFFS2_LZMA -+int jffs2_lzma_init(void); -+void jffs2_lzma_exit(void); -+#endif - - #endif /* __JFFS2_COMPR_H__ */ ---- /dev/null -+++ b/fs/jffs2/compr_lzma.c -@@ -0,0 +1,128 @@ -+/* -+ * JFFS2 -- Journalling Flash File System, Version 2. -+ * -+ * For licensing information, see the file 'LICENCE' in this directory. -+ * -+ * JFFS2 wrapper to the LZMA C SDK -+ * -+ */ -+ -+#include -+#include "compr.h" -+ -+#ifdef __KERNEL__ -+ static DEFINE_MUTEX(deflate_mutex); -+#endif -+ -+CLzmaEncHandle *p; -+Byte propsEncoded[LZMA_PROPS_SIZE]; -+SizeT propsSize = sizeof(propsEncoded); -+ -+STATIC void lzma_free_workspace(void) -+{ -+ LzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc); -+} -+ -+STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props) -+{ -+ if ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL) -+ { -+ PRINT_ERROR("Failed to allocate lzma deflate workspace\n"); -+ return -ENOMEM; -+ } -+ -+ if (LzmaEnc_SetProps(p, props) != SZ_OK) -+ { -+ lzma_free_workspace(); -+ return -1; -+ } -+ -+ if (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK) -+ { -+ lzma_free_workspace(); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out, -+ uint32_t *sourcelen, uint32_t *dstlen) -+{ -+ SizeT compress_size = (SizeT)(*dstlen); -+ int ret; -+ -+ #ifdef __KERNEL__ -+ mutex_lock(&deflate_mutex); -+ #endif -+ -+ ret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen, -+ 0, NULL, &lzma_alloc, &lzma_alloc); -+ -+ #ifdef __KERNEL__ -+ mutex_unlock(&deflate_mutex); -+ #endif -+ -+ if (ret != SZ_OK) -+ return -1; -+ -+ *dstlen = (uint32_t)compress_size; -+ -+ return 0; -+} -+ -+STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out, -+ uint32_t srclen, uint32_t destlen) -+{ -+ int ret; -+ SizeT dl = (SizeT)destlen; -+ SizeT sl = (SizeT)srclen; -+ ELzmaStatus status; -+ -+ ret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded, -+ propsSize, LZMA_FINISH_ANY, &status, &lzma_alloc); -+ -+ if (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen) -+ return -1; -+ -+ return 0; -+} -+ -+static struct jffs2_compressor jffs2_lzma_comp = { -+ .priority = JFFS2_LZMA_PRIORITY, -+ .name = "lzma", -+ .compr = JFFS2_COMPR_LZMA, -+ .compress = &jffs2_lzma_compress, -+ .decompress = &jffs2_lzma_decompress, -+ .disabled = 0, -+}; -+ -+int INIT jffs2_lzma_init(void) -+{ -+ int ret; -+ CLzmaEncProps props; -+ LzmaEncProps_Init(&props); -+ -+ props.dictSize = LZMA_BEST_DICT(0x2000); -+ props.level = LZMA_BEST_LEVEL; -+ props.lc = LZMA_BEST_LC; -+ props.lp = LZMA_BEST_LP; -+ props.pb = LZMA_BEST_PB; -+ props.fb = LZMA_BEST_FB; -+ -+ ret = lzma_alloc_workspace(&props); -+ if (ret < 0) -+ return ret; -+ -+ ret = jffs2_register_compressor(&jffs2_lzma_comp); -+ if (ret) -+ lzma_free_workspace(); -+ -+ return ret; -+} -+ -+void jffs2_lzma_exit(void) -+{ -+ jffs2_unregister_compressor(&jffs2_lzma_comp); -+ lzma_free_workspace(); -+} ---- a/fs/jffs2/super.c -+++ b/fs/jffs2/super.c -@@ -374,14 +374,41 @@ static int __init init_jffs2_fs(void) - BUILD_BUG_ON(sizeof(struct jffs2_raw_inode) != 68); - BUILD_BUG_ON(sizeof(struct jffs2_raw_summary) != 32); - -- pr_info("version 2.2." -+ pr_info("version 2.2" - #ifdef CONFIG_JFFS2_FS_WRITEBUFFER - " (NAND)" - #endif - #ifdef CONFIG_JFFS2_SUMMARY -- " (SUMMARY) " -+ " (SUMMARY)" - #endif -- " © 2001-2006 Red Hat, Inc.\n"); -+#ifdef CONFIG_JFFS2_ZLIB -+ " (ZLIB)" -+#endif -+#ifdef CONFIG_JFFS2_LZO -+ " (LZO)" -+#endif -+#ifdef CONFIG_JFFS2_LZMA -+ " (LZMA)" -+#endif -+#ifdef CONFIG_JFFS2_RTIME -+ " (RTIME)" -+#endif -+#ifdef CONFIG_JFFS2_RUBIN -+ " (RUBIN)" -+#endif -+#ifdef CONFIG_JFFS2_CMODE_NONE -+ " (CMODE_NONE)" -+#endif -+#ifdef CONFIG_JFFS2_CMODE_PRIORITY -+ " (CMODE_PRIORITY)" -+#endif -+#ifdef CONFIG_JFFS2_CMODE_SIZE -+ " (CMODE_SIZE)" -+#endif -+#ifdef CONFIG_JFFS2_CMODE_FAVOURLZO -+ " (CMODE_FAVOURLZO)" -+#endif -+ " (c) 2001-2006 Red Hat, Inc.\n"); - - jffs2_inode_cachep = kmem_cache_create("jffs2_i", - sizeof(struct jffs2_inode_info), ---- /dev/null -+++ b/include/linux/lzma.h -@@ -0,0 +1,62 @@ -+#ifndef __LZMA_H__ -+#define __LZMA_H__ -+ -+#ifdef __KERNEL__ -+ #include -+ #include -+ #include -+ #include -+ #include -+ #define LZMA_MALLOC vmalloc -+ #define LZMA_FREE vfree -+ #define PRINT_ERROR(msg) printk(KERN_WARNING #msg) -+ #define INIT __init -+ #define STATIC static -+#else -+ #include -+ #include -+ #include -+ #include -+ #include -+ #include -+ #include -+ #include -+ #ifndef PAGE_SIZE -+ extern int page_size; -+ #define PAGE_SIZE page_size -+ #endif -+ #define LZMA_MALLOC malloc -+ #define LZMA_FREE free -+ #define PRINT_ERROR(msg) fprintf(stderr, msg) -+ #define INIT -+ #define STATIC -+#endif -+ -+#include "lzma/LzmaDec.h" -+#include "lzma/LzmaEnc.h" -+ -+#define LZMA_BEST_LEVEL (9) -+#define LZMA_BEST_LC (0) -+#define LZMA_BEST_LP (0) -+#define LZMA_BEST_PB (0) -+#define LZMA_BEST_FB (273) -+ -+#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2) -+ -+static void *p_lzma_malloc(void *p, size_t size) -+{ -+ if (size == 0) -+ return NULL; -+ -+ return LZMA_MALLOC(size); -+} -+ -+static void p_lzma_free(void *p, void *address) -+{ -+ if (address != NULL) -+ LZMA_FREE(address); -+} -+ -+static ISzAlloc lzma_alloc = { .Alloc = p_lzma_malloc, .Free = p_lzma_free }; -+ -+#endif ---- /dev/null -+++ b/include/linux/lzma/LzFind.h -@@ -0,0 +1,98 @@ -+/* LzFind.h -- Match finder for LZ algorithms -+2009-04-22 : Igor Pavlov : Public domain */ -+ -+#ifndef __LZ_FIND_H -+#define __LZ_FIND_H -+ -+#include "Types.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef UInt32 CLzRef; -+ -+typedef struct _CMatchFinder -+{ -+ Byte *buffer; -+ UInt32 pos; -+ UInt32 posLimit; -+ UInt32 streamPos; -+ UInt32 lenLimit; -+ -+ UInt32 cyclicBufferPos; -+ UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */ -+ -+ UInt32 matchMaxLen; -+ CLzRef *hash; -+ CLzRef *son; -+ UInt32 hashMask; -+ UInt32 cutValue; -+ -+ Byte *bufferBase; -+ ISeqInStream *stream; -+ int streamEndWasReached; -+ -+ UInt32 blockSize; -+ UInt32 keepSizeBefore; -+ UInt32 keepSizeAfter; -+ -+ UInt32 numHashBytes; -+ int directInput; -+ size_t directInputRem; -+ int btMode; -+ int bigHash; -+ UInt32 historySize; -+ UInt32 fixedHashSize; -+ UInt32 hashSizeSum; -+ UInt32 numSons; -+ SRes result; -+ UInt32 crc[256]; -+} CMatchFinder; -+ -+#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer) -+#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)]) -+ -+#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos) -+ -+void MatchFinder_Construct(CMatchFinder *p); -+ -+/* Conditions: -+ historySize <= 3 GB -+ keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB -+*/ -+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, -+ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, -+ ISzAlloc *alloc); -+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc); -+ -+/* -+Conditions: -+ Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func. -+ Mf_GetPointerToCurrentPos_Func's result must be used only before any other function -+*/ -+ -+typedef void (*Mf_Init_Func)(void *object); -+typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index); -+typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object); -+typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object); -+typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances); -+typedef void (*Mf_Skip_Func)(void *object, UInt32); -+ -+typedef struct _IMatchFinder -+{ -+ Mf_Init_Func Init; -+ Mf_GetIndexByte_Func GetIndexByte; -+ Mf_GetNumAvailableBytes_Func GetNumAvailableBytes; -+ Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos; -+ Mf_GetMatches_Func GetMatches; -+ Mf_Skip_Func Skip; -+} IMatchFinder; -+ -+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif ---- /dev/null -+++ b/include/linux/lzma/LzHash.h -@@ -0,0 +1,54 @@ -+/* LzHash.h -- HASH functions for LZ algorithms -+2009-02-07 : Igor Pavlov : Public domain */ -+ -+#ifndef __LZ_HASH_H -+#define __LZ_HASH_H -+ -+#define kHash2Size (1 << 10) -+#define kHash3Size (1 << 16) -+#define kHash4Size (1 << 20) -+ -+#define kFix3HashSize (kHash2Size) -+#define kFix4HashSize (kHash2Size + kHash3Size) -+#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size) -+ -+#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8); -+ -+#define HASH3_CALC { \ -+ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ -+ hash2Value = temp & (kHash2Size - 1); \ -+ hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; } -+ -+#define HASH4_CALC { \ -+ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ -+ hash2Value = temp & (kHash2Size - 1); \ -+ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ -+ hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; } -+ -+#define HASH5_CALC { \ -+ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ -+ hash2Value = temp & (kHash2Size - 1); \ -+ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ -+ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \ -+ hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \ -+ hash4Value &= (kHash4Size - 1); } -+ -+/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */ -+#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF; -+ -+ -+#define MT_HASH2_CALC \ -+ hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1); -+ -+#define MT_HASH3_CALC { \ -+ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ -+ hash2Value = temp & (kHash2Size - 1); \ -+ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); } -+ -+#define MT_HASH4_CALC { \ -+ UInt32 temp = p->crc[cur[0]] ^ cur[1]; \ -+ hash2Value = temp & (kHash2Size - 1); \ -+ hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \ -+ hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); } -+ -+#endif ---- /dev/null -+++ b/include/linux/lzma/LzmaDec.h -@@ -0,0 +1,130 @@ -+/* LzmaDec.h -- LZMA Decoder -+2009-02-07 : Igor Pavlov : Public domain */ -+ -+#ifndef __LZMA_DEC_H -+#define __LZMA_DEC_H -+ -+#include "Types.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/* #define _LZMA_PROB32 */ -+/* _LZMA_PROB32 can increase the speed on some CPUs, -+ but memory usage for CLzmaDec::probs will be doubled in that case */ -+ -+#ifdef _LZMA_PROB32 -+#define CLzmaProb UInt32 -+#else -+#define CLzmaProb UInt16 -+#endif -+ -+ -+/* ---------- LZMA Properties ---------- */ -+ -+#define LZMA_PROPS_SIZE 5 -+ -+typedef struct _CLzmaProps -+{ -+ unsigned lc, lp, pb; -+ UInt32 dicSize; -+} CLzmaProps; -+ -+ -+/* ---------- LZMA Decoder state ---------- */ -+ -+/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case. -+ Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */ -+ -+#define LZMA_REQUIRED_INPUT_MAX 20 -+ -+typedef struct -+{ -+ CLzmaProps prop; -+ CLzmaProb *probs; -+ Byte *dic; -+ const Byte *buf; -+ UInt32 range, code; -+ SizeT dicPos; -+ SizeT dicBufSize; -+ UInt32 processedPos; -+ UInt32 checkDicSize; -+ unsigned state; -+ UInt32 reps[4]; -+ unsigned remainLen; -+ int needFlush; -+ int needInitState; -+ UInt32 numProbs; -+ unsigned tempBufSize; -+ Byte tempBuf[LZMA_REQUIRED_INPUT_MAX]; -+} CLzmaDec; -+ -+#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; } -+ -+/* There are two types of LZMA streams: -+ 0) Stream with end mark. That end mark adds about 6 bytes to compressed size. -+ 1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */ -+ -+typedef enum -+{ -+ LZMA_FINISH_ANY, /* finish at any point */ -+ LZMA_FINISH_END /* block must be finished at the end */ -+} ELzmaFinishMode; -+ -+/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!! -+ -+ You must use LZMA_FINISH_END, when you know that current output buffer -+ covers last bytes of block. In other cases you must use LZMA_FINISH_ANY. -+ -+ If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK, -+ and output value of destLen will be less than output buffer size limit. -+ You can check status result also. -+ -+ You can use multiple checks to test data integrity after full decompression: -+ 1) Check Result and "status" variable. -+ 2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize. -+ 3) Check that output(srcLen) = compressedSize, if you know real compressedSize. -+ You must use correct finish mode in that case. */ -+ -+typedef enum -+{ -+ LZMA_STATUS_NOT_SPECIFIED, /* use main error code instead */ -+ LZMA_STATUS_FINISHED_WITH_MARK, /* stream was finished with end mark. */ -+ LZMA_STATUS_NOT_FINISHED, /* stream was not finished */ -+ LZMA_STATUS_NEEDS_MORE_INPUT, /* you must provide more input bytes */ -+ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK /* there is probability that stream was finished without end mark */ -+} ELzmaStatus; -+ -+/* ELzmaStatus is used only as output value for function call */ -+ -+/* ---------- One Call Interface ---------- */ -+ -+/* LzmaDecode -+ -+finishMode: -+ It has meaning only if the decoding reaches output limit (*destLen). -+ LZMA_FINISH_ANY - Decode just destLen bytes. -+ LZMA_FINISH_END - Stream must be finished after (*destLen). -+ -+Returns: -+ SZ_OK -+ status: -+ LZMA_STATUS_FINISHED_WITH_MARK -+ LZMA_STATUS_NOT_FINISHED -+ LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK -+ SZ_ERROR_DATA - Data error -+ SZ_ERROR_MEM - Memory allocation error -+ SZ_ERROR_UNSUPPORTED - Unsupported properties -+ SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src). -+*/ -+ -+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, -+ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, -+ ELzmaStatus *status, ISzAlloc *alloc); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif ---- /dev/null -+++ b/include/linux/lzma/LzmaEnc.h -@@ -0,0 +1,60 @@ -+/* LzmaEnc.h -- LZMA Encoder -+2009-02-07 : Igor Pavlov : Public domain */ -+ -+#ifndef __LZMA_ENC_H -+#define __LZMA_ENC_H -+ -+#include "Types.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#define LZMA_PROPS_SIZE 5 -+ -+typedef struct _CLzmaEncProps -+{ -+ int level; /* 0 <= level <= 9 */ -+ UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version -+ (1 << 12) <= dictSize <= (1 << 30) for 64-bit version -+ default = (1 << 24) */ -+ int lc; /* 0 <= lc <= 8, default = 3 */ -+ int lp; /* 0 <= lp <= 4, default = 0 */ -+ int pb; /* 0 <= pb <= 4, default = 2 */ -+ int algo; /* 0 - fast, 1 - normal, default = 1 */ -+ int fb; /* 5 <= fb <= 273, default = 32 */ -+ int btMode; /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */ -+ int numHashBytes; /* 2, 3 or 4, default = 4 */ -+ UInt32 mc; /* 1 <= mc <= (1 << 30), default = 32 */ -+ unsigned writeEndMark; /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */ -+ int numThreads; /* 1 or 2, default = 2 */ -+} CLzmaEncProps; -+ -+void LzmaEncProps_Init(CLzmaEncProps *p); -+ -+/* ---------- CLzmaEncHandle Interface ---------- */ -+ -+/* LzmaEnc_* functions can return the following exit codes: -+Returns: -+ SZ_OK - OK -+ SZ_ERROR_MEM - Memory allocation error -+ SZ_ERROR_PARAM - Incorrect paramater in props -+ SZ_ERROR_WRITE - Write callback error. -+ SZ_ERROR_PROGRESS - some break from progress callback -+ SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version) -+*/ -+ -+typedef void * CLzmaEncHandle; -+ -+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc); -+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig); -+SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props); -+SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size); -+SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, -+ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif ---- /dev/null -+++ b/include/linux/lzma/Types.h -@@ -0,0 +1,226 @@ -+/* Types.h -- Basic types -+2009-11-23 : Igor Pavlov : Public domain */ -+ -+#ifndef __7Z_TYPES_H -+#define __7Z_TYPES_H -+ -+#include -+ -+#ifdef _WIN32 -+#include -+#endif -+ -+#ifndef EXTERN_C_BEGIN -+#ifdef __cplusplus -+#define EXTERN_C_BEGIN extern "C" { -+#define EXTERN_C_END } -+#else -+#define EXTERN_C_BEGIN -+#define EXTERN_C_END -+#endif -+#endif -+ -+EXTERN_C_BEGIN -+ -+#define SZ_OK 0 -+ -+#define SZ_ERROR_DATA 1 -+#define SZ_ERROR_MEM 2 -+#define SZ_ERROR_CRC 3 -+#define SZ_ERROR_UNSUPPORTED 4 -+#define SZ_ERROR_PARAM 5 -+#define SZ_ERROR_INPUT_EOF 6 -+#define SZ_ERROR_OUTPUT_EOF 7 -+#define SZ_ERROR_READ 8 -+#define SZ_ERROR_WRITE 9 -+#define SZ_ERROR_PROGRESS 10 -+#define SZ_ERROR_FAIL 11 -+#define SZ_ERROR_THREAD 12 -+ -+#define SZ_ERROR_ARCHIVE 16 -+#define SZ_ERROR_NO_ARCHIVE 17 -+ -+typedef int SRes; -+ -+#ifdef _WIN32 -+typedef DWORD WRes; -+#else -+typedef int WRes; -+#endif -+ -+#ifndef RINOK -+#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; } -+#endif -+ -+typedef unsigned char Byte; -+typedef short Int16; -+typedef unsigned short UInt16; -+ -+#ifdef _LZMA_UINT32_IS_ULONG -+typedef long Int32; -+typedef unsigned long UInt32; -+#else -+typedef int Int32; -+typedef unsigned int UInt32; -+#endif -+ -+#ifdef _SZ_NO_INT_64 -+ -+/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers. -+ NOTES: Some code will work incorrectly in that case! */ -+ -+typedef long Int64; -+typedef unsigned long UInt64; -+ -+#else -+ -+#if defined(_MSC_VER) || defined(__BORLANDC__) -+typedef __int64 Int64; -+typedef unsigned __int64 UInt64; -+#else -+typedef long long int Int64; -+typedef unsigned long long int UInt64; -+#endif -+ -+#endif -+ -+#ifdef _LZMA_NO_SYSTEM_SIZE_T -+typedef UInt32 SizeT; -+#else -+typedef size_t SizeT; -+#endif -+ -+typedef int Bool; -+#define True 1 -+#define False 0 -+ -+ -+#ifdef _WIN32 -+#define MY_STD_CALL __stdcall -+#else -+#define MY_STD_CALL -+#endif -+ -+#ifdef _MSC_VER -+ -+#if _MSC_VER >= 1300 -+#define MY_NO_INLINE __declspec(noinline) -+#else -+#define MY_NO_INLINE -+#endif -+ -+#define MY_CDECL __cdecl -+#define MY_FAST_CALL __fastcall -+ -+#else -+ -+#define MY_CDECL -+#define MY_FAST_CALL -+ -+#endif -+ -+ -+/* The following interfaces use first parameter as pointer to structure */ -+ -+typedef struct -+{ -+ SRes (*Read)(void *p, void *buf, size_t *size); -+ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. -+ (output(*size) < input(*size)) is allowed */ -+} ISeqInStream; -+ -+/* it can return SZ_ERROR_INPUT_EOF */ -+SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size); -+SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType); -+SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf); -+ -+typedef struct -+{ -+ size_t (*Write)(void *p, const void *buf, size_t size); -+ /* Returns: result - the number of actually written bytes. -+ (result < size) means error */ -+} ISeqOutStream; -+ -+typedef enum -+{ -+ SZ_SEEK_SET = 0, -+ SZ_SEEK_CUR = 1, -+ SZ_SEEK_END = 2 -+} ESzSeek; -+ -+typedef struct -+{ -+ SRes (*Read)(void *p, void *buf, size_t *size); /* same as ISeqInStream::Read */ -+ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); -+} ISeekInStream; -+ -+typedef struct -+{ -+ SRes (*Look)(void *p, void **buf, size_t *size); -+ /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream. -+ (output(*size) > input(*size)) is not allowed -+ (output(*size) < input(*size)) is allowed */ -+ SRes (*Skip)(void *p, size_t offset); -+ /* offset must be <= output(*size) of Look */ -+ -+ SRes (*Read)(void *p, void *buf, size_t *size); -+ /* reads directly (without buffer). It's same as ISeqInStream::Read */ -+ SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin); -+} ILookInStream; -+ -+SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size); -+SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset); -+ -+/* reads via ILookInStream::Read */ -+SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType); -+SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size); -+ -+#define LookToRead_BUF_SIZE (1 << 14) -+ -+typedef struct -+{ -+ ILookInStream s; -+ ISeekInStream *realStream; -+ size_t pos; -+ size_t size; -+ Byte buf[LookToRead_BUF_SIZE]; -+} CLookToRead; -+ -+void LookToRead_CreateVTable(CLookToRead *p, int lookahead); -+void LookToRead_Init(CLookToRead *p); -+ -+typedef struct -+{ -+ ISeqInStream s; -+ ILookInStream *realStream; -+} CSecToLook; -+ -+void SecToLook_CreateVTable(CSecToLook *p); -+ -+typedef struct -+{ -+ ISeqInStream s; -+ ILookInStream *realStream; -+} CSecToRead; -+ -+void SecToRead_CreateVTable(CSecToRead *p); -+ -+typedef struct -+{ -+ SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize); -+ /* Returns: result. (result != SZ_OK) means break. -+ Value (UInt64)(Int64)-1 for size means unknown value. */ -+} ICompressProgress; -+ -+typedef struct -+{ -+ void *(*Alloc)(void *p, size_t size); -+ void (*Free)(void *p, void *address); /* address can be 0 */ -+} ISzAlloc; -+ -+#define IAlloc_Alloc(p, size) (p)->Alloc((p), size) -+#define IAlloc_Free(p, a) (p)->Free((p), a) -+ -+EXTERN_C_END -+ -+#endif ---- a/include/uapi/linux/jffs2.h -+++ b/include/uapi/linux/jffs2.h -@@ -46,6 +46,7 @@ - #define JFFS2_COMPR_DYNRUBIN 0x05 - #define JFFS2_COMPR_ZLIB 0x06 - #define JFFS2_COMPR_LZO 0x07 -+#define JFFS2_COMPR_LZMA 0x08 - /* Compatibility flags. */ - #define JFFS2_COMPAT_MASK 0xc000 /* What do to if an unknown nodetype is found */ - #define JFFS2_NODE_ACCURATE 0x2000 ---- a/lib/Kconfig -+++ b/lib/Kconfig -@@ -320,6 +320,12 @@ config ZSTD_DECOMPRESS - - source "lib/xz/Kconfig" - -+config LZMA_COMPRESS -+ tristate -+ -+config LZMA_DECOMPRESS -+ tristate -+ - # - # These all provide a common interface (hence the apparent duplication with - # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.) ---- a/lib/Makefile -+++ b/lib/Makefile -@@ -136,6 +136,16 @@ CFLAGS_kobject.o += -DDEBUG - CFLAGS_kobject_uevent.o += -DDEBUG - endif - -+ifdef CONFIG_JFFS2_ZLIB -+ CONFIG_ZLIB_INFLATE:=y -+ CONFIG_ZLIB_DEFLATE:=y -+endif -+ -+ifdef CONFIG_JFFS2_LZMA -+ CONFIG_LZMA_DECOMPRESS:=y -+ CONFIG_LZMA_COMPRESS:=y -+endif -+ - obj-$(CONFIG_DEBUG_INFO_REDUCED) += debug_info.o - CFLAGS_debug_info.o += $(call cc-option, -femit-struct-debug-detailed=any) - -@@ -191,6 +201,8 @@ obj-$(CONFIG_ZSTD_COMPRESS) += zstd/ - obj-$(CONFIG_ZSTD_DECOMPRESS) += zstd/ - obj-$(CONFIG_XZ_DEC) += xz/ - obj-$(CONFIG_RAID6_PQ) += raid6/ -+obj-$(CONFIG_LZMA_COMPRESS) += lzma/ -+obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/ - - lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o - lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o ---- /dev/null -+++ b/lib/lzma/LzFind.c -@@ -0,0 +1,522 @@ -+/* LzFind.c -- Match finder for LZ algorithms -+2009-04-22 : Igor Pavlov : Public domain */ -+ -+#include -+ -+#include "LzFind.h" -+#include "LzHash.h" -+ -+#define kEmptyHashValue 0 -+#define kMaxValForNormalize ((UInt32)0xFFFFFFFF) -+#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */ -+#define kNormalizeMask (~(kNormalizeStepMin - 1)) -+#define kMaxHistorySize ((UInt32)3 << 30) -+ -+#define kStartMaxLen 3 -+ -+#if 0 -+#define DIRECT_INPUT p->directInput -+#else -+#define DIRECT_INPUT 1 -+#endif -+ -+static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc) -+{ -+ if (!DIRECT_INPUT) -+ { -+ alloc->Free(alloc, p->bufferBase); -+ p->bufferBase = 0; -+ } -+} -+ -+/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */ -+ -+static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc) -+{ -+ UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv; -+ if (DIRECT_INPUT) -+ { -+ p->blockSize = blockSize; -+ return 1; -+ } -+ if (p->bufferBase == 0 || p->blockSize != blockSize) -+ { -+ LzInWindow_Free(p, alloc); -+ p->blockSize = blockSize; -+ p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize); -+ } -+ return (p->bufferBase != 0); -+} -+ -+static Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; } -+static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; } -+ -+static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; } -+ -+static void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue) -+{ -+ p->posLimit -= subValue; -+ p->pos -= subValue; -+ p->streamPos -= subValue; -+} -+ -+static void MatchFinder_ReadBlock(CMatchFinder *p) -+{ -+ if (p->streamEndWasReached || p->result != SZ_OK) -+ return; -+ if (DIRECT_INPUT) -+ { -+ UInt32 curSize = 0xFFFFFFFF - p->streamPos; -+ if (curSize > p->directInputRem) -+ curSize = (UInt32)p->directInputRem; -+ p->directInputRem -= curSize; -+ p->streamPos += curSize; -+ if (p->directInputRem == 0) -+ p->streamEndWasReached = 1; -+ return; -+ } -+ for (;;) -+ { -+ Byte *dest = p->buffer + (p->streamPos - p->pos); -+ size_t size = (p->bufferBase + p->blockSize - dest); -+ if (size == 0) -+ return; -+ p->result = p->stream->Read(p->stream, dest, &size); -+ if (p->result != SZ_OK) -+ return; -+ if (size == 0) -+ { -+ p->streamEndWasReached = 1; -+ return; -+ } -+ p->streamPos += (UInt32)size; -+ if (p->streamPos - p->pos > p->keepSizeAfter) -+ return; -+ } -+} -+ -+static void MatchFinder_MoveBlock(CMatchFinder *p) -+{ -+ memmove(p->bufferBase, -+ p->buffer - p->keepSizeBefore, -+ (size_t)(p->streamPos - p->pos + p->keepSizeBefore)); -+ p->buffer = p->bufferBase + p->keepSizeBefore; -+} -+ -+static int MatchFinder_NeedMove(CMatchFinder *p) -+{ -+ if (DIRECT_INPUT) -+ return 0; -+ /* if (p->streamEndWasReached) return 0; */ -+ return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter); -+} -+ -+static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p) -+{ -+ if (MatchFinder_NeedMove(p)) -+ MatchFinder_MoveBlock(p); -+ MatchFinder_ReadBlock(p); -+} -+ -+static void MatchFinder_SetDefaultSettings(CMatchFinder *p) -+{ -+ p->cutValue = 32; -+ p->btMode = 1; -+ p->numHashBytes = 4; -+ p->bigHash = 0; -+} -+ -+#define kCrcPoly 0xEDB88320 -+ -+void MatchFinder_Construct(CMatchFinder *p) -+{ -+ UInt32 i; -+ p->bufferBase = 0; -+ p->directInput = 0; -+ p->hash = 0; -+ MatchFinder_SetDefaultSettings(p); -+ -+ for (i = 0; i < 256; i++) -+ { -+ UInt32 r = i; -+ int j; -+ for (j = 0; j < 8; j++) -+ r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1)); -+ p->crc[i] = r; -+ } -+} -+ -+static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc) -+{ -+ alloc->Free(alloc, p->hash); -+ p->hash = 0; -+} -+ -+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc) -+{ -+ MatchFinder_FreeThisClassMemory(p, alloc); -+ LzInWindow_Free(p, alloc); -+} -+ -+static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc) -+{ -+ size_t sizeInBytes = (size_t)num * sizeof(CLzRef); -+ if (sizeInBytes / sizeof(CLzRef) != num) -+ return 0; -+ return (CLzRef *)alloc->Alloc(alloc, sizeInBytes); -+} -+ -+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, -+ UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter, -+ ISzAlloc *alloc) -+{ -+ UInt32 sizeReserv; -+ if (historySize > kMaxHistorySize) -+ { -+ MatchFinder_Free(p, alloc); -+ return 0; -+ } -+ sizeReserv = historySize >> 1; -+ if (historySize > ((UInt32)2 << 30)) -+ sizeReserv = historySize >> 2; -+ sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19); -+ -+ p->keepSizeBefore = historySize + keepAddBufferBefore + 1; -+ p->keepSizeAfter = matchMaxLen + keepAddBufferAfter; -+ /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */ -+ if (LzInWindow_Create(p, sizeReserv, alloc)) -+ { -+ UInt32 newCyclicBufferSize = historySize + 1; -+ UInt32 hs; -+ p->matchMaxLen = matchMaxLen; -+ { -+ p->fixedHashSize = 0; -+ if (p->numHashBytes == 2) -+ hs = (1 << 16) - 1; -+ else -+ { -+ hs = historySize - 1; -+ hs |= (hs >> 1); -+ hs |= (hs >> 2); -+ hs |= (hs >> 4); -+ hs |= (hs >> 8); -+ hs >>= 1; -+ hs |= 0xFFFF; /* don't change it! It's required for Deflate */ -+ if (hs > (1 << 24)) -+ { -+ if (p->numHashBytes == 3) -+ hs = (1 << 24) - 1; -+ else -+ hs >>= 1; -+ } -+ } -+ p->hashMask = hs; -+ hs++; -+ if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size; -+ if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size; -+ if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size; -+ hs += p->fixedHashSize; -+ } -+ -+ { -+ UInt32 prevSize = p->hashSizeSum + p->numSons; -+ UInt32 newSize; -+ p->historySize = historySize; -+ p->hashSizeSum = hs; -+ p->cyclicBufferSize = newCyclicBufferSize; -+ p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize); -+ newSize = p->hashSizeSum + p->numSons; -+ if (p->hash != 0 && prevSize == newSize) -+ return 1; -+ MatchFinder_FreeThisClassMemory(p, alloc); -+ p->hash = AllocRefs(newSize, alloc); -+ if (p->hash != 0) -+ { -+ p->son = p->hash + p->hashSizeSum; -+ return 1; -+ } -+ } -+ } -+ MatchFinder_Free(p, alloc); -+ return 0; -+} -+ -+static void MatchFinder_SetLimits(CMatchFinder *p) -+{ -+ UInt32 limit = kMaxValForNormalize - p->pos; -+ UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos; -+ if (limit2 < limit) -+ limit = limit2; -+ limit2 = p->streamPos - p->pos; -+ if (limit2 <= p->keepSizeAfter) -+ { -+ if (limit2 > 0) -+ limit2 = 1; -+ } -+ else -+ limit2 -= p->keepSizeAfter; -+ if (limit2 < limit) -+ limit = limit2; -+ { -+ UInt32 lenLimit = p->streamPos - p->pos; -+ if (lenLimit > p->matchMaxLen) -+ lenLimit = p->matchMaxLen; -+ p->lenLimit = lenLimit; -+ } -+ p->posLimit = p->pos + limit; -+} -+ -+static void MatchFinder_Init(CMatchFinder *p) -+{ -+ UInt32 i; -+ for (i = 0; i < p->hashSizeSum; i++) -+ p->hash[i] = kEmptyHashValue; -+ p->cyclicBufferPos = 0; -+ p->buffer = p->bufferBase; -+ p->pos = p->streamPos = p->cyclicBufferSize; -+ p->result = SZ_OK; -+ p->streamEndWasReached = 0; -+ MatchFinder_ReadBlock(p); -+ MatchFinder_SetLimits(p); -+} -+ -+static UInt32 MatchFinder_GetSubValue(CMatchFinder *p) -+{ -+ return (p->pos - p->historySize - 1) & kNormalizeMask; -+} -+ -+static void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems) -+{ -+ UInt32 i; -+ for (i = 0; i < numItems; i++) -+ { -+ UInt32 value = items[i]; -+ if (value <= subValue) -+ value = kEmptyHashValue; -+ else -+ value -= subValue; -+ items[i] = value; -+ } -+} -+ -+static void MatchFinder_Normalize(CMatchFinder *p) -+{ -+ UInt32 subValue = MatchFinder_GetSubValue(p); -+ MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons); -+ MatchFinder_ReduceOffsets(p, subValue); -+} -+ -+static void MatchFinder_CheckLimits(CMatchFinder *p) -+{ -+ if (p->pos == kMaxValForNormalize) -+ MatchFinder_Normalize(p); -+ if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos) -+ MatchFinder_CheckAndMoveAndRead(p); -+ if (p->cyclicBufferPos == p->cyclicBufferSize) -+ p->cyclicBufferPos = 0; -+ MatchFinder_SetLimits(p); -+} -+ -+static UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, -+ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, -+ UInt32 *distances, UInt32 maxLen) -+{ -+ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; -+ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); -+ UInt32 len0 = 0, len1 = 0; -+ for (;;) -+ { -+ UInt32 delta = pos - curMatch; -+ if (cutValue-- == 0 || delta >= _cyclicBufferSize) -+ { -+ *ptr0 = *ptr1 = kEmptyHashValue; -+ return distances; -+ } -+ { -+ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); -+ const Byte *pb = cur - delta; -+ UInt32 len = (len0 < len1 ? len0 : len1); -+ if (pb[len] == cur[len]) -+ { -+ if (++len != lenLimit && pb[len] == cur[len]) -+ while (++len != lenLimit) -+ if (pb[len] != cur[len]) -+ break; -+ if (maxLen < len) -+ { -+ *distances++ = maxLen = len; -+ *distances++ = delta - 1; -+ if (len == lenLimit) -+ { -+ *ptr1 = pair[0]; -+ *ptr0 = pair[1]; -+ return distances; -+ } -+ } -+ } -+ if (pb[len] < cur[len]) -+ { -+ *ptr1 = curMatch; -+ ptr1 = pair + 1; -+ curMatch = *ptr1; -+ len1 = len; -+ } -+ else -+ { -+ *ptr0 = curMatch; -+ ptr0 = pair; -+ curMatch = *ptr0; -+ len0 = len; -+ } -+ } -+ } -+} -+ -+static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, -+ UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue) -+{ -+ CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1; -+ CLzRef *ptr1 = son + (_cyclicBufferPos << 1); -+ UInt32 len0 = 0, len1 = 0; -+ for (;;) -+ { -+ UInt32 delta = pos - curMatch; -+ if (cutValue-- == 0 || delta >= _cyclicBufferSize) -+ { -+ *ptr0 = *ptr1 = kEmptyHashValue; -+ return; -+ } -+ { -+ CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1); -+ const Byte *pb = cur - delta; -+ UInt32 len = (len0 < len1 ? len0 : len1); -+ if (pb[len] == cur[len]) -+ { -+ while (++len != lenLimit) -+ if (pb[len] != cur[len]) -+ break; -+ { -+ if (len == lenLimit) -+ { -+ *ptr1 = pair[0]; -+ *ptr0 = pair[1]; -+ return; -+ } -+ } -+ } -+ if (pb[len] < cur[len]) -+ { -+ *ptr1 = curMatch; -+ ptr1 = pair + 1; -+ curMatch = *ptr1; -+ len1 = len; -+ } -+ else -+ { -+ *ptr0 = curMatch; -+ ptr0 = pair; -+ curMatch = *ptr0; -+ len0 = len; -+ } -+ } -+ } -+} -+ -+#define MOVE_POS \ -+ ++p->cyclicBufferPos; \ -+ p->buffer++; \ -+ if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p); -+ -+static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; } -+ -+#define MOVE_POS_RET MatchFinder_MovePos(p); return offset; -+ -+#define GET_MATCHES_HEADER2(minLen, ret_op) \ -+ UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \ -+ lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \ -+ cur = p->buffer; -+ -+#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0) -+#define SKIP_HEADER(minLen) GET_MATCHES_HEADER2(minLen, continue) -+ -+#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue -+ -+#define GET_MATCHES_FOOTER(offset, maxLen) \ -+ offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \ -+ distances + offset, maxLen) - distances); MOVE_POS_RET; -+ -+#define SKIP_FOOTER \ -+ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MatchFinder_MovePos(p); -+ -+static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances) -+{ -+ UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset; -+ GET_MATCHES_HEADER(4) -+ -+ HASH4_CALC; -+ -+ delta2 = p->pos - p->hash[ hash2Value]; -+ delta3 = p->pos - p->hash[kFix3HashSize + hash3Value]; -+ curMatch = p->hash[kFix4HashSize + hashValue]; -+ -+ p->hash[ hash2Value] = -+ p->hash[kFix3HashSize + hash3Value] = -+ p->hash[kFix4HashSize + hashValue] = p->pos; -+ -+ maxLen = 1; -+ offset = 0; -+ if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur) -+ { -+ distances[0] = maxLen = 2; -+ distances[1] = delta2 - 1; -+ offset = 2; -+ } -+ if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur) -+ { -+ maxLen = 3; -+ distances[offset + 1] = delta3 - 1; -+ offset += 2; -+ delta2 = delta3; -+ } -+ if (offset != 0) -+ { -+ for (; maxLen != lenLimit; maxLen++) -+ if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen]) -+ break; -+ distances[offset - 2] = maxLen; -+ if (maxLen == lenLimit) -+ { -+ SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); -+ MOVE_POS_RET; -+ } -+ } -+ if (maxLen < 3) -+ maxLen = 3; -+ GET_MATCHES_FOOTER(offset, maxLen) -+} -+ -+static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num) -+{ -+ do -+ { -+ UInt32 hash2Value, hash3Value; -+ SKIP_HEADER(4) -+ HASH4_CALC; -+ curMatch = p->hash[kFix4HashSize + hashValue]; -+ p->hash[ hash2Value] = -+ p->hash[kFix3HashSize + hash3Value] = p->pos; -+ p->hash[kFix4HashSize + hashValue] = p->pos; -+ SKIP_FOOTER -+ } -+ while (--num != 0); -+} -+ -+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable) -+{ -+ vTable->Init = (Mf_Init_Func)MatchFinder_Init; -+ vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte; -+ vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes; -+ vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos; -+ vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches; -+ vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip; -+} ---- /dev/null -+++ b/lib/lzma/LzmaDec.c -@@ -0,0 +1,925 @@ -+/* LzmaDec.c -- LZMA Decoder -+2009-09-20 : Igor Pavlov : Public domain */ -+ -+#include "LzmaDec.h" -+ -+#include -+ -+#define kNumTopBits 24 -+#define kTopValue ((UInt32)1 << kNumTopBits) -+ -+#define kNumBitModelTotalBits 11 -+#define kBitModelTotal (1 << kNumBitModelTotalBits) -+#define kNumMoveBits 5 -+ -+#define RC_INIT_SIZE 5 -+ -+#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); } -+ -+#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) -+#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits)); -+#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits)); -+#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \ -+ { UPDATE_0(p); i = (i + i); A0; } else \ -+ { UPDATE_1(p); i = (i + i) + 1; A1; } -+#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;) -+ -+#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); } -+#define TREE_DECODE(probs, limit, i) \ -+ { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; } -+ -+/* #define _LZMA_SIZE_OPT */ -+ -+#ifdef _LZMA_SIZE_OPT -+#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i) -+#else -+#define TREE_6_DECODE(probs, i) \ -+ { i = 1; \ -+ TREE_GET_BIT(probs, i); \ -+ TREE_GET_BIT(probs, i); \ -+ TREE_GET_BIT(probs, i); \ -+ TREE_GET_BIT(probs, i); \ -+ TREE_GET_BIT(probs, i); \ -+ TREE_GET_BIT(probs, i); \ -+ i -= 0x40; } -+#endif -+ -+#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); } -+ -+#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound) -+#define UPDATE_0_CHECK range = bound; -+#define UPDATE_1_CHECK range -= bound; code -= bound; -+#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \ -+ { UPDATE_0_CHECK; i = (i + i); A0; } else \ -+ { UPDATE_1_CHECK; i = (i + i) + 1; A1; } -+#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;) -+#define TREE_DECODE_CHECK(probs, limit, i) \ -+ { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; } -+ -+ -+#define kNumPosBitsMax 4 -+#define kNumPosStatesMax (1 << kNumPosBitsMax) -+ -+#define kLenNumLowBits 3 -+#define kLenNumLowSymbols (1 << kLenNumLowBits) -+#define kLenNumMidBits 3 -+#define kLenNumMidSymbols (1 << kLenNumMidBits) -+#define kLenNumHighBits 8 -+#define kLenNumHighSymbols (1 << kLenNumHighBits) -+ -+#define LenChoice 0 -+#define LenChoice2 (LenChoice + 1) -+#define LenLow (LenChoice2 + 1) -+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) -+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -+#define kNumLenProbs (LenHigh + kLenNumHighSymbols) -+ -+ -+#define kNumStates 12 -+#define kNumLitStates 7 -+ -+#define kStartPosModelIndex 4 -+#define kEndPosModelIndex 14 -+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) -+ -+#define kNumPosSlotBits 6 -+#define kNumLenToPosStates 4 -+ -+#define kNumAlignBits 4 -+#define kAlignTableSize (1 << kNumAlignBits) -+ -+#define kMatchMinLen 2 -+#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) -+ -+#define IsMatch 0 -+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) -+#define IsRepG0 (IsRep + kNumStates) -+#define IsRepG1 (IsRepG0 + kNumStates) -+#define IsRepG2 (IsRepG1 + kNumStates) -+#define IsRep0Long (IsRepG2 + kNumStates) -+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) -+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) -+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) -+#define LenCoder (Align + kAlignTableSize) -+#define RepLenCoder (LenCoder + kNumLenProbs) -+#define Literal (RepLenCoder + kNumLenProbs) -+ -+#define LZMA_BASE_SIZE 1846 -+#define LZMA_LIT_SIZE 768 -+ -+#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp))) -+ -+#if Literal != LZMA_BASE_SIZE -+StopCompilingDueBUG -+#endif -+ -+#define LZMA_DIC_MIN (1 << 12) -+ -+/* First LZMA-symbol is always decoded. -+And it decodes new LZMA-symbols while (buf < bufLimit), but "buf" is without last normalization -+Out: -+ Result: -+ SZ_OK - OK -+ SZ_ERROR_DATA - Error -+ p->remainLen: -+ < kMatchSpecLenStart : normal remain -+ = kMatchSpecLenStart : finished -+ = kMatchSpecLenStart + 1 : Flush marker -+ = kMatchSpecLenStart + 2 : State Init Marker -+*/ -+ -+static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit) -+{ -+ CLzmaProb *probs = p->probs; -+ -+ unsigned state = p->state; -+ UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3]; -+ unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1; -+ unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1; -+ unsigned lc = p->prop.lc; -+ -+ Byte *dic = p->dic; -+ SizeT dicBufSize = p->dicBufSize; -+ SizeT dicPos = p->dicPos; -+ -+ UInt32 processedPos = p->processedPos; -+ UInt32 checkDicSize = p->checkDicSize; -+ unsigned len = 0; -+ -+ const Byte *buf = p->buf; -+ UInt32 range = p->range; -+ UInt32 code = p->code; -+ -+ do -+ { -+ CLzmaProb *prob; -+ UInt32 bound; -+ unsigned ttt; -+ unsigned posState = processedPos & pbMask; -+ -+ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; -+ IF_BIT_0(prob) -+ { -+ unsigned symbol; -+ UPDATE_0(prob); -+ prob = probs + Literal; -+ if (checkDicSize != 0 || processedPos != 0) -+ prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) + -+ (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc)))); -+ -+ if (state < kNumLitStates) -+ { -+ state -= (state < 4) ? state : 3; -+ symbol = 1; -+ do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100); -+ } -+ else -+ { -+ unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; -+ unsigned offs = 0x100; -+ state -= (state < 10) ? 3 : 6; -+ symbol = 1; -+ do -+ { -+ unsigned bit; -+ CLzmaProb *probLit; -+ matchByte <<= 1; -+ bit = (matchByte & offs); -+ probLit = prob + offs + bit + symbol; -+ GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit) -+ } -+ while (symbol < 0x100); -+ } -+ dic[dicPos++] = (Byte)symbol; -+ processedPos++; -+ continue; -+ } -+ else -+ { -+ UPDATE_1(prob); -+ prob = probs + IsRep + state; -+ IF_BIT_0(prob) -+ { -+ UPDATE_0(prob); -+ state += kNumStates; -+ prob = probs + LenCoder; -+ } -+ else -+ { -+ UPDATE_1(prob); -+ if (checkDicSize == 0 && processedPos == 0) -+ return SZ_ERROR_DATA; -+ prob = probs + IsRepG0 + state; -+ IF_BIT_0(prob) -+ { -+ UPDATE_0(prob); -+ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; -+ IF_BIT_0(prob) -+ { -+ UPDATE_0(prob); -+ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; -+ dicPos++; -+ processedPos++; -+ state = state < kNumLitStates ? 9 : 11; -+ continue; -+ } -+ UPDATE_1(prob); -+ } -+ else -+ { -+ UInt32 distance; -+ UPDATE_1(prob); -+ prob = probs + IsRepG1 + state; -+ IF_BIT_0(prob) -+ { -+ UPDATE_0(prob); -+ distance = rep1; -+ } -+ else -+ { -+ UPDATE_1(prob); -+ prob = probs + IsRepG2 + state; -+ IF_BIT_0(prob) -+ { -+ UPDATE_0(prob); -+ distance = rep2; -+ } -+ else -+ { -+ UPDATE_1(prob); -+ distance = rep3; -+ rep3 = rep2; -+ } -+ rep2 = rep1; -+ } -+ rep1 = rep0; -+ rep0 = distance; -+ } -+ state = state < kNumLitStates ? 8 : 11; -+ prob = probs + RepLenCoder; -+ } -+ { -+ unsigned limit, offset; -+ CLzmaProb *probLen = prob + LenChoice; -+ IF_BIT_0(probLen) -+ { -+ UPDATE_0(probLen); -+ probLen = prob + LenLow + (posState << kLenNumLowBits); -+ offset = 0; -+ limit = (1 << kLenNumLowBits); -+ } -+ else -+ { -+ UPDATE_1(probLen); -+ probLen = prob + LenChoice2; -+ IF_BIT_0(probLen) -+ { -+ UPDATE_0(probLen); -+ probLen = prob + LenMid + (posState << kLenNumMidBits); -+ offset = kLenNumLowSymbols; -+ limit = (1 << kLenNumMidBits); -+ } -+ else -+ { -+ UPDATE_1(probLen); -+ probLen = prob + LenHigh; -+ offset = kLenNumLowSymbols + kLenNumMidSymbols; -+ limit = (1 << kLenNumHighBits); -+ } -+ } -+ TREE_DECODE(probLen, limit, len); -+ len += offset; -+ } -+ -+ if (state >= kNumStates) -+ { -+ UInt32 distance; -+ prob = probs + PosSlot + -+ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits); -+ TREE_6_DECODE(prob, distance); -+ if (distance >= kStartPosModelIndex) -+ { -+ unsigned posSlot = (unsigned)distance; -+ int numDirectBits = (int)(((distance >> 1) - 1)); -+ distance = (2 | (distance & 1)); -+ if (posSlot < kEndPosModelIndex) -+ { -+ distance <<= numDirectBits; -+ prob = probs + SpecPos + distance - posSlot - 1; -+ { -+ UInt32 mask = 1; -+ unsigned i = 1; -+ do -+ { -+ GET_BIT2(prob + i, i, ; , distance |= mask); -+ mask <<= 1; -+ } -+ while (--numDirectBits != 0); -+ } -+ } -+ else -+ { -+ numDirectBits -= kNumAlignBits; -+ do -+ { -+ NORMALIZE -+ range >>= 1; -+ -+ { -+ UInt32 t; -+ code -= range; -+ t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */ -+ distance = (distance << 1) + (t + 1); -+ code += range & t; -+ } -+ /* -+ distance <<= 1; -+ if (code >= range) -+ { -+ code -= range; -+ distance |= 1; -+ } -+ */ -+ } -+ while (--numDirectBits != 0); -+ prob = probs + Align; -+ distance <<= kNumAlignBits; -+ { -+ unsigned i = 1; -+ GET_BIT2(prob + i, i, ; , distance |= 1); -+ GET_BIT2(prob + i, i, ; , distance |= 2); -+ GET_BIT2(prob + i, i, ; , distance |= 4); -+ GET_BIT2(prob + i, i, ; , distance |= 8); -+ } -+ if (distance == (UInt32)0xFFFFFFFF) -+ { -+ len += kMatchSpecLenStart; -+ state -= kNumStates; -+ break; -+ } -+ } -+ } -+ rep3 = rep2; -+ rep2 = rep1; -+ rep1 = rep0; -+ rep0 = distance + 1; -+ if (checkDicSize == 0) -+ { -+ if (distance >= processedPos) -+ return SZ_ERROR_DATA; -+ } -+ else if (distance >= checkDicSize) -+ return SZ_ERROR_DATA; -+ state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3; -+ } -+ -+ len += kMatchMinLen; -+ -+ if (limit == dicPos) -+ return SZ_ERROR_DATA; -+ { -+ SizeT rem = limit - dicPos; -+ unsigned curLen = ((rem < len) ? (unsigned)rem : len); -+ SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0); -+ -+ processedPos += curLen; -+ -+ len -= curLen; -+ if (pos + curLen <= dicBufSize) -+ { -+ Byte *dest = dic + dicPos; -+ ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos; -+ const Byte *lim = dest + curLen; -+ dicPos += curLen; -+ do -+ *(dest) = (Byte)*(dest + src); -+ while (++dest != lim); -+ } -+ else -+ { -+ do -+ { -+ dic[dicPos++] = dic[pos]; -+ if (++pos == dicBufSize) -+ pos = 0; -+ } -+ while (--curLen != 0); -+ } -+ } -+ } -+ } -+ while (dicPos < limit && buf < bufLimit); -+ NORMALIZE; -+ p->buf = buf; -+ p->range = range; -+ p->code = code; -+ p->remainLen = len; -+ p->dicPos = dicPos; -+ p->processedPos = processedPos; -+ p->reps[0] = rep0; -+ p->reps[1] = rep1; -+ p->reps[2] = rep2; -+ p->reps[3] = rep3; -+ p->state = state; -+ -+ return SZ_OK; -+} -+ -+static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit) -+{ -+ if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart) -+ { -+ Byte *dic = p->dic; -+ SizeT dicPos = p->dicPos; -+ SizeT dicBufSize = p->dicBufSize; -+ unsigned len = p->remainLen; -+ UInt32 rep0 = p->reps[0]; -+ if (limit - dicPos < len) -+ len = (unsigned)(limit - dicPos); -+ -+ if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len) -+ p->checkDicSize = p->prop.dicSize; -+ -+ p->processedPos += len; -+ p->remainLen -= len; -+ while (len-- != 0) -+ { -+ dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)]; -+ dicPos++; -+ } -+ p->dicPos = dicPos; -+ } -+} -+ -+static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit) -+{ -+ do -+ { -+ SizeT limit2 = limit; -+ if (p->checkDicSize == 0) -+ { -+ UInt32 rem = p->prop.dicSize - p->processedPos; -+ if (limit - p->dicPos > rem) -+ limit2 = p->dicPos + rem; -+ } -+ RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit)); -+ if (p->processedPos >= p->prop.dicSize) -+ p->checkDicSize = p->prop.dicSize; -+ LzmaDec_WriteRem(p, limit); -+ } -+ while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart); -+ -+ if (p->remainLen > kMatchSpecLenStart) -+ { -+ p->remainLen = kMatchSpecLenStart; -+ } -+ return 0; -+} -+ -+typedef enum -+{ -+ DUMMY_ERROR, /* unexpected end of input stream */ -+ DUMMY_LIT, -+ DUMMY_MATCH, -+ DUMMY_REP -+} ELzmaDummy; -+ -+static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize) -+{ -+ UInt32 range = p->range; -+ UInt32 code = p->code; -+ const Byte *bufLimit = buf + inSize; -+ CLzmaProb *probs = p->probs; -+ unsigned state = p->state; -+ ELzmaDummy res; -+ -+ { -+ CLzmaProb *prob; -+ UInt32 bound; -+ unsigned ttt; -+ unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1); -+ -+ prob = probs + IsMatch + (state << kNumPosBitsMax) + posState; -+ IF_BIT_0_CHECK(prob) -+ { -+ UPDATE_0_CHECK -+ -+ /* if (bufLimit - buf >= 7) return DUMMY_LIT; */ -+ -+ prob = probs + Literal; -+ if (p->checkDicSize != 0 || p->processedPos != 0) -+ prob += (LZMA_LIT_SIZE * -+ ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) + -+ (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc)))); -+ -+ if (state < kNumLitStates) -+ { -+ unsigned symbol = 1; -+ do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100); -+ } -+ else -+ { -+ unsigned matchByte = p->dic[p->dicPos - p->reps[0] + -+ ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)]; -+ unsigned offs = 0x100; -+ unsigned symbol = 1; -+ do -+ { -+ unsigned bit; -+ CLzmaProb *probLit; -+ matchByte <<= 1; -+ bit = (matchByte & offs); -+ probLit = prob + offs + bit + symbol; -+ GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit) -+ } -+ while (symbol < 0x100); -+ } -+ res = DUMMY_LIT; -+ } -+ else -+ { -+ unsigned len; -+ UPDATE_1_CHECK; -+ -+ prob = probs + IsRep + state; -+ IF_BIT_0_CHECK(prob) -+ { -+ UPDATE_0_CHECK; -+ state = 0; -+ prob = probs + LenCoder; -+ res = DUMMY_MATCH; -+ } -+ else -+ { -+ UPDATE_1_CHECK; -+ res = DUMMY_REP; -+ prob = probs + IsRepG0 + state; -+ IF_BIT_0_CHECK(prob) -+ { -+ UPDATE_0_CHECK; -+ prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState; -+ IF_BIT_0_CHECK(prob) -+ { -+ UPDATE_0_CHECK; -+ NORMALIZE_CHECK; -+ return DUMMY_REP; -+ } -+ else -+ { -+ UPDATE_1_CHECK; -+ } -+ } -+ else -+ { -+ UPDATE_1_CHECK; -+ prob = probs + IsRepG1 + state; -+ IF_BIT_0_CHECK(prob) -+ { -+ UPDATE_0_CHECK; -+ } -+ else -+ { -+ UPDATE_1_CHECK; -+ prob = probs + IsRepG2 + state; -+ IF_BIT_0_CHECK(prob) -+ { -+ UPDATE_0_CHECK; -+ } -+ else -+ { -+ UPDATE_1_CHECK; -+ } -+ } -+ } -+ state = kNumStates; -+ prob = probs + RepLenCoder; -+ } -+ { -+ unsigned limit, offset; -+ CLzmaProb *probLen = prob + LenChoice; -+ IF_BIT_0_CHECK(probLen) -+ { -+ UPDATE_0_CHECK; -+ probLen = prob + LenLow + (posState << kLenNumLowBits); -+ offset = 0; -+ limit = 1 << kLenNumLowBits; -+ } -+ else -+ { -+ UPDATE_1_CHECK; -+ probLen = prob + LenChoice2; -+ IF_BIT_0_CHECK(probLen) -+ { -+ UPDATE_0_CHECK; -+ probLen = prob + LenMid + (posState << kLenNumMidBits); -+ offset = kLenNumLowSymbols; -+ limit = 1 << kLenNumMidBits; -+ } -+ else -+ { -+ UPDATE_1_CHECK; -+ probLen = prob + LenHigh; -+ offset = kLenNumLowSymbols + kLenNumMidSymbols; -+ limit = 1 << kLenNumHighBits; -+ } -+ } -+ TREE_DECODE_CHECK(probLen, limit, len); -+ len += offset; -+ } -+ -+ if (state < 4) -+ { -+ unsigned posSlot; -+ prob = probs + PosSlot + -+ ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << -+ kNumPosSlotBits); -+ TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot); -+ if (posSlot >= kStartPosModelIndex) -+ { -+ int numDirectBits = ((posSlot >> 1) - 1); -+ -+ /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */ -+ -+ if (posSlot < kEndPosModelIndex) -+ { -+ prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1; -+ } -+ else -+ { -+ numDirectBits -= kNumAlignBits; -+ do -+ { -+ NORMALIZE_CHECK -+ range >>= 1; -+ code -= range & (((code - range) >> 31) - 1); -+ /* if (code >= range) code -= range; */ -+ } -+ while (--numDirectBits != 0); -+ prob = probs + Align; -+ numDirectBits = kNumAlignBits; -+ } -+ { -+ unsigned i = 1; -+ do -+ { -+ GET_BIT_CHECK(prob + i, i); -+ } -+ while (--numDirectBits != 0); -+ } -+ } -+ } -+ } -+ } -+ NORMALIZE_CHECK; -+ return res; -+} -+ -+ -+static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data) -+{ -+ p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]); -+ p->range = 0xFFFFFFFF; -+ p->needFlush = 0; -+} -+ -+static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) -+{ -+ p->needFlush = 1; -+ p->remainLen = 0; -+ p->tempBufSize = 0; -+ -+ if (initDic) -+ { -+ p->processedPos = 0; -+ p->checkDicSize = 0; -+ p->needInitState = 1; -+ } -+ if (initState) -+ p->needInitState = 1; -+} -+ -+static void LzmaDec_Init(CLzmaDec *p) -+{ -+ p->dicPos = 0; -+ LzmaDec_InitDicAndState(p, True, True); -+} -+ -+static void LzmaDec_InitStateReal(CLzmaDec *p) -+{ -+ UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp)); -+ UInt32 i; -+ CLzmaProb *probs = p->probs; -+ for (i = 0; i < numProbs; i++) -+ probs[i] = kBitModelTotal >> 1; -+ p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1; -+ p->state = 0; -+ p->needInitState = 0; -+} -+ -+static SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, -+ ELzmaFinishMode finishMode, ELzmaStatus *status) -+{ -+ SizeT inSize = *srcLen; -+ (*srcLen) = 0; -+ LzmaDec_WriteRem(p, dicLimit); -+ -+ *status = LZMA_STATUS_NOT_SPECIFIED; -+ -+ while (p->remainLen != kMatchSpecLenStart) -+ { -+ int checkEndMarkNow; -+ -+ if (p->needFlush != 0) -+ { -+ for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--) -+ p->tempBuf[p->tempBufSize++] = *src++; -+ if (p->tempBufSize < RC_INIT_SIZE) -+ { -+ *status = LZMA_STATUS_NEEDS_MORE_INPUT; -+ return SZ_OK; -+ } -+ if (p->tempBuf[0] != 0) -+ return SZ_ERROR_DATA; -+ -+ LzmaDec_InitRc(p, p->tempBuf); -+ p->tempBufSize = 0; -+ } -+ -+ checkEndMarkNow = 0; -+ if (p->dicPos >= dicLimit) -+ { -+ if (p->remainLen == 0 && p->code == 0) -+ { -+ *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK; -+ return SZ_OK; -+ } -+ if (finishMode == LZMA_FINISH_ANY) -+ { -+ *status = LZMA_STATUS_NOT_FINISHED; -+ return SZ_OK; -+ } -+ if (p->remainLen != 0) -+ { -+ *status = LZMA_STATUS_NOT_FINISHED; -+ return SZ_ERROR_DATA; -+ } -+ checkEndMarkNow = 1; -+ } -+ -+ if (p->needInitState) -+ LzmaDec_InitStateReal(p); -+ -+ if (p->tempBufSize == 0) -+ { -+ SizeT processed; -+ const Byte *bufLimit; -+ if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) -+ { -+ int dummyRes = LzmaDec_TryDummy(p, src, inSize); -+ if (dummyRes == DUMMY_ERROR) -+ { -+ memcpy(p->tempBuf, src, inSize); -+ p->tempBufSize = (unsigned)inSize; -+ (*srcLen) += inSize; -+ *status = LZMA_STATUS_NEEDS_MORE_INPUT; -+ return SZ_OK; -+ } -+ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) -+ { -+ *status = LZMA_STATUS_NOT_FINISHED; -+ return SZ_ERROR_DATA; -+ } -+ bufLimit = src; -+ } -+ else -+ bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX; -+ p->buf = src; -+ if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0) -+ return SZ_ERROR_DATA; -+ processed = (SizeT)(p->buf - src); -+ (*srcLen) += processed; -+ src += processed; -+ inSize -= processed; -+ } -+ else -+ { -+ unsigned rem = p->tempBufSize, lookAhead = 0; -+ while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize) -+ p->tempBuf[rem++] = src[lookAhead++]; -+ p->tempBufSize = rem; -+ if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow) -+ { -+ int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem); -+ if (dummyRes == DUMMY_ERROR) -+ { -+ (*srcLen) += lookAhead; -+ *status = LZMA_STATUS_NEEDS_MORE_INPUT; -+ return SZ_OK; -+ } -+ if (checkEndMarkNow && dummyRes != DUMMY_MATCH) -+ { -+ *status = LZMA_STATUS_NOT_FINISHED; -+ return SZ_ERROR_DATA; -+ } -+ } -+ p->buf = p->tempBuf; -+ if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0) -+ return SZ_ERROR_DATA; -+ lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf)); -+ (*srcLen) += lookAhead; -+ src += lookAhead; -+ inSize -= lookAhead; -+ p->tempBufSize = 0; -+ } -+ } -+ if (p->code == 0) -+ *status = LZMA_STATUS_FINISHED_WITH_MARK; -+ return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA; -+} -+ -+static void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) -+{ -+ alloc->Free(alloc, p->probs); -+ p->probs = 0; -+} -+ -+static SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size) -+{ -+ UInt32 dicSize; -+ Byte d; -+ -+ if (size < LZMA_PROPS_SIZE) -+ return SZ_ERROR_UNSUPPORTED; -+ else -+ dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24); -+ -+ if (dicSize < LZMA_DIC_MIN) -+ dicSize = LZMA_DIC_MIN; -+ p->dicSize = dicSize; -+ -+ d = data[0]; -+ if (d >= (9 * 5 * 5)) -+ return SZ_ERROR_UNSUPPORTED; -+ -+ p->lc = d % 9; -+ d /= 9; -+ p->pb = d / 5; -+ p->lp = d % 5; -+ -+ return SZ_OK; -+} -+ -+static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc) -+{ -+ UInt32 numProbs = LzmaProps_GetNumProbs(propNew); -+ if (p->probs == 0 || numProbs != p->numProbs) -+ { -+ LzmaDec_FreeProbs(p, alloc); -+ p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb)); -+ p->numProbs = numProbs; -+ if (p->probs == 0) -+ return SZ_ERROR_MEM; -+ } -+ return SZ_OK; -+} -+ -+static SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc) -+{ -+ CLzmaProps propNew; -+ RINOK(LzmaProps_Decode(&propNew, props, propsSize)); -+ RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc)); -+ p->prop = propNew; -+ return SZ_OK; -+} -+ -+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, -+ const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, -+ ELzmaStatus *status, ISzAlloc *alloc) -+{ -+ CLzmaDec p; -+ SRes res; -+ SizeT inSize = *srcLen; -+ SizeT outSize = *destLen; -+ *srcLen = *destLen = 0; -+ if (inSize < RC_INIT_SIZE) -+ return SZ_ERROR_INPUT_EOF; -+ -+ LzmaDec_Construct(&p); -+ res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc); -+ if (res != 0) -+ return res; -+ p.dic = dest; -+ p.dicBufSize = outSize; -+ -+ LzmaDec_Init(&p); -+ -+ *srcLen = inSize; -+ res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status); -+ -+ if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT) -+ res = SZ_ERROR_INPUT_EOF; -+ -+ (*destLen) = p.dicPos; -+ LzmaDec_FreeProbs(&p, alloc); -+ return res; -+} ---- /dev/null -+++ b/lib/lzma/LzmaEnc.c -@@ -0,0 +1,2123 @@ -+/* LzmaEnc.c -- LZMA Encoder -+2009-11-24 : Igor Pavlov : Public domain */ -+ -+#include -+ -+/* #define SHOW_STAT */ -+/* #define SHOW_STAT2 */ -+ -+#if defined(SHOW_STAT) || defined(SHOW_STAT2) -+#include -+#endif -+ -+#include "LzmaEnc.h" -+ -+/* disable MT */ -+#define _7ZIP_ST -+ -+#include "LzFind.h" -+#ifndef _7ZIP_ST -+#include "LzFindMt.h" -+#endif -+ -+#ifdef SHOW_STAT -+static int ttt = 0; -+#endif -+ -+#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1) -+ -+#define kBlockSize (9 << 10) -+#define kUnpackBlockSize (1 << 18) -+#define kMatchArraySize (1 << 21) -+#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX) -+ -+#define kNumMaxDirectBits (31) -+ -+#define kNumTopBits 24 -+#define kTopValue ((UInt32)1 << kNumTopBits) -+ -+#define kNumBitModelTotalBits 11 -+#define kBitModelTotal (1 << kNumBitModelTotalBits) -+#define kNumMoveBits 5 -+#define kProbInitValue (kBitModelTotal >> 1) -+ -+#define kNumMoveReducingBits 4 -+#define kNumBitPriceShiftBits 4 -+#define kBitPrice (1 << kNumBitPriceShiftBits) -+ -+void LzmaEncProps_Init(CLzmaEncProps *p) -+{ -+ p->level = 5; -+ p->dictSize = p->mc = 0; -+ p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1; -+ p->writeEndMark = 0; -+} -+ -+static void LzmaEncProps_Normalize(CLzmaEncProps *p) -+{ -+ int level = p->level; -+ if (level < 0) level = 5; -+ p->level = level; -+ if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26))); -+ if (p->lc < 0) p->lc = 3; -+ if (p->lp < 0) p->lp = 0; -+ if (p->pb < 0) p->pb = 2; -+ if (p->algo < 0) p->algo = (level < 5 ? 0 : 1); -+ if (p->fb < 0) p->fb = (level < 7 ? 32 : 64); -+ if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1); -+ if (p->numHashBytes < 0) p->numHashBytes = 4; -+ if (p->mc == 0) p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1); -+ if (p->numThreads < 0) -+ p->numThreads = -+ #ifndef _7ZIP_ST -+ ((p->btMode && p->algo) ? 2 : 1); -+ #else -+ 1; -+ #endif -+} -+ -+static UInt32 __maybe_unused LzmaEncProps_GetDictSize(const CLzmaEncProps *props2) -+{ -+ CLzmaEncProps props = *props2; -+ LzmaEncProps_Normalize(&props); -+ return props.dictSize; -+} -+ -+/* #define LZMA_LOG_BSR */ -+/* Define it for Intel's CPU */ -+ -+ -+#ifdef LZMA_LOG_BSR -+ -+#define kDicLogSizeMaxCompress 30 -+ -+#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); } -+ -+static UInt32 GetPosSlot1(UInt32 pos) -+{ -+ UInt32 res; -+ BSR2_RET(pos, res); -+ return res; -+} -+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } -+#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); } -+ -+#else -+ -+#define kNumLogBits (9 + (int)sizeof(size_t) / 2) -+#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7) -+ -+static void LzmaEnc_FastPosInit(Byte *g_FastPos) -+{ -+ int c = 2, slotFast; -+ g_FastPos[0] = 0; -+ g_FastPos[1] = 1; -+ -+ for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++) -+ { -+ UInt32 k = (1 << ((slotFast >> 1) - 1)); -+ UInt32 j; -+ for (j = 0; j < k; j++, c++) -+ g_FastPos[c] = (Byte)slotFast; -+ } -+} -+ -+#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \ -+ (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \ -+ res = p->g_FastPos[pos >> i] + (i * 2); } -+/* -+#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \ -+ p->g_FastPos[pos >> 6] + 12 : \ -+ p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; } -+*/ -+ -+#define GetPosSlot1(pos) p->g_FastPos[pos] -+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); } -+#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); } -+ -+#endif -+ -+ -+#define LZMA_NUM_REPS 4 -+ -+typedef unsigned CState; -+ -+typedef struct -+{ -+ UInt32 price; -+ -+ CState state; -+ int prev1IsChar; -+ int prev2; -+ -+ UInt32 posPrev2; -+ UInt32 backPrev2; -+ -+ UInt32 posPrev; -+ UInt32 backPrev; -+ UInt32 backs[LZMA_NUM_REPS]; -+} COptimal; -+ -+#define kNumOpts (1 << 12) -+ -+#define kNumLenToPosStates 4 -+#define kNumPosSlotBits 6 -+#define kDicLogSizeMin 0 -+#define kDicLogSizeMax 32 -+#define kDistTableSizeMax (kDicLogSizeMax * 2) -+ -+ -+#define kNumAlignBits 4 -+#define kAlignTableSize (1 << kNumAlignBits) -+#define kAlignMask (kAlignTableSize - 1) -+ -+#define kStartPosModelIndex 4 -+#define kEndPosModelIndex 14 -+#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex) -+ -+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) -+ -+#ifdef _LZMA_PROB32 -+#define CLzmaProb UInt32 -+#else -+#define CLzmaProb UInt16 -+#endif -+ -+#define LZMA_PB_MAX 4 -+#define LZMA_LC_MAX 8 -+#define LZMA_LP_MAX 4 -+ -+#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX) -+ -+ -+#define kLenNumLowBits 3 -+#define kLenNumLowSymbols (1 << kLenNumLowBits) -+#define kLenNumMidBits 3 -+#define kLenNumMidSymbols (1 << kLenNumMidBits) -+#define kLenNumHighBits 8 -+#define kLenNumHighSymbols (1 << kLenNumHighBits) -+ -+#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols) -+ -+#define LZMA_MATCH_LEN_MIN 2 -+#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1) -+ -+#define kNumStates 12 -+ -+typedef struct -+{ -+ CLzmaProb choice; -+ CLzmaProb choice2; -+ CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits]; -+ CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits]; -+ CLzmaProb high[kLenNumHighSymbols]; -+} CLenEnc; -+ -+typedef struct -+{ -+ CLenEnc p; -+ UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal]; -+ UInt32 tableSize; -+ UInt32 counters[LZMA_NUM_PB_STATES_MAX]; -+} CLenPriceEnc; -+ -+typedef struct -+{ -+ UInt32 range; -+ Byte cache; -+ UInt64 low; -+ UInt64 cacheSize; -+ Byte *buf; -+ Byte *bufLim; -+ Byte *bufBase; -+ ISeqOutStream *outStream; -+ UInt64 processed; -+ SRes res; -+} CRangeEnc; -+ -+typedef struct -+{ -+ CLzmaProb *litProbs; -+ -+ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; -+ CLzmaProb isRep[kNumStates]; -+ CLzmaProb isRepG0[kNumStates]; -+ CLzmaProb isRepG1[kNumStates]; -+ CLzmaProb isRepG2[kNumStates]; -+ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; -+ -+ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; -+ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; -+ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; -+ -+ CLenPriceEnc lenEnc; -+ CLenPriceEnc repLenEnc; -+ -+ UInt32 reps[LZMA_NUM_REPS]; -+ UInt32 state; -+} CSaveState; -+ -+typedef struct -+{ -+ IMatchFinder matchFinder; -+ void *matchFinderObj; -+ -+ #ifndef _7ZIP_ST -+ Bool mtMode; -+ CMatchFinderMt matchFinderMt; -+ #endif -+ -+ CMatchFinder matchFinderBase; -+ -+ #ifndef _7ZIP_ST -+ Byte pad[128]; -+ #endif -+ -+ UInt32 optimumEndIndex; -+ UInt32 optimumCurrentIndex; -+ -+ UInt32 longestMatchLength; -+ UInt32 numPairs; -+ UInt32 numAvail; -+ COptimal opt[kNumOpts]; -+ -+ #ifndef LZMA_LOG_BSR -+ Byte g_FastPos[1 << kNumLogBits]; -+ #endif -+ -+ UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits]; -+ UInt32 matches[LZMA_MATCH_LEN_MAX * 2 + 2 + 1]; -+ UInt32 numFastBytes; -+ UInt32 additionalOffset; -+ UInt32 reps[LZMA_NUM_REPS]; -+ UInt32 state; -+ -+ UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax]; -+ UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances]; -+ UInt32 alignPrices[kAlignTableSize]; -+ UInt32 alignPriceCount; -+ -+ UInt32 distTableSize; -+ -+ unsigned lc, lp, pb; -+ unsigned lpMask, pbMask; -+ -+ CLzmaProb *litProbs; -+ -+ CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX]; -+ CLzmaProb isRep[kNumStates]; -+ CLzmaProb isRepG0[kNumStates]; -+ CLzmaProb isRepG1[kNumStates]; -+ CLzmaProb isRepG2[kNumStates]; -+ CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX]; -+ -+ CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits]; -+ CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex]; -+ CLzmaProb posAlignEncoder[1 << kNumAlignBits]; -+ -+ CLenPriceEnc lenEnc; -+ CLenPriceEnc repLenEnc; -+ -+ unsigned lclp; -+ -+ Bool fastMode; -+ -+ CRangeEnc rc; -+ -+ Bool writeEndMark; -+ UInt64 nowPos64; -+ UInt32 matchPriceCount; -+ Bool finished; -+ Bool multiThread; -+ -+ SRes result; -+ UInt32 dictSize; -+ UInt32 matchFinderCycles; -+ -+ int needInit; -+ -+ CSaveState saveState; -+} CLzmaEnc; -+ -+SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2) -+{ -+ CLzmaEnc *p = (CLzmaEnc *)pp; -+ CLzmaEncProps props = *props2; -+ LzmaEncProps_Normalize(&props); -+ -+ if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX || -+ props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30)) -+ return SZ_ERROR_PARAM; -+ p->dictSize = props.dictSize; -+ p->matchFinderCycles = props.mc; -+ { -+ unsigned fb = props.fb; -+ if (fb < 5) -+ fb = 5; -+ if (fb > LZMA_MATCH_LEN_MAX) -+ fb = LZMA_MATCH_LEN_MAX; -+ p->numFastBytes = fb; -+ } -+ p->lc = props.lc; -+ p->lp = props.lp; -+ p->pb = props.pb; -+ p->fastMode = (props.algo == 0); -+ p->matchFinderBase.btMode = props.btMode; -+ { -+ UInt32 numHashBytes = 4; -+ if (props.btMode) -+ { -+ if (props.numHashBytes < 2) -+ numHashBytes = 2; -+ else if (props.numHashBytes < 4) -+ numHashBytes = props.numHashBytes; -+ } -+ p->matchFinderBase.numHashBytes = numHashBytes; -+ } -+ -+ p->matchFinderBase.cutValue = props.mc; -+ -+ p->writeEndMark = props.writeEndMark; -+ -+ #ifndef _7ZIP_ST -+ /* -+ if (newMultiThread != _multiThread) -+ { -+ ReleaseMatchFinder(); -+ _multiThread = newMultiThread; -+ } -+ */ -+ p->multiThread = (props.numThreads > 1); -+ #endif -+ -+ return SZ_OK; -+} -+ -+static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 4, 5}; -+static const int kMatchNextStates[kNumStates] = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10}; -+static const int kRepNextStates[kNumStates] = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11}; -+static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11}; -+ -+#define IsCharState(s) ((s) < 7) -+ -+#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1) -+ -+#define kInfinityPrice (1 << 30) -+ -+static void RangeEnc_Construct(CRangeEnc *p) -+{ -+ p->outStream = 0; -+ p->bufBase = 0; -+} -+ -+#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize) -+ -+#define RC_BUF_SIZE (1 << 16) -+static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc) -+{ -+ if (p->bufBase == 0) -+ { -+ p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE); -+ if (p->bufBase == 0) -+ return 0; -+ p->bufLim = p->bufBase + RC_BUF_SIZE; -+ } -+ return 1; -+} -+ -+static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc) -+{ -+ alloc->Free(alloc, p->bufBase); -+ p->bufBase = 0; -+} -+ -+static void RangeEnc_Init(CRangeEnc *p) -+{ -+ /* Stream.Init(); */ -+ p->low = 0; -+ p->range = 0xFFFFFFFF; -+ p->cacheSize = 1; -+ p->cache = 0; -+ -+ p->buf = p->bufBase; -+ -+ p->processed = 0; -+ p->res = SZ_OK; -+} -+ -+static void RangeEnc_FlushStream(CRangeEnc *p) -+{ -+ size_t num; -+ if (p->res != SZ_OK) -+ return; -+ num = p->buf - p->bufBase; -+ if (num != p->outStream->Write(p->outStream, p->bufBase, num)) -+ p->res = SZ_ERROR_WRITE; -+ p->processed += num; -+ p->buf = p->bufBase; -+} -+ -+static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p) -+{ -+ if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0) -+ { -+ Byte temp = p->cache; -+ do -+ { -+ Byte *buf = p->buf; -+ *buf++ = (Byte)(temp + (Byte)(p->low >> 32)); -+ p->buf = buf; -+ if (buf == p->bufLim) -+ RangeEnc_FlushStream(p); -+ temp = 0xFF; -+ } -+ while (--p->cacheSize != 0); -+ p->cache = (Byte)((UInt32)p->low >> 24); -+ } -+ p->cacheSize++; -+ p->low = (UInt32)p->low << 8; -+} -+ -+static void RangeEnc_FlushData(CRangeEnc *p) -+{ -+ int i; -+ for (i = 0; i < 5; i++) -+ RangeEnc_ShiftLow(p); -+} -+ -+static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits) -+{ -+ do -+ { -+ p->range >>= 1; -+ p->low += p->range & (0 - ((value >> --numBits) & 1)); -+ if (p->range < kTopValue) -+ { -+ p->range <<= 8; -+ RangeEnc_ShiftLow(p); -+ } -+ } -+ while (numBits != 0); -+} -+ -+static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol) -+{ -+ UInt32 ttt = *prob; -+ UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt; -+ if (symbol == 0) -+ { -+ p->range = newBound; -+ ttt += (kBitModelTotal - ttt) >> kNumMoveBits; -+ } -+ else -+ { -+ p->low += newBound; -+ p->range -= newBound; -+ ttt -= ttt >> kNumMoveBits; -+ } -+ *prob = (CLzmaProb)ttt; -+ if (p->range < kTopValue) -+ { -+ p->range <<= 8; -+ RangeEnc_ShiftLow(p); -+ } -+} -+ -+static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol) -+{ -+ symbol |= 0x100; -+ do -+ { -+ RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1); -+ symbol <<= 1; -+ } -+ while (symbol < 0x10000); -+} -+ -+static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte) -+{ -+ UInt32 offs = 0x100; -+ symbol |= 0x100; -+ do -+ { -+ matchByte <<= 1; -+ RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1); -+ symbol <<= 1; -+ offs &= ~(matchByte ^ symbol); -+ } -+ while (symbol < 0x10000); -+} -+ -+static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices) -+{ -+ UInt32 i; -+ for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits)) -+ { -+ const int kCyclesBits = kNumBitPriceShiftBits; -+ UInt32 w = i; -+ UInt32 bitCount = 0; -+ int j; -+ for (j = 0; j < kCyclesBits; j++) -+ { -+ w = w * w; -+ bitCount <<= 1; -+ while (w >= ((UInt32)1 << 16)) -+ { -+ w >>= 1; -+ bitCount++; -+ } -+ } -+ ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount); -+ } -+} -+ -+ -+#define GET_PRICE(prob, symbol) \ -+ p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; -+ -+#define GET_PRICEa(prob, symbol) \ -+ ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits]; -+ -+#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits] -+#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] -+ -+#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits] -+#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits] -+ -+static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices) -+{ -+ UInt32 price = 0; -+ symbol |= 0x100; -+ do -+ { -+ price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1); -+ symbol <<= 1; -+ } -+ while (symbol < 0x10000); -+ return price; -+} -+ -+static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices) -+{ -+ UInt32 price = 0; -+ UInt32 offs = 0x100; -+ symbol |= 0x100; -+ do -+ { -+ matchByte <<= 1; -+ price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1); -+ symbol <<= 1; -+ offs &= ~(matchByte ^ symbol); -+ } -+ while (symbol < 0x10000); -+ return price; -+} -+ -+ -+static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) -+{ -+ UInt32 m = 1; -+ int i; -+ for (i = numBitLevels; i != 0;) -+ { -+ UInt32 bit; -+ i--; -+ bit = (symbol >> i) & 1; -+ RangeEnc_EncodeBit(rc, probs + m, bit); -+ m = (m << 1) | bit; -+ } -+} -+ -+static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol) -+{ -+ UInt32 m = 1; -+ int i; -+ for (i = 0; i < numBitLevels; i++) -+ { -+ UInt32 bit = symbol & 1; -+ RangeEnc_EncodeBit(rc, probs + m, bit); -+ m = (m << 1) | bit; -+ symbol >>= 1; -+ } -+} -+ -+static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) -+{ -+ UInt32 price = 0; -+ symbol |= (1 << numBitLevels); -+ while (symbol != 1) -+ { -+ price += GET_PRICEa(probs[symbol >> 1], symbol & 1); -+ symbol >>= 1; -+ } -+ return price; -+} -+ -+static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices) -+{ -+ UInt32 price = 0; -+ UInt32 m = 1; -+ int i; -+ for (i = numBitLevels; i != 0; i--) -+ { -+ UInt32 bit = symbol & 1; -+ symbol >>= 1; -+ price += GET_PRICEa(probs[m], bit); -+ m = (m << 1) | bit; -+ } -+ return price; -+} -+ -+ -+static void LenEnc_Init(CLenEnc *p) -+{ -+ unsigned i; -+ p->choice = p->choice2 = kProbInitValue; -+ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++) -+ p->low[i] = kProbInitValue; -+ for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++) -+ p->mid[i] = kProbInitValue; -+ for (i = 0; i < kLenNumHighSymbols; i++) -+ p->high[i] = kProbInitValue; -+} -+ -+static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState) -+{ -+ if (symbol < kLenNumLowSymbols) -+ { -+ RangeEnc_EncodeBit(rc, &p->choice, 0); -+ RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol); -+ } -+ else -+ { -+ RangeEnc_EncodeBit(rc, &p->choice, 1); -+ if (symbol < kLenNumLowSymbols + kLenNumMidSymbols) -+ { -+ RangeEnc_EncodeBit(rc, &p->choice2, 0); -+ RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols); -+ } -+ else -+ { -+ RangeEnc_EncodeBit(rc, &p->choice2, 1); -+ RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols); -+ } -+ } -+} -+ -+static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices) -+{ -+ UInt32 a0 = GET_PRICE_0a(p->choice); -+ UInt32 a1 = GET_PRICE_1a(p->choice); -+ UInt32 b0 = a1 + GET_PRICE_0a(p->choice2); -+ UInt32 b1 = a1 + GET_PRICE_1a(p->choice2); -+ UInt32 i = 0; -+ for (i = 0; i < kLenNumLowSymbols; i++) -+ { -+ if (i >= numSymbols) -+ return; -+ prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices); -+ } -+ for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++) -+ { -+ if (i >= numSymbols) -+ return; -+ prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices); -+ } -+ for (; i < numSymbols; i++) -+ prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices); -+} -+ -+static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices) -+{ -+ LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices); -+ p->counters[posState] = p->tableSize; -+} -+ -+static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices) -+{ -+ UInt32 posState; -+ for (posState = 0; posState < numPosStates; posState++) -+ LenPriceEnc_UpdateTable(p, posState, ProbPrices); -+} -+ -+static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices) -+{ -+ LenEnc_Encode(&p->p, rc, symbol, posState); -+ if (updatePrice) -+ if (--p->counters[posState] == 0) -+ LenPriceEnc_UpdateTable(p, posState, ProbPrices); -+} -+ -+ -+ -+ -+static void MovePos(CLzmaEnc *p, UInt32 num) -+{ -+ #ifdef SHOW_STAT -+ ttt += num; -+ printf("\n MovePos %d", num); -+ #endif -+ if (num != 0) -+ { -+ p->additionalOffset += num; -+ p->matchFinder.Skip(p->matchFinderObj, num); -+ } -+} -+ -+static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes) -+{ -+ UInt32 lenRes = 0, numPairs; -+ p->numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj); -+ numPairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matches); -+ #ifdef SHOW_STAT -+ printf("\n i = %d numPairs = %d ", ttt, numPairs / 2); -+ ttt++; -+ { -+ UInt32 i; -+ for (i = 0; i < numPairs; i += 2) -+ printf("%2d %6d | ", p->matches[i], p->matches[i + 1]); -+ } -+ #endif -+ if (numPairs > 0) -+ { -+ lenRes = p->matches[numPairs - 2]; -+ if (lenRes == p->numFastBytes) -+ { -+ const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; -+ UInt32 distance = p->matches[numPairs - 1] + 1; -+ UInt32 numAvail = p->numAvail; -+ if (numAvail > LZMA_MATCH_LEN_MAX) -+ numAvail = LZMA_MATCH_LEN_MAX; -+ { -+ const Byte *pby2 = pby - distance; -+ for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++); -+ } -+ } -+ } -+ p->additionalOffset++; -+ *numDistancePairsRes = numPairs; -+ return lenRes; -+} -+ -+ -+#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False; -+#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False; -+#define IsShortRep(p) ((p)->backPrev == 0) -+ -+static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState) -+{ -+ return -+ GET_PRICE_0(p->isRepG0[state]) + -+ GET_PRICE_0(p->isRep0Long[state][posState]); -+} -+ -+static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState) -+{ -+ UInt32 price; -+ if (repIndex == 0) -+ { -+ price = GET_PRICE_0(p->isRepG0[state]); -+ price += GET_PRICE_1(p->isRep0Long[state][posState]); -+ } -+ else -+ { -+ price = GET_PRICE_1(p->isRepG0[state]); -+ if (repIndex == 1) -+ price += GET_PRICE_0(p->isRepG1[state]); -+ else -+ { -+ price += GET_PRICE_1(p->isRepG1[state]); -+ price += GET_PRICE(p->isRepG2[state], repIndex - 2); -+ } -+ } -+ return price; -+} -+ -+static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState) -+{ -+ return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] + -+ GetPureRepPrice(p, repIndex, state, posState); -+} -+ -+static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur) -+{ -+ UInt32 posMem = p->opt[cur].posPrev; -+ UInt32 backMem = p->opt[cur].backPrev; -+ p->optimumEndIndex = cur; -+ do -+ { -+ if (p->opt[cur].prev1IsChar) -+ { -+ MakeAsChar(&p->opt[posMem]) -+ p->opt[posMem].posPrev = posMem - 1; -+ if (p->opt[cur].prev2) -+ { -+ p->opt[posMem - 1].prev1IsChar = False; -+ p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2; -+ p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2; -+ } -+ } -+ { -+ UInt32 posPrev = posMem; -+ UInt32 backCur = backMem; -+ -+ backMem = p->opt[posPrev].backPrev; -+ posMem = p->opt[posPrev].posPrev; -+ -+ p->opt[posPrev].backPrev = backCur; -+ p->opt[posPrev].posPrev = cur; -+ cur = posPrev; -+ } -+ } -+ while (cur != 0); -+ *backRes = p->opt[0].backPrev; -+ p->optimumCurrentIndex = p->opt[0].posPrev; -+ return p->optimumCurrentIndex; -+} -+ -+#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300) -+ -+static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes) -+{ -+ UInt32 numAvail, mainLen, numPairs, repMaxIndex, i, posState, lenEnd, len, cur; -+ UInt32 matchPrice, repMatchPrice, normalMatchPrice; -+ UInt32 reps[LZMA_NUM_REPS], repLens[LZMA_NUM_REPS]; -+ UInt32 *matches; -+ const Byte *data; -+ Byte curByte, matchByte; -+ if (p->optimumEndIndex != p->optimumCurrentIndex) -+ { -+ const COptimal *opt = &p->opt[p->optimumCurrentIndex]; -+ UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex; -+ *backRes = opt->backPrev; -+ p->optimumCurrentIndex = opt->posPrev; -+ return lenRes; -+ } -+ p->optimumCurrentIndex = p->optimumEndIndex = 0; -+ -+ if (p->additionalOffset == 0) -+ mainLen = ReadMatchDistances(p, &numPairs); -+ else -+ { -+ mainLen = p->longestMatchLength; -+ numPairs = p->numPairs; -+ } -+ -+ numAvail = p->numAvail; -+ if (numAvail < 2) -+ { -+ *backRes = (UInt32)(-1); -+ return 1; -+ } -+ if (numAvail > LZMA_MATCH_LEN_MAX) -+ numAvail = LZMA_MATCH_LEN_MAX; -+ -+ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; -+ repMaxIndex = 0; -+ for (i = 0; i < LZMA_NUM_REPS; i++) -+ { -+ UInt32 lenTest; -+ const Byte *data2; -+ reps[i] = p->reps[i]; -+ data2 = data - (reps[i] + 1); -+ if (data[0] != data2[0] || data[1] != data2[1]) -+ { -+ repLens[i] = 0; -+ continue; -+ } -+ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); -+ repLens[i] = lenTest; -+ if (lenTest > repLens[repMaxIndex]) -+ repMaxIndex = i; -+ } -+ if (repLens[repMaxIndex] >= p->numFastBytes) -+ { -+ UInt32 lenRes; -+ *backRes = repMaxIndex; -+ lenRes = repLens[repMaxIndex]; -+ MovePos(p, lenRes - 1); -+ return lenRes; -+ } -+ -+ matches = p->matches; -+ if (mainLen >= p->numFastBytes) -+ { -+ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; -+ MovePos(p, mainLen - 1); -+ return mainLen; -+ } -+ curByte = *data; -+ matchByte = *(data - (reps[0] + 1)); -+ -+ if (mainLen < 2 && curByte != matchByte && repLens[repMaxIndex] < 2) -+ { -+ *backRes = (UInt32)-1; -+ return 1; -+ } -+ -+ p->opt[0].state = (CState)p->state; -+ -+ posState = (position & p->pbMask); -+ -+ { -+ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); -+ p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) + -+ (!IsCharState(p->state) ? -+ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : -+ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); -+ } -+ -+ MakeAsChar(&p->opt[1]); -+ -+ matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]); -+ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]); -+ -+ if (matchByte == curByte) -+ { -+ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState); -+ if (shortRepPrice < p->opt[1].price) -+ { -+ p->opt[1].price = shortRepPrice; -+ MakeAsShortRep(&p->opt[1]); -+ } -+ } -+ lenEnd = ((mainLen >= repLens[repMaxIndex]) ? mainLen : repLens[repMaxIndex]); -+ -+ if (lenEnd < 2) -+ { -+ *backRes = p->opt[1].backPrev; -+ return 1; -+ } -+ -+ p->opt[1].posPrev = 0; -+ for (i = 0; i < LZMA_NUM_REPS; i++) -+ p->opt[0].backs[i] = reps[i]; -+ -+ len = lenEnd; -+ do -+ p->opt[len--].price = kInfinityPrice; -+ while (len >= 2); -+ -+ for (i = 0; i < LZMA_NUM_REPS; i++) -+ { -+ UInt32 repLen = repLens[i]; -+ UInt32 price; -+ if (repLen < 2) -+ continue; -+ price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState); -+ do -+ { -+ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2]; -+ COptimal *opt = &p->opt[repLen]; -+ if (curAndLenPrice < opt->price) -+ { -+ opt->price = curAndLenPrice; -+ opt->posPrev = 0; -+ opt->backPrev = i; -+ opt->prev1IsChar = False; -+ } -+ } -+ while (--repLen >= 2); -+ } -+ -+ normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]); -+ -+ len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2); -+ if (len <= mainLen) -+ { -+ UInt32 offs = 0; -+ while (len > matches[offs]) -+ offs += 2; -+ for (; ; len++) -+ { -+ COptimal *opt; -+ UInt32 distance = matches[offs + 1]; -+ -+ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN]; -+ UInt32 lenToPosState = GetLenToPosState(len); -+ if (distance < kNumFullDistances) -+ curAndLenPrice += p->distancesPrices[lenToPosState][distance]; -+ else -+ { -+ UInt32 slot; -+ GetPosSlot2(distance, slot); -+ curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot]; -+ } -+ opt = &p->opt[len]; -+ if (curAndLenPrice < opt->price) -+ { -+ opt->price = curAndLenPrice; -+ opt->posPrev = 0; -+ opt->backPrev = distance + LZMA_NUM_REPS; -+ opt->prev1IsChar = False; -+ } -+ if (len == matches[offs]) -+ { -+ offs += 2; -+ if (offs == numPairs) -+ break; -+ } -+ } -+ } -+ -+ cur = 0; -+ -+ #ifdef SHOW_STAT2 -+ if (position >= 0) -+ { -+ unsigned i; -+ printf("\n pos = %4X", position); -+ for (i = cur; i <= lenEnd; i++) -+ printf("\nprice[%4X] = %d", position - cur + i, p->opt[i].price); -+ } -+ #endif -+ -+ for (;;) -+ { -+ UInt32 numAvailFull, newLen, numPairs, posPrev, state, posState, startLen; -+ UInt32 curPrice, curAnd1Price, matchPrice, repMatchPrice; -+ Bool nextIsChar; -+ Byte curByte, matchByte; -+ const Byte *data; -+ COptimal *curOpt; -+ COptimal *nextOpt; -+ -+ cur++; -+ if (cur == lenEnd) -+ return Backward(p, backRes, cur); -+ -+ newLen = ReadMatchDistances(p, &numPairs); -+ if (newLen >= p->numFastBytes) -+ { -+ p->numPairs = numPairs; -+ p->longestMatchLength = newLen; -+ return Backward(p, backRes, cur); -+ } -+ position++; -+ curOpt = &p->opt[cur]; -+ posPrev = curOpt->posPrev; -+ if (curOpt->prev1IsChar) -+ { -+ posPrev--; -+ if (curOpt->prev2) -+ { -+ state = p->opt[curOpt->posPrev2].state; -+ if (curOpt->backPrev2 < LZMA_NUM_REPS) -+ state = kRepNextStates[state]; -+ else -+ state = kMatchNextStates[state]; -+ } -+ else -+ state = p->opt[posPrev].state; -+ state = kLiteralNextStates[state]; -+ } -+ else -+ state = p->opt[posPrev].state; -+ if (posPrev == cur - 1) -+ { -+ if (IsShortRep(curOpt)) -+ state = kShortRepNextStates[state]; -+ else -+ state = kLiteralNextStates[state]; -+ } -+ else -+ { -+ UInt32 pos; -+ const COptimal *prevOpt; -+ if (curOpt->prev1IsChar && curOpt->prev2) -+ { -+ posPrev = curOpt->posPrev2; -+ pos = curOpt->backPrev2; -+ state = kRepNextStates[state]; -+ } -+ else -+ { -+ pos = curOpt->backPrev; -+ if (pos < LZMA_NUM_REPS) -+ state = kRepNextStates[state]; -+ else -+ state = kMatchNextStates[state]; -+ } -+ prevOpt = &p->opt[posPrev]; -+ if (pos < LZMA_NUM_REPS) -+ { -+ UInt32 i; -+ reps[0] = prevOpt->backs[pos]; -+ for (i = 1; i <= pos; i++) -+ reps[i] = prevOpt->backs[i - 1]; -+ for (; i < LZMA_NUM_REPS; i++) -+ reps[i] = prevOpt->backs[i]; -+ } -+ else -+ { -+ UInt32 i; -+ reps[0] = (pos - LZMA_NUM_REPS); -+ for (i = 1; i < LZMA_NUM_REPS; i++) -+ reps[i] = prevOpt->backs[i - 1]; -+ } -+ } -+ curOpt->state = (CState)state; -+ -+ curOpt->backs[0] = reps[0]; -+ curOpt->backs[1] = reps[1]; -+ curOpt->backs[2] = reps[2]; -+ curOpt->backs[3] = reps[3]; -+ -+ curPrice = curOpt->price; -+ nextIsChar = False; -+ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; -+ curByte = *data; -+ matchByte = *(data - (reps[0] + 1)); -+ -+ posState = (position & p->pbMask); -+ -+ curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]); -+ { -+ const CLzmaProb *probs = LIT_PROBS(position, *(data - 1)); -+ curAnd1Price += -+ (!IsCharState(state) ? -+ LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) : -+ LitEnc_GetPrice(probs, curByte, p->ProbPrices)); -+ } -+ -+ nextOpt = &p->opt[cur + 1]; -+ -+ if (curAnd1Price < nextOpt->price) -+ { -+ nextOpt->price = curAnd1Price; -+ nextOpt->posPrev = cur; -+ MakeAsChar(nextOpt); -+ nextIsChar = True; -+ } -+ -+ matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]); -+ repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]); -+ -+ if (matchByte == curByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0)) -+ { -+ UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState); -+ if (shortRepPrice <= nextOpt->price) -+ { -+ nextOpt->price = shortRepPrice; -+ nextOpt->posPrev = cur; -+ MakeAsShortRep(nextOpt); -+ nextIsChar = True; -+ } -+ } -+ numAvailFull = p->numAvail; -+ { -+ UInt32 temp = kNumOpts - 1 - cur; -+ if (temp < numAvailFull) -+ numAvailFull = temp; -+ } -+ -+ if (numAvailFull < 2) -+ continue; -+ numAvail = (numAvailFull <= p->numFastBytes ? numAvailFull : p->numFastBytes); -+ -+ if (!nextIsChar && matchByte != curByte) /* speed optimization */ -+ { -+ /* try Literal + rep0 */ -+ UInt32 temp; -+ UInt32 lenTest2; -+ const Byte *data2 = data - (reps[0] + 1); -+ UInt32 limit = p->numFastBytes + 1; -+ if (limit > numAvailFull) -+ limit = numAvailFull; -+ -+ for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++); -+ lenTest2 = temp - 1; -+ if (lenTest2 >= 2) -+ { -+ UInt32 state2 = kLiteralNextStates[state]; -+ UInt32 posStateNext = (position + 1) & p->pbMask; -+ UInt32 nextRepMatchPrice = curAnd1Price + -+ GET_PRICE_1(p->isMatch[state2][posStateNext]) + -+ GET_PRICE_1(p->isRep[state2]); -+ /* for (; lenTest2 >= 2; lenTest2--) */ -+ { -+ UInt32 curAndLenPrice; -+ COptimal *opt; -+ UInt32 offset = cur + 1 + lenTest2; -+ while (lenEnd < offset) -+ p->opt[++lenEnd].price = kInfinityPrice; -+ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); -+ opt = &p->opt[offset]; -+ if (curAndLenPrice < opt->price) -+ { -+ opt->price = curAndLenPrice; -+ opt->posPrev = cur + 1; -+ opt->backPrev = 0; -+ opt->prev1IsChar = True; -+ opt->prev2 = False; -+ } -+ } -+ } -+ } -+ -+ startLen = 2; /* speed optimization */ -+ { -+ UInt32 repIndex; -+ for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++) -+ { -+ UInt32 lenTest; -+ UInt32 lenTestTemp; -+ UInt32 price; -+ const Byte *data2 = data - (reps[repIndex] + 1); -+ if (data[0] != data2[0] || data[1] != data2[1]) -+ continue; -+ for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++); -+ while (lenEnd < cur + lenTest) -+ p->opt[++lenEnd].price = kInfinityPrice; -+ lenTestTemp = lenTest; -+ price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState); -+ do -+ { -+ UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2]; -+ COptimal *opt = &p->opt[cur + lenTest]; -+ if (curAndLenPrice < opt->price) -+ { -+ opt->price = curAndLenPrice; -+ opt->posPrev = cur; -+ opt->backPrev = repIndex; -+ opt->prev1IsChar = False; -+ } -+ } -+ while (--lenTest >= 2); -+ lenTest = lenTestTemp; -+ -+ if (repIndex == 0) -+ startLen = lenTest + 1; -+ -+ /* if (_maxMode) */ -+ { -+ UInt32 lenTest2 = lenTest + 1; -+ UInt32 limit = lenTest2 + p->numFastBytes; -+ UInt32 nextRepMatchPrice; -+ if (limit > numAvailFull) -+ limit = numAvailFull; -+ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); -+ lenTest2 -= lenTest + 1; -+ if (lenTest2 >= 2) -+ { -+ UInt32 state2 = kRepNextStates[state]; -+ UInt32 posStateNext = (position + lenTest) & p->pbMask; -+ UInt32 curAndLenCharPrice = -+ price + p->repLenEnc.prices[posState][lenTest - 2] + -+ GET_PRICE_0(p->isMatch[state2][posStateNext]) + -+ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), -+ data[lenTest], data2[lenTest], p->ProbPrices); -+ state2 = kLiteralNextStates[state2]; -+ posStateNext = (position + lenTest + 1) & p->pbMask; -+ nextRepMatchPrice = curAndLenCharPrice + -+ GET_PRICE_1(p->isMatch[state2][posStateNext]) + -+ GET_PRICE_1(p->isRep[state2]); -+ -+ /* for (; lenTest2 >= 2; lenTest2--) */ -+ { -+ UInt32 curAndLenPrice; -+ COptimal *opt; -+ UInt32 offset = cur + lenTest + 1 + lenTest2; -+ while (lenEnd < offset) -+ p->opt[++lenEnd].price = kInfinityPrice; -+ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); -+ opt = &p->opt[offset]; -+ if (curAndLenPrice < opt->price) -+ { -+ opt->price = curAndLenPrice; -+ opt->posPrev = cur + lenTest + 1; -+ opt->backPrev = 0; -+ opt->prev1IsChar = True; -+ opt->prev2 = True; -+ opt->posPrev2 = cur; -+ opt->backPrev2 = repIndex; -+ } -+ } -+ } -+ } -+ } -+ } -+ /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */ -+ if (newLen > numAvail) -+ { -+ newLen = numAvail; -+ for (numPairs = 0; newLen > matches[numPairs]; numPairs += 2); -+ matches[numPairs] = newLen; -+ numPairs += 2; -+ } -+ if (newLen >= startLen) -+ { -+ UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]); -+ UInt32 offs, curBack, posSlot; -+ UInt32 lenTest; -+ while (lenEnd < cur + newLen) -+ p->opt[++lenEnd].price = kInfinityPrice; -+ -+ offs = 0; -+ while (startLen > matches[offs]) -+ offs += 2; -+ curBack = matches[offs + 1]; -+ GetPosSlot2(curBack, posSlot); -+ for (lenTest = /*2*/ startLen; ; lenTest++) -+ { -+ UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN]; -+ UInt32 lenToPosState = GetLenToPosState(lenTest); -+ COptimal *opt; -+ if (curBack < kNumFullDistances) -+ curAndLenPrice += p->distancesPrices[lenToPosState][curBack]; -+ else -+ curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask]; -+ -+ opt = &p->opt[cur + lenTest]; -+ if (curAndLenPrice < opt->price) -+ { -+ opt->price = curAndLenPrice; -+ opt->posPrev = cur; -+ opt->backPrev = curBack + LZMA_NUM_REPS; -+ opt->prev1IsChar = False; -+ } -+ -+ if (/*_maxMode && */lenTest == matches[offs]) -+ { -+ /* Try Match + Literal + Rep0 */ -+ const Byte *data2 = data - (curBack + 1); -+ UInt32 lenTest2 = lenTest + 1; -+ UInt32 limit = lenTest2 + p->numFastBytes; -+ UInt32 nextRepMatchPrice; -+ if (limit > numAvailFull) -+ limit = numAvailFull; -+ for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++); -+ lenTest2 -= lenTest + 1; -+ if (lenTest2 >= 2) -+ { -+ UInt32 state2 = kMatchNextStates[state]; -+ UInt32 posStateNext = (position + lenTest) & p->pbMask; -+ UInt32 curAndLenCharPrice = curAndLenPrice + -+ GET_PRICE_0(p->isMatch[state2][posStateNext]) + -+ LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]), -+ data[lenTest], data2[lenTest], p->ProbPrices); -+ state2 = kLiteralNextStates[state2]; -+ posStateNext = (posStateNext + 1) & p->pbMask; -+ nextRepMatchPrice = curAndLenCharPrice + -+ GET_PRICE_1(p->isMatch[state2][posStateNext]) + -+ GET_PRICE_1(p->isRep[state2]); -+ -+ /* for (; lenTest2 >= 2; lenTest2--) */ -+ { -+ UInt32 offset = cur + lenTest + 1 + lenTest2; -+ UInt32 curAndLenPrice; -+ COptimal *opt; -+ while (lenEnd < offset) -+ p->opt[++lenEnd].price = kInfinityPrice; -+ curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext); -+ opt = &p->opt[offset]; -+ if (curAndLenPrice < opt->price) -+ { -+ opt->price = curAndLenPrice; -+ opt->posPrev = cur + lenTest + 1; -+ opt->backPrev = 0; -+ opt->prev1IsChar = True; -+ opt->prev2 = True; -+ opt->posPrev2 = cur; -+ opt->backPrev2 = curBack + LZMA_NUM_REPS; -+ } -+ } -+ } -+ offs += 2; -+ if (offs == numPairs) -+ break; -+ curBack = matches[offs + 1]; -+ if (curBack >= kNumFullDistances) -+ GetPosSlot2(curBack, posSlot); -+ } -+ } -+ } -+ } -+} -+ -+#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist)) -+ -+static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes) -+{ -+ UInt32 numAvail, mainLen, mainDist, numPairs, repIndex, repLen, i; -+ const Byte *data; -+ const UInt32 *matches; -+ -+ if (p->additionalOffset == 0) -+ mainLen = ReadMatchDistances(p, &numPairs); -+ else -+ { -+ mainLen = p->longestMatchLength; -+ numPairs = p->numPairs; -+ } -+ -+ numAvail = p->numAvail; -+ *backRes = (UInt32)-1; -+ if (numAvail < 2) -+ return 1; -+ if (numAvail > LZMA_MATCH_LEN_MAX) -+ numAvail = LZMA_MATCH_LEN_MAX; -+ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; -+ -+ repLen = repIndex = 0; -+ for (i = 0; i < LZMA_NUM_REPS; i++) -+ { -+ UInt32 len; -+ const Byte *data2 = data - (p->reps[i] + 1); -+ if (data[0] != data2[0] || data[1] != data2[1]) -+ continue; -+ for (len = 2; len < numAvail && data[len] == data2[len]; len++); -+ if (len >= p->numFastBytes) -+ { -+ *backRes = i; -+ MovePos(p, len - 1); -+ return len; -+ } -+ if (len > repLen) -+ { -+ repIndex = i; -+ repLen = len; -+ } -+ } -+ -+ matches = p->matches; -+ if (mainLen >= p->numFastBytes) -+ { -+ *backRes = matches[numPairs - 1] + LZMA_NUM_REPS; -+ MovePos(p, mainLen - 1); -+ return mainLen; -+ } -+ -+ mainDist = 0; /* for GCC */ -+ if (mainLen >= 2) -+ { -+ mainDist = matches[numPairs - 1]; -+ while (numPairs > 2 && mainLen == matches[numPairs - 4] + 1) -+ { -+ if (!ChangePair(matches[numPairs - 3], mainDist)) -+ break; -+ numPairs -= 2; -+ mainLen = matches[numPairs - 2]; -+ mainDist = matches[numPairs - 1]; -+ } -+ if (mainLen == 2 && mainDist >= 0x80) -+ mainLen = 1; -+ } -+ -+ if (repLen >= 2 && ( -+ (repLen + 1 >= mainLen) || -+ (repLen + 2 >= mainLen && mainDist >= (1 << 9)) || -+ (repLen + 3 >= mainLen && mainDist >= (1 << 15)))) -+ { -+ *backRes = repIndex; -+ MovePos(p, repLen - 1); -+ return repLen; -+ } -+ -+ if (mainLen < 2 || numAvail <= 2) -+ return 1; -+ -+ p->longestMatchLength = ReadMatchDistances(p, &p->numPairs); -+ if (p->longestMatchLength >= 2) -+ { -+ UInt32 newDistance = matches[p->numPairs - 1]; -+ if ((p->longestMatchLength >= mainLen && newDistance < mainDist) || -+ (p->longestMatchLength == mainLen + 1 && !ChangePair(mainDist, newDistance)) || -+ (p->longestMatchLength > mainLen + 1) || -+ (p->longestMatchLength + 1 >= mainLen && mainLen >= 3 && ChangePair(newDistance, mainDist))) -+ return 1; -+ } -+ -+ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1; -+ for (i = 0; i < LZMA_NUM_REPS; i++) -+ { -+ UInt32 len, limit; -+ const Byte *data2 = data - (p->reps[i] + 1); -+ if (data[0] != data2[0] || data[1] != data2[1]) -+ continue; -+ limit = mainLen - 1; -+ for (len = 2; len < limit && data[len] == data2[len]; len++); -+ if (len >= limit) -+ return 1; -+ } -+ *backRes = mainDist + LZMA_NUM_REPS; -+ MovePos(p, mainLen - 2); -+ return mainLen; -+} -+ -+static void WriteEndMarker(CLzmaEnc *p, UInt32 posState) -+{ -+ UInt32 len; -+ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); -+ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); -+ p->state = kMatchNextStates[p->state]; -+ len = LZMA_MATCH_LEN_MIN; -+ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); -+ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1); -+ RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits); -+ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask); -+} -+ -+static SRes CheckErrors(CLzmaEnc *p) -+{ -+ if (p->result != SZ_OK) -+ return p->result; -+ if (p->rc.res != SZ_OK) -+ p->result = SZ_ERROR_WRITE; -+ if (p->matchFinderBase.result != SZ_OK) -+ p->result = SZ_ERROR_READ; -+ if (p->result != SZ_OK) -+ p->finished = True; -+ return p->result; -+} -+ -+static SRes Flush(CLzmaEnc *p, UInt32 nowPos) -+{ -+ /* ReleaseMFStream(); */ -+ p->finished = True; -+ if (p->writeEndMark) -+ WriteEndMarker(p, nowPos & p->pbMask); -+ RangeEnc_FlushData(&p->rc); -+ RangeEnc_FlushStream(&p->rc); -+ return CheckErrors(p); -+} -+ -+static void FillAlignPrices(CLzmaEnc *p) -+{ -+ UInt32 i; -+ for (i = 0; i < kAlignTableSize; i++) -+ p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices); -+ p->alignPriceCount = 0; -+} -+ -+static void FillDistancesPrices(CLzmaEnc *p) -+{ -+ UInt32 tempPrices[kNumFullDistances]; -+ UInt32 i, lenToPosState; -+ for (i = kStartPosModelIndex; i < kNumFullDistances; i++) -+ { -+ UInt32 posSlot = GetPosSlot1(i); -+ UInt32 footerBits = ((posSlot >> 1) - 1); -+ UInt32 base = ((2 | (posSlot & 1)) << footerBits); -+ tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices); -+ } -+ -+ for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++) -+ { -+ UInt32 posSlot; -+ const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState]; -+ UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState]; -+ for (posSlot = 0; posSlot < p->distTableSize; posSlot++) -+ posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices); -+ for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++) -+ posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits); -+ -+ { -+ UInt32 *distancesPrices = p->distancesPrices[lenToPosState]; -+ UInt32 i; -+ for (i = 0; i < kStartPosModelIndex; i++) -+ distancesPrices[i] = posSlotPrices[i]; -+ for (; i < kNumFullDistances; i++) -+ distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i]; -+ } -+ } -+ p->matchPriceCount = 0; -+} -+ -+static void LzmaEnc_Construct(CLzmaEnc *p) -+{ -+ RangeEnc_Construct(&p->rc); -+ MatchFinder_Construct(&p->matchFinderBase); -+ #ifndef _7ZIP_ST -+ MatchFinderMt_Construct(&p->matchFinderMt); -+ p->matchFinderMt.MatchFinder = &p->matchFinderBase; -+ #endif -+ -+ { -+ CLzmaEncProps props; -+ LzmaEncProps_Init(&props); -+ LzmaEnc_SetProps(p, &props); -+ } -+ -+ #ifndef LZMA_LOG_BSR -+ LzmaEnc_FastPosInit(p->g_FastPos); -+ #endif -+ -+ LzmaEnc_InitPriceTables(p->ProbPrices); -+ p->litProbs = 0; -+ p->saveState.litProbs = 0; -+} -+ -+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc) -+{ -+ void *p; -+ p = alloc->Alloc(alloc, sizeof(CLzmaEnc)); -+ if (p != 0) -+ LzmaEnc_Construct((CLzmaEnc *)p); -+ return p; -+} -+ -+static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc) -+{ -+ alloc->Free(alloc, p->litProbs); -+ alloc->Free(alloc, p->saveState.litProbs); -+ p->litProbs = 0; -+ p->saveState.litProbs = 0; -+} -+ -+static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig) -+{ -+ #ifndef _7ZIP_ST -+ MatchFinderMt_Destruct(&p->matchFinderMt, allocBig); -+ #endif -+ MatchFinder_Free(&p->matchFinderBase, allocBig); -+ LzmaEnc_FreeLits(p, alloc); -+ RangeEnc_Free(&p->rc, alloc); -+} -+ -+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig) -+{ -+ LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig); -+ alloc->Free(alloc, p); -+} -+ -+static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize) -+{ -+ UInt32 nowPos32, startPos32; -+ if (p->needInit) -+ { -+ p->matchFinder.Init(p->matchFinderObj); -+ p->needInit = 0; -+ } -+ -+ if (p->finished) -+ return p->result; -+ RINOK(CheckErrors(p)); -+ -+ nowPos32 = (UInt32)p->nowPos64; -+ startPos32 = nowPos32; -+ -+ if (p->nowPos64 == 0) -+ { -+ UInt32 numPairs; -+ Byte curByte; -+ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) -+ return Flush(p, nowPos32); -+ ReadMatchDistances(p, &numPairs); -+ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0); -+ p->state = kLiteralNextStates[p->state]; -+ curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset); -+ LitEnc_Encode(&p->rc, p->litProbs, curByte); -+ p->additionalOffset--; -+ nowPos32++; -+ } -+ -+ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0) -+ for (;;) -+ { -+ UInt32 pos, len, posState; -+ -+ if (p->fastMode) -+ len = GetOptimumFast(p, &pos); -+ else -+ len = GetOptimum(p, nowPos32, &pos); -+ -+ #ifdef SHOW_STAT2 -+ printf("\n pos = %4X, len = %d pos = %d", nowPos32, len, pos); -+ #endif -+ -+ posState = nowPos32 & p->pbMask; -+ if (len == 1 && pos == (UInt32)-1) -+ { -+ Byte curByte; -+ CLzmaProb *probs; -+ const Byte *data; -+ -+ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0); -+ data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset; -+ curByte = *data; -+ probs = LIT_PROBS(nowPos32, *(data - 1)); -+ if (IsCharState(p->state)) -+ LitEnc_Encode(&p->rc, probs, curByte); -+ else -+ LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1)); -+ p->state = kLiteralNextStates[p->state]; -+ } -+ else -+ { -+ RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1); -+ if (pos < LZMA_NUM_REPS) -+ { -+ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1); -+ if (pos == 0) -+ { -+ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0); -+ RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1)); -+ } -+ else -+ { -+ UInt32 distance = p->reps[pos]; -+ RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1); -+ if (pos == 1) -+ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0); -+ else -+ { -+ RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1); -+ RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2); -+ if (pos == 3) -+ p->reps[3] = p->reps[2]; -+ p->reps[2] = p->reps[1]; -+ } -+ p->reps[1] = p->reps[0]; -+ p->reps[0] = distance; -+ } -+ if (len == 1) -+ p->state = kShortRepNextStates[p->state]; -+ else -+ { -+ LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); -+ p->state = kRepNextStates[p->state]; -+ } -+ } -+ else -+ { -+ UInt32 posSlot; -+ RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0); -+ p->state = kMatchNextStates[p->state]; -+ LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices); -+ pos -= LZMA_NUM_REPS; -+ GetPosSlot(pos, posSlot); -+ RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot); -+ -+ if (posSlot >= kStartPosModelIndex) -+ { -+ UInt32 footerBits = ((posSlot >> 1) - 1); -+ UInt32 base = ((2 | (posSlot & 1)) << footerBits); -+ UInt32 posReduced = pos - base; -+ -+ if (posSlot < kEndPosModelIndex) -+ RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced); -+ else -+ { -+ RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits); -+ RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask); -+ p->alignPriceCount++; -+ } -+ } -+ p->reps[3] = p->reps[2]; -+ p->reps[2] = p->reps[1]; -+ p->reps[1] = p->reps[0]; -+ p->reps[0] = pos; -+ p->matchPriceCount++; -+ } -+ } -+ p->additionalOffset -= len; -+ nowPos32 += len; -+ if (p->additionalOffset == 0) -+ { -+ UInt32 processed; -+ if (!p->fastMode) -+ { -+ if (p->matchPriceCount >= (1 << 7)) -+ FillDistancesPrices(p); -+ if (p->alignPriceCount >= kAlignTableSize) -+ FillAlignPrices(p); -+ } -+ if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0) -+ break; -+ processed = nowPos32 - startPos32; -+ if (useLimits) -+ { -+ if (processed + kNumOpts + 300 >= maxUnpackSize || -+ RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize) -+ break; -+ } -+ else if (processed >= (1 << 15)) -+ { -+ p->nowPos64 += nowPos32 - startPos32; -+ return CheckErrors(p); -+ } -+ } -+ } -+ p->nowPos64 += nowPos32 - startPos32; -+ return Flush(p, nowPos32); -+} -+ -+#define kBigHashDicLimit ((UInt32)1 << 24) -+ -+static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) -+{ -+ UInt32 beforeSize = kNumOpts; -+ Bool btMode; -+ if (!RangeEnc_Alloc(&p->rc, alloc)) -+ return SZ_ERROR_MEM; -+ btMode = (p->matchFinderBase.btMode != 0); -+ #ifndef _7ZIP_ST -+ p->mtMode = (p->multiThread && !p->fastMode && btMode); -+ #endif -+ -+ { -+ unsigned lclp = p->lc + p->lp; -+ if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp) -+ { -+ LzmaEnc_FreeLits(p, alloc); -+ p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); -+ p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb)); -+ if (p->litProbs == 0 || p->saveState.litProbs == 0) -+ { -+ LzmaEnc_FreeLits(p, alloc); -+ return SZ_ERROR_MEM; -+ } -+ p->lclp = lclp; -+ } -+ } -+ -+ p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit); -+ -+ if (beforeSize + p->dictSize < keepWindowSize) -+ beforeSize = keepWindowSize - p->dictSize; -+ -+ #ifndef _7ZIP_ST -+ if (p->mtMode) -+ { -+ RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)); -+ p->matchFinderObj = &p->matchFinderMt; -+ MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder); -+ } -+ else -+ #endif -+ { -+ if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig)) -+ return SZ_ERROR_MEM; -+ p->matchFinderObj = &p->matchFinderBase; -+ MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder); -+ } -+ return SZ_OK; -+} -+ -+static void LzmaEnc_Init(CLzmaEnc *p) -+{ -+ UInt32 i; -+ p->state = 0; -+ for (i = 0 ; i < LZMA_NUM_REPS; i++) -+ p->reps[i] = 0; -+ -+ RangeEnc_Init(&p->rc); -+ -+ -+ for (i = 0; i < kNumStates; i++) -+ { -+ UInt32 j; -+ for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++) -+ { -+ p->isMatch[i][j] = kProbInitValue; -+ p->isRep0Long[i][j] = kProbInitValue; -+ } -+ p->isRep[i] = kProbInitValue; -+ p->isRepG0[i] = kProbInitValue; -+ p->isRepG1[i] = kProbInitValue; -+ p->isRepG2[i] = kProbInitValue; -+ } -+ -+ { -+ UInt32 num = 0x300 << (p->lp + p->lc); -+ for (i = 0; i < num; i++) -+ p->litProbs[i] = kProbInitValue; -+ } -+ -+ { -+ for (i = 0; i < kNumLenToPosStates; i++) -+ { -+ CLzmaProb *probs = p->posSlotEncoder[i]; -+ UInt32 j; -+ for (j = 0; j < (1 << kNumPosSlotBits); j++) -+ probs[j] = kProbInitValue; -+ } -+ } -+ { -+ for (i = 0; i < kNumFullDistances - kEndPosModelIndex; i++) -+ p->posEncoders[i] = kProbInitValue; -+ } -+ -+ LenEnc_Init(&p->lenEnc.p); -+ LenEnc_Init(&p->repLenEnc.p); -+ -+ for (i = 0; i < (1 << kNumAlignBits); i++) -+ p->posAlignEncoder[i] = kProbInitValue; -+ -+ p->optimumEndIndex = 0; -+ p->optimumCurrentIndex = 0; -+ p->additionalOffset = 0; -+ -+ p->pbMask = (1 << p->pb) - 1; -+ p->lpMask = (1 << p->lp) - 1; -+} -+ -+static void LzmaEnc_InitPrices(CLzmaEnc *p) -+{ -+ if (!p->fastMode) -+ { -+ FillDistancesPrices(p); -+ FillAlignPrices(p); -+ } -+ -+ p->lenEnc.tableSize = -+ p->repLenEnc.tableSize = -+ p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN; -+ LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices); -+ LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices); -+} -+ -+static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) -+{ -+ UInt32 i; -+ for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++) -+ if (p->dictSize <= ((UInt32)1 << i)) -+ break; -+ p->distTableSize = i * 2; -+ -+ p->finished = False; -+ p->result = SZ_OK; -+ RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig)); -+ LzmaEnc_Init(p); -+ LzmaEnc_InitPrices(p); -+ p->nowPos64 = 0; -+ return SZ_OK; -+} -+ -+static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen) -+{ -+ p->matchFinderBase.directInput = 1; -+ p->matchFinderBase.bufferBase = (Byte *)src; -+ p->matchFinderBase.directInputRem = srcLen; -+} -+ -+static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen, -+ UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig) -+{ -+ CLzmaEnc *p = (CLzmaEnc *)pp; -+ LzmaEnc_SetInputBuf(p, src, srcLen); -+ p->needInit = 1; -+ -+ return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig); -+} -+ -+static void LzmaEnc_Finish(CLzmaEncHandle pp) -+{ -+ #ifndef _7ZIP_ST -+ CLzmaEnc *p = (CLzmaEnc *)pp; -+ if (p->mtMode) -+ MatchFinderMt_ReleaseStream(&p->matchFinderMt); -+ #else -+ pp = pp; -+ #endif -+} -+ -+typedef struct -+{ -+ ISeqOutStream funcTable; -+ Byte *data; -+ SizeT rem; -+ Bool overflow; -+} CSeqOutStreamBuf; -+ -+static size_t MyWrite(void *pp, const void *data, size_t size) -+{ -+ CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp; -+ if (p->rem < size) -+ { -+ size = p->rem; -+ p->overflow = True; -+ } -+ memcpy(p->data, data, size); -+ p->rem -= size; -+ p->data += size; -+ return size; -+} -+ -+static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress) -+{ -+ SRes res = SZ_OK; -+ -+ #ifndef _7ZIP_ST -+ Byte allocaDummy[0x300]; -+ int i = 0; -+ for (i = 0; i < 16; i++) -+ allocaDummy[i] = (Byte)i; -+ #endif -+ -+ for (;;) -+ { -+ res = LzmaEnc_CodeOneBlock(p, False, 0, 0); -+ if (res != SZ_OK || p->finished != 0) -+ break; -+ if (progress != 0) -+ { -+ res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc)); -+ if (res != SZ_OK) -+ { -+ res = SZ_ERROR_PROGRESS; -+ break; -+ } -+ } -+ } -+ LzmaEnc_Finish(p); -+ return res; -+} -+ -+SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size) -+{ -+ CLzmaEnc *p = (CLzmaEnc *)pp; -+ int i; -+ UInt32 dictSize = p->dictSize; -+ if (*size < LZMA_PROPS_SIZE) -+ return SZ_ERROR_PARAM; -+ *size = LZMA_PROPS_SIZE; -+ props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc); -+ -+ for (i = 11; i <= 30; i++) -+ { -+ if (dictSize <= ((UInt32)2 << i)) -+ { -+ dictSize = (2 << i); -+ break; -+ } -+ if (dictSize <= ((UInt32)3 << i)) -+ { -+ dictSize = (3 << i); -+ break; -+ } -+ } -+ -+ for (i = 0; i < 4; i++) -+ props[1 + i] = (Byte)(dictSize >> (8 * i)); -+ return SZ_OK; -+} -+ -+SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen, -+ int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig) -+{ -+ SRes res; -+ CLzmaEnc *p = (CLzmaEnc *)pp; -+ -+ CSeqOutStreamBuf outStream; -+ -+ LzmaEnc_SetInputBuf(p, src, srcLen); -+ -+ outStream.funcTable.Write = MyWrite; -+ outStream.data = dest; -+ outStream.rem = *destLen; -+ outStream.overflow = False; -+ -+ p->writeEndMark = writeEndMark; -+ -+ p->rc.outStream = &outStream.funcTable; -+ res = LzmaEnc_MemPrepare(pp, src, srcLen, 0, alloc, allocBig); -+ if (res == SZ_OK) -+ res = LzmaEnc_Encode2(p, progress); -+ -+ *destLen -= outStream.rem; -+ if (outStream.overflow) -+ return SZ_ERROR_OUTPUT_EOF; -+ return res; -+} ---- /dev/null -+++ b/lib/lzma/Makefile -@@ -0,0 +1,7 @@ -+lzma_compress-objs := LzFind.o LzmaEnc.o -+lzma_decompress-objs := LzmaDec.o -+ -+obj-$(CONFIG_LZMA_COMPRESS) += lzma_compress.o -+obj-$(CONFIG_LZMA_DECOMPRESS) += lzma_decompress.o -+ -+EXTRA_CFLAGS += -Iinclude/linux -Iinclude/linux/lzma -include types.h diff --git a/target/linux/generic/pending-5.10/532-jffs2_eofdetect.patch b/target/linux/generic/pending-5.10/532-jffs2_eofdetect.patch deleted file mode 100644 index 744fbd0e21..0000000000 --- a/target/linux/generic/pending-5.10/532-jffs2_eofdetect.patch +++ /dev/null @@ -1,65 +0,0 @@ -From: Felix Fietkau -Subject: fs: jffs2: EOF marker - -Signed-off-by: Felix Fietkau ---- - fs/jffs2/build.c | 10 ++++++++++ - fs/jffs2/scan.c | 21 +++++++++++++++++++-- - 2 files changed, 29 insertions(+), 2 deletions(-) - ---- a/fs/jffs2/build.c -+++ b/fs/jffs2/build.c -@@ -117,6 +117,16 @@ static int jffs2_build_filesystem(struct - dbg_fsbuild("scanned flash completely\n"); - jffs2_dbg_dump_block_lists_nolock(c); - -+ if (c->flags & (1 << 7)) { -+ printk("%s(): unlocking the mtd device... ", __func__); -+ mtd_unlock(c->mtd, 0, c->mtd->size); -+ printk("done.\n"); -+ -+ printk("%s(): erasing all blocks after the end marker... ", __func__); -+ jffs2_erase_pending_blocks(c, -1); -+ printk("done.\n"); -+ } -+ - dbg_fsbuild("pass 1 starting\n"); - c->flags |= JFFS2_SB_FLAG_BUILDING; - /* Now scan the directory tree, increasing nlink according to every dirent found. */ ---- a/fs/jffs2/scan.c -+++ b/fs/jffs2/scan.c -@@ -148,8 +148,14 @@ int jffs2_scan_medium(struct jffs2_sb_in - /* reset summary info for next eraseblock scan */ - jffs2_sum_reset_collected(s); - -- ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), -- buf_size, s); -+ if (c->flags & (1 << 7)) { -+ if (mtd_block_isbad(c->mtd, jeb->offset)) -+ ret = BLK_STATE_BADBLOCK; -+ else -+ ret = BLK_STATE_ALLFF; -+ } else -+ ret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset), -+ buf_size, s); - - if (ret < 0) - goto out; -@@ -567,6 +573,17 @@ full_scan: - return err; - } - -+ if ((buf[0] == 0xde) && -+ (buf[1] == 0xad) && -+ (buf[2] == 0xc0) && -+ (buf[3] == 0xde)) { -+ /* end of filesystem. erase everything after this point */ -+ printk("%s(): End of filesystem marker found at 0x%x\n", __func__, jeb->offset); -+ c->flags |= (1 << 7); -+ -+ return BLK_STATE_ALLFF; -+ } -+ - /* We temporarily use 'ofs' as a pointer into the buffer/jeb */ - ofs = 0; - max_ofs = EMPTY_SCAN_SIZE(c->sector_size); diff --git a/target/linux/generic/pending-5.10/600-netfilter_conntrack_flush.patch b/target/linux/generic/pending-5.10/600-netfilter_conntrack_flush.patch deleted file mode 100644 index ab6953e557..0000000000 --- a/target/linux/generic/pending-5.10/600-netfilter_conntrack_flush.patch +++ /dev/null @@ -1,88 +0,0 @@ -From: Felix Fietkau -Subject: netfilter: add support for flushing conntrack via /proc - -lede-commit 8193bbe59a74d34d6a26d4a8cb857b1952905314 -Signed-off-by: Felix Fietkau ---- - net/netfilter/nf_conntrack_standalone.c | 59 ++++++++++++++++++++++++++++++++- - 1 file changed, 58 insertions(+), 1 deletion(-) - ---- a/net/netfilter/nf_conntrack_standalone.c -+++ b/net/netfilter/nf_conntrack_standalone.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #ifdef CONFIG_SYSCTL - #include -@@ -457,6 +458,56 @@ static int ct_cpu_seq_show(struct seq_fi - return 0; - } - -+struct kill_request { -+ u16 family; -+ union nf_inet_addr addr; -+}; -+ -+static int kill_matching(struct nf_conn *i, void *data) -+{ -+ struct kill_request *kr = data; -+ struct nf_conntrack_tuple *t1 = &i->tuplehash[IP_CT_DIR_ORIGINAL].tuple; -+ struct nf_conntrack_tuple *t2 = &i->tuplehash[IP_CT_DIR_REPLY].tuple; -+ -+ if (!kr->family) -+ return 1; -+ -+ if (t1->src.l3num != kr->family) -+ return 0; -+ -+ return (nf_inet_addr_cmp(&kr->addr, &t1->src.u3) || -+ nf_inet_addr_cmp(&kr->addr, &t1->dst.u3) || -+ nf_inet_addr_cmp(&kr->addr, &t2->src.u3) || -+ nf_inet_addr_cmp(&kr->addr, &t2->dst.u3)); -+} -+ -+static int ct_file_write(struct file *file, char *buf, size_t count) -+{ -+ struct seq_file *seq = file->private_data; -+ struct net *net = seq_file_net(seq); -+ struct kill_request kr = { }; -+ -+ if (count == 0) -+ return 0; -+ -+ if (count >= INET6_ADDRSTRLEN) -+ count = INET6_ADDRSTRLEN - 1; -+ -+ if (strnchr(buf, count, ':')) { -+ kr.family = AF_INET6; -+ if (!in6_pton(buf, count, (void *)&kr.addr, '\n', NULL)) -+ return -EINVAL; -+ } else if (strnchr(buf, count, '.')) { -+ kr.family = AF_INET; -+ if (!in4_pton(buf, count, (void *)&kr.addr, '\n', NULL)) -+ return -EINVAL; -+ } -+ -+ nf_ct_iterate_cleanup_net(net, kill_matching, &kr, 0, 0); -+ -+ return 0; -+} -+ - static const struct seq_operations ct_cpu_seq_ops = { - .start = ct_cpu_seq_start, - .next = ct_cpu_seq_next, -@@ -470,8 +521,9 @@ static int nf_conntrack_standalone_init_ - kuid_t root_uid; - kgid_t root_gid; - -- pde = proc_create_net("nf_conntrack", 0440, net->proc_net, &ct_seq_ops, -- sizeof(struct ct_iter_state)); -+ pde = proc_create_net_data_write("nf_conntrack", 0440, net->proc_net, -+ &ct_seq_ops, &ct_file_write, -+ sizeof(struct ct_iter_state), NULL); - if (!pde) - goto out_nf_conntrack; - diff --git a/target/linux/generic/pending-5.10/610-netfilter_match_bypass_default_checks.patch b/target/linux/generic/pending-5.10/610-netfilter_match_bypass_default_checks.patch deleted file mode 100644 index c1e050e935..0000000000 --- a/target/linux/generic/pending-5.10/610-netfilter_match_bypass_default_checks.patch +++ /dev/null @@ -1,110 +0,0 @@ -From: Felix Fietkau -Subject: kernel: add a new version of my netfilter speedup patches for linux 2.6.39 and 3.0 - -Signed-off-by: Felix Fietkau ---- - include/uapi/linux/netfilter_ipv4/ip_tables.h | 1 + - net/ipv4/netfilter/ip_tables.c | 37 +++++++++++++++++++++++++++ - 2 files changed, 38 insertions(+) - ---- a/include/uapi/linux/netfilter_ipv4/ip_tables.h -+++ b/include/uapi/linux/netfilter_ipv4/ip_tables.h -@@ -89,6 +89,7 @@ struct ipt_ip { - #define IPT_F_FRAG 0x01 /* Set if rule is a fragment rule */ - #define IPT_F_GOTO 0x02 /* Set if jump is a goto */ - #define IPT_F_MASK 0x03 /* All possible flag bits mask. */ -+#define IPT_F_NO_DEF_MATCH 0x80 /* Internal: no default match rules present */ - - /* Values for "inv" field in struct ipt_ip. */ - #define IPT_INV_VIA_IN 0x01 /* Invert the sense of IN IFACE. */ ---- a/net/ipv4/netfilter/ip_tables.c -+++ b/net/ipv4/netfilter/ip_tables.c -@@ -50,6 +50,9 @@ ip_packet_match(const struct iphdr *ip, - { - unsigned long ret; - -+ if (ipinfo->flags & IPT_F_NO_DEF_MATCH) -+ return true; -+ - if (NF_INVF(ipinfo, IPT_INV_SRCIP, - (ip->saddr & ipinfo->smsk.s_addr) != ipinfo->src.s_addr) || - NF_INVF(ipinfo, IPT_INV_DSTIP, -@@ -80,6 +83,29 @@ ip_packet_match(const struct iphdr *ip, - return true; - } - -+static void -+ip_checkdefault(struct ipt_ip *ip) -+{ -+ static const char iface_mask[IFNAMSIZ] = {}; -+ -+ if (ip->invflags || ip->flags & IPT_F_FRAG) -+ return; -+ -+ if (memcmp(ip->iniface_mask, iface_mask, IFNAMSIZ) != 0) -+ return; -+ -+ if (memcmp(ip->outiface_mask, iface_mask, IFNAMSIZ) != 0) -+ return; -+ -+ if (ip->smsk.s_addr || ip->dmsk.s_addr) -+ return; -+ -+ if (ip->proto) -+ return; -+ -+ ip->flags |= IPT_F_NO_DEF_MATCH; -+} -+ - static bool - ip_checkentry(const struct ipt_ip *ip) - { -@@ -524,6 +550,8 @@ find_check_entry(struct ipt_entry *e, st - struct xt_mtchk_param mtpar; - struct xt_entry_match *ematch; - -+ ip_checkdefault(&e->ip); -+ - if (!xt_percpu_counter_alloc(alloc_state, &e->counters)) - return -ENOMEM; - -@@ -818,6 +846,7 @@ copy_entries_to_user(unsigned int total_ - const struct xt_table_info *private = table->private; - int ret = 0; - const void *loc_cpu_entry; -+ u8 flags; - - counters = alloc_counters(table); - if (IS_ERR(counters)) -@@ -845,6 +874,14 @@ copy_entries_to_user(unsigned int total_ - goto free_counters; - } - -+ flags = e->ip.flags & IPT_F_MASK; -+ if (copy_to_user(userptr + off -+ + offsetof(struct ipt_entry, ip.flags), -+ &flags, sizeof(flags)) != 0) { -+ ret = -EFAULT; -+ goto free_counters; -+ } -+ - for (i = sizeof(struct ipt_entry); - i < e->target_offset; - i += m->u.match_size) { -@@ -1222,12 +1259,15 @@ compat_copy_entry_to_user(struct ipt_ent - compat_uint_t origsize; - const struct xt_entry_match *ematch; - int ret = 0; -+ u8 flags = e->ip.flags & IPT_F_MASK; - - origsize = *size; - ce = *dstptr; - if (copy_to_user(ce, e, sizeof(struct ipt_entry)) != 0 || - copy_to_user(&ce->counters, &counters[i], -- sizeof(counters[i])) != 0) -+ sizeof(counters[i])) != 0 || -+ copy_to_user(&ce->ip.flags, &flags, -+ sizeof(flags)) != 0) - return -EFAULT; - - *dstptr += sizeof(struct compat_ipt_entry); diff --git a/target/linux/generic/pending-5.10/611-netfilter_match_bypass_default_table.patch b/target/linux/generic/pending-5.10/611-netfilter_match_bypass_default_table.patch deleted file mode 100644 index baf738a8d2..0000000000 --- a/target/linux/generic/pending-5.10/611-netfilter_match_bypass_default_table.patch +++ /dev/null @@ -1,106 +0,0 @@ -From: Felix Fietkau -Subject: netfilter: match bypass default table - -Signed-off-by: Felix Fietkau ---- - net/ipv4/netfilter/ip_tables.c | 79 +++++++++++++++++++++++++++++++----------- - 1 file changed, 58 insertions(+), 21 deletions(-) - ---- a/net/ipv4/netfilter/ip_tables.c -+++ b/net/ipv4/netfilter/ip_tables.c -@@ -246,6 +246,33 @@ struct ipt_entry *ipt_next_entry(const s - return (void *)entry + entry->next_offset; - } - -+static bool -+ipt_handle_default_rule(struct ipt_entry *e, unsigned int *verdict) -+{ -+ struct xt_entry_target *t; -+ struct xt_standard_target *st; -+ -+ if (e->target_offset != sizeof(struct ipt_entry)) -+ return false; -+ -+ if (!(e->ip.flags & IPT_F_NO_DEF_MATCH)) -+ return false; -+ -+ t = ipt_get_target(e); -+ if (t->u.kernel.target->target) -+ return false; -+ -+ st = (struct xt_standard_target *) t; -+ if (st->verdict == XT_RETURN) -+ return false; -+ -+ if (st->verdict >= 0) -+ return false; -+ -+ *verdict = (unsigned)(-st->verdict) - 1; -+ return true; -+} -+ - /* Returns one of the generic firewall policies, like NF_ACCEPT. */ - unsigned int - ipt_do_table(struct sk_buff *skb, -@@ -266,27 +293,28 @@ ipt_do_table(struct sk_buff *skb, - unsigned int addend; - - /* Initialization */ -+ WARN_ON(!(table->valid_hooks & (1 << hook))); -+ local_bh_disable(); -+ private = READ_ONCE(table->private); /* Address dependency. */ -+ cpu = smp_processor_id(); -+ table_base = private->entries; -+ -+ e = get_entry(table_base, private->hook_entry[hook]); -+ if (ipt_handle_default_rule(e, &verdict)) { -+ struct xt_counters *counter; -+ -+ counter = xt_get_this_cpu_counter(&e->counters); -+ ADD_COUNTER(*counter, skb->len, 1); -+ local_bh_enable(); -+ return verdict; -+ } -+ - stackidx = 0; - ip = ip_hdr(skb); - indev = state->in ? state->in->name : nulldevname; - outdev = state->out ? state->out->name : nulldevname; -- /* We handle fragments by dealing with the first fragment as -- * if it was a normal packet. All other fragments are treated -- * normally, except that they will NEVER match rules that ask -- * things we don't know, ie. tcp syn flag or ports). If the -- * rule is also a fragment-specific rule, non-fragments won't -- * match it. */ -- acpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET; -- acpar.thoff = ip_hdrlen(skb); -- acpar.hotdrop = false; -- acpar.state = state; - -- WARN_ON(!(table->valid_hooks & (1 << hook))); -- local_bh_disable(); - addend = xt_write_recseq_begin(); -- private = READ_ONCE(table->private); /* Address dependency. */ -- cpu = smp_processor_id(); -- table_base = private->entries; - jumpstack = (struct ipt_entry **)private->jumpstack[cpu]; - - /* Switch to alternate jumpstack if we're being invoked via TEE. -@@ -299,7 +327,16 @@ ipt_do_table(struct sk_buff *skb, - if (static_key_false(&xt_tee_enabled)) - jumpstack += private->stacksize * __this_cpu_read(nf_skb_duplicated); - -- e = get_entry(table_base, private->hook_entry[hook]); -+ /* We handle fragments by dealing with the first fragment as -+ * if it was a normal packet. All other fragments are treated -+ * normally, except that they will NEVER match rules that ask -+ * things we don't know, ie. tcp syn flag or ports). If the -+ * rule is also a fragment-specific rule, non-fragments won't -+ * match it. */ -+ acpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET; -+ acpar.thoff = ip_hdrlen(skb); -+ acpar.hotdrop = false; -+ acpar.state = state; - - do { - const struct xt_entry_target *t; diff --git a/target/linux/generic/pending-5.10/612-netfilter_match_reduce_memory_access.patch b/target/linux/generic/pending-5.10/612-netfilter_match_reduce_memory_access.patch deleted file mode 100644 index 79da6778b6..0000000000 --- a/target/linux/generic/pending-5.10/612-netfilter_match_reduce_memory_access.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Felix Fietkau -Subject: netfilter: reduce match memory access - -Signed-off-by: Felix Fietkau ---- - net/ipv4/netfilter/ip_tables.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/net/ipv4/netfilter/ip_tables.c -+++ b/net/ipv4/netfilter/ip_tables.c -@@ -53,9 +53,9 @@ ip_packet_match(const struct iphdr *ip, - if (ipinfo->flags & IPT_F_NO_DEF_MATCH) - return true; - -- if (NF_INVF(ipinfo, IPT_INV_SRCIP, -+ if (NF_INVF(ipinfo, IPT_INV_SRCIP, ipinfo->smsk.s_addr && - (ip->saddr & ipinfo->smsk.s_addr) != ipinfo->src.s_addr) || -- NF_INVF(ipinfo, IPT_INV_DSTIP, -+ NF_INVF(ipinfo, IPT_INV_DSTIP, ipinfo->dmsk.s_addr && - (ip->daddr & ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr)) - return false; - diff --git a/target/linux/generic/pending-5.10/620-net_sched-codel-do-not-defer-queue-length-update.patch b/target/linux/generic/pending-5.10/620-net_sched-codel-do-not-defer-queue-length-update.patch deleted file mode 100644 index 4b4825ae3b..0000000000 --- a/target/linux/generic/pending-5.10/620-net_sched-codel-do-not-defer-queue-length-update.patch +++ /dev/null @@ -1,86 +0,0 @@ -From: Konstantin Khlebnikov -Date: Mon, 21 Aug 2017 11:14:14 +0300 -Subject: [PATCH] net_sched/codel: do not defer queue length update - -When codel wants to drop last packet in ->dequeue() it cannot call -qdisc_tree_reduce_backlog() right away - it will notify parent qdisc -about zero qlen and HTB/HFSC will deactivate class. The same class will -be deactivated second time by caller of ->dequeue(). Currently codel and -fq_codel defer update. This triggers warning in HFSC when it's qlen != 0 -but there is no active classes. - -This patch update parent queue length immediately: just temporary increase -qlen around qdisc_tree_reduce_backlog() to prevent first class deactivation -if we have skb to return. - -This might open another problem in HFSC - now operation peek could fail and -deactivate parent class. - -Signed-off-by: Konstantin Khlebnikov -Link: https://bugzilla.kernel.org/show_bug.cgi?id=109581 ---- - ---- a/net/sched/sch_codel.c -+++ b/net/sched/sch_codel.c -@@ -95,11 +95,17 @@ static struct sk_buff *codel_qdisc_deque - &q->stats, qdisc_pkt_len, codel_get_enqueue_time, - drop_func, dequeue_func); - -- /* We cant call qdisc_tree_reduce_backlog() if our qlen is 0, -- * or HTB crashes. Defer it for next round. -+ /* If our qlen is 0 qdisc_tree_reduce_backlog() will deactivate -+ * parent class, dequeue in parent qdisc will do the same if we -+ * return skb. Temporary increment qlen if we have skb. - */ -- if (q->stats.drop_count && sch->q.qlen) { -- qdisc_tree_reduce_backlog(sch, q->stats.drop_count, q->stats.drop_len); -+ if (q->stats.drop_count) { -+ if (skb) -+ sch->q.qlen++; -+ qdisc_tree_reduce_backlog(sch, q->stats.drop_count, -+ q->stats.drop_len); -+ if (skb) -+ sch->q.qlen--; - q->stats.drop_count = 0; - q->stats.drop_len = 0; - } ---- a/net/sched/sch_fq_codel.c -+++ b/net/sched/sch_fq_codel.c -@@ -304,6 +304,21 @@ begin: - &flow->cvars, &q->cstats, qdisc_pkt_len, - codel_get_enqueue_time, drop_func, dequeue_func); - -+ /* If our qlen is 0 qdisc_tree_reduce_backlog() will deactivate -+ * parent class, dequeue in parent qdisc will do the same if we -+ * return skb. Temporary increment qlen if we have skb. -+ */ -+ if (q->cstats.drop_count) { -+ if (skb) -+ sch->q.qlen++; -+ qdisc_tree_reduce_backlog(sch, q->cstats.drop_count, -+ q->cstats.drop_len); -+ if (skb) -+ sch->q.qlen--; -+ q->cstats.drop_count = 0; -+ q->cstats.drop_len = 0; -+ } -+ - if (!skb) { - /* force a pass through old_flows to prevent starvation */ - if ((head == &q->new_flows) && !list_empty(&q->old_flows)) -@@ -314,15 +329,6 @@ begin: - } - qdisc_bstats_update(sch, skb); - flow->deficit -= qdisc_pkt_len(skb); -- /* We cant call qdisc_tree_reduce_backlog() if our qlen is 0, -- * or HTB crashes. Defer it for next round. -- */ -- if (q->cstats.drop_count && sch->q.qlen) { -- qdisc_tree_reduce_backlog(sch, q->cstats.drop_count, -- q->cstats.drop_len); -- q->cstats.drop_count = 0; -- q->cstats.drop_len = 0; -- } - return skb; - } - diff --git a/target/linux/generic/pending-5.10/630-packet_socket_type.patch b/target/linux/generic/pending-5.10/630-packet_socket_type.patch deleted file mode 100644 index e9ecd8a8b2..0000000000 --- a/target/linux/generic/pending-5.10/630-packet_socket_type.patch +++ /dev/null @@ -1,138 +0,0 @@ -From: Felix Fietkau -Subject: net: add an optimization for dealing with raw sockets - -lede-commit: 4898039703d7315f0f3431c860123338ec3be0f6 -Signed-off-by: Felix Fietkau ---- - include/uapi/linux/if_packet.h | 3 +++ - net/packet/af_packet.c | 34 +++++++++++++++++++++++++++------- - net/packet/internal.h | 1 + - 3 files changed, 31 insertions(+), 7 deletions(-) - ---- a/include/uapi/linux/if_packet.h -+++ b/include/uapi/linux/if_packet.h -@@ -33,6 +33,8 @@ struct sockaddr_ll { - #define PACKET_KERNEL 7 /* To kernel space */ - /* Unused, PACKET_FASTROUTE and PACKET_LOOPBACK are invisible to user space */ - #define PACKET_FASTROUTE 6 /* Fastrouted frame */ -+#define PACKET_MASK_ANY 0xffffffff /* mask for packet type bits */ -+ - - /* Packet socket options */ - -@@ -59,6 +61,7 @@ struct sockaddr_ll { - #define PACKET_ROLLOVER_STATS 21 - #define PACKET_FANOUT_DATA 22 - #define PACKET_IGNORE_OUTGOING 23 -+#define PACKET_RECV_TYPE 24 - - #define PACKET_FANOUT_HASH 0 - #define PACKET_FANOUT_LB 1 ---- a/net/packet/af_packet.c -+++ b/net/packet/af_packet.c -@@ -1822,6 +1822,7 @@ static int packet_rcv_spkt(struct sk_buf - { - struct sock *sk; - struct sockaddr_pkt *spkt; -+ struct packet_sock *po; - - /* - * When we registered the protocol we saved the socket in the data -@@ -1829,6 +1830,7 @@ static int packet_rcv_spkt(struct sk_buf - */ - - sk = pt->af_packet_priv; -+ po = pkt_sk(sk); - - /* - * Yank back the headers [hope the device set this -@@ -1841,7 +1843,7 @@ static int packet_rcv_spkt(struct sk_buf - * so that this procedure is noop. - */ - -- if (skb->pkt_type == PACKET_LOOPBACK) -+ if (!(po->pkt_type & (1 << skb->pkt_type))) - goto out; - - if (!net_eq(dev_net(dev), sock_net(sk))) -@@ -2089,12 +2091,12 @@ static int packet_rcv(struct sk_buff *sk - unsigned int snaplen, res; - bool is_drop_n_account = false; - -- if (skb->pkt_type == PACKET_LOOPBACK) -- goto drop; -- - sk = pt->af_packet_priv; - po = pkt_sk(sk); - -+ if (!(po->pkt_type & (1 << skb->pkt_type))) -+ goto drop; -+ - if (!net_eq(dev_net(dev), sock_net(sk))) - goto drop; - -@@ -2220,12 +2222,12 @@ static int tpacket_rcv(struct sk_buff *s - BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32); - BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48); - -- if (skb->pkt_type == PACKET_LOOPBACK) -- goto drop; -- - sk = pt->af_packet_priv; - po = pkt_sk(sk); - -+ if (!(po->pkt_type & (1 << skb->pkt_type))) -+ goto drop; -+ - if (!net_eq(dev_net(dev), sock_net(sk))) - goto drop; - -@@ -3339,6 +3341,7 @@ static int packet_create(struct net *net - mutex_init(&po->pg_vec_lock); - po->rollover = NULL; - po->prot_hook.func = packet_rcv; -+ po->pkt_type = PACKET_MASK_ANY & ~(1 << PACKET_LOOPBACK); - - if (sock->type == SOCK_PACKET) - po->prot_hook.func = packet_rcv_spkt; -@@ -3982,6 +3985,16 @@ packet_setsockopt(struct socket *sock, i - po->xmit = val ? packet_direct_xmit : dev_queue_xmit; - return 0; - } -+ case PACKET_RECV_TYPE: -+ { -+ unsigned int val; -+ if (optlen != sizeof(val)) -+ return -EINVAL; -+ if (copy_from_sockptr(&val, optval, sizeof(val))) -+ return -EFAULT; -+ po->pkt_type = val & ~BIT(PACKET_LOOPBACK); -+ return 0; -+ } - default: - return -ENOPROTOOPT; - } -@@ -4038,6 +4051,13 @@ static int packet_getsockopt(struct sock - case PACKET_VNET_HDR: - val = po->has_vnet_hdr; - break; -+ case PACKET_RECV_TYPE: -+ if (len > sizeof(unsigned int)) -+ len = sizeof(unsigned int); -+ val = po->pkt_type; -+ -+ data = &val; -+ break; - case PACKET_VERSION: - val = po->tp_version; - break; ---- a/net/packet/internal.h -+++ b/net/packet/internal.h -@@ -137,6 +137,7 @@ struct packet_sock { - int (*xmit)(struct sk_buff *skb); - struct packet_type prot_hook ____cacheline_aligned_in_smp; - atomic_t tp_drops ____cacheline_aligned_in_smp; -+ unsigned int pkt_type; - }; - - static struct packet_sock *pkt_sk(struct sock *sk) diff --git a/target/linux/generic/pending-5.10/655-increase_skb_pad.patch b/target/linux/generic/pending-5.10/655-increase_skb_pad.patch deleted file mode 100644 index dafafad588..0000000000 --- a/target/linux/generic/pending-5.10/655-increase_skb_pad.patch +++ /dev/null @@ -1,20 +0,0 @@ -From: Felix Fietkau -Subject: kernel: add a few patches for avoiding unnecessary skb reallocations - significantly improves ethernet<->wireless performance - -lede-commit: 6f89cffc9add6939d44a6b54cf9a5e77849aa7fd -Signed-off-by: Felix Fietkau ---- - include/linux/skbuff.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/include/linux/skbuff.h -+++ b/include/linux/skbuff.h -@@ -2694,7 +2694,7 @@ static inline int pskb_network_may_pull( - * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8) - */ - #ifndef NET_SKB_PAD --#define NET_SKB_PAD max(32, L1_CACHE_BYTES) -+#define NET_SKB_PAD max(64, L1_CACHE_BYTES) - #endif - - int ___pskb_trim(struct sk_buff *skb, unsigned int len); diff --git a/target/linux/generic/pending-5.10/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/pending-5.10/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch deleted file mode 100644 index 59f202c4c5..0000000000 --- a/target/linux/generic/pending-5.10/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch +++ /dev/null @@ -1,511 +0,0 @@ -From: Steven Barth -Subject: Add support for MAP-E FMRs (mesh mode) - -MAP-E FMRs (draft-ietf-softwire-map-10) are rules for IPv4-communication -between MAP CEs (mesh mode) without the need to forward such data to a -border relay. This is similar to how 6rd works but for IPv4 over IPv6. - -Signed-off-by: Steven Barth ---- - include/net/ip6_tunnel.h | 13 ++ - include/uapi/linux/if_tunnel.h | 13 ++ - net/ipv6/ip6_tunnel.c | 276 +++++++++++++++++++++++++++++++++++++++-- - 3 files changed, 291 insertions(+), 11 deletions(-) - ---- a/include/net/ip6_tunnel.h -+++ b/include/net/ip6_tunnel.h -@@ -18,6 +18,18 @@ - /* determine capability on a per-packet basis */ - #define IP6_TNL_F_CAP_PER_PACKET 0x40000 - -+/* IPv6 tunnel FMR */ -+struct __ip6_tnl_fmr { -+ struct __ip6_tnl_fmr *next; /* next fmr in list */ -+ struct in6_addr ip6_prefix; -+ struct in_addr ip4_prefix; -+ -+ __u8 ip6_prefix_len; -+ __u8 ip4_prefix_len; -+ __u8 ea_len; -+ __u8 offset; -+}; -+ - struct __ip6_tnl_parm { - char name[IFNAMSIZ]; /* name of tunnel device */ - int link; /* ifindex of underlying L2 interface */ -@@ -29,6 +41,7 @@ struct __ip6_tnl_parm { - __u32 flags; /* tunnel flags */ - struct in6_addr laddr; /* local tunnel end-point address */ - struct in6_addr raddr; /* remote tunnel end-point address */ -+ struct __ip6_tnl_fmr *fmrs; /* FMRs */ - - __be16 i_flags; - __be16 o_flags; ---- a/include/uapi/linux/if_tunnel.h -+++ b/include/uapi/linux/if_tunnel.h -@@ -77,10 +77,23 @@ enum { - IFLA_IPTUN_ENCAP_DPORT, - IFLA_IPTUN_COLLECT_METADATA, - IFLA_IPTUN_FWMARK, -+ IFLA_IPTUN_FMRS, - __IFLA_IPTUN_MAX, - }; - #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) - -+enum { -+ IFLA_IPTUN_FMR_UNSPEC, -+ IFLA_IPTUN_FMR_IP6_PREFIX, -+ IFLA_IPTUN_FMR_IP4_PREFIX, -+ IFLA_IPTUN_FMR_IP6_PREFIX_LEN, -+ IFLA_IPTUN_FMR_IP4_PREFIX_LEN, -+ IFLA_IPTUN_FMR_EA_LEN, -+ IFLA_IPTUN_FMR_OFFSET, -+ __IFLA_IPTUN_FMR_MAX, -+}; -+#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1) -+ - enum tunnel_encap_types { - TUNNEL_ENCAP_NONE, - TUNNEL_ENCAP_FOU, ---- a/net/ipv6/ip6_tunnel.c -+++ b/net/ipv6/ip6_tunnel.c -@@ -11,6 +11,9 @@ - * linux/net/ipv6/sit.c and linux/net/ipv4/ipip.c - * - * RFC 2473 -+ * -+ * Changes: -+ * Steven Barth : MAP-E FMR support - */ - - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -@@ -67,9 +70,9 @@ static bool log_ecn_error = true; - module_param(log_ecn_error, bool, 0644); - MODULE_PARM_DESC(log_ecn_error, "Log packets received with corrupted ECN"); - --static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2) -+static u32 HASH(const struct in6_addr *addr) - { -- u32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2); -+ u32 hash = ipv6_addr_hash(addr); - - return hash_32(hash, IP6_TUNNEL_HASH_SIZE_SHIFT); - } -@@ -144,17 +147,33 @@ static struct ip6_tnl * - ip6_tnl_lookup(struct net *net, int link, - const struct in6_addr *remote, const struct in6_addr *local) - { -- unsigned int hash = HASH(remote, local); -+ unsigned int hash = HASH(local); - struct ip6_tnl *t, *cand = NULL; - struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); - struct in6_addr any; - - for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { - if (!ipv6_addr_equal(local, &t->parms.laddr) || -- !ipv6_addr_equal(remote, &t->parms.raddr) || - !(t->dev->flags & IFF_UP)) - continue; - -+ if (!ipv6_addr_equal(remote, &t->parms.raddr)) { -+ struct __ip6_tnl_fmr *fmr; -+ bool found = false; -+ -+ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { -+ if (!ipv6_prefix_equal(remote, &fmr->ip6_prefix, -+ fmr->ip6_prefix_len)) -+ continue; -+ -+ found = true; -+ break; -+ } -+ -+ if (!found) -+ continue; -+ } -+ - if (link == t->parms.link) - return t; - else -@@ -162,7 +181,7 @@ ip6_tnl_lookup(struct net *net, int link - } - - memset(&any, 0, sizeof(any)); -- hash = HASH(&any, local); -+ hash = HASH(local); - for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { - if (!ipv6_addr_equal(local, &t->parms.laddr) || - !ipv6_addr_any(&t->parms.raddr) || -@@ -175,7 +194,7 @@ ip6_tnl_lookup(struct net *net, int link - cand = t; - } - -- hash = HASH(remote, &any); -+ hash = HASH(&any); - for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { - if (!ipv6_addr_equal(remote, &t->parms.raddr) || - !ipv6_addr_any(&t->parms.laddr) || -@@ -223,7 +242,7 @@ ip6_tnl_bucket(struct ip6_tnl_net *ip6n, - - if (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) { - prio = 1; -- h = HASH(remote, local); -+ h = HASH(local); - } - return &ip6n->tnls[prio][h]; - } -@@ -405,6 +424,12 @@ ip6_tnl_dev_uninit(struct net_device *de - struct net *net = t->net; - struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); - -+ while (t->parms.fmrs) { -+ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; -+ kfree(t->parms.fmrs); -+ t->parms.fmrs = next; -+ } -+ - if (dev == ip6n->fb_tnl_dev) - RCU_INIT_POINTER(ip6n->tnls_wc[0], NULL); - else -@@ -821,6 +846,107 @@ int ip6_tnl_rcv_ctl(struct ip6_tnl *t, - } - EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl); - -+/** -+ * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR -+ * @dest: destination IPv6 address buffer -+ * @skb: received socket buffer -+ * @fmr: MAP FMR -+ * @xmit: Calculate for xmit or rcv -+ **/ -+static void ip4ip6_fmr_calc(struct in6_addr *dest, -+ const struct iphdr *iph, const uint8_t *end, -+ const struct __ip6_tnl_fmr *fmr, bool xmit) -+{ -+ int psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len); -+ u8 *portp = NULL; -+ bool use_dest_addr; -+ const struct iphdr *dsth = iph; -+ -+ if ((u8*)dsth >= end) -+ return; -+ -+ /* find significant IP header */ -+ if (iph->protocol == IPPROTO_ICMP) { -+ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); -+ if (ih && ((u8*)&ih[1]) <= end && ( -+ ih->type == ICMP_DEST_UNREACH || -+ ih->type == ICMP_SOURCE_QUENCH || -+ ih->type == ICMP_TIME_EXCEEDED || -+ ih->type == ICMP_PARAMETERPROB || -+ ih->type == ICMP_REDIRECT)) -+ dsth = (const struct iphdr*)&ih[1]; -+ } -+ -+ /* in xmit-path use dest port by default and source port only if -+ this is an ICMP reply to something else; vice versa in rcv-path */ -+ use_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph); -+ -+ /* get dst port */ -+ if (((u8*)&dsth[1]) <= end && ( -+ dsth->protocol == IPPROTO_UDP || -+ dsth->protocol == IPPROTO_TCP || -+ dsth->protocol == IPPROTO_SCTP || -+ dsth->protocol == IPPROTO_DCCP)) { -+ /* for UDP, TCP, SCTP and DCCP source and dest port -+ follow IPv4 header directly */ -+ portp = ((u8*)dsth) + dsth->ihl * 4; -+ -+ if (use_dest_addr) -+ portp += sizeof(u16); -+ } else if (iph->protocol == IPPROTO_ICMP) { -+ struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); -+ -+ /* use icmp identifier as port */ -+ if (((u8*)&ih) <= end && ( -+ (use_dest_addr && ( -+ ih->type == ICMP_ECHOREPLY || -+ ih->type == ICMP_TIMESTAMPREPLY || -+ ih->type == ICMP_INFO_REPLY || -+ ih->type == ICMP_ADDRESSREPLY)) || -+ (!use_dest_addr && ( -+ ih->type == ICMP_ECHO || -+ ih->type == ICMP_TIMESTAMP || -+ ih->type == ICMP_INFO_REQUEST || -+ ih->type == ICMP_ADDRESS) -+ ))) -+ portp = (u8*)&ih->un.echo.id; -+ } -+ -+ if ((portp && &portp[2] <= end) || psidlen == 0) { -+ int frombyte = fmr->ip6_prefix_len / 8; -+ int fromrem = fmr->ip6_prefix_len % 8; -+ int bytes = sizeof(struct in6_addr) - frombyte; -+ const u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr; -+ u64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len); -+ u64 t = 0; -+ -+ /* extract PSID from port and add it to eabits */ -+ u16 psidbits = 0; -+ if (psidlen > 0) { -+ psidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]); -+ psidbits >>= 16 - psidlen - fmr->offset; -+ psidbits = (u16)(psidbits << (16 - psidlen)); -+ eabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen)); -+ } -+ -+ /* rewrite destination address */ -+ *dest = fmr->ip6_prefix; -+ memcpy(&dest->s6_addr[10], addr, sizeof(*addr)); -+ dest->s6_addr16[7] = htons(psidbits >> (16 - psidlen)); -+ -+ if (bytes > sizeof(u64)) -+ bytes = sizeof(u64); -+ -+ /* insert eabits */ -+ memcpy(&t, &dest->s6_addr[frombyte], bytes); -+ t = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1) -+ << (64 - fmr->ea_len - fromrem)); -+ t = cpu_to_be64(t | (eabits >> fromrem)); -+ memcpy(&dest->s6_addr[frombyte], &t, bytes); -+ } -+} -+ -+ - static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb, - const struct tnl_ptk_info *tpi, - struct metadata_dst *tun_dst, -@@ -873,6 +999,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl - skb_reset_network_header(skb); - memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); - -+ if (tpi->proto == htons(ETH_P_IP) && tunnel->parms.fmrs && -+ !ipv6_addr_equal(&ipv6h->saddr, &tunnel->parms.raddr)) { -+ /* Packet didn't come from BR, so lookup FMR */ -+ struct __ip6_tnl_fmr *fmr; -+ struct in6_addr expected = tunnel->parms.raddr; -+ for (fmr = tunnel->parms.fmrs; fmr; fmr = fmr->next) -+ if (ipv6_prefix_equal(&ipv6h->saddr, -+ &fmr->ip6_prefix, fmr->ip6_prefix_len)) -+ break; -+ -+ /* Check that IPv6 matches IPv4 source to prevent spoofing */ -+ if (fmr) -+ ip4ip6_fmr_calc(&expected, ip_hdr(skb), -+ skb_tail_pointer(skb), fmr, false); -+ -+ if (!ipv6_addr_equal(&ipv6h->saddr, &expected)) { -+ rcu_read_unlock(); -+ goto drop; -+ } -+ } -+ - __skb_tunnel_rx(skb, tunnel->dev, tunnel->net); - - err = dscp_ecn_decapsulate(tunnel, ipv6h, skb); -@@ -1024,6 +1171,7 @@ static void init_tel_txopt(struct ipv6_t - opt->ops.opt_nflen = 8; - } - -+ - /** - * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own - * @t: the outgoing tunnel device -@@ -1304,6 +1452,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str - u8 protocol) - { - struct ip6_tnl *t = netdev_priv(dev); -+ struct __ip6_tnl_fmr *fmr; - struct ipv6hdr *ipv6h; - const struct iphdr *iph; - int encap_limit = -1; -@@ -1403,6 +1552,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str - fl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL); - dsfield = INET_ECN_encapsulate(dsfield, orig_dsfield); - -+ /* try to find matching FMR */ -+ for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { -+ unsigned mshift = 32 - fmr->ip4_prefix_len; -+ if (ntohl(fmr->ip4_prefix.s_addr) >> mshift == -+ ntohl(ip_hdr(skb)->daddr) >> mshift) -+ break; -+ } -+ -+ /* change dstaddr according to FMR */ -+ if (fmr) -+ ip4ip6_fmr_calc(&fl6.daddr, ip_hdr(skb), skb_tail_pointer(skb), fmr, true); -+ - if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6)) - return -1; - -@@ -1556,6 +1717,14 @@ ip6_tnl_change(struct ip6_tnl *t, const - t->parms.link = p->link; - t->parms.proto = p->proto; - t->parms.fwmark = p->fwmark; -+ -+ while (t->parms.fmrs) { -+ struct __ip6_tnl_fmr *next = t->parms.fmrs->next; -+ kfree(t->parms.fmrs); -+ t->parms.fmrs = next; -+ } -+ t->parms.fmrs = p->fmrs; -+ - dst_cache_reset(&t->dst_cache); - ip6_tnl_link_config(t); - return 0; -@@ -1594,6 +1763,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_ - p->flowinfo = u->flowinfo; - p->link = u->link; - p->proto = u->proto; -+ p->fmrs = NULL; - memcpy(p->name, u->name, sizeof(u->name)); - } - -@@ -1979,6 +2149,15 @@ static int ip6_tnl_validate(struct nlatt - return 0; - } - -+static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = { -+ [IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) }, -+ [IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) }, -+ [IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 }, -+ [IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 }, -+ [IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 }, -+ [IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 } -+}; -+ - static void ip6_tnl_netlink_parms(struct nlattr *data[], - struct __ip6_tnl_parm *parms) - { -@@ -2016,6 +2195,46 @@ static void ip6_tnl_netlink_parms(struct - - if (data[IFLA_IPTUN_FWMARK]) - parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]); -+ -+ if (data[IFLA_IPTUN_FMRS]) { -+ unsigned rem; -+ struct nlattr *fmr; -+ nla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) { -+ struct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c; -+ struct __ip6_tnl_fmr *nfmr; -+ -+ nla_parse_nested(fmrd, IFLA_IPTUN_FMR_MAX, -+ fmr, ip6_tnl_fmr_policy, NULL); -+ -+ if (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL))) -+ continue; -+ -+ nfmr->offset = 6; -+ -+ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX])) -+ nla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX], -+ sizeof(nfmr->ip6_prefix)); -+ -+ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX])) -+ nla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX], -+ sizeof(nfmr->ip4_prefix)); -+ -+ if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN])) -+ nfmr->ip6_prefix_len = nla_get_u8(c); -+ -+ if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN])) -+ nfmr->ip4_prefix_len = nla_get_u8(c); -+ -+ if ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN])) -+ nfmr->ea_len = nla_get_u8(c); -+ -+ if ((c = fmrd[IFLA_IPTUN_FMR_OFFSET])) -+ nfmr->offset = nla_get_u8(c); -+ -+ nfmr->next = parms->fmrs; -+ parms->fmrs = nfmr; -+ } -+ } - } - - static bool ip6_tnl_netlink_encap_parms(struct nlattr *data[], -@@ -2131,6 +2350,12 @@ static void ip6_tnl_dellink(struct net_d - - static size_t ip6_tnl_get_size(const struct net_device *dev) - { -+ const struct ip6_tnl *t = netdev_priv(dev); -+ struct __ip6_tnl_fmr *c; -+ int fmrs = 0; -+ for (c = t->parms.fmrs; c; c = c->next) -+ ++fmrs; -+ - return - /* IFLA_IPTUN_LINK */ - nla_total_size(4) + -@@ -2160,6 +2385,24 @@ static size_t ip6_tnl_get_size(const str - nla_total_size(0) + - /* IFLA_IPTUN_FWMARK */ - nla_total_size(4) + -+ /* IFLA_IPTUN_FMRS */ -+ nla_total_size(0) + -+ ( -+ /* nest */ -+ nla_total_size(0) + -+ /* IFLA_IPTUN_FMR_IP6_PREFIX */ -+ nla_total_size(sizeof(struct in6_addr)) + -+ /* IFLA_IPTUN_FMR_IP4_PREFIX */ -+ nla_total_size(sizeof(struct in_addr)) + -+ /* IFLA_IPTUN_FMR_EA_LEN */ -+ nla_total_size(1) + -+ /* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */ -+ nla_total_size(1) + -+ /* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */ -+ nla_total_size(1) + -+ /* IFLA_IPTUN_FMR_OFFSET */ -+ nla_total_size(1) -+ ) * fmrs + - 0; - } - -@@ -2167,6 +2410,9 @@ static int ip6_tnl_fill_info(struct sk_b - { - struct ip6_tnl *tunnel = netdev_priv(dev); - struct __ip6_tnl_parm *parm = &tunnel->parms; -+ struct __ip6_tnl_fmr *c; -+ int fmrcnt = 0; -+ struct nlattr *fmrs; - - if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || - nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || -@@ -2176,9 +2422,27 @@ static int ip6_tnl_fill_info(struct sk_b - nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || - nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || - nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || -- nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark)) -+ nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark) || -+ !(fmrs = nla_nest_start(skb, IFLA_IPTUN_FMRS))) - goto nla_put_failure; - -+ for (c = parm->fmrs; c; c = c->next) { -+ struct nlattr *fmr = nla_nest_start(skb, ++fmrcnt); -+ if (!fmr || -+ nla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX, -+ sizeof(c->ip6_prefix), &c->ip6_prefix) || -+ nla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX, -+ sizeof(c->ip4_prefix), &c->ip4_prefix) || -+ nla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) || -+ nla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) || -+ nla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) || -+ nla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset)) -+ goto nla_put_failure; -+ -+ nla_nest_end(skb, fmr); -+ } -+ nla_nest_end(skb, fmrs); -+ - if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) || - nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) || - nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) || -@@ -2218,6 +2482,7 @@ static const struct nla_policy ip6_tnl_p - [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, - [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, - [IFLA_IPTUN_FWMARK] = { .type = NLA_U32 }, -+ [IFLA_IPTUN_FMRS] = { .type = NLA_NESTED }, - }; - - static struct rtnl_link_ops ip6_link_ops __read_mostly = { diff --git a/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch deleted file mode 100644 index ac1b327b9e..0000000000 --- a/target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch +++ /dev/null @@ -1,263 +0,0 @@ -From: Jonas Gorski -Subject: ipv6: allow rejecting with "source address failed policy" - -RFC6204 L-14 requires rejecting traffic from invalid addresses with -ICMPv6 Destination Unreachable, Code 5 (Source address failed ingress/ -egress policy) on the LAN side, so add an appropriate rule for that. - -Signed-off-by: Jonas Gorski ---- - include/net/netns/ipv6.h | 1 + - include/uapi/linux/fib_rules.h | 4 +++ - include/uapi/linux/rtnetlink.h | 1 + - net/ipv4/fib_semantics.c | 4 +++ - net/ipv4/fib_trie.c | 1 + - net/ipv4/ipmr.c | 1 + - net/ipv6/fib6_rules.c | 4 +++ - net/ipv6/ip6mr.c | 2 ++ - net/ipv6/route.c | 58 +++++++++++++++++++++++++++++++++++++++++- - 9 files changed, 75 insertions(+), 1 deletion(-) - ---- a/include/net/netns/ipv6.h -+++ b/include/net/netns/ipv6.h -@@ -88,6 +88,7 @@ struct netns_ipv6 { - unsigned int fib6_routes_require_src; - #endif - struct rt6_info *ip6_prohibit_entry; -+ struct rt6_info *ip6_policy_failed_entry; - struct rt6_info *ip6_blk_hole_entry; - struct fib6_table *fib6_local_tbl; - struct fib_rules_ops *fib6_rules_ops; ---- a/include/uapi/linux/fib_rules.h -+++ b/include/uapi/linux/fib_rules.h -@@ -82,6 +82,10 @@ enum { - FR_ACT_BLACKHOLE, /* Drop without notification */ - FR_ACT_UNREACHABLE, /* Drop with ENETUNREACH */ - FR_ACT_PROHIBIT, /* Drop with EACCES */ -+ FR_ACT_RES9, -+ FR_ACT_RES10, -+ FR_ACT_RES11, -+ FR_ACT_POLICY_FAILED, /* Drop with EACCES */ - __FR_ACT_MAX, - }; - ---- a/include/uapi/linux/rtnetlink.h -+++ b/include/uapi/linux/rtnetlink.h -@@ -249,6 +249,7 @@ enum { - RTN_THROW, /* Not in this table */ - RTN_NAT, /* Translate this address */ - RTN_XRESOLVE, /* Use external resolver */ -+ RTN_POLICY_FAILED, /* Failed ingress/egress policy */ - __RTN_MAX - }; - ---- a/net/ipv4/fib_semantics.c -+++ b/net/ipv4/fib_semantics.c -@@ -143,6 +143,10 @@ const struct fib_prop fib_props[RTN_MAX - .error = -EINVAL, - .scope = RT_SCOPE_NOWHERE, - }, -+ [RTN_POLICY_FAILED] = { -+ .error = -EACCES, -+ .scope = RT_SCOPE_UNIVERSE, -+ }, - }; - - static void rt_fibinfo_free(struct rtable __rcu **rtp) ---- a/net/ipv4/fib_trie.c -+++ b/net/ipv4/fib_trie.c -@@ -2736,6 +2736,7 @@ static const char *const rtn_type_names[ - [RTN_THROW] = "THROW", - [RTN_NAT] = "NAT", - [RTN_XRESOLVE] = "XRESOLVE", -+ [RTN_POLICY_FAILED] = "POLICY_FAILED", - }; - - static inline const char *rtn_type(char *buf, size_t len, unsigned int t) ---- a/net/ipv4/ipmr.c -+++ b/net/ipv4/ipmr.c -@@ -175,6 +175,7 @@ static int ipmr_rule_action(struct fib_r - case FR_ACT_UNREACHABLE: - return -ENETUNREACH; - case FR_ACT_PROHIBIT: -+ case FR_ACT_POLICY_FAILED: - return -EACCES; - case FR_ACT_BLACKHOLE: - default: ---- a/net/ipv6/fib6_rules.c -+++ b/net/ipv6/fib6_rules.c -@@ -220,6 +220,10 @@ static int __fib6_rule_action(struct fib - err = -EACCES; - rt = net->ipv6.ip6_prohibit_entry; - goto discard_pkt; -+ case FR_ACT_POLICY_FAILED: -+ err = -EACCES; -+ rt = net->ipv6.ip6_policy_failed_entry; -+ goto discard_pkt; - } - - tb_id = fib_rule_get_table(rule, arg); ---- a/net/ipv6/ip6mr.c -+++ b/net/ipv6/ip6mr.c -@@ -163,6 +163,8 @@ static int ip6mr_rule_action(struct fib_ - return -ENETUNREACH; - case FR_ACT_PROHIBIT: - return -EACCES; -+ case FR_ACT_POLICY_FAILED: -+ return -EACCES; - case FR_ACT_BLACKHOLE: - default: - return -EINVAL; ---- a/net/ipv6/route.c -+++ b/net/ipv6/route.c -@@ -95,6 +95,8 @@ static int ip6_pkt_discard(struct sk_bu - static int ip6_pkt_discard_out(struct net *net, struct sock *sk, struct sk_buff *skb); - static int ip6_pkt_prohibit(struct sk_buff *skb); - static int ip6_pkt_prohibit_out(struct net *net, struct sock *sk, struct sk_buff *skb); -+static int ip6_pkt_policy_failed(struct sk_buff *skb); -+static int ip6_pkt_policy_failed_out(struct net *net, struct sock *sk, struct sk_buff *skb); - static void ip6_link_failure(struct sk_buff *skb); - static void ip6_rt_update_pmtu(struct dst_entry *dst, struct sock *sk, - struct sk_buff *skb, u32 mtu, -@@ -310,6 +312,18 @@ static const struct rt6_info ip6_prohibi - .rt6i_flags = (RTF_REJECT | RTF_NONEXTHOP), - }; - -+static const struct rt6_info ip6_policy_failed_entry_template = { -+ .dst = { -+ .__refcnt = ATOMIC_INIT(1), -+ .__use = 1, -+ .obsolete = DST_OBSOLETE_FORCE_CHK, -+ .error = -EACCES, -+ .input = ip6_pkt_policy_failed, -+ .output = ip6_pkt_policy_failed_out, -+ }, -+ .rt6i_flags = (RTF_REJECT | RTF_NONEXTHOP), -+}; -+ - static const struct rt6_info ip6_blk_hole_entry_template = { - .dst = { - .__refcnt = ATOMIC_INIT(1), -@@ -1031,6 +1045,7 @@ static const int fib6_prop[RTN_MAX + 1] - [RTN_BLACKHOLE] = -EINVAL, - [RTN_UNREACHABLE] = -EHOSTUNREACH, - [RTN_PROHIBIT] = -EACCES, -+ [RTN_POLICY_FAILED] = -EACCES, - [RTN_THROW] = -EAGAIN, - [RTN_NAT] = -EINVAL, - [RTN_XRESOLVE] = -EINVAL, -@@ -1066,6 +1081,10 @@ static void ip6_rt_init_dst_reject(struc - rt->dst.output = ip6_pkt_prohibit_out; - rt->dst.input = ip6_pkt_prohibit; - break; -+ case RTN_POLICY_FAILED: -+ rt->dst.output = ip6_pkt_policy_failed_out; -+ rt->dst.input = ip6_pkt_policy_failed; -+ break; - case RTN_THROW: - case RTN_UNREACHABLE: - default: -@@ -4449,6 +4468,17 @@ static int ip6_pkt_prohibit_out(struct n - return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES); - } - -+static int ip6_pkt_policy_failed(struct sk_buff *skb) -+{ -+ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_INNOROUTES); -+} -+ -+static int ip6_pkt_policy_failed_out(struct net *net, struct sock *sk, struct sk_buff *skb) -+{ -+ skb->dev = skb_dst(skb)->dev; -+ return ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_OUTNOROUTES); -+} -+ - /* - * Allocate a dst for local (unicast / anycast) address. - */ -@@ -4936,7 +4966,8 @@ static int rtm_to_fib6_config(struct sk_ - if (rtm->rtm_type == RTN_UNREACHABLE || - rtm->rtm_type == RTN_BLACKHOLE || - rtm->rtm_type == RTN_PROHIBIT || -- rtm->rtm_type == RTN_THROW) -+ rtm->rtm_type == RTN_THROW || -+ rtm->rtm_type == RTN_POLICY_FAILED) - cfg->fc_flags |= RTF_REJECT; - - if (rtm->rtm_type == RTN_LOCAL) -@@ -6136,6 +6167,8 @@ static int ip6_route_dev_notify(struct n - #ifdef CONFIG_IPV6_MULTIPLE_TABLES - net->ipv6.ip6_prohibit_entry->dst.dev = dev; - net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev); -+ net->ipv6.ip6_policy_failed_entry->dst.dev = dev; -+ net->ipv6.ip6_policy_failed_entry->rt6i_idev = in6_dev_get(dev); - net->ipv6.ip6_blk_hole_entry->dst.dev = dev; - net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev); - #endif -@@ -6147,6 +6180,7 @@ static int ip6_route_dev_notify(struct n - in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev); - #ifdef CONFIG_IPV6_MULTIPLE_TABLES - in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev); -+ in6_dev_put_clear(&net->ipv6.ip6_policy_failed_entry->rt6i_idev); - in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev); - #endif - } -@@ -6338,6 +6372,8 @@ static int __net_init ip6_route_net_init - - #ifdef CONFIG_IPV6_MULTIPLE_TABLES - net->ipv6.fib6_has_custom_rules = false; -+ -+ - net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template, - sizeof(*net->ipv6.ip6_prohibit_entry), - GFP_KERNEL); -@@ -6348,11 +6384,21 @@ static int __net_init ip6_route_net_init - ip6_template_metrics, true); - INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached); - -+ net->ipv6.ip6_policy_failed_entry = -+ kmemdup(&ip6_policy_failed_entry_template, -+ sizeof(*net->ipv6.ip6_policy_failed_entry), GFP_KERNEL); -+ if (!net->ipv6.ip6_policy_failed_entry) -+ goto out_ip6_prohibit_entry; -+ net->ipv6.ip6_policy_failed_entry->dst.ops = &net->ipv6.ip6_dst_ops; -+ dst_init_metrics(&net->ipv6.ip6_policy_failed_entry->dst, -+ ip6_template_metrics, true); -+ INIT_LIST_HEAD(&net->ipv6.ip6_policy_failed_entry->rt6i_uncached); -+ - net->ipv6.ip6_blk_hole_entry = kmemdup(&ip6_blk_hole_entry_template, - sizeof(*net->ipv6.ip6_blk_hole_entry), - GFP_KERNEL); - if (!net->ipv6.ip6_blk_hole_entry) -- goto out_ip6_prohibit_entry; -+ goto out_ip6_policy_failed_entry; - net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops; - dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst, - ip6_template_metrics, true); -@@ -6379,6 +6425,8 @@ out: - return ret; - - #ifdef CONFIG_IPV6_MULTIPLE_TABLES -+out_ip6_policy_failed_entry: -+ kfree(net->ipv6.ip6_policy_failed_entry); - out_ip6_prohibit_entry: - kfree(net->ipv6.ip6_prohibit_entry); - out_ip6_null_entry: -@@ -6398,6 +6446,7 @@ static void __net_exit ip6_route_net_exi - kfree(net->ipv6.ip6_null_entry); - #ifdef CONFIG_IPV6_MULTIPLE_TABLES - kfree(net->ipv6.ip6_prohibit_entry); -+ kfree(net->ipv6.ip6_policy_failed_entry); - kfree(net->ipv6.ip6_blk_hole_entry); - #endif - dst_entries_destroy(&net->ipv6.ip6_dst_ops); -@@ -6481,6 +6530,9 @@ void __init ip6_route_init_special_entri - init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); - init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev; - init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev); -+ init_net.ipv6.ip6_policy_failed_entry->dst.dev = init_net.loopback_dev; -+ init_net.ipv6.ip6_policy_failed_entry->rt6i_idev = -+ in6_dev_get(init_net.loopback_dev); - #endif - } - diff --git a/target/linux/generic/pending-5.10/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch b/target/linux/generic/pending-5.10/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch deleted file mode 100644 index 0e7f35db89..0000000000 --- a/target/linux/generic/pending-5.10/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch +++ /dev/null @@ -1,50 +0,0 @@ -From: Jonas Gorski -Subject: net: provide defines for _POLICY_FAILED until all code is updated - -Upstream introduced ICMPV6_POLICY_FAIL for code 5 of destination -unreachable, conflicting with our name. - -Add appropriate defines to allow our code to build with the new -name until we have updated our local patches for older kernels -and userspace packages. - -Signed-off-by: Jonas Gorski ---- - include/uapi/linux/fib_rules.h | 2 ++ - include/uapi/linux/icmpv6.h | 2 ++ - include/uapi/linux/rtnetlink.h | 2 ++ - 3 files changed, 6 insertions(+) - ---- a/include/uapi/linux/fib_rules.h -+++ b/include/uapi/linux/fib_rules.h -@@ -89,6 +89,8 @@ enum { - __FR_ACT_MAX, - }; - -+#define FR_ACT_FAILED_POLICY FR_ACT_POLICY_FAILED -+ - #define FR_ACT_MAX (__FR_ACT_MAX - 1) - - #endif ---- a/include/uapi/linux/icmpv6.h -+++ b/include/uapi/linux/icmpv6.h -@@ -126,6 +126,8 @@ struct icmp6hdr { - #define ICMPV6_POLICY_FAIL 5 - #define ICMPV6_REJECT_ROUTE 6 - -+#define ICMPV6_FAILED_POLICY ICMPV6_POLICY_FAIL -+ - /* - * Codes for Time Exceeded - */ ---- a/include/uapi/linux/rtnetlink.h -+++ b/include/uapi/linux/rtnetlink.h -@@ -253,6 +253,8 @@ enum { - __RTN_MAX - }; - -+#define RTN_FAILED_POLICY RTN_POLICY_FAILED -+ - #define RTN_MAX (__RTN_MAX - 1) - - diff --git a/target/linux/generic/pending-5.10/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-5.10/680-NET-skip-GRO-for-foreign-MAC-addresses.patch deleted file mode 100644 index d948848cc6..0000000000 --- a/target/linux/generic/pending-5.10/680-NET-skip-GRO-for-foreign-MAC-addresses.patch +++ /dev/null @@ -1,149 +0,0 @@ -From: Felix Fietkau -Subject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses - -Signed-off-by: Felix Fietkau ---- - include/linux/netdevice.h | 2 ++ - include/linux/skbuff.h | 3 ++- - net/core/dev.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++ - net/ethernet/eth.c | 18 +++++++++++++++++- - 4 files changed, 69 insertions(+), 2 deletions(-) - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -2059,6 +2059,8 @@ struct net_device { - struct netdev_hw_addr_list mc; - struct netdev_hw_addr_list dev_addrs; - -+ unsigned char local_addr_mask[MAX_ADDR_LEN]; -+ - #ifdef CONFIG_SYSFS - struct kset *queues_kset; - #endif ---- a/include/linux/skbuff.h -+++ b/include/linux/skbuff.h -@@ -864,6 +864,7 @@ struct sk_buff { - __u8 decrypted:1; - #endif - __u8 scm_io_uring:1; -+ __u8 gro_skip:1; - - #ifdef CONFIG_NET_SCHED - __u16 tc_index; /* traffic control index */ ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -6069,6 +6069,9 @@ static enum gro_result dev_gro_receive(s - int same_flow; - int grow; - -+ if (skb->gro_skip) -+ goto normal; -+ - if (netif_elide_gro(skb->dev)) - goto normal; - -@@ -8048,6 +8051,48 @@ static void __netdev_adjacent_dev_unlink - &upper_dev->adj_list.lower); - } - -+static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr, -+ struct net_device *dev) -+{ -+ int i; -+ -+ for (i = 0; i < dev->addr_len; i++) -+ mask[i] |= addr[i] ^ dev->dev_addr[i]; -+} -+ -+static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev, -+ struct net_device *lower) -+{ -+ struct net_device *cur; -+ struct list_head *iter; -+ -+ netdev_for_each_upper_dev_rcu(dev, cur, iter) { -+ __netdev_addr_mask(mask, cur->dev_addr, lower); -+ __netdev_upper_mask(mask, cur, lower); -+ } -+} -+ -+static void __netdev_update_addr_mask(struct net_device *dev) -+{ -+ unsigned char mask[MAX_ADDR_LEN]; -+ struct net_device *cur; -+ struct list_head *iter; -+ -+ memset(mask, 0, sizeof(mask)); -+ __netdev_upper_mask(mask, dev, dev); -+ memcpy(dev->local_addr_mask, mask, dev->addr_len); -+ -+ netdev_for_each_lower_dev(dev, cur, iter) -+ __netdev_update_addr_mask(cur); -+} -+ -+static void netdev_update_addr_mask(struct net_device *dev) -+{ -+ rcu_read_lock(); -+ __netdev_update_addr_mask(dev); -+ rcu_read_unlock(); -+} -+ - static int __netdev_upper_dev_link(struct net_device *dev, - struct net_device *upper_dev, bool master, - void *upper_priv, void *upper_info, -@@ -8099,6 +8144,7 @@ static int __netdev_upper_dev_link(struc - if (ret) - return ret; - -+ netdev_update_addr_mask(dev); - ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, - &changeupper_info.info); - ret = notifier_to_errno(ret); -@@ -8195,6 +8241,7 @@ static void __netdev_upper_dev_unlink(st - - __netdev_adjacent_dev_unlink_neighbour(dev, upper_dev); - -+ netdev_update_addr_mask(dev); - call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, - &changeupper_info.info); - -@@ -8981,6 +9028,7 @@ int dev_set_mac_address(struct net_devic - if (err) - return err; - dev->addr_assign_type = NET_ADDR_SET; -+ netdev_update_addr_mask(dev); - call_netdevice_notifiers(NETDEV_CHANGEADDR, dev); - add_device_randomness(dev->dev_addr, dev->addr_len); - return 0; ---- a/net/ethernet/eth.c -+++ b/net/ethernet/eth.c -@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev - } - EXPORT_SYMBOL(eth_get_headlen); - -+static inline bool -+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask) -+{ -+ const u16 *a1 = addr1; -+ const u16 *a2 = addr2; -+ const u16 *m = mask; -+ -+ return (((a1[0] ^ a2[0]) & ~m[0]) | -+ ((a1[1] ^ a2[1]) & ~m[1]) | -+ ((a1[2] ^ a2[2]) & ~m[2])); -+} -+ - /** - * eth_type_trans - determine the packet's protocol ID. - * @skb: received socket data -@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk - } else { - skb->pkt_type = PACKET_OTHERHOST; - } -+ -+ if (eth_check_local_mask(eth->h_dest, dev->dev_addr, -+ dev->local_addr_mask)) -+ skb->gro_skip = 1; - } - - /* diff --git a/target/linux/generic/pending-5.10/682-of_net-add-mac-address-increment-support.patch b/target/linux/generic/pending-5.10/682-of_net-add-mac-address-increment-support.patch deleted file mode 100644 index 82e81f37c5..0000000000 --- a/target/linux/generic/pending-5.10/682-of_net-add-mac-address-increment-support.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 844c273286f328acf0dab5fbd5d864366b4904dc Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 30 Mar 2021 18:21:14 +0200 -Subject: [PATCH] of_net: add mac-address-increment support - -Lots of embedded devices use the mac-address of other interface -extracted from nvmem cells and increments it by one or two. Add two -bindings to integrate this and directly use the right mac-address for -the interface. Some example are some routers that use the gmac -mac-address stored in the art partition and increments it by one for the -wifi. mac-address-increment-byte bindings is used to tell what byte of -the mac-address has to be increased (if not defined the last byte is -increased) and mac-address-increment tells how much the byte decided -early has to be increased. - -Signed-off-by: Ansuel Smith ---- - drivers/of/of_net.c | 43 +++++++++++++++++++++++++++++++++++++++---- - 1 file changed, 39 insertions(+), 4 deletions(-) - ---- a/drivers/of/of_net.c -+++ b/drivers/of/of_net.c -@@ -115,27 +115,62 @@ static int of_get_mac_addr_nvmem(struct - * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists - * but is all zeros. - * -+ * DT can tell the system to increment the mac-address after is extracted by -+ * using: -+ * - mac-address-increment-byte to decide what byte to increase -+ * (if not defined is increased the last byte) -+ * - mac-address-increment to decide how much to increase. The value WILL -+ * overflow to other bytes if the increment is over 255 or the total -+ * increment will exceed 255 of the current byte. -+ * (example 00:01:02:03:04:ff + 1 == 00:01:02:03:05:00) -+ * (example 00:01:02:03:04:fe + 5 == 00:01:02:03:05:03) -+ * - * Return: 0 on success and errno in case of error. - */ - int of_get_mac_address(struct device_node *np, u8 *addr) - { -+ u32 inc_idx, mac_inc, mac_val; - int ret; - -+ /* Check first if the increment byte is present and valid. -+ * If not set assume to increment the last byte if found. -+ */ -+ if (of_property_read_u32(np, "mac-address-increment-byte", &inc_idx)) -+ inc_idx = 5; -+ if (inc_idx < 3 || inc_idx > 5) -+ return -EINVAL; -+ - if (!np) - return -ENODEV; - - ret = of_get_mac_addr(np, "mac-address", addr); - if (!ret) -- return 0; -+ goto found; - - ret = of_get_mac_addr(np, "local-mac-address", addr); - if (!ret) -- return 0; -+ goto found; - - ret = of_get_mac_addr(np, "address", addr); - if (!ret) -- return 0; -+ goto found; -+ -+ ret = of_get_mac_addr_nvmem(np, addr); -+ if (ret) -+ return ret; -+ -+found: -+ if (!of_property_read_u32(np, "mac-address-increment", &mac_inc)) { -+ /* Convert to a contiguous value */ -+ mac_val = (addr[3] << 16) + (addr[4] << 8) + addr[5]; -+ mac_val += mac_inc << 8 * (5-inc_idx); -+ -+ /* Apply the incremented value handling overflow case */ -+ addr[3] = (mac_val >> 16) & 0xff; -+ addr[4] = (mac_val >> 8) & 0xff; -+ addr[5] = (mac_val >> 0) & 0xff; -+ } - -- return of_get_mac_addr_nvmem(np, addr); -+ return ret; - } - EXPORT_SYMBOL(of_get_mac_address); diff --git a/target/linux/generic/pending-5.10/683-of_net-add-mac-address-to-of-tree.patch b/target/linux/generic/pending-5.10/683-of_net-add-mac-address-to-of-tree.patch deleted file mode 100644 index 501422551b..0000000000 --- a/target/linux/generic/pending-5.10/683-of_net-add-mac-address-to-of-tree.patch +++ /dev/null @@ -1,54 +0,0 @@ -From: David Bauer -Subject: of/net: Add MAC address to of tree - -The label-mac logic relies on the mac-address property of a netdev -devices of-node. However, the mac address can also be stored as a -different property or read from e.g. an mtd device. - -Create this node when reading a mac-address from OF if it does not -already exist and copy the mac-address used for the device to this -property. This way, the MAC address can be accessed using procfs. - -Submitted-by: David Bauer ---- - drivers/of/of_net.c | 22 ++++++++++++++ - 1 files changed, 22 insertions(+) - ---- a/drivers/of/of_net.c -+++ b/drivers/of/of_net.c -@@ -95,6 +95,27 @@ static int of_get_mac_addr_nvmem(struct - return 0; - } - -+static int of_add_mac_address(struct device_node *np, u8* addr) -+{ -+ struct property *prop; -+ -+ prop = kzalloc(sizeof(*prop), GFP_KERNEL); -+ if (!prop) -+ return -ENOMEM; -+ -+ prop->name = "mac-address"; -+ prop->length = ETH_ALEN; -+ prop->value = kmemdup(addr, ETH_ALEN, GFP_KERNEL); -+ if (!prop->value || of_update_property(np, prop)) -+ goto free; -+ -+ return 0; -+free: -+ kfree(prop->value); -+ kfree(prop); -+ return -ENOMEM; -+} -+ - /** - * Search the device tree for the best MAC address to use. 'mac-address' is - * checked first, because that is supposed to contain to "most recent" MAC -@@ -171,6 +192,7 @@ found: - addr[5] = (mac_val >> 0) & 0xff; - } - -+ of_add_mac_address(np, addr); - return ret; - } - EXPORT_SYMBOL(of_get_mac_address); diff --git a/target/linux/generic/pending-5.10/684-of_net-do-mac-address-increment-only-once.patch b/target/linux/generic/pending-5.10/684-of_net-do-mac-address-increment-only-once.patch deleted file mode 100644 index b1c5d9112a..0000000000 --- a/target/linux/generic/pending-5.10/684-of_net-do-mac-address-increment-only-once.patch +++ /dev/null @@ -1,31 +0,0 @@ -From dd07dd394d8bfdb5d527fab18ca54f20815ec4e4 Mon Sep 17 00:00:00 2001 -From: Will Moss -Date: Wed, 3 Aug 2022 13:48:55 +0000 -Subject: [PATCH] of_net: do mac-address-increment only once - -Remove mac-address-increment and mac-address-increment-byte -DT property after incrementing process to make sure MAC address -would not get incremented more if this function is stared again. -It could happen if device initialization is deferred after -unsuccessful attempt. - -Signed-off-by: Will Moss ---- - drivers/of/of_net.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/of/of_net.c -+++ b/drivers/of/of_net.c -@@ -190,6 +190,12 @@ found: - addr[3] = (mac_val >> 16) & 0xff; - addr[4] = (mac_val >> 8) & 0xff; - addr[5] = (mac_val >> 0) & 0xff; -+ -+ /* Remove mac-address-increment and mac-address-increment-byte -+ * DT property to make sure MAC address would not get incremented -+ * more if this function is stared again. */ -+ of_remove_property(np, of_find_property(np, "mac-address-increment", NULL)); -+ of_remove_property(np, of_find_property(np, "mac-address-increment-byte", NULL)); - } - - of_add_mac_address(np, addr); diff --git a/target/linux/generic/pending-5.10/700-net-ethernet-mtk_eth_soc-avoid-creating-duplicate-of.patch b/target/linux/generic/pending-5.10/700-net-ethernet-mtk_eth_soc-avoid-creating-duplicate-of.patch deleted file mode 100644 index ff090f07f1..0000000000 --- a/target/linux/generic/pending-5.10/700-net-ethernet-mtk_eth_soc-avoid-creating-duplicate-of.patch +++ /dev/null @@ -1,26 +0,0 @@ -From: Felix Fietkau -Date: Thu, 8 Jul 2021 07:08:29 +0200 -Subject: [PATCH] net: ethernet: mtk_eth_soc: avoid creating duplicate offload - entries - -Sometimes multiple CLS_REPLACE calls are issued for the same connection. -rhashtable_insert_fast does not check for these duplicates, so multiple -hardware flow entries can be created. -Fix this by checking for an existing entry early - -Fixes: 502e84e2382d ("net: ethernet: mtk_eth_soc: add flow offloading support") -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -187,6 +187,9 @@ mtk_flow_offload_replace(struct mtk_eth - int hash; - int i; - -+ if (rhashtable_lookup(ð->flow_table, &f->cookie, mtk_flow_ht_params)) -+ return -EEXIST; -+ - if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META)) { - struct flow_match_meta match; - diff --git a/target/linux/generic/pending-5.10/701-00-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch b/target/linux/generic/pending-5.10/701-00-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch deleted file mode 100644 index c7bb6c5e10..0000000000 --- a/target/linux/generic/pending-5.10/701-00-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch +++ /dev/null @@ -1,327 +0,0 @@ -From: Felix Fietkau -Date: Sat, 5 Feb 2022 17:59:07 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for coherent - DMA - -It improves performance by eliminating the need for a cache flush on rx and tx -In preparation for supporting WED (Wireless Ethernet Dispatch), also add a -function for disabling coherent DMA at runtime. - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -9,6 +9,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -833,7 +834,7 @@ static int mtk_init_fq_dma(struct mtk_et - dma_addr_t dma_addr; - int i; - -- eth->scratch_ring = dma_alloc_coherent(eth->dev, -+ eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, - cnt * sizeof(struct mtk_tx_dma), - ð->phy_scratch_ring, - GFP_ATOMIC); -@@ -845,10 +846,10 @@ static int mtk_init_fq_dma(struct mtk_et - if (unlikely(!eth->scratch_head)) - return -ENOMEM; - -- dma_addr = dma_map_single(eth->dev, -+ dma_addr = dma_map_single(eth->dma_dev, - eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, - DMA_FROM_DEVICE); -- if (unlikely(dma_mapping_error(eth->dev, dma_addr))) -+ if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) - return -ENOMEM; - - phy_ring_tail = eth->phy_scratch_ring + -@@ -902,26 +903,26 @@ static void mtk_tx_unmap(struct mtk_eth - { - if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { - if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { -- dma_unmap_single(eth->dev, -+ dma_unmap_single(eth->dma_dev, - dma_unmap_addr(tx_buf, dma_addr0), - dma_unmap_len(tx_buf, dma_len0), - DMA_TO_DEVICE); - } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { -- dma_unmap_page(eth->dev, -+ dma_unmap_page(eth->dma_dev, - dma_unmap_addr(tx_buf, dma_addr0), - dma_unmap_len(tx_buf, dma_len0), - DMA_TO_DEVICE); - } - } else { - if (dma_unmap_len(tx_buf, dma_len0)) { -- dma_unmap_page(eth->dev, -+ dma_unmap_page(eth->dma_dev, - dma_unmap_addr(tx_buf, dma_addr0), - dma_unmap_len(tx_buf, dma_len0), - DMA_TO_DEVICE); - } - - if (dma_unmap_len(tx_buf, dma_len1)) { -- dma_unmap_page(eth->dev, -+ dma_unmap_page(eth->dma_dev, - dma_unmap_addr(tx_buf, dma_addr1), - dma_unmap_len(tx_buf, dma_len1), - DMA_TO_DEVICE); -@@ -999,9 +1000,9 @@ static int mtk_tx_map(struct sk_buff *sk - if (skb_vlan_tag_present(skb)) - txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); - -- mapped_addr = dma_map_single(eth->dev, skb->data, -+ mapped_addr = dma_map_single(eth->dma_dev, skb->data, - skb_headlen(skb), DMA_TO_DEVICE); -- if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) -+ if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr))) - return -ENOMEM; - - WRITE_ONCE(itxd->txd1, mapped_addr); -@@ -1040,10 +1041,10 @@ static int mtk_tx_map(struct sk_buff *sk - - - frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); -- mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, -+ mapped_addr = skb_frag_dma_map(eth->dma_dev, frag, offset, - frag_map_size, - DMA_TO_DEVICE); -- if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) -+ if (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr))) - goto err_dma; - - if (i == nr_frags - 1 && -@@ -1324,18 +1325,18 @@ static int mtk_poll_rx(struct napi_struc - netdev->stats.rx_dropped++; - goto release_desc; - } -- dma_addr = dma_map_single(eth->dev, -+ dma_addr = dma_map_single(eth->dma_dev, - new_data + NET_SKB_PAD + - eth->ip_align, - ring->buf_size, - DMA_FROM_DEVICE); -- if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { -+ if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) { - skb_free_frag(new_data); - netdev->stats.rx_dropped++; - goto release_desc; - } - -- dma_unmap_single(eth->dev, trxd.rxd1, -+ dma_unmap_single(eth->dma_dev, trxd.rxd1, - ring->buf_size, DMA_FROM_DEVICE); - - /* receive data */ -@@ -1608,7 +1609,7 @@ static int mtk_tx_alloc(struct mtk_eth * - if (!ring->buf) - goto no_tx_mem; - -- ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, -+ ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, - &ring->phys, GFP_ATOMIC); - if (!ring->dma) - goto no_tx_mem; -@@ -1626,7 +1627,7 @@ static int mtk_tx_alloc(struct mtk_eth * - * descriptors in ring->dma_pdma. - */ - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { -- ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, -+ ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, - &ring->phys_pdma, - GFP_ATOMIC); - if (!ring->dma_pdma) -@@ -1685,7 +1686,7 @@ static void mtk_tx_clean(struct mtk_eth - } - - if (ring->dma) { -- dma_free_coherent(eth->dev, -+ dma_free_coherent(eth->dma_dev, - MTK_DMA_SIZE * sizeof(*ring->dma), - ring->dma, - ring->phys); -@@ -1693,7 +1694,7 @@ static void mtk_tx_clean(struct mtk_eth - } - - if (ring->dma_pdma) { -- dma_free_coherent(eth->dev, -+ dma_free_coherent(eth->dma_dev, - MTK_DMA_SIZE * sizeof(*ring->dma_pdma), - ring->dma_pdma, - ring->phys_pdma); -@@ -1741,18 +1742,18 @@ static int mtk_rx_alloc(struct mtk_eth * - return -ENOMEM; - } - -- ring->dma = dma_alloc_coherent(eth->dev, -+ ring->dma = dma_alloc_coherent(eth->dma_dev, - rx_dma_size * sizeof(*ring->dma), - &ring->phys, GFP_ATOMIC); - if (!ring->dma) - return -ENOMEM; - - for (i = 0; i < rx_dma_size; i++) { -- dma_addr_t dma_addr = dma_map_single(eth->dev, -+ dma_addr_t dma_addr = dma_map_single(eth->dma_dev, - ring->data[i] + NET_SKB_PAD + eth->ip_align, - ring->buf_size, - DMA_FROM_DEVICE); -- if (unlikely(dma_mapping_error(eth->dev, dma_addr))) -+ if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) - return -ENOMEM; - ring->dma[i].rxd1 = (unsigned int)dma_addr; - -@@ -1788,7 +1789,7 @@ static void mtk_rx_clean(struct mtk_eth - continue; - if (!ring->dma[i].rxd1) - continue; -- dma_unmap_single(eth->dev, -+ dma_unmap_single(eth->dma_dev, - ring->dma[i].rxd1, - ring->buf_size, - DMA_FROM_DEVICE); -@@ -1799,7 +1800,7 @@ static void mtk_rx_clean(struct mtk_eth - } - - if (ring->dma) { -- dma_free_coherent(eth->dev, -+ dma_free_coherent(eth->dma_dev, - ring->dma_size * sizeof(*ring->dma), - ring->dma, - ring->phys); -@@ -2155,7 +2156,7 @@ static void mtk_dma_free(struct mtk_eth - if (eth->netdev[i]) - netdev_reset_queue(eth->netdev[i]); - if (eth->scratch_ring) { -- dma_free_coherent(eth->dev, -+ dma_free_coherent(eth->dma_dev, - MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), - eth->scratch_ring, - eth->phy_scratch_ring); -@@ -2507,6 +2508,8 @@ static void mtk_dim_tx(struct work_struc - - static int mtk_hw_init(struct mtk_eth *eth) - { -+ u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | -+ ETHSYS_DMA_AG_MAP_PPE; - int i, val, ret; - - if (test_and_set_bit(MTK_HW_INIT, ð->state)) -@@ -2519,6 +2522,10 @@ static int mtk_hw_init(struct mtk_eth *e - if (ret) - goto err_disable_pm; - -+ if (eth->ethsys) -+ regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, -+ of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); -+ - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { - ret = device_reset(eth->dev); - if (ret) { -@@ -3068,6 +3075,35 @@ free_netdev: - return err; - } - -+void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) -+{ -+ struct net_device *dev, *tmp; -+ LIST_HEAD(dev_list); -+ int i; -+ -+ rtnl_lock(); -+ -+ for (i = 0; i < MTK_MAC_COUNT; i++) { -+ dev = eth->netdev[i]; -+ -+ if (!dev || !(dev->flags & IFF_UP)) -+ continue; -+ -+ list_add_tail(&dev->close_list, &dev_list); -+ } -+ -+ dev_close_many(&dev_list, false); -+ -+ eth->dma_dev = dma_dev; -+ -+ list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { -+ list_del_init(&dev->close_list); -+ dev_open(dev, NULL); -+ } -+ -+ rtnl_unlock(); -+} -+ - static int mtk_probe(struct platform_device *pdev) - { - struct device_node *mac_np; -@@ -3081,6 +3117,7 @@ static int mtk_probe(struct platform_dev - eth->soc = of_device_get_match_data(&pdev->dev); - - eth->dev = &pdev->dev; -+ eth->dma_dev = &pdev->dev; - eth->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(eth->base)) - return PTR_ERR(eth->base); -@@ -3129,6 +3166,16 @@ static int mtk_probe(struct platform_dev - } - } - -+ if (of_dma_is_coherent(pdev->dev.of_node)) { -+ struct regmap *cci; -+ -+ cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, -+ "mediatek,cci-control"); -+ /* enable CPU/bus coherency */ -+ if (!IS_ERR(cci)) -+ regmap_write(cci, 0, 3); -+ } -+ - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { - eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), - GFP_KERNEL); ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -457,6 +457,12 @@ - #define RSTCTRL_FE BIT(6) - #define RSTCTRL_PPE BIT(31) - -+/* ethernet dma channel agent map */ -+#define ETHSYS_DMA_AG_MAP 0x408 -+#define ETHSYS_DMA_AG_MAP_PDMA BIT(0) -+#define ETHSYS_DMA_AG_MAP_QDMA BIT(1) -+#define ETHSYS_DMA_AG_MAP_PPE BIT(2) -+ - /* SGMII subsystem config registers */ - /* Register to auto-negotiation restart */ - #define SGMSYS_PCS_CONTROL_1 0x0 -@@ -874,6 +880,7 @@ struct mtk_sgmii { - /* struct mtk_eth - This is the main datasructure for holding the state - * of the driver - * @dev: The device pointer -+ * @dev: The device pointer used for dma mapping/alloc - * @base: The mapped register i/o base - * @page_lock: Make sure that register operations are atomic - * @tx_irq__lock: Make sure that IRQ register operations are atomic -@@ -917,6 +924,7 @@ struct mtk_sgmii { - - struct mtk_eth { - struct device *dev; -+ struct device *dma_dev; - void __iomem *base; - spinlock_t page_lock; - spinlock_t tx_irq_lock; -@@ -1015,6 +1023,7 @@ int mtk_gmac_rgmii_path_setup(struct mtk - int mtk_eth_offload_init(struct mtk_eth *eth); - int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, - void *type_data); -+void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); - - - #endif /* MTK_ETH_H */ diff --git a/target/linux/generic/pending-5.10/701-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch b/target/linux/generic/pending-5.10/701-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch deleted file mode 100644 index d9015d4805..0000000000 --- a/target/linux/generic/pending-5.10/701-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: Felix Fietkau -Date: Mon, 7 Feb 2022 10:27:22 +0100 -Subject: [PATCH] arm64: dts: mediatek: mt7622: add support for coherent - DMA - -It improves performance by eliminating the need for a cache flush on rx and tx - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -357,7 +357,7 @@ - }; - - cci_control2: slave-if@5000 { -- compatible = "arm,cci-400-ctrl-if"; -+ compatible = "arm,cci-400-ctrl-if", "syscon"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; -@@ -937,6 +937,8 @@ - power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys>; -+ mediatek,cci-control = <&cci_control2>; -+ dma-coherent; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; diff --git a/target/linux/generic/pending-5.10/701-02-net-ethernet-mtk_eth_soc-add-support-for-Wireless-Et.patch b/target/linux/generic/pending-5.10/701-02-net-ethernet-mtk_eth_soc-add-support-for-Wireless-Et.patch deleted file mode 100644 index cd4adb94fd..0000000000 --- a/target/linux/generic/pending-5.10/701-02-net-ethernet-mtk_eth_soc-add-support-for-Wireless-Et.patch +++ /dev/null @@ -1,1679 +0,0 @@ -From: Felix Fietkau -Date: Sat, 5 Feb 2022 17:56:08 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for Wireless - Ethernet Dispatch (WED) - -The Wireless Ethernet Dispatch subsystem on the MT7622 SoC can be -configured to intercept and handle access to the DMA queues and -PCIe interrupts for a MT7615/MT7915 wireless card. -It can manage the internal WDMA (Wireless DMA) controller, which allows -ethernet packets to be passed from the packet switch engine (PSE) to the -wireless card, bypassing the CPU entirely. -This can be used to implement hardware flow offloading from ethernet to -WLAN. - -Signed-off-by: Felix Fietkau ---- - create mode 100644 drivers/net/ethernet/mediatek/mtk_wed.c - create mode 100644 drivers/net/ethernet/mediatek/mtk_wed.h - create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_debugfs.c - create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_ops.c - create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_regs.h - create mode 100644 include/linux/soc/mediatek/mtk_wed.h - ---- a/drivers/net/ethernet/mediatek/Kconfig -+++ b/drivers/net/ethernet/mediatek/Kconfig -@@ -7,6 +7,10 @@ config NET_VENDOR_MEDIATEK - - if NET_VENDOR_MEDIATEK - -+config NET_MEDIATEK_SOC_WED -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ def_bool NET_MEDIATEK_SOC != n -+ - config NET_MEDIATEK_SOC - tristate "MediaTek SoC Gigabit Ethernet support" - select PHYLINK ---- a/drivers/net/ethernet/mediatek/Makefile -+++ b/drivers/net/ethernet/mediatek/Makefile -@@ -5,4 +5,9 @@ - - obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o - mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o -+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o -+ifdef CONFIG_DEBUG_FS -+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o -+endif -+obj-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_ops.o - obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -24,6 +24,7 @@ - #include - - #include "mtk_eth_soc.h" -+#include "mtk_wed.h" - - static int mtk_msg_level = -1; - module_param_named(msg_level, mtk_msg_level, int, 0); -@@ -3198,6 +3199,22 @@ static int mtk_probe(struct platform_dev - } - } - -+ for (i = 0;; i++) { -+ struct device_node *np = of_parse_phandle(pdev->dev.of_node, -+ "mediatek,wed", i); -+ static const u32 wdma_regs[] = { -+ MTK_WDMA0_BASE, -+ MTK_WDMA1_BASE -+ }; -+ void __iomem *wdma; -+ -+ if (!np || i >= ARRAY_SIZE(wdma_regs)) -+ break; -+ -+ wdma = eth->base + wdma_regs[i]; -+ mtk_wed_add_hw(np, eth, wdma, i); -+ } -+ - for (i = 0; i < 3; i++) { - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) - eth->irq[i] = eth->irq[0]; ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -295,6 +295,9 @@ - #define MTK_GDM1_TX_GPCNT 0x2438 - #define MTK_STAT_OFFSET 0x40 - -+#define MTK_WDMA0_BASE 0x2800 -+#define MTK_WDMA1_BASE 0x2c00 -+ - /* QDMA descriptor txd4 */ - #define TX_DMA_CHKSUM (0x7 << 29) - #define TX_DMA_TSO BIT(28) ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -0,0 +1,875 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (C) 2021 Felix Fietkau */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mtk_eth_soc.h" -+#include "mtk_wed_regs.h" -+#include "mtk_wed.h" -+#include "mtk_ppe.h" -+ -+#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) -+ -+#define MTK_WED_PKT_SIZE 1900 -+#define MTK_WED_BUF_SIZE 2048 -+#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) -+ -+#define MTK_WED_TX_RING_SIZE 2048 -+#define MTK_WED_WDMA_RING_SIZE 1024 -+ -+static struct mtk_wed_hw *hw_list[2]; -+static DEFINE_MUTEX(hw_lock); -+ -+static void -+wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val) -+{ -+ regmap_update_bits(dev->hw->regs, reg, mask | val, val); -+} -+ -+static void -+wed_set(struct mtk_wed_device *dev, u32 reg, u32 mask) -+{ -+ return wed_m32(dev, reg, 0, mask); -+} -+ -+static void -+wed_clr(struct mtk_wed_device *dev, u32 reg, u32 mask) -+{ -+ return wed_m32(dev, reg, mask, 0); -+} -+ -+static void -+wdma_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val) -+{ -+ wdma_w32(dev, reg, (wdma_r32(dev, reg) & ~mask) | val); -+} -+ -+static void -+wdma_set(struct mtk_wed_device *dev, u32 reg, u32 mask) -+{ -+ wdma_m32(dev, reg, 0, mask); -+} -+ -+static u32 -+mtk_wed_read_reset(struct mtk_wed_device *dev) -+{ -+ return wed_r32(dev, MTK_WED_RESET); -+} -+ -+static void -+mtk_wed_reset(struct mtk_wed_device *dev, u32 mask) -+{ -+ u32 status; -+ -+ wed_w32(dev, MTK_WED_RESET, mask); -+ if (readx_poll_timeout(mtk_wed_read_reset, dev, status, -+ !(status & mask), 0, 1000)) -+ WARN_ON_ONCE(1); -+} -+ -+static struct mtk_wed_hw * -+mtk_wed_assign(struct mtk_wed_device *dev) -+{ -+ struct mtk_wed_hw *hw; -+ -+ hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)]; -+ if (!hw || hw->wed_dev) -+ return NULL; -+ -+ hw->wed_dev = dev; -+ return hw; -+} -+ -+static int -+mtk_wed_buffer_alloc(struct mtk_wed_device *dev) -+{ -+ struct mtk_wdma_desc *desc; -+ dma_addr_t desc_phys; -+ void **page_list; -+ int token = dev->wlan.token_start; -+ int ring_size; -+ int n_pages; -+ int i, page_idx; -+ -+ ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); -+ n_pages = ring_size / MTK_WED_BUF_PER_PAGE; -+ -+ page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL); -+ if (!page_list) -+ return -ENOMEM; -+ -+ dev->buf_ring.size = ring_size; -+ dev->buf_ring.pages = page_list; -+ -+ desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc), -+ &desc_phys, GFP_KERNEL); -+ if (!desc) -+ return -ENOMEM; -+ -+ dev->buf_ring.desc = desc; -+ dev->buf_ring.desc_phys = desc_phys; -+ -+ for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) { -+ dma_addr_t page_phys, buf_phys; -+ struct page *page; -+ void *buf; -+ int s; -+ -+ page = __dev_alloc_pages(GFP_KERNEL, 0); -+ if (!page) -+ return -ENOMEM; -+ -+ page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE, -+ DMA_BIDIRECTIONAL); -+ if (dma_mapping_error(dev->hw->dev, page_phys)) { -+ __free_page(page); -+ return -ENOMEM; -+ } -+ -+ page_list[page_idx++] = page; -+ dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE, -+ DMA_BIDIRECTIONAL); -+ -+ buf = page_to_virt(page); -+ buf_phys = page_phys; -+ -+ for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) { -+ u32 txd_size; -+ -+ txd_size = dev->wlan.init_buf(buf, buf_phys, token++); -+ -+ desc->buf0 = buf_phys; -+ desc->buf1 = buf_phys + txd_size; -+ desc->ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, -+ txd_size) | -+ FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1, -+ MTK_WED_BUF_SIZE - txd_size) | -+ MTK_WDMA_DESC_CTRL_LAST_SEG1; -+ desc->info = 0; -+ desc++; -+ -+ buf += MTK_WED_BUF_SIZE; -+ buf_phys += MTK_WED_BUF_SIZE; -+ } -+ -+ dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE, -+ DMA_BIDIRECTIONAL); -+ } -+ -+ return 0; -+} -+ -+static void -+mtk_wed_free_buffer(struct mtk_wed_device *dev) -+{ -+ struct mtk_wdma_desc *desc = dev->buf_ring.desc; -+ void **page_list = dev->buf_ring.pages; -+ int page_idx; -+ int i; -+ -+ if (!page_list) -+ return; -+ -+ if (!desc) -+ goto free_pagelist; -+ -+ for (i = 0, page_idx = 0; i < dev->buf_ring.size; i += MTK_WED_BUF_PER_PAGE) { -+ void *page = page_list[page_idx++]; -+ -+ if (!page) -+ break; -+ -+ dma_unmap_page(dev->hw->dev, desc[i].buf0, -+ PAGE_SIZE, DMA_BIDIRECTIONAL); -+ __free_page(page); -+ } -+ -+ dma_free_coherent(dev->hw->dev, dev->buf_ring.size * sizeof(*desc), -+ desc, dev->buf_ring.desc_phys); -+ -+free_pagelist: -+ kfree(page_list); -+} -+ -+static void -+mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring) -+{ -+ if (!ring->desc) -+ return; -+ -+ dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc), -+ ring->desc, ring->desc_phys); -+} -+ -+static void -+mtk_wed_free_tx_rings(struct mtk_wed_device *dev) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) -+ mtk_wed_free_ring(dev, &dev->tx_ring[i]); -+ for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) -+ mtk_wed_free_ring(dev, &dev->tx_wdma[i]); -+} -+ -+static void -+mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en) -+{ -+ u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK; -+ -+ if (!dev->hw->num_flows) -+ mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD; -+ -+ wed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0); -+ wed_r32(dev, MTK_WED_EXT_INT_MASK); -+} -+ -+static void -+mtk_wed_stop(struct mtk_wed_device *dev) -+{ -+ regmap_write(dev->hw->mirror, dev->hw->index * 4, 0); -+ mtk_wed_set_ext_int(dev, false); -+ -+ wed_clr(dev, MTK_WED_CTRL, -+ MTK_WED_CTRL_WDMA_INT_AGENT_EN | -+ MTK_WED_CTRL_WPDMA_INT_AGENT_EN | -+ MTK_WED_CTRL_WED_TX_BM_EN | -+ MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); -+ wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0); -+ wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0); -+ wdma_w32(dev, MTK_WDMA_INT_MASK, 0); -+ wdma_w32(dev, MTK_WDMA_INT_GRP2, 0); -+ wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0); -+ -+ wed_clr(dev, MTK_WED_GLO_CFG, -+ MTK_WED_GLO_CFG_TX_DMA_EN | -+ MTK_WED_GLO_CFG_RX_DMA_EN); -+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, -+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | -+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); -+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG, -+ MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); -+} -+ -+static void -+mtk_wed_detach(struct mtk_wed_device *dev) -+{ -+ struct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node; -+ struct mtk_wed_hw *hw = dev->hw; -+ -+ mutex_lock(&hw_lock); -+ -+ mtk_wed_stop(dev); -+ -+ wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX); -+ wdma_w32(dev, MTK_WDMA_RESET_IDX, 0); -+ -+ mtk_wed_reset(dev, MTK_WED_RESET_WED); -+ -+ mtk_wed_free_buffer(dev); -+ mtk_wed_free_tx_rings(dev); -+ -+ if (of_dma_is_coherent(wlan_node)) -+ regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, -+ BIT(hw->index), BIT(hw->index)); -+ -+ if (!hw_list[!hw->index]->wed_dev && -+ hw->eth->dma_dev != hw->eth->dev) -+ mtk_eth_set_dma_device(hw->eth, hw->eth->dev); -+ -+ memset(dev, 0, sizeof(*dev)); -+ module_put(THIS_MODULE); -+ -+ hw->wed_dev = NULL; -+ mutex_unlock(&hw_lock); -+} -+ -+static void -+mtk_wed_hw_init_early(struct mtk_wed_device *dev) -+{ -+ u32 mask, set; -+ u32 offset; -+ -+ mtk_wed_stop(dev); -+ mtk_wed_reset(dev, MTK_WED_RESET_WED); -+ -+ mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE | -+ MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE | -+ MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE; -+ set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) | -+ MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP | -+ MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY; -+ wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set); -+ -+ wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES); -+ -+ offset = dev->hw->index ? 0x04000400 : 0; -+ wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); -+ wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); -+ -+ wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index)); -+ wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); -+} -+ -+static void -+mtk_wed_hw_init(struct mtk_wed_device *dev) -+{ -+ if (dev->init_done) -+ return; -+ -+ dev->init_done = true; -+ mtk_wed_set_ext_int(dev, false); -+ wed_w32(dev, MTK_WED_TX_BM_CTRL, -+ MTK_WED_TX_BM_CTRL_PAUSE | -+ FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, -+ dev->buf_ring.size / 128) | -+ FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, -+ MTK_WED_TX_RING_SIZE / 256)); -+ -+ wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys); -+ -+ wed_w32(dev, MTK_WED_TX_BM_TKID, -+ FIELD_PREP(MTK_WED_TX_BM_TKID_START, -+ dev->wlan.token_start) | -+ FIELD_PREP(MTK_WED_TX_BM_TKID_END, -+ dev->wlan.token_start + dev->wlan.nbuf - 1)); -+ -+ wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE); -+ -+ wed_w32(dev, MTK_WED_TX_BM_DYN_THR, -+ FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) | -+ MTK_WED_TX_BM_DYN_THR_HI); -+ -+ mtk_wed_reset(dev, MTK_WED_RESET_TX_BM); -+ -+ wed_set(dev, MTK_WED_CTRL, -+ MTK_WED_CTRL_WED_TX_BM_EN | -+ MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); -+ -+ wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE); -+} -+ -+static void -+mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size) -+{ -+ int i; -+ -+ for (i = 0; i < size; i++) { -+ desc[i].buf0 = 0; -+ desc[i].ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE); -+ desc[i].buf1 = 0; -+ desc[i].info = 0; -+ } -+} -+ -+static u32 -+mtk_wed_check_busy(struct mtk_wed_device *dev) -+{ -+ if (wed_r32(dev, MTK_WED_GLO_CFG) & MTK_WED_GLO_CFG_TX_DMA_BUSY) -+ return true; -+ -+ if (wed_r32(dev, MTK_WED_WPDMA_GLO_CFG) & -+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY) -+ return true; -+ -+ if (wed_r32(dev, MTK_WED_CTRL) & MTK_WED_CTRL_WDMA_INT_AGENT_BUSY) -+ return true; -+ -+ if (wed_r32(dev, MTK_WED_WDMA_GLO_CFG) & -+ MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY) -+ return true; -+ -+ if (wdma_r32(dev, MTK_WDMA_GLO_CFG) & -+ MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY) -+ return true; -+ -+ if (wed_r32(dev, MTK_WED_CTRL) & -+ (MTK_WED_CTRL_WED_TX_BM_BUSY | MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY)) -+ return true; -+ -+ return false; -+} -+ -+static int -+mtk_wed_poll_busy(struct mtk_wed_device *dev) -+{ -+ int sleep = 15000; -+ int timeout = 100 * sleep; -+ u32 val; -+ -+ return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep, -+ timeout, false, dev); -+} -+ -+static void -+mtk_wed_reset_dma(struct mtk_wed_device *dev) -+{ -+ bool busy = false; -+ u32 val; -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) { -+ struct mtk_wdma_desc *desc = dev->tx_ring[i].desc; -+ -+ if (!desc) -+ continue; -+ -+ mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE); -+ } -+ -+ if (mtk_wed_poll_busy(dev)) -+ busy = mtk_wed_check_busy(dev); -+ -+ if (busy) { -+ mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA); -+ } else { -+ wed_w32(dev, MTK_WED_RESET_IDX, -+ MTK_WED_RESET_IDX_TX | -+ MTK_WED_RESET_IDX_RX); -+ wed_w32(dev, MTK_WED_RESET_IDX, 0); -+ } -+ -+ wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX); -+ wdma_w32(dev, MTK_WDMA_RESET_IDX, 0); -+ -+ if (busy) { -+ mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT); -+ mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV); -+ } else { -+ wed_w32(dev, MTK_WED_WDMA_RESET_IDX, -+ MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV); -+ wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0); -+ -+ wed_set(dev, MTK_WED_WDMA_GLO_CFG, -+ MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE); -+ -+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG, -+ MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE); -+ } -+ -+ for (i = 0; i < 100; i++) { -+ val = wed_r32(dev, MTK_WED_TX_BM_INTF); -+ if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40) -+ break; -+ } -+ -+ mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT); -+ mtk_wed_reset(dev, MTK_WED_RESET_TX_BM); -+ -+ if (busy) { -+ mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT); -+ mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV); -+ mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV); -+ } else { -+ wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, -+ MTK_WED_WPDMA_RESET_IDX_TX | -+ MTK_WED_WPDMA_RESET_IDX_RX); -+ wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0); -+ } -+ -+} -+ -+static int -+mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, -+ int size) -+{ -+ ring->desc = dma_alloc_coherent(dev->hw->dev, -+ size * sizeof(*ring->desc), -+ &ring->desc_phys, GFP_KERNEL); -+ if (!ring->desc) -+ return -ENOMEM; -+ -+ ring->size = size; -+ mtk_wed_ring_reset(ring->desc, size); -+ -+ return 0; -+} -+ -+static int -+mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size) -+{ -+ struct mtk_wed_ring *wdma = &dev->tx_wdma[idx]; -+ -+ if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE)) -+ return -ENOMEM; -+ -+ wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, -+ wdma->desc_phys); -+ wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT, -+ size); -+ wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0); -+ -+ wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, -+ wdma->desc_phys); -+ wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT, -+ size); -+ -+ return 0; -+} -+ -+static void -+mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) -+{ -+ u32 wdma_mask; -+ u32 val; -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) -+ if (!dev->tx_wdma[i].desc) -+ mtk_wed_wdma_ring_setup(dev, i, 16); -+ -+ wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0)); -+ -+ mtk_wed_hw_init(dev); -+ -+ wed_set(dev, MTK_WED_CTRL, -+ MTK_WED_CTRL_WDMA_INT_AGENT_EN | -+ MTK_WED_CTRL_WPDMA_INT_AGENT_EN | -+ MTK_WED_CTRL_WED_TX_BM_EN | -+ MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); -+ -+ wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS); -+ -+ wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, -+ MTK_WED_WPDMA_INT_TRIGGER_RX_DONE | -+ MTK_WED_WPDMA_INT_TRIGGER_TX_DONE); -+ -+ wed_set(dev, MTK_WED_WPDMA_INT_CTRL, -+ MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); -+ -+ wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask); -+ wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask); -+ -+ wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask); -+ wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask); -+ -+ wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); -+ wed_w32(dev, MTK_WED_INT_MASK, irq_mask); -+ -+ wed_set(dev, MTK_WED_GLO_CFG, -+ MTK_WED_GLO_CFG_TX_DMA_EN | -+ MTK_WED_GLO_CFG_RX_DMA_EN); -+ wed_set(dev, MTK_WED_WPDMA_GLO_CFG, -+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | -+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); -+ wed_set(dev, MTK_WED_WDMA_GLO_CFG, -+ MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); -+ -+ mtk_wed_set_ext_int(dev, true); -+ val = dev->wlan.wpdma_phys | -+ MTK_PCIE_MIRROR_MAP_EN | -+ FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index); -+ -+ if (dev->hw->index) -+ val |= BIT(1); -+ val |= BIT(0); -+ regmap_write(dev->hw->mirror, dev->hw->index * 4, val); -+ -+ dev->running = true; -+} -+ -+static int -+mtk_wed_attach(struct mtk_wed_device *dev) -+ __releases(RCU) -+{ -+ struct mtk_wed_hw *hw; -+ int ret = 0; -+ -+ RCU_LOCKDEP_WARN(!rcu_read_lock_held(), -+ "mtk_wed_attach without holding the RCU read lock"); -+ -+ if (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 || -+ !try_module_get(THIS_MODULE)) -+ ret = -ENODEV; -+ -+ rcu_read_unlock(); -+ -+ if (ret) -+ return ret; -+ -+ mutex_lock(&hw_lock); -+ -+ hw = mtk_wed_assign(dev); -+ if (!hw) { -+ module_put(THIS_MODULE); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ dev_info(&dev->wlan.pci_dev->dev, "attaching wed device %d\n", hw->index); -+ -+ dev->hw = hw; -+ dev->dev = hw->dev; -+ dev->irq = hw->irq; -+ dev->wdma_idx = hw->index; -+ -+ if (hw->eth->dma_dev == hw->eth->dev && -+ of_dma_is_coherent(hw->eth->dev->of_node)) -+ mtk_eth_set_dma_device(hw->eth, hw->dev); -+ -+ ret = mtk_wed_buffer_alloc(dev); -+ if (ret) { -+ mtk_wed_detach(dev); -+ goto out; -+ } -+ -+ mtk_wed_hw_init_early(dev); -+ regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0); -+ -+out: -+ mutex_unlock(&hw_lock); -+ -+ return ret; -+} -+ -+static int -+mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs) -+{ -+ struct mtk_wed_ring *ring = &dev->tx_ring[idx]; -+ -+ /* -+ * Tx ring redirection: -+ * Instead of configuring the WLAN PDMA TX ring directly, the WLAN -+ * driver allocated DMA ring gets configured into WED MTK_WED_RING_TX(n) -+ * registers. -+ * -+ * WED driver posts its own DMA ring as WLAN PDMA TX and configures it -+ * into MTK_WED_WPDMA_RING_TX(n) registers. -+ * It gets filled with packets picked up from WED TX ring and from -+ * WDMA RX. -+ */ -+ -+ BUG_ON(idx > ARRAY_SIZE(dev->tx_ring)); -+ -+ if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE)) -+ return -ENOMEM; -+ -+ if (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE)) -+ return -ENOMEM; -+ -+ ring->reg_base = MTK_WED_RING_TX(idx); -+ ring->wpdma = regs; -+ -+ /* WED -> WPDMA */ -+ wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys); -+ wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE); -+ wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_CPU_IDX, 0); -+ -+ wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE, -+ ring->desc_phys); -+ wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT, -+ MTK_WED_TX_RING_SIZE); -+ wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0); -+ -+ return 0; -+} -+ -+static int -+mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs) -+{ -+ struct mtk_wed_ring *ring = &dev->txfree_ring; -+ int i; -+ -+ /* -+ * For txfree event handling, the same DMA ring is shared between WED -+ * and WLAN. The WLAN driver accesses the ring index registers through -+ * WED -+ */ -+ ring->reg_base = MTK_WED_RING_RX(1); -+ ring->wpdma = regs; -+ -+ for (i = 0; i < 12; i += 4) { -+ u32 val = readl(regs + i); -+ -+ wed_w32(dev, MTK_WED_RING_RX(1) + i, val); -+ wed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val); -+ } -+ -+ return 0; -+} -+ -+static u32 -+mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask) -+{ -+ u32 val; -+ -+ val = wed_r32(dev, MTK_WED_EXT_INT_STATUS); -+ wed_w32(dev, MTK_WED_EXT_INT_STATUS, val); -+ val &= MTK_WED_EXT_INT_STATUS_ERROR_MASK; -+ if (!dev->hw->num_flows) -+ val &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD; -+ if (val && net_ratelimit()) -+ pr_err("mtk_wed%d: error status=%08x\n", dev->hw->index, val); -+ -+ val = wed_r32(dev, MTK_WED_INT_STATUS); -+ val &= mask; -+ wed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */ -+ -+ return val; -+} -+ -+static void -+mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask) -+{ -+ if (!dev->running) -+ return; -+ -+ mtk_wed_set_ext_int(dev, !!mask); -+ wed_w32(dev, MTK_WED_INT_MASK, mask); -+} -+ -+int mtk_wed_flow_add(int index) -+{ -+ struct mtk_wed_hw *hw = hw_list[index]; -+ int ret; -+ -+ if (!hw || !hw->wed_dev) -+ return -ENODEV; -+ -+ if (hw->num_flows) { -+ hw->num_flows++; -+ return 0; -+ } -+ -+ mutex_lock(&hw_lock); -+ if (!hw->wed_dev) { -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ ret = hw->wed_dev->wlan.offload_enable(hw->wed_dev); -+ if (!ret) -+ hw->num_flows++; -+ mtk_wed_set_ext_int(hw->wed_dev, true); -+ -+out: -+ mutex_unlock(&hw_lock); -+ -+ return ret; -+} -+ -+void mtk_wed_flow_remove(int index) -+{ -+ struct mtk_wed_hw *hw = hw_list[index]; -+ -+ if (!hw) -+ return; -+ -+ if (--hw->num_flows) -+ return; -+ -+ mutex_lock(&hw_lock); -+ if (!hw->wed_dev) -+ goto out; -+ -+ hw->wed_dev->wlan.offload_disable(hw->wed_dev); -+ mtk_wed_set_ext_int(hw->wed_dev, true); -+ -+out: -+ mutex_unlock(&hw_lock); -+} -+ -+void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, -+ void __iomem *wdma, int index) -+{ -+ static const struct mtk_wed_ops wed_ops = { -+ .attach = mtk_wed_attach, -+ .tx_ring_setup = mtk_wed_tx_ring_setup, -+ .txfree_ring_setup = mtk_wed_txfree_ring_setup, -+ .start = mtk_wed_start, -+ .stop = mtk_wed_stop, -+ .reset_dma = mtk_wed_reset_dma, -+ .reg_read = wed_r32, -+ .reg_write = wed_w32, -+ .irq_get = mtk_wed_irq_get, -+ .irq_set_mask = mtk_wed_irq_set_mask, -+ .detach = mtk_wed_detach, -+ }; -+ struct device_node *eth_np = eth->dev->of_node; -+ struct platform_device *pdev; -+ struct mtk_wed_hw *hw; -+ struct regmap *regs; -+ int irq; -+ -+ if (!np) -+ return; -+ -+ pdev = of_find_device_by_node(np); -+ if (!pdev) -+ return; -+ -+ get_device(&pdev->dev); -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) -+ return; -+ -+ regs = syscon_regmap_lookup_by_phandle(np, NULL); -+ if (!regs) -+ return; -+ -+ rcu_assign_pointer(mtk_soc_wed_ops, &wed_ops); -+ -+ mutex_lock(&hw_lock); -+ -+ if (WARN_ON(hw_list[index])) -+ goto unlock; -+ -+ hw = kzalloc(sizeof(*hw), GFP_KERNEL); -+ hw->node = np; -+ hw->regs = regs; -+ hw->eth = eth; -+ hw->dev = &pdev->dev; -+ hw->wdma = wdma; -+ hw->index = index; -+ hw->irq = irq; -+ hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, -+ "mediatek,pcie-mirror"); -+ hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np, -+ "mediatek,hifsys"); -+ if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) { -+ kfree(hw); -+ goto unlock; -+ } -+ -+ if (!index) { -+ regmap_write(hw->mirror, 0, 0); -+ regmap_write(hw->mirror, 4, 0); -+ } -+ mtk_wed_hw_add_debugfs(hw); -+ -+ hw_list[index] = hw; -+ -+unlock: -+ mutex_unlock(&hw_lock); -+} -+ -+void mtk_wed_exit(void) -+{ -+ int i; -+ -+ rcu_assign_pointer(mtk_soc_wed_ops, NULL); -+ -+ synchronize_rcu(); -+ -+ for (i = 0; i < ARRAY_SIZE(hw_list); i++) { -+ struct mtk_wed_hw *hw; -+ -+ hw = hw_list[i]; -+ if (!hw) -+ continue; -+ -+ hw_list[i] = NULL; -+ debugfs_remove(hw->debugfs_dir); -+ put_device(hw->dev); -+ kfree(hw); -+ } -+} ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_wed.h -@@ -0,0 +1,128 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (C) 2021 Felix Fietkau */ -+ -+#ifndef __MTK_WED_PRIV_H -+#define __MTK_WED_PRIV_H -+ -+#include -+#include -+#include -+ -+struct mtk_eth; -+ -+struct mtk_wed_hw { -+ struct device_node *node; -+ struct mtk_eth *eth; -+ struct regmap *regs; -+ struct regmap *hifsys; -+ struct device *dev; -+ void __iomem *wdma; -+ struct regmap *mirror; -+ struct dentry *debugfs_dir; -+ struct mtk_wed_device *wed_dev; -+ u32 debugfs_reg; -+ u32 num_flows; -+ char dirname[5]; -+ int irq; -+ int index; -+}; -+ -+ -+#ifdef CONFIG_NET_MEDIATEK_SOC_WED -+static inline void -+wed_w32(struct mtk_wed_device *dev, u32 reg, u32 val) -+{ -+ regmap_write(dev->hw->regs, reg, val); -+} -+ -+static inline u32 -+wed_r32(struct mtk_wed_device *dev, u32 reg) -+{ -+ unsigned int val; -+ -+ regmap_read(dev->hw->regs, reg, &val); -+ -+ return val; -+} -+ -+static inline void -+wdma_w32(struct mtk_wed_device *dev, u32 reg, u32 val) -+{ -+ writel(val, dev->hw->wdma + reg); -+} -+ -+static inline u32 -+wdma_r32(struct mtk_wed_device *dev, u32 reg) -+{ -+ return readl(dev->hw->wdma + reg); -+} -+ -+static inline u32 -+wpdma_tx_r32(struct mtk_wed_device *dev, int ring, u32 reg) -+{ -+ if (!dev->tx_ring[ring].wpdma) -+ return 0; -+ -+ return readl(dev->tx_ring[ring].wpdma + reg); -+} -+ -+static inline void -+wpdma_tx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val) -+{ -+ if (!dev->tx_ring[ring].wpdma) -+ return; -+ -+ writel(val, dev->tx_ring[ring].wpdma + reg); -+} -+ -+static inline u32 -+wpdma_txfree_r32(struct mtk_wed_device *dev, u32 reg) -+{ -+ if (!dev->txfree_ring.wpdma) -+ return 0; -+ -+ return readl(dev->txfree_ring.wpdma + reg); -+} -+ -+static inline void -+wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val) -+{ -+ if (!dev->txfree_ring.wpdma) -+ return; -+ -+ writel(val, dev->txfree_ring.wpdma + reg); -+} -+ -+void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, -+ void __iomem *wdma, int index); -+void mtk_wed_exit(void); -+int mtk_wed_flow_add(int index); -+void mtk_wed_flow_remove(int index); -+#else -+static inline void -+mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, -+ void __iomem *wdma, int index) -+{ -+} -+static inline void -+mtk_wed_exit(void) -+{ -+} -+static inline int mtk_wed_flow_add(int index) -+{ -+ return -EINVAL; -+} -+static inline void mtk_wed_flow_remove(int index) -+{ -+} -+#endif -+ -+#ifdef CONFIG_DEBUG_FS -+void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw); -+#else -+static inline void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw) -+{ -+} -+#endif -+ -+#endif ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c -@@ -0,0 +1,175 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (C) 2021 Felix Fietkau */ -+ -+#include -+#include "mtk_wed.h" -+#include "mtk_wed_regs.h" -+ -+struct reg_dump { -+ const char *name; -+ u16 offset; -+ u8 type; -+ u8 base; -+}; -+ -+enum { -+ DUMP_TYPE_STRING, -+ DUMP_TYPE_WED, -+ DUMP_TYPE_WDMA, -+ DUMP_TYPE_WPDMA_TX, -+ DUMP_TYPE_WPDMA_TXFREE, -+}; -+ -+#define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING } -+#define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ } -+#define DUMP_RING(_prefix, _base, ...) \ -+ { _prefix " BASE", _base, __VA_ARGS__ }, \ -+ { _prefix " CNT", _base + 0x4, __VA_ARGS__ }, \ -+ { _prefix " CIDX", _base + 0x8, __VA_ARGS__ }, \ -+ { _prefix " DIDX", _base + 0xc, __VA_ARGS__ } -+ -+#define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED) -+#define DUMP_WED_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WED) -+ -+#define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA) -+#define DUMP_WDMA_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WDMA) -+ -+#define DUMP_WPDMA_TX_RING(_n) DUMP_RING("WPDMA_TX" #_n, 0, DUMP_TYPE_WPDMA_TX, _n) -+#define DUMP_WPDMA_TXFREE_RING DUMP_RING("WPDMA_RX1", 0, DUMP_TYPE_WPDMA_TXFREE) -+ -+static void -+print_reg_val(struct seq_file *s, const char *name, u32 val) -+{ -+ seq_printf(s, "%-32s %08x\n", name, val); -+} -+ -+static void -+dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev, -+ const struct reg_dump *regs, int n_regs) -+{ -+ const struct reg_dump *cur; -+ u32 val; -+ -+ for (cur = regs; cur < ®s[n_regs]; cur++) { -+ switch (cur->type) { -+ case DUMP_TYPE_STRING: -+ seq_printf(s, "%s======== %s:\n", -+ cur > regs ? "\n" : "", -+ cur->name); -+ continue; -+ case DUMP_TYPE_WED: -+ val = wed_r32(dev, cur->offset); -+ break; -+ case DUMP_TYPE_WDMA: -+ val = wdma_r32(dev, cur->offset); -+ break; -+ case DUMP_TYPE_WPDMA_TX: -+ val = wpdma_tx_r32(dev, cur->base, cur->offset); -+ break; -+ case DUMP_TYPE_WPDMA_TXFREE: -+ val = wpdma_txfree_r32(dev, cur->offset); -+ break; -+ } -+ print_reg_val(s, cur->name, val); -+ } -+} -+ -+ -+static int -+wed_txinfo_show(struct seq_file *s, void *data) -+{ -+ static const struct reg_dump regs[] = { -+ DUMP_STR("WED TX"), -+ DUMP_WED(WED_TX_MIB(0)), -+ DUMP_WED_RING(WED_RING_TX(0)), -+ -+ DUMP_WED(WED_TX_MIB(1)), -+ DUMP_WED_RING(WED_RING_TX(1)), -+ -+ DUMP_STR("WPDMA TX"), -+ DUMP_WED(WED_WPDMA_TX_MIB(0)), -+ DUMP_WED_RING(WED_WPDMA_RING_TX(0)), -+ DUMP_WED(WED_WPDMA_TX_COHERENT_MIB(0)), -+ -+ DUMP_WED(WED_WPDMA_TX_MIB(1)), -+ DUMP_WED_RING(WED_WPDMA_RING_TX(1)), -+ DUMP_WED(WED_WPDMA_TX_COHERENT_MIB(1)), -+ -+ DUMP_STR("WPDMA TX"), -+ DUMP_WPDMA_TX_RING(0), -+ DUMP_WPDMA_TX_RING(1), -+ -+ DUMP_STR("WED WDMA RX"), -+ DUMP_WED(WED_WDMA_RX_MIB(0)), -+ DUMP_WED_RING(WED_WDMA_RING_RX(0)), -+ DUMP_WED(WED_WDMA_RX_THRES(0)), -+ DUMP_WED(WED_WDMA_RX_RECYCLE_MIB(0)), -+ DUMP_WED(WED_WDMA_RX_PROCESSED_MIB(0)), -+ -+ DUMP_WED(WED_WDMA_RX_MIB(1)), -+ DUMP_WED_RING(WED_WDMA_RING_RX(1)), -+ DUMP_WED(WED_WDMA_RX_THRES(1)), -+ DUMP_WED(WED_WDMA_RX_RECYCLE_MIB(1)), -+ DUMP_WED(WED_WDMA_RX_PROCESSED_MIB(1)), -+ -+ DUMP_STR("WDMA RX"), -+ DUMP_WDMA(WDMA_GLO_CFG), -+ DUMP_WDMA_RING(WDMA_RING_RX(0)), -+ DUMP_WDMA_RING(WDMA_RING_RX(1)), -+ }; -+ struct mtk_wed_hw *hw = s->private; -+ struct mtk_wed_device *dev = hw->wed_dev; -+ -+ if (!dev) -+ return 0; -+ -+ dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs)); -+ -+ return 0; -+} -+DEFINE_SHOW_ATTRIBUTE(wed_txinfo); -+ -+ -+static int -+mtk_wed_reg_set(void *data, u64 val) -+{ -+ struct mtk_wed_hw *hw = data; -+ -+ regmap_write(hw->regs, hw->debugfs_reg, val); -+ -+ return 0; -+} -+ -+static int -+mtk_wed_reg_get(void *data, u64 *val) -+{ -+ struct mtk_wed_hw *hw = data; -+ unsigned int regval; -+ int ret; -+ -+ ret = regmap_read(hw->regs, hw->debugfs_reg, ®val); -+ if (ret) -+ return ret; -+ -+ *val = regval; -+ -+ return 0; -+} -+ -+DEFINE_DEBUGFS_ATTRIBUTE(fops_regval, mtk_wed_reg_get, mtk_wed_reg_set, -+ "0x%08llx\n"); -+ -+void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw) -+{ -+ struct dentry *dir; -+ -+ snprintf(hw->dirname, sizeof(hw->dirname), "wed%d", hw->index); -+ dir = debugfs_create_dir(hw->dirname, NULL); -+ if (!dir) -+ return; -+ -+ hw->debugfs_dir = dir; -+ debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg); -+ debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval); -+ debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops); -+} ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_wed_ops.c -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (C) 2020 Felix Fietkau */ -+ -+#include -+#include -+ -+const struct mtk_wed_ops __rcu *mtk_soc_wed_ops; -+EXPORT_SYMBOL_GPL(mtk_soc_wed_ops); ---- /dev/null -+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h -@@ -0,0 +1,251 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* Copyright (C) 2020 Felix Fietkau */ -+ -+#ifndef __MTK_WED_REGS_H -+#define __MTK_WED_REGS_H -+ -+#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0) -+#define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15) -+#define MTK_WDMA_DESC_CTRL_BURST BIT(16) -+#define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16) -+#define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30) -+#define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31) -+ -+struct mtk_wdma_desc { -+ __le32 buf0; -+ __le32 ctrl; -+ __le32 buf1; -+ __le32 info; -+} __packed __aligned(4); -+ -+#define MTK_WED_RESET 0x008 -+#define MTK_WED_RESET_TX_BM BIT(0) -+#define MTK_WED_RESET_TX_FREE_AGENT BIT(4) -+#define MTK_WED_RESET_WPDMA_TX_DRV BIT(8) -+#define MTK_WED_RESET_WPDMA_RX_DRV BIT(9) -+#define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11) -+#define MTK_WED_RESET_WED_TX_DMA BIT(12) -+#define MTK_WED_RESET_WDMA_RX_DRV BIT(17) -+#define MTK_WED_RESET_WDMA_INT_AGENT BIT(19) -+#define MTK_WED_RESET_WED BIT(31) -+ -+#define MTK_WED_CTRL 0x00c -+#define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0) -+#define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1) -+#define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2) -+#define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3) -+#define MTK_WED_CTRL_WED_TX_BM_EN BIT(8) -+#define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9) -+#define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10) -+#define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11) -+#define MTK_WED_CTRL_RESERVE_EN BIT(12) -+#define MTK_WED_CTRL_RESERVE_BUSY BIT(13) -+#define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24) -+#define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28) -+ -+#define MTK_WED_EXT_INT_STATUS 0x020 -+#define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0) -+#define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD BIT(1) -+#define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4) -+#define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8) -+#define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9) -+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12) -+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13) -+#define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16) -+#define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17) -+#define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18) -+#define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19) -+#define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20) -+#define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21) -+#define MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR BIT(22) -+#define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24) -+#define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \ -+ MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \ -+ MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \ -+ MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \ -+ MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \ -+ MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \ -+ MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR | \ -+ MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR) -+ -+#define MTK_WED_EXT_INT_MASK 0x028 -+ -+#define MTK_WED_STATUS 0x060 -+#define MTK_WED_STATUS_TX GENMASK(15, 8) -+ -+#define MTK_WED_TX_BM_CTRL 0x080 -+#define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0) -+#define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16) -+#define MTK_WED_TX_BM_CTRL_PAUSE BIT(28) -+ -+#define MTK_WED_TX_BM_BASE 0x084 -+ -+#define MTK_WED_TX_BM_TKID 0x088 -+#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) -+#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) -+ -+#define MTK_WED_TX_BM_BUF_LEN 0x08c -+ -+#define MTK_WED_TX_BM_INTF 0x09c -+#define MTK_WED_TX_BM_INTF_TKID GENMASK(15, 0) -+#define MTK_WED_TX_BM_INTF_TKFIFO_FDEP GENMASK(23, 16) -+#define MTK_WED_TX_BM_INTF_TKID_VALID BIT(28) -+#define MTK_WED_TX_BM_INTF_TKID_READ BIT(29) -+ -+#define MTK_WED_TX_BM_DYN_THR 0x0a0 -+#define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0) -+#define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16) -+ -+#define MTK_WED_INT_STATUS 0x200 -+#define MTK_WED_INT_MASK 0x204 -+ -+#define MTK_WED_GLO_CFG 0x208 -+#define MTK_WED_GLO_CFG_TX_DMA_EN BIT(0) -+#define MTK_WED_GLO_CFG_TX_DMA_BUSY BIT(1) -+#define MTK_WED_GLO_CFG_RX_DMA_EN BIT(2) -+#define MTK_WED_GLO_CFG_RX_DMA_BUSY BIT(3) -+#define MTK_WED_GLO_CFG_RX_BT_SIZE GENMASK(5, 4) -+#define MTK_WED_GLO_CFG_TX_WB_DDONE BIT(6) -+#define MTK_WED_GLO_CFG_BIG_ENDIAN BIT(7) -+#define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8) -+#define MTK_WED_GLO_CFG_TX_BT_SIZE_LO BIT(9) -+#define MTK_WED_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10) -+#define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) -+#define MTK_WED_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13) -+#define MTK_WED_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22) -+#define MTK_WED_GLO_CFG_SW_RESET BIT(24) -+#define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) -+#define MTK_WED_GLO_CFG_OMIT_RX_INFO BIT(27) -+#define MTK_WED_GLO_CFG_OMIT_TX_INFO BIT(28) -+#define MTK_WED_GLO_CFG_BYTE_SWAP BIT(29) -+#define MTK_WED_GLO_CFG_RX_2B_OFFSET BIT(31) -+ -+#define MTK_WED_RESET_IDX 0x20c -+#define MTK_WED_RESET_IDX_TX GENMASK(3, 0) -+#define MTK_WED_RESET_IDX_RX GENMASK(17, 16) -+ -+#define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4) -+ -+#define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10) -+ -+#define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10) -+ -+#define MTK_WED_WPDMA_INT_TRIGGER 0x504 -+#define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1) -+#define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4) -+ -+#define MTK_WED_WPDMA_GLO_CFG 0x508 -+#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN BIT(0) -+#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1) -+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2) -+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3) -+#define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4) -+#define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6) -+#define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) -+#define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8) -+#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO BIT(9) -+#define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10) -+#define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12) -+#define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13) -+#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22) -+#define MTK_WED_WPDMA_GLO_CFG_SW_RESET BIT(24) -+#define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) -+#define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27) -+#define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28) -+#define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29) -+#define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) -+ -+#define MTK_WED_WPDMA_RESET_IDX 0x50c -+#define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0) -+#define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16) -+ -+#define MTK_WED_WPDMA_INT_CTRL 0x520 -+#define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21) -+ -+#define MTK_WED_WPDMA_INT_MASK 0x524 -+ -+#define MTK_WED_PCIE_CFG_BASE 0x560 -+ -+#define MTK_WED_PCIE_INT_TRIGGER 0x570 -+#define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16) -+ -+#define MTK_WED_WPDMA_CFG_BASE 0x580 -+ -+#define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4) -+#define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4) -+ -+#define MTK_WED_WPDMA_RING_TX(_n) (0x600 + (_n) * 0x10) -+#define MTK_WED_WPDMA_RING_RX(_n) (0x700 + (_n) * 0x10) -+#define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10) -+#define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4) -+ -+#define MTK_WED_WDMA_GLO_CFG 0xa04 -+#define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0) -+#define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2) -+#define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3) -+#define MTK_WED_WDMA_GLO_CFG_BT_SIZE GENMASK(5, 4) -+#define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE BIT(6) -+#define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE BIT(13) -+#define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL BIT(16) -+#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS BIT(17) -+#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS BIT(18) -+#define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE BIT(19) -+#define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT BIT(20) -+#define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW BIT(21) -+#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W BIT(22) -+#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY BIT(23) -+#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP BIT(24) -+#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE BIT(25) -+#define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE BIT(26) -+#define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS BIT(30) -+ -+#define MTK_WED_WDMA_RESET_IDX 0xa08 -+#define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16) -+#define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24) -+ -+#define MTK_WED_WDMA_INT_TRIGGER 0xa28 -+#define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16) -+ -+#define MTK_WED_WDMA_INT_CTRL 0xa2c -+#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16) -+ -+#define MTK_WED_WDMA_OFFSET0 0xaa4 -+#define MTK_WED_WDMA_OFFSET1 0xaa8 -+ -+#define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4) -+#define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4) -+#define MTK_WED_WDMA_RX_PROCESSED_MIB(_n) (0xaf0 + (_n) * 4) -+ -+#define MTK_WED_RING_OFS_BASE 0x00 -+#define MTK_WED_RING_OFS_COUNT 0x04 -+#define MTK_WED_RING_OFS_CPU_IDX 0x08 -+#define MTK_WED_RING_OFS_DMA_IDX 0x0c -+ -+#define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10) -+ -+#define MTK_WDMA_GLO_CFG 0x204 -+#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES GENMASK(28, 26) -+ -+#define MTK_WDMA_RESET_IDX 0x208 -+#define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0) -+#define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16) -+ -+#define MTK_WDMA_INT_MASK 0x228 -+#define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0) -+#define MTK_WDMA_INT_MASK_RX_DONE GENMASK(17, 16) -+#define MTK_WDMA_INT_MASK_TX_DELAY BIT(28) -+#define MTK_WDMA_INT_MASK_TX_COHERENT BIT(29) -+#define MTK_WDMA_INT_MASK_RX_DELAY BIT(30) -+#define MTK_WDMA_INT_MASK_RX_COHERENT BIT(31) -+ -+#define MTK_WDMA_INT_GRP1 0x250 -+#define MTK_WDMA_INT_GRP2 0x254 -+ -+#define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0) -+#define MTK_PCIE_MIRROR_MAP_EN BIT(0) -+#define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1) -+ -+/* DMA channel mapping */ -+#define HIFSYS_DMA_AG_MAP 0x008 -+ -+#endif ---- /dev/null -+++ b/include/linux/soc/mediatek/mtk_wed.h -@@ -0,0 +1,131 @@ -+#ifndef __MTK_WED_H -+#define __MTK_WED_H -+ -+#include -+#include -+#include -+#include -+ -+#define MTK_WED_TX_QUEUES 2 -+ -+struct mtk_wed_hw; -+struct mtk_wdma_desc; -+ -+struct mtk_wed_ring { -+ struct mtk_wdma_desc *desc; -+ dma_addr_t desc_phys; -+ int size; -+ -+ u32 reg_base; -+ void __iomem *wpdma; -+}; -+ -+struct mtk_wed_device { -+#ifdef CONFIG_NET_MEDIATEK_SOC_WED -+ const struct mtk_wed_ops *ops; -+ struct device *dev; -+ struct mtk_wed_hw *hw; -+ bool init_done, running; -+ int wdma_idx; -+ int irq; -+ -+ struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES]; -+ struct mtk_wed_ring txfree_ring; -+ struct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES]; -+ -+ struct { -+ int size; -+ void **pages; -+ struct mtk_wdma_desc *desc; -+ dma_addr_t desc_phys; -+ } buf_ring; -+ -+ /* filled by driver: */ -+ struct { -+ struct pci_dev *pci_dev; -+ -+ u32 wpdma_phys; -+ -+ u16 token_start; -+ unsigned int nbuf; -+ -+ u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id); -+ int (*offload_enable)(struct mtk_wed_device *wed); -+ void (*offload_disable)(struct mtk_wed_device *wed); -+ } wlan; -+#endif -+}; -+ -+struct mtk_wed_ops { -+ int (*attach)(struct mtk_wed_device *dev); -+ int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring, -+ void __iomem *regs); -+ int (*txfree_ring_setup)(struct mtk_wed_device *dev, -+ void __iomem *regs); -+ void (*detach)(struct mtk_wed_device *dev); -+ -+ void (*stop)(struct mtk_wed_device *dev); -+ void (*start)(struct mtk_wed_device *dev, u32 irq_mask); -+ void (*reset_dma)(struct mtk_wed_device *dev); -+ -+ u32 (*reg_read)(struct mtk_wed_device *dev, u32 reg); -+ void (*reg_write)(struct mtk_wed_device *dev, u32 reg, u32 val); -+ -+ u32 (*irq_get)(struct mtk_wed_device *dev, u32 mask); -+ void (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask); -+}; -+ -+extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops; -+ -+static inline int -+mtk_wed_device_attach(struct mtk_wed_device *dev) -+{ -+ int ret = -ENODEV; -+ -+#ifdef CONFIG_NET_MEDIATEK_SOC_WED -+ rcu_read_lock(); -+ dev->ops = rcu_dereference(mtk_soc_wed_ops); -+ if (dev->ops) -+ ret = dev->ops->attach(dev); -+ else -+ rcu_read_unlock(); -+ -+ if (ret) -+ dev->ops = NULL; -+#endif -+ -+ return ret; -+} -+ -+#ifdef CONFIG_NET_MEDIATEK_SOC_WED -+#define mtk_wed_device_active(_dev) !!(_dev)->ops -+#define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev) -+#define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask) -+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) \ -+ (_dev)->ops->tx_ring_setup(_dev, _ring, _regs) -+#define mtk_wed_device_txfree_ring_setup(_dev, _regs) \ -+ (_dev)->ops->txfree_ring_setup(_dev, _regs) -+#define mtk_wed_device_reg_read(_dev, _reg) \ -+ (_dev)->ops->reg_read(_dev, _reg) -+#define mtk_wed_device_reg_write(_dev, _reg, _val) \ -+ (_dev)->ops->reg_write(_dev, _reg, _val) -+#define mtk_wed_device_irq_get(_dev, _mask) \ -+ (_dev)->ops->irq_get(_dev, _mask) -+#define mtk_wed_device_irq_set_mask(_dev, _mask) \ -+ (_dev)->ops->irq_set_mask(_dev, _mask) -+#else -+static inline bool mtk_wed_device_active(struct mtk_wed_device *dev) -+{ -+ return false; -+} -+#define mtk_wed_device_detach(_dev) do {} while (0) -+#define mtk_wed_device_start(_dev, _mask) do {} while (0) -+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) -ENODEV -+#define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV -+#define mtk_wed_device_reg_read(_dev, _reg) 0 -+#define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0) -+#define mtk_wed_device_irq_get(_dev, _mask) 0 -+#define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0) -+#endif -+ -+#endif diff --git a/target/linux/generic/pending-5.10/701-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch b/target/linux/generic/pending-5.10/701-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch deleted file mode 100644 index b9c6d4378a..0000000000 --- a/target/linux/generic/pending-5.10/701-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch +++ /dev/null @@ -1,269 +0,0 @@ -From: Felix Fietkau -Date: Sat, 5 Feb 2022 18:29:22 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: implement flow offloading - to WED devices - -This allows hardware flow offloading from Ethernet to WLAN on MT7622 SoC - -Co-developed-by: Lorenzo Bianconi -Signed-off-by: Lorenzo Bianconi -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_ppe.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -329,6 +329,24 @@ int mtk_foe_entry_set_pppoe(struct mtk_f - return 0; - } - -+int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, -+ int bss, int wcid) -+{ -+ struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry); -+ u32 *ib2 = mtk_foe_entry_ib2(entry); -+ -+ *ib2 &= ~MTK_FOE_IB2_PORT_MG; -+ *ib2 |= MTK_FOE_IB2_WDMA_WINFO; -+ if (wdma_idx) -+ *ib2 |= MTK_FOE_IB2_WDMA_DEVIDX; -+ -+ l2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) | -+ FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) | -+ FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq); -+ -+ return 0; -+} -+ - static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry) - { - return !(entry->ib1 & MTK_FOE_IB1_STATIC) && ---- a/drivers/net/ethernet/mediatek/mtk_ppe.h -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -48,9 +48,9 @@ enum { - #define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5) - #define MTK_FOE_IB2_MULTICAST BIT(8) - --#define MTK_FOE_IB2_WHNAT_QID2 GENMASK(13, 12) --#define MTK_FOE_IB2_WHNAT_DEVIDX BIT(16) --#define MTK_FOE_IB2_WHNAT_NAT BIT(17) -+#define MTK_FOE_IB2_WDMA_QID2 GENMASK(13, 12) -+#define MTK_FOE_IB2_WDMA_DEVIDX BIT(16) -+#define MTK_FOE_IB2_WDMA_WINFO BIT(17) - - #define MTK_FOE_IB2_PORT_MG GENMASK(17, 12) - -@@ -58,9 +58,9 @@ enum { - - #define MTK_FOE_IB2_DSCP GENMASK(31, 24) - --#define MTK_FOE_VLAN2_WHNAT_BSS GEMMASK(5, 0) --#define MTK_FOE_VLAN2_WHNAT_WCID GENMASK(13, 6) --#define MTK_FOE_VLAN2_WHNAT_RING GENMASK(15, 14) -+#define MTK_FOE_VLAN2_WINFO_BSS GENMASK(5, 0) -+#define MTK_FOE_VLAN2_WINFO_WCID GENMASK(13, 6) -+#define MTK_FOE_VLAN2_WINFO_RING GENMASK(15, 14) - - enum { - MTK_FOE_STATE_INVALID, -@@ -281,6 +281,8 @@ int mtk_foe_entry_set_ipv6_tuple(struct - int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port); - int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid); - int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid); -+int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, -+ int bss, int wcid); - int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry, - u16 timestamp); - int mtk_ppe_debugfs_init(struct mtk_ppe *ppe); ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -11,6 +11,7 @@ - #include - #include - #include "mtk_eth_soc.h" -+#include "mtk_wed.h" - - struct mtk_flow_data { - struct ethhdr eth; -@@ -40,6 +41,7 @@ struct mtk_flow_entry { - struct rhash_head node; - unsigned long cookie; - u16 hash; -+ s8 wed_index; - }; - - static const struct rhashtable_params mtk_flow_ht_params = { -@@ -81,6 +83,35 @@ mtk_flow_offload_mangle_eth(const struct - memcpy(dest, src, act->mangle.mask ? 2 : 4); - } - -+static int -+mtk_flow_get_wdma_info(struct net_device *dev, const u8 *addr, struct mtk_wdma_info *info) -+{ -+ struct net_device_path_ctx ctx = { -+ .dev = dev, -+ .daddr = addr, -+ }; -+ struct net_device_path path = {}; -+ -+ if (!IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)) -+ return -1; -+ -+ if (!dev->netdev_ops->ndo_fill_forward_path) -+ return -1; -+ -+ if (dev->netdev_ops->ndo_fill_forward_path(&ctx, &path)) -+ return -1; -+ -+ if (path.type != DEV_PATH_MTK_WDMA) -+ return -1; -+ -+ info->wdma_idx = path.mtk_wdma.wdma_idx; -+ info->queue = path.mtk_wdma.queue; -+ info->bss = path.mtk_wdma.bss; -+ info->wcid = path.mtk_wdma.wcid; -+ -+ return 0; -+} -+ - - static int - mtk_flow_mangle_ports(const struct flow_action_entry *act, -@@ -150,10 +181,20 @@ mtk_flow_get_dsa_port(struct net_device - - static int - mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, -- struct net_device *dev) -+ struct net_device *dev, const u8 *dest_mac, -+ int *wed_index) - { -+ struct mtk_wdma_info info = {}; - int pse_port, dsa_port; - -+ if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) { -+ mtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss, -+ info.wcid); -+ pse_port = 3; -+ *wed_index = info.wdma_idx; -+ goto out; -+ } -+ - dsa_port = mtk_flow_get_dsa_port(&dev); - if (dsa_port >= 0) - mtk_foe_entry_set_dsa(foe, dsa_port); -@@ -165,6 +206,7 @@ mtk_flow_set_output_device(struct mtk_et - else - return -EOPNOTSUPP; - -+out: - mtk_foe_entry_set_pse_port(foe, pse_port); - - return 0; -@@ -180,6 +222,7 @@ mtk_flow_offload_replace(struct mtk_eth - struct net_device *odev = NULL; - struct mtk_flow_entry *entry; - int offload_type = 0; -+ int wed_index = -1; - u16 addr_type = 0; - u32 timestamp; - u8 l4proto = 0; -@@ -327,10 +370,14 @@ mtk_flow_offload_replace(struct mtk_eth - if (data.pppoe.num == 1) - mtk_foe_entry_set_pppoe(&foe, data.pppoe.sid); - -- err = mtk_flow_set_output_device(eth, &foe, odev); -+ err = mtk_flow_set_output_device(eth, &foe, odev, data.eth.h_dest, -+ &wed_index); - if (err) - return err; - -+ if (wed_index >= 0 && (err = mtk_wed_flow_add(wed_index)) < 0) -+ return err; -+ - entry = kzalloc(sizeof(*entry), GFP_KERNEL); - if (!entry) - return -ENOMEM; -@@ -344,6 +391,7 @@ mtk_flow_offload_replace(struct mtk_eth - } - - entry->hash = hash; -+ entry->wed_index = wed_index; - err = rhashtable_insert_fast(ð->flow_table, &entry->node, - mtk_flow_ht_params); - if (err < 0) -@@ -354,6 +402,8 @@ clear_flow: - mtk_foe_entry_clear(ð->ppe, hash); - free: - kfree(entry); -+ if (wed_index >= 0) -+ mtk_wed_flow_remove(wed_index); - return err; - } - -@@ -370,6 +420,8 @@ mtk_flow_offload_destroy(struct mtk_eth - mtk_foe_entry_clear(ð->ppe, entry->hash); - rhashtable_remove_fast(ð->flow_table, &entry->node, - mtk_flow_ht_params); -+ if (entry->wed_index >= 0) -+ mtk_wed_flow_remove(entry->wed_index); - kfree(entry); - - return 0; ---- a/drivers/net/ethernet/mediatek/mtk_wed.h -+++ b/drivers/net/ethernet/mediatek/mtk_wed.h -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - - struct mtk_eth; - -@@ -27,6 +28,12 @@ struct mtk_wed_hw { - int index; - }; - -+struct mtk_wdma_info { -+ u8 wdma_idx; -+ u8 queue; -+ u16 wcid; -+ u8 bss; -+}; - - #ifdef CONFIG_NET_MEDIATEK_SOC_WED - static inline void ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -856,6 +856,7 @@ enum net_device_path_type { - DEV_PATH_BRIDGE, - DEV_PATH_PPPOE, - DEV_PATH_DSA, -+ DEV_PATH_MTK_WDMA, - }; - - struct net_device_path { -@@ -881,6 +882,12 @@ struct net_device_path { - int port; - u16 proto; - } dsa; -+ struct { -+ u8 wdma_idx; -+ u8 queue; -+ u16 wcid; -+ u8 bss; -+ } mtk_wdma; - }; - }; - ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -883,6 +883,10 @@ int dev_fill_forward_path(const struct n - if (WARN_ON_ONCE(last_dev == ctx.dev)) - return -1; - } -+ -+ if (!ctx.dev) -+ return ret; -+ - path = dev_fwd_path(stack); - if (!path) - return -1; diff --git a/target/linux/generic/pending-5.10/701-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch b/target/linux/generic/pending-5.10/701-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch deleted file mode 100644 index f59a364a73..0000000000 --- a/target/linux/generic/pending-5.10/701-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch +++ /dev/null @@ -1,62 +0,0 @@ -From: Felix Fietkau -Date: Sat, 5 Feb 2022 18:36:36 +0100 -Subject: [PATCH] arm64: dts: mediatek: mt7622: introduce nodes for - Wireless Ethernet Dispatch - -Introduce wed0 and wed1 nodes in order to enable offloading forwarding -between ethernet and wireless devices on the mt7622 chipset. - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -893,6 +893,11 @@ - }; - }; - -+ hifsys: syscon@1af00000 { -+ compatible = "mediatek,mt7622-hifsys", "syscon"; -+ reg = <0 0x1af00000 0 0x70>; -+ }; -+ - ethsys: syscon@1b000000 { - compatible = "mediatek,mt7622-ethsys", - "syscon"; -@@ -911,6 +916,26 @@ - #dma-cells = <1>; - }; - -+ pcie_mirror: pcie-mirror@10000400 { -+ compatible = "mediatek,mt7622-pcie-mirror", -+ "syscon"; -+ reg = <0 0x10000400 0 0x10>; -+ }; -+ -+ wed0: wed@1020a000 { -+ compatible = "mediatek,mt7622-wed", -+ "syscon"; -+ reg = <0 0x1020a000 0 0x1000>; -+ interrupts = ; -+ }; -+ -+ wed1: wed@1020b000 { -+ compatible = "mediatek,mt7622-wed", -+ "syscon"; -+ reg = <0 0x1020b000 0 0x1000>; -+ interrupts = ; -+ }; -+ - eth: ethernet@1b100000 { - compatible = "mediatek,mt7622-eth", - "mediatek,mt2701-eth", -@@ -938,6 +963,9 @@ - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys>; - mediatek,cci-control = <&cci_control2>; -+ mediatek,wed = <&wed0>, <&wed1>; -+ mediatek,pcie-mirror = <&pcie_mirror>; -+ mediatek,hifsys = <&hifsys>; - dma-coherent; - #address-cells = <1>; - #size-cells = <0>; diff --git a/target/linux/generic/pending-5.10/701-05-net-ethernet-mtk_eth_soc-add-ipv6-flow-offload-suppo.patch b/target/linux/generic/pending-5.10/701-05-net-ethernet-mtk_eth_soc-add-ipv6-flow-offload-suppo.patch deleted file mode 100644 index 925c16ac69..0000000000 --- a/target/linux/generic/pending-5.10/701-05-net-ethernet-mtk_eth_soc-add-ipv6-flow-offload-suppo.patch +++ /dev/null @@ -1,79 +0,0 @@ -From: David Bentham -Date: Mon, 21 Feb 2022 15:36:16 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: add ipv6 flow offload - support - -Add the missing IPv6 flow offloading support for routing only. -Hardware flow offloading is done by the packet processing engine (PPE) -of the Ethernet MAC and as it doesn't support mangling of IPv6 packets, -IPv6 NAT cannot be supported. - -Signed-off-by: David Bentham -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -21,6 +22,11 @@ struct mtk_flow_data { - __be32 src_addr; - __be32 dst_addr; - } v4; -+ -+ struct { -+ struct in6_addr src_addr; -+ struct in6_addr dst_addr; -+ } v6; - }; - - __be16 src_port; -@@ -66,6 +72,14 @@ mtk_flow_set_ipv4_addr(struct mtk_foe_en - data->v4.dst_addr, data->dst_port); - } - -+static int -+mtk_flow_set_ipv6_addr(struct mtk_foe_entry *foe, struct mtk_flow_data *data) -+{ -+ return mtk_foe_entry_set_ipv6_tuple(foe, -+ data->v6.src_addr.s6_addr32, data->src_port, -+ data->v6.dst_addr.s6_addr32, data->dst_port); -+} -+ - static void - mtk_flow_offload_mangle_eth(const struct flow_action_entry *act, void *eth) - { -@@ -297,6 +311,9 @@ mtk_flow_offload_replace(struct mtk_eth - case FLOW_DISSECTOR_KEY_IPV4_ADDRS: - offload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT; - break; -+ case FLOW_DISSECTOR_KEY_IPV6_ADDRS: -+ offload_type = MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T; -+ break; - default: - return -EOPNOTSUPP; - } -@@ -332,6 +349,17 @@ mtk_flow_offload_replace(struct mtk_eth - mtk_flow_set_ipv4_addr(&foe, &data, false); - } - -+ if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { -+ struct flow_match_ipv6_addrs addrs; -+ -+ flow_rule_match_ipv6_addrs(rule, &addrs); -+ -+ data.v6.src_addr = addrs.key->src; -+ data.v6.dst_addr = addrs.key->dst; -+ -+ mtk_flow_set_ipv6_addr(&foe, &data); -+ } -+ - flow_action_for_each(i, act, &rule->action) { - if (act->id != FLOW_ACTION_MANGLE) - continue; diff --git a/target/linux/generic/pending-5.10/701-06-net-ethernet-mtk_eth_soc-support-TC_SETUP_BLOCK-for-.patch b/target/linux/generic/pending-5.10/701-06-net-ethernet-mtk_eth_soc-support-TC_SETUP_BLOCK-for-.patch deleted file mode 100644 index 1950d81ebb..0000000000 --- a/target/linux/generic/pending-5.10/701-06-net-ethernet-mtk_eth_soc-support-TC_SETUP_BLOCK-for-.patch +++ /dev/null @@ -1,29 +0,0 @@ -From: Felix Fietkau -Date: Mon, 21 Feb 2022 15:37:21 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: support TC_SETUP_BLOCK for - PPE offload - -This allows offload entries to be created from user space - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -564,10 +564,13 @@ mtk_eth_setup_tc_block(struct net_device - int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, - void *type_data) - { -- if (type == TC_SETUP_FT) -+ switch (type) { -+ case TC_SETUP_BLOCK: -+ case TC_SETUP_FT: - return mtk_eth_setup_tc_block(dev, type_data); -- -- return -EOPNOTSUPP; -+ default: -+ return -EOPNOTSUPP; -+ } - } - - int mtk_eth_offload_init(struct mtk_eth *eth) diff --git a/target/linux/generic/pending-5.10/701-07-net-ethernet-mtk_eth_soc-allocate-struct-mtk_ppe-sep.patch b/target/linux/generic/pending-5.10/701-07-net-ethernet-mtk_eth_soc-allocate-struct-mtk_ppe-sep.patch deleted file mode 100644 index 87fb1f49d6..0000000000 --- a/target/linux/generic/pending-5.10/701-07-net-ethernet-mtk_eth_soc-allocate-struct-mtk_ppe-sep.patch +++ /dev/null @@ -1,159 +0,0 @@ -From: Felix Fietkau -Date: Mon, 21 Feb 2022 15:38:20 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: allocate struct mtk_ppe - separately - -Preparation for adding more data to it, which will increase its size. - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2330,7 +2330,7 @@ static int mtk_open(struct net_device *d - return err; - } - -- if (eth->soc->offload_version && mtk_ppe_start(ð->ppe) == 0) -+ if (eth->soc->offload_version && mtk_ppe_start(eth->ppe) == 0) - gdm_config = MTK_GDMA_TO_PPE; - - mtk_gdm_config(eth, gdm_config); -@@ -2404,7 +2404,7 @@ static int mtk_stop(struct net_device *d - mtk_dma_free(eth); - - if (eth->soc->offload_version) -- mtk_ppe_stop(ð->ppe); -+ mtk_ppe_stop(eth->ppe); - - return 0; - } -@@ -3290,10 +3290,11 @@ static int mtk_probe(struct platform_dev - } - - if (eth->soc->offload_version) { -- err = mtk_ppe_init(ð->ppe, eth->dev, -- eth->base + MTK_ETH_PPE_BASE, 2); -- if (err) -+ eth->ppe = mtk_ppe_init(eth->dev, eth->base + MTK_ETH_PPE_BASE, 2); -+ if (!eth->ppe) { -+ err = -ENOMEM; - goto err_free_dev; -+ } - - err = mtk_eth_offload_init(eth); - if (err) ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -977,7 +977,7 @@ struct mtk_eth { - u32 rx_dma_l4_valid; - int ip_align; - -- struct mtk_ppe ppe; -+ struct mtk_ppe *ppe; - struct rhashtable flow_table; - }; - ---- a/drivers/net/ethernet/mediatek/mtk_ppe.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -384,10 +384,15 @@ int mtk_foe_entry_commit(struct mtk_ppe - return hash; - } - --int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base, -+struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base, - int version) - { - struct mtk_foe_entry *foe; -+ struct mtk_ppe *ppe; -+ -+ ppe = devm_kzalloc(dev, sizeof(*ppe), GFP_KERNEL); -+ if (!ppe) -+ return NULL; - - /* need to allocate a separate device, since it PPE DMA access is - * not coherent. -@@ -399,13 +404,13 @@ int mtk_ppe_init(struct mtk_ppe *ppe, st - foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe), - &ppe->foe_phys, GFP_KERNEL); - if (!foe) -- return -ENOMEM; -+ return NULL; - - ppe->foe_table = foe; - - mtk_ppe_debugfs_init(ppe); - -- return 0; -+ return ppe; - } - - static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe) ---- a/drivers/net/ethernet/mediatek/mtk_ppe.h -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -246,8 +246,7 @@ struct mtk_ppe { - void *acct_table; - }; - --int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base, -- int version); -+struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base, int version); - int mtk_ppe_start(struct mtk_ppe *ppe); - int mtk_ppe_stop(struct mtk_ppe *ppe); - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -412,7 +412,7 @@ mtk_flow_offload_replace(struct mtk_eth - - entry->cookie = f->cookie; - timestamp = mtk_eth_timestamp(eth); -- hash = mtk_foe_entry_commit(ð->ppe, &foe, timestamp); -+ hash = mtk_foe_entry_commit(eth->ppe, &foe, timestamp); - if (hash < 0) { - err = hash; - goto free; -@@ -427,7 +427,7 @@ mtk_flow_offload_replace(struct mtk_eth - - return 0; - clear_flow: -- mtk_foe_entry_clear(ð->ppe, hash); -+ mtk_foe_entry_clear(eth->ppe, hash); - free: - kfree(entry); - if (wed_index >= 0) -@@ -445,7 +445,7 @@ mtk_flow_offload_destroy(struct mtk_eth - if (!entry) - return -ENOENT; - -- mtk_foe_entry_clear(ð->ppe, entry->hash); -+ mtk_foe_entry_clear(eth->ppe, entry->hash); - rhashtable_remove_fast(ð->flow_table, &entry->node, - mtk_flow_ht_params); - if (entry->wed_index >= 0) -@@ -467,7 +467,7 @@ mtk_flow_offload_stats(struct mtk_eth *e - if (!entry) - return -ENOENT; - -- timestamp = mtk_foe_entry_timestamp(ð->ppe, entry->hash); -+ timestamp = mtk_foe_entry_timestamp(eth->ppe, entry->hash); - if (timestamp < 0) - return -ETIMEDOUT; - -@@ -523,7 +523,7 @@ mtk_eth_setup_tc_block(struct net_device - struct flow_block_cb *block_cb; - flow_setup_cb_t *cb; - -- if (!eth->ppe.foe_table) -+ if (!eth->ppe || !eth->ppe->foe_table) - return -EOPNOTSUPP; - - if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) -@@ -575,7 +575,7 @@ int mtk_eth_setup_tc(struct net_device * - - int mtk_eth_offload_init(struct mtk_eth *eth) - { -- if (!eth->ppe.foe_table) -+ if (!eth->ppe || !eth->ppe->foe_table) - return 0; - - return rhashtable_init(ð->flow_table, &mtk_flow_ht_params); diff --git a/target/linux/generic/pending-5.10/701-08-net-ethernet-mtk_eth_soc-rework-hardware-flow-table-.patch b/target/linux/generic/pending-5.10/701-08-net-ethernet-mtk_eth_soc-rework-hardware-flow-table-.patch deleted file mode 100644 index 447a7e9dcf..0000000000 --- a/target/linux/generic/pending-5.10/701-08-net-ethernet-mtk_eth_soc-rework-hardware-flow-table-.patch +++ /dev/null @@ -1,424 +0,0 @@ -From: Felix Fietkau -Date: Mon, 21 Feb 2022 15:39:18 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: rework hardware flow table - management - -The hardware was designed to handle flow detection and creation of flow entries -by itself, relying on the software primarily for filling in egress routing -information. -When there is a hash collision between multiple flows, this allows the hardware -to maintain the entry for the most active flow. -Additionally, the hardware only keeps offloading active for entries with at -least 30 packets per second. - -With this rework, the code no longer creates a hardware entries directly. -Instead, the hardware entry is only created when the PPE reports a matching -unbound flow with the minimum target rate. -In order to reduce CPU overhead, looking for flows belonging to a hash entry -is rate limited to once every 100ms. - -This rework is also used as preparation for emulating bridge offload by -managing L4 offload entries on demand. - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - #include - - #include "mtk_eth_soc.h" -@@ -1286,7 +1287,7 @@ static int mtk_poll_rx(struct napi_struc - struct net_device *netdev; - unsigned int pktlen; - dma_addr_t dma_addr; -- u32 hash; -+ u32 hash, reason; - int mac; - - ring = mtk_get_rx_ring(eth); -@@ -1365,6 +1366,11 @@ static int mtk_poll_rx(struct napi_struc - skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); - } - -+ reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); -+ if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) -+ mtk_ppe_check_skb(eth->ppe, skb, -+ trxd.rxd4 & MTK_RXD4_FOE_ENTRY); -+ - if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && - (trxd.rxd2 & RX_DMA_VTAG)) - __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), -@@ -3290,7 +3296,7 @@ static int mtk_probe(struct platform_dev - } - - if (eth->soc->offload_version) { -- eth->ppe = mtk_ppe_init(eth->dev, eth->base + MTK_ETH_PPE_BASE, 2); -+ eth->ppe = mtk_ppe_init(eth, eth->base + MTK_ETH_PPE_BASE, 2); - if (!eth->ppe) { - err = -ENOMEM; - goto err_free_dev; ---- a/drivers/net/ethernet/mediatek/mtk_ppe.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -6,9 +6,12 @@ - #include - #include - #include -+#include "mtk_eth_soc.h" - #include "mtk_ppe.h" - #include "mtk_ppe_regs.h" - -+static DEFINE_SPINLOCK(ppe_lock); -+ - static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val) - { - writel(val, ppe->base + reg); -@@ -41,6 +44,11 @@ static u32 ppe_clear(struct mtk_ppe *ppe - return ppe_m32(ppe, reg, val, 0); - } - -+static u32 mtk_eth_timestamp(struct mtk_eth *eth) -+{ -+ return mtk_r32(eth, 0x0010) & MTK_FOE_IB1_BIND_TIMESTAMP; -+} -+ - static int mtk_ppe_wait_busy(struct mtk_ppe *ppe) - { - int ret; -@@ -353,26 +361,59 @@ static inline bool mtk_foe_entry_usable( - FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1) != MTK_FOE_STATE_BIND; - } - --int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry, -- u16 timestamp) -+static bool -+mtk_flow_entry_match(struct mtk_flow_entry *entry, struct mtk_foe_entry *data) -+{ -+ int type, len; -+ -+ if ((data->ib1 ^ entry->data.ib1) & MTK_FOE_IB1_UDP) -+ return false; -+ -+ type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->data.ib1); -+ if (type > MTK_PPE_PKT_TYPE_IPV4_DSLITE) -+ len = offsetof(struct mtk_foe_entry, ipv6._rsv); -+ else -+ len = offsetof(struct mtk_foe_entry, ipv4.ib2); -+ -+ return !memcmp(&entry->data.data, &data->data, len - 4); -+} -+ -+static void -+mtk_flow_entry_update(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) - { - struct mtk_foe_entry *hwe; -- u32 hash; -+ struct mtk_foe_entry foe; - -+ spin_lock_bh(&ppe_lock); -+ if (entry->hash == 0xffff) -+ goto out; -+ -+ hwe = &ppe->foe_table[entry->hash]; -+ memcpy(&foe, hwe, sizeof(foe)); -+ if (!mtk_flow_entry_match(entry, &foe)) { -+ entry->hash = 0xffff; -+ goto out; -+ } -+ -+ entry->data.ib1 = foe.ib1; -+ -+out: -+ spin_unlock_bh(&ppe_lock); -+} -+ -+static void -+__mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry, -+ u16 hash) -+{ -+ struct mtk_foe_entry *hwe; -+ u16 timestamp; -+ -+ timestamp = mtk_eth_timestamp(ppe->eth); - timestamp &= MTK_FOE_IB1_BIND_TIMESTAMP; - entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP; - entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP, timestamp); - -- hash = mtk_ppe_hash_entry(entry); - hwe = &ppe->foe_table[hash]; -- if (!mtk_foe_entry_usable(hwe)) { -- hwe++; -- hash++; -- -- if (!mtk_foe_entry_usable(hwe)) -- return -ENOSPC; -- } -- - memcpy(&hwe->data, &entry->data, sizeof(hwe->data)); - wmb(); - hwe->ib1 = entry->ib1; -@@ -380,13 +421,77 @@ int mtk_foe_entry_commit(struct mtk_ppe - dma_wmb(); - - mtk_ppe_cache_clear(ppe); -+} - -- return hash; -+void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) -+{ -+ spin_lock_bh(&ppe_lock); -+ hlist_del_init(&entry->list); -+ if (entry->hash != 0xffff) { -+ ppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE; -+ ppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, -+ MTK_FOE_STATE_BIND); -+ dma_wmb(); -+ } -+ entry->hash = 0xffff; -+ spin_unlock_bh(&ppe_lock); -+} -+ -+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) -+{ -+ u32 hash = mtk_ppe_hash_entry(&entry->data); -+ -+ entry->hash = 0xffff; -+ spin_lock_bh(&ppe_lock); -+ hlist_add_head(&entry->list, &ppe->foe_flow[hash / 2]); -+ spin_unlock_bh(&ppe_lock); -+ -+ return 0; -+} -+ -+void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash) -+{ -+ struct hlist_head *head = &ppe->foe_flow[hash / 2]; -+ struct mtk_flow_entry *entry; -+ struct mtk_foe_entry *hwe = &ppe->foe_table[hash]; -+ bool found = false; -+ -+ if (hlist_empty(head)) -+ return; -+ -+ spin_lock_bh(&ppe_lock); -+ hlist_for_each_entry(entry, head, list) { -+ if (found || !mtk_flow_entry_match(entry, hwe)) { -+ if (entry->hash != 0xffff) -+ entry->hash = 0xffff; -+ continue; -+ } -+ -+ entry->hash = hash; -+ __mtk_foe_entry_commit(ppe, &entry->data, hash); -+ found = true; -+ } -+ spin_unlock_bh(&ppe_lock); -+} -+ -+int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) -+{ -+ u16 now = mtk_eth_timestamp(ppe->eth) & MTK_FOE_IB1_BIND_TIMESTAMP; -+ u16 timestamp; -+ -+ mtk_flow_entry_update(ppe, entry); -+ timestamp = entry->data.ib1 & MTK_FOE_IB1_BIND_TIMESTAMP; -+ -+ if (timestamp > now) -+ return MTK_FOE_IB1_BIND_TIMESTAMP + 1 - timestamp + now; -+ else -+ return now - timestamp; - } - --struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base, -+struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, - int version) - { -+ struct device *dev = eth->dev; - struct mtk_foe_entry *foe; - struct mtk_ppe *ppe; - -@@ -398,6 +503,7 @@ struct mtk_ppe *mtk_ppe_init(struct devi - * not coherent. - */ - ppe->base = base; -+ ppe->eth = eth; - ppe->dev = dev; - ppe->version = version; - ---- a/drivers/net/ethernet/mediatek/mtk_ppe.h -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -235,7 +235,17 @@ enum { - MTK_PPE_CPU_REASON_INVALID = 0x1f, - }; - -+struct mtk_flow_entry { -+ struct rhash_head node; -+ struct hlist_node list; -+ unsigned long cookie; -+ struct mtk_foe_entry data; -+ u16 hash; -+ s8 wed_index; -+}; -+ - struct mtk_ppe { -+ struct mtk_eth *eth; - struct device *dev; - void __iomem *base; - int version; -@@ -243,18 +253,33 @@ struct mtk_ppe { - struct mtk_foe_entry *foe_table; - dma_addr_t foe_phys; - -+ u16 foe_check_time[MTK_PPE_ENTRIES]; -+ struct hlist_head foe_flow[MTK_PPE_ENTRIES / 2]; -+ - void *acct_table; - }; - --struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base, int version); -+struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int version); - int mtk_ppe_start(struct mtk_ppe *ppe); - int mtk_ppe_stop(struct mtk_ppe *ppe); - -+void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash); -+ - static inline void --mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash) -+mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash) - { -- ppe->foe_table[hash].ib1 = 0; -- dma_wmb(); -+ u16 now, diff; -+ -+ if (!ppe) -+ return; -+ -+ now = (u16)jiffies; -+ diff = now - ppe->foe_check_time[hash]; -+ if (diff < HZ / 10) -+ return; -+ -+ ppe->foe_check_time[hash] = now; -+ __mtk_ppe_check_skb(ppe, skb, hash); - } - - static inline int -@@ -282,8 +307,9 @@ int mtk_foe_entry_set_vlan(struct mtk_fo - int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid); - int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, - int bss, int wcid); --int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry, -- u16 timestamp); -+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); -+void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); -+int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); - int mtk_ppe_debugfs_init(struct mtk_ppe *ppe); - - #endif ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -43,13 +43,6 @@ struct mtk_flow_data { - } pppoe; - }; - --struct mtk_flow_entry { -- struct rhash_head node; -- unsigned long cookie; -- u16 hash; -- s8 wed_index; --}; -- - static const struct rhashtable_params mtk_flow_ht_params = { - .head_offset = offsetof(struct mtk_flow_entry, node), - .key_offset = offsetof(struct mtk_flow_entry, cookie), -@@ -57,12 +50,6 @@ static const struct rhashtable_params mt - .automatic_shrinking = true, - }; - --static u32 --mtk_eth_timestamp(struct mtk_eth *eth) --{ -- return mtk_r32(eth, 0x0010) & MTK_FOE_IB1_BIND_TIMESTAMP; --} -- - static int - mtk_flow_set_ipv4_addr(struct mtk_foe_entry *foe, struct mtk_flow_data *data, - bool egress) -@@ -238,10 +225,8 @@ mtk_flow_offload_replace(struct mtk_eth - int offload_type = 0; - int wed_index = -1; - u16 addr_type = 0; -- u32 timestamp; - u8 l4proto = 0; - int err = 0; -- int hash; - int i; - - if (rhashtable_lookup(ð->flow_table, &f->cookie, mtk_flow_ht_params)) -@@ -411,23 +396,21 @@ mtk_flow_offload_replace(struct mtk_eth - return -ENOMEM; - - entry->cookie = f->cookie; -- timestamp = mtk_eth_timestamp(eth); -- hash = mtk_foe_entry_commit(eth->ppe, &foe, timestamp); -- if (hash < 0) { -- err = hash; -+ memcpy(&entry->data, &foe, sizeof(entry->data)); -+ entry->wed_index = wed_index; -+ -+ if (mtk_foe_entry_commit(eth->ppe, entry) < 0) - goto free; -- } - -- entry->hash = hash; -- entry->wed_index = wed_index; - err = rhashtable_insert_fast(ð->flow_table, &entry->node, - mtk_flow_ht_params); - if (err < 0) -- goto clear_flow; -+ goto clear; - - return 0; --clear_flow: -- mtk_foe_entry_clear(eth->ppe, hash); -+ -+clear: -+ mtk_foe_entry_clear(eth->ppe, entry); - free: - kfree(entry); - if (wed_index >= 0) -@@ -445,7 +428,7 @@ mtk_flow_offload_destroy(struct mtk_eth - if (!entry) - return -ENOENT; - -- mtk_foe_entry_clear(eth->ppe, entry->hash); -+ mtk_foe_entry_clear(eth->ppe, entry); - rhashtable_remove_fast(ð->flow_table, &entry->node, - mtk_flow_ht_params); - if (entry->wed_index >= 0) -@@ -459,7 +442,6 @@ static int - mtk_flow_offload_stats(struct mtk_eth *eth, struct flow_cls_offload *f) - { - struct mtk_flow_entry *entry; -- int timestamp; - u32 idle; - - entry = rhashtable_lookup(ð->flow_table, &f->cookie, -@@ -467,11 +449,7 @@ mtk_flow_offload_stats(struct mtk_eth *e - if (!entry) - return -ENOENT; - -- timestamp = mtk_foe_entry_timestamp(eth->ppe, entry->hash); -- if (timestamp < 0) -- return -ETIMEDOUT; -- -- idle = mtk_eth_timestamp(eth) - timestamp; -+ idle = mtk_foe_entry_idle_time(eth->ppe, entry); - f->stats.lastused = jiffies - idle * HZ; - - return 0; diff --git a/target/linux/generic/pending-5.10/701-09-net-ethernet-mtk_eth_soc-remove-bridge-flow-offload-.patch b/target/linux/generic/pending-5.10/701-09-net-ethernet-mtk_eth_soc-remove-bridge-flow-offload-.patch deleted file mode 100644 index 2ff0b341f9..0000000000 --- a/target/linux/generic/pending-5.10/701-09-net-ethernet-mtk_eth_soc-remove-bridge-flow-offload-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From: Felix Fietkau -Date: Mon, 21 Feb 2022 15:55:19 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: remove bridge flow offload - type entry support - -According to MediaTek, this feature is not supported in current hardware - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_ppe.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -84,13 +84,6 @@ static u32 mtk_ppe_hash_entry(struct mtk - u32 hash; - - switch (FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, e->ib1)) { -- case MTK_PPE_PKT_TYPE_BRIDGE: -- hv1 = e->bridge.src_mac_lo; -- hv1 ^= ((e->bridge.src_mac_hi & 0xffff) << 16); -- hv2 = e->bridge.src_mac_hi >> 16; -- hv2 ^= e->bridge.dest_mac_lo; -- hv3 = e->bridge.dest_mac_hi; -- break; - case MTK_PPE_PKT_TYPE_IPV4_ROUTE: - case MTK_PPE_PKT_TYPE_IPV4_HNAPT: - hv1 = e->ipv4.orig.ports; -@@ -572,7 +565,6 @@ int mtk_ppe_start(struct mtk_ppe *ppe) - MTK_PPE_FLOW_CFG_IP4_NAT | - MTK_PPE_FLOW_CFG_IP4_NAPT | - MTK_PPE_FLOW_CFG_IP4_DSLITE | -- MTK_PPE_FLOW_CFG_L2_BRIDGE | - MTK_PPE_FLOW_CFG_IP4_NAT_FRAG; - ppe_w32(ppe, MTK_PPE_FLOW_CFG, val); - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c -@@ -32,7 +32,6 @@ static const char *mtk_foe_pkt_type_str( - static const char * const type_str[] = { - [MTK_PPE_PKT_TYPE_IPV4_HNAPT] = "IPv4 5T", - [MTK_PPE_PKT_TYPE_IPV4_ROUTE] = "IPv4 3T", -- [MTK_PPE_PKT_TYPE_BRIDGE] = "L2", - [MTK_PPE_PKT_TYPE_IPV4_DSLITE] = "DS-LITE", - [MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T] = "IPv6 3T", - [MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T] = "IPv6 5T", diff --git a/target/linux/generic/pending-5.10/701-10-net-ethernet-mtk_eth_soc-support-creating-mac-addres.patch b/target/linux/generic/pending-5.10/701-10-net-ethernet-mtk_eth_soc-support-creating-mac-addres.patch deleted file mode 100644 index 99e597a3d1..0000000000 --- a/target/linux/generic/pending-5.10/701-10-net-ethernet-mtk_eth_soc-support-creating-mac-addres.patch +++ /dev/null @@ -1,553 +0,0 @@ -From: Felix Fietkau -Date: Wed, 23 Feb 2022 10:56:34 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: support creating mac - address based offload entries - -This will be used to implement a limited form of bridge offloading. -Since the hardware does not support flow table entries with just source -and destination MAC address, the driver has to emulate it. - -The hardware automatically creates entries entries for incoming flows, even -when they are bridged instead of routed, and reports when packets for these -flows have reached the minimum PPS rate for offloading. - -After this happens, we look up the L2 flow offload entry based on the MAC -header and fill in the output routing information in the flow table. -The dynamically created per-flow entries are automatically removed when -either the hardware flowtable entry expires, is replaced, or if the offload -rule they belong to is removed - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_ppe.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c -@@ -6,12 +6,22 @@ - #include - #include - #include -+#include -+#include -+#include - #include "mtk_eth_soc.h" - #include "mtk_ppe.h" - #include "mtk_ppe_regs.h" - - static DEFINE_SPINLOCK(ppe_lock); - -+static const struct rhashtable_params mtk_flow_l2_ht_params = { -+ .head_offset = offsetof(struct mtk_flow_entry, l2_node), -+ .key_offset = offsetof(struct mtk_flow_entry, data.bridge), -+ .key_len = offsetof(struct mtk_foe_bridge, key_end), -+ .automatic_shrinking = true, -+}; -+ - static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val) - { - writel(val, ppe->base + reg); -@@ -123,6 +133,9 @@ mtk_foe_entry_l2(struct mtk_foe_entry *e - { - int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); - -+ if (type == MTK_PPE_PKT_TYPE_BRIDGE) -+ return &entry->bridge.l2; -+ - if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) - return &entry->ipv6.l2; - -@@ -134,6 +147,9 @@ mtk_foe_entry_ib2(struct mtk_foe_entry * - { - int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1); - -+ if (type == MTK_PPE_PKT_TYPE_BRIDGE) -+ return &entry->bridge.ib2; -+ - if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) - return &entry->ipv6.ib2; - -@@ -168,7 +184,12 @@ int mtk_foe_entry_prepare(struct mtk_foe - if (type == MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T) - entry->ipv6.ports = ports_pad; - -- if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) { -+ if (type == MTK_PPE_PKT_TYPE_BRIDGE) { -+ ether_addr_copy(entry->bridge.src_mac, src_mac); -+ ether_addr_copy(entry->bridge.dest_mac, dest_mac); -+ entry->bridge.ib2 = val; -+ l2 = &entry->bridge.l2; -+ } else if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) { - entry->ipv6.ib2 = val; - l2 = &entry->ipv6.l2; - } else { -@@ -372,12 +393,96 @@ mtk_flow_entry_match(struct mtk_flow_ent - } - - static void -+__mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) -+{ -+ struct hlist_head *head; -+ struct hlist_node *tmp; -+ -+ if (entry->type == MTK_FLOW_TYPE_L2) { -+ rhashtable_remove_fast(&ppe->l2_flows, &entry->l2_node, -+ mtk_flow_l2_ht_params); -+ -+ head = &entry->l2_flows; -+ hlist_for_each_entry_safe(entry, tmp, head, l2_data.list) -+ __mtk_foe_entry_clear(ppe, entry); -+ return; -+ } -+ -+ hlist_del_init(&entry->list); -+ if (entry->hash != 0xffff) { -+ ppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE; -+ ppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, -+ MTK_FOE_STATE_BIND); -+ dma_wmb(); -+ } -+ entry->hash = 0xffff; -+ -+ if (entry->type != MTK_FLOW_TYPE_L2_SUBFLOW) -+ return; -+ -+ hlist_del_init(&entry->l2_data.list); -+ kfree(entry); -+} -+ -+static int __mtk_foe_entry_idle_time(struct mtk_ppe *ppe, u32 ib1) -+{ -+ u16 timestamp; -+ u16 now; -+ -+ now = mtk_eth_timestamp(ppe->eth) & MTK_FOE_IB1_BIND_TIMESTAMP; -+ timestamp = ib1 & MTK_FOE_IB1_BIND_TIMESTAMP; -+ -+ if (timestamp > now) -+ return MTK_FOE_IB1_BIND_TIMESTAMP + 1 - timestamp + now; -+ else -+ return now - timestamp; -+} -+ -+static void -+mtk_flow_entry_update_l2(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) -+{ -+ struct mtk_flow_entry *cur; -+ struct mtk_foe_entry *hwe; -+ struct hlist_node *tmp; -+ int idle; -+ -+ idle = __mtk_foe_entry_idle_time(ppe, entry->data.ib1); -+ hlist_for_each_entry_safe(cur, tmp, &entry->l2_flows, l2_data.list) { -+ int cur_idle; -+ u32 ib1; -+ -+ hwe = &ppe->foe_table[cur->hash]; -+ ib1 = READ_ONCE(hwe->ib1); -+ -+ if (FIELD_GET(MTK_FOE_IB1_STATE, ib1) != MTK_FOE_STATE_BIND) { -+ cur->hash = 0xffff; -+ __mtk_foe_entry_clear(ppe, cur); -+ continue; -+ } -+ -+ cur_idle = __mtk_foe_entry_idle_time(ppe, ib1); -+ if (cur_idle >= idle) -+ continue; -+ -+ idle = cur_idle; -+ entry->data.ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP; -+ entry->data.ib1 |= hwe->ib1 & MTK_FOE_IB1_BIND_TIMESTAMP; -+ } -+} -+ -+static void - mtk_flow_entry_update(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) - { - struct mtk_foe_entry *hwe; - struct mtk_foe_entry foe; - - spin_lock_bh(&ppe_lock); -+ -+ if (entry->type == MTK_FLOW_TYPE_L2) { -+ mtk_flow_entry_update_l2(ppe, entry); -+ goto out; -+ } -+ - if (entry->hash == 0xffff) - goto out; - -@@ -419,21 +524,28 @@ __mtk_foe_entry_commit(struct mtk_ppe *p - void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) - { - spin_lock_bh(&ppe_lock); -- hlist_del_init(&entry->list); -- if (entry->hash != 0xffff) { -- ppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE; -- ppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, -- MTK_FOE_STATE_BIND); -- dma_wmb(); -- } -- entry->hash = 0xffff; -+ __mtk_foe_entry_clear(ppe, entry); - spin_unlock_bh(&ppe_lock); - } - -+static int -+mtk_foe_entry_commit_l2(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) -+{ -+ entry->type = MTK_FLOW_TYPE_L2; -+ -+ return rhashtable_insert_fast(&ppe->l2_flows, &entry->l2_node, -+ mtk_flow_l2_ht_params); -+} -+ - int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) - { -- u32 hash = mtk_ppe_hash_entry(&entry->data); -+ int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->data.ib1); -+ u32 hash; -+ -+ if (type == MTK_PPE_PKT_TYPE_BRIDGE) -+ return mtk_foe_entry_commit_l2(ppe, entry); - -+ hash = mtk_ppe_hash_entry(&entry->data); - entry->hash = 0xffff; - spin_lock_bh(&ppe_lock); - hlist_add_head(&entry->list, &ppe->foe_flow[hash / 2]); -@@ -442,18 +554,72 @@ int mtk_foe_entry_commit(struct mtk_ppe - return 0; - } - -+static void -+mtk_foe_entry_commit_subflow(struct mtk_ppe *ppe, struct mtk_flow_entry *entry, -+ u16 hash) -+{ -+ struct mtk_flow_entry *flow_info; -+ struct mtk_foe_entry foe, *hwe; -+ struct mtk_foe_mac_info *l2; -+ u32 ib1_mask = MTK_FOE_IB1_PACKET_TYPE | MTK_FOE_IB1_UDP; -+ int type; -+ -+ flow_info = kzalloc(offsetof(struct mtk_flow_entry, l2_data.end), -+ GFP_ATOMIC); -+ if (!flow_info) -+ return; -+ -+ flow_info->l2_data.base_flow = entry; -+ flow_info->type = MTK_FLOW_TYPE_L2_SUBFLOW; -+ flow_info->hash = hash; -+ hlist_add_head(&flow_info->list, &ppe->foe_flow[hash / 2]); -+ hlist_add_head(&flow_info->l2_data.list, &entry->l2_flows); -+ -+ hwe = &ppe->foe_table[hash]; -+ memcpy(&foe, hwe, sizeof(foe)); -+ foe.ib1 &= ib1_mask; -+ foe.ib1 |= entry->data.ib1 & ~ib1_mask; -+ -+ l2 = mtk_foe_entry_l2(&foe); -+ memcpy(l2, &entry->data.bridge.l2, sizeof(*l2)); -+ -+ type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, foe.ib1); -+ if (type == MTK_PPE_PKT_TYPE_IPV4_HNAPT) -+ memcpy(&foe.ipv4.new, &foe.ipv4.orig, sizeof(foe.ipv4.new)); -+ else if (type >= MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T && l2->etype == ETH_P_IP) -+ l2->etype = ETH_P_IPV6; -+ -+ *mtk_foe_entry_ib2(&foe) = entry->data.bridge.ib2; -+ -+ __mtk_foe_entry_commit(ppe, &foe, hash); -+} -+ - void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash) - { - struct hlist_head *head = &ppe->foe_flow[hash / 2]; -- struct mtk_flow_entry *entry; - struct mtk_foe_entry *hwe = &ppe->foe_table[hash]; -+ struct mtk_flow_entry *entry; -+ struct mtk_foe_bridge key = {}; -+ struct ethhdr *eh; - bool found = false; -- -- if (hlist_empty(head)) -- return; -+ u8 *tag; - - spin_lock_bh(&ppe_lock); -+ -+ if (FIELD_GET(MTK_FOE_IB1_STATE, hwe->ib1) == MTK_FOE_STATE_BIND) -+ goto out; -+ - hlist_for_each_entry(entry, head, list) { -+ if (entry->type == MTK_FLOW_TYPE_L2_SUBFLOW) { -+ if (unlikely(FIELD_GET(MTK_FOE_IB1_STATE, hwe->ib1) == -+ MTK_FOE_STATE_BIND)) -+ continue; -+ -+ entry->hash = 0xffff; -+ __mtk_foe_entry_clear(ppe, entry); -+ continue; -+ } -+ - if (found || !mtk_flow_entry_match(entry, hwe)) { - if (entry->hash != 0xffff) - entry->hash = 0xffff; -@@ -464,21 +630,50 @@ void __mtk_ppe_check_skb(struct mtk_ppe - __mtk_foe_entry_commit(ppe, &entry->data, hash); - found = true; - } -+ -+ if (found) -+ goto out; -+ -+ eh = eth_hdr(skb); -+ ether_addr_copy(key.dest_mac, eh->h_dest); -+ ether_addr_copy(key.src_mac, eh->h_source); -+ tag = skb->data - 2; -+ key.vlan = 0; -+ switch (skb->protocol) { -+#if IS_ENABLED(CONFIG_NET_DSA) -+ case htons(ETH_P_XDSA): -+ if (!netdev_uses_dsa(skb->dev) || -+ skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) -+ goto out; -+ -+ tag += 4; -+ if (get_unaligned_be16(tag) != ETH_P_8021Q) -+ break; -+ -+ fallthrough; -+#endif -+ case htons(ETH_P_8021Q): -+ key.vlan = get_unaligned_be16(tag + 2) & VLAN_VID_MASK; -+ break; -+ default: -+ break; -+ } -+ -+ entry = rhashtable_lookup_fast(&ppe->l2_flows, &key, mtk_flow_l2_ht_params); -+ if (!entry) -+ goto out; -+ -+ mtk_foe_entry_commit_subflow(ppe, entry, hash); -+ -+out: - spin_unlock_bh(&ppe_lock); - } - - int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry) - { -- u16 now = mtk_eth_timestamp(ppe->eth) & MTK_FOE_IB1_BIND_TIMESTAMP; -- u16 timestamp; -- - mtk_flow_entry_update(ppe, entry); -- timestamp = entry->data.ib1 & MTK_FOE_IB1_BIND_TIMESTAMP; - -- if (timestamp > now) -- return MTK_FOE_IB1_BIND_TIMESTAMP + 1 - timestamp + now; -- else -- return now - timestamp; -+ return __mtk_foe_entry_idle_time(ppe, entry->data.ib1); - } - - struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, -@@ -492,6 +687,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_ - if (!ppe) - return NULL; - -+ rhashtable_init(&ppe->l2_flows, &mtk_flow_l2_ht_params); -+ - /* need to allocate a separate device, since it PPE DMA access is - * not coherent. - */ ---- a/drivers/net/ethernet/mediatek/mtk_ppe.h -+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h -@@ -6,6 +6,7 @@ - - #include - #include -+#include - - #define MTK_ETH_PPE_BASE 0xc00 - -@@ -84,19 +85,16 @@ struct mtk_foe_mac_info { - u16 src_mac_lo; - }; - -+/* software-only entry type */ - struct mtk_foe_bridge { -- u32 dest_mac_hi; -- -- u16 src_mac_lo; -- u16 dest_mac_lo; -+ u8 dest_mac[ETH_ALEN]; -+ u8 src_mac[ETH_ALEN]; -+ u16 vlan; - -- u32 src_mac_hi; -+ struct {} key_end; - - u32 ib2; - -- u32 _rsv[5]; -- -- u32 udf_tsid; - struct mtk_foe_mac_info l2; - }; - -@@ -235,13 +233,33 @@ enum { - MTK_PPE_CPU_REASON_INVALID = 0x1f, - }; - -+enum { -+ MTK_FLOW_TYPE_L4, -+ MTK_FLOW_TYPE_L2, -+ MTK_FLOW_TYPE_L2_SUBFLOW, -+}; -+ - struct mtk_flow_entry { -+ union { -+ struct hlist_node list; -+ struct { -+ struct rhash_head l2_node; -+ struct hlist_head l2_flows; -+ }; -+ }; -+ u8 type; -+ s8 wed_index; -+ u16 hash; -+ union { -+ struct mtk_foe_entry data; -+ struct { -+ struct mtk_flow_entry *base_flow; -+ struct hlist_node list; -+ struct {} end; -+ } l2_data; -+ }; - struct rhash_head node; -- struct hlist_node list; - unsigned long cookie; -- struct mtk_foe_entry data; -- u16 hash; -- s8 wed_index; - }; - - struct mtk_ppe { -@@ -256,6 +274,8 @@ struct mtk_ppe { - u16 foe_check_time[MTK_PPE_ENTRIES]; - struct hlist_head foe_flow[MTK_PPE_ENTRIES / 2]; - -+ struct rhashtable l2_flows; -+ - void *acct_table; - }; - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -32,6 +32,8 @@ struct mtk_flow_data { - __be16 src_port; - __be16 dst_port; - -+ u16 vlan_in; -+ - struct { - u16 id; - __be16 proto; -@@ -258,9 +260,45 @@ mtk_flow_offload_replace(struct mtk_eth - return -EOPNOTSUPP; - } - -+ switch (addr_type) { -+ case 0: -+ offload_type = MTK_PPE_PKT_TYPE_BRIDGE; -+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { -+ struct flow_match_eth_addrs match; -+ -+ flow_rule_match_eth_addrs(rule, &match); -+ memcpy(data.eth.h_dest, match.key->dst, ETH_ALEN); -+ memcpy(data.eth.h_source, match.key->src, ETH_ALEN); -+ } else { -+ return -EOPNOTSUPP; -+ } -+ -+ if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { -+ struct flow_match_vlan match; -+ -+ flow_rule_match_vlan(rule, &match); -+ -+ if (match.key->vlan_tpid != cpu_to_be16(ETH_P_8021Q)) -+ return -EOPNOTSUPP; -+ -+ data.vlan_in = match.key->vlan_id; -+ } -+ break; -+ case FLOW_DISSECTOR_KEY_IPV4_ADDRS: -+ offload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT; -+ break; -+ case FLOW_DISSECTOR_KEY_IPV6_ADDRS: -+ offload_type = MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T; -+ break; -+ default: -+ return -EOPNOTSUPP; -+ } -+ - flow_action_for_each(i, act, &rule->action) { - switch (act->id) { - case FLOW_ACTION_MANGLE: -+ if (offload_type == MTK_PPE_PKT_TYPE_BRIDGE) -+ return -EOPNOTSUPP; - if (act->mangle.htype == FLOW_ACT_MANGLE_HDR_TYPE_ETH) - mtk_flow_offload_mangle_eth(act, &data.eth); - break; -@@ -292,17 +330,6 @@ mtk_flow_offload_replace(struct mtk_eth - } - } - -- switch (addr_type) { -- case FLOW_DISSECTOR_KEY_IPV4_ADDRS: -- offload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT; -- break; -- case FLOW_DISSECTOR_KEY_IPV6_ADDRS: -- offload_type = MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T; -- break; -- default: -- return -EOPNOTSUPP; -- } -- - if (!is_valid_ether_addr(data.eth.h_source) || - !is_valid_ether_addr(data.eth.h_dest)) - return -EINVAL; -@@ -316,10 +343,13 @@ mtk_flow_offload_replace(struct mtk_eth - if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { - struct flow_match_ports ports; - -+ if (offload_type == MTK_PPE_PKT_TYPE_BRIDGE) -+ return -EOPNOTSUPP; -+ - flow_rule_match_ports(rule, &ports); - data.src_port = ports.key->src; - data.dst_port = ports.key->dst; -- } else { -+ } else if (offload_type != MTK_PPE_PKT_TYPE_BRIDGE) { - return -EOPNOTSUPP; - } - -@@ -349,6 +379,9 @@ mtk_flow_offload_replace(struct mtk_eth - if (act->id != FLOW_ACTION_MANGLE) - continue; - -+ if (offload_type == MTK_PPE_PKT_TYPE_BRIDGE) -+ return -EOPNOTSUPP; -+ - switch (act->mangle.htype) { - case FLOW_ACT_MANGLE_HDR_TYPE_TCP: - case FLOW_ACT_MANGLE_HDR_TYPE_UDP: -@@ -374,6 +407,9 @@ mtk_flow_offload_replace(struct mtk_eth - return err; - } - -+ if (offload_type == MTK_PPE_PKT_TYPE_BRIDGE) -+ foe.bridge.vlan = data.vlan_in; -+ - if (data.vlan.num == 1) { - if (data.vlan.proto != htons(ETH_P_8021Q)) - return -EOPNOTSUPP; diff --git a/target/linux/generic/pending-5.10/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-5.10/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch deleted file mode 100644 index a71cd92874..0000000000 --- a/target/linux/generic/pending-5.10/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: Felix Fietkau -Date: Mon, 21 Mar 2022 20:39:59 +0100 -Subject: [PATCH] net: ethernet: mtk_eth_soc: enable threaded NAPI - -This can improve performance under load by ensuring that NAPI processing is -not pinned on CPU 0. - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2200,8 +2200,8 @@ static irqreturn_t mtk_handle_irq_rx(int - - eth->rx_events++; - if (likely(napi_schedule_prep(ð->rx_napi))) { -- __napi_schedule(ð->rx_napi); - mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); -+ __napi_schedule(ð->rx_napi); - } - - return IRQ_HANDLED; -@@ -2213,8 +2213,8 @@ static irqreturn_t mtk_handle_irq_tx(int - - eth->tx_events++; - if (likely(napi_schedule_prep(ð->tx_napi))) { -- __napi_schedule(ð->tx_napi); - mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); -+ __napi_schedule(ð->tx_napi); - } - - return IRQ_HANDLED; -@@ -3325,6 +3325,8 @@ static int mtk_probe(struct platform_dev - * for NAPI to work - */ - init_dummy_netdev(ð->dummy_dev); -+ eth->dummy_dev.threaded = 1; -+ strcpy(eth->dummy_dev.name, "mtk_eth"); - netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, - MTK_NAPI_WEIGHT); - netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, diff --git a/target/linux/generic/pending-5.10/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-5.10/703-phy-add-detach-callback-to-struct-phy_driver.patch deleted file mode 100644 index 068ed323a9..0000000000 --- a/target/linux/generic/pending-5.10/703-phy-add-detach-callback-to-struct-phy_driver.patch +++ /dev/null @@ -1,38 +0,0 @@ -From: Gabor Juhos -Subject: generic: add detach callback to struct phy_driver - -lede-commit: fe61fc2d7d0b3fb348b502f68f98243b3ddf5867 - -Signed-off-by: Gabor Juhos ---- - drivers/net/phy/phy_device.c | 3 +++ - include/linux/phy.h | 6 ++++++ - 2 files changed, 9 insertions(+) - ---- a/drivers/net/phy/phy_device.c -+++ b/drivers/net/phy/phy_device.c -@@ -1652,6 +1652,9 @@ void phy_detach(struct phy_device *phyde - struct module *ndev_owner = NULL; - struct mii_bus *bus; - -+ if (phydev->drv && phydev->drv->detach) -+ phydev->drv->detach(phydev); -+ - if (phydev->sysfs_links) { - if (dev) - sysfs_remove_link(&dev->dev.kobj, "phydev"); ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -765,6 +765,12 @@ struct phy_driver { - /** @handle_interrupt: Override default interrupt handling */ - irqreturn_t (*handle_interrupt)(struct phy_device *phydev); - -+ /* -+ * Called before an ethernet device is detached -+ * from the PHY. -+ */ -+ void (*detach)(struct phy_device *phydev); -+ - /** @remove: Clears up any memory if needed */ - void (*remove)(struct phy_device *phydev); - diff --git a/target/linux/generic/pending-5.10/704-00-netfilter-flowtable-fix-excessive-hw-offload-attempt.patch b/target/linux/generic/pending-5.10/704-00-netfilter-flowtable-fix-excessive-hw-offload-attempt.patch deleted file mode 100644 index 67a72f825a..0000000000 --- a/target/linux/generic/pending-5.10/704-00-netfilter-flowtable-fix-excessive-hw-offload-attempt.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Felix Fietkau -Date: Fri, 6 May 2022 12:37:23 +0200 -Subject: [PATCH] netfilter: flowtable: fix excessive hw offload attempts - after failure - -If a flow cannot be offloaded, the code currently repeatedly tries again as -quickly as possible, which can significantly increase system load. -Fix this by limiting flow timeout update and hardware offload retry to once -per second. - -Signed-off-by: Felix Fietkau ---- - ---- a/net/netfilter/nf_flow_table_core.c -+++ b/net/netfilter/nf_flow_table_core.c -@@ -318,8 +318,10 @@ void flow_offload_refresh(struct nf_flow - u32 timeout; - - timeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow); -- if (READ_ONCE(flow->timeout) != timeout) -+ if (timeout - READ_ONCE(flow->timeout) > HZ) - WRITE_ONCE(flow->timeout, timeout); -+ else -+ return; - - if (likely(!nf_flowtable_hw_offload(flow_table))) - return; diff --git a/target/linux/generic/pending-5.10/704-01-netfilter-nft_flow_offload-skip-dst-neigh-lookup-for.patch b/target/linux/generic/pending-5.10/704-01-netfilter-nft_flow_offload-skip-dst-neigh-lookup-for.patch deleted file mode 100644 index 6683a53f76..0000000000 --- a/target/linux/generic/pending-5.10/704-01-netfilter-nft_flow_offload-skip-dst-neigh-lookup-for.patch +++ /dev/null @@ -1,64 +0,0 @@ -From: Felix Fietkau -Date: Fri, 6 May 2022 12:43:58 +0200 -Subject: [PATCH] netfilter: nft_flow_offload: skip dst neigh lookup for - ppp devices - -The dst entry does not contain a valid hardware address, so skip the lookup -in order to avoid running into errors here. -The proper hardware address is filled in from nft_dev_path_info - -Signed-off-by: Felix Fietkau ---- - ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -36,6 +36,15 @@ static void nft_default_forward_path(str - route->tuple[dir].xmit_type = nft_xmit_type(dst_cache); - } - -+static bool nft_is_valid_ether_device(const struct net_device *dev) -+{ -+ if (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER || -+ dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr)) -+ return false; -+ -+ return true; -+} -+ - static int nft_dev_fill_forward_path(const struct nf_flow_route *route, - const struct dst_entry *dst_cache, - const struct nf_conn *ct, -@@ -47,6 +56,9 @@ static int nft_dev_fill_forward_path(con - struct neighbour *n; - u8 nud_state; - -+ if (!nft_is_valid_ether_device(dev)) -+ goto out; -+ - n = dst_neigh_lookup(dst_cache, daddr); - if (!n) - return -1; -@@ -60,6 +72,7 @@ static int nft_dev_fill_forward_path(con - if (!(nud_state & NUD_VALID)) - return -1; - -+out: - return dev_fill_forward_path(dev, ha, stack); - } - -@@ -78,15 +91,6 @@ struct nft_forward_info { - enum flow_offload_xmit_type xmit_type; - }; - --static bool nft_is_valid_ether_device(const struct net_device *dev) --{ -- if (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER || -- dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr)) -- return false; -- -- return true; --} -- - static void nft_dev_path_info(const struct net_device_path_stack *stack, - struct nft_forward_info *info, - unsigned char *ha, struct nf_flowtable *flowtable) diff --git a/target/linux/generic/pending-5.10/704-02-net-fix-dev_fill_forward_path-with-pppoe-bridge.patch b/target/linux/generic/pending-5.10/704-02-net-fix-dev_fill_forward_path-with-pppoe-bridge.patch deleted file mode 100644 index c0660e50c4..0000000000 --- a/target/linux/generic/pending-5.10/704-02-net-fix-dev_fill_forward_path-with-pppoe-bridge.patch +++ /dev/null @@ -1,66 +0,0 @@ -From: Felix Fietkau -Date: Fri, 6 May 2022 13:54:44 +0200 -Subject: [PATCH] net: fix dev_fill_forward_path with pppoe + bridge - -When calling dev_fill_forward_path on a pppoe device, the provided destination -address is invalid. In order for the bridge fdb lookup to succeed, the pppoe -code needs to update ctx->daddr to the correct value. -Fix this by storing the address inside struct net_device_path_ctx - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c -@@ -91,7 +91,6 @@ mtk_flow_get_wdma_info(struct net_device - { - struct net_device_path_ctx ctx = { - .dev = dev, -- .daddr = addr, - }; - struct net_device_path path = {}; - -@@ -101,6 +100,7 @@ mtk_flow_get_wdma_info(struct net_device - if (!dev->netdev_ops->ndo_fill_forward_path) - return -1; - -+ memcpy(ctx.daddr, addr, sizeof(ctx.daddr)); - if (dev->netdev_ops->ndo_fill_forward_path(&ctx, &path)) - return -1; - ---- a/drivers/net/ppp/pppoe.c -+++ b/drivers/net/ppp/pppoe.c -@@ -988,6 +988,7 @@ static int pppoe_fill_forward_path(struc - path->encap.proto = htons(ETH_P_PPP_SES); - path->encap.id = be16_to_cpu(po->num); - memcpy(path->encap.h_dest, po->pppoe_pa.remote, ETH_ALEN); -+ memcpy(ctx->daddr, po->pppoe_pa.remote, ETH_ALEN); - path->dev = ctx->dev; - ctx->dev = dev; - ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -901,7 +901,7 @@ struct net_device_path_stack { - - struct net_device_path_ctx { - const struct net_device *dev; -- const u8 *daddr; -+ u8 daddr[ETH_ALEN]; - - int num_vlans; - struct { ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -863,11 +863,11 @@ int dev_fill_forward_path(const struct n - const struct net_device *last_dev; - struct net_device_path_ctx ctx = { - .dev = dev, -- .daddr = daddr, - }; - struct net_device_path *path; - int ret = 0; - -+ memcpy(ctx.daddr, daddr, sizeof(ctx.daddr)); - stack->num_paths = 0; - while (ctx.dev && ctx.dev->netdev_ops->ndo_fill_forward_path) { - last_dev = ctx.dev; diff --git a/target/linux/generic/pending-5.10/704-03-netfilter-nft_flow_offload-fix-offload-with-pppoe-vl.patch b/target/linux/generic/pending-5.10/704-03-netfilter-nft_flow_offload-fix-offload-with-pppoe-vl.patch deleted file mode 100644 index 1e0dc9957d..0000000000 --- a/target/linux/generic/pending-5.10/704-03-netfilter-nft_flow_offload-fix-offload-with-pppoe-vl.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: Felix Fietkau -Date: Fri, 6 May 2022 15:15:06 +0200 -Subject: [PATCH] netfilter: nft_flow_offload: fix offload with pppoe + - vlan - -When running a combination of PPPoE on top of a VLAN, we need to set -info->outdev to the PPPoE device, otherwise PPPoE encap is skipped -during software offload. - -Signed-off-by: Felix Fietkau ---- - ---- a/net/netfilter/nft_flow_offload.c -+++ b/net/netfilter/nft_flow_offload.c -@@ -123,7 +123,8 @@ static void nft_dev_path_info(const stru - info->indev = NULL; - break; - } -- info->outdev = path->dev; -+ if (!info->outdev) -+ info->outdev = path->dev; - info->encap[info->num_encaps].id = path->encap.id; - info->encap[info->num_encaps].proto = path->encap.proto; - info->num_encaps++; diff --git a/target/linux/generic/pending-5.10/705-net-dsa-tag_mtk-add-padding-for-tx-packets.patch b/target/linux/generic/pending-5.10/705-net-dsa-tag_mtk-add-padding-for-tx-packets.patch deleted file mode 100644 index 4f3af6c6b0..0000000000 --- a/target/linux/generic/pending-5.10/705-net-dsa-tag_mtk-add-padding-for-tx-packets.patch +++ /dev/null @@ -1,28 +0,0 @@ -From: Felix Fietkau -Date: Fri, 6 May 2022 21:38:42 +0200 -Subject: [PATCH] net: dsa: tag_mtk: add padding for tx packets - -Padding for transmitted packets needs to account for the special tag. -With not enough padding, garbage bytes are inserted by the switch at the -end of small packets. - -Fixes: 5cd8985a1909 ("net-next: dsa: add Mediatek tag RX/TX handler") -Signed-off-by: Felix Fietkau ---- - ---- a/net/dsa/tag_mtk.c -+++ b/net/dsa/tag_mtk.c -@@ -25,6 +25,13 @@ static struct sk_buff *mtk_tag_xmit(stru - u8 xmit_tpid; - u8 *mtk_tag; - -+ /* The Ethernet switch we are interfaced with needs packets to be at -+ * least 64 bytes (including FCS) otherwise their padding might be -+ * corrupted. With tags enabled, we need to make sure that packets are -+ * at least 68 bytes (including FCS and tag). -+ */ -+ eth_skb_pad(skb); -+ - /* Build the special tag after the MAC Source Address. If VLAN header - * is present, it's required that VLAN header and special tag is - * being combined. Only in this way we can allow the switch can parse diff --git a/target/linux/generic/pending-5.10/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch b/target/linux/generic/pending-5.10/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch deleted file mode 100644 index eb0478e0c6..0000000000 --- a/target/linux/generic/pending-5.10/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch +++ /dev/null @@ -1,177 +0,0 @@ -From: Felix Fietkau -Date: Fri, 27 Aug 2021 12:22:32 +0200 -Subject: [PATCH] bridge: add knob for filtering rx/tx BPDU packets on a port - -Some devices (e.g. wireless APs) can't have devices behind them be part of -a bridge topology with redundant links, due to address limitations. -Additionally, broadcast traffic on these devices is somewhat expensive, due to -the low data rate and wakeups of clients in powersave mode. -This knob can be used to ensure that BPDU packets are never sent or forwarded -to/from these devices - -Signed-off-by: Felix Fietkau ---- - ---- a/include/linux/if_bridge.h -+++ b/include/linux/if_bridge.h -@@ -56,6 +56,7 @@ struct br_ip_list { - #define BR_MRP_AWARE BIT(17) - #define BR_MRP_LOST_CONT BIT(18) - #define BR_MRP_LOST_IN_CONT BIT(19) -+#define BR_BPDU_FILTER BIT(20) - - #define BR_DEFAULT_AGEING_TIME (300 * HZ) - ---- a/net/bridge/br_forward.c -+++ b/net/bridge/br_forward.c -@@ -191,6 +191,7 @@ out: - void br_flood(struct net_bridge *br, struct sk_buff *skb, - enum br_pkt_type pkt_type, bool local_rcv, bool local_orig) - { -+ const unsigned char *dest = eth_hdr(skb)->h_dest; - struct net_bridge_port *prev = NULL; - struct net_bridge_port *p; - -@@ -206,6 +207,10 @@ void br_flood(struct net_bridge *br, str - case BR_PKT_MULTICAST: - if (!(p->flags & BR_MCAST_FLOOD) && skb->dev != br->dev) - continue; -+ if ((p->flags & BR_BPDU_FILTER) && -+ unlikely(is_link_local_ether_addr(dest) && -+ dest[5] == 0)) -+ continue; - break; - case BR_PKT_BROADCAST: - if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev) ---- a/net/bridge/br_input.c -+++ b/net/bridge/br_input.c -@@ -312,6 +312,8 @@ static rx_handler_result_t br_handle_fra - fwd_mask |= p->group_fwd_mask; - switch (dest[5]) { - case 0x00: /* Bridge Group Address */ -+ if (p->flags & BR_BPDU_FILTER) -+ goto drop; - /* If STP is turned off, - then must forward to keep loop detection */ - if (p->br->stp_enabled == BR_NO_STP || ---- a/net/bridge/br_sysfs_if.c -+++ b/net/bridge/br_sysfs_if.c -@@ -233,6 +233,7 @@ BRPORT_ATTR_FLAG(multicast_flood, BR_MCA - BRPORT_ATTR_FLAG(broadcast_flood, BR_BCAST_FLOOD); - BRPORT_ATTR_FLAG(neigh_suppress, BR_NEIGH_SUPPRESS); - BRPORT_ATTR_FLAG(isolated, BR_ISOLATED); -+BRPORT_ATTR_FLAG(bpdu_filter, BR_BPDU_FILTER); - - #ifdef CONFIG_BRIDGE_IGMP_SNOOPING - static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf) -@@ -285,6 +286,7 @@ static const struct brport_attribute *br - &brport_attr_group_fwd_mask, - &brport_attr_neigh_suppress, - &brport_attr_isolated, -+ &brport_attr_bpdu_filter, - &brport_attr_backup_port, - NULL - }; ---- a/net/bridge/br_stp_bpdu.c -+++ b/net/bridge/br_stp_bpdu.c -@@ -80,7 +80,8 @@ void br_send_config_bpdu(struct net_brid - { - unsigned char buf[35]; - -- if (p->br->stp_enabled != BR_KERNEL_STP) -+ if (p->br->stp_enabled != BR_KERNEL_STP || -+ (p->flags & BR_BPDU_FILTER)) - return; - - buf[0] = 0; -@@ -127,7 +128,8 @@ void br_send_tcn_bpdu(struct net_bridge_ - { - unsigned char buf[4]; - -- if (p->br->stp_enabled != BR_KERNEL_STP) -+ if (p->br->stp_enabled != BR_KERNEL_STP || -+ (p->flags & BR_BPDU_FILTER)) - return; - - buf[0] = 0; -@@ -172,6 +174,9 @@ void br_stp_rcv(const struct stp_proto * - if (!(br->dev->flags & IFF_UP)) - goto out; - -+ if (p->flags & BR_BPDU_FILTER) -+ goto out; -+ - if (p->state == BR_STATE_DISABLED) - goto out; - ---- a/include/uapi/linux/if_link.h -+++ b/include/uapi/linux/if_link.h -@@ -524,6 +524,7 @@ enum { - IFLA_BRPORT_BACKUP_PORT, - IFLA_BRPORT_MRP_RING_OPEN, - IFLA_BRPORT_MRP_IN_OPEN, -+ IFLA_BRPORT_BPDU_FILTER, - __IFLA_BRPORT_MAX - }; - #define IFLA_BRPORT_MAX (__IFLA_BRPORT_MAX - 1) ---- a/net/bridge/br_netlink.c -+++ b/net/bridge/br_netlink.c -@@ -137,6 +137,7 @@ static inline size_t br_port_info_size(v - + nla_total_size(1) /* IFLA_BRPORT_VLAN_TUNNEL */ - + nla_total_size(1) /* IFLA_BRPORT_NEIGH_SUPPRESS */ - + nla_total_size(1) /* IFLA_BRPORT_ISOLATED */ -+ + nla_total_size(1) /* IFLA_BRPORT_BPDU_FILTER */ - + nla_total_size(sizeof(struct ifla_bridge_id)) /* IFLA_BRPORT_ROOT_ID */ - + nla_total_size(sizeof(struct ifla_bridge_id)) /* IFLA_BRPORT_BRIDGE_ID */ - + nla_total_size(sizeof(u16)) /* IFLA_BRPORT_DESIGNATED_PORT */ -@@ -220,7 +221,8 @@ static int br_port_fill_attrs(struct sk_ - BR_MRP_LOST_CONT)) || - nla_put_u8(skb, IFLA_BRPORT_MRP_IN_OPEN, - !!(p->flags & BR_MRP_LOST_IN_CONT)) || -- nla_put_u8(skb, IFLA_BRPORT_ISOLATED, !!(p->flags & BR_ISOLATED))) -+ nla_put_u8(skb, IFLA_BRPORT_ISOLATED, !!(p->flags & BR_ISOLATED)) || -+ nla_put_u8(skb, IFLA_BRPORT_BPDU_FILTER, !!(p->flags & BR_BPDU_FILTER))) - return -EMSGSIZE; - - timerval = br_timer_value(&p->message_age_timer); -@@ -728,6 +730,7 @@ static const struct nla_policy br_port_p - [IFLA_BRPORT_NEIGH_SUPPRESS] = { .type = NLA_U8 }, - [IFLA_BRPORT_ISOLATED] = { .type = NLA_U8 }, - [IFLA_BRPORT_BACKUP_PORT] = { .type = NLA_U32 }, -+ [IFLA_BRPORT_BPDU_FILTER] = { .type = NLA_U8 }, - }; - - /* Change the state of the port and notify spanning tree */ -@@ -826,6 +829,10 @@ static int br_setport(struct net_bridge_ - if (err) - return err; - -+ err = br_set_port_flag(p, tb, IFLA_BRPORT_BPDU_FILTER, BR_BPDU_FILTER); -+ if (err) -+ return err; -+ - br_vlan_tunnel_old = (p->flags & BR_VLAN_TUNNEL) ? true : false; - err = br_set_port_flag(p, tb, IFLA_BRPORT_VLAN_TUNNEL, BR_VLAN_TUNNEL); - if (err) ---- a/net/core/rtnetlink.c -+++ b/net/core/rtnetlink.c -@@ -55,7 +55,7 @@ - #include - - #define RTNL_MAX_TYPE 50 --#define RTNL_SLAVE_MAX_TYPE 36 -+#define RTNL_SLAVE_MAX_TYPE 37 - - struct rtnl_link { - rtnl_doit_func doit; -@@ -4684,7 +4684,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu - brport_nla_put_flag(skb, flags, mask, - IFLA_BRPORT_MCAST_FLOOD, BR_MCAST_FLOOD) || - brport_nla_put_flag(skb, flags, mask, -- IFLA_BRPORT_BCAST_FLOOD, BR_BCAST_FLOOD)) { -+ IFLA_BRPORT_BCAST_FLOOD, BR_BCAST_FLOOD) || -+ brport_nla_put_flag(skb, flags, mask, -+ IFLA_BRPORT_BPDU_FILTER, BR_BPDU_FILTER)) { - nla_nest_cancel(skb, protinfo); - goto nla_put_failure; - } diff --git a/target/linux/generic/pending-5.10/750-skb-Do-mix-page-pool-and-page-referenced-frags-in-GR.patch b/target/linux/generic/pending-5.10/750-skb-Do-mix-page-pool-and-page-referenced-frags-in-GR.patch deleted file mode 100644 index d669a5dd1f..0000000000 --- a/target/linux/generic/pending-5.10/750-skb-Do-mix-page-pool-and-page-referenced-frags-in-GR.patch +++ /dev/null @@ -1,35 +0,0 @@ -From: Alexander Duyck -Date: Thu, 26 Jan 2023 11:06:59 -0800 -Subject: [PATCH] skb: Do mix page pool and page referenced frags in GRO - -GSO should not merge page pool recycled frames with standard reference -counted frames. Traditionally this didn't occur, at least not often. -However as we start looking at adding support for wireless adapters there -becomes the potential to mix the two due to A-MSDU repartitioning frames in -the receive path. There are possibly other places where this may have -occurred however I suspect they must be few and far between as we have not -seen this issue until now. - -Fixes: 53e0961da1c7 ("page_pool: add frag page recycling support in page pool") -Reported-by: Felix Fietkau -Signed-off-by: Alexander Duyck ---- - ---- a/net/core/skbuff.c -+++ b/net/core/skbuff.c -@@ -4164,6 +4164,15 @@ int skb_gro_receive(struct sk_buff *p, s - if (unlikely(p->len + len >= 65536 || NAPI_GRO_CB(skb)->flush)) - return -E2BIG; - -+ /* Do not splice page pool based packets w/ non-page pool -+ * packets. This can result in reference count issues as page -+ * pool pages will not decrement the reference count and will -+ * instead be immediately returned to the pool or have frag -+ * count decremented. -+ */ -+ if (p->pp_recycle != skb->pp_recycle) -+ return -ETOOMANYREFS; -+ - lp = NAPI_GRO_CB(p)->last; - pinfo = skb_shinfo(lp); - diff --git a/target/linux/generic/pending-5.10/760-net-dsa-mv88e6xxx-fix-vlan-setup.patch b/target/linux/generic/pending-5.10/760-net-dsa-mv88e6xxx-fix-vlan-setup.patch deleted file mode 100644 index 9c3b81fefb..0000000000 --- a/target/linux/generic/pending-5.10/760-net-dsa-mv88e6xxx-fix-vlan-setup.patch +++ /dev/null @@ -1,27 +0,0 @@ -From a1b291f3f6c80a6c5ccad7283fc472d77a2a4763 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Sun, 22 Dec 2019 12:40:11 +0000 -Subject: [PATCH] net: dsa: mv88e6xxx: fix vlan setup - -Provide an option that drivers can set to indicate they want to receive -vlan configuration even when vlan filtering is disabled. This is safe -for Marvell DSA bridges, which do not look up ingress traffic in the -VTU if the port is in 8021Q disabled state. Whether this change is -suitable for all DSA bridges is not known. - -Signed-off-by: Russell King -Signed-off-by: DENG Qingfang ---- - drivers/net/dsa/mv88e6xxx/chip.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/dsa/mv88e6xxx/chip.c -+++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -2934,6 +2934,7 @@ static int mv88e6xxx_setup(struct dsa_sw - - chip->ds = ds; - ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); -+ ds->configure_vlan_while_not_filtering = true; - - mv88e6xxx_reg_lock(chip); - diff --git a/target/linux/generic/pending-5.10/762-net-bridge-switchdev-Refactor-br_switchdev_fdb_notif.patch b/target/linux/generic/pending-5.10/762-net-bridge-switchdev-Refactor-br_switchdev_fdb_notif.patch deleted file mode 100644 index fbc8342b0e..0000000000 --- a/target/linux/generic/pending-5.10/762-net-bridge-switchdev-Refactor-br_switchdev_fdb_notif.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 46fe6cecb296d850c1ee2b333e57093ac4b733f3 Mon Sep 17 00:00:00 2001 -From: Tobias Waldekranz -Date: Sat, 16 Jan 2021 02:25:09 +0100 -Subject: [PATCH] net: bridge: switchdev: Refactor br_switchdev_fdb_notify - -Instead of having to add more and more arguments to -br_switchdev_fdb_call_notifiers, get rid of it and build the info -struct directly in br_switchdev_fdb_notify. - -Signed-off-by: Tobias Waldekranz -Reviewed-by: Vladimir Oltean ---- - net/bridge/br_switchdev.c | 41 +++++++++++---------------------------- - 1 file changed, 11 insertions(+), 30 deletions(-) - ---- a/net/bridge/br_switchdev.c -+++ b/net/bridge/br_switchdev.c -@@ -102,25 +102,16 @@ int br_switchdev_set_port_flag(struct ne - return 0; - } - --static void --br_switchdev_fdb_call_notifiers(bool adding, const unsigned char *mac, -- u16 vid, struct net_device *dev, -- bool added_by_user, bool offloaded) --{ -- struct switchdev_notifier_fdb_info info; -- unsigned long notifier_type; -- -- info.addr = mac; -- info.vid = vid; -- info.added_by_user = added_by_user; -- info.offloaded = offloaded; -- notifier_type = adding ? SWITCHDEV_FDB_ADD_TO_DEVICE : SWITCHDEV_FDB_DEL_TO_DEVICE; -- call_switchdev_notifiers(notifier_type, dev, &info.info, NULL); --} -- - void - br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb, int type) - { -+ struct switchdev_notifier_fdb_info info = { -+ .addr = fdb->key.addr.addr, -+ .vid = fdb->key.vlan_id, -+ .added_by_user = test_bit(BR_FDB_ADDED_BY_USER, &fdb->flags), -+ .offloaded = test_bit(BR_FDB_OFFLOADED, &fdb->flags), -+ }; -+ - if (!fdb->dst) - return; - if (test_bit(BR_FDB_LOCAL, &fdb->flags)) -@@ -128,22 +119,12 @@ br_switchdev_fdb_notify(const struct net - - switch (type) { - case RTM_DELNEIGH: -- br_switchdev_fdb_call_notifiers(false, fdb->key.addr.addr, -- fdb->key.vlan_id, -- fdb->dst->dev, -- test_bit(BR_FDB_ADDED_BY_USER, -- &fdb->flags), -- test_bit(BR_FDB_OFFLOADED, -- &fdb->flags)); -+ call_switchdev_notifiers(SWITCHDEV_FDB_DEL_TO_DEVICE, -+ fdb->dst->dev, &info.info, NULL); - break; - case RTM_NEWNEIGH: -- br_switchdev_fdb_call_notifiers(true, fdb->key.addr.addr, -- fdb->key.vlan_id, -- fdb->dst->dev, -- test_bit(BR_FDB_ADDED_BY_USER, -- &fdb->flags), -- test_bit(BR_FDB_OFFLOADED, -- &fdb->flags)); -+ call_switchdev_notifiers(SWITCHDEV_FDB_ADD_TO_DEVICE, -+ fdb->dst->dev, &info.info, NULL); - break; - } - } diff --git a/target/linux/generic/pending-5.10/763-net-bridge-switchdev-Include-local-flag-in-FDB-notif.patch b/target/linux/generic/pending-5.10/763-net-bridge-switchdev-Include-local-flag-in-FDB-notif.patch deleted file mode 100644 index 434288c3ef..0000000000 --- a/target/linux/generic/pending-5.10/763-net-bridge-switchdev-Include-local-flag-in-FDB-notif.patch +++ /dev/null @@ -1,42 +0,0 @@ -From ec5be4f79026282925ae383caa431a8d41e3456a Mon Sep 17 00:00:00 2001 -From: Tobias Waldekranz -Date: Sat, 16 Jan 2021 02:25:10 +0100 -Subject: [PATCH] net: bridge: switchdev: Include local flag in FDB - notifications - -Some switchdev drivers, notably DSA, ignore all dynamically learned -address notifications (!added_by_user) as these are autonomously added -by the switch. Previously, such a notification was indistinguishable -from a local address notification. Include a local bit in the -notification so that the two classes can be discriminated. - -This allows DSA-like devices to add local addresses to the hardware -FDB (with the CPU as the destination), thereby avoiding flows towards -the CPU being flooded by the switch as unknown unicast. - -Signed-off-by: Tobias Waldekranz ---- - include/net/switchdev.h | 1 + - net/bridge/br_switchdev.c | 1 + - 2 files changed, 2 insertions(+) - ---- a/include/net/switchdev.h -+++ b/include/net/switchdev.h -@@ -226,6 +226,7 @@ struct switchdev_notifier_fdb_info { - const unsigned char *addr; - u16 vid; - u8 added_by_user:1, -+ local:1, - offloaded:1; - }; - ---- a/net/bridge/br_switchdev.c -+++ b/net/bridge/br_switchdev.c -@@ -109,6 +109,7 @@ br_switchdev_fdb_notify(const struct net - .addr = fdb->key.addr.addr, - .vid = fdb->key.vlan_id, - .added_by_user = test_bit(BR_FDB_ADDED_BY_USER, &fdb->flags), -+ .local = test_bit(BR_FDB_LOCAL, &fdb->flags), - .offloaded = test_bit(BR_FDB_OFFLOADED, &fdb->flags), - }; - diff --git a/target/linux/generic/pending-5.10/764-net-bridge-switchdev-Send-FDB-notifications-for-host.patch b/target/linux/generic/pending-5.10/764-net-bridge-switchdev-Send-FDB-notifications-for-host.patch deleted file mode 100644 index 630e03bbfd..0000000000 --- a/target/linux/generic/pending-5.10/764-net-bridge-switchdev-Send-FDB-notifications-for-host.patch +++ /dev/null @@ -1,96 +0,0 @@ -From 2e50fd9322047253c327550b4485cf8761035a8c Mon Sep 17 00:00:00 2001 -From: Tobias Waldekranz -Date: Sat, 16 Jan 2021 02:25:11 +0100 -Subject: [PATCH] net: bridge: switchdev: Send FDB notifications for host - addresses - -Treat addresses added to the bridge itself in the same way as regular -ports and send out a notification so that drivers may sync it down to -the hardware FDB. - -Signed-off-by: Tobias Waldekranz ---- - net/bridge/br_fdb.c | 4 ++-- - net/bridge/br_private.h | 7 ++++--- - net/bridge/br_switchdev.c | 11 +++++------ - 3 files changed, 11 insertions(+), 11 deletions(-) - ---- a/net/bridge/br_fdb.c -+++ b/net/bridge/br_fdb.c -@@ -602,7 +602,7 @@ void br_fdb_update(struct net_bridge *br - /* fastpath: update of existing entry */ - if (unlikely(source != fdb->dst && - !test_bit(BR_FDB_STICKY, &fdb->flags))) { -- br_switchdev_fdb_notify(fdb, RTM_DELNEIGH); -+ br_switchdev_fdb_notify(br, fdb, RTM_DELNEIGH); - fdb->dst = source; - fdb_modified = true; - /* Take over HW learned entry */ -@@ -735,7 +735,7 @@ static void fdb_notify(struct net_bridge - int err = -ENOBUFS; - - if (swdev_notify) -- br_switchdev_fdb_notify(fdb, type); -+ br_switchdev_fdb_notify(br, fdb, type); - - skb = nlmsg_new(fdb_nlmsg_size(), GFP_ATOMIC); - if (skb == NULL) ---- a/net/bridge/br_private.h -+++ b/net/bridge/br_private.h -@@ -1525,8 +1525,8 @@ bool nbp_switchdev_allowed_egress(const - int br_switchdev_set_port_flag(struct net_bridge_port *p, - unsigned long flags, - unsigned long mask); --void br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb, -- int type); -+void br_switchdev_fdb_notify(struct net_bridge *br, -+ const struct net_bridge_fdb_entry *fdb, int type); - int br_switchdev_port_vlan_add(struct net_device *dev, u16 vid, u16 flags, - struct netlink_ext_ack *extack); - int br_switchdev_port_vlan_del(struct net_device *dev, u16 vid); -@@ -1572,7 +1572,8 @@ static inline int br_switchdev_port_vlan - } - - static inline void --br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb, int type) -+br_switchdev_fdb_notify(struct net_bridge *br, -+ const struct net_bridge_fdb_entry *fdb, int type) - { - } - ---- a/net/bridge/br_switchdev.c -+++ b/net/bridge/br_switchdev.c -@@ -103,7 +103,8 @@ int br_switchdev_set_port_flag(struct ne - } - - void --br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb, int type) -+br_switchdev_fdb_notify(struct net_bridge *br, -+ const struct net_bridge_fdb_entry *fdb, int type) - { - struct switchdev_notifier_fdb_info info = { - .addr = fdb->key.addr.addr, -@@ -112,20 +113,19 @@ br_switchdev_fdb_notify(const struct net - .local = test_bit(BR_FDB_LOCAL, &fdb->flags), - .offloaded = test_bit(BR_FDB_OFFLOADED, &fdb->flags), - }; -+ struct net_device *dev = fdb->dst ? fdb->dst->dev : br->dev; - -- if (!fdb->dst) -- return; - if (test_bit(BR_FDB_LOCAL, &fdb->flags)) - return; - - switch (type) { - case RTM_DELNEIGH: - call_switchdev_notifiers(SWITCHDEV_FDB_DEL_TO_DEVICE, -- fdb->dst->dev, &info.info, NULL); -+ dev, &info.info, NULL); - break; - case RTM_NEWNEIGH: - call_switchdev_notifiers(SWITCHDEV_FDB_ADD_TO_DEVICE, -- fdb->dst->dev, &info.info, NULL); -+ dev, &info.info, NULL); - break; - } - } diff --git a/target/linux/generic/pending-5.10/765-net-dsa-Include-local-addresses-in-assisted-CPU-port.patch b/target/linux/generic/pending-5.10/765-net-dsa-Include-local-addresses-in-assisted-CPU-port.patch deleted file mode 100644 index c0b4fd1d14..0000000000 --- a/target/linux/generic/pending-5.10/765-net-dsa-Include-local-addresses-in-assisted-CPU-port.patch +++ /dev/null @@ -1,36 +0,0 @@ -From dd082716b43a3684b2f473ae5d1e76d1c076d86d Mon Sep 17 00:00:00 2001 -From: Tobias Waldekranz -Date: Sat, 16 Jan 2021 02:25:12 +0100 -Subject: [PATCH] net: dsa: Include local addresses in assisted CPU port - learning - -Add local addresses (i.e. the ports' MAC addresses) to the hardware -FDB when assisted CPU port learning is enabled. - -NOTE: The bridge's own MAC address is also "local". If that address is -not shared with any port, the bridge's MAC is not be added by this -functionality - but the following commit takes care of that case. - -Signed-off-by: Tobias Waldekranz ---- - net/dsa/slave.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -2192,10 +2192,12 @@ static int dsa_slave_switchdev_event(str - fdb_info = ptr; - - if (dsa_slave_dev_check(dev)) { -- if (!fdb_info->added_by_user) -- return NOTIFY_OK; -- - dp = dsa_slave_to_port(dev); -+ -+ if (fdb_info->local && dp->ds->assisted_learning_on_cpu_port) -+ dp = dp->cpu_dp; -+ else if (!fdb_info->added_by_user) -+ return NOTIFY_OK; - } else { - /* Snoop addresses learnt on foreign interfaces - * bridged with us, for switches that don't diff --git a/target/linux/generic/pending-5.10/766-net-dsa-Include-bridge-addresses-in-assisted-CPU-por.patch b/target/linux/generic/pending-5.10/766-net-dsa-Include-bridge-addresses-in-assisted-CPU-por.patch deleted file mode 100644 index 0b644d8300..0000000000 --- a/target/linux/generic/pending-5.10/766-net-dsa-Include-bridge-addresses-in-assisted-CPU-por.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 0663ebde114a6fb2c28c622ba5212b302d4d2581 Mon Sep 17 00:00:00 2001 -From: Tobias Waldekranz -Date: Sat, 16 Jan 2021 02:25:13 +0100 -Subject: [PATCH] net: dsa: Include bridge addresses in assisted CPU port - learning - -Now that notifications are sent out for addresses added to the bridge -itself, extend DSA to include those addresses in the hardware FDB when -assisted CPU port learning is enabled. - -Signed-off-by: Tobias Waldekranz ---- - net/dsa/slave.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -2206,7 +2206,11 @@ static int dsa_slave_switchdev_event(str - struct net_device *br_dev; - struct dsa_slave_priv *p; - -- br_dev = netdev_master_upper_dev_get_rcu(dev); -+ if (netif_is_bridge_master(dev)) -+ br_dev = dev; -+ else -+ br_dev = netdev_master_upper_dev_get_rcu(dev); -+ - if (!br_dev) - return NOTIFY_DONE; - diff --git a/target/linux/generic/pending-5.10/767-net-dsa-Sync-static-FDB-entries-on-foreign-interface.patch b/target/linux/generic/pending-5.10/767-net-dsa-Sync-static-FDB-entries-on-foreign-interface.patch deleted file mode 100644 index f71ea16b97..0000000000 --- a/target/linux/generic/pending-5.10/767-net-dsa-Sync-static-FDB-entries-on-foreign-interface.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 81e39fd78db82fb51b05fff309b9c521f1a0bc5a Mon Sep 17 00:00:00 2001 -From: Tobias Waldekranz -Date: Sat, 16 Jan 2021 02:25:14 +0100 -Subject: [PATCH] net: dsa: Sync static FDB entries on foreign interfaces to - hardware - -Reuse the "assisted_learning_on_cpu_port" functionality to always add -entries for user-configured entries on foreign interfaces, even if -assisted_learning_on_cpu_port is not enabled. E.g. in this situation: - - br0 - / \ -swp0 dummy0 - -$ bridge fdb add 02:00:de:ad:00:01 dev dummy0 vlan 1 master - -Results in DSA adding an entry in the hardware FDB, pointing this -address towards the CPU port. - -The same is true for entries added to the bridge itself, e.g: - -$ bridge fdb add 02:00:de:ad:00:01 dev br0 vlan 1 self - -Signed-off-by: Tobias Waldekranz ---- - net/dsa/slave.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -2199,9 +2199,12 @@ static int dsa_slave_switchdev_event(str - else if (!fdb_info->added_by_user) - return NOTIFY_OK; - } else { -- /* Snoop addresses learnt on foreign interfaces -- * bridged with us, for switches that don't -- * automatically learn SA from CPU-injected traffic -+ /* Snoop addresses added to foreign interfaces -+ * bridged with us, or the bridge -+ * itself. Dynamically learned addresses can -+ * also be added for switches that don't -+ * automatically learn SA from CPU-injected -+ * traffic. - */ - struct net_device *br_dev; - struct dsa_slave_priv *p; -@@ -2223,7 +2226,8 @@ static int dsa_slave_switchdev_event(str - - dp = p->dp->cpu_dp; - -- if (!dp->ds->assisted_learning_on_cpu_port) -+ if (!fdb_info->added_by_user && -+ !dp->ds->assisted_learning_on_cpu_port) - return NOTIFY_DONE; - } - diff --git a/target/linux/generic/pending-5.10/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-5.10/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch deleted file mode 100644 index 07a166125b..0000000000 --- a/target/linux/generic/pending-5.10/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Tobias Waldekranz -Subject: [RFC net-next 7/7] net: dsa: mv88e6xxx: Request assisted learning on CPU port -Date: Sat, 16 Jan 2021 02:25:15 +0100 -Archived-At: - -While the hardware is capable of performing learning on the CPU port, -it requires alot of additions to the bridge's forwarding path in order -to handle multi-destination traffic correctly. - -Until that is in place, opt for the next best thing and let DSA sync -the relevant addresses down to the hardware FDB. - -Signed-off-by: Tobias Waldekranz ---- - drivers/net/dsa/mv88e6xxx/chip.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/dsa/mv88e6xxx/chip.c -+++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -5503,6 +5503,7 @@ static int mv88e6xxx_register_switch(str - ds->ops = &mv88e6xxx_switch_ops; - ds->ageing_time_min = chip->info->age_time_coeff; - ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; -+ ds->assisted_learning_on_cpu_port = true; - - dev_set_drvdata(dev, ds); - diff --git a/target/linux/generic/pending-5.10/780-ARM-kirkwood-add-missing-linux-if_ether.h-for-ETH_AL.patch b/target/linux/generic/pending-5.10/780-ARM-kirkwood-add-missing-linux-if_ether.h-for-ETH_AL.patch deleted file mode 100644 index fcf7892c04..0000000000 --- a/target/linux/generic/pending-5.10/780-ARM-kirkwood-add-missing-linux-if_ether.h-for-ETH_AL.patch +++ /dev/null @@ -1,61 +0,0 @@ -From patchwork Thu Aug 5 22:23:30 2021 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 12422209 -Date: Thu, 5 Aug 2021 23:23:30 +0100 -From: Daniel Golle -To: linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, - linux-kernel@vger.kernel.org -Cc: "David S. Miller" , Andrew Lunn , - Michael Walle -Subject: [PATCH] ARM: kirkwood: add missing for ETH_ALEN -Message-ID: -MIME-Version: 1.0 -Content-Disposition: inline -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Archive: -Sender: "linux-arm-kernel" - -After commit 83216e3988cd1 ("of: net: pass the dst buffer to -of_get_mac_address()") build fails for kirkwood as ETH_ALEN is not -defined. - -arch/arm/mach-mvebu/kirkwood.c: In function 'kirkwood_dt_eth_fixup': -arch/arm/mach-mvebu/kirkwood.c:87:13: error: 'ETH_ALEN' undeclared (first use in this function); did you mean 'ESTALE'? - u8 tmpmac[ETH_ALEN]; - ^~~~~~~~ - ESTALE -arch/arm/mach-mvebu/kirkwood.c:87:13: note: each undeclared identifier is reported only once for each function it appears in -arch/arm/mach-mvebu/kirkwood.c:87:6: warning: unused variable 'tmpmac' [-Wunused-variable] - u8 tmpmac[ETH_ALEN]; - ^~~~~~ -make[5]: *** [scripts/Makefile.build:262: arch/arm/mach-mvebu/kirkwood.o] Error 1 -make[5]: *** Waiting for unfinished jobs.... - -Add missing #include to fix this. - -Cc: David S. Miller -Cc: Andrew Lunn -Cc: Michael Walle -Reported-by: https://buildbot.openwrt.org/master/images/#/builders/56/builds/220/steps/44/logs/stdio -Fixes: 83216e3988cd1 ("of: net: pass the dst buffer to of_get_mac_address()") -Signed-off-by: Daniel Golle ---- - arch/arm/mach-mvebu/kirkwood.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-mvebu/kirkwood.c -+++ b/arch/arm/mach-mvebu/kirkwood.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include diff --git a/target/linux/generic/pending-5.10/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch b/target/linux/generic/pending-5.10/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch deleted file mode 100644 index 511a9f7555..0000000000 --- a/target/linux/generic/pending-5.10/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch +++ /dev/null @@ -1,64 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Subject: [PATCH] bcma: get SoC device struct & copy its DMA params to the - subdevices -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -For bus devices to be fully usable it's required to set their DMA -parameters. - -For years it has been missing and remained unnoticed because of -mips_dma_alloc_coherent() silently handling the empty coherent_dma_mask. -Kernel 4.19 came with a lot of DMA changes and caused a regression on -the bcm47xx. Starting with the commit f8c55dc6e828 ("MIPS: use generic -dma noncoherent ops for simple noncoherent platforms") DMA coherent -allocations just fail. Example: -[ 1.114914] bgmac_bcma bcma0:2: Allocation of TX ring 0x200 failed -[ 1.121215] bgmac_bcma bcma0:2: Unable to alloc memory for DMA -[ 1.127626] bgmac_bcma: probe of bcma0:2 failed with error -12 -[ 1.133838] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded - -This change fixes above regression in addition to the MIPS bcm47xx -commit 321c46b91550 ("MIPS: BCM47XX: Setup struct device for the SoC"). - -It also fixes another *old* GPIO regression caused by a parent pointing -to the NULL: -[ 0.157054] missing gpiochip .dev parent pointer -[ 0.157287] bcma: bus0: Error registering GPIO driver: -22 -introduced by the commit 74f4e0cc6108 ("bcma: switch GPIO portions to -use GPIOLIB_IRQCHIP"). - -Fixes: f8c55dc6e828 ("MIPS: use generic dma noncoherent ops for simple noncoherent platforms") -Fixes: 74f4e0cc6108 ("bcma: switch GPIO portions to use GPIOLIB_IRQCHIP") -Cc: linux-mips@linux-mips.org -Cc: Christoph Hellwig -Cc: Linus Walleij -Signed-off-by: Rafał Miłecki ---- - ---- a/drivers/bcma/host_soc.c -+++ b/drivers/bcma/host_soc.c -@@ -191,6 +191,8 @@ int __init bcma_host_soc_init(struct bcm - struct bcma_bus *bus = &soc->bus; - int err; - -+ bus->dev = soc->dev; -+ - /* Scan bus and initialize it */ - err = bcma_bus_early_register(bus); - if (err) ---- a/drivers/bcma/main.c -+++ b/drivers/bcma/main.c -@@ -241,8 +241,10 @@ void bcma_prepare_core(struct bcma_bus * - core->dev.bus = &bcma_bus_type; - dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index); - core->dev.parent = bus->dev; -- if (bus->dev) -+ if (bus->dev) { - bcma_of_fill_device(bus->dev, core); -+ dma_coerce_mask_and_coherent(&core->dev, bus->dev->coherent_dma_mask); -+ } - - switch (bus->hosttype) { - case BCMA_HOSTTYPE_PCI: diff --git a/target/linux/generic/pending-5.10/801-gpio-gpio-cascade-add-generic-GPIO-cascade.patch b/target/linux/generic/pending-5.10/801-gpio-gpio-cascade-add-generic-GPIO-cascade.patch deleted file mode 100644 index af44ff24ac..0000000000 --- a/target/linux/generic/pending-5.10/801-gpio-gpio-cascade-add-generic-GPIO-cascade.patch +++ /dev/null @@ -1,222 +0,0 @@ -From fc23ea48ba52c24f201fe5ca0132ee1a3de5a70a Mon Sep 17 00:00:00 2001 -From: Mauri Sandberg -Date: Thu, 25 Mar 2021 11:48:05 +0200 -Subject: [PATCH 2/2] gpio: gpio-cascade: add generic GPIO cascade - -Adds support for building cascades of GPIO lines. That is, it allows -setups when there is one upstream line and multiple cascaded lines, out -of which one can be chosen at a time. The status of the upstream line -can be conveyed to the selected cascaded line or, vice versa, the status -of the cascaded line can be conveyed to the upstream line. - -A multiplexer is being used to select, which cascaded GPIO line is being -used at any given time. - -At the moment only input direction is supported. In future it should be -possible to add support for output direction, too. - -Signed-off-by: Mauri Sandberg -Reviewed-by: Linus Walleij -Reviewed-by: Andy Shevchenko ---- -v7 -> v8: - - rearrange members in struct gpio_cascade - - cosmetic changes in file header and in one function declaration - - added Reviewed-by tags by Linus and Andy -v6 -> v7: - - In Kconfig add info about module name - - adhere to new convention that allows lines longer than 80 chars - - use dev_probe_err with upstream gpio line too - - refactor for cleaner exit of probe function. -v5 -> v6: - - In Kconfig, remove dependency to OF_GPIO and select only MULTIPLEXER - - refactor code preferring one-liners - - clean up prints, removing them from success-path. - - don't explicitly set gpio_chip.of_node as it's done in the GPIO library - - use devm_gpiochip_add_data instead of gpiochip_add -v4 -> v5: - - renamed gpio-mux-input -> gpio-cascade. refactored code accordingly - here and there and changed to use new bindings and compatible string - - ambigious and vague 'pin' was rename to 'upstream_line' - - dropped Tested-by and Reviewed-by due to changes in bindings - - dropped Reported-by suggested by an automatic bot as it was not really - appropriate to begin with - - functionally it's the same as v4 -v3 -> v4: - - Changed author email - - Included Tested-by and Reviewed-by from Drew -v2 -> v3: - - use managed device resources - - update Kconfig description -v1 -> v2: - - removed .owner from platform_driver as per test bot's instruction - - added MODULE_AUTHOR, MODULE_DESCRIPTION, MODULE_LICENSE - - added gpio_mux_input_get_direction as it's recommended for all chips - - removed because this is input only chip: gpio_mux_input_set_value - - removed because they are not needed for input/output only chips: - gpio_mux_input_direction_input - gpio_mux_input_direction_output - - fixed typo in an error message - - added info message about successful registration - - removed can_sleep flag as this does not sleep while getting GPIO value - like I2C or SPI do - - Updated description in Kconfig ---- - drivers/gpio/Kconfig | 15 +++++ - drivers/gpio/Makefile | 1 + - drivers/gpio/gpio-cascade.c | 117 ++++++++++++++++++++++++++++++++++++ - 3 files changed, 133 insertions(+) - create mode 100644 drivers/gpio/gpio-cascade.c - ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -1617,4 +1617,19 @@ config GPIO_MOCKUP - tools/testing/selftests/gpio/gpio-mockup.sh. Reference the usage in - it. - -+comment "Other GPIO expanders" -+ -+config GPIO_CASCADE -+ tristate "General GPIO cascade" -+ select MULTIPLEXER -+ help -+ Say yes here to enable support for generic GPIO cascade. -+ -+ This allows building one-to-many cascades of GPIO lines using -+ different types of multiplexers readily available. At the -+ moment only input lines are supported. -+ -+ To build the driver as a module choose 'm' and the resulting module -+ will be called 'gpio-cascade'. -+ - endif ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -44,6 +44,7 @@ obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd - obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o - obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o - obj-$(CONFIG_GPIO_CADENCE) += gpio-cadence.o -+obj-$(CONFIG_GPIO_CASCADE) += gpio-cascade.o - obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o - obj-$(CONFIG_GPIO_SNPS_CREG) += gpio-creg-snps.o - obj-$(CONFIG_GPIO_CRYSTAL_COVE) += gpio-crystalcove.o ---- /dev/null -+++ b/drivers/gpio/gpio-cascade.c -@@ -0,0 +1,117 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * A generic GPIO cascade driver -+ * -+ * Copyright (C) 2021 Mauri Sandberg -+ * -+ * This allows building cascades of GPIO lines in a manner illustrated -+ * below: -+ * -+ * /|---- Cascaded GPIO line 0 -+ * Upstream | |---- Cascaded GPIO line 1 -+ * GPIO line ----+ | . -+ * | | . -+ * \|---- Cascaded GPIO line n -+ * -+ * A multiplexer is being used to select, which cascaded line is being -+ * addressed at any given time. -+ * -+ * At the moment only input mode is supported due to lack of means for -+ * testing output functionality. At least theoretically output should be -+ * possible with open drain constructions. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct gpio_cascade { -+ struct gpio_chip gpio_chip; -+ struct device *parent; -+ struct mux_control *mux_control; -+ struct gpio_desc *upstream_line; -+}; -+ -+static struct gpio_cascade *chip_to_cascade(struct gpio_chip *gc) -+{ -+ return container_of(gc, struct gpio_cascade, gpio_chip); -+} -+ -+static int gpio_cascade_get_direction(struct gpio_chip *gc, unsigned int offset) -+{ -+ return GPIO_LINE_DIRECTION_IN; -+} -+ -+static int gpio_cascade_get_value(struct gpio_chip *gc, unsigned int offset) -+{ -+ struct gpio_cascade *cas = chip_to_cascade(gc); -+ int ret; -+ -+ ret = mux_control_select(cas->mux_control, offset); -+ if (ret) -+ return ret; -+ -+ ret = gpiod_get_value(cas->upstream_line); -+ mux_control_deselect(cas->mux_control); -+ return ret; -+} -+ -+static int gpio_cascade_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct gpio_cascade *cas; -+ struct mux_control *mc; -+ struct gpio_desc *upstream; -+ struct gpio_chip *gc; -+ -+ cas = devm_kzalloc(dev, sizeof(*cas), GFP_KERNEL); -+ if (!cas) -+ return -ENOMEM; -+ -+ mc = devm_mux_control_get(dev, NULL); -+ if (IS_ERR(mc)) -+ return dev_err_probe(dev, PTR_ERR(mc), "unable to get mux-control\n"); -+ -+ cas->mux_control = mc; -+ upstream = devm_gpiod_get(dev, "upstream", GPIOD_IN); -+ if (IS_ERR(upstream)) -+ return dev_err_probe(dev, PTR_ERR(upstream), "unable to claim upstream GPIO line\n"); -+ -+ cas->upstream_line = upstream; -+ cas->parent = dev; -+ -+ gc = &cas->gpio_chip; -+ gc->get = gpio_cascade_get_value; -+ gc->get_direction = gpio_cascade_get_direction; -+ gc->base = -1; -+ gc->ngpio = mux_control_states(mc); -+ gc->label = dev_name(cas->parent); -+ gc->parent = cas->parent; -+ gc->owner = THIS_MODULE; -+ -+ platform_set_drvdata(pdev, cas); -+ return devm_gpiochip_add_data(dev, &cas->gpio_chip, NULL); -+} -+ -+static const struct of_device_id gpio_cascade_id[] = { -+ { .compatible = "gpio-cascade" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, gpio_cascade_id); -+ -+static struct platform_driver gpio_cascade_driver = { -+ .driver = { -+ .name = "gpio-cascade", -+ .of_match_table = gpio_cascade_id, -+ }, -+ .probe = gpio_cascade_probe, -+}; -+module_platform_driver(gpio_cascade_driver); -+ -+MODULE_AUTHOR("Mauri Sandberg "); -+MODULE_DESCRIPTION("Generic GPIO cascade"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/pending-5.10/802-nvmem-u-boot-env-align-endianness-of-crc32-values.patch b/target/linux/generic/pending-5.10/802-nvmem-u-boot-env-align-endianness-of-crc32-values.patch deleted file mode 100644 index 9b111050ee..0000000000 --- a/target/linux/generic/pending-5.10/802-nvmem-u-boot-env-align-endianness-of-crc32-values.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 0e71cac033bb7689c4dfa2e6814191337ef770f5 Mon Sep 17 00:00:00 2001 -From: INAGAKI Hiroshi -Date: Thu, 13 Oct 2022 00:51:33 +0900 -Subject: [PATCH] nvmem: u-boot-env: align endianness of crc32 values -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This patch fixes crc32 error on Big-Endianness system by conversion of -calculated crc32 value. - -Little-Endianness system: - - obtained crc32: Little -calculated crc32: Little - -Big-Endianness system: - - obtained crc32: Little -calculated crc32: Big - -log (APRESIA ApresiaLightGS120GT-SS, RTL8382M, Big-Endianness): - -[ 8.570000] u_boot_env 18001200.spi:flash@0:partitions:partition@c0000: Invalid calculated CRC32: 0x88cd6f09 (expected: 0x096fcd88) -[ 8.580000] u_boot_env: probe of 18001200.spi:flash@0:partitions:partition@c0000 failed with error -22 - -Fixes: f955dc1445069 ("nvmem: add driver handling U-Boot environment variables") - -Signed-off-by: INAGAKI Hiroshi -Acked-by: Rafał Miłecki -Tested-by: Christian Lamparter -Signed-off-by: Srinivas Kandagatla ---- - drivers/nvmem/u-boot-env.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/nvmem/u-boot-env.c -+++ b/drivers/nvmem/u-boot-env.c -@@ -182,7 +182,7 @@ static int u_boot_env_parse(struct u_boo - crc32_data_len = priv->mtd->size - crc32_data_offset; - data_len = priv->mtd->size - data_offset; - -- calc = crc32(~0, buf + crc32_data_offset, crc32_data_len) ^ ~0L; -+ calc = le32_to_cpu((__le32)crc32(~0, buf + crc32_data_offset, crc32_data_len) ^ ~0L); - if (calc != crc32) { - dev_err(dev, "Invalid calculated CRC32: 0x%08x (expected: 0x%08x)\n", calc, crc32); - err = -EINVAL; diff --git a/target/linux/generic/pending-5.10/810-pci_disable_common_quirks.patch b/target/linux/generic/pending-5.10/810-pci_disable_common_quirks.patch deleted file mode 100644 index ac232c7197..0000000000 --- a/target/linux/generic/pending-5.10/810-pci_disable_common_quirks.patch +++ /dev/null @@ -1,62 +0,0 @@ -From: Gabor Juhos -Subject: debloat: add kernel config option to disabling common PCI quirks - -Signed-off-by: Gabor Juhos ---- - drivers/pci/Kconfig | 6 ++++++ - drivers/pci/quirks.c | 6 ++++++ - 2 files changed, 12 insertions(+) - ---- a/drivers/pci/Kconfig -+++ b/drivers/pci/Kconfig -@@ -118,6 +118,13 @@ config XEN_PCIDEV_FRONTEND - The PCI device frontend driver allows the kernel to import arbitrary - PCI devices from a PCI backend to support PCI driver domains. - -+config PCI_DISABLE_COMMON_QUIRKS -+ bool "PCI disable common quirks" -+ depends on PCI -+ help -+ If you don't know what to do here, say N. -+ -+ - config PCI_ATS - bool - ---- a/drivers/pci/quirks.c -+++ b/drivers/pci/quirks.c -@@ -206,6 +206,7 @@ static void quirk_mmio_always_on(struct - DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, - PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); - -+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS - /* - * The Mellanox Tavor device gives false positive parity errors. Mark this - * device with a broken_parity_status to allow PCI scanning code to "skip" -@@ -3335,6 +3336,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I - DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); - DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); - -+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ -+ - /* - * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. - * To work around this, query the size it should be configured to by the -@@ -3360,6 +3363,8 @@ static void quirk_intel_ntb(struct pci_d - DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); - DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); - -+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS -+ - /* - * Some BIOS implementations leave the Intel GPU interrupts enabled, even - * though no one is handling them (e.g., if the i915 driver is never -@@ -3398,6 +3403,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); - DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); - -+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */ -+ - /* - * PCI devices which are on Intel chips can skip the 10ms delay - * before entering D3 mode. diff --git a/target/linux/generic/pending-5.10/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/pending-5.10/811-pci_disable_usb_common_quirks.patch deleted file mode 100644 index 488f90a8d4..0000000000 --- a/target/linux/generic/pending-5.10/811-pci_disable_usb_common_quirks.patch +++ /dev/null @@ -1,115 +0,0 @@ -From: Felix Fietkau -Subject: debloat: disable common USB quirks - -Signed-off-by: Felix Fietkau ---- - drivers/usb/host/pci-quirks.c | 16 ++++++++++++++++ - drivers/usb/host/pci-quirks.h | 18 +++++++++++++++++- - include/linux/usb/hcd.h | 7 +++++++ - 3 files changed, 40 insertions(+), 1 deletion(-) - ---- a/drivers/usb/host/pci-quirks.c -+++ b/drivers/usb/host/pci-quirks.c -@@ -128,6 +128,8 @@ struct amd_chipset_type { - u8 rev; - }; - -+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS -+ - static struct amd_chipset_info { - struct pci_dev *nb_dev; - struct pci_dev *smbus_dev; -@@ -633,6 +635,10 @@ bool usb_amd_pt_check_port(struct device - } - EXPORT_SYMBOL_GPL(usb_amd_pt_check_port); - -+#endif /* CONFIG_PCI_DISABLE_COMMON_QUIRKS */ -+ -+#if IS_ENABLED(CONFIG_USB_UHCI_HCD) -+ - /* - * Make sure the controller is completely inactive, unable to - * generate interrupts or do DMA. -@@ -712,8 +718,17 @@ reset_needed: - uhci_reset_hc(pdev, base); - return 1; - } -+#else -+int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) -+{ -+ return 0; -+} -+ -+#endif - EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); - -+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS -+ - static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) - { - u16 cmd; -@@ -1285,3 +1300,4 @@ static void quirk_usb_early_handoff(stru - } - DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, - PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); -+#endif ---- a/drivers/usb/host/pci-quirks.h -+++ b/drivers/usb/host/pci-quirks.h -@@ -5,6 +5,9 @@ - #ifdef CONFIG_USB_PCI - void uhci_reset_hc(struct pci_dev *pdev, unsigned long base); - int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base); -+#endif /* CONFIG_USB_PCI */ -+ -+#if defined(CONFIG_USB_PCI) && !defined(CONFIG_PCI_DISABLE_COMMON_QUIRKS) - int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev); - bool usb_amd_hang_symptom_quirk(void); - bool usb_amd_prefetch_quirk(void); -@@ -19,6 +22,18 @@ void sb800_prefetch(struct device *dev, - bool usb_amd_pt_check_port(struct device *device, int port); - #else - struct pci_dev; -+static inline int usb_amd_quirk_pll_check(void) -+{ -+ return 0; -+} -+static inline bool usb_amd_hang_symptom_quirk(void) -+{ -+ return false; -+} -+static inline bool usb_amd_prefetch_quirk(void) -+{ -+ return false; -+} - static inline void usb_amd_quirk_pll_disable(void) {} - static inline void usb_amd_quirk_pll_enable(void) {} - static inline void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) {} -@@ -29,6 +44,11 @@ static inline bool usb_amd_pt_check_port - { - return false; - } -+static inline void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) {} -+static inline bool usb_xhci_needs_pci_reset(struct pci_dev *pdev) -+{ -+ return false; -+} - #endif /* CONFIG_USB_PCI */ - - #endif /* __LINUX_USB_PCI_QUIRKS_H */ ---- a/include/linux/usb/hcd.h -+++ b/include/linux/usb/hcd.h -@@ -487,7 +487,14 @@ extern int usb_hcd_pci_probe(struct pci_ - extern void usb_hcd_pci_remove(struct pci_dev *dev); - extern void usb_hcd_pci_shutdown(struct pci_dev *dev); - -+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS - extern int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev); -+#else -+static inline int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev) -+{ -+ return 0; -+} -+#endif - - #ifdef CONFIG_PM - extern const struct dev_pm_ops usb_hcd_pci_pm_ops; diff --git a/target/linux/generic/pending-5.10/820-w1-gpio-fix-problem-with-platfom-data-in-w1-gpio.patch b/target/linux/generic/pending-5.10/820-w1-gpio-fix-problem-with-platfom-data-in-w1-gpio.patch deleted file mode 100644 index 33eb34c913..0000000000 --- a/target/linux/generic/pending-5.10/820-w1-gpio-fix-problem-with-platfom-data-in-w1-gpio.patch +++ /dev/null @@ -1,26 +0,0 @@ -From d9c8bc8c1408f3e8529db6e4e04017b4c579c342 Mon Sep 17 00:00:00 2001 -From: Pawel Dembicki -Date: Sun, 18 Feb 2018 17:08:04 +0100 -Subject: [PATCH] w1: gpio: fix problem with platfom data in w1-gpio - -In devices, where fdt is used, is impossible to apply platform data -without proper fdt node. - -This patch allow to use platform data in devices with fdt. - -Signed-off-by: Pawel Dembicki ---- - drivers/w1/masters/w1-gpio.c | 7 +++---- - 1 file changed, 3 insertions(+), 4 deletions(-) - ---- a/drivers/w1/masters/w1-gpio.c -+++ b/drivers/w1/masters/w1-gpio.c -@@ -76,7 +76,7 @@ static int w1_gpio_probe(struct platform - enum gpiod_flags gflags = GPIOD_OUT_LOW_OPEN_DRAIN; - int err; - -- if (of_have_populated_dt()) { -+ if (of_have_populated_dt() && !dev_get_platdata(&pdev->dev)) { - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return -ENOMEM; diff --git a/target/linux/generic/pending-5.10/834-ledtrig-libata.patch b/target/linux/generic/pending-5.10/834-ledtrig-libata.patch deleted file mode 100644 index 636fe24aea..0000000000 --- a/target/linux/generic/pending-5.10/834-ledtrig-libata.patch +++ /dev/null @@ -1,149 +0,0 @@ -From: Daniel Golle -Subject: libata: add ledtrig support - -This adds a LED trigger for each ATA port indicating disk activity. - -As this is needed only on specific platforms (NAS SoCs and such), -these platforms should define ARCH_WANTS_LIBATA_LEDS if there -are boards with LED(s) intended to indicate ATA disk activity and -need the OS to take care of that. -In that way, if not selected, LED trigger support not will be -included in libata-core and both, codepaths and structures remain -untouched. - -Signed-off-by: Daniel Golle ---- - drivers/ata/Kconfig | 16 ++++++++++++++++ - drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++ - include/linux/libata.h | 9 +++++++++ - 3 files changed, 66 insertions(+) - ---- a/drivers/ata/Kconfig -+++ b/drivers/ata/Kconfig -@@ -67,6 +67,22 @@ config ATA_FORCE - - If unsure, say Y. - -+config ARCH_WANT_LIBATA_LEDS -+ bool -+ -+config ATA_LEDS -+ bool "support ATA port LED triggers" -+ depends on ARCH_WANT_LIBATA_LEDS -+ select NEW_LEDS -+ select LEDS_CLASS -+ select LEDS_TRIGGERS -+ default y -+ help -+ This option adds a LED trigger for each registered ATA port. -+ It is used to drive disk activity leds connected via GPIO. -+ -+ If unsure, say N. -+ - config ATA_ACPI - bool "ATA ACPI Support" - depends on ACPI ---- a/drivers/ata/libata-core.c -+++ b/drivers/ata/libata-core.c -@@ -650,6 +650,19 @@ u64 ata_tf_read_block(const struct ata_t - return block; - } - -+#ifdef CONFIG_ATA_LEDS -+#define LIBATA_BLINK_DELAY 20 /* ms */ -+static inline void ata_led_act(struct ata_port *ap) -+{ -+ unsigned long led_delay = LIBATA_BLINK_DELAY; -+ -+ if (unlikely(!ap->ledtrig)) -+ return; -+ -+ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0); -+} -+#endif -+ - /** - * ata_build_rw_tf - Build ATA taskfile for given read/write request - * @tf: Target ATA taskfile -@@ -4555,6 +4568,9 @@ struct ata_queued_cmd *ata_qc_new_init(s - if (tag < 0) - return NULL; - } -+#ifdef CONFIG_ATA_LEDS -+ ata_led_act(ap); -+#endif - - qc = __ata_qc_from_tag(ap, tag); - qc->tag = qc->hw_tag = tag; -@@ -5333,6 +5349,9 @@ struct ata_port *ata_port_alloc(struct a - ap->stats.unhandled_irq = 1; - ap->stats.idle_irq = 1; - #endif -+#ifdef CONFIG_ATA_LEDS -+ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL); -+#endif - ata_sff_port_init(ap); - - return ap; -@@ -5368,6 +5387,12 @@ static void ata_host_release(struct kref - - kfree(ap->pmp_link); - kfree(ap->slave_link); -+#ifdef CONFIG_ATA_LEDS -+ if (ap->ledtrig) { -+ led_trigger_unregister(ap->ledtrig); -+ kfree(ap->ledtrig); -+ }; -+#endif - kfree(ap); - host->ports[i] = NULL; - } -@@ -5774,7 +5799,23 @@ int ata_host_register(struct ata_host *h - host->ports[i]->print_id = atomic_inc_return(&ata_print_id); - host->ports[i]->local_port_no = i + 1; - } -+#ifdef CONFIG_ATA_LEDS -+ for (i = 0; i < host->n_ports; i++) { -+ if (unlikely(!host->ports[i]->ledtrig)) -+ continue; - -+ snprintf(host->ports[i]->ledtrig_name, -+ sizeof(host->ports[i]->ledtrig_name), "ata%u", -+ host->ports[i]->print_id); -+ -+ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name; -+ -+ if (led_trigger_register(host->ports[i]->ledtrig)) { -+ kfree(host->ports[i]->ledtrig); -+ host->ports[i]->ledtrig = NULL; -+ } -+ } -+#endif - /* Create associated sysfs transport objects */ - for (i = 0; i < host->n_ports; i++) { - rc = ata_tport_add(host->dev,host->ports[i]); ---- a/include/linux/libata.h -+++ b/include/linux/libata.h -@@ -23,6 +23,9 @@ - #include - #include - #include -+#ifdef CONFIG_ATA_LEDS -+#include -+#endif - - /* - * Define if arch has non-standard setup. This is a _PCI_ standard -@@ -883,6 +886,12 @@ struct ata_port { - #ifdef CONFIG_ATA_ACPI - struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ - #endif -+ -+#ifdef CONFIG_ATA_LEDS -+ struct led_trigger *ledtrig; -+ char ledtrig_name[8]; -+#endif -+ - /* owned by EH */ - u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned; - }; diff --git a/target/linux/generic/pending-5.10/840-hwrng-bcm2835-set-quality-to-1000.patch b/target/linux/generic/pending-5.10/840-hwrng-bcm2835-set-quality-to-1000.patch deleted file mode 100644 index 580f0b1bfa..0000000000 --- a/target/linux/generic/pending-5.10/840-hwrng-bcm2835-set-quality-to-1000.patch +++ /dev/null @@ -1,26 +0,0 @@ -From d6988cf1d16faac56899918bb2b1be8d85155e3f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= -Date: Sat, 20 Feb 2021 18:36:38 +0100 -Subject: [PATCH] hwrng: bcm2835: set quality to 1000 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This allows devices without a high precission timer to reduce boot from >100s -to <30s. - -Signed-off-by: Álvaro Fernández Rojas ---- - drivers/char/hw_random/bcm2835-rng.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/char/hw_random/bcm2835-rng.c -+++ b/drivers/char/hw_random/bcm2835-rng.c -@@ -163,6 +163,7 @@ static int bcm2835_rng_probe(struct plat - priv->rng.init = bcm2835_rng_init; - priv->rng.read = bcm2835_rng_read; - priv->rng.cleanup = bcm2835_rng_cleanup; -+ priv->rng.quality = 1000; - - if (dev_of_node(dev)) { - rng_id = of_match_node(bcm2835_rng_of_match, dev->of_node); diff --git a/target/linux/generic/pending-5.10/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch b/target/linux/generic/pending-5.10/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch deleted file mode 100644 index c6f127add1..0000000000 --- a/target/linux/generic/pending-5.10/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 078c6a1cbd4cd7496048786beec2e312577bebbf Mon Sep 17 00:00:00 2001 -From: Pawel Dembicki -Date: Tue, 11 Jan 2022 23:11:32 +0100 -Subject: [PATCH] net: qmi_wwan: add ZTE MF286D modem 19d2:1485 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Modem from ZTE MF286D is an Qualcomm MDM9250 based 3G/4G modem. - -T: Bus=02 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 3 Spd=5000 MxCh= 0 -D: Ver= 3.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs= 1 -P: Vendor=19d2 ProdID=1485 Rev=52.87 -S: Manufacturer=ZTE,Incorporated -S: Product=ZTE Technologies MSM -S: SerialNumber=MF286DZTED000000 -C:* #Ifs= 7 Cfg#= 1 Atr=80 MxPwr=896mA -A: FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=06 Prot=00 -I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=02 Prot=ff Driver=rndis_host -E: Ad=82(I) Atr=03(Int.) MxPS= 8 Ivl=32ms -I:* If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=rndis_host -E: Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option -E: Ad=83(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -I:* If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option -E: Ad=85(I) Atr=03(Int.) MxPS= 10 Ivl=32ms -E: Ad=84(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=03(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -I:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option -E: Ad=87(I) Atr=03(Int.) MxPS= 10 Ivl=32ms -E: Ad=86(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=04(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -I:* If#= 5 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan -E: Ad=88(I) Atr=03(Int.) MxPS= 8 Ivl=32ms -E: Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -I:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=usbfs -E: Ad=05(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=89(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms - -Signed-off-by: Pawel Dembicki -Acked-by: Bjørn Mork -Signed-off-by: David S. Miller ---- - drivers/net/usb/qmi_wwan.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/usb/qmi_wwan.c -+++ b/drivers/net/usb/qmi_wwan.c -@@ -1253,6 +1253,7 @@ static const struct usb_device_id produc - {QMI_FIXED_INTF(0x19d2, 0x1426, 2)}, /* ZTE MF91 */ - {QMI_FIXED_INTF(0x19d2, 0x1428, 2)}, /* Telewell TW-LTE 4G v2 */ - {QMI_FIXED_INTF(0x19d2, 0x1432, 3)}, /* ZTE ME3620 */ -+ {QMI_FIXED_INTF(0x19d2, 0x1485, 5)}, /* ZTE MF286D */ - {QMI_FIXED_INTF(0x19d2, 0x2002, 4)}, /* ZTE (Vodafone) K3765-Z */ - {QMI_FIXED_INTF(0x2001, 0x7e16, 3)}, /* D-Link DWM-221 */ - {QMI_FIXED_INTF(0x2001, 0x7e19, 4)}, /* D-Link DWM-221 B1 */ diff --git a/target/linux/generic/pending-5.10/850-0001-PCI-aardvark-Replace-custom-PCIE_CORE_INT_-macros-wi.patch b/target/linux/generic/pending-5.10/850-0001-PCI-aardvark-Replace-custom-PCIE_CORE_INT_-macros-wi.patch deleted file mode 100644 index cae329a582..0000000000 --- a/target/linux/generic/pending-5.10/850-0001-PCI-aardvark-Replace-custom-PCIE_CORE_INT_-macros-wi.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 43f3f187e6f62ca40802afe39495c8a3e20b4bfa Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Mon, 10 Jan 2022 01:50:50 +0100 -Subject: [PATCH] PCI: aardvark: Replace custom PCIE_CORE_INT_* macros with - PCI_INTERRUPT_* -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Header file linux/pci.h defines enum pci_interrupt_pin with corresponding -PCI_INTERRUPT_* values. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 6 +----- - 1 file changed, 1 insertion(+), 5 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -37,10 +37,6 @@ - #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) - #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) - #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) --#define PCIE_CORE_INT_A_ASSERT_ENABLE 1 --#define PCIE_CORE_INT_B_ASSERT_ENABLE 2 --#define PCIE_CORE_INT_C_ASSERT_ENABLE 3 --#define PCIE_CORE_INT_D_ASSERT_ENABLE 4 - /* PIO registers base address and register offsets */ - #define PIO_BASE_ADDR 0x4000 - #define PIO_CTRL (PIO_BASE_ADDR + 0x0) -@@ -968,7 +964,7 @@ static int advk_sw_pci_bridge_init(struc - bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); - - /* Support interrupt A for MSI feature */ -- bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; -+ bridge->conf.intpin = PCI_INTERRUPT_INTA; - - /* Aardvark HW provides PCIe Capability structure in version 2 */ - bridge->pcie_conf.cap = cpu_to_le16(2); diff --git a/target/linux/generic/pending-5.10/850-0004-PCI-aardvark-Rewrite-IRQ-code-to-chained-IRQ-handler.patch b/target/linux/generic/pending-5.10/850-0004-PCI-aardvark-Rewrite-IRQ-code-to-chained-IRQ-handler.patch deleted file mode 100644 index 426ba94b98..0000000000 --- a/target/linux/generic/pending-5.10/850-0004-PCI-aardvark-Rewrite-IRQ-code-to-chained-IRQ-handler.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 0cd5141d1866afb23286fe90cd846441fe7aeb39 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Sat, 27 Mar 2021 14:44:11 +0100 -Subject: [PATCH] PCI: aardvark: Rewrite IRQ code to chained IRQ handler -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Rewrite the code to use irq_set_chained_handler_and_data() handler with -chained_irq_enter() and chained_irq_exit() processing instead of using -devm_request_irq(). - -advk_pcie_irq_handler() reads IRQ status bits and calls other functions -based on which bits are set. These functions then read its own IRQ status -bits and calls other aardvark functions based on these bits. Finally -generic_handle_domain_irq() with translated linux IRQ numbers are called. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 48 +++++++++++++++------------ - 1 file changed, 26 insertions(+), 22 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -275,6 +275,7 @@ struct advk_pcie { - u32 actions; - } wins[OB_WIN_COUNT]; - u8 wins_count; -+ int irq; - struct irq_domain *irq_domain; - struct irq_chip irq_chip; - raw_spinlock_t irq_lock; -@@ -1441,21 +1442,26 @@ static void advk_pcie_handle_int(struct - } - } - --static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) -+static void advk_pcie_irq_handler(struct irq_desc *desc) - { -- struct advk_pcie *pcie = arg; -- u32 status; -+ struct advk_pcie *pcie = irq_desc_get_handler_data(desc); -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ u32 val, mask, status; - -- status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); -- if (!(status & PCIE_IRQ_CORE_INT)) -- return IRQ_NONE; -+ chained_irq_enter(chip, desc); - -- advk_pcie_handle_int(pcie); -+ val = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); -+ mask = advk_readl(pcie, HOST_CTRL_INT_MASK_REG); -+ status = val & ((~mask) & PCIE_IRQ_ALL_MASK); - -- /* Clear interrupt */ -- advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); -+ if (status & PCIE_IRQ_CORE_INT) { -+ advk_pcie_handle_int(pcie); - -- return IRQ_HANDLED; -+ /* Clear interrupt */ -+ advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); -+ } -+ -+ chained_irq_exit(chip, desc); - } - - static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) -@@ -1522,7 +1528,7 @@ static int advk_pcie_probe(struct platfo - struct advk_pcie *pcie; - struct pci_host_bridge *bridge; - struct resource_entry *entry; -- int ret, irq; -+ int ret; - - bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); - if (!bridge) -@@ -1610,17 +1616,9 @@ static int advk_pcie_probe(struct platfo - if (IS_ERR(pcie->base)) - return PTR_ERR(pcie->base); - -- irq = platform_get_irq(pdev, 0); -- if (irq < 0) -- return irq; -- -- ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, -- IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", -- pcie); -- if (ret) { -- dev_err(dev, "Failed to register interrupt\n"); -- return ret; -- } -+ pcie->irq = platform_get_irq(pdev, 0); -+ if (pcie->irq < 0) -+ return pcie->irq; - - pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, - "reset-gpios", 0, -@@ -1669,11 +1667,14 @@ static int advk_pcie_probe(struct platfo - return ret; - } - -+ irq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie); -+ - bridge->sysdata = pcie; - bridge->ops = &advk_pcie_ops; - - ret = pci_host_probe(bridge); - if (ret < 0) { -+ irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); - return ret; -@@ -1721,6 +1722,9 @@ static int advk_pcie_remove(struct platf - advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); - advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); - -+ /* Remove IRQ handler */ -+ irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); -+ - /* Remove IRQ domains */ - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); diff --git a/target/linux/generic/pending-5.10/850-0005-PCI-aardvark-Check-return-value-of-generic_handle_do.patch b/target/linux/generic/pending-5.10/850-0005-PCI-aardvark-Check-return-value-of-generic_handle_do.patch deleted file mode 100644 index a9c7f052b1..0000000000 --- a/target/linux/generic/pending-5.10/850-0005-PCI-aardvark-Check-return-value-of-generic_handle_do.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 69c1f2c6f45a556361fd8e8d2d4eb20e2c8d3d95 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 18 Mar 2021 17:04:32 +0100 -Subject: [PATCH] PCI: aardvark: Check return value of - generic_handle_domain_irq() when processing INTx IRQ -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -It is possible that we receive spurious INTx interrupt. Check for the -return value of generic_handle_domain_irq() when processing INTx IRQ. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1438,7 +1438,9 @@ static void advk_pcie_handle_int(struct - PCIE_ISR1_REG); - - virq = irq_find_mapping(pcie->irq_domain, i); -- generic_handle_irq(virq); -+ if (generic_handle_irq(virq) == -EINVAL) -+ dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n", -+ (char)i + 'A'); - } - } - diff --git a/target/linux/generic/pending-5.10/850-0006-PCI-aardvark-Make-MSI-irq_chip-structures-static-dri.patch b/target/linux/generic/pending-5.10/850-0006-PCI-aardvark-Make-MSI-irq_chip-structures-static-dri.patch deleted file mode 100644 index e7cee0a87a..0000000000 --- a/target/linux/generic/pending-5.10/850-0006-PCI-aardvark-Make-MSI-irq_chip-structures-static-dri.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 5eb36a6b9508da442aac80f4df23e3951bbfa7aa Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 10 Jan 2022 00:03:41 +0100 -Subject: [PATCH] PCI: aardvark: Make MSI irq_chip structures static driver - structures -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Marc Zyngier says [1] that we should use struct irq_chip as a global -static struct in the driver. Even though the structure currently -contains a dynamic member (parent_device), Marc says [2] that he plans -to kill it and make the structure completely static. - -Convert Aardvark's priv->msi_bottom_irq_chip and priv->msi_irq_chip to -static driver structure. - -[1] https://lore.kernel.org/linux-pci/877dbcvngf.wl-maz@kernel.org/ -[2] https://lore.kernel.org/linux-pci/874k6gvkhz.wl-maz@kernel.org/ - -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 26 ++++++++++++-------------- - 1 file changed, 12 insertions(+), 14 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -281,8 +281,6 @@ struct advk_pcie { - raw_spinlock_t irq_lock; - struct irq_domain *msi_domain; - struct irq_domain *msi_inner_domain; -- struct irq_chip msi_bottom_irq_chip; -- struct irq_chip msi_irq_chip; - struct msi_domain_info msi_domain_info; - DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); - struct mutex msi_used_lock; -@@ -1201,6 +1199,12 @@ static int advk_msi_set_affinity(struct - return -EINVAL; - } - -+static struct irq_chip advk_msi_bottom_irq_chip = { -+ .name = "MSI", -+ .irq_compose_msi_msg = advk_msi_irq_compose_msi_msg, -+ .irq_set_affinity = advk_msi_set_affinity, -+}; -+ - static int advk_msi_irq_domain_alloc(struct irq_domain *domain, - unsigned int virq, - unsigned int nr_irqs, void *args) -@@ -1217,7 +1221,7 @@ static int advk_msi_irq_domain_alloc(str - - for (i = 0; i < nr_irqs; i++) - irq_domain_set_info(domain, virq + i, hwirq + i, -- &pcie->msi_bottom_irq_chip, -+ &advk_msi_bottom_irq_chip, - domain->host_data, handle_simple_irq, - NULL, NULL); - -@@ -1287,29 +1291,23 @@ static const struct irq_domain_ops advk_ - .xlate = irq_domain_xlate_onecell, - }; - -+static struct irq_chip advk_msi_irq_chip = { -+ .name = "advk-MSI", -+}; -+ - static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) - { - struct device *dev = &pcie->pdev->dev; - struct device_node *node = dev->of_node; -- struct irq_chip *bottom_ic, *msi_ic; - struct msi_domain_info *msi_di; - phys_addr_t msi_msg_phys; - - mutex_init(&pcie->msi_used_lock); - -- bottom_ic = &pcie->msi_bottom_irq_chip; -- -- bottom_ic->name = "MSI"; -- bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; -- bottom_ic->irq_set_affinity = advk_msi_set_affinity; -- -- msi_ic = &pcie->msi_irq_chip; -- msi_ic->name = "advk-MSI"; -- - msi_di = &pcie->msi_domain_info; - msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI; -- msi_di->chip = msi_ic; -+ msi_di->chip = &advk_msi_irq_chip; - - msi_msg_phys = virt_to_phys(&pcie->msi_msg); - diff --git a/target/linux/generic/pending-5.10/850-0007-PCI-aardvark-Make-msi_domain_info-structure-a-static.patch b/target/linux/generic/pending-5.10/850-0007-PCI-aardvark-Make-msi_domain_info-structure-a-static.patch deleted file mode 100644 index beadf12234..0000000000 --- a/target/linux/generic/pending-5.10/850-0007-PCI-aardvark-Make-msi_domain_info-structure-a-static.patch +++ /dev/null @@ -1,64 +0,0 @@ -From c092ab8994f1f777054c0179a9deb40b87ee606f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 10 Jan 2022 00:10:46 +0100 -Subject: [PATCH] PCI: aardvark: Make msi_domain_info structure a static driver - structure -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Make Aardvark's msi_domain_info structure into a private driver structure. -Domain info is same for every potential instatination of a controller. - -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -281,7 +281,6 @@ struct advk_pcie { - raw_spinlock_t irq_lock; - struct irq_domain *msi_domain; - struct irq_domain *msi_inner_domain; -- struct msi_domain_info msi_domain_info; - DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); - struct mutex msi_used_lock; - u16 msi_msg; -@@ -1295,20 +1294,20 @@ static struct irq_chip advk_msi_irq_chip - .name = "advk-MSI", - }; - -+static struct msi_domain_info advk_msi_domain_info = { -+ .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | -+ MSI_FLAG_MULTI_PCI_MSI, -+ .chip = &advk_msi_irq_chip, -+}; -+ - static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) - { - struct device *dev = &pcie->pdev->dev; - struct device_node *node = dev->of_node; -- struct msi_domain_info *msi_di; - phys_addr_t msi_msg_phys; - - mutex_init(&pcie->msi_used_lock); - -- msi_di = &pcie->msi_domain_info; -- msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | -- MSI_FLAG_MULTI_PCI_MSI; -- msi_di->chip = &advk_msi_irq_chip; -- - msi_msg_phys = virt_to_phys(&pcie->msi_msg); - - advk_writel(pcie, lower_32_bits(msi_msg_phys), -@@ -1324,7 +1323,8 @@ static int advk_pcie_init_msi_irq_domain - - pcie->msi_domain = - pci_msi_create_irq_domain(of_node_to_fwnode(node), -- msi_di, pcie->msi_inner_domain); -+ &advk_msi_domain_info, -+ pcie->msi_inner_domain); - if (!pcie->msi_domain) { - irq_domain_remove(pcie->msi_inner_domain); - return -ENOMEM; diff --git a/target/linux/generic/pending-5.10/850-0008-PCI-aardvark-Use-dev_fwnode-instead-of-of_node_to_fw.patch b/target/linux/generic/pending-5.10/850-0008-PCI-aardvark-Use-dev_fwnode-instead-of-of_node_to_fw.patch deleted file mode 100644 index a40d3f0d8e..0000000000 --- a/target/linux/generic/pending-5.10/850-0008-PCI-aardvark-Use-dev_fwnode-instead-of-of_node_to_fw.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 59029739d42b439628e2f64f3d8f2db9be97deff Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 10 Jan 2022 00:15:17 +0100 -Subject: [PATCH] PCI: aardvark: Use dev_fwnode() instead of - of_node_to_fwnode(dev->of_node) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Use simple - dev_fwnode(dev) -instead of - struct device_node *node = dev->of_node; - of_node_to_fwnode(node) -especially since the node variable is not used elsewhere in the function. - -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1303,7 +1303,6 @@ static struct msi_domain_info advk_msi_d - static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) - { - struct device *dev = &pcie->pdev->dev; -- struct device_node *node = dev->of_node; - phys_addr_t msi_msg_phys; - - mutex_init(&pcie->msi_used_lock); -@@ -1322,7 +1321,7 @@ static int advk_pcie_init_msi_irq_domain - return -ENOMEM; - - pcie->msi_domain = -- pci_msi_create_irq_domain(of_node_to_fwnode(node), -+ pci_msi_create_irq_domain(dev_fwnode(dev), - &advk_msi_domain_info, - pcie->msi_inner_domain); - if (!pcie->msi_domain) { diff --git a/target/linux/generic/pending-5.10/850-0009-PCI-aardvark-Refactor-unmasking-summary-MSI-interrup.patch b/target/linux/generic/pending-5.10/850-0009-PCI-aardvark-Refactor-unmasking-summary-MSI-interrup.patch deleted file mode 100644 index 6cdaddc51c..0000000000 --- a/target/linux/generic/pending-5.10/850-0009-PCI-aardvark-Refactor-unmasking-summary-MSI-interrup.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 98feaf97bc64fc640a6c5b1394cd18fc7cd7dac8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Sun, 28 Mar 2021 14:34:49 +0200 -Subject: [PATCH] PCI: aardvark: Refactor unmasking summary MSI interrupt -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Refactor the masking of ISR0/1 Sources and unmasking of summary MSI interrupt -so that it corresponds to the comments: -- first mask all ISR0/1 -- then unmask all MSIs -- then unmask summary MSI interrupt - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 10 ++++++---- - 1 file changed, 6 insertions(+), 4 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -578,15 +578,17 @@ static void advk_pcie_setup_hw(struct ad - advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); - - /* Disable All ISR0/1 Sources */ -- reg = PCIE_ISR0_ALL_MASK; -- reg &= ~PCIE_ISR0_MSI_INT_PENDING; -- advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); -- -+ advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); - advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); - - /* Unmask all MSIs */ - advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); - -+ /* Unmask summary MSI interrupt */ -+ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); -+ reg &= ~PCIE_ISR0_MSI_INT_PENDING; -+ advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); -+ - /* Enable summary interrupt for GIC SPI source */ - reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); - advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); diff --git a/target/linux/generic/pending-5.10/850-0010-PCI-aardvark-Add-support-for-masking-MSI-interrupts.patch b/target/linux/generic/pending-5.10/850-0010-PCI-aardvark-Add-support-for-masking-MSI-interrupts.patch deleted file mode 100644 index 10ac58bd28..0000000000 --- a/target/linux/generic/pending-5.10/850-0010-PCI-aardvark-Add-support-for-masking-MSI-interrupts.patch +++ /dev/null @@ -1,117 +0,0 @@ -From 7f353accca6e4a3222991c65b1a6801503973bd3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 2 Jul 2021 16:44:10 +0200 -Subject: [PATCH] PCI: aardvark: Add support for masking MSI interrupts -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -We should not unmask MSIs at setup, but only when kernel asks for them -to be unmasked. - -At setup, mask all MSIs, and implement IRQ chip callbacks for masking -and unmasking particular MSIs. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 54 ++++++++++++++++++++++++--- - 1 file changed, 49 insertions(+), 5 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -281,6 +281,7 @@ struct advk_pcie { - raw_spinlock_t irq_lock; - struct irq_domain *msi_domain; - struct irq_domain *msi_inner_domain; -+ raw_spinlock_t msi_irq_lock; - DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); - struct mutex msi_used_lock; - u16 msi_msg; -@@ -577,12 +578,10 @@ static void advk_pcie_setup_hw(struct ad - advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); - advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); - -- /* Disable All ISR0/1 Sources */ -+ /* Disable All ISR0/1 and MSI Sources */ - advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); - advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); -- -- /* Unmask all MSIs */ -- advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); -+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); - - /* Unmask summary MSI interrupt */ - reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); -@@ -1200,10 +1199,52 @@ static int advk_msi_set_affinity(struct - return -EINVAL; - } - -+static void advk_msi_irq_mask(struct irq_data *d) -+{ -+ struct advk_pcie *pcie = d->domain->host_data; -+ irq_hw_number_t hwirq = irqd_to_hwirq(d); -+ unsigned long flags; -+ u32 mask; -+ -+ raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); -+ mask = advk_readl(pcie, PCIE_MSI_MASK_REG); -+ mask |= BIT(hwirq); -+ advk_writel(pcie, mask, PCIE_MSI_MASK_REG); -+ raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); -+} -+ -+static void advk_msi_irq_unmask(struct irq_data *d) -+{ -+ struct advk_pcie *pcie = d->domain->host_data; -+ irq_hw_number_t hwirq = irqd_to_hwirq(d); -+ unsigned long flags; -+ u32 mask; -+ -+ raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); -+ mask = advk_readl(pcie, PCIE_MSI_MASK_REG); -+ mask &= ~BIT(hwirq); -+ advk_writel(pcie, mask, PCIE_MSI_MASK_REG); -+ raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); -+} -+ -+static void advk_msi_top_irq_mask(struct irq_data *d) -+{ -+ pci_msi_mask_irq(d); -+ irq_chip_mask_parent(d); -+} -+ -+static void advk_msi_top_irq_unmask(struct irq_data *d) -+{ -+ pci_msi_unmask_irq(d); -+ irq_chip_unmask_parent(d); -+} -+ - static struct irq_chip advk_msi_bottom_irq_chip = { - .name = "MSI", - .irq_compose_msi_msg = advk_msi_irq_compose_msi_msg, - .irq_set_affinity = advk_msi_set_affinity, -+ .irq_mask = advk_msi_irq_mask, -+ .irq_unmask = advk_msi_irq_unmask, - }; - - static int advk_msi_irq_domain_alloc(struct irq_domain *domain, -@@ -1293,7 +1334,9 @@ static const struct irq_domain_ops advk_ - }; - - static struct irq_chip advk_msi_irq_chip = { -- .name = "advk-MSI", -+ .name = "advk-MSI", -+ .irq_mask = advk_msi_top_irq_mask, -+ .irq_unmask = advk_msi_top_irq_unmask, - }; - - static struct msi_domain_info advk_msi_domain_info = { -@@ -1307,6 +1350,7 @@ static int advk_pcie_init_msi_irq_domain - struct device *dev = &pcie->pdev->dev; - phys_addr_t msi_msg_phys; - -+ raw_spin_lock_init(&pcie->msi_irq_lock); - mutex_init(&pcie->msi_used_lock); - - msi_msg_phys = virt_to_phys(&pcie->msi_msg); diff --git a/target/linux/generic/pending-5.10/850-0011-PCI-aardvark-Fix-setting-MSI-address.patch b/target/linux/generic/pending-5.10/850-0011-PCI-aardvark-Fix-setting-MSI-address.patch deleted file mode 100644 index 587e78111a..0000000000 --- a/target/linux/generic/pending-5.10/850-0011-PCI-aardvark-Fix-setting-MSI-address.patch +++ /dev/null @@ -1,91 +0,0 @@ -From fa73c200f181436eab859374657c53a73778d8ad Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 26 Mar 2021 17:35:44 +0100 -Subject: [PATCH] PCI: aardvark: Fix setting MSI address -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -MSI address for receiving MSI interrupts needs to be correctly set before -enabling processing of MSI interrupts. - -Move code for setting PCIE_MSI_ADDR_LOW_REG and PCIE_MSI_ADDR_HIGH_REG -from advk_pcie_init_msi_irq_domain() to advk_pcie_setup_hw(), before -enabling PCIE_CORE_CTRL2_MSI_ENABLE. - -After this we can remove the now unused member msi_msg, which was used -only for MSI doorbell address. MSI address can be any address which cannot -be used to DMA to. So change it to the address of the main struct advk_pcie. - -Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") -Signed-off-by: Pali Rohár -Acked-by: Marc Zyngier -Signed-off-by: Marek Behún -Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") ---- - drivers/pci/controller/pci-aardvark.c | 21 +++++++++------------ - 1 file changed, 9 insertions(+), 12 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -284,7 +284,6 @@ struct advk_pcie { - raw_spinlock_t msi_irq_lock; - DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); - struct mutex msi_used_lock; -- u16 msi_msg; - int link_gen; - struct pci_bridge_emul bridge; - struct gpio_desc *reset_gpio; -@@ -479,6 +478,7 @@ static void advk_pcie_disable_ob_win(str - - static void advk_pcie_setup_hw(struct advk_pcie *pcie) - { -+ phys_addr_t msi_addr; - u32 reg; - int i; - -@@ -567,6 +567,11 @@ static void advk_pcie_setup_hw(struct ad - reg |= LANE_COUNT_1; - advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); - -+ /* Set MSI address */ -+ msi_addr = virt_to_phys(pcie); -+ advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); -+ advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); -+ - /* Enable MSI */ - reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); - reg |= PCIE_CORE_CTRL2_MSI_ENABLE; -@@ -1186,10 +1191,10 @@ static void advk_msi_irq_compose_msi_msg - struct msi_msg *msg) - { - struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); -- phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); -+ phys_addr_t msi_addr = virt_to_phys(pcie); - -- msg->address_lo = lower_32_bits(msi_msg); -- msg->address_hi = upper_32_bits(msi_msg); -+ msg->address_lo = lower_32_bits(msi_addr); -+ msg->address_hi = upper_32_bits(msi_addr); - msg->data = data->hwirq; - } - -@@ -1348,18 +1353,10 @@ static struct msi_domain_info advk_msi_d - static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) - { - struct device *dev = &pcie->pdev->dev; -- phys_addr_t msi_msg_phys; - - raw_spin_lock_init(&pcie->msi_irq_lock); - mutex_init(&pcie->msi_used_lock); - -- msi_msg_phys = virt_to_phys(&pcie->msi_msg); -- -- advk_writel(pcie, lower_32_bits(msi_msg_phys), -- PCIE_MSI_ADDR_LOW_REG); -- advk_writel(pcie, upper_32_bits(msi_msg_phys), -- PCIE_MSI_ADDR_HIGH_REG); -- - pcie->msi_inner_domain = - irq_domain_add_linear(NULL, MSI_IRQ_NUM, - &advk_msi_domain_ops, pcie); diff --git a/target/linux/generic/pending-5.10/850-0012-PCI-aardvark-Enable-MSI-X-support.patch b/target/linux/generic/pending-5.10/850-0012-PCI-aardvark-Enable-MSI-X-support.patch deleted file mode 100644 index 2e681cdffc..0000000000 --- a/target/linux/generic/pending-5.10/850-0012-PCI-aardvark-Enable-MSI-X-support.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 735a4ac9782b96fbe1543c578aa8334364f21abd Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 2 Apr 2021 14:05:24 +0200 -Subject: [PATCH] PCI: aardvark: Enable MSI-X support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -According to PCI 3.0 specification, sending both MSI and MSI-X interrupts -is done by DWORD memory write operation to doorbell message address. The -write operation for MSI has zero upper 16 bits and the MSI interrupt number -in the lower 16 bits, while the write operation for MSI-X contains a 32-bit -value from MSI-X table. - -Since the driver only uses interrupt numbers from range 0..31, the upper -16 bits of the DWORD memory write operation to doorbell message address -are zero even for MSI-X interrupts. Thus we can enable MSI-X interrupts. - -Testing proves that kernel can correctly receive MSI-X interrupts from PCIe -cards which supports both MSI and MSI-X interrupts. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1346,7 +1346,7 @@ static struct irq_chip advk_msi_irq_chip - - static struct msi_domain_info advk_msi_domain_info = { - .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | -- MSI_FLAG_MULTI_PCI_MSI, -+ MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, - .chip = &advk_msi_irq_chip, - }; - diff --git a/target/linux/generic/pending-5.10/850-0013-PCI-aardvark-Add-support-for-ERR-interrupt-on-emulat.patch b/target/linux/generic/pending-5.10/850-0013-PCI-aardvark-Add-support-for-ERR-interrupt-on-emulat.patch deleted file mode 100644 index 8665431961..0000000000 --- a/target/linux/generic/pending-5.10/850-0013-PCI-aardvark-Add-support-for-ERR-interrupt-on-emulat.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 7f3e55a3890fa26d15e2e4e90213962d1a7f6df9 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 12 Feb 2021 20:32:55 +0100 -Subject: [PATCH] PCI: aardvark: Add support for ERR interrupt on emulated - bridge -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -ERR interrupt is triggered when corresponding bit is unmasked in both ISR0 -and PCI_EXP_DEVCTL registers. Unmasking ERR bits in PCI_EXP_DEVCTL register -is not enough. This means that currently the ERR interrupt is never -triggered. - -Unmask ERR bits in ISR0 register at driver probe time. ERR interrupt is not -triggered until ERR bits are unmasked also in PCI_EXP_DEVCTL register, -which is done by AER driver. So it is safe to unconditionally unmask all -ERR bits in aardvark probe. - -Aardvark HW sets PCI_ERR_ROOT_AER_IRQ to zero and when corresponding bits -in ISR0 and PCI_EXP_DEVCTL are enabled, the HW triggers a generic interrupt -on GIC. Chain this interrupt to PCIe interrupt 0 with -generic_handle_domain_irq() to allow processing of ERR interrupts. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 36 ++++++++++++++++++++++++++- - 1 file changed, 35 insertions(+), 1 deletion(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -97,6 +97,10 @@ - #define PCIE_MSG_PM_PME_MASK BIT(7) - #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) - #define PCIE_ISR0_MSI_INT_PENDING BIT(24) -+#define PCIE_ISR0_CORR_ERR BIT(11) -+#define PCIE_ISR0_NFAT_ERR BIT(12) -+#define PCIE_ISR0_FAT_ERR BIT(13) -+#define PCIE_ISR0_ERR_MASK GENMASK(13, 11) - #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) - #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) - #define PCIE_ISR0_ALL_MASK GENMASK(31, 0) -@@ -785,11 +789,15 @@ advk_pci_bridge_emul_base_conf_read(stru - case PCI_INTERRUPT_LINE: { - /* - * From the whole 32bit register we support reading from HW only -- * one bit: PCI_BRIDGE_CTL_BUS_RESET. -+ * two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR. - * Other bits are retrieved only from emulated config buffer. - */ - __le32 *cfgspace = (__le32 *)&bridge->conf; - u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); -+ if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK) -+ val &= ~(PCI_BRIDGE_CTL_SERR << 16); -+ else -+ val |= PCI_BRIDGE_CTL_SERR << 16; - if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) - val |= PCI_BRIDGE_CTL_BUS_RESET << 16; - else -@@ -815,6 +823,19 @@ advk_pci_bridge_emul_base_conf_write(str - break; - - case PCI_INTERRUPT_LINE: -+ /* -+ * According to Figure 6-3: Pseudo Logic Diagram for Error -+ * Message Controls in PCIe base specification, SERR# Enable bit -+ * in Bridge Control register enable receiving of ERR_* messages -+ */ -+ if (mask & (PCI_BRIDGE_CTL_SERR << 16)) { -+ u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); -+ if (new & (PCI_BRIDGE_CTL_SERR << 16)) -+ val &= ~PCIE_ISR0_ERR_MASK; -+ else -+ val |= PCIE_ISR0_ERR_MASK; -+ advk_writel(pcie, val, PCIE_ISR0_MASK_REG); -+ } - if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { - u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); - if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) -@@ -1465,6 +1486,19 @@ static void advk_pcie_handle_int(struct - isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); - isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); - -+ /* Process ERR interrupt */ -+ if (isr0_status & PCIE_ISR0_ERR_MASK) { -+ advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG); -+ -+ /* -+ * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use -+ * PCIe interrupt 0 -+ */ -+ virq = irq_find_mapping(pcie->irq_domain, 0); -+ if (generic_handle_irq(virq) == -EINVAL) -+ dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); -+ } -+ - /* Process MSI interrupts */ - if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) - advk_pcie_handle_msi(pcie); diff --git a/target/linux/generic/pending-5.10/850-0015-PCI-aardvark-Optimize-writing-PCI_EXP_RTCTL_PMEIE-an.patch b/target/linux/generic/pending-5.10/850-0015-PCI-aardvark-Optimize-writing-PCI_EXP_RTCTL_PMEIE-an.patch deleted file mode 100644 index 5ed809def2..0000000000 --- a/target/linux/generic/pending-5.10/850-0015-PCI-aardvark-Optimize-writing-PCI_EXP_RTCTL_PMEIE-an.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 3fe0073d116d9902df08761c1cf0d733dd4c38fc Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Wed, 8 Dec 2021 06:03:50 +0100 -Subject: [PATCH] PCI: aardvark: Optimize writing PCI_EXP_RTCTL_PMEIE and - PCI_EXP_RTSTA_PME on emulated bridge -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -To optimize advk_pci_bridge_emul_pcie_conf_write() code, touch -PCIE_ISR0_REG and PCIE_ISR0_MASK_REG registers only when it is really -needed, when processing PCI_EXP_RTCTL_PMEIE and PCI_EXP_RTSTA_PME bits. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 20 +++++++++++--------- - 1 file changed, 11 insertions(+), 9 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -932,19 +932,21 @@ advk_pci_bridge_emul_pcie_conf_write(str - advk_pcie_wait_for_retrain(pcie); - break; - -- case PCI_EXP_RTCTL: { -+ case PCI_EXP_RTCTL: - /* Only mask/unmask PME interrupt */ -- u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & -- ~PCIE_MSG_PM_PME_MASK; -- if ((new & PCI_EXP_RTCTL_PMEIE) == 0) -- val |= PCIE_MSG_PM_PME_MASK; -- advk_writel(pcie, val, PCIE_ISR0_MASK_REG); -+ if (mask & PCI_EXP_RTCTL_PMEIE) { -+ u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); -+ if (new & PCI_EXP_RTCTL_PMEIE) -+ val &= ~PCIE_MSG_PM_PME_MASK; -+ else -+ val |= PCIE_MSG_PM_PME_MASK; -+ advk_writel(pcie, val, PCIE_ISR0_MASK_REG); -+ } - break; -- } - - case PCI_EXP_RTSTA: -- new = (new & PCI_EXP_RTSTA_PME) >> 9; -- advk_writel(pcie, new, PCIE_ISR0_REG); -+ if (new & PCI_EXP_RTSTA_PME) -+ advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG); - break; - - case PCI_EXP_DEVCTL: diff --git a/target/linux/generic/pending-5.10/850-0016-PCI-aardvark-Add-support-for-PME-interrupts.patch b/target/linux/generic/pending-5.10/850-0016-PCI-aardvark-Add-support-for-PME-interrupts.patch deleted file mode 100644 index 2b1a945b62..0000000000 --- a/target/linux/generic/pending-5.10/850-0016-PCI-aardvark-Add-support-for-PME-interrupts.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 7acd8ef92e8789e10b5d736d73cea3b625087f26 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Wed, 8 Dec 2021 06:07:44 +0100 -Subject: [PATCH] PCI: aardvark: Add support for PME interrupts -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Currently enabling PCI_EXP_RTSTA_PME bit in PCI_EXP_RTCTL register does -nothing. This is because PCIe PME driver expects to receive PCIe interrupt -defined in PCI_EXP_FLAGS_IRQ register, but aardvark hardware does not -trigger PCIe INTx/MSI interrupt for PME event, rather it triggers custom -aardvark interrupt which this driver is not processing yet. - -Fix this issue by handling PME interrupt in advk_pcie_handle_int() and -chaining it to PCIe interrupt 0 with generic_handle_domain_irq() (since -aardvark sets PCI_EXP_FLAGS_IRQ to zero). With this change PCIe PME driver -finally starts receiving PME interrupt. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1488,6 +1488,19 @@ static void advk_pcie_handle_int(struct - isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); - isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); - -+ /* Process PME interrupt */ -+ if (isr0_status & PCIE_MSG_PM_PME_MASK) { -+ /* -+ * Do not clear PME interrupt bit in ISR0, it is cleared by IRQ -+ * receiver by writing to the PCI_EXP_RTSTA register of emulated -+ * root bridge. Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, -+ * so use PCIe interrupt 0. -+ */ -+ virq = irq_find_mapping(pcie->irq_domain, 0); -+ if (generic_handle_irq(virq) == -EINVAL) -+ dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); -+ } -+ - /* Process ERR interrupt */ - if (isr0_status & PCIE_ISR0_ERR_MASK) { - advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG); diff --git a/target/linux/generic/pending-5.10/850-0017-PCI-aardvark-Fix-support-for-PME-requester-on-emulat.patch b/target/linux/generic/pending-5.10/850-0017-PCI-aardvark-Fix-support-for-PME-requester-on-emulat.patch deleted file mode 100644 index a59ff36b51..0000000000 --- a/target/linux/generic/pending-5.10/850-0017-PCI-aardvark-Fix-support-for-PME-requester-on-emulat.patch +++ /dev/null @@ -1,173 +0,0 @@ -From 68727b545332327b4c2f9c0f8d006be8970e7832 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 19 Feb 2021 14:22:22 +0100 -Subject: [PATCH] PCI: aardvark: Fix support for PME requester on emulated - bridge -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Enable aardvark PME interrupt unconditionally by unmasking it and read PME -requester ID to emulated bridge config space immediately after receiving -interrupt. - -PME requester ID is stored in the PCIE_MSG_LOG_REG register, which contains -the last inbound message. So when new inbound message is received by HW -(including non-PM), the content in PCIE_MSG_LOG_REG register is replaced by -a new value. - -PCIe specification mandates that subsequent PMEs are kept pending until the -PME Status Register bit is cleared by software by writing a 1b. - -Support for masking/unmasking PME interrupt on emulated bridge via -PCI_EXP_RTCTL_PMEIE bit is now implemented only in emulated bridge config -space, to ensure that we do not miss any aardvark PME interrupt. - -Reading of PCI_EXP_RTCAP and PCI_EXP_RTSTA registers is simplified as final -value is now always stored into emulated bridge config space by the -interrupt handler, so there is no need to implement support for these -registers in read_pcie callback. - -Clearing of W1C bit PCI_EXP_RTSTA_PME is now also simplified as it is done -by pci-bridge-emul.c code for emulated bridge config space. So there is no -need to implement support for clearing this bit in write_pcie callback. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 94 +++++++++++++++------------ - 1 file changed, 52 insertions(+), 42 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -597,6 +597,11 @@ static void advk_pcie_setup_hw(struct ad - reg &= ~PCIE_ISR0_MSI_INT_PENDING; - advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); - -+ /* Unmask PME interrupt for processing of PME requester */ -+ reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); -+ reg &= ~PCIE_MSG_PM_PME_MASK; -+ advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); -+ - /* Enable summary interrupt for GIC SPI source */ - reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); - advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); -@@ -863,22 +868,11 @@ advk_pci_bridge_emul_pcie_conf_read(stru - *value = PCI_EXP_SLTSTA_PDS << 16; - return PCI_BRIDGE_EMUL_HANDLED; - -- case PCI_EXP_RTCTL: { -- u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); -- *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE; -- *value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE; -- *value |= PCI_EXP_RTCAP_CRSVIS << 16; -- return PCI_BRIDGE_EMUL_HANDLED; -- } -- -- case PCI_EXP_RTSTA: { -- u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); -- u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); -- *value = msglog >> 16; -- if (isr0 & PCIE_MSG_PM_PME_MASK) -- *value |= PCI_EXP_RTSTA_PME; -- return PCI_BRIDGE_EMUL_HANDLED; -- } -+ /* -+ * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need -+ * to be handled here, because their values are stored in emulated -+ * config space buffer, and we read them from there when needed. -+ */ - - case PCI_EXP_LNKCAP: { - u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); -@@ -932,22 +926,19 @@ advk_pci_bridge_emul_pcie_conf_write(str - advk_pcie_wait_for_retrain(pcie); - break; - -- case PCI_EXP_RTCTL: -- /* Only mask/unmask PME interrupt */ -- if (mask & PCI_EXP_RTCTL_PMEIE) { -- u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); -- if (new & PCI_EXP_RTCTL_PMEIE) -- val &= ~PCIE_MSG_PM_PME_MASK; -- else -- val |= PCIE_MSG_PM_PME_MASK; -- advk_writel(pcie, val, PCIE_ISR0_MASK_REG); -- } -+ case PCI_EXP_RTCTL: { -+ u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); -+ /* Only emulation of PMEIE and CRSSVE bits is provided */ -+ rootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE; -+ bridge->pcie_conf.rootctl = cpu_to_le16(rootctl); - break; -+ } - -- case PCI_EXP_RTSTA: -- if (new & PCI_EXP_RTSTA_PME) -- advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG); -- break; -+ /* -+ * PCI_EXP_RTSTA is also supported, but does not need to be handled -+ * here, because its value is stored in emulated config space buffer, -+ * and we write it there when needed. -+ */ - - case PCI_EXP_DEVCTL: - case PCI_EXP_DEVCTL2: -@@ -1452,6 +1443,34 @@ static void advk_pcie_remove_irq_domain( - irq_domain_remove(pcie->irq_domain); - } - -+static void advk_pcie_handle_pme(struct advk_pcie *pcie) -+{ -+ u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; -+ int virq; -+ -+ advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG); -+ -+ /* -+ * PCIE_MSG_LOG_REG contains the last inbound message, so store -+ * the requester ID only when PME was not asserted yet. -+ * Also do not trigger PME interrupt when PME is still asserted. -+ */ -+ if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) { -+ pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME); -+ -+ /* -+ * Trigger PME interrupt only if PMEIE bit in Root Control is set. -+ * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0. -+ */ -+ if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE)) -+ return; -+ -+ virq = irq_find_mapping(pcie->irq_domain, 0); -+ if (generic_handle_irq(virq) == -EINVAL) -+ dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); -+ } -+} -+ - static void advk_pcie_handle_msi(struct advk_pcie *pcie) - { - u32 msi_val, msi_mask, msi_status, msi_idx; -@@ -1488,18 +1507,9 @@ static void advk_pcie_handle_int(struct - isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); - isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); - -- /* Process PME interrupt */ -- if (isr0_status & PCIE_MSG_PM_PME_MASK) { -- /* -- * Do not clear PME interrupt bit in ISR0, it is cleared by IRQ -- * receiver by writing to the PCI_EXP_RTSTA register of emulated -- * root bridge. Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, -- * so use PCIe interrupt 0. -- */ -- virq = irq_find_mapping(pcie->irq_domain, 0); -- if (generic_handle_irq(virq) == -EINVAL) -- dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); -- } -+ /* Process PME interrupt as the first one to do not miss PME requester id */ -+ if (isr0_status & PCIE_MSG_PM_PME_MASK) -+ advk_pcie_handle_pme(pcie); - - /* Process ERR interrupt */ - if (isr0_status & PCIE_ISR0_ERR_MASK) { diff --git a/target/linux/generic/pending-5.10/850-0018-PCI-aardvark-Use-separate-INTA-interrupt-for-emulate.patch b/target/linux/generic/pending-5.10/850-0018-PCI-aardvark-Use-separate-INTA-interrupt-for-emulate.patch deleted file mode 100644 index 62a4bfe807..0000000000 --- a/target/linux/generic/pending-5.10/850-0018-PCI-aardvark-Use-separate-INTA-interrupt-for-emulate.patch +++ /dev/null @@ -1,161 +0,0 @@ -From db305233136f5aa2444a8287a279384e8458c458 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 1 Apr 2021 20:12:48 +0200 -Subject: [PATCH] PCI: aardvark: Use separate INTA interrupt for emulated root - bridge -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Emulated root bridge currently provides only one Legacy INTA interrupt -which is used for reporting PCIe PME and ERR events and handled by kernel -PCIe PME and AER drivers. - -Aardvark HW reports these PME and ERR events separately, so there is no -need to mix real INTA interrupt and emulated INTA interrupt for PCIe PME -and AER drivers. - -Register a new advk-RP (as in Root Port) irq chip and a new irq domain -for emulated root bridge and use this new separate irq domain for -providing INTA interrupt from emulated root bridge for PME and ERR events. - -The real INTA interrupt from real devices is now separate. - -A custom map_irq callback function on PCI host bridge structure is used to -allocate IRQ mapping for emulated root bridge from new irq domain. Original -callback of_irq_parse_and_map_pci() is used for all other devices as before. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 69 ++++++++++++++++++++++++++- - 1 file changed, 67 insertions(+), 2 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -280,6 +280,7 @@ struct advk_pcie { - } wins[OB_WIN_COUNT]; - u8 wins_count; - int irq; -+ struct irq_domain *rp_irq_domain; - struct irq_domain *irq_domain; - struct irq_chip irq_chip; - raw_spinlock_t irq_lock; -@@ -1443,6 +1444,44 @@ static void advk_pcie_remove_irq_domain( - irq_domain_remove(pcie->irq_domain); - } - -+static struct irq_chip advk_rp_irq_chip = { -+ .name = "advk-RP", -+}; -+ -+static int advk_pcie_rp_irq_map(struct irq_domain *h, -+ unsigned int virq, irq_hw_number_t hwirq) -+{ -+ struct advk_pcie *pcie = h->host_data; -+ -+ irq_set_chip_and_handler(virq, &advk_rp_irq_chip, handle_simple_irq); -+ irq_set_chip_data(virq, pcie); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops advk_pcie_rp_irq_domain_ops = { -+ .map = advk_pcie_rp_irq_map, -+ .xlate = irq_domain_xlate_onecell, -+}; -+ -+static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie) -+{ -+ pcie->rp_irq_domain = irq_domain_add_linear(NULL, 1, -+ &advk_pcie_rp_irq_domain_ops, -+ pcie); -+ if (!pcie->rp_irq_domain) { -+ dev_err(&pcie->pdev->dev, "Failed to add Root Port IRQ domain\n"); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) -+{ -+ irq_domain_remove(pcie->rp_irq_domain); -+} -+ - static void advk_pcie_handle_pme(struct advk_pcie *pcie) - { - u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; -@@ -1465,7 +1504,7 @@ static void advk_pcie_handle_pme(struct - if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE)) - return; - -- virq = irq_find_mapping(pcie->irq_domain, 0); -+ virq = irq_find_mapping(pcie->rp_irq_domain, 0); - if (generic_handle_irq(virq) == -EINVAL) - dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); - } -@@ -1519,7 +1558,7 @@ static void advk_pcie_handle_int(struct - * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use - * PCIe interrupt 0 - */ -- virq = irq_find_mapping(pcie->irq_domain, 0); -+ virq = irq_find_mapping(pcie->rp_irq_domain, 0); - if (generic_handle_irq(virq) == -EINVAL) - dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); - } -@@ -1565,6 +1604,21 @@ static void advk_pcie_irq_handler(struct - chained_irq_exit(chip, desc); - } - -+static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ struct advk_pcie *pcie = dev->bus->sysdata; -+ -+ /* -+ * Emulated root bridge has its own emulated irq chip and irq domain. -+ * Argument pin is the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) and -+ * hwirq for irq_create_mapping() is indexed from zero. -+ */ -+ if (pci_is_root_bus(dev->bus)) -+ return irq_create_mapping(pcie->rp_irq_domain, pin - 1); -+ else -+ return of_irq_parse_and_map_pci(dev, slot, pin); -+} -+ - static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) - { - phy_power_off(pcie->phy); -@@ -1768,14 +1822,24 @@ static int advk_pcie_probe(struct platfo - return ret; - } - -+ ret = advk_pcie_init_rp_irq_domain(pcie); -+ if (ret) { -+ dev_err(dev, "Failed to initialize irq\n"); -+ advk_pcie_remove_msi_irq_domain(pcie); -+ advk_pcie_remove_irq_domain(pcie); -+ return ret; -+ } -+ - irq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie); - - bridge->sysdata = pcie; - bridge->ops = &advk_pcie_ops; -+ bridge->map_irq = advk_pcie_map_irq; - - ret = pci_host_probe(bridge); - if (ret < 0) { - irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); -+ advk_pcie_remove_rp_irq_domain(pcie); - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); - return ret; -@@ -1827,6 +1891,7 @@ static int advk_pcie_remove(struct platf - irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); - - /* Remove IRQ domains */ -+ advk_pcie_remove_rp_irq_domain(pcie); - advk_pcie_remove_msi_irq_domain(pcie); - advk_pcie_remove_irq_domain(pcie); - diff --git a/target/linux/generic/pending-5.10/850-0019-PCI-aardvark-Remove-irq_mask_ack-callback-for-INTx-i.patch b/target/linux/generic/pending-5.10/850-0019-PCI-aardvark-Remove-irq_mask_ack-callback-for-INTx-i.patch deleted file mode 100644 index 75f31ba19e..0000000000 --- a/target/linux/generic/pending-5.10/850-0019-PCI-aardvark-Remove-irq_mask_ack-callback-for-INTx-i.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 8c9eef96e24f34ff8b62b230700416b822691a37 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 1 Apr 2021 14:24:12 +0200 -Subject: [PATCH] PCI: aardvark: Remove irq_mask_ack callback for INTx - interrupts -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Callback for irq_mask_ack is the same as for irq_mask. As there is no -special handling for irq_ack, there is no need to define irq_mask_ack too. - -Signed-off-by: Pali Rohár -Acked-by: Marc Zyngier -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1422,7 +1422,6 @@ static int advk_pcie_init_irq_domain(str - } - - irq_chip->irq_mask = advk_pcie_irq_mask; -- irq_chip->irq_mask_ack = advk_pcie_irq_mask; - irq_chip->irq_unmask = advk_pcie_irq_unmask; - - pcie->irq_domain = diff --git a/target/linux/generic/pending-5.10/850-0020-PCI-aardvark-Don-t-mask-irq-when-mapping.patch b/target/linux/generic/pending-5.10/850-0020-PCI-aardvark-Don-t-mask-irq-when-mapping.patch deleted file mode 100644 index 5583dc1b6f..0000000000 --- a/target/linux/generic/pending-5.10/850-0020-PCI-aardvark-Don-t-mask-irq-when-mapping.patch +++ /dev/null @@ -1,27 +0,0 @@ -From dc01fca5a9d9c09ce9a3fb2bc2e7715c37ff3bd9 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 1 Apr 2021 14:30:06 +0200 -Subject: [PATCH] PCI: aardvark: Don't mask irq when mapping -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -By default, all Legacy INTx interrupts are masked, so there is no need to -mask this interrupt during irq_map callback. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1339,7 +1339,6 @@ static int advk_pcie_irq_map(struct irq_ - { - struct advk_pcie *pcie = h->host_data; - -- advk_pcie_irq_mask(irq_get_irq_data(virq)); - irq_set_status_flags(virq, IRQ_LEVEL); - irq_set_chip_and_handler(virq, &pcie->irq_chip, - handle_level_irq); diff --git a/target/linux/generic/pending-5.10/850-0021-PCI-aardvark-Drop-__maybe_unused-from-advk_pcie_disa.patch b/target/linux/generic/pending-5.10/850-0021-PCI-aardvark-Drop-__maybe_unused-from-advk_pcie_disa.patch deleted file mode 100644 index 5a1cff5310..0000000000 --- a/target/linux/generic/pending-5.10/850-0021-PCI-aardvark-Drop-__maybe_unused-from-advk_pcie_disa.patch +++ /dev/null @@ -1,28 +0,0 @@ -From a511c99262ce19ee06908d27212b39ec4c5aeb17 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Wed, 8 Dec 2021 04:40:29 +0100 -Subject: [PATCH] PCI: aardvark: Drop __maybe_unused from - advk_pcie_disable_phy() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This function is now always used in driver remove method, drop the -__maybe_unused attribute. - -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1617,7 +1617,7 @@ static int advk_pcie_map_irq(const struc - return of_irq_parse_and_map_pci(dev, slot, pin); - } - --static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) -+static void advk_pcie_disable_phy(struct advk_pcie *pcie) - { - phy_power_off(pcie->phy); - phy_exit(pcie->phy); diff --git a/target/linux/generic/pending-5.10/850-0022-PCI-aardvark-Update-comment-about-link-going-down-af.patch b/target/linux/generic/pending-5.10/850-0022-PCI-aardvark-Update-comment-about-link-going-down-af.patch deleted file mode 100644 index cc489ebc8a..0000000000 --- a/target/linux/generic/pending-5.10/850-0022-PCI-aardvark-Update-comment-about-link-going-down-af.patch +++ /dev/null @@ -1,35 +0,0 @@ -From bafda858364003a70b9cda84282f9761587f8033 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 10 Jan 2022 00:47:38 +0100 -Subject: [PATCH] PCI: aardvark: Update comment about link going down after - link-up -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Update the comment about what happens when link goes down after we have -checked for link-up. If a PIO request is done while link-down, we have -a serious problem. - -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1005,8 +1005,12 @@ static bool advk_pcie_valid_device(struc - return false; - - /* -- * If the link goes down after we check for link-up, nothing bad -- * happens but the config access times out. -+ * If the link goes down after we check for link-up, we have a problem: -+ * if a PIO request is executed while link-down, the whole controller -+ * gets stuck in a non-functional state, and even after link comes up -+ * again, PIO requests won't work anymore, and a reset of the whole PCIe -+ * controller is needed. Therefore we need to prevent sending PIO -+ * requests while the link is down. - */ - if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) - return false; diff --git a/target/linux/generic/pending-5.10/850-0023-PCI-aardvark-Make-main-irq_chip-structure-a-static-d.patch b/target/linux/generic/pending-5.10/850-0023-PCI-aardvark-Make-main-irq_chip-structure-a-static-d.patch deleted file mode 100644 index a5e2d8a3dd..0000000000 --- a/target/linux/generic/pending-5.10/850-0023-PCI-aardvark-Make-main-irq_chip-structure-a-static-d.patch +++ /dev/null @@ -1,102 +0,0 @@ -From 663b9f99bb35dbc0c7b685f71ee3668a60d31320 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 10 Jan 2022 02:02:00 +0100 -Subject: [PATCH] PCI: aardvark: Make main irq_chip structure a static driver - structure -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Marc Zyngier says [1] that we should use struct irq_chip as a global -static struct in the driver. Even though the structure currently -contains a dynamic member (parent_device), Marc says [2] that he plans -to kill it and make the structure completely static. - -We have already converted others irq_chip structures in this driver in -this way, but we omitted this one because the .name member is -dynamically created from device's name, and the name is displayed in -sysfs, so changing it would break sysfs ABI. - -The rationale for changing the name (to "advk-INT") in spite of sysfs -ABI, and thus allowing to convert to a static structure, is that after -the other changes we made in this series, the IRQ chip is basically -something different: it no logner generates ERR and PME interrupts (they -are generated by emulated bridge's rp_irq_chip). - -[1] https://lore.kernel.org/linux-pci/877dbcvngf.wl-maz@kernel.org/ -[2] https://lore.kernel.org/linux-pci/874k6gvkhz.wl-maz@kernel.org/ - -Signed-off-by: Marek Behún ---- - drivers/pci/controller/pci-aardvark.c | 25 +++++++------------------ - 1 file changed, 7 insertions(+), 18 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -282,7 +282,6 @@ struct advk_pcie { - int irq; - struct irq_domain *rp_irq_domain; - struct irq_domain *irq_domain; -- struct irq_chip irq_chip; - raw_spinlock_t irq_lock; - struct irq_domain *msi_domain; - struct irq_domain *msi_inner_domain; -@@ -1338,14 +1337,19 @@ static void advk_pcie_irq_unmask(struct - raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); - } - -+static struct irq_chip advk_irq_chip = { -+ .name = "advk-INT", -+ .irq_mask = advk_pcie_irq_mask, -+ .irq_unmask = advk_pcie_irq_unmask, -+}; -+ - static int advk_pcie_irq_map(struct irq_domain *h, - unsigned int virq, irq_hw_number_t hwirq) - { - struct advk_pcie *pcie = h->host_data; - - irq_set_status_flags(virq, IRQ_LEVEL); -- irq_set_chip_and_handler(virq, &pcie->irq_chip, -- handle_level_irq); -+ irq_set_chip_and_handler(virq, &advk_irq_chip, handle_level_irq); - irq_set_chip_data(virq, pcie); - - return 0; -@@ -1404,7 +1408,6 @@ static int advk_pcie_init_irq_domain(str - struct device *dev = &pcie->pdev->dev; - struct device_node *node = dev->of_node; - struct device_node *pcie_intc_node; -- struct irq_chip *irq_chip; - int ret = 0; - - raw_spin_lock_init(&pcie->irq_lock); -@@ -1415,28 +1418,14 @@ static int advk_pcie_init_irq_domain(str - return -ENODEV; - } - -- irq_chip = &pcie->irq_chip; -- -- irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", -- dev_name(dev)); -- if (!irq_chip->name) { -- ret = -ENOMEM; -- goto out_put_node; -- } -- -- irq_chip->irq_mask = advk_pcie_irq_mask; -- irq_chip->irq_unmask = advk_pcie_irq_unmask; -- - pcie->irq_domain = - irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, - &advk_pcie_irq_domain_ops, pcie); - if (!pcie->irq_domain) { - dev_err(dev, "Failed to get a INTx IRQ domain\n"); - ret = -ENOMEM; -- goto out_put_node; - } - --out_put_node: - of_node_put(pcie_intc_node); - return ret; - } diff --git a/target/linux/generic/pending-5.10/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch b/target/linux/generic/pending-5.10/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch deleted file mode 100644 index 4a963be952..0000000000 --- a/target/linux/generic/pending-5.10/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch +++ /dev/null @@ -1,217 +0,0 @@ -From a719f7ba7fcba05d85801c6f0267f389a21627c1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Fri, 24 Sep 2021 13:03:02 +0200 -Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove port from driver - configuration -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Port number is encoded into argument for SMC call. It is zero for SATA, -PCIe and also both USB 3.0 PHYs. It is non-zero only for Ethernet PHY -(incorrectly called SGMII) on lane 0. Ethernet PHY on lane 1 also uses zero -port number. - -So construct "port" bits for SMC call argument can be constructed directly -from PHY type and lane number. - -Change driver code to always pass zero port number for non-ethernet PHYs -and for ethernet PHYs determinate port number from lane number. This -simplifies the driver. - -As port number from DT PHY configuration is not used anymore, remove whole -driver code which parses it. This also simplifies the driver. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Reviewed-by: Miquel Raynal ---- - drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 62 +++++++++----------- - 1 file changed, 29 insertions(+), 33 deletions(-) - ---- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c -+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c -@@ -20,7 +20,6 @@ - #include - - #define MVEBU_A3700_COMPHY_LANES 3 --#define MVEBU_A3700_COMPHY_PORTS 2 - - /* COMPHY Fast SMC function identifiers */ - #define COMPHY_SIP_POWER_ON 0x82000001 -@@ -45,51 +44,47 @@ - #define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \ - ((idx) << 8) | \ - ((speed) << 2)) --#define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \ -+#define COMPHY_FW_PCIE(mode, speed, width) (COMPHY_FW_NET(mode, 0, speed) | \ - ((width) << 18)) - - struct mvebu_a3700_comphy_conf { - unsigned int lane; - enum phy_mode mode; - int submode; -- unsigned int port; - u32 fw_mode; - }; - --#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _port, _fw) \ -+#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _fw) \ - { \ - .lane = _lane, \ - .mode = _mode, \ - .submode = _smode, \ -- .port = _port, \ - .fw_mode = _fw, \ - } - --#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _port, _fw) \ -- MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _port, _fw) -+#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _fw) \ -+ MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _fw) - --#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _port, _fw) \ -- MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _port, _fw) -+#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _fw) \ -+ MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _fw) - - static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = { - /* lane 0 */ -- MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, 0, -+ MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, - COMPHY_FW_MODE_USB3H), -- MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1, -+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, - COMPHY_FW_MODE_SGMII), -- MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1, -+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, - COMPHY_FW_MODE_2500BASEX), - /* lane 1 */ -- MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0, -- COMPHY_FW_MODE_PCIE), -- MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0, -+ MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), -+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, - COMPHY_FW_MODE_SGMII), -- MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0, -+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, - COMPHY_FW_MODE_2500BASEX), - /* lane 2 */ -- MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0, -- COMPHY_FW_MODE_SATA), -- MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, 0, -+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, COMPHY_FW_MODE_SATA), -+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, - COMPHY_FW_MODE_USB3H), - }; - -@@ -98,7 +93,6 @@ struct mvebu_a3700_comphy_lane { - unsigned int id; - enum phy_mode mode; - int submode; -- int port; - }; - - static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane, -@@ -120,7 +114,7 @@ static int mvebu_a3700_comphy_smc(unsign - } - } - --static int mvebu_a3700_comphy_get_fw_mode(int lane, int port, -+static int mvebu_a3700_comphy_get_fw_mode(int lane, - enum phy_mode mode, - int submode) - { -@@ -132,7 +126,6 @@ static int mvebu_a3700_comphy_get_fw_mod - - for (i = 0; i < n; i++) { - if (mvebu_a3700_comphy_modes[i].lane == lane && -- mvebu_a3700_comphy_modes[i].port == port && - mvebu_a3700_comphy_modes[i].mode == mode && - mvebu_a3700_comphy_modes[i].submode == submode) - break; -@@ -153,7 +146,7 @@ static int mvebu_a3700_comphy_set_mode(s - if (submode == PHY_INTERFACE_MODE_1000BASEX) - submode = PHY_INTERFACE_MODE_SGMII; - -- fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode, -+ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode, - submode); - if (fw_mode < 0) { - dev_err(lane->dev, "invalid COMPHY mode\n"); -@@ -172,9 +165,10 @@ static int mvebu_a3700_comphy_power_on(s - struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); - u32 fw_param; - int fw_mode; -+ int fw_port; - int ret; - -- fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, -+ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, - lane->mode, lane->submode); - if (fw_mode < 0) { - dev_err(lane->dev, "invalid COMPHY mode\n"); -@@ -191,17 +185,18 @@ static int mvebu_a3700_comphy_power_on(s - fw_param = COMPHY_FW_MODE(fw_mode); - break; - case PHY_MODE_ETHERNET: -+ fw_port = (lane->id == 0) ? 1 : 0; - switch (lane->submode) { - case PHY_INTERFACE_MODE_SGMII: - dev_dbg(lane->dev, "set lane %d to SGMII mode\n", - lane->id); -- fw_param = COMPHY_FW_NET(fw_mode, lane->port, -+ fw_param = COMPHY_FW_NET(fw_mode, fw_port, - COMPHY_FW_SPEED_1_25G); - break; - case PHY_INTERFACE_MODE_2500BASEX: - dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n", - lane->id); -- fw_param = COMPHY_FW_NET(fw_mode, lane->port, -+ fw_param = COMPHY_FW_NET(fw_mode, fw_port, - COMPHY_FW_SPEED_3_125G); - break; - default: -@@ -212,8 +207,7 @@ static int mvebu_a3700_comphy_power_on(s - break; - case PHY_MODE_PCIE: - dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); -- fw_param = COMPHY_FW_PCIE(fw_mode, lane->port, -- COMPHY_FW_SPEED_5G, -+ fw_param = COMPHY_FW_PCIE(fw_mode, COMPHY_FW_SPEED_5G, - phy->attrs.bus_width); - break; - default: -@@ -247,17 +241,20 @@ static struct phy *mvebu_a3700_comphy_xl - struct of_phandle_args *args) - { - struct mvebu_a3700_comphy_lane *lane; -+ unsigned int port; - struct phy *phy; - -- if (WARN_ON(args->args[0] >= MVEBU_A3700_COMPHY_PORTS)) -- return ERR_PTR(-EINVAL); -- - phy = of_phy_simple_xlate(dev, args); - if (IS_ERR(phy)) - return phy; - - lane = phy_get_drvdata(phy); -- lane->port = args->args[0]; -+ -+ port = args->args[0]; -+ if (port != 0 && (port != 1 || lane->id != 0)) { -+ dev_err(lane->dev, "invalid port number %u\n", port); -+ return ERR_PTR(-EINVAL); -+ } - - return phy; - } -@@ -302,7 +299,6 @@ static int mvebu_a3700_comphy_probe(stru - lane->mode = PHY_MODE_INVALID; - lane->submode = PHY_INTERFACE_MODE_NA; - lane->id = lane_id; -- lane->port = -1; - phy_set_drvdata(phy, lane); - } - diff --git a/target/linux/generic/pending-5.10/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch b/target/linux/generic/pending-5.10/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch deleted file mode 100644 index 73ead1e16c..0000000000 --- a/target/linux/generic/pending-5.10/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch +++ /dev/null @@ -1,1564 +0,0 @@ -From 9d276da259cce20b2ed7a868b6e6a6a205f7bb04 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:20:13 +0200 -Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel - implementation -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Remove old RPC implementation and add a new native kernel implementation. - -The old implementation uses ARM SMC API to issue RPC calls to ARM Trusted -Firmware which provides real implementation of PHY configuration. - -But older versions of ARM Trusted Firmware do not provide this PHY -configuration functionality, simply returning: operation not supported; or -worse, some versions provide the configuration functionality incorrectly. - -For example the firmware shipped in ESPRESSObin board has this older -version of ARM Trusted Firmware and therefore SATA, USB 3.0 and PCIe -functionality do not work with newer versions of Linux kernel. - -Due to the above reasons, the following commits were introduced into Linux, -to workaround these issues by ignoring -EOPNOTSUPP error code from -phy-mvebu-a3700-comphy driver function phy_power_on(): - -commit 45aefe3d2251 ("ata: ahci: mvebu: Make SATA PHY optional for Armada -3720") -commit 3241929b67d2 ("usb: host: xhci: mvebu: make USB 3.0 PHY optional for -Armada 3720") -commit b0c6ae0f8948 ("PCI: aardvark: Fix initialization with old Marvell's -Arm Trusted Firmware") - -Replace this RPC implementation with proper native kernel implementation, -which is independent on the firmware. Never return -EOPNOTSUPP for proper -arguments. - -This should solve multiple issues with real-world boards, where it is not -possible or really inconvenient to change the firmware. Let's eliminate -these issues. - -This implementation is ported directly from Armada 3720 comphy driver found -in newest version of ARM Trusted Firmware source code, but with various -fixes of register names, some added comments, some refactoring due to the -original code not conforming to kernel standards. Also PCIe mode poweroff -support was added here, and PHY reset support. These changes are also going -to be sent to ARM Trusted Firmware. - -Signed-off-by: Pali Rohár -Acked-by: Miquel Raynal -[ Pali did the porting from ATF. - I (Marek) then fixed some register names, some various other things, - added some comments and refactored the code to kernel standards. Also - fixed PHY poweroff and added PHY reset. ] -Signed-off-by: Marek Behún ---- - drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1351 ++++++++++++++++-- - 1 file changed, 1234 insertions(+), 117 deletions(-) - ---- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c -+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c -@@ -5,12 +5,16 @@ - * Authors: - * Evan Wang - * Miquèl Raynal -+ * Pali Rohár -+ * Marek Behún - * - * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart. -- * SMC call initial support done by Grzegorz Jaszczyk. -+ * Comphy code from ARM Trusted Firmware ported by Pali Rohár -+ * and Marek Behún . - */ - --#include -+#include -+#include - #include - #include - #include -@@ -18,103 +22,1147 @@ - #include - #include - #include -+#include - --#define MVEBU_A3700_COMPHY_LANES 3 -+#define PLL_SET_DELAY_US 600 -+#define COMPHY_PLL_SLEEP 1000 -+#define COMPHY_PLL_TIMEOUT 150000 -+ -+/* Comphy lane2 indirect access register offset */ -+#define COMPHY_LANE2_INDIR_ADDR 0x0 -+#define COMPHY_LANE2_INDIR_DATA 0x4 -+ -+/* SATA and USB3 PHY offset compared to SATA PHY */ -+#define COMPHY_LANE2_REGS_BASE 0x200 -+ -+/* -+ * When accessing common PHY lane registers directly, we need to shift by 1, -+ * since the registers are 16-bit. -+ */ -+#define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1) -+ -+/* COMPHY registers */ -+#define COMPHY_POWER_PLL_CTRL 0x01 -+#define PU_IVREF_BIT BIT(15) -+#define PU_PLL_BIT BIT(14) -+#define PU_RX_BIT BIT(13) -+#define PU_TX_BIT BIT(12) -+#define PU_TX_INTP_BIT BIT(11) -+#define PU_DFE_BIT BIT(10) -+#define RESET_DTL_RX_BIT BIT(9) -+#define PLL_LOCK_BIT BIT(8) -+#define REF_FREF_SEL_MASK GENMASK(4, 0) -+#define REF_FREF_SEL_SERDES_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x1) -+#define REF_FREF_SEL_SERDES_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3) -+#define REF_FREF_SEL_SERDES_50MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x4) -+#define REF_FREF_SEL_PCIE_USB3_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x2) -+#define REF_FREF_SEL_PCIE_USB3_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3) -+#define COMPHY_MODE_MASK GENMASK(7, 5) -+#define COMPHY_MODE_SATA FIELD_PREP(COMPHY_MODE_MASK, 0x0) -+#define COMPHY_MODE_PCIE FIELD_PREP(COMPHY_MODE_MASK, 0x3) -+#define COMPHY_MODE_SERDES FIELD_PREP(COMPHY_MODE_MASK, 0x4) -+#define COMPHY_MODE_USB3 FIELD_PREP(COMPHY_MODE_MASK, 0x5) -+ -+#define COMPHY_KVCO_CAL_CTRL 0x02 -+#define USE_MAX_PLL_RATE_BIT BIT(12) -+#define SPEED_PLL_MASK GENMASK(7, 2) -+#define SPEED_PLL_VALUE_16 FIELD_PREP(SPEED_PLL_MASK, 0x10) -+ -+#define COMPHY_DIG_LOOPBACK_EN 0x23 -+#define SEL_DATA_WIDTH_MASK GENMASK(11, 10) -+#define DATA_WIDTH_10BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0) -+#define DATA_WIDTH_20BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1) -+#define DATA_WIDTH_40BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2) -+#define PLL_READY_TX_BIT BIT(4) -+ -+#define COMPHY_SYNC_PATTERN 0x24 -+#define TXD_INVERT_BIT BIT(10) -+#define RXD_INVERT_BIT BIT(11) -+ -+#define COMPHY_SYNC_MASK_GEN 0x25 -+#define PHY_GEN_MAX_MASK GENMASK(11, 10) -+#define PHY_GEN_MAX_USB3_5G FIELD_PREP(PHY_GEN_MAX_MASK, 0x1) -+ -+#define COMPHY_ISOLATION_CTRL 0x26 -+#define PHY_ISOLATE_MODE BIT(15) -+ -+#define COMPHY_GEN2_SET2 0x3e -+#define GS2_TX_SSC_AMP_MASK GENMASK(15, 9) -+#define GS2_TX_SSC_AMP_4128 FIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20) -+#define GS2_VREG_RXTX_MAS_ISET_MASK GENMASK(8, 7) -+#define GS2_VREG_RXTX_MAS_ISET_60U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ -+ 0x0) -+#define GS2_VREG_RXTX_MAS_ISET_80U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ -+ 0x1) -+#define GS2_VREG_RXTX_MAS_ISET_100U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ -+ 0x2) -+#define GS2_VREG_RXTX_MAS_ISET_120U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ -+ 0x3) -+#define GS2_RSVD_6_0_MASK GENMASK(6, 0) -+ -+#define COMPHY_GEN3_SET2 0x3f -+ -+#define COMPHY_IDLE_SYNC_EN 0x48 -+#define IDLE_SYNC_EN BIT(12) -+ -+#define COMPHY_MISC_CTRL0 0x4F -+#define CLK100M_125M_EN BIT(4) -+#define TXDCLK_2X_SEL BIT(6) -+#define CLK500M_EN BIT(7) -+#define PHY_REF_CLK_SEL BIT(10) -+ -+#define COMPHY_SFT_RESET 0x52 -+#define SFT_RST BIT(9) -+#define SFT_RST_NO_REG BIT(10) -+ -+#define COMPHY_MISC_CTRL1 0x73 -+#define SEL_BITS_PCIE_FORCE BIT(15) -+ -+#define COMPHY_GEN2_SET3 0x112 -+#define GS3_FFE_CAP_SEL_MASK GENMASK(3, 0) -+#define GS3_FFE_CAP_SEL_VALUE FIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF) -+ -+/* PIPE registers */ -+#define COMPHY_PIPE_LANE_CFG0 0x180 -+#define PRD_TXDEEMPH0_MASK BIT(0) -+#define PRD_TXMARGIN_MASK GENMASK(3, 1) -+#define PRD_TXSWING_MASK BIT(4) -+#define CFG_TX_ALIGN_POS_MASK GENMASK(8, 5) -+ -+#define COMPHY_PIPE_LANE_CFG1 0x181 -+#define PRD_TXDEEMPH1_MASK BIT(15) -+#define USE_MAX_PLL_RATE_EN BIT(9) -+#define TX_DET_RX_MODE BIT(6) -+#define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3) -+#define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2) -+#define TX_ELEC_IDLE_MODE_EN BIT(0) -+ -+#define COMPHY_PIPE_LANE_STAT1 0x183 -+#define TXDCLK_PCLK_EN BIT(0) -+ -+#define COMPHY_PIPE_LANE_CFG4 0x188 -+#define SPREAD_SPECTRUM_CLK_EN BIT(7) -+ -+#define COMPHY_PIPE_RST_CLK_CTRL 0x1C1 -+#define PIPE_SOFT_RESET BIT(0) -+#define PIPE_REG_RESET BIT(1) -+#define MODE_CORE_CLK_FREQ_SEL BIT(9) -+#define MODE_PIPE_WIDTH_32 BIT(3) -+#define MODE_REFDIV_MASK GENMASK(5, 4) -+#define MODE_REFDIV_BY_4 FIELD_PREP(MODE_REFDIV_MASK, 0x2) -+ -+#define COMPHY_PIPE_TEST_MODE_CTRL 0x1C2 -+#define MODE_MARGIN_OVERRIDE BIT(2) -+ -+#define COMPHY_PIPE_CLK_SRC_LO 0x1C3 -+#define MODE_CLK_SRC BIT(0) -+#define BUNDLE_PERIOD_SEL BIT(1) -+#define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2) -+#define BUNDLE_SAMPLE_CTRL BIT(4) -+#define PLL_READY_DLY_MASK GENMASK(7, 5) -+#define CFG_SEL_20B BIT(15) -+ -+#define COMPHY_PIPE_PWR_MGM_TIM1 0x1D0 -+#define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12) -+#define CFG_PM_RXDEN_WAIT_MASK GENMASK(11, 8) -+#define CFG_PM_RXDEN_WAIT_1_UNIT FIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1) -+#define CFG_PM_RXDLOZ_WAIT_MASK GENMASK(7, 0) -+#define CFG_PM_RXDLOZ_WAIT_7_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7) -+#define CFG_PM_RXDLOZ_WAIT_12_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC) -+ -+/* -+ * This register is not from PHY lane register space. It only exists in the -+ * indirect register space, before the actual PHY lane 2 registers. So the -+ * offset is absolute, not relative to COMPHY_LANE2_REGS_BASE. -+ * It is used only for SATA PHY initialization. -+ */ -+#define COMPHY_RESERVED_REG 0x0E -+#define PHYCTRL_FRM_PIN_BIT BIT(13) - --/* COMPHY Fast SMC function identifiers */ --#define COMPHY_SIP_POWER_ON 0x82000001 --#define COMPHY_SIP_POWER_OFF 0x82000002 --#define COMPHY_SIP_PLL_LOCK 0x82000003 -- --#define COMPHY_FW_MODE_SATA 0x1 --#define COMPHY_FW_MODE_SGMII 0x2 --#define COMPHY_FW_MODE_2500BASEX 0x3 --#define COMPHY_FW_MODE_USB3H 0x4 --#define COMPHY_FW_MODE_USB3D 0x5 --#define COMPHY_FW_MODE_PCIE 0x6 --#define COMPHY_FW_MODE_USB3 0xa -- --#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */ --#define COMPHY_FW_SPEED_2_5G 1 --#define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */ --#define COMPHY_FW_SPEED_5G 3 --#define COMPHY_FW_SPEED_MAX 0x3F -- --#define COMPHY_FW_MODE(mode) ((mode) << 12) --#define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \ -- ((idx) << 8) | \ -- ((speed) << 2)) --#define COMPHY_FW_PCIE(mode, speed, width) (COMPHY_FW_NET(mode, 0, speed) | \ -- ((width) << 18)) -+/* South Bridge PHY Configuration Registers */ -+#define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) -+ -+/* -+ * lane0: USB3/GbE1 PHY Configuration 1 -+ * lane1: PCIe/GbE0 PHY Configuration 1 -+ * (used only by SGMII code) -+ */ -+#define COMPHY_PHY_CFG1 0x0 -+#define PIN_PU_IVREF_BIT BIT(1) -+#define PIN_RESET_CORE_BIT BIT(11) -+#define PIN_RESET_COMPHY_BIT BIT(12) -+#define PIN_PU_PLL_BIT BIT(16) -+#define PIN_PU_RX_BIT BIT(17) -+#define PIN_PU_TX_BIT BIT(18) -+#define PIN_TX_IDLE_BIT BIT(19) -+#define GEN_RX_SEL_MASK GENMASK(25, 22) -+#define GEN_RX_SEL_VALUE(val) FIELD_PREP(GEN_RX_SEL_MASK, (val)) -+#define GEN_TX_SEL_MASK GENMASK(29, 26) -+#define GEN_TX_SEL_VALUE(val) FIELD_PREP(GEN_TX_SEL_MASK, (val)) -+#define SERDES_SPEED_1_25_G 0x6 -+#define SERDES_SPEED_3_125_G 0x8 -+#define PHY_RX_INIT_BIT BIT(30) -+ -+/* -+ * lane0: USB3/GbE1 PHY Status 1 -+ * lane1: PCIe/GbE0 PHY Status 1 -+ * (used only by SGMII code) -+ */ -+#define COMPHY_PHY_STAT1 0x18 -+#define PHY_RX_INIT_DONE_BIT BIT(0) -+#define PHY_PLL_READY_RX_BIT BIT(2) -+#define PHY_PLL_READY_TX_BIT BIT(3) -+ -+/* PHY Selector */ -+#define COMPHY_SELECTOR_PHY_REG 0xFC -+/* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */ -+#define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0) -+/* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */ -+#define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4) -+/* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */ -+#define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8) - - struct mvebu_a3700_comphy_conf { - unsigned int lane; - enum phy_mode mode; - int submode; -- u32 fw_mode; - }; - --#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _fw) \ -+#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode) \ - { \ - .lane = _lane, \ - .mode = _mode, \ - .submode = _smode, \ -- .fw_mode = _fw, \ - } - --#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _fw) \ -- MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _fw) -+#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode) \ -+ MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA) - --#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _fw) \ -- MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _fw) -+#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode) \ -+ MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode) - - static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = { - /* lane 0 */ -- MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, -- COMPHY_FW_MODE_USB3H), -- MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, -- COMPHY_FW_MODE_SGMII), -- MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, -- COMPHY_FW_MODE_2500BASEX), -+ MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS), -+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII), -+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_1000BASEX), -+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX), - /* lane 1 */ -- MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE), -- MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, -- COMPHY_FW_MODE_SGMII), -- MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, -- COMPHY_FW_MODE_2500BASEX), -+ MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE), -+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII), -+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_1000BASEX), -+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX), - /* lane 2 */ -- MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, COMPHY_FW_MODE_SATA), -- MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, -- COMPHY_FW_MODE_USB3H), -+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA), -+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS), -+}; -+ -+struct mvebu_a3700_comphy_priv { -+ void __iomem *comphy_regs; -+ void __iomem *lane0_phy_regs; /* USB3 and GbE1 */ -+ void __iomem *lane1_phy_regs; /* PCIe and GbE0 */ -+ void __iomem *lane2_phy_indirect; /* SATA and USB3 */ -+ spinlock_t lock; /* for PHY selector access */ -+ bool xtal_is_40m; - }; - - struct mvebu_a3700_comphy_lane { -+ struct mvebu_a3700_comphy_priv *priv; - struct device *dev; - unsigned int id; - enum phy_mode mode; - int submode; -+ bool invert_tx; -+ bool invert_rx; -+ bool needs_reset; -+}; -+ -+struct gbe_phy_init_data_fix { -+ u16 addr; -+ u16 value; -+}; -+ -+/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ -+static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = { -+ { 0x005, 0x07CC }, { 0x015, 0x0000 }, { 0x01B, 0x0000 }, -+ { 0x01D, 0x0000 }, { 0x01E, 0x0000 }, { 0x01F, 0x0000 }, -+ { 0x020, 0x0000 }, { 0x021, 0x0030 }, { 0x026, 0x0888 }, -+ { 0x04D, 0x0152 }, { 0x04F, 0xA020 }, { 0x050, 0x07CC }, -+ { 0x053, 0xE9CA }, { 0x055, 0xBD97 }, { 0x071, 0x3015 }, -+ { 0x076, 0x03AA }, { 0x07C, 0x0FDF }, { 0x0C2, 0x3030 }, -+ { 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 }, -+ { 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 }, -+ { 0x104, 0x0C10 } - }; - --static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane, -- unsigned long mode) -+/* 40M1G25 mode init data */ -+static u16 gbe_phy_init[512] = { -+ /* 0 1 2 3 4 5 6 7 */ -+ /*-----------------------------------------------------------*/ -+ /* 8 9 A B C D E F */ -+ 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ -+ 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ -+ 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ -+ 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ -+ 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ -+ 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ -+ 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ -+ 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ -+ 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ -+ 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ -+ 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ -+ 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ -+ 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ -+ 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ -+ 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ -+ 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ -+ 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ -+ 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ -+ 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ -+ 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ -+ 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ -+ 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ -+ 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ -+ 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ -+ 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ -+ 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ -+ 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ -+ 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ -+ 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ -+ 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ -+ 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ -+ 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ -+ 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ -+ 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ -+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ -+}; -+ -+static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask) - { -- struct arm_smccc_res res; -- s32 ret; -+ u32 val; - -- arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); -- ret = res.a0; -+ val = readl(addr); -+ val = (val & ~mask) | (data & mask); -+ writel(val, addr); -+} - -- switch (ret) { -- case SMCCC_RET_SUCCESS: -- return 0; -- case SMCCC_RET_NOT_SUPPORTED: -- return -EOPNOTSUPP; -+static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask) -+{ -+ u16 val; -+ -+ val = readw(addr); -+ val = (val & ~mask) | (data & mask); -+ writew(val, addr); -+} -+ -+/* Used for accessing lane 2 registers (SATA/USB3 PHY) */ -+static void comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv, -+ u32 offset, u16 data, u16 mask) -+{ -+ writel(offset, -+ priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); -+ comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, -+ data, mask); -+} -+ -+static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, -+ u16 reg, u16 data, u16 mask) -+{ -+ if (lane->id == 2) { -+ /* lane 2 PHY registers are accessed indirectly */ -+ comphy_set_indirect(lane->priv, -+ reg + COMPHY_LANE2_REGS_BASE, -+ data, mask); -+ } else { -+ void __iomem *base = lane->id == 1 ? -+ lane->priv->lane1_phy_regs : -+ lane->priv->lane0_phy_regs; -+ -+ comphy_reg_set16(base + COMPHY_LANE_REG_DIRECT(reg), -+ data, mask); -+ } -+} -+ -+static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane, -+ u16 reg, u16 bits, -+ ulong sleep_us, ulong timeout_us) -+{ -+ int ret; -+ -+ if (lane->id == 2) { -+ u32 data; -+ -+ /* lane 2 PHY registers are accessed indirectly */ -+ writel(reg + COMPHY_LANE2_REGS_BASE, -+ lane->priv->lane2_phy_indirect + -+ COMPHY_LANE2_INDIR_ADDR); -+ -+ ret = readl_poll_timeout(lane->priv->lane2_phy_indirect + -+ COMPHY_LANE2_INDIR_DATA, -+ data, (data & bits) == bits, -+ sleep_us, timeout_us); -+ } else { -+ void __iomem *base = lane->id == 1 ? -+ lane->priv->lane1_phy_regs : -+ lane->priv->lane0_phy_regs; -+ u16 data; -+ -+ ret = readw_poll_timeout(base + COMPHY_LANE_REG_DIRECT(reg), -+ data, (data & bits) == bits, -+ sleep_us, timeout_us); -+ } -+ -+ return ret; -+} -+ -+static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane, -+ u8 reg, u32 data, u32 mask) -+{ -+ comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg), -+ data, mask); -+} -+ -+static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane, -+ u8 reg, u32 bits, -+ ulong sleep_us, ulong timeout_us) -+{ -+ u32 data; -+ -+ return readl_poll_timeout(lane->priv->comphy_regs + -+ COMPHY_PHY_REG(lane->id, reg), -+ data, (data & bits) == bits, -+ sleep_us, timeout_us); -+} -+ -+/* PHY selector configures with corresponding modes */ -+static int -+mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane) -+{ -+ u32 old, new, clr = 0, set = 0; -+ unsigned long flags; -+ -+ switch (lane->mode) { -+ case PHY_MODE_SATA: -+ /* SATA must be in Lane2 */ -+ if (lane->id == 2) -+ clr = COMPHY_SELECTOR_USB3_PHY_SEL_BIT; -+ else -+ goto error; -+ break; -+ -+ case PHY_MODE_ETHERNET: -+ if (lane->id == 0) -+ clr = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; -+ else if (lane->id == 1) -+ clr = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; -+ else -+ goto error; -+ break; -+ -+ case PHY_MODE_USB_HOST_SS: -+ if (lane->id == 2) -+ set = COMPHY_SELECTOR_USB3_PHY_SEL_BIT; -+ else if (lane->id == 0) -+ set = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; -+ else -+ goto error; -+ break; -+ -+ case PHY_MODE_PCIE: -+ /* PCIE must be in Lane1 */ -+ if (lane->id == 1) -+ set = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; -+ else -+ goto error; -+ break; -+ -+ default: -+ goto error; -+ } -+ -+ spin_lock_irqsave(&lane->priv->lock, flags); -+ -+ old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); -+ new = (old & ~clr) | set; -+ writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); -+ -+ spin_unlock_irqrestore(&lane->priv->lock, flags); -+ -+ dev_dbg(lane->dev, -+ "COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n", -+ lane->id, lane->mode, old, new); -+ -+ return 0; -+error: -+ dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id, -+ lane->mode); -+ return -EINVAL; -+} -+ -+static int -+mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane) -+{ -+ u32 mask, data, ref_clk; -+ int ret; -+ -+ /* Configure phy selector for SATA */ -+ ret = mvebu_a3700_comphy_set_phy_selector(lane); -+ if (ret) -+ return ret; -+ -+ /* Clear phy isolation mode to make it work in normal mode */ -+ comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, -+ 0x0, PHY_ISOLATE_MODE); -+ -+ /* 0. Check the Polarity invert bits */ -+ data = 0x0; -+ if (lane->invert_tx) -+ data |= TXD_INVERT_BIT; -+ if (lane->invert_rx) -+ data |= RXD_INVERT_BIT; -+ mask = TXD_INVERT_BIT | RXD_INVERT_BIT; -+ comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); -+ -+ /* 1. Select 40-bit data width */ -+ comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, -+ DATA_WIDTH_40BIT, SEL_DATA_WIDTH_MASK); -+ -+ /* 2. Select reference clock(25M) and PHY mode (SATA) */ -+ if (lane->priv->xtal_is_40m) -+ ref_clk = REF_FREF_SEL_SERDES_40MHZ; -+ else -+ ref_clk = REF_FREF_SEL_SERDES_25MHZ; -+ -+ data = ref_clk | COMPHY_MODE_SATA; -+ mask = REF_FREF_SEL_MASK | COMPHY_MODE_MASK; -+ comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); -+ -+ /* 3. Use maximum PLL rate (no power save) */ -+ comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, -+ USE_MAX_PLL_RATE_BIT, USE_MAX_PLL_RATE_BIT); -+ -+ /* 4. Reset reserved bit */ -+ comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG, -+ 0x0, PHYCTRL_FRM_PIN_BIT); -+ -+ /* 5. Set vendor-specific configuration (It is done in sata driver) */ -+ /* XXX: in U-Boot below sequence was executed in this place, in Linux -+ * not. Now it is done only in U-Boot before this comphy -+ * initialization - tests shows that it works ok, but in case of any -+ * future problem it is left for reference. -+ * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); -+ * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); -+ */ -+ -+ /* Wait for > 55 us to allow PLL be enabled */ -+ udelay(PLL_SET_DELAY_US); -+ -+ /* Polling status */ -+ ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN, -+ PLL_READY_TX_BIT, COMPHY_PLL_SLEEP, -+ COMPHY_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(lane->dev, "Failed to lock SATA PLL\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, -+ bool is_1gbps) -+{ -+ int addr, fix_idx; -+ u16 val; -+ -+ fix_idx = 0; -+ for (addr = 0; addr < 512; addr++) { -+ /* -+ * All PHY register values are defined in full for 3.125Gbps -+ * SERDES speed. The values required for 1.25 Gbps are almost -+ * the same and only few registers should be "fixed" in -+ * comparison to 3.125 Gbps values. These register values are -+ * stored in "gbe_phy_init_fix" array. -+ */ -+ if (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) { -+ /* Use new value */ -+ val = gbe_phy_init_fix[fix_idx].value; -+ if (fix_idx < ARRAY_SIZE(gbe_phy_init_fix)) -+ fix_idx++; -+ } else { -+ val = gbe_phy_init[addr]; -+ } -+ -+ comphy_lane_reg_set(lane, addr, val, 0xFFFF); -+ } -+} -+ -+static int -+mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane) -+{ -+ u32 mask, data, speed_sel; -+ int ret; -+ -+ /* Set selector */ -+ ret = mvebu_a3700_comphy_set_phy_selector(lane); -+ if (ret) -+ return ret; -+ -+ /* -+ * 1. Reset PHY by setting PHY input port PIN_RESET=1. -+ * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep -+ * PHY TXP/TXN output to idle state during PHY initialization -+ * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. -+ */ -+ data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; -+ mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | -+ PIN_PU_TX_BIT | PHY_RX_INIT_BIT; -+ comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); -+ -+ /* 4. Release reset to the PHY by setting PIN_RESET=0. */ -+ data = 0x0; -+ mask = PIN_RESET_COMPHY_BIT; -+ comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); -+ -+ /* -+ * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY -+ * bit rate -+ */ -+ switch (lane->submode) { -+ case PHY_INTERFACE_MODE_SGMII: -+ case PHY_INTERFACE_MODE_1000BASEX: -+ /* SGMII 1G, SerDes speed 1.25G */ -+ speed_sel = SERDES_SPEED_1_25_G; -+ break; -+ case PHY_INTERFACE_MODE_2500BASEX: -+ /* 2500Base-X, SerDes speed 3.125G */ -+ speed_sel = SERDES_SPEED_3_125_G; -+ break; - default: -+ /* Other rates are not supported */ -+ dev_err(lane->dev, -+ "unsupported phy speed %d on comphy lane%d\n", -+ lane->submode, lane->id); - return -EINVAL; - } -+ data = GEN_RX_SEL_VALUE(speed_sel) | GEN_TX_SEL_VALUE(speed_sel); -+ mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; -+ comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); -+ -+ /* -+ * 6. Wait 10mS for bandgap and reference clocks to stabilize; then -+ * start SW programming. -+ */ -+ mdelay(10); -+ -+ /* 7. Program COMPHY register PHY_MODE */ -+ data = COMPHY_MODE_SERDES; -+ mask = COMPHY_MODE_MASK; -+ comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); -+ -+ /* -+ * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK -+ * source -+ */ -+ data = 0x0; -+ mask = PHY_REF_CLK_SEL; -+ comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); -+ -+ /* -+ * 9. Set correct reference clock frequency in COMPHY register -+ * REF_FREF_SEL. -+ */ -+ if (lane->priv->xtal_is_40m) -+ data = REF_FREF_SEL_SERDES_50MHZ; -+ else -+ data = REF_FREF_SEL_SERDES_25MHZ; -+ -+ mask = REF_FREF_SEL_MASK; -+ comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); -+ -+ /* 10. Program COMPHY register PHY_GEN_MAX[1:0] -+ * This step is mentioned in the flow received from verification team. -+ * However the PHY_GEN_MAX value is only meaningful for other interfaces -+ * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or -+ * PCIe speed 2.5/5 Gbps -+ */ -+ -+ /* -+ * 11. Program COMPHY register SEL_BITS to set correct parallel data -+ * bus width -+ */ -+ data = DATA_WIDTH_10BIT; -+ mask = SEL_DATA_WIDTH_MASK; -+ comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask); -+ -+ /* -+ * 12. As long as DFE function needs to be enabled in any mode, -+ * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F -+ * for real chip during COMPHY power on. -+ * The step 14 exists (and empty) in the original initialization flow -+ * obtained from the verification team. According to the functional -+ * specification DFE_UPDATE_EN already has the default value 0x3F -+ */ -+ -+ /* -+ * 13. Program COMPHY GEN registers. -+ * These registers should be programmed based on the lab testing result -+ * to achieve optimal performance. Please contact the CEA group to get -+ * the related GEN table during real chip bring-up. We only required to -+ * run though the entire registers programming flow defined by -+ * "comphy_gbe_phy_init" when the REF clock is 40 MHz. For REF clock -+ * 25 MHz the default values stored in PHY registers are OK. -+ */ -+ dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n", -+ lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G"); -+ if (lane->priv->xtal_is_40m) -+ comphy_gbe_phy_init(lane, -+ lane->submode != PHY_INTERFACE_MODE_2500BASEX); -+ -+ /* -+ * 14. [Simulation Only] should not be used for real chip. -+ * By pass power up calibration by programming EXT_FORCE_CAL_DONE -+ * (R02h[9]) to 1 to shorten COMPHY simulation time. -+ */ -+ -+ /* -+ * 15. [Simulation Only: should not be used for real chip] -+ * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training -+ * simulation time. -+ */ -+ -+ /* -+ * 16. Check the PHY Polarity invert bit -+ */ -+ data = 0x0; -+ if (lane->invert_tx) -+ data |= TXD_INVERT_BIT; -+ if (lane->invert_rx) -+ data |= RXD_INVERT_BIT; -+ mask = TXD_INVERT_BIT | RXD_INVERT_BIT; -+ comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); -+ -+ /* -+ * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to -+ * start PHY power up sequence. All the PHY register programming should -+ * be done before PIN_PU_PLL=1. There should be no register programming -+ * for normal PHY operation from this point. -+ */ -+ data = PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; -+ mask = data; -+ comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); -+ -+ /* -+ * 18. Wait for PHY power up sequence to finish by checking output ports -+ * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. -+ */ -+ ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, -+ PHY_PLL_READY_TX_BIT | -+ PHY_PLL_READY_RX_BIT, -+ COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", -+ lane->id); -+ return ret; -+ } -+ -+ /* -+ * 19. Set COMPHY input port PIN_TX_IDLE=0 -+ */ -+ comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT); -+ -+ /* -+ * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To -+ * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the -+ * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to -+ * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please -+ * refer to RX initialization part for details. -+ */ -+ comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, -+ PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); -+ -+ ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, -+ PHY_PLL_READY_TX_BIT | -+ PHY_PLL_READY_RX_BIT, -+ COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", -+ lane->id); -+ return ret; -+ } -+ -+ ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, -+ PHY_RX_INIT_DONE_BIT, -+ COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n", -+ lane->id); -+ return ret; -+ } -+ -+ return 0; - } - --static int mvebu_a3700_comphy_get_fw_mode(int lane, -+static int -+mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane) -+{ -+ u32 mask, data, cfg, ref_clk; -+ int ret; -+ -+ /* Set phy seclector */ -+ ret = mvebu_a3700_comphy_set_phy_selector(lane); -+ if (ret) -+ return ret; -+ -+ /* -+ * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The -+ * register belong to UTMI module, so it is set in UTMI phy driver. -+ */ -+ -+ /* -+ * 1. Set PRD_TXDEEMPH (3.5db de-emph) -+ */ -+ data = PRD_TXDEEMPH0_MASK; -+ mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | -+ CFG_TX_ALIGN_POS_MASK; -+ comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask); -+ -+ /* -+ * 2. Set BIT0: enable transmitter in high impedance mode -+ * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency -+ * Set BIT6: Tx detect Rx at HiZ mode -+ * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db -+ * together with bit 0 of COMPHY_PIPE_LANE_CFG0 register -+ */ -+ data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; -+ mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | -+ TX_ELEC_IDLE_MODE_EN; -+ comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask); -+ -+ /* -+ * 3. Set Spread Spectrum Clock Enabled -+ */ -+ comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4, -+ SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN); -+ -+ /* -+ * 4. Set Override Margining Controls From the MAC: -+ * Use margining signals from lane configuration -+ */ -+ comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL, -+ MODE_MARGIN_OVERRIDE, 0xFFFF); -+ -+ /* -+ * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles -+ * set Mode Clock Source = PCLK is generated from REFCLK -+ */ -+ data = 0x0; -+ mask = MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE_MASK | -+ BUNDLE_SAMPLE_CTRL | PLL_READY_DLY_MASK; -+ comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask); -+ -+ /* -+ * 6. Set G2 Spread Spectrum Clock Amplitude at 4K -+ */ -+ comphy_lane_reg_set(lane, COMPHY_GEN2_SET2, -+ GS2_TX_SSC_AMP_4128, GS2_TX_SSC_AMP_MASK); -+ -+ /* -+ * 7. Unset G3 Spread Spectrum Clock Amplitude -+ * set G3 TX and RX Register Master Current Select -+ */ -+ data = GS2_VREG_RXTX_MAS_ISET_60U; -+ mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK | -+ GS2_RSVD_6_0_MASK; -+ comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask); -+ -+ /* -+ * 8. Check crystal jumper setting and program the Power and PLL Control -+ * accordingly Change RX wait -+ */ -+ if (lane->priv->xtal_is_40m) { -+ ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; -+ cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; -+ } else { -+ ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; -+ cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; -+ } -+ -+ data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | -+ PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_USB3 | ref_clk; -+ mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | -+ PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | COMPHY_MODE_MASK | -+ REF_FREF_SEL_MASK; -+ comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); -+ -+ data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; -+ mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | -+ CFG_PM_RXDLOZ_WAIT_MASK; -+ comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); -+ -+ /* -+ * 9. Enable idle sync -+ */ -+ comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, -+ IDLE_SYNC_EN, IDLE_SYNC_EN); -+ -+ /* -+ * 10. Enable the output of 500M clock -+ */ -+ comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN); -+ -+ /* -+ * 11. Set 20-bit data width -+ */ -+ comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, -+ DATA_WIDTH_20BIT, 0xFFFF); -+ -+ /* -+ * 12. Override Speed_PLL value and use MAC PLL -+ */ -+ data = SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT; -+ mask = 0xFFFF; -+ comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask); -+ -+ /* -+ * 13. Check the Polarity invert bit -+ */ -+ data = 0x0; -+ if (lane->invert_tx) -+ data |= TXD_INVERT_BIT; -+ if (lane->invert_rx) -+ data |= RXD_INVERT_BIT; -+ mask = TXD_INVERT_BIT | RXD_INVERT_BIT; -+ comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); -+ -+ /* -+ * 14. Set max speed generation to USB3.0 5Gbps -+ */ -+ comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN, -+ PHY_GEN_MAX_USB3_5G, PHY_GEN_MAX_MASK); -+ -+ /* -+ * 15. Set capacitor value for FFE gain peaking to 0xF -+ */ -+ comphy_lane_reg_set(lane, COMPHY_GEN2_SET3, -+ GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK); -+ -+ /* -+ * 16. Release SW reset -+ */ -+ data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; -+ mask = 0xFFFF; -+ comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); -+ -+ /* Wait for > 55 us to allow PCLK be enabled */ -+ udelay(PLL_SET_DELAY_US); -+ -+ ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, -+ COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(lane->dev, "Failed to lock USB3 PLL\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int -+mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane) -+{ -+ u32 mask, data, ref_clk; -+ int ret; -+ -+ /* Configure phy selector for PCIe */ -+ ret = mvebu_a3700_comphy_set_phy_selector(lane); -+ if (ret) -+ return ret; -+ -+ /* 1. Enable max PLL. */ -+ comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, -+ USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); -+ -+ /* 2. Select 20 bit SERDES interface. */ -+ comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, -+ CFG_SEL_20B, CFG_SEL_20B); -+ -+ /* 3. Force to use reg setting for PCIe mode */ -+ comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1, -+ SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); -+ -+ /* 4. Change RX wait */ -+ data = CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT; -+ mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | -+ CFG_PM_RXDLOZ_WAIT_MASK; -+ comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); -+ -+ /* 5. Enable idle sync */ -+ comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, -+ IDLE_SYNC_EN, IDLE_SYNC_EN); -+ -+ /* 6. Enable the output of 100M/125M/500M clock */ -+ data = CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN; -+ mask = data; -+ comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); -+ -+ /* -+ * 7. Enable TX, PCIE global register, 0xd0074814, it is done in -+ * PCI-E driver -+ */ -+ -+ /* -+ * 8. Check crystal jumper setting and program the Power and PLL -+ * Control accordingly -+ */ -+ -+ if (lane->priv->xtal_is_40m) -+ ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; -+ else -+ ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; -+ -+ data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | -+ PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_PCIE | ref_clk; -+ mask = 0xFFFF; -+ comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); -+ -+ /* 9. Override Speed_PLL value and use MAC PLL */ -+ comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, -+ SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, -+ 0xFFFF); -+ -+ /* 10. Check the Polarity invert bit */ -+ data = 0x0; -+ if (lane->invert_tx) -+ data |= TXD_INVERT_BIT; -+ if (lane->invert_rx) -+ data |= RXD_INVERT_BIT; -+ mask = TXD_INVERT_BIT | RXD_INVERT_BIT; -+ comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); -+ -+ /* 11. Release SW reset */ -+ data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32; -+ mask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK; -+ comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); -+ -+ /* Wait for > 55 us to allow PCLK be enabled */ -+ udelay(PLL_SET_DELAY_US); -+ -+ ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, -+ COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); -+ if (ret) { -+ dev_err(lane->dev, "Failed to lock PCIE PLL\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void -+mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane) -+{ -+ /* -+ * Currently the USB3 MAC sets the USB3 PHY to low state, so we do not -+ * need to power off USB3 PHY again. -+ */ -+} -+ -+static void -+mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane) -+{ -+ /* Set phy isolation mode */ -+ comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, -+ PHY_ISOLATE_MODE, PHY_ISOLATE_MODE); -+ -+ /* Power off PLL, Tx, Rx */ -+ comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, -+ 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); -+} -+ -+static void -+mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane) -+{ -+ u32 mask, data; -+ -+ data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | PIN_PU_IVREF_BIT | -+ PHY_RX_INIT_BIT; -+ mask = data; -+ comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); -+} -+ -+static void -+mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane) -+{ -+ /* Power off PLL, Tx, Rx */ -+ comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, -+ 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); -+} -+ -+static int mvebu_a3700_comphy_reset(struct phy *phy) -+{ -+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); -+ u16 mask, data; -+ -+ dev_dbg(lane->dev, "resetting lane %d\n", lane->id); -+ -+ /* COMPHY reset for internal logic */ -+ comphy_lane_reg_set(lane, COMPHY_SFT_RESET, -+ SFT_RST_NO_REG, SFT_RST_NO_REG); -+ -+ /* COMPHY register reset (cleared automatically) */ -+ comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST); -+ -+ /* PIPE soft and register reset */ -+ data = PIPE_SOFT_RESET | PIPE_REG_RESET; -+ mask = data; -+ comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); -+ -+ /* Release PIPE register reset */ -+ comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, -+ 0x0, PIPE_REG_RESET); -+ -+ /* Reset SB configuration register (only for lanes 0 and 1) */ -+ if (lane->id == 0 || lane->id == 1) { -+ u32 mask, data; -+ -+ data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | -+ PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; -+ mask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT; -+ comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); -+ } -+ -+ return 0; -+} -+ -+static bool mvebu_a3700_comphy_check_mode(int lane, - enum phy_mode mode, - int submode) - { -@@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mod - - /* Unused PHY mux value is 0x0 */ - if (mode == PHY_MODE_INVALID) -- return -EINVAL; -+ return false; - - for (i = 0; i < n; i++) { - if (mvebu_a3700_comphy_modes[i].lane == lane && -@@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mod - } - - if (i == n) -- return -EINVAL; -+ return false; - -- return mvebu_a3700_comphy_modes[i].fw_mode; -+ return true; - } - - static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode, - int submode) - { - struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); -- int fw_mode; -- -- if (submode == PHY_INTERFACE_MODE_1000BASEX) -- submode = PHY_INTERFACE_MODE_SGMII; - -- fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode, -- submode); -- if (fw_mode < 0) { -+ if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) { - dev_err(lane->dev, "invalid COMPHY mode\n"); -- return fw_mode; -+ return -EINVAL; - } - -+ /* Mode cannot be changed while the PHY is powered on */ -+ if (phy->power_count && -+ (lane->mode != mode || lane->submode != submode)) -+ return -EBUSY; -+ -+ /* If changing mode, ensure reset is called */ -+ if (lane->mode != PHY_MODE_INVALID && lane->mode != mode) -+ lane->needs_reset = true; -+ - /* Just remember the mode, ->power_on() will do the real setup */ - lane->mode = mode; - lane->submode = submode; -@@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(s - static int mvebu_a3700_comphy_power_on(struct phy *phy) - { - struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); -- u32 fw_param; -- int fw_mode; -- int fw_port; - int ret; - -- fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, -- lane->mode, lane->submode); -- if (fw_mode < 0) { -+ if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, -+ lane->submode)) { - dev_err(lane->dev, "invalid COMPHY mode\n"); -- return fw_mode; -+ return -EINVAL; -+ } -+ -+ if (lane->needs_reset) { -+ ret = mvebu_a3700_comphy_reset(phy); -+ if (ret) -+ return ret; -+ -+ lane->needs_reset = false; - } - - switch (lane->mode) { - case PHY_MODE_USB_HOST_SS: - dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id); -- fw_param = COMPHY_FW_MODE(fw_mode); -- break; -+ return mvebu_a3700_comphy_usb3_power_on(lane); - case PHY_MODE_SATA: - dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); -- fw_param = COMPHY_FW_MODE(fw_mode); -- break; -+ return mvebu_a3700_comphy_sata_power_on(lane); - case PHY_MODE_ETHERNET: -- fw_port = (lane->id == 0) ? 1 : 0; -- switch (lane->submode) { -- case PHY_INTERFACE_MODE_SGMII: -- dev_dbg(lane->dev, "set lane %d to SGMII mode\n", -- lane->id); -- fw_param = COMPHY_FW_NET(fw_mode, fw_port, -- COMPHY_FW_SPEED_1_25G); -- break; -- case PHY_INTERFACE_MODE_2500BASEX: -- dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n", -- lane->id); -- fw_param = COMPHY_FW_NET(fw_mode, fw_port, -- COMPHY_FW_SPEED_3_125G); -- break; -- default: -- dev_err(lane->dev, "unsupported PHY submode (%d)\n", -- lane->submode); -- return -ENOTSUPP; -- } -- break; -+ dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id); -+ return mvebu_a3700_comphy_ethernet_power_on(lane); - case PHY_MODE_PCIE: - dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); -- fw_param = COMPHY_FW_PCIE(fw_mode, COMPHY_FW_SPEED_5G, -- phy->attrs.bus_width); -- break; -+ return mvebu_a3700_comphy_pcie_power_on(lane); - default: - dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode); -- return -ENOTSUPP; -+ return -EOPNOTSUPP; - } -- -- ret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param); -- if (ret == -EOPNOTSUPP) -- dev_err(lane->dev, -- "unsupported SMC call, try updating your firmware\n"); -- -- return ret; - } - - static int mvebu_a3700_comphy_power_off(struct phy *phy) - { - struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); - -- return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0); -+ switch (lane->mode) { -+ case PHY_MODE_USB_HOST_SS: -+ mvebu_a3700_comphy_usb3_power_off(lane); -+ return 0; -+ case PHY_MODE_SATA: -+ mvebu_a3700_comphy_sata_power_off(lane); -+ return 0; -+ case PHY_MODE_ETHERNET: -+ mvebu_a3700_comphy_ethernet_power_off(lane); -+ return 0; -+ case PHY_MODE_PCIE: -+ mvebu_a3700_comphy_pcie_power_off(lane); -+ return 0; -+ default: -+ dev_err(lane->dev, "invalid COMPHY mode\n"); -+ return -EINVAL; -+ } - } - - static const struct phy_ops mvebu_a3700_comphy_ops = { - .power_on = mvebu_a3700_comphy_power_on, - .power_off = mvebu_a3700_comphy_power_off, -+ .reset = mvebu_a3700_comphy_reset, - .set_mode = mvebu_a3700_comphy_set_mode, - .owner = THIS_MODULE, - }; -@@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xl - return ERR_PTR(-EINVAL); - } - -+ lane->invert_tx = args->args[1] & BIT(0); -+ lane->invert_rx = args->args[1] & BIT(1); -+ - return phy; - } - - static int mvebu_a3700_comphy_probe(struct platform_device *pdev) - { -+ struct mvebu_a3700_comphy_priv *priv; - struct phy_provider *provider; - struct device_node *child; -+ struct resource *res; -+ struct clk *clk; -+ int ret; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ spin_lock_init(&priv->lock); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "comphy"); -+ priv->comphy_regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(priv->comphy_regs)) -+ return PTR_ERR(priv->comphy_regs); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, -+ "lane1_pcie_gbe"); -+ priv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(priv->lane1_phy_regs)) -+ return PTR_ERR(priv->lane1_phy_regs); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, -+ "lane0_usb3_gbe"); -+ priv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(priv->lane0_phy_regs)) -+ return PTR_ERR(priv->lane0_phy_regs); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, -+ "lane2_sata_usb3"); -+ priv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(priv->lane2_phy_indirect)) -+ return PTR_ERR(priv->lane2_phy_indirect); -+ -+ /* -+ * Driver needs to know if reference xtal clock is 40MHz or 25MHz. -+ * Old DT bindings do not have xtal clk present. So do not fail here -+ * and expects that default 25MHz reference clock is used. -+ */ -+ clk = clk_get(&pdev->dev, "xtal"); -+ if (IS_ERR(clk)) { -+ if (PTR_ERR(clk) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; -+ dev_warn(&pdev->dev, "missing 'xtal' clk (%ld)\n", -+ PTR_ERR(clk)); -+ } else { -+ ret = clk_prepare_enable(clk); -+ if (ret) { -+ dev_warn(&pdev->dev, "enabling xtal clk failed (%d)\n", -+ ret); -+ } else { -+ if (clk_get_rate(clk) == 40000000) -+ priv->xtal_is_40m = true; -+ clk_disable_unprepare(clk); -+ } -+ clk_put(clk); -+ } -+ -+ dev_set_drvdata(&pdev->dev, priv); - - for_each_available_child_of_node(pdev->dev.of_node, child) { - struct mvebu_a3700_comphy_lane *lane; -@@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(stru - continue; - } - -- if (lane_id >= MVEBU_A3700_COMPHY_LANES) { -+ if (lane_id >= 3) { - dev_err(&pdev->dev, "invalid 'reg' property\n"); - continue; - } -@@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(stru - return PTR_ERR(phy); - } - -+ lane->priv = priv; - lane->dev = &pdev->dev; - lane->mode = PHY_MODE_INVALID; - lane->submode = PHY_INTERFACE_MODE_NA; - lane->id = lane_id; -+ lane->invert_tx = false; -+ lane->invert_rx = false; - phy_set_drvdata(phy, lane); -+ -+ /* -+ * To avoid relying on the bootloader/firmware configuration, -+ * power off all comphys. -+ */ -+ mvebu_a3700_comphy_reset(phy); -+ lane->needs_reset = false; - } - - provider = devm_of_phy_provider_register(&pdev->dev, -@@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a370 - module_platform_driver(mvebu_a3700_comphy_driver); - - MODULE_AUTHOR("Miquèl Raynal "); -+MODULE_AUTHOR("Pali Rohár "); -+MODULE_AUTHOR("Marek Behún "); - MODULE_DESCRIPTION("Common PHY driver for A3700"); - MODULE_LICENSE("GPL v2"); diff --git a/target/linux/generic/pending-5.10/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch b/target/linux/generic/pending-5.10/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch deleted file mode 100644 index 33203a154d..0000000000 --- a/target/linux/generic/pending-5.10/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 66c51c39fd4bf05e99debf0e71de5704231c57dc Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:26:26 +0200 -Subject: [PATCH] arm64: dts: marvell: armada-37xx: Add xtal clock to comphy - node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Kernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the -reference xtal clock. So add missing xtal clock source into comphy device -tree node. If the property is not present, the driver defaults to 25 MHz -xtal rate (which, as far as we know, is used by all the existing boards). - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún ---- - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -@@ -265,6 +265,8 @@ - "lane2_sata_usb3"; - #address-cells = <1>; - #size-cells = <0>; -+ clocks = <&xtalclk>; -+ clock-names = "xtal"; - - comphy0: phy@0 { - reg = <0>; diff --git a/target/linux/generic/pending-5.10/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch b/target/linux/generic/pending-5.10/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch deleted file mode 100644 index 3c994d2548..0000000000 --- a/target/linux/generic/pending-5.10/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 750bb44dbbe9dfb4ba3e1f8a746b831b39ba3cd9 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:35:57 +0200 -Subject: [PATCH] Revert "ata: ahci: mvebu: Make SATA PHY optional for Armada - 3720" -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This reverts commit 45aefe3d2251e4e229d7662052739f96ad1d08d9. - -Armada 3720 PHY driver (phy-mvebu-a3700-comphy.c) does not return --EOPNOTSUPP from phy_power_on() callback anymore. - -So remove AHCI_HFLAG_IGN_NOTSUPP_POWER_ON flag from Armada 3720 plat data. - -AHCI_HFLAG_IGN_NOTSUPP_POWER_ON is not used by any other ahci driver, so -remove this flag completely. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Acked-by: Miquel Raynal ---- - drivers/ata/ahci.h | 2 -- - drivers/ata/ahci_mvebu.c | 2 +- - drivers/ata/libahci_platform.c | 2 +- - 3 files changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/ata/ahci.h -+++ b/drivers/ata/ahci.h -@@ -240,8 +240,6 @@ enum { - as default lpm_policy */ - AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during - suspend/resume */ -- AHCI_HFLAG_IGN_NOTSUPP_POWER_ON = (1 << 27), /* ignore -EOPNOTSUPP -- from phy_power_on() */ - AHCI_HFLAG_NO_SXS = (1 << 28), /* SXS not supported */ - - /* ap->flags bits */ ---- a/drivers/ata/ahci_mvebu.c -+++ b/drivers/ata/ahci_mvebu.c -@@ -227,7 +227,7 @@ static const struct ahci_mvebu_plat_data - - static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = { - .plat_config = ahci_mvebu_armada_3700_config, -- .flags = AHCI_HFLAG_SUSPEND_PHYS | AHCI_HFLAG_IGN_NOTSUPP_POWER_ON, -+ .flags = AHCI_HFLAG_SUSPEND_PHYS, - }; - - static const struct of_device_id ahci_mvebu_of_match[] = { ---- a/drivers/ata/libahci_platform.c -+++ b/drivers/ata/libahci_platform.c -@@ -59,7 +59,7 @@ int ahci_platform_enable_phys(struct ahc - } - - rc = phy_power_on(hpriv->phys[i]); -- if (rc && !(rc == -EOPNOTSUPP && (hpriv->flags & AHCI_HFLAG_IGN_NOTSUPP_POWER_ON))) { -+ if (rc) { - phy_exit(hpriv->phys[i]); - goto disable_phys; - } diff --git a/target/linux/generic/pending-5.10/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch b/target/linux/generic/pending-5.10/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch deleted file mode 100644 index b8a3e880ce..0000000000 --- a/target/linux/generic/pending-5.10/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch +++ /dev/null @@ -1,163 +0,0 @@ -From 9f0dfb279b1dd505d5e10b10e4a78a62030978d8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:40:06 +0200 -Subject: [PATCH] Revert "usb: host: xhci: mvebu: make USB 3.0 PHY optional for - Armada 3720" -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This reverts commit 3241929b67d28c83945d3191c6816a3271fd6b85. - -Armada 3720 phy driver (phy-mvebu-a3700-comphy.c) does not return --EOPNOTSUPP from phy_power_on() callback anymore. - -So remove XHCI_SKIP_PHY_INIT flag from xhci_mvebu_a3700_plat_setup() and -then also whole xhci_mvebu_a3700_plat_setup() function which is there just -to handle -EOPNOTSUPP for XHCI_SKIP_PHY_INIT. - -xhci plat_setup callback is not used by any other xhci plat driver, so -remove this callback completely. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Acked-by: Miquel Raynal ---- - drivers/usb/host/xhci-mvebu.c | 42 ----------------------------------- - drivers/usb/host/xhci-mvebu.h | 6 ----- - drivers/usb/host/xhci-plat.c | 20 +---------------- - drivers/usb/host/xhci-plat.h | 1 - - 4 files changed, 1 insertion(+), 68 deletions(-) - ---- a/drivers/usb/host/xhci-mvebu.c -+++ b/drivers/usb/host/xhci-mvebu.c -@@ -8,7 +8,6 @@ - #include - #include - #include --#include - - #include - #include -@@ -74,47 +73,6 @@ int xhci_mvebu_mbus_init_quirk(struct us - - return 0; - } -- --int xhci_mvebu_a3700_plat_setup(struct usb_hcd *hcd) --{ -- struct xhci_hcd *xhci = hcd_to_xhci(hcd); -- struct device *dev = hcd->self.controller; -- struct phy *phy; -- int ret; -- -- /* Old bindings miss the PHY handle */ -- phy = of_phy_get(dev->of_node, "usb3-phy"); -- if (IS_ERR(phy) && PTR_ERR(phy) == -EPROBE_DEFER) -- return -EPROBE_DEFER; -- else if (IS_ERR(phy)) -- goto phy_out; -- -- ret = phy_init(phy); -- if (ret) -- goto phy_put; -- -- ret = phy_set_mode(phy, PHY_MODE_USB_HOST_SS); -- if (ret) -- goto phy_exit; -- -- ret = phy_power_on(phy); -- if (ret == -EOPNOTSUPP) { -- /* Skip initializatin of XHCI PHY when it is unsupported by firmware */ -- dev_warn(dev, "PHY unsupported by firmware\n"); -- xhci->quirks |= XHCI_SKIP_PHY_INIT; -- } -- if (ret) -- goto phy_exit; -- -- phy_power_off(phy); --phy_exit: -- phy_exit(phy); --phy_put: -- of_phy_put(phy); --phy_out: -- -- return 0; --} - - int xhci_mvebu_a3700_init_quirk(struct usb_hcd *hcd) - { ---- a/drivers/usb/host/xhci-mvebu.h -+++ b/drivers/usb/host/xhci-mvebu.h -@@ -12,18 +12,12 @@ struct usb_hcd; - - #if IS_ENABLED(CONFIG_USB_XHCI_MVEBU) - int xhci_mvebu_mbus_init_quirk(struct usb_hcd *hcd); --int xhci_mvebu_a3700_plat_setup(struct usb_hcd *hcd); - int xhci_mvebu_a3700_init_quirk(struct usb_hcd *hcd); - #else - static inline int xhci_mvebu_mbus_init_quirk(struct usb_hcd *hcd) - { - return 0; - } -- --static inline int xhci_mvebu_a3700_plat_setup(struct usb_hcd *hcd) --{ -- return 0; --} - - static inline int xhci_mvebu_a3700_init_quirk(struct usb_hcd *hcd) - { ---- a/drivers/usb/host/xhci-plat.c -+++ b/drivers/usb/host/xhci-plat.c -@@ -44,16 +44,6 @@ static void xhci_priv_plat_start(struct - priv->plat_start(hcd); - } - --static int xhci_priv_plat_setup(struct usb_hcd *hcd) --{ -- struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd); -- -- if (!priv->plat_setup) -- return 0; -- -- return priv->plat_setup(hcd); --} -- - static int xhci_priv_init_quirk(struct usb_hcd *hcd) - { - struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd); -@@ -121,7 +111,6 @@ static const struct xhci_plat_priv xhci_ - }; - - static const struct xhci_plat_priv xhci_plat_marvell_armada3700 = { -- .plat_setup = xhci_mvebu_a3700_plat_setup, - .init_quirk = xhci_mvebu_a3700_init_quirk, - }; - -@@ -341,14 +330,7 @@ static int xhci_plat_probe(struct platfo - - hcd->tpl_support = of_usb_host_tpl_support(sysdev->of_node); - xhci->shared_hcd->tpl_support = hcd->tpl_support; -- -- if (priv) { -- ret = xhci_priv_plat_setup(hcd); -- if (ret) -- goto disable_usb_phy; -- } -- -- if ((xhci->quirks & XHCI_SKIP_PHY_INIT) || (priv && (priv->quirks & XHCI_SKIP_PHY_INIT))) -+ if (priv && (priv->quirks & XHCI_SKIP_PHY_INIT)) - hcd->skip_phy_initialization = 1; - - if (priv && (priv->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK)) ---- a/drivers/usb/host/xhci-plat.h -+++ b/drivers/usb/host/xhci-plat.h -@@ -13,7 +13,6 @@ - struct xhci_plat_priv { - const char *firmware_name; - unsigned long long quirks; -- int (*plat_setup)(struct usb_hcd *); - void (*plat_start)(struct usb_hcd *); - int (*init_quirk)(struct usb_hcd *); - int (*suspend_quirk)(struct usb_hcd *); diff --git a/target/linux/generic/pending-5.10/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch b/target/linux/generic/pending-5.10/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch deleted file mode 100644 index 3ac9269812..0000000000 --- a/target/linux/generic/pending-5.10/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 9a352062b7e3857742389dff6f64393481dc755e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= -Date: Thu, 23 Sep 2021 19:37:05 +0200 -Subject: [PATCH] Revert "PCI: aardvark: Fix initialization with old Marvell's - Arm Trusted Firmware" -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This reverts commit b0c6ae0f8948a2be6bf4e8b4bbab9ca1343289b6. - -Armada 3720 phy driver (phy-mvebu-a3700-comphy.c) does not return --EOPNOTSUPP from phy_power_on() callback anymore. - -So remove dead code which handles -EOPNOTSUPP return value. - -Signed-off-by: Pali Rohár -Signed-off-by: Marek Behún -Acked-by: Miquel Raynal ---- - drivers/pci/controller/pci-aardvark.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -1634,9 +1634,7 @@ static int advk_pcie_enable_phy(struct a - } - - ret = phy_power_on(pcie->phy); -- if (ret == -EOPNOTSUPP) { -- dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); -- } else if (ret) { -+ if (ret) { - phy_exit(pcie->phy); - return ret; - } diff --git a/target/linux/generic/pending-5.10/920-mangle_bootargs.patch b/target/linux/generic/pending-5.10/920-mangle_bootargs.patch deleted file mode 100644 index 390152078f..0000000000 --- a/target/linux/generic/pending-5.10/920-mangle_bootargs.patch +++ /dev/null @@ -1,71 +0,0 @@ -From: Imre Kaloz -Subject: init: add CONFIG_MANGLE_BOOTARGS and disable it by default - -Enabling this option renames the bootloader supplied root= -and rootfstype= variables, which might have to be know but -would break the automatisms OpenWrt uses. - -Signed-off-by: Imre Kaloz ---- - init/Kconfig | 9 +++++++++ - init/main.c | 24 ++++++++++++++++++++++++ - 2 files changed, 33 insertions(+) - ---- a/init/Kconfig -+++ b/init/Kconfig -@@ -1817,6 +1817,15 @@ config EMBEDDED - an embedded system so certain expert options are available - for configuration. - -+config MANGLE_BOOTARGS -+ bool "Rename offending bootargs" -+ depends on EXPERT -+ help -+ Sometimes the bootloader passed bogus root= and rootfstype= -+ parameters to the kernel, and while you want to ignore them, -+ you need to know the values f.e. to support dual firmware -+ layouts on the flash. -+ - config HAVE_PERF_EVENTS - bool - help ---- a/init/main.c -+++ b/init/main.c -@@ -608,6 +608,29 @@ static inline void setup_nr_cpu_ids(void - static inline void smp_prepare_cpus(unsigned int maxcpus) { } - #endif - -+#ifdef CONFIG_MANGLE_BOOTARGS -+static void __init mangle_bootargs(char *command_line) -+{ -+ char *rootdev; -+ char *rootfs; -+ -+ rootdev = strstr(command_line, "root=/dev/mtdblock"); -+ -+ if (rootdev) -+ strncpy(rootdev, "mangled_rootblock=", 18); -+ -+ rootfs = strstr(command_line, "rootfstype"); -+ -+ if (rootfs) -+ strncpy(rootfs, "mangled_fs", 10); -+ -+} -+#else -+static void __init mangle_bootargs(char *command_line) -+{ -+} -+#endif -+ - /* - * We need to store the untouched command line for future reference. - * We also need to store the touched command line since the parameter -@@ -869,6 +892,7 @@ asmlinkage __visible void __init __no_sa - pr_notice("%s", linux_banner); - early_security_init(); - setup_arch(&command_line); -+ mangle_bootargs(command_line); - setup_boot_config(command_line); - setup_command_line(command_line); - setup_nr_cpu_ids(); diff --git a/target/linux/ipq806x/config-5.10 b/target/linux/ipq806x/config-5.10 deleted file mode 100644 index 1f1af06b29..0000000000 --- a/target/linux/ipq806x/config-5.10 +++ /dev/null @@ -1,492 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APQ_GCC_8084 is not set -# CONFIG_APQ_MMCC_8084 is not set -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -# CONFIG_ARCH_IPQ40XX is not set -CONFIG_ARCH_KEEP_MEMBLOCK=y -# CONFIG_ARCH_MDM9615 is not set -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MSM8960=y -CONFIG_ARCH_MSM8974=y -CONFIG_ARCH_MSM8X60=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_MODULE_PLTS=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_QCOM_CPUFREQ_HW is not set -CONFIG_ARM_QCOM_CPUFREQ_KRAIT=y -CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -CONFIG_ARM_QCOM_SPM_CPUIDLE=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_AT803X_PHY=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_QCOM=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_QCOM_RNG=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -# CONFIG_DWMAC_GENERIC is not set -CONFIG_DWMAC_IPQ806X=y -# CONFIG_DWMAC_QCOM_ETHQOS is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -# CONFIG_I2C_QCOM_CCI is not set -CONFIG_I2C_QUP=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IPQ_APSS_PLL is not set -# CONFIG_IPQ_GCC_4019 is not set -# CONFIG_IPQ_GCC_6018 is not set -CONFIG_IPQ_GCC_806X=y -# CONFIG_IPQ_GCC_8074 is not set -# CONFIG_IPQ_LCC_806X is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_KPSS_XCC=y -CONFIG_KRAITCC=y -CONFIG_KRAIT_CLOCKS=y -CONFIG_KRAIT_L2_ACCESSORS=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MDIO_IPQ8064=y -# CONFIG_MDM_GCC_9615 is not set -# CONFIG_MDM_LCC_9615 is not set -CONFIG_MEMFD_CREATE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_QCOM_RPM=y -# CONFIG_MFD_SPMI_PMIC is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_ARMMMCI=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=16 -CONFIG_MMC_CQHCI=y -CONFIG_MMC_QCOM_DML=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_MSM=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MSM_GCC_8660=y -# CONFIG_MSM_GCC_8916 is not set -# CONFIG_MSM_GCC_8939 is not set -# CONFIG_MSM_GCC_8960 is not set -# CONFIG_MSM_GCC_8974 is not set -# CONFIG_MSM_GCC_8994 is not set -# CONFIG_MSM_GCC_8996 is not set -# CONFIG_MSM_GCC_8998 is not set -# CONFIG_MSM_GPUCC_8998 is not set -# CONFIG_MSM_IOMMU is not set -# CONFIG_MSM_LCC_8960 is not set -# CONFIG_MSM_MMCC_8960 is not set -# CONFIG_MSM_MMCC_8974 is not set -# CONFIG_MSM_MMCC_8996 is not set -# CONFIG_MSM_MMCC_8998 is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_QCOM=y -CONFIG_MTD_QCOMSMEM_PARTS=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_QCA8K=y -CONFIG_NET_DSA_TAG_QCA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_QCOM_QFPROM=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_QCOM=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_XPCS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_QCOM_APQ8064_SATA is not set -# CONFIG_PHY_QCOM_IPQ4019_USB is not set -CONFIG_PHY_QCOM_IPQ806X_SATA=y -# CONFIG_PHY_QCOM_IPQ806X_USB is not set -# CONFIG_PHY_QCOM_PCIE2 is not set -# CONFIG_PHY_QCOM_QMP is not set -# CONFIG_PHY_QCOM_QUSB2 is not set -# CONFIG_PHY_QCOM_USB_HS_28NM is not set -# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set -# CONFIG_PHY_QCOM_USB_SS is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_APQ8064 is not set -# CONFIG_PINCTRL_APQ8084 is not set -# CONFIG_PINCTRL_IPQ4019 is not set -# CONFIG_PINCTRL_IPQ6018 is not set -CONFIG_PINCTRL_IPQ8064=y -# CONFIG_PINCTRL_IPQ8074 is not set -# CONFIG_PINCTRL_MDM9615 is not set -CONFIG_PINCTRL_MSM=y -# CONFIG_PINCTRL_MSM8226 is not set -# CONFIG_PINCTRL_MSM8660 is not set -# CONFIG_PINCTRL_MSM8916 is not set -# CONFIG_PINCTRL_MSM8960 is not set -# CONFIG_PINCTRL_MSM8976 is not set -# CONFIG_PINCTRL_MSM8994 is not set -# CONFIG_PINCTRL_MSM8996 is not set -# CONFIG_PINCTRL_MSM8998 is not set -# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set -# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set -# CONFIG_PINCTRL_QCS404 is not set -# CONFIG_PINCTRL_SC7180 is not set -# CONFIG_PINCTRL_SDM660 is not set -# CONFIG_PINCTRL_SDM845 is not set -# CONFIG_PINCTRL_SM8150 is not set -# CONFIG_PINCTRL_SM8250 is not set -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_MSM=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK=y -# CONFIG_QCOM_A53PLL is not set -CONFIG_QCOM_ADM=y -CONFIG_QCOM_BAM_DMA=y -CONFIG_QCOM_CLK_RPM=y -# CONFIG_QCOM_COMMAND_DB is not set -# CONFIG_QCOM_CPR is not set -# CONFIG_QCOM_EBI2 is not set -# CONFIG_QCOM_GENI_SE is not set -CONFIG_QCOM_GSBI=y -CONFIG_QCOM_HFPLL=y -# CONFIG_QCOM_IOMMU is not set -# CONFIG_QCOM_LLCC is not set -# CONFIG_QCOM_OCMEM is not set -# CONFIG_QCOM_PDC is not set -# CONFIG_QCOM_RMTFS_MEM is not set -CONFIG_QCOM_RPMCC=y -# CONFIG_QCOM_RPMH is not set -CONFIG_QCOM_SCM=y -# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set -CONFIG_QCOM_SMEM=y -# CONFIG_QCOM_SMSM is not set -# CONFIG_QCOM_SOCINFO is not set -CONFIG_QCOM_TCSR=y -CONFIG_QCOM_TSENS=y -CONFIG_QCOM_WDT=y -# CONFIG_QCS_GCC_404 is not set -# CONFIG_QCS_Q6SSTOP_404 is not set -# CONFIG_QCS_TURING_404 is not set -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_QCOM_LABIBB is not set -CONFIG_REGULATOR_QCOM_RPM=y -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set -CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_QCOM_AOSS is not set -# CONFIG_RESET_QCOM_PDC is not set -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SC_DISPCC_7180 is not set -# CONFIG_SC_GCC_7180 is not set -# CONFIG_SC_GPUCC_7180 is not set -# CONFIG_SC_LPASS_CORECC_7180 is not set -# CONFIG_SC_MSS_7180 is not set -# CONFIG_SC_VIDEOCC_7180 is not set -# CONFIG_SDM_CAMCC_845 is not set -# CONFIG_SDM_DISPCC_845 is not set -# CONFIG_SDM_GCC_660 is not set -# CONFIG_SDM_GCC_845 is not set -# CONFIG_SDM_GPUCC_845 is not set -# CONFIG_SDM_LPASSCC_845 is not set -# CONFIG_SDM_VIDEOCC_845 is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -# CONFIG_SM_GCC_8150 is not set -# CONFIG_SM_GCC_8250 is not set -# CONFIG_SM_GPUCC_8150 is not set -# CONFIG_SM_GPUCC_8250 is not set -# CONFIG_SM_VIDEOCC_8150 is not set -# CONFIG_SM_VIDEOCC_8250 is not set -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_QUP=y -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -CONFIG_SPMI_MSM_PMIC_ARB=y -# CONFIG_SPMI_PMIC_CLKDIV is not set -CONFIG_SRCU=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -# CONFIG_STMMAC_SELFTESTS is not set -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts deleted file mode 100644 index c1c21856ca..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts +++ /dev/null @@ -1,479 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8062.dtsi" -#include - -/delete-node/ &nand_pins; - -/ { - model = "NEC Platforms Aterm WG2600HP3"; - compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064"; - - memory { - device_type = "memory"; - reg = <0x42000000 0x1e000000>; - }; - - aliases { - label-mac-device = &gmac2; - - led-boot = &led_power_green; - led-failsafe = &led_power_red; - led-running = &led_power_green; - led-upgrade = &led_power_red; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&buttons_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - mode0 { - label = "mode0"; - gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - mode1 { - label = "mode1"; - gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&leds_pins>; - pinctrl-names = "default"; - - led_power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; - }; - - led_power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>; - }; - - active_green { - label = "green:active"; - gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>; - }; - - active_red { - label = "red:active"; - gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy1tpt"; - }; - - wlan2g_red { - label = "red:wlan2g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tpt"; - }; - - wlan5g_red { - label = "red:wlan5g"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; - }; - - tv_green { - label = "green:tv"; - gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>; - }; - - tv_red { - label = "red:tv"; - gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>; - }; - - converter_green { - label = "green:converter"; - gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>; - }; - - converter_red { - label = "red:converter"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - pinctrl-0 = <&akro_pins>; - pinctrl-names = "default"; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - buttons_pins: buttons_pins { - mux { - pins = "gpio22", "gpio24", "gpio40", - "gpio41"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - leds_pins: leds_pins { - mux { - pins = "gpio14", "gpio15", "gpio35", - "gpio36", "gpio38", "gpio42", - "gpio43", "gpio46", "gpio55", - "gpio56", "gpio57", "gpio58"; - function = "gpio"; - bias-pull-down; - }; - - akro2 { - pins = "gpio15", "gpio35", "gpio38", - "gpio42", "gpio43", "gpio46", - "gpio55", "gpio56", "gpio57", - "gpio58"; - drive-strength = <2>; - }; - - akro4 { - pins = "gpio14", "gpio36"; - drive-strength = <4>; - }; - }; - - /* - * Stock firmware has the following settings, so let's do the same. - * I don't sure why these are required. - */ - akro_pins: akro_pinmux { - akro { - pins = "gpio17", "gpio26", "gpio47"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - reset { - pins = "gpio45"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - gmac0_rgmii { - pins = "gpio25"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - }; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0000000 0x0020000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x0020000 0x0020000>; - read-only; - }; - - partition@40000 { - label = "SBL2"; - reg = <0x0040000 0x0040000>; - read-only; - }; - - partition@80000 { - label = "SBL3"; - reg = <0x0080000 0x0080000>; - read-only; - }; - - partition@100000 { - label = "DDRCONFIG"; - reg = <0x0100000 0x0010000>; - read-only; - }; - - partition@110000 { - label = "SSD"; - reg = <0x0110000 0x0010000>; - read-only; - }; - - partition@120000 { - label = "TZ"; - reg = <0x0120000 0x0080000>; - read-only; - }; - - partition@1a0000 { - label = "RPM"; - reg = <0x01a0000 0x0080000>; - read-only; - }; - - partition@220000 { - label = "APPSBL"; - reg = <0x0220000 0x0080000>; - read-only; - }; - - partition@2a0000 { - label = "APPSBLENV"; - reg = <0x02a0000 0x0010000>; - read-only; - }; - - factory: partition@2b0000 { - label = "PRODUCTDATA"; - reg = <0x02b0000 0x0030000>; - read-only; - }; - - partition@2e0000 { - label = "ART"; - reg = <0x02e0000 0x0040000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@320000 { - label = "TP"; - reg = <0x0320000 0x0040000>; - read-only; - }; - - partition@360000 { - label = "TINY"; - reg = <0x0360000 0x0500000>; - read-only; - }; - - partition@860000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x0860000 0x17a0000>; - }; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - reg = <0x00010000 0 0 0 0>; - - qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; - - nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - force_gen1 = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - reg = <0x00010000 0 0 0 0>; - - ieee80211-freq-limit = <2400000 2483000>; - qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; - - nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x04 0x80080080 /* PAD0_MODE */ - 0x0c 0x06000000 /* PAD6_MODE */ - 0x10 0x002613a0 /* PWS_REG */ - 0x50 0xcc36cc36 /* LED_CTRL0 */ - 0x54 0xca36ca36 /* LED_CTRL1 */ - 0x58 0xc936c936 /* LED_CTRL2 */ - 0x5c 0x03ffff00 /* LED_CTRL3 */ - 0x7c 0x0000004e /* PORT0_STATUS */ - 0x94 0x0000004e /* PORT6_STATUS */ - 0xe0 0xc74164de /* SGMII_CTRL */ - 0xe4 0x0006a545 /* MAC_PWR_SEL */ - >; - }; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - mdiobus = <&mdio0>; - nvmem-cells = <&macaddr_factory_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - mdiobus = <&mdio0>; - nvmem-cells = <&macaddr_factory_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&factory { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_factory_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_factory_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_PRODUCTDATA_c: macaddr@c { - reg = <0xc 0x6>; - }; - - macaddr_PRODUCTDATA_12: macaddr@12 { - reg = <0x12 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8062.dtsi b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8062.dtsi deleted file mode 100644 index 29226ca275..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8062.dtsi +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "qcom-ipq8064.dtsi" - -/ { - model = "Qualcomm IPQ8062"; - compatible = "qcom,ipq8062", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&gsbi4 { - qcom,mode = ; - status = "okay"; - - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ -}; - -&opp_table0 { - /delete-node/opp-1200000000; - /delete-node/opp-1400000000; - - /* - * Voltage thresholds are - */ - opp-384000000 { - opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; - opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>; - opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>; - opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>; - }; - - opp-600000000 { - opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; - opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>; - opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>; - opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>; - }; - - opp-800000000 { - opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; - opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>; - opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>; - }; - - opp-1000000000 { - opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; - opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; - opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>; - }; -}; - -&pcie0 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie1 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie2 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&smb208_s2a { - regulator-max-microvolt = <1150000>; -}; - -&smb208_s2b { - regulator-max-microvolt = <1150000>; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi deleted file mode 100644 index 115c6d43d2..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi +++ /dev/null @@ -1,375 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - label-mac-device = &gmac2; - }; -}; - -&qcom_pinmux { - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - usb0_pwr_en_pin: usb0_pwr_en_pin { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - }; - - usb1_pwr_en_pin: usb1_pwr_en_pin { - mux { - pins = "gpio23"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - output-high; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - partition@40000 { - label = "SBL2"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "SBL3"; - reg = <0x60000 0x30000>; - read-only; - }; - - partition@90000 { - label = "DDRCONFIG"; - reg = <0x90000 0x10000>; - read-only; - }; - - partition@a0000 { - label = "SSD"; - reg = <0xa0000 0x10000>; - read-only; - }; - - partition@b0000 { - label = "TZ"; - reg = <0xb0000 0x30000>; - read-only; - }; - - partition@e0000 { - label = "RPM"; - reg = <0xe0000 0x20000>; - read-only; - }; - - partition@100000 { - label = "fs-uboot"; - reg = <0x100000 0x70000>; - read-only; - }; - - partition@170000 { - label = "uboot-env"; - reg = <0x170000 0x40000>; - read-only; - }; - - partition@1b0000 { - label = "radio"; - reg = <0x1b0000 0x40000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_radio_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_radio_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@1f0000 { - label = "os-image"; - reg = <0x1f0000 0x400000>; - }; - - partition@5f0000 { - label = "rootfs"; - reg = <0x5f0000 0x1900000>; - }; - - defaultmac: partition@1ef0000 { - label = "default-mac"; - reg = <0x1ef0000 0x00200>; - read-only; - }; - - partition@1ef0200 { - label = "pin"; - reg = <0x1ef0200 0x00200>; - read-only; - }; - - partition@1ef0400 { - label = "product-info"; - reg = <0x1ef0400 0x0fc00>; - read-only; - }; - - partition@1f00000 { - label = "partition-table"; - reg = <0x1f00000 0x10000>; - read-only; - }; - - partition@1f10000 { - label = "soft-version"; - reg = <0x1f10000 0x10000>; - read-only; - }; - - partition@1f20000 { - label = "support-list"; - reg = <0x1f20000 0x10000>; - read-only; - }; - - partition@1f30000 { - label = "profile"; - reg = <0x1f30000 0x10000>; - read-only; - }; - - partition@1f40000 { - label = "default-config"; - reg = <0x1f40000 0x10000>; - read-only; - }; - - partition@1f50000 { - label = "user-config"; - reg = <0x1f50000 0x40000>; - read-only; - }; - - partition@1f90000 { - label = "qos-db"; - reg = <0x1f90000 0x40000>; - read-only; - }; - - partition@1fd0000 { - label = "usb-config"; - reg = <0x1fd0000 0x10000>; - read-only; - }; - - partition@1fe0000 { - label = "log"; - reg = <0x1fe0000 0x20000>; - read-only; - }; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pin>; - pinctrl-names = "default"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pin>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(-1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_defaultmac_8>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_defaultmac_8>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&defaultmac { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_defaultmac_8: macaddr@8 { - reg = <0x8 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts deleted file mode 100644 index 6cb21fc4f3..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-ad7200-c2600.dtsi" - -/ { - model = "TP-Link Talon AD7200"; - compatible = "tplink,ad7200", "qcom,ipq8064"; - - aliases { - led-boot = &led_status; - led-failsafe = &led_status; - led-running = &led_status; - led-upgrade = &led_status; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - led_enable { - label = "led-enable"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - lan { - label = "blue:lan"; - gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>; - }; - - usb1 { - label = "blue:usb1"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - wlan5g { - label = "blue:wlan5g"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - - usb3 { - label = "blue:usb3"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan2g { - label = "blue:wlan2g"; - gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; - }; - - wan_orange { - label = "orange:wan"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - wan_blue { - label = "blue:wan"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "blue:wps"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; - - wlan60g { - label = "blue:wlan60g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - led_status: status { - label = "blue:status"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio53", "gpio54", "gpio67"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26", - "gpio33", "gpio55", "gpio56", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&pcie2 { - status = "okay"; - max-link-speed = <1>; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ap148.dts deleted file mode 100644 index 70034a50e3..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ /dev/null @@ -1,121 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; - compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&flash { - partitions { - compatible = "qcom,smem-part"; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ap161.dts deleted file mode 100644 index c771a627ca..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ap161.dts +++ /dev/null @@ -1,159 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/AP161"; - compatible = "qcom,ipq8064-ap161", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - }; -}; - -&qcom_pinmux { - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", - "gpio60", "gpio61", "gpio62", - "gpio2", "gpio66"; - }; - }; -}; - -&flash { - partitions { - compatible = "qcom,smem-part"; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; -}; - -&pcie2 { - status = "okay"; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x20080 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,phy-rgmii-en; - qca,txclk-delay-en; - qca,rxclk-delay-en; - }; - - phy3: ethernet-phy@3 { - device_type = "ethernet-phy"; - reg = <3>; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-c2600.dts deleted file mode 100644 index cef1aba344..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-c2600.dts +++ /dev/null @@ -1,119 +0,0 @@ -#include "qcom-ipq8064-ad7200-c2600.dtsi" - -/ { - model = "TP-Link Archer C2600"; - compatible = "tplink,c2600", "qcom,ipq8064"; - - aliases { - led-boot = &power; - led-failsafe = &general; - led-running = &power; - led-upgrade = &general; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - ledswitch { - label = "ledswitch"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - lan { - label = "white:lan"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; - }; - - usb4 { - label = "white:usb_4"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb_2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - general: general { - label = "white:general"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio16", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33", - "gpio53", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-d7800.dts deleted file mode 100644 index 23487c9ca0..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-d7800.dts +++ /dev/null @@ -1,384 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "Netgear Nighthawk X4 D7800"; - compatible = "netgear,d7800", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(2)>; - }; - }; -}; - -&pcie2 { - status = "okay"; - reset-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie2_pins>; - pinctrl-names = "default"; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - artbak: art@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - kernel@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - - ubi@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - reserve@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-db149.dts deleted file mode 100644 index 8e8d942fbd..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-db149.dts +++ /dev/null @@ -1,163 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/DB149"; - compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi2_serial; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&qcom_pinmux { - rgmii0_pins: rgmii0_pins { - mux { - pins = "gpio2", "gpio66"; - drive-strength = <8>; - bias-disable; - }; - }; -}; - -&gsbi2 { - qcom,mode = ; - status = "okay"; - - gsbi2_serial: serial@12490000 { - status = "okay"; - }; -}; - -&gsbi4 { - status = "disabled"; -}; - -&gsbi4_serial { - status = "disabled"; -}; - -&flash { - m25p,fast-read; - - partition@0 { - label = "lowlevel_init"; - reg = <0x0 0x1b0000>; - }; - - partition@1 { - label = "u-boot"; - reg = <0x1b0000 0x80000>; - }; - - partition@2 { - label = "u-boot-env"; - reg = <0x230000 0x40000>; - }; - - partition@3 { - label = "caldata"; - reg = <0x270000 0x40000>; - }; - - partition@4 { - label = "firmware"; - reg = <0x2b0000 0x1d50000>; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy6: ethernet-phy@6 { - reg = <6>; - }; - - phy7: ethernet-phy@7 { - reg = <7>; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - phy-handle = <&phy4>; - - pinctrl-0 = <&rgmii0_pins>; - pinctrl-names = "default"; -}; - -&gmac1 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - phy-handle = <&phy6>; -}; - -&gmac3 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <3>; - phy-handle = <&phy7>; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts deleted file mode 100644 index 9d82d52d27..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-eax500.dtsi" - -/ { - model = "Linksys EA7500 V1 WiFi Router"; - compatible = "linksys,ea7500-v1", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0xe000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - }; - - chosen { - /* look for root deviceblock nbr in this bootarg */ - find-rootblock = "ubi.mtd="; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power: power { - label = "white:power"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio65", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&partitions { - partition@5f80000 { - label = "sysdiag"; - reg = <0x5f80000 0x100000>; - }; - - partition@6080000 { - label = "syscfg"; - reg = <0x6080000 0x1f80000>; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts deleted file mode 100644 index 1c6a4bdacd..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts +++ /dev/null @@ -1,128 +0,0 @@ -#include "qcom-ipq8064-eax500.dtsi" - -/ { - model = "Linksys EA8500 WiFi Router"; - compatible = "linksys,ea8500", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - wps { - label = "green:wps"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - led_power: power { - label = "white:power"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - wifi { - label = "green:wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio65", "gpio67", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio53", "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&partitions { - partition@5f80000 { - label = "syscfg"; - reg = <0x5f80000 0x2080000>; - }; -}; - -&mdio0 { - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <1>; - qcom,rgmii_delay = <0>; - qcom,emulation = <0>; -}; - -/* LAN */ -&gmac2 { - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,emulation = <0>; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi deleted file mode 100644 index e5282efaab..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi +++ /dev/null @@ -1,219 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - chosen { - bootargs = "console=ttyMSM0,115200n8"; - /* append to bootargs adding the root deviceblock nbr from bootloader */ - append-rootblock = "ubi.mtd="; - }; -}; - -&qcom_pinmux { - /* eax500 routers reuse the pcie2 reset pin for switch reset pin */ - switch_reset: switch_reset_pins { - mux { - pins = "gpio63"; - function = "gpio"; - drive-strength = <12>; - bias-pull-up; - }; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - max-link-speed = <1>; -}; - -&pcie1 { - status = "okay"; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot_pages_size = <0x0c80000>; - - partitions: partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - partition@40000 { - label = "MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - partition@180000 { - label = "SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - partition@2c0000 { - label = "SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - partition@540000 { - label = "DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - partition@660000 { - label = "SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - partition@780000 { - label = "TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - partition@a00000 { - label = "RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - art: partition@c80000 { - label = "art"; - reg = <0x0c80000 0x0140000>; - read-only; - }; - - partition@dc0000 { - label = "APPSBL"; - reg = <0x0dc0000 0x0100000>; - read-only; - }; - - partition@ec0000 { - label = "u_env"; - reg = <0x0ec0000 0x0040000>; - }; - - partition@f00000 { - label = "s_env"; - reg = <0x0f00000 0x0040000>; - }; - - partition@f40000 { - label = "devinfo"; - reg = <0x0f40000 0x0040000>; - }; - - partition@f80000 { - label = "kernel1"; - reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */ - }; - - partition@1380000 { - label = "rootfs1"; - reg = <0x1380000 0x2400000>; - }; - - partition@3780000 { - label = "kernel2"; - reg = <0x3780000 0x2800000>; - }; - - partition@3b80000 { - label = "rootfs2"; - reg = <0x3b80000 0x2400000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - /* Switch from documentation require at least 10ms for reset */ - reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>; - reset-post-delay-us = <12000>; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x00010 0x2613a0 /* PWS_REG */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-g10.dts deleted file mode 100644 index 735ccb2d53..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-g10.dts +++ /dev/null @@ -1,279 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-ipq8064-v2.0.dtsi" - -#include -#include - -/ { - compatible = "asrock,g10", "qcom,ipq8064"; - model = "ASRock G10"; - - aliases { - ethernet0 = &gmac1; - ethernet1 = &gmac0; - - led-boot = &led_status_blue; - led-failsafe = &led_status_amber; - led-running = &led_status_blue; - led-upgrade = &led_status_amber; - }; - - chosen { - bootargs-override = "console=ttyMSM0,115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - /* - * this is a bit misleading. Because there are about seven - * multicolor LEDs connected all wired together in parallel. - */ - - status_yellow { - label = "yellow:status"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - led_status_amber: status_amber { - label = "amber:status"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - led_status_blue: status_blue { - label = "blue:status"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - /* - * LED is declared in vendors boardfile but it's not - * working and the manual doesn't mention anything - * about the LED being white. - - status_white { - label = "white:status"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - */ - }; - - i2c-gpio { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "i2c-gpio"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */ - <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <5>; - i2c-gpio,scl-output-only; - - mcu@50 { - reg = <0x50>; - compatible = "sonix,sn8f25e21"; - }; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - ir-remote { - label = "ir-remote"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps5g { - label = "wps5g"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps2g { - label = "wps2g"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4_serial { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot_pages_size = <0x1200000>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi5g: wifi@1,0 { - reg = <0x00010000 0 0 0 0>; - compatible = "qcom,ath10k"; - qcom,ath10k-calibration-variant = "ASRock-G10"; - }; - }; -}; - -&pcie1 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi2g: wifi@1,0 { - reg = <0x00010000 0 0 0 0>; - compatible = "qcom,ath10k"; - qcom,ath10k-calibration-variant = "ASRock-G10"; - }; - }; -}; - -&qcom_pinmux { - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio15", "gpio16", "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; -}; - -&rpm { - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&tcsr { - qcom,usb-ctrl-select = ; -}; - -/delete-node/ &pcie2_pins; -/delete-node/ &pcie2; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-r7500.dts deleted file mode 100644 index 0970eaf0ec..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-r7500.dts +++ /dev/null @@ -1,314 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -#include -#include - -/ { - model = "Netgear Nighthawk X4 R7500"; - compatible = "netgear,r7500", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0xe000000>; - device_type = "memory"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; -}; - -&gsbi5 { - status = "disabled"; - - spi@1a280000 { - status = "disabled"; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - }; - - kernel@1340000 { - label = "kernel"; - reg = <0x1340000 0x0400000>; - }; - - ubi@1740000 { - label = "ubi"; - reg = <0x1740000 0x1600000>; - }; - - netgear@2d40000 { - label = "netgear"; - reg = <0x2d40000 0x0c00000>; - read-only; - }; - - reserve@3940000 { - label = "reserve"; - reg = <0x3940000 0x46c0000>; - read-only; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&tcsr { - qcom,usb-ctrl-select = ; - compatible = "qcom,tcsr"; -}; - -&adm_dma { - status = "okay"; -}; - -&art { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts deleted file mode 100644 index 30b56bb9d6..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts +++ /dev/null @@ -1,374 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "Netgear Nighthawk X4 R7500v2"; - compatible = "netgear,r7500v2", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb1 { - label = "amber:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb3 { - label = "amber:usb3"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - status { - label = "amber:status"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - internet { - label = "white:internet"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "white:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", - "gpio24","gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(2)>; - }; - }; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qcadata@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - artbak: art@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - kernel@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - - ubi@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - reserve@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts deleted file mode 100644 index b3e06db86d..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts +++ /dev/null @@ -1,317 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8064-v2.0.dtsi" - -#include -#include - -/ { - model = "Ubiquiti UniFi AC HD"; - compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064"; - - aliases { - label-mac-device = &gmac2; - led-boot = &led_dome_white; - led-failsafe = &led_dome_white; - led-running = &led_dome_blue; - led-upgrade = &led_dome_blue; - mdio-gpio0 = &mdio0; - ethernet0 = &gmac2; - ethernet1 = &gmac1; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_dome_blue: dome_blue { - label = "blue:dome"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - led_dome_white: dome_white { - label = "white:dome"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio9", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; -}; - -&CPU_SPC { - status = "disabled"; -}; - -&gsbi5 { - status = "okay"; - - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - cs-gpios = <&qcom_pinmux 20 0>; - - flash@0 { - compatible = "mx25u25635f", "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x20000 0x10000>; - read-only; - }; - - partition@30000 { - label = "SBL2"; - reg = <0x30000 0x20000>; - read-only; - }; - - partition@50000 { - label = "SBL3"; - reg = <0x50000 0x30000>; - read-only; - }; - - partition@80000 { - label = "DDRCONFIG"; - reg = <0x80000 0x10000>; - read-only; - }; - - partition@90000 { - label = "SSD"; - reg = <0x90000 0x10000>; - read-only; - }; - - partition@a0000 { - label = "TZ"; - reg = <0xa0000 0x30000>; - read-only; - }; - - partition@d0000 { - label = "RPM"; - reg = <0xd0000 0x20000>; - read-only; - }; - - partition@f0000 { - label = "APPSBL"; - reg = <0xf0000 0xc0000>; - read-only; - }; - - partition@1b0000 { - label = "APPSBLENV"; - reg = <0x1b0000 0x10000>; - read-only; - }; - - eeprom: partition@1c0000 { - label = "EEPROM"; - reg = <0x1c0000 0x10000>; - read-only; - }; - - partition@1d0000 { - label = "bootselect"; - reg = <0x1d0000 0x10000>; - }; - - partition@1e0000 { - compatible = "denx,fit"; - label = "firmware"; - reg = <0x1e0000 0xe70000>; - }; - - partition@1050000 { - label = "kernel1"; - reg = <0x1050000 0xe70000>; - read-only; - }; - - partition@1ec0000 { - label = "debug"; - reg = <0x1ec0000 0x100000>; - read-only; - }; - - partition@1fc0000 { - label = "cfg"; - reg = <0x1fc0000 0x40000>; - read-only; - }; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - nand-ecc-strength = <4>; - nand-bus-width = <8>; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy4: ethernet-phy@4 { - reg = <4>; - }; - - phy5: ethernet-phy@5 { - reg = <5>; - }; -}; - -&gmac1 { - status = "okay"; - - mdiobus = <&mdio0>; - phy-handle = <&phy5>; - phy-mode = "sgmii"; - qcom,id = <1>; - - nvmem-cells = <&macaddr_eeprom_6>; - nvmem-cell-names = "mac-address"; -}; - -&gmac2 { - status = "okay"; - - mdiobus = <&mdio0>; - phy-handle = <&phy4>; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_eeprom_0>; - nvmem-cell-names = "mac-address"; -}; - -&pcie0 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; -}; - -&tcsr { - status = "okay"; -}; - -&hs_phy_0 { - status = "okay"; -}; - -&ss_phy_0 { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&hs_phy_1 { - status = "okay"; -}; - -&ss_phy_1 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&eeprom { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_eeprom_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_eeprom_6: macaddr@6 { - reg = <0x6 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi deleted file mode 100644 index b9ee86a891..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -#include "qcom-ipq8064.dtsi" - -/ { - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&gsbi4 { - qcom,mode = ; - status = "okay"; - - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ -}; - -&CPU_SPC { - status = "okay"; -}; - -&pcie0 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie1 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie2 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&sata { - ports-implemented = <0x1>; -}; - -&ss_phy_0 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; - -&ss_phy_1 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts deleted file mode 100644 index 27d9fc84b3..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts +++ /dev/null @@ -1,408 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "TP-Link Archer VR2600v"; - compatible = "tplink,vr2600v", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power; - led-failsafe = &general; - led-running = &power; - led-upgrade = &general; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - dect { - label = "dect"; - gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - ledswitch { - label = "ledswitch"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - dsl { - label = "white:dsl"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb { - label = "white:usb"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - lan { - label = "white:lan"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wlan2g { - label = "white:wlan2g"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan5g { - label = "white:wlan5g"; - gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - phone { - label = "white:phone"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - wan { - label = "white:wan"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - general: general { - label = "white:general"; - gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", - "gpio26", "gpio53", "gpio56", "gpio66"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - partition@40000 { - label = "SBL2"; - reg = <0x40000 0x40000>; - read-only; - }; - - partition@80000 { - label = "SBL3"; - reg = <0x80000 0x80000>; - read-only; - }; - - partition@100000 { - label = "DDRCONFIG"; - reg = <0x100000 0x10000>; - read-only; - }; - - partition@110000 { - label = "SSD"; - reg = <0x110000 0x10000>; - read-only; - }; - - partition@120000 { - label = "TZ"; - reg = <0x120000 0x80000>; - read-only; - }; - - partition@1a0000 { - label = "RPM"; - reg = <0x1a0000 0x80000>; - read-only; - }; - - partition@220000 { - label = "APPSBL"; - reg = <0x220000 0x80000>; - read-only; - }; - - partition@2a0000 { - label = "APPSBLENV"; - reg = <0x2a0000 0x40000>; - read-only; - }; - - partition@2e0000 { - label = "OLDART"; - reg = <0x2e0000 0x40000>; - read-only; - }; - - partition@320000 { - label = "firmware"; - reg = <0x320000 0xc60000>; - compatible = "openwrt,uimage"; - openwrt,offset = <512>; /* account for pad-extra 512 */ - }; - - /* hole 0xf80000 - 0xfaf100 */ - - partition@faf100 { - label = "default-mac"; - reg = <0xfaf100 0x00200>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_defaultmac_0: macaddr@0 { - reg = <0x0 0x6>; - }; - }; - - partition@fc0000 { - label = "ART"; - reg = <0xfc0000 0x40000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(-1)>; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_defaultmac_0>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_defaultmac_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts deleted file mode 100644 index 998dad55c5..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts +++ /dev/null @@ -1,447 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "NEC Aterm WG2600HP"; - compatible = "nec,wg2600hp", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - led-upgrade = &power_green; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - bridge { - label = "bridge"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - converter { - label = "converter"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - converter_green { - label = "green:converter"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; - }; - - power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - active_green { - label = "green:active"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - active_red { - label = "red:active"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; - }; - - converter_red { - label = "red:converter"; - gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_red { - label = "red:wlan2g"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; - }; - - wlan5g_red { - label = "red:wlan5g"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; - }; - - tv_green { - label = "green:tv"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - tv_red { - label = "red:tv"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&CPU_SPC { - status = "disabled"; -}; - -&adm_dma { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x06000000 /* PAD0_MODE */ - 0x0000c 0x00080080 /* PAD6_MODE */ - 0x000e4 0x0006a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x0000004e /* PORT0_STATUS */ - 0x00094 0x0000004e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_PRODUCTDATA_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_PRODUCTDATA_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi5 { - status = "okay"; - - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x20000>; - read-only; - }; - - MIBIB@20000 { - label = "MIBIB"; - reg = <0x20000 0x20000>; - read-only; - }; - - SBL2@40000 { - label = "SBL2"; - reg = <0x40000 0x40000>; - read-only; - }; - - SBL3@80000 { - label = "SBL3"; - reg = <0x80000 0x80000>; - read-only; - }; - - DDRCONFIG@100000 { - label = "DDRCONFIG"; - reg = <0x100000 0x10000>; - read-only; - }; - - SSD@110000 { - label = "SSD"; - reg = <0x110000 0x10000>; - read-only; - }; - - TZ@120000 { - label = "TZ"; - reg = <0x120000 0x80000>; - read-only; - }; - - RPM@1a0000 { - label = "RPM"; - reg = <0x1a0000 0x80000>; - read-only; - }; - - APPSBL@220000 { - label = "APPSBL"; - reg = <0x220000 0x80000>; - read-only; - }; - - APPSBLENV@2a0000 { - label = "APPSBLENV"; - reg = <0x2a0000 0x10000>; - }; - - PRODUCTDATA: PRODUCTDATA@2b0000 { - label = "PRODUCTDATA"; - reg = <0x2b0000 0x30000>; - read-only; - }; - - ART@2e0000 { - label = "ART"; - reg = <0x2e0000 0x40000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - TP@320000 { - label = "TP"; - reg = <0x320000 0x40000>; - read-only; - }; - - TINY@360000 { - label = "TINY"; - reg = <0x360000 0x500000>; - read-only; - }; - - firmware@860000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x860000 0x17a0000>; - }; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio16", "gpio54", "gpio24", "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14", - "gpio15", "gpio55", "gpio56", "gpio57", "gpio58", - "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - usb_pwr_en_pins: usb_pwr_en_pins { - mux { - pins = "gpio22"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-high; - }; - }; -}; - -&PRODUCTDATA { - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_PRODUCTDATA_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_PRODUCTDATA_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_PRODUCTDATA_c: macaddr@c { - reg = <0xc 0x6>; - }; - - macaddr_PRODUCTDATA_12: macaddr@12 { - reg = <0x12 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts deleted file mode 100644 index d7f3a7f881..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts +++ /dev/null @@ -1,465 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (C) 2017 Christian Mehlis - * Copyright (C) 2018 Mathias Kresin - * All rights reserved. - */ - -#include "qcom-ipq8064-v1.0.dtsi" - -#include -#include - -/ { - compatible = "compex,wpq864", "qcom,ipq8064"; - model = "Compex WPQ864"; - - aliases { - mdio-gpio0 = &mdio0; - ethernet0 = &gmac1; - ethernet1 = &gmac0; - - led-boot = &led_pass; - led-failsafe = &led_fail; - led-running = &led_pass; - led-upgrade = &led_pass; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - rss4 { - label = "green:rss4"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - rss3 { - label = "green:rss3"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - rss2 { - label = "orange:rss2"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - - rss1 { - label = "red:rss1"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - led_pass: pass { - label = "green:pass"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - - led_fail: fail { - label = "green:fail"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - usb { - label = "green:usb"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb-pcie { - label = "green:usb-pcie"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - beeper { - compatible = "gpio-beeper"; - - pinctrl-0 = <&beeper_pins>; - pinctrl-names = "default"; - - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; - }; -}; - -&rpm { - pinctrl-0 = <&rpm_pins>; - pinctrl-names = "default"; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - mt29f2g08abbeah4@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - MIBIB@40000 { - label = "MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - SBL2@180000 { - label = "SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - SBL3@2c0000 { - label = "SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - DDRCONFIG@540000 { - label = "DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - SSD@660000 { - label = "SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - TZ@780000 { - label = "TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - RPM@a00000 { - label = "RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - APPSBL@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - APPSBLENV@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - - ART@1200000 { - label = "ART"; - reg = <0x1200000 0x0140000>; - }; - - ubi@1340000 { - label = "ubi"; - reg = <0x1340000 0x4000000>; - }; - - BOOTCONFIG@5340000 { - label = "BOOTCONFIG"; - reg = <0x5340000 0x0060000>; - }; - - SBL2-1@53a0000- { - label = "SBL2_1"; - reg = <0x53a0000 0x0140000>; - read-only; - }; - - SBL3-1@54e0000 { - label = "SBL3_1"; - reg = <0x54e0000 0x0280000>; - read-only; - }; - - DDRCONFIG-1@5760000 { - label = "DDRCONFIG_1"; - reg = <0x5760000 0x0120000>; - read-only; - }; - - SSD-1@5880000 { - label = "SSD_1"; - reg = <0x5880000 0x0120000>; - read-only; - }; - - TZ-1@59a0000 { - label = "TZ_1"; - reg = <0x59a0000 0x0280000>; - read-only; - }; - - RPM-1@5c20000 { - label = "RPM_1"; - reg = <0x5c20000 0x0280000>; - read-only; - }; - - BOOTCONFIG1@5ea0000 { - label = "BOOTCONFIG1"; - reg = <0x5ea0000 0x0060000>; - }; - - APPSBL-1@5f00000 { - label = "APPSBL_1"; - reg = <0x5f00000 0x0500000>; - read-only; - }; - - ubi-1@6400000 { - label = "ubi_1"; - reg = <0x6400000 0x4000000>; - }; - - unused@a400000 { - label = "unused"; - reg = <0xa400000 0x5c00000>; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4_serial { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&flash { - compatible = "jedec,spi-nor"; -}; - -&sata_phy { - status = "disabled"; -}; - -&sata { - status = "disabled"; -}; - -&ss_phy_0 { /* USB3 port 0 SS phy */ - status = "okay"; - - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <160>; -}; - -&ss_phy_1 { /* USB3 port 1 SS phy */ - status = "okay"; - - rx_eq = <2>; - tx_deamp_3_5db = <32>; - mpll = <160>; -}; - -&pcie0 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; -}; - -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; -}; - -&qcom_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - pcie0_pcie2_perst { - pins = "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio22", - "gpio23", "gpio24", "gpio25", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - beeper_pins: beeper_pins { - mux { - pins = "gpio55"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - rpm_pins: rpm_pins { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <10>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - drive-strength = <10>; - bias-pull-down; - }; - - clk { - pins = "gpio21"; - function = "gsbi5"; - drive-strength = <12>; - bias-pull-down; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - }; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&tcsr { - qcom,usb-ctrl-select = ; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts deleted file mode 100644 index 04a2261929..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts +++ /dev/null @@ -1,526 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "qcom-ipq8064-v2.0.dtsi" - -#include - -/ { - model = "Buffalo WXR-2533DHP"; - compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064"; - - memory@42000000 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &power; - led-failsafe = &diag; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - /* use "ubi_rootfs" volume in "ubi" partition as rootfs */ - bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - usb { - label = "green:usb"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "usbport"; - trigger-sources = <&hub_port0 &hub_port1>; - }; - - guestport { - label = "green:guestport"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - diag: diag { - label = "orange:diag"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - internet_orange { - label = "orange:internet"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - internet_white { - label = "white:internet"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wireless_orange { - label = "orange:wireless"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wireless_white { - label = "white:wireless"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - router_orange { - label = "orange:router"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; - }; - - router_white { - label = "white:router"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - power { - label = "power"; - gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - eject { - label = "eject"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - guest { - label = "guest"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - ap { - label = "ap"; - gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - router { - label = "router"; - gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - auto { - label = "auto"; - gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - }; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - cs@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ubi@0 { - label = "ubi"; - reg = <0x0000000 0x4000000>; - }; - - rootfs_1@4000000 { - label = "rootfs_1"; - reg = <0x4000000 0x4000000>; - }; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x07600000 /* PAD0_MODE */ - 0x00008 0x01000000 /* PAD5_MODE */ - 0x0000c 0x00000080 /* PAD6_MODE */ - 0x00050 0xcc35cc35 /* LED_CTRL0 */ - 0x00054 0xca35ca35 /* LED_CTRL1 */ - 0x00058 0xc935c935 /* LED_CTRL2 */ - 0x0005c 0x03ffff00 /* LED_CTRL3 */ - 0x000e4 0x0006a545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x0000007e /* PORT0_STATUS */ - 0x00094 0x0000007e /* PORT6_STATUS */ - >; - }; - - ethernet-phy@4 { - reg = <4>; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_ART_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - - nvmem-cells = <&macaddr_ART_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gsbi4_serial { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; -}; - -&gsbi5 { - status = "okay"; - qcom,mode = ; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - SBL1@0 { - label = "SBL1"; - reg = <0x0 0x10000>; - read-only; - }; - - MIBIB@10000 { - label = "MIBIB"; - reg = <0x10000 0x20000>; - read-only; - }; - - SBL2@30000 { - label = "SBL2"; - reg = <0x30000 0x30000>; - read-only; - }; - - SBL3@60000 { - label = "SBL3"; - reg = <0x60000 0x30000>; - read-only; - }; - - DDRCONFIG@90000 { - label = "DDRCONFIG"; - reg = <0x90000 0x10000>; - read-only; - }; - - SSD@a0000 { - label = "SSD"; - reg = <0xa0000 0x10000>; - read-only; - }; - - TZ@b0000 { - label = "TZ"; - reg = <0xb0000 0x30000>; - read-only; - }; - - RPM@e0000 { - label = "RPM"; - reg = <0xe0000 0x20000>; - read-only; - }; - - APPSBL@100000 { - label = "APPSBL"; - reg = <0x100000 0x70000>; - read-only; - }; - - APPSBLENV@170000 { - label = "APPSBLENV"; - reg = <0x170000 0x10000>; - read-only; - }; - - ART@180000 { - label = "ART"; - reg = <0x180000 0x40000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_ART_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_ART_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - macaddr_ART_18: macaddr@18 { - reg = <0x18 0x6>; - }; - - macaddr_ART_1e: macaddr@1e { - reg = <0x1e 0x6>; - }; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - BOOTCONFIG@1c0000 { - label = "BOOTCONFIG"; - reg = <0x1c0000 0x10000>; - read-only; - }; - - APPSBL_1@1d0000 { - label = "APPSBL_1"; - reg = <0x1d0000 0x70000>; - read-only; - }; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&usb3_1 { - status = "okay"; -}; - -&dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; - - hub_port0: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; -}; - -&dwc3_1 { - #address-cells = <1>; - #size-cells = <0>; - - hub_port1: port@1 { - reg = <1>; - #trigger-source-cells = <0>; - }; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57", - "gpio58", "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22", - "gpio23", "gpio24", "gpio25", "gpio26", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart0_pins: uart0_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gsbi4"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs{ - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - usb_pwr_en_pins: usb_pwr_en_pins { - mux{ - pins = "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-high; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts deleted file mode 100644 index 969ca724e3..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts +++ /dev/null @@ -1,316 +0,0 @@ -#include "qcom-ipq8065.dtsi" - -#include - -/ { - model = "ZyXEL NBG6817"; - compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - mdio-gpio0 = &mdio0; - sdcc1 = &sdcc1; - - led-boot = &power; - led-failsafe = &power; - led-running = &power; - led-upgrade = &power; - }; - - chosen { - bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1"; - append-rootblock = "root=/dev/mmcblk0p"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - internet { - label = "white:internet"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - power: power { - label = "white:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - wifi2g { - label = "amber:wifi2g"; - gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; - }; - - /* wifi2g amber from the manual is missing */ - - wifi5g { - label = "amber:wifi5g"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - - /* wifi5g amber from the manual is missing */ - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio53", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio9", "gpio26", "gpio33", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - mdio0_pins: mdio0_pins { - clk { - pins = "gpio1"; - input-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ; - input-disable; - }; - }; - - spi_pins: spi_pins { - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio16", "gpio17"; - function = "gpio"; - drive-strength = <12>; - }; - - pwr { - pins = "gpio17"; - bias-pull-down; - output-high; - }; - - ovc { - pins = "gpio16"; - bias-pull-up; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <12>; - }; - - pwr { - pins = "gpio14"; - bias-pull-down; - output-high; - }; - - ovc { - pins = "gpio15"; - bias-pull-up; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <51200000>; - reg = <0>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; - }; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ - 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ - 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ - 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ - 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ - 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ - 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ - 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ - 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ - 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ - 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ - 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ - 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ - 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,ar8327-initvals = < - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x0000c 0x80 /* PAD6_MODE */ - >; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <1>; - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <0>; - qcom,rgmii_delay = <1>; - qcom,phy_mii_type = <0>; - qcom,emulation = <0>; - qcom,irq = <255>; - mdiobus = <&mdio0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <2>; - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,phy_mii_type = <1>; - qcom,emulation = <0>; - qcom,irq = <258>; - mdiobus = <&mdio0>; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&amba { - sdcc1: sdcc@12400000 { - status = "okay"; - }; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi deleted file mode 100644 index c899fa7c75..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi +++ /dev/null @@ -1,453 +0,0 @@ -#include "qcom-ipq8065.dtsi" - -#include - -/ { - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - reserved-memory { - rsvd@5fe00000 { - reg = <0x5fe00000 0x200000>; - reusable; - }; - - ramoops@42100000 { - compatible = "ramoops"; - reg = <0x42100000 0x40000>; - record-size = <0x4000>; - console-size = <0x4000>; - ftrace-size = <0x4000>; - pmsg-size = <0x4000>; - }; - }; - - aliases { - label-mac-device = &gmac2; - - led-boot = &power_white; - led-failsafe = &power_amber; - led-running = &power_white; - led-upgrade = &power_amber; - - mdio-gpio0 = &mdio0; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - wifi { - label = "wifi"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - power_white: power_white { - label = "white:power"; - gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - power_amber: power_amber { - label = "amber:power"; - gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; - }; - - wan_white { - label = "white:wan"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - wan_amber { - label = "amber:wan"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - wifi { - label = "white:wifi"; - gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; - }; - - wps { - label = "white:wps"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54", "gpio65"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", - "gpio22", "gpio23", "gpio24", - "gpio26", "gpio53", "gpio64"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - mdio0_pins: mdio0_pins { - clk { - pins = "gpio1"; - input-disable; - }; - }; - - rgmii2_pins: rgmii2_pins { - tx { - pins = "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32"; - input-disable; - }; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - bias-pull-down; - }; - - data { - pins = "gpio18", "gpio19"; - drive-strength = <10>; - }; - - cs { - pins = "gpio20"; - drive-strength = <10>; - bias-pull-up; - }; - - clk { - pins = "gpio21"; - drive-strength = <12>; - }; - }; - - spi6_pins: spi6_pins { - mux { - pins = "gpio55", "gpio56", "gpio58"; - function = "gsbi6"; - bias-pull-down; - }; - - mosi { - pins = "gpio55"; - drive-strength = <12>; - }; - - miso { - pins = "gpio56"; - drive-strength = <14>; - }; - - cs { - pins = "gpio57"; - drive-strength = <12>; - bias-pull-up; - }; - - clk { - pins = "gpio58"; - drive-strength = <12>; - }; - - reset { - pins = "gpio33"; - drive-strength = <10>; - bias-pull-down; - output-high; - }; - }; - - usb0_pwr_en_pins: usb0_pwr_en_pins { - mux { - pins = "gpio15"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; - - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio16", "gpio68"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-high; - }; - }; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot_pages_size = <0x1180000>; - - partitions: partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "qcadata"; - reg = <0x0000000 0x0c80000>; - read-only; - }; - - partition@c80000 { - label = "APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - partition@1180000 { - label = "APPSBLENV"; - reg = <0x1180000 0x0080000>; - read-only; - }; - - art: partition@1200000 { - label = "art"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_art_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_art_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@1340000 { - label = "artbak"; - reg = <0x1340000 0x0140000>; - read-only; - }; - - partition@1480000 { - label = "kernel"; - reg = <0x1480000 0x0400000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ - 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ - 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ - 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ - 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ - 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ - 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ - 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ - 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ - 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ - 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ - 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ - 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ - 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ - >; - qca,ar8327-vlans = < - 0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */ - 0x2 0x21 /* VLAN2 Ports 0/5 */ - >; - }; - - phy4: ethernet-phy@4 { - reg = <4>; - qca,ar8327-initvals = < - 0x000e4 0x6a545 /* MAC_POWER_SEL */ - 0x0000c 0x80 /* PAD6_MODE */ - >; - }; -}; - -&gmac1 { - status = "okay"; - - phy-mode = "rgmii"; - qcom,id = <1>; - qcom,phy_mdio_addr = <4>; - qcom,poll_required = <0>; - qcom,rgmii_delay = <1>; - qcom,phy_mii_type = <0>; - qcom,emulation = <0>; - qcom,irq = <255>; - mdiobus = <&mdio0>; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - nvmem-cells = <&macaddr_art_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac2 { - status = "okay"; - - phy-mode = "sgmii"; - qcom,id = <2>; - qcom,phy_mdio_addr = <0>; /* none */ - qcom,poll_required = <0>; /* no polling */ - qcom,rgmii_delay = <0>; - qcom,phy_mii_type = <1>; - qcom,emulation = <0>; - qcom,irq = <258>; - mdiobus = <&mdio0>; - - nvmem-cells = <&macaddr_art_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&sata_phy { - status = "okay"; -}; - -&sata { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; - - pinctrl-0 = <&usb0_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&usb3_1 { - status = "okay"; - - pinctrl-0 = <&usb1_pwr_en_pins>; - pinctrl-names = "default"; -}; - -&pcie0 { - status = "okay"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - }; - }; -}; - -&pcie1 { - status = "okay"; - - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-r7800.dts deleted file mode 100644 index bf7c963944..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-r7800.dts +++ /dev/null @@ -1,48 +0,0 @@ -#include "qcom-ipq8065-nighthawk.dtsi" - -/ { - model = "Netgear Nighthawk X4S R7800"; - compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064"; -}; - -&leds { - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - esata { - label = "white:esata"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&partitions { - partition@1880000 { - label = "ubi"; - reg = <0x1880000 0x6080000>; - }; - - partition@7900000 { - label = "reserve"; - reg = <0x7900000 0x0700000>; - read-only; - }; -}; - -&wifi0 { - nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(1)>; -}; - -&wifi1 { - nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; - mac-address-increment = <(2)>; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts deleted file mode 100644 index 96163331f3..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts +++ /dev/null @@ -1,403 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "qcom-ipq8065.dtsi" -#include - -/ { - model = "Askey RT4230W REV6"; - compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x3e000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &ledctrl3; - led-failsafe = &ledctrl1; - led-running = &ledctrl2; - led-upgrade = &ledctrl3; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - ledctrl1: ledctrl1 { - label = "ledctrl1"; - gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; - }; - - ledctrl2: ledctrl2 { - label = "ledctrl2"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - ledctrl3: ledctrl3 { - label = "ledctrl3"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio54", "gpio68"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio22", "gpio23", "gpio24"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - rgmii2_pins: rgmii2_pins { - mux { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62"; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; - - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; - input-disable; - }; - }; - - spi_pins: spi_pins { - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "everspin,mr25h256"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - - partition@40000 { - label = "0:MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - - partition@180000 { - label = "0:SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - - partition@2c0000 { - label = "0:SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - - partition@540000 { - label = "0:DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - - partition@660000 { - label = "0:SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - - partition@780000 { - label = "0:TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - - partition@a00000 { - label = "0:RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - - partition@c80000 { - label = "0:APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - - partition@1180000 { - label = "0:APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - - partition@1200000 { - label = "0:ART"; - reg = <0x1200000 0x0140000>; - read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_ART_0: macaddr@0 { - reg = <0x0 0x6>; - }; - - macaddr_ART_6: macaddr@6 { - reg = <0x6 0x6>; - }; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - - partition@1340000 { - label = "0:BOOTCONFIG"; - reg = <0x1340000 0x0060000>; - read-only; - }; - - partition@13a0000 { - label = "0:SBL2_1"; - reg = <0x13a0000 0x0140000>; - read-only; - }; - - partition@14e0000 { - label = "0:SBL3_1"; - reg = <0x14e0000 0x0280000>; - read-only; - }; - - partition@1760000 { - label = "0:DDRCONFIG_1"; - reg = <0x1760000 0x0120000>; - read-only; - }; - - partition@1880000 { - label = "0:SSD_1"; - reg = <0x1880000 0x0120000>; - read-only; - }; - - partition@19a0000 { - label = "0:TZ_1"; - reg = <0x19a0000 0x0280000>; - read-only; - }; - - partition@1c20000 { - label = "0:RPM_1"; - reg = <0x1c20000 0x0280000>; - read-only; - }; - - partition@1ea0000 { - label = "0:BOOTCONFIG1"; - reg = <0x1ea0000 0x0060000>; - read-only; - }; - - partition@1f00000 { - label = "0:APPSBL_1"; - reg = <0x1f00000 0x0500000>; - read-only; - }; - - partition@2400000 { - label = "ubi"; - reg = <0x2400000 0x1a000000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - 0x00050 0xcf02cf02 /* LED_CTRL_0 */ - 0x00054 0xc832c832 /* LED_CTRL_1 */ - >; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - nvmem-cells = <&macaddr_ART_0>; - nvmem-cell-names = "mac-address"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - nvmem-cells = <&macaddr_ART_6>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_1000>; - nvmem-cell-names = "pre-calibration"; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_5000>; - nvmem-cell-names = "pre-calibration"; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts deleted file mode 100644 index 871cc09502..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts +++ /dev/null @@ -1,425 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "qcom-ipq8065.dtsi" -#include - -/ { - model = "Arris TR4400 v2"; - compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064"; - - memory@0 { - reg = <0x42000000 0x1e000000>; - device_type = "memory"; - }; - - aliases { - led-boot = &led_status_blue; - led-failsafe = &led_status_red; - led-running = &led_status_blue; - led-upgrade = &led_status_red; - }; - - chosen { - bootargs = "rootfstype=squashfs noinitrd"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - - wps { - label = "wps"; - gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_status_red: status_red { - label = "red:status"; - gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; - }; - - led_status_blue: status_blue { - label = "blue:status"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&qcom_pinmux { - button_pins: button_pins { - mux { - pins = "gpio6", "gpio54"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio7", "gpio8"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - rgmii2_pins: rgmii2_pins { - tx { - pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; - input-disable; - }; - }; - - spi_pins: spi_pins { - cs { - pins = "gpio20"; - drive-strength = <12>; - }; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi@1a280000 { - status = "okay"; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - flash@0 { - compatible = "everspin,mr25h256"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - reg = <0>; - compatible = "qcom,nandcs"; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "0:SBL1"; - reg = <0x0000000 0x0040000>; - read-only; - }; - partition@40000 { - label = "0:MIBIB"; - reg = <0x0040000 0x0140000>; - read-only; - }; - partition@180000 { - label = "0:SBL2"; - reg = <0x0180000 0x0140000>; - read-only; - }; - partition@2c0000 { - label = "0:SBL3"; - reg = <0x02c0000 0x0280000>; - read-only; - }; - partition@540000 { - label = "0:DDRCONFIG"; - reg = <0x0540000 0x0120000>; - read-only; - }; - partition@660000 { - label = "0:SSD"; - reg = <0x0660000 0x0120000>; - read-only; - }; - partition@780000 { - label = "0:TZ"; - reg = <0x0780000 0x0280000>; - read-only; - }; - partition@a00000 { - label = "0:RPM"; - reg = <0x0a00000 0x0280000>; - read-only; - }; - partition@c80000 { - label = "0:APPSBL"; - reg = <0x0c80000 0x0500000>; - read-only; - }; - partition@1180000 { - label = "0:APPSBLENV"; - reg = <0x1180000 0x0080000>; - }; - partition@1200000 { - label = "0:ART"; - reg = <0x1200000 0x0140000>; - read-only; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - precal_ART_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; - precal_ART_5000: precal@5000 { - reg = <0x5000 0x2f20>; - }; - }; - stock_partition@1340000 { - label = "stock_rootfs"; - reg = <0x1340000 0x4000000>; - }; - partition@5340000 { - label = "0:BOOTCONFIG"; - reg = <0x5340000 0x0060000>; - read-only; - }; - partition@53a0000 { - label = "0:SBL2_1"; - reg = <0x53a0000 0x0140000>; - read-only; - }; - partition@54e0000 { - label = "0:SBL3_1"; - reg = <0x54e0000 0x0280000>; - read-only; - }; - partition@5760000 { - label = "0:DDRCONFIG_1"; - reg = <0x5760000 0x0120000>; - read-only; - }; - partition@5880000 { - label = "0:SSD_1"; - reg = <0x5880000 0x0120000>; - read-only; - }; - partition@59a0000 { - label = "0:TZ_1"; - reg = <0x59a0000 0x0280000>; - read-only; - }; - partition@5c20000 { - label = "0:RPM_1"; - reg = <0x5c20000 0x0280000>; - read-only; - }; - partition@5ea0000 { - label = "0:BOOTCONFIG1"; - reg = <0x5ea0000 0x0060000>; - read-only; - }; - partition@5f00000 { - label = "0:APPSBL_1"; - reg = <0x5f00000 0x0500000>; - read-only; - }; - stock_partition@6400000 { - label = "stock_rootfs_1"; - reg = <0x6400000 0x4000000>; - }; - stock_partition@a400000 { - label = "stock_fw_env"; - reg = <0xa400000 0x0100000>; - }; - stock_partition@a500000 { - label = "stock_config"; - reg = <0xa500000 0x0800000>; - }; - stock_partition@ad00000 { - label = "stock_PKI"; - reg = <0xad00000 0x0200000>; - }; - stock_partition@af00000 { - label = "stock_scfgmgr"; - reg = <0xaf00000 0x0100000>; - }; - - partition@6400000 { - label = "fw_env"; - reg = <0x6400000 0x0100000>; - - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - - macaddr_fw_env_0: macaddr@0 { - reg = <0x00 0x6>; - }; - macaddr_fw_env_6: macaddr@6 { - reg = <0x06 0x6>; - }; - macaddr_fw_env_c: macaddr@c { - reg = <0x0c 0x6>; - }; - macaddr_fw_env_12: macaddr@12 { - reg = <0x12 0x6>; - }; - macaddr_fw_env_18: macaddr@18 { - reg = <0x18 0x6>; - }; - }; - partition@6500000 { - label = "ubi"; - reg = <0x6500000 0x9b00000>; - }; - partition@1340000 { - label = "extra"; - reg = <0x1340000 0x4000000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - ethernet-phy@0 { - reg = <0x0>; - qca,ar8327-initvals = < - 0x00004 0x7600000 /* PAD0_MODE */ - 0x00008 0x1000000 /* PAD5_MODE */ - 0x0000c 0x80 /* PAD6_MODE */ - 0x000e4 0xaa545 /* MAC_POWER_SEL */ - 0x000e0 0xc74164de /* SGMII_CTRL */ - 0x0007c 0x4e /* PORT0_STATUS */ - 0x00094 0x4e /* PORT6_STATUS */ - >; - }; - - phy7: ethernet-phy@7 { - reg = <7>; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - qcom,id = <0>; - - nvmem-cells = <&macaddr_fw_env_18>; - nvmem-cell-names = "mac-address"; - - pinctrl-0 = <&rgmii2_pins>; - pinctrl-names = "default"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <1>; - - nvmem-cells = <&macaddr_fw_env_0>; - nvmem-cell-names = "mac-address"; - - fixed-link { - speed = <1000>; - full-duplex; - }; -}; - -&gmac3 { - status = "okay"; - phy-mode = "sgmii"; - qcom,id = <3>; - phy-handle = <&phy7>; - - nvmem-cells = <&macaddr_fw_env_6>; - nvmem-cell-names = "mac-address"; -}; - -&adm_dma { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; - reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_pins>; - pinctrl-names = "default"; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "pci168c,0046"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>; - nvmem-cell-names = "pre-calibration", "mac-address"; - }; - }; -}; - -&pcie1 { - status = "okay"; - reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie1_pins>; - pinctrl-names = "default"; - max-link-speed = <1>; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "pci168c,0040"; - reg = <0x00010000 0 0 0 0>; - - nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>; - nvmem-cell-names = "pre-calibration", "mac-address"; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-xr500.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-xr500.dts deleted file mode 100644 index f584735e15..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065-xr500.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "qcom-ipq8065-nighthawk.dtsi" - -/ { - model = "Netgear Nighthawk XR500"; - compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064"; - -}; - -&leds { - usb1 { - label = "white:usb1"; - gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; - }; - - usb2 { - label = "white:usb2"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; - }; -}; - -&partitions { - partition@1880000 { - label = "ubi"; - reg = <0x1880000 0xce00000>; - }; - - partition@e680000 { - label = "reserve"; - reg = <0xe680000 0x0780000>; - read-only; - }; -}; - -&wifi0 { - nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&wifi1 { - nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>; - nvmem-cell-names = "mac-address", "pre-calibration"; -}; - -&art { - macaddr_art_c: macaddr@c { - reg = <0xc 0x6>; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065.dtsi b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065.dtsi deleted file mode 100644 index c70a5cbaed..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8065.dtsi +++ /dev/null @@ -1,167 +0,0 @@ -#include "qcom-ipq8064.dtsi" - -/ { - model = "Qualcomm IPQ8065"; - compatible = "qcom,ipq8065", "qcom,ipq8064"; - - aliases { - serial0 = &gsbi4_serial; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; -}; - -&gsbi4 { - qcom,mode = ; - status = "okay"; - - serial@16340000 { - status = "okay"; - }; - /* - * The i2c device on gsbi4 should not be enabled. - * On ipq806x designs gsbi4 i2c is meant for exclusive - * RPM usage. Turning this on in kernel manifests as - * i2c failure for the RPM. - */ -}; - -&pcie0 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie1 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&pcie2 { - compatible = "qcom,pcie-ipq8064-v2"; -}; - -&sata { - ports-implemented = <0x1>; -}; - -&smb208_s2a { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; -}; - -&smb208_s2b { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; -}; - -&ss_phy_0 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; - -&ss_phy_1 { - qcom,rx-eq = <2>; - qcom,tx-deamp_3_5db = <32>; - qcom,mpll = <5>; -}; - -&opp_table_l2 { - /delete-node/opp-1200000000; - - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1150000>; - clock-latency-ns = <100000>; - opp-level = <2>; - }; -}; - -&opp_table0 { - /* - * On ipq8065 1.2 ghz freq is not present - * Remove it to make cpufreq work and not - * complain for missing definition - */ - - /delete-node/opp-1200000000; - - /* - * Voltage thresholds are - */ - opp-384000000 { - opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>; - opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>; - opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; - opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; - opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>; - opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>; - opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>; - }; - - opp-600000000 { - opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; - opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; - opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>; - opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>; - opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>; - opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>; - opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>; - }; - - opp-800000000 { - opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; - opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>; - opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>; - opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>; - opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>; - opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>; - }; - - opp-1000000000 { - opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; - opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; - opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>; - opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>; - opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>; - opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>; - }; - - opp-1400000000 { - opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>; - opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>; - opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; - opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>; - opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>; - opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>; - opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>; - opp-level = <1>; - }; - - opp-1725000000 { - opp-hz = /bits/ 64 <1725000000>; - opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>; - opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>; - opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>; - opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>; - opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>; - opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>; - opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>; - opp-supported-hw = <0x1>; - clock-latency-ns = <100000>; - opp-level = <2>; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi deleted file mode 100644 index 141c71a8aa..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi +++ /dev/null @@ -1,239 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include "qcom-ipq8064-v2.0.dtsi" - -/ { - memory { - device_type = "memory"; - linux,usable-memory = <0x41500000 0x1ea00000>; - reg = <0x40000000 0x20000000>; - }; - - cpus { - idle-states { - CPU_SPC: spc { - status = "disabled"; - }; - }; - }; - - chosen { - bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art"; - }; -}; - -&qcom_pinmux { - mdio0_pins_active: mdio0_pins_active { - mux { - pins = "gpio0", "gpio1"; - function = "mdio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - - clk { - pins = "gpio1"; - input-disable; - }; - }; - - phy_active: phy_active { - phy { - pins = "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-high; - }; - }; - - uart1_pins: uart1_pins { - mux { - pins = "gpio51", "gpio52"; - function = "gsbi1"; - drive-strength = <4>; - bias-disable; - }; - }; -}; - -&gsbi1 { - status = "okay"; - qcom,mode = ; - - serial@12450000 { - status = "okay"; - - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - }; -}; - -&pcie0 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x0 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi0: wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x10000 0 0 0 0>; - }; - }; -}; - -&pcie1 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x0 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi1: wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x10000 0 0 0 0>; - }; - }; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x0 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi2: wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x10000 0 0 0 0>; - }; - }; -}; - -&adm_dma { - status = "okay"; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - nand-is-boot-medium; - qcom,boot_pages_size = <0x2140000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "sbl1"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "mibib"; - reg = <0x40000 0x140000>; - read-only; - }; - - partition@180000 { - label = "sbl2"; - reg = <0x180000 0x140000>; - read-only; - }; - - partition@2c0000 { - label = "sbl3"; - reg = <0x2c0000 0x280000>; - read-only; - }; - - partition@540000 { - label = "ddrconfig"; - reg = <0x540000 0x120000>; - read-only; - }; - - partition@660000 { - label = "ssd"; - reg = <0x660000 0x120000>; - read-only; - }; - - partition@780000 { - label = "tz"; - reg = <0x780000 0x280000>; - read-only; - }; - - partition@a00000 { - label = "rpm"; - reg = <0xa00000 0x280000>; - read-only; - }; - - partition@1fc0000 { - label = "u-boot"; - reg = <0x1fc0000 0x180000>; - read-only; - }; - - partition@21c0000 { - label = "bootkernel1"; - reg = <0x21c0000 0xa80000>; - }; - - partition@2c40000 { - label = "bootkernel2"; - reg = <0x2c40000 0xa80000>; - }; - - partition@36c0000 { - label = "ubi"; - reg = <0x36c0000 0x46c0000>; - }; - - partition@7d80000 { - label = "art"; - reg = <0x7d80000 0x200000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts deleted file mode 100644 index 85b0dc3b8c..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts +++ /dev/null @@ -1,332 +0,0 @@ -#include "qcom-ipq8064-v2.0.dtsi" - -#include -#include - -/ { - model = "Edgecore ECW5410"; - compatible = "edgecore,ecw5410", "qcom,ipq8064"; - - reserved-memory { - nss@40000000 { - reg = <0x40000000 0x1000000>; - no-map; - }; - - smem: smem@41000000 { - reg = <0x41000000 0x200000>; - no-map; - }; - - wifi_dump@44000000 { - reg = <0x44000000 0x600000>; - no-map; - }; - }; - - cpus { - idle-states { - CPU_SPC: spc { - status = "disabled"; - }; - }; - }; - - aliases { - serial1 = &gsbi1_serial; - ethernet0 = &gmac2; - ethernet1 = &gmac3; - - led-boot = &led_power_green; - led-failsafe = &led_power_red; - led-running = &led_power_green; - led-upgrade = &led_power_green; - }; - - chosen { - bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1"; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power_green: power_green { - label = "green:power"; - gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; - }; - - wlan2g_green { - label = "green:wlan2g"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; - }; - - wlan2g_yellow { - label = "yellow:wlan2g"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; - }; - - wlan5g_green { - label = "green:wlan5g"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - led_power_red: power_red { - label = "red:power"; - gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; - }; - - wlan5g_yellow { - label = "yellow:wlan5g"; - gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>; - }; - }; -}; - - -&qcom_pinmux { - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi5"; - drive-strength = <10>; - bias-pull-down; - }; - - clk { - pins = "gpio21"; - function = "gsbi5"; - drive-strength = <12>; - bias-pull-down; - }; - - cs { - pins = "gpio20"; - function = "gpio"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio16", "gpio23", "gpio24", "gpio26", - "gpio28", "gpio59"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - uart1_pins: uart1_pins { - mux { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - function = "gsbi1"; - drive-strength = <12>; - bias-none; - }; - }; -}; - -&gsbi1 { - qcom,mode = ; - status = "okay"; - - serial@12450000 { - status = "okay"; - - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - }; -}; - -&gsbi5 { - qcom,mode = ; - status = "okay"; - - spi4: spi@1a280000 { - status = "okay"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; - - m25p80@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partitions { - compatible = "qcom,smem-part"; - }; - }; - }; -}; - -&hs_phy_0 { /* USB3 port 0 HS phy */ - status = "okay"; -}; - -&hs_phy_1 { /* USB3 port 1 HS phy */ - status = "okay"; -}; - -&ss_phy_0 { /* USB3 port 0 SS phy */ - status = "okay"; -}; - -&ss_phy_1 { /* USB3 port 1 SS phy */ - status = "okay"; -}; - -&usb3_0 { - status = "okay"; -}; - -&usb3_1 { - status = "okay"; -}; - -&pcie1 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; - }; - }; -}; - -&pcie2 { - status = "okay"; - - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - /delete-property/ perst-gpios; - - bridge@0,0 { - reg = <0x00000000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - wifi@1,0 { - compatible = "qcom,ath10k"; - status = "okay"; - reg = <0x00010000 0 0 0 0>; - qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; - }; - }; -}; - -&nand { - status = "okay"; - - pinctrl-0 = <&nand_pins>; - pinctrl-names = "default"; - - nand@0 { - compatible = "qcom,nandcs"; - - reg = <0>; - - nand-ecc-strength = <4>; - nand-bus-width = <8>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - rootfs1@0 { - label = "rootfs1"; - reg = <0x0000000 0x4000000>; - }; - - rootfs2@4000000 { - label = "rootfs2"; - reg = <0x4000000 0x4000000>; - }; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&gmac2 { - status = "okay"; - - qcom,id = <2>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy1>; -}; - -&gmac3 { - status = "okay"; - - qcom,id = <3>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy0>; -}; - -&adm_dma { - status = "okay"; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-mr42.dts deleted file mode 100644 index ccf2554ca3..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-mr42.dts +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include "qcom-ipq8068-cryptid-common.dtsi" - -#include - -/ { - model = "Meraki MR42"; - compatible = "meraki,mr42", "qcom,ipq8064"; - - aliases { - serial1 = &gsbi1_serial; - ethernet0 = &gmac3; - - led-boot = &led_active; - led-failsafe = &led_power; - led-running = &led_active; - led-upgrade = &led_active; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power: power { - label = "orange:power"; - gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>; - }; - - led_active: active { - label = "white:active"; - gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gmac3 { - status = "okay"; - - qcom,id = <3>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy2>; - - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; -}; - -&gsbi2 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi2_i2c { - status = "okay"; - - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - ina2xx@40 { - compatible = "ina219"; - shunt-resistor = <40000>; - reg = <0x40>; - }; - - eeprom@56 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x56>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; -}; - -&gsbi6 { - qcom,mode = ; - status = "okay"; -}; - -&gsbi6_i2c { - status = "okay"; - - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - tlc591xx@40 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tlc59108"; - reg = <0x40>; - - red@0 { - label = "red:user"; - reg = <0x0>; - }; - - green@1 { - label = "green:user"; - reg = <0x1>; - }; - - blue@2 { - label = "blue:user"; - reg = <0x2>; - }; - }; -}; - -&mdio0 { - status = "okay"; - - pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; - pinctrl-names = "default"; - - phy2: ethernet-phy2 { - reg = <2>; - - reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - reset-assert-us = <24000>; - - eee-broken-100tx; - eee-broken-1000t; - }; -}; - -&qcom_pinmux { - i2c0_pins: i2c0_pins { - mux { - pins = "gpio24", "gpio25"; - function = "gsbi2"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - i2c1_pins: i2c1_pins { - mux { - pins = "gpio29", "gpio30"; - function = "gsbi6"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio31", "gpio32"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-low; - }; - }; -}; - -&wifi0 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; -}; - -&wifi1 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; -}; - -&wifi2 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <3>; -}; diff --git a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-mr52.dts deleted file mode 100644 index e1c233254d..0000000000 --- a/target/linux/ipq806x/files-5.10/arch/arm/boot/dts/qcom-ipq8068-mr52.dts +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT - -#include "qcom-ipq8068-cryptid-common.dtsi" - -#include - -/ { - model = "Meraki MR52"; - compatible = "meraki,mr52", "qcom,ipq8064"; - - aliases { - serial1 = &gsbi1_serial; - mdio-gpio0 = &mdio_gpio0; - ethernet0 = &gmac2; - ethernet1 = &gmac3; - - led-boot = &led_active; - led-failsafe = &led_power; - led-running = &led_active; - led-upgrade = &led_active; - }; - - keys { - compatible = "gpio-keys"; - pinctrl-0 = <&button_pins>; - pinctrl-names = "default"; - - reset { - label = "reset"; - gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <60>; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&led_pins>; - pinctrl-names = "default"; - - led_power: power { - label = "orange:power"; - gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>; - }; - - lan2_green { - label = "green:lan2"; - gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; - }; - - lan1_green { - label = "green:lan1"; - gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; - }; - - led_active: active { - label = "white:active"; - gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; - }; - - lan2_orange { - label = "orange:lan2"; - gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>; - }; - - lan1_orange { - label = "orange:lan1"; - gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&gmac2 { - status = "okay"; - - qcom,id = <2>; - mdiobus = <&mdio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy0>; - - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; -}; - -&gmac3 { - status = "okay"; - - qcom,id = <3>; - mdiobus = <&mdio_gpio0>; - - phy-mode = "sgmii"; - phy-handle = <&phy4>; - - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <1>; -}; - -&gsbi7 { - status = "okay"; - qcom,mode = ; -}; - -&gsbi7_i2c { - status = "okay"; - - pinctrl-0 = <&i2c_pins>; - pinctrl-names = "default"; - - ina2xx@45 { - compatible = "ina219"; - shunt-resistor = <80000>; - reg = <0x45>; - }; - - tlc591xx@49 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tlc59108"; - reg = <0x49>; - - red@0 { - label = "red:user"; - reg = <0x0>; - }; - - green@1 { - label = "green:user"; - reg = <0x1>; - }; - - blue@2 { - label = "blue:user"; - reg = <0x2>; - }; - }; - - eeprom@52 { - compatible = "atmel,24c64"; - pagesize = <32>; - reg = <0x52>; - read-only; - #address-cells = <1>; - #size-cells = <1>; - - mac_address: mac-address@66 { - reg = <0x66 0x6>; - }; - }; -}; - -&qcom_pinmux { - i2c_pins: i2c_pins { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi7"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; - - led_pins: led_pins { - mux { - pins = "gpio19", "gpio26"; - function = "gpio"; - drive-strength = <12>; - bias-pull-down; - output-low; - }; - }; - - button_pins: button_pins { - mux { - pins = "gpio25"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - input; - }; - }; -}; - -&soc { - mdio_gpio0: mdio { - compatible = "virtual,mdio-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - status = "okay"; - - pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; - pinctrl-names = "default"; - - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH - &qcom_pinmux 0 GPIO_ACTIVE_HIGH>; - - phy0: ethernet-phy0 { - reg = <0>; - reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; - reset-assert-us = <24000>; - }; - - phy4: ethernet-phy4 { - reg = <4>; - reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; - reset-assert-us = <24000>; - }; - }; -}; - -&wifi0 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <4>; -}; - -&wifi1 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <3>; -}; - -&wifi2 { - nvmem-cells = <&mac_address>; - nvmem-cell-names = "mac-address"; - mac-address-increment = <2>; -}; diff --git a/target/linux/ipq806x/patches-5.10/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch b/target/linux/ipq806x/patches-5.10/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch deleted file mode 100644 index 83d7bbc6f4..0000000000 --- a/target/linux/ipq806x/patches-5.10/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 28d0ed88f536dd639adf1b0c7c08e04be3c8f294 Mon Sep 17 00:00:00 2001 -From: Thomas Pedersen -Date: Mon, 16 May 2016 17:58:50 -0700 -Subject: [PATCH 01/69] dtbindings: qcom_adm: Fix channel specifiers - -Original patch from Andy Gross. - -This patch removes the crci information from the dma -channel property. At least one client device requires -using more than one CRCI value for a channel. This does -not match the current binding and the crci information -needs to be removed. - -Instead, the client device will provide this information -via other means. - -Signed-off-by: Andy Gross -Signed-off-by: Thomas Pedersen ---- - Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++++++---------- - 1 file changed, 6 insertions(+), 10 deletions(-) - ---- a/Documentation/devicetree/bindings/dma/qcom_adm.txt -+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt -@@ -4,8 +4,7 @@ Required properties: - - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 - - reg: Address range for DMA registers - - interrupts: Should contain one interrupt shared by all channels --- #dma-cells: must be <2>. First cell denotes the channel number. Second cell -- denotes CRCI (client rate control interface) flow control assignment. -+- #dma-cells: must be <1>. First cell denotes the channel number. - - clocks: Should contain the core clock and interface clock. - - clock-names: Must contain "core" for the core clock and "iface" for the - interface clock. -@@ -22,7 +21,7 @@ Example: - compatible = "qcom,adm"; - reg = <0x18300000 0x100000>; - interrupts = <0 170 0>; -- #dma-cells = <2>; -+ #dma-cells = <1>; - - clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; - clock-names = "core", "iface"; -@@ -35,15 +34,12 @@ Example: - qcom,ee = <0>; - }; - --DMA clients must use the format descripted in the dma.txt file, using a three -+DMA clients must use the format descripted in the dma.txt file, using a two - cell specifier for each channel. - --Each dmas request consists of 3 cells: -+Each dmas request consists of two cells: - 1. phandle pointing to the DMA controller - 2. channel number -- 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. -- The CRCI is used for flow control. It identifies the peripheral device that -- is the source/destination for the transferred data. - - Example: - -@@ -55,7 +51,7 @@ Example: - - cs-gpios = <&qcom_pinmux 20 0>; - -- dmas = <&adm_dma 6 9>, -- <&adm_dma 5 10>; -+ dmas = <&adm_dma 6>, -+ <&adm_dma 5>; - dma-names = "rx", "tx"; - }; diff --git a/target/linux/ipq806x/patches-5.10/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch b/target/linux/ipq806x/patches-5.10/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch deleted file mode 100644 index a12aa721e2..0000000000 --- a/target/linux/ipq806x/patches-5.10/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 48051ece78136e4235a2415a52797db56f8a4478 Mon Sep 17 00:00:00 2001 -From: Mathieu Olivari -Date: Tue, 21 Apr 2015 19:09:07 -0700 -Subject: [PATCH 33/69] ARM: qcom: automatically select PCI_DOMAINS if PCI is - enabled - -If multiple PCIe devices are present in the system, the kernel will -panic at boot time when trying to scan the PCI buses. This happens on -IPQ806x based platforms, which has 3 PCIe ports. - -Enabling this option allows the kernel to assign the pci-domains -according to the device-tree content. This allows multiple PCIe -controllers to coexist in the system. - -Signed-off-by: Mathieu Olivari ---- - arch/arm/mach-qcom/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-qcom/Kconfig -+++ b/arch/arm/mach-qcom/Kconfig -@@ -7,6 +7,7 @@ menuconfig ARCH_QCOM - select ARM_AMBA - select PINCTRL - select QCOM_SCM if SMP -+ select PCI_DOMAINS if PCI - help - Support for Qualcomm's devicetree based systems. - diff --git a/target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch b/target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch deleted file mode 100644 index b73218e71b..0000000000 --- a/target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch +++ /dev/null @@ -1,62 +0,0 @@ -From fa71139b55e114aa8c3c4823ff8ee7d49ee810d4 Mon Sep 17 00:00:00 2001 -From: Mathieu Olivari -Date: Wed, 29 Apr 2015 15:21:46 -0700 -Subject: [PATCH 60/69] HACK: arch: arm: force ZRELADDR on arch-qcom - -ARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended -on most ARM architectures. This automatically calculate ZRELADDR by -masking PHYS_OFFSET with 0xf8000000. - -However, on IPQ806x, the first ~20MB of RAM is reserved for the hardware -network accelerators, and the bootloader removes this section from the -layout passed from the ATAGS (when used). - -For newer bootloader, when DT is used, this is not a problem, we just -reserve this memory in the device tree. But if the bootloader doesn't -have DT support, then ATAGS have to be used. In this case, the ARM -decompressor will position the kernel in this low mem, which will not be -in the RAM section mapped by the bootloader, which means the kernel will -freeze in the middle of the boot process trying to map the memory. - -As a work around, this patch allows disabling AUTO_ZRELADDR when -ARCH_QCOM is selected. It makes the zImage usage possible on bootloaders -which don't support device-tree, which is the case on certain early -IPQ806x based designs. - -Signed-off-by: Mathieu Olivari ---- - arch/arm/Kconfig | 2 +- - arch/arm/Makefile | 2 ++ - arch/arm/mach-qcom/Makefile.boot | 1 + - 3 files changed, 4 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/mach-qcom/Makefile.boot - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM - select ARCH_SELECT_MEMORY_MODEL - select ARM_HAS_SG_CHAIN - select ARM_PATCH_PHYS_VIRT -- select AUTO_ZRELADDR -+ select AUTO_ZRELADDR if !ARCH_QCOM - select TIMER_OF - select COMMON_CLK - select GENERIC_CLOCKEVENTS ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -251,9 +251,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac - else - MACHINE := - endif -+ifeq ($(CONFIG_ARCH_QCOM),) - ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y) - MACHINE := - endif -+endif - - machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) - platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y))) ---- /dev/null -+++ b/arch/arm/mach-qcom/Makefile.boot -@@ -0,0 +1 @@ -+zreladdr-y+= 0x42208000 diff --git a/target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch b/target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch deleted file mode 100644 index a1a0371fbc..0000000000 --- a/target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 4d8e29642661397a339ac3485f212c6360445421 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 09:33:32 +0100 -Subject: [PATCH 65/69] arm: override compiler flags - -Signed-off-by: John Crispin ---- - arch/arm/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -61,7 +61,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-i - # macro, but instead defines a whole series of macros which makes - # testing for a specific architecture or later rather impossible. - arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m --arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -march=armv7-a -+arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15 - arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 -march=armv6 - # Only override the compiler option if ARMv6. The ARMv6K extensions are - # always available in ARMv7 diff --git a/target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch deleted file mode 100644 index e9f2d05937..0000000000 --- a/target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch +++ /dev/null @@ -1,210 +0,0 @@ -From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 09:37:17 +0100 -Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - -Signed-off-by: Adrian Panella ---- - arch/arm/Kconfig | 11 +++++ - arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++- - init/main.c | 16 ++++++++ - 3 files changed, 98 insertions(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1777,6 +1777,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -5,6 +5,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -69,6 +71,80 @@ static uint32_t get_cell_size(const void - return cell_size; - } - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+/** -+ * taken from arch/x86/boot/string.c -+ * local_strstr - Find the first substring in a %NUL terminated string -+ * @s1: The string to be searched -+ * @s2: The string to search for -+ */ -+static char *local_strstr(const char *s1, const char *s2) -+{ -+ size_t l1, l2; -+ -+ l2 = strlen(s2); -+ if (!l2) -+ return (char *)s1; -+ l1 = strlen(s1); -+ while (l1 >= l2) { -+ l1--; -+ if (!memcmp(s1, s2, l2)) -+ return (char *)s1; -+ s1++; -+ } -+ return NULL; -+} -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ char *ptr, *end, *tmp; -+ char *root="root="; -+ char *find_rootblock; -+ int i, l; -+ const char *rootblock; -+ -+ find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l); -+ if(!find_rootblock) -+ find_rootblock = root; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 -+ ptr = local_strstr(str, find_rootblock); -+ -+ if(!ptr) -+ return dest; -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ // Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. -+ tmp = strchr(ptr, ','); -+ -+ if(tmp) -+ end = end < tmp ? end : tmp - 1; -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if(rootblock != NULL) { -+ if(*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ } -+ return dest; -+} -+#endif -+ - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { - char cmdline[COMMAND_LINE_SIZE]; -@@ -88,12 +164,21 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - -@@ -168,7 +253,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -212,6 +299,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -110,6 +110,10 @@ - - #include - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -906,6 +910,18 @@ asmlinkage __visible void __init __no_sa - pr_notice("Kernel command line: %s\n", saved_command_line); - /* parameters may set static keys */ - jump_label_init(); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - parse_early_param(); - after_dashes = parse_args("Booting kernel", - static_command_line, __start___param, diff --git a/target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch b/target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch deleted file mode 100644 index b3c8a514e5..0000000000 --- a/target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/firmware/qcom_scm.c -+++ b/drivers/firmware/qcom_scm.c -@@ -1269,6 +1269,7 @@ static const struct of_device_id qcom_sc - SCM_HAS_BUS_CLK) - }, - { .compatible = "qcom,scm-ipq4019" }, -+ { .compatible = "qcom,scm-ipq806x" }, - { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK }, - { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK }, - { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK | diff --git a/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch b/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch deleted file mode 100644 index 1046af15d4..0000000000 --- a/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch +++ /dev/null @@ -1,212 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -20,7 +20,7 @@ - #address-cells = <1>; - #size-cells = <0>; - -- cpu@0 { -+ cpu0: cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; -@@ -30,7 +30,7 @@ - qcom,saw = <&saw0>; - }; - -- cpu@1 { -+ cpu1: cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; -@@ -67,7 +67,7 @@ - no-map; - }; - -- smem@41000000 { -+ smem: smem@41000000 { - reg = <0x41000000 0x200000>; - no-map; - }; -@@ -128,6 +128,7 @@ - gpio-ranges = <&qcom_pinmux 0 0 69>; - #gpio-cells = <2>; - interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <2>; - interrupts = ; - -@@ -190,6 +191,7 @@ - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; -@@ -219,21 +221,23 @@ - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; -+ clock-output-names = "acpu0_aux"; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; -+ clock-output-names = "acpu1_aux"; - }; - - saw0: regulator@2089000 { -- compatible = "qcom,saw2"; -+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { -- compatible = "qcom,saw2"; -+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; -@@ -251,7 +255,7 @@ - - syscon-tcsr = <&tcsr>; - -- serial@12490000 { -+ gsbi2_serial: serial@12490000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12490000 0x1000>, - <0x12480000 0x1000>; -@@ -261,7 +265,7 @@ - status = "disabled"; - }; - -- i2c@124a0000 { -+ gsbi2_i2c: i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = ; -@@ -326,7 +330,7 @@ - - syscon-tcsr = <&tcsr>; - -- serial@1a240000 { -+ gsbi5_serial: serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x1000>, - <0x1a200000 0x1000>; -@@ -397,7 +401,7 @@ - status = "disabled"; - }; - -- sata@29000000 { -+ sata: sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; - -@@ -430,13 +434,35 @@ - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ tsens_calib: calib@400 { -+ reg = <0x400 0xb>; -+ }; -+ tsens_backup: backup@410 { -+ reg = <0x410 0xb>; -+ }; -+ speedbin_efuse: speedbin@0c0 { -+ reg = <0x0c0 0x4>; -+ }; - }; - - gcc: clock-controller@900000 { -- compatible = "qcom,gcc-ipq8064"; -+ compatible = "qcom,gcc-ipq8064", "syscon"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; -+ #power-domain-cells = <1>; -+ -+ tsens: thermal-sensor@900000 { -+ compatible = "qcom,ipq8064-tsens"; -+ -+ nvmem-cells = <&tsens_calib>, <&tsens_backup>; -+ nvmem-cell-names = "calib", "calib_backup"; -+ interrupts = ; -+ interrupt-names = "uplow"; -+ #thermal-sensor-cells = <1>; -+ #qcom,sensors = <11>; -+ }; - }; - - tcsr: syscon@1a400000 { -@@ -622,7 +648,7 @@ - - gmac0: ethernet@37000000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37000000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -645,7 +671,7 @@ - - gmac1: ethernet@37200000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37200000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -668,7 +694,7 @@ - - gmac2: ethernet@37400000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37400000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -691,7 +717,7 @@ - - gmac3: ethernet@37600000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37600000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -740,13 +766,13 @@ - qcom,ee = <0>; - }; - -- amba { -- compatible = "simple-bus"; -+ amba: amba { -+ compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - -- sdcc@12400000 { -+ sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; -@@ -760,13 +786,12 @@ - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; -- mmc-ddr-1_8v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - -- sdcc@12180000 { -+ sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; diff --git a/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch b/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch deleted file mode 100644 index 82d91e1242..0000000000 --- a/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch +++ /dev/null @@ -1,846 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -8,6 +8,8 @@ - #include - #include - #include -+#include -+#include - - / { - #address-cells = <1>; -@@ -28,6 +30,16 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; -+ clocks = <&kraitcc 0>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ cpu-supply = <&smb208_s2a>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; - }; - - cpu1: cpu@1 { -@@ -38,14 +50,350 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; -+ clocks = <&kraitcc 1>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ cpu-supply = <&smb208_s2b>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; -+ }; -+ -+ idle-states { -+ CPU_SPC: spc { -+ compatible = "qcom,idle-state-spc"; -+ status = "disabled"; -+ entry-latency-us = <400>; -+ exit-latency-us = <900>; -+ min-residency-us = <3000>; -+ }; - }; -+ }; - -- L2: l2-cache { -- compatible = "cache"; -- cache-level = <2>; -+ opp_table_l2: opp_table_l2 { -+ compatible = "operating-points-v2"; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1150000>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ -+ opp_table0: opp_table0 { -+ compatible = "operating-points-v2-kryo-cpu"; -+ nvmem-cells = <&speedbin_efuse>; -+ -+ /* -+ * Voltage thresholds are -+ */ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; -+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; -+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; -+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; -+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; -+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; - }; - }; - -+ thermal-zones { -+ tsens_tz_sensor0 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 0>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor1 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 1>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor2 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 2>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor3 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 3>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor4 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 4>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor5 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 5>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor6 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 6>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor7 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 7>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor8 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 8>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor9 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 9>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ -+ tsens_tz_sensor10 { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsens 10>; -+ -+ trips { -+ cpu-critical { -+ temperature = <105000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ -+ cpu-hot { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "hot"; -+ }; -+ }; -+ }; -+ }; -+ - memory { - device_type = "memory"; - reg = <0x0 0x0>; -@@ -93,6 +441,15 @@ - }; - }; - -+ fab-scaling { -+ compatible = "qcom,fab-scaling"; -+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>; -+ clock-names = "apps-fab-clk", "ddr-fab-clk"; -+ fab_freq_high = <533000000>; -+ fab_freq_nominal = <400000000>; -+ cpu_freq_threshold = <1000000000>; -+ }; -+ - firmware { - scm { - compatible = "qcom,scm-ipq806x", "qcom,scm"; -@@ -120,6 +477,78 @@ - reg-names = "lpass-lpaif"; - }; - -+ L2: l2-cache { -+ compatible = "qcom,krait-cache", "cache"; -+ cache-level = <2>; -+ qcom,saw = <&saw_l2>; -+ -+ clocks = <&kraitcc 4>; -+ clock-names = "l2"; -+ l2-supply = <&smb208_s1a>; -+ operating-points-v2 = <&opp_table_l2>; -+ }; -+ -+ rpm: rpm@108000 { -+ compatible = "qcom,rpm-ipq8064"; -+ reg = <0x108000 0x1000>; -+ qcom,ipc = <&l2cc 0x8 2>; -+ -+ interrupts = , -+ , -+ ; -+ interrupt-names = "ack", "err", "wakeup"; -+ -+ clocks = <&gcc RPM_MSG_RAM_H_CLK>; -+ clock-names = "ram"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rpmcc: clock-controller { -+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; -+ #clock-cells = <1>; -+ }; -+ -+ regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; -+ }; -+ -+ rng@1a500000 { -+ compatible = "qcom,prng"; -+ reg = <0x1a500000 0x200>; -+ clocks = <&gcc PRNG_CLK>; -+ clock-names = "core"; -+ }; -+ - qcom_pinmux: pinmux@800000 { - compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; -@@ -159,6 +588,15 @@ - }; - }; - -+ i2c4_pins: i2c4_pinmux { -+ mux { -+ pins = "gpio12", "gpio13"; -+ function = "gsbi4"; -+ drive-strength = <12>; -+ bias-disable; -+ }; -+ }; -+ - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; -@@ -168,6 +606,53 @@ - }; - }; - -+ nand_pins: nand_pins { -+ disable { -+ pins = "gpio34", "gpio35", "gpio36", -+ "gpio37", "gpio38"; -+ function = "nand"; -+ drive-strength = <10>; -+ bias-disable; -+ }; -+ -+ pullups { -+ pins = "gpio39"; -+ function = "nand"; -+ drive-strength = <10>; -+ bias-pull-up; -+ }; -+ -+ hold { -+ pins = "gpio40", "gpio41", "gpio42", -+ "gpio43", "gpio44", "gpio45", -+ "gpio46", "gpio47"; -+ function = "nand"; -+ drive-strength = <10>; -+ bias-bus-hold; -+ }; -+ }; -+ -+ mdio0_pins: mdio0_pins { -+ mux { -+ pins = "gpio0", "gpio1"; -+ function = "mdio"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; -+ -+ rgmii2_pins: rgmii2_pins { -+ mux { -+ pins = "gpio27", "gpio28", "gpio29", -+ "gpio30", "gpio31", "gpio32", -+ "gpio51", "gpio52", "gpio59", -+ "gpio60", "gpio61", "gpio62"; -+ function = "rgmii2"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; -+ - leds_pins: leds_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", -@@ -230,6 +715,17 @@ - clock-output-names = "acpu1_aux"; - }; - -+ l2cc: clock-controller@2011000 { -+ compatible = "qcom,kpss-gcc", "syscon"; -+ reg = <0x2011000 0x1000>; -+ clock-output-names = "acpu_l2_aux"; -+ }; -+ -+ kraitcc: clock-controller { -+ compatible = "qcom,krait-cc-v1"; -+ #clock-cells = <1>; -+ }; -+ - saw0: regulator@2089000 { - compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; -@@ -242,6 +738,52 @@ - regulator; - }; - -+ saw_l2: regulator@02012000 { -+ compatible = "qcom,saw2", "syscon"; -+ reg = <0x02012000 0x1000>; -+ regulator; -+ }; -+ -+ sic_non_secure: sic-non-secure@12100000 { -+ compatible = "syscon"; -+ reg = <0x12100000 0x10000>; -+ }; -+ -+ gsbi1: gsbi@12440000 { -+ compatible = "qcom,gsbi-v1.0.0"; -+ cell-index = <1>; -+ reg = <0x12440000 0x100>; -+ clocks = <&gcc GSBI1_H_CLK>; -+ clock-names = "iface"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ status = "disabled"; -+ -+ syscon-tcsr = <&tcsr>; -+ -+ gsbi1_serial: serial@12450000 { -+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; -+ reg = <0x12450000 0x100>, -+ <0x12400000 0x03>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ gsbi1_i2c: i2c@12460000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x12460000 0x1000>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; -@@ -367,6 +909,33 @@ - }; - }; - -+ gsbi6: gsbi@16500000 { -+ status = "disabled"; -+ compatible = "qcom,gsbi-v1.0.0"; -+ cell-index = <6>; -+ reg = <0x16500000 0x100>; -+ clocks = <&gcc GSBI6_H_CLK>; -+ clock-names = "iface"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ -+ syscon-tcsr = <&tcsr>; -+ -+ gsbi6_i2c: i2c@16580000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x16580000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; -@@ -388,6 +957,19 @@ - clock-names = "core", "iface"; - status = "disabled"; - }; -+ -+ gsbi7_i2c: i2c@16680000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x16680000 0x1000>; -+ interrupts = ; -+ -+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; - }; - - sata_phy: sata-phy@1b400000 { -@@ -477,6 +1059,95 @@ - #reset-cells = <1>; - }; - -+ sfpb_mutex_block: syscon@1200600 { -+ compatible = "syscon"; -+ reg = <0x01200600 0x100>; -+ }; -+ -+ hs_phy_0: hs_phy_0 { -+ compatible = "qcom,ipq806x-usb-phy-hs"; -+ reg = <0x100f8800 0x30>; -+ clocks = <&gcc USB30_0_UTMI_CLK>; -+ clock-names = "ref"; -+ #phy-cells = <0>; -+ }; -+ -+ ss_phy_0: ss_phy_0 { -+ compatible = "qcom,ipq806x-usb-phy-ss"; -+ reg = <0x100f8830 0x30>; -+ clocks = <&gcc USB30_0_MASTER_CLK>; -+ clock-names = "ref"; -+ #phy-cells = <0>; -+ }; -+ -+ usb3_0: usb3@100f8800 { -+ compatible = "qcom,dwc3", "syscon"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x100f8800 0x8000>; -+ clocks = <&gcc USB30_0_MASTER_CLK>; -+ clock-names = "core"; -+ -+ ranges; -+ -+ resets = <&gcc USB30_0_MASTER_RESET>; -+ reset-names = "master"; -+ -+ status = "disabled"; -+ -+ dwc3_0: dwc3@10000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x10000000 0xcd00>; -+ interrupts = ; -+ phys = <&hs_phy_0>, <&ss_phy_0>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ dr_mode = "host"; -+ snps,dis_u3_susphy_quirk; -+ }; -+ }; -+ -+ hs_phy_1: hs_phy_1 { -+ compatible = "qcom,ipq806x-usb-phy-hs"; -+ reg = <0x110f8800 0x30>; -+ clocks = <&gcc USB30_1_UTMI_CLK>; -+ clock-names = "ref"; -+ #phy-cells = <0>; -+ }; -+ -+ ss_phy_1: ss_phy_1 { -+ compatible = "qcom,ipq806x-usb-phy-ss"; -+ reg = <0x110f8830 0x30>; -+ clocks = <&gcc USB30_1_MASTER_CLK>; -+ clock-names = "ref"; -+ #phy-cells = <0>; -+ }; -+ -+ usb3_1: usb3@110f8800 { -+ compatible = "qcom,dwc3", "syscon"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x110f8800 0x8000>; -+ clocks = <&gcc USB30_1_MASTER_CLK>; -+ clock-names = "core"; -+ -+ ranges; -+ -+ resets = <&gcc USB30_1_MASTER_RESET>; -+ reset-names = "master"; -+ -+ status = "disabled"; -+ -+ dwc3_1: dwc3@11000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x11000000 0xcd00>; -+ interrupts = ; -+ phys = <&hs_phy_1>, <&ss_phy_1>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ dr_mode = "host"; -+ snps,dis_u3_susphy_quirk; -+ }; -+ }; -+ - pcie0: pci@1b500000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b500000 0x1000 -@@ -738,6 +1409,59 @@ - status = "disabled"; - }; - -+ adm_dma: dma@18300000 { -+ compatible = "qcom,adm"; -+ reg = <0x18300000 0x100000>; -+ interrupts = ; -+ #dma-cells = <1>; -+ -+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; -+ clock-names = "core", "iface"; -+ -+ resets = <&gcc ADM0_RESET>, -+ <&gcc ADM0_PBUS_RESET>, -+ <&gcc ADM0_C0_RESET>, -+ <&gcc ADM0_C1_RESET>, -+ <&gcc ADM0_C2_RESET>; -+ reset-names = "clk", "pbus", "c0", "c1", "c2"; -+ qcom,ee = <0>; -+ -+ status = "disabled"; -+ }; -+ -+ nand: nand-controller@1ac00000 { -+ compatible = "qcom,ipq806x-nand"; -+ reg = <0x1ac00000 0x800>; -+ -+ clocks = <&gcc EBI2_CLK>, -+ <&gcc EBI2_AON_CLK>; -+ clock-names = "core", "aon"; -+ -+ dmas = <&adm_dma 3>; -+ dma-names = "rxtx"; -+ qcom,cmd-crci = <15>; -+ qcom,data-crci = <3>; -+ -+ status = "disabled"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ mdio0: mdio@37000000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "qcom,ipq8064-mdio", "syscon"; -+ reg = <0x37000000 0x200000>; -+ resets = <&gcc GMAC_CORE1_RESET>; -+ reset-names = "stmmaceth"; -+ clocks = <&gcc GMAC_CORE1_CLK>; -+ clock-names = "stmmaceth"; -+ -+ status = "disabled"; -+ }; -+ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; -@@ -813,4 +1537,17 @@ - }; - }; - }; -+ -+ sfpb_mutex: sfpb-mutex { -+ compatible = "qcom,sfpb-mutex"; -+ syscon = <&sfpb_mutex_block 4 4>; -+ -+ #hwlock-cells = <1>; -+ }; -+ -+ smem { -+ compatible = "qcom,smem"; -+ memory-region = <&smem>; -+ hwlocks = <&sfpb_mutex 3>; -+ }; - }; diff --git a/target/linux/ipq806x/patches-5.10/084-ipq8064-v1.0-dtsi-cleanup.patch b/target/linux/ipq806x/patches-5.10/084-ipq8064-v1.0-dtsi-cleanup.patch deleted file mode 100644 index e5ea8e6393..0000000000 --- a/target/linux/ipq806x/patches-5.10/084-ipq8064-v1.0-dtsi-cleanup.patch +++ /dev/null @@ -1,89 +0,0 @@ -This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches -instead of keeping a local version. -We drop partitions, LEDs and keys from the file as we will implement -them differently anyway. - ---- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi -@@ -42,16 +42,6 @@ - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; -- -- partition@0 { -- label = "rootfs"; -- reg = <0x0 0x1000000>; -- }; -- -- partition@1 { -- label = "scratch"; -- reg = <0x1000000 0x1000000>; -- }; - }; - }; - }; -@@ -64,64 +54,5 @@ - ports-implemented = <0x1>; - status = "ok"; - }; -- -- gpio_keys { -- compatible = "gpio-keys"; -- pinctrl-0 = <&buttons_pins>; -- pinctrl-names = "default"; -- -- button@1 { -- label = "reset"; -- linux,code = ; -- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; -- linux,input-type = <1>; -- debounce-interval = <60>; -- }; -- button@2 { -- label = "wps"; -- linux,code = ; -- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; -- linux,input-type = <1>; -- debounce-interval = <60>; -- }; -- }; -- -- leds { -- compatible = "gpio-leds"; -- pinctrl-0 = <&leds_pins>; -- pinctrl-names = "default"; -- -- led@7 { -- label = "led_usb1"; -- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "usbdev"; -- default-state = "off"; -- }; -- -- led@8 { -- label = "led_usb3"; -- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "usbdev"; -- default-state = "off"; -- }; -- -- led@9 { -- label = "status_led_fail"; -- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- -- led@26 { -- label = "sata_led"; -- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- -- led@53 { -- label = "status_led_pass"; -- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; -- default-state = "off"; -- }; -- }; - }; - }; diff --git a/target/linux/ipq806x/patches-5.10/085-ipq8064-v1.0-dtsi-additions.patch b/target/linux/ipq806x/patches-5.10/085-ipq8064-v1.0-dtsi-additions.patch deleted file mode 100644 index 58f6a46e4f..0000000000 --- a/target/linux/ipq806x/patches-5.10/085-ipq8064-v1.0-dtsi-additions.patch +++ /dev/null @@ -1,14 +0,0 @@ -This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches -instead of keeping a local version. This patch adds our local adjustments -for the (local) additional contents of qcom-ipq8064.dtsi - ---- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi -@@ -56,3 +56,7 @@ - }; - }; - }; -+ -+&CPU_SPC { -+ status = "okay"; -+}; diff --git a/target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch b/target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch deleted file mode 100644 index 747fa8c019..0000000000 --- a/target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch +++ /dev/null @@ -1,145 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts -@@ -24,73 +24,6 @@ - device_type = "memory"; - }; - -- mdio0: mdio-0 { -- status = "okay"; -- compatible = "virtual,mdio-gpio"; -- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, -- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>; -- #address-cells = <1>; -- #size-cells = <0>; -- -- pinctrl-0 = <&mdio0_pins>; -- pinctrl-names = "default"; -- -- switch0: switch@10 { -- compatible = "qca,qca8337"; -- #address-cells = <1>; -- #size-cells = <0>; -- -- dsa,member = <0 0>; -- -- pinctrl-0 = <&sw0_reset_pin>; -- pinctrl-names = "default"; -- -- reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; -- reg = <0x10>; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- switch0cpu: port@0 { -- reg = <0>; -- label = "cpu"; -- ethernet = <&gmac0>; -- phy-mode = "rgmii-id"; -- fixed-link { -- speed = <1000>; -- full-duplex; -- }; -- }; -- -- port@1 { -- reg = <1>; -- label = "sw1"; -- }; -- -- port@2 { -- reg = <2>; -- label = "sw2"; -- }; -- -- port@3 { -- reg = <3>; -- label = "sw3"; -- }; -- -- port@4 { -- reg = <4>; -- label = "sw4"; -- }; -- -- port@5 { -- reg = <5>; -- label = "sw5"; -- }; -- }; -- }; -- }; -- - mdio1: mdio-1 { - status = "okay"; - compatible = "virtual,mdio-gpio"; -@@ -216,6 +149,68 @@ - }; - }; - -+&mdio0 { -+ status = "okay"; -+ -+ pinctrl-0 = <&mdio0_pins>; -+ pinctrl-names = "default"; -+ -+ switch0: switch@10 { -+ compatible = "qca,qca8337"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dsa,member = <0 0>; -+ -+ pinctrl-0 = <&sw0_reset_pin>; -+ pinctrl-names = "default"; -+ -+ reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; -+ reg = <0x10>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ switch0cpu: port@0 { -+ reg = <0>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ phy-mode = "rgmii-id"; -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "sw1"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "sw2"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "sw3"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "sw4"; -+ }; -+ -+ port@5 { -+ reg = <5>; -+ label = "sw5"; -+ }; -+ }; -+ }; -+}; -+ - &gmac0 { - status = "okay"; - diff --git a/target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch b/target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch deleted file mode 100644 index 8a25b17a19..0000000000 --- a/target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch +++ /dev/null @@ -1,51 +0,0 @@ -From a206d4061f1cc2c5cd17ee45c53a0ba711e48e6d Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 16:42:52 +0100 -Subject: [PATCH 3/3] drivers: cpufreq: qcom-cpufreq-nvmem: support specific - cpufreq driver - -Add support for specific cpufreq driver for qcom-cpufreq-nvmem driver. - -Signed-off-by: Ansuel Smith ---- - drivers/cpufreq/qcom-cpufreq-nvmem.c | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/drivers/cpufreq/qcom-cpufreq-nvmem.c -+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c -@@ -52,6 +52,7 @@ struct qcom_cpufreq_match_data { - char **pvs_name, - struct qcom_cpufreq_drv *drv); - const char **genpd_names; -+ const char *cpufreq_driver; - }; - - struct qcom_cpufreq_drv { -@@ -253,6 +254,7 @@ static const struct qcom_cpufreq_match_d - - static const struct qcom_cpufreq_match_data match_data_krait = { - .get_version = qcom_cpufreq_krait_name_version, -+ .cpufreq_driver = "krait-cpufreq", - }; - - static const char *qcs404_genpd_names[] = { "cpr", NULL }; -@@ -389,6 +391,19 @@ static int qcom_cpufreq_probe(struct pla - } - } - -+ if (drv->data->cpufreq_driver) { -+ cpufreq_dt_pdev = platform_device_register_simple( -+ drv->data->cpufreq_driver, -1, NULL, 0); -+ if (!IS_ERR(cpufreq_dt_pdev)) { -+ platform_set_drvdata(pdev, drv); -+ return 0; -+ } else { -+ dev_err(cpu_dev, -+ "Failed to register dedicated %s cpufreq\n", -+ drv->data->cpufreq_driver); -+ } -+ } -+ - cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1, - NULL, 0); - if (!IS_ERR(cpufreq_dt_pdev)) { diff --git a/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch b/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch deleted file mode 100644 index 3b4900fafb..0000000000 --- a/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 16:52:56 +0100 -Subject: [PATCH 1/4] ipq806x: gcc: add missing clk flag - -Some flag are missing from the original code. -These clk can't be set using the protected-clock proprities as they -cause the malfunction of the serial interface. -These clks are needed for the rpm interface to work proprely or the -cpu regulators starts to fail as soon as they are disabled by the -kernel. - -Signed-off-by: Ansuel Smith ---- - drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------ - 1 file changed, 13 insertions(+), 6 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -65,6 +65,7 @@ static struct clk_pll pll3 = { - .parent_names = (const char *[]){ "pxo" }, - .num_parents = 1, - .ops = &clk_pll_ops, -+ .flags = CLK_IS_CRITICAL, - }, - }; - -@@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk = - .parent_names = (const char *[]){ "gsbi4_qup_src" }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -- .flags = CLK_SET_PARENT_GATE, -+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk = - .parent_names = (const char *[]){ "gsbi7_qup_src" }, - .num_parents = 1, - .ops = &clk_branch_ops, -- .flags = CLK_SET_RATE_PARENT, -+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gsbi4_h_clk", - .ops = &clk_branch_ops, -+ .flags = CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -+ .flags = CLK_SET_RATE_GATE, - }, - } - }; -@@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, -- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | -+ CLK_IGNORE_UNUSED, - }, - }, - }; -@@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, - .ops = &clk_dyn_rcg_ops, -- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | -+ CLK_IGNORE_UNUSED, - }, - }, - }; diff --git a/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch b/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch deleted file mode 100644 index cd2cb33356..0000000000 --- a/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 3a5f1793c0bf4a6b536751886b0a44589fe05f35 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 17:00:07 +0100 -Subject: [PATCH 2/4] ipq806x: lcc: add missing reset - -Add missing reset for ipq806x lcc clk - -Signed-off-by: Ansuel Smith ---- - drivers/clk/qcom/lcc-ipq806x.c | 8 ++++++++ - include/dt-bindings/clock/qcom,lcc-ipq806x.h | 1 + - 2 files changed, 9 insertions(+) - ---- a/drivers/clk/qcom/lcc-ipq806x.c -+++ b/drivers/clk/qcom/lcc-ipq806x.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - #include - -@@ -22,6 +23,7 @@ - #include "clk-branch.h" - #include "clk-regmap-divider.h" - #include "clk-regmap-mux.h" -+#include "reset.h" - - static struct clk_pll pll4 = { - .l_reg = 0x4, -@@ -39,6 +41,10 @@ static struct clk_pll pll4 = { - }, - }; - -+static const struct qcom_reset_map lcc_ipq806x_resets[] = { -+ [LCC_PCM_RESET] = { 0x54, 13 }, -+}; -+ - static const struct pll_config pll4_config = { - .l = 0xf, - .m = 0x91, -@@ -417,6 +423,8 @@ static const struct qcom_cc_desc lcc_ipq - .config = &lcc_ipq806x_regmap_config, - .clks = lcc_ipq806x_clks, - .num_clks = ARRAY_SIZE(lcc_ipq806x_clks), -+ .resets = lcc_ipq806x_resets, -+ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets), - }; - - static const struct of_device_id lcc_ipq806x_match_table[] = { ---- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h -@@ -19,4 +19,5 @@ - #define SPDIF_CLK 10 - #define AHBIX_CLK 11 - -+#define LCC_PCM_RESET 0 - #endif diff --git a/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch b/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch deleted file mode 100644 index 78068f359c..0000000000 --- a/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch +++ /dev/null @@ -1,57 +0,0 @@ -From f8fdbecdaca97f0f2eebd77256e2eca4a8da6c39 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 17:08:16 +0100 -Subject: [PATCH 3/4] clk: qcom: krait: add missing enable disable - -Add missing enable disable mux function. Add extra check to -div2_round_rate. - -Signed-off-by: Ansuel Smith ---- - drivers/clk/qcom/clk-krait.c | 27 +++++++++++++++++++++++++-- - 1 file changed, 25 insertions(+), 2 deletions(-) - ---- a/drivers/clk/qcom/clk-krait.c -+++ b/drivers/clk/qcom/clk-krait.c -@@ -73,7 +73,25 @@ static u8 krait_mux_get_parent(struct cl - return clk_mux_val_to_index(hw, mux->parent_map, 0, sel); - } - -+static int krait_mux_enable(struct clk_hw *hw) -+{ -+ struct krait_mux_clk *mux = to_krait_mux_clk(hw); -+ -+ __krait_mux_set_sel(mux, mux->en_mask); -+ -+ return 0; -+} -+ -+static void krait_mux_disable(struct clk_hw *hw) -+{ -+ struct krait_mux_clk *mux = to_krait_mux_clk(hw); -+ -+ __krait_mux_set_sel(mux, mux->safe_sel); -+} -+ - const struct clk_ops krait_mux_clk_ops = { -+ .enable = krait_mux_enable, -+ .disable = krait_mux_disable, - .set_parent = krait_mux_set_parent, - .get_parent = krait_mux_get_parent, - .determine_rate = __clk_mux_determine_rate_closest, -@@ -84,8 +102,13 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops); - static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) - { -- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2); -- return DIV_ROUND_UP(*parent_rate, 2); -+ struct clk_hw *hw_parent = clk_hw_get_parent(hw); -+ -+ if (hw_parent) { -+ *parent_rate = clk_hw_round_rate(hw_parent, rate * 2); -+ return DIV_ROUND_UP(*parent_rate, 2); -+ } else -+ return -1; - } - - static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch b/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch deleted file mode 100644 index d1e047cabf..0000000000 --- a/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch +++ /dev/null @@ -1,372 +0,0 @@ -From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sun, 7 Feb 2021 17:23:38 +0100 -Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine - -Add missing clk and reset needed for nss additional core and crypto -engine. - -Signed-off-by: Ansuel Smith ---- - drivers/clk/qcom/gcc-ipq806x.c | 250 +++++++++++++++++++ - include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +- - include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 + - 3 files changed, 259 insertions(+), 1 deletion(-) - ---- a/drivers/clk/qcom/gcc-ipq806x.c -+++ b/drivers/clk/qcom/gcc-ipq806x.c -@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = { - - static struct pll_freq_tbl pll18_freq_tbl[] = { - NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), -+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), - NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), -+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), - }; - - static struct clk_pll pll18 = { -@@ -245,6 +247,22 @@ static struct clk_pll pll18 = { - }, - }; - -+static struct clk_pll pll11 = { -+ .l_reg = 0x3184, -+ .m_reg = 0x3188, -+ .n_reg = 0x318c, -+ .config_reg = 0x3194, -+ .mode_reg = 0x3180, -+ .status_reg = 0x3198, -+ .status_bit = 16, -+ .clkr.hw.init = &(struct clk_init_data){ -+ .name = "pll11", -+ .parent_names = (const char *[]){ "pxo" }, -+ .num_parents = 1, -+ .ops = &clk_pll_ops, -+ }, -+}; -+ - enum { - P_PXO, - P_PLL8, -@@ -253,6 +271,7 @@ enum { - P_CXO, - P_PLL14, - P_PLL18, -+ P_PLL11, - }; - - static const struct parent_map gcc_pxo_pll8_map[] = { -@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p - "pll18", - }; - -+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { -+ { P_PXO, 0 }, -+ { P_PLL8, 4 }, -+ { P_PLL0, 2 }, -+ { P_PLL14, 5 }, -+ { P_PLL18, 1 }, -+ { P_PLL11, 3 }, -+}; -+ -+static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { -+ "pxo", -+ "pll8_vote", -+ "pll0_vote", -+ "pll14", -+ "pll18", -+ "pll11" -+}; -+ -+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { -+ { P_PXO, 0 }, -+ { P_PLL3, 6 }, -+ { P_PLL0, 2 }, -+ { P_PLL14, 5 }, -+ { P_PLL18, 1 }, -+ { P_PLL11, 3 }, -+}; -+ -+static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { -+ "pxo", -+ "pll3", -+ "pll0_vote", -+ "pll14", -+ "pll18", -+ "pll11" -+}; -+ - static struct freq_tbl clk_tbl_gsbi_uart[] = { - { 1843200, P_PLL8, 2, 6, 625 }, - { 3686400, P_PLL8, 2, 12, 625 }, -@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc - { 20210000, P_PLL8, 1, 1, 19 }, - { 24000000, P_PLL8, 4, 1, 4 }, - { 48000000, P_PLL8, 4, 1, 2 }, -+ { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */ - { 64000000, P_PLL8, 3, 1, 2 }, - { 96000000, P_PLL8, 4, 0, 0 }, - { 192000000, P_PLL8, 2, 0, 0 }, -@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss - { 110000000, P_PLL18, 1, 1, 5 }, - { 275000000, P_PLL18, 2, 0, 0 }, - { 550000000, P_PLL18, 1, 0, 0 }, -+ { 600000000, P_PLL18, 1, 0, 0 }, - { 733000000, P_PLL18, 1, 0, 0 }, -+ { 800000000, P_PLL18, 1, 0, 0 }, - { } - }; - -@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr - }, - }; - -+static const struct freq_tbl clk_tbl_ce5_core[] = { -+ { 150000000, P_PLL3, 8, 1, 1 }, -+ { 213200000, P_PLL11, 5, 1, 1 }, -+ { } -+}; -+ -+static struct clk_dyn_rcg ce5_core_src = { -+ .ns_reg[0] = 0x36C4, -+ .ns_reg[1] = 0x36C8, -+ .bank_reg = 0x36C0, -+ .s[0] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, -+ }, -+ .s[1] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, -+ }, -+ .p[0] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .p[1] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .mux_sel_bit = 0, -+ .freq_tbl = clk_tbl_ce5_core, -+ .clkr = { -+ .enable_reg = 0x36C0, -+ .enable_mask = BIT(1), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_core_src", -+ .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11, -+ .num_parents = 6, -+ .ops = &clk_dyn_rcg_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch ce5_core_clk = { -+ .halt_reg = 0x2FDC, -+ .halt_bit = 5, -+ .hwcg_reg = 0x36CC, -+ .hwcg_bit = 6, -+ .clkr = { -+ .enable_reg = 0x36CC, -+ .enable_mask = BIT(4), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_core_clk", -+ .parent_names = (const char *[]){ -+ "ce5_core_src", -+ }, -+ .num_parents = 1, -+ .ops = &clk_branch_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+ }, -+}; -+ -+static const struct freq_tbl clk_tbl_ce5_a_clk[] = { -+ { 160000000, P_PLL0, 5, 1, 1 }, -+ { 213200000, P_PLL11, 5, 1, 1 }, -+ { } -+}; -+ -+static struct clk_dyn_rcg ce5_a_clk_src = { -+ .ns_reg[0] = 0x3d84, -+ .ns_reg[1] = 0x3d88, -+ .bank_reg = 0x3d80, -+ .s[0] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .s[1] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .p[0] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .p[1] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .mux_sel_bit = 0, -+ .freq_tbl = clk_tbl_ce5_a_clk, -+ .clkr = { -+ .enable_reg = 0x3d80, -+ .enable_mask = BIT(1), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_a_clk_src", -+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = 6, -+ .ops = &clk_dyn_rcg_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch ce5_a_clk = { -+ .halt_reg = 0x3c20, -+ .halt_bit = 12, -+ .hwcg_reg = 0x3d8c, -+ .hwcg_bit = 6, -+ .clkr = { -+ .enable_reg = 0x3d8c, -+ .enable_mask = BIT(4), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_a_clk", -+ .parent_names = (const char *[]){ -+ "ce5_a_clk_src", -+ }, -+ .num_parents = 1, -+ .ops = &clk_branch_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+ }, -+}; -+ -+static const struct freq_tbl clk_tbl_ce5_h_clk[] = { -+ { 160000000, P_PLL0, 5, 1, 1 }, -+ { 213200000, P_PLL11, 5, 1, 1 }, -+ { } -+}; -+ -+static struct clk_dyn_rcg ce5_h_clk_src = { -+ .ns_reg[0] = 0x3c64, -+ .ns_reg[1] = 0x3c68, -+ .bank_reg = 0x3c60, -+ .s[0] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .s[1] = { -+ .src_sel_shift = 0, -+ .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, -+ }, -+ .p[0] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .p[1] = { -+ .pre_div_shift = 3, -+ .pre_div_width = 4, -+ }, -+ .mux_sel_bit = 0, -+ .freq_tbl = clk_tbl_ce5_h_clk, -+ .clkr = { -+ .enable_reg = 0x3c60, -+ .enable_mask = BIT(1), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_h_clk_src", -+ .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11, -+ .num_parents = 6, -+ .ops = &clk_dyn_rcg_ops, -+ }, -+ }, -+}; -+ -+static struct clk_branch ce5_h_clk = { -+ .halt_reg = 0x3c20, -+ .halt_bit = 11, -+ .hwcg_reg = 0x3c6c, -+ .hwcg_bit = 6, -+ .clkr = { -+ .enable_reg = 0x3c6c, -+ .enable_mask = BIT(4), -+ .hw.init = &(struct clk_init_data){ -+ .name = "ce5_h_clk", -+ .parent_names = (const char *[]){ -+ "ce5_h_clk_src", -+ }, -+ .num_parents = 1, -+ .ops = &clk_branch_ops, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+ }, -+}; -+ - static struct clk_regmap *gcc_ipq806x_clks[] = { - [PLL0] = &pll0.clkr, - [PLL0_VOTE] = &pll0_vote, -@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl - [PLL4_VOTE] = &pll4_vote, - [PLL8] = &pll8.clkr, - [PLL8_VOTE] = &pll8_vote, -+ [PLL11] = &pll11.clkr, - [PLL14] = &pll14.clkr, - [PLL14_VOTE] = &pll14_vote, - [PLL18] = &pll18.clkr, -@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl - [PLL9] = &hfpll0.clkr, - [PLL10] = &hfpll1.clkr, - [PLL12] = &hfpll_l2.clkr, -+ [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr, -+ [CE5_A_CLK] = &ce5_a_clk.clkr, -+ [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr, -+ [CE5_H_CLK] = &ce5_h_clk.clkr, -+ [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr, -+ [CE5_CORE_CLK] = &ce5_core_clk.clkr, - }; - - static const struct qcom_reset_map gcc_ipq806x_resets[] = { -@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i - [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, - [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, - [GMAC_AHB_RESET] = { 0x3e24, 0 }, -+ [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, -+ [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, -+ [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, -+ [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, -+ [CRYPTO_AHB_RESET] = { 0x3e10, 0}, - [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, - [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, - [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, ---- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h -@@ -240,7 +240,7 @@ - #define PLL14 232 - #define PLL14_VOTE 233 - #define PLL18 234 --#define CE5_SRC 235 -+#define CE5_A_CLK 235 - #define CE5_H_CLK 236 - #define CE5_CORE_CLK 237 - #define CE3_SLEEP_CLK 238 -@@ -283,5 +283,8 @@ - #define EBI2_AON_CLK 281 - #define NSSTCM_CLK_SRC 282 - #define NSSTCM_CLK 283 -+#define CE5_A_CLK_SRC 285 -+#define CE5_H_CLK_SRC 286 -+#define CE5_CORE_CLK_SRC 287 - - #endif ---- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h -+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h -@@ -163,5 +163,10 @@ - #define NSS_CAL_PRBS_RST_N_RESET 154 - #define NSS_LCKDT_RST_N_RESET 155 - #define NSS_SRDS_N_RESET 156 -+#define CRYPTO_ENG1_RESET 157 -+#define CRYPTO_ENG2_RESET 158 -+#define CRYPTO_ENG3_RESET 159 -+#define CRYPTO_ENG4_RESET 160 -+#define CRYPTO_AHB_RESET 161 - - #endif diff --git a/target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch b/target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch deleted file mode 100644 index d3677253f6..0000000000 --- a/target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch +++ /dev/null @@ -1,687 +0,0 @@ -From cc41a266280cad0b55319e614167c88dff344248 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 22 Feb 2020 16:33:10 +0100 -Subject: [PATCH 1/8] cpufreq: add Krait dedicated scaling driver - -This new driver is based on generic cpufreq-dt driver. -Krait SoCs have 2-4 cpu and one shared L2 cache that can -operate at different frequency based on the maximum cpu clk -across all core. -L2 frequency and voltage are scaled on every frequency change -if needed. On Krait SoCs is present a bug that can cause -transition problem between frequency bin, to workaround this -on more than one transition, the L2 frequency is first set to the -base rate and then to the target rate. -The L2 frequency use the OPP framework and use the opp-level -bindings to link the l2 freq to different cpu freq. This is needed -as the Krait l2 clk are note mapped 1:1 to the core clks and some -of the l2 clk is set based on a range of the cpu clks. If the driver -find a broken config (for example no opp-level set) the l2 scaling is -skipped. - -Signed-off-by: Ansuel Smith ---- - drivers/cpufreq/Kconfig.arm | 14 +- - drivers/cpufreq/Makefile | 2 + - drivers/cpufreq/qcom-cpufreq-krait.c | 589 +++++++++++++++++++++++++++ - 3 files changed, 604 insertions(+), 1 deletion(-) - create mode 100644 drivers/cpufreq/qcom-cpufreq-krait.c - ---- a/drivers/cpufreq/Kconfig.arm -+++ b/drivers/cpufreq/Kconfig.arm -@@ -150,6 +150,18 @@ config ARM_QCOM_CPUFREQ_HW - The driver implements the cpufreq interface for this HW engine. - Say Y if you want to support CPUFreq HW. - -+config ARM_QCOM_CPUFREQ_KRAIT -+ tristate "CPU Frequency scaling support for Krait SoCs" -+ depends on ARCH_QCOM || COMPILE_TEST -+ select PM_OPP -+ select ARM_QCOM_CPUFREQ_NVMEM -+ help -+ This adds the CPUFreq driver for Qualcomm Krait SoC based boards. -+ This scale the cache clk and regulator based on the different cpu -+ clks when scaling the different cores clk. -+ -+ If in doubt, say N. -+ - config ARM_RASPBERRYPI_CPUFREQ - tristate "Raspberry Pi cpufreq support" - depends on CLK_RASPBERRYPI || COMPILE_TEST -@@ -339,4 +351,4 @@ config ARM_PXA2xx_CPUFREQ - help - This add the CPUFreq driver support for Intel PXA2xx SOCs. - -- If in doubt, say N. -+ If in doubt, say N. -\ No newline at end of file ---- a/drivers/cpufreq/Makefile -+++ b/drivers/cpufreq/Makefile -@@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2 - obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o - obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o - obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o -+obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRAIT) += qcom-cpufreq-krait.o - obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o - obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o - obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o -@@ -86,6 +87,7 @@ obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += te - obj-$(CONFIG_ARM_TEGRA194_CPUFREQ) += tegra194-cpufreq.o - obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o - obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o -+obj-$(CONFIG_ARM_KRAIT_CPUFREQ) += krait-cpufreq.o - - - ################################################################################## ---- /dev/null -+++ b/drivers/cpufreq/qcom-cpufreq-krait.c -@@ -0,0 +1,609 @@ -+// SPDX-License-Identifier: GPL-2.0 -+ -+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "cpufreq-dt.h" -+ -+static struct platform_device *l2_pdev; -+ -+struct private_data { -+ struct opp_table *opp_table; -+ struct device *cpu_dev; -+ const char *reg_name; -+ bool have_static_opps; -+}; -+ -+static int set_target(struct cpufreq_policy *policy, unsigned int index) -+{ -+ struct private_data *priv = policy->driver_data; -+ unsigned long freq = policy->freq_table[index].frequency; -+ unsigned long target_freq = freq * 1000; -+ struct dev_pm_opp *opp; -+ unsigned int level; -+ int cpu, ret; -+ -+ if (l2_pdev) { -+ int policy_cpu = policy->cpu; -+ -+ /* find the max freq across all core */ -+ for_each_present_cpu(cpu) -+ if (cpu != policy_cpu) -+ target_freq = max( -+ target_freq, -+ (unsigned long)cpufreq_quick_get(cpu)); -+ -+ opp = dev_pm_opp_find_freq_exact(priv->cpu_dev, target_freq, -+ true); -+ if (IS_ERR(opp)) { -+ dev_err(&l2_pdev->dev, "failed to find OPP for %ld\n", -+ target_freq); -+ return PTR_ERR(opp); -+ } -+ level = dev_pm_opp_get_level(opp); -+ dev_pm_opp_put(opp); -+ -+ /* -+ * Hardware constraint: -+ * Krait CPU cannot operate at 384MHz with L2 at 1Ghz. -+ * Assume index 0 with the idle freq and level > 0 as -+ * any L2 freq > 384MHz. -+ * Skip CPU freq change in this corner case. -+ */ -+ if (unlikely(index == 0 && level != 0)) { -+ dev_err(priv->cpu_dev, "Krait CPU can't operate at idle freq with L2 at 1GHz"); -+ return -EINVAL; -+ } -+ -+ opp = dev_pm_opp_find_level_exact(&l2_pdev->dev, level); -+ if (IS_ERR(opp)) { -+ dev_err(&l2_pdev->dev, -+ "failed to find level OPP for %d\n", level); -+ return PTR_ERR(opp); -+ } -+ target_freq = dev_pm_opp_get_freq(opp); -+ dev_pm_opp_put(opp); -+ -+ ret = dev_pm_opp_set_rate(&l2_pdev->dev, target_freq); -+ if (ret) -+ return ret; -+ } -+ -+ ret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000); -+ if (ret) -+ return ret; -+ -+ arch_set_freq_scale(policy->related_cpus, freq, -+ policy->cpuinfo.max_freq); -+ -+ return 0; -+} -+ -+/* -+ * An earlier version of opp-v1 bindings used to name the regulator -+ * "cpu0-supply", we still need to handle that for backwards compatibility. -+ */ -+static const char *find_supply_name(struct device *dev) -+{ -+ struct device_node *np; -+ struct property *pp; -+ int cpu = dev->id; -+ const char *name = NULL; -+ -+ np = of_node_get(dev->of_node); -+ -+ /* This must be valid for sure */ -+ if (WARN_ON(!np)) -+ return NULL; -+ -+ /* Try "cpu0" for older DTs */ -+ if (!cpu) { -+ pp = of_find_property(np, "cpu0-supply", NULL); -+ if (pp) { -+ name = "cpu0"; -+ goto node_put; -+ } -+ } -+ -+ pp = of_find_property(np, "cpu-supply", NULL); -+ if (pp) { -+ name = "cpu"; -+ goto node_put; -+ } -+ -+ dev_dbg(dev, "no regulator for cpu%d\n", cpu); -+node_put: -+ of_node_put(np); -+ return name; -+} -+ -+static int resources_available(void) -+{ -+ struct device *cpu_dev; -+ struct regulator *cpu_reg; -+ struct clk *cpu_clk; -+ int ret = 0; -+ const char *name; -+ -+ cpu_dev = get_cpu_device(0); -+ if (!cpu_dev) { -+ pr_err("failed to get cpu0 device\n"); -+ return -ENODEV; -+ } -+ -+ cpu_clk = clk_get(cpu_dev, NULL); -+ ret = PTR_ERR_OR_ZERO(cpu_clk); -+ if (ret) { -+ /* -+ * If cpu's clk node is present, but clock is not yet -+ * registered, we should try defering probe. -+ */ -+ if (ret == -EPROBE_DEFER) -+ dev_dbg(cpu_dev, "clock not ready, retry\n"); -+ else -+ dev_err(cpu_dev, "failed to get clock: %d\n", ret); -+ -+ return ret; -+ } -+ -+ clk_put(cpu_clk); -+ -+ name = find_supply_name(cpu_dev); -+ /* Platform doesn't require regulator */ -+ if (!name) -+ return 0; -+ -+ cpu_reg = regulator_get_optional(cpu_dev, name); -+ ret = PTR_ERR_OR_ZERO(cpu_reg); -+ if (ret) { -+ /* -+ * If cpu's regulator supply node is present, but regulator is -+ * not yet registered, we should try defering probe. -+ */ -+ if (ret == -EPROBE_DEFER) -+ dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n"); -+ else -+ dev_dbg(cpu_dev, "no regulator for cpu0: %d\n", ret); -+ -+ return ret; -+ } -+ -+ regulator_put(cpu_reg); -+ return 0; -+} -+ -+static int cpufreq_init(struct cpufreq_policy *policy) -+{ -+ struct cpufreq_frequency_table *freq_table; -+ struct opp_table *opp_table = NULL; -+ unsigned int transition_latency; -+ struct private_data *priv; -+ struct device *cpu_dev; -+ bool fallback = false; -+ struct clk *cpu_clk; -+ const char *name; -+ int ret; -+ -+ cpu_dev = get_cpu_device(policy->cpu); -+ if (!cpu_dev) { -+ pr_err("failed to get cpu%d device\n", policy->cpu); -+ return -ENODEV; -+ } -+ -+ cpu_clk = clk_get(cpu_dev, NULL); -+ if (IS_ERR(cpu_clk)) { -+ ret = PTR_ERR(cpu_clk); -+ dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret); -+ return ret; -+ } -+ -+ /* Get OPP-sharing information from "operating-points-v2" bindings */ -+ ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus); -+ if (ret) { -+ if (ret != -ENOENT) -+ goto out_put_clk; -+ -+ /* -+ * operating-points-v2 not supported, fallback to old method of -+ * finding shared-OPPs for backward compatibility if the -+ * platform hasn't set sharing CPUs. -+ */ -+ if (dev_pm_opp_get_sharing_cpus(cpu_dev, policy->cpus)) -+ fallback = true; -+ } -+ -+ /* -+ * OPP layer will be taking care of regulators now, but it needs to know -+ * the name of the regulator first. -+ */ -+ name = find_supply_name(cpu_dev); -+ if (name) { -+ opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1); -+ if (IS_ERR(opp_table)) { -+ ret = PTR_ERR(opp_table); -+ dev_err(cpu_dev, -+ "Failed to set regulator for cpu%d: %d\n", -+ policy->cpu, ret); -+ goto out_put_clk; -+ } -+ } -+ -+ priv = kzalloc(sizeof(*priv), GFP_KERNEL); -+ if (!priv) { -+ ret = -ENOMEM; -+ goto out_put_regulator; -+ } -+ -+ priv->reg_name = name; -+ priv->opp_table = opp_table; -+ -+ /* -+ * Initialize OPP tables for all policy->cpus. They will be shared by -+ * all CPUs which have marked their CPUs shared with OPP bindings. -+ * -+ * For platforms not using operating-points-v2 bindings, we do this -+ * before updating policy->cpus. Otherwise, we will end up creating -+ * duplicate OPPs for policy->cpus. -+ * -+ * OPPs might be populated at runtime, don't check for error here -+ */ -+ if (!dev_pm_opp_of_cpumask_add_table(policy->cpus)) -+ priv->have_static_opps = true; -+ -+ /* -+ * But we need OPP table to function so if it is not there let's -+ * give platform code chance to provide it for us. -+ */ -+ ret = dev_pm_opp_get_opp_count(cpu_dev); -+ if (ret <= 0) { -+ dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n"); -+ ret = -EPROBE_DEFER; -+ goto out_free_opp; -+ } -+ -+ if (fallback) { -+ cpumask_setall(policy->cpus); -+ -+ /* -+ * OPP tables are initialized only for policy->cpu, do it for -+ * others as well. -+ */ -+ ret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); -+ if (ret) -+ dev_err(cpu_dev, -+ "%s: failed to mark OPPs as shared: %d\n", -+ __func__, ret); -+ } -+ -+ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); -+ if (ret) { -+ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); -+ goto out_free_opp; -+ } -+ -+ priv->cpu_dev = cpu_dev; -+ -+ policy->driver_data = priv; -+ policy->clk = cpu_clk; -+ policy->freq_table = freq_table; -+ -+ policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000; -+ -+ transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev); -+ if (!transition_latency) -+ transition_latency = CPUFREQ_ETERNAL; -+ -+ policy->cpuinfo.transition_latency = transition_latency; -+ policy->dvfs_possible_from_any_cpu = true; -+ -+ dev_pm_opp_of_register_em(cpu_dev, policy->cpus); -+ -+ return 0; -+ -+out_free_opp: -+ if (priv->have_static_opps) -+ dev_pm_opp_of_cpumask_remove_table(policy->cpus); -+ kfree(priv); -+out_put_regulator: -+ if (name) -+ dev_pm_opp_put_regulators(opp_table); -+out_put_clk: -+ clk_put(cpu_clk); -+ -+ return ret; -+} -+ -+static int cpufreq_online(struct cpufreq_policy *policy) -+{ -+ /* We did light-weight tear down earlier, nothing to do here */ -+ return 0; -+} -+ -+static int cpufreq_offline(struct cpufreq_policy *policy) -+{ -+ /* -+ * Preserve policy->driver_data and don't free resources on light-weight -+ * tear down. -+ */ -+ return 0; -+} -+ -+static int cpufreq_exit(struct cpufreq_policy *policy) -+{ -+ struct private_data *priv = policy->driver_data; -+ -+ dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table); -+ if (priv->have_static_opps) -+ dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); -+ if (priv->reg_name) -+ dev_pm_opp_put_regulators(priv->opp_table); -+ -+ clk_put(policy->clk); -+ kfree(priv); -+ -+ return 0; -+} -+ -+static struct freq_attr *krait_cpufreq_attr[] = { -+ &cpufreq_freq_attr_scaling_available_freqs, -+ NULL, -+}; -+ -+static struct cpufreq_driver krait_cpufreq_driver = { -+ .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | -+ CPUFREQ_IS_COOLING_DEV, -+ .verify = cpufreq_generic_frequency_table_verify, -+ .target_index = set_target, -+ .get = cpufreq_generic_get, -+ .init = cpufreq_init, -+ .exit = cpufreq_exit, -+ .online = cpufreq_online, -+ .offline = cpufreq_offline, -+ .name = "krait-cpufreq", -+ .attr = krait_cpufreq_attr, -+ .suspend = cpufreq_generic_suspend, -+}; -+ -+struct krait_data { -+ unsigned long idle_freq; -+ bool regulator_enabled; -+}; -+ -+static int krait_cache_set_opp(struct dev_pm_set_opp_data *data) -+{ -+ unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate; -+ struct dev_pm_opp_supply *supply = &data->new_opp.supplies[0]; -+ struct regulator *reg = data->regulators[0]; -+ struct clk *clk = data->clk; -+ struct krait_data *kdata; -+ unsigned long idle_freq; -+ int ret; -+ -+ kdata = (struct krait_data *)dev_get_drvdata(data->dev); -+ idle_freq = kdata->idle_freq; -+ -+ /* Scaling up? Scale voltage before frequency */ -+ if (freq >= old_freq) { -+ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, -+ supply->u_volt, -+ supply->u_volt_max); -+ if (ret) -+ goto exit; -+ } -+ -+ /* -+ * Set to idle bin if switching from normal to high bin -+ * or vice versa. It has been notice that a bug is triggered -+ * in cache scaling when more than one bin is scaled, to fix -+ * this we first need to transition to the base rate and then -+ * to target rate -+ */ -+ if (likely(freq != idle_freq && old_freq != idle_freq)) { -+ ret = clk_set_rate(clk, idle_freq); -+ if (ret) -+ goto exit; -+ } -+ -+ ret = clk_set_rate(clk, freq); -+ if (ret) -+ goto exit; -+ -+ /* Scaling down? Scale voltage after frequency */ -+ if (freq < old_freq) { -+ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, -+ supply->u_volt, -+ supply->u_volt_max); -+ } -+ -+ if (unlikely(!kdata->regulator_enabled)) { -+ ret = regulator_enable(reg); -+ if (ret < 0) -+ dev_warn(data->dev, "Failed to enable regulator: %d", ret); -+ else -+ kdata->regulator_enabled = true; -+ } -+ -+exit: -+ return ret; -+}; -+ -+static int krait_cache_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct krait_data *data; -+ struct opp_table *table; -+ struct dev_pm_opp *opp; -+ struct device *cpu_dev; -+ int ret; -+ -+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); -+ if (!data) -+ return -ENOMEM; -+ -+ table = dev_pm_opp_set_regulators(dev, (const char *[]){ "l2" }, 1); -+ if (IS_ERR(table)) { -+ ret = PTR_ERR(table); -+ if (ret != -EPROBE_DEFER) -+ dev_err(dev, "failed to set regulators %d\n", ret); -+ -+ return ret; -+ } -+ -+ ret = PTR_ERR_OR_ZERO( -+ dev_pm_opp_register_set_opp_helper(dev, krait_cache_set_opp)); -+ if (ret) -+ return ret; -+ -+ ret = dev_pm_opp_of_add_table(dev); -+ if (ret) { -+ dev_err(dev, "failed to parse L2 freq thresholds\n"); -+ return ret; -+ } -+ -+ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq); -+ dev_pm_opp_put(opp); -+ -+ /* -+ * Check opp-level configuration -+ * At least 2 level must be set or the cache will always be scaled -+ * the idle freq causing some performance problem -+ * -+ * In case of invalid configuration, the l2 scaling is skipped -+ */ -+ cpu_dev = get_cpu_device(0); -+ if (!cpu_dev) { -+ pr_err("failed to get cpu0 device\n"); -+ return -ENODEV; -+ } -+ -+ /* -+ * Check if we have at least opp-level 1, 0 should always be set to -+ * the idle freq -+ */ -+ opp = dev_pm_opp_find_level_exact(dev, 1); -+ if (IS_ERR(opp)) { -+ dev_err(dev, -+ "Invalid configuration found of l2 opp. Can't find opp-level 1"); -+ goto invalid_conf; -+ } -+ dev_pm_opp_put(opp); -+ -+ /* -+ * Check if we have at least opp-level 1 in the cpu opp, 0 should always -+ * be set to the idle freq -+ */ -+ opp = dev_pm_opp_find_level_exact(cpu_dev, 1); -+ if (IS_ERR(opp)) { -+ dev_err(dev, -+ "Invalid configuration found of cpu opp. Can't find opp-level 1"); -+ goto invalid_conf; -+ } -+ dev_pm_opp_put(opp); -+ -+ platform_set_drvdata(pdev, data); -+ -+ /* The l2 scaling is enabled by linking the cpufreq driver */ -+ l2_pdev = pdev; -+ -+ return 0; -+ -+invalid_conf: -+ dev_pm_opp_remove_table(dev); -+ dev_pm_opp_put_regulators(table); -+ dev_pm_opp_unregister_set_opp_helper(table); -+ -+ return -EINVAL; -+}; -+ -+static int krait_cache_remove(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct opp_table *table = dev_pm_opp_get_opp_table(dev); -+ -+ dev_pm_opp_remove_table(dev); -+ dev_pm_opp_put_regulators(table); -+ dev_pm_opp_unregister_set_opp_helper(table); -+ -+ return 0; -+}; -+ -+static const struct of_device_id krait_cache_match_table[] = { -+ { .compatible = "qcom,krait-cache" }, -+ {} -+}; -+ -+static struct platform_driver krait_cache_driver = { -+ .driver = { -+ .name = "krait-cache", -+ .of_match_table = krait_cache_match_table, -+ }, -+ .probe = krait_cache_probe, -+ .remove = krait_cache_remove, -+}; -+module_platform_driver(krait_cache_driver); -+ -+static int krait_cpufreq_probe(struct platform_device *pdev) -+{ -+ struct cpufreq_dt_platform_data *data = dev_get_platdata(&pdev->dev); -+ int ret; -+ -+ /* -+ * All per-cluster (CPUs sharing clock/voltages) initialization is done -+ * from ->init(). In probe(), we just need to make sure that clk and -+ * regulators are available. Else defer probe and retry. -+ * -+ * FIXME: Is checking this only for CPU0 sufficient ? -+ */ -+ ret = resources_available(); -+ if (ret) -+ return ret; -+ -+ if (data) { -+ if (data->have_governor_per_policy) -+ krait_cpufreq_driver.flags |= -+ CPUFREQ_HAVE_GOVERNOR_PER_POLICY; -+ -+ krait_cpufreq_driver.resume = data->resume; -+ if (data->suspend) -+ krait_cpufreq_driver.suspend = data->suspend; -+ } -+ -+ ret = cpufreq_register_driver(&krait_cpufreq_driver); -+ if (ret) -+ dev_err(&pdev->dev, "failed register driver: %d\n", ret); -+ -+ return ret; -+} -+ -+static int krait_cpufreq_remove(struct platform_device *pdev) -+{ -+ cpufreq_unregister_driver(&krait_cpufreq_driver); -+ return 0; -+} -+ -+static struct platform_driver krait_cpufreq_platdrv = { -+ .driver = { -+ .name = "krait-cpufreq", -+ }, -+ .probe = krait_cpufreq_probe, -+ .remove = krait_cpufreq_remove, -+}; -+module_platform_driver(krait_cpufreq_platdrv); -+ -+MODULE_ALIAS("platform:krait-cpufreq"); -+MODULE_AUTHOR("Ansuel Smith "); -+MODULE_DESCRIPTION("Dedicated Krait SoC cpufreq driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/ipq806x/patches-5.10/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch b/target/linux/ipq806x/patches-5.10/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch deleted file mode 100644 index 316e18b790..0000000000 --- a/target/linux/ipq806x/patches-5.10/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch +++ /dev/null @@ -1,237 +0,0 @@ -From c9ecd920324a647bf1f2b47f771c8f599cc7b551 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 22 Feb 2020 18:02:17 +0100 -Subject: [PATCH 2/8] Documentation: cpufreq: add qcom,krait-cache bindings - -Document dedicated cpufreq for Krait CPUs. - -Signed-off-by: Ansuel Smith ---- - .../bindings/cpufreq/qcom-cpufreq-krait.yaml | 221 ++++++++++++++++++ - 1 file changed, 221 insertions(+) - create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml -@@ -0,0 +1,221 @@ -+# SPDX-License-Identifier: GPL-2.0 -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-krait.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: CPU Frequency scaling driver for Krait SoCs -+ -+maintainers: -+ - Ansuel Smith -+ -+description: | -+ The krait cpufreq driver is a dedicated frequency scaling driver -+ based on cpufreq-dt generic driver that scale L2 cache and the -+ cores. TEST -+ -+ The L2 cache is scaled based on the max clk across all cores and -+ the clock is decided based on the opp-level set in the device tree. -+ -+ Different core freq can be linked to a specific l2 freq and the driver -+ on frequency change will scale the core and the l2 clk based of the -+ linked freq. -+ -+ On Krait SoC is present a bug and on every L2 clk change the driver -+ needs to set the clk to the idle freq before changing it to the new value. -+ -+ This requires the qcom cpufreq nvmem driver to parse the different opp -+ core clk and an additional opp table for the l2 scaling. -+ -+ If the driver detect broken config (for example missing opp-level) the -+ cpufreq driver skips the l2 scaling -+ -+ Referring to this example opp-level can be used to link a range of cpu freq -+ to a specific l2 freq: -+ cpu opp freq 384000000 has opp-level 0 -+ l2 opp freq 384000000 has opp-level 0 -+ The driver will scale l2 to 384000000 -+ -+ cpu opp freq 600000000-1000000000 has opp-level 1 -+ l2 opp freq 1000000000 has opp-level 1 -+ The driver will scale l2 to 1000000000 -+ -+allOf: -+ - $ref: /schemas/cache-controller.yaml# -+ -+select: -+ properties: -+ compatible: -+ items: -+ - enum: -+ - qcom,krait-cache -+ -+ required: -+ - compatible -+ -+properties: -+ compatible: -+ items: -+ - const: qcom,krait-cache -+ - const: cache -+ -+ cache-level: -+ const: 2 -+ -+ clocks: -+ maxItems: 1 -+ -+ clock-names: -+ const: l2 -+ -+ l2-supply: true -+ -+ operating-points-v2: true -+ -+required: -+ - compatible -+ - cache-level -+ - clocks -+ - clock-names -+ - l2-supply -+ - operating-points-v2 -+ -+additionalProperties: false -+ -+examples: -+ - | -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ compatible = "qcom,krait"; -+ enable-method = "qcom,kpss-acc-v1"; -+ device_type = "cpu"; -+ reg = <0>; -+ next-level-cache = <&L2>; -+ qcom,acc = <&acc0>; -+ qcom,saw = <&saw0>; -+ clocks = <&kraitcc 0>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ cpu-supply = <&smb208_s2a>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; -+ }; -+ -+ /* ... */ -+ -+ }; -+ -+ opp_table0: opp_table0 { -+ compatible = "operating-points-v2-kryo-cpu"; -+ nvmem-cells = <&speedbin_efuse>; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1000000>; -+ opp-microvolt-speed0-pvs1-v0 = <925000>; -+ opp-microvolt-speed0-pvs2-v0 = <875000>; -+ opp-microvolt-speed0-pvs3-v0 = <800000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1050000>; -+ opp-microvolt-speed0-pvs1-v0 = <975000>; -+ opp-microvolt-speed0-pvs2-v0 = <925000>; -+ opp-microvolt-speed0-pvs3-v0 = <850000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1100000>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000>; -+ opp-microvolt-speed0-pvs2-v0 = <995000>; -+ opp-microvolt-speed0-pvs3-v0 = <900000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1150000>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000>; -+ opp-microvolt-speed0-pvs2-v0 = <1025000>; -+ opp-microvolt-speed0-pvs3-v0 = <950000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1200000>; -+ opp-microvolt-speed0-pvs1-v0 = <1125000>; -+ opp-microvolt-speed0-pvs2-v0 = <1075000>; -+ opp-microvolt-speed0-pvs3-v0 = <1000000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1250000>; -+ opp-microvolt-speed0-pvs1-v0 = <1175000>; -+ opp-microvolt-speed0-pvs2-v0 = <1125000>; -+ opp-microvolt-speed0-pvs3-v0 = <1050000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ -+ opp_table_l2: opp_table_l2 { -+ compatible = "operating-points-v2"; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1150000>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ -+ soc { -+ L2: l2-cache { -+ compatible = "qcom,krait-cache", "cache"; -+ cache-level = <2>; -+ -+ clocks = <&kraitcc 4>; -+ clock-names = "l2"; -+ l2-supply = <&smb208_s1a>; -+ operating-points-v2 = <&opp_table_l2>; -+ }; -+ }; -+ -+... diff --git a/target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch b/target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch deleted file mode 100644 index 8ce3f062cf..0000000000 --- a/target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch +++ /dev/null @@ -1,243 +0,0 @@ ---- a/drivers/clk/qcom/Makefile -+++ b/drivers/clk/qcom/Makefile -@@ -15,6 +15,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-k - clk-qcom-y += clk-hfpll.o - clk-qcom-y += reset.o - clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o -+clk-qcom-y += fab_scaling.o - - # Keep alphabetically sorted by config - obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o ---- /dev/null -+++ b/drivers/clk/qcom/fab_scaling.c -@@ -0,0 +1,172 @@ -+/* -+ * Copyright (c) 2015, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for any -+ * purpose with or without fee is hereby granted, provided that the above -+ * copyright notice and this permission notice appear in all copies. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct qcom_fab_scaling_data { -+ u32 fab_freq_high; -+ u32 fab_freq_nominal; -+ u32 cpu_freq_threshold; -+ struct clk *apps_fab_clk; -+ struct clk *ddr_fab_clk; -+}; -+ -+static struct qcom_fab_scaling_data *drv_data; -+ -+int scale_fabrics(unsigned long max_cpu_freq) -+{ -+ struct clk *apps_fab_clk = drv_data->apps_fab_clk, -+ *ddr_fab_clk = drv_data->ddr_fab_clk; -+ unsigned long target_freq, cur_freq; -+ int ret; -+ -+ /* Skip fab scaling if the driver is not ready */ -+ if (!apps_fab_clk || !ddr_fab_clk) -+ return 0; -+ -+ if (max_cpu_freq > drv_data->cpu_freq_threshold) -+ target_freq = drv_data->fab_freq_high; -+ else -+ target_freq = drv_data->fab_freq_nominal; -+ -+ cur_freq = clk_get_rate(ddr_fab_clk); -+ -+ if (target_freq != cur_freq) { -+ ret = clk_set_rate(apps_fab_clk, target_freq); -+ if (ret) -+ return ret; -+ ret = clk_set_rate(ddr_fab_clk, target_freq); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(scale_fabrics); -+ -+static int ipq806x_fab_scaling_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct clk *apps_fab_clk, *ddr_fab_clk; -+ int ret; -+ -+ if (!np) -+ return -ENODEV; -+ -+ drv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL); -+ if (!drv_data) -+ return -ENOMEM; -+ -+ if (of_property_read_u32(np, "fab_freq_high", &drv_data->fab_freq_high)) { -+ pr_err("FABRICS turbo freq not found. Using defaults...\n"); -+ drv_data->fab_freq_high = 533000000; -+ } -+ -+ if (of_property_read_u32(np, "fab_freq_nominal", &drv_data->fab_freq_nominal)) { -+ pr_err("FABRICS nominal freq not found. Using defaults...\n"); -+ drv_data->fab_freq_nominal = 400000000; -+ } -+ -+ if (of_property_read_u32(np, "cpu_freq_threshold", &drv_data->cpu_freq_threshold)) { -+ pr_err("FABRICS cpu freq threshold not found. Using defaults...\n"); -+ drv_data->cpu_freq_threshold = 1000000000; -+ } -+ -+ apps_fab_clk = devm_clk_get(&pdev->dev, "apps-fab-clk"); -+ ret = PTR_ERR_OR_ZERO(apps_fab_clk); -+ if (ret) { -+ /* -+ * If apps fab clk node is present, but clock is not yet -+ * registered, we should try defering probe. -+ */ -+ if (ret != -EPROBE_DEFER) { -+ pr_err("Failed to get APPS FABRIC clock: %d\n", ret); -+ ret = -ENODEV; -+ } -+ goto err; -+ } -+ -+ clk_prepare_enable(apps_fab_clk); -+ clk_set_rate(apps_fab_clk, drv_data->fab_freq_high); -+ drv_data->apps_fab_clk = apps_fab_clk; -+ -+ ddr_fab_clk = devm_clk_get(&pdev->dev, "ddr-fab-clk"); -+ ret = PTR_ERR_OR_ZERO(ddr_fab_clk); -+ if (ret) { -+ /* -+ * If ddr fab clk node is present, but clock is not yet -+ * registered, we should try defering probe. -+ */ -+ if (ret != -EPROBE_DEFER) { -+ pr_err("Failed to get DDR FABRIC clock: %d\n", ret); -+ ddr_fab_clk = NULL; -+ ret = -ENODEV; -+ } -+ goto err; -+ } -+ -+ clk_prepare_enable(ddr_fab_clk); -+ clk_set_rate(ddr_fab_clk, drv_data->fab_freq_high); -+ drv_data->ddr_fab_clk = ddr_fab_clk; -+ -+ return 0; -+err: -+ kfree(drv_data); -+ return ret; -+} -+ -+static int ipq806x_fab_scaling_remove(struct platform_device *pdev) -+{ -+ kfree(drv_data); -+ return 0; -+} -+ -+static const struct of_device_id fab_scaling_ipq806x_match_table[] = { -+ { .compatible = "qcom,fab-scaling" }, -+ { } -+}; -+ -+static struct platform_driver fab_scaling_ipq806x_driver = { -+ .probe = ipq806x_fab_scaling_probe, -+ .remove = ipq806x_fab_scaling_remove, -+ .driver = { -+ .name = "fab-scaling", -+ .of_match_table = fab_scaling_ipq806x_match_table, -+ }, -+}; -+ -+static int __init fab_scaling_ipq806x_init(void) -+{ -+ return platform_driver_register(&fab_scaling_ipq806x_driver); -+} -+late_initcall(fab_scaling_ipq806x_init); -+ -+static void __exit fab_scaling_ipq806x_exit(void) -+{ -+ platform_driver_unregister(&fab_scaling_ipq806x_driver); -+} -+module_exit(fab_scaling_ipq806x_exit); ---- /dev/null -+++ b/include/linux/fab_scaling.h -@@ -0,0 +1,31 @@ -+/* -+ * Copyright (c) 2015, The Linux Foundation. All rights reserved. -+ * -+ * Permission to use, copy, modify, and/or distribute this software for any -+ * purpose with or without fee is hereby granted, provided that the above -+ * copyright notice and this permission notice appear in all copies. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ */ -+ -+ -+#ifndef __FAB_SCALING_H -+#define __FAB_SCALING_H -+ -+/** -+ * scale_fabrics - Scale DDR and APPS FABRICS -+ * -+ * This function monitors all the registered clocks and does APPS -+ * and DDR FABRIC scaling based on the idle frequencies with which -+ * it was registered. -+ * -+ */ -+int scale_fabrics(unsigned long max_cpu_freq); -+ -+#endif ---- a/drivers/cpufreq/qcom-cpufreq-krait.c -+++ b/drivers/cpufreq/qcom-cpufreq-krait.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - - #include "cpufreq-dt.h" - -@@ -68,6 +69,13 @@ static int set_target(struct cpufreq_pol - return -EINVAL; - } - -+ /* -+ * Scale fabrics with max freq across all cores -+ */ -+ ret = scale_fabrics(target_freq); -+ if (ret) -+ return ret; -+ - opp = dev_pm_opp_find_level_exact(&l2_pdev->dev, level); - if (IS_ERR(opp)) { - dev_err(&l2_pdev->dev, diff --git a/target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch b/target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch deleted file mode 100644 index 37501bc64b..0000000000 --- a/target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch +++ /dev/null @@ -1,239 +0,0 @@ -From 6949d651e3be3ebbfedb6bbd5b541cfda6ee58a9 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 10 Feb 2021 10:40:17 +0100 -Subject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: add boot_layout_mode support - -ipq806x nand have a special ecc configuration for the boot pages. The -use of the non-boot pages configuration on boot pages cause I/O error -and can cause broken data written to the nand. Add support for this -special configuration if the page to be read/write is in the size of the -boot pages set by the dts. - -Signed-off-by: Ansuel Smith ---- - drivers/mtd/nand/raw/qcom_nandc.c | 82 +++++++++++++++++++++++++++++-- - 1 file changed, 77 insertions(+), 5 deletions(-) - ---- a/drivers/mtd/nand/raw/qcom_nandc.c -+++ b/drivers/mtd/nand/raw/qcom_nandc.c -@@ -158,6 +158,11 @@ - /* NAND_CTRL bits */ - #define BAM_MODE_EN BIT(0) - -+ -+#define UD_SIZE_BYTES_MASK (0x3ff << UD_SIZE_BYTES) -+#define SPARE_SIZE_BYTES_MASK (0xf << SPARE_SIZE_BYTES) -+#define ECC_NUM_DATA_BYTES_MASK (0x3ff << ECC_NUM_DATA_BYTES) -+ - /* - * the NAND controller performs reads/writes with ECC in 516 byte chunks. - * the driver calls the chunks 'step' or 'codeword' interchangeably -@@ -429,6 +434,13 @@ struct qcom_nand_controller { - * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for - * ecc/non-ecc mode for the current nand flash - * device -+ * -+ * @boot_pages_conf: keep track of the current ecc configuration used by -+ * the driver for read/write operation. (boot pages -+ * have different configuration than normal page) -+ * @boot_pages: number of pages starting from 0 used as boot pages -+ * where the driver will use the boot pages ecc -+ * configuration for read/write operation - */ - struct qcom_nand_host { - struct nand_chip chip; -@@ -451,6 +463,9 @@ struct qcom_nand_host { - u32 ecc_bch_cfg; - u32 clrflashstatus; - u32 clrreadstatus; -+ -+ bool boot_pages_conf; -+ u32 boot_pages; - }; - - /* -@@ -459,12 +474,14 @@ struct qcom_nand_host { - * @ecc_modes - ecc mode for NAND - * @is_bam - whether NAND controller is using BAM - * @is_qpic - whether NAND CTRL is part of qpic IP -+ * @has_boot_pages - whether NAND has different ecc settings for boot pages - * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset - */ - struct qcom_nandc_props { - u32 ecc_modes; - bool is_bam; - bool is_qpic; -+ bool has_boot_pages; - u32 dev_cmd_reg_start; - }; - -@@ -1603,7 +1620,7 @@ qcom_nandc_read_cw_raw(struct mtd_info * - data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); - oob_size1 = host->bbm_size; - -- if (cw == (ecc->steps - 1)) { -+ if (cw == (ecc->steps - 1) && !host->boot_pages_conf) { - data_size2 = ecc->size - data_size1 - - ((ecc->steps - 1) * 4); - oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + -@@ -1684,7 +1701,7 @@ check_for_erased_page(struct qcom_nand_h - } - - for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { -- if (cw == (ecc->steps - 1)) { -+ if (cw == (ecc->steps - 1) && !host->boot_pages_conf) { - data_size = ecc->size - ((ecc->steps - 1) * 4); - oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; - } else { -@@ -1843,7 +1860,7 @@ static int read_page_ecc(struct qcom_nan - for (i = 0; i < ecc->steps; i++) { - int data_size, oob_size; - -- if (i == (ecc->steps - 1)) { -+ if (i == (ecc->steps - 1) && !host->boot_pages_conf) { - data_size = ecc->size - ((ecc->steps - 1) << 2); - oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + - host->spare_bytes; -@@ -1940,6 +1957,30 @@ static int copy_last_cw(struct qcom_nand - return ret; - } - -+static void -+check_boot_pages_conf(struct qcom_nand_host *host, int page) -+{ -+ bool boot_pages_conf = page < host->boot_pages; -+ -+ /* Skip conf write if we are already in the correct mode */ -+ if (boot_pages_conf != host->boot_pages_conf) { -+ host->boot_pages_conf = boot_pages_conf; -+ -+ host->cw_data = boot_pages_conf ? 512 : 516; -+ host->spare_bytes = host->cw_size - host->ecc_bytes_hw - -+ host->bbm_size - host->cw_data; -+ -+ host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); -+ host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | -+ host->cw_data << UD_SIZE_BYTES; -+ -+ host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; -+ host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; -+ host->ecc_buf_cfg = (boot_pages_conf ? 0x1ff : 0x203) << -+ NUM_STEPS; -+ } -+} -+ - /* implements ecc->read_page() */ - static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, - int oob_required, int page) -@@ -1948,6 +1989,9 @@ static int qcom_nandc_read_page(struct n - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - u8 *data_buf, *oob_buf = NULL; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - nand_read_page_op(chip, page, 0, NULL, 0); - data_buf = buf; - oob_buf = oob_required ? chip->oob_poi : NULL; -@@ -1967,6 +2011,9 @@ static int qcom_nandc_read_page_raw(stru - int cw, ret; - u8 *data_buf = buf, *oob_buf = chip->oob_poi; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - for (cw = 0; cw < ecc->steps; cw++) { - ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf, - page, cw); -@@ -1987,6 +2034,9 @@ static int qcom_nandc_read_oob(struct na - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - struct nand_ecc_ctrl *ecc = &chip->ecc; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - clear_read_regs(nandc); - clear_bam_transaction(nandc); - -@@ -2007,6 +2057,9 @@ static int qcom_nandc_write_page(struct - u8 *data_buf, *oob_buf; - int i, ret; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - - clear_read_regs(nandc); -@@ -2022,7 +2075,7 @@ static int qcom_nandc_write_page(struct - for (i = 0; i < ecc->steps; i++) { - int data_size, oob_size; - -- if (i == (ecc->steps - 1)) { -+ if (i == (ecc->steps - 1) && !host->boot_pages_conf) { - data_size = ecc->size - ((ecc->steps - 1) << 2); - oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + - host->spare_bytes; -@@ -2079,6 +2132,9 @@ static int qcom_nandc_write_page_raw(str - u8 *data_buf, *oob_buf; - int i, ret; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - nand_prog_page_begin_op(chip, page, 0, NULL, 0); - clear_read_regs(nandc); - clear_bam_transaction(nandc); -@@ -2097,7 +2153,7 @@ static int qcom_nandc_write_page_raw(str - data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); - oob_size1 = host->bbm_size; - -- if (i == (ecc->steps - 1)) { -+ if (i == (ecc->steps - 1) && !host->boot_pages_conf) { - data_size2 = ecc->size - data_size1 - - ((ecc->steps - 1) << 2); - oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + -@@ -2157,6 +2213,9 @@ static int qcom_nandc_write_oob(struct n - int data_size, oob_size; - int ret; - -+ if (host->boot_pages) -+ check_boot_pages_conf(host, page); -+ - host->use_ecc = true; - clear_bam_transaction(nandc); - -@@ -2805,6 +2864,7 @@ static int qcom_nand_host_init_and_regis - struct nand_chip *chip = &host->chip; - struct mtd_info *mtd = nand_to_mtd(chip); - struct device *dev = nandc->dev; -+ u32 boot_pages_size; - int ret; - - ret = of_property_read_u32(dn, "reg", &host->cs); -@@ -2865,6 +2925,17 @@ static int qcom_nand_host_init_and_regis - if (ret) - nand_cleanup(chip); - -+ if (nandc->props->has_boot_pages && -+ of_property_read_bool(dn, "nand-is-boot-medium")) { -+ ret = of_property_read_u32(dn, "qcom,boot_pages_size", -+ &boot_pages_size); -+ if (ret) -+ dev_warn(dev, "can't get boot pages size"); -+ else -+ /* Convert size to nand pages */ -+ host->boot_pages = boot_pages_size / mtd->writesize; -+ } -+ - return ret; - } - -@@ -3030,6 +3101,7 @@ static int qcom_nandc_remove(struct plat - static const struct qcom_nandc_props ipq806x_nandc_props = { - .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), - .is_bam = false, -+ .has_boot_pages = true, - .dev_cmd_reg_start = 0x0, - }; - diff --git a/target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch b/target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch deleted file mode 100644 index 79036cb057..0000000000 --- a/target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 6fb003a7a117f97a35b078ba726c84adeae29c4c Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 10 Feb 2021 10:54:19 +0100 -Subject: [PATCH 2/2] Documentation: devicetree: mtd: qcom_nandc: document - qcom,boot_layout_size binding - -Document new qcom,boot_layout_size binding used to apply special -read/write confituation to boots partitions. - -Signed-off-by: Ansuel Smith ---- - Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt -+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt -@@ -52,6 +52,15 @@ Optional properties: - be used according to chip requirement and available - OOB size. - -+EBI2 specific properties: -+- nand-is-boot-medium: nand contains boot partitions and different ecc configuration -+ should be used for these partitions. -+- qcom,boot_pages_size: should contain the size of the total boot partitions -+ where the boot layout read/write specific configuration -+ should be used. The boot layout is considered from the -+ start of the nand to the value set in this binding. -+ Only used in combination with 'nand-is-boot-medium'. -+ - Each nandcs device node may optionally contain a 'partitions' sub-node, which - further contains sub-nodes describing the flash partition mapping. See - partition.txt for more detail. -@@ -80,6 +89,9 @@ nand-controller@1ac00000 { - nand-ecc-strength = <4>; - nand-bus-width = <8>; - -+ nand-is-boot-medium; -+ qcom,boot_pages_size: <0x58a0000>; -+ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; diff --git a/target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch b/target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch deleted file mode 100644 index 2d24da01e4..0000000000 --- a/target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch +++ /dev/null @@ -1,965 +0,0 @@ -From 5c9f8c2dbdbe53818bcde6aa6695e1331e5f841f Mon Sep 17 00:00:00 2001 -From: Jonathan McDowell -Date: Sat, 14 Nov 2020 14:02:33 +0000 -Subject: dmaengine: qcom: Add ADM driver - -Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA -controller found in the MSM8x60 and IPQ/APQ8064 platforms. - -The ADM supports both memory to memory transactions and memory -to/from peripheral device transactions. The controller also provides -flow control capabilities for transactions to/from peripheral devices. - -The initial release of this driver supports slave transfers to/from -peripherals and also incorporates CRCI (client rate control interface) -flow control. - -The hardware only supports a 32 bit physical address, so specifying -!PHYS_ADDR_T_64BIT gives maximum COMPILE_TEST coverage without having to -spend effort on kludging things in the code that will never actually be -needed on real hardware. - -Signed-off-by: Andy Gross -Signed-off-by: Thomas Pedersen -Signed-off-by: Jonathan McDowell -Link: https://lore.kernel.org/r/20201114140233.GM32650@earth.li -Signed-off-by: Vinod Koul ---- - drivers/dma/qcom/Kconfig | 11 + - drivers/dma/qcom/Makefile | 1 + - drivers/dma/qcom/qcom_adm.c | 903 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 915 insertions(+) - create mode 100644 drivers/dma/qcom/qcom_adm.c - ---- a/drivers/dma/qcom/Kconfig -+++ b/drivers/dma/qcom/Kconfig -@@ -1,4 +1,15 @@ - # SPDX-License-Identifier: GPL-2.0-only -+config QCOM_ADM -+ tristate "Qualcomm ADM support" -+ depends on (ARCH_QCOM || COMPILE_TEST) && !PHYS_ADDR_T_64BIT -+ select DMA_ENGINE -+ select DMA_VIRTUAL_CHANNELS -+ help -+ Enable support for the Qualcomm Application Data Mover (ADM) DMA -+ controller, as present on MSM8x60, APQ8064, and IPQ8064 devices. -+ This controller provides DMA capabilities for both general purpose -+ and on-chip peripheral devices. -+ - config QCOM_BAM_DMA - tristate "QCOM BAM DMA support" - depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) ---- a/drivers/dma/qcom/Makefile -+++ b/drivers/dma/qcom/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 -+obj-$(CONFIG_QCOM_ADM) += qcom_adm.o - obj-$(CONFIG_QCOM_BAM_DMA) += bam_dma.o - obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mgmt.o - hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o ---- /dev/null -+++ b/drivers/dma/qcom/qcom_adm.c -@@ -0,0 +1,903 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../dmaengine.h" -+#include "../virt-dma.h" -+ -+/* ADM registers - calculated from channel number and security domain */ -+#define ADM_CHAN_MULTI 0x4 -+#define ADM_CI_MULTI 0x4 -+#define ADM_CRCI_MULTI 0x4 -+#define ADM_EE_MULTI 0x800 -+#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * (chan)) -+#define ADM_EE_OFFS(ee) (ADM_EE_MULTI * (ee)) -+#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee)) -+#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * (chan)) -+#define ADM_CI_OFFS(ci) (ADM_CHAN_OFF(ci)) -+#define ADM_CH_CMD_PTR(chan, ee) (ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_CH_RSLT(chan, ee) (0x40 + ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_CH_FLUSH_STATE0(chan, ee) (0x80 + ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_CH_CONF(chan) (0x240 + ADM_CHAN_OFFS(chan)) -+#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee)) -+#define ADM_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + ADM_EE_OFFS(ee)) -+#define ADM_CI_CONF(ci) (0x390 + (ci) * ADM_CI_MULTI) -+#define ADM_GP_CTL 0x3d8 -+#define ADM_CRCI_CTL(crci, ee) (0x400 + (crci) * ADM_CRCI_MULTI + \ -+ ADM_EE_OFFS(ee)) -+ -+/* channel status */ -+#define ADM_CH_STATUS_VALID BIT(1) -+ -+/* channel result */ -+#define ADM_CH_RSLT_VALID BIT(31) -+#define ADM_CH_RSLT_ERR BIT(3) -+#define ADM_CH_RSLT_FLUSH BIT(2) -+#define ADM_CH_RSLT_TPD BIT(1) -+ -+/* channel conf */ -+#define ADM_CH_CONF_SHADOW_EN BIT(12) -+#define ADM_CH_CONF_MPU_DISABLE BIT(11) -+#define ADM_CH_CONF_PERM_MPU_CONF BIT(9) -+#define ADM_CH_CONF_FORCE_RSLT_EN BIT(7) -+#define ADM_CH_CONF_SEC_DOMAIN(ee) ((((ee) & 0x3) << 4) | (((ee) & 0x4) << 11)) -+ -+/* channel result conf */ -+#define ADM_CH_RSLT_CONF_FLUSH_EN BIT(1) -+#define ADM_CH_RSLT_CONF_IRQ_EN BIT(0) -+ -+/* CRCI CTL */ -+#define ADM_CRCI_CTL_MUX_SEL BIT(18) -+#define ADM_CRCI_CTL_RST BIT(17) -+ -+/* CI configuration */ -+#define ADM_CI_RANGE_END(x) ((x) << 24) -+#define ADM_CI_RANGE_START(x) ((x) << 16) -+#define ADM_CI_BURST_4_WORDS BIT(2) -+#define ADM_CI_BURST_8_WORDS BIT(3) -+ -+/* GP CTL */ -+#define ADM_GP_CTL_LP_EN BIT(12) -+#define ADM_GP_CTL_LP_CNT(x) ((x) << 8) -+ -+/* Command pointer list entry */ -+#define ADM_CPLE_LP BIT(31) -+#define ADM_CPLE_CMD_PTR_LIST BIT(29) -+ -+/* Command list entry */ -+#define ADM_CMD_LC BIT(31) -+#define ADM_CMD_DST_CRCI(n) (((n) & 0xf) << 7) -+#define ADM_CMD_SRC_CRCI(n) (((n) & 0xf) << 3) -+ -+#define ADM_CMD_TYPE_SINGLE 0x0 -+#define ADM_CMD_TYPE_BOX 0x3 -+ -+#define ADM_CRCI_MUX_SEL BIT(4) -+#define ADM_DESC_ALIGN 8 -+#define ADM_MAX_XFER (SZ_64K - 1) -+#define ADM_MAX_ROWS (SZ_64K - 1) -+#define ADM_MAX_CHANNELS 16 -+ -+struct adm_desc_hw_box { -+ u32 cmd; -+ u32 src_addr; -+ u32 dst_addr; -+ u32 row_len; -+ u32 num_rows; -+ u32 row_offset; -+}; -+ -+struct adm_desc_hw_single { -+ u32 cmd; -+ u32 src_addr; -+ u32 dst_addr; -+ u32 len; -+}; -+ -+struct adm_async_desc { -+ struct virt_dma_desc vd; -+ struct adm_device *adev; -+ -+ size_t length; -+ enum dma_transfer_direction dir; -+ dma_addr_t dma_addr; -+ size_t dma_len; -+ -+ void *cpl; -+ dma_addr_t cp_addr; -+ u32 crci; -+ u32 mux; -+ u32 blk_size; -+}; -+ -+struct adm_chan { -+ struct virt_dma_chan vc; -+ struct adm_device *adev; -+ -+ /* parsed from DT */ -+ u32 id; /* channel id */ -+ -+ struct adm_async_desc *curr_txd; -+ struct dma_slave_config slave; -+ struct list_head node; -+ -+ int error; -+ int initialized; -+}; -+ -+static inline struct adm_chan *to_adm_chan(struct dma_chan *common) -+{ -+ return container_of(common, struct adm_chan, vc.chan); -+} -+ -+struct adm_device { -+ void __iomem *regs; -+ struct device *dev; -+ struct dma_device common; -+ struct device_dma_parameters dma_parms; -+ struct adm_chan *channels; -+ -+ u32 ee; -+ -+ struct clk *core_clk; -+ struct clk *iface_clk; -+ -+ struct reset_control *clk_reset; -+ struct reset_control *c0_reset; -+ struct reset_control *c1_reset; -+ struct reset_control *c2_reset; -+ int irq; -+}; -+ -+/** -+ * adm_free_chan - Frees dma resources associated with the specific channel -+ * -+ * Free all allocated descriptors associated with this channel -+ * -+ */ -+static void adm_free_chan(struct dma_chan *chan) -+{ -+ /* free all queued descriptors */ -+ vchan_free_chan_resources(to_virt_chan(chan)); -+} -+ -+/** -+ * adm_get_blksize - Get block size from burst value -+ * -+ */ -+static int adm_get_blksize(unsigned int burst) -+{ -+ int ret; -+ -+ switch (burst) { -+ case 16: -+ case 32: -+ case 64: -+ case 128: -+ ret = ffs(burst >> 4) - 1; -+ break; -+ case 192: -+ ret = 4; -+ break; -+ case 256: -+ ret = 5; -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/** -+ * adm_process_fc_descriptors - Process descriptors for flow controlled xfers -+ * -+ * @achan: ADM channel -+ * @desc: Descriptor memory pointer -+ * @sg: Scatterlist entry -+ * @crci: CRCI value -+ * @burst: Burst size of transaction -+ * @direction: DMA transfer direction -+ */ -+static void *adm_process_fc_descriptors(struct adm_chan *achan, void *desc, -+ struct scatterlist *sg, u32 crci, -+ u32 burst, -+ enum dma_transfer_direction direction) -+{ -+ struct adm_desc_hw_box *box_desc = NULL; -+ struct adm_desc_hw_single *single_desc; -+ u32 remainder = sg_dma_len(sg); -+ u32 rows, row_offset, crci_cmd; -+ u32 mem_addr = sg_dma_address(sg); -+ u32 *incr_addr = &mem_addr; -+ u32 *src, *dst; -+ -+ if (direction == DMA_DEV_TO_MEM) { -+ crci_cmd = ADM_CMD_SRC_CRCI(crci); -+ row_offset = burst; -+ src = &achan->slave.src_addr; -+ dst = &mem_addr; -+ } else { -+ crci_cmd = ADM_CMD_DST_CRCI(crci); -+ row_offset = burst << 16; -+ src = &mem_addr; -+ dst = &achan->slave.dst_addr; -+ } -+ -+ while (remainder >= burst) { -+ box_desc = desc; -+ box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd; -+ box_desc->row_offset = row_offset; -+ box_desc->src_addr = *src; -+ box_desc->dst_addr = *dst; -+ -+ rows = remainder / burst; -+ rows = min_t(u32, rows, ADM_MAX_ROWS); -+ box_desc->num_rows = rows << 16 | rows; -+ box_desc->row_len = burst << 16 | burst; -+ -+ *incr_addr += burst * rows; -+ remainder -= burst * rows; -+ desc += sizeof(*box_desc); -+ } -+ -+ /* if leftover bytes, do one single descriptor */ -+ if (remainder) { -+ single_desc = desc; -+ single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd; -+ single_desc->len = remainder; -+ single_desc->src_addr = *src; -+ single_desc->dst_addr = *dst; -+ desc += sizeof(*single_desc); -+ -+ if (sg_is_last(sg)) -+ single_desc->cmd |= ADM_CMD_LC; -+ } else { -+ if (box_desc && sg_is_last(sg)) -+ box_desc->cmd |= ADM_CMD_LC; -+ } -+ -+ return desc; -+} -+ -+/** -+ * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers -+ * -+ * @achan: ADM channel -+ * @desc: Descriptor memory pointer -+ * @sg: Scatterlist entry -+ * @direction: DMA transfer direction -+ */ -+static void *adm_process_non_fc_descriptors(struct adm_chan *achan, void *desc, -+ struct scatterlist *sg, -+ enum dma_transfer_direction direction) -+{ -+ struct adm_desc_hw_single *single_desc; -+ u32 remainder = sg_dma_len(sg); -+ u32 mem_addr = sg_dma_address(sg); -+ u32 *incr_addr = &mem_addr; -+ u32 *src, *dst; -+ -+ if (direction == DMA_DEV_TO_MEM) { -+ src = &achan->slave.src_addr; -+ dst = &mem_addr; -+ } else { -+ src = &mem_addr; -+ dst = &achan->slave.dst_addr; -+ } -+ -+ do { -+ single_desc = desc; -+ single_desc->cmd = ADM_CMD_TYPE_SINGLE; -+ single_desc->src_addr = *src; -+ single_desc->dst_addr = *dst; -+ single_desc->len = (remainder > ADM_MAX_XFER) ? -+ ADM_MAX_XFER : remainder; -+ -+ remainder -= single_desc->len; -+ *incr_addr += single_desc->len; -+ desc += sizeof(*single_desc); -+ } while (remainder); -+ -+ /* set last command if this is the end of the whole transaction */ -+ if (sg_is_last(sg)) -+ single_desc->cmd |= ADM_CMD_LC; -+ -+ return desc; -+} -+ -+/** -+ * adm_prep_slave_sg - Prep slave sg transaction -+ * -+ * @chan: dma channel -+ * @sgl: scatter gather list -+ * @sg_len: length of sg -+ * @direction: DMA transfer direction -+ * @flags: DMA flags -+ * @context: transfer context (unused) -+ */ -+static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan, -+ struct scatterlist *sgl, -+ unsigned int sg_len, -+ enum dma_transfer_direction direction, -+ unsigned long flags, -+ void *context) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ struct adm_device *adev = achan->adev; -+ struct adm_async_desc *async_desc; -+ struct scatterlist *sg; -+ dma_addr_t cple_addr; -+ u32 i, burst; -+ u32 single_count = 0, box_count = 0, crci = 0; -+ void *desc; -+ u32 *cple; -+ int blk_size = 0; -+ -+ if (!is_slave_direction(direction)) { -+ dev_err(adev->dev, "invalid dma direction\n"); -+ return NULL; -+ } -+ -+ /* -+ * get burst value from slave configuration -+ */ -+ burst = (direction == DMA_MEM_TO_DEV) ? -+ achan->slave.dst_maxburst : -+ achan->slave.src_maxburst; -+ -+ /* if using flow control, validate burst and crci values */ -+ if (achan->slave.device_fc) { -+ blk_size = adm_get_blksize(burst); -+ if (blk_size < 0) { -+ dev_err(adev->dev, "invalid burst value: %d\n", -+ burst); -+ return ERR_PTR(-EINVAL); -+ } -+ -+ crci = achan->slave.slave_id & 0xf; -+ if (!crci || achan->slave.slave_id > 0x1f) { -+ dev_err(adev->dev, "invalid crci value\n"); -+ return ERR_PTR(-EINVAL); -+ } -+ } -+ -+ /* iterate through sgs and compute allocation size of structures */ -+ for_each_sg(sgl, sg, sg_len, i) { -+ if (achan->slave.device_fc) { -+ box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst, -+ ADM_MAX_ROWS); -+ if (sg_dma_len(sg) % burst) -+ single_count++; -+ } else { -+ single_count += DIV_ROUND_UP(sg_dma_len(sg), -+ ADM_MAX_XFER); -+ } -+ } -+ -+ async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT); -+ if (!async_desc) -+ return ERR_PTR(-ENOMEM); -+ -+ if (crci) -+ async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ? -+ ADM_CRCI_CTL_MUX_SEL : 0; -+ async_desc->crci = crci; -+ async_desc->blk_size = blk_size; -+ async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) + -+ box_count * sizeof(struct adm_desc_hw_box) + -+ sizeof(*cple) + 2 * ADM_DESC_ALIGN; -+ -+ async_desc->cpl = kzalloc(async_desc->dma_len, GFP_NOWAIT); -+ if (!async_desc->cpl) -+ goto free; -+ -+ async_desc->adev = adev; -+ -+ /* both command list entry and descriptors must be 8 byte aligned */ -+ cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN); -+ desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN); -+ -+ for_each_sg(sgl, sg, sg_len, i) { -+ async_desc->length += sg_dma_len(sg); -+ -+ if (achan->slave.device_fc) -+ desc = adm_process_fc_descriptors(achan, desc, sg, crci, -+ burst, direction); -+ else -+ desc = adm_process_non_fc_descriptors(achan, desc, sg, -+ direction); -+ } -+ -+ async_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl, -+ async_desc->dma_len, -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(adev->dev, async_desc->dma_addr)) -+ goto free; -+ -+ cple_addr = async_desc->dma_addr + ((void *)cple - async_desc->cpl); -+ -+ /* init cmd list */ -+ dma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple), -+ DMA_TO_DEVICE); -+ *cple = ADM_CPLE_LP; -+ *cple |= (async_desc->dma_addr + ADM_DESC_ALIGN) >> 3; -+ dma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple), -+ DMA_TO_DEVICE); -+ -+ return vchan_tx_prep(&achan->vc, &async_desc->vd, flags); -+ -+free: -+ kfree(async_desc); -+ return ERR_PTR(-ENOMEM); -+} -+ -+/** -+ * adm_terminate_all - terminate all transactions on a channel -+ * @achan: adm dma channel -+ * -+ * Dequeues and frees all transactions, aborts current transaction -+ * No callbacks are done -+ * -+ */ -+static int adm_terminate_all(struct dma_chan *chan) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ struct adm_device *adev = achan->adev; -+ unsigned long flags; -+ LIST_HEAD(head); -+ -+ spin_lock_irqsave(&achan->vc.lock, flags); -+ vchan_get_all_descriptors(&achan->vc, &head); -+ -+ /* send flush command to terminate current transaction */ -+ writel_relaxed(0x0, -+ adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee)); -+ -+ spin_unlock_irqrestore(&achan->vc.lock, flags); -+ -+ vchan_dma_desc_free_list(&achan->vc, &head); -+ -+ return 0; -+} -+ -+static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ unsigned long flag; -+ -+ spin_lock_irqsave(&achan->vc.lock, flag); -+ memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config)); -+ spin_unlock_irqrestore(&achan->vc.lock, flag); -+ -+ return 0; -+} -+ -+/** -+ * adm_start_dma - start next transaction -+ * @achan - ADM dma channel -+ */ -+static void adm_start_dma(struct adm_chan *achan) -+{ -+ struct virt_dma_desc *vd = vchan_next_desc(&achan->vc); -+ struct adm_device *adev = achan->adev; -+ struct adm_async_desc *async_desc; -+ -+ lockdep_assert_held(&achan->vc.lock); -+ -+ if (!vd) -+ return; -+ -+ list_del(&vd->node); -+ -+ /* write next command list out to the CMD FIFO */ -+ async_desc = container_of(vd, struct adm_async_desc, vd); -+ achan->curr_txd = async_desc; -+ -+ /* reset channel error */ -+ achan->error = 0; -+ -+ if (!achan->initialized) { -+ /* enable interrupts */ -+ writel(ADM_CH_CONF_SHADOW_EN | -+ ADM_CH_CONF_PERM_MPU_CONF | -+ ADM_CH_CONF_MPU_DISABLE | -+ ADM_CH_CONF_SEC_DOMAIN(adev->ee), -+ adev->regs + ADM_CH_CONF(achan->id)); -+ -+ writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN, -+ adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); -+ -+ achan->initialized = 1; -+ } -+ -+ /* set the crci block size if this transaction requires CRCI */ -+ if (async_desc->crci) { -+ writel(async_desc->mux | async_desc->blk_size, -+ adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee)); -+ } -+ -+ /* make sure IRQ enable doesn't get reordered */ -+ wmb(); -+ -+ /* write next command list out to the CMD FIFO */ -+ writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3, -+ adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee)); -+} -+ -+/** -+ * adm_dma_irq - irq handler for ADM controller -+ * @irq: IRQ of interrupt -+ * @data: callback data -+ * -+ * IRQ handler for the bam controller -+ */ -+static irqreturn_t adm_dma_irq(int irq, void *data) -+{ -+ struct adm_device *adev = data; -+ u32 srcs, i; -+ struct adm_async_desc *async_desc; -+ unsigned long flags; -+ -+ srcs = readl_relaxed(adev->regs + -+ ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee)); -+ -+ for (i = 0; i < ADM_MAX_CHANNELS; i++) { -+ struct adm_chan *achan = &adev->channels[i]; -+ u32 status, result; -+ -+ if (srcs & BIT(i)) { -+ status = readl_relaxed(adev->regs + -+ ADM_CH_STATUS_SD(i, adev->ee)); -+ -+ /* if no result present, skip */ -+ if (!(status & ADM_CH_STATUS_VALID)) -+ continue; -+ -+ result = readl_relaxed(adev->regs + -+ ADM_CH_RSLT(i, adev->ee)); -+ -+ /* no valid results, skip */ -+ if (!(result & ADM_CH_RSLT_VALID)) -+ continue; -+ -+ /* flag error if transaction was flushed or failed */ -+ if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH)) -+ achan->error = 1; -+ -+ spin_lock_irqsave(&achan->vc.lock, flags); -+ async_desc = achan->curr_txd; -+ -+ achan->curr_txd = NULL; -+ -+ if (async_desc) { -+ vchan_cookie_complete(&async_desc->vd); -+ -+ /* kick off next DMA */ -+ adm_start_dma(achan); -+ } -+ -+ spin_unlock_irqrestore(&achan->vc.lock, flags); -+ } -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/** -+ * adm_tx_status - returns status of transaction -+ * @chan: dma channel -+ * @cookie: transaction cookie -+ * @txstate: DMA transaction state -+ * -+ * Return status of dma transaction -+ */ -+static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie, -+ struct dma_tx_state *txstate) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ struct virt_dma_desc *vd; -+ enum dma_status ret; -+ unsigned long flags; -+ size_t residue = 0; -+ -+ ret = dma_cookie_status(chan, cookie, txstate); -+ if (ret == DMA_COMPLETE || !txstate) -+ return ret; -+ -+ spin_lock_irqsave(&achan->vc.lock, flags); -+ -+ vd = vchan_find_desc(&achan->vc, cookie); -+ if (vd) -+ residue = container_of(vd, struct adm_async_desc, vd)->length; -+ -+ spin_unlock_irqrestore(&achan->vc.lock, flags); -+ -+ /* -+ * residue is either the full length if it is in the issued list, or 0 -+ * if it is in progress. We have no reliable way of determining -+ * anything inbetween -+ */ -+ dma_set_residue(txstate, residue); -+ -+ if (achan->error) -+ return DMA_ERROR; -+ -+ return ret; -+} -+ -+/** -+ * adm_issue_pending - starts pending transactions -+ * @chan: dma channel -+ * -+ * Issues all pending transactions and starts DMA -+ */ -+static void adm_issue_pending(struct dma_chan *chan) -+{ -+ struct adm_chan *achan = to_adm_chan(chan); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&achan->vc.lock, flags); -+ -+ if (vchan_issue_pending(&achan->vc) && !achan->curr_txd) -+ adm_start_dma(achan); -+ spin_unlock_irqrestore(&achan->vc.lock, flags); -+} -+ -+/** -+ * adm_dma_free_desc - free descriptor memory -+ * @vd: virtual descriptor -+ * -+ */ -+static void adm_dma_free_desc(struct virt_dma_desc *vd) -+{ -+ struct adm_async_desc *async_desc = container_of(vd, -+ struct adm_async_desc, vd); -+ -+ dma_unmap_single(async_desc->adev->dev, async_desc->dma_addr, -+ async_desc->dma_len, DMA_TO_DEVICE); -+ kfree(async_desc->cpl); -+ kfree(async_desc); -+} -+ -+static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan, -+ u32 index) -+{ -+ achan->id = index; -+ achan->adev = adev; -+ -+ vchan_init(&achan->vc, &adev->common); -+ achan->vc.desc_free = adm_dma_free_desc; -+} -+ -+static int adm_dma_probe(struct platform_device *pdev) -+{ -+ struct adm_device *adev; -+ int ret; -+ u32 i; -+ -+ adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL); -+ if (!adev) -+ return -ENOMEM; -+ -+ adev->dev = &pdev->dev; -+ -+ adev->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(adev->regs)) -+ return PTR_ERR(adev->regs); -+ -+ adev->irq = platform_get_irq(pdev, 0); -+ if (adev->irq < 0) -+ return adev->irq; -+ -+ ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee); -+ if (ret) { -+ dev_err(adev->dev, "Execution environment unspecified\n"); -+ return ret; -+ } -+ -+ adev->core_clk = devm_clk_get(adev->dev, "core"); -+ if (IS_ERR(adev->core_clk)) -+ return PTR_ERR(adev->core_clk); -+ -+ adev->iface_clk = devm_clk_get(adev->dev, "iface"); -+ if (IS_ERR(adev->iface_clk)) -+ return PTR_ERR(adev->iface_clk); -+ -+ adev->clk_reset = devm_reset_control_get_exclusive(&pdev->dev, "clk"); -+ if (IS_ERR(adev->clk_reset)) { -+ dev_err(adev->dev, "failed to get ADM0 reset\n"); -+ return PTR_ERR(adev->clk_reset); -+ } -+ -+ adev->c0_reset = devm_reset_control_get_exclusive(&pdev->dev, "c0"); -+ if (IS_ERR(adev->c0_reset)) { -+ dev_err(adev->dev, "failed to get ADM0 C0 reset\n"); -+ return PTR_ERR(adev->c0_reset); -+ } -+ -+ adev->c1_reset = devm_reset_control_get_exclusive(&pdev->dev, "c1"); -+ if (IS_ERR(adev->c1_reset)) { -+ dev_err(adev->dev, "failed to get ADM0 C1 reset\n"); -+ return PTR_ERR(adev->c1_reset); -+ } -+ -+ adev->c2_reset = devm_reset_control_get_exclusive(&pdev->dev, "c2"); -+ if (IS_ERR(adev->c2_reset)) { -+ dev_err(adev->dev, "failed to get ADM0 C2 reset\n"); -+ return PTR_ERR(adev->c2_reset); -+ } -+ -+ ret = clk_prepare_enable(adev->core_clk); -+ if (ret) { -+ dev_err(adev->dev, "failed to prepare/enable core clock\n"); -+ return ret; -+ } -+ -+ ret = clk_prepare_enable(adev->iface_clk); -+ if (ret) { -+ dev_err(adev->dev, "failed to prepare/enable iface clock\n"); -+ goto err_disable_core_clk; -+ } -+ -+ reset_control_assert(adev->clk_reset); -+ reset_control_assert(adev->c0_reset); -+ reset_control_assert(adev->c1_reset); -+ reset_control_assert(adev->c2_reset); -+ -+ udelay(2); -+ -+ reset_control_deassert(adev->clk_reset); -+ reset_control_deassert(adev->c0_reset); -+ reset_control_deassert(adev->c1_reset); -+ reset_control_deassert(adev->c2_reset); -+ -+ adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS, -+ sizeof(*adev->channels), GFP_KERNEL); -+ -+ if (!adev->channels) { -+ ret = -ENOMEM; -+ goto err_disable_clks; -+ } -+ -+ /* allocate and initialize channels */ -+ INIT_LIST_HEAD(&adev->common.channels); -+ -+ for (i = 0; i < ADM_MAX_CHANNELS; i++) -+ adm_channel_init(adev, &adev->channels[i], i); -+ -+ /* reset CRCIs */ -+ for (i = 0; i < 16; i++) -+ writel(ADM_CRCI_CTL_RST, adev->regs + -+ ADM_CRCI_CTL(i, adev->ee)); -+ -+ /* configure client interfaces */ -+ writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) | -+ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0)); -+ writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) | -+ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1)); -+ writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) | -+ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2)); -+ writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf), -+ adev->regs + ADM_GP_CTL); -+ -+ ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq, -+ 0, "adm_dma", adev); -+ if (ret) -+ goto err_disable_clks; -+ -+ platform_set_drvdata(pdev, adev); -+ -+ adev->common.dev = adev->dev; -+ adev->common.dev->dma_parms = &adev->dma_parms; -+ -+ /* set capabilities */ -+ dma_cap_zero(adev->common.cap_mask); -+ dma_cap_set(DMA_SLAVE, adev->common.cap_mask); -+ dma_cap_set(DMA_PRIVATE, adev->common.cap_mask); -+ -+ /* initialize dmaengine apis */ -+ adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV); -+ adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; -+ adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ adev->common.device_free_chan_resources = adm_free_chan; -+ adev->common.device_prep_slave_sg = adm_prep_slave_sg; -+ adev->common.device_issue_pending = adm_issue_pending; -+ adev->common.device_tx_status = adm_tx_status; -+ adev->common.device_terminate_all = adm_terminate_all; -+ adev->common.device_config = adm_slave_config; -+ -+ ret = dma_async_device_register(&adev->common); -+ if (ret) { -+ dev_err(adev->dev, "failed to register dma async device\n"); -+ goto err_disable_clks; -+ } -+ -+ ret = of_dma_controller_register(pdev->dev.of_node, -+ of_dma_xlate_by_chan_id, -+ &adev->common); -+ if (ret) -+ goto err_unregister_dma; -+ -+ return 0; -+ -+err_unregister_dma: -+ dma_async_device_unregister(&adev->common); -+err_disable_clks: -+ clk_disable_unprepare(adev->iface_clk); -+err_disable_core_clk: -+ clk_disable_unprepare(adev->core_clk); -+ -+ return ret; -+} -+ -+static int adm_dma_remove(struct platform_device *pdev) -+{ -+ struct adm_device *adev = platform_get_drvdata(pdev); -+ struct adm_chan *achan; -+ u32 i; -+ -+ of_dma_controller_free(pdev->dev.of_node); -+ dma_async_device_unregister(&adev->common); -+ -+ for (i = 0; i < ADM_MAX_CHANNELS; i++) { -+ achan = &adev->channels[i]; -+ -+ /* mask IRQs for this channel/EE pair */ -+ writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); -+ -+ tasklet_kill(&adev->channels[i].vc.task); -+ adm_terminate_all(&adev->channels[i].vc.chan); -+ } -+ -+ devm_free_irq(adev->dev, adev->irq, adev); -+ -+ clk_disable_unprepare(adev->core_clk); -+ clk_disable_unprepare(adev->iface_clk); -+ -+ return 0; -+} -+ -+static const struct of_device_id adm_of_match[] = { -+ { .compatible = "qcom,adm", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, adm_of_match); -+ -+static struct platform_driver adm_dma_driver = { -+ .probe = adm_dma_probe, -+ .remove = adm_dma_remove, -+ .driver = { -+ .name = "adm-dma-engine", -+ .of_match_table = adm_of_match, -+ }, -+}; -+ -+module_platform_driver(adm_dma_driver); -+ -+MODULE_AUTHOR("Andy Gross "); -+MODULE_DESCRIPTION("QCOM ADM DMA engine driver"); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch b/target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch deleted file mode 100644 index 13b7c137e0..0000000000 --- a/target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch +++ /dev/null @@ -1,217 +0,0 @@ -From 803eb124e1a64e42888542c3444bfe6dac412c7f Mon Sep 17 00:00:00 2001 -From: Manivannan Sadhasivam -Date: Mon, 4 Jan 2021 09:41:35 +0530 -Subject: mtd: parsers: Add Qcom SMEM parser - -NAND based Qualcomm platforms have the partition table populated in the -Shared Memory (SMEM). Hence, add a parser for parsing the partitions -from it. - -Signed-off-by: Manivannan Sadhasivam -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-3-manivannan.sadhasivam@linaro.org ---- - drivers/mtd/parsers/Kconfig | 8 ++ - drivers/mtd/parsers/Makefile | 1 + - drivers/mtd/parsers/qcomsmempart.c | 170 +++++++++++++++++++++++++++++++++++++ - 3 files changed, 179 insertions(+) - create mode 100644 drivers/mtd/parsers/qcomsmempart.c - ---- a/drivers/mtd/parsers/Kconfig -+++ b/drivers/mtd/parsers/Kconfig -@@ -220,6 +220,14 @@ config MTD_SERCOMM_PARTS - offsets, which may differ from device to device depending on the - number and location of bad blocks on NAND. - -+config MTD_QCOMSMEM_PARTS -+ tristate "Qualcomm SMEM NAND flash partition parser" -+ depends on MTD_NAND_QCOM || COMPILE_TEST -+ depends on QCOM_SMEM -+ help -+ This provides support for parsing partitions from Shared Memory (SMEM) -+ for NAND flash on Qualcomm platforms. -+ - config MTD_ROUTERBOOT_PARTS - tristate "RouterBoot flash partition parser" - depends on MTD && OF ---- a/drivers/mtd/parsers/Makefile -+++ b/drivers/mtd/parsers/Makefile -@@ -15,4 +15,5 @@ obj-$(CONFIG_MTD_PARSER_TRX) += parser_ - obj-$(CONFIG_MTD_SERCOMM_PARTS) += scpart.o - obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o - obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o -+obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o - obj-$(CONFIG_MTD_ROUTERBOOT_PARTS) += routerbootpart.o ---- /dev/null -+++ b/drivers/mtd/parsers/qcomsmempart.c -@@ -0,0 +1,170 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Qualcomm SMEM NAND flash partition parser -+ * -+ * Copyright (C) 2020, Linaro Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SMEM_AARM_PARTITION_TABLE 9 -+#define SMEM_APPS 0 -+ -+#define SMEM_FLASH_PART_MAGIC1 0x55ee73aa -+#define SMEM_FLASH_PART_MAGIC2 0xe35ebddb -+#define SMEM_FLASH_PTABLE_V3 3 -+#define SMEM_FLASH_PTABLE_V4 4 -+#define SMEM_FLASH_PTABLE_MAX_PARTS_V3 16 -+#define SMEM_FLASH_PTABLE_MAX_PARTS_V4 48 -+#define SMEM_FLASH_PTABLE_HDR_LEN (4 * sizeof(u32)) -+#define SMEM_FLASH_PTABLE_NAME_SIZE 16 -+ -+/** -+ * struct smem_flash_pentry - SMEM Flash partition entry -+ * @name: Name of the partition -+ * @offset: Offset in blocks -+ * @length: Length of the partition in blocks -+ * @attr: Flags for this partition -+ */ -+struct smem_flash_pentry { -+ char name[SMEM_FLASH_PTABLE_NAME_SIZE]; -+ __le32 offset; -+ __le32 length; -+ u8 attr; -+} __packed __aligned(4); -+ -+/** -+ * struct smem_flash_ptable - SMEM Flash partition table -+ * @magic1: Partition table Magic 1 -+ * @magic2: Partition table Magic 2 -+ * @version: Partition table version -+ * @numparts: Number of partitions in this ptable -+ * @pentry: Flash partition entries belonging to this ptable -+ */ -+struct smem_flash_ptable { -+ __le32 magic1; -+ __le32 magic2; -+ __le32 version; -+ __le32 numparts; -+ struct smem_flash_pentry pentry[SMEM_FLASH_PTABLE_MAX_PARTS_V4]; -+} __packed __aligned(4); -+ -+static int parse_qcomsmem_part(struct mtd_info *mtd, -+ const struct mtd_partition **pparts, -+ struct mtd_part_parser_data *data) -+{ -+ struct smem_flash_pentry *pentry; -+ struct smem_flash_ptable *ptable; -+ size_t len = SMEM_FLASH_PTABLE_HDR_LEN; -+ struct mtd_partition *parts; -+ int ret, i, numparts; -+ char *name, *c; -+ -+ pr_debug("Parsing partition table info from SMEM\n"); -+ ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); -+ if (IS_ERR(ptable)) { -+ pr_err("Error reading partition table header\n"); -+ return PTR_ERR(ptable); -+ } -+ -+ /* Verify ptable magic */ -+ if (le32_to_cpu(ptable->magic1) != SMEM_FLASH_PART_MAGIC1 || -+ le32_to_cpu(ptable->magic2) != SMEM_FLASH_PART_MAGIC2) { -+ pr_err("Partition table magic verification failed\n"); -+ return -EINVAL; -+ } -+ -+ /* Ensure that # of partitions is less than the max we have allocated */ -+ numparts = le32_to_cpu(ptable->numparts); -+ if (numparts > SMEM_FLASH_PTABLE_MAX_PARTS_V4) { -+ pr_err("Partition numbers exceed the max limit\n"); -+ return -EINVAL; -+ } -+ -+ /* Find out length of partition data based on table version */ -+ if (le32_to_cpu(ptable->version) <= SMEM_FLASH_PTABLE_V3) { -+ len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V3 * -+ sizeof(struct smem_flash_pentry); -+ } else if (le32_to_cpu(ptable->version) == SMEM_FLASH_PTABLE_V4) { -+ len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V4 * -+ sizeof(struct smem_flash_pentry); -+ } else { -+ pr_err("Unknown ptable version (%d)", le32_to_cpu(ptable->version)); -+ return -EINVAL; -+ } -+ -+ /* -+ * Now that the partition table header has been parsed, verified -+ * and the length of the partition table calculated, read the -+ * complete partition table -+ */ -+ ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); -+ if (IS_ERR_OR_NULL(ptable)) { -+ pr_err("Error reading partition table\n"); -+ return PTR_ERR(ptable); -+ } -+ -+ parts = kcalloc(numparts, sizeof(*parts), GFP_KERNEL); -+ if (!parts) -+ return -ENOMEM; -+ -+ for (i = 0; i < numparts; i++) { -+ pentry = &ptable->pentry[i]; -+ if (pentry->name[0] == '\0') -+ continue; -+ -+ name = kstrdup(pentry->name, GFP_KERNEL); -+ if (!name) { -+ ret = -ENOMEM; -+ goto out_free_parts; -+ } -+ -+ /* Convert name to lower case */ -+ for (c = name; *c != '\0'; c++) -+ *c = tolower(*c); -+ -+ parts[i].name = name; -+ parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize; -+ parts[i].mask_flags = pentry->attr; -+ parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize; -+ pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x\n", -+ i, pentry->name, le32_to_cpu(pentry->offset), -+ le32_to_cpu(pentry->length), pentry->attr); -+ } -+ -+ pr_debug("SMEM partition table found: ver: %d len: %d\n", -+ le32_to_cpu(ptable->version), numparts); -+ *pparts = parts; -+ -+ return numparts; -+ -+out_free_parts: -+ while (--i >= 0) -+ kfree(parts[i].name); -+ kfree(parts); -+ *pparts = NULL; -+ -+ return ret; -+} -+ -+static const struct of_device_id qcomsmem_of_match_table[] = { -+ { .compatible = "qcom,smem-part" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, qcomsmem_of_match_table); -+ -+static struct mtd_part_parser mtd_parser_qcomsmem = { -+ .parse_fn = parse_qcomsmem_part, -+ .name = "qcomsmem", -+ .of_match_table = qcomsmem_of_match_table, -+}; -+module_mtd_part_parser(mtd_parser_qcomsmem); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Manivannan Sadhasivam "); -+MODULE_DESCRIPTION("Qualcomm SMEM NAND flash partition parser"); diff --git a/target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch b/target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch deleted file mode 100644 index 2210f4e249..0000000000 --- a/target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch +++ /dev/null @@ -1,83 +0,0 @@ ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c -@@ -64,6 +64,17 @@ - #define NSS_COMMON_CLK_DIV_SGMII_100 4 - #define NSS_COMMON_CLK_DIV_SGMII_10 49 - -+#define QSGMII_PCS_ALL_CH_CTL 0x80 -+#define QSGMII_PCS_CH_SPEED_FORCE 0x2 -+#define QSGMII_PCS_CH_SPEED_10 0x0 -+#define QSGMII_PCS_CH_SPEED_100 0x4 -+#define QSGMII_PCS_CH_SPEED_1000 0x8 -+#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \ -+ QSGMII_PCS_CH_SPEED_10 | \ -+ QSGMII_PCS_CH_SPEED_100 | \ -+ QSGMII_PCS_CH_SPEED_1000) -+#define QSGMII_PCS_CH_SPEED_SHIFT(x) (x * 4) -+ - #define QSGMII_PCS_CAL_LCKDT_CTL 0x120 - #define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19) - -@@ -242,6 +253,36 @@ static void ipq806x_gmac_fix_mac_speed(v - ipq806x_gmac_set_speed(gmac, speed); - } - -+static int -+ipq806x_gmac_get_qsgmii_pcs_speed_val(struct platform_device *pdev) { -+ struct device_node *fixed_link_node; -+ int rv; -+ int fixed_link_speed; -+ -+ if (!of_phy_is_fixed_link(pdev->dev.of_node)) -+ return 0; -+ -+ fixed_link_node = of_get_child_by_name(pdev->dev.of_node, "fixed-link"); -+ if (!fixed_link_node) -+ return -1; -+ -+ rv = of_property_read_u32(fixed_link_node, "speed", &fixed_link_speed); -+ of_node_put(fixed_link_node); -+ if (rv) -+ return -1; -+ -+ switch (fixed_link_speed) { -+ case SPEED_1000: -+ return QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_1000; -+ case SPEED_100: -+ return QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_100; -+ case SPEED_10: -+ return QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_10; -+ } -+ -+ return -1; -+} -+ - static int ipq806x_gmac_probe(struct platform_device *pdev) - { - struct plat_stmmacenet_data *plat_dat; -@@ -250,6 +291,7 @@ static int ipq806x_gmac_probe(struct pla - struct ipq806x_gmac *gmac; - int val; - int err; -+ int qsgmii_pcs_speed; - - val = stmmac_get_platform_resources(pdev, &stmmac_res); - if (val) -@@ -339,6 +381,17 @@ static int ipq806x_gmac_probe(struct pla - 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET | - 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET | - 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET); -+ -+ qsgmii_pcs_speed = ipq806x_gmac_get_qsgmii_pcs_speed_val(pdev); -+ if (qsgmii_pcs_speed != -1) { -+ regmap_update_bits( -+ gmac->qsgmii_csr, -+ QSGMII_PCS_ALL_CH_CTL, -+ QSGMII_PCS_CH_SPEED_MASK << -+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id), -+ qsgmii_pcs_speed << -+ QSGMII_PCS_CH_SPEED_SHIFT(gmac->id)); -+ } - } - - plat_dat->has_gmac = true; diff --git a/target/linux/ipq806x/patches-5.10/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/target/linux/ipq806x/patches-5.10/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch deleted file mode 100644 index e83872935f..0000000000 --- a/target/linux/ipq806x/patches-5.10/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 9 Mar 2017 09:31:44 +0100 -Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting - -Signed-off-by: John Crispin ---- - drivers/mtd/parsers/qcomsmempart.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/parsers/qcomsmempart.c -+++ b/drivers/mtd/parsers/qcomsmempart.c -@@ -132,6 +132,11 @@ static int parse_qcomsmem_part(struct mt - parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize; - parts[i].mask_flags = pentry->attr; - parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize; -+ -+ /* "rootfs" conflicts with OpenWrt auto mounting */ -+ if (mtd_type_is_nand(mtd) && !strcmp(name, "rootfs")) -+ parts[i].name = "ubi"; -+ - pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x\n", - i, pentry->name, le32_to_cpu(pentry->offset), - le32_to_cpu(pentry->length), pentry->attr); diff --git a/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch b/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch deleted file mode 100644 index 2a6d4007fa..0000000000 --- a/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 84909e85881d67244240c9f40974ce12a51e3886 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 11 May 2021 23:09:45 +0200 -Subject: [PATCH] ARM: dts: qcom: reduce pci IO size to 64K - -The current value is probably a typo and is actually uncommon to find -1MB IO space even on a x86 arch. Also with recent changes to the pci -driver, pci1 and pci2 now fails to function as any connected device -fails any reg read/write. Reduce this to 64K as it should be more than -enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT -hardcoded for the ARM arch. - -Signed-off-by: Ansuel Smith ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1162,7 +1162,7 @@ - #address-cells = <3>; - #size-cells = <2>; - -- ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ -+ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ - - interrupts = ; -@@ -1213,7 +1213,7 @@ - #address-cells = <3>; - #size-cells = <2>; - -- ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ -+ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ - - interrupts = ; -@@ -1264,7 +1264,7 @@ - #address-cells = <3>; - #size-cells = <2>; - -- ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ -+ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ - - interrupts = ; diff --git a/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch b/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch deleted file mode 100644 index 5f422c1dde..0000000000 --- a/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch +++ /dev/null @@ -1,285 +0,0 @@ -From 5c7d1181056feef0b58fb2f556f55e170ba5b479 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 25 Jul 2020 19:14:59 +0200 -Subject: [PATCH 01/10] drivers: thermal: tsens: Add VER_0 tsens version - -VER_0 is used to describe device based on tsens version before v0.1. -These device are devices based on msm8960 for example apq8064 or -ipq806x. - -Signed-off-by: Ansuel Smith -Reviewed-by: Thara Gopinath -Reported-by: kernel test robot -Reported-by: Dan Carpenter ---- - drivers/thermal/qcom/tsens.c | 150 ++++++++++++++++++++++++++++------- - drivers/thermal/qcom/tsens.h | 4 +- - 2 files changed, 124 insertions(+), 30 deletions(-) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -515,6 +516,15 @@ static irqreturn_t tsens_irq_thread(int - dev_dbg(priv->dev, "[%u] %s: no violation: %d\n", - hw_id, __func__, temp); - } -+ -+ if (tsens_version(priv) < VER_0_1) { -+ /* Constraint: There is only 1 interrupt control register for all -+ * 11 temperature sensor. So monitoring more than 1 sensor based -+ * on interrupts will yield inconsistent result. To overcome this -+ * issue we will monitor only sensor 0 which is the master sensor. -+ */ -+ break; -+ } - } - - return IRQ_HANDLED; -@@ -530,6 +540,13 @@ static int tsens_set_trips(void *_sensor - int high_val, low_val, cl_high, cl_low; - u32 hw_id = s->hw_id; - -+ if (tsens_version(priv) < VER_0_1) { -+ /* Pre v0.1 IP had a single register for each type of interrupt -+ * and thresholds -+ */ -+ hw_id = 0; -+ } -+ - dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", - hw_id, __func__, low, high); - -@@ -584,18 +601,21 @@ int get_temp_tsens_valid(const struct ts - u32 valid; - int ret; - -- ret = regmap_field_read(priv->rf[valid_idx], &valid); -- if (ret) -- return ret; -- while (!valid) { -- /* Valid bit is 0 for 6 AHB clock cycles. -- * At 19.2MHz, 1 AHB clock is ~60ns. -- * We should enter this loop very, very rarely. -- */ -- ndelay(400); -+ /* VER_0 doesn't have VALID bit */ -+ if (tsens_version(priv) >= VER_0_1) { - ret = regmap_field_read(priv->rf[valid_idx], &valid); - if (ret) - return ret; -+ while (!valid) { -+ /* Valid bit is 0 for 6 AHB clock cycles. -+ * At 19.2MHz, 1 AHB clock is ~60ns. -+ * We should enter this loop very, very rarely. -+ */ -+ ndelay(400); -+ ret = regmap_field_read(priv->rf[valid_idx], &valid); -+ if (ret) -+ return ret; -+ } - } - - /* Valid bit is set, OK to read the temperature */ -@@ -608,15 +628,29 @@ int get_temp_common(const struct tsens_s - { - struct tsens_priv *priv = s->priv; - int hw_id = s->hw_id; -- int last_temp = 0, ret; -+ int last_temp = 0, ret, trdy; -+ unsigned long timeout; - -- ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); -- if (ret) -- return ret; -+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); -+ do { -+ if (tsens_version(priv) == VER_0) { -+ ret = regmap_field_read(priv->rf[TRDY], &trdy); -+ if (ret) -+ return ret; -+ if (!trdy) -+ continue; -+ } - -- *temp = code_to_degc(last_temp, s) * 1000; -+ ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); -+ if (ret) -+ return ret; - -- return 0; -+ *temp = code_to_degc(last_temp, s) * 1000; -+ -+ return 0; -+ } while (time_before(jiffies, timeout)); -+ -+ return -ETIMEDOUT; - } - - #ifdef CONFIG_DEBUG_FS -@@ -738,19 +772,34 @@ int __init init_common(struct tsens_priv - priv->tm_offset = 0x1000; - } - -- res = platform_get_resource(op, IORESOURCE_MEM, 0); -- tm_base = devm_ioremap_resource(dev, res); -- if (IS_ERR(tm_base)) { -- ret = PTR_ERR(tm_base); -- goto err_put_device; -+ if (tsens_version(priv) >= VER_0_1) { -+ res = platform_get_resource(op, IORESOURCE_MEM, 0); -+ tm_base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(tm_base)) { -+ ret = PTR_ERR(tm_base); -+ goto err_put_device; -+ } -+ -+ priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); -+ } else { /* VER_0 share the same gcc regs using a syscon */ -+ struct device *parent = priv->dev->parent; -+ -+ if (parent) -+ priv->tm_map = syscon_node_to_regmap(parent->of_node); - } - -- priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); -- if (IS_ERR(priv->tm_map)) { -- ret = PTR_ERR(priv->tm_map); -+ if (IS_ERR_OR_NULL(priv->tm_map)) { -+ if (!priv->tm_map) -+ ret = -ENODEV; -+ else -+ ret = PTR_ERR(priv->tm_map); - goto err_put_device; - } - -+ /* VER_0 have only tm_map */ -+ if (!priv->srot_map) -+ priv->srot_map = priv->tm_map; -+ - if (tsens_version(priv) > VER_0_1) { - for (i = VER_MAJOR; i <= VER_STEP; i++) { - priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, -@@ -771,6 +820,10 @@ int __init init_common(struct tsens_priv - ret = PTR_ERR(priv->rf[TSENS_EN]); - goto err_put_device; - } -+ /* in VER_0 TSENS need to be explicitly enabled */ -+ if (tsens_version(priv) == VER_0) -+ regmap_field_write(priv->rf[TSENS_EN], 1); -+ - ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); - if (ret) - goto err_put_device; -@@ -793,6 +846,19 @@ int __init init_common(struct tsens_priv - goto err_put_device; - } - -+ priv->rf[TSENS_SW_RST] = -+ devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_SW_RST]); -+ if (IS_ERR(priv->rf[TSENS_SW_RST])) { -+ ret = PTR_ERR(priv->rf[TSENS_SW_RST]); -+ goto err_put_device; -+ } -+ -+ priv->rf[TRDY] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]); -+ if (IS_ERR(priv->rf[TRDY])) { -+ ret = PTR_ERR(priv->rf[TRDY]); -+ goto err_put_device; -+ } -+ - /* This loop might need changes if enum regfield_ids is reordered */ - for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { - for (i = 0; i < priv->feat->max_sensors; i++) { -@@ -808,7 +874,7 @@ int __init init_common(struct tsens_priv - } - } - -- if (priv->feat->crit_int) { -+ if (priv->feat->crit_int || tsens_version(priv) < VER_0_1) { - /* Loop might need changes if enum regfield_ids is reordered */ - for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) { - for (i = 0; i < priv->feat->max_sensors; i++) { -@@ -846,7 +912,11 @@ int __init init_common(struct tsens_priv - } - - spin_lock_init(&priv->ul_lock); -- tsens_enable_irq(priv); -+ -+ /* VER_0 interrupt doesn't need to be enabled */ -+ if (tsens_version(priv) >= VER_0_1) -+ tsens_enable_irq(priv); -+ - tsens_debug_init(op); - - err_put_device: -@@ -951,10 +1021,19 @@ static int tsens_register_irq(struct tse - if (irq == -ENXIO) - ret = 0; - } else { -- ret = devm_request_threaded_irq(&pdev->dev, irq, -- NULL, thread_fn, -- IRQF_ONESHOT, -- dev_name(&pdev->dev), priv); -+ /* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */ -+ if (tsens_version(priv) == VER_0) -+ ret = devm_request_threaded_irq(&pdev->dev, irq, -+ thread_fn, NULL, -+ IRQF_TRIGGER_RISING, -+ dev_name(&pdev->dev), -+ priv); -+ else -+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, -+ thread_fn, IRQF_ONESHOT, -+ dev_name(&pdev->dev), -+ priv); -+ - if (ret) - dev_err(&pdev->dev, "%s: failed to get irq\n", - __func__); -@@ -983,6 +1062,19 @@ static int tsens_register(struct tsens_p - priv->ops->enable(priv, i); - } - -+ /* VER_0 require to set MIN and MAX THRESH -+ * These 2 regs are set using the: -+ * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C -+ * - CRIT_THRESH_1 for MIN THRESH hardcoded to 0°C -+ */ -+ if (tsens_version(priv) < VER_0_1) { -+ regmap_field_write(priv->rf[CRIT_THRESH_0], -+ tsens_mC_to_hw(priv->sensor, 120000)); -+ -+ regmap_field_write(priv->rf[CRIT_THRESH_1], -+ tsens_mC_to_hw(priv->sensor, 0)); -+ } -+ - ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); - if (ret < 0) - return ret; ---- a/drivers/thermal/qcom/tsens.h -+++ b/drivers/thermal/qcom/tsens.h -@@ -13,6 +13,7 @@ - #define CAL_DEGC_PT2 120 - #define SLOPE_FACTOR 1000 - #define SLOPE_DEFAULT 3200 -+#define TIMEOUT_US 100 - #define THRESHOLD_MAX_ADC_CODE 0x3ff - #define THRESHOLD_MIN_ADC_CODE 0x0 - -@@ -25,7 +26,8 @@ struct tsens_priv; - - /* IP version numbers in ascending order */ - enum tsens_ver { -- VER_0_1 = 0, -+ VER_0 = 0, -+ VER_0_1, - VER_1_X, - VER_2_X, - }; diff --git a/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch b/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch deleted file mode 100644 index 109f524bbd..0000000000 --- a/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch +++ /dev/null @@ -1,28 +0,0 @@ -From efa0d50a6c5ec7619371dfe4d3e6ca54b73787d5 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 25 Nov 2020 16:47:21 +0100 -Subject: [PATCH 02/10] drivers: thermal: tsens: Don't hardcode sensor slope - -Function compute_intercept_slope hardcode the sensor slope to -SLOPE_DEFAULT. Change this and use the default value only if a slope is -not defined. This is needed for tsens VER_0 that has a hardcoded slope -table. - -Signed-off-by: Ansuel Smith -Reviewed-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -86,7 +86,8 @@ void compute_intercept_slope(struct tsen - "%s: sensor%d - data_point1:%#x data_point2:%#x\n", - __func__, i, p1[i], p2[i]); - -- priv->sensor[i].slope = SLOPE_DEFAULT; -+ if (!priv->sensor[i].slope) -+ priv->sensor[i].slope = SLOPE_DEFAULT; - if (mode == TWO_PT_CALIB) { - /* - * slope (m) = adc_code2 - adc_code1 (y2 - y1)/ diff --git a/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch b/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch deleted file mode 100644 index bf378107c6..0000000000 --- a/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch +++ /dev/null @@ -1,119 +0,0 @@ -From 6bac2e2fa36c2d7c304768a689d8b73155b90aa2 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 25 Nov 2020 17:15:51 +0100 -Subject: [PATCH 03/10] drivers: thermal: tsens: Convert msm8960 to reg_field - -Convert msm9860 driver to reg_field to use the init_common -function. - -Signed-off-by: Ansuel Smith -Acked-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens-8960.c | 80 ++++++++++++++++++++++++++++++- - 1 file changed, 79 insertions(+), 1 deletion(-) - ---- a/drivers/thermal/qcom/tsens-8960.c -+++ b/drivers/thermal/qcom/tsens-8960.c -@@ -51,11 +51,22 @@ - #define MIN_LIMIT_TH 0x0 - #define MAX_LIMIT_TH 0xff - --#define S0_STATUS_ADDR 0x3628 - #define INT_STATUS_ADDR 0x363c - #define TRDY_MASK BIT(7) - #define TIMEOUT_US 100 - -+#define S0_STATUS_OFF 0x3628 -+#define S1_STATUS_OFF 0x362c -+#define S2_STATUS_OFF 0x3630 -+#define S3_STATUS_OFF 0x3634 -+#define S4_STATUS_OFF 0x3638 -+#define S5_STATUS_OFF 0x3664 /* Sensors 5-10 found on apq8064/msm8960 */ -+#define S6_STATUS_OFF 0x3668 -+#define S7_STATUS_OFF 0x366c -+#define S8_STATUS_OFF 0x3670 -+#define S9_STATUS_OFF 0x3674 -+#define S10_STATUS_OFF 0x3678 -+ - static int suspend_8960(struct tsens_priv *priv) - { - int ret; -@@ -269,6 +280,71 @@ static int get_temp_8960(const struct ts - return -ETIMEDOUT; - } - -+static struct tsens_features tsens_8960_feat = { -+ .ver_major = VER_0, -+ .crit_int = 0, -+ .adc = 1, -+ .srot_split = 0, -+ .max_sensors = 11, -+}; -+ -+static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = { -+ /* ----- SROT ------ */ -+ /* No VERSION information */ -+ -+ /* CNTL */ -+ [TSENS_EN] = REG_FIELD(CNTL_ADDR, 0, 0), -+ [TSENS_SW_RST] = REG_FIELD(CNTL_ADDR, 1, 1), -+ /* 8960 has 5 sensors, 8660 has 11, we only handle 5 */ -+ [SENSOR_EN] = REG_FIELD(CNTL_ADDR, 3, 7), -+ -+ /* ----- TM ------ */ -+ /* INTERRUPT ENABLE */ -+ /* NO INTERRUPT ENABLE */ -+ -+ /* Single UPPER/LOWER TEMPERATURE THRESHOLD for all sensors */ -+ [LOW_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 0, 7), -+ [UP_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 8, 15), -+ /* MIN_THRESH_0 and MAX_THRESH_0 are not present in the regfield -+ * Recycle CRIT_THRESH_0 and 1 to set the required regs to hardcoded temp -+ * MIN_THRESH_0 -> CRIT_THRESH_1 -+ * MAX_THRESH_0 -> CRIT_THRESH_0 -+ */ -+ [CRIT_THRESH_1] = REG_FIELD(THRESHOLD_ADDR, 16, 23), -+ [CRIT_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 24, 31), -+ -+ /* UPPER/LOWER INTERRUPT [CLEAR/STATUS] */ -+ /* 1 == clear, 0 == normal operation */ -+ [LOW_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 9, 9), -+ [UP_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 10, 10), -+ -+ /* NO CRITICAL INTERRUPT SUPPORT on 8960 */ -+ -+ /* Sn_STATUS */ -+ [LAST_TEMP_0] = REG_FIELD(S0_STATUS_OFF, 0, 7), -+ [LAST_TEMP_1] = REG_FIELD(S1_STATUS_OFF, 0, 7), -+ [LAST_TEMP_2] = REG_FIELD(S2_STATUS_OFF, 0, 7), -+ [LAST_TEMP_3] = REG_FIELD(S3_STATUS_OFF, 0, 7), -+ [LAST_TEMP_4] = REG_FIELD(S4_STATUS_OFF, 0, 7), -+ [LAST_TEMP_5] = REG_FIELD(S5_STATUS_OFF, 0, 7), -+ [LAST_TEMP_6] = REG_FIELD(S6_STATUS_OFF, 0, 7), -+ [LAST_TEMP_7] = REG_FIELD(S7_STATUS_OFF, 0, 7), -+ [LAST_TEMP_8] = REG_FIELD(S8_STATUS_OFF, 0, 7), -+ [LAST_TEMP_9] = REG_FIELD(S9_STATUS_OFF, 0, 7), -+ [LAST_TEMP_10] = REG_FIELD(S10_STATUS_OFF, 0, 7), -+ -+ /* No VALID field on 8960 */ -+ /* TSENS_INT_STATUS bits: 1 == threshold violated */ -+ [MIN_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 0, 0), -+ [LOWER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 1, 1), -+ [UPPER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 2, 2), -+ /* No CRITICAL field on 8960 */ -+ [MAX_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 3, 3), -+ -+ /* TRDY: 1=ready, 0=in progress */ -+ [TRDY] = REG_FIELD(INT_STATUS_ADDR, 7, 7), -+}; -+ - static const struct tsens_ops ops_8960 = { - .init = init_8960, - .calibrate = calibrate_8960, -@@ -282,4 +358,6 @@ static const struct tsens_ops ops_8960 = - struct tsens_plat_data data_8960 = { - .num_sensors = 11, - .ops = &ops_8960, -+ .feat = &tsens_8960_feat, -+ .fields = tsens_8960_regfields, - }; diff --git a/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch b/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch deleted file mode 100644 index ae8a52c100..0000000000 --- a/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch +++ /dev/null @@ -1,81 +0,0 @@ -From c04f98a496929f75d75c65115d5717423c3d0634 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 25 Nov 2020 17:16:36 +0100 -Subject: [PATCH 04/10] drivers: thermal: tsens: Use init_common for msm8960 - -Use init_common and drop custom init for msm8960. - -Signed-off-by: Ansuel Smith -Reviewed-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens-8960.c | 52 +------------------------------ - 1 file changed, 1 insertion(+), 51 deletions(-) - ---- a/drivers/thermal/qcom/tsens-8960.c -+++ b/drivers/thermal/qcom/tsens-8960.c -@@ -173,56 +173,6 @@ static void disable_8960(struct tsens_pr - regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); - } - --static int init_8960(struct tsens_priv *priv) --{ -- int ret, i; -- u32 reg_cntl; -- -- priv->tm_map = dev_get_regmap(priv->dev, NULL); -- if (!priv->tm_map) -- return -ENODEV; -- -- /* -- * The status registers for each sensor are discontiguous -- * because some SoCs have 5 sensors while others have more -- * but the control registers stay in the same place, i.e -- * directly after the first 5 status registers. -- */ -- for (i = 0; i < priv->num_sensors; i++) { -- if (i >= 5) -- priv->sensor[i].status = S0_STATUS_ADDR + 40; -- priv->sensor[i].status += i * 4; -- } -- -- reg_cntl = SW_RST; -- ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl); -- if (ret) -- return ret; -- -- if (priv->num_sensors > 1) { -- reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18); -- reg_cntl &= ~SW_RST; -- ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR, -- CONFIG_MASK, CONFIG); -- } else { -- reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16); -- reg_cntl &= ~CONFIG_MASK_8660; -- reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660; -- } -- -- reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT; -- ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); -- if (ret) -- return ret; -- -- reg_cntl |= EN; -- ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); -- if (ret) -- return ret; -- -- return 0; --} -- - static int calibrate_8960(struct tsens_priv *priv) - { - int i; -@@ -346,7 +296,7 @@ static const struct reg_field tsens_8960 - }; - - static const struct tsens_ops ops_8960 = { -- .init = init_8960, -+ .init = init_common, - .calibrate = calibrate_8960, - .get_temp = get_temp_8960, - .enable = enable_8960, diff --git a/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch b/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch deleted file mode 100644 index 7b01a67d90..0000000000 --- a/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch +++ /dev/null @@ -1,66 +0,0 @@ -From b3e8bd33b84a6b6c863bd1733bd15b5f1483b8ab Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 25 Nov 2020 17:06:55 +0100 -Subject: [PATCH 05/10] drivers: thermal: tsens: Fix bug in sensor enable for - msm8960 - -Device based on tsens VER_0 contains a hardware bug that results in some -problem with sensor enablement. Sensor id 6-11 can't be enabled -selectively and all of them must be enabled in one step. - -Signed-off-by: Ansuel Smith -Acked-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens-8960.c | 23 ++++++++++++++++++++--- - 1 file changed, 20 insertions(+), 3 deletions(-) - ---- a/drivers/thermal/qcom/tsens-8960.c -+++ b/drivers/thermal/qcom/tsens-8960.c -@@ -27,9 +27,9 @@ - #define EN BIT(0) - #define SW_RST BIT(1) - #define SENSOR0_EN BIT(3) -+#define MEASURE_PERIOD BIT(18) - #define SLP_CLK_ENA BIT(26) - #define SLP_CLK_ENA_8660 BIT(24) --#define MEASURE_PERIOD 1 - #define SENSOR0_SHIFT 3 - - /* INT_STATUS_ADDR bitmasks */ -@@ -126,17 +126,34 @@ static int resume_8960(struct tsens_priv - static int enable_8960(struct tsens_priv *priv, int id) - { - int ret; -- u32 reg, mask; -+ u32 reg, mask = BIT(id); - - ret = regmap_read(priv->tm_map, CNTL_ADDR, ®); - if (ret) - return ret; - -- mask = BIT(id + SENSOR0_SHIFT); -+ /* HARDWARE BUG: -+ * On platforms with more than 6 sensors, all remaining sensors -+ * must be enabled together, otherwise undefined results are expected. -+ * (Sensor 6-7 disabled, Sensor 3 disabled...) In the original driver, -+ * all the sensors are enabled in one step hence this bug is not -+ * triggered. -+ */ -+ if (id > 5) -+ mask = GENMASK(10, 6); -+ -+ mask <<= SENSOR0_SHIFT; -+ -+ /* Sensors already enabled. Skip. */ -+ if ((reg & mask) == mask) -+ return 0; -+ - ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST); - if (ret) - return ret; - -+ reg |= MEASURE_PERIOD; -+ - if (priv->num_sensors > 1) - reg |= mask | SLP_CLK_ENA | EN; - else diff --git a/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch b/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch deleted file mode 100644 index a82f596954..0000000000 --- a/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch +++ /dev/null @@ -1,109 +0,0 @@ -From 1ff9f982051759e0387e8c7e793b49c48eae291d Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Wed, 25 Nov 2020 17:11:05 +0100 -Subject: [PATCH 06/10] drivers: thermal: tsens: Replace custom 8960 apis with - generic apis - -Rework calibrate function to use common function. Derive the offset from -a missing hardcoded slope table and the data from the nvmem calib -efuses. -Drop custom get_temp function and use generic api. - -Signed-off-by: Ansuel Smith -Acked-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens-8960.c | 56 +++++++++---------------------- - 1 file changed, 15 insertions(+), 41 deletions(-) - ---- a/drivers/thermal/qcom/tsens-8960.c -+++ b/drivers/thermal/qcom/tsens-8960.c -@@ -67,6 +67,13 @@ - #define S9_STATUS_OFF 0x3674 - #define S10_STATUS_OFF 0x3678 - -+/* Original slope - 200 to compensate mC to C inaccuracy */ -+static u32 tsens_msm8960_slope[] = { -+ 976, 976, 954, 976, -+ 911, 932, 932, 999, -+ 932, 999, 932 -+ }; -+ - static int suspend_8960(struct tsens_priv *priv) - { - int ret; -@@ -194,9 +201,7 @@ static int calibrate_8960(struct tsens_p - { - int i; - char *data; -- -- ssize_t num_read = priv->num_sensors; -- struct tsens_sensor *s = priv->sensor; -+ u32 p1[11]; - - data = qfprom_read(priv->dev, "calib"); - if (IS_ERR(data)) -@@ -204,49 +209,18 @@ static int calibrate_8960(struct tsens_p - if (IS_ERR(data)) - return PTR_ERR(data); - -- for (i = 0; i < num_read; i++, s++) -- s->offset = data[i]; -+ for (i = 0; i < priv->num_sensors; i++) { -+ p1[i] = data[i]; -+ priv->sensor[i].slope = tsens_msm8960_slope[i]; -+ } -+ -+ compute_intercept_slope(priv, p1, NULL, ONE_PT_CALIB); - - kfree(data); - - return 0; - } - --/* Temperature on y axis and ADC-code on x-axis */ --static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) --{ -- int slope, offset; -- -- slope = thermal_zone_get_slope(s->tzd); -- offset = CAL_MDEGC - slope * s->offset; -- -- return adc_code * slope + offset; --} -- --static int get_temp_8960(const struct tsens_sensor *s, int *temp) --{ -- int ret; -- u32 code, trdy; -- struct tsens_priv *priv = s->priv; -- unsigned long timeout; -- -- timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); -- do { -- ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy); -- if (ret) -- return ret; -- if (!(trdy & TRDY_MASK)) -- continue; -- ret = regmap_read(priv->tm_map, s->status, &code); -- if (ret) -- return ret; -- *temp = code_to_mdegC(code, s); -- return 0; -- } while (time_before(jiffies, timeout)); -- -- return -ETIMEDOUT; --} -- - static struct tsens_features tsens_8960_feat = { - .ver_major = VER_0, - .crit_int = 0, -@@ -315,7 +289,7 @@ static const struct reg_field tsens_8960 - static const struct tsens_ops ops_8960 = { - .init = init_common, - .calibrate = calibrate_8960, -- .get_temp = get_temp_8960, -+ .get_temp = get_temp_common, - .enable = enable_8960, - .disable = disable_8960, - .suspend = suspend_8960, diff --git a/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch b/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch deleted file mode 100644 index 77ca3cfe45..0000000000 --- a/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 5716a61239c6ac9ceb137e825e93c3aea06c4634 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Fri, 19 Mar 2021 00:48:23 +0100 -Subject: [PATCH 07/10] drivers: thermal: tsens: Drop unused define for msm8960 - -Drop unused define for msm8960 replaced by generic api and reg_field. - -Signed-off-by: Ansuel Smith -Reviewed-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens-8960.c | 24 +----------------------- - 1 file changed, 1 insertion(+), 23 deletions(-) - ---- a/drivers/thermal/qcom/tsens-8960.c -+++ b/drivers/thermal/qcom/tsens-8960.c -@@ -10,8 +10,6 @@ - #include - #include "tsens.h" - --#define CAL_MDEGC 30000 -- - #define CONFIG_ADDR 0x3640 - #define CONFIG_ADDR_8660 0x3620 - /* CONFIG_ADDR bitmasks */ -@@ -21,39 +19,19 @@ - #define CONFIG_SHIFT_8660 28 - #define CONFIG_MASK_8660 (3 << CONFIG_SHIFT_8660) - --#define STATUS_CNTL_ADDR_8064 0x3660 - #define CNTL_ADDR 0x3620 - /* CNTL_ADDR bitmasks */ - #define EN BIT(0) - #define SW_RST BIT(1) --#define SENSOR0_EN BIT(3) -+ - #define MEASURE_PERIOD BIT(18) - #define SLP_CLK_ENA BIT(26) - #define SLP_CLK_ENA_8660 BIT(24) - #define SENSOR0_SHIFT 3 - --/* INT_STATUS_ADDR bitmasks */ --#define MIN_STATUS_MASK BIT(0) --#define LOWER_STATUS_CLR BIT(1) --#define UPPER_STATUS_CLR BIT(2) --#define MAX_STATUS_MASK BIT(3) -- - #define THRESHOLD_ADDR 0x3624 --/* THRESHOLD_ADDR bitmasks */ --#define THRESHOLD_MAX_LIMIT_SHIFT 24 --#define THRESHOLD_MIN_LIMIT_SHIFT 16 --#define THRESHOLD_UPPER_LIMIT_SHIFT 8 --#define THRESHOLD_LOWER_LIMIT_SHIFT 0 -- --/* Initial temperature threshold values */ --#define LOWER_LIMIT_TH 0x50 --#define UPPER_LIMIT_TH 0xdf --#define MIN_LIMIT_TH 0x0 --#define MAX_LIMIT_TH 0xff - - #define INT_STATUS_ADDR 0x363c --#define TRDY_MASK BIT(7) --#define TIMEOUT_US 100 - - #define S0_STATUS_OFF 0x3628 - #define S1_STATUS_OFF 0x362c diff --git a/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch b/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch deleted file mode 100644 index 127abaefc3..0000000000 --- a/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 0d0c22a59bf2672b57e23da9a9ea743e91b71f54 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Sat, 25 Jul 2020 19:55:57 +0200 -Subject: [PATCH 08/10] drivers: thermal: tsens: Add support for ipq8064-tsens - -Add support for tsens present in ipq806x SoCs based on generic msm8960 -tsens driver. - -Signed-off-by: Ansuel Smith -Reviewed-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -968,6 +968,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, t - - static const struct of_device_id tsens_table[] = { - { -+ .compatible = "qcom,ipq8064-tsens", -+ .data = &data_8960, -+ }, { - .compatible = "qcom,msm8916-tsens", - .data = &data_8916, - }, { diff --git a/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch b/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch deleted file mode 100644 index 382106863f..0000000000 --- a/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch +++ /dev/null @@ -1,112 +0,0 @@ -From ac369071920d427dd484cf74cddba2774bba45f5 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Thu, 9 Jul 2020 22:35:54 +0200 -Subject: [PATCH 09/10] dt-bindings: thermal: tsens: Document ipq8064 bindings - -Document the use of bindings used for msm8960 tsens based devices. -msm8960 use the same gcc regs and is set as a child of the qcom gcc. - -Signed-off-by: Ansuel Smith -Reviewed-by: Rob Herring ---- - .../bindings/thermal/qcom-tsens.yaml | 56 ++++++++++++++++--- - 1 file changed, 48 insertions(+), 8 deletions(-) - ---- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml -+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml -@@ -19,6 +19,11 @@ description: | - properties: - compatible: - oneOf: -+ - description: msm9860 TSENS based -+ items: -+ - enum: -+ - qcom,ipq8064-tsens -+ - - description: v0.1 of TSENS - items: - - enum: -@@ -73,7 +78,9 @@ properties: - maxItems: 2 - items: - - const: calib -- - const: calib_sel -+ - enum: -+ - calib_backup -+ - calib_sel - - "#qcom,sensors": - description: -@@ -88,12 +95,20 @@ properties: - Number of cells required to uniquely identify the thermal sensors. Since - we have multiple sensors this is set to 1 - -+required: -+ - compatible -+ - interrupts -+ - interrupt-names -+ - "#thermal-sensor-cells" -+ - "#qcom,sensors" -+ - allOf: - - if: - properties: - compatible: - contains: - enum: -+ - qcom,ipq8064-tsens - - qcom,msm8916-tsens - - qcom,msm8974-tsens - - qcom,msm8976-tsens -@@ -114,19 +129,44 @@ allOf: - interrupt-names: - minItems: 2 - --required: -- - compatible -- - reg -- - "#qcom,sensors" -- - interrupts -- - interrupt-names -- - "#thermal-sensor-cells" -+ - if: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - qcom,tsens-v0_1 -+ - qcom,tsens-v1 -+ - qcom,tsens-v2 -+ -+ then: -+ required: -+ - reg - - additionalProperties: false - - examples: - - | - #include -+ // Example msm9860 based SoC (ipq8064): -+ gcc: clock-controller { -+ -+ /* ... */ -+ -+ tsens: thermal-sensor { -+ compatible = "qcom,ipq8064-tsens"; -+ -+ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; -+ nvmem-cell-names = "calib", "calib_backup"; -+ interrupts = ; -+ interrupt-names = "uplow"; -+ -+ #qcom,sensors = <11>; -+ #thermal-sensor-cells = <1>; -+ }; -+ }; -+ -+ - | -+ #include - // Example 1 (legacy: for pre v1 IP): - tsens1: thermal-sensor@900000 { - compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; diff --git a/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch b/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch deleted file mode 100644 index 6cdc0b263f..0000000000 --- a/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 68e720ed73c8f038c8c500e4c49c1e65a993a448 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Tue, 6 Apr 2021 04:45:31 +0200 -Subject: [PATCH 10/10] drivers: thermal: tsens: Fix wrong slope on msm-8960 - -Some user using some stats with the old legacy implementation and the -new implementation using the compute_intercept_slope reported an offset -of 3C. Fix the slope table to reflect the original temp. - -Signed-off-by: Ansuel Smith ---- - drivers/thermal/qcom/tsens-8960.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/thermal/qcom/tsens-8960.c -+++ b/drivers/thermal/qcom/tsens-8960.c -@@ -45,11 +45,11 @@ - #define S9_STATUS_OFF 0x3674 - #define S10_STATUS_OFF 0x3678 - --/* Original slope - 200 to compensate mC to C inaccuracy */ -+/* Original slope - 350 to compensate mC to C inaccuracy */ - static u32 tsens_msm8960_slope[] = { -- 976, 976, 954, 976, -- 911, 932, 932, 999, -- 932, 999, 932 -+ 826, 826, 804, 826, -+ 761, 782, 782, 849, -+ 782, 849, 782 - }; - - static int suspend_8960(struct tsens_priv *priv) diff --git a/target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch b/target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch deleted file mode 100644 index 5c9ba71c79..0000000000 --- a/target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 8f32d48a309246a80bdca505968085a484d54408 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 19 Apr 2021 03:01:53 +0200 -Subject: [thermal-next PATCH v2 1/2] thermal: qcom: tsens: init debugfs only with - successful probe - -calibrate and tsens_register can fail or PROBE_DEFER. This will cause a -double or a wrong init of the debugfs information. Init debugfs only -with successful probe fixing warning about directory already present. - -Signed-off-by: Ansuel Smith -Acked-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -918,8 +918,6 @@ int __init init_common(struct tsens_priv - if (tsens_version(priv) >= VER_0_1) - tsens_enable_irq(priv); - -- tsens_debug_init(op); -- - err_put_device: - put_device(&op->dev); - return ret; -@@ -1161,7 +1159,12 @@ static int tsens_probe(struct platform_d - } - } - -- return tsens_register(priv); -+ ret = tsens_register(priv); -+ -+ if (!ret) -+ tsens_debug_init(pdev); -+ -+ return ret; - } - - static int tsens_remove(struct platform_device *pdev) diff --git a/target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch b/target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch deleted file mode 100644 index 0fbc4bd8ca..0000000000 --- a/target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 4204f22060f7a5d42c6ccb4d4c25a6a875571099 Mon Sep 17 00:00:00 2001 -From: Ansuel Smith -Date: Mon, 19 Apr 2021 03:08:37 +0200 -Subject: [thermal-next PATCH v2 2/2] thermal: qcom: tsens: simplify debugfs init - function - -Simplify debugfs init function. -- Add check for existing dev directory. -- Fix wrong version in dbg_version_show (with version 0.0.0, 0.1.0 was - incorrectly reported) - -Signed-off-by: Ansuel Smith -Reviewed-by: Thara Gopinath ---- - drivers/thermal/qcom/tsens.c | 16 +++++++--------- - 1 file changed, 7 insertions(+), 9 deletions(-) - ---- a/drivers/thermal/qcom/tsens.c -+++ b/drivers/thermal/qcom/tsens.c -@@ -692,7 +692,7 @@ static int dbg_version_show(struct seq_f - return ret; - seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver); - } else { -- seq_puts(s, "0.1.0\n"); -+ seq_printf(s, "0.%d.0\n", priv->feat->ver_major); - } - - return 0; -@@ -704,21 +704,17 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors); - static void tsens_debug_init(struct platform_device *pdev) - { - struct tsens_priv *priv = platform_get_drvdata(pdev); -- struct dentry *root, *file; - -- root = debugfs_lookup("tsens", NULL); -- if (!root) -+ priv->debug_root = debugfs_lookup("tsens", NULL); -+ if (!priv->debug_root) - priv->debug_root = debugfs_create_dir("tsens", NULL); -- else -- priv->debug_root = root; - -- file = debugfs_lookup("version", priv->debug_root); -- if (!file) -+ if (!debugfs_lookup("version", priv->debug_root)) - debugfs_create_file("version", 0444, priv->debug_root, - pdev, &dbg_version_fops); - - /* A directory for each instance of the TSENS IP */ -- priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root); -+ priv->debug = debugfs_lookup(dev_name(&pdev->dev), priv->debug_root); - debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops); - } - #else diff --git a/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch b/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch deleted file mode 100644 index 508c6ba65e..0000000000 --- a/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch +++ /dev/null @@ -1,75 +0,0 @@ -From e67f325e9cd67562b761e884680c0fec03a6f404 Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Tue, 8 Jun 2021 19:59:06 +0100 -Subject: net: stmmac: explicitly deassert GMAC_AHB_RESET - -We are currently assuming that GMAC_AHB_RESET will already be deasserted -by the bootloader. However if this has not been done, probing of the GMAC -will fail. To remedy this we must ensure GMAC_AHB_RESET has been deasserted -prior to probing. - -v2 changes: - - remove NULL condition check for stmmac_ahb_rst in stmmac_main.c - - unwrap dev_err() message in stmmac_main.c - - add PTR_ERR() around plat->stmmac_ahb_rst in stmmac_platform.c - -v3 changes: - - add error pointer to dev_err() output - - add reset_control_assert(stmmac_ahb_rst) in stmmac_dvr_remove - - revert PTR_ERR() around plat->stmmac_ahb_rst since this is performed - on the returned value of ret by the calling function - -Signed-off-by: Matthew Hagan -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++++ - drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 6 ++++++ - include/linux/stmmac.h | 1 + - 3 files changed, 12 insertions(+) - ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5052,6 +5052,10 @@ int stmmac_dvr_probe(struct device *devi - reset_control_reset(priv->plat->stmmac_rst); - } - -+ ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); -+ if (ret == -ENOTSUPP) -+ dev_err(priv->device, "unable to bring out of ahb reset\n"); -+ - /* Init MAC and get the capabilities */ - ret = stmmac_hw_init(priv); - if (ret) -@@ -5266,6 +5270,7 @@ int stmmac_dvr_remove(struct device *dev - phylink_destroy(priv->phylink); - if (priv->plat->stmmac_rst) - reset_control_assert(priv->plat->stmmac_rst); -+ reset_control_assert(priv->plat->stmmac_ahb_rst); - pm_runtime_put(dev); - pm_runtime_disable(dev); - if (priv->hw->pcs != STMMAC_PCS_TBI && ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -@@ -616,6 +616,12 @@ stmmac_probe_config_dt(struct platform_d - plat->stmmac_rst = NULL; - } - -+ plat->stmmac_ahb_rst = devm_reset_control_get_optional_shared( -+ &pdev->dev, "ahb"); -+ if (IS_ERR(plat->stmmac_ahb_rst)) -+ if (PTR_ERR(plat->stmmac_ahb_rst) == -EPROBE_DEFER) -+ goto error_hw_init; -+ - return plat; - - error_hw_init: ---- a/include/linux/stmmac.h -+++ b/include/linux/stmmac.h -@@ -192,6 +192,7 @@ struct plat_stmmacenet_data { - unsigned int clk_ref_rate; - s32 ptp_max_adj; - struct reset_control *stmmac_rst; -+ struct reset_control *stmmac_ahb_rst; - struct stmmac_axi *axi; - int has_gmac4; - bool has_sun8i; diff --git a/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch b/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch deleted file mode 100644 index d94d898233..0000000000 --- a/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch +++ /dev/null @@ -1,64 +0,0 @@ -From f95c4c56d65225a537a2d88735fde7ec4d37641d Mon Sep 17 00:00:00 2001 -From: Matthew Hagan -Date: Sat, 5 Jun 2021 18:35:38 +0100 -Subject: ARM: dts: qcom: add ahb reset to ipq806x-gmac - -Add GMAC_AHB_RESET to the resets property of each gmac node. - -Signed-off-by: Matthew Hagan -Link: https://lore.kernel.org/r/20210605173546.4102455-2-mnhagan88@gmail.com -Signed-off-by: Bjorn Andersson ---- - arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 ++++++++++++-------- - 1 file changed, 12 insertions(+), 8 deletions(-) - ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1334,8 +1334,9 @@ - clocks = <&gcc GMAC_CORE1_CLK>; - clock-names = "stmmaceth"; - -- resets = <&gcc GMAC_CORE1_RESET>; -- reset-names = "stmmaceth"; -+ resets = <&gcc GMAC_CORE1_RESET>, -+ <&gcc GMAC_AHB_RESET>; -+ reset-names = "stmmaceth", "ahb"; - - status = "disabled"; - }; -@@ -1357,8 +1358,9 @@ - clocks = <&gcc GMAC_CORE2_CLK>; - clock-names = "stmmaceth"; - -- resets = <&gcc GMAC_CORE2_RESET>; -- reset-names = "stmmaceth"; -+ resets = <&gcc GMAC_CORE2_RESET>, -+ <&gcc GMAC_AHB_RESET>; -+ reset-names = "stmmaceth", "ahb"; - - status = "disabled"; - }; -@@ -1380,8 +1382,9 @@ - clocks = <&gcc GMAC_CORE3_CLK>; - clock-names = "stmmaceth"; - -- resets = <&gcc GMAC_CORE3_RESET>; -- reset-names = "stmmaceth"; -+ resets = <&gcc GMAC_CORE3_RESET>, -+ <&gcc GMAC_AHB_RESET>; -+ reset-names = "stmmaceth", "ahb"; - - status = "disabled"; - }; -@@ -1403,8 +1406,9 @@ - clocks = <&gcc GMAC_CORE4_CLK>; - clock-names = "stmmaceth"; - -- resets = <&gcc GMAC_CORE4_RESET>; -- reset-names = "stmmaceth"; -+ resets = <&gcc GMAC_CORE4_RESET>, -+ <&gcc GMAC_AHB_RESET>; -+ reset-names = "stmmaceth", "ahb"; - - status = "disabled"; - }; diff --git a/target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch deleted file mode 100644 index d433cb49b8..0000000000 --- a/target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch +++ /dev/null @@ -1,121 +0,0 @@ -From: Christian Lamparter -Subject: SoC: add qualcomm syscon ---- a/drivers/soc/qcom/Makefile -+++ b/drivers/soc/qcom/Makefile -@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o - obj-$(CONFIG_QCOM_SMSM) += smsm.o - obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o - obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o -+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o - obj-$(CONFIG_QCOM_APR) += apr.o - obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o - obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o ---- a/drivers/soc/qcom/Kconfig -+++ b/drivers/soc/qcom/Kconfig -@@ -191,6 +191,13 @@ config QCOM_SOCINFO - Say yes here to support the Qualcomm socinfo driver, providing - information about the SoC to user space. - -+config QCOM_TCSR -+ tristate "QCOM Top Control and Status Registers" -+ depends on ARCH_QCOM -+ help -+ Say y here to enable TCSR support. The TCSR provides control -+ functions for various peripherals. -+ - config QCOM_WCNSS_CTRL - tristate "Qualcomm WCNSS control driver" - depends on ARCH_QCOM || COMPILE_TEST ---- /dev/null -+++ b/drivers/soc/qcom/qcom_tcsr.c -@@ -0,0 +1,64 @@ -+/* -+ * Copyright (c) 2014, The Linux foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License rev 2 and -+ * only rev 2 as published by the free Software foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TCSR_USB_PORT_SEL 0xb0 -+ -+static int tcsr_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ const struct device_node *node = pdev->dev.of_node; -+ void __iomem *base; -+ u32 val; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) { -+ dev_err(&pdev->dev, "setting usb port select = %d\n", val); -+ writel(val, base + TCSR_USB_PORT_SEL); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id tcsr_dt_match[] = { -+ { .compatible = "qcom,tcsr", }, -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(of, tcsr_dt_match); -+ -+static struct platform_driver tcsr_driver = { -+ .driver = { -+ .name = "tcsr", -+ .owner = THIS_MODULE, -+ .of_match_table = tcsr_dt_match, -+ }, -+ .probe = tcsr_probe, -+}; -+ -+module_platform_driver(tcsr_driver); -+ -+MODULE_AUTHOR("Andy Gross "); -+MODULE_DESCRIPTION("QCOM TCSR driver"); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/include/dt-bindings/soc/qcom,tcsr.h -@@ -0,0 +1,23 @@ -+/* Copyright (c) 2014, The Linux Foundation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 and -+ * only version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+#ifndef __DT_BINDINGS_QCOM_TCSR_H -+#define __DT_BINDINGS_QCOM_TCSR_H -+ -+#define TCSR_USB_SELECT_USB3_P0 0x1 -+#define TCSR_USB_SELECT_USB3_P1 0x2 -+#define TCSR_USB_SELECT_USB3_DUAL 0x3 -+ -+/* TCSR A/B REG */ -+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0 -+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1 -+ -+#endif diff --git a/target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch deleted file mode 100644 index 3f43328961..0000000000 --- a/target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1790,6 +1790,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config CMDLINE - string "Default kernel command string" - default "" ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1058,6 +1058,17 @@ int __init early_init_dt_scan_chosen(uns - if (p != NULL && l > 0) - strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else - * managed to set the command line, unless CONFIG_CMDLINE_FORCE diff --git a/target/linux/kirkwood/config-5.10 b/target/linux/kirkwood/config-5.10 deleted file mode 100644 index 9c9afa4b62..0000000000 --- a/target/linux/kirkwood/config-5.10 +++ /dev/null @@ -1,293 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_CPU_AUTO=y -# CONFIG_ARCH_MULTI_V4 is not set -# CONFIG_ARCH_MULTI_V4T is not set -CONFIG_ARCH_MULTI_V4_V5=y -CONFIG_ARCH_MULTI_V5=y -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -# CONFIG_ARMADA_37XX_WATCHDOG is not set -# CONFIG_ARMADA_THERMAL is not set -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y -CONFIG_ARM_HAS_SG_CHAIN=y -# CONFIG_ARM_KIRKWOOD_CPUIDLE is not set -CONFIG_ARM_L1_CACHE_SHIFT=5 -# CONFIG_ARM_MVEBU_V7_CPUIDLE is not set -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_THUMB is not set -CONFIG_ARM_UNWIND=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_ATA_LEDS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_CACHE_FEROCEON_L2=y -# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_32v5=y -CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_FEROCEON=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FEROCEON=y -# CONFIG_CPU_FEROCEON_OLD_ID is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_PABRT_LEGACY=y -CONFIG_CPU_PM=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_FEROCEON=y -CONFIG_CPU_USE_DOMAINS=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_MARVELL=y -CONFIG_CRYPTO_DEV_MARVELL_CESA=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MVEBU_UART0_ALTERNATE=y -# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0xf1012000 -CONFIG_DEBUG_UART_VIRT=0xfed12000 -CONFIG_DEBUG_UNCOMPRESS=y -# CONFIG_DLCI is not set -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -# CONFIG_EARLY_PRINTK is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FORCE_PCI=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_MVEBU=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_OMAP=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MV64XXX=y -# CONFIG_I2C_PXA is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_KIRKWOOD_CLK=y -CONFIG_KIRKWOOD_THERMAL=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_NETXBIG=y -CONFIG_LEDS_NS2=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACH_KIRKWOOD=y -CONFIG_MACH_MVEBU_ANY=y -CONFIG_MANGLE_BOOTARGS=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -# CONFIG_MTD_NAND_MARVELL is not set -CONFIG_MTD_NAND_ORION=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MV643XX_ETH=y -CONFIG_MVEBU_CLK_COMMON=y -CONFIG_MVEBU_MBUS=y -CONFIG_MVMDIO=y -# CONFIG_MVNETA is not set -# CONFIG_MVPP2 is not set -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_KUSER_HELPERS=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MV88E6XXX=y -CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y -CONFIG_NET_DSA_TAG_DSA=y -CONFIG_NET_DSA_TAG_EDSA=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_ORION_IRQCHIP=y -CONFIG_ORION_TIMER=y -CONFIG_ORION_WATCHDOG=y -CONFIG_OUTER_CACHE=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCI_BRIDGE_EMUL=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MVEBU=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MVEBU_A3700_UTMI is not set -# CONFIG_PHY_MVEBU_A38X_COMPHY is not set -CONFIG_PHY_MVEBU_SATA=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_KIRKWOOD=y -CONFIG_PINCTRL_MVEBU=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_SX150X=y -CONFIG_PLAT_ORION=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_LINKSTATION=y -CONFIG_POWER_SUPPLY=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MV=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SATA_HOST=y -CONFIG_SATA_PMP=y -CONFIG_SCSI=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -# CONFIG_SERIAL_MVEBU_UART is not set -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SOC_BUS=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -# CONFIG_SPI_ARMADA_3700 is not set -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_ORION=y -CONFIG_SPLIT_PTLOCK_CPUS=999999 -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_LED_TRIG=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WAN=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/kirkwood/patches-5.10/100-ib62x0.patch b/target/linux/kirkwood/patches-5.10/100-ib62x0.patch deleted file mode 100644 index 0637c24b63..0000000000 --- a/target/linux/kirkwood/patches-5.10/100-ib62x0.patch +++ /dev/null @@ -1,53 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-ib62x0.dts -+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts -@@ -6,7 +6,14 @@ - - / { - model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; -- compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -+ compatible = "raidsonic,ib-nas62x0", "marvell,kirkwood-88f6281", "marvell,kirkwood"; -+ -+ aliases { -+ led-boot = &led_green_os; -+ led-failsafe = &led_red_os; -+ led-running = &led_green_os; -+ led-upgrade = &led_red_os; -+ }; - - memory { - device_type = "memory"; -@@ -81,12 +88,12 @@ - &pmx_led_usb_transfer>; - pinctrl-names = "default"; - -- green-os { -+ led_green_os: green-os { - label = "ib62x0:green:os"; - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; -- default-state = "keep"; -+ default-state = "on"; - }; -- red-os { -+ led_red_os: red-os { - label = "ib62x0:red:os"; - gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; - }; -@@ -118,13 +125,13 @@ - }; - - partition@100000 { -- label = "uImage"; -- reg = <0x0100000 0x600000>; -+ label = "second stage u-boot"; -+ reg = <0x100000 0x200000>; - }; - -- partition@700000 { -- label = "root"; -- reg = <0x0700000 0xf900000>; -+ partition@200000 { -+ label = "ubi"; -+ reg = <0x200000 0xfe00000>; - }; - - }; diff --git a/target/linux/kirkwood/patches-5.10/101-iconnect.patch b/target/linux/kirkwood/patches-5.10/101-iconnect.patch deleted file mode 100644 index 935e2dfcf5..0000000000 --- a/target/linux/kirkwood/patches-5.10/101-iconnect.patch +++ /dev/null @@ -1,80 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-iconnect.dts -+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts -@@ -8,6 +8,13 @@ - model = "Iomega Iconnect"; - compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - -+ aliases { -+ led-boot = &led_power_blue; -+ led-failsafe = &led_power_red; -+ led-running = &led_power_blue; -+ led-upgrade = &led_power_red; -+ }; -+ - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; -@@ -16,8 +23,6 @@ - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; -- linux,initrd-start = <0x4500040>; -- linux,initrd-end = <0x4800000>; - }; - - ocp@f1000000 { -@@ -89,12 +94,12 @@ - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; -- power-blue { -+ led_power_blue: power-blue { - label = "power:blue"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; -- default-state = "keep"; -+ default-state = "on"; - }; -- power-red { -+ led_power_red: power-red { - label = "power:red"; - gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; -@@ -146,28 +151,23 @@ - status = "okay"; - - partition@0 { -- label = "uboot"; -- reg = <0x0000000 0xc0000>; -+ label = "u-boot"; -+ reg = <0x0000000 0xe0000>; - }; - -- partition@a0000 { -- label = "env"; -- reg = <0xa0000 0x20000>; -+ partition@e0000 { -+ label = "u-boot environment"; -+ reg = <0xe0000 0x100000>; - }; - - partition@100000 { -- label = "zImage"; -- reg = <0x100000 0x300000>; -- }; -- -- partition@540000 { -- label = "initrd"; -- reg = <0x540000 0x300000>; -+ label = "second stage u-boot"; -+ reg = <0x100000 0x200000>; - }; - -- partition@980000 { -- label = "boot"; -- reg = <0x980000 0x1f400000>; -+ partition@200000 { -+ label = "ubi"; -+ reg = <0x200000 0x1fe00000>; - }; - }; - diff --git a/target/linux/kirkwood/patches-5.10/102-dockstar.patch b/target/linux/kirkwood/patches-5.10/102-dockstar.patch deleted file mode 100644 index 127f84962c..0000000000 --- a/target/linux/kirkwood/patches-5.10/102-dockstar.patch +++ /dev/null @@ -1,62 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-dockstar.dts -+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts -@@ -8,6 +8,13 @@ - model = "Seagate FreeAgent Dockstar"; - compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - -+ aliases { -+ led-boot = &led_health; -+ led-failsafe = &led_fault; -+ led-running = &led_health; -+ led-upgrade = &led_fault; -+ }; -+ - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; -@@ -42,12 +49,12 @@ - pinctrl-0 = <&pmx_led_green &pmx_led_orange>; - pinctrl-names = "default"; - -- health { -+ led_health: health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; -- default-state = "keep"; -+ default-state = "on"; - }; -- fault { -+ led_fault: fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; -@@ -78,18 +85,22 @@ - - partition@0 { - label = "u-boot"; -- reg = <0x0000000 0x100000>; -- read-only; -+ reg = <0x0000000 0xe0000>; -+ }; -+ -+ partition@e0000 { -+ label = "u-boot environment"; -+ reg = <0xe0000 0x100000>; - }; - - partition@100000 { -- label = "uImage"; -- reg = <0x0100000 0x400000>; -+ label = "second stage u-boot"; -+ reg = <0x100000 0x200000>; - }; - -- partition@500000 { -- label = "data"; -- reg = <0x0500000 0xfb00000>; -+ partition@200000 { -+ label = "ubi"; -+ reg = <0x200000 0xfe00000>; - }; - }; - diff --git a/target/linux/kirkwood/patches-5.10/103-iomega-ix2-200.patch b/target/linux/kirkwood/patches-5.10/103-iomega-ix2-200.patch deleted file mode 100644 index 9313b4bc3e..0000000000 --- a/target/linux/kirkwood/patches-5.10/103-iomega-ix2-200.patch +++ /dev/null @@ -1,67 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts -+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts -@@ -8,6 +8,13 @@ - model = "Iomega StorCenter ix2-200"; - compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - -+ aliases { -+ led-boot = &led_power; -+ led-failsafe = &led_health; -+ led-running = &led_power; -+ led-upgrade = &led_health; -+ }; -+ - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; -@@ -127,16 +134,16 @@ - &pmx_led_rebuild &pmx_led_health >; - pinctrl-names = "default"; - -- power_led { -+ led_power: power_led { - label = "status:white:power_led"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; -- default-state = "keep"; -+ default-state = "on"; - }; - rebuild_led { - label = "status:white:rebuild_led"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - }; -- health_led { -+ led_health: health_led { - label = "status:red:health_led"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; -@@ -186,18 +193,18 @@ - }; - - partition@a0000 { -- label = "env"; -+ label = "u-boot environment"; - reg = <0xa0000 0x20000>; - read-only; - }; - - partition@100000 { -- label = "uImage"; -+ label = "kernel"; - reg = <0x100000 0x300000>; - }; - - partition@400000 { -- label = "rootfs"; -+ label = "ubi"; - reg = <0x400000 0x1C00000>; - }; - }; -@@ -211,7 +218,7 @@ - }; - - ð0 { -- status = "okay"; -+ status = "disabled"; - ethernet0-port@0 { - speed = <1000>; - duplex = <1>; diff --git a/target/linux/kirkwood/patches-5.10/105-linksys-viper-dts.patch b/target/linux/kirkwood/patches-5.10/105-linksys-viper-dts.patch deleted file mode 100644 index d56a469d94..0000000000 --- a/target/linux/kirkwood/patches-5.10/105-linksys-viper-dts.patch +++ /dev/null @@ -1,59 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts -+++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts -@@ -24,6 +24,10 @@ - }; - - aliases { -+ led-boot = &led_white_health; -+ led-failsafe = &led_white_health; -+ led-running = &led_white_health; -+ led-upgrade = &led_white_health; - serial0 = &uart0; - }; - -@@ -56,9 +60,10 @@ - pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; - pinctrl-names = "default"; - -- white-health { -+ led_white_health: white-health { - label = "viper:white:health"; - gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; - }; - - white-pulse { -@@ -114,23 +119,23 @@ - }; - - partition@200000 { -- label = "kernel"; -- reg = <0x200000 0x2A0000>; -+ label = "kernel1"; -+ reg = <0x200000 0x1A00000>; - }; - -- partition@4a0000 { -- label = "rootfs"; -- reg = <0x4A0000 0x1760000>; -+ partition@500000 { -+ label = "rootfs1"; -+ reg = <0x500000 0x1700000>; - }; - - partition@1c00000 { -- label = "alt_kernel"; -- reg = <0x1C00000 0x2A0000>; -+ label = "kernel2"; -+ reg = <0x1C00000 0x1A00000>; - }; - -- partition@1ea0000 { -- label = "alt_rootfs"; -- reg = <0x1EA0000 0x1760000>; -+ partition@1f00000 { -+ label = "rootfs2"; -+ reg = <0x1F00000 0x1700000>; - }; - - partition@3600000 { diff --git a/target/linux/kirkwood/patches-5.10/106-goflexnet.patch b/target/linux/kirkwood/patches-5.10/106-goflexnet.patch deleted file mode 100644 index 82cf90841e..0000000000 --- a/target/linux/kirkwood/patches-5.10/106-goflexnet.patch +++ /dev/null @@ -1,53 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-goflexnet.dts -+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts -@@ -8,6 +8,13 @@ - model = "Seagate GoFlex Net"; - compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - -+ aliases { -+ led-boot = &led_health; -+ led-failsafe = &led_fault; -+ led-running = &led_health; -+ led-upgrade = &led_fault; -+ }; -+ - memory { - device_type = "memory"; - reg = <0x00000000 0x8000000>; -@@ -85,12 +92,12 @@ - >; - pinctrl-names = "default"; - -- health { -+ led_health: health { - label = "status:green:health"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; -- default-state = "keep"; -+ default-state = "on"; - }; -- fault { -+ led_fault: fault { - label = "status:orange:fault"; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; -@@ -159,18 +166,8 @@ - }; - - partition@100000 { -- label = "uImage"; -- reg = <0x0100000 0x400000>; -- }; -- -- partition@500000 { -- label = "pogoplug"; -- reg = <0x0500000 0x2000000>; -- }; -- -- partition@2500000 { -- label = "root"; -- reg = <0x02500000 0xd800000>; -+ label = "ubi"; -+ reg = <0x0100000 0x0ff00000>; - }; - }; - diff --git a/target/linux/kirkwood/patches-5.10/107-01-zyxel-nsa3x0-common-nand-partitions.patch b/target/linux/kirkwood/patches-5.10/107-01-zyxel-nsa3x0-common-nand-partitions.patch deleted file mode 100644 index df654033fd..0000000000 --- a/target/linux/kirkwood/patches-5.10/107-01-zyxel-nsa3x0-common-nand-partitions.patch +++ /dev/null @@ -1,48 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi -+++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi -@@ -112,40 +112,16 @@ - - partition@0 { - label = "uboot"; -- reg = <0x0000000 0x0100000>; -+ reg = <0x0000000 0x00c0000>; - read-only; - }; - partition@100000 { - label = "uboot_env"; -- reg = <0x0100000 0x0080000>; -+ reg = <0x00c0000 0x0080000>; - }; -- partition@180000 { -- label = "key_store"; -- reg = <0x0180000 0x0080000>; -- }; -- partition@200000 { -- label = "info"; -- reg = <0x0200000 0x0080000>; -- }; -- partition@280000 { -- label = "etc"; -- reg = <0x0280000 0x0a00000>; -- }; -- partition@c80000 { -- label = "kernel_1"; -- reg = <0x0c80000 0x0a00000>; -- }; -- partition@1680000 { -- label = "rootfs1"; -- reg = <0x1680000 0x2fc0000>; -- }; -- partition@4640000 { -- label = "kernel_2"; -- reg = <0x4640000 0x0a00000>; -- }; -- partition@5040000 { -- label = "rootfs2"; -- reg = <0x5040000 0x2fc0000>; -+ partition@140000 { -+ label = "ubi"; -+ reg = <0x0140000 0x7ec0000>; - }; - }; - diff --git a/target/linux/kirkwood/patches-5.10/107-03-nsa325.patch b/target/linux/kirkwood/patches-5.10/107-03-nsa325.patch deleted file mode 100644 index 374c0895a9..0000000000 --- a/target/linux/kirkwood/patches-5.10/107-03-nsa325.patch +++ /dev/null @@ -1,54 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-nsa325.dts -+++ b/arch/arm/boot/dts/kirkwood-nsa325.dts -@@ -15,6 +15,13 @@ - model = "ZyXEL NSA325"; - compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; - -+ aliases { -+ led-boot = &led_green_sys; -+ led-failsafe = &led_orange_sys; -+ led-running = &led_green_sys; -+ led-upgrade = &led_orange_sys; -+ }; -+ - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; -@@ -162,17 +169,19 @@ - &pmx_led_hdd1_green &pmx_led_hdd1_red>; - pinctrl-names = "default"; - -- green-sys { -+ led_green_sys: green-sys { - label = "nsa325:green:sys"; - gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; - }; -- orange-sys { -+ led_orange_sys: orange-sys { - label = "nsa325:orange:sys"; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - green-hdd1 { - label = "nsa325:green:hdd1"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "ata1"; - }; - red-hdd1 { - label = "nsa325:red:hdd1"; -@@ -181,6 +190,7 @@ - green-hdd2 { - label = "nsa325:green:hdd2"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "ata2"; - }; - red-hdd2 { - label = "nsa325:red:hdd2"; -@@ -189,6 +199,7 @@ - green-usb { - label = "nsa325:green:usb"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "usb-host"; - }; - green-copy { - label = "nsa325:green:copy"; diff --git a/target/linux/kirkwood/patches-5.10/109-pogoplug_v4.patch b/target/linux/kirkwood/patches-5.10/109-pogoplug_v4.patch deleted file mode 100644 index 4273eb9af1..0000000000 --- a/target/linux/kirkwood/patches-5.10/109-pogoplug_v4.patch +++ /dev/null @@ -1,87 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts -+++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts -@@ -18,12 +18,20 @@ - compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", - "marvell,kirkwood"; - -+ aliases { -+ led-boot = &led_health; -+ led-failsafe = &led_fault; -+ led-running = &led_health; -+ led-upgrade = &led_fault; -+ }; -+ - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - chosen { -+ bootargs = "console=ttyS0,115200"; - stdout-path = "uart0:115200n8"; - }; - -@@ -37,8 +45,8 @@ - eject { - debounce-interval = <50>; - wakeup-source; -- linux,code = ; -- label = "Eject Button"; -+ linux,code = ; -+ label = "Reset"; - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - }; - }; -@@ -48,12 +56,12 @@ - pinctrl-0 = <&pmx_led_green &pmx_led_red>; - pinctrl-names = "default"; - -- health { -+ led_health: health { - label = "pogoplugv4:green:health"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; -- fault { -+ led_fault: fault { - label = "pogoplugv4:red:fault"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - }; -@@ -137,29 +145,19 @@ - #size-cells = <1>; - - partition@0 { -- label = "u-boot"; -- reg = <0x00000000 0x200000>; -+ label = "uboot"; -+ reg = <0x00000000 0x1c0000>; - read-only; - }; - -- partition@200000 { -- label = "uImage"; -- reg = <0x00200000 0x300000>; -- }; -- -- partition@500000 { -- label = "uImage2"; -- reg = <0x00500000 0x300000>; -- }; -- -- partition@800000 { -- label = "failsafe"; -- reg = <0x00800000 0x800000>; -+ partition@1c0000 { -+ label = "uboot_env"; -+ reg = <0x001c0000 0x40000>; - }; - -- partition@1000000 { -- label = "root"; -- reg = <0x01000000 0x7000000>; -+ partition@200000 { -+ label = "ubi"; -+ reg = <0x00200000 0x7e00000>; - }; - }; - }; diff --git a/target/linux/kirkwood/patches-5.10/110-pogo_e02.patch b/target/linux/kirkwood/patches-5.10/110-pogo_e02.patch deleted file mode 100644 index fc384d3521..0000000000 --- a/target/linux/kirkwood/patches-5.10/110-pogo_e02.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-pogo_e02.dts -+++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts -@@ -20,6 +20,13 @@ - compatible = "cloudengines,pogoe02", "marvell,kirkwood-88f6281", - "marvell,kirkwood"; - -+ aliases { -+ led-boot = &led_health; -+ led-failsafe = &led_fault; -+ led-running = &led_health; -+ led-upgrade = &led_fault; -+ }; -+ - memory { - device_type = "memory"; - reg = <0x00000000 0x10000000>; -@@ -33,12 +40,12 @@ - gpio-leds { - compatible = "gpio-leds"; - -- health { -+ led_health: health { - label = "pogo_e02:green:health"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; -- default-state = "keep"; -+ default-state = "on"; - }; -- fault { -+ led_fault: fault { - label = "pogo_e02:orange:fault"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - }; -@@ -95,24 +102,24 @@ - status = "okay"; - - partition@0 { -- label = "u-boot"; -- reg = <0x0000000 0x100000>; -+ label = "uboot"; -+ reg = <0x0 0xe0000>; - read-only; - }; - -- partition@100000 { -- label = "uImage"; -- reg = <0x0100000 0x400000>; -+ partition@e0000 { -+ label = "uboot_env"; -+ reg = <0xe0000 0x20000>; - }; - -- partition@500000 { -- label = "pogoplug"; -- reg = <0x0500000 0x2000000>; -+ partition@100000 { -+ label = "second_stage_uboot"; -+ reg = <0x100000 0x100000>; - }; - -- partition@2500000 { -- label = "root"; -- reg = <0x02500000 0x5b00000>; -+ partition@200000 { -+ label = "ubi"; -+ reg = <0x200000 0x7e00000>; - }; - }; - diff --git a/target/linux/kirkwood/patches-5.10/111-l-50.patch b/target/linux/kirkwood/patches-5.10/111-l-50.patch deleted file mode 100644 index bc933cb610..0000000000 --- a/target/linux/kirkwood/patches-5.10/111-l-50.patch +++ /dev/null @@ -1,47 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-l-50.dts -+++ b/arch/arm/boot/dts/kirkwood-l-50.dts -@@ -18,6 +18,13 @@ - reg = <0x00000000 0x20000000>; - }; - -+ aliases { -+ led-boot = &led_status_green; -+ led-failsafe = &led_status_red; -+ led-running = &led_status_green; -+ led-upgrade = &led_status_red; -+ }; -+ - chosen { - bootargs = "console=ttyS0,115200n8"; - stdout-path = &uart0; -@@ -95,12 +102,12 @@ - leds { - compatible = "gpio-leds"; - -- status_green { -+ led_status_green: status_green { - label = "l-50:green:status"; - gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; - -- status_red { -+ led_status_red: status_red { - label = "l-50:red:status"; - gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; - }; -@@ -349,13 +356,8 @@ - }; - - partition@100000 { -- label = "kernel-1"; -- reg = <0x00100000 0x00800000>; -- }; -- -- partition@900000 { -- label = "rootfs-1"; -- reg = <0x00900000 0x07100000>; -+ label = "ubi"; -+ reg = <0x00100000 0x07900000>; - }; - - partition@7a00000 { diff --git a/target/linux/kirkwood/patches-5.10/112-sheevaplug.patch b/target/linux/kirkwood/patches-5.10/112-sheevaplug.patch deleted file mode 100644 index d1ff9884a0..0000000000 --- a/target/linux/kirkwood/patches-5.10/112-sheevaplug.patch +++ /dev/null @@ -1,47 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi -+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi -@@ -78,13 +78,8 @@ - }; - - partition@100000 { -- label = "uImage"; -- reg = <0x0100000 0x400000>; -- }; -- -- partition@500000 { -- label = "root"; -- reg = <0x0500000 0x1fb00000>; -+ label = "ubi"; -+ reg = <0x0100000 0x1ff00000>; - }; - }; - ---- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts -+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts -@@ -13,6 +13,13 @@ - model = "Globalscale Technologies SheevaPlug"; - compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - -+ aliases { -+ led-boot = &led_health; -+ led-failsafe = &led_health; -+ led-running = &led_health; -+ led-upgrade = &led_health; -+ }; -+ - ocp@f1000000 { - mvsdio@90000 { - pinctrl-0 = <&pmx_sdio>; -@@ -28,10 +35,10 @@ - pinctrl-0 = <&pmx_led_blue &pmx_led_red>; - pinctrl-names = "default"; - -- health { -+ led_health: health { - label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; -- default-state = "keep"; -+ default-state = "on"; - }; - - misc { diff --git a/target/linux/kirkwood/patches-5.10/113-readynas_duo_v2.patch b/target/linux/kirkwood/patches-5.10/113-readynas_duo_v2.patch deleted file mode 100644 index c6452c55a3..0000000000 --- a/target/linux/kirkwood/patches-5.10/113-readynas_duo_v2.patch +++ /dev/null @@ -1,76 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts -+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts -@@ -19,6 +19,13 @@ - reg = <0x00000000 0x10000000>; - }; - -+ aliases { -+ led-boot = &led_power; -+ led-failsafe = &led_power; -+ led-running = &led_power; -+ led-upgrade = &led_power; -+ }; -+ - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; -@@ -115,7 +122,7 @@ - &pmx_led_blue_backup >; - pinctrl-names = "default"; - -- power_led { -+ led_power: power_led { - label = "status:blue:power_led"; - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - default-state = "keep"; -@@ -129,11 +136,13 @@ - disk1_led { - label = "status:blue:disk1_led"; - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "ata1"; - }; - - disk2_led { - label = "status:blue:disk2_led"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "ata2"; - }; - - backup_led { -@@ -150,7 +159,13 @@ - - power-button { - label = "Power Button"; -- linux,code = ; -+ /* Power button and INT pin from PHY are both connected -+ * to this GPIO. Every network restart causes PHY restart -+ * and button is pressed. It's difficult to use it as -+ * KEY_POWER without changes in kernel (or netifd) so -+ * the button is configured as regular one. -+ */ -+ linux,code = ; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; - -@@ -208,18 +223,13 @@ - }; - - partition@200000 { -- label = "uImage"; -+ label = "kernel"; - reg = <0x0200000 0x600000>; - }; - - partition@800000 { -- label = "minirootfs"; -- reg = <0x0800000 0x1000000>; -- }; -- -- partition@1800000 { -- label = "jffs2"; -- reg = <0x1800000 0x6800000>; -+ label = "ubi"; -+ reg = <0x0800000 0x7800000>; - }; - }; - diff --git a/target/linux/kirkwood/patches-5.10/201-enable-sata-port-specific-led-triggers.patch b/target/linux/kirkwood/patches-5.10/201-enable-sata-port-specific-led-triggers.patch deleted file mode 100644 index 35db065727..0000000000 --- a/target/linux/kirkwood/patches-5.10/201-enable-sata-port-specific-led-triggers.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/mach-mvebu/Kconfig -+++ b/arch/arm/mach-mvebu/Kconfig -@@ -116,6 +116,7 @@ config MACH_DOVE - config MACH_KIRKWOOD - bool "Marvell Kirkwood boards" - depends on ARCH_MULTI_V5 -+ select ARCH_WANT_LIBATA_LEDS - select CPU_FEROCEON - select GPIOLIB - select KIRKWOOD_CLK diff --git a/target/linux/kirkwood/patches-5.10/202-linksys-find-active-root.patch b/target/linux/kirkwood/patches-5.10/202-linksys-find-active-root.patch deleted file mode 100644 index 515bb21707..0000000000 --- a/target/linux/kirkwood/patches-5.10/202-linksys-find-active-root.patch +++ /dev/null @@ -1,62 +0,0 @@ -The WRT1900AC among other Linksys routers uses a dual-firmware layout. -Dynamically rename the active partition to "ubi". - -Signed-off-by: Imre Kaloz ---- ---- a/drivers/mtd/parsers/ofpart_core.c -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d - return of_get_property(pp, "compatible", NULL); - } - -+static int mangled_rootblock; -+ - static int parse_fixed_partitions(struct mtd_info *master, - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) -@@ -47,6 +49,7 @@ static int parse_fixed_partitions(struct - struct mtd_partition *parts; - struct device_node *mtd_node; - struct device_node *ofpart_node; -+ const char *owrtpart = "ubi"; - const char *partname; - struct device_node *pp; - int nr_parts, i, ret = 0; -@@ -133,9 +136,15 @@ static int parse_fixed_partitions(struct - parts[i].size = of_read_number(reg + a_cells, s_cells); - parts[i].of_node = pp; - -- partname = of_get_property(pp, "label", &len); -- if (!partname) -- partname = of_get_property(pp, "name", &len); -+ if (mangled_rootblock && (i == mangled_rootblock)) { -+ partname = owrtpart; -+ } else { -+ partname = of_get_property(pp, "label", &len); -+ -+ if (!partname) -+ partname = of_get_property(pp, "name", &len); -+ } -+ - parts[i].name = partname; - - if (of_get_property(pp, "read-only", &len)) -@@ -252,6 +261,18 @@ static int __init ofpart_parser_init(voi - return 0; - } - -+static int __init active_root(char *str) -+{ -+ get_option(&str, &mangled_rootblock); -+ -+ if (!mangled_rootblock) -+ return 1; -+ -+ return 1; -+} -+ -+__setup("mangled_rootblock=", active_root); -+ - static void __exit ofpart_parser_exit(void) - { - deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/kirkwood/patches-5.10/203-blackarmor-nas220.patch b/target/linux/kirkwood/patches-5.10/203-blackarmor-nas220.patch deleted file mode 100644 index e04a28206a..0000000000 --- a/target/linux/kirkwood/patches-5.10/203-blackarmor-nas220.patch +++ /dev/null @@ -1,99 +0,0 @@ ---- a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts -+++ b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts -@@ -17,6 +17,13 @@ - compatible = "seagate,blackarmor-nas220","marvell,kirkwood-88f6192", - "marvell,kirkwood"; - -+ aliases { -+ led-boot = &led_status_amber; -+ led-failsafe = &led_status_amber; -+ led-running = &led_status_blue; -+ led-upgrade = &led_status_amber; -+ }; -+ - memory { /* 128 MB */ - device_type = "memory"; - reg = <0x00000000 0x8000000>; -@@ -36,14 +43,14 @@ - compatible = "gpio-keys"; - - reset { -- label = "Reset"; -- linux,code = ; -+ label = "Reset Button"; -+ linux,code = ; - gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; - }; - -- button { -- label = "Power"; -- linux,code = ; -+ power { -+ label = "Power Button"; -+ linux,code = ; - gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - }; - }; -@@ -51,11 +58,27 @@ - gpio-leds { - compatible = "gpio-leds"; - -- blue-power { -+ led_power_blue: power_blue { - label = "nas220:blue:power"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; -+ -+ disk_blue { -+ label = "nas220:blue:disk"; -+ gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; -+ linux,default-trigger = "disk-activity"; -+ }; -+ -+ led_status_blue: status_blue { -+ label = "nas220:blue:status"; -+ gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led_status_amber: status_amber { -+ label = "nas220:amber:status"; -+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; -+ }; - }; - - regulators { -@@ -153,6 +176,33 @@ - - &nand { - status = "okay"; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ -+ partition@0 { -+ label = "uboot"; -+ reg = <0x0 0xa0000>; -+ read-only; -+ }; -+ -+ partition@a0000 { -+ label = "uboot-env"; -+ reg = <0xa0000 0x10000>; -+ read-only; -+ }; -+ -+ partition@b0000 { -+ label = "reserved"; -+ reg = <0xb0000 0x10000>; -+ read-only; -+ }; -+ -+ partition@c0000 { -+ label = "ubi"; -+ reg = <0xc0000 0x1e80000>; -+ }; -+ }; - }; - - &mdio { diff --git a/target/linux/kirkwood/patches-5.10/800-power-reset-linkstation-poweroff-prepare-for-new-dev.patch b/target/linux/kirkwood/patches-5.10/800-power-reset-linkstation-poweroff-prepare-for-new-dev.patch deleted file mode 100644 index 4b4d03839a..0000000000 --- a/target/linux/kirkwood/patches-5.10/800-power-reset-linkstation-poweroff-prepare-for-new-dev.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 11cab9f5cd9390cd83747e579957c8f5b807c09c Mon Sep 17 00:00:00 2001 -From: Pawel Dembicki -Date: Fri, 18 Jun 2021 12:37:27 +0200 -Subject: [PATCH 1/2] power: reset: linkstation-poweroff: prepare for new - devices - -This commit prepare driver for another device support. - -New power_off_cfg structure describes two most important things: name of -mdio bus and pointer to register setting function. It allow to add new -device with different mdio bus node and other phy register config. - -Signed-off-by: Pawel Dembicki ---- - drivers/power/reset/linkstation-poweroff.c | 35 ++++++++++++++++++---- - 1 file changed, 29 insertions(+), 6 deletions(-) - ---- a/drivers/power/reset/linkstation-poweroff.c -+++ b/drivers/power/reset/linkstation-poweroff.c -@@ -29,11 +29,21 @@ - #define LED2_FORCE_ON (0x8 << 8) - #define LEDMASK GENMASK(11,8) - -+struct power_off_cfg { -+ char *mdio_node_name; -+ void (*phy_set_reg)(bool restart); -+}; -+ - static struct phy_device *phydev; -+static const struct power_off_cfg *cfg; - --static void mvphy_reg_intn(u16 data) -+static void linkstation_mvphy_reg_intn(bool restart) - { - int rc = 0, saved_page; -+ u16 data = 0; -+ -+ if(restart) -+ data = MII_88E1318S_PHY_LED_TCR_FORCE_INT; - - saved_page = phy_select_page(phydev, MII_MARVELL_LED_PAGE); - if (saved_page < 0) -@@ -66,11 +76,16 @@ err: - dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc); - } - -+static const struct power_off_cfg linkstation_power_off_cfg = { -+ .mdio_node_name = "mdio", -+ .phy_set_reg = linkstation_mvphy_reg_intn, -+}; -+ - static int linkstation_reboot_notifier(struct notifier_block *nb, - unsigned long action, void *unused) - { - if (action == SYS_RESTART) -- mvphy_reg_intn(MII_88E1318S_PHY_LED_TCR_FORCE_INT); -+ cfg->phy_set_reg(true); - - return NOTIFY_DONE; - } -@@ -82,14 +97,18 @@ static struct notifier_block linkstation - static void linkstation_poweroff(void) - { - unregister_reboot_notifier(&linkstation_reboot_nb); -- mvphy_reg_intn(0); -+ cfg->phy_set_reg(false); - - kernel_restart("Power off"); - } - - static const struct of_device_id ls_poweroff_of_match[] = { -- { .compatible = "buffalo,ls421d" }, -- { .compatible = "buffalo,ls421de" }, -+ { .compatible = "buffalo,ls421d", -+ .data = &linkstation_power_off_cfg, -+ }, -+ { .compatible = "buffalo,ls421de", -+ .data = &linkstation_power_off_cfg, -+ }, - { }, - }; - -@@ -97,13 +116,17 @@ static int __init linkstation_poweroff_i - { - struct mii_bus *bus; - struct device_node *dn; -+ const struct of_device_id *match; - - dn = of_find_matching_node(NULL, ls_poweroff_of_match); - if (!dn) - return -ENODEV; - of_node_put(dn); - -- dn = of_find_node_by_name(NULL, "mdio"); -+ match = of_match_node(ls_poweroff_of_match, dn); -+ cfg = match->data; -+ -+ dn = of_find_node_by_name(NULL, cfg->mdio_node_name); - if (!dn) - return -ENODEV; - diff --git a/target/linux/kirkwood/patches-5.10/801-power-reset-linkstation-poweroff-add-new-device.patch b/target/linux/kirkwood/patches-5.10/801-power-reset-linkstation-poweroff-add-new-device.patch deleted file mode 100644 index a929aacfd0..0000000000 --- a/target/linux/kirkwood/patches-5.10/801-power-reset-linkstation-poweroff-add-new-device.patch +++ /dev/null @@ -1,97 +0,0 @@ -From a2d9c86df8d12646f5bf66920e4f1e6d940cfc62 Mon Sep 17 00:00:00 2001 -From: Pawel Dembicki -Date: Fri, 18 Jun 2021 13:25:33 +0200 -Subject: [PATCH 2/2] power: reset: linkstation-poweroff: add new device - -This commit introduces support for NETGEAR ReadyNAS Duo v2. -This device use bit 4 of LED[2:0] Polarity Control Register to indicate -AC Power loss. - -For more details about AC loss detection in NETGEAR ReadyNAS Duo v2, -please look at the file: -RND_5.3.13_WW.src/u-boot/board/mv_feroceon/mv_hal/usibootup/usibootup.c -from Netgear GPL sources. - -Signed-off-by: Pawel Dembicki ---- - drivers/power/reset/linkstation-poweroff.c | 43 ++++++++++++++++++++++ - 1 file changed, 43 insertions(+) - ---- a/drivers/power/reset/linkstation-poweroff.c -+++ b/drivers/power/reset/linkstation-poweroff.c -@@ -19,6 +19,7 @@ - #define MII_MARVELL_PHY_PAGE 22 - - #define MII_PHY_LED_CTRL 16 -+#define MII_PHY_LED_POL_CTRL 17 - #define MII_88E1318S_PHY_LED_TCR 18 - #define MII_88E1318S_PHY_WOL_CTRL 16 - #define MII_M1011_IEVENT 19 -@@ -29,6 +30,8 @@ - #define LED2_FORCE_ON (0x8 << 8) - #define LEDMASK GENMASK(11,8) - -+#define MII_88E1318S_PHY_LED_POL_LED2 BIT(4) -+ - struct power_off_cfg { - char *mdio_node_name; - void (*phy_set_reg)(bool restart); -@@ -76,11 +79,48 @@ err: - dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc); - } - -+static void readynas_mvphy_set_reg(bool restart) -+{ -+ int rc = 0, saved_page; -+ u16 data = 0; -+ -+ if(restart) -+ data = MII_88E1318S_PHY_LED_POL_LED2; -+ -+ saved_page = phy_select_page(phydev, MII_MARVELL_LED_PAGE); -+ if (saved_page < 0) -+ goto err; -+ -+ /* Set the LED[2].0 Polarity bit to the required state */ -+ __phy_modify(phydev, MII_PHY_LED_POL_CTRL, -+ MII_88E1318S_PHY_LED_POL_LED2, data); -+ -+ if (!data) { -+ -+ /* If WOL was enabled and a magic packet was received before powering -+ * off, we won't be able to wake up by sending another magic packet. -+ * Clear WOL status. -+ */ -+ __phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_MARVELL_WOL_PAGE); -+ __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL, -+ MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS); -+ } -+err: -+ rc = phy_restore_page(phydev, saved_page, rc); -+ if (rc < 0) -+ dev_err(&phydev->mdio.dev, "Write register failed, %d\n", rc); -+} -+ - static const struct power_off_cfg linkstation_power_off_cfg = { - .mdio_node_name = "mdio", - .phy_set_reg = linkstation_mvphy_reg_intn, - }; - -+static const struct power_off_cfg readynas_power_off_cfg = { -+ .mdio_node_name = "mdio-bus", -+ .phy_set_reg = readynas_mvphy_set_reg, -+}; -+ - static int linkstation_reboot_notifier(struct notifier_block *nb, - unsigned long action, void *unused) - { -@@ -109,6 +149,9 @@ static const struct of_device_id ls_powe - { .compatible = "buffalo,ls421de", - .data = &linkstation_power_off_cfg, - }, -+ { .compatible = "netgear,readynas-duo-v2", -+ .data = &readynas_power_off_cfg, -+ }, - { }, - }; - diff --git a/target/linux/lantiq/ase/config-5.10 b/target/linux/lantiq/ase/config-5.10 deleted file mode 100644 index 195e49df69..0000000000 --- a/target/linux/lantiq/ase/config-5.10 +++ /dev/null @@ -1,25 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -CONFIG_CPU_MIPSR1=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HW_RANDOM=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_ETOP=y -CONFIG_NLS=y -CONFIG_SGL_ALLOC=y -CONFIG_SOC_AMAZON_SE=y -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SWCONFIG=y -CONFIG_TARGET_ISA_REV=1 -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/config-5.10 b/target/linux/lantiq/config-5.10 deleted file mode 100644 index c37a543e1e..0000000000 --- a/target/linux/lantiq/config-5.10 +++ /dev/null @@ -1,225 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y -CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y -CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y -CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_USE_MEMREMAP_PROT=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_LOAD_STORE_LR=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y -CONFIG_DTC=y -# CONFIG_DT_EASY50712 is not set -CONFIG_EARLY_PRINTK=y -CONFIG_EFI_EARLYCON=y -CONFIG_FIXED_PHY=y -CONFIG_FONT_8x16=y -CONFIG_FONT_AUTOSELECT=y -CONFIG_FONT_SUPPORT=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_MM_LANTIQ=y -CONFIG_GPIO_STP_XWAY=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARCH_COMPILER_H=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ASM_MODVERSIONS=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_COPY_THREAD_TLS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FAST_GUP=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_VDSO=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PCI=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LANTIQ=y -CONFIG_LANTIQ_DT_NONE=y -# CONFIG_LANTIQ_ETOP is not set -CONFIG_LANTIQ_WDT=y -# CONFIG_LANTIQ_XRX200 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_CORE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_LANTIQ=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_BRNIMAGE_FW=y -CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -# CONFIG_PCIE_LANTIQ is not set -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_LANTIQ_RCU_USB2=y -# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_LANTIQ=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_XWAY=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_LANTIQ=y -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_LANTIQ=y -CONFIG_SERIAL_LANTIQ_CONSOLE=y -# CONFIG_SOC_AMAZON_SE is not set -# CONFIG_SOC_FALCON is not set -# CONFIG_SOC_XWAY is not set -CONFIG_SPI=y -CONFIG_SPI_LANTIQ_SSC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_VPE_LOADER=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/lantiq/falcon/config-5.10 b/target/linux/lantiq/falcon/config-5.10 deleted file mode 100644 index 3041c65dbd..0000000000 --- a/target/linux/lantiq/falcon/config-5.10 +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_CPU_HAS_DIEI=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" -CONFIG_PINCTRL_FALCON=y -CONFIG_SOC_FALCON=y -CONFIG_SPI_FALCON=y diff --git a/target/linux/lantiq/patches-5.10/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-5.10/0001-MIPS-lantiq-add-pcie-driver.patch deleted file mode 100644 index 9068be5d4a..0000000000 --- a/target/linux/lantiq/patches-5.10/0001-MIPS-lantiq-add-pcie-driver.patch +++ /dev/null @@ -1,5507 +0,0 @@ -From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:12:28 +0200 -Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/Kconfig | 10 + - arch/mips/lantiq/xway/sysctrl.c | 2 + - arch/mips/pci/Makefile | 2 + - arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ - arch/mips/pci/fixup-lantiq.c | 5 +- - arch/mips/pci/ifxmips_pci_common.h | 57 ++ - arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ - arch/mips/pci/ifxmips_pcie.h | 135 ++++ - arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ - arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ - arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ - arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ - arch/mips/pci/ifxmips_pcie_pm.h | 36 + - arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ - arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ - arch/mips/pci/pci.c | 25 + - arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ - drivers/pci/pcie/aer/Kconfig | 2 +- - include/linux/pci.h | 2 + - include/linux/pci_ids.h | 6 + - 20 files changed, 5374 insertions(+), 2 deletions(-) - create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c - create mode 100644 arch/mips/pci/ifxmips_pci_common.h - create mode 100644 arch/mips/pci/ifxmips_pcie.c - create mode 100644 arch/mips/pci/ifxmips_pcie.h - create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h - create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c - create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c - create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c - create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h - create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h - create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h - create mode 100644 arch/mips/pci/pcie-lantiq.h - ---- a/arch/mips/lantiq/Kconfig -+++ b/arch/mips/lantiq/Kconfig -@@ -20,6 +20,7 @@ config SOC_XWAY - bool "XWAY" - select SOC_TYPE_XWAY - select HAVE_PCI -+ select ARCH_SUPPORTS_MSI - select MFD_SYSCON - select MFD_CORE - -@@ -52,4 +53,13 @@ config PCI_LANTIQ - bool "PCI Support" - depends on SOC_XWAY && PCI - -+config PCIE_LANTIQ -+ bool "PCIE Support" -+ depends on SOC_XWAY && PCI -+ -+config PCIE_LANTIQ_MSI -+ bool -+ depends on PCIE_LANTIQ && PCI_MSI -+ default y -+ - endif ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -43,6 +43,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o - obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o - obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o - obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o -+obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o -+obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o - obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o ---- /dev/null -+++ b/arch/mips/pci/fixup-lantiq-pcie.c -@@ -0,0 +1,74 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_fixup_pcie.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \file ifxmips_fixup_pcie.c -+ \ingroup IFX_PCIE -+ \brief PCIe Fixup functions source file -+*/ -+#include -+#include -+#include -+ -+#include -+ -+#include "pcie-lantiq.h" -+ -+static void -+ifx_pcie_fixup_resource(struct pci_dev *dev) -+{ -+ u32 reg; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); -+ -+ printk("%s: fixup host controller %s (%04x:%04x)\n", -+ __func__, pci_name(dev), dev->vendor, dev->device); -+ -+ /* Setup COMMAND register */ -+ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | -+ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; -+ pci_write_config_word(dev, PCI_COMMAND, reg); -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); -+ -+static void -+ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); -+ -+ if (dev->devfn == PCI_DEVFN(0, 0) && -+ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { -+ -+ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); -+ -+ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); -+ } -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -+ mdelay(10); -+} -+ -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, -+ ifx_pcie_rc_class_early_fixup); -+ -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, -+ ifx_pcie_rc_class_early_fixup); ---- a/arch/mips/pci/fixup-lantiq.c -+++ b/arch/mips/pci/fixup-lantiq.c -@@ -6,12 +6,19 @@ - - #include - #include -+#include -+#include "ifxmips_pci_common.h" - - int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; - int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; - - int pcibios_plat_dev_init(struct pci_dev *dev) - { -+#ifdef CONFIG_PCIE_LANTIQ -+ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) -+ ifx_pcie_bios_plat_dev_init(dev); -+#endif -+ - if (ltq_pci_plat_arch_init) - return ltq_pci_plat_arch_init(dev); - -@@ -23,5 +30,10 @@ int pcibios_plat_dev_init(struct pci_dev - - int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) - { -+#ifdef CONFIG_PCIE_LANTIQ -+ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) -+ return ifx_pcie_bios_map_irq(dev, slot, pin); -+#endif -+ - return of_irq_parse_and_map_pci(dev, slot, pin); - } ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pci_common.h -@@ -0,0 +1,53 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pci_common.h -+** PROJECT : IFX UEIP -+** MODULES : PCI subsystem -+** -+** DATE : 30 June 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 30 June,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+ -+#ifndef IFXMIPS_PCI_COMMON_H -+#define IFXMIPS_PCI_COMMON_H -+#include -+/*! -+ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration -+ \brief PCI/PCIe common parts -+*/ -+ -+/*! -+ \defgroup IFX_PCI_COM_OS OS APIs -+ \ingroup IFX_PCI_COM -+ \brief PCI/PCIe bus driver OS interface functions -+*/ -+/*! -+ \file ifxmips_pci_common.h -+ \ingroup IFX_PCI_COM -+ \brief PCI/PCIe bus driver common OS header file -+*/ -+#define IFX_PCI_CONST const -+#ifdef CONFIG_IFX_PCI -+extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); -+extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); -+#endif /* COFNIG_IFX_PCI */ -+ -+#ifdef CONFIG_PCIE_LANTIQ -+extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); -+extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); -+#endif -+ -+#endif /* IFXMIPS_PCI_COMMON_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie.c -@@ -0,0 +1,1092 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2009 Lei Chuanhua -+ * Copyright (C) 2013 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ifxmips_pcie.h" -+#include "ifxmips_pcie_reg.h" -+ -+/* Enable 32bit io due to its mem mapped io nature */ -+#define IFX_PCIE_ERROR_INT -+#define IFX_PCIE_IO_32BIT -+ -+#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) -+#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) -+#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) -+#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) -+#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) -+#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) -+#define SM(_v, _f) (((_v) << _f##_S) & (_f)) -+#define IFX_REG_SET_BIT(_f, _r) \ -+ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) -+ -+#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 -+ -+static DEFINE_SPINLOCK(ifx_pcie_lock); -+ -+u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); -+ -+static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { -+ { -+ .ir_irq = { -+ .irq = IFX_PCIE_IR, -+ .name = "ifx_pcie_rc0", -+ }, -+ -+ .legacy_irq = { -+ { -+ .irq_bit = PCIE_IRN_INTA, -+ .irq = IFX_PCIE_INTA, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTB, -+ .irq = IFX_PCIE_INTB, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTC, -+ .irq = IFX_PCIE_INTC, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTD, -+ .irq = IFX_PCIE_INTD, -+ }, -+ }, -+ }, -+ -+}; -+ -+void ifx_pcie_debug(const char *fmt, ...) -+{ -+ static char buf[256] = {0}; /* XXX */ -+ va_list ap; -+ -+ va_start(ap, fmt); -+ vsnprintf(buf, sizeof(buf), fmt, ap); -+ va_end(ap); -+ -+ printk("%s", buf); -+} -+ -+ -+static inline int pcie_ltssm_enable(int pcie_port) -+{ -+ int i; -+ -+ /* Enable LTSSM */ -+ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); -+ -+ /* Wait for the link to come up */ -+ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { -+ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) -+ return 0; -+ udelay(10); -+ } -+ -+ printk("%s link timeout!!!!!\n", __func__); -+ return -1; -+} -+ -+static inline void pcie_status_register_clear(int pcie_port) -+{ -+ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); -+ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); -+ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); -+ IFX_REG_W32(0, PCIE_UESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_CESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); -+ IFX_REG_W32(0, PCIE_RESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); -+ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); -+ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_QSR(pcie_port)); -+ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); -+} -+ -+static inline int ifx_pcie_link_up(int pcie_port) -+{ -+ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; -+} -+ -+ -+static inline void pcie_mem_io_setup(int pcie_port) -+{ -+ u32 reg; -+ /* -+ * BAR[0:1] readonly register -+ * RC contains only minimal BARs for packets mapped to this device -+ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that -+ * reside on the downstream side fo the bridge. -+ */ -+ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) -+ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); -+ -+ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); -+ -+ -+#ifdef IFX_PCIE_PREFETCH_MEM_64BIT -+ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) -+ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) -+ | PCIE_PMBL_64BIT_ADDR; -+ IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); -+ -+ /* Must configure upper 32bit */ -+ IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); -+ IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); -+#else -+ /* PCIe_PBML, same as MBML */ -+ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); -+#endif -+ -+ /* IO Address Range */ -+ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) -+ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); -+#ifdef IFX_PCIE_IO_32BIT -+ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; -+#endif /* IFX_PCIE_IO_32BIT */ -+ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); -+ -+#ifdef IFX_PCIE_IO_32BIT -+ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) -+ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); -+ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); -+ -+#endif /* IFX_PCIE_IO_32BIT */ -+} -+ -+static inline void -+pcie_device_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Device capability register, set up Maximum payload size */ -+ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); -+ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; -+ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); -+ -+ /* Only available for EP */ -+ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); -+ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); -+ -+ /* Device control and status register */ -+ /* Set Maximum Read Request size for the device as a Requestor */ -+ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); -+ -+ /* -+ * Request size can be larger than the MPS used, but the completions returned -+ * for the read will be bounded by the MPS size. -+ * In our system, Max request size depends on AHB burst size. It is 64 bytes. -+ * but we set it as 128 as minimum one. -+ */ -+ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) -+ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); -+ -+ /* Enable relaxed ordering, no snoop, and all kinds of errors */ -+ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; -+ -+ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); -+} -+ -+static inline void -+pcie_link_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* -+ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM -+ * L0s is reported during link training via TS1 order set by N_FTS -+ */ -+ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); -+ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; -+ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); -+ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); -+ -+ /* Link control and status register */ -+ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); -+ -+ /* Link Enable, ASPM enabled */ -+ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; -+ -+#ifdef CONFIG_PCIEASPM -+ /* -+ * We use the same physical reference clock that the platform provides on the connector -+ * It paved the way for ASPM to calculate the new exit Latency -+ */ -+ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; -+ reg |= PCIE_LCTLSTS_COM_CLK_CFG; -+ /* -+ * We should disable ASPM by default except that we have dedicated power management support -+ * Enable ASPM will cause the system hangup/instability, performance degration -+ */ -+ reg |= PCIE_LCTLSTS_ASPM_ENABLE; -+#else -+ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; -+#endif /* CONFIG_PCIEASPM */ -+ -+ /* -+ * The maximum size of any completion with data packet is bounded by the MPS setting -+ * in device control register -+ */ -+ -+ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ -+ reg &= ~ PCIE_LCTLSTS_RCB128; -+ -+ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); -+} -+ -+static inline void pcie_error_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* -+ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone -+ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE -+ */ -+ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); -+ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; -+ -+ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); -+ -+ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ -+ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); -+ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; -+ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); -+ -+ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ -+ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); -+ -+ /* Correctable Error Mask Register, unmask all bits */ -+ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); -+ reg &= ~PCIE_CORRECTABLE_ERR; -+ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); -+ -+ /* Advanced Error Capabilities and Control Registr */ -+ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); -+ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; -+ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); -+ -+ /* Root Error Command Register, Report all types of errors */ -+ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); -+ reg |= PCIE_RECR_ERR_REPORT_EN; -+ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); -+ -+ /* Clear the Root status register */ -+ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); -+ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); -+} -+ -+static inline void pcie_port_logic_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ -+ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); -+ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); -+ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) -+ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); -+ /* L0s and L1 entry latency */ -+ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); -+ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) -+ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); -+ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); -+ -+ -+ /* Port Link Control Register */ -+ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); -+ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ -+ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); -+ -+ /* Lane Skew Register */ -+ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); -+ /* Enable ACK/NACK and FC */ -+ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); -+ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); -+ -+ /* Symbol Timer Register and Filter Mask Register 1 */ -+ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); -+ -+ /* Default SKP interval is very accurate already, 5us */ -+ /* Enable IO/CFG transaction */ -+ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; -+ /* Disable FC WDT */ -+ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; -+ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); -+ -+ /* Filter Masker Register 2 */ -+ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); -+ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; -+ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); -+ -+ /* VC0 Completion Receive Queue Control Register */ -+ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); -+ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; -+ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); -+ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); -+} -+ -+static inline void pcie_rc_cfg_reg_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Disable LTSSM */ -+ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ -+ -+ pcie_mem_io_setup(pcie_port); -+ -+ /* XXX, MSI stuff should only apply to EP */ -+ /* MSI Capability: Only enable 32-bit addresses */ -+ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); -+ reg &= ~PCIE_MCAPR_ADDR64_CAP; -+ -+ reg |= PCIE_MCAPR_MSI_ENABLE; -+ -+ /* Disable multiple message */ -+ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); -+ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); -+ -+ -+ /* Enable PME, Soft reset enabled */ -+ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); -+ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; -+ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); -+ -+ /* setup the bus */ -+ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); -+ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); -+ -+ -+ pcie_device_setup(pcie_port); -+ pcie_link_setup(pcie_port); -+ pcie_error_setup(pcie_port); -+ -+ /* Root control and capabilities register */ -+ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); -+ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; -+ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); -+ -+ /* Port VC Capability Register 2 */ -+ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); -+ reg &= ~PCIE_PVC2_VC_ARB_WRR; -+ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; -+ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); -+ -+ /* VC0 Resource Capability Register */ -+ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); -+ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; -+ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); -+ -+ pcie_port_logic_setup(pcie_port); -+} -+ -+static int ifx_pcie_wait_phy_link_up(int pcie_port) -+{ -+#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ -+ int i; -+ -+ /* Wait for PHY link is up */ -+ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { -+ if (ifx_pcie_link_up(pcie_port)) { -+ break; -+ } -+ udelay(100); -+ } -+ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { -+ printk(KERN_ERR "%s timeout\n", __func__); -+ return -1; -+ } -+ -+ /* Check data link up or not */ -+ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { -+ printk(KERN_ERR "%s DLL link is still down\n", __func__); -+ return -1; -+ } -+ -+ /* Check Data link active or not */ -+ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { -+ printk(KERN_ERR "%s DLL is not active\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static inline int pcie_app_loigc_setup(int pcie_port) -+{ -+ /* supress ahb bus errrors */ -+ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); -+ -+ /* Pull PCIe EP out of reset */ -+ pcie_device_rst_deassert(pcie_port); -+ -+ /* Start LTSSM training between RC and EP */ -+ pcie_ltssm_enable(pcie_port); -+ -+ /* Check PHY status after enabling LTSSM */ -+ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) -+ return -1; -+ -+ return 0; -+} -+ -+/* -+ * The numbers below are directly from the PCIe spec table 3-4/5. -+ */ -+static inline void pcie_replay_time_update(int pcie_port) -+{ -+ u32 reg; -+ int nlw; -+ int rtl; -+ -+ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); -+ -+ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); -+ switch (nlw) { -+ case PCIE_MAX_LENGTH_WIDTH_X1: -+ rtl = 1677; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X2: -+ rtl = 867; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X4: -+ rtl = 462; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X8: -+ rtl = 258; -+ break; -+ default: -+ rtl = 1677; -+ break; -+ } -+ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); -+ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; -+ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); -+ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); -+} -+ -+/* -+ * Table 359 Enhanced Configuration Address Mapping1) -+ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 -+ * Memory Address PCI Express Configuration Space -+ * A[(20+n-1):20] Bus Number 1 < n < 8 -+ * A[19:15] Device Number -+ * A[14:12] Function Number -+ * A[11:8] Extended Register Number -+ * A[7:2] Register Number -+ * A[1:0] Along with size of the access, used to generate Byte Enables -+ * For VR9, only the address bits [22:0] are mapped to the configuration space: -+ * . Address bits [22:20] select the target bus (1-of-8)1) -+ * . Address bits [19:15] select the target device (1-of-32) on the bus -+ * . Address bits [14:12] select the target function (1-of-8) within the device. -+ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space -+ * . Address bits [1:0] define the start byte location within the selected dword. -+ */ -+static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) -+{ -+ u32 addr; -+ u8 bus; -+ -+ if (!bus_num) { -+ /* type 0 */ -+ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); -+ } else { -+ bus = bus_num; -+ /* type 1, only support 8 buses */ -+ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | -+ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); -+ } -+ return addr; -+} -+ -+static int pcie_valid_config(int pcie_port, int bus, int dev) -+{ -+ /* RC itself */ -+ if ((bus == 0) && (dev == 0)) { -+ return 1; -+ } -+ -+ /* No physical link */ -+ if (!ifx_pcie_link_up(pcie_port)) { -+ return 0; -+ } -+ -+ /* Bus zero only has RC itself -+ * XXX, check if EP will be integrated -+ */ -+ if ((bus == 0) && (dev != 0)) { -+ return 0; -+ } -+ -+ /* Maximum 8 buses supported for VRX */ -+ if (bus > 9) { -+ return 0; -+ } -+ -+ /* -+ * PCIe is PtP link, one bus only supports only one device -+ * except bus zero and PCIe switch which is virtual bus device -+ * The following two conditions really depends on the system design -+ * and attached the device. -+ * XXX, how about more new switch -+ */ -+ if ((bus == 1) && (dev != 0)) { -+ return 0; -+ } -+ -+ if ((bus >= 3) && (dev != 0)) { -+ return 0; -+ } -+ return 1; -+} -+ -+static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) -+{ -+ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) -+{ -+ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) -+{ -+ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) -+{ -+ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) -+{ -+ u32 tvalue = value; -+ -+ if (where == PCI_PRIMARY_BUS) { -+ u8 primary, secondary, subordinate; -+ -+ primary = tvalue & 0xFF; -+ secondary = (tvalue >> 8) & 0xFF; -+ subordinate = (tvalue >> 16) & 0xFF; -+ primary += pcibios_1st_host_bus_nr(); -+ secondary += pcibios_1st_host_bus_nr(); -+ subordinate += pcibios_1st_host_bus_nr(); -+ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); -+ } -+ return tvalue; -+} -+ -+u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) -+{ -+ u32 tvalue = value; -+ -+ if (where == PCI_PRIMARY_BUS) { -+ u8 primary, secondary, subordinate; -+ -+ primary = tvalue & 0xFF; -+ secondary = (tvalue >> 8) & 0xFF; -+ subordinate = (tvalue >> 16) & 0xFF; -+ if (primary > 0 && primary != 0xFF) { -+ primary -= pcibios_1st_host_bus_nr(); -+ } -+ -+ if (secondary > 0 && secondary != 0xFF) { -+ secondary -= pcibios_1st_host_bus_nr(); -+ } -+ if (subordinate > 0 && subordinate != 0xFF) { -+ subordinate -= pcibios_1st_host_bus_nr(); -+ } -+ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); -+ } -+ else if (where == PCI_SUBORDINATE_BUS) { -+ u8 subordinate = tvalue & 0xFF; -+ -+ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; -+ tvalue = subordinate; -+ } -+ return tvalue; -+} -+ -+static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, -+ int where, int size, u32 *value) -+{ -+ u32 data = 0; -+ int bus_number = bus->number; -+ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; -+ int ret = PCIBIOS_SUCCESSFUL; -+ struct ifx_pci_controller *ctrl = bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ if (unlikely(size != 1 && size != 2 && size != 4)){ -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ -+ /* Make sure the address is aligned to natural boundary */ -+ if (unlikely(((size - 1) & where))) { -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ -+ /* -+ * If we are second controller, we have to cheat OS so that it assume -+ * its bus number starts from 0 in host controller -+ */ -+ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); -+ -+ /* -+ * We need to force the bus number to be zero on the root -+ * bus. Linux numbers the 2nd root bus to start after all -+ * busses on root 0. -+ */ -+ if (bus->parent == NULL) { -+ bus_number = 0; -+ } -+ -+ /* -+ * PCIe only has a single device connected to it. It is -+ * always device ID 0. Don't bother doing reads for other -+ * device IDs on the first segment. -+ */ -+ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { -+ ret = PCIBIOS_FUNC_NOT_SUPPORTED; -+ goto out; -+ } -+ -+ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { -+ *value = 0xffffffff; -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ goto out; -+ } -+ -+ PCIE_IRQ_LOCK(ifx_pcie_lock); -+ if (bus_number == 0) { /* RC itself */ -+ u32 t; -+ -+ t = (where & ~3); -+ data = ifx_pcie_rc_cfg_rd(pcie_port, t); -+ } else { -+ u32 addr = pcie_bus_addr(bus_number, devfn, where); -+ -+ data = ifx_pcie_cfg_rd(pcie_port, addr); -+ #ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = le32_to_cpu(data); -+ #endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ } -+ /* To get a correct PCI topology, we have to restore the bus number to OS */ -+ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); -+ -+ PCIE_IRQ_UNLOCK(ifx_pcie_lock); -+ -+ *value = (data >> (8 * (where & 3))) & mask[size & 7]; -+out: -+ return ret; -+} -+ -+static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) -+{ -+ u32 shift; -+ u32 tdata = data; -+ -+ switch (size) { -+ case 1: -+ shift = (where & 0x3) << 3; -+ tdata &= ~(0xffU << shift); -+ tdata |= ((value & 0xffU) << shift); -+ break; -+ case 2: -+ shift = (where & 3) << 3; -+ tdata &= ~(0xffffU << shift); -+ tdata |= ((value & 0xffffU) << shift); -+ break; -+ case 4: -+ tdata = value; -+ break; -+ } -+ return tdata; -+} -+ -+static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, -+ int where, int size, u32 value) -+{ -+ int bus_number = bus->number; -+ int ret = PCIBIOS_SUCCESSFUL; -+ struct ifx_pci_controller *ctrl = bus->sysdata; -+ int pcie_port = ctrl->port; -+ u32 tvalue = value; -+ u32 data; -+ -+ /* Make sure the address is aligned to natural boundary */ -+ if (unlikely(((size - 1) & where))) { -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ /* -+ * If we are second controller, we have to cheat OS so that it assume -+ * its bus number starts from 0 in host controller -+ */ -+ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); -+ -+ /* -+ * We need to force the bus number to be zero on the root -+ * bus. Linux numbers the 2nd root bus to start after all -+ * busses on root 0. -+ */ -+ if (bus->parent == NULL) { -+ bus_number = 0; -+ } -+ -+ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ goto out; -+ } -+ -+ /* XXX, some PCIe device may need some delay */ -+ PCIE_IRQ_LOCK(ifx_pcie_lock); -+ -+ /* -+ * To configure the correct bus topology using native way, we have to cheat Os so that -+ * it can configure the PCIe hardware correctly. -+ */ -+ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); -+ -+ if (bus_number == 0) { /* RC itself */ -+ u32 t; -+ -+ t = (where & ~3); -+ data = ifx_pcie_rc_cfg_rd(pcie_port, t); -+ -+ data = ifx_pcie_size_to_value(where, size, data, tvalue); -+ -+ ifx_pcie_rc_cfg_wr(pcie_port, t, data); -+ } else { -+ u32 addr = pcie_bus_addr(bus_number, devfn, where); -+ -+ data = ifx_pcie_cfg_rd(pcie_port, addr); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = le32_to_cpu(data); -+#endif -+ -+ data = ifx_pcie_size_to_value(where, size, data, tvalue); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = cpu_to_le32(data); -+#endif -+ ifx_pcie_cfg_wr(pcie_port, addr, data); -+ } -+ PCIE_IRQ_UNLOCK(ifx_pcie_lock); -+out: -+ return ret; -+} -+ -+static struct resource ifx_pcie_io_resource = { -+ .name = "PCIe0 I/O space", -+ .start = PCIE_IO_PHY_BASE, -+ .end = PCIE_IO_PHY_END, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ifx_pcie_mem_resource = { -+ .name = "PCIe0 Memory space", -+ .start = PCIE_MEM_PHY_BASE, -+ .end = PCIE_MEM_PHY_END, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct pci_ops ifx_pcie_ops = { -+ .read = ifx_pcie_read_config, -+ .write = ifx_pcie_write_config, -+}; -+ -+static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { -+ { -+ .pcic = { -+ .pci_ops = &ifx_pcie_ops, -+ .mem_resource = &ifx_pcie_mem_resource, -+ .io_resource = &ifx_pcie_io_resource, -+ }, -+ .port = IFX_PCIE_PORT0, -+ }, -+}; -+ -+#ifdef IFX_PCIE_ERROR_INT -+ -+static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) -+{ -+ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; -+ int pcie_port = ctrl->port; -+ u32 reg; -+ -+ pr_debug("PCIe RC error intr %d\n", irq); -+ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); -+ reg &= PCIE_RC_CORE_COMBINED_INT; -+ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); -+ -+ return IRQ_HANDLED; -+} -+ -+static int -+pcie_rc_core_int_init(int pcie_port) -+{ -+ int ret; -+ -+ /* Enable core interrupt */ -+ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); -+ -+ /* Clear it first */ -+ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); -+ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, -+ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); -+ if (ret) -+ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); -+ -+ return ret; -+} -+#endif -+ -+int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ u32 irq_bit = 0; -+ int irq = 0; -+ struct ifx_pci_controller *ctrl = dev->bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); -+ -+ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { -+ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); -+ return -1; -+ } -+ -+ /* Pin index so minus one */ -+ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; -+ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; -+ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); -+ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); -+ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); -+ return irq; -+} -+ -+int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) -+{ -+ u16 config; -+#ifdef IFX_PCIE_ERROR_INT -+ u32 dconfig; -+ int pos; -+#endif -+ -+ /* Enable reporting System errors and parity errors on all devices */ -+ /* Enable parity checking and error reporting */ -+ pci_read_config_word(dev, PCI_COMMAND, &config); -+ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | -+ PCI_COMMAND_FAST_BACK*/; -+ pci_write_config_word(dev, PCI_COMMAND, config); -+ -+ if (dev->subordinate) { -+ /* Set latency timers on sub bridges */ -+ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ -+ /* More bridge error detection */ -+ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); -+ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; -+ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); -+ } -+#ifdef IFX_PCIE_ERROR_INT -+ /* Enable the PCIe normal error reporting */ -+ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); -+ if (pos) { -+ -+ /* Disable system error generation in response to error messages */ -+ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); -+ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); -+ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); -+ -+ /* Clear PCIE Capability's Device Status */ -+ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); -+ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); -+ -+ /* Update Device Control */ -+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); -+ /* Correctable Error Reporting */ -+ config |= PCI_EXP_DEVCTL_CERE; -+ /* Non-Fatal Error Reporting */ -+ config |= PCI_EXP_DEVCTL_NFERE; -+ /* Fatal Error Reporting */ -+ config |= PCI_EXP_DEVCTL_FERE; -+ /* Unsupported Request */ -+ config |= PCI_EXP_DEVCTL_URRE; -+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); -+ } -+ -+ /* Find the Advanced Error Reporting capability */ -+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); -+ if (pos) { -+ /* Clear Uncorrectable Error Status */ -+ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); -+ /* Enable reporting of all uncorrectable errors */ -+ /* Uncorrectable Error Mask - turned on bits disable errors */ -+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); -+ /* -+ * Leave severity at HW default. This only controls if -+ * errors are reported as uncorrectable or -+ * correctable, not if the error is reported. -+ */ -+ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ -+ /* Clear Correctable Error Status */ -+ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); -+ /* Enable reporting of all correctable errors */ -+ /* Correctable Error Mask - turned on bits disable errors */ -+ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); -+ /* Advanced Error Capabilities */ -+ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); -+ /* ECRC Generation Enable */ -+ if (dconfig & PCI_ERR_CAP_ECRC_GENC) { -+ dconfig |= PCI_ERR_CAP_ECRC_GENE; -+ } -+ /* ECRC Check Enable */ -+ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { -+ dconfig |= PCI_ERR_CAP_ECRC_CHKE; -+ } -+ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); -+ -+ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ -+ /* Enable Root Port's interrupt in response to error messages */ -+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, -+ PCI_ERR_ROOT_CMD_COR_EN | -+ PCI_ERR_ROOT_CMD_NONFATAL_EN | -+ PCI_ERR_ROOT_CMD_FATAL_EN); -+ /* Clear the Root status register */ -+ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); -+ } -+#endif /* IFX_PCIE_ERROR_INT */ -+ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ -+ pcie_set_readrq(dev, 128); -+ return 0; -+} -+ -+static int -+pcie_rc_initialize(int pcie_port) -+{ -+ int i; -+#define IFX_PCIE_PHY_LOOP_CNT 5 -+ -+ pcie_rcu_endian_setup(pcie_port); -+ -+ pcie_ep_gpio_rst_init(pcie_port); -+ -+ /* -+ * XXX, PCIe elastic buffer bug will cause not to be detected. One more -+ * reset PCIe PHY will solve this issue -+ */ -+ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { -+ /* Disable PCIe PHY Analog part for sanity check */ -+ pcie_phy_pmu_disable(pcie_port); -+ -+ pcie_phy_rst_assert(pcie_port); -+ pcie_phy_rst_deassert(pcie_port); -+ -+ /* Make sure PHY PLL is stable */ -+ udelay(20); -+ -+ /* PCIe Core reset enabled, low active, sw programmed */ -+ pcie_core_rst_assert(pcie_port); -+ -+ /* Put PCIe EP in reset status */ -+ pcie_device_rst_assert(pcie_port); -+ -+ /* PCI PHY & Core reset disabled, high active, sw programmed */ -+ pcie_core_rst_deassert(pcie_port); -+ -+ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ -+ pcie_phy_clock_mode_setup(pcie_port); -+ -+ /* Enable PCIe PHY and Clock */ -+ pcie_core_pmu_setup(pcie_port); -+ -+ /* Clear status registers */ -+ pcie_status_register_clear(pcie_port); -+ -+#ifdef CONFIG_PCI_MSI -+ pcie_msi_init(pcie_port); -+#endif /* CONFIG_PCI_MSI */ -+ pcie_rc_cfg_reg_setup(pcie_port); -+ -+ /* Once link is up, break out */ -+ if (pcie_app_loigc_setup(pcie_port) == 0) -+ break; -+ } -+ if (i >= IFX_PCIE_PHY_LOOP_CNT) { -+ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); -+ return -EIO; -+ } -+ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ -+ pcie_replay_time_update(pcie_port); -+ return 0; -+} -+ -+static int __init ifx_pcie_bios_init(void) -+{ -+ void __iomem *io_map_base; -+ int pcie_port; -+ int startup_port; -+ -+ /* Enable AHB Master/ Slave */ -+ pcie_ahb_pmu_setup(); -+ -+ startup_port = IFX_PCIE_PORT0; -+ -+ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ -+ if (pcie_rc_initialize(pcie_port) == 0) { -+ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", -+ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); -+ /* Otherwise, warning will pop up */ -+ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); -+ if (io_map_base == NULL) { -+ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); -+ return -ENOMEM; -+ } -+ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; -+ -+ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); -+ /* XXX, clear error status */ -+ -+ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", -+ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, -+ &ifx_pcie_controller[pcie_port].pcic.io_resource); -+ -+ #ifdef IFX_PCIE_ERROR_INT -+ pcie_rc_core_int_init(pcie_port); -+ #endif /* IFX_PCIE_ERROR_INT */ -+ } -+ } -+ -+ return 0; -+} -+arch_initcall(ifx_pcie_bios_init); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -+MODULE_SUPPORTED_DEVICE("Infineon builtin PCIe RC module"); -+MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie.h -@@ -0,0 +1,131 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_H -+#define IFXMIPS_PCIE_H -+#include -+#include -+#include -+#include -+#include "ifxmips_pci_common.h" -+#include "ifxmips_pcie_reg.h" -+ -+/*! -+ \defgroup IFX_PCIE PCI Express bus driver module -+ \brief PCI Express IP module support VRX200 -+*/ -+ -+/*! -+ \defgroup IFX_PCIE_OS OS APIs -+ \ingroup IFX_PCIE -+ \brief PCIe bus driver OS interface functions -+*/ -+ -+/*! -+ \file ifxmips_pcie.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module common header file -+*/ -+#define PCIE_IRQ_LOCK(lock) do { \ -+ unsigned long flags; \ -+ spin_lock_irqsave(&(lock), flags); -+#define PCIE_IRQ_UNLOCK(lock) \ -+ spin_unlock_irqrestore(&(lock), flags); \ -+} while (0) -+ -+#define PCIE_MSG_MSI 0x00000001 -+#define PCIE_MSG_ISR 0x00000002 -+#define PCIE_MSG_FIXUP 0x00000004 -+#define PCIE_MSG_READ_CFG 0x00000008 -+#define PCIE_MSG_WRITE_CFG 0x00000010 -+#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) -+#define PCIE_MSG_REG 0x00000020 -+#define PCIE_MSG_INIT 0x00000040 -+#define PCIE_MSG_ERR 0x00000080 -+#define PCIE_MSG_PHY 0x00000100 -+#define PCIE_MSG_ANY 0x000001ff -+ -+#define IFX_PCIE_PORT0 0 -+#define IFX_PCIE_PORT1 1 -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+#define IFX_PCIE_CORE_NR 2 -+#else -+#define IFX_PCIE_CORE_NR 1 -+#endif -+ -+#define IFX_PCIE_ERROR_INT -+ -+//#define IFX_PCIE_DBG -+ -+#if defined(IFX_PCIE_DBG) -+#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ -+ ifx_pcie_debug((_fmt), ##args); \ -+} while (0) -+ -+#define INLINE -+#else -+#define IFX_PCIE_PRINT(_m, _fmt, args...) \ -+ do {} while(0) -+#define INLINE inline -+#endif -+ -+struct ifx_pci_controller { -+ struct pci_controller pcic; -+ -+ /* RC specific, per host bus information */ -+ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ -+}; -+ -+typedef struct ifx_pcie_ir_irq { -+ const unsigned int irq; -+ const char name[16]; -+}ifx_pcie_ir_irq_t; -+ -+typedef struct ifx_pcie_legacy_irq{ -+ const u32 irq_bit; -+ const int irq; -+}ifx_pcie_legacy_irq_t; -+ -+typedef struct ifx_pcie_irq { -+ ifx_pcie_ir_irq_t ir_irq; -+ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; -+}ifx_pcie_irq_t; -+ -+extern u32 g_pcie_debug_flag; -+extern void ifx_pcie_debug(const char *fmt, ...); -+extern void pcie_phy_clock_mode_setup(int pcie_port); -+extern void pcie_msi_pic_init(int pcie_port); -+extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); -+extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); -+ -+#define CONFIG_VR9 -+ -+#ifdef CONFIG_VR9 -+#include "ifxmips_pcie_vr9.h" -+#elif defined (CONFIG_AR10) -+#include "ifxmips_pcie_ar10.h" -+#else -+#error "PCIE: platform not defined" -+#endif /* CONFIG_VR9 */ -+ -+#endif /* IFXMIPS_PCIE_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_ar10.h -@@ -0,0 +1,290 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ *****************************************************************************/ -+/*! -+ \file ifxmips_pcie_ar10.h -+ \ingroup IFX_PCIE -+ \brief PCIe RC driver ar10 specific file -+*/ -+ -+#ifndef IFXMIPS_PCIE_AR10_H -+#define IFXMIPS_PCIE_AR10_H -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif /* AUTOCONF_INCLUDED */ -+#include -+#include -+ -+/* Project header file */ -+#include -+#include -+#include -+#include -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+ ifx_ebu_led_enable(); -+ if (pcie_port == 0) { -+ ifx_ebu_led_set_data(11, 1); -+ } -+ else { -+ ifx_ebu_led_set_data(12, 1); -+ } -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ /* XXX, moved to CGU to control AHBM */ -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+ /* Inbound, big endian */ -+ reg |= IFX_RCU_BE_AHB4S; -+ if (pcie_port == 0) { -+ reg |= IFX_RCU_BE_PCIE0M; -+ -+ #ifdef CONFIG_IFX_PCIE_HW_SWAP -+ /* Outbound, software swap needed */ -+ reg |= IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE0S; -+ #else -+ /* Outbound little endian */ -+ reg &= ~IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE0S; -+ #endif -+ } -+ else { -+ reg |= IFX_RCU_BE_PCIE1M; -+ #ifdef CONFIG_IFX_PCIE1_HW_SWAP -+ /* Outbound, software swap needed */ -+ reg |= IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE1S; -+ #else -+ /* Outbound little endian */ -+ reg &= ~IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE1S; -+ #endif -+ } -+ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ if (pcie_port == 0) { /* XXX, should use macro*/ -+ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline void pcie_phy_pmu_disable(int pcie_port) -+{ -+ if (pcie_port == 0) { /* XXX, should use macro*/ -+ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+ } -+ else { -+ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+ } -+} -+ -+static inline void pcie_pdi_big_endian(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+ if (pcie_port == 0) { -+ /* Config AHB->PCIe and PDI endianness */ -+ reg |= IFX_RCU_BE_PCIE0_PDI; -+ } -+ else { -+ /* Config AHB->PCIe and PDI endianness */ -+ reg |= IFX_RCU_BE_PCIE1_PDI; -+ } -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ if (pcie_port == 0) { -+ /* Enable PDI to access PCIe PHY register */ -+ PDI0_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ PDI1_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline void pcie_core_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ -+ /* Reset Core, bit 22 */ -+ if (pcie_port == 0) { -+ reg |= 0x00400000; -+ } -+ else { -+ reg |= 0x08000000; /* Bit 27 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_core_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ if (pcie_port == 0) { -+ reg &= ~0x00400000; /* bit 22 */ -+ } -+ else { -+ reg &= ~0x08000000; /* Bit 27 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ if (pcie_port == 0) { -+ reg |= 0x00001000; /* Bit 12 */ -+ } -+ else { -+ reg |= 0x00002000; /* Bit 13 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ if (pcie_port == 0) { -+ reg &= ~0x00001000; /* Bit 12 */ -+ } -+ else { -+ reg &= ~0x00002000; /* Bit 13 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_device_rst_assert(int pcie_port) -+{ -+ if (pcie_port == 0) { -+ ifx_ebu_led_set_data(11, 0); -+ } -+ else { -+ ifx_ebu_led_set_data(12, 0); -+ } -+} -+ -+static inline void pcie_device_rst_deassert(int pcie_port) -+{ -+ mdelay(100); -+ if (pcie_port == 0) { -+ ifx_ebu_led_set_data(11, 1); -+ } -+ else { -+ ifx_ebu_led_set_data(12, 1); -+ } -+ ifx_ebu_led_disable(); -+} -+ -+static inline void pcie_core_pmu_setup(int pcie_port) -+{ -+ if (pcie_port == 0) { -+ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline void pcie_msi_init(int pcie_port) -+{ -+ pcie_msi_pic_init(pcie_port); -+ if (pcie_port == 0) { -+ MSI0_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ MSI1_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline u32 -+ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) -+{ -+ u32 tbus_number = bus_number; -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ -+ if (pcibios_host_nr() > 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+ } -+#endif /* CONFIG_IFX_PCI */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_IFX_PCIE_2ND_CORE -+ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ } -+ #endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_IFX_PCIE_2ND_CORE -+ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_AR10_H */ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_msi.c -@@ -0,0 +1,392 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_msi.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCI MSI sub module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe MSI Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Date $Author $Comment -+** 02 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \defgroup IFX_PCIE_MSI MSI OS APIs -+ \ingroup IFX_PCIE -+ \brief PCIe bus driver OS interface functions -+*/ -+ -+/*! -+ \file ifxmips_pcie_msi.c -+ \ingroup IFX_PCIE -+ \brief PCIe MSI OS interface file -+*/ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif /* AUTOCONF_INCLUDED */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "ifxmips_pcie_reg.h" -+#include "ifxmips_pcie.h" -+ -+#define IFX_MSI_IRQ_NUM 16 -+ -+enum { -+ IFX_PCIE_MSI_IDX0 = 0, -+ IFX_PCIE_MSI_IDX1, -+ IFX_PCIE_MSI_IDX2, -+ IFX_PCIE_MSI_IDX3, -+}; -+ -+typedef struct ifx_msi_irq_idx { -+ const int irq; -+ const int idx; -+}ifx_msi_irq_idx_t; -+ -+struct ifx_msi_pic { -+ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; -+ volatile u32 pic_endian; /* 0x40 */ -+}; -+typedef struct ifx_msi_pic *ifx_msi_pic_t; -+ -+typedef struct ifx_msi_irq { -+ const volatile ifx_msi_pic_t msi_pic_p; -+ const u32 msi_phy_base; -+ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; -+ /* -+ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is -+ * in use. -+ */ -+ u16 msi_free_irq_bitmask; -+ -+ /* -+ * Each bit in msi_multiple_irq_bitmask tells that the device using -+ * this bit in msi_free_irq_bitmask is also using the next bit. This -+ * is used so we can disable all of the MSI interrupts when a device -+ * uses multiple. -+ */ -+ u16 msi_multiple_irq_bitmask; -+}ifx_msi_irq_t; -+ -+static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { -+ { -+ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, -+ .msi_phy_base = PCIE_MSI_PHY_BASE, -+ .msi_irq_idx = { -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ }, -+ .msi_free_irq_bitmask = 0, -+ .msi_multiple_irq_bitmask= 0, -+ }, -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ { -+ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, -+ .msi_phy_base = PCIE1_MSI_PHY_BASE, -+ .msi_irq_idx = { -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ }, -+ .msi_free_irq_bitmask = 0, -+ .msi_multiple_irq_bitmask= 0, -+ -+ }, -+#endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+}; -+ -+/* -+ * This lock controls updates to msi_free_irq_bitmask, -+ * msi_multiple_irq_bitmask and pic register settting -+ */ -+static DEFINE_SPINLOCK(ifx_pcie_msi_lock); -+ -+void pcie_msi_pic_init(int pcie_port) -+{ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; -+ spin_unlock(&ifx_pcie_msi_lock); -+} -+ -+/** -+ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -+ * \brief Called when a driver request MSI interrupts instead of the -+ * legacy INT A-D. This routine will allocate multiple interrupts -+ * for MSI devices that support them. A device can override this by -+ * programming the MSI control bits [6:4] before calling -+ * pci_enable_msi(). -+ * -+ * \param[in] pdev Device requesting MSI interrupts -+ * \param[in] desc MSI descriptor -+ * -+ * \return -EINVAL Invalid pcie root port or invalid msi bit -+ * \return 0 OK -+ * \ingroup IFX_PCIE_MSI -+ */ -+int -+arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -+{ -+ int irq, pos; -+ u16 control; -+ int irq_idx; -+ int irq_step; -+ int configured_private_bits; -+ int request_private_bits; -+ struct msi_msg msg; -+ u16 search_mask; -+ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); -+ -+ /* XXX, skip RC MSI itself */ -+ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); -+ return -EINVAL; -+ } -+ -+ /* -+ * Read the MSI config to figure out how many IRQs this device -+ * wants. Most devices only want 1, which will give -+ * configured_private_bits and request_private_bits equal 0. -+ */ -+ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); -+ -+ /* -+ * If the number of private bits has been configured then use -+ * that value instead of the requested number. This gives the -+ * driver the chance to override the number of interrupts -+ * before calling pci_enable_msi(). -+ */ -+ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; -+ if (configured_private_bits == 0) { -+ /* Nothing is configured, so use the hardware requested size */ -+ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; -+ } -+ else { -+ /* -+ * Use the number of configured bits, assuming the -+ * driver wanted to override the hardware request -+ * value. -+ */ -+ request_private_bits = configured_private_bits; -+ } -+ -+ /* -+ * The PCI 2.3 spec mandates that there are at most 32 -+ * interrupts. If this device asks for more, only give it one. -+ */ -+ if (request_private_bits > 5) { -+ request_private_bits = 0; -+ } -+again: -+ /* -+ * The IRQs have to be aligned on a power of two based on the -+ * number being requested. -+ */ -+ irq_step = (1 << request_private_bits); -+ -+ /* Mask with one bit for each IRQ */ -+ search_mask = (1 << irq_step) - 1; -+ -+ /* -+ * We're going to search msi_free_irq_bitmask_lock for zero -+ * bits. This represents an MSI interrupt number that isn't in -+ * use. -+ */ -+ spin_lock(&ifx_pcie_msi_lock); -+ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { -+ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { -+ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; -+ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; -+ break; -+ } -+ } -+ spin_unlock(&ifx_pcie_msi_lock); -+ -+ /* Make sure the search for available interrupts didn't fail */ -+ if (pos >= IFX_MSI_IRQ_NUM) { -+ if (request_private_bits) { -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " -+ "interrupts, trying just one", __func__, 1 << request_private_bits); -+ request_private_bits = 0; -+ goto again; -+ } -+ else { -+ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); -+ return -EINVAL; -+ } -+ } -+ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; -+ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); -+ -+ /* -+ * Initialize MSI. This has to match the memory-write endianess from the device -+ * Address bits [23:12] -+ */ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | -+ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | -+ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); -+ -+ /* Enable this entry */ -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; -+ spin_unlock(&ifx_pcie_msi_lock); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", -+ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); -+ -+ /* Update the number of IRQs the device has available to it */ -+ control &= ~PCI_MSI_FLAGS_QSIZE; -+ control |= (request_private_bits << 4); -+ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); -+ -+ set_irq_msi(irq, desc); -+ msg.address_hi = 0x0; -+ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; -+ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); -+ -+ write_msi_msg(irq, &msg); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); -+ return 0; -+} -+ -+static int -+pcie_msi_irq_to_port(unsigned int irq, int *port) -+{ -+ int ret = 0; -+ -+ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || -+ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { -+ *port = IFX_PCIE_PORT0; -+ } -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || -+ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { -+ *port = IFX_PCIE_PORT1; -+ } -+#endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+ else { -+ printk(KERN_ERR "%s: Attempted to teardown illegal " -+ "MSI interrupt (%d)\n", __func__, irq); -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+/** -+ * \fn void arch_teardown_msi_irq(unsigned int irq) -+ * \brief Called when a device no longer needs its MSI interrupts. All -+ * MSI interrupts for the device are freed. -+ * -+ * \param irq The devices first irq number. There may be multple in sequence. -+ * \return none -+ * \ingroup IFX_PCIE_MSI -+ */ -+void -+arch_teardown_msi_irq(unsigned int irq) -+{ -+ int pos; -+ int number_irqs; -+ u16 bitmask; -+ int pcie_port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); -+ -+ BUG_ON(irq > INT_NUM_IM4_IRL31); -+ -+ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { -+ return; -+ } -+ -+ /* Shift the mask to the correct bit location, not always correct -+ * Probally, the first match will be chosen. -+ */ -+ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { -+ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) -+ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { -+ break; -+ } -+ } -+ if (pos >= IFX_MSI_IRQ_NUM) { -+ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); -+ return; -+ } -+ spin_lock(&ifx_pcie_msi_lock); -+ /* Disable this entry */ -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); -+ spin_unlock(&ifx_pcie_msi_lock); -+ /* -+ * Count the number of IRQs we need to free by looking at the -+ * msi_multiple_irq_bitmask. Each bit set means that the next -+ * IRQ is also owned by this device. -+ */ -+ number_irqs = 0; -+ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && -+ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { -+ number_irqs++; -+ } -+ number_irqs++; -+ -+ /* Mask with one bit for each IRQ */ -+ bitmask = (1 << number_irqs) - 1; -+ -+ bitmask <<= pos; -+ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { -+ printk(KERN_ERR "%s: Attempted to teardown MSI " -+ "interrupt (%d) not in use\n", __func__, irq); -+ return; -+ } -+ /* Checks are done, update the in use bitmask */ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; -+ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); -+ spin_unlock(&ifx_pcie_msi_lock); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); -+} -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -+MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); -+MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_phy.c -@@ -0,0 +1,478 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_phy.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe PHY sub module -+** -+** DATE : 14 May 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 14 May,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \file ifxmips_pcie_phy.c -+ \ingroup IFX_PCIE -+ \brief PCIe PHY PLL register programming source file -+*/ -+#include -+#include -+#include -+#include -+ -+#include "ifxmips_pcie_reg.h" -+#include "ifxmips_pcie.h" -+ -+/* PCIe PDI only supports 16 bit operation */ -+ -+#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ -+ ((*(volatile u16 *) (__addr)) = (__data)) -+ -+#define IFX_PCIE_PHY_REG_READ16(__addr) \ -+ (*(volatile u16 *) (__addr)) -+ -+#define IFX_PCIE_PHY_REG16(__addr) \ -+ (*(volatile u16 *) (__addr)) -+ -+#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ -+ u16 read_data; \ -+ u16 write_data; \ -+ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ -+ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ -+ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ -+} while (0) -+ -+#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ -+ -+//#define IFX_PCI_PHY_REG_DUMP -+ -+#ifdef IFX_PCI_PHY_REG_DUMP -+static void -+pcie_phy_reg_dump(int pcie_port) -+{ -+ printk("PLL REGFILE\n"); -+ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); -+ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); -+ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); -+ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); -+ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); -+ -+ printk("TX1 REGFILE\n"); -+ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); -+ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); -+ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); -+ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); -+ -+ printk("TX2 REGFILE\n"); -+ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); -+ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); -+ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); -+ -+ printk("RX1 REGFILE\n"); -+ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); -+ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); -+ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); -+ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); -+ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); -+} -+#endif /* IFX_PCI_PHY_REG_DUMP */ -+ -+static void -+pcie_phy_comm_setup(int pcie_port) -+{ -+ /* PLL Setting */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); -+ -+ /* increase the bias reference voltage */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); -+ -+ /* Endcnt */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); -+ -+ /* force */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); -+ -+ /* ctrl_lim */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); -+ -+ /* ctrl */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); -+ -+ /* RTERM*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); -+ -+ /* Improved 100MHz clock output */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); -+ -+ /* Reduced CDR BW to avoid glitches */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); -+} -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+static void -+pcie_phy_36mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE -+static void -+pcie_phy_36mhz_ssc_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ -+ /* PLL Setting */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); -+ -+ /* Increase the bias reference voltage */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); -+ -+ /* Endcnt */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); -+ -+ /* Force */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); -+ -+ /* Predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); -+ -+ /* ctrl_lim */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); -+ -+ /* ctrl */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); -+ -+ /* RTERM*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); -+ -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); -+ -+ /* improved 100MHz clock output */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); -+ -+ /* reduced CDR BW to avoid glitches */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE -+static void -+pcie_phy_25mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); -+ -+ /* en_ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE -+static void -+pcie_phy_100mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ -+ -+static int -+pcie_phy_wait_startup_ready(int pcie_port) -+{ -+ int i; -+ -+ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { -+ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { -+ break; -+ } -+ udelay(10); -+ } -+ if (i >= IFX_PCIE_PLL_TIMEOUT) { -+ printk(KERN_ERR "%s PLL Link timeout\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static void -+pcie_phy_load_enable(int pcie_port, int slice) -+{ -+ /* Set the load_en of tx/rx slice to '1' */ -+ switch (slice) { -+ case 1: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); -+ break; -+ case 2: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); -+ break; -+ case 3: -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); -+ break; -+ } -+} -+ -+static void -+pcie_phy_load_disable(int pcie_port, int slice) -+{ -+ /* set the load_en of tx/rx slice to '0' */ -+ switch (slice) { -+ case 1: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); -+ break; -+ case 2: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); -+ break; -+ case 3: -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); -+ break; -+ } -+} -+ -+static void -+pcie_phy_load_war(int pcie_port) -+{ -+ int slice; -+ -+ for (slice = 1; slice < 4; slice++) { -+ pcie_phy_load_enable(pcie_port, slice); -+ udelay(1); -+ pcie_phy_load_disable(pcie_port, slice); -+ } -+} -+ -+static void -+pcie_phy_tx2_modulation(int pcie_port) -+{ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); -+ mdelay(1); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); -+} -+ -+static void -+pcie_phy_tx1_modulation(int pcie_port) -+{ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); -+ mdelay(1); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); -+} -+ -+static void -+pcie_phy_tx_modulation_war(int pcie_port) -+{ -+ int i; -+ -+#define PCIE_PHY_MODULATION_NUM 5 -+ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { -+ pcie_phy_tx2_modulation(pcie_port); -+ pcie_phy_tx1_modulation(pcie_port); -+ } -+#undef PCIE_PHY_MODULATION_NUM -+} -+ -+void -+pcie_phy_clock_mode_setup(int pcie_port) -+{ -+ pcie_pdi_big_endian(pcie_port); -+ -+ /* Enable PDI to access PCIe PHY register */ -+ pcie_pdi_pmu_enable(pcie_port); -+ -+ /* Configure PLL and PHY clock */ -+ pcie_phy_comm_setup(pcie_port); -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ pcie_phy_36mhz_mode_setup(pcie_port); -+#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) -+ pcie_phy_36mhz_ssc_mode_setup(pcie_port); -+#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) -+ pcie_phy_25mhz_mode_setup(pcie_port); -+#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) -+ pcie_phy_100mhz_mode_setup(pcie_port); -+#else -+ #error "PCIE PHY Clock Mode must be chosen first!!!!" -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ -+ -+ /* Enable PCIe PHY and make PLL setting take effect */ -+ pcie_phy_pmu_enable(pcie_port); -+ -+ /* Check if we are in startup_ready status */ -+ pcie_phy_wait_startup_ready(pcie_port); -+ -+ pcie_phy_load_war(pcie_port); -+ -+ /* Apply TX modulation workarounds */ -+ pcie_phy_tx_modulation_war(pcie_port); -+ -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+} -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_pm.c -@@ -0,0 +1,176 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_pm.c -+** PROJECT : IFX UEIP -+** MODULES : PCIE Root Complex Driver -+** -+** DATE : 21 Dec 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIE Root Complex Driver Power Managment -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 21 Dec,2009 Lei Chuanhua First UEIP release -+*******************************************************************************/ -+/*! -+ \defgroup IFX_PCIE_PM Power Management functions -+ \ingroup IFX_PCIE -+ \brief IFX PCIE Root Complex Driver power management functions -+*/ -+ -+/*! -+ \file ifxmips_pcie_pm.c -+ \ingroup IFX_PCIE -+ \brief source file for PCIE Root Complex Driver Power Management -+*/ -+ -+#ifndef EXPORT_SYMTAB -+#define EXPORT_SYMTAB -+#endif -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif /* AUTOCONF_INCLUDED */ -+#include -+#include -+#include -+#include -+#include -+ -+/* Project header */ -+#include -+#include -+#include -+#include -+#include "ifxmips_pcie_pm.h" -+ -+/** -+ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) -+ * \brief the callback function to request pmcu state in the power management hardware-dependent module -+ * -+ * \param pmcuState This parameter is a PMCU state. -+ * -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) -+{ -+ switch(pmcuState) -+ { -+ case IFX_PMCU_STATE_D0: -+ return IFX_PMCU_RETURN_SUCCESS; -+ case IFX_PMCU_STATE_D1: // Not Applicable -+ return IFX_PMCU_RETURN_DENIED; -+ case IFX_PMCU_STATE_D2: // Not Applicable -+ return IFX_PMCU_RETURN_DENIED; -+ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating -+ return IFX_PMCU_RETURN_SUCCESS; -+ default: -+ return IFX_PMCU_RETURN_DENIED; -+ } -+} -+ -+/** -+ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) -+ * \brief the callback function to get pmcu state in the power management hardware-dependent module -+ -+ * \param pmcuState Pointer to return power state. -+ * -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) -+{ -+ return IFX_PMCU_RETURN_SUCCESS; -+} -+ -+/** -+ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule -+ * -+ * \param pmcuModule Module -+ * \param newState New state -+ * \param oldState Old state -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+{ -+ return IFX_PMCU_RETURN_SUCCESS; -+} -+ -+/** -+ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule -+ * -+ * \param pmcuModule Module -+ * \param newState New state -+ * \param oldState Old state -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+{ -+ return IFX_PMCU_RETURN_SUCCESS; -+} -+ -+/** -+ * \fn static void ifx_pcie_pmcu_init(void) -+ * \brief Register with central PMCU module -+ * \return none -+ * \ingroup IFX_PCIE_PM -+ */ -+void -+ifx_pcie_pmcu_init(void) -+{ -+ IFX_PMCU_REGISTER_t pmcuRegister; -+ -+ /* XXX, hook driver context */ -+ -+ /* State function register */ -+ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); -+ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; -+ pmcuRegister.pmcuModuleNr = 0; -+ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; -+ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; -+ pmcuRegister.pre = ifx_pcie_pmcu_prechange; -+ pmcuRegister.post= ifx_pcie_pmcu_postchange; -+ ifx_pmcu_register(&pmcuRegister); -+} -+ -+/** -+ * \fn static void ifx_pcie_pmcu_exit(void) -+ * \brief Unregister with central PMCU module -+ * -+ * \return none -+ * \ingroup IFX_PCIE_PM -+ */ -+void -+ifx_pcie_pmcu_exit(void) -+{ -+ IFX_PMCU_REGISTER_t pmcuUnRegister; -+ -+ /* XXX, hook driver context */ -+ -+ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; -+ pmcuUnRegister.pmcuModuleNr = 0; -+ ifx_pmcu_unregister(&pmcuUnRegister); -+} -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_pm.h -@@ -0,0 +1,36 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_pm.h -+** PROJECT : IFX UEIP -+** MODULES : PCIe Root Complex Driver -+** -+** DATE : 21 Dec 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver Power Managment -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 21 Dec,2009 Lei Chuanhua First UEIP release -+*******************************************************************************/ -+/*! -+ \file ifxmips_pcie_pm.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe Root Complex Driver Power Management -+*/ -+ -+#ifndef IFXMIPS_PCIE_PM_H -+#define IFXMIPS_PCIE_PM_H -+ -+void ifx_pcie_pmcu_init(void); -+void ifx_pcie_pmcu_exit(void); -+ -+#endif /* IFXMIPS_PCIE_PM_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_reg.h -@@ -0,0 +1,1001 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_reg.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_REG_H -+#define IFXMIPS_PCIE_REG_H -+/*! -+ \file ifxmips_pcie_reg.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module register definition -+*/ -+/* PCIe Address Mapping Base */ -+#define PCIE_CFG_PHY_BASE 0x1D000000UL -+#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) -+#define PCIE_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE_MEM_PHY_BASE 0x1C000000UL -+#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) -+#define PCIE_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) -+ -+#define PCIE_IO_PHY_BASE 0x1D800000UL -+#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) -+#define PCIE_IO_SIZE (1 * 1024 * 1024) -+#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) -+ -+#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) -+#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) -+#define PCIE_MSI_PHY_BASE 0x1F600000UL -+ -+#define PCIE_PDI_PHY_BASE 0x1F106800UL -+#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) -+#define PCIE_PDI_SIZE 0x400 -+ -+#define PCIE1_CFG_PHY_BASE 0x19000000UL -+#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) -+#define PCIE1_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE1_MEM_PHY_BASE 0x18000000UL -+#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) -+#define PCIE1_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) -+ -+#define PCIE1_IO_PHY_BASE 0x19800000UL -+#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) -+#define PCIE1_IO_SIZE (1 * 1024 * 1024) -+#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) -+ -+#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) -+#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) -+#define PCIE1_MSI_PHY_BASE 0x1F400000UL -+ -+#define PCIE1_PDI_PHY_BASE 0x1F700400UL -+#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) -+#define PCIE1_PDI_SIZE 0x400 -+ -+#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) -+#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) -+#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) -+#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) -+#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) -+#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) -+#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) -+#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) -+ -+/* PCIe Application Logic Register */ -+/* RC Core Control Register */ -+#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) -+/* This should be enabled after initializing configuratin registers -+ * Also should check link status retraining bit -+ */ -+#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ -+ -+/* RC Core Debug Register */ -+#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) -+#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 -+ -+#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ -+#define PCIE_RC_DR_PM_DEV_STATE_S 9 -+ -+#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ -+#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ -+#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ -+ -+/* Current Power State Definition */ -+enum { -+ PCIE_RC_DR_D0 = 0, -+ PCIE_RC_DR_D1, /* Not supported */ -+ PCIE_RC_DR_D2, /* Not supported */ -+ PCIE_RC_DR_D3, -+ PCIE_RC_DR_UN, -+}; -+ -+/* PHY Link Status Register */ -+#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) -+#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ -+ -+/* Electromechanical Control Register */ -+#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) -+#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ -+#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ -+#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ -+#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ -+#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ -+#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ -+#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ -+#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ -+ -+/* Interrupt Status Register */ -+#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) -+#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ -+#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ -+#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ -+#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ -+#define PCIE_IR_SR_AHB_LU_ERR_S 4 -+#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ -+#define PCIE_IR_SR_INT_MSG_NUM_S 9 -+#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 -+ -+/* Message Control Register */ -+#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) -+#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ -+#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ -+ -+#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) -+ -+/* Vendor-Defined Message Requester ID Register */ -+#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) -+#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF -+#define PCIE_VDM_RID_VDMRID_S 0 -+ -+/* ASPM Control Register */ -+#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) -+#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ -+#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ -+#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ -+ -+/* Vendor Message DW0 Register */ -+#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) -+#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ -+#define PCIE_VM_MSG_DW0_TYPE_S 0 -+#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ -+#define PCIE_VM_MSG_DW0_FORMAT_S 5 -+#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ -+#define PCIE_VM_MSG_DW0_TC_S 12 -+#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ -+#define PCIE_VM_MSG_DW0_ATTR_S 18 -+#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ -+#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ -+#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ -+#define PCIE_VM_MSG_DW0_LEN_S 22 -+ -+/* Format Definition */ -+enum { -+ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ -+ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ -+ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ -+ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ -+}; -+ -+/* Traffic Class Definition */ -+enum { -+ PCIE_VM_MSG_TC0 = 0, -+ PCIE_VM_MSG_TC1, -+ PCIE_VM_MSG_TC2, -+ PCIE_VM_MSG_TC3, -+ PCIE_VM_MSG_TC4, -+ PCIE_VM_MSG_TC5, -+ PCIE_VM_MSG_TC6, -+ PCIE_VM_MSG_TC7, -+}; -+ -+/* Attributes Definition */ -+enum { -+ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ -+ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ -+ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ -+ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ -+}; -+ -+/* Payload Size Definition */ -+#define PCIE_VM_MSG_LEN_MIN 0 -+#define PCIE_VM_MSG_LEN_MAX 1024 -+ -+/* Vendor Message DW1 Register */ -+#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) -+#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ -+#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 -+#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ -+#define PCIE_VM_MSG_DW1_CODE_S 16 -+#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ -+#define PCIE_VM_MSG_DW1_TAG_S 24 -+ -+#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) -+#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) -+ -+/* Vendor Message Request Register */ -+#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) -+#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ -+ -+ -+/* AHB Slave Side Band Control Register */ -+#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) -+#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ -+#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ -+#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ -+#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ -+#define PCIE_AHB_SSB_REQ_ATTR_S 3 -+#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ -+#define PCIE_AHB_SSB_REQ_TC_S 5 -+ -+/* AHB Master SideBand Ctrl Register */ -+#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) -+#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ -+#define PCIE_AHB_MSB_RESP_ATTR_S 0 -+#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ -+#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ -+#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ -+#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 -+ -+/* AHB Control Register, fixed bus enumeration exception */ -+#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) -+#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 -+ -+/* Interrupt Enalbe Register */ -+#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) -+#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) -+#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) -+ -+/* PCIe interrupt enable/control/capture register definition */ -+#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ -+#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ -+#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ -+#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ -+#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ -+#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ -+#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ -+#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ -+#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ -+#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ -+#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ -+#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ -+#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ -+#define PCIE_IRN_INTA 0x00002000 /* INTA */ -+#define PCIE_IRN_INTB 0x00004000 /* INTB */ -+#define PCIE_IRN_INTC 0x00008000 /* INTC */ -+#define PCIE_IRN_INTD 0x00010000 /* INTD */ -+#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ -+ -+#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ -+ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ -+ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ -+ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ -+ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) -+/* PCIe RC Configuration Register */ -+#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) -+ -+/* Bit definition from pci_reg.h */ -+#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) -+#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) -+#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ -+/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ -+#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ -+#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ -+ -+#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ -+/* Bus Number Register bits */ -+#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF -+#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 -+#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 -+#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 -+#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 -+#define PCIE_PNR_SUB_BUS_NUM_S 16 -+ -+/* IO Base/Limit Register bits */ -+#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ -+#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 -+#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 -+#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 -+#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 -+ -+/* Non-prefetchable Memory Base/Limit Register bit */ -+#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ -+#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 -+#define PCIE_MBML_MEM_BASE_ADDR_S 4 -+#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 -+#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 -+ -+/* Prefetchable Memory Base/Limit Register bit */ -+#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ -+#define PCIE_PMBL_64BIT_ADDR 0x00000001 -+#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 -+#define PCIE_PMBL_UPPER_12BIT_S 4 -+#define PCIE_PMBL_E64MA 0x00010000 -+#define PCIE_PMBL_END_ADDR 0xFFF00000 -+#define PCIE_PMBL_END_ADDR_S 20 -+#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ -+#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ -+ -+/* I/O Base/Limit Upper 16 bits register */ -+#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 -+ -+#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) -+#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) -+ -+/* Interrupt and Secondary Bridge Control Register */ -+#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) -+ -+#define PCIE_INTRBCTRL_INT_LINE 0x000000FF -+#define PCIE_INTRBCTRL_INT_LINE_S 0 -+#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 -+#define PCIE_INTRBCTRL_INT_PIN_S 8 -+#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ -+#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ -+#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ -+#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ -+#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ -+#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ -+/* Others are read only */ -+enum { -+ PCIE_INTRBCTRL_INT_NON = 0, -+ PCIE_INTRBCTRL_INTA, -+ PCIE_INTRBCTRL_INTB, -+ PCIE_INTRBCTRL_INTC, -+ PCIE_INTRBCTRL_INTD, -+}; -+ -+#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) -+ -+/* Power Management Control and Status Register */ -+#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) -+ -+#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ -+#define PCIE_PM_CSR_POWER_STATE_S 0 -+#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ -+#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ -+#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ -+ -+/* MSI Capability Register for EP */ -+#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) -+ -+#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ -+#define PCIE_MCAPR_MSI_CAP_ID_S 0 -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 -+#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 -+#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ -+#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 -+#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ -+ -+/* MSI Message Address Register */ -+#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) -+ -+#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ -+ -+/* MSI Message Upper Address Register */ -+#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) -+ -+/* MSI Message Data Register */ -+#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) -+ -+#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ -+#define PCIE_MD_DATA_S 0 -+ -+/* PCI Express Capability Register */ -+#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) -+ -+#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ -+#define PCIE_XCAP_ID_S 0 -+#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_XCAP_NEXT_CAP_S 8 -+#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ -+#define PCIE_XCAP_VER_S 16 -+#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ -+#define PCIE_XCAP_DEV_PORT_TYPE_S 20 -+#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ -+#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ -+#define PCIE_XCAP_MSG_INT_NUM_S 25 -+ -+/* Device Capability Register */ -+#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) -+ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 -+#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ -+#define PCIE_DCAP_PHANTOM_FUNC_S 3 -+#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ -+#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ -+#define PCIE_DCAP_EP_L0S_LATENCY_S 6 -+#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ -+#define PCIE_DCAP_EP_L1_LATENCY_S 9 -+#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ -+ -+/* Maximum payload size supported */ -+enum { -+ PCIE_MAX_PAYLOAD_128 = 0, -+ PCIE_MAX_PAYLOAD_256, -+ PCIE_MAX_PAYLOAD_512, -+ PCIE_MAX_PAYLOAD_1024, -+ PCIE_MAX_PAYLOAD_2048, -+ PCIE_MAX_PAYLOAD_4096, -+}; -+ -+/* Device Control and Status Register */ -+#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) -+ -+#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ -+#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ -+#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ -+#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 -+#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ -+#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ -+#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ -+#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 -+#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ -+#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ -+#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ -+#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ -+#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ -+#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ -+ -+#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ -+ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ -+ PCIE_DCTLSYS_UR_REQ_EN) -+ -+/* Link Capability Register */ -+#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) -+#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ -+#define PCIE_LCAP_MAX_LINK_SPEED_S 0 -+#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ -+#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 -+#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ -+#define PCIE_LCAP_ASPM_LEVEL_S 10 -+#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ -+#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 -+#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ -+#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 -+#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ -+#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ -+#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ -+#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ -+#define PCIE_LCAP_PORT_NUM_S 24 -+ -+/* Maximum Length width definition */ -+#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 -+#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ -+#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 -+#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 -+#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 -+#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C -+#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 -+#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 -+ -+/* Active State Link PM definition */ -+enum { -+ PCIE_ASPM_RES0 = 0, -+ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ -+ PCIE_ASPM_RES1, -+ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ -+}; -+ -+/* L0s Exit Latency definition */ -+enum { -+ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ -+ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ -+ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ -+ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ -+ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ -+ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ -+ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ -+ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ -+}; -+ -+/* L1 Exit Latency definition */ -+enum { -+ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ -+ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ -+ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ -+ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ -+ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ -+ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ -+ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ -+ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ -+}; -+ -+/* Link Control and Status Register */ -+#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) -+#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ -+#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 -+#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ -+#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ -+#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ -+#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ -+#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ -+#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ -+#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ -+#define PCIE_LCTLSTS_LINK_SPEED_S 16 -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 -+#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ -+#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ -+#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ -+ -+/* Slot Capabilities Register */ -+#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) -+ -+/* Slot Capabilities */ -+#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) -+ -+/* Root Control and Capability Register */ -+#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) -+#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ -+#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ -+#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ -+#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ -+#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ -+ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) -+/* Root Status Register */ -+#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) -+#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ -+#define PCIE_RSTS_PME_REQ_ID_S 0 -+#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ -+#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ -+ -+/* PCI Express Enhanced Capability Header */ -+#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) -+#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ -+#define PCIE_ENHANCED_CAP_ID_S 0 -+#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ -+#define PCIE_ENHANCED_CAP_VER_S 16 -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 -+ -+/* Uncorrectable Error Status Register */ -+#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) -+#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ -+#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ -+#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ -+#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ -+#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ -+#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ -+#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ -+#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ -+#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ -+#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ -+#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ -+#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ -+ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ -+ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ -+ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) -+ -+/* Uncorrectable Error Mask Register, Mask means no report */ -+#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) -+ -+/* Uncorrectable Error Severity Register */ -+#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) -+ -+/* Correctable Error Status Register */ -+#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) -+#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ -+#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ -+#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ -+#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ -+#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ -+#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ -+#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ -+ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) -+ -+/* Correctable Error Mask Register */ -+#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) -+ -+/* Advanced Error Capabilities and Control Register */ -+#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) -+#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ -+#define PCIE_AECCR_FIRST_ERR_PTR_S 0 -+#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ -+#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ -+#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ -+#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ -+ -+/* Header Log Register 1 */ -+#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) -+ -+/* Header Log Register 2 */ -+#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) -+ -+/* Header Log Register 3 */ -+#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) -+ -+/* Header Log Register 4 */ -+#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) -+ -+/* Root Error Command Register */ -+#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) -+#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ -+#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ -+#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ -+ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) -+ -+/* Root Error Status Register */ -+#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) -+#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ -+#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ -+#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ -+#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ -+#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ -+#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_RESR_AER_INT_MSG_NUM_S 27 -+ -+/* Error Source Indentification Register */ -+#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 -+ -+/* VC Enhanced Capability Header */ -+#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) -+ -+/* Port VC Capability Register */ -+#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) -+#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ -+#define PCIE_PVC1_EXT_VC_CNT_S 0 -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 -+#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ -+#define PCIE_PVC1_REF_CLK_S 8 -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 -+ -+/* Extended Virtual Channel Count Defintion */ -+#define PCIE_EXT_VC_CNT_MIN 0 -+#define PCIE_EXT_VC_CNT_MAX 7 -+ -+/* Port Arbitration Table Entry Size Definition */ -+enum { -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, -+}; -+ -+/* Port VC Capability Register 2 */ -+#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) -+#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ -+#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_PVC2_VC_ARB_WRR 0x0000000F -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 -+ -+/* Port VC Control and Status Register */ -+#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) -+#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ -+#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ -+#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 -+#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ -+ -+/* VC0 Resource Capability Register */ -+#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) -+#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ -+#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ -+ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ -+ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) -+ -+#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 -+ -+/* VC0 Resource Control Register */ -+#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) -+#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ -+#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ -+#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ -+#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ -+#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ -+#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ -+#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ -+#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ -+#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ -+ -+#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 -+#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ -+#define PCIE_VC0_RC0_VC_ID_S 24 -+#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ -+ -+/* VC0 Resource Status Register */ -+#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) -+#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ -+#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ -+ -+/* Ack Latency Timer and Replay Timer Register */ -+#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 -+ -+/* Other Message Register */ -+#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) -+ -+/* Port Force Link Register */ -+#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) -+#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ -+#define PCIE_PFLR_LINK_NUM_S 0 -+#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ -+#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ -+#define PCIE_PFLR_LINK_STATE_S 16 -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 -+ -+/* Ack Frequency Register */ -+#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) -+#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ -+#define PCIE_AFR_AF_S 0 -+#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ -+#define PCIE_AFR_FTS_NUM_S 8 -+#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ -+#define PCIE_AFR_COM_FTS_NUM_S 16 -+#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ -+#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 -+#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ -+#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 -+#define PCIE_AFR_FTS_NUM_DEFAULT 32 -+#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 -+#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 -+ -+/* Port Link Control Register */ -+#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) -+#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ -+#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ -+#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ -+#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ -+#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ -+#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ -+#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ -+#define PCIE_PLCR_LINK_MODE_S 16 -+#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ -+ -+/* Lane Skew Register */ -+#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) -+#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ -+#define PCIE_LSR_LANE_SKEW_NUM_S 0 -+#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ -+#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ -+#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ -+ -+/* Symbol Number Register */ -+#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) -+#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ -+#define PCIE_SNR_TS_S 0 -+#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ -+#define PCIE_SNR_SKP_S 8 -+#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ -+#define PCIE_SNR_REPLAY_TIMER_S 14 -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 -+#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ -+#define PCIE_SNR_FC_TIMER_S 28 -+ -+/* Symbol Timer Register and Filter Mask Register 1 */ -+#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) -+#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ -+#define PCIE_STRFMR_SKP_INTERVAL_S 0 -+#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ -+#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ -+#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ -+#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ -+#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ -+#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ -+#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ -+#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ -+#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ -+#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ -+#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ -+#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ -+ -+#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ -+ -+/* Filter Masker Register 2 */ -+#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) -+#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ -+#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ -+ -+/* Debug Register 0 */ -+#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) -+ -+/* Debug Register 1 */ -+#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) -+ -+/* Transmit Posted FC Credit Status Register */ -+#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Non-Posted FC Credit Status */ -+#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Complete FC Credit Status Register */ -+#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 -+ -+/* Queue Status Register */ -+#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) -+#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ -+#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ -+#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ -+ -+/* VC Transmit Arbitration Register 1 */ -+#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) -+#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ -+ -+/* VC Transmit Arbitration Register 2 */ -+#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) -+#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ -+ -+/* VC0 Posted Receive Queue Control Register */ -+#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 -+#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ -+#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ -+ -+/* VC0 Non-Posted Receive Queue Control */ -+#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 -+ -+/* VC0 Completion Receive Queue Control */ -+#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 -+ -+/* Applicable to the above three registers */ -+enum { -+ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, -+ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, -+ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, -+}; -+ -+/* VC0 Posted Buffer Depth Register */ -+#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Non-Posted Buffer Depth Register */ -+#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Completion Buffer Depth Register */ -+#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 -+ -+/* PHY Status Register, all zeros in VR9 */ -+#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) -+ -+/* PHY Control Register, all zeros in VR9 */ -+#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) -+ -+/* -+ * PCIe PDI PHY register definition, suppose all the following -+ * stuff is confidential. -+ * XXX, detailed bit definition -+ */ -+#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) -+#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) -+#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) -+#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) -+#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) -+#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) -+#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) -+#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) -+#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) -+#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) -+#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) -+ -+#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) -+#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) -+#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) -+#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) -+#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) -+#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) -+#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) -+#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) -+ -+#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) -+#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) -+#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) -+#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) -+#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) -+#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) -+#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) -+ -+#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) -+#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) -+#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) -+#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) -+#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) -+ -+/* Interrupt related stuff */ -+#define PCIE_LEGACY_DISABLE 0 -+#define PCIE_LEGACY_INTA 1 -+#define PCIE_LEGACY_INTB 2 -+#define PCIE_LEGACY_INTC 3 -+#define PCIE_LEGACY_INTD 4 -+#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD -+ -+#endif /* IFXMIPS_PCIE_REG_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_vr9.h -@@ -0,0 +1,269 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ *****************************************************************************/ -+/*! -+ \file ifxmips_pcie_vr9.h -+ \ingroup IFX_PCIE -+ \brief PCIe RC driver vr9 specific file -+*/ -+ -+#ifndef IFXMIPS_PCIE_VR9_H -+#define IFXMIPS_PCIE_VR9_H -+ -+#include -+#include -+ -+#include -+#include -+ -+#define IFX_PCIE_GPIO_RESET 494 -+ -+#define IFX_REG_R32 ltq_r32 -+#define IFX_REG_W32 ltq_w32 -+#define CONFIG_IFX_PCIE_HW_SWAP -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ -+#define IFX_PMU1_MODULE_PCIE_PHY (0) -+#define IFX_PMU1_MODULE_PCIE_CTRL (1) -+#define IFX_PMU1_MODULE_PDI (4) -+#define IFX_PMU1_MODULE_MSI (5) -+ -+#define IFX_PMU_MODULE_PCIE_L0_CLK (31) -+ -+ -+#define IFX_GPIO (KSEG1 | 0x1E100B00) -+#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) -+#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) -+#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) -+#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) -+#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) -+ -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+ -+ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); -+ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); -+ gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -+ -+/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ /* Enable AHB bus master/slave */ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "ahb"); -+ clk_enable(clk); -+ -+ //AHBM_PMU_SETUP(IFX_PMU_ENABLE); -+ //AHBS_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg |= IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#else -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg &= ~IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "phy"); -+ clk_enable(clk); -+ -+ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_phy_pmu_disable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "phy"); -+ clk_disable(clk); -+ -+// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+} -+ -+static inline void pcie_pdi_big_endian(int pcie_port) -+{ -+ u32 reg; -+ -+ /* SRAM2PDI endianness control. */ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+ /* Config AHB->PCIe and PDI endianness */ -+ reg |= IFX_RCU_AHB_BE_PCIE_PDI; -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ /* Enable PDI to access PCIe PHY register */ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "pdi"); -+ clk_enable(clk); -+ //PDI_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_core_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ -+ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ -+ reg |= 0x00400000; -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_core_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ /* Reset PCIe PHY & Core, bit 22 */ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ reg &= ~0x00400000; -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ reg |= 0x00001000; /* Bit 12 */ -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ reg &= ~0x00001000; /* Bit 12 */ -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_device_rst_assert(int pcie_port) -+{ -+ gpio_set_value(IFX_PCIE_GPIO_RESET, 0); -+// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+} -+ -+static inline void pcie_device_rst_deassert(int pcie_port) -+{ -+ mdelay(100); -+ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); -+// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -+ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+} -+ -+static inline void pcie_core_pmu_setup(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "ctl"); -+ clk_enable(clk); -+ clk = clk_get_sys("1d900000.pcie", "bus"); -+ clk_enable(clk); -+ -+ /* PCIe Core controller enabled */ -+// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ -+ /* Enable PCIe L0 Clock */ -+// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_msi_init(int pcie_port) -+{ -+ struct clk *clk; -+ pcie_msi_pic_init(pcie_port); -+ clk = clk_get_sys("ltq_pcie", "msi"); -+ clk_enable(clk); -+// MSI_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline u32 -+ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) -+{ -+ u32 tbus_number = bus_number; -+ -+#ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+#endif /* CONFIG_PCI_LANTIQ */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ #endif /* CONFIG_PCI_LANTIQ */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_VR9_H */ -+ ---- a/arch/mips/pci/pci-legacy.c -+++ b/arch/mips/pci/pci-legacy.c -@@ -313,3 +313,30 @@ char *__init pcibios_setup(char *str) - return pcibios_plat_setup(str); - return str; - } -+ -+int pcibios_host_nr(void) -+{ -+ int count = 0; -+ struct pci_controller *hose; -+ list_for_each_entry(hose, &controllers, list) { -+ count++; -+ } -+ return count; -+} -+EXPORT_SYMBOL(pcibios_host_nr); -+ -+int pcibios_1st_host_bus_nr(void) -+{ -+ int bus_nr = 0; -+ struct pci_controller *hose; -+ -+ hose = list_first_entry_or_null(&controllers, struct pci_controller, list); -+ -+ if (hose != NULL) { -+ if (hose->bus != NULL) { -+ bus_nr = hose->bus->number + 1; -+ } -+ } -+ return bus_nr; -+} -+EXPORT_SYMBOL(pcibios_1st_host_bus_nr); ---- /dev/null -+++ b/arch/mips/pci/pcie-lantiq.h -@@ -0,0 +1,1301 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_reg.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_REG_H -+#define IFXMIPS_PCIE_REG_H -+#include -+#include -+#include -+#include -+/*! -+ \file ifxmips_pcie_reg.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module register definition -+*/ -+/* PCIe Address Mapping Base */ -+#define PCIE_CFG_PHY_BASE 0x1D000000UL -+#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) -+#define PCIE_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE_MEM_PHY_BASE 0x1C000000UL -+#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) -+#define PCIE_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) -+ -+#define PCIE_IO_PHY_BASE 0x1D800000UL -+#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) -+#define PCIE_IO_SIZE (1 * 1024 * 1024) -+#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) -+ -+#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) -+#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) -+#define PCIE_MSI_PHY_BASE 0x1F600000UL -+ -+#define PCIE_PDI_PHY_BASE 0x1F106800UL -+#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) -+#define PCIE_PDI_SIZE 0x400 -+ -+#define PCIE1_CFG_PHY_BASE 0x19000000UL -+#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) -+#define PCIE1_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE1_MEM_PHY_BASE 0x18000000UL -+#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) -+#define PCIE1_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) -+ -+#define PCIE1_IO_PHY_BASE 0x19800000UL -+#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) -+#define PCIE1_IO_SIZE (1 * 1024 * 1024) -+#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) -+ -+#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) -+#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) -+#define PCIE1_MSI_PHY_BASE 0x1F400000UL -+ -+#define PCIE1_PDI_PHY_BASE 0x1F700400UL -+#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) -+#define PCIE1_PDI_SIZE 0x400 -+ -+#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) -+#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) -+#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) -+#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) -+#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) -+#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) -+#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) -+#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) -+ -+/* PCIe Application Logic Register */ -+/* RC Core Control Register */ -+#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) -+/* This should be enabled after initializing configuratin registers -+ * Also should check link status retraining bit -+ */ -+#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ -+ -+/* RC Core Debug Register */ -+#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) -+#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 -+ -+#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ -+#define PCIE_RC_DR_PM_DEV_STATE_S 9 -+ -+#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ -+#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ -+#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ -+ -+/* Current Power State Definition */ -+enum { -+ PCIE_RC_DR_D0 = 0, -+ PCIE_RC_DR_D1, /* Not supported */ -+ PCIE_RC_DR_D2, /* Not supported */ -+ PCIE_RC_DR_D3, -+ PCIE_RC_DR_UN, -+}; -+ -+/* PHY Link Status Register */ -+#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) -+#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ -+ -+/* Electromechanical Control Register */ -+#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) -+#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ -+#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ -+#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ -+#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ -+#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ -+#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ -+#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ -+#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ -+ -+/* Interrupt Status Register */ -+#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) -+#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ -+#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ -+#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ -+#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ -+#define PCIE_IR_SR_AHB_LU_ERR_S 4 -+#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ -+#define PCIE_IR_SR_INT_MSG_NUM_S 9 -+#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 -+ -+/* Message Control Register */ -+#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) -+#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ -+#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ -+ -+#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) -+ -+/* Vendor-Defined Message Requester ID Register */ -+#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) -+#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF -+#define PCIE_VDM_RID_VDMRID_S 0 -+ -+/* ASPM Control Register */ -+#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) -+#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ -+#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ -+#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ -+ -+/* Vendor Message DW0 Register */ -+#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) -+#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ -+#define PCIE_VM_MSG_DW0_TYPE_S 0 -+#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ -+#define PCIE_VM_MSG_DW0_FORMAT_S 5 -+#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ -+#define PCIE_VM_MSG_DW0_TC_S 12 -+#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ -+#define PCIE_VM_MSG_DW0_ATTR_S 18 -+#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ -+#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ -+#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ -+#define PCIE_VM_MSG_DW0_LEN_S 22 -+ -+/* Format Definition */ -+enum { -+ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ -+ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ -+ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ -+ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ -+}; -+ -+/* Traffic Class Definition */ -+enum { -+ PCIE_VM_MSG_TC0 = 0, -+ PCIE_VM_MSG_TC1, -+ PCIE_VM_MSG_TC2, -+ PCIE_VM_MSG_TC3, -+ PCIE_VM_MSG_TC4, -+ PCIE_VM_MSG_TC5, -+ PCIE_VM_MSG_TC6, -+ PCIE_VM_MSG_TC7, -+}; -+ -+/* Attributes Definition */ -+enum { -+ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ -+ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ -+ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ -+ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ -+}; -+ -+/* Payload Size Definition */ -+#define PCIE_VM_MSG_LEN_MIN 0 -+#define PCIE_VM_MSG_LEN_MAX 1024 -+ -+/* Vendor Message DW1 Register */ -+#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) -+#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ -+#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 -+#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ -+#define PCIE_VM_MSG_DW1_CODE_S 16 -+#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ -+#define PCIE_VM_MSG_DW1_TAG_S 24 -+ -+#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) -+#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) -+ -+/* Vendor Message Request Register */ -+#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) -+#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ -+ -+ -+/* AHB Slave Side Band Control Register */ -+#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) -+#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ -+#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ -+#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ -+#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ -+#define PCIE_AHB_SSB_REQ_ATTR_S 3 -+#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ -+#define PCIE_AHB_SSB_REQ_TC_S 5 -+ -+/* AHB Master SideBand Ctrl Register */ -+#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) -+#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ -+#define PCIE_AHB_MSB_RESP_ATTR_S 0 -+#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ -+#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ -+#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ -+#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 -+ -+/* AHB Control Register, fixed bus enumeration exception */ -+#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) -+#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 -+ -+/* Interrupt Enalbe Register */ -+#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) -+#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) -+#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) -+ -+/* PCIe interrupt enable/control/capture register definition */ -+#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ -+#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ -+#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ -+#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ -+#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ -+#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ -+#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ -+#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ -+#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ -+#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ -+#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ -+#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ -+#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ -+#define PCIE_IRN_INTA 0x00002000 /* INTA */ -+#define PCIE_IRN_INTB 0x00004000 /* INTB */ -+#define PCIE_IRN_INTC 0x00008000 /* INTC */ -+#define PCIE_IRN_INTD 0x00010000 /* INTD */ -+#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ -+ -+#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ -+ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ -+ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ -+ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ -+ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) -+/* PCIe RC Configuration Register */ -+#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) -+ -+/* Bit definition from pci_reg.h */ -+#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) -+#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) -+#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ -+/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ -+#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ -+#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ -+ -+#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ -+/* Bus Number Register bits */ -+#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF -+#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 -+#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 -+#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 -+#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 -+#define PCIE_PNR_SUB_BUS_NUM_S 16 -+ -+/* IO Base/Limit Register bits */ -+#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ -+#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 -+#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 -+#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 -+#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 -+ -+/* Non-prefetchable Memory Base/Limit Register bit */ -+#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ -+#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 -+#define PCIE_MBML_MEM_BASE_ADDR_S 4 -+#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 -+#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 -+ -+/* Prefetchable Memory Base/Limit Register bit */ -+#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ -+#define PCIE_PMBL_64BIT_ADDR 0x00000001 -+#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 -+#define PCIE_PMBL_UPPER_12BIT_S 4 -+#define PCIE_PMBL_E64MA 0x00010000 -+#define PCIE_PMBL_END_ADDR 0xFFF00000 -+#define PCIE_PMBL_END_ADDR_S 20 -+#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ -+#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ -+ -+/* I/O Base/Limit Upper 16 bits register */ -+#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 -+ -+#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) -+#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) -+ -+/* Interrupt and Secondary Bridge Control Register */ -+#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) -+ -+#define PCIE_INTRBCTRL_INT_LINE 0x000000FF -+#define PCIE_INTRBCTRL_INT_LINE_S 0 -+#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 -+#define PCIE_INTRBCTRL_INT_PIN_S 8 -+#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ -+#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ -+#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ -+#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ -+#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ -+#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ -+/* Others are read only */ -+enum { -+ PCIE_INTRBCTRL_INT_NON = 0, -+ PCIE_INTRBCTRL_INTA, -+ PCIE_INTRBCTRL_INTB, -+ PCIE_INTRBCTRL_INTC, -+ PCIE_INTRBCTRL_INTD, -+}; -+ -+#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) -+ -+/* Power Management Control and Status Register */ -+#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) -+ -+#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ -+#define PCIE_PM_CSR_POWER_STATE_S 0 -+#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ -+#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ -+#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ -+ -+/* MSI Capability Register for EP */ -+#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) -+ -+#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ -+#define PCIE_MCAPR_MSI_CAP_ID_S 0 -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 -+#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 -+#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ -+#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 -+#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ -+ -+/* MSI Message Address Register */ -+#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) -+ -+#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ -+ -+/* MSI Message Upper Address Register */ -+#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) -+ -+/* MSI Message Data Register */ -+#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) -+ -+#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ -+#define PCIE_MD_DATA_S 0 -+ -+/* PCI Express Capability Register */ -+#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) -+ -+#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ -+#define PCIE_XCAP_ID_S 0 -+#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_XCAP_NEXT_CAP_S 8 -+#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ -+#define PCIE_XCAP_VER_S 16 -+#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ -+#define PCIE_XCAP_DEV_PORT_TYPE_S 20 -+#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ -+#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ -+#define PCIE_XCAP_MSG_INT_NUM_S 25 -+ -+/* Device Capability Register */ -+#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) -+ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 -+#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ -+#define PCIE_DCAP_PHANTOM_FUNC_S 3 -+#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ -+#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ -+#define PCIE_DCAP_EP_L0S_LATENCY_S 6 -+#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ -+#define PCIE_DCAP_EP_L1_LATENCY_S 9 -+#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ -+ -+/* Maximum payload size supported */ -+enum { -+ PCIE_MAX_PAYLOAD_128 = 0, -+ PCIE_MAX_PAYLOAD_256, -+ PCIE_MAX_PAYLOAD_512, -+ PCIE_MAX_PAYLOAD_1024, -+ PCIE_MAX_PAYLOAD_2048, -+ PCIE_MAX_PAYLOAD_4096, -+}; -+ -+/* Device Control and Status Register */ -+#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) -+ -+#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ -+#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ -+#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ -+#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 -+#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ -+#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ -+#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ -+#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 -+#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ -+#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ -+#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ -+#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ -+#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ -+#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ -+ -+#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ -+ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ -+ PCIE_DCTLSYS_UR_REQ_EN) -+ -+/* Link Capability Register */ -+#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) -+#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ -+#define PCIE_LCAP_MAX_LINK_SPEED_S 0 -+#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ -+#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 -+#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ -+#define PCIE_LCAP_ASPM_LEVEL_S 10 -+#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ -+#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 -+#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ -+#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 -+#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ -+#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ -+#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ -+#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ -+#define PCIE_LCAP_PORT_NUM_S 24 -+ -+/* Maximum Length width definition */ -+#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 -+#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ -+#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 -+#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 -+#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 -+#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C -+#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 -+#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 -+ -+/* Active State Link PM definition */ -+enum { -+ PCIE_ASPM_RES0 = 0, -+ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ -+ PCIE_ASPM_RES1, -+ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ -+}; -+ -+/* L0s Exit Latency definition */ -+enum { -+ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ -+ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ -+ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ -+ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ -+ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ -+ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ -+ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ -+ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ -+}; -+ -+/* L1 Exit Latency definition */ -+enum { -+ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ -+ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ -+ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ -+ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ -+ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ -+ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ -+ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ -+ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ -+}; -+ -+/* Link Control and Status Register */ -+#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) -+#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ -+#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 -+#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ -+#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ -+#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ -+#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ -+#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ -+#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ -+#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ -+#define PCIE_LCTLSTS_LINK_SPEED_S 16 -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 -+#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ -+#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ -+#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ -+ -+/* Slot Capabilities Register */ -+#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) -+ -+/* Slot Capabilities */ -+#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) -+ -+/* Root Control and Capability Register */ -+#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) -+#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ -+#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ -+#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ -+#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ -+#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ -+ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) -+/* Root Status Register */ -+#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) -+#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ -+#define PCIE_RSTS_PME_REQ_ID_S 0 -+#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ -+#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ -+ -+/* PCI Express Enhanced Capability Header */ -+#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) -+#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ -+#define PCIE_ENHANCED_CAP_ID_S 0 -+#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ -+#define PCIE_ENHANCED_CAP_VER_S 16 -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 -+ -+/* Uncorrectable Error Status Register */ -+#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) -+#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ -+#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ -+#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ -+#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ -+#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ -+#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ -+#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ -+#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ -+#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ -+#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ -+#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ -+#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ -+ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ -+ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ -+ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) -+ -+/* Uncorrectable Error Mask Register, Mask means no report */ -+#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) -+ -+/* Uncorrectable Error Severity Register */ -+#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) -+ -+/* Correctable Error Status Register */ -+#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) -+#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ -+#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ -+#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ -+#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ -+#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ -+#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ -+#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ -+ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) -+ -+/* Correctable Error Mask Register */ -+#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) -+ -+/* Advanced Error Capabilities and Control Register */ -+#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) -+#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ -+#define PCIE_AECCR_FIRST_ERR_PTR_S 0 -+#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ -+#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ -+#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ -+#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ -+ -+/* Header Log Register 1 */ -+#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) -+ -+/* Header Log Register 2 */ -+#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) -+ -+/* Header Log Register 3 */ -+#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) -+ -+/* Header Log Register 4 */ -+#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) -+ -+/* Root Error Command Register */ -+#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) -+#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ -+#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ -+#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ -+ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) -+ -+/* Root Error Status Register */ -+#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) -+#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ -+#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ -+#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ -+#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ -+#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ -+#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_RESR_AER_INT_MSG_NUM_S 27 -+ -+/* Error Source Indentification Register */ -+#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 -+ -+/* VC Enhanced Capability Header */ -+#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) -+ -+/* Port VC Capability Register */ -+#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) -+#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ -+#define PCIE_PVC1_EXT_VC_CNT_S 0 -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 -+#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ -+#define PCIE_PVC1_REF_CLK_S 8 -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 -+ -+/* Extended Virtual Channel Count Defintion */ -+#define PCIE_EXT_VC_CNT_MIN 0 -+#define PCIE_EXT_VC_CNT_MAX 7 -+ -+/* Port Arbitration Table Entry Size Definition */ -+enum { -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, -+}; -+ -+/* Port VC Capability Register 2 */ -+#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) -+#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ -+#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_PVC2_VC_ARB_WRR 0x0000000F -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 -+ -+/* Port VC Control and Status Register */ -+#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) -+#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ -+#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ -+#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 -+#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ -+ -+/* VC0 Resource Capability Register */ -+#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) -+#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ -+#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ -+ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ -+ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) -+ -+#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 -+ -+/* VC0 Resource Control Register */ -+#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) -+#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ -+#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ -+#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ -+#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ -+#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ -+#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ -+#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ -+#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ -+#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ -+ -+#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 -+#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ -+#define PCIE_VC0_RC0_VC_ID_S 24 -+#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ -+ -+/* VC0 Resource Status Register */ -+#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) -+#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ -+#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ -+ -+/* Ack Latency Timer and Replay Timer Register */ -+#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 -+ -+/* Other Message Register */ -+#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) -+ -+/* Port Force Link Register */ -+#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) -+#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ -+#define PCIE_PFLR_LINK_NUM_S 0 -+#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ -+#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ -+#define PCIE_PFLR_LINK_STATE_S 16 -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 -+ -+/* Ack Frequency Register */ -+#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) -+#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ -+#define PCIE_AFR_AF_S 0 -+#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ -+#define PCIE_AFR_FTS_NUM_S 8 -+#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ -+#define PCIE_AFR_COM_FTS_NUM_S 16 -+#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ -+#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 -+#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ -+#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 -+#define PCIE_AFR_FTS_NUM_DEFAULT 32 -+#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 -+#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 -+ -+/* Port Link Control Register */ -+#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) -+#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ -+#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ -+#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ -+#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ -+#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ -+#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ -+#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ -+#define PCIE_PLCR_LINK_MODE_S 16 -+#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ -+ -+/* Lane Skew Register */ -+#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) -+#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ -+#define PCIE_LSR_LANE_SKEW_NUM_S 0 -+#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ -+#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ -+#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ -+ -+/* Symbol Number Register */ -+#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) -+#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ -+#define PCIE_SNR_TS_S 0 -+#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ -+#define PCIE_SNR_SKP_S 8 -+#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ -+#define PCIE_SNR_REPLAY_TIMER_S 14 -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 -+#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ -+#define PCIE_SNR_FC_TIMER_S 28 -+ -+/* Symbol Timer Register and Filter Mask Register 1 */ -+#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) -+#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ -+#define PCIE_STRFMR_SKP_INTERVAL_S 0 -+#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ -+#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ -+#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ -+#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ -+#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ -+#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ -+#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ -+#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ -+#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ -+#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ -+#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ -+#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ -+ -+#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ -+ -+/* Filter Masker Register 2 */ -+#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) -+#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ -+#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ -+ -+/* Debug Register 0 */ -+#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) -+ -+/* Debug Register 1 */ -+#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) -+ -+/* Transmit Posted FC Credit Status Register */ -+#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Non-Posted FC Credit Status */ -+#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Complete FC Credit Status Register */ -+#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 -+ -+/* Queue Status Register */ -+#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) -+#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ -+#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ -+#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ -+ -+/* VC Transmit Arbitration Register 1 */ -+#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) -+#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ -+ -+/* VC Transmit Arbitration Register 2 */ -+#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) -+#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ -+ -+/* VC0 Posted Receive Queue Control Register */ -+#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 -+#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ -+#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ -+ -+/* VC0 Non-Posted Receive Queue Control */ -+#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 -+ -+/* VC0 Completion Receive Queue Control */ -+#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 -+ -+/* Applicable to the above three registers */ -+enum { -+ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, -+ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, -+ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, -+}; -+ -+/* VC0 Posted Buffer Depth Register */ -+#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Non-Posted Buffer Depth Register */ -+#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Completion Buffer Depth Register */ -+#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 -+ -+/* PHY Status Register, all zeros in VR9 */ -+#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) -+ -+/* PHY Control Register, all zeros in VR9 */ -+#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) -+ -+/* -+ * PCIe PDI PHY register definition, suppose all the following -+ * stuff is confidential. -+ * XXX, detailed bit definition -+ */ -+#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) -+#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) -+#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) -+#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) -+#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) -+#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) -+#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) -+#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) -+#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) -+#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) -+#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) -+ -+#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) -+#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) -+#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) -+#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) -+#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) -+#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) -+#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) -+#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) -+ -+#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) -+#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) -+#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) -+#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) -+#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) -+#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) -+#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) -+ -+#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) -+#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) -+#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) -+#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) -+#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) -+ -+/* Interrupt related stuff */ -+#define PCIE_LEGACY_DISABLE 0 -+#define PCIE_LEGACY_INTA 1 -+#define PCIE_LEGACY_INTB 2 -+#define PCIE_LEGACY_INTC 3 -+#define PCIE_LEGACY_INTD 4 -+#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD -+ -+#define PCIE_IRQ_LOCK(lock) do { \ -+ unsigned long flags; \ -+ spin_lock_irqsave(&(lock), flags); -+#define PCIE_IRQ_UNLOCK(lock) \ -+ spin_unlock_irqrestore(&(lock), flags); \ -+} while (0) -+ -+#define PCIE_MSG_MSI 0x00000001 -+#define PCIE_MSG_ISR 0x00000002 -+#define PCIE_MSG_FIXUP 0x00000004 -+#define PCIE_MSG_READ_CFG 0x00000008 -+#define PCIE_MSG_WRITE_CFG 0x00000010 -+#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) -+#define PCIE_MSG_REG 0x00000020 -+#define PCIE_MSG_INIT 0x00000040 -+#define PCIE_MSG_ERR 0x00000080 -+#define PCIE_MSG_PHY 0x00000100 -+#define PCIE_MSG_ANY 0x000001ff -+ -+#define IFX_PCIE_PORT0 0 -+#define IFX_PCIE_PORT1 1 -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+#define IFX_PCIE_CORE_NR 2 -+#else -+#define IFX_PCIE_CORE_NR 1 -+#endif -+ -+//#define IFX_PCIE_ERROR_INT -+ -+//#define IFX_PCIE_DBG -+ -+#if defined(IFX_PCIE_DBG) -+#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ -+ if (g_pcie_debug_flag & (_m)) { \ -+ ifx_pcie_debug((_fmt), ##args); \ -+ } \ -+} while (0) -+ -+#define INLINE -+#else -+#define IFX_PCIE_PRINT(_m, _fmt, args...) \ -+ do {} while(0) -+#define INLINE inline -+#endif -+ -+struct ifx_pci_controller { -+ struct pci_controller pcic; -+ -+ /* RC specific, per host bus information */ -+ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ -+}; -+ -+typedef struct ifx_pcie_ir_irq { -+ const unsigned int irq; -+ const char name[16]; -+}ifx_pcie_ir_irq_t; -+ -+typedef struct ifx_pcie_legacy_irq{ -+ const u32 irq_bit; -+ const int irq; -+}ifx_pcie_legacy_irq_t; -+ -+typedef struct ifx_pcie_irq { -+ ifx_pcie_ir_irq_t ir_irq; -+ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; -+}ifx_pcie_irq_t; -+ -+extern u32 g_pcie_debug_flag; -+extern void ifx_pcie_debug(const char *fmt, ...); -+extern void pcie_phy_clock_mode_setup(int pcie_port); -+extern void pcie_msi_pic_init(int pcie_port); -+extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); -+extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); -+ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define IFX_PCIE_GPIO_RESET 38 -+#define IFX_REG_R32 ltq_r32 -+#define IFX_REG_W32 ltq_w32 -+#define CONFIG_IFX_PCIE_HW_SWAP -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ -+#define IFX_PMU1_MODULE_PCIE_PHY (0) -+#define IFX_PMU1_MODULE_PCIE_CTRL (1) -+#define IFX_PMU1_MODULE_PDI (4) -+#define IFX_PMU1_MODULE_MSI (5) -+ -+#define IFX_PMU_MODULE_PCIE_L0_CLK (31) -+ -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "ahb"); -+ clk_enable(clk); -+ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg |= IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#else -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg &= ~IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "phy"); -+ clk_enable(clk); -+ //ltq_pmu1_enable(1<PCIe and PDI endianness */ -+ reg |= IFX_RCU_AHB_BE_PCIE_PDI; -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "pdi"); -+ clk_enable(clk); -+ //ltq_pmu1_enable(1< 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+#endif /* CONFIG_PCI_LANTIQ */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ #endif /* CONFIG_PCI_LANTIQ */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_VR9_H */ -+ ---- a/drivers/pci/pcie/Kconfig -+++ b/drivers/pci/pcie/Kconfig -@@ -51,6 +51,7 @@ config PCIEAER_INJECT - config PCIE_ECRC - bool "PCI Express ECRC settings control" - depends on PCIEAER -+ default n - help - Used to override firmware/bios settings for PCI Express ECRC - (transaction layer end-to-end CRC checking). ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -1421,6 +1421,8 @@ void pci_walk_bus(struct pci_bus *top, i - void *userdata); - int pci_cfg_space_size(struct pci_dev *dev); - unsigned char pci_bus_max_busnr(struct pci_bus *bus); -+int pcibios_host_nr(void); -+int pcibios_1st_host_bus_nr(void); - void pci_setup_bridge(struct pci_bus *bus); - resource_size_t pcibios_window_alignment(struct pci_bus *bus, - unsigned long type); ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -1079,6 +1079,12 @@ - #define PCI_DEVICE_ID_SGI_IOC3 0x0003 - #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 - -+#define PCI_VENDOR_ID_INFINEON 0x15D1 -+#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F -+#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 -+#define PCI_VENDOR_ID_LANTIQ 0x1BEF -+#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 -+ - #define PCI_VENDOR_ID_WINBOND 0x10ad - #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 - #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-5.10/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-5.10/0004-MIPS-lantiq-add-atm-hack.patch deleted file mode 100644 index e215df60ee..0000000000 --- a/target/linux/lantiq/patches-5.10/0004-MIPS-lantiq-add-atm-hack.patch +++ /dev/null @@ -1,482 +0,0 @@ -From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 3 Aug 2012 10:27:25 +0200 -Subject: [PATCH 04/36] MIPS: lantiq: add atm hack - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ - arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ - arch/mips/lantiq/irq.c | 2 + - arch/mips/mm/cache.c | 4 + - include/uapi/linux/atm.h | 6 + - net/atm/common.c | 6 + - net/atm/proc.c | 2 +- - 7 files changed, 416 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h -@@ -0,0 +1,196 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_atm.h -+** PROJECT : UEIP -+** MODULES : ATM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global ATM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_ATM_H -+#define IFX_ATM_H -+ -+ -+ -+/*! -+ \defgroup IFX_ATM UEIP Project - ATM driver module -+ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_IOCTL IOCTL Commands -+ \ingroup IFX_ATM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_STRUCT Structures -+ \ingroup IFX_ATM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_atm.h -+ \ingroup IFX_ATM -+ \brief ATM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ATM MIB -+ */ -+ -+/*! -+ \struct atm_cell_ifEntry_t -+ \brief Structure used for Cell Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifInErrors; /*!< counter of error ingress cells */ -+ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ -+ __u32 ifOutErrors; /*!< counter of error egress cells */ -+} atm_cell_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_ifEntry_t -+ \brief Structure used for AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifInUcastPkts; /*!< counter of ingress packets */ -+ __u32 ifOutUcastPkts; /*!< counter of egress packets */ -+ __u32 ifInErrors; /*!< counter of error ingress packets */ -+ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ -+ __u32 ifOutErros; /*!< counter of error egress packets */ -+ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ -+} atm_aal5_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_vcc_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ This structure is a part of structure "atm_aal5_vcc_x_t". -+ */ -+typedef struct { -+ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ -+ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet -+ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ -+} atm_aal5_vcc_t; -+ -+/*! -+ \struct atm_aal5_vcc_x_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". -+ */ -+typedef struct { -+ int vpi; /*!< VPI of the VCC to get MIB counters */ -+ int vci; /*!< VCI of the VCC to get MIB counters */ -+ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ -+} atm_aal5_vcc_x_t; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief ATM IOCTL Magic Number -+ */ -+#define PPE_ATM_IOC_MAGIC 'o' -+/*! -+ \brief ATM IOCTL Command - Get Cell Level MIB Counters -+ -+ This command is obsolete. User can get cell level MIB from DSL API. -+ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters -+ -+ Get AAL5 packet counters. -+ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get Per PVC MIB Counters -+ -+ Get AAL5 packet counters for each PVC. -+ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. -+ */ -+#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) -+/*! -+ \brief Total Number of ATM IOCTL Commands -+ */ -+#define PPE_ATM_IOC_MAXNR 3 -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_ATM_H -+ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h -@@ -0,0 +1,203 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ptm.h -+** PROJECT : UEIP -+** MODULES : PTM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global PTM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_PTM_H -+#define IFX_PTM_H -+ -+ -+ -+/*! -+ \defgroup IFX_PTM UEIP Project - PTM driver module -+ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_IOCTL IOCTL Commands -+ \ingroup IFX_PTM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_STRUCT Structures -+ \ingroup IFX_PTM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_ptm.h -+ \ingroup IFX_PTM -+ \brief PTM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_PTM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief PTM IOCTL Command - Get codeword MIB counters. -+ -+ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. -+ */ -+#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 -+/*! -+ \brief PTM IOCTL Command - Get packet MIB counters. -+ -+ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. -+ */ -+#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 -+/*! -+ \brief PTM IOCTL Command - Get firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 -+/*! -+ \brief PTM IOCTL Command - Set firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 -+/*! -+ \brief PTM IOCTL Command - Program priority value to TX queue mapping. -+ -+ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. -+ */ -+#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 -+ -+/*@}*/ -+ -+ -+/*! -+ \addtogroup IFX_PTM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Data Type -+ */ -+ -+/*! -+ \typedef PTM_CW_IF_ENTRY_T -+ \brief Wrapping of structure "ptm_cw_ifEntry_t". -+ */ -+/*! -+ \struct ptm_cw_ifEntry_t -+ \brief Structure used for CodeWord level MIB counters. -+ */ -+typedef struct ptm_cw_ifEntry_t { -+ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ -+ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ -+ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ -+ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ -+ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ -+} PTM_CW_IF_ENTRY_T; -+ -+/*! -+ \typedef PTM_FRAME_MIB_T -+ \brief Wrapping of structure "ptm_frame_mib_t". -+ */ -+/*! -+ \struct ptm_frame_mib_t -+ \brief Structure used for packet level MIB counters. -+ */ -+typedef struct ptm_frame_mib_t { -+ uint32_t RxCorrect; /*!< output, number of ingress packet */ -+ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ -+ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ -+ uint32_t TxSend; /*!< output, number of egress packet */ -+} PTM_FRAME_MIB_T; -+ -+/*! -+ \typedef IFX_PTM_CFG_T -+ \brief Wrapping of structure "ptm_cfg_t". -+ */ -+/*! -+ \struct ptm_cfg_t -+ \brief Structure used for ETH/TC CRC configuration. -+ */ -+typedef struct ptm_cfg_t { -+ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ -+ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ -+ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ -+ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ -+ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ -+ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ -+ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ -+} IFX_PTM_CFG_T; -+ -+/*! -+ \typedef IFX_PTM_PRIO_Q_MAP_T -+ \brief Wrapping of structure "ppe_prio_q_map". -+ */ -+/*! -+ \struct ppe_prio_q_map -+ \brief Structure used for Priority Value to TX Queue mapping. -+ */ -+typedef struct ppe_prio_q_map { -+ int pkt_prio; -+ int qid; -+ int vpi; // ignored in eth interface -+ int vci; // ignored in eth interface -+} IFX_PTM_PRIO_Q_MAP_T; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_PTM_H -+ ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -91,6 +92,7 @@ void ltq_disable_irq(struct irq_data *d) - } - raw_spin_unlock_irqrestore(<q_icu_lock, flags); - } -+EXPORT_SYMBOL(ltq_mask_and_ack_irq); - - void ltq_mask_and_ack_irq(struct irq_data *d) - { ---- a/arch/mips/mm/cache.c -+++ b/arch/mips/mm/cache.c -@@ -61,6 +61,10 @@ void (*_dma_cache_wback_inv)(unsigned lo - void (*_dma_cache_wback)(unsigned long start, unsigned long size); - void (*_dma_cache_inv)(unsigned long start, unsigned long size); - -+EXPORT_SYMBOL(_dma_cache_wback_inv); -+EXPORT_SYMBOL(_dma_cache_wback); -+EXPORT_SYMBOL(_dma_cache_inv); -+ - #endif /* CONFIG_DMA_NONCOHERENT */ - - /* ---- a/include/uapi/linux/atm.h -+++ b/include/uapi/linux/atm.h -@@ -131,8 +131,14 @@ - #define ATM_ABR 4 - #define ATM_ANYCLASS 5 /* compatible with everything */ - -+#define ATM_VBR_NRT ATM_VBR -+#define ATM_VBR_RT 6 -+#define ATM_UBR_PLUS 7 -+#define ATM_GFR 8 -+ - #define ATM_MAX_PCR -1 /* maximum available PCR */ - -+ - struct atm_trafprm { - unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ - int max_pcr; /* maximum PCR in cells per second */ ---- a/net/atm/proc.c -+++ b/net/atm/proc.c -@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil - static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) - { - static const char *const class_name[] = { -- "off", "UBR", "CBR", "VBR", "ABR"}; -+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; - static const char *const aal_name[] = { - "---", "1", "2", "3/4", /* 0- 3 */ - "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-5.10/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-5.10/0008-MIPS-lantiq-backport-old-timer-code.patch deleted file mode 100644 index 1d869afd9a..0000000000 --- a/target/linux/lantiq/patches-5.10/0008-MIPS-lantiq-backport-old-timer-code.patch +++ /dev/null @@ -1,1035 +0,0 @@ -From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:30:56 +0200 -Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ - arch/mips/lantiq/xway/Makefile | 2 +- - arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ - 3 files changed, 1001 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h - create mode 100644 arch/mips/lantiq/xway/timer.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h -@@ -0,0 +1,155 @@ -+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+ -+ -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/* -+ * Available Timer/Counter Index -+ */ -+#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) -+#define TIMER_ANY 0x00 -+#define TIMER1A TIMER(1, 0) -+#define TIMER1B TIMER(1, 1) -+#define TIMER2A TIMER(2, 0) -+#define TIMER2B TIMER(2, 1) -+#define TIMER3A TIMER(3, 0) -+#define TIMER3B TIMER(3, 1) -+ -+/* -+ * Flag of Timer/Counter -+ * These flags specify the way in which timer is configured. -+ */ -+/* Bit size of timer/counter. */ -+#define TIMER_FLAG_16BIT 0x0000 -+#define TIMER_FLAG_32BIT 0x0001 -+/* Switch between timer and counter. */ -+#define TIMER_FLAG_TIMER 0x0000 -+#define TIMER_FLAG_COUNTER 0x0002 -+/* Stop or continue when overflowing/underflowing. */ -+#define TIMER_FLAG_ONCE 0x0000 -+#define TIMER_FLAG_CYCLIC 0x0004 -+/* Count up or counter down. */ -+#define TIMER_FLAG_UP 0x0000 -+#define TIMER_FLAG_DOWN 0x0008 -+/* Count on specific level or edge. */ -+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 -+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 -+#define TIMER_FLAG_RISE_EDGE 0x0010 -+#define TIMER_FLAG_FALL_EDGE 0x0020 -+#define TIMER_FLAG_ANY_EDGE 0x0030 -+/* Signal is syncronous to module clock or not. */ -+#define TIMER_FLAG_UNSYNC 0x0000 -+#define TIMER_FLAG_SYNC 0x0080 -+/* Different interrupt handle type. */ -+#define TIMER_FLAG_NO_HANDLE 0x0000 -+#if defined(__KERNEL__) -+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 -+#endif // defined(__KERNEL__) -+#define TIMER_FLAG_SIGNAL 0x0300 -+/* Internal clock source or external clock source */ -+#define TIMER_FLAG_INT_SRC 0x0000 -+#define TIMER_FLAG_EXT_SRC 0x1000 -+ -+ -+/* -+ * ioctl Command -+ */ -+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ -+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ -+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ -+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ -+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ -+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ -+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ -+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ -+ -+/* -+ * Data Type Used to Call ioctl -+ */ -+struct gptu_ioctl_param { -+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field is ID of expected * -+ * timer/counter. If it's zero, a timer/counter would * -+ * be dynamically allocated and ID would be stored in * -+ * this field. * -+ * In command GPTU_GET_COUNT_VALUE, this field is * -+ * ignored. * -+ * In other command, this field is ID of timer/counter * -+ * allocated. */ -+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field contains flags to * -+ * specify how to configure timer/counter. * -+ * In command GPTU_START_TIMER, zero indicate start * -+ * and non-zero indicate resume timer/counter. * -+ * In other command, this field is ignored. */ -+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * -+ * init/reload value. * -+ * In command GPTU_SET_TIMER, this field contains * -+ * frequency (0.001Hz) of timer. * -+ * In command GPTU_GET_COUNT_VALUE, current count * -+ * value would be stored in this field. * -+ * In command GPTU_CALCULATE_DIVIDER, this field * -+ * contains frequency wanted, and after calculation, * -+ * divider would be stored in this field to overwrite * -+ * the frequency. * -+ * In other command, this field is ignored. */ -+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains process * -+ * ID to which signal would be sent. * -+ * In other command, this field is ignored. */ -+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains signal * -+ * number which would be sent. * -+ * In other command, this field is ignored. */ -+}; -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+typedef void (*timer_callback)(unsigned long arg); -+ -+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); -+extern int lq_free_timer(unsigned int); -+extern int lq_start_timer(unsigned int, int); -+extern int lq_stop_timer(unsigned int); -+extern int lq_reset_counter_flags(u32 timer, u32 flags); -+extern int lq_get_count_value(unsigned int, unsigned long *); -+extern u32 lq_cal_divider(unsigned long); -+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -+extern int lq_set_counter(unsigned int timer, unsigned int flag, -+ u32 reload, unsigned long arg1, unsigned long arg2); -+ -+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,4 +1,10 @@ - # SPDX-License-Identifier: GPL-2.0-only --obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o -+obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o -+ -+ifdef CONFIG_SOC_AMAZON_SE -+obj-y += gptu.o -+else -+obj-y += timer.o -+endif - - obj-y += vmmc.o ---- /dev/null -+++ b/arch/mips/lantiq/xway/timer.c -@@ -0,0 +1,846 @@ -+#ifndef CONFIG_SOC_AMAZON_SE -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "../clk.h" -+ -+#include -+#include -+#include -+ -+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 -+ -+#ifdef TIMER1A -+#define FIRST_TIMER TIMER1A -+#else -+#define FIRST_TIMER 2 -+#endif -+ -+/* -+ * GPTC divider is set or not. -+ */ -+#define GPTU_CLC_RMC_IS_SET 0 -+ -+/* -+ * Timer Interrupt (IRQ) -+ */ -+/* Must be adjusted when ICU driver is available */ -+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) -+ -+/* -+ * Bits Operation -+ */ -+#define GET_BITS(x, msb, lsb) \ -+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -+#define SET_BITS(x, msb, lsb, value) \ -+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ -+ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) -+ -+/* -+ * GPTU Register Mapping -+ */ -+#define LQ_GPTU (KSEG1 + 0x1E100A00) -+#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) -+#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) -+#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) -+#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) -+#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) -+ -+/* -+ * Clock Control Register -+ */ -+#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) -+#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) -+#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) -+#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) -+#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) -+#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) -+#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) -+ -+#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) -+#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) -+#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) -+ -+/* -+ * ID Register -+ */ -+#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) -+#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) -+#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) -+ -+/* -+ * Control Register of Timer/Counter nX -+ * n is the index of block (1 based index) -+ * X is either A or B -+ */ -+#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) -+#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) -+#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) -+#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) -+#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) -+#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ -+#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) -+#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) -+#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) -+#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) -+ -+#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) -+#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) -+#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) -+#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) -+#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) -+ -+#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) -+#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) -+ -+#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+ -+#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) -+#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) -+#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) -+#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) -+#define TIMER_FLAG_NONE_EDGE 0x0000 -+#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) -+#define TIMER_FLAG_REAL 0x0000 -+#define TIMER_FLAG_INVERT 0x0040 -+#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) -+#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) -+#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) -+#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 -+#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) -+#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) -+ -+struct timer_dev_timer { -+ unsigned int f_irq_on; -+ unsigned int irq; -+ unsigned int flag; -+ unsigned long arg1; -+ unsigned long arg2; -+}; -+ -+struct timer_dev { -+ struct mutex gptu_mutex; -+ unsigned int number_of_timers; -+ unsigned int occupation; -+ unsigned int f_gptu_on; -+ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; -+}; -+ -+ -+unsigned int ltq_get_fpi_bus_clock(int fpi) { -+ struct clk *clk = clk_get_fpi(); -+ return clk_get_rate(clk); -+} -+ -+ -+static long gptu_ioctl(struct file *, unsigned int, unsigned long); -+static int gptu_open(struct inode *, struct file *); -+static int gptu_release(struct inode *, struct file *); -+ -+static struct file_operations gptu_fops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = gptu_ioctl, -+ .open = gptu_open, -+ .release = gptu_release -+}; -+ -+static struct miscdevice gptu_miscdev = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = "gptu", -+ .fops = &gptu_fops, -+}; -+ -+static struct timer_dev timer_dev; -+ -+static irqreturn_t timer_irq_handler(int irq, void *p) -+{ -+ unsigned int timer; -+ unsigned int flag; -+ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; -+ -+ timer = irq - TIMER_INTERRUPT; -+ if (timer < timer_dev.number_of_timers -+ && dev_timer == &timer_dev.timer[timer]) { -+ /* Clear interrupt. */ -+ ltq_w32(1 << timer, LQ_GPTU_IRNCR); -+ -+ /* Call user hanler or signal. */ -+ flag = dev_timer->flag; -+ if (!(timer & 0x01) -+ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ /* 16-bit timer or timer A of 32-bit timer */ -+ switch (TIMER_FLAG_MASK_HANDLE(flag)) { -+ case TIMER_FLAG_CALLBACK_IN_IRQ: -+ case TIMER_FLAG_CALLBACK_IN_HB: -+ if (dev_timer->arg1) -+ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); -+ break; -+ case TIMER_FLAG_SIGNAL: -+ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); -+ break; -+ } -+ } -+ } -+ return IRQ_HANDLED; -+} -+ -+static inline void lq_enable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); -+ clk_enable(clk); -+ -+ //ltq_pmu_enable(PMU_GPT); -+ -+ /* Set divider as 1, disable write protection for SPEN, enable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x01) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(1) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(0); -+} -+ -+static inline void lq_disable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); -+ ltq_w32(0x00, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ /* Set divider as 0, enable write protection for SPEN, disable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x00) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(0) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(1); -+ -+ clk_enable(clk); -+} -+ -+int lq_request_timer(unsigned int timer, unsigned int flag, -+ unsigned long value, unsigned long arg1, unsigned long arg2) -+{ -+ int ret = 0; -+ unsigned int con_reg, irnen_reg; -+ int n, X; -+ -+ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", -+ timer, flag, value); -+ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) -+ value &= 0xFFFF; -+ else -+ timer &= ~0x01; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ /* -+ * Allocate timer. -+ */ -+ if (timer < FIRST_TIMER) { -+ unsigned int mask; -+ unsigned int shift; -+ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ -+ unsigned int offset = TIMER2A; -+ -+ /* -+ * Pick up a free timer. -+ */ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ mask = 1 << offset; -+ shift = 1; -+ } else { -+ mask = 3 << offset; -+ shift = 2; -+ } -+ for (timer = offset; -+ timer < offset + timer_dev.number_of_timers; -+ timer += shift, mask <<= shift) -+ if (!(timer_dev.occupation & mask)) { -+ timer_dev.occupation |= mask; -+ break; -+ } -+ if (timer >= offset + timer_dev.number_of_timers) { -+ printk("failed![%d]\n", __LINE__); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } else -+ ret = timer; -+ } else { -+ register unsigned int mask; -+ -+ /* -+ * Check if the requested timer is free. -+ */ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if ((timer_dev.occupation & mask)) { -+ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", -+ __LINE__, mask, timer_dev.occupation); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EBUSY; -+ } else { -+ timer_dev.occupation |= mask; -+ ret = 0; -+ } -+ } -+ -+ /* -+ * Prepare control register value. -+ */ -+ switch (TIMER_FLAG_MASK_EDGE(flag)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : -+ GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : -+ GPTU_CON_SRC_EG_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_SYNC(flag) == -+ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : -+ GPTU_CON_SYNC_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_INVERT(flag) == -+ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : -+ GPTU_CON_EXT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_STOP(flag) == -+ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_TYPE(flag) == -+ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : -+ GPTU_CON_CNT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_DIR(flag) == -+ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ /* -+ * Fill up running data. -+ */ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flag; -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; -+ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; -+ -+ /* -+ * Enable GPTU module. -+ */ -+ if (!timer_dev.f_gptu_on) { -+ lq_enable_gptu(); -+ timer_dev.f_gptu_on = 1; -+ } -+ -+ /* -+ * Enable IRQ. -+ */ -+ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = -+ (unsigned long) find_task_by_vpid((int) arg1); -+ -+ irnen_reg = 1 << (timer - FIRST_TIMER); -+ -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL -+ || (TIMER_FLAG_MASK_HANDLE(flag) == -+ TIMER_FLAG_CALLBACK_IN_IRQ -+ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { -+ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; -+ } -+ } else -+ irnen_reg = 0; -+ -+ /* -+ * Write config register, reload value and enable interrupt. -+ */ -+ n = timer >> 1; -+ X = timer & 0x01; -+ *LQ_GPTU_CON(n, X) = con_reg; -+ *LQ_GPTU_RELOAD(n, X) = value; -+ /* printk("reload value = %d\n", (u32)value); */ -+ *LQ_GPTU_IRNEN |= irnen_reg; -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ printk("successful!\n"); -+ return ret; -+} -+EXPORT_SYMBOL(lq_request_timer); -+ -+int lq_free_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ if (GPTU_CON_EN(n, X)) -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); -+ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); -+ -+ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { -+ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; -+ } -+ -+ timer_dev.occupation &= ~mask; -+ if (!timer_dev.occupation && timer_dev.f_gptu_on) { -+ lq_disable_gptu(); -+ timer_dev.f_gptu_on = 0; -+ } -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_free_timer); -+ -+int lq_start_timer(unsigned int timer, int is_resume) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); -+ -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_start_timer); -+ -+int lq_stop_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_stop_timer); -+ -+int lq_reset_counter_flags(u32 timer, u32 flags) -+{ -+ unsigned int oflag; -+ unsigned int mask, con_reg; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ switch (TIMER_FLAG_MASK_EDGE(flags)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); -+ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); -+ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flags; -+ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_CON(n, X) = con_reg; -+ smp_wmb(); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return 0; -+} -+EXPORT_SYMBOL(lq_reset_counter_flags); -+ -+int lq_get_count_value(unsigned int timer, unsigned long *value) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *value = *LQ_GPTU_COUNT(n, X); -+ -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_get_count_value); -+ -+u32 lq_cal_divider(unsigned long freq) -+{ -+ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); -+ u32 clock_divider = 1; -+ module_freq = fpi * 1000; -+ do_div(module_freq, clock_divider * freq); -+ return module_freq; -+} -+EXPORT_SYMBOL(lq_cal_divider); -+ -+int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, -+ int is_ext_src, unsigned int handle_flag, unsigned long arg1, -+ unsigned long arg2) -+{ -+ unsigned long divider; -+ unsigned int flag; -+ -+ divider = lq_cal_divider(freq); -+ if (divider == 0) -+ return -EINVAL; -+ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) -+ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) -+ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) -+ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN -+ | TIMER_FLAG_MASK_HANDLE(handle_flag); -+ -+ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", -+ timer, freq, divider); -+ return lq_request_timer(timer, flag, divider, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_timer); -+ -+int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, -+ unsigned long arg1, unsigned long arg2) -+{ -+ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); -+ return lq_request_timer(timer, flag, reload, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_counter); -+ -+static long gptu_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ int ret; -+ struct gptu_ioctl_param param; -+ -+ if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ copy_from_user(¶m, (void __user *)arg, sizeof(param)); -+ -+ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER -+ || GPTU_SET_COUNTER) && param.timer < 2) -+ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) -+ && !access_ok((void __user *)arg, -+ sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ -+ switch (cmd) { -+ case GPTU_REQUEST_TIMER: -+ ret = lq_request_timer(param.timer, param.flag, param.value, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ case GPTU_FREE_TIMER: -+ ret = lq_free_timer(param.timer); -+ break; -+ case GPTU_START_TIMER: -+ ret = lq_start_timer(param.timer, param.flag); -+ break; -+ case GPTU_STOP_TIMER: -+ ret = lq_stop_timer(param.timer); -+ break; -+ case GPTU_GET_COUNT_VALUE: -+ ret = lq_get_count_value(param.timer, ¶m.value); -+ if (!ret) -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value)); -+ break; -+ case GPTU_CALCULATE_DIVIDER: -+ param.value = lq_cal_divider(param.value); -+ if (param.value == 0) -+ ret = -EINVAL; -+ else { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value)); -+ ret = 0; -+ } -+ break; -+ case GPTU_SET_TIMER: -+ ret = lq_set_timer(param.timer, param.value, -+ TIMER_FLAG_MASK_STOP(param.flag) != -+ TIMER_FLAG_ONCE ? 1 : 0, -+ TIMER_FLAG_MASK_SRC(param.flag) == -+ TIMER_FLAG_EXT_SRC ? 1 : 0, -+ TIMER_FLAG_MASK_HANDLE(param.flag) == -+ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : -+ TIMER_FLAG_NO_HANDLE, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ case GPTU_SET_COUNTER: -+ lq_set_counter(param.timer, param.flag, param.value, 0, 0); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ default: -+ ret = -ENOTTY; -+ } -+ -+ return ret; -+} -+ -+static int gptu_open(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+static int gptu_release(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+int __init lq_gptu_init(void) -+{ -+ int ret; -+ unsigned int i; -+ -+ ltq_w32(0, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ memset(&timer_dev, 0, sizeof(timer_dev)); -+ mutex_init(&timer_dev.gptu_mutex); -+ -+ lq_enable_gptu(); -+ timer_dev.number_of_timers = GPTU_ID_CFG * 2; -+ lq_disable_gptu(); -+ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) -+ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; -+ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); -+ -+ ret = misc_register(&gptu_miscdev); -+ if (ret) { -+ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); -+ return ret; -+ } else { -+ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); -+ } -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); -+ if (ret) { -+ for (; i >= 0; i--) -+ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); -+ misc_deregister(&gptu_miscdev); -+ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); -+ return ret; -+ } else { -+ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; -+ disable_irq(timer_dev.timer[i].irq); -+ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); -+ } -+ } -+ -+ return 0; -+} -+ -+void __exit lq_gptu_exit(void) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ if (timer_dev.timer[i].f_irq_on) -+ disable_irq(timer_dev.timer[i].irq); -+ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); -+ } -+ lq_disable_gptu(); -+ misc_deregister(&gptu_miscdev); -+} -+ -+module_init(lq_gptu_init); -+module_exit(lq_gptu_exit); -+ -+#endif diff --git a/target/linux/lantiq/patches-5.10/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-5.10/0018-MTD-nand-lots-of-xrx200-fixes.patch deleted file mode 100644 index 35f656da6e..0000000000 --- a/target/linux/lantiq/patches-5.10/0018-MTD-nand-lots-of-xrx200-fixes.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 9 Sep 2014 23:12:15 +0200 -Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes - -Signed-off-by: John Crispin ---- - drivers/mtd/nand/raw/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 63 insertions(+) - ---- a/drivers/mtd/nand/raw/xway_nand.c -+++ b/drivers/mtd/nand/raw/xway_nand.c -@@ -61,6 +61,24 @@ - #define NAND_CON_CSMUX (1 << 1) - #define NAND_CON_NANDM 1 - -+#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) -+#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) -+#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) -+ -+/* -+ * req_mask provides a mechanism to prevent interference between -+ * nand and pci (probably only relevant for the BT Home Hub 2B). -+ * Setting it causes the corresponding pci req pins to be masked -+ * during nand access, and also moves ebu locking from the read/write -+ * functions to the chip select function to ensure that the whole -+ * operation runs with interrupts disabled. -+ * In addition it switches on some extra waiting in xway_cmd_ctrl(). -+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, -+ * which in turn seems to be necessary for the nor chip to be recognised -+ * reliably, on a board (Home Hub 2B again) which has both nor and nand. -+ */ -+static __be32 req_mask = 0; -+ - struct xway_nand_data { - struct nand_controller controller; - struct nand_chip chip; -@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand - case -1: - ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); - ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); -+ -+ if (req_mask) { -+ /* Unmask all external PCI request */ -+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); -+ } -+ - spin_unlock_irqrestore(&ebu_lock, data->csflags); - break; - case 0: - spin_lock_irqsave(&ebu_lock, data->csflags); -+ -+ if (req_mask) { -+ /* Mask all external PCI request */ -+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); -+ } -+ - ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); - ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); - break; -@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch - { - struct mtd_info *mtd = nand_to_mtd(chip); - -+ if (req_mask) { -+ if (cmd != NAND_CMD_STATUS) -+ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */ -+ } -+ - if (cmd == NAND_CMD_NONE) - return; - -@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch - - while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) - ; -+ -+ if (req_mask) { -+ /* -+ * program and erase have their own busy handlers -+ * status and sequential in needs no delay -+ */ -+ switch (cmd) { -+ case NAND_CMD_ERASE1: -+ case NAND_CMD_SEQIN: -+ case NAND_CMD_STATUS: -+ case NAND_CMD_READID: -+ return; -+ } -+ -+ /* wait until command is processed */ -+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) -+ ; -+ } - } - - static int xway_dev_ready(struct nand_chip *chip) -@@ -170,6 +223,7 @@ static int xway_nand_probe(struct platfo - int err; - u32 cs; - u32 cs_flag = 0; -+ const __be32 *req_mask_ptr; - - /* Allocate memory for the device structure (and zero it) */ - data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), -@@ -206,6 +260,15 @@ static int xway_nand_probe(struct platfo - if (!err && cs == 1) - cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; - -+ req_mask_ptr = of_get_property(pdev->dev.of_node, -+ "req-mask", NULL); -+ -+ /* -+ * Load the PCI req lines to mask from the device tree. If the -+ * property is not present, setting req_mask to 0 disables masking. -+ */ -+ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); -+ - /* setup the EBU to run in NAND mode on our base addr */ - ltq_ebu_w32(CPHYSADDR(data->nandaddr) - | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-5.10/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-5.10/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch deleted file mode 100644 index c1fc59487a..0000000000 --- a/target/linux/lantiq/patches-5.10/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch +++ /dev/null @@ -1,25 +0,0 @@ -From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:18:00 +0200 -Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash - -Signed-off-by: John Crispin ---- - drivers/mtd/maps/lantiq-flash.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/maps/lantiq-flash.c -+++ b/drivers/mtd/maps/lantiq-flash.c -@@ -129,7 +129,11 @@ ltq_mtd_probe(struct platform_device *pd - if (!ltq_mtd->map) - return -ENOMEM; - -- ltq_mtd->map->phys = ltq_mtd->res->start; -+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) -+ ltq_mtd->map->phys = NO_XIP; -+ else -+ ltq_mtd->map->phys = ltq_mtd->res->start; -+ ltq_mtd->res->start; - ltq_mtd->map->size = resource_size(ltq_mtd->res); - ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); - if (IS_ERR(ltq_mtd->map->virt)) diff --git a/target/linux/lantiq/patches-5.10/0023-NET-PHY-add-led-support-for-intel-xway.patch b/target/linux/lantiq/patches-5.10/0023-NET-PHY-add-led-support-for-intel-xway.patch deleted file mode 100644 index fb8d975110..0000000000 --- a/target/linux/lantiq/patches-5.10/0023-NET-PHY-add-led-support-for-intel-xway.patch +++ /dev/null @@ -1,294 +0,0 @@ -From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:15:36 +0200 -Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G - -Signed-off-by: John Crispin ---- - drivers/net/phy/Kconfig | 5 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 237 insertions(+) - create mode 100644 drivers/net/phy/lantiq.c - ---- a/drivers/net/phy/intel-xway.c -+++ b/drivers/net/phy/intel-xway.c -@@ -157,6 +157,51 @@ - #define PHY_ID_PHY11G_VR9_1_2 0xD565A409 - #define PHY_ID_PHY22F_VR9_1_2 0xD565A419 - -+#if IS_ENABLED(CONFIG_OF_MDIO) -+static int vr9_gphy_of_reg_init(struct phy_device *phydev) -+{ -+ u32 tmp; -+ -+ /* store the led values if one was passed by the devicetree */ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp)) -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp); -+ -+ return 0; -+} -+#else -+static int vr9_gphy_of_reg_init(struct phy_device *phydev) -+{ -+ return 0; -+} -+#endif /* CONFIG_OF_MDIO */ -+ - static int xway_gphy_config_init(struct phy_device *phydev) - { - int err; -@@ -204,6 +249,7 @@ static int xway_gphy_config_init(struct - phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); - phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); - -+ vr9_gphy_of_reg_init(phydev); - return 0; - } - ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt -@@ -0,0 +1,216 @@ -+Lanitq PHY binding -+============================================ -+ -+This devicetree binding controls the lantiq ethernet phys led functionality. -+ -+Example: -+ mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "lantiq,xrx200-mdio"; -+ phy5: ethernet-phy@5 { -+ reg = <0x1>; -+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; -+ }; -+ phy11: ethernet-phy@11 { -+ reg = <0x11>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led2h = <0x00>; -+ lantiq,led2l = <0x03>; -+ }; -+ phy12: ethernet-phy@12 { -+ reg = <0x12>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led1h = <0x00>; -+ lantiq,led1l = <0x03>; -+ }; -+ phy13: ethernet-phy@13 { -+ reg = <0x13>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led2h = <0x00>; -+ lantiq,led2l = <0x03>; -+ }; -+ phy14: ethernet-phy@14 { -+ reg = <0x14>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led1h = <0x00>; -+ lantiq,led1l = <0x03>; -+ }; -+ }; -+ -+Register Description -+============================================ -+ -+LEDCH: -+ -+Name Hardware Reset Value -+LEDCH 0x00C5 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| FBF | SBF |RES | NACS | -+========================================= -+ -+Field Bits Type Description -+FBF 7:6 RW Fast Blink Frequency -+ --- -+ 0x0 (00b) F02HZ 2 Hz blinking frequency -+ 0x1 (01b) F04HZ 4 Hz blinking frequency -+ 0x2 (10b) F08HZ 8 Hz blinking frequency -+ 0x3 (11b) F16HZ 16 Hz blinking frequency -+ -+SBF 5:4 RW Slow Blink Frequency -+ --- -+ 0x0 (00b) F02HZ 2 Hz blinking frequency -+ 0x1 (01b) F04HZ 4 Hz blinking frequency -+ 0x2 (10b) F08HZ 8 Hz blinking frequency -+ 0x3 (11b) F16HZ 16 Hz blinking frequency -+ -+NACS 2:0 RW Inverse of Scan Function -+ --- -+ 0x0 (000b) NONE No Function -+ 0x1 (001b) LINK Complex function enabled when link is up -+ 0x2 (010b) PDOWN Complex function enabled when device is powered-down -+ 0x3 (011b) EEE Complex function enabled when device is in EEE mode -+ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running -+ 0x5 (101b) ABIST Complex function enabled when analog self-test is running -+ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running -+ 0x7 (111b) TEST Complex function enabled when test mode is running -+ -+LEDCL: -+ -+Name Hardware Reset Value -+LEDCL 0x0067 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+|RES | SCAN |RES | CBLINK | -+========================================= -+ -+Field Bits Type Description -+SCAN 6:4 RW Complex Scan Configuration -+ --- -+ 000 B NONE No Function -+ 001 B LINK Complex function enabled when link is up -+ 010 B PDOWN Complex function enabled when device is powered-down -+ 011 B EEE Complex function enabled when device is in EEE mode -+ 100 B ANEG Complex function enabled when auto-negotiation is running -+ 101 B ABIST Complex function enabled when analog self-test is running -+ 110 B CDIAG Complex function enabled when cable diagnostics are running -+ 111 B TEST Complex function enabled when test mode is running -+ -+CBLINK 2:0 RW Complex Blinking Configuration -+ --- -+ 000 B NONE No Function -+ 001 B LINK Complex function enabled when link is up -+ 010 B PDOWN Complex function enabled when device is powered-down -+ 011 B EEE Complex function enabled when device is in EEE mode -+ 100 B ANEG Complex function enabled when auto-negotiation is running -+ 101 B ABIST Complex function enabled when analog self-test is running -+ 110 B CDIAG Complex function enabled when cable diagnostics are running -+ 111 B TEST Complex function enabled when test mode is running -+ -+LEDxH: -+ -+Name Hardware Reset Value -+LED0H 0x0070 -+LED1H 0x0020 -+LED2H 0x0040 -+LED3H 0x0040 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| CON | BLINKF | -+========================================= -+ -+Field Bits Type Description -+CON 7:4 RW Constant On Configuration -+ --- -+ 0x0 (0000b) NONE LED does not light up constantly -+ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN LED is on when device is powered-down -+ 0x9 (1001b) EEE LED is on when device is in EEE mode -+ 0xA (1010b) ANEG LED is on when auto-negotiation is running -+ 0xB (1011b) ABIST LED is on when analog self-test is running -+ 0xC (1100b) CDIAG LED is on when cable diagnostics are running -+ -+BLINKF 3:0 RW Fast Blinking Configuration -+ --- -+ 0x0 (0000b) NONE No Blinking -+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN Blink when device is powered-down -+ 0x9 (1001b) EEE Blink when device is in EEE mode -+ 0xA (1010b) ANEG Blink when auto-negotiation is running -+ 0xB (1011b) ABIST Blink when analog self-test is running -+ 0xC (1100b) CDIAG Blink when cable diagnostics are running -+ -+LEDxL: -+ -+Name Hardware Reset Value -+LED0L 0x0003 -+LED1L 0x0000 -+LED2L 0x0000 -+LED3L 0x0020 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| BLINKS | PULSE | -+========================================= -+ -+Field Bits Type Description -+BLINKS 7:4 RW Slow Blinkin Configuration -+ --- -+ 0x0 (0000b) NONE No Blinking -+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN Blink when device is powered-down -+ 0x9 (1001b) EEE Blink when device is in EEE mode -+ 0xA (1010b) ANEG Blink when auto-negotiation is running -+ 0xB (1011b) ABIST Blink when analog self-test is running -+ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning -+ -+PULSE 3:0 RW Pulsing Configuration -+ The pulse field is a mask field by which certain events can be combined -+ --- -+ 0x0 (0000b) NONE No pulsing -+ 0x1 (0001b) TXACT Transmit activity -+ 0x2 (0010b) RXACT Receive activity -+ 0x4 (0100b) COL Collision -+ 0x8 (1000b) RES Reserved diff --git a/target/linux/lantiq/patches-5.10/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-5.10/0028-NET-lantiq-various-etop-fixes.patch deleted file mode 100644 index e9f3ee473b..0000000000 --- a/target/linux/lantiq/patches-5.10/0028-NET-lantiq-various-etop-fixes.patch +++ /dev/null @@ -1,864 +0,0 @@ -From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 9 Sep 2014 22:45:34 +0200 -Subject: [PATCH 28/36] NET: lantiq: various etop fixes - -Signed-off-by: John Crispin ---- - drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- - 1 file changed, 389 insertions(+), 166 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -1,7 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* - * -- * Copyright (C) 2011 John Crispin -+ * Copyright (C) 2011-12 John Crispin - */ - - #include -@@ -20,11 +20,16 @@ - #include - #include - #include -+#include - #include - #include - #include - #include - #include -+#include -+#include -+#include -+#include - - #include - -@@ -32,7 +37,7 @@ - #include - #include - --#define LTQ_ETOP_MDIO 0x11804 -+#define LTQ_ETOP_MDIO_ACC 0x11804 - #define MDIO_REQUEST 0x80000000 - #define MDIO_READ 0x40000000 - #define MDIO_ADDR_MASK 0x1f -@@ -41,44 +46,91 @@ - #define MDIO_REG_OFFSET 0x10 - #define MDIO_VAL_MASK 0xffff - --#define PPE32_CGEN 0x800 --#define LQ_PPE32_ENET_MAC_CFG 0x1840 -+#define LTQ_ETOP_MDIO_CFG 0x11800 -+#define MDIO_CFG_MASK 0x6 -+ -+#define LTQ_ETOP_CFG 0x11808 -+#define LTQ_ETOP_IGPLEN 0x11820 -+#define LTQ_ETOP_MAC_CFG 0x11840 - - #define LTQ_ETOP_ENETS0 0x11850 - #define LTQ_ETOP_MAC_DA0 0x1186C - #define LTQ_ETOP_MAC_DA1 0x11870 --#define LTQ_ETOP_CFG 0x16020 --#define LTQ_ETOP_IGPLEN 0x16080 -+ -+#define MAC_CFG_MASK 0xfff -+#define MAC_CFG_CGEN (1 << 11) -+#define MAC_CFG_DUPLEX (1 << 2) -+#define MAC_CFG_SPEED (1 << 1) -+#define MAC_CFG_LINK (1 << 0) - - #define MAX_DMA_CHAN 0x8 - #define MAX_DMA_CRC_LEN 0x4 - #define MAX_DMA_DATA_LEN 0x600 - - #define ETOP_FTCU BIT(28) --#define ETOP_MII_MASK 0xf --#define ETOP_MII_NORMAL 0xd --#define ETOP_MII_REVERSE 0xe - #define ETOP_PLEN_UNDER 0x40 --#define ETOP_CGEN 0x800 -+#define ETOP_CFG_MII0 0x01 - --/* use 2 static channels for TX/RX */ --#define LTQ_ETOP_TX_CHANNEL 1 --#define LTQ_ETOP_RX_CHANNEL 6 --#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) --#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) -+#define ETOP_CFG_MASK 0xfff -+#define ETOP_CFG_FEN0 (1 << 8) -+#define ETOP_CFG_SEN0 (1 << 6) -+#define ETOP_CFG_OFF1 (1 << 3) -+#define ETOP_CFG_REMII0 (1 << 1) -+#define ETOP_CFG_OFF0 (1 << 0) -+ -+#define LTQ_GBIT_MDIO_CTL 0xCC -+#define LTQ_GBIT_MDIO_DATA 0xd0 -+#define LTQ_GBIT_GCTL0 0x68 -+#define LTQ_GBIT_PMAC_HD_CTL 0x8c -+#define LTQ_GBIT_P0_CTL 0x4 -+#define LTQ_GBIT_PMAC_RX_IPG 0xa8 -+#define LTQ_GBIT_RGMII_CTL 0x78 -+ -+#define PMAC_HD_CTL_AS (1 << 19) -+#define PMAC_HD_CTL_RXSH (1 << 22) -+ -+/* Switch Enable (0=disable, 1=enable) */ -+#define GCTL0_SE 0x80000000 -+/* Disable MDIO auto polling (0=disable, 1=enable) */ -+#define PX_CTL_DMDIO 0x00400000 -+ -+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ -+#define MDC_CLOCK_MASK 0xff000000 -+#define MDC_CLOCK_OFFSET 24 -+ -+/* register information for the gbit's MDIO bus */ -+#define MDIO_XR9_REQUEST 0x00008000 -+#define MDIO_XR9_READ 0x00000800 -+#define MDIO_XR9_WRITE 0x00000400 -+#define MDIO_XR9_REG_MASK 0x1f -+#define MDIO_XR9_ADDR_MASK 0x1f -+#define MDIO_XR9_RD_MASK 0xffff -+#define MDIO_XR9_REG_OFFSET 0 -+#define MDIO_XR9_ADDR_OFFSET 5 -+#define MDIO_XR9_WR_OFFSET 16 - -+#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ -+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) -+ -+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ - #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) - #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) - #define ltq_etop_w32_mask(x, y, z) \ - ltq_w32_mask(x, y, ltq_etop_membase + (z)) - --#define DRV_VERSION "1.0" -+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) -+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) -+#define ltq_gbit_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) -+ -+#define DRV_VERSION "1.2" - - static void __iomem *ltq_etop_membase; -+static void __iomem *ltq_gbit_membase; - - struct ltq_etop_chan { -- int idx; - int tx_free; -+ int irq; - struct net_device *netdev; - struct napi_struct napi; - struct ltq_dma_channel dma; -@@ -88,23 +140,36 @@ struct ltq_etop_chan { - struct ltq_etop_priv { - struct net_device *netdev; - struct platform_device *pdev; -- struct ltq_eth_data *pldata; - struct resource *res; - - struct mii_bus *mii_bus; - -- struct ltq_etop_chan ch[MAX_DMA_CHAN]; -- int tx_free[MAX_DMA_CHAN >> 1]; -+ struct ltq_etop_chan txch; -+ struct ltq_etop_chan rxch; - -- spinlock_t lock; -+ int tx_irq; -+ int rx_irq; -+ -+ unsigned char mac[6]; -+ phy_interface_t mii_mode; -+ -+ spinlock_t lock; -+ -+ struct clk *clk_ppe; -+ struct clk *clk_switch; -+ struct clk *clk_ephy; -+ struct clk *clk_ephycgu; - }; - -+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data); -+ - static int - ltq_etop_alloc_skb(struct ltq_etop_chan *ch) - { - struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - -- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); -+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); - if (!ch->skb[ch->dma.desc]) - return -ENOMEM; - ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev, -@@ -139,8 +204,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan - spin_unlock_irqrestore(&priv->lock, flags); - - skb_put(skb, len); -+ skb->dev = ch->netdev; - skb->protocol = eth_type_trans(skb, ch->netdev); - netif_receive_skb(skb); -+ ch->netdev->stats.rx_packets++; -+ ch->netdev->stats.rx_bytes += len; - } - - static int -@@ -148,7 +216,9 @@ ltq_etop_poll_rx(struct napi_struct *nap - { - struct ltq_etop_chan *ch = container_of(napi, - struct ltq_etop_chan, napi); -+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - int work_done = 0; -+ unsigned long flags; - - while (work_done < budget) { - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -@@ -160,7 +230,9 @@ ltq_etop_poll_rx(struct napi_struct *nap - } - if (work_done < budget) { - napi_complete_done(&ch->napi, work_done); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - } - return work_done; - } -@@ -172,12 +244,14 @@ ltq_etop_poll_tx(struct napi_struct *nap - container_of(napi, struct ltq_etop_chan, napi); - struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - struct netdev_queue *txq = -- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); -+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - while ((ch->dma.desc_base[ch->tx_free].ctl & - (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+ ch->netdev->stats.tx_packets++; -+ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; - dev_kfree_skb_any(ch->skb[ch->tx_free]); - ch->skb[ch->tx_free] = NULL; - memset(&ch->dma.desc_base[ch->tx_free], 0, -@@ -190,7 +264,9 @@ ltq_etop_poll_tx(struct napi_struct *nap - if (netif_tx_queue_stopped(txq)) - netif_tx_start_queue(txq); - napi_complete(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - return 1; - } - -@@ -198,9 +274,10 @@ static irqreturn_t - ltq_etop_dma_irq(int irq, void *_priv) - { - struct ltq_etop_priv *priv = _priv; -- int ch = irq - LTQ_DMA_CH0_INT; -- -- napi_schedule(&priv->ch[ch].napi); -+ if (irq == priv->txch.dma.irq) -+ napi_schedule(&priv->txch.napi); -+ else -+ napi_schedule(&priv->rxch.napi); - return IRQ_HANDLED; - } - -@@ -212,7 +289,7 @@ ltq_etop_free_channel(struct net_device - ltq_dma_free(&ch->dma); - if (ch->dma.irq) - free_irq(ch->dma.irq, priv); -- if (IS_RX(ch->idx)) { -+ if (ch == &priv->txch) { - int desc; - for (desc = 0; desc < LTQ_DESC_NUM; desc++) - dev_kfree_skb_any(ch->skb[ch->dma.desc]); -@@ -223,66 +300,135 @@ static void - ltq_etop_hw_exit(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; - -- ltq_pmu_disable(PMU_PPE); -- for (i = 0; i < MAX_DMA_CHAN; i++) -- if (IS_TX(i) || IS_RX(i)) -- ltq_etop_free_channel(dev, &priv->ch[i]); -+ clk_disable(priv->clk_ppe); -+ -+ if (of_machine_is_compatible("lantiq,ar9")) -+ clk_disable(priv->clk_switch); -+ -+ if (of_machine_is_compatible("lantiq,ase")) { -+ clk_disable(priv->clk_ephy); -+ clk_disable(priv->clk_ephycgu); -+ } -+ -+ ltq_etop_free_channel(dev, &priv->txch); -+ ltq_etop_free_channel(dev, &priv->rxch); -+} -+ -+static void -+ltq_etop_gbit_init(struct net_device *dev) -+{ -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ -+ clk_enable(priv->clk_switch); -+ -+ /* enable gbit port0 on the SoC */ -+ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); -+ -+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); -+ /* disable MDIO auto polling mode */ -+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); -+ /* set 1522 packet size */ -+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); -+ /* disable pmac & dmac headers */ -+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, -+ LTQ_GBIT_PMAC_HD_CTL); -+ /* Due to traffic halt when burst length 8, -+ replace default IPG value with 0x3B */ -+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); -+ /* set mdc clock to 2.5 MHz */ -+ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, -+ LTQ_GBIT_RGMII_CTL); - } - - static int - ltq_etop_hw_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ phy_interface_t mii_mode = priv->mii_mode; - -- ltq_pmu_enable(PMU_PPE); -+ clk_enable(priv->clk_ppe); - -- switch (priv->pldata->mii_mode) { -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ ltq_etop_gbit_init(dev); -+ /* force the etops link to the gbit to MII */ -+ mii_mode = PHY_INTERFACE_MODE_MII; -+ } -+ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); -+ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | -+ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); -+ -+ switch (mii_mode) { - case PHY_INTERFACE_MODE_RMII: -- ltq_etop_w32_mask(ETOP_MII_MASK, -- ETOP_MII_REVERSE, LTQ_ETOP_CFG); -+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | -+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); - break; - - case PHY_INTERFACE_MODE_MII: -- ltq_etop_w32_mask(ETOP_MII_MASK, -- ETOP_MII_NORMAL, LTQ_ETOP_CFG); -+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | -+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); - break; - - default: -+ if (of_machine_is_compatible("lantiq,ase")) { -+ clk_enable(priv->clk_ephy); -+ /* disable external MII */ -+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); -+ /* enable clock for internal PHY */ -+ clk_enable(priv->clk_ephycgu); -+ /* we need to write this magic to the internal phy to -+ make it work */ -+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); -+ pr_info("Selected EPHY mode\n"); -+ break; -+ } - netdev_err(dev, "unknown mii mode %d\n", -- priv->pldata->mii_mode); -+ mii_mode); - return -ENOTSUPP; - } - -- /* enable crc generation */ -- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); -+ return 0; -+} -+ -+static int -+ltq_etop_dma_init(struct net_device *dev) -+{ -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ int tx = priv->tx_irq - LTQ_DMA_ETOP; -+ int rx = priv->rx_irq - LTQ_DMA_ETOP; -+ int err; - - ltq_dma_init_port(DMA_PORT_ETOP); - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- int irq = LTQ_DMA_CH0_INT + i; -- struct ltq_etop_chan *ch = &priv->ch[i]; -- -- ch->idx = ch->dma.nr = i; -- ch->dma.dev = &priv->pdev->dev; -- -- if (IS_TX(i)) { -- ltq_dma_alloc_tx(&ch->dma); -- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); -- } else if (IS_RX(i)) { -- ltq_dma_alloc_rx(&ch->dma); -- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; -- ch->dma.desc++) -- if (ltq_etop_alloc_skb(ch)) -- return -ENOMEM; -- ch->dma.desc = 0; -- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); -+ priv->txch.dma.nr = tx; -+ priv->txch.dma.dev = &priv->pdev->dev; -+ ltq_dma_alloc_tx(&priv->txch.dma); -+ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); -+ if (err) { -+ netdev_err(dev, "failed to allocate tx irq\n"); -+ goto err_out; -+ } -+ priv->txch.dma.irq = priv->tx_irq; -+ -+ priv->rxch.dma.nr = rx; -+ priv->rxch.dma.dev = &priv->pdev->dev; -+ ltq_dma_alloc_rx(&priv->rxch.dma); -+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; -+ priv->rxch.dma.desc++) { -+ if (ltq_etop_alloc_skb(&priv->rxch)) { -+ netdev_err(dev, "failed to allocate skbs\n"); -+ err = -ENOMEM; -+ goto err_out; - } -- ch->dma.irq = irq; - } -- return 0; -+ priv->rxch.dma.desc = 0; -+ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); -+ if (err) -+ netdev_err(dev, "failed to allocate rx irq\n"); -+ else -+ priv->rxch.dma.irq = priv->rx_irq; -+err_out: -+ return err; - } - - static void -@@ -301,6 +447,39 @@ static const struct ethtool_ops ltq_etop - }; - - static int -+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | -+ (phy_data << MDIO_XR9_WR_OFFSET) | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ return 0; -+} -+ -+static int -+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; -+ return val; -+} -+ -+static int - ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) - { - u32 val = MDIO_REQUEST | -@@ -308,9 +487,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in - ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | - phy_data; - -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- ltq_etop_w32(val, LTQ_ETOP_MDIO); -+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); - return 0; - } - -@@ -321,12 +500,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in - ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | - ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); - -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- ltq_etop_w32(val, LTQ_ETOP_MDIO); -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; -+ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; - return val; - } - -@@ -342,7 +521,10 @@ ltq_etop_mdio_probe(struct net_device *d - struct ltq_etop_priv *priv = netdev_priv(dev); - struct phy_device *phydev; - -- phydev = phy_find_first(priv->mii_bus); -+ if (of_machine_is_compatible("lantiq,ase")) -+ phydev = mdiobus_get_phy(priv->mii_bus, 8); -+ else -+ phydev = mdiobus_get_phy(priv->mii_bus, 0); - - if (!phydev) { - netdev_err(dev, "no PHY found\n"); -@@ -350,14 +532,17 @@ ltq_etop_mdio_probe(struct net_device *d - } - - phydev = phy_connect(dev, phydev_name(phydev), -- <q_etop_mdio_link, priv->pldata->mii_mode); -+ <q_etop_mdio_link, priv->mii_mode); - - if (IS_ERR(phydev)) { - netdev_err(dev, "Could not attach to PHY\n"); - return PTR_ERR(phydev); - } - -- phy_set_max_speed(phydev, SPEED_100); -+ if (of_machine_is_compatible("lantiq,ar9")) -+ phy_set_max_speed(phydev, SPEED_1000); -+ else -+ phy_set_max_speed(phydev, SPEED_100); - - phy_attached_info(phydev); - -@@ -378,8 +563,13 @@ ltq_etop_mdio_init(struct net_device *de - } - - priv->mii_bus->priv = dev; -- priv->mii_bus->read = ltq_etop_mdio_rd; -- priv->mii_bus->write = ltq_etop_mdio_wr; -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; -+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; -+ } else { -+ priv->mii_bus->read = ltq_etop_mdio_rd; -+ priv->mii_bus->write = ltq_etop_mdio_wr; -+ } - priv->mii_bus->name = "ltq_mii"; - snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", - priv->pdev->name, priv->pdev->id); -@@ -416,18 +606,21 @@ static int - ltq_etop_open(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -+ napi_enable(&priv->txch.napi); -+ napi_enable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_open(&priv->txch.dma); -+ ltq_dma_enable_irq(&priv->txch.dma); -+ ltq_dma_open(&priv->rxch.dma); -+ ltq_dma_enable_irq(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ if (dev->phydev) -+ phy_start(dev->phydev); - -- if (!IS_TX(i) && (!IS_RX(i))) -- continue; -- ltq_dma_open(&ch->dma); -- ltq_dma_enable_irq(&ch->dma); -- napi_enable(&ch->napi); -- } -- phy_start(dev->phydev); - netif_tx_start_all_queues(dev); - return 0; - } -@@ -436,18 +629,19 @@ static int - ltq_etop_stop(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - - netif_tx_stop_all_queues(dev); -- phy_stop(dev->phydev); -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -- -- if (!IS_RX(i) && !IS_TX(i)) -- continue; -- napi_disable(&ch->napi); -- ltq_dma_close(&ch->dma); -- } -+ if (dev->phydev) -+ phy_stop(dev->phydev); -+ napi_disable(&priv->txch.napi); -+ napi_disable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_close(&priv->txch.dma); -+ ltq_dma_close(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ - return 0; - } - -@@ -457,15 +651,16 @@ ltq_etop_tx(struct sk_buff *skb, struct - int queue = skb_get_queue_mapping(skb); - struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); - struct ltq_etop_priv *priv = netdev_priv(dev); -- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; -- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -- int len; -+ struct ltq_dma_desc *desc = -+ &priv->txch.dma.desc_base[priv->txch.dma.desc]; - unsigned long flags; - u32 byte_offset; -+ int len; - - len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; - -- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || -+ priv->txch.skb[priv->txch.dma.desc]) { - netdev_err(dev, "tx ring full\n"); - netif_tx_stop_queue(txq); - return NETDEV_TX_BUSY; -@@ -473,7 +668,7 @@ ltq_etop_tx(struct sk_buff *skb, struct - - /* dma needs to start on a 16 byte aligned address */ - byte_offset = CPHYSADDR(skb->data) % 16; -- ch->skb[ch->dma.desc] = skb; -+ priv->txch.skb[priv->txch.dma.desc] = skb; - - netif_trans_update(dev); - -@@ -483,11 +678,11 @@ ltq_etop_tx(struct sk_buff *skb, struct - wmb(); - desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | - LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); -- ch->dma.desc++; -- ch->dma.desc %= LTQ_DESC_NUM; -+ priv->txch.dma.desc++; -+ priv->txch.dma.desc %= LTQ_DESC_NUM; - spin_unlock_irqrestore(&priv->lock, flags); - -- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) -+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) - netif_tx_stop_queue(txq); - - return NETDEV_TX_OK; -@@ -498,11 +693,14 @@ ltq_etop_change_mtu(struct net_device *d - { - struct ltq_etop_priv *priv = netdev_priv(dev); - unsigned long flags; -+ int max; - - dev->mtu = new_mtu; - -+ max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; -+ - spin_lock_irqsave(&priv->lock, flags); -- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); -+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN); - spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -@@ -555,6 +753,9 @@ ltq_etop_init(struct net_device *dev) - if (err) - goto err_hw; - ltq_etop_change_mtu(dev, 1500); -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; - - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); - if (!is_valid_ether_addr(mac.sa_data)) { -@@ -572,9 +773,10 @@ ltq_etop_init(struct net_device *dev) - dev->addr_assign_type = NET_ADDR_RANDOM; - - ltq_etop_set_multicast_list(dev); -- err = ltq_etop_mdio_init(dev); -- if (err) -- goto err_netdev; -+ if (!ltq_etop_mdio_init(dev)) -+ dev->ethtool_ops = <q_etop_ethtool_ops; -+ else -+ pr_warn("etop: mdio probe failed\n");; - return 0; - - err_netdev: -@@ -594,6 +796,9 @@ ltq_etop_tx_timeout(struct net_device *d - err = ltq_etop_hw_init(dev); - if (err) - goto err_hw; -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; - netif_trans_update(dev); - netif_wake_queue(dev); - return; -@@ -617,14 +822,18 @@ static const struct net_device_ops ltq_e - .ndo_tx_timeout = ltq_etop_tx_timeout, - }; - --static int __init --ltq_etop_probe(struct platform_device *pdev) -+static int ltq_etop_probe(struct platform_device *pdev) - { - struct net_device *dev; - struct ltq_etop_priv *priv; -- struct resource *res; -+ struct resource *res, *gbit_res, irqres[2]; - int err; -- int i; -+ -+ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); -+ if (err != 2) { -+ dev_err(&pdev->dev, "failed to get etop irqs\n"); -+ return -EINVAL; -+ } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { -@@ -650,31 +859,62 @@ ltq_etop_probe(struct platform_device *p - goto err_out; - } - -- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); -- if (!dev) { -- err = -ENOMEM; -- goto err_out; -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ if (!gbit_res) { -+ dev_err(&pdev->dev, "failed to get gbit resource\n"); -+ err = -ENOENT; -+ goto err_out; -+ } -+ ltq_gbit_membase = devm_ioremap(&pdev->dev, -+ gbit_res->start, resource_size(gbit_res)); -+ if (!ltq_gbit_membase) { -+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", -+ pdev->id); -+ err = -ENOMEM; -+ goto err_out; -+ } - } -+ -+ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); - strcpy(dev->name, "eth%d"); - dev->netdev_ops = <q_eth_netdev_ops; -- dev->ethtool_ops = <q_etop_ethtool_ops; - priv = netdev_priv(dev); - priv->res = res; - priv->pdev = pdev; -- priv->pldata = dev_get_platdata(&pdev->dev); - priv->netdev = dev; -+ priv->tx_irq = irqres[0].start; -+ priv->rx_irq = irqres[1].start; -+ err = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode); -+ if (err) -+ pr_err("Can't find phy-mode for port\n"); -+ -+ of_get_mac_address(pdev->dev.of_node, priv->mac); -+ -+ priv->clk_ppe = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_ppe)) -+ return PTR_ERR(priv->clk_ppe); -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ priv->clk_switch = clk_get(&pdev->dev, "switch"); -+ if (IS_ERR(priv->clk_switch)) -+ return PTR_ERR(priv->clk_switch); -+ } -+ if (of_machine_is_compatible("lantiq,ase")) { -+ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); -+ if (IS_ERR(priv->clk_ephy)) -+ return PTR_ERR(priv->clk_ephy); -+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); -+ if (IS_ERR(priv->clk_ephycgu)) -+ return PTR_ERR(priv->clk_ephycgu); -+ } -+ - spin_lock_init(&priv->lock); - SET_NETDEV_DEV(dev, &pdev->dev); - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- if (IS_TX(i)) -- netif_napi_add(dev, &priv->ch[i].napi, -- ltq_etop_poll_tx, 8); -- else if (IS_RX(i)) -- netif_napi_add(dev, &priv->ch[i].napi, -- ltq_etop_poll_rx, 32); -- priv->ch[i].netdev = dev; -- } -+ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); -+ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); -+ priv->txch.netdev = dev; -+ priv->rxch.netdev = dev; - - err = register_netdev(dev); - if (err) -@@ -703,31 +943,22 @@ ltq_etop_remove(struct platform_device * - return 0; - } - -+static const struct of_device_id ltq_etop_match[] = { -+ { .compatible = "lantiq,etop-xway" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ltq_etop_match); -+ - static struct platform_driver ltq_mii_driver = { -+ .probe = ltq_etop_probe, - .remove = ltq_etop_remove, - .driver = { - .name = "ltq_etop", -+ .of_match_table = ltq_etop_match, - }, - }; - --int __init --init_ltq_etop(void) --{ -- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); -- -- if (ret) -- pr_err("ltq_etop: Error registering platform driver!"); -- return ret; --} -- --static void __exit --exit_ltq_etop(void) --{ -- platform_driver_unregister(<q_mii_driver); --} -- --module_init(init_ltq_etop); --module_exit(exit_ltq_etop); -+module_platform_driver(ltq_mii_driver); - - MODULE_AUTHOR("John Crispin "); - MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-5.10/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-5.10/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch deleted file mode 100644 index 154cf226c1..0000000000 --- a/target/linux/lantiq/patches-5.10/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch +++ /dev/null @@ -1,1034 +0,0 @@ -From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:26:42 +0200 -Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master - -This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - drivers/i2c/busses/Kconfig | 10 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ - drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ - 4 files changed, 992 insertions(+) - create mode 100644 drivers/i2c/busses/i2c-lantiq.c - create mode 100644 drivers/i2c/busses/i2c-lantiq.h - ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -753,6 +753,16 @@ config I2C_MESON - If you say yes to this option, support will be included for the - I2C interface on the Amlogic Meson family of SoCs. - -+config I2C_LANTIQ -+ tristate "Lantiq I2C interface" -+ depends on LANTIQ && SOC_FALCON -+ help -+ If you say yes to this option, support will be included for the -+ Lantiq I2C core. -+ -+ This driver can also be built as a module. If so, the module -+ will be called i2c-lantiq. -+ - config I2C_MPC - tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" - depends on PPC ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -72,6 +72,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-l - obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o - obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o - obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o -+obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o - obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o - obj-$(CONFIG_I2C_MESON) += i2c-meson.o - obj-$(CONFIG_I2C_MPC) += i2c-mpc.o ---- /dev/null -+++ b/drivers/i2c/busses/i2c-lantiq.c -@@ -0,0 +1,747 @@ -+ -+/* -+ * Lantiq I2C bus adapter -+ * -+ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * Copyright (C) 2012 Thomas Langer -+ */ -+ -+#include -+#include -+#include -+#include /* for kzalloc, kfree */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "i2c-lantiq.h" -+ -+/* -+ * CURRENT ISSUES: -+ * - no high speed support -+ * - ten bit mode is not tested (no slave devices) -+ */ -+ -+/* access macros */ -+#define i2c_r32(reg) \ -+ __raw_readl(&(priv->membase)->reg) -+#define i2c_w32(val, reg) \ -+ __raw_writel(val, &(priv->membase)->reg) -+#define i2c_w32_mask(clear, set, reg) \ -+ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) -+ -+#define DRV_NAME "i2c-lantiq" -+#define DRV_VERSION "1.00" -+ -+#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ -+ -+#ifdef DEBUG -+#define LTQ_I2C_XFER_TIMEOUT (25*HZ) -+#else -+#define LTQ_I2C_XFER_TIMEOUT HZ -+#endif -+ -+#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ -+ I2C_IMSC_I2C_ERR_INT_EN) -+ -+#define LTQ_I2C_ARB_LOST (1 << 0) -+#define LTQ_I2C_NACK (1 << 1) -+#define LTQ_I2C_RX_UFL (1 << 2) -+#define LTQ_I2C_RX_OFL (1 << 3) -+#define LTQ_I2C_TX_UFL (1 << 4) -+#define LTQ_I2C_TX_OFL (1 << 5) -+ -+struct ltq_i2c { -+ struct mutex mutex; -+ -+ -+ /* active clock settings */ -+ unsigned int input_clock; /* clock input for i2c hardware block */ -+ unsigned int i2c_clock; /* approximated bus clock in kHz */ -+ -+ struct clk *clk_gate; -+ struct clk *clk_input; -+ -+ -+ /* resources (memory and interrupts) */ -+ int irq_lb; /* last burst irq */ -+ -+ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ -+ -+ struct i2c_adapter adap; -+ struct device *dev; -+ -+ struct completion cmd_complete; -+ -+ -+ /* message transfer data */ -+ struct i2c_msg *current_msg; /* current message */ -+ int msgs_num; /* number of messages to handle */ -+ u8 *msg_buf; /* current buffer */ -+ u32 msg_buf_len; /* remaining length of current buffer */ -+ int msg_err; /* error status of the current transfer */ -+ -+ -+ /* master status codes */ -+ enum { -+ STATUS_IDLE, -+ STATUS_ADDR, /* address phase */ -+ STATUS_WRITE, -+ STATUS_READ, -+ STATUS_READ_END, -+ STATUS_STOP -+ } status; -+}; -+ -+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); -+ -+static inline void enable_burst_irq(struct ltq_i2c *priv) -+{ -+ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); -+} -+static inline void disable_burst_irq(struct ltq_i2c *priv) -+{ -+ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); -+} -+ -+static void prepare_msg_send_addr(struct ltq_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ -+ u16 addr = msg->addr; -+ -+ /* new i2c_msg */ -+ priv->msg_buf = msg->buf; -+ priv->msg_buf_len = msg->len; -+ if (rd) -+ priv->status = STATUS_READ; -+ else -+ priv->status = STATUS_WRITE; -+ -+ /* send slave address */ -+ if (msg->flags & I2C_M_TEN) { -+ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); -+ i2c_w32(addr & 0xff, txd); -+ } else { -+ i2c_w32((addr & 0x7f) << 1 | rd, txd); -+ } -+} -+ -+static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; -+ -+ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); -+ -+ priv->status = STATUS_ADDR; -+ -+ if (!(msg->flags & I2C_M_RD)) -+ len += msg->len; -+ else -+ /* set maximum received packet size (before rx int!) */ -+ i2c_w32(msg->len, mrps_ctrl); -+ i2c_w32(len, tps_ctrl); -+ enable_burst_irq(priv); -+} -+ -+static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) -+{ -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ unsigned int input_clock = clk_get_rate(priv->clk_input); -+ u32 dec, inc = 1; -+ -+ /* clock changed? */ -+ if (priv->input_clock == input_clock) -+ return 0; -+ -+ /* -+ * this formula is only an approximation, found by the recommended -+ * values in the "I2C Architecture Specification 1.7.1" -+ */ -+ dec = input_clock / (priv->i2c_clock * 2); -+ if (dec <= 6) -+ return -ENXIO; -+ -+ i2c_w32(0, fdiv_high_cfg); -+ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | -+ (dec << I2C_FDIV_CFG_DEC_OFFSET), -+ fdiv_cfg); -+ -+ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", -+ input_clock, priv->i2c_clock, dec); -+ -+ priv->input_clock = input_clock; -+ return 0; -+} -+ -+static int ltq_i2c_hw_init(struct i2c_adapter *adap) -+{ -+ int ret = 0; -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+#ifndef DEBUG -+ /* set normal operation clock divider */ -+ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); -+#else -+ /* for debugging a higher divider value! */ -+ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); -+#endif -+ -+ /* setup clock */ -+ ret = ltq_i2c_hw_set_clock(adap); -+ if (ret != 0) { -+ dev_warn(priv->dev, "invalid clock settings\n"); -+ return ret; -+ } -+ -+ /* configure fifo */ -+ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ -+ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ -+ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ -+ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ -+ fifo_cfg); -+ -+ /* configure address */ -+ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in -+ the fifo */ -+ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ -+ I2C_ADDR_CFG_MnS_EN | /* we are master device */ -+ 0, /* our slave address (not used!) */ -+ addr_cfg); -+ -+ /* enable bus */ -+ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); -+ -+ return 0; -+} -+ -+static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) -+{ -+ unsigned long timeout; -+ -+ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); -+ -+ do { -+ u32 stat = i2c_r32(bus_stat); -+ -+ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) -+ return 0; -+ -+ cond_resched(); -+ } while (!time_after_eq(jiffies, timeout)); -+ -+ dev_err(priv->dev, "timeout waiting for bus ready\n"); -+ return -ETIMEDOUT; -+} -+ -+static void ltq_i2c_tx(struct ltq_i2c *priv, int last) -+{ -+ if (priv->msg_buf_len && priv->msg_buf) { -+ i2c_w32(*priv->msg_buf, txd); -+ -+ if (--priv->msg_buf_len) -+ priv->msg_buf++; -+ else -+ priv->msg_buf = NULL; -+ } else { -+ last = 1; -+ } -+ -+ if (last) -+ disable_burst_irq(priv); -+} -+ -+static void ltq_i2c_rx(struct ltq_i2c *priv, int last) -+{ -+ u32 fifo_stat, timeout; -+ if (priv->msg_buf_len && priv->msg_buf) { -+ timeout = 5000000; -+ do { -+ fifo_stat = i2c_r32(ffs_stat); -+ } while (!fifo_stat && --timeout); -+ if (!timeout) { -+ last = 1; -+ pr_debug("\nrx timeout\n"); -+ goto err; -+ } -+ while (fifo_stat) { -+ *priv->msg_buf = i2c_r32(rxd); -+ if (--priv->msg_buf_len) { -+ priv->msg_buf++; -+ } else { -+ priv->msg_buf = NULL; -+ last = 1; -+ break; -+ } -+ /* -+ * do not read more than burst size, otherwise no "last -+ * burst" is generated and the transaction is blocked! -+ */ -+ fifo_stat = 0; -+ } -+ } else { -+ last = 1; -+ } -+err: -+ if (last) { -+ disable_burst_irq(priv); -+ -+ if (priv->status == STATUS_READ_END) { -+ /* -+ * do the STATUS_STOP and complete() here, as sometimes -+ * the tx_end is already seen before this is finished -+ */ -+ priv->status = STATUS_STOP; -+ complete(&priv->cmd_complete); -+ } else { -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+ priv->status = STATUS_READ_END; -+ } -+ } -+} -+ -+static void ltq_i2c_xfer_init(struct ltq_i2c *priv) -+{ -+ /* enable interrupts */ -+ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); -+ -+ /* trigger transfer of first msg */ -+ ltq_i2c_set_tx_len(priv); -+} -+ -+static void dump_msgs(struct i2c_msg msgs[], int num, int rx) -+{ -+#if defined(DEBUG) -+ int i, j; -+ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); -+ for (i = 0; i < num; i++) { -+ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, -+ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', -+ msgs[i].len, msgs[i].addr); -+ if (!(msgs[i].flags & I2C_M_RD) || rx) { -+ for (j = 0; j < msgs[i].len; j++) -+ pr_debug("%02X ", msgs[i].buf[j]); -+ } -+ pr_debug("\n"); -+ } -+#endif -+} -+ -+static void ltq_i2c_release_bus(struct ltq_i2c *priv) -+{ -+ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+} -+ -+static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], -+ int num) -+{ -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ int ret; -+ -+ dev_dbg(priv->dev, "xfer %u messages\n", num); -+ dump_msgs(msgs, num, 0); -+ -+ mutex_lock(&priv->mutex); -+ -+ init_completion(&priv->cmd_complete); -+ priv->current_msg = msgs; -+ priv->msgs_num = num; -+ priv->msg_err = 0; -+ priv->status = STATUS_IDLE; -+ -+ /* wait for the bus to become ready */ -+ ret = ltq_i2c_wait_bus_not_busy(priv); -+ if (ret) -+ goto done; -+ -+ while (priv->msgs_num) { -+ /* start the transfers */ -+ ltq_i2c_xfer_init(priv); -+ -+ /* wait for transfers to complete */ -+ ret = wait_for_completion_interruptible_timeout( -+ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); -+ if (ret == 0) { -+ dev_err(priv->dev, "controller timed out\n"); -+ ltq_i2c_hw_init(adap); -+ ret = -ETIMEDOUT; -+ goto done; -+ } else if (ret < 0) -+ goto done; -+ -+ if (priv->msg_err) { -+ if (priv->msg_err & LTQ_I2C_NACK) -+ ret = -ENXIO; -+ else -+ ret = -EREMOTEIO; -+ goto done; -+ } -+ if (--priv->msgs_num) -+ priv->current_msg++; -+ } -+ /* no error? */ -+ ret = num; -+ -+done: -+ ltq_i2c_release_bus(priv); -+ -+ mutex_unlock(&priv->mutex); -+ -+ if (ret >= 0) -+ dump_msgs(msgs, num, 1); -+ -+ pr_debug("XFER ret %d\n", ret); -+ return ret; -+} -+ -+static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) -+{ -+ struct ltq_i2c *priv = dev_id; -+ struct i2c_msg *msg = priv->current_msg; -+ int last = (irq == priv->irq_lb); -+ -+ if (last) -+ pr_debug("LB "); -+ else -+ pr_debug("B "); -+ -+ if (msg->flags & I2C_M_RD) { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ pr_debug("X"); -+ prepare_msg_send_addr(priv); -+ disable_burst_irq(priv); -+ break; -+ case STATUS_READ: -+ case STATUS_READ_END: -+ pr_debug("R"); -+ ltq_i2c_rx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ pr_warn("Status R %d\n", priv->status); -+ break; -+ } -+ } else { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ pr_debug("x"); -+ prepare_msg_send_addr(priv); -+ break; -+ case STATUS_WRITE: -+ pr_debug("w"); -+ ltq_i2c_tx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ pr_warn("Status W %d\n", priv->status); -+ break; -+ } -+ } -+ -+ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); -+ return IRQ_HANDLED; -+} -+ -+static void ltq_i2c_isr_prot(struct ltq_i2c *priv) -+{ -+ u32 i_pro = i2c_r32(p_irqss); -+ -+ pr_debug("i2c-p"); -+ -+ /* not acknowledge */ -+ if (i_pro & I2C_P_IRQSS_NACK) { -+ priv->msg_err |= LTQ_I2C_NACK; -+ pr_debug(" nack"); -+ } -+ -+ /* arbitration lost */ -+ if (i_pro & I2C_P_IRQSS_AL) { -+ priv->msg_err |= LTQ_I2C_ARB_LOST; -+ pr_debug(" arb-lost"); -+ } -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) -+ pr_debug(" rx"); -+ -+ /* tx end */ -+ if (i_pro & I2C_P_IRQSS_TX_END) -+ pr_debug(" txend"); -+ pr_debug("\n"); -+ -+ if (!priv->msg_err) { -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) { -+ priv->status = STATUS_READ; -+ enable_burst_irq(priv); -+ } -+ if (i_pro & I2C_P_IRQSS_TX_END) { -+ if (priv->status == STATUS_READ) -+ priv->status = STATUS_READ_END; -+ else { -+ disable_burst_irq(priv); -+ priv->status = STATUS_STOP; -+ } -+ } -+ } -+ -+ i2c_w32(i_pro, p_irqsc); -+} -+ -+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) -+{ -+ u32 i_raw, i_err = 0; -+ struct ltq_i2c *priv = dev_id; -+ -+ i_raw = i2c_r32(mis); -+ pr_debug("i_raw 0x%08X\n", i_raw); -+ -+ /* error interrupt */ -+ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { -+ i_err = i2c_r32(err_irqss); -+ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", -+ i_err, i2c_r32(bus_stat)); -+ -+ /* tx fifo overflow (8) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_OFL) -+ priv->msg_err |= LTQ_I2C_TX_OFL; -+ -+ /* tx fifo underflow (4) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_UFL) -+ priv->msg_err |= LTQ_I2C_TX_UFL; -+ -+ /* rx fifo overflow (2) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_OFL) -+ priv->msg_err |= LTQ_I2C_RX_OFL; -+ -+ /* rx fifo underflow (1) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_UFL) -+ priv->msg_err |= LTQ_I2C_RX_UFL; -+ -+ i2c_w32(i_err, err_irqsc); -+ } -+ -+ /* protocol interrupt */ -+ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) -+ ltq_i2c_isr_prot(priv); -+ -+ if ((priv->msg_err) || (priv->status == STATUS_STOP)) -+ complete(&priv->cmd_complete); -+ -+ return IRQ_HANDLED; -+} -+ -+static u32 ltq_i2c_functionality(struct i2c_adapter *adap) -+{ -+ return I2C_FUNC_I2C | -+ I2C_FUNC_10BIT_ADDR | -+ I2C_FUNC_SMBUS_EMUL; -+} -+ -+static struct i2c_algorithm ltq_i2c_algorithm = { -+ .master_xfer = ltq_i2c_xfer, -+ .functionality = ltq_i2c_functionality, -+}; -+ -+static int ltq_i2c_probe(struct platform_device *pdev) -+{ -+ struct device_node *node = pdev->dev.of_node; -+ struct ltq_i2c *priv; -+ struct i2c_adapter *adap; -+ struct resource *mmres, irqres[4]; -+ int ret = 0; -+ -+ dev_dbg(&pdev->dev, "probing\n"); -+ -+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ ret = of_irq_to_resource_table(node, irqres, 4); -+ if (!mmres || (ret != 4)) { -+ dev_err(&pdev->dev, "no resources\n"); -+ return -ENODEV; -+ } -+ -+ /* allocate private data */ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) { -+ dev_err(&pdev->dev, "can't allocate private data\n"); -+ return -ENOMEM; -+ } -+ -+ adap = &priv->adap; -+ i2c_set_adapdata(adap, priv); -+ adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; -+ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); -+ adap->algo = <q_i2c_algorithm; -+ adap->dev.parent = &pdev->dev; -+ adap->dev.of_node = pdev->dev.of_node; -+ -+ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { -+ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); -+ priv->i2c_clock = 100000; -+ } -+ -+ init_completion(&priv->cmd_complete); -+ mutex_init(&priv->mutex); -+ -+ priv->membase = devm_ioremap_resource(&pdev->dev, mmres); -+ if (IS_ERR(priv->membase)) -+ return PTR_ERR(priv->membase); -+ -+ priv->dev = &pdev->dev; -+ priv->irq_lb = irqres[0].start; -+ -+ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, -+ 0x0, "i2c lb", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", -+ irqres[0].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, -+ 0x0, "i2c b", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get burst IRQ %d\n", -+ irqres[1].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, -+ 0x0, "i2c err", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get error IRQ %d\n", -+ irqres[2].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, -+ 0x0, "i2c p", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", -+ irqres[3].start); -+ return -ENODEV; -+ } -+ -+ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); -+ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, -+ irqres[1].start, irqres[2].start, irqres[3].start); -+ -+ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_gate)) { -+ dev_err(&pdev->dev, "failed to get i2c clk\n"); -+ return -ENOENT; -+ } -+ -+ /* this is a static clock, which has no refcounting */ -+ priv->clk_input = clk_get_fpi(); -+ if (IS_ERR(priv->clk_input)) { -+ dev_err(&pdev->dev, "failed to get fpi clk\n"); -+ return -ENOENT; -+ } -+ -+ clk_activate(priv->clk_gate); -+ -+ /* add our adapter to the i2c stack */ -+ ret = i2c_add_numbered_adapter(adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't register I2C adapter\n"); -+ goto out; -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ i2c_set_adapdata(adap, priv); -+ -+ /* print module version information */ -+ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", -+ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, -+ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); -+ -+ /* initialize HW */ -+ ret = ltq_i2c_hw_init(adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't configure adapter\n"); -+ i2c_del_adapter(adap); -+ platform_set_drvdata(pdev, NULL); -+ goto out; -+ } else { -+ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); -+ } -+ -+out: -+ /* if init failed, we need to deactivate the clock gate */ -+ if (ret) -+ clk_deactivate(priv->clk_gate); -+ -+ return ret; -+} -+ -+static int ltq_i2c_remove(struct platform_device *pdev) -+{ -+ struct ltq_i2c *priv = platform_get_drvdata(pdev); -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+ /* power down the core */ -+ clk_deactivate(priv->clk_gate); -+ -+ /* remove driver */ -+ i2c_del_adapter(&priv->adap); -+ kfree(priv); -+ -+ dev_dbg(&pdev->dev, "removed\n"); -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+static const struct of_device_id ltq_i2c_match[] = { -+ { .compatible = "lantiq,lantiq-i2c" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ltq_i2c_match); -+ -+static struct platform_driver ltq_i2c_driver = { -+ .probe = ltq_i2c_probe, -+ .remove = ltq_i2c_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = ltq_i2c_match, -+ }, -+}; -+ -+module_platform_driver(ltq_i2c_driver); -+ -+MODULE_DESCRIPTION("Lantiq I2C bus adapter"); -+MODULE_AUTHOR("Thomas Langer "); -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION(DRV_VERSION); ---- /dev/null -+++ b/drivers/i2c/busses/i2c-lantiq.h -@@ -0,0 +1,234 @@ -+#ifndef I2C_LANTIQ_H -+#define I2C_LANTIQ_H -+ -+/* I2C register structure */ -+struct lantiq_reg_i2c { -+ /* I2C Kernel Clock Control Register */ -+ unsigned int clc; /* 0x00000000 */ -+ /* Reserved */ -+ unsigned int res_0; /* 0x00000004 */ -+ /* I2C Identification Register */ -+ unsigned int id; /* 0x00000008 */ -+ /* Reserved */ -+ unsigned int res_1; /* 0x0000000C */ -+ /* -+ * I2C RUN Control Register -+ * This register enables and disables the I2C peripheral. Before -+ * enabling, the I2C has to be configured properly. After enabling -+ * no configuration is possible -+ */ -+ unsigned int run_ctrl; /* 0x00000010 */ -+ /* -+ * I2C End Data Control Register -+ * This register is used to either turn around the data transmission -+ * direction or to address another slave without sending a stop -+ * condition. Also the software can stop the slave-transmitter by -+ * sending a not-accolade when working as master-receiver or even -+ * stop data transmission immediately when operating as -+ * master-transmitter. The writing to the bits of this control -+ * register is only effective when in MASTER RECEIVES BYTES, MASTER -+ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state -+ */ -+ unsigned int endd_ctrl; /* 0x00000014 */ -+ /* -+ * I2C Fractional Divider Configuration Register -+ * These register is used to program the fractional divider of the I2C -+ * bus. Before the peripheral is switched on by setting the RUN-bit the -+ * two (fixed) values for the two operating frequencies are programmed -+ * into these (configuration) registers. The Register FDIV_HIGH_CFG has -+ * the same layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_cfg; /* 0x00000018 */ -+ /* -+ * I2C Fractional Divider (highspeed mode) Configuration Register -+ * These register is used to program the fractional divider of the I2C -+ * bus. Before the peripheral is switched on by setting the RUN-bit the -+ * two (fixed) values for the two operating frequencies are programmed -+ * into these (configuration) registers. The Register FDIV_CFG has the -+ * same layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_high_cfg; /* 0x0000001C */ -+ /* I2C Address Configuration Register */ -+ unsigned int addr_cfg; /* 0x00000020 */ -+ /* I2C Bus Status Register -+ * This register gives a status information of the I2C. This additional -+ * information can be used by the software to start proper actions. -+ */ -+ unsigned int bus_stat; /* 0x00000024 */ -+ /* I2C FIFO Configuration Register */ -+ unsigned int fifo_cfg; /* 0x00000028 */ -+ /* I2C Maximum Received Packet Size Register */ -+ unsigned int mrps_ctrl; /* 0x0000002C */ -+ /* I2C Received Packet Size Status Register */ -+ unsigned int rps_stat; /* 0x00000030 */ -+ /* I2C Transmit Packet Size Register */ -+ unsigned int tps_ctrl; /* 0x00000034 */ -+ /* I2C Filled FIFO Stages Status Register */ -+ unsigned int ffs_stat; /* 0x00000038 */ -+ /* Reserved */ -+ unsigned int res_2; /* 0x0000003C */ -+ /* I2C Timing Configuration Register */ -+ unsigned int tim_cfg; /* 0x00000040 */ -+ /* Reserved */ -+ unsigned int res_3[7]; /* 0x00000044 */ -+ /* I2C Error Interrupt Request Source Mask Register */ -+ unsigned int err_irqsm; /* 0x00000060 */ -+ /* I2C Error Interrupt Request Source Status Register */ -+ unsigned int err_irqss; /* 0x00000064 */ -+ /* I2C Error Interrupt Request Source Clear Register */ -+ unsigned int err_irqsc; /* 0x00000068 */ -+ /* Reserved */ -+ unsigned int res_4; /* 0x0000006C */ -+ /* I2C Protocol Interrupt Request Source Mask Register */ -+ unsigned int p_irqsm; /* 0x00000070 */ -+ /* I2C Protocol Interrupt Request Source Status Register */ -+ unsigned int p_irqss; /* 0x00000074 */ -+ /* I2C Protocol Interrupt Request Source Clear Register */ -+ unsigned int p_irqsc; /* 0x00000078 */ -+ /* Reserved */ -+ unsigned int res_5; /* 0x0000007C */ -+ /* I2C Raw Interrupt Status Register */ -+ unsigned int ris; /* 0x00000080 */ -+ /* I2C Interrupt Mask Control Register */ -+ unsigned int imsc; /* 0x00000084 */ -+ /* I2C Masked Interrupt Status Register */ -+ unsigned int mis; /* 0x00000088 */ -+ /* I2C Interrupt Clear Register */ -+ unsigned int icr; /* 0x0000008C */ -+ /* I2C Interrupt Set Register */ -+ unsigned int isr; /* 0x00000090 */ -+ /* I2C DMA Enable Register */ -+ unsigned int dmae; /* 0x00000094 */ -+ /* Reserved */ -+ unsigned int res_6[8154]; /* 0x00000098 */ -+ /* I2C Transmit Data Register */ -+ unsigned int txd; /* 0x00008000 */ -+ /* Reserved */ -+ unsigned int res_7[4095]; /* 0x00008004 */ -+ /* I2C Receive Data Register */ -+ unsigned int rxd; /* 0x0000C000 */ -+ /* Reserved */ -+ unsigned int res_8[4095]; /* 0x0000C004 */ -+}; -+ -+/* -+ * Clock Divider for Normal Run Mode -+ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long -+ * as the new divider value RMC is not valid, the register returns 0x0000 00xx -+ * on reading. -+ */ -+#define I2C_CLC_RMC_MASK 0x0000FF00 -+/* field offset */ -+#define I2C_CLC_RMC_OFFSET 8 -+ -+/* Fields of "I2C Identification Register" */ -+/* Module ID */ -+#define I2C_ID_ID_MASK 0x0000FF00 -+/* field offset */ -+#define I2C_ID_ID_OFFSET 8 -+/* Revision */ -+#define I2C_ID_REV_MASK 0x000000FF -+/* field offset */ -+#define I2C_ID_REV_OFFSET 0 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/* Enable */ -+#define I2C_IMSC_BREQ_INT_EN 0x00000008 -+/* Enable */ -+#define I2C_IMSC_LBREQ_INT_EN 0x00000004 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/* field offset */ -+#define I2C_FDIV_CFG_INC_OFFSET 16 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/* Enable */ -+#define I2C_IMSC_I2C_P_INT_EN 0x00000020 -+/* Enable */ -+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 -+ -+/* Fields of "I2C Error Interrupt Request Source Status Register" */ -+/* TXF_OFL */ -+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 -+/* TXF_UFL */ -+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 -+/* RXF_OFL */ -+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 -+/* RXF_UFL */ -+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 -+ -+/* Fields of "I2C Raw Interrupt Status Register" */ -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/* TX FIFO Flow Control */ -+#define I2C_FIFO_CFG_TXFC 0x00020000 -+/* RX FIFO Flow Control */ -+#define I2C_FIFO_CFG_RXFC 0x00010000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 -+/* 1 word */ -+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/* 1 word */ -+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 -+/* Stop on Packet End Enable */ -+#define I2C_ADDR_CFG_SOPE_EN 0x00200000 -+/* Stop on Not Acknowledge Enable */ -+#define I2C_ADDR_CFG_SONA_EN 0x00100000 -+/* Enable */ -+#define I2C_ADDR_CFG_MnS_EN 0x00080000 -+ -+/* Fields of "I2C Interrupt Clear Register" */ -+/* Clear */ -+#define I2C_ICR_BREQ_INT_CLR 0x00000008 -+/* Clear */ -+#define I2C_ICR_LBREQ_INT_CLR 0x00000004 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/* field offset */ -+#define I2C_FDIV_CFG_DEC_OFFSET 0 -+ -+/* Fields of "I2C Bus Status Register" */ -+/* Bus Status */ -+#define I2C_BUS_STAT_BS_MASK 0x00000003 -+/* Read from I2C Bus. */ -+#define I2C_BUS_STAT_RNW_READ 0x00000004 -+/* I2C Bus is free. */ -+#define I2C_BUS_STAT_BS_FREE 0x00000000 -+/* -+ * The device is working as master and has claimed the control on the -+ * I2C-bus (busy master). -+ */ -+#define I2C_BUS_STAT_BS_BM 0x00000002 -+ -+/* Fields of "I2C RUN Control Register" */ -+/* Enable */ -+#define I2C_RUN_CTRL_RUN_EN 0x00000001 -+ -+/* Fields of "I2C End Data Control Register" */ -+/* -+ * Set End of Transmission -+ * Note:Do not write '1' to this bit when bus is free. This will cause an -+ * abort after the first byte when a new transfer is started. -+ */ -+#define I2C_ENDD_CTRL_SETEND 0x00000002 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ -+/* NACK */ -+#define I2C_P_IRQSS_NACK 0x00000010 -+/* AL */ -+#define I2C_P_IRQSS_AL 0x00000008 -+/* RX */ -+#define I2C_P_IRQSS_RX 0x00000040 -+/* TX_END */ -+#define I2C_P_IRQSS_TX_END 0x00000020 -+ -+ -+#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-5.10/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-5.10/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch deleted file mode 100644 index c80045e878..0000000000 --- a/target/linux/lantiq/patches-5.10/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch +++ /dev/null @@ -1,218 +0,0 @@ -From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 10 Sep 2014 22:42:14 +0200 -Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling - -Signed-off-by: John Crispin ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + - arch/mips/lantiq/xway/Makefile | 3 + - arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++ - arch/mips/lantiq/xway/eth_mac.c | 25 ++++ - drivers/net/ethernet/lantiq_etop.c | 6 +- - 5 files changed, 172 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c - create mode 100644 arch/mips/lantiq/xway/eth_mac.c - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -102,5 +102,8 @@ int xrx200_gphy_boot(struct device *dev, - extern void ltq_pmu_enable(unsigned int module); - extern void ltq_pmu_disable(unsigned int module); - -+/* allow the ethernet driver to load a flash mapped mac addr */ -+const u8* ltq_get_eth_mac(void); -+ - #endif /* CONFIG_SOC_TYPE_XWAY */ - #endif /* _LTQ_XWAY_H__ */ ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -8,3 +8,6 @@ obj-y += timer.o - endif - - obj-y += vmmc.o -+ -+obj-y += eth_mac.o -+obj-$(CONFIG_PCI) += ath5k_eep.o ---- /dev/null -+++ b/arch/mips/lantiq/xway/ath5k_eep.c -@@ -0,0 +1,136 @@ -+/* -+ * Copyright (C) 2011 Luca Olivetti -+ * Copyright (C) 2011 John Crispin -+ * Copyright (C) 2011 Andrej VlaÅ¡ić -+ * Copyright (C) 2013 Álvaro Fernández Rojas -+ * Copyright (C) 2013 Daniel Gimpelevich -+ * Copyright (C) 2015 Vittorio Gambaletta -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); -+struct ath5k_platform_data ath5k_pdata; -+static u8 athxk_eeprom_mac[6]; -+ -+static int ath5k_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ dev->dev.platform_data = &ath5k_pdata; -+ return 0; -+} -+ -+static int ath5k_eep_load; -+int __init of_ath5k_eeprom_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL; -+ int mac_offset; -+ u32 mac_inc = 0; -+ int i; -+ struct mtd_info *the_mtd; -+ size_t flash_readlen; -+ const __be32 *list; -+ const char *part; -+ phandle phandle; -+ -+ list = of_get_property(np, "ath,eep-flash", &i); -+ if (!list || (i != (2 * sizeof(*list)))) -+ return -ENODEV; -+ -+ phandle = be32_to_cpup(list++); -+ if (phandle) -+ mtd_np = of_find_node_by_phandle(phandle); -+ -+ if (!mtd_np) -+ return -ENODEV; -+ -+ part = of_get_property(mtd_np, "label", NULL); -+ if (!part) -+ part = mtd_np->name; -+ -+ the_mtd = get_mtd_device_nm(part); -+ if (IS_ERR(the_mtd)) -+ return -ENODEV; -+ -+ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL); -+ -+ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1, -+ &flash_readlen, (void *) ath5k_pdata.eeprom_data); -+ -+ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { -+ size_t mac_readlen; -+ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, -+ (void *) athxk_eeprom_mac); -+ } -+ put_mtd_device(the_mtd); -+ -+ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) { -+ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); -+ return -ENODEV; -+ } -+ -+ if (of_find_property(np, "ath,eep-swap", NULL)) -+ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) -+ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); -+ -+ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac()) -+ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac()); -+ -+ if (!is_valid_ether_addr(athxk_eeprom_mac)) { -+ dev_warn(&pdev->dev, "using random mac\n"); -+ random_ether_addr(athxk_eeprom_mac); -+ } -+ -+ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) -+ athxk_eeprom_mac[5] += mac_inc; -+ -+ ath5k_pdata.macaddr = athxk_eeprom_mac; -+ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; -+ -+ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); -+ -+ return 0; -+} -+ -+static struct of_device_id ath5k_eeprom_ids[] = { -+ { .compatible = "ath5k,eeprom" }, -+ { } -+}; -+ -+static struct platform_driver ath5k_eeprom_driver = { -+ .driver = { -+ .name = "ath5k,eeprom", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(ath5k_eeprom_ids), -+ }, -+}; -+ -+static int __init of_ath5k_eeprom_init(void) -+{ -+ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); -+ -+ if (ret) -+ ath5k_eep_load = 1; -+ -+ return ret; -+} -+ -+static int __init of_ath5k_eeprom_init_late(void) -+{ -+ if (!ath5k_eep_load) -+ return 0; -+ -+ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); -+} -+late_initcall(of_ath5k_eeprom_init_late); -+subsys_initcall(of_ath5k_eeprom_init); ---- /dev/null -+++ b/arch/mips/lantiq/xway/eth_mac.c -@@ -0,0 +1,25 @@ -+/* -+ * Copyright (C) 2012 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+static u8 eth_mac[6]; -+static int eth_mac_set; -+ -+const u8* ltq_get_eth_mac(void) -+{ -+ return eth_mac; -+} -+ -+static int __init setup_ethaddr(char *str) -+{ -+ eth_mac_set = mac_pton(str, eth_mac); -+ return !eth_mac_set; -+} -+early_param("ethaddr", setup_ethaddr); ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -757,7 +757,11 @@ ltq_etop_init(struct net_device *dev) - if (err) - goto err_hw; - -- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); -+ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); -+ -+ if (priv->mac && !is_valid_ether_addr(mac.sa_data)) -+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); -+ - if (!is_valid_ether_addr(mac.sa_data)) { - pr_warn("etop: invalid MAC, using random\n"); - eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-5.10/0042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-5.10/0042-arch-mips-increase-io_space_limit.patch deleted file mode 100644 index c81222af57..0000000000 --- a/target/linux/lantiq/patches-5.10/0042-arch-mips-increase-io_space_limit.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 3 Jun 2016 13:12:20 +0200 -Subject: [PATCH] arch: mips: increase io_space_limit - -this value comes from x86 and breaks some pci devices - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++ - 1 file changed, 8 insertions(+) - create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/spaces.h -@@ -0,0 +1,8 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+#ifndef __ASM_MACH_LANTIQ_SPACES_H_ -+#define __ASM_MACH_LANTIQ_SPACES_H_ -+ -+#define IO_SPACE_LIMIT 0xffffffff -+ -+#include -+#endif diff --git a/target/linux/lantiq/patches-5.10/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-5.10/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch deleted file mode 100644 index 333a2e6377..0000000000 --- a/target/linux/lantiq/patches-5.10/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch +++ /dev/null @@ -1,78 +0,0 @@ -From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Fri, 6 Jan 2017 17:55:24 +0100 -Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs - -The size of the internal RAM of the DesignWare USB controller changed -between the different Lantiq SoCs. We have the following sizes: - -Amazon + Danube: 8 KByte -Amazon SE + arx100: 2 KByte -xrx200 + xrx300: 2.5 KByte - -For Danube SoC we do not provide the params and let the driver decide -to use sane defaults, for the Amazon SE and arx100 we use small fifos -and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo. -The auto detection of max_transfer_size and max_packet_count should -work, so remove it. - -Signed-off-by: Hauke Mehrtens ---- - drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++------- - 1 file changed, 39 insertions(+), 7 deletions(-) - ---- a/drivers/usb/dwc2/params.c -+++ b/drivers/usb/dwc2/params.c -@@ -92,7 +92,14 @@ static void dwc2_set_rk_params(struct dw - p->power_down = DWC2_POWER_DOWN_PARAM_NONE; - } - --static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) -+static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg) -+{ -+ struct dwc2_core_params *p = &hsotg->params; -+ -+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; -+} -+ -+static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg) - { - struct dwc2_core_params *p = &hsotg->params; - -@@ -100,12 +107,20 @@ static void dwc2_set_ltq_params(struct d - p->host_rx_fifo_size = 288; - p->host_nperio_tx_fifo_size = 128; - p->host_perio_tx_fifo_size = 96; -- p->max_transfer_size = 65535; -- p->max_packet_count = 511; - p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << - GAHBCFG_HBSTLEN_SHIFT; - } - -+static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg) -+{ -+ struct dwc2_core_params *p = &hsotg->params; -+ -+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; -+ p->host_rx_fifo_size = 288; -+ p->host_nperio_tx_fifo_size = 128; -+ p->host_perio_tx_fifo_size = 136; -+} -+ - static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) - { - struct dwc2_core_params *p = &hsotg->params; -@@ -196,8 +211,11 @@ const struct of_device_id dwc2_of_match_ - { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, - { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, - { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, -- { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, -- { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, -+ { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params }, -+ { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params }, -+ { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params }, -+ { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params }, -+ { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params }, - { .compatible = "snps,dwc2" }, - { .compatible = "samsung,s3c6400-hsotg", - .data = dwc2_set_s3c6400_params }, diff --git a/target/linux/lantiq/patches-5.10/0051-MIPS-lantiq-improve-USB-initialization.patch b/target/linux/lantiq/patches-5.10/0051-MIPS-lantiq-improve-USB-initialization.patch deleted file mode 100644 index 9d62892b56..0000000000 --- a/target/linux/lantiq/patches-5.10/0051-MIPS-lantiq-improve-USB-initialization.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Fri, 6 Jan 2017 17:40:12 +0100 -Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization - -This adds code to initialize the USB controller and PHY also on Danube, -Amazon SE and AR10. This code is based on the Vendor driver from -different UGW versions and compared to the hardware documentation. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/lantiq/xway/sysctrl.c | 20 +++++++ - 2 files changed, 110 insertions(+), 30 deletions(-) - - ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -248,6 +248,25 @@ static void pmu_disable(struct clk *clk) - pr_warn("deactivating PMU module failed!"); - } - -+static void usb_set_clock(void) -+{ -+ unsigned int val = ltq_cgu_r32(ifccr); -+ -+ if (of_machine_is_compatible("lantiq,ar10") || -+ of_machine_is_compatible("lantiq,grx390")) { -+ val &= ~0x03; /* XTAL divided by 3 */ -+ } else if (of_machine_is_compatible("lantiq,ar9") || -+ of_machine_is_compatible("lantiq,vr9")) { -+ /* TODO: this depends on the XTAL frequency */ -+ val |= 0x03; /* XTAL divided by 3 */ -+ } else if (of_machine_is_compatible("lantiq,ase")) { -+ val |= 0x20; /* from XTAL */ -+ } else if (of_machine_is_compatible("lantiq,danube")) { -+ val |= 0x30; /* 12 MHz, generated from 36 MHz */ -+ } -+ ltq_cgu_w32(val, ifccr); -+} -+ - /* the pci enable helper */ - static int pci_enable(struct clk *clk) - { -@@ -585,4 +604,5 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE); - clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); - } -+ usb_set_clock(); - } diff --git a/target/linux/lantiq/patches-5.10/0101-find_active_root.patch b/target/linux/lantiq/patches-5.10/0101-find_active_root.patch deleted file mode 100644 index 925ac9dbba..0000000000 --- a/target/linux/lantiq/patches-5.10/0101-find_active_root.patch +++ /dev/null @@ -1,93 +0,0 @@ ---- a/drivers/mtd/parsers/ofpart_core.c -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d - return of_get_property(pp, "compatible", NULL); - } - -+static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master, -+ loff_t offset) -+{ -+ static uint8_t root_id; -+ int err, len; -+ -+ err = mtd_read(master, offset, 0x01, &len, &root_id); -+ -+ if (mtd_is_bitflip(err) || !err) -+ return &root_id; -+ -+ return NULL; -+} -+ -+static void brnboot_set_active_root_part(struct mtd_partition *pparts, -+ struct device_node **part_nodes, -+ int nr_parts, -+ uint8_t *root_id) -+{ -+ int i; -+ -+ for (i = 0; i < nr_parts; i++) { -+ int part_root_id; -+ -+ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id) -+ && part_root_id == *root_id) { -+ pparts[i].name = "firmware"; -+ break; -+ } -+ } -+} -+ - static int parse_fixed_partitions(struct mtd_info *master, - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) -@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct - struct device_node *pp; - int nr_parts, i, ret = 0; - bool dedicated = true; -+ uint8_t *proot_id = NULL; -+ struct device_node **part_nodes; - - /* Pull of_node from the master device node */ - mtd_node = mtd_get_of_node(master); -@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct - return 0; - - parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL); -- if (!parts) -+ part_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL); -+ -+ if (!parts || !part_nodes) - return -ENOMEM; - - i = 0; -@@ -147,6 +183,11 @@ static int parse_fixed_partitions(struct - if (of_property_read_bool(pp, "slc-mode")) - parts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION; - -+ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector")) -+ proot_id = brnboot_get_selected_root_part(master, parts[i].offset); -+ -+ part_nodes[i] = pp; -+ - i++; - } - -@@ -156,6 +197,11 @@ static int parse_fixed_partitions(struct - if (quirks && quirks->post_parse) - quirks->post_parse(master, parts, nr_parts); - -+ if (proot_id) -+ brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id); -+ -+ kfree(part_nodes); -+ - *pparts = parts; - return nr_parts; - -@@ -166,6 +212,7 @@ ofpart_fail: - ofpart_none: - of_node_put(pp); - kfree(parts); -+ kfree(part_nodes); - return ret; - } - diff --git a/target/linux/lantiq/patches-5.10/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-5.10/0151-lantiq-ifxmips_pcie-use-of.patch deleted file mode 100644 index 10633199e6..0000000000 --- a/target/linux/lantiq/patches-5.10/0151-lantiq-ifxmips_pcie-use-of.patch +++ /dev/null @@ -1,387 +0,0 @@ ---- a/arch/mips/pci/ifxmips_pcie.c -+++ b/arch/mips/pci/ifxmips_pcie.c -@@ -16,8 +16,15 @@ - #include - #include - #include -+#include -+#include -+#include -+#include - #include - -+#include -+#include -+ - #include "ifxmips_pcie.h" - #include "ifxmips_pcie_reg.h" - -@@ -40,6 +47,10 @@ - static DEFINE_SPINLOCK(ifx_pcie_lock); - - u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); -+static int pcie_reset_gpio; -+static struct phy *ltq_pcie_phy; -+static struct reset_control *ltq_pcie_reset; -+static struct regmap *ltq_rcu_regmap; - - static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { - { -@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ... - printk("%s", buf); - } - -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+ gpio_direction_output(pcie_reset_gpio, 1); -+ gpio_set_value(pcie_reset_gpio, 1); -+} -+ -+static inline void pcie_device_rst_assert(int pcie_port) -+{ -+ gpio_set_value(pcie_reset_gpio, 0); -+} -+ -+static inline void pcie_device_rst_deassert(int pcie_port) -+{ -+ mdelay(100); -+ gpio_direction_output(pcie_reset_gpio, 1); -+} - - static inline int pcie_ltssm_enable(int pcie_port) - { -@@ -988,10 +1015,22 @@ int ifx_pcie_bios_plat_dev_init(struct - static int - pcie_rc_initialize(int pcie_port) - { -- int i; -+ int i, ret; - #define IFX_PCIE_PHY_LOOP_CNT 5 - -- pcie_rcu_endian_setup(pcie_port); -+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M, -+ IFX_RCU_AHB_BE_PCIE_M); -+ -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, -+ IFX_RCU_AHB_BE_PCIE_S); -+#else -+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S, -+ 0x0); -+#endif -+ -+ regmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M, -+ 0x0); - - pcie_ep_gpio_rst_init(pcie_port); - -@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port) - * reset PCIe PHY will solve this issue - */ - for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { -- /* Disable PCIe PHY Analog part for sanity check */ -- pcie_phy_pmu_disable(pcie_port); -- -- pcie_phy_rst_assert(pcie_port); -- pcie_phy_rst_deassert(pcie_port); -- -- /* Make sure PHY PLL is stable */ -- udelay(20); -- -- /* PCIe Core reset enabled, low active, sw programmed */ -- pcie_core_rst_assert(pcie_port); -+ ret = phy_init(ltq_pcie_phy); -+ if (ret) -+ continue; - - /* Put PCIe EP in reset status */ - pcie_device_rst_assert(pcie_port); - -- /* PCI PHY & Core reset disabled, high active, sw programmed */ -- pcie_core_rst_deassert(pcie_port); -+ udelay(1); -+ reset_control_deassert(ltq_pcie_reset); - -- /* Already in a quiet state, program PLL, enable PHY, check ready bit */ -- pcie_phy_clock_mode_setup(pcie_port); -+ ret = phy_power_on(ltq_pcie_phy); -+ if (ret) { -+ phy_exit(ltq_pcie_phy); -+ continue; -+ } - - /* Enable PCIe PHY and Clock */ - pcie_core_pmu_setup(pcie_port); -@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port) - /* Once link is up, break out */ - if (pcie_app_loigc_setup(pcie_port) == 0) - break; -+ -+ phy_power_off(ltq_pcie_phy); -+ reset_control_assert(ltq_pcie_reset); -+ phy_exit(ltq_pcie_phy); - } - if (i >= IFX_PCIE_PHY_LOOP_CNT) { - printk(KERN_ERR "%s link up failed!!!!!\n", __func__); -@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port) - return 0; - } - --static int __init ifx_pcie_bios_init(void) -+static int ifx_pcie_bios_probe(struct platform_device *pdev) - { -+ struct device_node *node = pdev->dev.of_node; - void __iomem *io_map_base; - int pcie_port; - int startup_port; -+ struct device_node *np; -+ struct pci_bus *bus; -+ -+ /* -+ * In case a PCI device is physical present, the Lantiq PCI driver need -+ * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them -+ * will work. -+ * -+ * In case the lantiq PCI driver is enabled in the device tree, check if -+ * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already -+ * registered. -+ * -+ * It will fail if there is another PCI controller, this controller is -+ * registered before the Lantiq PCIe driver is probe and the lantiq PCI -+ */ -+ np = of_find_compatible_node(NULL, NULL, "lantiq,pci-xway"); -+ -+ if (of_device_is_available(np)) { -+ bus = pci_find_next_bus(bus); -+ -+ if (!bus) -+ return -EPROBE_DEFER; -+ } - - /* Enable AHB Master/ Slave */ - pcie_ahb_pmu_setup(); - - startup_port = IFX_PCIE_PORT0; -- -+ -+ ltq_pcie_phy = devm_phy_get(&pdev->dev, "pcie"); -+ if (IS_ERR(ltq_pcie_phy)) { -+ dev_err(&pdev->dev, "failed to get the PCIe PHY\n"); -+ return PTR_ERR(ltq_pcie_phy); -+ } -+ -+ ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL); -+ if (IS_ERR(ltq_pcie_reset)) { -+ dev_err(&pdev->dev, "failed to get the PCIe reset line\n"); -+ return PTR_ERR(ltq_pcie_reset); -+ } -+ -+ ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, "lantiq,rcu"); -+ if (IS_ERR(ltq_rcu_regmap)) -+ return PTR_ERR(ltq_rcu_regmap); -+ -+ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); -+ if (gpio_is_valid(pcie_reset_gpio)) { -+ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset"); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio); -+ return ret; -+ } -+ gpio_direction_output(pcie_reset_gpio, 1); -+ } -+ - for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ - if (pcie_rc_initialize(pcie_port) == 0) { - IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", -@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi - return -ENOMEM; - } - ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; -+ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node); - - register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); - /* XXX, clear error status */ -@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi - - return 0; - } -+ -+static const struct of_device_id ifxmips_pcie_match[] = { -+ { .compatible = "lantiq,pcie-xrx200" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ifxmips_pcie_match); -+ -+static struct platform_driver ltq_pci_driver = { -+ .probe = ifx_pcie_bios_probe, -+ .driver = { -+ .name = "pcie-xrx200", -+ .owner = THIS_MODULE, -+ .of_match_table = ifxmips_pcie_match, -+ }, -+}; -+ -+int __init ifx_pcie_bios_init(void) -+{ -+ int ret = platform_driver_register(<q_pci_driver); -+ if (ret) -+ pr_info("pcie-xrx200: Error registering platform driver!"); -+ return ret; -+} -+ - arch_initcall(ifx_pcie_bios_init); - - MODULE_LICENSE("GPL"); ---- a/arch/mips/pci/ifxmips_pcie_vr9.h -+++ b/arch/mips/pci/ifxmips_pcie_vr9.h -@@ -22,8 +22,6 @@ - #include - #include - --#define IFX_PCIE_GPIO_RESET 494 -- - #define IFX_REG_R32 ltq_r32 - #define IFX_REG_W32 ltq_w32 - #define CONFIG_IFX_PCIE_HW_SWAP -@@ -53,21 +51,6 @@ - #define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) - - --static inline void pcie_ep_gpio_rst_init(int pcie_port) --{ -- -- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); -- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); -- gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -- --/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ --} -- - static inline void pcie_ahb_pmu_setup(void) - { - /* Enable AHB bus master/slave */ -@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo - //AHBS_PMU_SETUP(IFX_PMU_ENABLE); - } - --static inline void pcie_rcu_endian_setup(int pcie_port) --{ -- u32 reg; -- -- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); --#ifdef CONFIG_IFX_PCIE_HW_SWAP -- reg |= IFX_RCU_AHB_BE_PCIE_M; -- reg |= IFX_RCU_AHB_BE_PCIE_S; -- reg &= ~IFX_RCU_AHB_BE_XBAR_M; --#else -- reg |= IFX_RCU_AHB_BE_PCIE_M; -- reg &= ~IFX_RCU_AHB_BE_PCIE_S; -- reg &= ~IFX_RCU_AHB_BE_XBAR_M; --#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -- IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); --} -- - static inline void pcie_phy_pmu_enable(int pcie_port) - { - struct clk *clk; -@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable( - // PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); - } - --static inline void pcie_pdi_big_endian(int pcie_port) --{ -- u32 reg; -- -- /* SRAM2PDI endianness control. */ -- reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -- /* Config AHB->PCIe and PDI endianness */ -- reg |= IFX_RCU_AHB_BE_PCIE_PDI; -- IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); --} -- - static inline void pcie_pdi_pmu_enable(int pcie_port) - { - /* Enable PDI to access PCIe PHY register */ -@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i - //PDI_PMU_SETUP(IFX_PMU_ENABLE); - } - --static inline void pcie_core_rst_assert(int pcie_port) --{ -- u32 reg; -- -- reg = IFX_REG_R32(IFX_RCU_RST_REQ); -- -- /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ -- reg |= 0x00400000; -- IFX_REG_W32(reg, IFX_RCU_RST_REQ); --} -- --static inline void pcie_core_rst_deassert(int pcie_port) --{ -- u32 reg; -- -- /* Make sure one micro-second delay */ -- udelay(1); -- -- /* Reset PCIe PHY & Core, bit 22 */ -- reg = IFX_REG_R32(IFX_RCU_RST_REQ); -- reg &= ~0x00400000; -- IFX_REG_W32(reg, IFX_RCU_RST_REQ); --} -- --static inline void pcie_phy_rst_assert(int pcie_port) --{ -- u32 reg; -- -- reg = IFX_REG_R32(IFX_RCU_RST_REQ); -- reg |= 0x00001000; /* Bit 12 */ -- IFX_REG_W32(reg, IFX_RCU_RST_REQ); --} -- --static inline void pcie_phy_rst_deassert(int pcie_port) --{ -- u32 reg; -- -- /* Make sure one micro-second delay */ -- udelay(1); -- -- reg = IFX_REG_R32(IFX_RCU_RST_REQ); -- reg &= ~0x00001000; /* Bit 12 */ -- IFX_REG_W32(reg, IFX_RCU_RST_REQ); --} -- --static inline void pcie_device_rst_assert(int pcie_port) --{ -- gpio_set_value(IFX_PCIE_GPIO_RESET, 0); --// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); --} -- --static inline void pcie_device_rst_deassert(int pcie_port) --{ -- mdelay(100); -- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); --// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); --} -- - static inline void pcie_core_pmu_setup(int pcie_port) - { - struct clk *clk; ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -43,7 +43,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o - obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o - obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o - obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o --obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o -+obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie.o fixup-lantiq-pcie.o - obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o diff --git a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch deleted file mode 100644 index cde8ae5ed0..0000000000 --- a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch +++ /dev/null @@ -1,172 +0,0 @@ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -2434,6 +2434,12 @@ config MIPS_VPE_LOADER - Includes a loader for loading an elf relocatable object - onto another VPE and running it. - -+config IFX_VPE_EXT -+ bool "IFX APRP Extensions" -+ depends on MIPS_VPE_LOADER -+ help -+ IFX included extensions in APRP -+ - config MIPS_VPE_LOADER_CMP - bool - default "y" ---- a/arch/mips/include/asm/vpe.h -+++ b/arch/mips/include/asm/vpe.h -@@ -126,4 +126,13 @@ void cleanup_tc(struct tc *tc); - - int __init vpe_module_init(void); - void __exit vpe_module_exit(void); -+ -+/* For the explanation of the APIs please refer the section "MT APRP Kernel -+ * Programming" in AR9 SW Architecture Specification -+ */ -+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags); -+int32_t vpe1_sw_stop(uint32_t flags); -+uint32_t vpe1_get_load_addr(uint32_t flags); -+uint32_t vpe1_get_max_mem(uint32_t flags); -+ - #endif /* _ASM_VPE_H */ ---- a/arch/mips/kernel/vpe-mt.c -+++ b/arch/mips/kernel/vpe-mt.c -@@ -415,6 +415,8 @@ int __init vpe_module_init(void) - } - - v->ntcs = hw_tcs - aprp_cpu_index(); -+ write_tc_c0_tcbind((read_tc_c0_tcbind() & -+ ~TCBIND_CURVPE) | 1); - - /* add the tc to the list of this vpe's tc's. */ - list_add(&t->tc, &v->tc); -@@ -518,3 +520,47 @@ void __exit vpe_module_exit(void) - release_vpe(v); - } - } -+ -+#ifdef CONFIG_IFX_VPE_EXT -+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags) -+{ -+ enum vpe_state state; -+ struct vpe *v = get_vpe(tclimit); -+ struct vpe_notifications *not; -+ -+ if (tcmask || flags) { -+ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n"); -+ return -1; -+ } -+ -+ state = xchg(&v->state, VPE_STATE_INUSE); -+ if (state != VPE_STATE_UNUSED) { -+ vpe_stop(v); -+ -+ list_for_each_entry(not, &v->notify, list) { -+ not->stop(tclimit); -+ } -+ } -+ -+ v->__start = (unsigned long)sw_start_addr; -+ -+ if (!vpe_run(v)) { -+ pr_debug("VPE loader: VPE1 running successfully\n"); -+ return 0; -+ } -+ return -1; -+} -+EXPORT_SYMBOL(vpe1_sw_start); -+ -+int32_t vpe1_sw_stop(uint32_t flags) -+{ -+ struct vpe *v = get_vpe(tclimit); -+ -+ if (!vpe_free(v)) { -+ pr_debug("RP Stopped\n"); -+ return 0; -+ } else -+ return -1; -+} -+EXPORT_SYMBOL(vpe1_sw_stop); -+#endif ---- a/arch/mips/kernel/vpe.c -+++ b/arch/mips/kernel/vpe.c -@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = { - .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) - }; - -+#ifdef CONFIG_IFX_VPE_EXT -+unsigned int vpe1_load_addr; -+ -+static int __init load_address(char *str) -+{ -+ get_option(&str, &vpe1_load_addr); -+ return 1; -+} -+__setup("vpe1_load_addr=", load_address); -+ -+static unsigned int vpe1_mem; -+static int __init vpe1mem(char *str) -+{ -+ vpe1_mem = memparse(str, &str); -+ return 1; -+} -+__setup("vpe1_mem=", vpe1mem); -+ -+uint32_t vpe1_get_load_addr(uint32_t flags) -+{ -+ return vpe1_load_addr; -+} -+EXPORT_SYMBOL(vpe1_get_load_addr); -+ -+uint32_t vpe1_get_max_mem(uint32_t flags) -+{ -+ if (!vpe1_mem) -+ return P_SIZE; -+ else -+ return vpe1_mem; -+} -+EXPORT_SYMBOL(vpe1_get_max_mem); -+ -+#endif -+ - /* get the vpe associated with this minor */ - struct vpe *get_vpe(int minor) - { ---- a/arch/mips/lantiq/prom.c -+++ b/arch/mips/lantiq/prom.c -@@ -28,10 +28,14 @@ EXPORT_SYMBOL_GPL(ebu_lock); - */ - static struct ltq_soc_info soc_info; - -+/* for Multithreading (APRP), vpe.c will use it */ -+unsigned long cp0_memsize; -+ - const char *get_system_type(void) - { - return soc_info.sys_type; - } -+EXPORT_SYMBOL(ltq_soc_type); - - int ltq_soc_type(void) - { ---- a/arch/mips/include/asm/mipsmtregs.h -+++ b/arch/mips/include/asm/mipsmtregs.h -@@ -32,6 +32,9 @@ - #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) - #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) - -+#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) -+#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) -+ - #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) - #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) - -@@ -378,6 +381,8 @@ do { \ - #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) - #define read_vpe_c0_vpeconf1() mftc0(1, 3) - #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) -+#define read_vpe_c0_vpeopt() mftc0(1, 7) -+#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) - #define read_vpe_c0_count() mftc0(9, 0) - #define write_vpe_c0_count(val) mttc0(9, 0, val) - #define read_vpe_c0_status() mftc0(12, 0) diff --git a/target/linux/lantiq/patches-5.10/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-5.10/0154-lantiq-pci-bar11mask-fix.patch deleted file mode 100644 index d6556d115d..0000000000 --- a/target/linux/lantiq/patches-5.10/0154-lantiq-pci-bar11mask-fix.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/arch/mips/pci/pci-lantiq.c -+++ b/arch/mips/pci/pci-lantiq.c -@@ -59,6 +59,8 @@ - #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) - #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) - -+extern u32 max_low_pfn; -+ - __iomem void *ltq_pci_mapped_cfg; - static __iomem void *ltq_pci_membase; - -@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi - u32 mem, bar11mask; - - /* BAR11MASK value depends on available memory on system. */ -- mem = get_num_physpages() * PAGE_SIZE; -- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; -+ mem = max_low_pfn << PAGE_SHIFT; -+ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8; - - return bar11mask; - } diff --git a/target/linux/lantiq/patches-5.10/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-5.10/0155-lantiq-VPE-nosmp.patch deleted file mode 100644 index 2705723dda..0000000000 --- a/target/linux/lantiq/patches-5.10/0155-lantiq-VPE-nosmp.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/mips/kernel/vpe-mt.c -+++ b/arch/mips/kernel/vpe-mt.c -@@ -130,7 +130,10 @@ int vpe_run(struct vpe *v) - * kernels need to turn it on, even if that wasn't the pre-dvpe() state. - */ - #ifdef CONFIG_SMP -- evpe(vpeflags); -+ if (!setup_max_cpus) /* nosmp is set */ -+ evpe(EVPE_ENABLE); -+ else -+ evpe(vpeflags); - #else - evpe(EVPE_ENABLE); - #endif diff --git a/target/linux/lantiq/patches-5.10/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-5.10/0160-owrt-lantiq-multiple-flash.patch deleted file mode 100644 index 796220b2bc..0000000000 --- a/target/linux/lantiq/patches-5.10/0160-owrt-lantiq-multiple-flash.patch +++ /dev/null @@ -1,220 +0,0 @@ ---- a/drivers/mtd/maps/lantiq-flash.c -+++ b/drivers/mtd/maps/lantiq-flash.c -@@ -17,6 +17,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -36,13 +37,16 @@ enum { - LTQ_NOR_NORMAL - }; - -+#define MAX_RESOURCES 4 -+ - struct ltq_mtd { -- struct resource *res; -- struct mtd_info *mtd; -- struct map_info *map; -+ struct mtd_info *mtd[MAX_RESOURCES]; -+ struct mtd_info *cmtd; -+ struct map_info map[MAX_RESOURCES]; - }; - - static const char ltq_map_name[] = "ltq_nor"; -+static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL }; - - static map_word - ltq_read16(struct map_info *map, unsigned long adr) -@@ -106,11 +110,43 @@ ltq_copy_to(struct map_info *map, unsign - } - - static int -+ltq_mtd_remove(struct platform_device *pdev) -+{ -+ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); -+ int i; -+ -+ if (ltq_mtd == NULL) -+ return 0; -+ -+ if (ltq_mtd->cmtd) { -+ mtd_device_unregister(ltq_mtd->cmtd); -+ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) -+ mtd_concat_destroy(ltq_mtd->cmtd); -+ } -+ -+ for (i = 0; i < MAX_RESOURCES; i++) { -+ if (ltq_mtd->mtd[i] != NULL) -+ map_destroy(ltq_mtd->mtd[i]); -+ } -+ -+ kfree(ltq_mtd); -+ -+ return 0; -+} -+ -+static int - ltq_mtd_probe(struct platform_device *pdev) - { - struct ltq_mtd *ltq_mtd; - struct cfi_private *cfi; -- int err; -+ int err = 0; -+ int i; -+ int devices_found = 0; -+ -+ static const char *rom_probe_types[] = { -+ "cfi_probe", "jedec_probe", NULL -+ }; -+ const char **type; - - ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL); - if (!ltq_mtd) -@@ -118,75 +154,89 @@ ltq_mtd_probe(struct platform_device *pd - - platform_set_drvdata(pdev, ltq_mtd); - -- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- if (!ltq_mtd->res) { -- dev_err(&pdev->dev, "failed to get memory resource\n"); -- return -ENOENT; -+ for (i = 0; i < pdev->num_resources; i++) { -+ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", -+ (unsigned long long)resource_size(&pdev->resource[i]), -+ (unsigned long long)pdev->resource[i].start); -+ -+ if (!devm_request_mem_region(&pdev->dev, -+ pdev->resource[i].start, -+ resource_size(&pdev->resource[i]), -+ dev_name(&pdev->dev))) { -+ dev_err(&pdev->dev, "Could not reserve memory region\n"); -+ return -ENOMEM; -+ } -+ -+ ltq_mtd->map[i].name = ltq_map_name; -+ ltq_mtd->map[i].bankwidth = 2; -+ ltq_mtd->map[i].read = ltq_read16; -+ ltq_mtd->map[i].write = ltq_write16; -+ ltq_mtd->map[i].copy_from = ltq_copy_from; -+ ltq_mtd->map[i].copy_to = ltq_copy_to; -+ -+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) -+ ltq_mtd->map[i].phys = NO_XIP; -+ else -+ ltq_mtd->map[i].phys = pdev->resource[i].start; -+ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); -+ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, -+ ltq_mtd->map[i].size); -+ if (IS_ERR(ltq_mtd->map[i].virt)) -+ return PTR_ERR(ltq_mtd->map[i].virt); -+ -+ if (ltq_mtd->map[i].virt == NULL) { -+ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); -+ err = PTR_ERR(ltq_mtd->map[i].virt); -+ goto err_out; -+ } -+ -+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; -+ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) -+ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); -+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; -+ -+ if (!ltq_mtd->mtd[i]) { -+ dev_err(&pdev->dev, "probing failed\n"); -+ return -ENXIO; -+ } else { -+ devices_found++; -+ } -+ -+ ltq_mtd->mtd[i]->owner = THIS_MODULE; -+ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; -+ -+ cfi = ltq_mtd->map[i].fldrv_priv; -+ cfi->addr_unlock1 ^= 1; -+ cfi->addr_unlock2 ^= 1; - } - -- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), -- GFP_KERNEL); -- if (!ltq_mtd->map) -- return -ENOMEM; -- -- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) -- ltq_mtd->map->phys = NO_XIP; -- else -- ltq_mtd->map->phys = ltq_mtd->res->start; -- ltq_mtd->res->start; -- ltq_mtd->map->size = resource_size(ltq_mtd->res); -- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); -- if (IS_ERR(ltq_mtd->map->virt)) -- return PTR_ERR(ltq_mtd->map->virt); -- -- ltq_mtd->map->name = ltq_map_name; -- ltq_mtd->map->bankwidth = 2; -- ltq_mtd->map->read = ltq_read16; -- ltq_mtd->map->write = ltq_write16; -- ltq_mtd->map->copy_from = ltq_copy_from; -- ltq_mtd->map->copy_to = ltq_copy_to; -- -- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; -- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); -- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; -- -- if (!ltq_mtd->mtd) { -- dev_err(&pdev->dev, "probing failed\n"); -- return -ENXIO; -+ if (devices_found == 1) { -+ ltq_mtd->cmtd = ltq_mtd->mtd[0]; -+ } else if (devices_found > 1) { -+ /* -+ * We detected multiple devices. Concatenate them together. -+ */ -+ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); -+ if (ltq_mtd->cmtd == NULL) -+ err = -ENXIO; - } - -- ltq_mtd->mtd->dev.parent = &pdev->dev; -- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node); -- -- cfi = ltq_mtd->map->fldrv_priv; -- cfi->addr_unlock1 ^= 1; -- cfi->addr_unlock2 ^= 1; -+ ltq_mtd->cmtd->dev.parent = &pdev->dev; -+ mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node); - -- err = mtd_device_register(ltq_mtd->mtd, NULL, 0); -+ err = mtd_device_register(ltq_mtd->cmtd, NULL, 0); - if (err) { - dev_err(&pdev->dev, "failed to add partitions\n"); -- goto err_destroy; -+ goto err_out; - } - - return 0; - --err_destroy: -- map_destroy(ltq_mtd->mtd); -+err_out: -+ ltq_mtd_remove(pdev); - return err; - } - --static int --ltq_mtd_remove(struct platform_device *pdev) --{ -- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); -- -- if (ltq_mtd && ltq_mtd->mtd) { -- mtd_device_unregister(ltq_mtd->mtd); -- map_destroy(ltq_mtd->mtd); -- } -- return 0; --} -- - static const struct of_device_id ltq_mtd_match[] = { - { .compatible = "lantiq,nor" }, - {}, diff --git a/target/linux/lantiq/patches-5.10/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-5.10/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch deleted file mode 100644 index d153c521d3..0000000000 --- a/target/linux/lantiq/patches-5.10/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0001.c -+++ b/drivers/mtd/chips/cfi_cmdset_0001.c -@@ -39,7 +39,7 @@ - /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ - - // debugging, turns off buffer write mode if set to 1 --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - /* Intel chips */ - #define I82802AB 0x00ad diff --git a/target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch deleted file mode 100644 index 92c4b56493..0000000000 --- a/target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -440,6 +440,20 @@ static void clkdev_add_clkout(void) - } - } - -+static void set_phy_clock_source(struct device_node *np_cgu) -+{ -+ u32 phy_clk_src, ifcc; -+ -+ if (!np_cgu) -+ return; -+ -+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) -+ return; -+ -+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); -+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); -+} -+ - /* bring up all register ranges that we need for basic system control */ - void __init ltq_soc_init(void) - { -@@ -605,4 +619,6 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0); - } - usb_set_clock(); -+ -+ set_phy_clock_source(np_cgu); - } diff --git a/target/linux/lantiq/patches-5.10/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch b/target/linux/lantiq/patches-5.10/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch deleted file mode 100644 index 33c06e9d77..0000000000 --- a/target/linux/lantiq/patches-5.10/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch +++ /dev/null @@ -1,86 +0,0 @@ -From 49293bbc50cb7d44223eb49e0f7cb38e7dac2361 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Tue, 14 Sep 2021 23:21:01 +0200 -Subject: [PATCH 4/5] MIPS: lantiq: dma: make the burst length configurable by - the drivers - -Make the burst length configurable by the drivers. - -Signed-off-by: Aleksander Jan Bajkowski -Acked-by: Hauke Mehrtens -Signed-off-by: David S. Miller ---- - .../include/asm/mach-lantiq/xway/xway_dma.h | 2 +- - arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++--- - 2 files changed, 34 insertions(+), 6 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h -@@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma - extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch); - extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch); - extern void ltq_dma_free(struct ltq_dma_channel *ch); --extern void ltq_dma_init_port(int p); -+extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst); - - #endif ---- a/arch/mips/lantiq/xway/dma.c -+++ b/arch/mips/lantiq/xway/dma.c -@@ -181,7 +181,7 @@ ltq_dma_free(struct ltq_dma_channel *ch) - EXPORT_SYMBOL_GPL(ltq_dma_free); - - void --ltq_dma_init_port(int p) -+ltq_dma_init_port(int p, int tx_burst, int rx_burst) - { - ltq_dma_w32(p, LTQ_DMA_PS); - switch (p) { -@@ -190,16 +190,44 @@ ltq_dma_init_port(int p) - * Tell the DMA engine to swap the endianness of data frames and - * drop packets if the channel arbitration fails. - */ -- ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, -+ ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN), - LTQ_DMA_PCTRL); - break; - -- case DMA_PORT_DEU: -- ltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) | -- (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT), -+ default: -+ break; -+ } -+ -+ switch (rx_burst) { -+ case 8: -+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT), - LTQ_DMA_PCTRL); - break; -+ case 4: -+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT), -+ LTQ_DMA_PCTRL); -+ break; -+ case 2: -+ ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT), -+ LTQ_DMA_PCTRL); -+ break; -+ default: -+ break; -+ } - -+ switch (tx_burst) { -+ case 8: -+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT), -+ LTQ_DMA_PCTRL); -+ break; -+ case 4: -+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT), -+ LTQ_DMA_PCTRL); -+ break; -+ case 2: -+ ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT), -+ LTQ_DMA_PCTRL); -+ break; - default: - break; - } diff --git a/target/linux/lantiq/patches-5.10/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch b/target/linux/lantiq/patches-5.10/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch deleted file mode 100644 index 0bb1fefc5f..0000000000 --- a/target/linux/lantiq/patches-5.10/0320-v6.1-MIPS-lantiq-enable-all-hardware-interrupts-on-second.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 730320fd770d4114a2ecb6fb223dcc8c3cecdc5b Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Wed, 21 Sep 2022 22:59:44 +0200 -Subject: [PATCH] MIPS: lantiq: enable all hardware interrupts on second VPE - -This patch is needed to handle interrupts by the second VPE on the Lantiq -ARX100, xRX200, xRX300 and xRX330 SoCs. Switching some ICU interrupts to -the second VPE results in a hang. Currently, the vsmp_init_secondary() -function is responsible for enabling these interrupts. It only enables -Malta-specific interrupts (SW0, SW1, HW4 and HW5). - -The MIPS core has 8 interrupts defined. On Lantiq SoCs, hardware -interrupts are wired to an ICU instance. Each VPE has an independent -instance of the ICU. The mapping of the ICU interrupts is shown below: -SW0(IP0) - IPI call, -SW1(IP1) - IPI resched, -HW0(IP2) - ICU 0-31, -HW1(IP3) - ICU 32-63, -HW2(IP4) - ICU 64-95, -HW3(IP5) - ICU 96-127, -HW4(IP6) - ICU 128-159, -HW5(IP7) - timer. - -This patch enables all interrupt lines on the second VPE. - -This problem affects multithreaded SoCs with a custom interrupt controller. -SOCs with 1004Kc core and newer use the MIPS GIC. At this point, I am aware -that the Realtek RTL839x and RTL930x SoCs may need a similar fix. In the -future, this may be replaced with some generic solution. - -Tested on Lantiq xRX200. - -Suggested-by: Thomas Bogendoerfer -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/lantiq/prom.c | 26 ++++++++++++++++++++++++-- - 1 file changed, 24 insertions(+), 2 deletions(-) - ---- a/arch/mips/lantiq/prom.c -+++ b/arch/mips/lantiq/prom.c -@@ -31,6 +31,14 @@ static struct ltq_soc_info soc_info; - /* for Multithreading (APRP), vpe.c will use it */ - unsigned long cp0_memsize; - -+/* -+ * These structs are used to override vsmp_init_secondary() -+ */ -+#if defined(CONFIG_MIPS_MT_SMP) -+extern const struct plat_smp_ops vsmp_smp_ops; -+static struct plat_smp_ops lantiq_smp_ops; -+#endif -+ - const char *get_system_type(void) - { - return soc_info.sys_type; -@@ -94,6 +102,17 @@ void __init device_tree_init(void) - unflatten_and_copy_device_tree(); - } - -+#if defined(CONFIG_MIPS_MT_SMP) -+static void lantiq_init_secondary(void) -+{ -+ /* -+ * MIPS CPU startup function vsmp_init_secondary() will only -+ * enable some of the interrupts for the second CPU/VPE. -+ */ -+ set_c0_status(ST0_IM); -+} -+#endif -+ - void __init prom_init(void) - { - /* call the soc specific detetcion code and get it to fill soc_info */ -@@ -105,7 +124,10 @@ void __init prom_init(void) - prom_init_cmdline(); - - #if defined(CONFIG_MIPS_MT_SMP) -- if (register_vsmp_smp_ops()) -- panic("failed to register_vsmp_smp_ops()"); -+ if (cpu_has_mipsmt) { -+ lantiq_smp_ops = vsmp_smp_ops; -+ lantiq_smp_ops.init_secondary = lantiq_init_secondary; -+ register_smp_ops(&lantiq_smp_ops); -+ } - #endif - } diff --git a/target/linux/lantiq/patches-5.10/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch b/target/linux/lantiq/patches-5.10/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch deleted file mode 100644 index edf0626860..0000000000 --- a/target/linux/lantiq/patches-5.10/0400-mtd-rawnand-xway-don-t-yield-while-holding-spinlock.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 416f25a948d11ef15733f2e31658d31b5cc7bef6 Mon Sep 17 00:00:00 2001 -From: Thomas Nixon -Date: Sun, 26 Mar 2023 11:08:49 +0100 -Subject: [PATCH] mtd: rawnand: xway: don't yield while holding spinlock - -The nand driver normally while waiting for the device to become ready; -this is normally fine, but xway_nand holds the ebu_lock spinlock, and -this can cause lockups if other threads which use ebu_lock are -interleaved. Fix this by waiting instead of polling. - -This mainly showed up as crashes in ath9k_pci_owl_loader (see -https://github.com/openwrt/openwrt/issues/9829 ), but turning on -spinlock debugging shows this happening in other places too. - -This doesn't seem to measurably impact boot time. - -Signed-off-by: Thomas Nixon ---- - drivers/mtd/nand/raw/xway_nand.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/raw/xway_nand.c -+++ b/drivers/mtd/nand/raw/xway_nand.c -@@ -175,7 +175,13 @@ static void xway_cmd_ctrl(struct nand_ch - - static int xway_dev_ready(struct nand_chip *chip) - { -- return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD; -+ /* -+ * wait until ready, as otherwise the driver will yield in nand_wait or -+ * nand_wait_ready, which is a bad idea when we're holding ebu_lock -+ */ -+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) -+ cpu_relax(); -+ return 1; - } - - static unsigned char xway_read_byte(struct nand_chip *chip) diff --git a/target/linux/lantiq/patches-5.10/0701-NET-lantiq-etop-of-mido.patch b/target/linux/lantiq/patches-5.10/0701-NET-lantiq-etop-of-mido.patch deleted file mode 100644 index 2cc541ae3c..0000000000 --- a/target/linux/lantiq/patches-5.10/0701-NET-lantiq-etop-of-mido.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -30,6 +30,7 @@ - #include - #include - #include -+#include - - #include - -@@ -553,7 +554,8 @@ static int - ltq_etop_mdio_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int err; -+ struct device_node *mdio_np = NULL; -+ int err, ret; - - priv->mii_bus = mdiobus_alloc(); - if (!priv->mii_bus) { -@@ -573,7 +575,15 @@ ltq_etop_mdio_init(struct net_device *de - priv->mii_bus->name = "ltq_mii"; - snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", - priv->pdev->name, priv->pdev->id); -- if (mdiobus_register(priv->mii_bus)) { -+ -+ mdio_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); -+ -+ if (mdio_np) -+ ret = of_mdiobus_register(priv->mii_bus, mdio_np); -+ else -+ ret = mdiobus_register(priv->mii_bus); -+ -+ if (ret) { - err = -ENXIO; - goto err_out_free_mdiobus; - } diff --git a/target/linux/lantiq/patches-5.10/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch b/target/linux/lantiq/patches-5.10/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch deleted file mode 100644 index 5bbf752dba..0000000000 --- a/target/linux/lantiq/patches-5.10/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch +++ /dev/null @@ -1,145 +0,0 @@ -From 998ac358019e491217e752bc6dcbb3afb2a6fa3e Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Sun, 19 Sep 2021 20:24:28 +0200 -Subject: [PATCH] net: lantiq: add support for jumbo frames - -Add support for jumbo frames. Full support for jumbo frames requires -changes in the DSA switch driver (lantiq_gswip.c). - -Tested on BT Hone Hub 5A. - -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/lantiq_xrx200.c | 64 +++++++++++++++++++++++++--- - 1 file changed, 57 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -14,13 +14,15 @@ - #include - #include - -+#include -+ - #include - #include - - #include - - /* DMA */ --#define XRX200_DMA_DATA_LEN 0x600 -+#define XRX200_DMA_DATA_LEN (SZ_64K - 1) - #define XRX200_DMA_RX 0 - #define XRX200_DMA_TX 1 - -@@ -106,7 +108,8 @@ static void xrx200_flush_dma(struct xrx2 - break; - - desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | -- XRX200_DMA_DATA_LEN; -+ (ch->priv->net_dev->mtu + VLAN_ETH_HLEN + -+ ETH_FCS_LEN); - ch->dma.desc++; - ch->dma.desc %= LTQ_DESC_NUM; - } -@@ -154,19 +157,20 @@ static int xrx200_close(struct net_devic - - static int xrx200_alloc_skb(struct xrx200_chan *ch) - { -+ int len = ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; - struct sk_buff *skb = ch->skb[ch->dma.desc]; - dma_addr_t mapping; - int ret = 0; - - ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev, -- XRX200_DMA_DATA_LEN); -+ len); - if (!ch->skb[ch->dma.desc]) { - ret = -ENOMEM; - goto skip; - } - - mapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data, -- XRX200_DMA_DATA_LEN, DMA_FROM_DEVICE); -+ len, DMA_FROM_DEVICE); - if (unlikely(dma_mapping_error(ch->priv->dev, mapping))) { - dev_kfree_skb_any(ch->skb[ch->dma.desc]); - ch->skb[ch->dma.desc] = skb; -@@ -179,8 +183,7 @@ static int xrx200_alloc_skb(struct xrx20 - wmb(); - skip: - ch->dma.desc_base[ch->dma.desc].ctl = -- LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | -- XRX200_DMA_DATA_LEN; -+ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | len; - - return ret; - } -@@ -340,10 +343,57 @@ err_drop: - return NETDEV_TX_OK; - } - -+static int -+xrx200_change_mtu(struct net_device *net_dev, int new_mtu) -+{ -+ struct xrx200_priv *priv = netdev_priv(net_dev); -+ struct xrx200_chan *ch_rx = &priv->chan_rx; -+ int old_mtu = net_dev->mtu; -+ bool running = false; -+ struct sk_buff *skb; -+ int curr_desc; -+ int ret = 0; -+ -+ net_dev->mtu = new_mtu; -+ -+ if (new_mtu <= old_mtu) -+ return ret; -+ -+ running = netif_running(net_dev); -+ if (running) { -+ napi_disable(&ch_rx->napi); -+ ltq_dma_close(&ch_rx->dma); -+ } -+ -+ xrx200_poll_rx(&ch_rx->napi, LTQ_DESC_NUM); -+ curr_desc = ch_rx->dma.desc; -+ -+ for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; -+ ch_rx->dma.desc++) { -+ skb = ch_rx->skb[ch_rx->dma.desc]; -+ ret = xrx200_alloc_skb(ch_rx); -+ if (ret) { -+ net_dev->mtu = old_mtu; -+ break; -+ } -+ dev_kfree_skb_any(skb); -+ } -+ -+ ch_rx->dma.desc = curr_desc; -+ if (running) { -+ napi_enable(&ch_rx->napi); -+ ltq_dma_open(&ch_rx->dma); -+ ltq_dma_enable_irq(&ch_rx->dma); -+ } -+ -+ return ret; -+} -+ - static const struct net_device_ops xrx200_netdev_ops = { - .ndo_open = xrx200_open, - .ndo_stop = xrx200_close, - .ndo_start_xmit = xrx200_start_xmit, -+ .ndo_change_mtu = xrx200_change_mtu, - .ndo_set_mac_address = eth_mac_addr, - .ndo_validate_addr = eth_validate_addr, - }; -@@ -454,7 +504,7 @@ static int xrx200_probe(struct platform_ - net_dev->netdev_ops = &xrx200_netdev_ops; - SET_NETDEV_DEV(net_dev, dev); - net_dev->min_mtu = ETH_ZLEN; -- net_dev->max_mtu = XRX200_DMA_DATA_LEN; -+ net_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN; - - /* load the memory ranges */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/lantiq/patches-5.10/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch b/target/linux/lantiq/patches-5.10/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch deleted file mode 100644 index 77c0eb6354..0000000000 --- a/target/linux/lantiq/patches-5.10/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 1488fc204568f707fe2a42a913788c00a95af30e Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Fri, 17 Dec 2021 01:07:40 +0100 -Subject: [PATCH] net: lantiq_xrx200: increase buffer reservation - -If the user sets a lower mtu on the CPU port than on the switch, -then DMA inserts a few more bytes into the buffer than expected. -In the worst case, it may exceed the size of the buffer. The -experiments showed that the buffer should be a multiple of the -burst length value. This patch rounds the length of the rx buffer -upwards and fixes this bug. The reservation of FCS space in the -buffer has been removed as PMAC strips the FCS. - -Fixes: 998ac358019e ("net: lantiq: add support for jumbo frames") -Reported-by: Thomas Nixon -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/lantiq_xrx200.c | 34 ++++++++++++++++++++-------- - 1 file changed, 24 insertions(+), 10 deletions(-) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -70,6 +70,8 @@ struct xrx200_priv { - struct xrx200_chan chan_tx; - struct xrx200_chan chan_rx; - -+ u16 rx_buf_size; -+ - struct net_device *net_dev; - struct device *dev; - -@@ -96,6 +98,16 @@ static void xrx200_pmac_mask(struct xrx2 - xrx200_pmac_w32(priv, val, offset); - } - -+static int xrx200_max_frame_len(int mtu) -+{ -+ return VLAN_ETH_HLEN + mtu; -+} -+ -+static int xrx200_buffer_size(int mtu) -+{ -+ return round_up(xrx200_max_frame_len(mtu), 4 * XRX200_DMA_BURST_LEN); -+} -+ - /* drop all the packets from the DMA ring */ - static void xrx200_flush_dma(struct xrx200_chan *ch) - { -@@ -108,8 +120,7 @@ static void xrx200_flush_dma(struct xrx2 - break; - - desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | -- (ch->priv->net_dev->mtu + VLAN_ETH_HLEN + -- ETH_FCS_LEN); -+ ch->priv->rx_buf_size; - ch->dma.desc++; - ch->dma.desc %= LTQ_DESC_NUM; - } -@@ -157,21 +168,21 @@ static int xrx200_close(struct net_devic - - static int xrx200_alloc_skb(struct xrx200_chan *ch) - { -- int len = ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; - struct sk_buff *skb = ch->skb[ch->dma.desc]; -+ struct xrx200_priv *priv = ch->priv; - dma_addr_t mapping; - int ret = 0; - -- ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev, -- len); -+ ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(priv->net_dev, -+ priv->rx_buf_size); - if (!ch->skb[ch->dma.desc]) { - ret = -ENOMEM; - goto skip; - } - -- mapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data, -- len, DMA_FROM_DEVICE); -- if (unlikely(dma_mapping_error(ch->priv->dev, mapping))) { -+ mapping = dma_map_single(priv->dev, ch->skb[ch->dma.desc]->data, -+ priv->rx_buf_size, DMA_FROM_DEVICE); -+ if (unlikely(dma_mapping_error(priv->dev, mapping))) { - dev_kfree_skb_any(ch->skb[ch->dma.desc]); - ch->skb[ch->dma.desc] = skb; - ret = -ENOMEM; -@@ -183,7 +194,7 @@ static int xrx200_alloc_skb(struct xrx20 - wmb(); - skip: - ch->dma.desc_base[ch->dma.desc].ctl = -- LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | len; -+ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | priv->rx_buf_size; - - return ret; - } -@@ -355,6 +366,7 @@ xrx200_change_mtu(struct net_device *net - int ret = 0; - - net_dev->mtu = new_mtu; -+ priv->rx_buf_size = xrx200_buffer_size(new_mtu); - - if (new_mtu <= old_mtu) - return ret; -@@ -374,6 +386,7 @@ xrx200_change_mtu(struct net_device *net - ret = xrx200_alloc_skb(ch_rx); - if (ret) { - net_dev->mtu = old_mtu; -+ priv->rx_buf_size = xrx200_buffer_size(old_mtu); - break; - } - dev_kfree_skb_any(skb); -@@ -504,7 +517,8 @@ static int xrx200_probe(struct platform_ - net_dev->netdev_ops = &xrx200_netdev_ops; - SET_NETDEV_DEV(net_dev, dev); - net_dev->min_mtu = ETH_ZLEN; -- net_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN; -+ net_dev->max_mtu = XRX200_DMA_DATA_LEN - xrx200_max_frame_len(0); -+ priv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN); - - /* load the memory ranges */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/lantiq/patches-5.10/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch b/target/linux/lantiq/patches-5.10/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch deleted file mode 100644 index f2c36952fc..0000000000 --- a/target/linux/lantiq/patches-5.10/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch +++ /dev/null @@ -1,104 +0,0 @@ -From c3e6b2c35b34214c58c1e90d65dab5f5393608e7 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Mon, 3 Jan 2022 20:43:16 +0100 -Subject: [PATCH] net: lantiq_xrx200: add ingress SG DMA support - -This patch adds support for scatter gather DMA. DMA in PMAC splits -the packet into several buffers when the MTU on the CPU port is -less than the MTU of the switch. The first buffer starts at an -offset of NET_IP_ALIGN. In subsequent buffers, dma ignores the -offset. Thanks to this patch, the user can still connect to the -device in such a situation. For normal configurations, the patch -has no effect on performance. - -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/lantiq_xrx200.c | 47 +++++++++++++++++++++++----- - 1 file changed, 40 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -26,6 +26,9 @@ - #define XRX200_DMA_RX 0 - #define XRX200_DMA_TX 1 - -+#define XRX200_DMA_PACKET_COMPLETE 0 -+#define XRX200_DMA_PACKET_IN_PROGRESS 1 -+ - /* cpu port mac */ - #define PMAC_RX_IPG 0x0024 - #define PMAC_RX_IPG_MASK 0xf -@@ -61,6 +64,9 @@ struct xrx200_chan { - struct ltq_dma_channel dma; - struct sk_buff *skb[LTQ_DESC_NUM]; - -+ struct sk_buff *skb_head; -+ struct sk_buff *skb_tail; -+ - struct xrx200_priv *priv; - }; - -@@ -204,7 +210,8 @@ static int xrx200_hw_receive(struct xrx2 - struct xrx200_priv *priv = ch->priv; - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; - struct sk_buff *skb = ch->skb[ch->dma.desc]; -- int len = (desc->ctl & LTQ_DMA_SIZE_MASK); -+ u32 ctl = desc->ctl; -+ int len = (ctl & LTQ_DMA_SIZE_MASK); - struct net_device *net_dev = priv->net_dev; - int ret; - -@@ -220,12 +227,36 @@ static int xrx200_hw_receive(struct xrx2 - } - - skb_put(skb, len); -- skb->protocol = eth_type_trans(skb, net_dev); -- netif_receive_skb(skb); -- net_dev->stats.rx_packets++; -- net_dev->stats.rx_bytes += len; - -- return 0; -+ /* add buffers to skb via skb->frag_list */ -+ if (ctl & LTQ_DMA_SOP) { -+ ch->skb_head = skb; -+ ch->skb_tail = skb; -+ } else if (ch->skb_head) { -+ if (ch->skb_head == ch->skb_tail) -+ skb_shinfo(ch->skb_tail)->frag_list = skb; -+ else -+ ch->skb_tail->next = skb; -+ ch->skb_tail = skb; -+ skb_reserve(ch->skb_tail, -NET_IP_ALIGN); -+ ch->skb_head->len += skb->len; -+ ch->skb_head->data_len += skb->len; -+ ch->skb_head->truesize += skb->truesize; -+ } -+ -+ if (ctl & LTQ_DMA_EOP) { -+ ch->skb_head->protocol = eth_type_trans(ch->skb_head, net_dev); -+ netif_receive_skb(ch->skb_head); -+ net_dev->stats.rx_packets++; -+ net_dev->stats.rx_bytes += ch->skb_head->len; -+ ch->skb_head = NULL; -+ ch->skb_tail = NULL; -+ ret = XRX200_DMA_PACKET_COMPLETE; -+ } else { -+ ret = XRX200_DMA_PACKET_IN_PROGRESS; -+ } -+ -+ return ret; - } - - static int xrx200_poll_rx(struct napi_struct *napi, int budget) -@@ -240,7 +271,9 @@ static int xrx200_poll_rx(struct napi_st - - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { - ret = xrx200_hw_receive(ch); -- if (ret) -+ if (ret == XRX200_DMA_PACKET_IN_PROGRESS) -+ continue; -+ if (ret != XRX200_DMA_PACKET_COMPLETE) - return ret; - rx++; - } else { diff --git a/target/linux/lantiq/patches-5.10/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch b/target/linux/lantiq/patches-5.10/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch deleted file mode 100644 index a69f682c03..0000000000 --- a/target/linux/lantiq/patches-5.10/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch +++ /dev/null @@ -1,275 +0,0 @@ -From a09d042b086202735c4ed64573cdd79933020001 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Mon, 22 Mar 2021 21:37:15 +0100 -Subject: [PATCH] net: dsa: lantiq: allow to use all GPHYs on xRX300 and xRX330 - -This patch allows to use all PHYs on GRX300 and GRX330. The ARX300 -has 3 and the GRX330 has 4 integrated PHYs connected to different -ports compared to VRX200. Each integrated PHY can work as single -Gigabit Ethernet PHY (GMII) or as double Fast Ethernet PHY (MII). - -Allowed port configurations: - -xRX200: -GMAC0: RGMII, MII, REVMII or RMII port -GMAC1: RGMII, MII, REVMII or RMII port -GMAC2: GPHY0 (GMII) -GMAC3: GPHY0 (MII) -GMAC4: GPHY1 (GMII) -GMAC5: GPHY1 (MII) or RGMII port - -xRX300: -GMAC0: RGMII port -GMAC1: GPHY2 (GMII) -GMAC2: GPHY0 (GMII) -GMAC3: GPHY0 (MII) -GMAC4: GPHY1 (GMII) -GMAC5: GPHY1 (MII) or RGMII port - -xRX330: -GMAC0: RGMII, GMII or RMII port -GMAC1: GPHY2 (GMII) -GMAC2: GPHY0 (GMII) -GMAC3: GPHY0 (MII) or GPHY3 (GMII) -GMAC4: GPHY1 (GMII) -GMAC5: GPHY1 (MII), RGMII or RMII port - -Tested on D-Link DWR966 (xRX330) with OpenWRT. - -Signed-off-by: Aleksander Jan Bajkowski -Acked-by: Hauke Mehrtens -Signed-off-by: David S. Miller ---- - drivers/net/dsa/lantiq_gswip.c | 142 ++++++++++++++++++++++++++------- - 1 file changed, 113 insertions(+), 29 deletions(-) - ---- a/drivers/net/dsa/lantiq_gswip.c -+++ b/drivers/net/dsa/lantiq_gswip.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0 - /* -- * Lantiq / Intel GSWIP switch driver for VRX200 SoCs -+ * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs - * - * Copyright (C) 2010 Lantiq Deutschland - * Copyright (C) 2012 John Crispin -@@ -104,6 +104,7 @@ - #define GSWIP_MII_CFG_MODE_RMIIP 0x2 - #define GSWIP_MII_CFG_MODE_RMIIM 0x3 - #define GSWIP_MII_CFG_MODE_RGMII 0x4 -+#define GSWIP_MII_CFG_MODE_GMII 0x9 - #define GSWIP_MII_CFG_MODE_MASK 0xf - #define GSWIP_MII_CFG_RATE_M2P5 0x00 - #define GSWIP_MII_CFG_RATE_M25 0x10 -@@ -241,6 +242,7 @@ - struct gswip_hw_info { - int max_ports; - int cpu_port; -+ const struct dsa_switch_ops *ops; - }; - - struct xway_gphy_match_data { -@@ -1438,12 +1440,42 @@ static int gswip_port_fdb_dump(struct ds - return 0; - } - --static void gswip_phylink_validate(struct dsa_switch *ds, int port, -- unsigned long *supported, -- struct phylink_link_state *state) -+static void gswip_phylink_set_capab(unsigned long *supported, -+ struct phylink_link_state *state) - { - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - -+ /* Allow all the expected bits */ -+ phylink_set(mask, Autoneg); -+ phylink_set_port_modes(mask); -+ phylink_set(mask, Pause); -+ phylink_set(mask, Asym_Pause); -+ -+ /* With the exclusion of MII, Reverse MII and Reduced MII, we -+ * support Gigabit, including Half duplex -+ */ -+ if (state->interface != PHY_INTERFACE_MODE_MII && -+ state->interface != PHY_INTERFACE_MODE_REVMII && -+ state->interface != PHY_INTERFACE_MODE_RMII) { -+ phylink_set(mask, 1000baseT_Full); -+ phylink_set(mask, 1000baseT_Half); -+ } -+ -+ phylink_set(mask, 10baseT_Half); -+ phylink_set(mask, 10baseT_Full); -+ phylink_set(mask, 100baseT_Half); -+ phylink_set(mask, 100baseT_Full); -+ -+ bitmap_and(supported, supported, mask, -+ __ETHTOOL_LINK_MODE_MASK_NBITS); -+ bitmap_and(state->advertising, state->advertising, mask, -+ __ETHTOOL_LINK_MODE_MASK_NBITS); -+} -+ -+static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, -+ unsigned long *supported, -+ struct phylink_link_state *state) -+{ - switch (port) { - case 0: - case 1: -@@ -1470,38 +1502,54 @@ static void gswip_phylink_validate(struc - return; - } - -- /* Allow all the expected bits */ -- phylink_set(mask, Autoneg); -- phylink_set_port_modes(mask); -- phylink_set(mask, Pause); -- phylink_set(mask, Asym_Pause); -+ gswip_phylink_set_capab(supported, state); - -- /* With the exclusion of MII, Reverse MII and Reduced MII, we -- * support Gigabit, including Half duplex -- */ -- if (state->interface != PHY_INTERFACE_MODE_MII && -- state->interface != PHY_INTERFACE_MODE_REVMII && -- state->interface != PHY_INTERFACE_MODE_RMII) { -- phylink_set(mask, 1000baseT_Full); -- phylink_set(mask, 1000baseT_Half); -+ return; -+ -+unsupported: -+ bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); -+ dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", -+ phy_modes(state->interface), port); -+} -+ -+static void gswip_xrx300_phylink_validate(struct dsa_switch *ds, int port, -+ unsigned long *supported, -+ struct phylink_link_state *state) -+{ -+ switch (port) { -+ case 0: -+ if (!phy_interface_mode_is_rgmii(state->interface) && -+ state->interface != PHY_INTERFACE_MODE_GMII && -+ state->interface != PHY_INTERFACE_MODE_RMII) -+ goto unsupported; -+ break; -+ case 1: -+ case 2: -+ case 3: -+ case 4: -+ if (state->interface != PHY_INTERFACE_MODE_INTERNAL) -+ goto unsupported; -+ break; -+ case 5: -+ if (!phy_interface_mode_is_rgmii(state->interface) && -+ state->interface != PHY_INTERFACE_MODE_INTERNAL && -+ state->interface != PHY_INTERFACE_MODE_RMII) -+ goto unsupported; -+ break; -+ default: -+ bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); -+ dev_err(ds->dev, "Unsupported port: %i\n", port); -+ return; - } - -- phylink_set(mask, 10baseT_Half); -- phylink_set(mask, 10baseT_Full); -- phylink_set(mask, 100baseT_Half); -- phylink_set(mask, 100baseT_Full); -+ gswip_phylink_set_capab(supported, state); - -- bitmap_and(supported, supported, mask, -- __ETHTOOL_LINK_MODE_MASK_NBITS); -- bitmap_and(state->advertising, state->advertising, mask, -- __ETHTOOL_LINK_MODE_MASK_NBITS); - return; - - unsupported: - bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); - dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", - phy_modes(state->interface), port); -- return; - } - - static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) -@@ -1636,6 +1684,9 @@ static void gswip_phylink_mac_config(str - case PHY_INTERFACE_MODE_RGMII_TXID: - miicfg |= GSWIP_MII_CFG_MODE_RGMII; - break; -+ case PHY_INTERFACE_MODE_GMII: -+ miicfg |= GSWIP_MII_CFG_MODE_GMII; -+ break; - default: - dev_err(ds->dev, - "Unsupported interface: %d\n", state->interface); -@@ -1762,7 +1813,7 @@ static int gswip_get_sset_count(struct d - return ARRAY_SIZE(gswip_rmon_cnt); - } - --static const struct dsa_switch_ops gswip_switch_ops = { -+static const struct dsa_switch_ops gswip_xrx200_switch_ops = { - .get_tag_protocol = gswip_get_tag_protocol, - .setup = gswip_setup, - .port_enable = gswip_port_enable, -@@ -1778,7 +1829,31 @@ static const struct dsa_switch_ops gswip - .port_fdb_add = gswip_port_fdb_add, - .port_fdb_del = gswip_port_fdb_del, - .port_fdb_dump = gswip_port_fdb_dump, -- .phylink_validate = gswip_phylink_validate, -+ .phylink_validate = gswip_xrx200_phylink_validate, -+ .phylink_mac_config = gswip_phylink_mac_config, -+ .phylink_mac_link_down = gswip_phylink_mac_link_down, -+ .phylink_mac_link_up = gswip_phylink_mac_link_up, -+ .get_strings = gswip_get_strings, -+ .get_ethtool_stats = gswip_get_ethtool_stats, -+ .get_sset_count = gswip_get_sset_count, -+}; -+ -+static const struct dsa_switch_ops gswip_xrx300_switch_ops = { -+ .get_tag_protocol = gswip_get_tag_protocol, -+ .setup = gswip_setup, -+ .port_enable = gswip_port_enable, -+ .port_disable = gswip_port_disable, -+ .port_bridge_join = gswip_port_bridge_join, -+ .port_bridge_leave = gswip_port_bridge_leave, -+ .port_fast_age = gswip_port_fast_age, -+ .port_vlan_filtering = gswip_port_vlan_filtering, -+ .port_vlan_add = gswip_port_vlan_add, -+ .port_vlan_del = gswip_port_vlan_del, -+ .port_stp_state_set = gswip_port_stp_state_set, -+ .port_fdb_add = gswip_port_fdb_add, -+ .port_fdb_del = gswip_port_fdb_del, -+ .port_fdb_dump = gswip_port_fdb_dump, -+ .phylink_validate = gswip_xrx300_phylink_validate, - .phylink_mac_config = gswip_phylink_mac_config, - .phylink_mac_link_down = gswip_phylink_mac_link_down, - .phylink_mac_link_up = gswip_phylink_mac_link_up, -@@ -2042,7 +2117,7 @@ static int gswip_probe(struct platform_d - priv->ds->dev = dev; - priv->ds->num_ports = priv->hw_info->max_ports; - priv->ds->priv = priv; -- priv->ds->ops = &gswip_switch_ops; -+ priv->ds->ops = priv->hw_info->ops; - priv->dev = dev; - version = gswip_switch_r(priv, GSWIP_VERSION); - -@@ -2126,10 +2201,19 @@ static int gswip_remove(struct platform_ - static const struct gswip_hw_info gswip_xrx200 = { - .max_ports = 7, - .cpu_port = 6, -+ .ops = &gswip_xrx200_switch_ops, -+}; -+ -+static const struct gswip_hw_info gswip_xrx300 = { -+ .max_ports = 7, -+ .cpu_port = 6, -+ .ops = &gswip_xrx300_switch_ops, - }; - - static const struct of_device_id gswip_of_match[] = { - { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, -+ { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, -+ { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, - {}, - }; - MODULE_DEVICE_TABLE(of, gswip_of_match); diff --git a/target/linux/lantiq/patches-5.10/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch b/target/linux/lantiq/patches-5.10/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch deleted file mode 100644 index 49a19bebee..0000000000 --- a/target/linux/lantiq/patches-5.10/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch +++ /dev/null @@ -1,127 +0,0 @@ -From c40bb4fedcd6b8b6a714da5dd466eb88ed2652d1 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Wed, 9 Mar 2022 00:04:57 +0100 -Subject: net: dsa: lantiq_gswip: enable jumbo frames on GSWIP - -This enables non-standard MTUs on a per-port basis, with the overall -frame size set based on the CPU port. - -When the MTU is not changed, this should have no effect. - -Long packets crash the switch with MTUs of greater than 2526, so the -maximum is limited for now. Medium packets are sometimes dropped (e.g. -TCP over 2477, UDP over 2516-2519, ICMP over 2526), Hence an MTU value -of 2400 seems safe. - -Signed-off-by: Thomas Nixon -Signed-off-by: Aleksander Jan Bajkowski -Link: https://lore.kernel.org/r/20220308230457.1599237-1-olek2@wp.pl -Signed-off-by: Jakub Kicinski ---- - drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++++++++++++++++++++++++---- - 1 file changed, 49 insertions(+), 4 deletions(-) - ---- a/drivers/net/dsa/lantiq_gswip.c -+++ b/drivers/net/dsa/lantiq_gswip.c -@@ -213,6 +213,7 @@ - #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 - #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 - #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) -+#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */ - #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ - - /* Ethernet Switch Fetch DMA Port Control Register */ -@@ -239,6 +240,15 @@ - - #define XRX200_GPHY_FW_ALIGN (16 * 1024) - -+/* Maximum packet size supported by the switch. In theory this should be 10240, -+ * but long packets currently cause lock-ups with an MTU of over 2526. Medium -+ * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP -+ * over 2526), hence an MTU value of 2400 seems safe. This issue only affects -+ * packet reception. This is probably caused by the PPA engine, which is on the -+ * RX part of the device. Packet transmission works properly up to 10240. -+ */ -+#define GSWIP_MAX_PACKET_LENGTH 2400 -+ - struct gswip_hw_info { - int max_ports; - int cpu_port; -@@ -858,10 +868,6 @@ static int gswip_setup(struct dsa_switch - gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, - GSWIP_PCE_PCTRL_0p(cpu_port)); - -- gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, -- GSWIP_MAC_CTRL_2p(cpu_port)); -- gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN, -- GSWIP_MAC_FLEN); - gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, - GSWIP_BM_QUEUE_GCTRL); - -@@ -878,6 +884,8 @@ static int gswip_setup(struct dsa_switch - return err; - } - -+ ds->mtu_enforcement_ingress = true; -+ - gswip_port_enable(ds, cpu_port, NULL); - return 0; - } -@@ -1472,6 +1480,39 @@ static void gswip_phylink_set_capab(unsi - __ETHTOOL_LINK_MODE_MASK_NBITS); - } - -+static int gswip_port_max_mtu(struct dsa_switch *ds, int port) -+{ -+ /* Includes 8 bytes for special header. */ -+ return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN; -+} -+ -+static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) -+{ -+ struct gswip_priv *priv = ds->priv; -+ int cpu_port = priv->hw_info->cpu_port; -+ -+ /* CPU port always has maximum mtu of user ports, so use it to set -+ * switch frame size, including 8 byte special header. -+ */ -+ if (port == cpu_port) { -+ new_mtu += 8; -+ gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, -+ GSWIP_MAC_FLEN); -+ } -+ -+ /* Enable MLEN for ports with non-standard MTUs, including the special -+ * header on the CPU port added above. -+ */ -+ if (new_mtu != ETH_DATA_LEN) -+ gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, -+ GSWIP_MAC_CTRL_2p(port)); -+ else -+ gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0, -+ GSWIP_MAC_CTRL_2p(port)); -+ -+ return 0; -+} -+ - static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port, - unsigned long *supported, - struct phylink_link_state *state) -@@ -1829,6 +1870,8 @@ static const struct dsa_switch_ops gswip - .port_fdb_add = gswip_port_fdb_add, - .port_fdb_del = gswip_port_fdb_del, - .port_fdb_dump = gswip_port_fdb_dump, -+ .port_change_mtu = gswip_port_change_mtu, -+ .port_max_mtu = gswip_port_max_mtu, - .phylink_validate = gswip_xrx200_phylink_validate, - .phylink_mac_config = gswip_phylink_mac_config, - .phylink_mac_link_down = gswip_phylink_mac_link_down, -@@ -1853,6 +1896,8 @@ static const struct dsa_switch_ops gswip - .port_fdb_add = gswip_port_fdb_add, - .port_fdb_del = gswip_port_fdb_del, - .port_fdb_dump = gswip_port_fdb_dump, -+ .port_change_mtu = gswip_port_change_mtu, -+ .port_max_mtu = gswip_port_max_mtu, - .phylink_validate = gswip_xrx300_phylink_validate, - .phylink_mac_config = gswip_phylink_mac_config, - .phylink_mac_link_down = gswip_phylink_mac_link_down, diff --git a/target/linux/lantiq/patches-5.10/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch b/target/linux/lantiq/patches-5.10/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch deleted file mode 100644 index 4fb7d0767b..0000000000 --- a/target/linux/lantiq/patches-5.10/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch +++ /dev/null @@ -1,126 +0,0 @@ -From 14d4e308e0aa0b78dc7a059716861a4380de3535 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Tue, 14 Sep 2021 23:21:02 +0200 -Subject: [PATCH 5/5] net: lantiq: configure the burst length in ethernet - drivers - -Configure the burst length in Ethernet drivers. This improves -Ethernet performance by 58%. According to the vendor BSP, -8W burst length is supported by ar9 and newer SoCs. - -The NAT benchmark results on xRX200 (Down/Up): -* 2W: 330 Mb/s -* 4W: 432 Mb/s 372 Mb/s -* 8W: 520 Mb/s 389 Mb/s - -Tested on xRX200 and xRX330. - -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/lantiq_etop.c | 21 ++++++++++++++++++--- - drivers/net/ethernet/lantiq_xrx200.c | 21 ++++++++++++++++++--- - 2 files changed, 36 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -148,6 +148,9 @@ struct ltq_etop_priv { - struct ltq_etop_chan txch; - struct ltq_etop_chan rxch; - -+ int tx_burst_len; -+ int rx_burst_len; -+ - int tx_irq; - int rx_irq; - -@@ -399,7 +402,7 @@ ltq_etop_dma_init(struct net_device *dev - int rx = priv->rx_irq - LTQ_DMA_ETOP; - int err; - -- ltq_dma_init_port(DMA_PORT_ETOP); -+ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); - - priv->txch.dma.nr = tx; - priv->txch.dma.dev = &priv->pdev->dev; -@@ -676,8 +679,8 @@ ltq_etop_tx(struct sk_buff *skb, struct - return NETDEV_TX_BUSY; - } - -- /* dma needs to start on a 16 byte aligned address */ -- byte_offset = CPHYSADDR(skb->data) % 16; -+ /* dma needs to start on a burst length value aligned address */ -+ byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4); - priv->txch.skb[priv->txch.dma.desc] = skb; - - netif_trans_update(dev); -@@ -925,6 +928,18 @@ static int ltq_etop_probe(struct platfor - spin_lock_init(&priv->lock); - SET_NETDEV_DEV(dev, &pdev->dev); - -+ err = device_property_read_u32(&pdev->dev, "lantiq,tx-burst-length", &priv->tx_burst_len); -+ if (err < 0) { -+ dev_err(&pdev->dev, "unable to read tx-burst-length property\n"); -+ return err; -+ } -+ -+ err = device_property_read_u32(&pdev->dev, "lantiq,rx-burst-length", &priv->rx_burst_len); -+ if (err < 0) { -+ dev_err(&pdev->dev, "unable to read rx-burst-length property\n"); -+ return err; -+ } -+ - netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); - netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); - priv->txch.netdev = dev; ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -81,6 +81,9 @@ struct xrx200_priv { - struct net_device *net_dev; - struct device *dev; - -+ int tx_burst_len; -+ int rx_burst_len; -+ - __iomem void *pmac_reg; - }; - -@@ -363,8 +366,8 @@ static netdev_tx_t xrx200_start_xmit(str - if (unlikely(dma_mapping_error(priv->dev, mapping))) - goto err_drop; - -- /* dma needs to start on a 16 byte aligned address */ -- byte_offset = mapping % 16; -+ /* dma needs to start on a burst length value aligned address */ -+ byte_offset = mapping % (priv->tx_burst_len * 4); - - desc->addr = mapping - byte_offset; - /* Make sure the address is written before we give it to HW */ -@@ -465,7 +468,7 @@ static int xrx200_dma_init(struct xrx200 - int ret = 0; - int i; - -- ltq_dma_init_port(DMA_PORT_ETOP); -+ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); - - ch_rx->dma.nr = XRX200_DMA_RX; - ch_rx->dma.dev = priv->dev; -@@ -584,6 +587,18 @@ static int xrx200_probe(struct platform_ - if (err) - eth_hw_addr_random(net_dev); - -+ err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len); -+ if (err < 0) { -+ dev_err(dev, "unable to read tx-burst-length property\n"); -+ return err; -+ } -+ -+ err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len); -+ if (err < 0) { -+ dev_err(dev, "unable to read rx-burst-length property\n"); -+ return err; -+ } -+ - /* bring up the dma engine and IP core */ - err = xrx200_dma_init(priv); - if (err) diff --git a/target/linux/lantiq/patches-5.10/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch b/target/linux/lantiq/patches-5.10/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch deleted file mode 100644 index 7448af8c26..0000000000 --- a/target/linux/lantiq/patches-5.10/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch +++ /dev/null @@ -1,73 +0,0 @@ -From 7e553c44f09a8f536090904c6db5b8c9dbafa03b Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Tue, 26 Oct 2021 22:59:01 +0200 -Subject: [PATCH] net: lantiq_xrx200: Hardcode the burst length value - -All SoCs with this IP core support 8 burst length. Hauke -suggested to hardcode this value and simplify the driver. - -Link: https://lkml.org/lkml/2021/9/14/1533 -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/lantiq_xrx200.c | 21 ++++----------------- - 1 file changed, 4 insertions(+), 17 deletions(-) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -25,6 +25,7 @@ - #define XRX200_DMA_DATA_LEN (SZ_64K - 1) - #define XRX200_DMA_RX 0 - #define XRX200_DMA_TX 1 -+#define XRX200_DMA_BURST_LEN 8 - - #define XRX200_DMA_PACKET_COMPLETE 0 - #define XRX200_DMA_PACKET_IN_PROGRESS 1 -@@ -81,9 +82,6 @@ struct xrx200_priv { - struct net_device *net_dev; - struct device *dev; - -- int tx_burst_len; -- int rx_burst_len; -- - __iomem void *pmac_reg; - }; - -@@ -367,7 +365,7 @@ static netdev_tx_t xrx200_start_xmit(str - goto err_drop; - - /* dma needs to start on a burst length value aligned address */ -- byte_offset = mapping % (priv->tx_burst_len * 4); -+ byte_offset = mapping % (XRX200_DMA_BURST_LEN * 4); - - desc->addr = mapping - byte_offset; - /* Make sure the address is written before we give it to HW */ -@@ -468,7 +466,8 @@ static int xrx200_dma_init(struct xrx200 - int ret = 0; - int i; - -- ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); -+ ltq_dma_init_port(DMA_PORT_ETOP, XRX200_DMA_BURST_LEN, -+ XRX200_DMA_BURST_LEN); - - ch_rx->dma.nr = XRX200_DMA_RX; - ch_rx->dma.dev = priv->dev; -@@ -587,18 +586,6 @@ static int xrx200_probe(struct platform_ - if (err) - eth_hw_addr_random(net_dev); - -- err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len); -- if (err < 0) { -- dev_err(dev, "unable to read tx-burst-length property\n"); -- return err; -- } -- -- err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len); -- if (err < 0) { -- dev_err(dev, "unable to read rx-burst-length property\n"); -- return err; -- } -- - /* bring up the dma engine and IP core */ - err = xrx200_dma_init(priv); - if (err) diff --git a/target/linux/lantiq/patches-5.10/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch b/target/linux/lantiq/patches-5.10/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch deleted file mode 100644 index 06f4bc2eee..0000000000 --- a/target/linux/lantiq/patches-5.10/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 68eabc348148ae051631e8dab13c3b1a85c82896 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Tue, 9 Nov 2021 23:23:54 +0100 -Subject: [PATCH] net: ethernet: lantiq_etop: Fix compilation error - -This fixes the error detected when compiling the driver. - -Fixes: 14d4e308e0aa ("net: lantiq: configure the burst length in ethernet drivers") -Reported-by: kernel test robot -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/lantiq_etop.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -402,7 +402,7 @@ ltq_etop_dma_init(struct net_device *dev - int rx = priv->rx_irq - LTQ_DMA_ETOP; - int err; - -- ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); -+ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len); - - priv->txch.dma.nr = tx; - priv->txch.dma.dev = &priv->pdev->dev; diff --git a/target/linux/lantiq/patches-5.10/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch b/target/linux/lantiq/patches-5.10/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch deleted file mode 100644 index 37ed1d4f31..0000000000 --- a/target/linux/lantiq/patches-5.10/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 5112e9234bbb89f8dd15c983206bd9107b8436d5 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Tue, 4 Jan 2022 16:11:42 +0100 -Subject: [PATCH 713/715] MIPS: lantiq: dma: increase descritor count - -NAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500): - - Down Up -Before 539 Mbps 599 Mbps -After 545 Mbps 625 Mbps - -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: Jakub Kicinski ---- - arch/mips/include/asm/mach-lantiq/xway/xway_dma.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h -@@ -8,7 +8,7 @@ - #define LTQ_DMA_H__ - - #define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */ --#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */ -+#define LTQ_DESC_NUM 0xC0 /* 192 descriptors / channel */ - - #define LTQ_DMA_OWN BIT(31) /* owner bit */ - #define LTQ_DMA_C BIT(30) /* complete bit */ diff --git a/target/linux/lantiq/patches-5.10/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch b/target/linux/lantiq/patches-5.10/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch deleted file mode 100644 index 1fa49f406e..0000000000 --- a/target/linux/lantiq/patches-5.10/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 768818d772d5d4ddc0c7eb2e62848929270ab7a3 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Tue, 4 Jan 2022 16:11:43 +0100 -Subject: [PATCH 714/715] net: lantiq_xrx200: increase napi poll weigth - -NAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500): - - Down Up -Before 545 Mbps 625 Mbps -After 577 Mbps 648 Mbps - -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/lantiq_xrx200.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -606,8 +606,10 @@ static int xrx200_probe(struct platform_ - PMAC_HD_CTL); - - /* setup NAPI */ -- netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32); -- netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32); -+ netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, -+ NAPI_POLL_WEIGHT); -+ netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, -+ NAPI_POLL_WEIGHT); - - platform_set_drvdata(pdev, priv); - diff --git a/target/linux/lantiq/patches-5.10/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch b/target/linux/lantiq/patches-5.10/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch deleted file mode 100644 index b2b014832c..0000000000 --- a/target/linux/lantiq/patches-5.10/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch +++ /dev/null @@ -1,206 +0,0 @@ -From e015593573b3e3f74bd8a63c05fa92902194a354 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Tue, 4 Jan 2022 16:11:44 +0100 -Subject: [PATCH 715/715] net: lantiq_xrx200: convert to build_skb - -We can increase the efficiency of rx path by using buffers to receive -packets then build SKBs around them just before passing into the network -stack. In contrast, preallocating SKBs too early reduces CPU cache -efficiency. - -NAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500): - - Down Up -Before 577 Mbps 648 Mbps -After 624 Mbps 695 Mbps - -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/lantiq_xrx200.c | 56 ++++++++++++++++++---------- - 1 file changed, 36 insertions(+), 20 deletions(-) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -63,7 +63,11 @@ struct xrx200_chan { - - struct napi_struct napi; - struct ltq_dma_channel dma; -- struct sk_buff *skb[LTQ_DESC_NUM]; -+ -+ union { -+ struct sk_buff *skb[LTQ_DESC_NUM]; -+ void *rx_buff[LTQ_DESC_NUM]; -+ }; - - struct sk_buff *skb_head; - struct sk_buff *skb_tail; -@@ -78,6 +82,7 @@ struct xrx200_priv { - struct xrx200_chan chan_rx; - - u16 rx_buf_size; -+ u16 rx_skb_size; - - struct net_device *net_dev; - struct device *dev; -@@ -115,6 +120,12 @@ static int xrx200_buffer_size(int mtu) - return round_up(xrx200_max_frame_len(mtu), 4 * XRX200_DMA_BURST_LEN); - } - -+static int xrx200_skb_size(u16 buf_size) -+{ -+ return SKB_DATA_ALIGN(buf_size + NET_SKB_PAD + NET_IP_ALIGN) + -+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); -+} -+ - /* drop all the packets from the DMA ring */ - static void xrx200_flush_dma(struct xrx200_chan *ch) - { -@@ -173,30 +184,29 @@ static int xrx200_close(struct net_devic - return 0; - } - --static int xrx200_alloc_skb(struct xrx200_chan *ch) -+static int xrx200_alloc_buf(struct xrx200_chan *ch, void *(*alloc)(unsigned int size)) - { -- struct sk_buff *skb = ch->skb[ch->dma.desc]; -+ void *buf = ch->rx_buff[ch->dma.desc]; - struct xrx200_priv *priv = ch->priv; - dma_addr_t mapping; - int ret = 0; - -- ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(priv->net_dev, -- priv->rx_buf_size); -- if (!ch->skb[ch->dma.desc]) { -+ ch->rx_buff[ch->dma.desc] = alloc(priv->rx_skb_size); -+ if (!ch->rx_buff[ch->dma.desc]) { - ret = -ENOMEM; - goto skip; - } - -- mapping = dma_map_single(priv->dev, ch->skb[ch->dma.desc]->data, -+ mapping = dma_map_single(priv->dev, ch->rx_buff[ch->dma.desc], - priv->rx_buf_size, DMA_FROM_DEVICE); - if (unlikely(dma_mapping_error(priv->dev, mapping))) { -- dev_kfree_skb_any(ch->skb[ch->dma.desc]); -- ch->skb[ch->dma.desc] = skb; -+ skb_free_frag(ch->rx_buff[ch->dma.desc]); -+ ch->rx_buff[ch->dma.desc] = buf; - ret = -ENOMEM; - goto skip; - } - -- ch->dma.desc_base[ch->dma.desc].addr = mapping; -+ ch->dma.desc_base[ch->dma.desc].addr = mapping + NET_SKB_PAD + NET_IP_ALIGN; - /* Make sure the address is written before we give it to HW */ - wmb(); - skip: -@@ -210,13 +220,14 @@ static int xrx200_hw_receive(struct xrx2 - { - struct xrx200_priv *priv = ch->priv; - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -- struct sk_buff *skb = ch->skb[ch->dma.desc]; -+ void *buf = ch->rx_buff[ch->dma.desc]; - u32 ctl = desc->ctl; - int len = (ctl & LTQ_DMA_SIZE_MASK); - struct net_device *net_dev = priv->net_dev; -+ struct sk_buff *skb; - int ret; - -- ret = xrx200_alloc_skb(ch); -+ ret = xrx200_alloc_buf(ch, napi_alloc_frag); - - ch->dma.desc++; - ch->dma.desc %= LTQ_DESC_NUM; -@@ -227,19 +238,21 @@ static int xrx200_hw_receive(struct xrx2 - return ret; - } - -+ skb = build_skb(buf, priv->rx_skb_size); -+ skb_reserve(skb, NET_SKB_PAD); - skb_put(skb, len); - - /* add buffers to skb via skb->frag_list */ - if (ctl & LTQ_DMA_SOP) { - ch->skb_head = skb; - ch->skb_tail = skb; -+ skb_reserve(skb, NET_IP_ALIGN); - } else if (ch->skb_head) { - if (ch->skb_head == ch->skb_tail) - skb_shinfo(ch->skb_tail)->frag_list = skb; - else - ch->skb_tail->next = skb; - ch->skb_tail = skb; -- skb_reserve(ch->skb_tail, -NET_IP_ALIGN); - ch->skb_head->len += skb->len; - ch->skb_head->data_len += skb->len; - ch->skb_head->truesize += skb->truesize; -@@ -395,12 +408,13 @@ xrx200_change_mtu(struct net_device *net - struct xrx200_chan *ch_rx = &priv->chan_rx; - int old_mtu = net_dev->mtu; - bool running = false; -- struct sk_buff *skb; -+ void *buff; - int curr_desc; - int ret = 0; - - net_dev->mtu = new_mtu; - priv->rx_buf_size = xrx200_buffer_size(new_mtu); -+ priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); - - if (new_mtu <= old_mtu) - return ret; -@@ -416,14 +430,15 @@ xrx200_change_mtu(struct net_device *net - - for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; - ch_rx->dma.desc++) { -- skb = ch_rx->skb[ch_rx->dma.desc]; -- ret = xrx200_alloc_skb(ch_rx); -+ buff = ch_rx->rx_buff[ch_rx->dma.desc]; -+ ret = xrx200_alloc_buf(ch_rx, netdev_alloc_frag); - if (ret) { - net_dev->mtu = old_mtu; - priv->rx_buf_size = xrx200_buffer_size(old_mtu); -+ priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); - break; - } -- dev_kfree_skb_any(skb); -+ skb_free_frag(buff); - } - - ch_rx->dma.desc = curr_desc; -@@ -476,7 +491,7 @@ static int xrx200_dma_init(struct xrx200 - ltq_dma_alloc_rx(&ch_rx->dma); - for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; - ch_rx->dma.desc++) { -- ret = xrx200_alloc_skb(ch_rx); -+ ret = xrx200_alloc_buf(ch_rx, netdev_alloc_frag); - if (ret) - goto rx_free; - } -@@ -511,7 +526,7 @@ rx_ring_free: - /* free the allocated RX ring */ - for (i = 0; i < LTQ_DESC_NUM; i++) { - if (priv->chan_rx.skb[i]) -- dev_kfree_skb_any(priv->chan_rx.skb[i]); -+ skb_free_frag(priv->chan_rx.rx_buff[i]); - } - - rx_free: -@@ -528,7 +543,7 @@ static void xrx200_hw_cleanup(struct xrx - - /* free the allocated RX ring */ - for (i = 0; i < LTQ_DESC_NUM; i++) -- dev_kfree_skb_any(priv->chan_rx.skb[i]); -+ skb_free_frag(priv->chan_rx.rx_buff[i]); - } - - static int xrx200_probe(struct platform_device *pdev) -@@ -554,6 +569,7 @@ static int xrx200_probe(struct platform_ - net_dev->min_mtu = ETH_ZLEN; - net_dev->max_mtu = XRX200_DMA_DATA_LEN - xrx200_max_frame_len(0); - priv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN); -+ priv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size); - - /* load the memory ranges */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/lantiq/patches-5.10/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch b/target/linux/lantiq/patches-5.10/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch deleted file mode 100644 index 090b7e3111..0000000000 --- a/target/linux/lantiq/patches-5.10/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch +++ /dev/null @@ -1,30 +0,0 @@ -From dd830aed23c6e07cd8e2a163742bf3d63c9add08 Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Sat, 5 Mar 2022 12:20:39 +0100 -Subject: net: lantiq_xrx200: fix use after free bug - -The skb->len field is read after the packet is sent to the network -stack. In the meantime, skb can be freed. This patch fixes this bug. - -Fixes: c3e6b2c35b34 ("net: lantiq_xrx200: add ingress SG DMA support") -Reported-by: Eric Dumazet -Signed-off-by: Aleksander Jan Bajkowski -Acked-by: Hauke Mehrtens -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/lantiq_xrx200.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -260,9 +260,9 @@ static int xrx200_hw_receive(struct xrx2 - - if (ctl & LTQ_DMA_EOP) { - ch->skb_head->protocol = eth_type_trans(ch->skb_head, net_dev); -- netif_receive_skb(ch->skb_head); - net_dev->stats.rx_packets++; - net_dev->stats.rx_bytes += ch->skb_head->len; -+ netif_receive_skb(ch->skb_head); - ch->skb_head = NULL; - ch->skb_tail = NULL; - ret = XRX200_DMA_PACKET_COMPLETE; diff --git a/target/linux/lantiq/patches-5.10/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch b/target/linux/lantiq/patches-5.10/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch deleted file mode 100644 index 9eaec58033..0000000000 --- a/target/linux/lantiq/patches-5.10/0717-v6.0-net-lantiq_xrx200-confirm-skb-is-allocated-before-us.patch +++ /dev/null @@ -1,33 +0,0 @@ -From c8b043702dc0894c07721c5b019096cebc8c798f Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Wed, 24 Aug 2022 23:54:06 +0200 -Subject: [PATCH] net: lantiq_xrx200: confirm skb is allocated before using - -xrx200_hw_receive() assumes build_skb() always works and goes straight -to skb_reserve(). However, build_skb() can fail under memory pressure. - -Add a check in case build_skb() failed to allocate and return NULL. - -Fixes: e015593573b3 ("net: lantiq_xrx200: convert to build_skb") -Reported-by: Eric Dumazet -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/lantiq_xrx200.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -239,6 +239,12 @@ static int xrx200_hw_receive(struct xrx2 - } - - skb = build_skb(buf, priv->rx_skb_size); -+ if (!skb) { -+ skb_free_frag(buf); -+ net_dev->stats.rx_dropped++; -+ return -ENOMEM; -+ } -+ - skb_reserve(skb, NET_SKB_PAD); - skb_put(skb, len); - diff --git a/target/linux/lantiq/patches-5.10/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch b/target/linux/lantiq/patches-5.10/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch deleted file mode 100644 index 929ae57ace..0000000000 --- a/target/linux/lantiq/patches-5.10/0718-v6.0-net-lantiq_xrx200-fix-lock-under-memory-pressure.patch +++ /dev/null @@ -1,33 +0,0 @@ -From c4b6e9341f930e4dd089231c0414758f5f1f9dbd Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Wed, 24 Aug 2022 23:54:07 +0200 -Subject: [PATCH] net: lantiq_xrx200: fix lock under memory pressure - -When the xrx200_hw_receive() function returns -ENOMEM, the NAPI poll -function immediately returns an error. -This is incorrect for two reasons: -* the function terminates without enabling interrupts or scheduling NAPI, -* the error code (-ENOMEM) is returned instead of the number of received -packets. - -After the first memory allocation failure occurs, packet reception is -locked due to disabled interrupts from DMA.. - -Fixes: fe1a56420cf2 ("net: lantiq: Add Lantiq / Intel VRX200 Ethernet driver") -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/lantiq_xrx200.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -294,7 +294,7 @@ static int xrx200_poll_rx(struct napi_st - if (ret == XRX200_DMA_PACKET_IN_PROGRESS) - continue; - if (ret != XRX200_DMA_PACKET_COMPLETE) -- return ret; -+ break; - rx++; - } else { - break; diff --git a/target/linux/lantiq/patches-5.10/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch b/target/linux/lantiq/patches-5.10/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch deleted file mode 100644 index 182da58ed9..0000000000 --- a/target/linux/lantiq/patches-5.10/0719-v6.0-net-lantiq_xrx200-restore-buffer-if-memory-allocatio.patch +++ /dev/null @@ -1,27 +0,0 @@ -From c9c3b1775f80fa21f5bff874027d2ccb10f5d90c Mon Sep 17 00:00:00 2001 -From: Aleksander Jan Bajkowski -Date: Wed, 24 Aug 2022 23:54:08 +0200 -Subject: [PATCH] net: lantiq_xrx200: restore buffer if memory allocation - failed - -In a situation where memory allocation fails, an invalid buffer address -is stored. When this descriptor is used again, the system panics in the -build_skb() function when accessing memory. - -Fixes: 7ea6cd16f159 ("lantiq: net: fix duplicated skb in rx descriptor ring") -Signed-off-by: Aleksander Jan Bajkowski -Signed-off-by: Jakub Kicinski ---- - drivers/net/ethernet/lantiq_xrx200.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/ethernet/lantiq_xrx200.c -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -193,6 +193,7 @@ static int xrx200_alloc_buf(struct xrx20 - - ch->rx_buff[ch->dma.desc] = alloc(priv->rx_skb_size); - if (!ch->rx_buff[ch->dma.desc]) { -+ ch->rx_buff[ch->dma.desc] = buf; - ret = -ENOMEM; - goto skip; - } diff --git a/target/linux/lantiq/xrx200/config-5.10 b/target/linux/lantiq/xrx200/config-5.10 deleted file mode 100644 index 4dfd55274a..0000000000 --- a/target/linux/lantiq/xrx200/config-5.10 +++ /dev/null @@ -1,93 +0,0 @@ -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin" -CONFIG_EXTRA_FIRMWARE_DIR="firmware" -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GRO_CELLS=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_ICPLUS_PHY=y -CONFIG_IFX_VPE_EXT=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y -CONFIG_INTEL_XWAY_PHY=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_XRX200=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MIPS_MT=y -# CONFIG_MIPS_MT_FPAFF is not set -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NR_CPU_NR_MAP=2 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MIPS_VPE_APSP_API=y -CONFIG_MIPS_VPE_APSP_API_MT=y -CONFIG_MIPS_VPE_LOADER=y -CONFIG_MIPS_VPE_LOADER_MT=y -CONFIG_MIPS_VPE_LOADER_TOM=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_MTD_NAND_XWAY=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_LANTIQ_GSWIP=y -CONFIG_NET_DSA_TAG_GSWIP=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NR_CPUS=2 -CONFIG_PADATA=y -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_LANTIQ=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_PHY_LANTIQ_VRX200_PCIE=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_SENSORS_LTQ_CPUTEMP=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SOC_XWAY=y -CONFIG_SYNC_R4K=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xway/config-5.10 b/target/linux/lantiq/xway/config-5.10 deleted file mode 100644 index eafa4ef0bb..0000000000 --- a/target/linux/lantiq/xway/config-5.10 +++ /dev/null @@ -1,77 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_AR8216_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_HW_RANDOM=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_ETOP=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MIPS_EBPF_JIT=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NR_CPU_NR_MAP=2 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_XWAY=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NR_CPUS=2 -CONFIG_PADATA=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_PSB6970_PHY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366RB_PHY=y -CONFIG_RTL8366_SMI=y -CONFIG_SCHED_SMT=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SOC_XWAY=y -CONFIG_SWCONFIG=y -CONFIG_SYNC_R4K=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/lantiq/xway_legacy/config-5.10 b/target/linux/lantiq/xway_legacy/config-5.10 deleted file mode 100644 index c177d2a935..0000000000 --- a/target/linux/lantiq/xway_legacy/config-5.10 +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_GENERIC_ALLOCATOR=y -# CONFIG_GPIO_SYSFS is not set -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_ETOP=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_NLS=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RTL8306_PHY=y -CONFIG_SGL_ALLOC=y -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SOC_XWAY=y -CONFIG_SWCONFIG=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/layerscape/armv7/config-5.10 b/target/linux/layerscape/armv7/config-5.10 deleted file mode 100644 index f3b8a16234..0000000000 --- a/target/linux/layerscape/armv7/config-5.10 +++ /dev/null @@ -1,668 +0,0 @@ -CONFIG_AD525X_DPOT=y -CONFIG_AD525X_DPOT_I2C=y -# CONFIG_AD525X_DPOT_SPI is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_APDS9802ALS=y -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_MXC=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_ERRATA_430973=y -CONFIG_ARM_ERRATA_643719=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_754327=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_ARM_ERRATA_798181=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -# CONFIG_ARM_HIGHBANK_CPUIDLE is not set -# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set -# CONFIG_ARM_IMX_BUS_DEVFREQ is not set -# CONFIG_ARM_IMX_CPUFREQ_DT is not set -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_LPAE=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_PSCI=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTOFS4_FS=y -CONFIG_AUTOFS_FS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BATTERY_SBS=y -CONFIG_BCM_NET_PHYLIB=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_CMDLINE_PARSER=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=262144 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_MQ_VIRTIO=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_BOUNCE=y -CONFIG_BRCMSTB_GISB_ARB=y -CONFIG_BROADCOM_PHY=y -CONFIG_CACHE_L2X0=y -CONFIG_CDROM=y -CONFIG_CHECKPOINT_RESTORE=y -CONFIG_CHR_DEV_SG=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_IMX_GPT=y -CONFIG_CLKSRC_MMIO=y -# CONFIG_CLK_IMX8MM is not set -# CONFIG_CLK_IMX8MN is not set -# CONFIG_CLK_IMX8MP is not set -# CONFIG_CLK_IMX8MQ is not set -CONFIG_CLK_QORIQ=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=64 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_COREDUMP=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRASH_CORE=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DW_DMAC=y -CONFIG_DW_DMAC_CORE=y -CONFIG_DW_WATCHDOG=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_93CX6=y -CONFIG_EEPROM_AT24=y -CONFIG_ELF_CORE=y -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_F2FS_FS=y -CONFIG_FAILOVER=y -CONFIG_FAT_FS=y -# CONFIG_FEC is not set -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FORCE_MAX_ZONEORDER=12 -CONFIG_FREEZER=y -CONFIG_FSL_EDMA=y -CONFIG_FSL_GUTS=y -CONFIG_FSL_IFC=y -# CONFIG_FSL_PPFE is not set -CONFIG_FSL_PQ_MDIO=y -CONFIG_FSL_RCPM=y -CONFIG_FSL_XGMAC_MDIO=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FTRACE=y -# CONFIG_FTRACE_SYSCALLS is not set -CONFIG_FUSE_FS=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GIANFAR=y -CONFIG_GLOB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_GPIO_MXC=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HVC_DRIVER=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_DEMUX_PINCTRL=y -CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_IMX=y -# CONFIG_I2C_IMX_LPI2C is not set -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_I2C_MUX_PINCTRL=y -CONFIG_I2C_RK3X=y -CONFIG_I2C_SLAVE=y -CONFIG_I2C_SLAVE_EEPROM=y -# CONFIG_I2C_SLAVE_TESTUNIT is not set -CONFIG_I2C_XILINX=y -CONFIG_ICPLUS_PHY=y -CONFIG_ICS932S401=y -CONFIG_IMX2_WDT=y -# CONFIG_IMX7ULP_WDT is not set -# CONFIG_IMX8MM_THERMAL is not set -CONFIG_IMX_DMA=y -# CONFIG_IMX_GPCV2_PM_DOMAINS is not set -CONFIG_IMX_INTMUX=y -# CONFIG_IMX_IRQSTEER is not set -CONFIG_IMX_SDMA=y -# CONFIG_IMX_WEIM is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IPC_NS=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_ISDN is not set -CONFIG_ISL29003=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_XZ is not set -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LS_EXTIRQ=y -CONFIG_LS_SCFG_MSI=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MANDATORY_FILE_LOCKING=y -CONFIG_MARVELL_PHY=y -CONFIG_MCPM=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_GPIO is not set -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MEMORY_ISOLATION=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_SYSCON=y -# CONFIG_MFD_VEXPRESS_SYSREG is not set -CONFIG_MICREL_PHY=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=16 -# CONFIG_MMC_MXC is not set -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_ESDHC_IMX is not set -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MSDOS_FS=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_DATAFLASH=y -# CONFIG_MTD_DATAFLASH_OTP is not set -# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_FSL_IFC=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SST25L=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -# CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_MX3_IPU=y -CONFIG_MX3_IPU_IRQS=4 -CONFIG_MXC_CLK=y -# CONFIG_MXS_DMA is not set -CONFIG_NAMESPACES=y -CONFIG_NATIONAL_PHY=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_FAILOVER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_NS=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=16 -CONFIG_NTFS_FS=y -CONFIG_NVMEM=y -# CONFIG_NVMEM_IMX_IIM is not set -# CONFIG_NVMEM_SNVS_LPGPR is not set -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PACKET_DIAG=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_ECAM=y -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -# CONFIG_PCI_IMX6 is not set -CONFIG_PCI_LAYERSCAPE=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PID_NS=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_IMX8MM is not set -# CONFIG_PINCTRL_IMX8MN is not set -# CONFIG_PINCTRL_IMX8MP is not set -# CONFIG_PINCTRL_IMX8MQ is not set -CONFIG_PL310_ERRATA_588369=y -CONFIG_PL310_ERRATA_727915=y -CONFIG_PL310_ERRATA_753970=y -CONFIG_PL310_ERRATA_769419=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_BRCMKONA=y -CONFIG_POWER_RESET_BRCMSTB=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_POWER_RESET_VEXPRESS=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PROC_CHILDREN=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_QORIQ=y -CONFIG_QORIQ_CPUFREQ=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RD_LZMA=y -CONFIG_RD_LZO=y -CONFIG_RD_XZ=y -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_DS3232=y -CONFIG_RTC_DRV_EM3027=y -CONFIG_RTC_DRV_FSL_FTM_ALARM=y -# CONFIG_RTC_DRV_IMXDI is not set -# CONFIG_RTC_DRV_MXC is not set -# CONFIG_RTC_DRV_MXC_V2 is not set -CONFIG_RTC_DRV_PCF2127=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_DEBUG=y -CONFIG_SCSI=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -# CONFIG_SECURITY_DMESG_RESTRICT is not set -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_EM=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_BCM63XX=y -CONFIG_SERIAL_BCM63XX_CONSOLE=y -CONFIG_SERIAL_CONEXANT_DIGICOLOR=y -CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_IMX_EARLYCON=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_ST_ASC=y -CONFIG_SERIAL_ST_ASC_CONSOLE=y -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SLUB_DEBUG=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SMSC_PHY=y -CONFIG_SOCK_DIAG=y -CONFIG_SOC_BRCMSTB=y -CONFIG_SOC_BUS=y -# CONFIG_SOC_IMX50 is not set -# CONFIG_SOC_IMX51 is not set -# CONFIG_SOC_IMX53 is not set -# CONFIG_SOC_IMX6Q is not set -# CONFIG_SOC_IMX6SL is not set -# CONFIG_SOC_IMX6SLL is not set -# CONFIG_SOC_IMX6SX is not set -# CONFIG_SOC_IMX6UL is not set -# CONFIG_SOC_IMX7D is not set -# CONFIG_SOC_IMX7ULP is not set -# CONFIG_SOC_IMX8M is not set -CONFIG_SOC_LS1021A=y -# CONFIG_SOC_VF610 is not set -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_CADENCE=y -CONFIG_SPI_DYNAMIC=y -# CONFIG_SPI_FSL_LPSPI is not set -# CONFIG_SPI_FSL_QUADSPI is not set -# CONFIG_SPI_IMX is not set -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPI_XILINX=y -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -CONFIG_SQUASHFS_LZO=y -CONFIG_SQUASHFS_ZLIB=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -CONFIG_STAGING_BOARD=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNIX_DIAG=y -CONFIG_UNWINDER_ARM=y -CONFIG_USB_SUPPORT=y -CONFIG_USER_NS=y -CONFIG_USE_OF=y -CONFIG_UTS_NS=y -CONFIG_VEXPRESS_CONFIG=y -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_VIRTIO_MMIO=y -CONFIG_VIRTIO_NET=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y -CONFIG_VITESSE_PHY=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XILINX_WATCHDOG=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_X86=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/layerscape/armv8_64b/config-5.10 b/target/linux/layerscape/armv8_64b/config-5.10 deleted file mode 100644 index 4b8a819edf..0000000000 --- a/target/linux/layerscape/armv8_64b/config-5.10 +++ /dev/null @@ -1,851 +0,0 @@ -CONFIG_64BIT=y -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_HEADER=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_LAYERSCAPE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=33 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CNP=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_ERRATUM_1742098=y -CONFIG_ARM64_ERRATUM_1165522=y -CONFIG_ARM64_ERRATUM_1286807=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_MODULE_PLTS=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PAN=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_UAO=y -CONFIG_ARM64_VA_BITS=48 -# CONFIG_ARM64_VA_BITS_39 is not set -CONFIG_ARM64_VA_BITS_48=y -CONFIG_ARM64_VHE=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_FSL_MC=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -# CONFIG_ARM_PL172_MPMC is not set -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ARM_SMMU=y -# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set -# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set -CONFIG_ARM_SMMU_V3=y -# CONFIG_ARM_SMMU_V3_SVA is not set -CONFIG_ARM_SP805_WATCHDOG=y -CONFIG_ASM_MODVERSIONS=y -CONFIG_ASN1=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATA=y -CONFIG_AUDIT=y -CONFIG_AUDITSYSCALL=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_AUDIT_GENERIC=y -CONFIG_AUTOFS4_FS=y -CONFIG_AUTOFS_FS=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BALLOON_COMPACTION=y -CONFIG_BATTERY_BQ27XXX=y -# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set -CONFIG_BATTERY_BQ27XXX_I2C=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=262144 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_MQ_VIRTIO=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_BTRFS_FS=y -# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set -CONFIG_BTRFS_FS_POSIX_ACL=y -CONFIG_CAVIUM_ERRATUM_22375=y -CONFIG_CAVIUM_ERRATUM_23144=y -CONFIG_CAVIUM_ERRATUM_23154=y -CONFIG_CAVIUM_ERRATUM_27456=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CHECKPOINT_RESTORE=y -CONFIG_CHROME_PLATFORMS=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLK_LS1028A_PLLDIG=y -CONFIG_CLK_QORIQ=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_CS2000_CP=y -# CONFIG_COMMON_CLK_FSL_SAI is not set -CONFIG_COMMON_CLK_XGENE=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_COREDUMP=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_THERMAL=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRASH_CORE=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC7=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC_T10DIF=y -CONFIG_CROSS_MEMORY_ATTACH=y -# CONFIG_CROS_EC is not set -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_BLAKE2B=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_FSL_CAAM=y -CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y -CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y -CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y -# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set -# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set -CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y -CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y -CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 -CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y -CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ENGINE=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_XTS=y -CONFIG_CRYPTO_XXHASH=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_CMA=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DNOTIFY=y -CONFIG_DPAA2_CONSOLE=y -CONFIG_DPAA_ERRATUM_A050385=y -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_ELF_CORE=y -# CONFIG_EMBEDDED is not set -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_EXTCON=y -CONFIG_EXTCON_USB_GPIO=y -CONFIG_F2FS_FS=y -CONFIG_FAILOVER=y -CONFIG_FANOTIFY=y -CONFIG_FAT_FS=y -CONFIG_FB=y -CONFIG_FB_ARMCLCD=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_FRAME_POINTER=y -CONFIG_FRAME_WARN=2048 -CONFIG_FREEZER=y -# CONFIG_FSL_BMAN_TEST is not set -CONFIG_FSL_DPAA=y -CONFIG_FSL_DPAA2=y -CONFIG_FSL_DPAA2_ETH=y -CONFIG_FSL_DPAA2_ETHSW=y -CONFIG_FSL_DPAA2_PTP_CLOCK=y -# CONFIG_FSL_DPAA2_QDMA is not set -# CONFIG_FSL_DPAA_CHECKING is not set -CONFIG_FSL_DPAA_ETH=y -CONFIG_FSL_EDMA=y -CONFIG_FSL_ENETC=y -CONFIG_FSL_ENETC_MDIO=y -CONFIG_FSL_ENETC_PTP_CLOCK=y -CONFIG_FSL_ENETC_VF=y -CONFIG_FSL_ERRATUM_A008585=y -CONFIG_FSL_FMAN=y -CONFIG_FSL_GUTS=y -CONFIG_FSL_IFC=y -CONFIG_FSL_MC_BUS=y -CONFIG_FSL_MC_DPIO=y -# CONFIG_FSL_PPFE is not set -# CONFIG_FSL_PPFE_UTIL_DISABLED is not set -# CONFIG_FSL_QMAN_TEST is not set -CONFIG_FSL_RCPM=y -CONFIG_FSL_XGMAC_MDIO=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FUSE_FS=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set -CONFIG_GARP=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -# CONFIG_GIANFAR is not set -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HIBERNATE_CALLBACKS=y -CONFIG_HIBERNATION=y -CONFIG_HIBERNATION_SNAPSHOT_DEV=y -CONFIG_HID=y -CONFIG_HID_A4TECH=y -CONFIG_HID_APPLE=y -CONFIG_HID_BELKIN=y -CONFIG_HID_CHERRY=y -CONFIG_HID_CYPRESS=y -CONFIG_HID_EZKEY=y -CONFIG_HID_GENERIC=y -CONFIG_HID_KENSINGTON=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MONTEREY=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_HVC_DRIVER=y -CONFIG_HVC_IRQ=y -CONFIG_HVC_XEN=y -CONFIG_HVC_XEN_FRONTEND=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_DESIGNWARE_CORE=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_IMX=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_PCA954x=y -CONFIG_I2C_RK3X=y -CONFIG_I2C_SLAVE=y -# CONFIG_I2C_SLAVE_TESTUNIT is not set -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_IMX2_WDT=y -CONFIG_INET_DIAG=y -# CONFIG_INET_DIAG_DESTROY is not set -# CONFIG_INET_RAW_DIAG is not set -CONFIG_INET_TCP_DIAG=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y -CONFIG_INTERVAL_TREE=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_IO_PGTABLE=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IPC_NS=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_BYPASS_MANAGER=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_IRQ_WORK=y -# CONFIG_ISDN is not set -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -CONFIG_KCMP=y -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -CONFIG_KEYBOARD_ATKBD=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_KSM=y -CONFIG_LIBCRC32C=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LS_EXTIRQ=y -CONFIG_LS_SCFG_MSI=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MANDATORY_FILE_LOCKING=y -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_BUS_MUX=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_GPIO is not set -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MEMORY_BALLOON=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MEMTEST=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_SYSCON=y -# CONFIG_MFD_VEXPRESS_SYSREG is not set -CONFIG_MICREL_PHY=y -CONFIG_MICROSEMI_PHY=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_OF_ESDHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMU_NOTIFIER=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_BYD=y -CONFIG_MOUSE_PS2_CYPRESS=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -CONFIG_MOUSE_PS2_FOCALTECH=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SMBUS=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_MPILIB=y -CONFIG_MRP=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -# CONFIG_MTD_CFI_GEOMETRY is not set -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_DATAFLASH=y -# CONFIG_MTD_DATAFLASH_OTP is not set -# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_FSL_IFC=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SST25L=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -# CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MULTIPLEXER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_MUX_MMIO=y -CONFIG_MV_XOR_V2=y -CONFIG_NAMESPACES=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_FAILOVER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_NS=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NODES_SHIFT=2 -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=64 -CONFIG_NUMA=y -CONFIG_NUMA_BALANCING=y -CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y -CONFIG_NVMEM=y -# CONFIG_NVMEM_LAYERSCAPE_SFP is not set -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_NUMA=y -CONFIG_PACKET_DIAG=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_REPORTING=y -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_PARAVIRT=y -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y -CONFIG_PCIE_MOBIVEIL=y -CONFIG_PCIE_MOBIVEIL_HOST=y -CONFIG_PCIE_PME=y -CONFIG_PCI_ATS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_ECAM=y -CONFIG_PCI_HISI=y -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCI_IOV=y -CONFIG_PCI_LAYERSCAPE=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_LYNX=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_XGENE=y -CONFIG_PID_IN_CONTEXTIDR=y -CONFIG_PID_NS=y -CONFIG_PL330_DMA=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_PM_STD_PARTITION="" -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_VEXPRESS=y -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_PROC_CHILDREN=y -CONFIG_PROFILING=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PTP_1588_CLOCK_QORIQ=y -CONFIG_QCOM_HIDMA=y -CONFIG_QCOM_HIDMA_MGMT=y -CONFIG_QCOM_QDF2400_ERRATUM_0065=y -# CONFIG_QFMT_V1 is not set -# CONFIG_QFMT_V2 is not set -CONFIG_QORIQ_CPUFREQ=y -CONFIG_QORIQ_THERMAL=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_RAID6_PQ=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RD_LZMA=y -CONFIG_RD_LZO=y -CONFIG_RD_XZ=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_DS3232=y -CONFIG_RTC_DRV_FSL_FTM_ALARM=y -CONFIG_RTC_DRV_PCF2127=y -CONFIG_RTC_DRV_PL031=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_INFO=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_THERMAL_PRESSURE=y -CONFIG_SCSI=y -# CONFIG_SCSI_PROC_FS is not set -# CONFIG_SCSI_SAS_ATA is not set -CONFIG_SCSI_SAS_ATTRS=y -CONFIG_SCSI_SAS_HOST_SMP=y -CONFIG_SCSI_SAS_LIBSAS=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_FSL_LPUART=y -CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_SC16IS7XX=y -CONFIG_SERIAL_SC16IS7XX_CORE=y -# CONFIG_SERIAL_SC16IS7XX_I2C is not set -CONFIG_SERIAL_SC16IS7XX_SPI=y -CONFIG_SERIAL_XILINX_PS_UART=y -CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y -CONFIG_SERIO=y -CONFIG_SERIO_AMBAKMI=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -CONFIG_SMP=y -CONFIG_SOCK_DIAG=y -CONFIG_SOC_BUS=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_FSL_DSPI=y -CONFIG_SPI_FSL_QUADSPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_NXP_FLEXSPI=y -CONFIG_SPI_PL022=y -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -# CONFIG_SQUASHFS_XZ is not set -CONFIG_SQUASHFS_ZLIB=y -CONFIG_SRAM=y -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWIOTLB=y -CONFIG_SWIOTLB_XEN=y -CONFIG_SWPHY=y -CONFIG_SYNC_FILE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYS_HYPERVISOR=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_TASK_XACCT=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UIO=y -CONFIG_UIO_AEC=y -CONFIG_UIO_CIF=y -CONFIG_UIO_DMEM_GENIRQ=y -CONFIG_UIO_MF624=y -CONFIG_UIO_NETX=y -CONFIG_UIO_PCI_GENERIC=y -CONFIG_UIO_PDRV_GENIRQ=y -# CONFIG_UIO_PRUSS is not set -CONFIG_UIO_SERCOS3=y -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNIX_DIAG=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB_SUPPORT=y -CONFIG_USER_NS=y -CONFIG_USE_PERCPU_NUMA_NODE_ID=y -CONFIG_UTS_NS=y -CONFIG_VEXPRESS_CONFIG=y -CONFIG_VFAT_FS=y -CONFIG_VFIO=y -CONFIG_VFIO_FSL_MC=y -CONFIG_VFIO_IOMMU_TYPE1=y -# CONFIG_VFIO_MDEV is not set -# CONFIG_VFIO_NOIOMMU is not set -CONFIG_VFIO_PCI=y -CONFIG_VFIO_PCI_INTX=y -CONFIG_VFIO_PCI_MMAP=y -# CONFIG_VFIO_PLATFORM is not set -CONFIG_VFIO_VIRQFD=y -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_VIRTIO_MMIO=y -CONFIG_VIRTIO_NET=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y -CONFIG_VITESSE_PHY=y -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_VMAP_STACK=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XARRAY_MULTI=y -CONFIG_XEN=y -CONFIG_XENFS=y -CONFIG_XEN_AUTO_XLATE=y -CONFIG_XEN_BACKEND=y -CONFIG_XEN_BALLOON=y -# CONFIG_XEN_BLKDEV_BACKEND is not set -CONFIG_XEN_BLKDEV_FRONTEND=y -CONFIG_XEN_COMPAT_XENFS=y -CONFIG_XEN_DEV_EVTCHN=y -CONFIG_XEN_DOM0=y -CONFIG_XEN_FBDEV_FRONTEND=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -# CONFIG_XEN_NETDEV_BACKEND is not set -CONFIG_XEN_NETDEV_FRONTEND=y -CONFIG_XEN_PRIVCMD=y -# CONFIG_XEN_PVCALLS_BACKEND is not set -# CONFIG_XEN_SCSI_FRONTEND is not set -CONFIG_XEN_SYS_HYPERVISOR=y -# CONFIG_XEN_WDT is not set -CONFIG_XEN_XENBUS_FRONTEND=y -CONFIG_XFS_FS=y -CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y -CONFIG_XOR_BLOCKS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_X86=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/layerscape/patches-5.10/300-add-DTS-for-Traverse-LS1043-Boards.patch b/target/linux/layerscape/patches-5.10/300-add-DTS-for-Traverse-LS1043-Boards.patch deleted file mode 100644 index 9dcd9348b2..0000000000 --- a/target/linux/layerscape/patches-5.10/300-add-DTS-for-Traverse-LS1043-Boards.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 5b35aae22b4ca2400e49561c9267aa01346f91d4 Mon Sep 17 00:00:00 2001 -From: Mathew McBride -Date: Tue, 17 Apr 2018 10:01:03 +1000 -Subject: [PATCH] add DTS for Traverse LS1043 Boards - -Signed-off-by: Mathew McBride -[rebase] -Signed-off-by: Yangbo Lu ---- - arch/arm64/boot/dts/freescale/Makefile | 3 +++ - arch/arm64/boot/dts/freescale/traverse-ls1043s.dts | 29 ++++++++++++++++++++++ - arch/arm64/boot/dts/freescale/traverse-ls1043v.dts | 29 ++++++++++++++++++++++ - 3 files changed, 61 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -28,6 +28,9 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2 - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb - -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043v.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043s.dtb -+ - dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb - dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb diff --git a/target/linux/layerscape/patches-5.10/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch b/target/linux/layerscape/patches-5.10/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch deleted file mode 100644 index ce6a19c896..0000000000 --- a/target/linux/layerscape/patches-5.10/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch +++ /dev/null @@ -1,291 +0,0 @@ -From 55e00e402d6143aeb153761f8144d9fee5f1f009 Mon Sep 17 00:00:00 2001 -From: Biwen Li -Date: Fri, 26 Oct 2018 16:00:37 +0800 -Subject: [PATCH] arm: dts: ls1021a: Add LS1021A-IOT board support - -Signed-off-by: Biwen Li -[rebase] -Signed-off-by: Yangbo Lu ---- - arch/arm/boot/dts/Makefile | 3 +- - arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++++++++++++++++++++++++++++++++++++ - 2 files changed, 264 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -666,7 +666,8 @@ dtb-$(CONFIG_SOC_LS1021A) += \ - ls1021a-moxa-uc-8410a.dtb \ - ls1021a-qds.dtb \ - ls1021a-tsn.dtb \ -- ls1021a-twr.dtb -+ ls1021a-twr.dtb \ -+ ls1021a-iot.dtb - dtb-$(CONFIG_SOC_VF610) += \ - vf500-colibri-eval-v3.dtb \ - vf610-bk4.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/ls1021a-iot.dts -@@ -0,0 +1,262 @@ -+/* -+ * Copyright 2013-2016 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+/dts-v1/; -+#include "ls1021a.dtsi" -+ -+/ { -+ model = "LS1021A IOT Board"; -+ -+ sys_mclk: clock-mclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24576000>; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_3p3v: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <0>; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_2p5v: regulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <1>; -+ regulator-name = "2P5V"; -+ regulator-min-microvolt = <2500000>; -+ regulator-max-microvolt = <2500000>; -+ regulator-always-on; -+ }; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,widgets = -+ "Microphone", "Microphone Jack", -+ "Headphone", "Headphone Jack", -+ "Speaker", "Speaker Ext", -+ "Line", "Line In Jack"; -+ simple-audio-card,routing = -+ "MIC_IN", "Microphone Jack", -+ "Microphone Jack", "Mic Bias", -+ "LINE_IN", "Line In Jack", -+ "Headphone Jack", "HP_OUT", -+ "Speaker Ext", "LINE_OUT"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&sai2>; -+ frame-master; -+ bitclock-master; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&codec>; -+ frame-master; -+ bitclock-master; -+ }; -+ }; -+ -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ }; -+}; -+ -+&enet0 { -+ tbi-handle = <&tbi1>; -+ phy-handle = <&phy1>; -+ phy-connection-type = "sgmii"; -+ status = "okay"; -+}; -+ -+&enet1 { -+ tbi-handle = <&tbi1>; -+ phy-handle = <&phy3>; -+ phy-connection-type = "sgmii"; -+ status = "okay"; -+}; -+ -+&enet2 { -+ fixed-link = <0 1 1000 0 0>; -+ phy-connection-type = "rgmii-id"; -+ status = "okay"; -+}; -+ -+&can0{ -+ status = "disabled"; -+}; -+ -+&can1{ -+ status = "disabled"; -+}; -+ -+&can2{ -+ status = "disabled"; -+}; -+ -+&can3{ -+ status = "okay"; -+}; -+ -+&esdhc{ -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ max1239@35 { -+ compatible = "maxim,max1239"; -+ reg = <0x35>; -+ #io-channel-cells = <1>; -+ }; -+ -+ codec: sgtl5000@2a { -+ #sound-dai-cells=<0x0>; -+ compatible = "fsl,sgtl5000"; -+ reg = <0x2a>; -+ VDDA-supply = <®_3p3v>; -+ VDDIO-supply = <®_2p5v>; -+ clocks = <&sys_mclk 1>; -+ }; -+ -+ pca9555: pca9555@23 { -+ compatible = "nxp,pca9555"; -+ /*pinctrl-names = "default";*/ -+ /*interrupt-parent = <&gpio2>; -+ interrupts = <19 0x2>;*/ -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ reg = <0x23>; -+ }; -+ -+ ina220@44 { -+ compatible = "ti,ina220"; -+ reg = <0x44>; -+ shunt-resistor = <1000>; -+ }; -+ -+ ina220@45 { -+ compatible = "ti,ina220"; -+ reg = <0x45>; -+ shunt-resistor = <1000>; -+ }; -+ -+ lm75b@48 { -+ compatible = "nxp,lm75a"; -+ reg = <0x48>; -+ }; -+ -+ adt7461a@4c { -+ compatible = "adt7461a"; -+ reg = <0x4c>; -+ }; -+ -+ hdmi: sii9022a@39 { -+ compatible = "fsl,sii902x"; -+ reg = <0x39>; -+ interrupts = ; -+ }; -+}; -+ -+&i2c1 { -+ status = "disabled"; -+}; -+ -+&ifc { -+ status = "disabled"; -+}; -+ -+&lpuart0 { -+ status = "okay"; -+}; -+ -+&mdio0 { -+ phy0: ethernet-phy@0 { -+ reg = <0x0>; -+ }; -+ phy1: ethernet-phy@1 { -+ reg = <0x1>; -+ }; -+ phy2: ethernet-phy@2 { -+ reg = <0x2>; -+ }; -+ phy3: ethernet-phy@3 { -+ reg = <0x3>; -+ }; -+ tbi1: tbi-phy@1f { -+ reg = <0x1f>; -+ device_type = "tbi-phy"; -+ }; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ status = "okay"; -+ -+ qflash0: s25fl128s@0 { -+ compatible = "spansion,s25fl129p1"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ -+&sai2 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ status = "okay"; -+}; -+ -+&dcu { -+ display = <&display>; -+ status = "okay"; -+ -+ display: display@0 { -+ bits-per-pixel = <24>; -+ -+ display-timings { -+ native-mode = <&timing0>; -+ -+ timing0: mode0 { -+ clock-frequency = <25000000>; -+ hactive = <640>; -+ vactive = <480>; -+ hback-porch = <80>; -+ hfront-porch = <80>; -+ vback-porch = <16>; -+ vfront-porch = <16>; -+ hsync-len = <12>; -+ vsync-len = <2>; -+ hsync-active = <1>; -+ vsync-active = <1>; -+ }; -+ }; -+ }; -+}; diff --git a/target/linux/layerscape/patches-5.10/302-arm64-dts-ls1012a-update-with-ppfe-support.patch b/target/linux/layerscape/patches-5.10/302-arm64-dts-ls1012a-update-with-ppfe-support.patch deleted file mode 100644 index ef645f123d..0000000000 --- a/target/linux/layerscape/patches-5.10/302-arm64-dts-ls1012a-update-with-ppfe-support.patch +++ /dev/null @@ -1,295 +0,0 @@ -From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001 -From: Calvin Johnson -Date: Sat, 16 Sep 2017 14:20:23 +0530 -Subject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support - -Update ls1012a dtsi and platform dts files with support for ppfe. - -Signed-off-by: Calvin Johnson -Signed-off-by: Anjaneyulu Jagarlmudi ---- - .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 43 +++++++++++++++++ - .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 43 +++++++++++++++++ - .../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 +++++++++++++++++ - .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 47 +++++++++++++++++++ - .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++ - 5 files changed, 205 insertions(+) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -@@ -13,6 +13,11 @@ - model = "LS1012A Freedom Board"; - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; - -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+ - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -74,6 +79,44 @@ - }; - }; - -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; -+ - &qspi { - status = "okay"; - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -@@ -14,6 +14,11 @@ - / { - model = "LS1012A FRWY Board"; - compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; - }; - - &duart0 { -@@ -24,6 +29,44 @@ - status = "okay"; - }; - -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; -+ - &qspi { - status = "okay"; - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -@@ -13,6 +13,11 @@ - model = "LS1012A QDS Board"; - compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; - -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+ - sys_mclk: clock-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -127,6 +132,44 @@ - }; - }; - }; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x2>; -+ phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x3>; -+ phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; - - &qspi { - status = "okay"; ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -@@ -12,6 +12,15 @@ - / { - model = "LS1012A RDB Board"; - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+}; -+ -+&pcie1 { -+ status = "okay"; - }; - - &duart0 { -@@ -35,6 +44,44 @@ - status = "okay"; - }; - -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pfe_mac0: ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */ -+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "rgmii-txid"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; -+ - &qspi { - status = "okay"; - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi -@@ -531,6 +531,35 @@ - }; - }; - -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ pfe_reserved: packetbuffer@83400000 { -+ reg = <0 0x83400000 0 0xc00000>; -+ }; -+ }; -+ -+ pfe: pfe@04000000 { -+ compatible = "fsl,pfe"; -+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ -+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ -+ reg-names = "pfe", "pfe-ddr"; -+ fsl,pfe-num-interfaces = <0x2>; -+ interrupts = <0 172 0x4>, /* HIF interrupt */ -+ <0 173 0x4>, /*HIF_NOCPY interrupt */ -+ <0 174 0x4>; /* WoL interrupt */ -+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; -+ memory-region = <&pfe_reserved>; -+ fsl,pfe-scfg = <&scfg 0>; -+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "pfe"; -+ -+ status = "okay"; -+ }; -+ - firmware { - optee { - compatible = "linaro,optee-tz"; diff --git a/target/linux/layerscape/patches-5.10/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch b/target/linux/layerscape/patches-5.10/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch deleted file mode 100644 index 9cd016deab..0000000000 --- a/target/linux/layerscape/patches-5.10/303-arm64-dts-ls1012a-frdm-workaround-by-updating-qspi-f.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001 -From: Pawel Dembicki -Date: Fri, 28 Sep 2022 17:14:32 +0200 -Subject: [PATCH] arm64: dts: ls1012a-frdm/qds: workaround by updating qspi flash to - single mode - -Update rx and tx bus-width to 1 to use single mode to workaround ubifs -issue found with double mode. (The same method as RDB board) - -Signed-off-by: Pawel Dembicki ---- - arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 4 ++-- - arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 4 ++-- - 2 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -@@ -127,8 +127,8 @@ - spi-max-frequency = <50000000>; - m25p,fast-read; - reg = <0>; -- spi-rx-bus-width = <2>; -- spi-tx-bus-width = <2>; -+ spi-rx-bus-width = <1>; -+ spi-tx-bus-width = <1>; - }; - }; - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -@@ -181,8 +181,8 @@ - spi-max-frequency = <50000000>; - m25p,fast-read; - reg = <0>; -- spi-rx-bus-width = <2>; -- spi-tx-bus-width = <2>; -+ spi-rx-bus-width = <1>; -+ spi-tx-bus-width = <1>; - }; - }; - diff --git a/target/linux/layerscape/patches-5.10/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch b/target/linux/layerscape/patches-5.10/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch deleted file mode 100644 index 67eb5300e8..0000000000 --- a/target/linux/layerscape/patches-5.10/304-arm64-dts-ls1012a-rdb-workaround-by-updating-qspi-fl.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001 -From: Kuldeep Singh -Date: Tue, 7 Jan 2020 17:14:32 +0530 -Subject: [PATCH] arm64: dts: ls1012a-rdb: workaround by updating qspi flash to - single mode - -Update rx and tx bus-width to 1 to use single mode to workaround ubifs -issue found with double mode. - -[ Leo: Local workaround ] - -Signed-off-by: Kuldeep Singh ---- - arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -@@ -92,8 +92,8 @@ - spi-max-frequency = <50000000>; - m25p,fast-read; - reg = <0>; -- spi-rx-bus-width = <2>; -- spi-tx-bus-width = <2>; -+ spi-rx-bus-width = <1>; -+ spi-tx-bus-width = <1>; - }; - }; - diff --git a/target/linux/layerscape/patches-5.10/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch b/target/linux/layerscape/patches-5.10/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch deleted file mode 100644 index a7af6e16ad..0000000000 --- a/target/linux/layerscape/patches-5.10/305-arm64-dts-ls1046a-rdb-Update-qspi-spi-rx-bus-width-t.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 38093ebbf25eb60a1aa863f46118a68a0300c56e Mon Sep 17 00:00:00 2001 -From: Kuldeep Singh -Date: Fri, 3 Jan 2020 14:49:07 +0530 -Subject: [PATCH] arm64: dts: ls1046a-rdb: Update qspi spi-rx-bus-width to 1 - -Update rx width from quad mode to single mode as a workaround. - -[Leo: Local workaround ] - -Signed-off-by: Kuldeep Singh ---- - arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts -@@ -101,7 +101,7 @@ - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; -- spi-rx-bus-width = <4>; -+ spi-rx-bus-width = <1>; - spi-tx-bus-width = <1>; - reg = <0>; - }; -@@ -111,7 +111,7 @@ - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; -- spi-rx-bus-width = <4>; -+ spi-rx-bus-width = <1>; - spi-tx-bus-width = <1>; - reg = <1>; - }; diff --git a/target/linux/layerscape/patches-5.10/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch b/target/linux/layerscape/patches-5.10/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch deleted file mode 100644 index aea483d1af..0000000000 --- a/target/linux/layerscape/patches-5.10/400-LF-20-3-mtd-spi-nor-Use-1-bit-mode-of-spansion-s25fs.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 2b84e88d36de482da0370290ad4af09a71993f08 Mon Sep 17 00:00:00 2001 -From: Han Xu -Date: Tue, 14 Apr 2020 11:58:44 -0500 -Subject: [PATCH] LF-20-3 mtd: spi-nor: Use 1 bit mode of spansion(s25fs512s) - flash - -This is a workaround patch which uses only single bit mode of s25fs512s -flash - -Signed-off-by: Han Xu -Signed-off-by: Kuldeep Singh ---- - drivers/mtd/spi-nor/spansion.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/spansion.c -+++ b/drivers/mtd/spi-nor/spansion.c -@@ -62,7 +62,7 @@ static const struct flash_info spansion_ - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - USE_CLSR) }, - { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, -- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) -+ SPI_NOR_4B_OPCODES | USE_CLSR) - .fixups = &s25fs_s_fixups, }, - { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, - { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, diff --git a/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch deleted file mode 100644 index 71c86e55fd..0000000000 --- a/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch +++ /dev/null @@ -1,12036 +0,0 @@ -From ab06204b9ae48324ed5b7e7026cce47ecd0a376d Mon Sep 17 00:00:00 2001 -From: Martin Schiller -Date: Mon, 8 Nov 2021 14:56:10 +0100 -Subject: [PATCH] staging: add fsl_ppfe driver -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This patch is the squashed version of all ppfe related commits from -LSDK-21.08. - -See the following git log for further details: - -commit bc389fa57819620b61f86a39444cf22c70e291ad -Author: Calvin Johnson -Date: Sat Sep 16 07:05:49 2017 +0530 - - net: fsl_ppfe: dts binding for ppfe - - Signed-off-by: Calvin Johnson - Signed-off-by: Anjaneyulu Jagarlmudi - -commit d3822b65f897e4c421c72bd215f34e41d8c4a40e -Author: Calvin Johnson -Date: Sat Sep 16 14:21:37 2017 +0530 - - staging: fsl_ppfe/eth: header files for pfe driver - - This patch has all pfe header files. - - Signed-off-by: Calvin Johnson - Signed-off-by: Anjaneyulu Jagarlmudi - -commit 9184a85f93816a8b81cb363464925757185b7138 -Author: Calvin Johnson -Date: Sat Sep 16 14:22:17 2017 +0530 - - staging: fsl_ppfe/eth: introduce pfe driver - - This patch introduces Linux support for NXP's LS1012A Packet - Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding - engine to provide high performance Ethernet interfaces. The device - includes two Ethernet ports. - - Signed-off-by: Calvin Johnson - Signed-off-by: Anjaneyulu Jagarlmudi - -commit 63f6117f1c9af34bc333425507a8b858fcd61951 -Author: Calvin Johnson -Date: Wed Oct 11 19:23:38 2017 +0530 - - staging: fsl_ppfe/eth: fix RGMII tx delay issue - - Recently logic to enable RGMII tx delay was changed by - below patch. - - https://patchwork.kernel.org/patch/9447581/ - - Based on the patch, appropriate change is made in PFE driver. - - Signed-off-by: Calvin Johnson - Signed-off-by: Anjaneyulu Jagarlmudi - -commit adf71df9d53026513da71892a27c455ae23a6d06 -Author: Calvin Johnson -Date: Wed Oct 18 14:29:30 2017 +0530 - - staging: fsl_ppfe/eth: remove unused functions - - Remove unused functions hif_xmit_pkt & hif_lib_xmit_pkt. - - Signed-off-by: Calvin Johnson - -commit ea632882dacf4ec21f84fa73ebff7d89d46fbeb3 -Author: Calvin Johnson -Date: Wed Oct 18 18:34:41 2017 +0530 - - staging: fsl_ppfe/eth: fix read/write/ack idx issue - - While fixing checkpatch errors some of the index increments - were commented out. They are enabled. - - Signed-off-by: Calvin Johnson - -commit 75dc5856eafe3ec988aa52f498ad683332e5a528 -Author: Calvin Johnson -Date: Fri Oct 27 11:20:47 2017 +0530 - - staging: fsl_ppfe/eth: Make phy_ethtool_ksettings_get return void - - Make return value void since function never return meaningful value - - Signed-off-by: Calvin Johnson - -commit fd60dff2329a4c20f5638147db315879d4b92097 -Author: Calvin Johnson -Date: Wed Nov 15 13:45:27 2017 +0530 - - staging: fsl_ppfe/eth: add function to update tmu credits - - __hif_lib_update_credit function is used to update the tmu credits. - If tx_qos is set, tmu credit is updated based on the number of packets - transmitted by tmu. - - Signed-off-by: Calvin Johnson - Signed-off-by: Anjaneyulu Jagarlmudi - -commit 259418d3755afeabca062df4c177cb6617be7e2b -Author: Kavi Akhila-B46177 -Date: Thu Nov 2 12:05:35 2017 +0530 - - staging: fsl_ppfe/eth: Avoid packet drop at TMU queues - - Added flow control between TMU queues and PFE Linux driver, - based on TMU credits availability. - Added tx_qos module parameter to control this behavior. - Use queue-0 as default queue to transmit packets. - - Signed-off-by: Calvin Johnson - Signed-off-by: Akhila Kavi - Signed-off-by: Anjaneyulu Jagarlmudi - -commit 48f8aa50bdcccdec699550d10e274711f9f8cb4d -Author: Bhaskar Upadhaya -Date: Wed Nov 29 12:08:00 2017 +0530 - - staging: fsl_ppfe/eth: Enable PFE in clause 45 mode - - when we opearate in clause 45 mode, we need to call - the function get_phy_device() with its 3rd argument as - "true" and then the resultant phy device needs to be - register with phy layer via phy_device_register() - - Signed-off-by: Bhaskar Upadhaya - -commit 217cf01a1eb7c0a1f44c250ab05bb832287069ca -Author: Bhaskar Upadhaya -Date: Wed Nov 29 12:21:43 2017 +0530 - - staging: fsl_ppfe/eth: Disable autonegotiation for 2.5G SGMII - - PCS initialization sequence for 2.5G SGMII interface governs - auto negotiation to be in disabled mode - - Signed-off-by: Bhaskar Upadhaya - -commit 0758955e5d8be44260c3b6877ff78e18c2dc2706 -Author: Calvin Johnson -Date: Thu Mar 8 13:58:38 2018 +0530 - - staging: fsl_ppfe/eth: calculate PFE_PKT_SIZE with SKB_DATA_ALIGN - - pfe packet size was calculated without considering skb data alignment - and this resulted in jumbo frames crashing kernel when the - cacheline size increased from 64 to 128 bytes with - commit 97303480753e ("arm64: Increase the max granular size"). - - Modify pfe packet size caclulation to include skb data alignment of - sizeof(struct skb_shared_info). - - Signed-off-by: Calvin Johnson - -commit d336c470781a28fe44a494b4f537a4dbac9fd1dd -Author: Akhil Goyal -Date: Fri Apr 13 15:41:28 2018 +0530 - - staging: fsl_ppfe/eth: support for userspace networking - - This patch adds the userspace mode support to fsl_ppfe network driver. - In the new mode, basic hardware initialization is performed in kernel, while - the datapath and HIF handling is the responsibility of the userspace. - - The new command line parameter is added to initialize the ppfe module - in userspace mode. By default the module remains in kernelspace networking - mode. - To enable userspace mode, use "insmod pfe.ko us=1" - - Signed-off-by: Akhil Goyal - Signed-off-by: Gagandeep Singh - -commit 30f97a6ae76cf7a284fee4b8ad30bce24568ac53 -Author: Calvin Johnson -Date: Mon Apr 30 11:40:01 2018 +0530 - - staging: fsl_ppfe/eth: unregister netdev after pfe_phy_exit - - rmmod pfe.ko throws below warning: - - kernfs: can not remove 'phydev', no directory - ------------[ cut here ]------------ - WARNING: CPU: 0 PID: 2230 at fs/kernfs/dir.c:1481 - kernfs_remove_by_name_ns+0x90/0xa0 - - This is caused when the unregistered netdev structure is accessed to - disconnect phy. - - Resolve the issue by unregistering netdev after disconnecting phy. - - Signed-off-by: Calvin Johnson - -commit 1b7daa665cd53fe51f19689c5b209fd89551f131 -Author: anuj batham -Date: Fri Apr 27 14:38:09 2018 +0530 - - staging: fsl_ppfe/eth: HW parse results for DPDK - - HW Parse results are included in the packet headroom. - Length and Offset calculation now accommodates parse info size. - - Signed-off-by: Archana Madhavan - -commit 0aeb9981d44aad6a45eb8f3ead37f91258be173f -Author: Calvin Johnson -Date: Wed Jun 20 10:22:32 2018 +0530 - - staging: fsl_ppfe/eth: reorganize pfe_netdev_ops - - Reorganize members of struct pfe_netdev_ops to match with the order - of members in struct net_device_ops defined in include/linux/netdevice.h - - Signed-off-by: Calvin Johnson - -commit 1cbccc5028c337e7c88bf61cf89038cfad449d34 -Author: Calvin Johnson -Date: Wed Jun 20 10:22:50 2018 +0530 - - staging: fsl_ppfe/eth: use mask for rx max frame len - - Define and use PFE_RCR_MAX_FL_MASK to properly set Rx max frame - length of MAC Receive Control Register. - - Signed-off-by: Calvin Johnson - -commit d8c8ed721470bd47ad5414d8fdc5d093cdd247f7 -Author: Calvin Johnson -Date: Wed Jun 20 10:23:01 2018 +0530 - - staging: fsl_ppfe/eth: define pfe ndo_change_mtu function - - Define ndo_change_mtu function for pfe. This sets the max Rx frame - length to the new mtu. - - Signed-off-by: Calvin Johnson - -commit f5f50edda84cf9305db06310536525c206970d6c -Author: Calvin Johnson -Date: Wed Jun 20 10:23:16 2018 +0530 - - staging: fsl_ppfe/eth: remove jumbo frame enable from gemac init - - MAC Receive Control Register was configured to allow jumbo frames. - This is removed as jumbo frames can be supported anytime by changing - mtu which will in turn modify MAX_FL field of MAC RCR. - Jumbo frames caused pfe to hang on LS1012A rev 1.0 Silicon due to - erratum A-010897. - - Signed-off-by: Calvin Johnson - -commit 53e3c57af87d72ee0299a723499bd911cb1ed25a -Author: Calvin Johnson -Date: Wed Jun 20 10:23:32 2018 +0530 - - staging: fsl_ppfe/eth: disable CRC removal - - Disable CRC removal from the packet, so that packets are forwarded - as is to Linux. - CRC configuration in MAC will be reflected in the packet received - to Linux. - - Signed-off-by: Calvin Johnson - -commit eb55f7878a6ece7edbecd648e147a5683da18c76 -Author: Calvin Johnson -Date: Wed Jun 20 10:23:41 2018 +0530 - - staging: fsl_ppfe/eth: handle ls1012a errata_a010897 - - On LS1012A rev 1.0, Jumbo frames are not supported as it causes - the PFE controller to hang. A reset of the entire chip is required - to resume normal operation. - - To handle this errata, frames with length > 1900 are truncated for - rev 1.0 of LS1012A. - - Signed-off-by: Calvin Johnson - -commit c7b4f5f8f74925ce1d209ee4fcd5973d5cc5b61c -Author: Calvin Johnson -Date: Thu Oct 4 09:38:34 2018 +0530 - - staging: fsl_ppfe/eth: replace magic numbers - - Replace magic numbers and some cosmetic changes. - - Signed-off-by: Calvin Johnson - -commit c0ed379aa248dd70b2acf5dd8908bec1f6de5487 -Author: Calvin Johnson -Date: Thu Oct 4 09:39:00 2018 +0530 - - staging: fsl_ppfe/eth: resolve indentation warning - - Resolve the following indentation warning: - - drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c: - In function ‘pfe_get_gemac_if_proprties’: - drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:96:2: - warning: this ‘else’ clause does not guard... - [-Wmisleading-indentation] - else - ^~~~ - drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:98:3: - note: ...this statement, but the latter is misleadingly indented as - if it were guarded by the ‘else’ - pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id; - ^~~~~ - - Signed-off-by: Calvin Johnson - -commit c509cb585af2848dbb4ab194bf0fa435e356cb0a -Author: Calvin Johnson -Date: Thu Oct 4 09:38:17 2018 +0530 - - staging: fsl_ppfe/eth: add fixed-link support - - In cases where MAC is not connected to a normal MDIO-managed PHY - device, and instead to a switch, it is configured as a "fixed-link". - Code to handle this scenario is added here. - - phy_node in the dtb is checked to identify a fixed-link. - On identification of a fixed-link, it is registered and connected. - - Signed-off-by: Calvin Johnson - -commit 5e93b6ed52d4cdce12a481866c6f211299940734 -Author: Shreyansh Jain -Date: Wed Jun 6 14:19:34 2018 +0530 - - staging: fsl_ppfe: add support for a char dev for link status - - Read and IOCTL support is added. Application would need to open, - read/ioctl the /dev/pfe_us_cdev device. - select is pending as it requires a wait_queue. - - Signed-off-by: Shreyansh Jain - Signed-off-by: Calvin Johnson - -commit 48e064df94157b0c34f2d75e164ea5c7f4970b7b -Author: Akhil Goyal -Date: Thu Jul 5 20:14:21 2018 +0530 - - staging: fsl_ppfe: enable hif event from userspace - - HIF interrupts are enabled using ioctl from user space, - and epoll wait from user space wakes up when there is an HIF - interrupt. - - Signed-off-by: Akhil Goyal - -commit d16d91d3250abec31422b28ff04a973b8b3d73c5 -Author: Akhil Goyal -Date: Fri Jul 20 16:43:25 2018 +0530 - - staging: fsl_ppfe: performance tuning for user space - - interrupt coalescing of 100 usec is added. - - Signed-off-by: Akhil Goyal - Signed-off-by: Sachin Saxena - -commit eadb4c9d3e37c44659284fc9190d7e4f04b12aa0 -Author: Calvin Johnson -Date: Tue Nov 20 21:50:23 2018 +0530 - - staging: fsl_ppfe/eth: Update to use SPDX identifiers - - Replace license text with corresponding SPDX identifiers and update the - format of existing SPDX identifiers to follow the new guideline - Documentation/process/license-rules.rst. - - Signed-off-by: Calvin Johnson - -commit a468be7bda6fd98afab1cccb4e7151f23ca096e9 -Author: Calvin Johnson -Date: Tue Nov 20 21:50:40 2018 +0530 - - staging: fsl_ppfe/eth: misc clean up - - - remove redundant hwfeature init - - remove unused vars from ls1012a_eth_platform_data - - To handle ls1012a errata_a010897, PPFE driver requires GUTS driver - to be compiled in. Select FSL_GUTS when PPFE driver is compiled. - - Signed-off-by: Calvin Johnson - -commit 0e37bfbeda9510688ad987251aa07e3c88d6ba41 -Author: Calvin Johnson -Date: Tue Nov 20 21:50:51 2018 +0530 - - staging: fsl_ppfe/eth: reorganize platform phy parameters - - - Use "phy-handle" and of_* functions to get phy node and fixed-link - parameters - - - Reorganize phy parameters and initialize them only if phy-handle - or fixed-link is defined in the dtb. - - - correct typo pfe_get_gemac_if_proprties to pfe_get_gemac_if_properties - - Signed-off-by: Calvin Johnson - -commit c8703ab06e644e853b12baf082dd703f6a4440a5 -Author: Calvin Johnson -Date: Fri Nov 23 23:58:28 2018 +0530 - - staging: fsl_ppfe/eth: support single interface initialization - - - arrange members of struct mii_bus in sequence matching phy.h - - if mdio node is defined, use of_mdiobus_register to register - child nodes (phy devices) available on the mdio bus. - - remove of_phy_register_fixed_link from pfe_phy_init as it is being - handled in pfe_get_gemac_if_properties - - remove mdio enabled check - - skip phy init, if no PHY or fixed-link - - Signed-off-by: Calvin Johnson - -commit 89804e2d74002d01ea3f174048176e498298329a -Author: Calvin Johnson -Date: Tue Nov 20 21:51:53 2018 +0530 - - net: fsl_ppfe: update dts properties for phy - - Use commonly used phy-handle property and mdio subnode to handle - phy properties. - - Deprecate bindings fsl,gemac-phy-id & fsl,pfe-phy-if-flags. - - Signed-off-by: Calvin Johnson - -commit 5b0cc262ba7791fb0fae1f81f9619f54a15a75ba -Author: Calvin Johnson -Date: Fri Dec 7 19:30:03 2018 +0530 - - staging: fsl_ppfe/eth: remove unused code - - - remove gemac-bus-id related code that is unused. - - remove unused prototype gemac_set_mdc_div. - - Signed-off-by: Calvin Johnson - -commit a5a237f331ab7fcd85b95466f481ddb7023aecc3 -Author: Calvin Johnson -Date: Mon Dec 10 10:22:33 2018 +0530 - - staging: fsl_ppfe/eth: separate mdio init from mac init - - - separate mdio initialization from mac initialization - - Define pfe_mdio_priv_s structure to hold mii_bus structure and other - related data. - - Modify functions to work with the separted mdio init model. - - Signed-off-by: Calvin Johnson - -commit 262a03c082de5a93efd7f54bec48b39cda9042a8 -Author: Calvin Johnson -Date: Wed Mar 27 13:25:57 2019 +0530 - - staging: fsl_ppfe/eth: adapt to link mode based phydev changes - - Setting link mode bits have changed with the integration of - commit (3c1bcc8 net: ethernet: Convert phydev advertize and - supported from u32 to link mode). Adapt to the new method of - setting and clearing the link mode bits. - - Signed-off-by: Calvin Johnson - -commit 75f911d8ae45215f1c188191da92905ad3f7ad4a -Author: Calvin Johnson -Date: Wed Mar 27 19:31:35 2019 +0530 - - staging: fsl_ppfe/eth: use generic soc_device infra instead of fsl_guts_get_svr() - - Commit ("soc: fsl: guts: make fsl_guts_get_svr() static") has - made fsl_guts_get_svr() static and hence use generic soc_device - infrastructure to check SoC revision. - - Signed-off-by: Calvin Johnson - -commit 0a0ca3d898d15b3d7a206597a68f28134d4dfebd -Author: Calvin Johnson -Date: Tue Mar 26 16:52:22 2019 +0530 - - staging: fsl_ppfe/eth: use memremap() to map RAM area used by PFE - - RAM area used by PFE should be mapped using memremap() instead of - directly traslating physical addr to virtual. This will ensure proper - checks are done before the area is used. - - Signed-off-by: Calvin Johnson - -commit bfc0c2fedb76ad9c888db421b435d51e33fe276a -Author: Li Yang -Date: Tue Jun 11 18:24:37 2019 -0500 - - staging: fsl_ppfe/eth: remove 'fallback' argument from dev->ndo_select_queue() - - To be consistent with upstream API change. - - Signed-off-by: Li Yang - -commit cfd0841983961067efe69379371ddcb49b230dac -Author: Ting Liu -Date: Mon Jun 17 09:27:53 2019 +0200 - - staging: fsl_ppfe/eth: prefix header search paths with $(srctree)/ - - Currently, the rules for configuring search paths in Kbuild have - changed: https://lkml.org/lkml/2019/5/13/37 - - This will lead the below error: - - fatal error: pfe/pfe.h: No such file or directory - - Fix it by adding $(srctree)/ prefix to the search paths. - - Signed-off-by: Ting Liu - -commit 4be722099e4b6bdff2e683234ffaa2dc62fc773d -Author: Calvin Johnson -Date: Wed Nov 1 11:11:30 2017 +0530 - - staging: fsl_ppfe/eth: add pfe support to Kconfig and Makefile - - Signed-off-by: Calvin Johnson - [ Aisheng: fix minor conflict due to removed VBOXSF_FS ] - Signed-off-by: Dong Aisheng - -commit 5a2c9482ec3959dc2010f99897359b9e4006d2a4 -Author: Nagesh Koneti -Date: Wed Sep 25 12:01:19 2019 +0530 - - staging: fsl_ppfe/eth: Disable termination of CRC fwd. - - LS1012A MAC PCS block has an erratum that is seen with specific PHY AR803x. - The issue is triggered by the (spec-compliant) operation of the AR803x PHY - on the LS1012A-FRWY board.Due to this, good FCS packet is reported as error - packet by MAC, so for these error packets FCS should be validated and - discard only real error packets in PFE Rx packet path. - - Signed-off-by: Nagesh Koneti - Signed-off-by: Nagesh Koneti <“koneti.nagesh@nxp.com”> - -commit 36344cfc28f4cbdf606330ab8929e10d0778a087 -Author: Li Yang -Date: Sun Dec 8 18:19:18 2019 -0600 - - net: ppfe: Cope with of_get_phy_mode() API change - - Signed-off-by: Li Yang - -commit ee2a796cf8990ac06f329c580f18fffefbac6a9a -Author: Anji Jagarlmudi -Date: Wed Jan 8 19:06:12 2020 +0530 - - staging: fsl_ppfe/eth: Enhance error checking in platform probe - - Fix the kernel crash when MAC addr is not passed in dtb. - - Signed-off-by: Anji Jagarlmudi - -commit 2e8ca14ea6cc8d6816f2a445f3610f6b5b852e7c -Author: Anji Jagarlmudi -Date: Mon Apr 6 19:46:05 2020 +0530 - - staging: fsl_ppfe/eth: reject unsupported coalescing params - - Set ethtool_ops->supported_coalesce_params to let - the core reject unsupported coalescing parameters. - - Signed-off-by: Anji Jagarlmudi - -commit 7ce4dd75c94d8a7dbe4e4ad747b4ddc5be6d83b4 -Author: Chaitanya Sakinam -Date: Sat Mar 28 00:30:53 2020 +0530 - - staging: fsl_ppfe/eth:check "reg" property before pfe_get_gemac_if_properties() - - It has been observed that the function pfe_get_gemac_if_properties() is - been called blindly for the next two child nodes. There might be some - cases where it may go wrong and that lead to missing interfaces. - with these changes it is ensured thats not the case. - - Signed-off-by: Chaitanya Sakinam - Signed-off-by: Anji J - -commit 7ba7cfb799c8928f4963f86a1ad47e2dd56022b2 -Author: Chaitanya Sakinam -Date: Sat Mar 28 00:34:13 2020 +0530 - - staging: fsl_ppfe/eth: "struct firmware" dereference is reduced in many functions - - firmware structure's data variable is the actual elf data. It has been - dereferenced in multiple functions and this has been reduced. - - Signed-off-by: Chaitanya Sakinam - Signed-off-by: Anji J - -commit 443538bb09b979fcc98a58e18a3eb8cebe25ad4f -Author: Chaitanya Sakinam -Date: Sun Mar 29 18:05:50 2020 +0530 - - staging: fsl_ppfe/eth: LF-27 load pfe binaries from FDT - - FDT prepared in uboot now has pfe firmware part of it. - These changes will read the firmware by default from it and tries to load - the elf into the PFE PEs. This help build the pfe driver pasrt of kernel. - - Signed-off-by: Chaitanya Sakinam - Signed-off-by: Anji J - -commit 2b1f551c2aee4550ffca5f86031bc4f5e6ccb848 -Author: Chaitanya Sakinam -Date: Tue Jun 9 15:33:42 2020 +0530 - - staging: fsl_ppfe/eth: proper handling for RGMII delay mode - - The correct setting for the RGMII ports on LS1012ARDB is to - enable delay on both Tx and Rx. So the phy mode to be matched - is PHY_INTERFACE_MODE_RGMII_ID. - - Signed-off-by: Chaitanya Sakinam - Signed-off-by: Anji Jagarlmudi - -commit a95d84b87e743bd7c57b287901524f2cffbf38d7 -Author: Dong Aisheng -Date: Wed Jul 15 16:06:24 2020 +0800 - - LF-1762-2 staging: fsl_ppfe: replace '---help---' in Kconfig files with 'help' - - Update Kconfig to cope with upstream change - commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over - '---help---'"). - - Signed-off-by: Dong Aisheng - -commit 546ef027c2b0768517d903429d56bcd89b919e6d -Author: Chaitanya Sakinam -Date: Wed Jul 15 10:36:07 2020 +0530 - - staging: fsl_ppfe/eth: Nesting level does not match indentation - - corrected nesting level - LF-1661 and Coverity CID: 8879316 - - Signed-off-by: Chaitanya Sakinam - -commit c76a95f776e0f3e1a2c8abc1748c662151e29be5 -Author: Chaitanya Sakinam -Date: Wed Jul 15 11:19:57 2020 +0530 - - staging: fsl_ppfe/eth: Initialized scalar variable - - Proper initialization of scalar variable - LF-1657 and Coverity CID: 3335133 - - Signed-off-by: Chaitanya Sakinam - -commit f48286af915f664c15aa327aaf6d9b61d33eea67 -Author: Chaitanya Sakinam -Date: Wed Jul 15 11:47:50 2020 +0530 - - staging: fsl_ppfe/eth: misspelt variable name - - variable name corrected - LF-1656 and Coverity CID: 3335119 - - Signed-off-by: Chaitanya Sakinam - -commit a5e006f71fce8e76831704b31218f3d57c0b9924 -Author: Chaitanya Sakinam -Date: Wed Jul 15 12:10:47 2020 +0530 - - staging: fsl_ppfe/eth: Avoiding out-of-bound writes - - avoid out-of-bound writes with proper error handling - LF-1654, LF-1652 and Coverity CID: 3335106, 3335090 - - Signed-off-by: Chaitanya Sakinam - -commit 957fde83420b6a74a5e96b2f27183274b04211d9 -Author: Chaitanya Sakinam -Date: Wed Jul 15 13:09:35 2020 +0530 - - staging: fsl_ppfe/eth: Initializing scalar variable - - proper initialization of scalar variable. - LF-1653 and Coverity CID: 3335101 - - Signed-off-by: Chaitanya Sakinam - -commit fae95666a4c992b7f9035ee978e3e289495cbd47 -Author: Chaitanya Sakinam -Date: Wed Jul 15 13:45:50 2020 +0530 - - staging: fsl_ppfe/eth: checking return value - - proper checks added and handled for return value. - LF-1644 and Coverity CID: 241888 - - Signed-off-by: Chaitanya Sakinam - -commit 5bf7baddb22ecafd6064c9062a804bcd17a326cc -Author: Chaitanya Sakinam -Date: Wed Jul 15 14:04:10 2020 +0530 - - staging: fsl_ppfe/eth: Avoid out-of-bound access - - proper handling to avoid out-of-bound access - LF-1642, LF-1641 and Coverity CID: 240910, 240891 - - Signed-off-by: Chaitanya Sakinam - -commit b15d480d66277fc00bc610a91af56263733a4e13 -Author: Chaitanya Sakinam -Date: Fri Jul 31 10:19:00 2020 +0530 - - staging: fsl_ppfe/eth: Avoiding out-of-bound writes - - avoid out-of-bound writes with proper error handling - LF-1654, LF-1652 and Coverity CID: 3335106, 3335090 - - Signed-off-by: Chaitanya Sakinam - -commit 188992fc4d4173c6bb36e924b5833bb092f7d602 -Author: Chaitanya Sakinam -Date: Fri Jul 31 10:23:59 2020 +0530 - - staging: fsl_ppfe/eth: return value init in error case - - proper err return in error case. - LF-1806 and Coverity CID: 10468592 - - Signed-off-by: Chaitanya Sakinam - -commit 26d6dd0bd1331dd07764914033fd8e98777fc165 -Author: Chaitanya Sakinam -Date: Thu Aug 13 12:04:48 2020 +0530 - - staging: fsl_ppfe/eth: Avoid recursion in header inclusion - - Avoiding header inclusions that are not necessary and also that are - causing header inclusion recursion. - - LF-2102 and Coverity CID: 240838 - - Signed-off-by: Chaitanya Sakinam - -commit f18618582d078b87c9ee2e93ebbffee44cd76ec0 -Author: Chaitanya Sakinam -Date: Thu Aug 13 12:28:25 2020 +0530 - - staging: fsl_ppfe/eth: Avoiding return value overwrite - - avoid return value overwrite at the end of function. - LF-2136, LF-2137 and Coverity CID: 8879341, 8879364 - - Signed-off-by: Chaitanya Sakinam - -commit 4cd4e5f325516d91c630311af4d36472ce19124e -Author: Chaitanya Sakinam -Date: Wed Sep 9 17:50:10 2020 +0530 - - staging: fsl_ppfe/eth: LF-27 enabling PFE firmware load from FDT - - The macro, "LOAD_PFEFIRMWARE_FROM_FILESYSTEM" is been disabled to load - the firmware from FDT by default. Enabling the macro will load the - firmware from filesystem. - - Also, the Makefile is now tuned to build pfe as per the config option - - Signed-off-by: Chaitanya Sakinam - -commit 175a310323ccfab0025f2da56799bb3939b65c9d -Author: Chaitanya Sakinam -Date: Thu Apr 9 18:17:48 2020 +0530 - - staging: fsl_ppfe/eth: Ethtool stats correction for IEEE_rx_drop counter - - Due to carrier extended bug the phy counter IEEE_rx_drop counter is - incremented some times and phy reports the packet has crc error. - Because of this PFE revalidates all the packets that are marked crc - error by phy. Now, the counter phy reports is till bogus and this - patch decrements the counter by pfe revalidated (and are crc ok) - counter amount. - - Signed-off-by: Chaitanya Sakinam - -commit a4683911f7a7d71762a90dabf72faadab5766774 -Author: Chaitanya Sakinam -Date: Wed Sep 30 17:20:19 2020 +0530 - - staging: fsl_ppfe/eth: PFE firmware load enhancements - - PFE driver enhancements to load the PE firmware from filesystem - when the firmware is not found in FDT. - - Signed-off-by: Chaitanya Sakinam ---- - .../devicetree/bindings/net/fsl_ppfe/pfe.txt | 199 ++ - MAINTAINERS | 8 + - drivers/staging/Kconfig | 2 + - drivers/staging/Makefile | 1 + - drivers/staging/fsl_ppfe/Kconfig | 21 + - drivers/staging/fsl_ppfe/Makefile | 20 + - drivers/staging/fsl_ppfe/TODO | 2 + - drivers/staging/fsl_ppfe/include/pfe/cbus.h | 78 + - .../staging/fsl_ppfe/include/pfe/cbus/bmu.h | 55 + - .../fsl_ppfe/include/pfe/cbus/class_csr.h | 289 ++ - .../fsl_ppfe/include/pfe/cbus/emac_mtip.h | 242 ++ - .../staging/fsl_ppfe/include/pfe/cbus/gpi.h | 86 + - .../staging/fsl_ppfe/include/pfe/cbus/hif.h | 100 + - .../fsl_ppfe/include/pfe/cbus/hif_nocpy.h | 50 + - .../fsl_ppfe/include/pfe/cbus/tmu_csr.h | 168 ++ - .../fsl_ppfe/include/pfe/cbus/util_csr.h | 61 + - drivers/staging/fsl_ppfe/include/pfe/pfe.h | 372 +++ - drivers/staging/fsl_ppfe/pfe_cdev.c | 258 ++ - drivers/staging/fsl_ppfe/pfe_cdev.h | 41 + - drivers/staging/fsl_ppfe/pfe_ctrl.c | 226 ++ - drivers/staging/fsl_ppfe/pfe_ctrl.h | 100 + - drivers/staging/fsl_ppfe/pfe_debugfs.c | 99 + - drivers/staging/fsl_ppfe/pfe_debugfs.h | 13 + - drivers/staging/fsl_ppfe/pfe_eth.c | 2587 +++++++++++++++++ - drivers/staging/fsl_ppfe/pfe_eth.h | 175 ++ - drivers/staging/fsl_ppfe/pfe_firmware.c | 398 +++ - drivers/staging/fsl_ppfe/pfe_firmware.h | 21 + - drivers/staging/fsl_ppfe/pfe_hal.c | 1517 ++++++++++ - drivers/staging/fsl_ppfe/pfe_hif.c | 1064 +++++++ - drivers/staging/fsl_ppfe/pfe_hif.h | 199 ++ - drivers/staging/fsl_ppfe/pfe_hif_lib.c | 628 ++++ - drivers/staging/fsl_ppfe/pfe_hif_lib.h | 229 ++ - drivers/staging/fsl_ppfe/pfe_hw.c | 164 ++ - drivers/staging/fsl_ppfe/pfe_hw.h | 15 + - .../staging/fsl_ppfe/pfe_ls1012a_platform.c | 383 +++ - drivers/staging/fsl_ppfe/pfe_mod.c | 158 + - drivers/staging/fsl_ppfe/pfe_mod.h | 103 + - drivers/staging/fsl_ppfe/pfe_perfmon.h | 26 + - drivers/staging/fsl_ppfe/pfe_sysfs.c | 840 ++++++ - drivers/staging/fsl_ppfe/pfe_sysfs.h | 17 + - 40 files changed, 11015 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt - create mode 100644 drivers/staging/fsl_ppfe/Kconfig - create mode 100644 drivers/staging/fsl_ppfe/Makefile - create mode 100644 drivers/staging/fsl_ppfe/TODO - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h - create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_hal.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h - create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c - create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h - ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt -@@ -0,0 +1,199 @@ -+============================================================================= -+NXP Programmable Packet Forwarding Engine Device Bindings -+ -+CONTENTS -+ - PFE Node -+ - Ethernet Node -+ -+============================================================================= -+PFE Node -+ -+DESCRIPTION -+ -+PFE Node has all the properties associated with Packet Forwarding Engine block. -+ -+PROPERTIES -+ -+- compatible -+ Usage: required -+ Value type: -+ Definition: Must include "fsl,pfe" -+ -+- reg -+ Usage: required -+ Value type: -+ Definition: A standard property. -+ Specifies the offset of the following registers: -+ - PFE configuration registers -+ - DDR memory used by PFE -+ -+- fsl,pfe-num-interfaces -+ Usage: required -+ Value type: -+ Definition: Must be present. Value can be either one or two. -+ -+- interrupts -+ Usage: required -+ Value type: -+ Definition: Three interrupts are specified in this property. -+ - HIF interrupt -+ - HIF NO COPY interrupt -+ - Wake On LAN interrupt -+ -+- interrupt-names -+ Usage: required -+ Value type: -+ Definition: Following strings are defined for the 3 interrupts. -+ "pfe_hif" - HIF interrupt -+ "pfe_hif_nocpy" - HIF NO COPY interrupt -+ "pfe_wol" - Wake On LAN interrupt -+ -+- memory-region -+ Usage: required -+ Value type: -+ Definition: phandle to a node describing reserved memory used by pfe. -+ Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt -+ -+- fsl,pfe-scfg -+ Usage: required -+ Value type: -+ Definition: phandle for scfg. -+ -+- fsl,rcpm-wakeup -+ Usage: required -+ Value type: -+ Definition: phandle for rcpm. -+ -+- clocks -+ Usage: required -+ Value type: -+ Definition: phandle for clockgen. -+ -+- clock-names -+ Usage: required -+ Value type: -+ Definition: phandle for clock name. -+ -+EXAMPLE -+ -+pfe: pfe@04000000 { -+ compatible = "fsl,pfe"; -+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ -+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ -+ reg-names = "pfe", "pfe-ddr"; -+ fsl,pfe-num-interfaces = <0x2>; -+ interrupts = <0 172 0x4>, /* HIF interrupt */ -+ <0 173 0x4>, /*HIF_NOCPY interrupt */ -+ <0 174 0x4>; /* WoL interrupt */ -+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; -+ memory-region = <&pfe_reserved>; -+ fsl,pfe-scfg = <&scfg 0>; -+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "pfe"; -+ -+ status = "okay"; -+ pfe_mac0: ethernet@0 { -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ }; -+}; -+ -+============================================================================= -+Ethernet Node -+ -+DESCRIPTION -+ -+Ethernet Node has all the properties associated with PFE used by platforms to -+connect to PHY: -+ -+PROPERTIES -+ -+- compatible -+ Usage: required -+ Value type: -+ Definition: Must include "fsl,pfe-gemac-port" -+ -+- reg -+ Usage: required -+ Value type: -+ Definition: A standard property. -+ Specifies the gemacid of the interface. -+ -+- fsl,gemac-bus-id -+ Usage: required -+ Value type: -+ Definition: Must be present. Value should be the id of the bus -+ connected to gemac. -+ -+- fsl,gemac-phy-id (deprecated binding) -+ Usage: required -+ Value type: -+ Definition: This binding shouldn't be used with new platforms. -+ Must be present. Value should be the id of the phy -+ connected to gemac. -+ -+- fsl,mdio-mux-val -+ Usage: required -+ Value type: -+ Definition: Must be present. Value can be either 0 or 2 or 3. -+ This value is used to configure the mux to enable mdio. -+ -+- phy-mode -+ Usage: required -+ Value type: -+ Definition: Must include "sgmii" -+ -+- fsl,pfe-phy-if-flags (deprecated binding) -+ Usage: required -+ Value type: -+ Definition: This binding shouldn't be used with new platforms. -+ Must be present. Value should be 0 by default. -+ If there is not phy connected, this need to be 1. -+ -+- phy-handle -+ Usage: optional -+ Value type: -+ Definition: phandle to the PHY device connected to this device. -+ -+- mdio : A required subnode which specifies the mdio bus in the PFE and used as -+a container for phy nodes according to ../phy.txt. -+ -+EXAMPLE -+ -+ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ phy-handle = <&sgmii_phy1>; -+}; -+ -+ -+ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ phy-handle = <&sgmii_phy2>; -+}; -+ -+mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sgmii_phy1: ethernet-phy@2 { -+ reg = <0x2>; -+ }; -+ -+ sgmii_phy2: ethernet-phy@1 { -+ reg = <0x1>; -+ }; -+}; ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -7068,6 +7068,14 @@ F: drivers/ptp/ptp_qoriq.c - F: drivers/ptp/ptp_qoriq_debugfs.c - F: include/linux/fsl/ptp_qoriq.h - -+FREESCALE QORIQ PPFE ETHERNET DRIVER -+M: Anji Jagarlmudi -+M: Calvin Johnson -+L: netdev@vger.kernel.org -+S: Maintained -+F: drivers/staging/fsl_ppfe -+F: Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt -+ - FREESCALE QUAD SPI DRIVER - M: Han Xu - L: linux-spi@vger.kernel.org ---- a/drivers/staging/Kconfig -+++ b/drivers/staging/Kconfig -@@ -118,4 +118,6 @@ source "drivers/staging/wfx/Kconfig" - - source "drivers/staging/hikey9xx/Kconfig" - -+source "drivers/staging/fsl_ppfe/Kconfig" -+ - endif # STAGING ---- a/drivers/staging/Makefile -+++ b/drivers/staging/Makefile -@@ -49,3 +49,4 @@ obj-$(CONFIG_KPC2000) += kpc2000/ - obj-$(CONFIG_QLGE) += qlge/ - obj-$(CONFIG_WFX) += wfx/ - obj-y += hikey9xx/ -+obj-$(CONFIG_FSL_PPFE) += fsl_ppfe/ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/Kconfig -@@ -0,0 +1,21 @@ -+# -+# Freescale Programmable Packet Forwarding Engine driver -+# -+config FSL_PPFE -+ tristate "Freescale PPFE Driver" -+ select FSL_GUTS -+ default n -+ help -+ Freescale LS1012A SoC has a Programmable Packet Forwarding Engine. -+ It provides two high performance ethernet interfaces. -+ This driver initializes, programs and controls the PPFE. -+ Use this driver to enable network connectivity on LS1012A platforms. -+ -+if FSL_PPFE -+ -+config FSL_PPFE_UTIL_DISABLED -+ bool "Disable PPFE UTIL Processor Engine" -+ help -+ UTIL PE has to be enabled only if required. -+ -+endif # FSL_PPFE ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/Makefile -@@ -0,0 +1,20 @@ -+# -+# Makefile for Freesecale PPFE driver -+# -+ -+ccflags-y += -I $(srctree)/$(src)/include -I $(srctree)/$(src) -+ -+obj-$(CONFIG_FSL_PPFE) += pfe.o -+ -+pfe-y += pfe_mod.o \ -+ pfe_hw.o \ -+ pfe_firmware.o \ -+ pfe_ctrl.o \ -+ pfe_hif.o \ -+ pfe_hif_lib.o\ -+ pfe_eth.o \ -+ pfe_sysfs.o \ -+ pfe_debugfs.o \ -+ pfe_ls1012a_platform.o \ -+ pfe_hal.o \ -+ pfe_cdev.o ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/TODO -@@ -0,0 +1,2 @@ -+TODO: -+ - provide pfe pe monitoring support ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h -@@ -0,0 +1,78 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _CBUS_H_ -+#define _CBUS_H_ -+ -+#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) -+#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) -+#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) -+#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) -+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) -+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) -+#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) -+#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) -+#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) -+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) -+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) -+#define LMEM_SIZE 0x10000 -+#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) -+#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) -+#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) -+#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) -+#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) -+#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) -+ -+/* -+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR -+ * XXX_MEM_ACCESS_ADDR register bit definitions. -+ */ -+#define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */ -+#define PE_MEM_ACCESS_IMEM BIT(15) -+#define PE_MEM_ACCESS_DMEM BIT(16) -+ -+/* Byte Enables of the Internal memory access. These are interpred in BE */ -+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) \ -+ ({ typeof(size) size_ = (size); \ -+ (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; }) -+ -+#include "cbus/emac_mtip.h" -+#include "cbus/gpi.h" -+#include "cbus/bmu.h" -+#include "cbus/hif.h" -+#include "cbus/tmu_csr.h" -+#include "cbus/class_csr.h" -+#include "cbus/hif_nocpy.h" -+#include "cbus/util_csr.h" -+ -+/* PFE cores states */ -+#define CORE_DISABLE 0x00000000 -+#define CORE_ENABLE 0x00000001 -+#define CORE_SW_RESET 0x00000002 -+ -+/* LMEM defines */ -+#define LMEM_HDR_SIZE 0x0010 -+#define LMEM_BUF_SIZE_LN2 0x7 -+#define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2) -+ -+/* DDR defines */ -+#define DDR_HDR_SIZE 0x0100 -+#define DDR_BUF_SIZE_LN2 0xb -+#define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2) -+ -+#endif /* _CBUS_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h -@@ -0,0 +1,55 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _BMU_H_ -+#define _BMU_H_ -+ -+#define BMU_VERSION 0x000 -+#define BMU_CTRL 0x004 -+#define BMU_UCAST_CONFIG 0x008 -+#define BMU_UCAST_BASE_ADDR 0x00c -+#define BMU_BUF_SIZE 0x010 -+#define BMU_BUF_CNT 0x014 -+#define BMU_THRES 0x018 -+#define BMU_INT_SRC 0x020 -+#define BMU_INT_ENABLE 0x024 -+#define BMU_ALLOC_CTRL 0x030 -+#define BMU_FREE_CTRL 0x034 -+#define BMU_FREE_ERR_ADDR 0x038 -+#define BMU_CURR_BUF_CNT 0x03c -+#define BMU_MCAST_CNT 0x040 -+#define BMU_MCAST_ALLOC_CTRL 0x044 -+#define BMU_REM_BUF_CNT 0x048 -+#define BMU_LOW_WATERMARK 0x050 -+#define BMU_HIGH_WATERMARK 0x054 -+#define BMU_INT_MEM_ACCESS 0x100 -+ -+struct BMU_CFG { -+ unsigned long baseaddr; -+ u32 count; -+ u32 size; -+ u32 low_watermark; -+ u32 high_watermark; -+}; -+ -+#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2 -+#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2 -+ -+#define BMU2_MCAST_ALLOC_CTRL (BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL) -+ -+#endif /* _BMU_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h -@@ -0,0 +1,289 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _CLASS_CSR_H_ -+#define _CLASS_CSR_H_ -+ -+/* @file class_csr.h. -+ * class_csr - block containing all the classifier control and status register. -+ * Mapped on CBUS and accessible from all PE's and ARM. -+ */ -+#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000) -+#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004) -+#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010) -+ -+/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */ -+#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014) -+ -+/* LMEM header size for the Classifier block.\ Data in the LMEM -+ * is written from this offset. -+ */ -+#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f) -+ -+/* DDR header size for the Classifier block.\ Data in the DDR -+ * is written from this offset. -+ */ -+#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16) -+ -+#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020) -+ -+/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */ -+#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024) -+ -+/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */ -+#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060) -+ -+/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */ -+#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064) -+ -+/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */ -+ -+/* @name Class PE memory access. Allows external PE's and HOST to -+ * read/write PMEM/DMEM memory ranges for each classifier PE. -+ */ -+/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, -+ * See \ref XXX_MEM_ACCESS_ADDR for details. -+ */ -+#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100) -+ -+/* Internal Memory Access Write Data [31:0] */ -+#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104) -+ -+/* Internal Memory Access Read Data [31:0] */ -+#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108) -+#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114) -+#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118) -+ -+#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c) -+#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120) -+#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124) -+#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128) -+#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c) -+#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130) -+#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134) -+#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138) -+#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c) -+#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140) -+#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144) -+#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148) -+#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c) -+#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150) -+#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154) -+#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158) -+#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c) -+#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160) -+#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164) -+#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168) -+#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c) -+#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170) -+#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174) -+#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178) -+#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c) -+#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180) -+#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184) -+#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188) -+#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c) -+#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190) -+#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194) -+#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198) -+#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c) -+#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0) -+#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4) -+#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8) -+#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac) -+#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0) -+#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4) -+#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8) -+#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc) -+#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0) -+#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4) -+#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8) -+#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc) -+#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0) -+#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4) -+#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8) -+#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc) -+#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0) -+#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4) -+#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8) -+#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec) -+#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0) -+#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4) -+#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8) -+ -+#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200) -+#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204) -+#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208) -+#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c) -+#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210) -+#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214) -+#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218) -+#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c) -+#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220) -+#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224) -+ -+#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228) -+ -+#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c) -+#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230) -+ -+/* (route_entry_size[9:0], route_hash_size[23:16] -+ * (this is actually ln2(size))) -+ */ -+#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234) -+ -+#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff) -+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16) -+ -+#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238) -+ -+#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c) -+#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240) -+#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244) -+#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248) -+#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c) -+#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250) -+#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254) -+ -+#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258) -+#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000) -+/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */ -+ -+#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c) -+ -+#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260) -+#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264) -+#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268) -+#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c) -+#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270) -+#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274) -+#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278) -+#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c) -+#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280) -+#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284) -+#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288) -+#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c) -+ -+#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290) -+#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294) -+ -+#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298) -+#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c) -+ -+#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0) -+ -+#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4) -+#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8) -+#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac) -+#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0) -+#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4) -+#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8) -+ -+#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc) -+ -+/* CLASS defines */ -+#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */ -+#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */ -+ -+/* Can be configured */ -+#define CLASS_PBUF0_BASE_ADDR 0x000 -+/* Can be configured */ -+#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE) -+/* Can be configured */ -+#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE) -+/* Can be configured */ -+#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE) -+ -+#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + \ -+ CLASS_PBUF_HEADER_OFFSET) -+#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + \ -+ CLASS_PBUF_HEADER_OFFSET) -+#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + \ -+ CLASS_PBUF_HEADER_OFFSET) -+#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + \ -+ CLASS_PBUF_HEADER_OFFSET) -+ -+#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | \ -+ CLASS_PBUF0_BASE_ADDR) -+#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | \ -+ CLASS_PBUF2_BASE_ADDR) -+ -+#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\ -+ CLASS_PBUF0_HEADER_BASE_ADDR) -+#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\ -+ CLASS_PBUF2_HEADER_BASE_ADDR) -+ -+#define CLASS_ROUTE_SIZE 128 -+#define CLASS_MAX_ROUTE_SIZE 256 -+#define CLASS_ROUTE_HASH_BITS 20 -+#define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1) -+ -+/* Can be configured */ -+#define CLASS_ROUTE0_BASE_ADDR 0x400 -+/* Can be configured */ -+#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE) -+/* Can be configured */ -+#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE) -+/* Can be configured */ -+#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE) -+ -+#define CLASS_SA_SIZE 128 -+#define CLASS_IPSEC_SA0_BASE_ADDR 0x600 -+/* not used */ -+#define CLASS_IPSEC_SA1_BASE_ADDR (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE) -+/* not used */ -+#define CLASS_IPSEC_SA2_BASE_ADDR (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE) -+/* not used */ -+#define CLASS_IPSEC_SA3_BASE_ADDR (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE) -+ -+/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */ -+#define CLASS_GP_DMEM_BUF_SIZE (2048 - (CLASS_PBUF_SIZE * 4) - \ -+ (CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE)) -+#define CLASS_GP_DMEM_BUF ((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \ -+ CLASS_SA_SIZE)) -+ -+#define TWO_LEVEL_ROUTE BIT(0) -+#define PHYNO_IN_HASH BIT(1) -+#define HW_ROUTE_FETCH BIT(3) -+#define HW_BRIDGE_FETCH BIT(5) -+#define IP_ALIGNED BIT(6) -+#define ARC_HIT_CHECK_EN BIT(7) -+#define CLASS_TOE BIT(11) -+#define HASH_NORMAL (0 << 12) -+#define HASH_CRC_PORT BIT(12) -+#define HASH_CRC_IP (2 << 12) -+#define HASH_CRC_PORT_IP (3 << 12) -+#define QB2BUS_LE BIT(15) -+ -+#define TCP_CHKSUM_DROP BIT(0) -+#define UDP_CHKSUM_DROP BIT(1) -+#define IPV4_CHKSUM_DROP BIT(9) -+ -+/*CLASS_HIF_PARSE bits*/ -+#define HIF_PKT_CLASS_EN BIT(0) -+#define HIF_PKT_OFFSET(ofst) (((ofst) & 0xF) << 1) -+ -+struct class_cfg { -+ u32 toe_mode; -+ unsigned long route_table_baseaddr; -+ u32 route_table_hash_bits; -+ u32 pe_sys_clk_ratio; -+ u32 resume; -+}; -+ -+#endif /* _CLASS_CSR_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h -@@ -0,0 +1,242 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _EMAC_H_ -+#define _EMAC_H_ -+ -+#include -+ -+#define EMAC_IEVENT_REG 0x004 -+#define EMAC_IMASK_REG 0x008 -+#define EMAC_R_DES_ACTIVE_REG 0x010 -+#define EMAC_X_DES_ACTIVE_REG 0x014 -+#define EMAC_ECNTRL_REG 0x024 -+#define EMAC_MII_DATA_REG 0x040 -+#define EMAC_MII_CTRL_REG 0x044 -+#define EMAC_MIB_CTRL_STS_REG 0x064 -+#define EMAC_RCNTRL_REG 0x084 -+#define EMAC_TCNTRL_REG 0x0C4 -+#define EMAC_PHY_ADDR_LOW 0x0E4 -+#define EMAC_PHY_ADDR_HIGH 0x0E8 -+#define EMAC_GAUR 0x120 -+#define EMAC_GALR 0x124 -+#define EMAC_TFWR_STR_FWD 0x144 -+#define EMAC_RX_SECTION_FULL 0x190 -+#define EMAC_RX_SECTION_EMPTY 0x194 -+#define EMAC_TX_SECTION_EMPTY 0x1A0 -+#define EMAC_TRUNC_FL 0x1B0 -+ -+#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ -+#define RMON_T_PACKETS 0x204 /* RMON TX packet count */ -+#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ -+#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */ -+#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ -+#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ -+#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ -+#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */ -+#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ -+#define RMON_T_COL 0x224 /* RMON TX collision count */ -+#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ -+#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */ -+#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ -+#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ -+#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ -+#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */ -+#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ -+#define RMON_T_OCTETS 0x244 /* RMON TX octets */ -+#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ -+#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */ -+#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ -+#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ -+#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ -+#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */ -+#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ -+#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ -+#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ -+#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */ -+#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ -+#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ -+#define RMON_R_PACKETS 0x284 /* RMON RX packet count */ -+#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ -+#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */ -+#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ -+#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ -+#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ -+#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */ -+#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ -+#define RMON_R_RESVD_O 0x2a4 /* Reserved */ -+#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */ -+#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */ -+#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */ -+#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */ -+#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */ -+#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */ -+#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */ -+#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */ -+#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */ -+#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */ -+#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */ -+#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */ -+#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */ -+#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */ -+#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */ -+ -+#define EMAC_SMAC_0_0 0x500 /*Supplemental MAC Address 0 (RW).*/ -+#define EMAC_SMAC_0_1 0x504 /*Supplemental MAC Address 0 (RW).*/ -+ -+/* GEMAC definitions and settings */ -+ -+#define EMAC_PORT_0 0 -+#define EMAC_PORT_1 1 -+ -+/* GEMAC Bit definitions */ -+#define EMAC_IEVENT_HBERR 0x80000000 -+#define EMAC_IEVENT_BABR 0x40000000 -+#define EMAC_IEVENT_BABT 0x20000000 -+#define EMAC_IEVENT_GRA 0x10000000 -+#define EMAC_IEVENT_TXF 0x08000000 -+#define EMAC_IEVENT_TXB 0x04000000 -+#define EMAC_IEVENT_RXF 0x02000000 -+#define EMAC_IEVENT_RXB 0x01000000 -+#define EMAC_IEVENT_MII 0x00800000 -+#define EMAC_IEVENT_EBERR 0x00400000 -+#define EMAC_IEVENT_LC 0x00200000 -+#define EMAC_IEVENT_RL 0x00100000 -+#define EMAC_IEVENT_UN 0x00080000 -+ -+#define EMAC_IMASK_HBERR 0x80000000 -+#define EMAC_IMASK_BABR 0x40000000 -+#define EMAC_IMASKT_BABT 0x20000000 -+#define EMAC_IMASK_GRA 0x10000000 -+#define EMAC_IMASKT_TXF 0x08000000 -+#define EMAC_IMASK_TXB 0x04000000 -+#define EMAC_IMASKT_RXF 0x02000000 -+#define EMAC_IMASK_RXB 0x01000000 -+#define EMAC_IMASK_MII 0x00800000 -+#define EMAC_IMASK_EBERR 0x00400000 -+#define EMAC_IMASK_LC 0x00200000 -+#define EMAC_IMASKT_RL 0x00100000 -+#define EMAC_IMASK_UN 0x00080000 -+ -+#define EMAC_RCNTRL_MAX_FL_SHIFT 16 -+#define EMAC_RCNTRL_LOOP 0x00000001 -+#define EMAC_RCNTRL_DRT 0x00000002 -+#define EMAC_RCNTRL_MII_MODE 0x00000004 -+#define EMAC_RCNTRL_PROM 0x00000008 -+#define EMAC_RCNTRL_BC_REJ 0x00000010 -+#define EMAC_RCNTRL_FCE 0x00000020 -+#define EMAC_RCNTRL_RGMII 0x00000040 -+#define EMAC_RCNTRL_SGMII 0x00000080 -+#define EMAC_RCNTRL_RMII 0x00000100 -+#define EMAC_RCNTRL_RMII_10T 0x00000200 -+#define EMAC_RCNTRL_CRC_FWD 0x00004000 -+ -+#define EMAC_TCNTRL_GTS 0x00000001 -+#define EMAC_TCNTRL_HBC 0x00000002 -+#define EMAC_TCNTRL_FDEN 0x00000004 -+#define EMAC_TCNTRL_TFC_PAUSE 0x00000008 -+#define EMAC_TCNTRL_RFC_PAUSE 0x00000010 -+ -+#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */ -+#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */ -+#define EMAC_ECNTRL_MAGIC_ENA 0x00000004 -+#define EMAC_ECNTRL_SLEEP 0x00000008 -+#define EMAC_ECNTRL_SPEED 0x00000020 -+#define EMAC_ECNTRL_DBSWAP 0x00000100 -+ -+#define EMAC_X_WMRK_STRFWD 0x00000100 -+ -+#define EMAC_X_DES_ACTIVE_TDAR 0x01000000 -+#define EMAC_R_DES_ACTIVE_RDAR 0x01000000 -+ -+#define EMAC_RX_SECTION_EMPTY_V 0x00010006 -+/* -+ * The possible operating speeds of the MAC, currently supporting 10, 100 and -+ * 1000Mb modes. -+ */ -+enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS}; -+ -+/* MII-related definitios */ -+#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ -+#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ -+#define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */ -+#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ -+#define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */ -+#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ -+#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ -+#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */ -+#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ -+ -+#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ -+#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */ -+#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ -+#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */ -+ -+#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \ -+ EMAC_MII_DATA_RA_SHIFT) -+#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \ -+ EMAC_MII_DATA_PA_SHIFT) -+#define EMAC_MII_DATA(v) ((v) & 0xffff) -+ -+#define EMAC_MII_SPEED_SHIFT 1 -+#define EMAC_HOLDTIME_SHIFT 8 -+#define EMAC_HOLDTIME_MASK 0x7 -+#define EMAC_HOLDTIME(v) (((v) & EMAC_HOLDTIME_MASK) << \ -+ EMAC_HOLDTIME_SHIFT) -+ -+/* -+ * The Address organisation for the MAC device. All addresses are split into -+ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of -+ * the address and the other field are the high order bits - this may be 16-bits -+ * in the case of MAC addresses, or 32-bits for the hash address. -+ * In terms of memory storage, the first item (bottom) is assumed to be at a -+ * lower address location than 'top'. i.e. top should be at address location of -+ * 'bottom' + 4 bytes. -+ */ -+struct pfe_mac_addr { -+ u32 bottom; /* Lower 32-bits of address. */ -+ u32 top; /* Upper 32-bits of address. */ -+}; -+ -+/* -+ * The following is the organisation of the address filters section of the MAC -+ * registers. The Cadence MAC contains four possible specific address match -+ * addresses, if an incoming frame corresponds to any one of these four -+ * addresses then the frame will be copied to memory. -+ * It is not necessary for all four of the address match registers to be -+ * programmed, this is application dependent. -+ */ -+struct spec_addr { -+ struct pfe_mac_addr one; /* Specific address register 1. */ -+ struct pfe_mac_addr two; /* Specific address register 2. */ -+ struct pfe_mac_addr three; /* Specific address register 3. */ -+ struct pfe_mac_addr four; /* Specific address register 4. */ -+}; -+ -+struct gemac_cfg { -+ u32 mode; -+ u32 speed; -+ u32 duplex; -+}; -+ -+/* EMAC Hash size */ -+#define EMAC_HASH_REG_BITS 64 -+ -+#define EMAC_SPEC_ADDR_MAX 4 -+ -+#endif /* _EMAC_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h -@@ -0,0 +1,86 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _GPI_H_ -+#define _GPI_H_ -+ -+#define GPI_VERSION 0x00 -+#define GPI_CTRL 0x04 -+#define GPI_RX_CONFIG 0x08 -+#define GPI_HDR_SIZE 0x0c -+#define GPI_BUF_SIZE 0x10 -+#define GPI_LMEM_ALLOC_ADDR 0x14 -+#define GPI_LMEM_FREE_ADDR 0x18 -+#define GPI_DDR_ALLOC_ADDR 0x1c -+#define GPI_DDR_FREE_ADDR 0x20 -+#define GPI_CLASS_ADDR 0x24 -+#define GPI_DRX_FIFO 0x28 -+#define GPI_TRX_FIFO 0x2c -+#define GPI_INQ_PKTPTR 0x30 -+#define GPI_DDR_DATA_OFFSET 0x34 -+#define GPI_LMEM_DATA_OFFSET 0x38 -+#define GPI_TMLF_TX 0x4c -+#define GPI_DTX_ASEQ 0x50 -+#define GPI_FIFO_STATUS 0x54 -+#define GPI_FIFO_DEBUG 0x58 -+#define GPI_TX_PAUSE_TIME 0x5c -+#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60 -+#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64 -+#define GPI_TOE_CHKSUM_EN 0x68 -+#define GPI_OVERRUN_DROPCNT 0x6c -+#define GPI_CSR_MTIP_PAUSE_REG 0x74 -+#define GPI_CSR_MTIP_PAUSE_QUANTUM 0x78 -+#define GPI_CSR_RX_CNT 0x7c -+#define GPI_CSR_TX_CNT 0x80 -+#define GPI_CSR_DEBUG1 0x84 -+#define GPI_CSR_DEBUG2 0x88 -+ -+struct gpi_cfg { -+ u32 lmem_rtry_cnt; -+ u32 tmlf_txthres; -+ u32 aseq_len; -+ u32 mtip_pause_reg; -+}; -+ -+/* GPI commons defines */ -+#define GPI_LMEM_BUF_EN 0x1 -+#define GPI_DDR_BUF_EN 0x1 -+ -+/* EGPI 1 defines */ -+#define EGPI1_LMEM_RTRY_CNT 0x40 -+#define EGPI1_TMLF_TXTHRES 0xBC -+#define EGPI1_ASEQ_LEN 0x50 -+ -+/* EGPI 2 defines */ -+#define EGPI2_LMEM_RTRY_CNT 0x40 -+#define EGPI2_TMLF_TXTHRES 0xBC -+#define EGPI2_ASEQ_LEN 0x40 -+ -+/* EGPI 3 defines */ -+#define EGPI3_LMEM_RTRY_CNT 0x40 -+#define EGPI3_TMLF_TXTHRES 0xBC -+#define EGPI3_ASEQ_LEN 0x40 -+ -+/* HGPI defines */ -+#define HGPI_LMEM_RTRY_CNT 0x40 -+#define HGPI_TMLF_TXTHRES 0xBC -+#define HGPI_ASEQ_LEN 0x40 -+ -+#define EGPI_PAUSE_TIME 0x000007D0 -+#define EGPI_PAUSE_ENABLE 0x40000000 -+#endif /* _GPI_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h -@@ -0,0 +1,100 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _HIF_H_ -+#define _HIF_H_ -+ -+/* @file hif.h. -+ * hif - PFE hif block control and status register. -+ * Mapped on CBUS and accessible from all PE's and ARM. -+ */ -+#define HIF_VERSION (HIF_BASE_ADDR + 0x00) -+#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04) -+#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08) -+#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c) -+#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10) -+#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14) -+#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20) -+#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24) -+#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30) -+#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34) -+#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38) -+#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c) -+#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40) -+#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44) -+#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48) -+#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c) -+#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50) -+ -+/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */ -+#define HIF_INT BIT(0) -+#define HIF_RXBD_INT BIT(1) -+#define HIF_RXPKT_INT BIT(2) -+#define HIF_TXBD_INT BIT(3) -+#define HIF_TXPKT_INT BIT(4) -+ -+/* HIF_TX_CTRL bits */ -+#define HIF_CTRL_DMA_EN BIT(0) -+#define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1) -+#define HIF_CTRL_BDP_CH_START_WSTB BIT(2) -+ -+/* HIF_RX_STATUS bits */ -+#define BDP_CSR_RX_DMA_ACTV BIT(16) -+ -+/* HIF_INT_ENABLE bits */ -+#define HIF_INT_EN BIT(0) -+#define HIF_RXBD_INT_EN BIT(1) -+#define HIF_RXPKT_INT_EN BIT(2) -+#define HIF_TXBD_INT_EN BIT(3) -+#define HIF_TXPKT_INT_EN BIT(4) -+ -+/* HIF_POLL_CTRL bits*/ -+#define HIF_RX_POLL_CTRL_CYCLE 0x0400 -+#define HIF_TX_POLL_CTRL_CYCLE 0x0400 -+ -+/* HIF_INT_COAL bits*/ -+#define HIF_INT_COAL_ENABLE BIT(31) -+ -+/* Buffer descriptor control bits */ -+#define BD_CTRL_BUFLEN_MASK 0x3fff -+#define BD_BUF_LEN(x) ((x) & BD_CTRL_BUFLEN_MASK) -+#define BD_CTRL_CBD_INT_EN BIT(16) -+#define BD_CTRL_PKT_INT_EN BIT(17) -+#define BD_CTRL_LIFM BIT(18) -+#define BD_CTRL_LAST_BD BIT(19) -+#define BD_CTRL_DIR BIT(20) -+#define BD_CTRL_LMEM_CPY BIT(21) /* Valid only for HIF_NOCPY */ -+#define BD_CTRL_PKT_XFER BIT(24) -+#define BD_CTRL_DESC_EN BIT(31) -+#define BD_CTRL_PARSE_DISABLE BIT(25) -+#define BD_CTRL_BRFETCH_DISABLE BIT(26) -+#define BD_CTRL_RTFETCH_DISABLE BIT(27) -+ -+/* Buffer descriptor status bits*/ -+#define BD_STATUS_CONN_ID(x) ((x) & 0xffff) -+#define BD_STATUS_DIR_PROC_ID BIT(16) -+#define BD_STATUS_CONN_ID_EN BIT(17) -+#define BD_STATUS_PE2PROC_ID(x) (((x) & 7) << 18) -+#define BD_STATUS_LE_DATA BIT(21) -+#define BD_STATUS_CHKSUM_EN BIT(22) -+ -+/* HIF Buffer descriptor status bits */ -+#define DIR_PROC_ID BIT(16) -+#define PROC_ID(id) ((id) << 18) -+ -+#endif /* _HIF_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h -@@ -0,0 +1,50 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _HIF_NOCPY_H_ -+#define _HIF_NOCPY_H_ -+ -+#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00) -+#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04) -+#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08) -+#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c) -+#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10) -+#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14) -+#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20) -+#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24) -+#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30) -+#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34) -+#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38) -+#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c) -+#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40) -+#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44) -+#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48) -+#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c) -+#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50) -+#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54) -+#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60) -+#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64) -+#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68) -+#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70) -+#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74) -+#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c) -+#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80) -+#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84) -+#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90) -+ -+#endif /* _HIF_NOCPY_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h -@@ -0,0 +1,168 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _TMU_CSR_H_ -+#define _TMU_CSR_H_ -+ -+#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000) -+#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004) -+#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008) -+#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c) -+#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010) -+#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014) -+#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018) -+#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c) -+#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020) -+#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024) -+#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028) -+#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c) -+#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030) -+#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034) -+#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038) -+#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c) -+#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040) -+#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044) -+#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048) -+#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c) -+#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050) -+#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054) -+#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058) -+#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c) -+#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060) -+#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064) -+#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068) -+#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c) -+#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070) -+#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074) -+#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078) -+#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c) -+#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080) -+#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084) -+#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088) -+#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c) -+#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090) -+#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094) -+#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098) -+#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c) -+#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0) -+#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4) -+#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8) -+#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac) -+#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0) -+#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4) -+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. -+ * This is a global Enable for all schedulers in PHY0 -+ */ -+#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8) -+ -+#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc) -+#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0) -+#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4) -+#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8) -+#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc) -+#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0) -+#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4) -+#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8) -+#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc) -+#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0) -+ -+/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory -+ * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of -+ * the internal memory. This address is used to access both the PM and DM of -+ * all the PE's -+ */ -+#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4) -+ -+/* Internal Memory Access Write Data */ -+#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8) -+/* Internal Memory Access Read Data. The commands are blocked -+ * at the mem_access only -+ */ -+#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec) -+ -+/* [31:0] PHY0 in queue address (must be initialized with one of the -+ * xxx_INQ_PKTPTR cbus addresses) -+ */ -+#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0) -+/* [31:0] PHY1 in queue address (must be initialized with one of the -+ * xxx_INQ_PKTPTR cbus addresses) -+ */ -+#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4) -+/* [31:0] PHY2 in queue address (must be initialized with one of the -+ * xxx_INQ_PKTPTR cbus addresses) -+ */ -+#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8) -+/* [31:0] PHY3 in queue address (must be initialized with one of the -+ * xxx_INQ_PKTPTR cbus addresses) -+ */ -+#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc) -+#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100) -+#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104) -+ -+#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108) -+#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c) -+#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110) -+ -+#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114) -+#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118) -+#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c) -+/* [31:0] PHY4 in queue address (must be initialized with one of the -+ * xxx_INQ_PKTPTR cbus addresses) -+ */ -+#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134) -+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. -+ * This is a global Enable for all schedulers in PHY1 -+ */ -+#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138) -+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. -+ * This is a global Enable for all schedulers in PHY2 -+ */ -+#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c) -+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. -+ * This is a global Enable for all schedulers in PHY3 -+ */ -+#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140) -+#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144) -+/* [31:0] PHY5 in queue address (must be initialized with one of the -+ * xxx_INQ_PKTPTR cbus addresses) -+ */ -+#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148) -+ -+#define SW_RESET BIT(0) /* Global software reset */ -+#define INQ_RESET BIT(2) -+#define TEQ_RESET BIT(3) -+#define TDQ_RESET BIT(4) -+#define PE_RESET BIT(5) -+#define MEM_INIT BIT(6) -+#define MEM_INIT_DONE BIT(7) -+#define LLM_INIT BIT(8) -+#define LLM_INIT_DONE BIT(9) -+#define ECC_MEM_INIT_DONE BIT(10) -+ -+struct tmu_cfg { -+ u32 pe_sys_clk_ratio; -+ unsigned long llm_base_addr; -+ u32 llm_queue_len; -+}; -+ -+/* Not HW related for pfe_ctrl / pfe common defines */ -+#define DEFAULT_MAX_QDEPTH 80 -+#define DEFAULT_Q0_QDEPTH 511 /*We keep one large queue for host tx qos */ -+#define DEFAULT_TMU3_QDEPTH 127 -+ -+#endif /* _TMU_CSR_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h -@@ -0,0 +1,61 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _UTIL_CSR_H_ -+#define _UTIL_CSR_H_ -+ -+#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000) -+#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004) -+#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010) -+ -+#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014) -+ -+#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020) -+#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024) -+#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060) -+#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064) -+ -+#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100) -+#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104) -+#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108) -+ -+#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114) -+#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118) -+ -+#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200) -+#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204) -+#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208) -+#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c) -+#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210) -+#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214) -+#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218) -+#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c) -+#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220) -+#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224) -+ -+#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228) -+#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c) -+#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230) -+ -+#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234) -+ -+struct util_cfg { -+ u32 pe_sys_clk_ratio; -+}; -+ -+#endif /* _UTIL_CSR_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h -@@ -0,0 +1,372 @@ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#ifndef _PFE_H_ -+#define _PFE_H_ -+ -+#include "cbus.h" -+ -+#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) -+/* -+ * Only valid for mem access register interface -+ */ -+#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20)) -+#define CLASS_DMEM_SIZE 0x00002000 -+#define CLASS_IMEM_SIZE 0x00008000 -+ -+#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) -+/* -+ * Only valid for mem access register interface -+ */ -+#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20)) -+#define TMU_DMEM_SIZE 0x00000800 -+#define TMU_IMEM_SIZE 0x00002000 -+ -+#define UTIL_DMEM_BASE_ADDR 0x00000000 -+#define UTIL_DMEM_SIZE 0x00002000 -+ -+#define PE_LMEM_BASE_ADDR 0xc3010000 -+#define PE_LMEM_SIZE 0x8000 -+#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE) -+ -+#define DMEM_BASE_ADDR 0x00000000 -+#define DMEM_SIZE 0x2000 /* TMU has less... */ -+#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE) -+ -+#define PMEM_BASE_ADDR 0x00010000 -+#define PMEM_SIZE 0x8000 /* TMU has less... */ -+#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE) -+ -+/* These check memory ranges from PE point of view/memory map */ -+#define IS_DMEM(addr, len) \ -+ ({ typeof(addr) addr_ = (addr); \ -+ ((unsigned long)(addr_) >= DMEM_BASE_ADDR) && \ -+ (((unsigned long)(addr_) + (len)) <= DMEM_END); }) -+ -+#define IS_PMEM(addr, len) \ -+ ({ typeof(addr) addr_ = (addr); \ -+ ((unsigned long)(addr_) >= PMEM_BASE_ADDR) && \ -+ (((unsigned long)(addr_) + (len)) <= PMEM_END); }) -+ -+#define IS_PE_LMEM(addr, len) \ -+ ({ typeof(addr) addr_ = (addr); \ -+ ((unsigned long)(addr_) >= \ -+ PE_LMEM_BASE_ADDR) && \ -+ (((unsigned long)(addr_) + \ -+ (len)) <= PE_LMEM_END); }) -+ -+#define IS_PFE_LMEM(addr, len) \ -+ ({ typeof(addr) addr_ = (addr); \ -+ ((unsigned long)(addr_) >= \ -+ CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && \ -+ (((unsigned long)(addr_) + (len)) <= \ -+ CBUS_VIRT_TO_PFE(LMEM_END)); }) -+ -+#define __IS_PHYS_DDR(addr, len) \ -+ ({ typeof(addr) addr_ = (addr); \ -+ ((unsigned long)(addr_) >= \ -+ DDR_PHYS_BASE_ADDR) && \ -+ (((unsigned long)(addr_) + (len)) <= \ -+ DDR_PHYS_END); }) -+ -+#define IS_PHYS_DDR(addr, len) __IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len) -+ -+/* -+ * If using a run-time virtual address for the cbus base address use this code -+ */ -+extern void *cbus_base_addr; -+extern void *ddr_base_addr; -+extern unsigned long ddr_phys_base_addr; -+extern unsigned int ddr_size; -+ -+#define CBUS_BASE_ADDR cbus_base_addr -+#define DDR_PHYS_BASE_ADDR ddr_phys_base_addr -+#define DDR_BASE_ADDR ddr_base_addr -+#define DDR_SIZE ddr_size -+ -+#define DDR_PHYS_END (DDR_PHYS_BASE_ADDR + DDR_SIZE) -+ -+#define LS1012A_PFE_RESET_WA /* -+ * PFE doesn't have global reset and re-init -+ * should takecare few things to make PFE -+ * functional after reset -+ */ -+#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /* CBUS physical base address -+ * as seen by PE's. -+ */ -+/* CBUS physical base address as seen by PE's. */ -+#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE 0xc0000000 -+ -+#define DDR_PHYS_TO_PFE(p) (((unsigned long int)(p)) & 0x7FFFFFFF) -+#define DDR_PFE_TO_PHYS(p) (((unsigned long int)(p)) | 0x80000000) -+#define CBUS_PHYS_TO_PFE(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + \ -+ PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE) -+/* Translates to PFE address map */ -+ -+#define DDR_PHYS_TO_VIRT(p) (((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR) -+#define DDR_VIRT_TO_PHYS(v) (((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR) -+#define DDR_VIRT_TO_PFE(p) (DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p))) -+ -+#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + \ -+ PFE_CBUS_PHYS_BASE_ADDR) -+#define CBUS_PFE_TO_VIRT(p) (((unsigned long int)(p) - \ -+ PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR) -+ -+/* The below part of the code is used in QOS control driver from host */ -+#define TMU_APB_BASE_ADDR 0xc1000000 /* TMU base address seen by -+ * pe's -+ */ -+ -+enum { -+ CLASS0_ID = 0, -+ CLASS1_ID, -+ CLASS2_ID, -+ CLASS3_ID, -+ CLASS4_ID, -+ CLASS5_ID, -+ TMU0_ID, -+ TMU1_ID, -+ TMU2_ID, -+ TMU3_ID, -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ UTIL_ID, -+#endif -+ MAX_PE -+}; -+ -+#define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) |\ -+ BIT(CLASS2_ID) | BIT(CLASS3_ID) |\ -+ BIT(CLASS4_ID) | BIT(CLASS5_ID)) -+#define CLASS_MAX_ID CLASS5_ID -+ -+#define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) |\ -+ BIT(TMU3_ID)) -+ -+#define TMU_MAX_ID TMU3_ID -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+#define UTIL_MASK BIT(UTIL_ID) -+#endif -+ -+struct pe_status { -+ u32 cpu_state; -+ u32 activity_counter; -+ u32 rx; -+ union { -+ u32 tx; -+ u32 tmu_qstatus; -+ }; -+ u32 drop; -+#if defined(CFG_PE_DEBUG) -+ u32 debug_indicator; -+ u32 debug[16]; -+#endif -+} __aligned(16); -+ -+struct pe_sync_mailbox { -+ u32 stop; -+ u32 stopped; -+}; -+ -+/* Drop counter definitions */ -+ -+#define CLASS_NUM_DROP_COUNTERS 13 -+#define UTIL_NUM_DROP_COUNTERS 8 -+ -+/* PE information. -+ * Structure containing PE's specific information. It is used to create -+ * generic C functions common to all PE's. -+ * Before using the library functions this structure needs to be initialized -+ * with the different registers virtual addresses -+ * (according to the ARM MMU mmaping). The default initialization supports a -+ * virtual == physical mapping. -+ */ -+struct pe_info { -+ u32 dmem_base_addr; /* PE's dmem base address */ -+ u32 pmem_base_addr; /* PE's pmem base address */ -+ u32 pmem_size; /* PE's pmem size */ -+ -+ void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA register -+ * address -+ */ -+ void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR register -+ * address -+ */ -+ void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA register -+ * address -+ */ -+}; -+ -+void pe_lmem_read(u32 *dst, u32 len, u32 offset); -+void pe_lmem_write(u32 *src, u32 len, u32 offset); -+ -+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); -+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len); -+ -+u32 pe_pmem_read(int id, u32 addr, u8 size); -+ -+void pe_dmem_write(int id, u32 val, u32 addr, u8 size); -+u32 pe_dmem_read(int id, u32 addr, u8 size); -+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len); -+void class_pe_lmem_memset(u32 dst, int val, unsigned int len); -+void class_bus_write(u32 val, u32 addr, u8 size); -+u32 class_bus_read(u32 addr, u8 size); -+ -+#define class_bus_readl(addr) class_bus_read(addr, 4) -+#define class_bus_readw(addr) class_bus_read(addr, 2) -+#define class_bus_readb(addr) class_bus_read(addr, 1) -+ -+#define class_bus_writel(val, addr) class_bus_write(val, addr, 4) -+#define class_bus_writew(val, addr) class_bus_write(val, addr, 2) -+#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1) -+ -+#define pe_dmem_readl(id, addr) pe_dmem_read(id, addr, 4) -+#define pe_dmem_readw(id, addr) pe_dmem_read(id, addr, 2) -+#define pe_dmem_readb(id, addr) pe_dmem_read(id, addr, 1) -+ -+#define pe_dmem_writel(id, val, addr) pe_dmem_write(id, val, addr, 4) -+#define pe_dmem_writew(id, val, addr) pe_dmem_write(id, val, addr, 2) -+#define pe_dmem_writeb(id, val, addr) pe_dmem_write(id, val, addr, 1) -+ -+/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */ -+int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr, -+ struct device *dev); -+ -+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, -+ unsigned int ddr_size); -+void bmu_init(void *base, struct BMU_CFG *cfg); -+void bmu_reset(void *base); -+void bmu_enable(void *base); -+void bmu_disable(void *base); -+void bmu_set_config(void *base, struct BMU_CFG *cfg); -+ -+/* -+ * An enumerated type for loopback values. This can be one of three values, no -+ * loopback -normal operation, local loopback with internal loopback module of -+ * MAC or PHY loopback which is through the external PHY. -+ */ -+#ifndef __MAC_LOOP_ENUM__ -+#define __MAC_LOOP_ENUM__ -+enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL}; -+#endif -+ -+void gemac_init(void *base, void *config); -+void gemac_disable_rx_checksum_offload(void *base); -+void gemac_enable_rx_checksum_offload(void *base); -+void gemac_set_speed(void *base, enum mac_speed gem_speed); -+void gemac_set_duplex(void *base, int duplex); -+void gemac_set_mode(void *base, int mode); -+void gemac_enable(void *base); -+void gemac_tx_disable(void *base); -+void gemac_tx_enable(void *base); -+void gemac_disable(void *base); -+void gemac_reset(void *base); -+void gemac_set_address(void *base, struct spec_addr *addr); -+struct spec_addr gemac_get_address(void *base); -+void gemac_set_loop(void *base, enum mac_loop gem_loop); -+void gemac_set_laddr1(void *base, struct pfe_mac_addr *address); -+void gemac_set_laddr2(void *base, struct pfe_mac_addr *address); -+void gemac_set_laddr3(void *base, struct pfe_mac_addr *address); -+void gemac_set_laddr4(void *base, struct pfe_mac_addr *address); -+void gemac_set_laddrN(void *base, struct pfe_mac_addr *address, -+ unsigned int entry_index); -+void gemac_clear_laddr1(void *base); -+void gemac_clear_laddr2(void *base); -+void gemac_clear_laddr3(void *base); -+void gemac_clear_laddr4(void *base); -+void gemac_clear_laddrN(void *base, unsigned int entry_index); -+struct pfe_mac_addr gemac_get_hash(void *base); -+void gemac_set_hash(void *base, struct pfe_mac_addr *hash); -+struct pfe_mac_addr gem_get_laddr1(void *base); -+struct pfe_mac_addr gem_get_laddr2(void *base); -+struct pfe_mac_addr gem_get_laddr3(void *base); -+struct pfe_mac_addr gem_get_laddr4(void *base); -+struct pfe_mac_addr gem_get_laddrN(void *base, unsigned int entry_index); -+void gemac_set_config(void *base, struct gemac_cfg *cfg); -+void gemac_allow_broadcast(void *base); -+void gemac_no_broadcast(void *base); -+void gemac_enable_1536_rx(void *base); -+void gemac_disable_1536_rx(void *base); -+void gemac_set_rx_max_fl(void *base, int mtu); -+void gemac_enable_rx_jmb(void *base); -+void gemac_disable_rx_jmb(void *base); -+void gemac_enable_stacked_vlan(void *base); -+void gemac_disable_stacked_vlan(void *base); -+void gemac_enable_pause_rx(void *base); -+void gemac_disable_pause_rx(void *base); -+void gemac_enable_copy_all(void *base); -+void gemac_disable_copy_all(void *base); -+void gemac_set_bus_width(void *base, int width); -+void gemac_set_wol(void *base, u32 wol_conf); -+ -+void gpi_init(void *base, struct gpi_cfg *cfg); -+void gpi_reset(void *base); -+void gpi_enable(void *base); -+void gpi_disable(void *base); -+void gpi_set_config(void *base, struct gpi_cfg *cfg); -+ -+void class_init(struct class_cfg *cfg); -+void class_reset(void); -+void class_enable(void); -+void class_disable(void); -+void class_set_config(struct class_cfg *cfg); -+ -+void tmu_reset(void); -+void tmu_init(struct tmu_cfg *cfg); -+void tmu_enable(u32 pe_mask); -+void tmu_disable(u32 pe_mask); -+u32 tmu_qstatus(u32 if_id); -+u32 tmu_pkts_processed(u32 if_id); -+ -+void util_init(struct util_cfg *cfg); -+void util_reset(void); -+void util_enable(void); -+void util_disable(void); -+ -+void hif_init(void); -+void hif_tx_enable(void); -+void hif_tx_disable(void); -+void hif_rx_enable(void); -+void hif_rx_disable(void); -+ -+/* Get Chip Revision level -+ * -+ */ -+static inline unsigned int CHIP_REVISION(void) -+{ -+ /*For LS1012A return always 1 */ -+ return 1; -+} -+ -+/* Start HIF rx DMA -+ * -+ */ -+static inline void hif_rx_dma_start(void) -+{ -+ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL); -+} -+ -+/* Start HIF tx DMA -+ * -+ */ -+static inline void hif_tx_dma_start(void) -+{ -+ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL); -+} -+ -+#endif /* _PFE_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_cdev.c -@@ -0,0 +1,258 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2018 NXP -+ */ -+ -+/* @pfe_cdev.c. -+ * Dummy device representing the PFE US in userspace. -+ * - used for interacting with the kernel layer for link status -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "pfe_cdev.h" -+#include "pfe_mod.h" -+ -+static int pfe_majno; -+static struct class *pfe_char_class; -+static struct device *pfe_char_dev; -+struct eventfd_ctx *g_trigger; -+ -+struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT]; -+ -+static int pfe_cdev_open(struct inode *inp, struct file *fp) -+{ -+ pr_debug("PFE CDEV device opened.\n"); -+ return 0; -+} -+ -+static ssize_t pfe_cdev_read(struct file *fp, char *buf, -+ size_t len, loff_t *off) -+{ -+ int ret = 0; -+ -+ pr_info("PFE CDEV attempt copying (%lu) size of user.\n", -+ sizeof(link_states)); -+ -+ pr_debug("Dump link_state on screen before copy_to_user\n"); -+ for (; ret < PFE_CDEV_ETH_COUNT; ret++) { -+ pr_debug("%u %u", link_states[ret].phy_id, -+ link_states[ret].state); -+ pr_debug("\n"); -+ } -+ -+ /* Copy to user the value in buffer sized len */ -+ ret = copy_to_user(buf, &link_states, sizeof(link_states)); -+ if (ret != 0) { -+ pr_err("Failed to send (%d)bytes of (%lu) requested.\n", -+ ret, len); -+ return -EFAULT; -+ } -+ -+ /* offset set back to 0 as there is contextual reading offset */ -+ *off = 0; -+ pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states)); -+ -+ return sizeof(link_states); -+} -+ -+/** -+ * This function is for getting some commands from user through non-IOCTL -+ * channel. It can used to configure the device. -+ * TODO: To be filled in future, if require duplex communication with user -+ * space. -+ */ -+static ssize_t pfe_cdev_write(struct file *fp, const char *buf, -+ size_t len, loff_t *off) -+{ -+ pr_info("PFE CDEV Write operation not supported!\n"); -+ -+ return -EFAULT; -+} -+ -+static int pfe_cdev_release(struct inode *inp, struct file *fp) -+{ -+ if (g_trigger) { -+ free_irq(pfe->hif_irq, g_trigger); -+ eventfd_ctx_put(g_trigger); -+ g_trigger = NULL; -+ } -+ -+ pr_info("PFE_CDEV: Device successfully closed\n"); -+ return 0; -+} -+ -+/* -+ * hif_us_isr- -+ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block -+ */ -+static irqreturn_t hif_us_isr(int irq, void *arg) -+{ -+ struct eventfd_ctx *trigger = (struct eventfd_ctx *)arg; -+ int int_status; -+ int int_enable_mask; -+ -+ /*Read hif interrupt source register */ -+ int_status = readl_relaxed(HIF_INT_SRC); -+ int_enable_mask = readl_relaxed(HIF_INT_ENABLE); -+ -+ if ((int_status & HIF_INT) == 0) -+ return IRQ_NONE; -+ -+ if (int_status & HIF_RXPKT_INT) { -+ int_enable_mask &= ~(HIF_RXPKT_INT); -+ /* Disable interrupts, they will be enabled after -+ * they are serviced -+ */ -+ writel_relaxed(int_enable_mask, HIF_INT_ENABLE); -+ -+ eventfd_signal(trigger, 1); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+#define PFE_INTR_COAL_USECS 100 -+static long pfe_cdev_ioctl(struct file *fp, unsigned int cmd, -+ unsigned long arg) -+{ -+ int ret = -EFAULT; -+ int __user *argp = (int __user *)arg; -+ -+ pr_debug("PFE CDEV IOCTL Called with cmd=(%u)\n", cmd); -+ -+ switch (cmd) { -+ case PFE_CDEV_ETH0_STATE_GET: -+ /* Return an unsigned int (link state) for ETH0 */ -+ *argp = link_states[0].state; -+ pr_debug("Returning state=%d for ETH0\n", *argp); -+ ret = 0; -+ break; -+ case PFE_CDEV_ETH1_STATE_GET: -+ /* Return an unsigned int (link state) for ETH0 */ -+ *argp = link_states[1].state; -+ pr_debug("Returning state=%d for ETH1\n", *argp); -+ ret = 0; -+ break; -+ case PFE_CDEV_HIF_INTR_EN: -+ /* Return success/failure */ -+ g_trigger = eventfd_ctx_fdget(*argp); -+ if (IS_ERR(g_trigger)) -+ return PTR_ERR(g_trigger); -+ ret = request_irq(pfe->hif_irq, hif_us_isr, 0, "pfe_hif", -+ g_trigger); -+ if (ret) { -+ pr_err("%s: failed to get the hif IRQ = %d\n", -+ __func__, pfe->hif_irq); -+ eventfd_ctx_put(g_trigger); -+ g_trigger = NULL; -+ } -+ writel((PFE_INTR_COAL_USECS * (pfe->ctrl.sys_clk / 1000)) | -+ HIF_INT_COAL_ENABLE, HIF_INT_COAL); -+ -+ pr_debug("request_irq for hif interrupt: %d\n", pfe->hif_irq); -+ ret = 0; -+ break; -+ default: -+ pr_info("Unsupport cmd (%d) for PFE CDEV.\n", cmd); -+ break; -+ }; -+ -+ return ret; -+} -+ -+static unsigned int pfe_cdev_poll(struct file *fp, -+ struct poll_table_struct *wait) -+{ -+ pr_info("PFE CDEV poll method not supported\n"); -+ return 0; -+} -+ -+static const struct file_operations pfe_cdev_fops = { -+ .open = pfe_cdev_open, -+ .read = pfe_cdev_read, -+ .write = pfe_cdev_write, -+ .release = pfe_cdev_release, -+ .unlocked_ioctl = pfe_cdev_ioctl, -+ .poll = pfe_cdev_poll, -+}; -+ -+int pfe_cdev_init(void) -+{ -+ int ret; -+ -+ pr_debug("PFE CDEV initialization begin\n"); -+ -+ /* Register the major number for the device */ -+ pfe_majno = register_chrdev(0, PFE_CDEV_NAME, &pfe_cdev_fops); -+ if (pfe_majno < 0) { -+ pr_err("Unable to register PFE CDEV. PFE CDEV not available\n"); -+ ret = pfe_majno; -+ goto cleanup; -+ } -+ -+ pr_debug("PFE CDEV assigned major number: %d\n", pfe_majno); -+ -+ /* Register the class for the device */ -+ pfe_char_class = class_create(THIS_MODULE, PFE_CLASS_NAME); -+ if (IS_ERR(pfe_char_class)) { -+ pr_err( -+ "Failed to init class for PFE CDEV. PFE CDEV not available.\n"); -+ ret = PTR_ERR(pfe_char_class); -+ goto cleanup; -+ } -+ -+ pr_debug("PFE CDEV Class created successfully.\n"); -+ -+ /* Create the device without any parent and without any callback data */ -+ pfe_char_dev = device_create(pfe_char_class, NULL, -+ MKDEV(pfe_majno, 0), NULL, -+ PFE_CDEV_NAME); -+ if (IS_ERR(pfe_char_dev)) { -+ pr_err("Unable to PFE CDEV device. PFE CDEV not available.\n"); -+ ret = PTR_ERR(pfe_char_dev); -+ goto cleanup; -+ } -+ -+ /* Information structure being shared with the userspace */ -+ memset(link_states, 0, sizeof(struct pfe_shared_info) * -+ PFE_CDEV_ETH_COUNT); -+ -+ pr_info("PFE CDEV created: %s\n", PFE_CDEV_NAME); -+ -+ ret = 0; -+ return ret; -+ -+cleanup: -+ if (!IS_ERR(pfe_char_class)) -+ class_destroy(pfe_char_class); -+ -+ if (pfe_majno > 0) -+ unregister_chrdev(pfe_majno, PFE_CDEV_NAME); -+ -+ return ret; -+} -+ -+void pfe_cdev_exit(void) -+{ -+ if (!IS_ERR(pfe_char_dev)) -+ device_destroy(pfe_char_class, MKDEV(pfe_majno, 0)); -+ -+ if (!IS_ERR(pfe_char_class)) { -+ class_unregister(pfe_char_class); -+ class_destroy(pfe_char_class); -+ } -+ -+ if (pfe_majno > 0) -+ unregister_chrdev(pfe_majno, PFE_CDEV_NAME); -+ -+ /* reset the variables */ -+ pfe_majno = 0; -+ pfe_char_class = NULL; -+ pfe_char_dev = NULL; -+ -+ pr_info("PFE CDEV Removed.\n"); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_cdev.h -@@ -0,0 +1,41 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2018 NXP -+ */ -+ -+#ifndef _PFE_CDEV_H_ -+#define _PFE_CDEV_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define PFE_CDEV_NAME "pfe_us_cdev" -+#define PFE_CLASS_NAME "ppfe_us" -+ -+/* Extracted from ls1012a_pfe_platform_data, there are 3 interfaces which are -+ * supported by PFE driver. Should be updated if number of eth devices are -+ * changed. -+ */ -+#define PFE_CDEV_ETH_COUNT 3 -+ -+struct pfe_shared_info { -+ uint32_t phy_id; /* Link phy ID */ -+ uint8_t state; /* Has either 0 or 1 */ -+}; -+ -+extern struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT]; -+ -+/* IOCTL Commands */ -+#define PFE_CDEV_ETH0_STATE_GET _IOR('R', 0, int) -+#define PFE_CDEV_ETH1_STATE_GET _IOR('R', 1, int) -+#define PFE_CDEV_HIF_INTR_EN _IOWR('R', 2, int) -+ -+int pfe_cdev_init(void); -+void pfe_cdev_exit(void); -+ -+#endif /* _PFE_CDEV_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_ctrl.c -@@ -0,0 +1,226 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "pfe_mod.h" -+#include "pfe_ctrl.h" -+ -+#define TIMEOUT_MS 1000 -+ -+int relax(unsigned long end) -+{ -+ if (time_after(jiffies, end)) { -+ if (time_after(jiffies, end + (TIMEOUT_MS * HZ) / 1000)) -+ return -1; -+ -+ if (need_resched()) -+ schedule(); -+ } -+ -+ return 0; -+} -+ -+void pfe_ctrl_suspend(struct pfe_ctrl *ctrl) -+{ -+ int id; -+ -+ mutex_lock(&ctrl->mutex); -+ -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) -+ pe_dmem_write(id, cpu_to_be32(0x1), CLASS_DM_RESUME, 4); -+ -+ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { -+ if (id == TMU2_ID) -+ continue; -+ pe_dmem_write(id, cpu_to_be32(0x1), TMU_DM_RESUME, 4); -+ } -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ pe_dmem_write(UTIL_ID, cpu_to_be32(0x1), UTIL_DM_RESUME, 4); -+#endif -+ mutex_unlock(&ctrl->mutex); -+} -+ -+void pfe_ctrl_resume(struct pfe_ctrl *ctrl) -+{ -+ int pe_mask = CLASS_MASK | TMU_MASK; -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ pe_mask |= UTIL_MASK; -+#endif -+ mutex_lock(&ctrl->mutex); -+ pe_start(&pfe->ctrl, pe_mask); -+ mutex_unlock(&ctrl->mutex); -+} -+ -+/* PE sync stop. -+ * Stops packet processing for a list of PE's (specified using a bitmask). -+ * The caller must hold ctrl->mutex. -+ * -+ * @param ctrl Control context -+ * @param pe_mask Mask of PE id's to stop -+ * -+ */ -+int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask) -+{ -+ struct pe_sync_mailbox *mbox; -+ int pe_stopped = 0; -+ unsigned long end = jiffies + 2; -+ int i; -+ -+ pe_mask &= 0x2FF; /*Exclude Util + TMU2 */ -+ -+ for (i = 0; i < MAX_PE; i++) -+ if (pe_mask & (1 << i)) { -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ pe_dmem_write(i, cpu_to_be32(0x1), (unsigned -+ long)&mbox->stop, 4); -+ } -+ -+ while (pe_stopped != pe_mask) { -+ for (i = 0; i < MAX_PE; i++) -+ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) { -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ if (pe_dmem_read(i, (unsigned -+ long)&mbox->stopped, 4) & -+ cpu_to_be32(0x1)) -+ pe_stopped |= (1 << i); -+ } -+ -+ if (relax(end) < 0) -+ goto err; -+ } -+ -+ return 0; -+ -+err: -+ pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped); -+ -+ for (i = 0; i < MAX_PE; i++) -+ if (pe_mask & (1 << i)) { -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned -+ long)&mbox->stop, 4); -+ } -+ -+ return -EIO; -+} -+ -+/* PE start. -+ * Starts packet processing for a list of PE's (specified using a bitmask). -+ * The caller must hold ctrl->mutex. -+ * -+ * @param ctrl Control context -+ * @param pe_mask Mask of PE id's to start -+ * -+ */ -+void pe_start(struct pfe_ctrl *ctrl, int pe_mask) -+{ -+ struct pe_sync_mailbox *mbox; -+ int i; -+ -+ for (i = 0; i < MAX_PE; i++) -+ if (pe_mask & (1 << i)) { -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned -+ long)&mbox->stop, 4); -+ } -+} -+ -+/* This function will ensure all PEs are put in to idle state */ -+int pe_reset_all(struct pfe_ctrl *ctrl) -+{ -+ struct pe_sync_mailbox *mbox; -+ int pe_stopped = 0; -+ unsigned long end = jiffies + 2; -+ int i; -+ int pe_mask = CLASS_MASK | TMU_MASK; -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ pe_mask |= UTIL_MASK; -+#endif -+ -+ for (i = 0; i < MAX_PE; i++) -+ if (pe_mask & (1 << i)) { -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ pe_dmem_write(i, cpu_to_be32(0x2), (unsigned -+ long)&mbox->stop, 4); -+ } -+ -+ while (pe_stopped != pe_mask) { -+ for (i = 0; i < MAX_PE; i++) -+ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) { -+ mbox = (void *)ctrl->sync_mailbox_baseaddr[i]; -+ -+ if (pe_dmem_read(i, (unsigned long) -+ &mbox->stopped, 4) & -+ cpu_to_be32(0x1)) -+ pe_stopped |= (1 << i); -+ } -+ -+ if (relax(end) < 0) -+ goto err; -+ } -+ -+ return 0; -+ -+err: -+ pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped); -+ return -EIO; -+} -+ -+int pfe_ctrl_init(struct pfe *pfe) -+{ -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ int id; -+ -+ pr_info("%s\n", __func__); -+ -+ mutex_init(&ctrl->mutex); -+ spin_lock_init(&ctrl->lock); -+ -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { -+ ctrl->sync_mailbox_baseaddr[id] = CLASS_DM_SYNC_MBOX; -+ ctrl->msg_mailbox_baseaddr[id] = CLASS_DM_MSG_MBOX; -+ } -+ -+ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { -+ if (id == TMU2_ID) -+ continue; -+ ctrl->sync_mailbox_baseaddr[id] = TMU_DM_SYNC_MBOX; -+ ctrl->msg_mailbox_baseaddr[id] = TMU_DM_MSG_MBOX; -+ } -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ ctrl->sync_mailbox_baseaddr[UTIL_ID] = UTIL_DM_SYNC_MBOX; -+ ctrl->msg_mailbox_baseaddr[UTIL_ID] = UTIL_DM_MSG_MBOX; -+#endif -+ -+ ctrl->hash_array_baseaddr = pfe->ddr_baseaddr + ROUTE_TABLE_BASEADDR; -+ ctrl->hash_array_phys_baseaddr = pfe->ddr_phys_baseaddr + -+ ROUTE_TABLE_BASEADDR; -+ -+ ctrl->dev = pfe->dev; -+ -+ pr_info("%s finished\n", __func__); -+ -+ return 0; -+} -+ -+void pfe_ctrl_exit(struct pfe *pfe) -+{ -+ pr_info("%s\n", __func__); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h -@@ -0,0 +1,100 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_CTRL_H_ -+#define _PFE_CTRL_H_ -+ -+#include -+ -+#include "pfe/pfe.h" -+ -+#define DMA_BUF_SIZE_128 0x80 /* enough for 1 conntracks */ -+#define DMA_BUF_SIZE_256 0x100 -+/* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */ -+#define DMA_BUF_SIZE_512 0x200 -+/* 512bytes dma allocated buffers used by rtp relay feature */ -+#define DMA_BUF_MIN_ALIGNMENT 8 -+#define DMA_BUF_BOUNDARY (4 * 1024) -+/* bursts can not cross 4k boundary */ -+ -+#define CMD_TX_ENABLE 0x0501 -+#define CMD_TX_DISABLE 0x0502 -+ -+#define CMD_RX_LRO 0x0011 -+#define CMD_PKTCAP_ENABLE 0x0d01 -+#define CMD_QM_EXPT_RATE 0x020c -+ -+#define CLASS_DM_SH_STATIC (0x800) -+#define CLASS_DM_CPU_TICKS (CLASS_DM_SH_STATIC) -+#define CLASS_DM_SYNC_MBOX (0x808) -+#define CLASS_DM_MSG_MBOX (0x810) -+#define CLASS_DM_DROP_CNTR (0x820) -+#define CLASS_DM_RESUME (0x854) -+#define CLASS_DM_PESTATUS (0x860) -+#define CLASS_DM_CRC_VALIDATED (0x14b0) -+ -+#define TMU_DM_SH_STATIC (0x80) -+#define TMU_DM_CPU_TICKS (TMU_DM_SH_STATIC) -+#define TMU_DM_SYNC_MBOX (0x88) -+#define TMU_DM_MSG_MBOX (0x90) -+#define TMU_DM_RESUME (0xA0) -+#define TMU_DM_PESTATUS (0xB0) -+#define TMU_DM_CONTEXT (0x300) -+#define TMU_DM_TX_TRANS (0x480) -+ -+#define UTIL_DM_SH_STATIC (0x0) -+#define UTIL_DM_CPU_TICKS (UTIL_DM_SH_STATIC) -+#define UTIL_DM_SYNC_MBOX (0x8) -+#define UTIL_DM_MSG_MBOX (0x10) -+#define UTIL_DM_DROP_CNTR (0x20) -+#define UTIL_DM_RESUME (0x40) -+#define UTIL_DM_PESTATUS (0x50) -+ -+struct pfe_ctrl { -+ struct mutex mutex; /* to serialize pfe control access */ -+ spinlock_t lock; -+ -+ void *dma_pool; -+ void *dma_pool_512; -+ void *dma_pool_128; -+ -+ struct device *dev; -+ -+ void *hash_array_baseaddr; /* -+ * Virtual base address of -+ * the conntrack hash array -+ */ -+ unsigned long hash_array_phys_baseaddr; /* -+ * Physical base address of -+ * the conntrack hash array -+ */ -+ -+ int (*event_cb)(u16, u16, u16*); -+ -+ unsigned long sync_mailbox_baseaddr[MAX_PE]; /* -+ * Sync mailbox PFE -+ * internal address, -+ * initialized -+ * when parsing elf images -+ */ -+ unsigned long msg_mailbox_baseaddr[MAX_PE]; /* -+ * Msg mailbox PFE internal -+ * address, initialized -+ * when parsing elf images -+ */ -+ unsigned int sys_clk; /* AXI clock value, in KHz */ -+}; -+ -+int pfe_ctrl_init(struct pfe *pfe); -+void pfe_ctrl_exit(struct pfe *pfe); -+int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask); -+void pe_start(struct pfe_ctrl *ctrl, int pe_mask); -+int pe_reset_all(struct pfe_ctrl *ctrl); -+void pfe_ctrl_suspend(struct pfe_ctrl *ctrl); -+void pfe_ctrl_resume(struct pfe_ctrl *ctrl); -+int relax(unsigned long end); -+ -+#endif /* _PFE_CTRL_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_debugfs.c -@@ -0,0 +1,99 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include -+#include -+#include -+ -+#include "pfe_mod.h" -+ -+static int dmem_show(struct seq_file *s, void *unused) -+{ -+ u32 dmem_addr, val; -+ int id = (long int)s->private; -+ int i; -+ -+ for (dmem_addr = 0; dmem_addr < CLASS_DMEM_SIZE; dmem_addr += 8 * 4) { -+ seq_printf(s, "%04x:", dmem_addr); -+ -+ for (i = 0; i < 8; i++) { -+ val = pe_dmem_read(id, dmem_addr + i * 4, 4); -+ seq_printf(s, " %02x %02x %02x %02x", val & 0xff, -+ (val >> 8) & 0xff, (val >> 16) & 0xff, -+ (val >> 24) & 0xff); -+ } -+ -+ seq_puts(s, "\n"); -+ } -+ -+ return 0; -+} -+ -+static int dmem_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, dmem_show, inode->i_private); -+} -+ -+static const struct file_operations dmem_fops = { -+ .open = dmem_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+int pfe_debugfs_init(struct pfe *pfe) -+{ -+ struct dentry *d; -+ -+ pr_info("%s\n", __func__); -+ -+ pfe->dentry = debugfs_create_dir("pfe", NULL); -+ if (IS_ERR_OR_NULL(pfe->dentry)) -+ goto err_dir; -+ -+ d = debugfs_create_file("pe0_dmem", 0444, pfe->dentry, (void *)0, -+ &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe1_dmem", 0444, pfe->dentry, (void *)1, -+ &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe2_dmem", 0444, pfe->dentry, (void *)2, -+ &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe3_dmem", 0444, pfe->dentry, (void *)3, -+ &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe4_dmem", 0444, pfe->dentry, (void *)4, -+ &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ d = debugfs_create_file("pe5_dmem", 0444, pfe->dentry, (void *)5, -+ &dmem_fops); -+ if (IS_ERR_OR_NULL(d)) -+ goto err_pe; -+ -+ return 0; -+ -+err_pe: -+ debugfs_remove_recursive(pfe->dentry); -+ -+err_dir: -+ return -1; -+} -+ -+void pfe_debugfs_exit(struct pfe *pfe) -+{ -+ debugfs_remove_recursive(pfe->dentry); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h -@@ -0,0 +1,13 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_DEBUGFS_H_ -+#define _PFE_DEBUGFS_H_ -+ -+int pfe_debugfs_init(struct pfe *pfe); -+void pfe_debugfs_exit(struct pfe *pfe); -+ -+#endif /* _PFE_DEBUGFS_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_eth.c -@@ -0,0 +1,2587 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+/* @pfe_eth.c. -+ * Ethernet driver for to handle exception path for PFE. -+ * - uses HIF functions to send/receive packets. -+ * - uses ctrl function to start/stop interfaces. -+ * - uses direct register accesses to control phy operation. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if defined(CONFIG_NF_CONNTRACK_MARK) -+#include -+#endif -+ -+#include "pfe_mod.h" -+#include "pfe_eth.h" -+#include "pfe_cdev.h" -+ -+#define LS1012A_REV_1_0 0x87040010 -+ -+bool pfe_use_old_dts_phy; -+bool pfe_errata_a010897; -+ -+static void *cbus_emac_base[3]; -+static void *cbus_gpi_base[3]; -+ -+/* Forward Declaration */ -+static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv); -+static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv); -+static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int -+ from_tx, int n_desc); -+ -+/* MDIO registers */ -+#define MDIO_SGMII_CR 0x00 -+#define MDIO_SGMII_SR 0x01 -+#define MDIO_SGMII_DEV_ABIL_SGMII 0x04 -+#define MDIO_SGMII_LINK_TMR_L 0x12 -+#define MDIO_SGMII_LINK_TMR_H 0x13 -+#define MDIO_SGMII_IF_MODE 0x14 -+ -+/* SGMII Control defines */ -+#define SGMII_CR_RST 0x8000 -+#define SGMII_CR_AN_EN 0x1000 -+#define SGMII_CR_RESTART_AN 0x0200 -+#define SGMII_CR_FD 0x0100 -+#define SGMII_CR_SPEED_SEL1_1G 0x0040 -+#define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \ -+ SGMII_CR_SPEED_SEL1_1G) -+ -+/* SGMII IF Mode */ -+#define SGMII_DUPLEX_HALF 0x10 -+#define SGMII_SPEED_10MBPS 0x00 -+#define SGMII_SPEED_100MBPS 0x04 -+#define SGMII_SPEED_1GBPS 0x08 -+#define SGMII_USE_SGMII_AN 0x02 -+#define SGMII_EN 0x01 -+ -+/* SGMII Device Ability for SGMII */ -+#define SGMII_DEV_ABIL_ACK 0x4000 -+#define SGMII_DEV_ABIL_EEE_CLK_STP_EN 0x0100 -+#define SGMII_DEV_ABIL_SGMII 0x0001 -+ -+unsigned int gemac_regs[] = { -+ 0x0004, /* Interrupt event */ -+ 0x0008, /* Interrupt mask */ -+ 0x0024, /* Ethernet control */ -+ 0x0064, /* MIB Control/Status */ -+ 0x0084, /* Receive control/status */ -+ 0x00C4, /* Transmit control */ -+ 0x00E4, /* Physical address low */ -+ 0x00E8, /* Physical address high */ -+ 0x0144, /* Transmit FIFO Watermark and Store and Forward Control*/ -+ 0x0190, /* Receive FIFO Section Full Threshold */ -+ 0x01A0, /* Transmit FIFO Section Empty Threshold */ -+ 0x01B0, /* Frame Truncation Length */ -+}; -+ -+const struct soc_device_attribute ls1012a_rev1_soc_attr[] = { -+ { .family = "QorIQ LS1012A", -+ .soc_id = "svr:0x87040010", -+ .revision = "1.0", -+ .data = NULL }, -+ { }, -+}; -+ -+/********************************************************************/ -+/* SYSFS INTERFACE */ -+/********************************************************************/ -+ -+#ifdef PFE_ETH_NAPI_STATS -+/* -+ * pfe_eth_show_napi_stats -+ */ -+static ssize_t pfe_eth_show_napi_stats(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ ssize_t len = 0; -+ -+ len += sprintf(buf + len, "sched: %u\n", -+ priv->napi_counters[NAPI_SCHED_COUNT]); -+ len += sprintf(buf + len, "poll: %u\n", -+ priv->napi_counters[NAPI_POLL_COUNT]); -+ len += sprintf(buf + len, "packet: %u\n", -+ priv->napi_counters[NAPI_PACKET_COUNT]); -+ len += sprintf(buf + len, "budget: %u\n", -+ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]); -+ len += sprintf(buf + len, "desc: %u\n", -+ priv->napi_counters[NAPI_DESC_COUNT]); -+ -+ return len; -+} -+ -+/* -+ * pfe_eth_set_napi_stats -+ */ -+static ssize_t pfe_eth_set_napi_stats(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ -+ memset(priv->napi_counters, 0, sizeof(priv->napi_counters)); -+ -+ return count; -+} -+#endif -+#ifdef PFE_ETH_TX_STATS -+/* pfe_eth_show_tx_stats -+ * -+ */ -+static ssize_t pfe_eth_show_tx_stats(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ ssize_t len = 0; -+ int i; -+ -+ len += sprintf(buf + len, "TX queues stats:\n"); -+ -+ for (i = 0; i < emac_txq_cnt; i++) { -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, -+ i); -+ -+ len += sprintf(buf + len, "\n"); -+ __netif_tx_lock_bh(tx_queue); -+ -+ hif_tx_lock(&pfe->hif); -+ len += sprintf(buf + len, -+ "Queue %2d : credits = %10d\n" -+ , i, hif_lib_tx_credit_avail(pfe, priv->id, i)); -+ len += sprintf(buf + len, -+ " tx packets = %10d\n" -+ , pfe->tmu_credit.tx_packets[priv->id][i]); -+ hif_tx_unlock(&pfe->hif); -+ -+ /* Don't output additionnal stats if queue never used */ -+ if (!pfe->tmu_credit.tx_packets[priv->id][i]) -+ goto skip; -+ -+ len += sprintf(buf + len, -+ " clean_fail = %10d\n" -+ , priv->clean_fail[i]); -+ len += sprintf(buf + len, -+ " stop_queue = %10d\n" -+ , priv->stop_queue_total[i]); -+ len += sprintf(buf + len, -+ " stop_queue_hif = %10d\n" -+ , priv->stop_queue_hif[i]); -+ len += sprintf(buf + len, -+ " stop_queue_hif_client = %10d\n" -+ , priv->stop_queue_hif_client[i]); -+ len += sprintf(buf + len, -+ " stop_queue_credit = %10d\n" -+ , priv->stop_queue_credit[i]); -+skip: -+ __netif_tx_unlock_bh(tx_queue); -+ } -+ return len; -+} -+ -+/* pfe_eth_set_tx_stats -+ * -+ */ -+static ssize_t pfe_eth_set_tx_stats(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ int i; -+ -+ for (i = 0; i < emac_txq_cnt; i++) { -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, -+ i); -+ -+ __netif_tx_lock_bh(tx_queue); -+ priv->clean_fail[i] = 0; -+ priv->stop_queue_total[i] = 0; -+ priv->stop_queue_hif[i] = 0; -+ priv->stop_queue_hif_client[i] = 0; -+ priv->stop_queue_credit[i] = 0; -+ __netif_tx_unlock_bh(tx_queue); -+ } -+ -+ return count; -+} -+#endif -+/* pfe_eth_show_txavail -+ * -+ */ -+static ssize_t pfe_eth_show_txavail(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ ssize_t len = 0; -+ int i; -+ -+ for (i = 0; i < emac_txq_cnt; i++) { -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, -+ i); -+ -+ __netif_tx_lock_bh(tx_queue); -+ -+ len += sprintf(buf + len, "%d", -+ hif_lib_tx_avail(&priv->client, i)); -+ -+ __netif_tx_unlock_bh(tx_queue); -+ -+ if (i == (emac_txq_cnt - 1)) -+ len += sprintf(buf + len, "\n"); -+ else -+ len += sprintf(buf + len, " "); -+ } -+ -+ return len; -+} -+ -+/* pfe_eth_show_default_priority -+ * -+ */ -+static ssize_t pfe_eth_show_default_priority(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ unsigned long flags; -+ int rc; -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ rc = sprintf(buf, "%d\n", priv->default_priority); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ return rc; -+} -+ -+/* pfe_eth_set_default_priority -+ * -+ */ -+ -+static ssize_t pfe_eth_set_default_priority(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev)); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ priv->default_priority = kstrtoul(buf, 0, 0); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ return count; -+} -+ -+static DEVICE_ATTR(txavail, 0444, pfe_eth_show_txavail, NULL); -+static DEVICE_ATTR(default_priority, 0644, pfe_eth_show_default_priority, -+ pfe_eth_set_default_priority); -+ -+#ifdef PFE_ETH_NAPI_STATS -+static DEVICE_ATTR(napi_stats, 0644, pfe_eth_show_napi_stats, -+ pfe_eth_set_napi_stats); -+#endif -+ -+#ifdef PFE_ETH_TX_STATS -+static DEVICE_ATTR(tx_stats, 0644, pfe_eth_show_tx_stats, -+ pfe_eth_set_tx_stats); -+#endif -+ -+/* -+ * pfe_eth_sysfs_init -+ * -+ */ -+static int pfe_eth_sysfs_init(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ int err; -+ -+ /* Initialize the default values */ -+ -+ /* -+ * By default, packets without conntrack will use this default low -+ * priority queue -+ */ -+ priv->default_priority = 0; -+ -+ /* Create our sysfs files */ -+ err = device_create_file(&ndev->dev, &dev_attr_default_priority); -+ if (err) { -+ netdev_err(ndev, -+ "failed to create default_priority sysfs files\n"); -+ goto err_priority; -+ } -+ -+ err = device_create_file(&ndev->dev, &dev_attr_txavail); -+ if (err) { -+ netdev_err(ndev, -+ "failed to create default_priority sysfs files\n"); -+ goto err_txavail; -+ } -+ -+#ifdef PFE_ETH_NAPI_STATS -+ err = device_create_file(&ndev->dev, &dev_attr_napi_stats); -+ if (err) { -+ netdev_err(ndev, "failed to create napi stats sysfs files\n"); -+ goto err_napi; -+ } -+#endif -+ -+#ifdef PFE_ETH_TX_STATS -+ err = device_create_file(&ndev->dev, &dev_attr_tx_stats); -+ if (err) { -+ netdev_err(ndev, "failed to create tx stats sysfs files\n"); -+ goto err_tx; -+ } -+#endif -+ -+ return 0; -+ -+#ifdef PFE_ETH_TX_STATS -+err_tx: -+#endif -+#ifdef PFE_ETH_NAPI_STATS -+ device_remove_file(&ndev->dev, &dev_attr_napi_stats); -+ -+err_napi: -+#endif -+ device_remove_file(&ndev->dev, &dev_attr_txavail); -+ -+err_txavail: -+ device_remove_file(&ndev->dev, &dev_attr_default_priority); -+ -+err_priority: -+ return -1; -+} -+ -+/* pfe_eth_sysfs_exit -+ * -+ */ -+void pfe_eth_sysfs_exit(struct net_device *ndev) -+{ -+#ifdef PFE_ETH_TX_STATS -+ device_remove_file(&ndev->dev, &dev_attr_tx_stats); -+#endif -+ -+#ifdef PFE_ETH_NAPI_STATS -+ device_remove_file(&ndev->dev, &dev_attr_napi_stats); -+#endif -+ device_remove_file(&ndev->dev, &dev_attr_txavail); -+ device_remove_file(&ndev->dev, &dev_attr_default_priority); -+} -+ -+/*************************************************************************/ -+/* ETHTOOL INTERCAE */ -+/*************************************************************************/ -+ -+/*MTIP GEMAC */ -+static const struct fec_stat { -+ char name[ETH_GSTRING_LEN]; -+ u16 offset; -+} fec_stats[] = { -+ /* RMON TX */ -+ { "tx_dropped", RMON_T_DROP }, -+ { "tx_packets", RMON_T_PACKETS }, -+ { "tx_broadcast", RMON_T_BC_PKT }, -+ { "tx_multicast", RMON_T_MC_PKT }, -+ { "tx_crc_errors", RMON_T_CRC_ALIGN }, -+ { "tx_undersize", RMON_T_UNDERSIZE }, -+ { "tx_oversize", RMON_T_OVERSIZE }, -+ { "tx_fragment", RMON_T_FRAG }, -+ { "tx_jabber", RMON_T_JAB }, -+ { "tx_collision", RMON_T_COL }, -+ { "tx_64byte", RMON_T_P64 }, -+ { "tx_65to127byte", RMON_T_P65TO127 }, -+ { "tx_128to255byte", RMON_T_P128TO255 }, -+ { "tx_256to511byte", RMON_T_P256TO511 }, -+ { "tx_512to1023byte", RMON_T_P512TO1023 }, -+ { "tx_1024to2047byte", RMON_T_P1024TO2047 }, -+ { "tx_GTE2048byte", RMON_T_P_GTE2048 }, -+ { "tx_octets", RMON_T_OCTETS }, -+ -+ /* IEEE TX */ -+ { "IEEE_tx_drop", IEEE_T_DROP }, -+ { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, -+ { "IEEE_tx_1col", IEEE_T_1COL }, -+ { "IEEE_tx_mcol", IEEE_T_MCOL }, -+ { "IEEE_tx_def", IEEE_T_DEF }, -+ { "IEEE_tx_lcol", IEEE_T_LCOL }, -+ { "IEEE_tx_excol", IEEE_T_EXCOL }, -+ { "IEEE_tx_macerr", IEEE_T_MACERR }, -+ { "IEEE_tx_cserr", IEEE_T_CSERR }, -+ { "IEEE_tx_sqe", IEEE_T_SQE }, -+ { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, -+ { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, -+ -+ /* RMON RX */ -+ { "rx_packets", RMON_R_PACKETS }, -+ { "rx_broadcast", RMON_R_BC_PKT }, -+ { "rx_multicast", RMON_R_MC_PKT }, -+ { "rx_crc_errors", RMON_R_CRC_ALIGN }, -+ { "rx_undersize", RMON_R_UNDERSIZE }, -+ { "rx_oversize", RMON_R_OVERSIZE }, -+ { "rx_fragment", RMON_R_FRAG }, -+ { "rx_jabber", RMON_R_JAB }, -+ { "rx_64byte", RMON_R_P64 }, -+ { "rx_65to127byte", RMON_R_P65TO127 }, -+ { "rx_128to255byte", RMON_R_P128TO255 }, -+ { "rx_256to511byte", RMON_R_P256TO511 }, -+ { "rx_512to1023byte", RMON_R_P512TO1023 }, -+ { "rx_1024to2047byte", RMON_R_P1024TO2047 }, -+ { "rx_GTE2048byte", RMON_R_P_GTE2048 }, -+ { "rx_octets", RMON_R_OCTETS }, -+ -+ /* IEEE RX */ -+ { "IEEE_rx_drop", IEEE_R_DROP }, -+ { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, -+ { "IEEE_rx_crc", IEEE_R_CRC }, -+ { "IEEE_rx_align", IEEE_R_ALIGN }, -+ { "IEEE_rx_macerr", IEEE_R_MACERR }, -+ { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, -+ { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, -+}; -+ -+static void pfe_eth_fill_stats(struct net_device *ndev, struct ethtool_stats -+ *stats, u64 *data) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ int i; -+ u64 pfe_crc_validated = 0; -+ int id; -+ -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { -+ pfe_crc_validated += be32_to_cpu(pe_dmem_read(id, -+ CLASS_DM_CRC_VALIDATED + (priv->id * 4), 4)); -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(fec_stats); i++) { -+ data[i] = readl(priv->EMAC_baseaddr + fec_stats[i].offset); -+ -+ if (fec_stats[i].offset == IEEE_R_DROP) -+ data[i] -= pfe_crc_validated; -+ } -+} -+ -+static void pfe_eth_gstrings(struct net_device *netdev, -+ u32 stringset, u8 *data) -+{ -+ int i; -+ -+ switch (stringset) { -+ case ETH_SS_STATS: -+ for (i = 0; i < ARRAY_SIZE(fec_stats); i++) -+ memcpy(data + i * ETH_GSTRING_LEN, -+ fec_stats[i].name, ETH_GSTRING_LEN); -+ break; -+ } -+} -+ -+static int pfe_eth_stats_count(struct net_device *ndev, int sset) -+{ -+ switch (sset) { -+ case ETH_SS_STATS: -+ return ARRAY_SIZE(fec_stats); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ -+/* -+ * pfe_eth_gemac_reglen - Return the length of the register structure. -+ * -+ */ -+static int pfe_eth_gemac_reglen(struct net_device *ndev) -+{ -+ pr_info("%s()\n", __func__); -+ return (sizeof(gemac_regs) / sizeof(u32)); -+} -+ -+/* -+ * pfe_eth_gemac_get_regs - Return the gemac register structure. -+ * -+ */ -+static void pfe_eth_gemac_get_regs(struct net_device *ndev, struct ethtool_regs -+ *regs, void *regbuf) -+{ -+ int i; -+ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ u32 *buf = (u32 *)regbuf; -+ -+ pr_info("%s()\n", __func__); -+ for (i = 0; i < sizeof(gemac_regs) / sizeof(u32); i++) -+ buf[i] = readl(priv->EMAC_baseaddr + gemac_regs[i]); -+} -+ -+/* -+ * pfe_eth_set_wol - Set the magic packet option, in WoL register. -+ * -+ */ -+static int pfe_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ if (wol->wolopts & ~WAKE_MAGIC) -+ return -EOPNOTSUPP; -+ -+ /* for MTIP we store wol->wolopts */ -+ priv->wol = wol->wolopts; -+ -+ device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC); -+ -+ return 0; -+} -+ -+/* -+ * -+ * pfe_eth_get_wol - Get the WoL options. -+ * -+ */ -+static void pfe_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo -+ *wol) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ wol->supported = WAKE_MAGIC; -+ wol->wolopts = 0; -+ -+ if (priv->wol & WAKE_MAGIC) -+ wol->wolopts = WAKE_MAGIC; -+ -+ memset(&wol->sopass, 0, sizeof(wol->sopass)); -+} -+ -+/* -+ * pfe_eth_get_drvinfo - Fills in the drvinfo structure with some basic info -+ * -+ */ -+static void pfe_eth_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo -+ *drvinfo) -+{ -+ strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver)); -+ strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version)); -+ strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); -+ strlcpy(drvinfo->bus_info, "N/A", sizeof(drvinfo->bus_info)); -+} -+ -+/* -+ * pfe_eth_set_settings - Used to send commands to PHY. -+ * -+ */ -+static int pfe_eth_set_settings(struct net_device *ndev, -+ const struct ethtool_link_ksettings *cmd) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ struct phy_device *phydev = priv->phydev; -+ -+ if (!phydev) -+ return -ENODEV; -+ -+ return phy_ethtool_ksettings_set(phydev, cmd); -+} -+ -+/* -+ * pfe_eth_getsettings - Return the current settings in the ethtool_cmd -+ * structure. -+ * -+ */ -+static int pfe_eth_get_settings(struct net_device *ndev, -+ struct ethtool_link_ksettings *cmd) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ struct phy_device *phydev = priv->phydev; -+ -+ if (!phydev) -+ return -ENODEV; -+ -+ phy_ethtool_ksettings_get(phydev, cmd); -+ -+ return 0; -+} -+ -+/* -+ * pfe_eth_get_msglevel - Gets the debug message mask. -+ * -+ */ -+static uint32_t pfe_eth_get_msglevel(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ return priv->msg_enable; -+} -+ -+/* -+ * pfe_eth_set_msglevel - Sets the debug message mask. -+ * -+ */ -+static void pfe_eth_set_msglevel(struct net_device *ndev, uint32_t data) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ priv->msg_enable = data; -+} -+ -+#define HIF_RX_COAL_MAX_CLKS (~(1 << 31)) -+#define HIF_RX_COAL_CLKS_PER_USEC (pfe->ctrl.sys_clk / 1000) -+#define HIF_RX_COAL_MAX_USECS (HIF_RX_COAL_MAX_CLKS / \ -+ HIF_RX_COAL_CLKS_PER_USEC) -+ -+/* -+ * pfe_eth_set_coalesce - Sets rx interrupt coalescing timer. -+ * -+ */ -+static int pfe_eth_set_coalesce(struct net_device *ndev, -+ struct ethtool_coalesce *ec) -+{ -+ if (ec->rx_coalesce_usecs > HIF_RX_COAL_MAX_USECS) -+ return -EINVAL; -+ -+ if (!ec->rx_coalesce_usecs) { -+ writel(0, HIF_INT_COAL); -+ return 0; -+ } -+ -+ writel((ec->rx_coalesce_usecs * HIF_RX_COAL_CLKS_PER_USEC) | -+ HIF_INT_COAL_ENABLE, HIF_INT_COAL); -+ -+ return 0; -+} -+ -+/* -+ * pfe_eth_get_coalesce - Gets rx interrupt coalescing timer value. -+ * -+ */ -+static int pfe_eth_get_coalesce(struct net_device *ndev, -+ struct ethtool_coalesce *ec) -+{ -+ int reg_val = readl(HIF_INT_COAL); -+ -+ if (reg_val & HIF_INT_COAL_ENABLE) -+ ec->rx_coalesce_usecs = (reg_val & HIF_RX_COAL_MAX_CLKS) / -+ HIF_RX_COAL_CLKS_PER_USEC; -+ else -+ ec->rx_coalesce_usecs = 0; -+ -+ return 0; -+} -+ -+/* -+ * pfe_eth_set_pauseparam - Sets pause parameters -+ * -+ */ -+static int pfe_eth_set_pauseparam(struct net_device *ndev, -+ struct ethtool_pauseparam *epause) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ if (epause->tx_pause != epause->rx_pause) { -+ netdev_info(ndev, -+ "hardware only support enable/disable both tx and rx\n"); -+ return -EINVAL; -+ } -+ -+ priv->pause_flag = 0; -+ priv->pause_flag |= epause->rx_pause ? PFE_PAUSE_FLAG_ENABLE : 0; -+ priv->pause_flag |= epause->autoneg ? PFE_PAUSE_FLAG_AUTONEG : 0; -+ -+ if (epause->rx_pause || epause->autoneg) { -+ gemac_enable_pause_rx(priv->EMAC_baseaddr); -+ writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) | -+ EGPI_PAUSE_ENABLE), -+ priv->GPI_baseaddr + GPI_TX_PAUSE_TIME); -+ if (priv->phydev) { -+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, -+ priv->phydev->supported); -+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, -+ priv->phydev->supported); -+ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, -+ priv->phydev->advertising); -+ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, -+ priv->phydev->advertising); -+ } -+ } else { -+ gemac_disable_pause_rx(priv->EMAC_baseaddr); -+ writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) & -+ ~EGPI_PAUSE_ENABLE), -+ priv->GPI_baseaddr + GPI_TX_PAUSE_TIME); -+ if (priv->phydev) { -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, -+ priv->phydev->supported); -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, -+ priv->phydev->supported); -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, -+ priv->phydev->advertising); -+ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, -+ priv->phydev->advertising); -+ } -+ } -+ -+ return 0; -+} -+ -+/* -+ * pfe_eth_get_pauseparam - Gets pause parameters -+ * -+ */ -+static void pfe_eth_get_pauseparam(struct net_device *ndev, -+ struct ethtool_pauseparam *epause) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ epause->autoneg = (priv->pause_flag & PFE_PAUSE_FLAG_AUTONEG) != 0; -+ epause->tx_pause = (priv->pause_flag & PFE_PAUSE_FLAG_ENABLE) != 0; -+ epause->rx_pause = epause->tx_pause; -+} -+ -+/* -+ * pfe_eth_get_hash -+ */ -+#define PFE_HASH_BITS 6 /* #bits in hash */ -+#define CRC32_POLY 0xEDB88320 -+ -+static int pfe_eth_get_hash(u8 *addr) -+{ -+ unsigned int i, bit, data, crc, hash; -+ -+ /* calculate crc32 value of mac address */ -+ crc = 0xffffffff; -+ -+ for (i = 0; i < 6; i++) { -+ data = addr[i]; -+ for (bit = 0; bit < 8; bit++, data >>= 1) { -+ crc = (crc >> 1) ^ -+ (((crc ^ data) & 1) ? CRC32_POLY : 0); -+ } -+ } -+ -+ /* -+ * only upper 6 bits (PFE_HASH_BITS) are used -+ * which point to specific bit in the hash registers -+ */ -+ hash = (crc >> (32 - PFE_HASH_BITS)) & 0x3f; -+ -+ return hash; -+} -+ -+const struct ethtool_ops pfe_ethtool_ops = { -+ .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS, -+ .get_drvinfo = pfe_eth_get_drvinfo, -+ .get_regs_len = pfe_eth_gemac_reglen, -+ .get_regs = pfe_eth_gemac_get_regs, -+ .get_link = ethtool_op_get_link, -+ .get_wol = pfe_eth_get_wol, -+ .set_wol = pfe_eth_set_wol, -+ .set_pauseparam = pfe_eth_set_pauseparam, -+ .get_pauseparam = pfe_eth_get_pauseparam, -+ .get_strings = pfe_eth_gstrings, -+ .get_sset_count = pfe_eth_stats_count, -+ .get_ethtool_stats = pfe_eth_fill_stats, -+ .get_msglevel = pfe_eth_get_msglevel, -+ .set_msglevel = pfe_eth_set_msglevel, -+ .set_coalesce = pfe_eth_set_coalesce, -+ .get_coalesce = pfe_eth_get_coalesce, -+ .get_link_ksettings = pfe_eth_get_settings, -+ .set_link_ksettings = pfe_eth_set_settings, -+}; -+ -+/* pfe_eth_mdio_reset -+ */ -+int pfe_eth_mdio_reset(struct mii_bus *bus) -+{ -+ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; -+ u32 phy_speed; -+ -+ -+ mutex_lock(&bus->mdio_lock); -+ -+ /* -+ * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) -+ * -+ * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while -+ * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. -+ */ -+ phy_speed = (DIV_ROUND_UP((pfe->ctrl.sys_clk * 1000), 4000000) -+ << EMAC_MII_SPEED_SHIFT); -+ phy_speed |= EMAC_HOLDTIME(0x5); -+ __raw_writel(phy_speed, priv->mdio_base + EMAC_MII_CTRL_REG); -+ -+ mutex_unlock(&bus->mdio_lock); -+ -+ return 0; -+} -+ -+/* pfe_eth_mdio_timeout -+ * -+ */ -+static int pfe_eth_mdio_timeout(struct pfe_mdio_priv_s *priv, int timeout) -+{ -+ while (!(__raw_readl(priv->mdio_base + EMAC_IEVENT_REG) & -+ EMAC_IEVENT_MII)) { -+ if (timeout-- <= 0) -+ return -1; -+ usleep_range(10, 20); -+ } -+ __raw_writel(EMAC_IEVENT_MII, priv->mdio_base + EMAC_IEVENT_REG); -+ return 0; -+} -+ -+static int pfe_eth_mdio_mux(u8 muxval) -+{ -+ struct i2c_adapter *a; -+ struct i2c_msg msg; -+ unsigned char buf[2]; -+ int ret; -+ -+ a = i2c_get_adapter(0); -+ if (!a) -+ return -ENODEV; -+ -+ /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */ -+ buf[0] = 0x54; /* reg number */ -+ buf[1] = (muxval << 6) | 0x3; /* data */ -+ msg.addr = 0x66; -+ msg.buf = buf; -+ msg.len = 2; -+ msg.flags = 0; -+ ret = i2c_transfer(a, &msg, 1); -+ i2c_put_adapter(a); -+ if (ret != 1) -+ return -ENODEV; -+ return 0; -+} -+ -+static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id, -+ int dev_addr, int regnum) -+{ -+ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; -+ -+ __raw_writel(EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA(dev_addr) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(regnum), -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ -+ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { -+ dev_err(&bus->dev, "phy MDIO address write timeout\n"); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum, -+ u16 value) -+{ -+ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; -+ -+ /*To access external PHYs on QDS board mux needs to be configured*/ -+ if ((mii_id) && (pfe->mdio_muxval[mii_id])) -+ pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); -+ -+ if (regnum & MII_ADDR_C45) { -+ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, -+ regnum & 0xffff); -+ __raw_writel(EMAC_MII_DATA_OP_CL45_WR | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ } else { -+ /* start a write op */ -+ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA(regnum) | -+ EMAC_MII_DATA_TA | EMAC_MII_DATA(value), -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ } -+ -+ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { -+ dev_err(&bus->dev, "%s: phy MDIO write timeout\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -+{ -+ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv; -+ u16 value = 0; -+ -+ /*To access external PHYs on QDS board mux needs to be configured*/ -+ if ((mii_id) && (pfe->mdio_muxval[mii_id])) -+ pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]); -+ -+ if (regnum & MII_ADDR_C45) { -+ pfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f, -+ regnum & 0xffff); -+ __raw_writel(EMAC_MII_DATA_OP_CL45_RD | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) | -+ EMAC_MII_DATA_TA, -+ priv->mdio_base + EMAC_MII_DATA_REG); -+ } else { -+ /* start a read op */ -+ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | -+ EMAC_MII_DATA_PA(mii_id) | -+ EMAC_MII_DATA_RA(regnum) | -+ EMAC_MII_DATA_TA, priv->mdio_base + -+ EMAC_MII_DATA_REG); -+ } -+ -+ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) { -+ dev_err(&bus->dev, "%s: phy MDIO read timeout\n", __func__); -+ return -1; -+ } -+ -+ value = EMAC_MII_DATA(__raw_readl(priv->mdio_base + -+ EMAC_MII_DATA_REG)); -+ return value; -+} -+ -+static int pfe_eth_mdio_init(struct pfe *pfe, -+ struct ls1012a_pfe_platform_data *pfe_info, -+ int ii) -+{ -+ struct pfe_mdio_priv_s *priv = NULL; -+ struct ls1012a_mdio_platform_data *mdio_info; -+ struct mii_bus *bus; -+ struct device_node *mdio_node; -+ int rc = 0; -+ -+ mdio_info = (struct ls1012a_mdio_platform_data *) -+ pfe_info->ls1012a_mdio_pdata; -+ mdio_info->id = ii; -+ -+ bus = mdiobus_alloc_size(sizeof(struct pfe_mdio_priv_s)); -+ if (!bus) { -+ pr_err("mdiobus_alloc() failed\n"); -+ rc = -ENOMEM; -+ goto err_mdioalloc; -+ } -+ -+ bus->name = "ls1012a MDIO Bus"; -+ snprintf(bus->id, MII_BUS_ID_SIZE, "ls1012a-%x", mdio_info->id); -+ -+ bus->read = &pfe_eth_mdio_read; -+ bus->write = &pfe_eth_mdio_write; -+ bus->reset = &pfe_eth_mdio_reset; -+ bus->parent = pfe->dev; -+ bus->phy_mask = mdio_info->phy_mask; -+ bus->irq[0] = mdio_info->irq[0]; -+ priv = bus->priv; -+ priv->mdio_base = cbus_emac_base[ii]; -+ -+ priv->mdc_div = mdio_info->mdc_div; -+ if (!priv->mdc_div) -+ priv->mdc_div = 64; -+ -+ dev_info(bus->parent, "%s: mdc_div: %d, phy_mask: %x\n", -+ __func__, priv->mdc_div, bus->phy_mask); -+ mdio_node = of_get_child_by_name(pfe->dev->of_node, "mdio"); -+ if ((mdio_info->id == 0) && mdio_node) { -+ rc = of_mdiobus_register(bus, mdio_node); -+ of_node_put(mdio_node); -+ } else { -+ rc = mdiobus_register(bus); -+ } -+ -+ if (rc) { -+ dev_err(bus->parent, "mdiobus_register(%s) failed\n", -+ bus->name); -+ goto err_mdioregister; -+ } -+ -+ priv->mii_bus = bus; -+ pfe->mdio.mdio_priv[ii] = priv; -+ -+ pfe_eth_mdio_reset(bus); -+ -+ return 0; -+ -+err_mdioregister: -+ mdiobus_free(bus); -+err_mdioalloc: -+ return rc; -+} -+ -+/* pfe_eth_mdio_exit -+ */ -+static void pfe_eth_mdio_exit(struct pfe *pfe, -+ int ii) -+{ -+ struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[ii]; -+ struct mii_bus *bus = mdio_priv->mii_bus; -+ -+ if (!bus) -+ return; -+ mdiobus_unregister(bus); -+ mdiobus_free(bus); -+} -+ -+/* pfe_get_phydev_speed -+ */ -+static int pfe_get_phydev_speed(struct phy_device *phydev) -+{ -+ switch (phydev->speed) { -+ case 10: -+ return SPEED_10M; -+ case 100: -+ return SPEED_100M; -+ case 1000: -+ default: -+ return SPEED_1000M; -+ } -+} -+ -+/* pfe_set_rgmii_speed -+ */ -+#define RGMIIPCR 0x434 -+/* RGMIIPCR bit definitions*/ -+#define SCFG_RGMIIPCR_EN_AUTO (0x00000008) -+#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004) -+#define SCFG_RGMIIPCR_SETSP_100M (0x00000000) -+#define SCFG_RGMIIPCR_SETSP_10M (0x00000002) -+#define SCFG_RGMIIPCR_SETFD (0x00000001) -+ -+#define MDIOSELCR 0x484 -+#define MDIOSEL_SERDES 0x0 -+#define MDIOSEL_EXTPHY 0x80000000 -+ -+static void pfe_set_rgmii_speed(struct phy_device *phydev) -+{ -+ u32 rgmii_pcr; -+ -+ regmap_read(pfe->scfg, RGMIIPCR, &rgmii_pcr); -+ rgmii_pcr &= ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M); -+ -+ switch (phydev->speed) { -+ case 10: -+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M; -+ break; -+ case 1000: -+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M; -+ break; -+ case 100: -+ default: -+ /* Default is 100M */ -+ break; -+ } -+ regmap_write(pfe->scfg, RGMIIPCR, rgmii_pcr); -+} -+ -+/* pfe_get_phydev_duplex -+ */ -+static int pfe_get_phydev_duplex(struct phy_device *phydev) -+{ -+ /*return (phydev->duplex == DUPLEX_HALF) ? DUP_HALF:DUP_FULL ; */ -+ return DUPLEX_FULL; -+} -+ -+/* pfe_eth_adjust_link -+ */ -+static void pfe_eth_adjust_link(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ unsigned long flags; -+ struct phy_device *phydev = priv->phydev; -+ int new_state = 0; -+ -+ netif_info(priv, drv, ndev, "%s\n", __func__); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ -+ if (phydev->link) { -+ /* -+ * Now we make sure that we can be in full duplex mode. -+ * If not, we operate in half-duplex mode. -+ */ -+ if (phydev->duplex != priv->oldduplex) { -+ new_state = 1; -+ gemac_set_duplex(priv->EMAC_baseaddr, -+ pfe_get_phydev_duplex(phydev)); -+ priv->oldduplex = phydev->duplex; -+ } -+ -+ if (phydev->speed != priv->oldspeed) { -+ new_state = 1; -+ gemac_set_speed(priv->EMAC_baseaddr, -+ pfe_get_phydev_speed(phydev)); -+ if (priv->einfo->mii_config == -+ PHY_INTERFACE_MODE_RGMII_ID) -+ pfe_set_rgmii_speed(phydev); -+ priv->oldspeed = phydev->speed; -+ } -+ -+ if (!priv->oldlink) { -+ new_state = 1; -+ priv->oldlink = 1; -+ } -+ -+ } else if (priv->oldlink) { -+ new_state = 1; -+ priv->oldlink = 0; -+ priv->oldspeed = 0; -+ priv->oldduplex = -1; -+ } -+ -+ if (new_state && netif_msg_link(priv)) -+ phy_print_status(phydev); -+ -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ /* Now, dump the details to the cdev. -+ * XXX: Locking would be required? (uniprocess arch) -+ * Or, maybe move it in spinlock above -+ */ -+ if (us && priv->einfo->gem_id < PFE_CDEV_ETH_COUNT) { -+ pr_debug("Changing link state from (%u) to (%u) for ID=(%u)\n", -+ link_states[priv->einfo->gem_id].state, -+ phydev->link, -+ priv->einfo->gem_id); -+ link_states[priv->einfo->gem_id].phy_id = priv->einfo->gem_id; -+ link_states[priv->einfo->gem_id].state = phydev->link; -+ } -+} -+ -+/* pfe_phy_exit -+ */ -+static void pfe_phy_exit(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ netif_info(priv, drv, ndev, "%s\n", __func__); -+ -+ phy_disconnect(priv->phydev); -+ priv->phydev = NULL; -+} -+ -+/* pfe_eth_stop -+ */ -+static void pfe_eth_stop(struct net_device *ndev, int wake) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ netif_info(priv, drv, ndev, "%s\n", __func__); -+ -+ if (wake) { -+ gemac_tx_disable(priv->EMAC_baseaddr); -+ } else { -+ gemac_disable(priv->EMAC_baseaddr); -+ gpi_disable(priv->GPI_baseaddr); -+ -+ if (priv->phydev) -+ phy_stop(priv->phydev); -+ } -+} -+ -+/* pfe_eth_start -+ */ -+static int pfe_eth_start(struct pfe_eth_priv_s *priv) -+{ -+ netif_info(priv, drv, priv->ndev, "%s\n", __func__); -+ -+ if (priv->phydev) -+ phy_start(priv->phydev); -+ -+ gpi_enable(priv->GPI_baseaddr); -+ gemac_enable(priv->EMAC_baseaddr); -+ -+ return 0; -+} -+ -+/* -+ * Configure on chip serdes through mdio -+ */ -+static void ls1012a_configure_serdes(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *eth_priv = netdev_priv(ndev); -+ struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[eth_priv->id]; -+ int sgmii_2500 = 0; -+ struct mii_bus *bus = mdio_priv->mii_bus; -+ u16 value = 0; -+ -+ if (eth_priv->einfo->mii_config == PHY_INTERFACE_MODE_2500SGMII) -+ sgmii_2500 = 1; -+ -+ netif_info(eth_priv, drv, ndev, "%s\n", __func__); -+ /* PCS configuration done with corresponding GEMAC */ -+ -+ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR); -+ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR); -+ -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST); -+ -+ if (sgmii_2500) { -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS -+ | SGMII_EN); -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII, -+ SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII); -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120); -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7); -+ /* Autonegotiation need to be disabled for 2.5G SGMII mode*/ -+ value = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G; -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value); -+ } else { -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, -+ SGMII_SPEED_1GBPS -+ | SGMII_USE_SGMII_AN -+ | SGMII_EN); -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII, -+ SGMII_DEV_ABIL_EEE_CLK_STP_EN -+ | 0xa0 -+ | SGMII_DEV_ABIL_SGMII); -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400); -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0); -+ value = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G; -+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value); -+ } -+} -+ -+/* -+ * pfe_phy_init -+ * -+ */ -+static int pfe_phy_init(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ struct phy_device *phydev; -+ char phy_id[MII_BUS_ID_SIZE + 3]; -+ char bus_id[MII_BUS_ID_SIZE]; -+ phy_interface_t interface; -+ -+ priv->oldlink = 0; -+ priv->oldspeed = 0; -+ priv->oldduplex = -1; -+ -+ snprintf(bus_id, MII_BUS_ID_SIZE, "ls1012a-%d", 0); -+ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, -+ priv->einfo->phy_id); -+ netif_info(priv, drv, ndev, "%s: %s\n", __func__, phy_id); -+ interface = priv->einfo->mii_config; -+ if ((interface == PHY_INTERFACE_MODE_SGMII) || -+ (interface == PHY_INTERFACE_MODE_2500SGMII)) { -+ /*Configure SGMII PCS */ -+ if (pfe->scfg) { -+ /* Config MDIO from serdes */ -+ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES); -+ } -+ ls1012a_configure_serdes(ndev); -+ } -+ -+ if (pfe->scfg) { -+ /*Config MDIO from PAD */ -+ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY); -+ } -+ -+ priv->oldlink = 0; -+ priv->oldspeed = 0; -+ priv->oldduplex = -1; -+ pr_info("%s interface %x\n", __func__, interface); -+ -+ if (priv->phy_node) { -+ phydev = of_phy_connect(ndev, priv->phy_node, -+ pfe_eth_adjust_link, 0, -+ priv->einfo->mii_config); -+ if (!(phydev)) { -+ netdev_err(ndev, "Unable to connect to phy\n"); -+ return -ENODEV; -+ } -+ -+ } else { -+ phydev = phy_connect(ndev, phy_id, -+ &pfe_eth_adjust_link, interface); -+ if (IS_ERR(phydev)) { -+ netdev_err(ndev, "Unable to connect to phy\n"); -+ return PTR_ERR(phydev); -+ } -+ } -+ -+ priv->phydev = phydev; -+ phydev->irq = PHY_POLL; -+ -+ return 0; -+} -+ -+/* pfe_gemac_init -+ */ -+static int pfe_gemac_init(struct pfe_eth_priv_s *priv) -+{ -+ struct gemac_cfg cfg; -+ -+ netif_info(priv, ifup, priv->ndev, "%s\n", __func__); -+ -+ cfg.mode = 0; -+ cfg.speed = SPEED_1000M; -+ cfg.duplex = DUPLEX_FULL; -+ -+ gemac_set_config(priv->EMAC_baseaddr, &cfg); -+ gemac_allow_broadcast(priv->EMAC_baseaddr); -+ gemac_enable_1536_rx(priv->EMAC_baseaddr); -+ gemac_enable_stacked_vlan(priv->EMAC_baseaddr); -+ gemac_enable_pause_rx(priv->EMAC_baseaddr); -+ gemac_set_bus_width(priv->EMAC_baseaddr, 64); -+ -+ /*GEM will perform checksum verifications*/ -+ if (priv->ndev->features & NETIF_F_RXCSUM) -+ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr); -+ else -+ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr); -+ -+ return 0; -+} -+ -+/* pfe_eth_event_handler -+ */ -+static int pfe_eth_event_handler(void *data, int event, int qno) -+{ -+ struct pfe_eth_priv_s *priv = data; -+ -+ switch (event) { -+ case EVENT_RX_PKT_IND: -+ -+ if (qno == 0) { -+ if (napi_schedule_prep(&priv->high_napi)) { -+ netif_info(priv, intr, priv->ndev, -+ "%s: schedule high prio poll\n" -+ , __func__); -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_SCHED_COUNT]++; -+#endif -+ -+ __napi_schedule(&priv->high_napi); -+ } -+ } else if (qno == 1) { -+ if (napi_schedule_prep(&priv->low_napi)) { -+ netif_info(priv, intr, priv->ndev, -+ "%s: schedule low prio poll\n" -+ , __func__); -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_SCHED_COUNT]++; -+#endif -+ __napi_schedule(&priv->low_napi); -+ } -+ } else if (qno == 2) { -+ if (napi_schedule_prep(&priv->lro_napi)) { -+ netif_info(priv, intr, priv->ndev, -+ "%s: schedule lro prio poll\n" -+ , __func__); -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_SCHED_COUNT]++; -+#endif -+ __napi_schedule(&priv->lro_napi); -+ } -+ } -+ -+ break; -+ -+ case EVENT_TXDONE_IND: -+ pfe_eth_flush_tx(priv); -+ hif_lib_event_handler_start(&priv->client, EVENT_TXDONE_IND, 0); -+ break; -+ case EVENT_HIGH_RX_WM: -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static int pfe_eth_change_mtu(struct net_device *ndev, int new_mtu) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ ndev->mtu = new_mtu; -+ new_mtu += ETH_HLEN + ETH_FCS_LEN; -+ gemac_set_rx_max_fl(priv->EMAC_baseaddr, new_mtu); -+ -+ return 0; -+} -+ -+/* pfe_eth_open -+ */ -+static int pfe_eth_open(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ struct hif_client_s *client; -+ int rc; -+ -+ netif_info(priv, ifup, ndev, "%s\n", __func__); -+ -+ /* Register client driver with HIF */ -+ client = &priv->client; -+ memset(client, 0, sizeof(*client)); -+ client->id = PFE_CL_GEM0 + priv->id; -+ client->tx_qn = emac_txq_cnt; -+ client->rx_qn = EMAC_RXQ_CNT; -+ client->priv = priv; -+ client->pfe = priv->pfe; -+ client->event_handler = pfe_eth_event_handler; -+ -+ client->tx_qsize = EMAC_TXQ_DEPTH; -+ client->rx_qsize = EMAC_RXQ_DEPTH; -+ -+ rc = hif_lib_client_register(client); -+ if (rc) { -+ netdev_err(ndev, "%s: hif_lib_client_register(%d) failed\n", -+ __func__, client->id); -+ goto err0; -+ } -+ -+ netif_info(priv, drv, ndev, "%s: registered client: %p\n", __func__, -+ client); -+ -+ pfe_gemac_init(priv); -+ -+ if (!is_valid_ether_addr(ndev->dev_addr)) { -+ netdev_err(ndev, "%s: invalid MAC address\n", __func__); -+ rc = -EADDRNOTAVAIL; -+ goto err1; -+ } -+ -+ gemac_set_laddrN(priv->EMAC_baseaddr, -+ (struct pfe_mac_addr *)ndev->dev_addr, 1); -+ -+ napi_enable(&priv->high_napi); -+ napi_enable(&priv->low_napi); -+ napi_enable(&priv->lro_napi); -+ -+ rc = pfe_eth_start(priv); -+ -+ netif_tx_wake_all_queues(ndev); -+ -+ return rc; -+ -+err1: -+ hif_lib_client_unregister(&priv->client); -+ -+err0: -+ return rc; -+} -+ -+/* -+ * pfe_eth_shutdown -+ */ -+int pfe_eth_shutdown(struct net_device *ndev, int wake) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ int i, qstatus, id; -+ unsigned long next_poll = jiffies + 1, end = jiffies + -+ (TX_POLL_TIMEOUT_MS * HZ) / 1000; -+ int tx_pkts, prv_tx_pkts; -+ -+ netif_info(priv, ifdown, ndev, "%s\n", __func__); -+ -+ for (i = 0; i < emac_txq_cnt; i++) -+ hrtimer_cancel(&priv->fast_tx_timeout[i].timer); -+ -+ netif_tx_stop_all_queues(ndev); -+ -+ do { -+ tx_pkts = 0; -+ pfe_eth_flush_tx(priv); -+ -+ for (i = 0; i < emac_txq_cnt; i++) -+ tx_pkts += hif_lib_tx_pending(&priv->client, i); -+ -+ if (tx_pkts) { -+ /*Don't wait forever, break if we cross max timeout */ -+ if (time_after(jiffies, end)) { -+ pr_err( -+ "(%s)Tx is not complete after %dmsec\n", -+ ndev->name, TX_POLL_TIMEOUT_MS); -+ break; -+ } -+ -+ pr_info("%s : (%s) Waiting for tx packets to free. Pending tx pkts = %d.\n" -+ , __func__, ndev->name, tx_pkts); -+ if (need_resched()) -+ schedule(); -+ } -+ -+ } while (tx_pkts); -+ -+ end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000; -+ -+ prv_tx_pkts = tmu_pkts_processed(priv->id); -+ /* -+ * Wait till TMU transmits all pending packets -+ * poll tmu_qstatus and pkts processed by TMU for every 10ms -+ * Consider TMU is busy, If we see TMU qeueu pending or any packets -+ * processed by TMU -+ */ -+ while (1) { -+ if (time_after(jiffies, next_poll)) { -+ tx_pkts = tmu_pkts_processed(priv->id); -+ qstatus = tmu_qstatus(priv->id) & 0x7ffff; -+ -+ if (!qstatus && (tx_pkts == prv_tx_pkts)) -+ break; -+ /* Don't wait forever, break if we cross max -+ * timeout(TX_POLL_TIMEOUT_MS) -+ */ -+ if (time_after(jiffies, end)) { -+ pr_err("TMU%d is busy after %dmsec\n", -+ priv->id, TX_POLL_TIMEOUT_MS); -+ break; -+ } -+ prv_tx_pkts = tx_pkts; -+ next_poll++; -+ } -+ if (need_resched()) -+ schedule(); -+ } -+ /* Wait for some more time to complete transmitting packet if any */ -+ next_poll = jiffies + 1; -+ while (1) { -+ if (time_after(jiffies, next_poll)) -+ break; -+ if (need_resched()) -+ schedule(); -+ } -+ -+ pfe_eth_stop(ndev, wake); -+ -+ napi_disable(&priv->lro_napi); -+ napi_disable(&priv->low_napi); -+ napi_disable(&priv->high_napi); -+ -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { -+ pe_dmem_write(id, 0, CLASS_DM_CRC_VALIDATED -+ + (priv->id * 4), 4); -+ } -+ -+ hif_lib_client_unregister(&priv->client); -+ -+ return 0; -+} -+ -+/* pfe_eth_close -+ * -+ */ -+static int pfe_eth_close(struct net_device *ndev) -+{ -+ pfe_eth_shutdown(ndev, 0); -+ -+ return 0; -+} -+ -+/* pfe_eth_suspend -+ * -+ * return value : 1 if netdevice is configured to wakeup system -+ * 0 otherwise -+ */ -+int pfe_eth_suspend(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ int retval = 0; -+ -+ if (priv->wol) { -+ gemac_set_wol(priv->EMAC_baseaddr, priv->wol); -+ retval = 1; -+ } -+ pfe_eth_shutdown(ndev, priv->wol); -+ -+ return retval; -+} -+ -+/* pfe_eth_resume -+ * -+ */ -+int pfe_eth_resume(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ if (priv->wol) -+ gemac_set_wol(priv->EMAC_baseaddr, 0); -+ gemac_tx_enable(priv->EMAC_baseaddr); -+ -+ return pfe_eth_open(ndev); -+} -+ -+/* pfe_eth_get_queuenum -+ */ -+static int pfe_eth_get_queuenum(struct pfe_eth_priv_s *priv, struct sk_buff -+ *skb) -+{ -+ int queuenum = 0; -+ unsigned long flags; -+ -+ /* Get the Fast Path queue number */ -+ /* -+ * Use conntrack mark (if conntrack exists), then packet mark (if any), -+ * then fallback to default -+ */ -+#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK) -+ if (skb->_nfct) { -+ enum ip_conntrack_info cinfo; -+ struct nf_conn *ct; -+ -+ ct = nf_ct_get(skb, &cinfo); -+ -+ if (ct) { -+ u32 connmark; -+ -+ connmark = ct->mark; -+ -+ if ((connmark & 0x80000000) && priv->id != 0) -+ connmark >>= 16; -+ -+ queuenum = connmark & EMAC_QUEUENUM_MASK; -+ } -+ } else {/* continued after #endif ... */ -+#endif -+ if (skb->mark) { -+ queuenum = skb->mark & EMAC_QUEUENUM_MASK; -+ } else { -+ spin_lock_irqsave(&priv->lock, flags); -+ queuenum = priv->default_priority & EMAC_QUEUENUM_MASK; -+ spin_unlock_irqrestore(&priv->lock, flags); -+ } -+#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK) -+ } -+#endif -+ return queuenum; -+} -+ -+/* pfe_eth_might_stop_tx -+ * -+ */ -+static int pfe_eth_might_stop_tx(struct pfe_eth_priv_s *priv, int queuenum, -+ struct netdev_queue *tx_queue, -+ unsigned int n_desc, -+ unsigned int n_segs) -+{ -+ ktime_t kt; -+ int tried = 0; -+ -+try_again: -+ if (unlikely((__hif_tx_avail(&pfe->hif) < n_desc) || -+ (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) || -+ (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs))) { -+ if (!tried) { -+ __hif_lib_update_credit(&priv->client, queuenum); -+ tried = 1; -+ goto try_again; -+ } -+#ifdef PFE_ETH_TX_STATS -+ if (__hif_tx_avail(&pfe->hif) < n_desc) { -+ priv->stop_queue_hif[queuenum]++; -+ } else if (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) { -+ priv->stop_queue_hif_client[queuenum]++; -+ } else if (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < -+ n_segs) { -+ priv->stop_queue_credit[queuenum]++; -+ } -+ priv->stop_queue_total[queuenum]++; -+#endif -+ netif_tx_stop_queue(tx_queue); -+ -+ kt = ktime_set(0, LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS * -+ NSEC_PER_MSEC); -+ hrtimer_start(&priv->fast_tx_timeout[queuenum].timer, kt, -+ HRTIMER_MODE_REL); -+ return -1; -+ } else { -+ return 0; -+ } -+} -+ -+#define SA_MAX_OP 2 -+/* pfe_hif_send_packet -+ * -+ * At this level if TX fails we drop the packet -+ */ -+static void pfe_hif_send_packet(struct sk_buff *skb, struct pfe_eth_priv_s -+ *priv, int queuenum) -+{ -+ struct skb_shared_info *sh = skb_shinfo(skb); -+ unsigned int nr_frags; -+ u32 ctrl = 0; -+ -+ netif_info(priv, tx_queued, priv->ndev, "%s\n", __func__); -+ -+ if (skb_is_gso(skb)) { -+ priv->stats.tx_dropped++; -+ return; -+ } -+ -+ if (skb->ip_summed == CHECKSUM_PARTIAL) -+ ctrl = HIF_CTRL_TX_CHECKSUM; -+ -+ nr_frags = sh->nr_frags; -+ -+ if (nr_frags) { -+ skb_frag_t *f; -+ int i; -+ -+ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, -+ skb_headlen(skb), ctrl, HIF_FIRST_BUFFER, -+ skb); -+ -+ for (i = 0; i < nr_frags - 1; i++) { -+ f = &sh->frags[i]; -+ __hif_lib_xmit_pkt(&priv->client, queuenum, -+ skb_frag_address(f), -+ skb_frag_size(f), -+ 0x0, 0x0, skb); -+ } -+ -+ f = &sh->frags[i]; -+ -+ __hif_lib_xmit_pkt(&priv->client, queuenum, -+ skb_frag_address(f), skb_frag_size(f), -+ 0x0, HIF_LAST_BUFFER | HIF_DATA_VALID, -+ skb); -+ -+ netif_info(priv, tx_queued, priv->ndev, -+ "%s: pkt sent successfully skb:%p nr_frags:%d len:%d\n", -+ __func__, skb, nr_frags, skb->len); -+ } else { -+ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data, -+ skb->len, ctrl, HIF_FIRST_BUFFER | -+ HIF_LAST_BUFFER | HIF_DATA_VALID, -+ skb); -+ netif_info(priv, tx_queued, priv->ndev, -+ "%s: pkt sent successfully skb:%p len:%d\n", -+ __func__, skb, skb->len); -+ } -+ hif_tx_dma_start(); -+ priv->stats.tx_packets++; -+ priv->stats.tx_bytes += skb->len; -+ hif_lib_tx_credit_use(pfe, priv->id, queuenum, 1); -+} -+ -+/* pfe_eth_flush_txQ -+ */ -+static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int -+ from_tx, int n_desc) -+{ -+ struct sk_buff *skb; -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, -+ tx_q_num); -+ unsigned int flags; -+ -+ netif_info(priv, tx_done, priv->ndev, "%s\n", __func__); -+ -+ if (!from_tx) -+ __netif_tx_lock_bh(tx_queue); -+ -+ /* Clean HIF and client queue */ -+ while ((skb = hif_lib_tx_get_next_complete(&priv->client, -+ tx_q_num, &flags, -+ HIF_TX_DESC_NT))) { -+ if (flags & HIF_DATA_VALID) -+ dev_kfree_skb_any(skb); -+ } -+ if (!from_tx) -+ __netif_tx_unlock_bh(tx_queue); -+} -+ -+/* pfe_eth_flush_tx -+ */ -+static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv) -+{ -+ int ii; -+ -+ netif_info(priv, tx_done, priv->ndev, "%s\n", __func__); -+ -+ for (ii = 0; ii < emac_txq_cnt; ii++) { -+ pfe_eth_flush_txQ(priv, ii, 0, 0); -+ __hif_lib_update_credit(&priv->client, ii); -+ } -+} -+ -+void pfe_tx_get_req_desc(struct sk_buff *skb, unsigned int *n_desc, unsigned int -+ *n_segs) -+{ -+ struct skb_shared_info *sh = skb_shinfo(skb); -+ -+ /* Scattered data */ -+ if (sh->nr_frags) { -+ *n_desc = sh->nr_frags + 1; -+ *n_segs = 1; -+ /* Regular case */ -+ } else { -+ *n_desc = 1; -+ *n_segs = 1; -+ } -+} -+ -+/* pfe_eth_send_packet -+ */ -+static int pfe_eth_send_packet(struct sk_buff *skb, struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ int tx_q_num = skb_get_queue_mapping(skb); -+ int n_desc, n_segs; -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, -+ tx_q_num); -+ -+ netif_info(priv, tx_queued, ndev, "%s\n", __func__); -+ -+ if ((!skb_is_gso(skb)) && (skb_headroom(skb) < (PFE_PKT_HEADER_SZ + -+ sizeof(unsigned long)))) { -+ netif_warn(priv, tx_err, priv->ndev, "%s: copying skb\n", -+ __func__); -+ -+ if (pskb_expand_head(skb, (PFE_PKT_HEADER_SZ + sizeof(unsigned -+ long)), 0, GFP_ATOMIC)) { -+ /* No need to re-transmit, no way to recover*/ -+ kfree_skb(skb); -+ priv->stats.tx_dropped++; -+ return NETDEV_TX_OK; -+ } -+ } -+ -+ pfe_tx_get_req_desc(skb, &n_desc, &n_segs); -+ -+ hif_tx_lock(&pfe->hif); -+ if (unlikely(pfe_eth_might_stop_tx(priv, tx_q_num, tx_queue, n_desc, -+ n_segs))) { -+#ifdef PFE_ETH_TX_STATS -+ if (priv->was_stopped[tx_q_num]) { -+ priv->clean_fail[tx_q_num]++; -+ priv->was_stopped[tx_q_num] = 0; -+ } -+#endif -+ hif_tx_unlock(&pfe->hif); -+ return NETDEV_TX_BUSY; -+ } -+ -+ pfe_hif_send_packet(skb, priv, tx_q_num); -+ -+ hif_tx_unlock(&pfe->hif); -+ -+ tx_queue->trans_start = jiffies; -+ -+#ifdef PFE_ETH_TX_STATS -+ priv->was_stopped[tx_q_num] = 0; -+#endif -+ -+ return NETDEV_TX_OK; -+} -+ -+/* pfe_eth_select_queue -+ * -+ */ -+static u16 pfe_eth_select_queue(struct net_device *ndev, struct sk_buff *skb, -+ struct net_device *sb_dev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ return pfe_eth_get_queuenum(priv, skb); -+} -+ -+/* pfe_eth_get_stats -+ */ -+static struct net_device_stats *pfe_eth_get_stats(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ -+ netif_info(priv, drv, ndev, "%s\n", __func__); -+ -+ return &priv->stats; -+} -+ -+/* pfe_eth_set_mac_address -+ */ -+static int pfe_eth_set_mac_address(struct net_device *ndev, void *addr) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ struct sockaddr *sa = addr; -+ -+ netif_info(priv, drv, ndev, "%s\n", __func__); -+ -+ if (!is_valid_ether_addr(sa->sa_data)) -+ return -EADDRNOTAVAIL; -+ -+ memcpy(ndev->dev_addr, sa->sa_data, ETH_ALEN); -+ -+ gemac_set_laddrN(priv->EMAC_baseaddr, -+ (struct pfe_mac_addr *)ndev->dev_addr, 1); -+ -+ return 0; -+} -+ -+/* pfe_eth_enet_addr_byte_mac -+ */ -+int pfe_eth_enet_addr_byte_mac(u8 *enet_byte_addr, -+ struct pfe_mac_addr *enet_addr) -+{ -+ if (!enet_byte_addr || !enet_addr) { -+ return -1; -+ -+ } else { -+ enet_addr->bottom = enet_byte_addr[0] | -+ (enet_byte_addr[1] << 8) | -+ (enet_byte_addr[2] << 16) | -+ (enet_byte_addr[3] << 24); -+ enet_addr->top = enet_byte_addr[4] | -+ (enet_byte_addr[5] << 8); -+ return 0; -+ } -+} -+ -+/* pfe_eth_set_multi -+ */ -+static void pfe_eth_set_multi(struct net_device *ndev) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ struct pfe_mac_addr hash_addr; /* hash register structure */ -+ /* specific mac address register structure */ -+ struct pfe_mac_addr spec_addr; -+ int result; /* index into hash register to set.. */ -+ int uc_count = 0; -+ struct netdev_hw_addr *ha; -+ -+ if (ndev->flags & IFF_PROMISC) { -+ netif_info(priv, drv, ndev, "entering promiscuous mode\n"); -+ -+ priv->promisc = 1; -+ gemac_enable_copy_all(priv->EMAC_baseaddr); -+ } else { -+ priv->promisc = 0; -+ gemac_disable_copy_all(priv->EMAC_baseaddr); -+ } -+ -+ /* Enable broadcast frame reception if required. */ -+ if (ndev->flags & IFF_BROADCAST) { -+ gemac_allow_broadcast(priv->EMAC_baseaddr); -+ } else { -+ netif_info(priv, drv, ndev, -+ "disabling broadcast frame reception\n"); -+ -+ gemac_no_broadcast(priv->EMAC_baseaddr); -+ } -+ -+ if (ndev->flags & IFF_ALLMULTI) { -+ /* Set the hash to rx all multicast frames */ -+ hash_addr.bottom = 0xFFFFFFFF; -+ hash_addr.top = 0xFFFFFFFF; -+ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr); -+ netdev_for_each_uc_addr(ha, ndev) { -+ if (uc_count >= MAX_UC_SPEC_ADDR_REG) -+ break; -+ pfe_eth_enet_addr_byte_mac(ha->addr, &spec_addr); -+ gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr, -+ uc_count + 2); -+ uc_count++; -+ } -+ } else if ((netdev_mc_count(ndev) > 0) || (netdev_uc_count(ndev))) { -+ u8 *addr; -+ -+ hash_addr.bottom = 0; -+ hash_addr.top = 0; -+ -+ netdev_for_each_mc_addr(ha, ndev) { -+ addr = ha->addr; -+ -+ netif_info(priv, drv, ndev, -+ "adding multicast address %X:%X:%X:%X:%X:%X to gem filter\n", -+ addr[0], addr[1], addr[2], -+ addr[3], addr[4], addr[5]); -+ -+ result = pfe_eth_get_hash(addr); -+ -+ if (result < EMAC_HASH_REG_BITS) { -+ if (result < 32) -+ hash_addr.bottom |= (1 << result); -+ else -+ hash_addr.top |= (1 << (result - 32)); -+ } else { -+ break; -+ } -+ } -+ -+ uc_count = -1; -+ netdev_for_each_uc_addr(ha, ndev) { -+ addr = ha->addr; -+ -+ if (++uc_count < MAX_UC_SPEC_ADDR_REG) { -+ netdev_info(ndev, -+ "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem filter\n", -+ addr[0], addr[1], addr[2], -+ addr[3], addr[4], addr[5]); -+ pfe_eth_enet_addr_byte_mac(addr, &spec_addr); -+ gemac_set_laddrN(priv->EMAC_baseaddr, -+ &spec_addr, uc_count + 2); -+ } else { -+ netif_info(priv, drv, ndev, -+ "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem hash\n", -+ addr[0], addr[1], addr[2], -+ addr[3], addr[4], addr[5]); -+ -+ result = pfe_eth_get_hash(addr); -+ if (result >= EMAC_HASH_REG_BITS) { -+ break; -+ -+ } else { -+ if (result < 32) -+ hash_addr.bottom |= (1 << -+ result); -+ else -+ hash_addr.top |= (1 << -+ (result - 32)); -+ } -+ } -+ } -+ -+ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr); -+ } -+ -+ if (!(netdev_uc_count(ndev) >= MAX_UC_SPEC_ADDR_REG)) { -+ /* -+ * Check if there are any specific address HW registers that -+ * need to be flushed -+ */ -+ for (uc_count = netdev_uc_count(ndev); uc_count < -+ MAX_UC_SPEC_ADDR_REG; uc_count++) -+ gemac_clear_laddrN(priv->EMAC_baseaddr, uc_count + 2); -+ } -+ -+ if (ndev->flags & IFF_LOOPBACK) -+ gemac_set_loop(priv->EMAC_baseaddr, LB_LOCAL); -+} -+ -+/* pfe_eth_set_features -+ */ -+static int pfe_eth_set_features(struct net_device *ndev, netdev_features_t -+ features) -+{ -+ struct pfe_eth_priv_s *priv = netdev_priv(ndev); -+ int rc = 0; -+ -+ if (features & NETIF_F_RXCSUM) -+ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr); -+ else -+ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr); -+ return rc; -+} -+ -+/* pfe_eth_fast_tx_timeout -+ */ -+static enum hrtimer_restart pfe_eth_fast_tx_timeout(struct hrtimer *timer) -+{ -+ struct pfe_eth_fast_timer *fast_tx_timeout = container_of(timer, struct -+ pfe_eth_fast_timer, -+ timer); -+ struct pfe_eth_priv_s *priv = container_of(fast_tx_timeout->base, -+ struct pfe_eth_priv_s, -+ fast_tx_timeout); -+ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev, -+ fast_tx_timeout->queuenum); -+ -+ if (netif_tx_queue_stopped(tx_queue)) { -+#ifdef PFE_ETH_TX_STATS -+ priv->was_stopped[fast_tx_timeout->queuenum] = 1; -+#endif -+ netif_tx_wake_queue(tx_queue); -+ } -+ -+ return HRTIMER_NORESTART; -+} -+ -+/* pfe_eth_fast_tx_timeout_init -+ */ -+static void pfe_eth_fast_tx_timeout_init(struct pfe_eth_priv_s *priv) -+{ -+ int i; -+ -+ for (i = 0; i < emac_txq_cnt; i++) { -+ priv->fast_tx_timeout[i].queuenum = i; -+ hrtimer_init(&priv->fast_tx_timeout[i].timer, CLOCK_MONOTONIC, -+ HRTIMER_MODE_REL); -+ priv->fast_tx_timeout[i].timer.function = -+ pfe_eth_fast_tx_timeout; -+ priv->fast_tx_timeout[i].base = priv->fast_tx_timeout; -+ } -+} -+ -+static struct sk_buff *pfe_eth_rx_skb(struct net_device *ndev, -+ struct pfe_eth_priv_s *priv, -+ unsigned int qno) -+{ -+ void *buf_addr; -+ unsigned int rx_ctrl; -+ unsigned int desc_ctrl = 0; -+ struct hif_ipsec_hdr *ipsec_hdr = NULL; -+ struct sk_buff *skb; -+ struct sk_buff *skb_frag, *skb_frag_last = NULL; -+ int length = 0, offset; -+ -+ skb = priv->skb_inflight[qno]; -+ -+ if (skb) { -+ skb_frag_last = skb_shinfo(skb)->frag_list; -+ if (skb_frag_last) { -+ while (skb_frag_last->next) -+ skb_frag_last = skb_frag_last->next; -+ } -+ } -+ -+ while (!(desc_ctrl & CL_DESC_LAST)) { -+ buf_addr = hif_lib_receive_pkt(&priv->client, qno, &length, -+ &offset, &rx_ctrl, &desc_ctrl, -+ (void **)&ipsec_hdr); -+ if (!buf_addr) -+ goto incomplete; -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_DESC_COUNT]++; -+#endif -+ -+ /* First frag */ -+ if (desc_ctrl & CL_DESC_FIRST) { -+ skb = build_skb(buf_addr, 0); -+ if (unlikely(!skb)) -+ goto pkt_drop; -+ -+ skb_reserve(skb, offset); -+ skb_put(skb, length); -+ skb->dev = ndev; -+ -+ if ((ndev->features & NETIF_F_RXCSUM) && (rx_ctrl & -+ HIF_CTRL_RX_CHECKSUMMED)) -+ skb->ip_summed = CHECKSUM_UNNECESSARY; -+ else -+ skb_checksum_none_assert(skb); -+ -+ } else { -+ /* Next frags */ -+ if (unlikely(!skb)) { -+ pr_err("%s: NULL skb_inflight\n", -+ __func__); -+ goto pkt_drop; -+ } -+ -+ skb_frag = build_skb(buf_addr, 0); -+ -+ if (unlikely(!skb_frag)) { -+ kfree(buf_addr); -+ goto pkt_drop; -+ } -+ -+ skb_reserve(skb_frag, offset); -+ skb_put(skb_frag, length); -+ -+ skb_frag->dev = ndev; -+ -+ if (skb_shinfo(skb)->frag_list) -+ skb_frag_last->next = skb_frag; -+ else -+ skb_shinfo(skb)->frag_list = skb_frag; -+ -+ skb->truesize += skb_frag->truesize; -+ skb->data_len += length; -+ skb->len += length; -+ skb_frag_last = skb_frag; -+ } -+ } -+ -+ priv->skb_inflight[qno] = NULL; -+ return skb; -+ -+incomplete: -+ priv->skb_inflight[qno] = skb; -+ return NULL; -+ -+pkt_drop: -+ priv->skb_inflight[qno] = NULL; -+ -+ if (skb) -+ kfree_skb(skb); -+ else -+ kfree(buf_addr); -+ -+ priv->stats.rx_errors++; -+ -+ return NULL; -+} -+ -+/* pfe_eth_poll -+ */ -+static int pfe_eth_poll(struct pfe_eth_priv_s *priv, struct napi_struct *napi, -+ unsigned int qno, int budget) -+{ -+ struct net_device *ndev = priv->ndev; -+ struct sk_buff *skb; -+ int work_done = 0; -+ unsigned int len; -+ -+ netif_info(priv, intr, priv->ndev, "%s\n", __func__); -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_POLL_COUNT]++; -+#endif -+ -+ do { -+ skb = pfe_eth_rx_skb(ndev, priv, qno); -+ -+ if (!skb) -+ break; -+ -+ len = skb->len; -+ -+ /* Packet will be processed */ -+ skb->protocol = eth_type_trans(skb, ndev); -+ -+ netif_receive_skb(skb); -+ -+ priv->stats.rx_packets++; -+ priv->stats.rx_bytes += len; -+ -+ work_done++; -+ -+#ifdef PFE_ETH_NAPI_STATS -+ priv->napi_counters[NAPI_PACKET_COUNT]++; -+#endif -+ -+ } while (work_done < budget); -+ -+ /* -+ * If no Rx receive nor cleanup work was done, exit polling mode. -+ * No more netif_running(dev) check is required here , as this is -+ * checked in net/core/dev.c (2.6.33.5 kernel specific). -+ */ -+ if (work_done < budget) { -+ napi_complete(napi); -+ -+ hif_lib_event_handler_start(&priv->client, EVENT_RX_PKT_IND, -+ qno); -+ } -+#ifdef PFE_ETH_NAPI_STATS -+ else -+ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]++; -+#endif -+ -+ return work_done; -+} -+ -+/* -+ * pfe_eth_lro_poll -+ */ -+static int pfe_eth_lro_poll(struct napi_struct *napi, int budget) -+{ -+ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, -+ lro_napi); -+ -+ netif_info(priv, intr, priv->ndev, "%s\n", __func__); -+ -+ return pfe_eth_poll(priv, napi, 2, budget); -+} -+ -+/* pfe_eth_low_poll -+ */ -+static int pfe_eth_low_poll(struct napi_struct *napi, int budget) -+{ -+ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, -+ low_napi); -+ -+ netif_info(priv, intr, priv->ndev, "%s\n", __func__); -+ -+ return pfe_eth_poll(priv, napi, 1, budget); -+} -+ -+/* pfe_eth_high_poll -+ */ -+static int pfe_eth_high_poll(struct napi_struct *napi, int budget) -+{ -+ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s, -+ high_napi); -+ -+ netif_info(priv, intr, priv->ndev, "%s\n", __func__); -+ -+ return pfe_eth_poll(priv, napi, 0, budget); -+} -+ -+static const struct net_device_ops pfe_netdev_ops = { -+ .ndo_open = pfe_eth_open, -+ .ndo_stop = pfe_eth_close, -+ .ndo_start_xmit = pfe_eth_send_packet, -+ .ndo_select_queue = pfe_eth_select_queue, -+ .ndo_set_rx_mode = pfe_eth_set_multi, -+ .ndo_set_mac_address = pfe_eth_set_mac_address, -+ .ndo_validate_addr = eth_validate_addr, -+ .ndo_change_mtu = pfe_eth_change_mtu, -+ .ndo_get_stats = pfe_eth_get_stats, -+ .ndo_set_features = pfe_eth_set_features, -+}; -+ -+/* pfe_eth_init_one -+ */ -+static int pfe_eth_init_one(struct pfe *pfe, -+ struct ls1012a_pfe_platform_data *pfe_info, -+ int id) -+{ -+ struct net_device *ndev = NULL; -+ struct pfe_eth_priv_s *priv = NULL; -+ struct ls1012a_eth_platform_data *einfo; -+ int err; -+ -+ einfo = (struct ls1012a_eth_platform_data *) -+ pfe_info->ls1012a_eth_pdata; -+ -+ /* einfo never be NULL, but no harm in having this check */ -+ if (!einfo) { -+ pr_err( -+ "%s: pfe missing additional gemacs platform data\n" -+ , __func__); -+ err = -ENODEV; -+ goto err0; -+ } -+ -+ if (us) -+ emac_txq_cnt = EMAC_TXQ_CNT; -+ /* Create an ethernet device instance */ -+ ndev = alloc_etherdev_mq(sizeof(*priv), emac_txq_cnt); -+ -+ if (!ndev) { -+ pr_err("%s: gemac %d device allocation failed\n", -+ __func__, einfo[id].gem_id); -+ err = -ENOMEM; -+ goto err0; -+ } -+ -+ priv = netdev_priv(ndev); -+ priv->ndev = ndev; -+ priv->id = einfo[id].gem_id; -+ priv->pfe = pfe; -+ priv->phy_node = einfo[id].phy_node; -+ -+ SET_NETDEV_DEV(priv->ndev, priv->pfe->dev); -+ -+ pfe->eth.eth_priv[id] = priv; -+ -+ /* Set the info in the priv to the current info */ -+ priv->einfo = &einfo[id]; -+ priv->EMAC_baseaddr = cbus_emac_base[id]; -+ priv->GPI_baseaddr = cbus_gpi_base[id]; -+ -+ spin_lock_init(&priv->lock); -+ -+ pfe_eth_fast_tx_timeout_init(priv); -+ -+ /* Copy the station address into the dev structure, */ -+ memcpy(ndev->dev_addr, einfo[id].mac_addr, ETH_ALEN); -+ -+ if (us) -+ goto phy_init; -+ -+ ndev->mtu = 1500; -+ -+ /* Set MTU limits */ -+ ndev->min_mtu = ETH_MIN_MTU; -+ -+/* -+ * Jumbo frames are not supported on LS1012A rev-1.0. -+ * So max mtu should be restricted to supported frame length. -+ */ -+ if (pfe_errata_a010897) -+ ndev->max_mtu = JUMBO_FRAME_SIZE_V1 - ETH_HLEN - ETH_FCS_LEN; -+ else -+ ndev->max_mtu = JUMBO_FRAME_SIZE_V2 - ETH_HLEN - ETH_FCS_LEN; -+ -+ /*Enable after checksum offload is validated */ -+ ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | -+ NETIF_F_IPV6_CSUM | NETIF_F_SG; -+ -+ /* enabled by default */ -+ ndev->features = ndev->hw_features; -+ -+ priv->usr_features = ndev->features; -+ -+ ndev->netdev_ops = &pfe_netdev_ops; -+ -+ ndev->ethtool_ops = &pfe_ethtool_ops; -+ -+ /* Enable basic messages by default */ -+ priv->msg_enable = NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK | -+ NETIF_MSG_PROBE; -+ -+ netif_napi_add(ndev, &priv->low_napi, pfe_eth_low_poll, -+ HIF_RX_POLL_WEIGHT - 16); -+ netif_napi_add(ndev, &priv->high_napi, pfe_eth_high_poll, -+ HIF_RX_POLL_WEIGHT - 16); -+ netif_napi_add(ndev, &priv->lro_napi, pfe_eth_lro_poll, -+ HIF_RX_POLL_WEIGHT - 16); -+ -+ err = register_netdev(ndev); -+ if (err) { -+ netdev_err(ndev, "register_netdev() failed\n"); -+ goto err1; -+ } -+ -+ if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) || -+ ((pfe_use_old_dts_phy) && -+ (priv->einfo->phy_flags & GEMAC_NO_PHY))) { -+ pr_info("%s: No PHY or fixed-link\n", __func__); -+ goto skip_phy_init; -+ } -+ -+phy_init: -+ device_init_wakeup(&ndev->dev, WAKE_MAGIC); -+ -+ err = pfe_phy_init(ndev); -+ if (err) { -+ netdev_err(ndev, "%s: pfe_phy_init() failed\n", -+ __func__); -+ goto err2; -+ } -+ -+ if (us) { -+ if (priv->phydev) -+ phy_start(priv->phydev); -+ return 0; -+ } -+ -+ netif_carrier_on(ndev); -+ -+skip_phy_init: -+ /* Create all the sysfs files */ -+ if (pfe_eth_sysfs_init(ndev)) -+ goto err3; -+ -+ netif_info(priv, probe, ndev, "%s: created interface, baseaddr: %p\n", -+ __func__, priv->EMAC_baseaddr); -+ -+ return 0; -+ -+err3: -+ pfe_phy_exit(priv->ndev); -+err2: -+ if (us) -+ goto err1; -+ unregister_netdev(ndev); -+err1: -+ free_netdev(priv->ndev); -+err0: -+ return err; -+} -+ -+/* pfe_eth_init -+ */ -+int pfe_eth_init(struct pfe *pfe) -+{ -+ int ii = 0; -+ int err; -+ struct ls1012a_pfe_platform_data *pfe_info; -+ -+ pr_info("%s\n", __func__); -+ -+ cbus_emac_base[0] = EMAC1_BASE_ADDR; -+ cbus_emac_base[1] = EMAC2_BASE_ADDR; -+ -+ cbus_gpi_base[0] = EGPI1_BASE_ADDR; -+ cbus_gpi_base[1] = EGPI2_BASE_ADDR; -+ -+ pfe_info = (struct ls1012a_pfe_platform_data *) -+ pfe->dev->platform_data; -+ if (!pfe_info) { -+ pr_err("%s: pfe missing additional platform data\n", __func__); -+ err = -ENODEV; -+ goto err_pdata; -+ } -+ -+ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) { -+ err = pfe_eth_mdio_init(pfe, pfe_info, ii); -+ if (err) { -+ pr_err("%s: pfe_eth_mdio_init() failed\n", __func__); -+ goto err_mdio_init; -+ } -+ } -+ -+ if (soc_device_match(ls1012a_rev1_soc_attr)) -+ pfe_errata_a010897 = true; -+ else -+ pfe_errata_a010897 = false; -+ -+ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) { -+ err = pfe_eth_init_one(pfe, pfe_info, ii); -+ if (err) -+ goto err_eth_init; -+ } -+ -+ return 0; -+ -+err_eth_init: -+ while (ii--) { -+ pfe_eth_exit_one(pfe->eth.eth_priv[ii]); -+ pfe_eth_mdio_exit(pfe, ii); -+ } -+ -+err_mdio_init: -+err_pdata: -+ return err; -+} -+ -+/* pfe_eth_exit_one -+ */ -+static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv) -+{ -+ netif_info(priv, probe, priv->ndev, "%s\n", __func__); -+ -+ if (!us) -+ pfe_eth_sysfs_exit(priv->ndev); -+ -+ if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) || -+ ((pfe_use_old_dts_phy) && -+ (priv->einfo->phy_flags & GEMAC_NO_PHY))) { -+ pr_info("%s: No PHY or fixed-link\n", __func__); -+ goto skip_phy_exit; -+ } -+ -+ pfe_phy_exit(priv->ndev); -+ -+skip_phy_exit: -+ if (!us) -+ unregister_netdev(priv->ndev); -+ -+ free_netdev(priv->ndev); -+} -+ -+/* pfe_eth_exit -+ */ -+void pfe_eth_exit(struct pfe *pfe) -+{ -+ int ii; -+ -+ pr_info("%s\n", __func__); -+ -+ for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--) -+ pfe_eth_exit_one(pfe->eth.eth_priv[ii]); -+ -+ for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--) -+ pfe_eth_mdio_exit(pfe, ii); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_eth.h -@@ -0,0 +1,175 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_ETH_H_ -+#define _PFE_ETH_H_ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define PFE_ETH_NAPI_STATS -+#define PFE_ETH_TX_STATS -+ -+#define PFE_ETH_FRAGS_MAX (65536 / HIF_RX_PKT_MIN_SIZE) -+#define LRO_LEN_COUNT_MAX 32 -+#define LRO_NB_COUNT_MAX 32 -+ -+#define PFE_PAUSE_FLAG_ENABLE 1 -+#define PFE_PAUSE_FLAG_AUTONEG 2 -+ -+/* GEMAC configured by SW */ -+/* GEMAC configured by phy lines (not for MII/GMII) */ -+ -+#define GEMAC_SW_FULL_DUPLEX BIT(9) -+#define GEMAC_SW_SPEED_10M (0 << 12) -+#define GEMAC_SW_SPEED_100M BIT(12) -+#define GEMAC_SW_SPEED_1G (2 << 12) -+ -+#define GEMAC_NO_PHY BIT(0) -+ -+struct ls1012a_eth_platform_data { -+ /* board specific information */ -+ phy_interface_t mii_config; -+ u32 phy_flags; -+ u32 gem_id; -+ u32 phy_id; -+ u32 mdio_muxval; -+ u8 mac_addr[ETH_ALEN]; -+ struct device_node *phy_node; -+}; -+ -+struct ls1012a_mdio_platform_data { -+ int id; -+ int irq[32]; -+ u32 phy_mask; -+ int mdc_div; -+}; -+ -+struct ls1012a_pfe_platform_data { -+ struct ls1012a_eth_platform_data ls1012a_eth_pdata[3]; -+ struct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3]; -+}; -+ -+#define NUM_GEMAC_SUPPORT 2 -+#define DRV_NAME "pfe-eth" -+#define DRV_VERSION "1.0" -+ -+#define LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS 3 -+#define TX_POLL_TIMEOUT_MS 1000 -+ -+#define EMAC_TXQ_CNT 16 -+#define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT) -+ -+#define JUMBO_FRAME_SIZE_V1 1900 -+#define JUMBO_FRAME_SIZE_V2 10258 -+/* -+ * Client Tx queue threshold, for txQ flush condition. -+ * It must be smaller than the queue size (in case we ever change it in the -+ * future). -+ */ -+#define HIF_CL_TX_FLUSH_MARK 32 -+ -+/* -+ * Max number of TX resources (HIF descriptors or skbs) that will be released -+ * in a single go during batch recycling. -+ * Should be lower than the flush mark so the SW can provide the HW with a -+ * continuous stream of packets instead of bursts. -+ */ -+#define TX_FREE_MAX_COUNT 16 -+#define EMAC_RXQ_CNT 3 -+#define EMAC_RXQ_DEPTH HIF_RX_DESC_NT -+/* make sure clients can receive a full burst of packets */ -+#define EMAC_RMON_TXBYTES_POS 0x00 -+#define EMAC_RMON_RXBYTES_POS 0x14 -+ -+#define EMAC_QUEUENUM_MASK (emac_txq_cnt - 1) -+#define EMAC_MDIO_TIMEOUT 1000 -+#define MAX_UC_SPEC_ADDR_REG 31 -+ -+struct pfe_eth_fast_timer { -+ int queuenum; -+ struct hrtimer timer; -+ void *base; -+}; -+ -+struct pfe_eth_priv_s { -+ struct pfe *pfe; -+ struct hif_client_s client; -+ struct napi_struct lro_napi; -+ struct napi_struct low_napi; -+ struct napi_struct high_napi; -+ int low_tmu_q; -+ int high_tmu_q; -+ struct net_device_stats stats; -+ struct net_device *ndev; -+ int id; -+ int promisc; -+ unsigned int msg_enable; -+ unsigned int usr_features; -+ -+ spinlock_t lock; /* protect member variables */ -+ unsigned int event_status; -+ int irq; -+ void *EMAC_baseaddr; -+ void *GPI_baseaddr; -+ /* PHY stuff */ -+ struct phy_device *phydev; -+ int oldspeed; -+ int oldduplex; -+ int oldlink; -+ struct device_node *phy_node; -+ struct clk *gemtx_clk; -+ int wol; -+ int pause_flag; -+ -+ int default_priority; -+ struct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT]; -+ -+ struct ls1012a_eth_platform_data *einfo; -+ struct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6]; -+ -+#ifdef PFE_ETH_TX_STATS -+ unsigned int stop_queue_total[EMAC_TXQ_CNT]; -+ unsigned int stop_queue_hif[EMAC_TXQ_CNT]; -+ unsigned int stop_queue_hif_client[EMAC_TXQ_CNT]; -+ unsigned int stop_queue_credit[EMAC_TXQ_CNT]; -+ unsigned int clean_fail[EMAC_TXQ_CNT]; -+ unsigned int was_stopped[EMAC_TXQ_CNT]; -+#endif -+ -+#ifdef PFE_ETH_NAPI_STATS -+ unsigned int napi_counters[NAPI_MAX_COUNT]; -+#endif -+ unsigned int frags_inflight[EMAC_RXQ_CNT + 6]; -+}; -+ -+struct pfe_eth { -+ struct pfe_eth_priv_s *eth_priv[3]; -+}; -+ -+struct pfe_mdio_priv_s { -+ void __iomem *mdio_base; -+ int mdc_div; -+ struct mii_bus *mii_bus; -+}; -+ -+struct pfe_mdio { -+ struct pfe_mdio_priv_s *mdio_priv[3]; -+}; -+ -+int pfe_eth_init(struct pfe *pfe); -+void pfe_eth_exit(struct pfe *pfe); -+int pfe_eth_suspend(struct net_device *dev); -+int pfe_eth_resume(struct net_device *dev); -+int pfe_eth_mdio_reset(struct mii_bus *bus); -+ -+#endif /* _PFE_ETH_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_firmware.c -@@ -0,0 +1,398 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+/* -+ * @file -+ * Contains all the functions to handle parsing and loading of PE firmware -+ * files. -+ */ -+#include -+ -+#include "pfe_mod.h" -+#include "pfe_firmware.h" -+#include "pfe/pfe.h" -+#include -+#include -+ -+static struct elf32_shdr *get_elf_section_header(const u8 *fw, -+ const char *section) -+{ -+ struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw; -+ struct elf32_shdr *shdr; -+ struct elf32_shdr *shdr_shstr; -+ Elf32_Off e_shoff = be32_to_cpu(elf_hdr->e_shoff); -+ Elf32_Half e_shentsize = be16_to_cpu(elf_hdr->e_shentsize); -+ Elf32_Half e_shnum = be16_to_cpu(elf_hdr->e_shnum); -+ Elf32_Half e_shstrndx = be16_to_cpu(elf_hdr->e_shstrndx); -+ Elf32_Off shstr_offset; -+ Elf32_Word sh_name; -+ const char *name; -+ int i; -+ -+ /* Section header strings */ -+ shdr_shstr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff + e_shstrndx -+ * e_shentsize); -+ shstr_offset = be32_to_cpu(shdr_shstr->sh_offset); -+ -+ for (i = 0; i < e_shnum; i++) { -+ shdr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff -+ + i * e_shentsize); -+ -+ sh_name = be32_to_cpu(shdr->sh_name); -+ -+ name = (const char *)((u8 *)elf_hdr + shstr_offset + sh_name); -+ -+ if (!strcmp(name, section)) -+ return shdr; -+ } -+ -+ pr_err("%s: didn't find section %s\n", __func__, section); -+ -+ return NULL; -+} -+ -+#if defined(CFG_DIAGS) -+static int pfe_get_diags_info(const u8 *fw, struct pfe_diags_info -+ *diags_info) -+{ -+ struct elf32_shdr *shdr; -+ unsigned long offset, size; -+ -+ shdr = get_elf_section_header(fw, ".pfe_diags_str"); -+ if (shdr) { -+ offset = be32_to_cpu(shdr->sh_offset); -+ size = be32_to_cpu(shdr->sh_size); -+ diags_info->diags_str_base = be32_to_cpu(shdr->sh_addr); -+ diags_info->diags_str_size = size; -+ diags_info->diags_str_array = kmalloc(size, GFP_KERNEL); -+ memcpy(diags_info->diags_str_array, fw + offset, size); -+ -+ return 0; -+ } else { -+ return -1; -+ } -+} -+#endif -+ -+static void pfe_check_version_info(const u8 *fw) -+{ -+ /*static char *version = NULL;*/ -+ const u8 *elf_data = fw; -+ static char *version; -+ -+ struct elf32_shdr *shdr = get_elf_section_header(fw, ".version"); -+ -+ if (shdr) { -+ if (!version) { -+ /* -+ * this is the first fw we load, use its version -+ * string as reference (whatever it is) -+ */ -+ version = (char *)(elf_data + -+ be32_to_cpu(shdr->sh_offset)); -+ -+ pr_info("PFE binary version: %s\n", version); -+ } else { -+ /* -+ * already have loaded at least one firmware, check -+ * sequence can start now -+ */ -+ if (strcmp(version, (char *)(elf_data + -+ be32_to_cpu(shdr->sh_offset)))) { -+ pr_info( -+ "WARNING: PFE firmware binaries from incompatible version\n"); -+ } -+ } -+ } else { -+ /* -+ * version cannot be verified, a potential issue that should -+ * be reported -+ */ -+ pr_info( -+ "WARNING: PFE firmware binaries from incompatible version\n"); -+ } -+} -+ -+/* PFE elf firmware loader. -+ * Loads an elf firmware image into a list of PE's (specified using a bitmask) -+ * -+ * @param pe_mask Mask of PE id's to load firmware to -+ * @param fw Pointer to the firmware image -+ * -+ * @return 0 on success, a negative value on error -+ * -+ */ -+int pfe_load_elf(int pe_mask, const u8 *fw, struct pfe *pfe) -+{ -+ struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw; -+ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum); -+ struct elf32_shdr *shdr = (struct elf32_shdr *)(fw + -+ be32_to_cpu(elf_hdr->e_shoff)); -+ int id, section; -+ int rc; -+ -+ pr_info("%s\n", __func__); -+ -+ /* Some sanity checks */ -+ if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) { -+ pr_err("%s: incorrect elf magic number\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) { -+ pr_err("%s: incorrect elf class(%x)\n", __func__, -+ elf_hdr->e_ident[EI_CLASS]); -+ return -EINVAL; -+ } -+ -+ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) { -+ pr_err("%s: incorrect elf data(%x)\n", __func__, -+ elf_hdr->e_ident[EI_DATA]); -+ return -EINVAL; -+ } -+ -+ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) { -+ pr_err("%s: incorrect elf file type(%x)\n", __func__, -+ be16_to_cpu(elf_hdr->e_type)); -+ return -EINVAL; -+ } -+ -+ for (section = 0; section < sections; section++, shdr++) { -+ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC | -+ SHF_EXECINSTR))) -+ continue; -+ -+ for (id = 0; id < MAX_PE; id++) -+ if (pe_mask & (1 << id)) { -+ rc = pe_load_elf_section(id, elf_hdr, shdr, -+ pfe->dev); -+ if (rc < 0) -+ goto err; -+ } -+ } -+ -+ pfe_check_version_info(fw); -+ -+ return 0; -+ -+err: -+ return rc; -+} -+ -+int get_firmware_in_fdt(const u8 **pe_fw, const char *name) -+{ -+ struct device_node *np; -+ const unsigned int *len; -+ const void *data; -+ -+ if (!strcmp(name, CLASS_FIRMWARE_FILENAME)) { -+ /* The firmware should be inside the device tree. */ -+ np = of_find_compatible_node(NULL, NULL, -+ "fsl,pfe-class-firmware"); -+ if (!np) { -+ pr_info("Failed to find the node\n"); -+ return -ENOENT; -+ } -+ -+ data = of_get_property(np, "fsl,class-firmware", NULL); -+ if (data) { -+ len = of_get_property(np, "length", NULL); -+ pr_info("CLASS fw of length %d bytes loaded from FDT.\n", -+ be32_to_cpu(*len)); -+ } else { -+ pr_info("fsl,class-firmware not found!!!!\n"); -+ return -ENOENT; -+ } -+ of_node_put(np); -+ *pe_fw = data; -+ } else if (!strcmp(name, TMU_FIRMWARE_FILENAME)) { -+ np = of_find_compatible_node(NULL, NULL, -+ "fsl,pfe-tmu-firmware"); -+ if (!np) { -+ pr_info("Failed to find the node\n"); -+ return -ENOENT; -+ } -+ -+ data = of_get_property(np, "fsl,tmu-firmware", NULL); -+ if (data) { -+ len = of_get_property(np, "length", NULL); -+ pr_info("TMU fw of length %d bytes loaded from FDT.\n", -+ be32_to_cpu(*len)); -+ } else { -+ pr_info("fsl,tmu-firmware not found!!!!\n"); -+ return -ENOENT; -+ } -+ of_node_put(np); -+ *pe_fw = data; -+ } else if (!strcmp(name, UTIL_FIRMWARE_FILENAME)) { -+ np = of_find_compatible_node(NULL, NULL, -+ "fsl,pfe-util-firmware"); -+ if (!np) { -+ pr_info("Failed to find the node\n"); -+ return -ENOENT; -+ } -+ -+ data = of_get_property(np, "fsl,util-firmware", NULL); -+ if (data) { -+ len = of_get_property(np, "length", NULL); -+ pr_info("UTIL fw of length %d bytes loaded from FDT.\n", -+ be32_to_cpu(*len)); -+ } else { -+ pr_info("fsl,util-firmware not found!!!!\n"); -+ return -ENOENT; -+ } -+ of_node_put(np); -+ *pe_fw = data; -+ } else { -+ pr_err("firmware:%s not known\n", name); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/* PFE firmware initialization. -+ * Loads different firmware files from filesystem. -+ * Initializes PE IMEM/DMEM and UTIL-PE DDR -+ * Initializes control path symbol addresses (by looking them up in the elf -+ * firmware files -+ * Takes PE's out of reset -+ * -+ * @return 0 on success, a negative value on error -+ * -+ */ -+int pfe_firmware_init(struct pfe *pfe) -+{ -+ const struct firmware *class_fw, *tmu_fw; -+ const u8 *class_elf_fw, *tmu_elf_fw; -+ int rc = 0, fs_load = 0; -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ const struct firmware *util_fw; -+ const u8 *util_elf_fw; -+ -+#endif -+ -+ pr_info("%s\n", __func__); -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) || -+ get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME) || -+ get_firmware_in_fdt(&util_elf_fw, UTIL_FIRMWARE_FILENAME)) -+#else -+ if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) || -+ get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME)) -+#endif -+ { -+ pr_info("%s:PFE firmware not found in FDT.\n", __func__); -+ pr_info("%s:Trying to load firmware from filesystem...!\n", __func__); -+ -+ /* look for firmware in filesystem...!*/ -+ fs_load = 1; -+ if (request_firmware(&class_fw, CLASS_FIRMWARE_FILENAME, pfe->dev)) { -+ pr_err("%s: request firmware %s failed\n", __func__, -+ CLASS_FIRMWARE_FILENAME); -+ rc = -ETIMEDOUT; -+ goto err0; -+ } -+ class_elf_fw = class_fw->data; -+ -+ if (request_firmware(&tmu_fw, TMU_FIRMWARE_FILENAME, pfe->dev)) { -+ pr_err("%s: request firmware %s failed\n", __func__, -+ TMU_FIRMWARE_FILENAME); -+ rc = -ETIMEDOUT; -+ goto err1; -+ } -+ tmu_elf_fw = tmu_fw->data; -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ if (request_firmware(&util_fw, UTIL_FIRMWARE_FILENAME, pfe->dev)) { -+ pr_err("%s: request firmware %s failed\n", __func__, -+ UTIL_FIRMWARE_FILENAME); -+ rc = -ETIMEDOUT; -+ goto err2; -+ } -+ util_elf_fw = util_fw->data; -+#endif -+ } -+ -+ rc = pfe_load_elf(CLASS_MASK, class_elf_fw, pfe); -+ if (rc < 0) { -+ pr_err("%s: class firmware load failed\n", __func__); -+ goto err3; -+ } -+ -+#if defined(CFG_DIAGS) -+ rc = pfe_get_diags_info(class_elf_fw, &pfe->diags.class_diags_info); -+ if (rc < 0) { -+ pr_warn( -+ "PFE diags won't be available for class PEs\n"); -+ rc = 0; -+ } -+#endif -+ -+ rc = pfe_load_elf(TMU_MASK, tmu_elf_fw, pfe); -+ if (rc < 0) { -+ pr_err("%s: tmu firmware load failed\n", __func__); -+ goto err3; -+ } -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ rc = pfe_load_elf(UTIL_MASK, util_elf_fw, pfe); -+ if (rc < 0) { -+ pr_err("%s: util firmware load failed\n", __func__); -+ goto err3; -+ } -+ -+#if defined(CFG_DIAGS) -+ rc = pfe_get_diags_info(util_elf_fw, &pfe->diags.util_diags_info); -+ if (rc < 0) { -+ pr_warn( -+ "PFE diags won't be available for util PE\n"); -+ rc = 0; -+ } -+#endif -+ -+ util_enable(); -+#endif -+ -+ tmu_enable(0xf); -+ class_enable(); -+ -+err3: -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ if (fs_load) -+ release_firmware(util_fw); -+err2: -+#endif -+ if (fs_load) -+ release_firmware(tmu_fw); -+ -+err1: -+ if (fs_load) -+ release_firmware(class_fw); -+ -+err0: -+ return rc; -+} -+ -+/* PFE firmware cleanup -+ * Puts PE's in reset -+ * -+ * -+ */ -+void pfe_firmware_exit(struct pfe *pfe) -+{ -+ pr_info("%s\n", __func__); -+ -+ if (pe_reset_all(&pfe->ctrl) != 0) -+ pr_err("Error: Failed to stop PEs, PFE reload may not work correctly\n"); -+ -+ class_disable(); -+ tmu_disable(0xf); -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ util_disable(); -+#endif -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_firmware.h -@@ -0,0 +1,21 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_FIRMWARE_H_ -+#define _PFE_FIRMWARE_H_ -+ -+#define CLASS_FIRMWARE_FILENAME "ppfe_class_ls1012a.elf" -+#define TMU_FIRMWARE_FILENAME "ppfe_tmu_ls1012a.elf" -+#define UTIL_FIRMWARE_FILENAME "ppfe_util_ls1012a.elf" -+ -+#define PFE_FW_CHECK_PASS 0 -+#define PFE_FW_CHECK_FAIL 1 -+#define NUM_PFE_FW 3 -+ -+int pfe_firmware_init(struct pfe *pfe); -+void pfe_firmware_exit(struct pfe *pfe); -+ -+#endif /* _PFE_FIRMWARE_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hal.c -@@ -0,0 +1,1517 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include "pfe_mod.h" -+#include "pfe/pfe.h" -+ -+/* A-010897: Jumbo frame is not supported */ -+extern bool pfe_errata_a010897; -+ -+#define PFE_RCR_MAX_FL_MASK 0xC000FFFF -+ -+void *cbus_base_addr; -+void *ddr_base_addr; -+unsigned long ddr_phys_base_addr; -+unsigned int ddr_size; -+ -+static struct pe_info pe[MAX_PE]; -+ -+/* Initializes the PFE library. -+ * Must be called before using any of the library functions. -+ * -+ * @param[in] cbus_base CBUS virtual base address (as mapped in -+ * the host CPU address space) -+ * @param[in] ddr_base PFE DDR range virtual base address (as -+ * mapped in the host CPU address space) -+ * @param[in] ddr_phys_base PFE DDR range physical base address (as -+ * mapped in platform) -+ * @param[in] size PFE DDR range size (as defined by the host -+ * software) -+ */ -+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base, -+ unsigned int size) -+{ -+ cbus_base_addr = cbus_base; -+ ddr_base_addr = ddr_base; -+ ddr_phys_base_addr = ddr_phys_base; -+ ddr_size = size; -+ -+ pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0); -+ pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0); -+ pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1); -+ pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1); -+ pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2); -+ pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2); -+ pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3); -+ pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3); -+ pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4); -+ pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4); -+ pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5); -+ pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5); -+ pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE; -+ pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA; -+ pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR; -+ pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA; -+ -+ pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0); -+ pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0); -+ pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE; -+ pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; -+ pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; -+ pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; -+ -+ pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1); -+ pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1); -+ pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE; -+ pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; -+ pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; -+ pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; -+ -+ pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3); -+ pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3); -+ pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE; -+ pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA; -+ pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR; -+ pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA; -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR; -+ pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA; -+ pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR; -+ pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA; -+#endif -+} -+ -+/* Writes a buffer to PE internal memory from the host -+ * through indirect access registers. -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, -+ * ..., UTIL_ID) -+ * @param[in] src Buffer source address -+ * @param[in] mem_access_addr DMEM destination address (must be 32bit -+ * aligned) -+ * @param[in] len Number of bytes to copy -+ */ -+void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned -+int len) -+{ -+ u32 offset = 0, val, addr; -+ unsigned int len32 = len >> 2; -+ int i; -+ -+ addr = mem_access_addr | PE_MEM_ACCESS_WRITE | -+ PE_MEM_ACCESS_BYTE_ENABLE(0, 4); -+ -+ for (i = 0; i < len32; i++, offset += 4, src += 4) { -+ val = *(u32 *)src; -+ writel(cpu_to_be32(val), pe[id].mem_access_wdata); -+ writel(addr + offset, pe[id].mem_access_addr); -+ } -+ -+ len = (len & 0x3); -+ if (len) { -+ val = 0; -+ -+ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | -+ PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset; -+ -+ for (i = 0; i < len; i++, src++) -+ val |= (*(u8 *)src) << (8 * i); -+ -+ writel(cpu_to_be32(val), pe[id].mem_access_wdata); -+ writel(addr, pe[id].mem_access_addr); -+ } -+} -+ -+/* Writes a buffer to PE internal data memory (DMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, -+ * ..., UTIL_ID) -+ * @param[in] src Buffer source address -+ * @param[in] dst DMEM destination address (must be 32bit -+ * aligned) -+ * @param[in] len Number of bytes to copy -+ */ -+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len) -+{ -+ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | -+ PE_MEM_ACCESS_DMEM, src, len); -+} -+ -+/* Writes a buffer to PE internal program memory (PMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, -+ * ..., TMU3_ID) -+ * @param[in] src Buffer source address -+ * @param[in] dst PMEM destination address (must be 32bit -+ * aligned) -+ * @param[in] len Number of bytes to copy -+ */ -+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len) -+{ -+ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size -+ - 1)) | PE_MEM_ACCESS_IMEM, src, len); -+} -+ -+/* Reads PE internal program memory (IMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, -+ * ..., TMU3_ID) -+ * @param[in] addr PMEM read address (must be aligned on size) -+ * @param[in] size Number of bytes to read (maximum 4, must not -+ * cross 32bit boundaries) -+ * @return the data read (in PE endianness, i.e BE). -+ */ -+u32 pe_pmem_read(int id, u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ u32 mask = 0xffffffff >> ((4 - size) << 3); -+ u32 val; -+ -+ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) -+ | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size); -+ -+ writel(addr, pe[id].mem_access_addr); -+ val = be32_to_cpu(readl(pe[id].mem_access_rdata)); -+ -+ return (val >> (offset << 3)) & mask; -+} -+ -+/* Writes PE internal data memory (DMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, -+ * ..., UTIL_ID) -+ * @param[in] addr DMEM write address (must be aligned on size) -+ * @param[in] val Value to write (in PE endianness, i.e BE) -+ * @param[in] size Number of bytes to write (maximum 4, must not -+ * cross 32bit boundaries) -+ */ -+void pe_dmem_write(int id, u32 val, u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ -+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | -+ PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size); -+ -+ /* Indirect access interface is byte swapping data being written */ -+ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata); -+ writel(addr, pe[id].mem_access_addr); -+} -+ -+/* Reads PE internal data memory (DMEM) from the host -+ * through indirect access registers. -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, -+ * ..., UTIL_ID) -+ * @param[in] addr DMEM read address (must be aligned on size) -+ * @param[in] size Number of bytes to read (maximum 4, must not -+ * cross 32bit boundaries) -+ * @return the data read (in PE endianness, i.e BE). -+ */ -+u32 pe_dmem_read(int id, u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ u32 mask = 0xffffffff >> ((4 - size) << 3); -+ u32 val; -+ -+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_DMEM | -+ PE_MEM_ACCESS_BYTE_ENABLE(offset, size); -+ -+ writel(addr, pe[id].mem_access_addr); -+ -+ /* Indirect access interface is byte swapping data being read */ -+ val = be32_to_cpu(readl(pe[id].mem_access_rdata)); -+ -+ return (val >> (offset << 3)) & mask; -+} -+ -+/* This function is used to write to CLASS internal bus peripherals (ccu, -+ * pe-lem) from the host -+ * through indirect access registers. -+ * @param[in] val value to write -+ * @param[in] addr Address to write to (must be aligned on size) -+ * @param[in] size Number of bytes to write (1, 2 or 4) -+ * -+ */ -+void class_bus_write(u32 val, u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ -+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE); -+ -+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE | -+ (size << 24); -+ -+ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA); -+ writel(addr, CLASS_BUS_ACCESS_ADDR); -+} -+ -+/* Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host -+ * through indirect access registers. -+ * @param[in] addr Address to read from (must be aligned on size) -+ * @param[in] size Number of bytes to read (1, 2 or 4) -+ * @return the read data -+ * -+ */ -+u32 class_bus_read(u32 addr, u8 size) -+{ -+ u32 offset = addr & 0x3; -+ u32 mask = 0xffffffff >> ((4 - size) << 3); -+ u32 val; -+ -+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE); -+ -+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24); -+ -+ writel(addr, CLASS_BUS_ACCESS_ADDR); -+ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA)); -+ -+ return (val >> (offset << 3)) & mask; -+} -+ -+/* Writes data to the cluster memory (PE_LMEM) -+ * @param[in] dst PE LMEM destination address (must be 32bit aligned) -+ * @param[in] src Buffer source address -+ * @param[in] len Number of bytes to copy -+ */ -+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len) -+{ -+ u32 len32 = len >> 2; -+ int i; -+ -+ for (i = 0; i < len32; i++, src += 4, dst += 4) -+ class_bus_write(*(u32 *)src, dst, 4); -+ -+ if (len & 0x2) { -+ class_bus_write(*(u16 *)src, dst, 2); -+ src += 2; -+ dst += 2; -+ } -+ -+ if (len & 0x1) { -+ class_bus_write(*(u8 *)src, dst, 1); -+ src++; -+ dst++; -+ } -+} -+ -+/* Writes value to the cluster memory (PE_LMEM) -+ * @param[in] dst PE LMEM destination address (must be 32bit aligned) -+ * @param[in] val Value to write -+ * @param[in] len Number of bytes to write -+ */ -+void class_pe_lmem_memset(u32 dst, int val, unsigned int len) -+{ -+ u32 len32 = len >> 2; -+ int i; -+ -+ val = val | (val << 8) | (val << 16) | (val << 24); -+ -+ for (i = 0; i < len32; i++, dst += 4) -+ class_bus_write(val, dst, 4); -+ -+ if (len & 0x2) { -+ class_bus_write(val, dst, 2); -+ dst += 2; -+ } -+ -+ if (len & 0x1) { -+ class_bus_write(val, dst, 1); -+ dst++; -+ } -+} -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ -+/* Writes UTIL program memory (DDR) from the host. -+ * -+ * @param[in] addr Address to write (virtual, must be aligned on size) -+ * @param[in] val Value to write (in PE endianness, i.e BE) -+ * @param[in] size Number of bytes to write (2 or 4) -+ */ -+static void util_pmem_write(u32 val, void *addr, u8 size) -+{ -+ void *addr64 = (void *)((unsigned long)addr & ~0x7); -+ unsigned long off = 8 - ((unsigned long)addr & 0x7) - size; -+ -+ /* -+ * IMEM should be loaded as a 64bit swapped value in a 64bit aligned -+ * location -+ */ -+ if (size == 4) -+ writel(be32_to_cpu(val), addr64 + off); -+ else -+ writew(be16_to_cpu((u16)val), addr64 + off); -+} -+ -+/* Writes a buffer to UTIL program memory (DDR) from the host. -+ * -+ * @param[in] dst Address to write (virtual, must be at least 16bit -+ * aligned) -+ * @param[in] src Buffer to write (in PE endianness, i.e BE, must have -+ * same alignment as dst) -+ * @param[in] len Number of bytes to write (must be at least 16bit -+ * aligned) -+ */ -+static void util_pmem_memcpy(void *dst, const void *src, unsigned int len) -+{ -+ unsigned int len32; -+ int i; -+ -+ if ((unsigned long)src & 0x2) { -+ util_pmem_write(*(u16 *)src, dst, 2); -+ src += 2; -+ dst += 2; -+ len -= 2; -+ } -+ -+ len32 = len >> 2; -+ -+ for (i = 0; i < len32; i++, dst += 4, src += 4) -+ util_pmem_write(*(u32 *)src, dst, 4); -+ -+ if (len & 0x2) -+ util_pmem_write(*(u16 *)src, dst, len & 0x2); -+} -+#endif -+ -+/* Loads an elf section into pmem -+ * Code needs to be at least 16bit aligned and only PROGBITS sections are -+ * supported -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ..., -+ * TMU3_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+static int pe_load_pmem_section(int id, const void *data, -+ struct elf32_shdr *shdr) -+{ -+ u32 offset = be32_to_cpu(shdr->sh_offset); -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ u32 type = be32_to_cpu(shdr->sh_type); -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ if (id == UTIL_ID) { -+ pr_err("%s: unsupported pmem section for UTIL\n", -+ __func__); -+ return -EINVAL; -+ } -+#endif -+ -+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) { -+ pr_err( -+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n" -+ , __func__, addr, (unsigned long)data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x1) { -+ pr_err("%s: load address(%x) is not 16bit aligned\n", -+ __func__, addr); -+ return -EINVAL; -+ } -+ -+ if (size & 0x1) { -+ pr_err("%s: load size(%x) is not 16bit aligned\n", -+ __func__, size); -+ return -EINVAL; -+ } -+ -+ switch (type) { -+ case SHT_PROGBITS: -+ pe_pmem_memcpy_to32(id, addr, data + offset, size); -+ -+ break; -+ -+ default: -+ pr_err("%s: unsupported section type(%x)\n", __func__, -+ type); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/* Loads an elf section into dmem -+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly -+ * initialized to 0 -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, -+ * ..., UTIL_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+static int pe_load_dmem_section(int id, const void *data, -+ struct elf32_shdr *shdr) -+{ -+ u32 offset = be32_to_cpu(shdr->sh_offset); -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ u32 type = be32_to_cpu(shdr->sh_type); -+ u32 size32 = size >> 2; -+ int i; -+ -+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) { -+ pr_err( -+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", -+ __func__, addr, (unsigned long)data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x3) { -+ pr_err("%s: load address(%x) is not 32bit aligned\n", -+ __func__, addr); -+ return -EINVAL; -+ } -+ -+ switch (type) { -+ case SHT_PROGBITS: -+ pe_dmem_memcpy_to32(id, addr, data + offset, size); -+ break; -+ -+ case SHT_NOBITS: -+ for (i = 0; i < size32; i++, addr += 4) -+ pe_dmem_write(id, 0, addr, 4); -+ -+ if (size & 0x3) -+ pe_dmem_write(id, 0, addr, size & 0x3); -+ -+ break; -+ -+ default: -+ pr_err("%s: unsupported section type(%x)\n", __func__, -+ type); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/* Loads an elf section into DDR -+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly -+ * initialized to 0 -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, -+ * ..., UTIL_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+static int pe_load_ddr_section(int id, const void *data, -+ struct elf32_shdr *shdr, -+ struct device *dev) { -+ u32 offset = be32_to_cpu(shdr->sh_offset); -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ u32 type = be32_to_cpu(shdr->sh_type); -+ u32 flags = be32_to_cpu(shdr->sh_flags); -+ -+ switch (type) { -+ case SHT_PROGBITS: -+ if (flags & SHF_EXECINSTR) { -+ if (id <= CLASS_MAX_ID) { -+ /* DO the loading only once in DDR */ -+ if (id == CLASS0_ID) { -+ pr_err( -+ "%s: load address(%x) and elf file address(%lx) rcvd\n", -+ __func__, addr, -+ (unsigned long)data + offset); -+ if (((unsigned long)(data + offset) -+ & 0x3) != (addr & 0x3)) { -+ pr_err( -+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n" -+ , __func__, addr, -+ (unsigned long)data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x1) { -+ pr_err( -+ "%s: load address(%x) is not 16bit aligned\n" -+ , __func__, addr); -+ return -EINVAL; -+ } -+ -+ if (size & 0x1) { -+ pr_err( -+ "%s: load length(%x) is not 16bit aligned\n" -+ , __func__, size); -+ return -EINVAL; -+ } -+ memcpy(DDR_PHYS_TO_VIRT( -+ DDR_PFE_TO_PHYS(addr)), -+ data + offset, size); -+ } -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ } else if (id == UTIL_ID) { -+ if (((unsigned long)(data + offset) & 0x3) -+ != (addr & 0x3)) { -+ pr_err( -+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n" -+ , __func__, addr, -+ (unsigned long)data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x1) { -+ pr_err( -+ "%s: load address(%x) is not 16bit aligned\n" -+ , __func__, addr); -+ return -EINVAL; -+ } -+ -+ if (size & 0x1) { -+ pr_err( -+ "%s: load length(%x) is not 16bit aligned\n" -+ , __func__, size); -+ return -EINVAL; -+ } -+ -+ util_pmem_memcpy(DDR_PHYS_TO_VIRT( -+ DDR_PFE_TO_PHYS(addr)), -+ data + offset, size); -+ } -+#endif -+ } else { -+ pr_err( -+ "%s: unsupported ddr section type(%x) for PE(%d)\n" -+ , __func__, type, id); -+ return -EINVAL; -+ } -+ -+ } else { -+ memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data -+ + offset, size); -+ } -+ -+ break; -+ -+ case SHT_NOBITS: -+ memset(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), 0, size); -+ -+ break; -+ -+ default: -+ pr_err("%s: unsupported section type(%x)\n", __func__, -+ type); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/* Loads an elf section into pe lmem -+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly -+ * initialized to 0 -+ * -+ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+static int pe_load_pe_lmem_section(int id, const void *data, -+ struct elf32_shdr *shdr) -+{ -+ u32 offset = be32_to_cpu(shdr->sh_offset); -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ u32 type = be32_to_cpu(shdr->sh_type); -+ -+ if (id > CLASS_MAX_ID) { -+ pr_err( -+ "%s: unsupported pe-lmem section type(%x) for PE(%d)\n", -+ __func__, type, id); -+ return -EINVAL; -+ } -+ -+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) { -+ pr_err( -+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n", -+ __func__, addr, (unsigned long)data + offset); -+ -+ return -EINVAL; -+ } -+ -+ if (addr & 0x3) { -+ pr_err("%s: load address(%x) is not 32bit aligned\n", -+ __func__, addr); -+ return -EINVAL; -+ } -+ -+ switch (type) { -+ case SHT_PROGBITS: -+ class_pe_lmem_memcpy_to32(addr, data + offset, size); -+ break; -+ -+ case SHT_NOBITS: -+ class_pe_lmem_memset(addr, 0, size); -+ break; -+ -+ default: -+ pr_err("%s: unsupported section type(%x)\n", __func__, -+ type); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/* Loads an elf section into a PE -+ * For now only supports loading a section to dmem (all PE's), pmem (class and -+ * tmu PE's), -+ * DDDR (util PE code) -+ * -+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, -+ * ..., UTIL_ID) -+ * @param[in] data pointer to the elf firmware -+ * @param[in] shdr pointer to the elf section header -+ * -+ */ -+int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr, -+ struct device *dev) { -+ u32 addr = be32_to_cpu(shdr->sh_addr); -+ u32 size = be32_to_cpu(shdr->sh_size); -+ -+ if (IS_DMEM(addr, size)) -+ return pe_load_dmem_section(id, data, shdr); -+ else if (IS_PMEM(addr, size)) -+ return pe_load_pmem_section(id, data, shdr); -+ else if (IS_PFE_LMEM(addr, size)) -+ return 0; -+ else if (IS_PHYS_DDR(addr, size)) -+ return pe_load_ddr_section(id, data, shdr, dev); -+ else if (IS_PE_LMEM(addr, size)) -+ return pe_load_pe_lmem_section(id, data, shdr); -+ -+ pr_err("%s: unsupported memory range(%x)\n", __func__, -+ addr); -+ return 0; -+} -+ -+/**************************** BMU ***************************/ -+ -+/* Initializes a BMU block. -+ * @param[in] base BMU block base address -+ * @param[in] cfg BMU configuration -+ */ -+void bmu_init(void *base, struct BMU_CFG *cfg) -+{ -+ bmu_disable(base); -+ -+ bmu_set_config(base, cfg); -+ -+ bmu_reset(base); -+} -+ -+/* Resets a BMU block. -+ * @param[in] base BMU block base address -+ */ -+void bmu_reset(void *base) -+{ -+ writel(CORE_SW_RESET, base + BMU_CTRL); -+ -+ /* Wait for self clear */ -+ while (readl(base + BMU_CTRL) & CORE_SW_RESET) -+ ; -+} -+ -+/* Enabled a BMU block. -+ * @param[in] base BMU block base address -+ */ -+void bmu_enable(void *base) -+{ -+ writel(CORE_ENABLE, base + BMU_CTRL); -+} -+ -+/* Disables a BMU block. -+ * @param[in] base BMU block base address -+ */ -+void bmu_disable(void *base) -+{ -+ writel(CORE_DISABLE, base + BMU_CTRL); -+} -+ -+/* Sets the configuration of a BMU block. -+ * @param[in] base BMU block base address -+ * @param[in] cfg BMU configuration -+ */ -+void bmu_set_config(void *base, struct BMU_CFG *cfg) -+{ -+ writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR); -+ writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG); -+ writel(cfg->size & 0xffff, base + BMU_BUF_SIZE); -+ -+ /* Interrupts are never used */ -+ writel(cfg->low_watermark, base + BMU_LOW_WATERMARK); -+ writel(cfg->high_watermark, base + BMU_HIGH_WATERMARK); -+ writel(0x0, base + BMU_INT_ENABLE); -+} -+ -+/**************************** MTIP GEMAC ***************************/ -+ -+/* Enable Rx Checksum Engine. With this enabled, Frame with bad IP, -+ * TCP or UDP checksums are discarded -+ * -+ * @param[in] base GEMAC base address. -+ */ -+void gemac_enable_rx_checksum_offload(void *base) -+{ -+ /*Do not find configuration to do this */ -+} -+ -+/* Disable Rx Checksum Engine. -+ * -+ * @param[in] base GEMAC base address. -+ */ -+void gemac_disable_rx_checksum_offload(void *base) -+{ -+ /*Do not find configuration to do this */ -+} -+ -+/* GEMAC set speed. -+ * @param[in] base GEMAC base address -+ * @param[in] speed GEMAC speed (10, 100 or 1000 Mbps) -+ */ -+void gemac_set_speed(void *base, enum mac_speed gem_speed) -+{ -+ u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED; -+ u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T; -+ -+ switch (gem_speed) { -+ case SPEED_10M: -+ rcr |= EMAC_RCNTRL_RMII_10T; -+ break; -+ -+ case SPEED_1000M: -+ ecr |= EMAC_ECNTRL_SPEED; -+ break; -+ -+ case SPEED_100M: -+ default: -+ /*It is in 100M mode */ -+ break; -+ } -+ writel(ecr, (base + EMAC_ECNTRL_REG)); -+ writel(rcr, (base + EMAC_RCNTRL_REG)); -+} -+ -+/* GEMAC set duplex. -+ * @param[in] base GEMAC base address -+ * @param[in] duplex GEMAC duplex mode (Full, Half) -+ */ -+void gemac_set_duplex(void *base, int duplex) -+{ -+ if (duplex == DUPLEX_HALF) { -+ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base -+ + EMAC_TCNTRL_REG); -+ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base -+ + EMAC_RCNTRL_REG)); -+ } else{ -+ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base -+ + EMAC_TCNTRL_REG); -+ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base -+ + EMAC_RCNTRL_REG)); -+ } -+} -+ -+/* GEMAC set mode. -+ * @param[in] base GEMAC base address -+ * @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII) -+ */ -+void gemac_set_mode(void *base, int mode) -+{ -+ u32 val = readl(base + EMAC_RCNTRL_REG); -+ -+ /*Remove loopbank*/ -+ val &= ~EMAC_RCNTRL_LOOP; -+ -+ /* Enable flow control and MII mode.PFE firmware always expects -+ CRC should be forwarded by MAC to validate CRC in software.*/ -+ val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE); -+ -+ writel(val, base + EMAC_RCNTRL_REG); -+} -+ -+/* GEMAC enable function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_enable(void *base) -+{ -+ writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base + -+ EMAC_ECNTRL_REG); -+} -+ -+/* GEMAC disable function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_disable(void *base) -+{ -+ writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base + -+ EMAC_ECNTRL_REG); -+} -+ -+/* GEMAC TX disable function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_tx_disable(void *base) -+{ -+ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base + -+ EMAC_TCNTRL_REG); -+} -+ -+void gemac_tx_enable(void *base) -+{ -+ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base + -+ EMAC_TCNTRL_REG); -+} -+ -+/* Sets the hash register of the MAC. -+ * This register is used for matching unicast and multicast frames. -+ * -+ * @param[in] base GEMAC base address. -+ * @param[in] hash 64-bit hash to be configured. -+ */ -+void gemac_set_hash(void *base, struct pfe_mac_addr *hash) -+{ -+ writel(hash->bottom, base + EMAC_GALR); -+ writel(hash->top, base + EMAC_GAUR); -+} -+ -+void gemac_set_laddrN(void *base, struct pfe_mac_addr *address, -+ unsigned int entry_index) -+{ -+ if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX)) -+ return; -+ -+ entry_index = entry_index - 1; -+ if (entry_index < 1) { -+ writel(htonl(address->bottom), base + EMAC_PHY_ADDR_LOW); -+ writel((htonl(address->top) | 0x8808), base + -+ EMAC_PHY_ADDR_HIGH); -+ } else { -+ writel(htonl(address->bottom), base + ((entry_index - 1) * 8) -+ + EMAC_SMAC_0_0); -+ writel((htonl(address->top) | 0x8808), base + ((entry_index - -+ 1) * 8) + EMAC_SMAC_0_1); -+ } -+} -+ -+void gemac_clear_laddrN(void *base, unsigned int entry_index) -+{ -+ if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX)) -+ return; -+ -+ entry_index = entry_index - 1; -+ if (entry_index < 1) { -+ writel(0, base + EMAC_PHY_ADDR_LOW); -+ writel(0, base + EMAC_PHY_ADDR_HIGH); -+ } else { -+ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0); -+ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1); -+ } -+} -+ -+/* Set the loopback mode of the MAC. This can be either no loopback for -+ * normal operation, local loopback through MAC internal loopback module or PHY -+ * loopback for external loopback through a PHY. This asserts the external -+ * loop pin. -+ * -+ * @param[in] base GEMAC base address. -+ * @param[in] gem_loop Loopback mode to be enabled. LB_LOCAL - MAC -+ * Loopback, -+ * LB_EXT - PHY Loopback. -+ */ -+void gemac_set_loop(void *base, enum mac_loop gem_loop) -+{ -+ pr_info("%s()\n", __func__); -+ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base + -+ EMAC_RCNTRL_REG)); -+} -+ -+/* GEMAC allow frames -+ * @param[in] base GEMAC base address -+ */ -+void gemac_enable_copy_all(void *base) -+{ -+ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base + -+ EMAC_RCNTRL_REG)); -+} -+ -+/* GEMAC do not allow frames -+ * @param[in] base GEMAC base address -+ */ -+void gemac_disable_copy_all(void *base) -+{ -+ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base + -+ EMAC_RCNTRL_REG)); -+} -+ -+/* GEMAC allow broadcast function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_allow_broadcast(void *base) -+{ -+ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base + -+ EMAC_RCNTRL_REG); -+} -+ -+/* GEMAC no broadcast function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_no_broadcast(void *base) -+{ -+ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base + -+ EMAC_RCNTRL_REG); -+} -+ -+/* GEMAC enable 1536 rx function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_enable_1536_rx(void *base) -+{ -+ /* Set 1536 as Maximum frame length */ -+ writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK) -+ | (1536 << 16), base + EMAC_RCNTRL_REG); -+} -+ -+/* GEMAC set rx Max frame length. -+ * @param[in] base GEMAC base address -+ * @param[in] mtu new mtu -+ */ -+void gemac_set_rx_max_fl(void *base, int mtu) -+{ -+ /* Set mtu as Maximum frame length */ -+ writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK) -+ | (mtu << 16), base + EMAC_RCNTRL_REG); -+} -+ -+/* GEMAC enable stacked vlan function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_enable_stacked_vlan(void *base) -+{ -+ /* MTIP doesn't support stacked vlan */ -+} -+ -+/* GEMAC enable pause rx function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_enable_pause_rx(void *base) -+{ -+ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE, -+ base + EMAC_RCNTRL_REG); -+} -+ -+/* GEMAC disable pause rx function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_disable_pause_rx(void *base) -+{ -+ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE, -+ base + EMAC_RCNTRL_REG); -+} -+ -+/* GEMAC enable pause tx function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_enable_pause_tx(void *base) -+{ -+ writel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY); -+} -+ -+/* GEMAC disable pause tx function. -+ * @param[in] base GEMAC base address -+ */ -+void gemac_disable_pause_tx(void *base) -+{ -+ writel(0x0, base + EMAC_RX_SECTION_EMPTY); -+} -+ -+/* GEMAC wol configuration -+ * @param[in] base GEMAC base address -+ * @param[in] wol_conf WoL register configuration -+ */ -+void gemac_set_wol(void *base, u32 wol_conf) -+{ -+ u32 val = readl(base + EMAC_ECNTRL_REG); -+ -+ if (wol_conf) -+ val |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP); -+ else -+ val &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP); -+ writel(val, base + EMAC_ECNTRL_REG); -+} -+ -+/* Sets Gemac bus width to 64bit -+ * @param[in] base GEMAC base address -+ * @param[in] width gemac bus width to be set possible values are 32/64/128 -+ */ -+void gemac_set_bus_width(void *base, int width) -+{ -+} -+ -+/* Sets Gemac configuration. -+ * @param[in] base GEMAC base address -+ * @param[in] cfg GEMAC configuration -+ */ -+void gemac_set_config(void *base, struct gemac_cfg *cfg) -+{ -+ /*GEMAC config taken from VLSI */ -+ writel(0x00000004, base + EMAC_TFWR_STR_FWD); -+ writel(0x00000005, base + EMAC_RX_SECTION_FULL); -+ -+ if (pfe_errata_a010897) -+ writel(0x0000076c, base + EMAC_TRUNC_FL); -+ else -+ writel(0x00003fff, base + EMAC_TRUNC_FL); -+ -+ writel(0x00000030, base + EMAC_TX_SECTION_EMPTY); -+ writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG); -+ -+ gemac_set_mode(base, cfg->mode); -+ -+ gemac_set_speed(base, cfg->speed); -+ -+ gemac_set_duplex(base, cfg->duplex); -+} -+ -+/**************************** GPI ***************************/ -+ -+/* Initializes a GPI block. -+ * @param[in] base GPI base address -+ * @param[in] cfg GPI configuration -+ */ -+void gpi_init(void *base, struct gpi_cfg *cfg) -+{ -+ gpi_reset(base); -+ -+ gpi_disable(base); -+ -+ gpi_set_config(base, cfg); -+} -+ -+/* Resets a GPI block. -+ * @param[in] base GPI base address -+ */ -+void gpi_reset(void *base) -+{ -+ writel(CORE_SW_RESET, base + GPI_CTRL); -+} -+ -+/* Enables a GPI block. -+ * @param[in] base GPI base address -+ */ -+void gpi_enable(void *base) -+{ -+ writel(CORE_ENABLE, base + GPI_CTRL); -+} -+ -+/* Disables a GPI block. -+ * @param[in] base GPI base address -+ */ -+void gpi_disable(void *base) -+{ -+ writel(CORE_DISABLE, base + GPI_CTRL); -+} -+ -+/* Sets the configuration of a GPI block. -+ * @param[in] base GPI base address -+ * @param[in] cfg GPI configuration -+ */ -+void gpi_set_config(void *base, struct gpi_cfg *cfg) -+{ -+ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base -+ + GPI_LMEM_ALLOC_ADDR); -+ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base -+ + GPI_LMEM_FREE_ADDR); -+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base -+ + GPI_DDR_ALLOC_ADDR); -+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base -+ + GPI_DDR_FREE_ADDR); -+ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR); -+ writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET); -+ writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET); -+ writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET); -+ writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET); -+ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE); -+ writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE); -+ -+ writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | -+ GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG); -+ writel(cfg->tmlf_txthres, base + GPI_TMLF_TX); -+ writel(cfg->aseq_len, base + GPI_DTX_ASEQ); -+ writel(1, base + GPI_TOE_CHKSUM_EN); -+ -+ if (cfg->mtip_pause_reg) { -+ writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG); -+ writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME); -+ } -+} -+ -+/**************************** CLASSIFIER ***************************/ -+ -+/* Initializes CLASSIFIER block. -+ * @param[in] cfg CLASSIFIER configuration -+ */ -+void class_init(struct class_cfg *cfg) -+{ -+ class_reset(); -+ -+ class_disable(); -+ -+ class_set_config(cfg); -+} -+ -+/* Resets CLASSIFIER block. -+ * -+ */ -+void class_reset(void) -+{ -+ writel(CORE_SW_RESET, CLASS_TX_CTRL); -+} -+ -+/* Enables all CLASS-PE's cores. -+ * -+ */ -+void class_enable(void) -+{ -+ writel(CORE_ENABLE, CLASS_TX_CTRL); -+} -+ -+/* Disables all CLASS-PE's cores. -+ * -+ */ -+void class_disable(void) -+{ -+ writel(CORE_DISABLE, CLASS_TX_CTRL); -+} -+ -+/* -+ * Sets the configuration of the CLASSIFIER block. -+ * @param[in] cfg CLASSIFIER configuration -+ */ -+void class_set_config(struct class_cfg *cfg) -+{ -+ u32 val; -+ -+ /* Initialize route table */ -+ if (!cfg->resume) -+ memset(DDR_PHYS_TO_VIRT(cfg->route_table_baseaddr), 0, (1 << -+ cfg->route_table_hash_bits) * CLASS_ROUTE_SIZE); -+ -+#if !defined(LS1012A_PFE_RESET_WA) -+ writel(cfg->pe_sys_clk_ratio, CLASS_PE_SYS_CLK_RATIO); -+#endif -+ -+ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE); -+ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE); -+ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) | -+ CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits), -+ CLASS_ROUTE_HASH_ENTRY_SIZE); -+ writel(HIF_PKT_CLASS_EN | HIF_PKT_OFFSET(sizeof(struct hif_hdr)), -+ CLASS_HIF_PARSE); -+ -+ val = HASH_CRC_PORT_IP | QB2BUS_LE; -+ -+#if defined(CONFIG_IP_ALIGNED) -+ val |= IP_ALIGNED; -+#endif -+ -+ /* -+ * Class PE packet steering will only work if TOE mode, bridge fetch or -+ * route fetch are enabled (see class/qb_fet.v). Route fetch would -+ * trigger additional memory copies (likely from DDR because of hash -+ * table size, which cannot be reduced because PE software still -+ * relies on hash value computed in HW), so when not in TOE mode we -+ * simply enable HW bridge fetch even though we don't use it. -+ */ -+ if (cfg->toe_mode) -+ val |= CLASS_TOE; -+ else -+ val |= HW_BRIDGE_FETCH; -+ -+ writel(val, CLASS_ROUTE_MULTI); -+ -+ writel(DDR_PHYS_TO_PFE(cfg->route_table_baseaddr), -+ CLASS_ROUTE_TABLE_BASE); -+ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0); -+ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1); -+ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0); -+ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1); -+ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR); -+ -+ writel(23, CLASS_AFULL_THRES); -+ writel(23, CLASS_TSQ_FIFO_THRES); -+ -+ writel(24, CLASS_MAX_BUF_CNT); -+ writel(24, CLASS_TSQ_MAX_CNT); -+} -+ -+/**************************** TMU ***************************/ -+ -+void tmu_reset(void) -+{ -+ writel(SW_RESET, TMU_CTRL); -+} -+ -+/* Initializes TMU block. -+ * @param[in] cfg TMU configuration -+ */ -+void tmu_init(struct tmu_cfg *cfg) -+{ -+ int q, phyno; -+ -+ tmu_disable(0xF); -+ mdelay(10); -+ -+#if !defined(LS1012A_PFE_RESET_WA) -+ /* keep in soft reset */ -+ writel(SW_RESET, TMU_CTRL); -+#endif -+ writel(0x3, TMU_SYS_GENERIC_CONTROL); -+ writel(750, TMU_INQ_WATERMARK); -+ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + -+ GPI_INQ_PKTPTR), TMU_PHY0_INQ_ADDR); -+ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + -+ GPI_INQ_PKTPTR), TMU_PHY1_INQ_ADDR); -+ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + -+ GPI_INQ_PKTPTR), TMU_PHY3_INQ_ADDR); -+ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR); -+ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR); -+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), -+ TMU_BMU_INQ_ADDR); -+ -+ writel(0x3FF, TMU_TDQ0_SCH_CTRL); /* -+ * enabling all 10 -+ * schedulers [9:0] of each TDQ -+ */ -+ writel(0x3FF, TMU_TDQ1_SCH_CTRL); -+ writel(0x3FF, TMU_TDQ3_SCH_CTRL); -+ -+#if !defined(LS1012A_PFE_RESET_WA) -+ writel(cfg->pe_sys_clk_ratio, TMU_PE_SYS_CLK_RATIO); -+#endif -+ -+#if !defined(LS1012A_PFE_RESET_WA) -+ writel(DDR_PHYS_TO_PFE(cfg->llm_base_addr), TMU_LLM_BASE_ADDR); -+ /* Extra packet pointers will be stored from this address onwards */ -+ -+ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN); -+ writel(5, TMU_TDQ_IIFG_CFG); -+ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE); -+ -+ writel(0x0, TMU_CTRL); -+ -+ /* MEM init */ -+ pr_info("%s: mem init\n", __func__); -+ writel(MEM_INIT, TMU_CTRL); -+ -+ while (!(readl(TMU_CTRL) & MEM_INIT_DONE)) -+ ; -+ -+ /* LLM init */ -+ pr_info("%s: lmem init\n", __func__); -+ writel(LLM_INIT, TMU_CTRL); -+ -+ while (!(readl(TMU_CTRL) & LLM_INIT_DONE)) -+ ; -+#endif -+ /* set up each queue for tail drop */ -+ for (phyno = 0; phyno < 4; phyno++) { -+ if (phyno == 2) -+ continue; -+ for (q = 0; q < 16; q++) { -+ u32 qdepth; -+ -+ writel((phyno << 8) | q, TMU_TEQ_CTRL); -+ writel(1 << 22, TMU_TEQ_QCFG); /*Enable tail drop */ -+ -+ if (phyno == 3) -+ qdepth = DEFAULT_TMU3_QDEPTH; -+ else -+ qdepth = (q == 0) ? DEFAULT_Q0_QDEPTH : -+ DEFAULT_MAX_QDEPTH; -+ -+ /* LOG: 68855 */ -+ /* -+ * The following is a workaround for the reordered -+ * packet and BMU2 buffer leakage issue. -+ */ -+ if (CHIP_REVISION() == 0) -+ qdepth = 31; -+ -+ writel(qdepth << 18, TMU_TEQ_HW_PROB_CFG2); -+ writel(qdepth >> 14, TMU_TEQ_HW_PROB_CFG3); -+ } -+ } -+ -+#ifdef CFG_LRO -+ /* Set TMU-3 queue 5 (LRO) in no-drop mode */ -+ writel((3 << 8) | TMU_QUEUE_LRO, TMU_TEQ_CTRL); -+ writel(0, TMU_TEQ_QCFG); -+#endif -+ -+ writel(0x05, TMU_TEQ_DISABLE_DROPCHK); -+ -+ writel(0x0, TMU_CTRL); -+} -+ -+/* Enables TMU-PE cores. -+ * @param[in] pe_mask TMU PE mask -+ */ -+void tmu_enable(u32 pe_mask) -+{ -+ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL); -+} -+ -+/* Disables TMU cores. -+ * @param[in] pe_mask TMU PE mask -+ */ -+void tmu_disable(u32 pe_mask) -+{ -+ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL); -+} -+ -+/* This will return the tmu queue status -+ * @param[in] if_id gem interface id or TMU index -+ * @return returns the bit mask of busy queues, zero means all -+ * queues are empty -+ */ -+u32 tmu_qstatus(u32 if_id) -+{ -+ return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS + -+ offsetof(struct pe_status, tmu_qstatus), 4)); -+} -+ -+u32 tmu_pkts_processed(u32 if_id) -+{ -+ return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS + -+ offsetof(struct pe_status, rx), 4)); -+} -+ -+/**************************** UTIL ***************************/ -+ -+/* Resets UTIL block. -+ */ -+void util_reset(void) -+{ -+ writel(CORE_SW_RESET, UTIL_TX_CTRL); -+} -+ -+/* Initializes UTIL block. -+ * @param[in] cfg UTIL configuration -+ */ -+void util_init(struct util_cfg *cfg) -+{ -+ writel(cfg->pe_sys_clk_ratio, UTIL_PE_SYS_CLK_RATIO); -+} -+ -+/* Enables UTIL-PE core. -+ * -+ */ -+void util_enable(void) -+{ -+ writel(CORE_ENABLE, UTIL_TX_CTRL); -+} -+ -+/* Disables UTIL-PE core. -+ * -+ */ -+void util_disable(void) -+{ -+ writel(CORE_DISABLE, UTIL_TX_CTRL); -+} -+ -+/**************************** HIF ***************************/ -+/* Initializes HIF copy block. -+ * -+ */ -+void hif_init(void) -+{ -+ /*Initialize HIF registers*/ -+ writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE, -+ HIF_POLL_CTRL); -+} -+ -+/* Enable hif tx DMA and interrupt -+ * -+ */ -+void hif_tx_enable(void) -+{ -+ writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL); -+ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), -+ HIF_INT_ENABLE); -+} -+ -+/* Disable hif tx DMA and interrupt -+ * -+ */ -+void hif_tx_disable(void) -+{ -+ u32 hif_int; -+ -+ writel(0, HIF_TX_CTRL); -+ -+ hif_int = readl(HIF_INT_ENABLE); -+ hif_int &= HIF_TXPKT_INT_EN; -+ writel(hif_int, HIF_INT_ENABLE); -+} -+ -+/* Enable hif rx DMA and interrupt -+ * -+ */ -+void hif_rx_enable(void) -+{ -+ hif_rx_dma_start(); -+ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), -+ HIF_INT_ENABLE); -+} -+ -+/* Disable hif rx DMA and interrupt -+ * -+ */ -+void hif_rx_disable(void) -+{ -+ u32 hif_int; -+ -+ writel(0, HIF_RX_CTRL); -+ -+ hif_int = readl(HIF_INT_ENABLE); -+ hif_int &= HIF_RXPKT_INT_EN; -+ writel(hif_int, HIF_INT_ENABLE); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hif.c -@@ -0,0 +1,1064 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "pfe_mod.h" -+ -+#define HIF_INT_MASK (HIF_INT | HIF_RXPKT_INT | HIF_TXPKT_INT) -+ -+unsigned char napi_first_batch; -+ -+static void pfe_tx_do_cleanup(unsigned long data); -+ -+static int pfe_hif_alloc_descr(struct pfe_hif *hif) -+{ -+ void *addr; -+ dma_addr_t dma_addr; -+ int err = 0; -+ -+ pr_info("%s\n", __func__); -+ addr = dma_alloc_coherent(pfe->dev, -+ HIF_RX_DESC_NT * sizeof(struct hif_desc) + -+ HIF_TX_DESC_NT * sizeof(struct hif_desc), -+ &dma_addr, GFP_KERNEL); -+ -+ if (!addr) { -+ pr_err("%s: Could not allocate buffer descriptors!\n" -+ , __func__); -+ err = -ENOMEM; -+ goto err0; -+ } -+ -+ hif->descr_baseaddr_p = dma_addr; -+ hif->descr_baseaddr_v = addr; -+ hif->rx_ring_size = HIF_RX_DESC_NT; -+ hif->tx_ring_size = HIF_TX_DESC_NT; -+ -+ return 0; -+ -+err0: -+ return err; -+} -+ -+#if defined(LS1012A_PFE_RESET_WA) -+static void pfe_hif_disable_rx_desc(struct pfe_hif *hif) -+{ -+ int ii; -+ struct hif_desc *desc = hif->rx_base; -+ -+ /*Mark all descriptors as LAST_BD */ -+ for (ii = 0; ii < hif->rx_ring_size; ii++) { -+ desc->ctrl |= BD_CTRL_LAST_BD; -+ desc++; -+ } -+} -+ -+struct class_rx_hdr_t { -+ u32 next_ptr; /* ptr to the start of the first DDR buffer */ -+ u16 length; /* total packet length */ -+ u16 phyno; /* input physical port number */ -+ u32 status; /* gemac status bits */ -+ u32 status2; /* reserved for software usage */ -+}; -+ -+/* STATUS_BAD_FRAME_ERR is set for all errors (including checksums if enabled) -+ * except overflow -+ */ -+#define STATUS_BAD_FRAME_ERR BIT(16) -+#define STATUS_LENGTH_ERR BIT(17) -+#define STATUS_CRC_ERR BIT(18) -+#define STATUS_TOO_SHORT_ERR BIT(19) -+#define STATUS_TOO_LONG_ERR BIT(20) -+#define STATUS_CODE_ERR BIT(21) -+#define STATUS_MC_HASH_MATCH BIT(22) -+#define STATUS_CUMULATIVE_ARC_HIT BIT(23) -+#define STATUS_UNICAST_HASH_MATCH BIT(24) -+#define STATUS_IP_CHECKSUM_CORRECT BIT(25) -+#define STATUS_TCP_CHECKSUM_CORRECT BIT(26) -+#define STATUS_UDP_CHECKSUM_CORRECT BIT(27) -+#define STATUS_OVERFLOW_ERR BIT(28) /* GPI error */ -+#define MIN_PKT_SIZE 64 -+ -+static inline void copy_to_lmem(u32 *dst, u32 *src, int len) -+{ -+ int i; -+ -+ for (i = 0; i < len; i += sizeof(u32)) { -+ *dst = htonl(*src); -+ dst++; src++; -+ } -+} -+ -+static void send_dummy_pkt_to_hif(void) -+{ -+ void *lmem_ptr, *ddr_ptr, *lmem_virt_addr; -+ u32 physaddr; -+ struct class_rx_hdr_t local_hdr; -+ static u32 dummy_pkt[] = { -+ 0x33221100, 0x2b785544, 0xd73093cb, 0x01000608, -+ 0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0, -+ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000, -+ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f }; -+ -+ ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL)); -+ if (!ddr_ptr) -+ return; -+ -+ lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL)); -+ if (!lmem_ptr) -+ return; -+ -+ pr_info("Sending a dummy pkt to HIF %p %p\n", ddr_ptr, lmem_ptr); -+ physaddr = (u32)DDR_VIRT_TO_PFE(ddr_ptr); -+ -+ lmem_virt_addr = (void *)CBUS_PFE_TO_VIRT((unsigned long int)lmem_ptr); -+ -+ local_hdr.phyno = htons(0); /* RX_PHY_0 */ -+ local_hdr.length = htons(MIN_PKT_SIZE); -+ -+ local_hdr.next_ptr = htonl((u32)physaddr); -+ /*Mark checksum is correct */ -+ local_hdr.status = htonl((STATUS_IP_CHECKSUM_CORRECT | -+ STATUS_UDP_CHECKSUM_CORRECT | -+ STATUS_TCP_CHECKSUM_CORRECT | -+ STATUS_UNICAST_HASH_MATCH | -+ STATUS_CUMULATIVE_ARC_HIT)); -+ local_hdr.status2 = 0; -+ -+ copy_to_lmem((u32 *)lmem_virt_addr, (u32 *)&local_hdr, -+ sizeof(local_hdr)); -+ -+ copy_to_lmem((u32 *)(lmem_virt_addr + LMEM_HDR_SIZE), (u32 *)dummy_pkt, -+ 0x40); -+ -+ writel((unsigned long int)lmem_ptr, CLASS_INQ_PKTPTR); -+} -+ -+void pfe_hif_rx_idle(struct pfe_hif *hif) -+{ -+ int hif_stop_loop = 10; -+ u32 rx_status; -+ -+ pfe_hif_disable_rx_desc(hif); -+ pr_info("Bringing hif to idle state..."); -+ writel(0, HIF_INT_ENABLE); -+ /*If HIF Rx BDP is busy send a dummy packet */ -+ do { -+ rx_status = readl(HIF_RX_STATUS); -+ if (rx_status & BDP_CSR_RX_DMA_ACTV) -+ send_dummy_pkt_to_hif(); -+ -+ usleep_range(100, 150); -+ } while (--hif_stop_loop); -+ -+ if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV) -+ pr_info("Failed\n"); -+ else -+ pr_info("Done\n"); -+} -+#endif -+ -+static void pfe_hif_free_descr(struct pfe_hif *hif) -+{ -+ pr_info("%s\n", __func__); -+ -+ dma_free_coherent(pfe->dev, -+ hif->rx_ring_size * sizeof(struct hif_desc) + -+ hif->tx_ring_size * sizeof(struct hif_desc), -+ hif->descr_baseaddr_v, hif->descr_baseaddr_p); -+} -+ -+void pfe_hif_desc_dump(struct pfe_hif *hif) -+{ -+ struct hif_desc *desc; -+ unsigned long desc_p; -+ int ii = 0; -+ -+ pr_info("%s\n", __func__); -+ -+ desc = hif->rx_base; -+ desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v + -+ hif->descr_baseaddr_p); -+ -+ pr_info("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p); -+ for (ii = 0; ii < hif->rx_ring_size; ii++) { -+ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n", -+ readl(&desc->status), readl(&desc->ctrl), -+ readl(&desc->data), readl(&desc->next)); -+ desc++; -+ } -+ -+ desc = hif->tx_base; -+ desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v + -+ hif->descr_baseaddr_p); -+ -+ pr_info("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p); -+ for (ii = 0; ii < hif->tx_ring_size; ii++) { -+ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n", -+ readl(&desc->status), readl(&desc->ctrl), -+ readl(&desc->data), readl(&desc->next)); -+ desc++; -+ } -+} -+ -+/* pfe_hif_release_buffers */ -+static void pfe_hif_release_buffers(struct pfe_hif *hif) -+{ -+ struct hif_desc *desc; -+ int i = 0; -+ -+ hif->rx_base = hif->descr_baseaddr_v; -+ -+ pr_info("%s\n", __func__); -+ -+ /*Free Rx buffers */ -+ desc = hif->rx_base; -+ for (i = 0; i < hif->rx_ring_size; i++) { -+ if (readl(&desc->data)) { -+ if ((i < hif->shm->rx_buf_pool_cnt) && -+ (!hif->shm->rx_buf_pool[i])) { -+ /* -+ * dma_unmap_single(hif->dev, desc->data, -+ * hif->rx_buf_len[i], DMA_FROM_DEVICE); -+ */ -+ dma_unmap_single(hif->dev, -+ DDR_PFE_TO_PHYS( -+ readl(&desc->data)), -+ hif->rx_buf_len[i], -+ DMA_FROM_DEVICE); -+ hif->shm->rx_buf_pool[i] = hif->rx_buf_addr[i]; -+ } else { -+ pr_err("%s: buffer pool already full\n" -+ , __func__); -+ } -+ } -+ -+ writel(0, &desc->data); -+ writel(0, &desc->status); -+ writel(0, &desc->ctrl); -+ desc++; -+ } -+} -+ -+/* -+ * pfe_hif_init_buffers -+ * This function initializes the HIF Rx/Tx ring descriptors and -+ * initialize Rx queue with buffers. -+ */ -+static int pfe_hif_init_buffers(struct pfe_hif *hif) -+{ -+ struct hif_desc *desc, *first_desc_p; -+ u32 data; -+ int i = 0; -+ -+ pr_info("%s\n", __func__); -+ -+ /* Check enough Rx buffers available in the shared memory */ -+ if (hif->shm->rx_buf_pool_cnt < hif->rx_ring_size) -+ return -ENOMEM; -+ -+ hif->rx_base = hif->descr_baseaddr_v; -+ memset(hif->rx_base, 0, hif->rx_ring_size * sizeof(struct hif_desc)); -+ -+ /*Initialize Rx descriptors */ -+ desc = hif->rx_base; -+ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p; -+ -+ for (i = 0; i < hif->rx_ring_size; i++) { -+ /* Initialize Rx buffers from the shared memory */ -+ -+ data = (u32)dma_map_single(hif->dev, hif->shm->rx_buf_pool[i], -+ pfe_pkt_size, DMA_FROM_DEVICE); -+ hif->rx_buf_addr[i] = hif->shm->rx_buf_pool[i]; -+ hif->rx_buf_len[i] = pfe_pkt_size; -+ hif->shm->rx_buf_pool[i] = NULL; -+ -+ if (likely(dma_mapping_error(hif->dev, data) == 0)) { -+ writel(DDR_PHYS_TO_PFE(data), &desc->data); -+ } else { -+ pr_err("%s : low on mem\n", __func__); -+ -+ goto err; -+ } -+ -+ writel(0, &desc->status); -+ -+ /* -+ * Ensure everything else is written to DDR before -+ * writing bd->ctrl -+ */ -+ wmb(); -+ -+ writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM -+ | BD_CTRL_DIR | BD_CTRL_DESC_EN -+ | BD_BUF_LEN(pfe_pkt_size)), &desc->ctrl); -+ -+ /* Chain descriptors */ -+ writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next); -+ desc++; -+ } -+ -+ /* Overwrite last descriptor to chain it to first one*/ -+ desc--; -+ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next); -+ -+ hif->rxtoclean_index = 0; -+ -+ /*Initialize Rx buffer descriptor ring base address */ -+ writel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR); -+ -+ hif->tx_base = hif->rx_base + hif->rx_ring_size; -+ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p + -+ hif->rx_ring_size; -+ memset(hif->tx_base, 0, hif->tx_ring_size * sizeof(struct hif_desc)); -+ -+ /*Initialize tx descriptors */ -+ desc = hif->tx_base; -+ -+ for (i = 0; i < hif->tx_ring_size; i++) { -+ /* Chain descriptors */ -+ writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next); -+ writel(0, &desc->ctrl); -+ desc++; -+ } -+ -+ /* Overwrite last descriptor to chain it to first one */ -+ desc--; -+ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next); -+ hif->txavail = hif->tx_ring_size; -+ hif->txtosend = 0; -+ hif->txtoclean = 0; -+ hif->txtoflush = 0; -+ -+ /*Initialize Tx buffer descriptor ring base address */ -+ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR); -+ -+ return 0; -+ -+err: -+ pfe_hif_release_buffers(hif); -+ return -ENOMEM; -+} -+ -+/* -+ * pfe_hif_client_register -+ * -+ * This function used to register a client driver with the HIF driver. -+ * -+ * Return value: -+ * 0 - on Successful registration -+ */ -+static int pfe_hif_client_register(struct pfe_hif *hif, u32 client_id, -+ struct hif_client_shm *client_shm) -+{ -+ struct hif_client *client = &hif->client[client_id]; -+ u32 i, cnt; -+ struct rx_queue_desc *rx_qbase; -+ struct tx_queue_desc *tx_qbase; -+ struct hif_rx_queue *rx_queue; -+ struct hif_tx_queue *tx_queue; -+ int err = 0; -+ -+ pr_info("%s\n", __func__); -+ -+ spin_lock_bh(&hif->tx_lock); -+ -+ if (test_bit(client_id, &hif->shm->g_client_status[0])) { -+ pr_err("%s: client %d already registered\n", -+ __func__, client_id); -+ err = -1; -+ goto unlock; -+ } -+ -+ memset(client, 0, sizeof(struct hif_client)); -+ -+ /* Initialize client Rx queues baseaddr, size */ -+ -+ cnt = CLIENT_CTRL_RX_Q_CNT(client_shm->ctrl); -+ /* Check if client is requesting for more queues than supported */ -+ if (cnt > HIF_CLIENT_QUEUES_MAX) -+ cnt = HIF_CLIENT_QUEUES_MAX; -+ -+ client->rx_qn = cnt; -+ rx_qbase = (struct rx_queue_desc *)client_shm->rx_qbase; -+ for (i = 0; i < cnt; i++) { -+ rx_queue = &client->rx_q[i]; -+ rx_queue->base = rx_qbase + i * client_shm->rx_qsize; -+ rx_queue->size = client_shm->rx_qsize; -+ rx_queue->write_idx = 0; -+ } -+ -+ /* Initialize client Tx queues baseaddr, size */ -+ cnt = CLIENT_CTRL_TX_Q_CNT(client_shm->ctrl); -+ -+ /* Check if client is requesting for more queues than supported */ -+ if (cnt > HIF_CLIENT_QUEUES_MAX) -+ cnt = HIF_CLIENT_QUEUES_MAX; -+ -+ client->tx_qn = cnt; -+ tx_qbase = (struct tx_queue_desc *)client_shm->tx_qbase; -+ for (i = 0; i < cnt; i++) { -+ tx_queue = &client->tx_q[i]; -+ tx_queue->base = tx_qbase + i * client_shm->tx_qsize; -+ tx_queue->size = client_shm->tx_qsize; -+ tx_queue->ack_idx = 0; -+ } -+ -+ set_bit(client_id, &hif->shm->g_client_status[0]); -+ -+unlock: -+ spin_unlock_bh(&hif->tx_lock); -+ -+ return err; -+} -+ -+/* -+ * pfe_hif_client_unregister -+ * -+ * This function used to unregister a client from the HIF driver. -+ * -+ */ -+static void pfe_hif_client_unregister(struct pfe_hif *hif, u32 client_id) -+{ -+ pr_info("%s\n", __func__); -+ -+ /* -+ * Mark client as no longer available (which prevents further packet -+ * receive for this client) -+ */ -+ spin_lock_bh(&hif->tx_lock); -+ -+ if (!test_bit(client_id, &hif->shm->g_client_status[0])) { -+ pr_err("%s: client %d not registered\n", __func__, -+ client_id); -+ -+ spin_unlock_bh(&hif->tx_lock); -+ return; -+ } -+ -+ clear_bit(client_id, &hif->shm->g_client_status[0]); -+ -+ spin_unlock_bh(&hif->tx_lock); -+} -+ -+/* -+ * client_put_rxpacket- -+ * This functions puts the Rx pkt in the given client Rx queue. -+ * It actually swap the Rx pkt in the client Rx descriptor buffer -+ * and returns the free buffer from it. -+ * -+ * If the function returns NULL means client Rx queue is full and -+ * packet couldn't send to client queue. -+ */ -+static void *client_put_rxpacket(struct hif_rx_queue *queue, void *pkt, u32 len, -+ u32 flags, u32 client_ctrl, u32 *rem_len) -+{ -+ void *free_pkt = NULL; -+ struct rx_queue_desc *desc = queue->base + queue->write_idx; -+ -+ if (readl(&desc->ctrl) & CL_DESC_OWN) { -+ if (page_mode) { -+ int rem_page_size = PAGE_SIZE - -+ PRESENT_OFST_IN_PAGE(pkt); -+ int cur_pkt_size = ROUND_MIN_RX_SIZE(len + -+ pfe_pkt_headroom); -+ *rem_len = (rem_page_size - cur_pkt_size); -+ if (*rem_len) { -+ free_pkt = pkt + cur_pkt_size; -+ get_page(virt_to_page(free_pkt)); -+ } else { -+ free_pkt = (void -+ *)__get_free_page(GFP_ATOMIC | GFP_DMA_PFE); -+ *rem_len = pfe_pkt_size; -+ } -+ } else { -+ free_pkt = kmalloc(PFE_BUF_SIZE, GFP_ATOMIC | -+ GFP_DMA_PFE); -+ *rem_len = PFE_BUF_SIZE - pfe_pkt_headroom; -+ } -+ -+ if (free_pkt) { -+ desc->data = pkt; -+ desc->client_ctrl = client_ctrl; -+ /* -+ * Ensure everything else is written to DDR before -+ * writing bd->ctrl -+ */ -+ smp_wmb(); -+ writel(CL_DESC_BUF_LEN(len) | flags, &desc->ctrl); -+ queue->write_idx = (queue->write_idx + 1) -+ & (queue->size - 1); -+ -+ free_pkt += pfe_pkt_headroom; -+ } -+ } -+ -+ return free_pkt; -+} -+ -+/* -+ * pfe_hif_rx_process- -+ * This function does pfe hif rx queue processing. -+ * Dequeue packet from Rx queue and send it to corresponding client queue -+ */ -+static int pfe_hif_rx_process(struct pfe_hif *hif, int budget) -+{ -+ struct hif_desc *desc; -+ struct hif_hdr *pkt_hdr; -+ struct __hif_hdr hif_hdr; -+ void *free_buf; -+ int rtc, len, rx_processed = 0; -+ struct __hif_desc local_desc; -+ int flags; -+ unsigned int desc_p; -+ unsigned int buf_size = 0; -+ -+ spin_lock_bh(&hif->lock); -+ -+ rtc = hif->rxtoclean_index; -+ -+ while (rx_processed < budget) { -+ desc = hif->rx_base + rtc; -+ -+ __memcpy12(&local_desc, desc); -+ -+ /* ACK pending Rx interrupt */ -+ if (local_desc.ctrl & BD_CTRL_DESC_EN) { -+ writel(HIF_INT | HIF_RXPKT_INT, HIF_INT_SRC); -+ -+ if (rx_processed == 0) { -+ if (napi_first_batch == 1) { -+ desc_p = hif->descr_baseaddr_p + -+ ((unsigned long int)(desc) - -+ (unsigned long -+ int)hif->descr_baseaddr_v); -+ napi_first_batch = 0; -+ } -+ } -+ -+ __memcpy12(&local_desc, desc); -+ -+ if (local_desc.ctrl & BD_CTRL_DESC_EN) -+ break; -+ } -+ -+ napi_first_batch = 0; -+ -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_DESC_COUNT]++; -+#endif -+ len = BD_BUF_LEN(local_desc.ctrl); -+ /* -+ * dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), -+ * hif->rx_buf_len[rtc], DMA_FROM_DEVICE); -+ */ -+ dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data), -+ hif->rx_buf_len[rtc], DMA_FROM_DEVICE); -+ -+ pkt_hdr = (struct hif_hdr *)hif->rx_buf_addr[rtc]; -+ -+ /* Track last HIF header received */ -+ if (!hif->started) { -+ hif->started = 1; -+ -+ __memcpy8(&hif_hdr, pkt_hdr); -+ -+ hif->qno = hif_hdr.hdr.q_num; -+ hif->client_id = hif_hdr.hdr.client_id; -+ hif->client_ctrl = (hif_hdr.hdr.client_ctrl1 << 16) | -+ hif_hdr.hdr.client_ctrl; -+ flags = CL_DESC_FIRST; -+ -+ } else { -+ flags = 0; -+ } -+ -+ if (local_desc.ctrl & BD_CTRL_LIFM) -+ flags |= CL_DESC_LAST; -+ -+ /* Check for valid client id and still registered */ -+ if ((hif->client_id >= HIF_CLIENTS_MAX) || -+ !(test_bit(hif->client_id, -+ &hif->shm->g_client_status[0]))) { -+ printk_ratelimited("%s: packet with invalid client id %d q_num %d\n", -+ __func__, -+ hif->client_id, -+ hif->qno); -+ -+ free_buf = pkt_hdr; -+ -+ goto pkt_drop; -+ } -+ -+ /* Check to valid queue number */ -+ if (hif->client[hif->client_id].rx_qn <= hif->qno) { -+ pr_info("%s: packet with invalid queue: %d\n" -+ , __func__, hif->qno); -+ hif->qno = 0; -+ } -+ -+ free_buf = -+ client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno], -+ (void *)pkt_hdr, len, flags, -+ hif->client_ctrl, &buf_size); -+ -+ hif_lib_indicate_client(hif->client_id, EVENT_RX_PKT_IND, -+ hif->qno); -+ -+ if (unlikely(!free_buf)) { -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_CLIENT_FULL_COUNT]++; -+#endif -+ /* -+ * If we want to keep in polling mode to retry later, -+ * we need to tell napi that we consumed -+ * the full budget or we will hit a livelock scenario. -+ * The core code keeps this napi instance -+ * at the head of the list and none of the other -+ * instances get to run -+ */ -+ rx_processed = budget; -+ -+ if (flags & CL_DESC_FIRST) -+ hif->started = 0; -+ -+ break; -+ } -+ -+pkt_drop: -+ /*Fill free buffer in the descriptor */ -+ hif->rx_buf_addr[rtc] = free_buf; -+ hif->rx_buf_len[rtc] = min(pfe_pkt_size, buf_size); -+ writel((DDR_PHYS_TO_PFE -+ ((u32)dma_map_single(hif->dev, -+ free_buf, hif->rx_buf_len[rtc], DMA_FROM_DEVICE))), -+ &desc->data); -+ /* -+ * Ensure everything else is written to DDR before -+ * writing bd->ctrl -+ */ -+ wmb(); -+ writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR | -+ BD_CTRL_DESC_EN | BD_BUF_LEN(hif->rx_buf_len[rtc])), -+ &desc->ctrl); -+ -+ rtc = (rtc + 1) & (hif->rx_ring_size - 1); -+ -+ if (local_desc.ctrl & BD_CTRL_LIFM) { -+ if (!(hif->client_ctrl & HIF_CTRL_RX_CONTINUED)) { -+ rx_processed++; -+ -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_PACKET_COUNT]++; -+#endif -+ } -+ hif->started = 0; -+ } -+ } -+ -+ hif->rxtoclean_index = rtc; -+ spin_unlock_bh(&hif->lock); -+ -+ /* we made some progress, re-start rx dma in case it stopped */ -+ hif_rx_dma_start(); -+ -+ return rx_processed; -+} -+ -+/* -+ * client_ack_txpacket- -+ * This function ack the Tx packet in the give client Tx queue by resetting -+ * ownership bit in the descriptor. -+ */ -+static int client_ack_txpacket(struct pfe_hif *hif, unsigned int client_id, -+ unsigned int q_no) -+{ -+ struct hif_tx_queue *queue = &hif->client[client_id].tx_q[q_no]; -+ struct tx_queue_desc *desc = queue->base + queue->ack_idx; -+ -+ if (readl(&desc->ctrl) & CL_DESC_OWN) { -+ writel((readl(&desc->ctrl) & ~CL_DESC_OWN), &desc->ctrl); -+ queue->ack_idx = (queue->ack_idx + 1) & (queue->size - 1); -+ -+ return 0; -+ -+ } else { -+ /*This should not happen */ -+ pr_err("%s: %d %d %d %d %d %p %d\n", __func__, -+ hif->txtosend, hif->txtoclean, hif->txavail, -+ client_id, q_no, queue, queue->ack_idx); -+ WARN(1, "%s: doesn't own this descriptor", __func__); -+ return 1; -+ } -+} -+ -+void __hif_tx_done_process(struct pfe_hif *hif, int count) -+{ -+ struct hif_desc *desc; -+ struct hif_desc_sw *desc_sw; -+ int ttc, tx_avl; -+ int pkts_done[HIF_CLIENTS_MAX] = {0, 0}; -+ -+ ttc = hif->txtoclean; -+ tx_avl = hif->txavail; -+ -+ while ((tx_avl < hif->tx_ring_size) && count--) { -+ desc = hif->tx_base + ttc; -+ -+ if (readl(&desc->ctrl) & BD_CTRL_DESC_EN) -+ break; -+ -+ desc_sw = &hif->tx_sw_queue[ttc]; -+ -+ if (desc_sw->data) { -+ /* -+ * dmap_unmap_single(hif->dev, desc_sw->data, -+ * desc_sw->len, DMA_TO_DEVICE); -+ */ -+ dma_unmap_single(hif->dev, desc_sw->data, -+ desc_sw->len, DMA_TO_DEVICE); -+ } -+ -+ if (desc_sw->client_id >= HIF_CLIENTS_MAX) { -+ pr_err("Invalid cl id %d\n", desc_sw->client_id); -+ break; -+ } -+ -+ pkts_done[desc_sw->client_id]++; -+ -+ client_ack_txpacket(hif, desc_sw->client_id, desc_sw->q_no); -+ -+ ttc = (ttc + 1) & (hif->tx_ring_size - 1); -+ tx_avl++; -+ } -+ -+ if (pkts_done[0]) -+ hif_lib_indicate_client(0, EVENT_TXDONE_IND, 0); -+ if (pkts_done[1]) -+ hif_lib_indicate_client(1, EVENT_TXDONE_IND, 0); -+ -+ hif->txtoclean = ttc; -+ hif->txavail = tx_avl; -+ -+ if (!count) { -+ tasklet_schedule(&hif->tx_cleanup_tasklet); -+ } else { -+ /*Enable Tx done interrupt */ -+ writel(readl_relaxed(HIF_INT_ENABLE) | HIF_TXPKT_INT, -+ HIF_INT_ENABLE); -+ } -+} -+ -+static void pfe_tx_do_cleanup(unsigned long data) -+{ -+ struct pfe_hif *hif = (struct pfe_hif *)data; -+ -+ writel(HIF_INT | HIF_TXPKT_INT, HIF_INT_SRC); -+ -+ hif_tx_done_process(hif, 64); -+} -+ -+/* -+ * __hif_xmit_pkt - -+ * This function puts one packet in the HIF Tx queue -+ */ -+void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int -+ q_no, void *data, u32 len, unsigned int flags) -+{ -+ struct hif_desc *desc; -+ struct hif_desc_sw *desc_sw; -+ -+ desc = hif->tx_base + hif->txtosend; -+ desc_sw = &hif->tx_sw_queue[hif->txtosend]; -+ -+ desc_sw->len = len; -+ desc_sw->client_id = client_id; -+ desc_sw->q_no = q_no; -+ desc_sw->flags = flags; -+ -+ if (flags & HIF_DONT_DMA_MAP) { -+ desc_sw->data = 0; -+ writel((u32)DDR_PHYS_TO_PFE(data), &desc->data); -+ } else { -+ desc_sw->data = dma_map_single(hif->dev, data, len, -+ DMA_TO_DEVICE); -+ writel((u32)DDR_PHYS_TO_PFE(desc_sw->data), &desc->data); -+ } -+ -+ hif->txtosend = (hif->txtosend + 1) & (hif->tx_ring_size - 1); -+ hif->txavail--; -+ -+ if ((!((flags & HIF_DATA_VALID) && (flags & -+ HIF_LAST_BUFFER)))) -+ goto skip_tx; -+ -+ /* -+ * Ensure everything else is written to DDR before -+ * writing bd->ctrl -+ */ -+ wmb(); -+ -+ do { -+ desc_sw = &hif->tx_sw_queue[hif->txtoflush]; -+ desc = hif->tx_base + hif->txtoflush; -+ -+ if (desc_sw->flags & HIF_LAST_BUFFER) { -+ writel((BD_CTRL_LIFM | -+ BD_CTRL_BRFETCH_DISABLE | BD_CTRL_RTFETCH_DISABLE -+ | BD_CTRL_PARSE_DISABLE | BD_CTRL_DESC_EN | -+ BD_CTRL_PKT_INT_EN | BD_BUF_LEN(desc_sw->len)), -+ &desc->ctrl); -+ } else { -+ writel((BD_CTRL_DESC_EN | -+ BD_BUF_LEN(desc_sw->len)), &desc->ctrl); -+ } -+ hif->txtoflush = (hif->txtoflush + 1) & (hif->tx_ring_size - 1); -+ } -+ while (hif->txtoflush != hif->txtosend) -+ ; -+ -+skip_tx: -+ return; -+} -+ -+static irqreturn_t wol_isr(int irq, void *dev_id) -+{ -+ pr_info("WoL\n"); -+ gemac_set_wol(EMAC1_BASE_ADDR, 0); -+ gemac_set_wol(EMAC2_BASE_ADDR, 0); -+ return IRQ_HANDLED; -+} -+ -+/* -+ * hif_isr- -+ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block -+ */ -+static irqreturn_t hif_isr(int irq, void *dev_id) -+{ -+ struct pfe_hif *hif = (struct pfe_hif *)dev_id; -+ int int_status; -+ int int_enable_mask; -+ -+ /*Read hif interrupt source register */ -+ int_status = readl_relaxed(HIF_INT_SRC); -+ int_enable_mask = readl_relaxed(HIF_INT_ENABLE); -+ -+ if ((int_status & HIF_INT) == 0) -+ return IRQ_NONE; -+ -+ int_status &= ~(HIF_INT); -+ -+ if (int_status & HIF_RXPKT_INT) { -+ int_status &= ~(HIF_RXPKT_INT); -+ int_enable_mask &= ~(HIF_RXPKT_INT); -+ -+ napi_first_batch = 1; -+ -+ if (napi_schedule_prep(&hif->napi)) { -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_SCHED_COUNT]++; -+#endif -+ __napi_schedule(&hif->napi); -+ } -+ } -+ -+ if (int_status & HIF_TXPKT_INT) { -+ int_status &= ~(HIF_TXPKT_INT); -+ int_enable_mask &= ~(HIF_TXPKT_INT); -+ /*Schedule tx cleanup tassklet */ -+ tasklet_schedule(&hif->tx_cleanup_tasklet); -+ } -+ -+ /*Disable interrupts, they will be enabled after they are serviced */ -+ writel_relaxed(int_enable_mask, HIF_INT_ENABLE); -+ -+ if (int_status) { -+ pr_info("%s : Invalid interrupt : %d\n", __func__, -+ int_status); -+ writel(int_status, HIF_INT_SRC); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2) -+{ -+ unsigned int client_id = data1; -+ -+ if (client_id >= HIF_CLIENTS_MAX) { -+ pr_err("%s: client id %d out of bounds\n", __func__, -+ client_id); -+ return; -+ } -+ -+ switch (req) { -+ case REQUEST_CL_REGISTER: -+ /* Request for register a client */ -+ pr_info("%s: register client_id %d\n", -+ __func__, client_id); -+ pfe_hif_client_register(hif, client_id, (struct -+ hif_client_shm *)&hif->shm->client[client_id]); -+ break; -+ -+ case REQUEST_CL_UNREGISTER: -+ pr_info("%s: unregister client_id %d\n", -+ __func__, client_id); -+ -+ /* Request for unregister a client */ -+ pfe_hif_client_unregister(hif, client_id); -+ -+ break; -+ -+ default: -+ pr_err("%s: unsupported request %d\n", -+ __func__, req); -+ break; -+ } -+ -+ /* -+ * Process client Tx queues -+ * Currently we don't have checking for tx pending -+ */ -+} -+ -+/* -+ * pfe_hif_rx_poll -+ * This function is NAPI poll function to process HIF Rx queue. -+ */ -+static int pfe_hif_rx_poll(struct napi_struct *napi, int budget) -+{ -+ struct pfe_hif *hif = container_of(napi, struct pfe_hif, napi); -+ int work_done; -+ -+#ifdef HIF_NAPI_STATS -+ hif->napi_counters[NAPI_POLL_COUNT]++; -+#endif -+ -+ work_done = pfe_hif_rx_process(hif, budget); -+ -+ if (work_done < budget) { -+ napi_complete(napi); -+ writel(readl_relaxed(HIF_INT_ENABLE) | HIF_RXPKT_INT, -+ HIF_INT_ENABLE); -+ } -+#ifdef HIF_NAPI_STATS -+ else -+ hif->napi_counters[NAPI_FULL_BUDGET_COUNT]++; -+#endif -+ -+ return work_done; -+} -+ -+/* -+ * pfe_hif_init -+ * This function initializes the baseaddresses and irq, etc. -+ */ -+int pfe_hif_init(struct pfe *pfe) -+{ -+ struct pfe_hif *hif = &pfe->hif; -+ int err; -+ -+ pr_info("%s\n", __func__); -+ -+ hif->dev = pfe->dev; -+ hif->irq = pfe->hif_irq; -+ -+ err = pfe_hif_alloc_descr(hif); -+ if (err) -+ goto err0; -+ -+ if (pfe_hif_init_buffers(hif)) { -+ pr_err("%s: Could not initialize buffer descriptors\n" -+ , __func__); -+ err = -ENOMEM; -+ goto err1; -+ } -+ -+ /* Initialize NAPI for Rx processing */ -+ init_dummy_netdev(&hif->dummy_dev); -+ netif_napi_add(&hif->dummy_dev, &hif->napi, pfe_hif_rx_poll, -+ HIF_RX_POLL_WEIGHT); -+ napi_enable(&hif->napi); -+ -+ spin_lock_init(&hif->tx_lock); -+ spin_lock_init(&hif->lock); -+ -+ hif_init(); -+ hif_rx_enable(); -+ hif_tx_enable(); -+ -+ /* Disable tx done interrupt */ -+ writel(HIF_INT_MASK, HIF_INT_ENABLE); -+ -+ gpi_enable(HGPI_BASE_ADDR); -+ -+ err = request_irq(hif->irq, hif_isr, 0, "pfe_hif", hif); -+ if (err) { -+ pr_err("%s: failed to get the hif IRQ = %d\n", -+ __func__, hif->irq); -+ goto err1; -+ } -+ -+ err = request_irq(pfe->wol_irq, wol_isr, 0, "pfe_wol", pfe); -+ if (err) { -+ pr_err("%s: failed to get the wol IRQ = %d\n", -+ __func__, pfe->wol_irq); -+ goto err1; -+ } -+ -+ tasklet_init(&hif->tx_cleanup_tasklet, -+ (void(*)(unsigned long))pfe_tx_do_cleanup, -+ (unsigned long)hif); -+ -+ return 0; -+err1: -+ pfe_hif_free_descr(hif); -+err0: -+ return err; -+} -+ -+/* pfe_hif_exit- */ -+void pfe_hif_exit(struct pfe *pfe) -+{ -+ struct pfe_hif *hif = &pfe->hif; -+ -+ pr_info("%s\n", __func__); -+ -+ tasklet_kill(&hif->tx_cleanup_tasklet); -+ -+ spin_lock_bh(&hif->lock); -+ hif->shm->g_client_status[0] = 0; -+ /* Make sure all clients are disabled*/ -+ hif->shm->g_client_status[1] = 0; -+ -+ spin_unlock_bh(&hif->lock); -+ -+ /*Disable Rx/Tx */ -+ gpi_disable(HGPI_BASE_ADDR); -+ hif_rx_disable(); -+ hif_tx_disable(); -+ -+ napi_disable(&hif->napi); -+ netif_napi_del(&hif->napi); -+ -+ free_irq(pfe->wol_irq, pfe); -+ free_irq(hif->irq, hif); -+ -+ pfe_hif_release_buffers(hif); -+ pfe_hif_free_descr(hif); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hif.h -@@ -0,0 +1,199 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_HIF_H_ -+#define _PFE_HIF_H_ -+ -+#include -+ -+#define HIF_NAPI_STATS -+ -+#define HIF_CLIENT_QUEUES_MAX 16 -+#define HIF_RX_POLL_WEIGHT 64 -+ -+#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */ -+#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1) -+#define ROUND_MIN_RX_SIZE(_sz) (((_sz) + (HIF_RX_PKT_MIN_SIZE - 1)) \ -+ & HIF_RX_PKT_MIN_SIZE_MASK) -+#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)(_buf) & (PAGE_SIZE \ -+ - 1)) & HIF_RX_PKT_MIN_SIZE_MASK) -+ -+enum { -+ NAPI_SCHED_COUNT = 0, -+ NAPI_POLL_COUNT, -+ NAPI_PACKET_COUNT, -+ NAPI_DESC_COUNT, -+ NAPI_FULL_BUDGET_COUNT, -+ NAPI_CLIENT_FULL_COUNT, -+ NAPI_MAX_COUNT -+}; -+ -+/* -+ * HIF_TX_DESC_NT value should be always greter than 4, -+ * Otherwise HIF_TX_POLL_MARK will become zero. -+ */ -+#define HIF_RX_DESC_NT 256 -+#define HIF_TX_DESC_NT 2048 -+ -+#define HIF_FIRST_BUFFER BIT(0) -+#define HIF_LAST_BUFFER BIT(1) -+#define HIF_DONT_DMA_MAP BIT(2) -+#define HIF_DATA_VALID BIT(3) -+#define HIF_TSO BIT(4) -+ -+enum { -+ PFE_CL_GEM0 = 0, -+ PFE_CL_GEM1, -+ HIF_CLIENTS_MAX -+}; -+ -+/*structure to store client queue info */ -+struct hif_rx_queue { -+ struct rx_queue_desc *base; -+ u32 size; -+ u32 write_idx; -+}; -+ -+struct hif_tx_queue { -+ struct tx_queue_desc *base; -+ u32 size; -+ u32 ack_idx; -+}; -+ -+/*Structure to store the client info */ -+struct hif_client { -+ int rx_qn; -+ struct hif_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX]; -+ int tx_qn; -+ struct hif_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX]; -+}; -+ -+/*HIF hardware buffer descriptor */ -+struct hif_desc { -+ u32 ctrl; -+ u32 status; -+ u32 data; -+ u32 next; -+}; -+ -+struct __hif_desc { -+ u32 ctrl; -+ u32 status; -+ u32 data; -+}; -+ -+struct hif_desc_sw { -+ dma_addr_t data; -+ u16 len; -+ u8 client_id; -+ u8 q_no; -+ u16 flags; -+}; -+ -+struct hif_hdr { -+ u8 client_id; -+ u8 q_num; -+ u16 client_ctrl; -+ u16 client_ctrl1; -+}; -+ -+struct __hif_hdr { -+ union { -+ struct hif_hdr hdr; -+ u32 word[2]; -+ }; -+}; -+ -+struct hif_ipsec_hdr { -+ u16 sa_handle[2]; -+} __packed; -+ -+/* HIF_CTRL_TX... defines */ -+#define HIF_CTRL_TX_CHECKSUM BIT(2) -+ -+/* HIF_CTRL_RX... defines */ -+#define HIF_CTRL_RX_OFFSET_OFST (24) -+#define HIF_CTRL_RX_CHECKSUMMED BIT(2) -+#define HIF_CTRL_RX_CONTINUED BIT(1) -+ -+struct pfe_hif { -+ /* To store registered clients in hif layer */ -+ struct hif_client client[HIF_CLIENTS_MAX]; -+ struct hif_shm *shm; -+ int irq; -+ -+ void *descr_baseaddr_v; -+ unsigned long descr_baseaddr_p; -+ -+ struct hif_desc *rx_base; -+ u32 rx_ring_size; -+ u32 rxtoclean_index; -+ void *rx_buf_addr[HIF_RX_DESC_NT]; -+ int rx_buf_len[HIF_RX_DESC_NT]; -+ unsigned int qno; -+ unsigned int client_id; -+ unsigned int client_ctrl; -+ unsigned int started; -+ -+ struct hif_desc *tx_base; -+ u32 tx_ring_size; -+ u32 txtosend; -+ u32 txtoclean; -+ u32 txavail; -+ u32 txtoflush; -+ struct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT]; -+ -+/* tx_lock synchronizes hif packet tx as well as pfe_hif structure access */ -+ spinlock_t tx_lock; -+/* lock synchronizes hif rx queue processing */ -+ spinlock_t lock; -+ struct net_device dummy_dev; -+ struct napi_struct napi; -+ struct device *dev; -+ -+#ifdef HIF_NAPI_STATS -+ unsigned int napi_counters[NAPI_MAX_COUNT]; -+#endif -+ struct tasklet_struct tx_cleanup_tasklet; -+}; -+ -+void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int -+ q_no, void *data, u32 len, unsigned int flags); -+int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no, -+ void *data, unsigned int len); -+void __hif_tx_done_process(struct pfe_hif *hif, int count); -+void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int -+ data2); -+int pfe_hif_init(struct pfe *pfe); -+void pfe_hif_exit(struct pfe *pfe); -+void pfe_hif_rx_idle(struct pfe_hif *hif); -+static inline void hif_tx_done_process(struct pfe_hif *hif, int count) -+{ -+ spin_lock_bh(&hif->tx_lock); -+ __hif_tx_done_process(hif, count); -+ spin_unlock_bh(&hif->tx_lock); -+} -+ -+static inline void hif_tx_lock(struct pfe_hif *hif) -+{ -+ spin_lock_bh(&hif->tx_lock); -+} -+ -+static inline void hif_tx_unlock(struct pfe_hif *hif) -+{ -+ spin_unlock_bh(&hif->tx_lock); -+} -+ -+static inline int __hif_tx_avail(struct pfe_hif *hif) -+{ -+ return hif->txavail; -+} -+ -+#define __memcpy8(dst, src) memcpy(dst, src, 8) -+#define __memcpy12(dst, src) memcpy(dst, src, 12) -+#define __memcpy(dst, src, len) memcpy(dst, src, len) -+ -+#endif /* _PFE_HIF_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c -@@ -0,0 +1,628 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pfe_mod.h" -+#include "pfe_hif.h" -+#include "pfe_hif_lib.h" -+ -+unsigned int lro_mode; -+unsigned int page_mode; -+unsigned int tx_qos = 1; -+module_param(tx_qos, uint, 0444); -+MODULE_PARM_DESC(tx_qos, "0: disable ,\n" -+ "1: enable (default), guarantee no packet drop at TMU level\n"); -+unsigned int pfe_pkt_size; -+unsigned int pfe_pkt_headroom; -+unsigned int emac_txq_cnt; -+ -+/* -+ * @pfe_hal_lib.c. -+ * Common functions used by HIF client drivers -+ */ -+ -+/*HIF shared memory Global variable */ -+struct hif_shm ghif_shm; -+ -+/* Cleanup the HIF shared memory, release HIF rx_buffer_pool. -+ * This function should be called after pfe_hif_exit -+ * -+ * @param[in] hif_shm Shared memory address location in DDR -+ */ -+static void pfe_hif_shm_clean(struct hif_shm *hif_shm) -+{ -+ int i; -+ void *pkt; -+ -+ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) { -+ pkt = hif_shm->rx_buf_pool[i]; -+ if (pkt) { -+ hif_shm->rx_buf_pool[i] = NULL; -+ pkt -= pfe_pkt_headroom; -+ -+ if (page_mode) -+ put_page(virt_to_page(pkt)); -+ else -+ kfree(pkt); -+ } -+ } -+} -+ -+/* Initialize shared memory used between HIF driver and clients, -+ * allocate rx_buffer_pool required for HIF Rx descriptors. -+ * This function should be called before initializing HIF driver. -+ * -+ * @param[in] hif_shm Shared memory address location in DDR -+ * @rerurn 0 - on succes, <0 on fail to initialize -+ */ -+static int pfe_hif_shm_init(struct hif_shm *hif_shm) -+{ -+ int i; -+ void *pkt; -+ -+ memset(hif_shm, 0, sizeof(struct hif_shm)); -+ hif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT; -+ -+ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) { -+ if (page_mode) { -+ pkt = (void *)__get_free_page(GFP_KERNEL | -+ GFP_DMA_PFE); -+ } else { -+ pkt = kmalloc(PFE_BUF_SIZE, GFP_KERNEL | GFP_DMA_PFE); -+ } -+ -+ if (pkt) -+ hif_shm->rx_buf_pool[i] = pkt + pfe_pkt_headroom; -+ else -+ goto err0; -+ } -+ -+ return 0; -+ -+err0: -+ pr_err("%s Low memory\n", __func__); -+ pfe_hif_shm_clean(hif_shm); -+ return -ENOMEM; -+} -+ -+/*This function sends indication to HIF driver -+ * -+ * @param[in] hif hif context -+ */ -+static void hif_lib_indicate_hif(struct pfe_hif *hif, int req, int data1, int -+ data2) -+{ -+ hif_process_client_req(hif, req, data1, data2); -+} -+ -+void hif_lib_indicate_client(int client_id, int event_type, int qno) -+{ -+ struct hif_client_s *client = pfe->hif_client[client_id]; -+ -+ if (!client || (event_type >= HIF_EVENT_MAX) || (qno >= -+ HIF_CLIENT_QUEUES_MAX)) -+ return; -+ -+ if (!test_and_set_bit(qno, &client->queue_mask[event_type])) -+ client->event_handler(client->priv, event_type, qno); -+} -+ -+/*This function releases Rx queue descriptors memory and pre-filled buffers -+ * -+ * @param[in] client hif_client context -+ */ -+static void hif_lib_client_release_rx_buffers(struct hif_client_s *client) -+{ -+ struct rx_queue_desc *desc; -+ int qno, ii; -+ void *buf; -+ -+ for (qno = 0; qno < client->rx_qn; qno++) { -+ desc = client->rx_q[qno].base; -+ -+ for (ii = 0; ii < client->rx_q[qno].size; ii++) { -+ buf = (void *)desc->data; -+ if (buf) { -+ buf -= pfe_pkt_headroom; -+ -+ if (page_mode) -+ free_page((unsigned long)buf); -+ else -+ kfree(buf); -+ -+ desc->ctrl = 0; -+ } -+ -+ desc++; -+ } -+ } -+ -+ kfree(client->rx_qbase); -+} -+ -+/*This function allocates memory for the rxq descriptors and pre-fill rx queues -+ * with buffers. -+ * @param[in] client client context -+ * @param[in] q_size size of the rxQ, all queues are of same size -+ */ -+static int hif_lib_client_init_rx_buffers(struct hif_client_s *client, int -+ q_size) -+{ -+ struct rx_queue_desc *desc; -+ struct hif_client_rx_queue *queue; -+ int ii, qno; -+ -+ /*Allocate memory for the client queues */ -+ client->rx_qbase = kzalloc(client->rx_qn * q_size * sizeof(struct -+ rx_queue_desc), GFP_KERNEL); -+ if (!client->rx_qbase) -+ goto err; -+ -+ for (qno = 0; qno < client->rx_qn; qno++) { -+ queue = &client->rx_q[qno]; -+ -+ queue->base = client->rx_qbase + qno * q_size * sizeof(struct -+ rx_queue_desc); -+ queue->size = q_size; -+ queue->read_idx = 0; -+ queue->write_idx = 0; -+ -+ pr_debug("rx queue: %d, base: %p, size: %d\n", qno, -+ queue->base, queue->size); -+ } -+ -+ for (qno = 0; qno < client->rx_qn; qno++) { -+ queue = &client->rx_q[qno]; -+ desc = queue->base; -+ -+ for (ii = 0; ii < queue->size; ii++) { -+ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | -+ CL_DESC_OWN; -+ desc++; -+ } -+ } -+ -+ return 0; -+ -+err: -+ return 1; -+} -+ -+ -+static void hif_lib_client_cleanup_tx_queue(struct hif_client_tx_queue *queue) -+{ -+ pr_debug("%s\n", __func__); -+ -+ /* -+ * Check if there are any pending packets. Client must flush the tx -+ * queues before unregistering, by calling by calling -+ * hif_lib_tx_get_next_complete() -+ * -+ * Hif no longer calls since we are no longer registered -+ */ -+ if (queue->tx_pending) -+ pr_err("%s: pending transmit packets\n", __func__); -+} -+ -+static void hif_lib_client_release_tx_buffers(struct hif_client_s *client) -+{ -+ int qno; -+ -+ pr_debug("%s\n", __func__); -+ -+ for (qno = 0; qno < client->tx_qn; qno++) -+ hif_lib_client_cleanup_tx_queue(&client->tx_q[qno]); -+ -+ kfree(client->tx_qbase); -+} -+ -+static int hif_lib_client_init_tx_buffers(struct hif_client_s *client, int -+ q_size) -+{ -+ struct hif_client_tx_queue *queue; -+ int qno; -+ -+ client->tx_qbase = kzalloc(client->tx_qn * q_size * sizeof(struct -+ tx_queue_desc), GFP_KERNEL); -+ if (!client->tx_qbase) -+ return 1; -+ -+ for (qno = 0; qno < client->tx_qn; qno++) { -+ queue = &client->tx_q[qno]; -+ -+ queue->base = client->tx_qbase + qno * q_size * sizeof(struct -+ tx_queue_desc); -+ queue->size = q_size; -+ queue->read_idx = 0; -+ queue->write_idx = 0; -+ queue->tx_pending = 0; -+ queue->nocpy_flag = 0; -+ queue->prev_tmu_tx_pkts = 0; -+ queue->done_tmu_tx_pkts = 0; -+ -+ pr_debug("tx queue: %d, base: %p, size: %d\n", qno, -+ queue->base, queue->size); -+ } -+ -+ return 0; -+} -+ -+static int hif_lib_event_dummy(void *priv, int event_type, int qno) -+{ -+ return 0; -+} -+ -+int hif_lib_client_register(struct hif_client_s *client) -+{ -+ struct hif_shm *hif_shm; -+ struct hif_client_shm *client_shm; -+ int err, i; -+ /* int loop_cnt = 0; */ -+ -+ pr_debug("%s\n", __func__); -+ -+ /*Allocate memory before spin_lock*/ -+ if (hif_lib_client_init_rx_buffers(client, client->rx_qsize)) { -+ err = -ENOMEM; -+ goto err_rx; -+ } -+ -+ if (hif_lib_client_init_tx_buffers(client, client->tx_qsize)) { -+ err = -ENOMEM; -+ goto err_tx; -+ } -+ -+ spin_lock_bh(&pfe->hif.lock); -+ if (!(client->pfe) || (client->id >= HIF_CLIENTS_MAX) || -+ (pfe->hif_client[client->id])) { -+ err = -EINVAL; -+ goto err; -+ } -+ -+ hif_shm = client->pfe->hif.shm; -+ -+ if (!client->event_handler) -+ client->event_handler = hif_lib_event_dummy; -+ -+ /*Initialize client specific shared memory */ -+ client_shm = (struct hif_client_shm *)&hif_shm->client[client->id]; -+ client_shm->rx_qbase = (unsigned long int)client->rx_qbase; -+ client_shm->rx_qsize = client->rx_qsize; -+ client_shm->tx_qbase = (unsigned long int)client->tx_qbase; -+ client_shm->tx_qsize = client->tx_qsize; -+ client_shm->ctrl = (client->tx_qn << CLIENT_CTRL_TX_Q_CNT_OFST) | -+ (client->rx_qn << CLIENT_CTRL_RX_Q_CNT_OFST); -+ /* spin_lock_init(&client->rx_lock); */ -+ -+ for (i = 0; i < HIF_EVENT_MAX; i++) { -+ client->queue_mask[i] = 0; /* -+ * By default all events are -+ * unmasked -+ */ -+ } -+ -+ /*Indicate to HIF driver*/ -+ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_REGISTER, client->id, 0); -+ -+ pr_debug("%s: client: %p, client_id: %d, tx_qsize: %d, rx_qsize: %d\n", -+ __func__, client, client->id, client->tx_qsize, -+ client->rx_qsize); -+ -+ client->cpu_id = -1; -+ -+ pfe->hif_client[client->id] = client; -+ spin_unlock_bh(&pfe->hif.lock); -+ -+ return 0; -+ -+err: -+ spin_unlock_bh(&pfe->hif.lock); -+ hif_lib_client_release_tx_buffers(client); -+ -+err_tx: -+ hif_lib_client_release_rx_buffers(client); -+ -+err_rx: -+ return err; -+} -+ -+int hif_lib_client_unregister(struct hif_client_s *client) -+{ -+ struct pfe *pfe = client->pfe; -+ u32 client_id = client->id; -+ -+ pr_info( -+ "%s : client: %p, client_id: %d, txQ_depth: %d, rxQ_depth: %d\n" -+ , __func__, client, client->id, client->tx_qsize, -+ client->rx_qsize); -+ -+ spin_lock_bh(&pfe->hif.lock); -+ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_UNREGISTER, client->id, 0); -+ -+ hif_lib_client_release_tx_buffers(client); -+ hif_lib_client_release_rx_buffers(client); -+ pfe->hif_client[client_id] = NULL; -+ spin_unlock_bh(&pfe->hif.lock); -+ -+ return 0; -+} -+ -+int hif_lib_event_handler_start(struct hif_client_s *client, int event, -+ int qno) -+{ -+ struct hif_client_rx_queue *queue = &client->rx_q[qno]; -+ struct rx_queue_desc *desc = queue->base + queue->read_idx; -+ -+ if ((event >= HIF_EVENT_MAX) || (qno >= HIF_CLIENT_QUEUES_MAX)) { -+ pr_debug("%s: Unsupported event : %d queue number : %d\n", -+ __func__, event, qno); -+ return -1; -+ } -+ -+ test_and_clear_bit(qno, &client->queue_mask[event]); -+ -+ switch (event) { -+ case EVENT_RX_PKT_IND: -+ if (!(desc->ctrl & CL_DESC_OWN)) -+ hif_lib_indicate_client(client->id, -+ EVENT_RX_PKT_IND, qno); -+ break; -+ -+ case EVENT_HIGH_RX_WM: -+ case EVENT_TXDONE_IND: -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+/* -+ * This function gets one packet from the specified client queue -+ * It also refill the rx buffer -+ */ -+void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int -+ *ofst, unsigned int *rx_ctrl, -+ unsigned int *desc_ctrl, void **priv_data) -+{ -+ struct hif_client_rx_queue *queue = &client->rx_q[qno]; -+ struct rx_queue_desc *desc; -+ void *pkt = NULL; -+ -+ /* -+ * Following lock is to protect rx queue access from, -+ * hif_lib_event_handler_start. -+ * In general below lock is not required, because hif_lib_xmit_pkt and -+ * hif_lib_event_handler_start are called from napi poll and which is -+ * not re-entrant. But if some client use in different way this lock is -+ * required. -+ */ -+ /*spin_lock_irqsave(&client->rx_lock, flags); */ -+ desc = queue->base + queue->read_idx; -+ if (!(desc->ctrl & CL_DESC_OWN)) { -+ pkt = desc->data - pfe_pkt_headroom; -+ -+ *rx_ctrl = desc->client_ctrl; -+ *desc_ctrl = desc->ctrl; -+ -+ if (desc->ctrl & CL_DESC_FIRST) { -+ u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST; -+ -+ if (size) { -+ size += PFE_PARSE_INFO_SIZE; -+ *len = CL_DESC_BUF_LEN(desc->ctrl) - -+ PFE_PKT_HEADER_SZ - size; -+ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ -+ + size; -+ *priv_data = desc->data + PFE_PKT_HEADER_SZ; -+ } else { -+ *len = CL_DESC_BUF_LEN(desc->ctrl) - -+ PFE_PKT_HEADER_SZ - PFE_PARSE_INFO_SIZE; -+ *ofst = pfe_pkt_headroom -+ + PFE_PKT_HEADER_SZ -+ + PFE_PARSE_INFO_SIZE; -+ *priv_data = NULL; -+ } -+ -+ } else { -+ *len = CL_DESC_BUF_LEN(desc->ctrl); -+ *ofst = pfe_pkt_headroom; -+ } -+ -+ /* -+ * Needed so we don't free a buffer/page -+ * twice on module_exit -+ */ -+ desc->data = NULL; -+ -+ /* -+ * Ensure everything else is written to DDR before -+ * writing bd->ctrl -+ */ -+ smp_wmb(); -+ -+ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN; -+ queue->read_idx = (queue->read_idx + 1) & (queue->size - 1); -+ } -+ -+ /*spin_unlock_irqrestore(&client->rx_lock, flags); */ -+ return pkt; -+} -+ -+static inline void hif_hdr_write(struct hif_hdr *pkt_hdr, unsigned int -+ client_id, unsigned int qno, -+ u32 client_ctrl) -+{ -+ /* Optimize the write since the destinaton may be non-cacheable */ -+ if (!((unsigned long)pkt_hdr & 0x3)) { -+ ((u32 *)pkt_hdr)[0] = (client_ctrl << 16) | (qno << 8) | -+ client_id; -+ } else { -+ ((u16 *)pkt_hdr)[0] = (qno << 8) | (client_id & 0xFF); -+ ((u16 *)pkt_hdr)[1] = (client_ctrl & 0xFFFF); -+ } -+} -+ -+/*This function puts the given packet in the specific client queue */ -+void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void -+ *data, unsigned int len, u32 client_ctrl, -+ unsigned int flags, void *client_data) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ struct tx_queue_desc *desc = queue->base + queue->write_idx; -+ -+ /* First buffer */ -+ if (flags & HIF_FIRST_BUFFER) { -+ data -= sizeof(struct hif_hdr); -+ len += sizeof(struct hif_hdr); -+ -+ hif_hdr_write(data, client->id, qno, client_ctrl); -+ } -+ -+ desc->data = client_data; -+ desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(flags); -+ -+ __hif_xmit_pkt(&pfe->hif, client->id, qno, data, len, flags); -+ -+ queue->write_idx = (queue->write_idx + 1) & (queue->size - 1); -+ queue->tx_pending++; -+ queue->jiffies_last_packet = jiffies; -+} -+ -+void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, -+ unsigned int *flags, int count) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ struct tx_queue_desc *desc = queue->base + queue->read_idx; -+ -+ pr_debug("%s: qno : %d rd_indx: %d pending:%d\n", __func__, qno, -+ queue->read_idx, queue->tx_pending); -+ -+ if (!queue->tx_pending) -+ return NULL; -+ -+ if (queue->nocpy_flag && !queue->done_tmu_tx_pkts) { -+ u32 tmu_tx_pkts = be32_to_cpu(pe_dmem_read(TMU0_ID + -+ client->id, TMU_DM_TX_TRANS, 4)); -+ -+ if (queue->prev_tmu_tx_pkts > tmu_tx_pkts) -+ queue->done_tmu_tx_pkts = UINT_MAX - -+ queue->prev_tmu_tx_pkts + tmu_tx_pkts; -+ else -+ queue->done_tmu_tx_pkts = tmu_tx_pkts - -+ queue->prev_tmu_tx_pkts; -+ -+ queue->prev_tmu_tx_pkts = tmu_tx_pkts; -+ -+ if (!queue->done_tmu_tx_pkts) -+ return NULL; -+ } -+ -+ if (desc->ctrl & CL_DESC_OWN) -+ return NULL; -+ -+ queue->read_idx = (queue->read_idx + 1) & (queue->size - 1); -+ queue->tx_pending--; -+ -+ *flags = CL_DESC_GET_FLAGS(desc->ctrl); -+ -+ if (queue->done_tmu_tx_pkts && (*flags & HIF_LAST_BUFFER)) -+ queue->done_tmu_tx_pkts--; -+ -+ return desc->data; -+} -+ -+static void hif_lib_tmu_credit_init(struct pfe *pfe) -+{ -+ int i, q; -+ -+ for (i = 0; i < NUM_GEMAC_SUPPORT; i++) -+ for (q = 0; q < emac_txq_cnt; q++) { -+ pfe->tmu_credit.tx_credit_max[i][q] = (q == 0) ? -+ DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH; -+ pfe->tmu_credit.tx_credit[i][q] = -+ pfe->tmu_credit.tx_credit_max[i][q]; -+ } -+} -+ -+/* __hif_lib_update_credit -+ * -+ * @param[in] client hif client context -+ * @param[in] queue queue number in match with TMU -+ */ -+void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue) -+{ -+ unsigned int tmu_tx_packets, tmp; -+ -+ if (tx_qos) { -+ tmu_tx_packets = be32_to_cpu(pe_dmem_read(TMU0_ID + -+ client->id, (TMU_DM_TX_TRANS + (queue * 4)), 4)); -+ -+ /* tx_packets counter overflowed */ -+ if (tmu_tx_packets > -+ pfe->tmu_credit.tx_packets[client->id][queue]) { -+ tmp = UINT_MAX - tmu_tx_packets + -+ pfe->tmu_credit.tx_packets[client->id][queue]; -+ -+ pfe->tmu_credit.tx_credit[client->id][queue] = -+ pfe->tmu_credit.tx_credit_max[client->id][queue] - tmp; -+ } else { -+ /* TMU tx <= pfe_eth tx, normal case or both OF since -+ * last time -+ */ -+ pfe->tmu_credit.tx_credit[client->id][queue] = -+ pfe->tmu_credit.tx_credit_max[client->id][queue] - -+ (pfe->tmu_credit.tx_packets[client->id][queue] - -+ tmu_tx_packets); -+ } -+ } -+} -+ -+int pfe_hif_lib_init(struct pfe *pfe) -+{ -+ int rc; -+ -+ pr_info("%s\n", __func__); -+ -+ if (lro_mode) { -+ page_mode = 1; -+ pfe_pkt_size = min(PAGE_SIZE, MAX_PFE_PKT_SIZE); -+ pfe_pkt_headroom = 0; -+ } else { -+ page_mode = 0; -+ pfe_pkt_size = PFE_PKT_SIZE; -+ pfe_pkt_headroom = PFE_PKT_HEADROOM; -+ } -+ -+ if (tx_qos) -+ emac_txq_cnt = EMAC_TXQ_CNT / 2; -+ else -+ emac_txq_cnt = EMAC_TXQ_CNT; -+ -+ hif_lib_tmu_credit_init(pfe); -+ pfe->hif.shm = &ghif_shm; -+ rc = pfe_hif_shm_init(pfe->hif.shm); -+ -+ return rc; -+} -+ -+void pfe_hif_lib_exit(struct pfe *pfe) -+{ -+ pr_info("%s\n", __func__); -+ -+ pfe_hif_shm_clean(pfe->hif.shm); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h -@@ -0,0 +1,229 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_HIF_LIB_H_ -+#define _PFE_HIF_LIB_H_ -+ -+#include "pfe_hif.h" -+ -+#define HIF_CL_REQ_TIMEOUT 10 -+#define GFP_DMA_PFE 0 -+#define PFE_PARSE_INFO_SIZE 16 -+ -+enum { -+ REQUEST_CL_REGISTER = 0, -+ REQUEST_CL_UNREGISTER, -+ HIF_REQUEST_MAX -+}; -+ -+enum { -+ /* Event to indicate that client rx queue is reached water mark level */ -+ EVENT_HIGH_RX_WM = 0, -+ /* Event to indicate that, packet received for client */ -+ EVENT_RX_PKT_IND, -+ /* Event to indicate that, packet tx done for client */ -+ EVENT_TXDONE_IND, -+ HIF_EVENT_MAX -+}; -+ -+/*structure to store client queue info */ -+ -+/*structure to store client queue info */ -+struct hif_client_rx_queue { -+ struct rx_queue_desc *base; -+ u32 size; -+ u32 read_idx; -+ u32 write_idx; -+}; -+ -+struct hif_client_tx_queue { -+ struct tx_queue_desc *base; -+ u32 size; -+ u32 read_idx; -+ u32 write_idx; -+ u32 tx_pending; -+ unsigned long jiffies_last_packet; -+ u32 nocpy_flag; -+ u32 prev_tmu_tx_pkts; -+ u32 done_tmu_tx_pkts; -+}; -+ -+struct hif_client_s { -+ int id; -+ int tx_qn; -+ int rx_qn; -+ void *rx_qbase; -+ void *tx_qbase; -+ int tx_qsize; -+ int rx_qsize; -+ int cpu_id; -+ struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX]; -+ struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX]; -+ int (*event_handler)(void *priv, int event, int data); -+ unsigned long queue_mask[HIF_EVENT_MAX]; -+ struct pfe *pfe; -+ void *priv; -+}; -+ -+/* -+ * Client specific shared memory -+ * It contains number of Rx/Tx queues, base addresses and queue sizes -+ */ -+struct hif_client_shm { -+ u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */ -+ unsigned long rx_qbase; /*Rx queue base address */ -+ u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */ -+ unsigned long tx_qbase; /* Tx queue base address */ -+ u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */ -+}; -+ -+/*Client shared memory ctrl bit description */ -+#define CLIENT_CTRL_RX_Q_CNT_OFST 0 -+#define CLIENT_CTRL_TX_Q_CNT_OFST 8 -+#define CLIENT_CTRL_RX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \ -+ & 0xFF) -+#define CLIENT_CTRL_TX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \ -+ & 0xFF) -+ -+/* -+ * Shared memory used to communicate between HIF driver and host/client drivers -+ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be -+ * initialized with host buffers and buffers count in the pool. -+ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT. -+ * -+ */ -+struct hif_shm { -+ u32 rx_buf_pool_cnt; /*Number of rx buffers available*/ -+ /*Rx buffers required to initialize HIF rx descriptors */ -+ void *rx_buf_pool[HIF_RX_DESC_NT]; -+ unsigned long g_client_status[2]; /*Global client status bit mask */ -+ /* Client specific shared memory */ -+ struct hif_client_shm client[HIF_CLIENTS_MAX]; -+}; -+ -+#define CL_DESC_OWN BIT(31) -+/* This sets owner ship to HIF driver */ -+#define CL_DESC_LAST BIT(30) -+/* This indicates last packet for multi buffers handling */ -+#define CL_DESC_FIRST BIT(29) -+/* This indicates first packet for multi buffers handling */ -+ -+#define CL_DESC_BUF_LEN(x) ((x) & 0xFFFF) -+#define CL_DESC_FLAGS(x) (((x) & 0xF) << 16) -+#define CL_DESC_GET_FLAGS(x) (((x) >> 16) & 0xF) -+ -+struct rx_queue_desc { -+ void *data; -+ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ -+ u32 client_ctrl; -+}; -+ -+struct tx_queue_desc { -+ void *data; -+ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/ -+}; -+ -+/* HIF Rx is not working properly for 2-byte aligned buffers and -+ * ip_header should be 4byte aligned for better iperformance. -+ * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned. -+ */ -+#define PFE_PKT_HEADER_SZ sizeof(struct hif_hdr) -+/* must be big enough for headroom, pkt size and skb shared info */ -+#define PFE_BUF_SIZE 2048 -+#define PFE_PKT_HEADROOM 128 -+ -+#define SKB_SHARED_INFO_SIZE SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) -+#define PFE_PKT_SIZE (PFE_BUF_SIZE - PFE_PKT_HEADROOM \ -+ - SKB_SHARED_INFO_SIZE) -+#define MAX_L2_HDR_SIZE 14 /* Not correct for VLAN/PPPoE */ -+#define MAX_L3_HDR_SIZE 20 /* Not correct for IPv6 */ -+#define MAX_L4_HDR_SIZE 60 /* TCP with maximum options */ -+#define MAX_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \ -+ + MAX_L4_HDR_SIZE) -+/* Used in page mode to clamp packet size to the maximum supported by the hif -+ *hw interface (<16KiB) -+ */ -+#define MAX_PFE_PKT_SIZE 16380UL -+ -+extern unsigned int pfe_pkt_size; -+extern unsigned int pfe_pkt_headroom; -+extern unsigned int page_mode; -+extern unsigned int lro_mode; -+extern unsigned int tx_qos; -+extern unsigned int emac_txq_cnt; -+ -+int pfe_hif_lib_init(struct pfe *pfe); -+void pfe_hif_lib_exit(struct pfe *pfe); -+int hif_lib_client_register(struct hif_client_s *client); -+int hif_lib_client_unregister(struct hif_client_s *client); -+void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void -+ *data, unsigned int len, u32 client_ctrl, -+ unsigned int flags, void *client_data); -+int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data, -+ unsigned int len, u32 client_ctrl, void *client_data); -+void hif_lib_indicate_client(int cl_id, int event, int data); -+int hif_lib_event_handler_start(struct hif_client_s *client, int event, int -+ data); -+int hif_lib_tmu_queue_start(struct hif_client_s *client, int qno); -+int hif_lib_tmu_queue_stop(struct hif_client_s *client, int qno); -+void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno, -+ unsigned int *flags, int count); -+void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int -+ *ofst, unsigned int *rx_ctrl, -+ unsigned int *desc_ctrl, void **priv_data); -+void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue); -+void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id); -+void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int -+ enable); -+static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int -+ qno) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ -+ return (queue->size - queue->tx_pending); -+} -+ -+static inline int hif_lib_get_tx_wr_index(struct hif_client_s *client, unsigned -+ int qno) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ -+ return queue->write_idx; -+} -+ -+static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int -+ qno) -+{ -+ struct hif_client_tx_queue *queue = &client->tx_q[qno]; -+ -+ return queue->tx_pending; -+} -+ -+#define hif_lib_tx_credit_avail(pfe, id, qno) \ -+ ((pfe)->tmu_credit.tx_credit[id][qno]) -+ -+#define hif_lib_tx_credit_max(pfe, id, qno) \ -+ ((pfe)->tmu_credit.tx_credit_max[id][qno]) -+ -+/* -+ * Test comment -+ */ -+#define hif_lib_tx_credit_use(pfe, id, qno, credit) \ -+ ({ typeof(pfe) pfe_ = pfe; \ -+ typeof(id) id_ = id; \ -+ typeof(qno) qno_ = qno; \ -+ typeof(credit) credit_ = credit; \ -+ do { \ -+ if (tx_qos) { \ -+ (pfe_)->tmu_credit.tx_credit[id_][qno_]\ -+ -= credit_; \ -+ (pfe_)->tmu_credit.tx_packets[id_][qno_]\ -+ += credit_; \ -+ } \ -+ } while (0); \ -+ }) -+ -+#endif /* _PFE_HIF_LIB_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hw.c -@@ -0,0 +1,164 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include "pfe_mod.h" -+#include "pfe_hw.h" -+ -+/* Functions to handle most of pfe hw register initialization */ -+int pfe_hw_init(struct pfe *pfe, int resume) -+{ -+ struct class_cfg class_cfg = { -+ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, -+ .route_table_baseaddr = pfe->ddr_phys_baseaddr + -+ ROUTE_TABLE_BASEADDR, -+ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS, -+ }; -+ -+ struct tmu_cfg tmu_cfg = { -+ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, -+ .llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR, -+ .llm_queue_len = TMU_LLM_QUEUE_LEN, -+ }; -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ struct util_cfg util_cfg = { -+ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO, -+ }; -+#endif -+ -+ struct BMU_CFG bmu1_cfg = { -+ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + -+ BMU1_LMEM_BASEADDR), -+ .count = BMU1_BUF_COUNT, -+ .size = BMU1_BUF_SIZE, -+ .low_watermark = 10, -+ .high_watermark = 15, -+ }; -+ -+ struct BMU_CFG bmu2_cfg = { -+ .baseaddr = DDR_PHYS_TO_PFE(pfe->ddr_phys_baseaddr + -+ BMU2_DDR_BASEADDR), -+ .count = BMU2_BUF_COUNT, -+ .size = BMU2_BUF_SIZE, -+ .low_watermark = 250, -+ .high_watermark = 253, -+ }; -+ -+ struct gpi_cfg egpi1_cfg = { -+ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT, -+ .tmlf_txthres = EGPI1_TMLF_TXTHRES, -+ .aseq_len = EGPI1_ASEQ_LEN, -+ .mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC1_BASE_ADDR + -+ EMAC_TCNTRL_REG), -+ }; -+ -+ struct gpi_cfg egpi2_cfg = { -+ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT, -+ .tmlf_txthres = EGPI2_TMLF_TXTHRES, -+ .aseq_len = EGPI2_ASEQ_LEN, -+ .mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC2_BASE_ADDR + -+ EMAC_TCNTRL_REG), -+ }; -+ -+ struct gpi_cfg hgpi_cfg = { -+ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT, -+ .tmlf_txthres = HGPI_TMLF_TXTHRES, -+ .aseq_len = HGPI_ASEQ_LEN, -+ .mtip_pause_reg = 0, -+ }; -+ -+ pr_info("%s\n", __func__); -+ -+#if !defined(LS1012A_PFE_RESET_WA) -+ /* LS1012A needs this to make PE work correctly */ -+ writel(0x3, CLASS_PE_SYS_CLK_RATIO); -+ writel(0x3, TMU_PE_SYS_CLK_RATIO); -+ writel(0x3, UTIL_PE_SYS_CLK_RATIO); -+ usleep_range(10, 20); -+#endif -+ -+ pr_info("CLASS version: %x\n", readl(CLASS_VERSION)); -+ pr_info("TMU version: %x\n", readl(TMU_VERSION)); -+ -+ pr_info("BMU1 version: %x\n", readl(BMU1_BASE_ADDR + -+ BMU_VERSION)); -+ pr_info("BMU2 version: %x\n", readl(BMU2_BASE_ADDR + -+ BMU_VERSION)); -+ -+ pr_info("EGPI1 version: %x\n", readl(EGPI1_BASE_ADDR + -+ GPI_VERSION)); -+ pr_info("EGPI2 version: %x\n", readl(EGPI2_BASE_ADDR + -+ GPI_VERSION)); -+ pr_info("HGPI version: %x\n", readl(HGPI_BASE_ADDR + -+ GPI_VERSION)); -+ -+ pr_info("HIF version: %x\n", readl(HIF_VERSION)); -+ pr_info("HIF NOPCY version: %x\n", readl(HIF_NOCPY_VERSION)); -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ pr_info("UTIL version: %x\n", readl(UTIL_VERSION)); -+#endif -+ while (!(readl(TMU_CTRL) & ECC_MEM_INIT_DONE)) -+ ; -+ -+ hif_rx_disable(); -+ hif_tx_disable(); -+ -+ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg); -+ -+ pr_info("bmu_init(1) done\n"); -+ -+ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg); -+ -+ pr_info("bmu_init(2) done\n"); -+ -+ class_cfg.resume = resume ? 1 : 0; -+ -+ class_init(&class_cfg); -+ -+ pr_info("class_init() done\n"); -+ -+ tmu_init(&tmu_cfg); -+ -+ pr_info("tmu_init() done\n"); -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ util_init(&util_cfg); -+ -+ pr_info("util_init() done\n"); -+#endif -+ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg); -+ -+ pr_info("gpi_init(1) done\n"); -+ -+ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg); -+ -+ pr_info("gpi_init(2) done\n"); -+ -+ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg); -+ -+ pr_info("gpi_init(hif) done\n"); -+ -+ bmu_enable(BMU1_BASE_ADDR); -+ -+ pr_info("bmu_enable(1) done\n"); -+ -+ bmu_enable(BMU2_BASE_ADDR); -+ -+ pr_info("bmu_enable(2) done\n"); -+ -+ return 0; -+} -+ -+void pfe_hw_exit(struct pfe *pfe) -+{ -+ pr_info("%s\n", __func__); -+ -+ bmu_disable(BMU1_BASE_ADDR); -+ bmu_reset(BMU1_BASE_ADDR); -+ -+ bmu_disable(BMU2_BASE_ADDR); -+ bmu_reset(BMU2_BASE_ADDR); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_hw.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_HW_H_ -+#define _PFE_HW_H_ -+ -+#define PE_SYS_CLK_RATIO 1 /* SYS/AXI = 250MHz, HFE = 500MHz */ -+ -+int pfe_hw_init(struct pfe *pfe, int resume); -+void pfe_hw_exit(struct pfe *pfe); -+ -+#endif /* _PFE_HW_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c -@@ -0,0 +1,383 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pfe_mod.h" -+ -+extern bool pfe_use_old_dts_phy; -+struct ls1012a_pfe_platform_data pfe_platform_data; -+ -+static int pfe_get_gemac_if_properties(struct device_node *gem, -+ int port, -+ struct ls1012a_pfe_platform_data *pdata) -+{ -+ struct device_node *phy_node = NULL; -+ int size; -+ int phy_id = 0; -+ const u32 *addr; -+ int err; -+ -+ addr = of_get_property(gem, "reg", &size); -+ if (addr) -+ port = be32_to_cpup(addr); -+ else -+ goto err; -+ -+ pdata->ls1012a_eth_pdata[port].gem_id = port; -+ -+ of_get_mac_address(gem, pdata->ls1012a_eth_pdata[port].mac_addr); -+ -+ phy_node = of_parse_phandle(gem, "phy-handle", 0); -+ pdata->ls1012a_eth_pdata[port].phy_node = phy_node; -+ if (phy_node) { -+ pfe_use_old_dts_phy = false; -+ goto process_phynode; -+ } else if (of_phy_is_fixed_link(gem)) { -+ pfe_use_old_dts_phy = false; -+ if (of_phy_register_fixed_link(gem) < 0) { -+ pr_err("broken fixed-link specification\n"); -+ goto err; -+ } -+ phy_node = of_node_get(gem); -+ pdata->ls1012a_eth_pdata[port].phy_node = phy_node; -+ } else if (of_get_property(gem, "fsl,pfe-phy-if-flags", &size)) { -+ pfe_use_old_dts_phy = true; -+ /* Use old dts properties for phy handling */ -+ addr = of_get_property(gem, "fsl,pfe-phy-if-flags", &size); -+ pdata->ls1012a_eth_pdata[port].phy_flags = be32_to_cpup(addr); -+ -+ addr = of_get_property(gem, "fsl,gemac-phy-id", &size); -+ if (!addr) { -+ pr_err("%s:%d Invalid gemac-phy-id....\n", __func__, -+ __LINE__); -+ } else { -+ phy_id = be32_to_cpup(addr); -+ pdata->ls1012a_eth_pdata[port].phy_id = phy_id; -+ pdata->ls1012a_mdio_pdata[0].phy_mask &= ~(1 << phy_id); -+ } -+ -+ /* If PHY is enabled, read mdio properties */ -+ if (pdata->ls1012a_eth_pdata[port].phy_flags & GEMAC_NO_PHY) -+ goto done; -+ -+ } else { -+ pr_info("%s: No PHY or fixed-link\n", __func__); -+ return 0; -+ } -+ -+process_phynode: -+ err = of_get_phy_mode(gem, &pdata->ls1012a_eth_pdata[port].mii_config); -+ if (err) -+ pr_err("%s:%d Incorrect Phy mode....\n", __func__, -+ __LINE__); -+ -+ addr = of_get_property(gem, "fsl,mdio-mux-val", &size); -+ if (!addr) { -+ pr_err("%s: Invalid mdio-mux-val....\n", __func__); -+ } else { -+ phy_id = be32_to_cpup(addr); -+ pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id; -+ } -+ -+ if (pdata->ls1012a_eth_pdata[port].phy_id < 32) -+ pfe->mdio_muxval[pdata->ls1012a_eth_pdata[port].phy_id] = -+ pdata->ls1012a_eth_pdata[port].mdio_muxval; -+ -+ -+ pdata->ls1012a_mdio_pdata[port].irq[0] = PHY_POLL; -+ -+done: -+ return 0; -+ -+err: -+ return -1; -+} -+ -+/* -+ * -+ * pfe_platform_probe - -+ * -+ * -+ */ -+static int pfe_platform_probe(struct platform_device *pdev) -+{ -+ struct resource res; -+ int ii = 0, rc, interface_count = 0, size = 0; -+ const u32 *prop; -+ struct device_node *np, *gem = NULL; -+ struct clk *pfe_clk; -+ -+ np = pdev->dev.of_node; -+ -+ if (!np) { -+ pr_err("Invalid device node\n"); -+ return -EINVAL; -+ } -+ -+ pfe = kzalloc(sizeof(*pfe), GFP_KERNEL); -+ if (!pfe) { -+ rc = -ENOMEM; -+ goto err_alloc; -+ } -+ -+ platform_set_drvdata(pdev, pfe); -+ -+ if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { -+ rc = -ENOMEM; -+ pr_err("unable to configure DMA mask.\n"); -+ goto err_ddr; -+ } -+ -+ if (of_address_to_resource(np, 1, &res)) { -+ rc = -ENOMEM; -+ pr_err("failed to get ddr resource\n"); -+ goto err_ddr; -+ } -+ -+ pfe->ddr_phys_baseaddr = res.start; -+ pfe->ddr_size = resource_size(&res); -+ -+ pfe->ddr_baseaddr = memremap(res.start, resource_size(&res), -+ MEMREMAP_WB); -+ if (!pfe->ddr_baseaddr) { -+ pr_err("memremap() ddr failed\n"); -+ rc = -ENOMEM; -+ goto err_ddr; -+ } -+ -+ pfe->scfg = -+ syscon_regmap_lookup_by_phandle(pdev->dev.of_node, -+ "fsl,pfe-scfg"); -+ if (IS_ERR(pfe->scfg)) { -+ dev_err(&pdev->dev, "No syscfg phandle specified\n"); -+ return PTR_ERR(pfe->scfg); -+ } -+ -+ pfe->cbus_baseaddr = of_iomap(np, 0); -+ if (!pfe->cbus_baseaddr) { -+ rc = -ENOMEM; -+ pr_err("failed to get axi resource\n"); -+ goto err_axi; -+ } -+ -+ pfe->hif_irq = platform_get_irq(pdev, 0); -+ if (pfe->hif_irq < 0) { -+ pr_err("platform_get_irq for hif failed\n"); -+ rc = pfe->hif_irq; -+ goto err_hif_irq; -+ } -+ -+ pfe->wol_irq = platform_get_irq(pdev, 2); -+ if (pfe->wol_irq < 0) { -+ pr_err("platform_get_irq for WoL failed\n"); -+ rc = pfe->wol_irq; -+ goto err_hif_irq; -+ } -+ -+ /* Read interface count */ -+ prop = of_get_property(np, "fsl,pfe-num-interfaces", &size); -+ if (!prop) { -+ pr_err("Failed to read number of interfaces\n"); -+ rc = -ENXIO; -+ goto err_prop; -+ } -+ -+ interface_count = be32_to_cpup(prop); -+ if (interface_count <= 0) { -+ pr_err("No ethernet interface count : %d\n", -+ interface_count); -+ rc = -ENXIO; -+ goto err_prop; -+ } -+ -+ pfe_platform_data.ls1012a_mdio_pdata[0].phy_mask = 0xffffffff; -+ -+ while ((gem = of_get_next_child(np, gem))) { -+ if (of_find_property(gem, "reg", &size)) { -+ pfe_get_gemac_if_properties(gem, ii, -+ &pfe_platform_data); -+ ii++; -+ } -+ } -+ -+ if (interface_count != ii) -+ pr_info("missing some of gemac interface properties.\n"); -+ -+ pfe->dev = &pdev->dev; -+ -+ pfe->dev->platform_data = &pfe_platform_data; -+ -+ /* declare WoL capabilities */ -+ device_init_wakeup(&pdev->dev, true); -+ -+ /* find the clocks */ -+ pfe_clk = devm_clk_get(pfe->dev, "pfe"); -+ if (IS_ERR(pfe_clk)) -+ return PTR_ERR(pfe_clk); -+ -+ /* PFE clock is (platform clock / 2) */ -+ /* save sys_clk value as KHz */ -+ pfe->ctrl.sys_clk = clk_get_rate(pfe_clk) / (2 * 1000); -+ -+ rc = pfe_probe(pfe); -+ if (rc < 0) -+ goto err_probe; -+ -+ return 0; -+ -+err_probe: -+err_prop: -+err_hif_irq: -+ iounmap(pfe->cbus_baseaddr); -+ -+err_axi: -+ memunmap(pfe->ddr_baseaddr); -+ -+err_ddr: -+ platform_set_drvdata(pdev, NULL); -+ -+ kfree(pfe); -+ -+err_alloc: -+ return rc; -+} -+ -+/* -+ * pfe_platform_remove - -+ */ -+static int pfe_platform_remove(struct platform_device *pdev) -+{ -+ struct pfe *pfe = platform_get_drvdata(pdev); -+ int rc; -+ -+ pr_info("%s\n", __func__); -+ -+ rc = pfe_remove(pfe); -+ -+ iounmap(pfe->cbus_baseaddr); -+ -+ memunmap(pfe->ddr_baseaddr); -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ kfree(pfe); -+ -+ return rc; -+} -+ -+#ifdef CONFIG_PM -+#ifdef CONFIG_PM_SLEEP -+int pfe_platform_suspend(struct device *dev) -+{ -+ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev)); -+ struct net_device *netdev; -+ int i; -+ -+ pfe->wake = 0; -+ -+ for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) { -+ netdev = pfe->eth.eth_priv[i]->ndev; -+ -+ netif_device_detach(netdev); -+ -+ if (netif_running(netdev)) -+ if (pfe_eth_suspend(netdev)) -+ pfe->wake = 1; -+ } -+ -+ /* Shutdown PFE only if we're not waking up the system */ -+ if (!pfe->wake) { -+#if defined(LS1012A_PFE_RESET_WA) -+ pfe_hif_rx_idle(&pfe->hif); -+#endif -+ pfe_ctrl_suspend(&pfe->ctrl); -+ pfe_firmware_exit(pfe); -+ -+ pfe_hif_exit(pfe); -+ pfe_hif_lib_exit(pfe); -+ -+ pfe_hw_exit(pfe); -+ } -+ -+ return 0; -+} -+ -+static int pfe_platform_resume(struct device *dev) -+{ -+ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev)); -+ struct net_device *netdev; -+ int i; -+ -+ if (!pfe->wake) { -+ pfe_hw_init(pfe, 1); -+ pfe_hif_lib_init(pfe); -+ pfe_hif_init(pfe); -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ util_enable(); -+#endif -+ tmu_enable(0xf); -+ class_enable(); -+ pfe_ctrl_resume(&pfe->ctrl); -+ } -+ -+ for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) { -+ netdev = pfe->eth.eth_priv[i]->ndev; -+ -+ if (pfe->mdio.mdio_priv[i]->mii_bus) -+ pfe_eth_mdio_reset(pfe->mdio.mdio_priv[i]->mii_bus); -+ -+ if (netif_running(netdev)) -+ pfe_eth_resume(netdev); -+ -+ netif_device_attach(netdev); -+ } -+ return 0; -+} -+#else -+#define pfe_platform_suspend NULL -+#define pfe_platform_resume NULL -+#endif -+ -+static const struct dev_pm_ops pfe_platform_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(pfe_platform_suspend, pfe_platform_resume) -+}; -+#endif -+ -+static const struct of_device_id pfe_match[] = { -+ { -+ .compatible = "fsl,pfe", -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, pfe_match); -+ -+static struct platform_driver pfe_platform_driver = { -+ .probe = pfe_platform_probe, -+ .remove = pfe_platform_remove, -+ .driver = { -+ .name = "pfe", -+ .of_match_table = pfe_match, -+#ifdef CONFIG_PM -+ .pm = &pfe_platform_pm_ops, -+#endif -+ }, -+}; -+ -+module_platform_driver(pfe_platform_driver); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("PFE Ethernet driver"); -+MODULE_AUTHOR("NXP DNCPE"); ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_mod.c -@@ -0,0 +1,158 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include -+#include "pfe_mod.h" -+#include "pfe_cdev.h" -+ -+unsigned int us; -+module_param(us, uint, 0444); -+MODULE_PARM_DESC(us, "0: module enabled for kernel networking (DEFAULT)\n" -+ "1: module enabled for userspace networking\n"); -+struct pfe *pfe; -+ -+/* -+ * pfe_probe - -+ */ -+int pfe_probe(struct pfe *pfe) -+{ -+ int rc; -+ -+ if (pfe->ddr_size < DDR_MAX_SIZE) { -+ pr_err("%s: required DDR memory (%x) above platform ddr memory (%x)\n", -+ __func__, (unsigned int)DDR_MAX_SIZE, pfe->ddr_size); -+ rc = -ENOMEM; -+ goto err_hw; -+ } -+ -+ if (((int)(pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR) & -+ (8 * SZ_1M - 1)) != 0) { -+ pr_err("%s: BMU2 base address (0x%x) must be aligned on 8MB boundary\n", -+ __func__, (int)pfe->ddr_phys_baseaddr + -+ BMU2_DDR_BASEADDR); -+ rc = -ENOMEM; -+ goto err_hw; -+ } -+ -+ pr_info("cbus_baseaddr: %lx, ddr_baseaddr: %lx, ddr_phys_baseaddr: %lx, ddr_size: %x\n", -+ (unsigned long)pfe->cbus_baseaddr, -+ (unsigned long)pfe->ddr_baseaddr, -+ pfe->ddr_phys_baseaddr, pfe->ddr_size); -+ -+ pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr, -+ pfe->ddr_phys_baseaddr, pfe->ddr_size); -+ -+ rc = pfe_hw_init(pfe, 0); -+ if (rc < 0) -+ goto err_hw; -+ -+ if (us) -+ goto firmware_init; -+ -+ rc = pfe_hif_lib_init(pfe); -+ if (rc < 0) -+ goto err_hif_lib; -+ -+ rc = pfe_hif_init(pfe); -+ if (rc < 0) -+ goto err_hif; -+ -+firmware_init: -+ rc = pfe_firmware_init(pfe); -+ if (rc < 0) -+ goto err_firmware; -+ -+ rc = pfe_ctrl_init(pfe); -+ if (rc < 0) -+ goto err_ctrl; -+ -+ rc = pfe_eth_init(pfe); -+ if (rc < 0) -+ goto err_eth; -+ -+ rc = pfe_sysfs_init(pfe); -+ if (rc < 0) -+ goto err_sysfs; -+ -+ rc = pfe_debugfs_init(pfe); -+ if (rc < 0) -+ goto err_debugfs; -+ -+ if (us) { -+ /* Creating a character device */ -+ rc = pfe_cdev_init(); -+ if (rc < 0) -+ goto err_cdev; -+ } -+ -+ return 0; -+ -+err_cdev: -+ pfe_debugfs_exit(pfe); -+ -+err_debugfs: -+ pfe_sysfs_exit(pfe); -+ -+err_sysfs: -+ pfe_eth_exit(pfe); -+ -+err_eth: -+ pfe_ctrl_exit(pfe); -+ -+err_ctrl: -+ pfe_firmware_exit(pfe); -+ -+err_firmware: -+ if (us) -+ goto err_hif_lib; -+ -+ pfe_hif_exit(pfe); -+ -+err_hif: -+ pfe_hif_lib_exit(pfe); -+ -+err_hif_lib: -+ pfe_hw_exit(pfe); -+ -+err_hw: -+ return rc; -+} -+ -+/* -+ * pfe_remove - -+ */ -+int pfe_remove(struct pfe *pfe) -+{ -+ pr_info("%s\n", __func__); -+ -+ if (us) -+ pfe_cdev_exit(); -+ -+ pfe_debugfs_exit(pfe); -+ -+ pfe_sysfs_exit(pfe); -+ -+ pfe_eth_exit(pfe); -+ -+ pfe_ctrl_exit(pfe); -+ -+#if defined(LS1012A_PFE_RESET_WA) -+ pfe_hif_rx_idle(&pfe->hif); -+#endif -+ pfe_firmware_exit(pfe); -+ -+ if (us) -+ goto hw_exit; -+ -+ pfe_hif_exit(pfe); -+ -+ pfe_hif_lib_exit(pfe); -+ -+hw_exit: -+ pfe_hw_exit(pfe); -+ -+ return 0; -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_mod.h -@@ -0,0 +1,103 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_MOD_H_ -+#define _PFE_MOD_H_ -+ -+#include -+#include -+ -+extern unsigned int us; -+ -+struct pfe; -+ -+#include "pfe_hw.h" -+#include "pfe_firmware.h" -+#include "pfe_ctrl.h" -+#include "pfe_hif.h" -+#include "pfe_hif_lib.h" -+#include "pfe_eth.h" -+#include "pfe_sysfs.h" -+#include "pfe_perfmon.h" -+#include "pfe_debugfs.h" -+ -+#define PHYID_MAX_VAL 32 -+ -+struct pfe_tmu_credit { -+ /* Number of allowed TX packet in-flight, matches TMU queue size */ -+ unsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; -+ unsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; -+ unsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT]; -+}; -+ -+struct pfe { -+ struct regmap *scfg; -+ unsigned long ddr_phys_baseaddr; -+ void *ddr_baseaddr; -+ unsigned int ddr_size; -+ void *cbus_baseaddr; -+ void *apb_baseaddr; -+ unsigned long iram_phys_baseaddr; -+ void *iram_baseaddr; -+ unsigned long ipsec_phys_baseaddr; -+ void *ipsec_baseaddr; -+ int hif_irq; -+ int wol_irq; -+ int hif_client_irq; -+ struct device *dev; -+ struct dentry *dentry; -+ struct pfe_ctrl ctrl; -+ struct pfe_hif hif; -+ struct pfe_eth eth; -+ struct pfe_mdio mdio; -+ struct hif_client_s *hif_client[HIF_CLIENTS_MAX]; -+#if defined(CFG_DIAGS) -+ struct pfe_diags diags; -+#endif -+ struct pfe_tmu_credit tmu_credit; -+ struct pfe_cpumon cpumon; -+ struct pfe_memmon memmon; -+ int wake; -+ int mdio_muxval[PHYID_MAX_VAL]; -+ struct clk *hfe_clock; -+}; -+ -+extern struct pfe *pfe; -+ -+int pfe_probe(struct pfe *pfe); -+int pfe_remove(struct pfe *pfe); -+ -+/* DDR Mapping in reserved memory*/ -+#define ROUTE_TABLE_BASEADDR 0 -+#define ROUTE_TABLE_HASH_BITS 15 /* 32K entries */ -+#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) \ -+ * CLASS_ROUTE_SIZE) -+#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE) -+#define BMU2_BUF_COUNT (4096 - 256) -+/* This is to get a total DDR size of 12MiB */ -+#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT) -+#define UTIL_CODE_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE) -+#define UTIL_CODE_SIZE (128 * SZ_1K) -+#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE) -+#define UTIL_DDR_DATA_SIZE (64 * SZ_1K) -+#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE) -+#define CLASS_DDR_DATA_SIZE (32 * SZ_1K) -+#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE) -+#define TMU_DDR_DATA_SIZE (32 * SZ_1K) -+#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE) -+#define TMU_LLM_QUEUE_LEN (8 * 512) -+/* Must be power of two and at least 16 * 8 = 128 bytes */ -+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN) -+/* (4 TMU's x 16 queues x queue_len) */ -+ -+#define DDR_MAX_SIZE (TMU_LLM_BASEADDR + TMU_LLM_SIZE) -+ -+/* LMEM Mapping */ -+#define BMU1_LMEM_BASEADDR 0 -+#define BMU1_BUF_COUNT 256 -+#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT) -+ -+#endif /* _PFE_MOD_H */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h -@@ -0,0 +1,26 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_PERFMON_H_ -+#define _PFE_PERFMON_H_ -+ -+#include "pfe/pfe.h" -+ -+#define CT_CPUMON_INTERVAL (1 * TIMER_TICKS_PER_SEC) -+ -+struct pfe_cpumon { -+ u32 cpu_usage_pct[MAX_PE]; -+ u32 class_usage_pct; -+}; -+ -+struct pfe_memmon { -+ u32 kernel_memory_allocated; -+}; -+ -+int pfe_perfmon_init(struct pfe *pfe); -+void pfe_perfmon_exit(struct pfe *pfe); -+ -+#endif /* _PFE_PERFMON_H_ */ ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c -@@ -0,0 +1,840 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#include -+#include -+ -+#include "pfe_mod.h" -+ -+#define PE_EXCEPTION_DUMP_ADDRESS 0x1fa8 -+#define NUM_QUEUES 16 -+ -+static char register_name[20][5] = { -+ "EPC", "ECAS", "EID", "ED", -+ "r0", "r1", "r2", "r3", -+ "r4", "r5", "r6", "r7", -+ "r8", "r9", "r10", "r11", -+ "r12", "r13", "r14", "r15", -+}; -+ -+static char exception_name[14][20] = { -+ "Reset", -+ "HardwareFailure", -+ "NMI", -+ "InstBreakpoint", -+ "DataBreakpoint", -+ "Unsupported", -+ "PrivilegeViolation", -+ "InstBusError", -+ "DataBusError", -+ "AlignmentError", -+ "ArithmeticError", -+ "SystemCall", -+ "MemoryManagement", -+ "Interrupt", -+}; -+ -+static unsigned long class_do_clear; -+static unsigned long tmu_do_clear; -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+static unsigned long util_do_clear; -+#endif -+ -+static ssize_t display_pe_status(char *buf, int id, u32 dmem_addr, unsigned long -+ do_clear) -+{ -+ ssize_t len = 0; -+ u32 val; -+ char statebuf[5]; -+ struct pfe_cpumon *cpumon = &pfe->cpumon; -+ u32 debug_indicator; -+ u32 debug[20]; -+ -+ if (id < CLASS0_ID || id >= MAX_PE) -+ return len; -+ -+ *(u32 *)statebuf = pe_dmem_read(id, dmem_addr, 4); -+ dmem_addr += 4; -+ -+ statebuf[4] = '\0'; -+ len += sprintf(buf + len, "state=%4s ", statebuf); -+ -+ val = pe_dmem_read(id, dmem_addr, 4); -+ dmem_addr += 4; -+ len += sprintf(buf + len, "ctr=%08x ", cpu_to_be32(val)); -+ -+ val = pe_dmem_read(id, dmem_addr, 4); -+ if (do_clear && val) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ dmem_addr += 4; -+ len += sprintf(buf + len, "rx=%u ", cpu_to_be32(val)); -+ -+ val = pe_dmem_read(id, dmem_addr, 4); -+ if (do_clear && val) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ dmem_addr += 4; -+ if (id >= TMU0_ID && id <= TMU_MAX_ID) -+ len += sprintf(buf + len, "qstatus=%x", cpu_to_be32(val)); -+ else -+ len += sprintf(buf + len, "tx=%u", cpu_to_be32(val)); -+ -+ val = pe_dmem_read(id, dmem_addr, 4); -+ if (do_clear && val) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ dmem_addr += 4; -+ if (val) -+ len += sprintf(buf + len, " drop=%u", cpu_to_be32(val)); -+ -+ len += sprintf(buf + len, " load=%d%%", cpumon->cpu_usage_pct[id]); -+ -+ len += sprintf(buf + len, "\n"); -+ -+ debug_indicator = pe_dmem_read(id, dmem_addr, 4); -+ dmem_addr += 4; -+ if (!strncmp((char *)&debug_indicator, "DBUG", 4)) { -+ int j, last = 0; -+ -+ for (j = 0; j < 16; j++) { -+ debug[j] = pe_dmem_read(id, dmem_addr, 4); -+ if (debug[j]) { -+ if (do_clear) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ last = j + 1; -+ } -+ dmem_addr += 4; -+ } -+ for (j = 0; j < last; j++) { -+ len += sprintf(buf + len, "%08x%s", -+ cpu_to_be32(debug[j]), -+ (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " "); -+ } -+ } -+ -+ if (!strncmp(statebuf, "DEAD", 4)) { -+ u32 i, dump = PE_EXCEPTION_DUMP_ADDRESS; -+ -+ len += sprintf(buf + len, "Exception details:\n"); -+ for (i = 0; i < 20; i++) { -+ debug[i] = pe_dmem_read(id, dump, 4); -+ dump += 4; -+ if (i == 2) -+ len += sprintf(buf + len, "%4s = %08x (=%s) ", -+ register_name[i], cpu_to_be32(debug[i]), -+ exception_name[min((u32) -+ cpu_to_be32(debug[i]), (u32)13)]); -+ else -+ len += sprintf(buf + len, "%4s = %08x%s", -+ register_name[i], cpu_to_be32(debug[i]), -+ (i & 0x3) == 0x3 || i == 19 ? "\n" : " "); -+ } -+ } -+ -+ return len; -+} -+ -+static ssize_t class_phy_stats(char *buf, int phy) -+{ -+ ssize_t len = 0; -+ int off1 = phy * 0x28; -+ int off2 = phy * 0x10; -+ -+ if (phy == 3) -+ off1 = CLASS_PHY4_RX_PKTS - CLASS_PHY1_RX_PKTS; -+ -+ len += sprintf(buf + len, "phy: %d\n", phy); -+ len += sprintf(buf + len, -+ " rx: %10u, tx: %10u, intf: %10u, ipv4: %10u, ipv6: %10u\n", -+ readl(CLASS_PHY1_RX_PKTS + off1), -+ readl(CLASS_PHY1_TX_PKTS + off1), -+ readl(CLASS_PHY1_INTF_MATCH_PKTS + off1), -+ readl(CLASS_PHY1_V4_PKTS + off1), -+ readl(CLASS_PHY1_V6_PKTS + off1)); -+ -+ len += sprintf(buf + len, -+ " icmp: %10u, igmp: %10u, tcp: %10u, udp: %10u\n", -+ readl(CLASS_PHY1_ICMP_PKTS + off2), -+ readl(CLASS_PHY1_IGMP_PKTS + off2), -+ readl(CLASS_PHY1_TCP_PKTS + off2), -+ readl(CLASS_PHY1_UDP_PKTS + off2)); -+ -+ len += sprintf(buf + len, " err\n"); -+ len += sprintf(buf + len, -+ " lp: %10u, intf: %10u, l3: %10u, chcksum: %10u, ttl: %10u\n", -+ readl(CLASS_PHY1_LP_FAIL_PKTS + off1), -+ readl(CLASS_PHY1_INTF_FAIL_PKTS + off1), -+ readl(CLASS_PHY1_L3_FAIL_PKTS + off1), -+ readl(CLASS_PHY1_CHKSUM_ERR_PKTS + off1), -+ readl(CLASS_PHY1_TTL_ERR_PKTS + off1)); -+ -+ return len; -+} -+ -+/* qm_read_drop_stat -+ * This function is used to read the drop statistics from the TMU -+ * hw drop counter. Since the hw counter is always cleared afer -+ * reading, this function maintains the previous drop count, and -+ * adds the new value to it. That value can be retrieved by -+ * passing a pointer to it with the total_drops arg. -+ * -+ * @param tmu TMU number (0 - 3) -+ * @param queue queue number (0 - 15) -+ * @param total_drops pointer to location to store total drops (or NULL) -+ * @param do_reset if TRUE, clear total drops after updating -+ */ -+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset) -+{ -+ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES]; -+ u32 val; -+ -+ writel((tmu << 8) | queue, TMU_TEQ_CTRL); -+ writel((tmu << 8) | queue, TMU_LLM_CTRL); -+ val = readl(TMU_TEQ_DROP_STAT); -+ qtotal[tmu][queue] += val; -+ if (total_drops) -+ *total_drops = qtotal[tmu][queue]; -+ if (do_reset) -+ qtotal[tmu][queue] = 0; -+ return val; -+} -+ -+static ssize_t tmu_queue_stats(char *buf, int tmu, int queue) -+{ -+ ssize_t len = 0; -+ u32 drops; -+ -+ len += sprintf(buf + len, "%d-%02d, ", tmu, queue); -+ -+ drops = qm_read_drop_stat(tmu, queue, NULL, 0); -+ -+ /* Select queue */ -+ writel((tmu << 8) | queue, TMU_TEQ_CTRL); -+ writel((tmu << 8) | queue, TMU_LLM_CTRL); -+ -+ len += sprintf(buf + len, -+ "(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n", -+ drops, readl(TMU_TEQ_TRANS_STAT), -+ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR), -+ readl(TMU_LLM_QUE_DROPCNT)); -+ -+ return len; -+} -+ -+static ssize_t tmu_queues(char *buf, int tmu) -+{ -+ ssize_t len = 0; -+ int queue; -+ -+ for (queue = 0; queue < 16; queue++) -+ len += tmu_queue_stats(buf + len, tmu, queue); -+ -+ return len; -+} -+ -+static ssize_t block_version(char *buf, void *addr) -+{ -+ ssize_t len = 0; -+ u32 val; -+ -+ val = readl(addr); -+ len += sprintf(buf + len, "revision: %x, version: %x, id: %x\n", -+ (val >> 24) & 0xff, (val >> 16) & 0xff, val & 0xffff); -+ -+ return len; -+} -+ -+static ssize_t bmu(char *buf, int id, void *base) -+{ -+ ssize_t len = 0; -+ -+ len += sprintf(buf + len, "%s: %d\n ", __func__, id); -+ -+ len += block_version(buf + len, base + BMU_VERSION); -+ -+ len += sprintf(buf + len, " buf size: %x\n", (1 << readl(base + -+ BMU_BUF_SIZE))); -+ len += sprintf(buf + len, " buf count: %x\n", readl(base + -+ BMU_BUF_CNT)); -+ len += sprintf(buf + len, " buf rem: %x\n", readl(base + -+ BMU_REM_BUF_CNT)); -+ len += sprintf(buf + len, " buf curr: %x\n", readl(base + -+ BMU_CURR_BUF_CNT)); -+ len += sprintf(buf + len, " free err: %x\n", readl(base + -+ BMU_FREE_ERR_ADDR)); -+ -+ return len; -+} -+ -+static ssize_t gpi(char *buf, int id, void *base) -+{ -+ ssize_t len = 0; -+ u32 val; -+ -+ len += sprintf(buf + len, "%s%d:\n ", __func__, id); -+ len += block_version(buf + len, base + GPI_VERSION); -+ -+ len += sprintf(buf + len, " tx under stick: %x\n", readl(base + -+ GPI_FIFO_STATUS)); -+ val = readl(base + GPI_FIFO_DEBUG); -+ len += sprintf(buf + len, " tx pkts: %x\n", (val >> 23) & -+ 0x3f); -+ len += sprintf(buf + len, " rx pkts: %x\n", (val >> 18) & -+ 0x3f); -+ len += sprintf(buf + len, " tx bytes: %x\n", (val >> 9) & -+ 0x1ff); -+ len += sprintf(buf + len, " rx bytes: %x\n", (val >> 0) & -+ 0x1ff); -+ len += sprintf(buf + len, " overrun: %x\n", readl(base + -+ GPI_OVERRUN_DROPCNT)); -+ -+ return len; -+} -+ -+static ssize_t pfe_set_class(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ class_do_clear = kstrtoul(buf, 0, 0); -+ return count; -+} -+ -+static ssize_t pfe_show_class(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ ssize_t len = 0; -+ int id; -+ u32 val; -+ struct pfe_cpumon *cpumon = &pfe->cpumon; -+ -+ len += block_version(buf + len, CLASS_VERSION); -+ -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { -+ len += sprintf(buf + len, "%d: ", id - CLASS0_ID); -+ -+ val = readl(CLASS_PE0_DEBUG + id * 4); -+ len += sprintf(buf + len, "pc=1%04x ", val & 0xffff); -+ -+ len += display_pe_status(buf + len, id, CLASS_DM_PESTATUS, -+ class_do_clear); -+ } -+ len += sprintf(buf + len, "aggregate load=%d%%\n\n", -+ cpumon->class_usage_pct); -+ -+ len += sprintf(buf + len, "pe status: 0x%x\n", -+ readl(CLASS_PE_STATUS)); -+ len += sprintf(buf + len, "max buf cnt: 0x%x afull thres: 0x%x\n", -+ readl(CLASS_MAX_BUF_CNT), readl(CLASS_AFULL_THRES)); -+ len += sprintf(buf + len, "tsq max cnt: 0x%x tsq fifo thres: 0x%x\n", -+ readl(CLASS_TSQ_MAX_CNT), readl(CLASS_TSQ_FIFO_THRES)); -+ len += sprintf(buf + len, "state: 0x%x\n", readl(CLASS_STATE)); -+ -+ len += class_phy_stats(buf + len, 0); -+ len += class_phy_stats(buf + len, 1); -+ len += class_phy_stats(buf + len, 2); -+ len += class_phy_stats(buf + len, 3); -+ -+ return len; -+} -+ -+static ssize_t pfe_set_tmu(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ tmu_do_clear = kstrtoul(buf, 0, 0); -+ return count; -+} -+ -+static ssize_t pfe_show_tmu(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ ssize_t len = 0; -+ int id; -+ u32 val; -+ -+ len += block_version(buf + len, TMU_VERSION); -+ -+ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) { -+ if (id == TMU2_ID) -+ continue; -+ len += sprintf(buf + len, "%d: ", id - TMU0_ID); -+ -+ len += display_pe_status(buf + len, id, TMU_DM_PESTATUS, -+ tmu_do_clear); -+ } -+ -+ len += sprintf(buf + len, "pe status: %x\n", readl(TMU_PE_STATUS)); -+ len += sprintf(buf + len, "inq fifo cnt: %x\n", -+ readl(TMU_PHY_INQ_FIFO_CNT)); -+ val = readl(TMU_INQ_STAT); -+ len += sprintf(buf + len, "inq wr ptr: %x\n", val & 0x3ff); -+ len += sprintf(buf + len, "inq rd ptr: %x\n", val >> 10); -+ -+ return len; -+} -+ -+static unsigned long drops_do_clear; -+static u32 class_drop_counter[CLASS_NUM_DROP_COUNTERS]; -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+static u32 util_drop_counter[UTIL_NUM_DROP_COUNTERS]; -+#endif -+ -+char *class_drop_description[CLASS_NUM_DROP_COUNTERS] = { -+ "ICC", -+ "Host Pkt Error", -+ "Rx Error", -+ "IPsec Outbound", -+ "IPsec Inbound", -+ "EXPT IPsec Error", -+ "Reassembly", -+ "Fragmenter", -+ "NAT-T", -+ "Socket", -+ "Multicast", -+ "NAT-PT", -+ "Tx Disabled", -+}; -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+char *util_drop_description[UTIL_NUM_DROP_COUNTERS] = { -+ "IPsec Outbound", -+ "IPsec Inbound", -+ "IPsec Rate Limiter", -+ "Fragmenter", -+ "Socket", -+ "Tx Disabled", -+ "Rx Error", -+}; -+#endif -+ -+static ssize_t pfe_set_drops(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ drops_do_clear = kstrtoul(buf, 0, 0); -+ return count; -+} -+ -+static u32 tmu_drops[4][16]; -+static ssize_t pfe_show_drops(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ ssize_t len = 0; -+ int id, dropnum; -+ int tmu, queue; -+ u32 val; -+ u32 dmem_addr; -+ int num_class_drops = 0, num_tmu_drops = 0, num_util_drops = 0; -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ memset(class_drop_counter, 0, sizeof(class_drop_counter)); -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { -+ if (drops_do_clear) -+ pe_sync_stop(ctrl, (1 << id)); -+ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; -+ dropnum++) { -+ dmem_addr = CLASS_DM_DROP_CNTR; -+ val = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4)); -+ class_drop_counter[dropnum] += val; -+ num_class_drops += val; -+ if (drops_do_clear) -+ pe_dmem_write(id, 0, dmem_addr, 4); -+ } -+ if (drops_do_clear) -+ pe_start(ctrl, (1 << id)); -+ } -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ if (drops_do_clear) -+ pe_sync_stop(ctrl, (1 << UTIL_ID)); -+ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) { -+ dmem_addr = UTIL_DM_DROP_CNTR; -+ val = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4)); -+ util_drop_counter[dropnum] = val; -+ num_util_drops += val; -+ if (drops_do_clear) -+ pe_dmem_write(UTIL_ID, 0, dmem_addr, 4); -+ } -+ if (drops_do_clear) -+ pe_start(ctrl, (1 << UTIL_ID)); -+#endif -+ for (tmu = 0; tmu < 4; tmu++) { -+ for (queue = 0; queue < 16; queue++) { -+ qm_read_drop_stat(tmu, queue, &tmu_drops[tmu][queue], -+ drops_do_clear); -+ num_tmu_drops += tmu_drops[tmu][queue]; -+ } -+ } -+ -+ if (num_class_drops == 0 && num_util_drops == 0 && num_tmu_drops == 0) -+ len += sprintf(buf + len, "No PE drops\n\n"); -+ -+ if (num_class_drops > 0) { -+ len += sprintf(buf + len, "Class PE drops --\n"); -+ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS; -+ dropnum++) { -+ if (class_drop_counter[dropnum] > 0) -+ len += sprintf(buf + len, " %s: %d\n", -+ class_drop_description[dropnum], -+ class_drop_counter[dropnum]); -+ } -+ len += sprintf(buf + len, "\n"); -+ } -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ if (num_util_drops > 0) { -+ len += sprintf(buf + len, "Util PE drops --\n"); -+ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) { -+ if (util_drop_counter[dropnum] > 0) -+ len += sprintf(buf + len, " %s: %d\n", -+ util_drop_description[dropnum], -+ util_drop_counter[dropnum]); -+ } -+ len += sprintf(buf + len, "\n"); -+ } -+#endif -+ if (num_tmu_drops > 0) { -+ len += sprintf(buf + len, "TMU drops --\n"); -+ for (tmu = 0; tmu < 4; tmu++) { -+ for (queue = 0; queue < 16; queue++) { -+ if (tmu_drops[tmu][queue] > 0) -+ len += sprintf(buf + len, -+ " TMU%d-Q%d: %d\n" -+ , tmu, queue, tmu_drops[tmu][queue]); -+ } -+ } -+ len += sprintf(buf + len, "\n"); -+ } -+ -+ return len; -+} -+ -+static ssize_t pfe_show_tmu0_queues(struct device *dev, struct device_attribute -+ *attr, char *buf) -+{ -+ return tmu_queues(buf, 0); -+} -+ -+static ssize_t pfe_show_tmu1_queues(struct device *dev, struct device_attribute -+ *attr, char *buf) -+{ -+ return tmu_queues(buf, 1); -+} -+ -+static ssize_t pfe_show_tmu2_queues(struct device *dev, struct device_attribute -+ *attr, char *buf) -+{ -+ return tmu_queues(buf, 2); -+} -+ -+static ssize_t pfe_show_tmu3_queues(struct device *dev, struct device_attribute -+ *attr, char *buf) -+{ -+ return tmu_queues(buf, 3); -+} -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ util_do_clear = kstrtoul(buf, NULL, 0); -+ return count; -+} -+ -+static ssize_t pfe_show_util(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ ssize_t len = 0; -+ struct pfe_ctrl *ctrl = &pfe->ctrl; -+ -+ len += block_version(buf + len, UTIL_VERSION); -+ -+ pe_sync_stop(ctrl, (1 << UTIL_ID)); -+ len += display_pe_status(buf + len, UTIL_ID, UTIL_DM_PESTATUS, -+ util_do_clear); -+ pe_start(ctrl, (1 << UTIL_ID)); -+ -+ len += sprintf(buf + len, "pe status: %x\n", readl(UTIL_PE_STATUS)); -+ len += sprintf(buf + len, "max buf cnt: %x\n", -+ readl(UTIL_MAX_BUF_CNT)); -+ len += sprintf(buf + len, "tsq max cnt: %x\n", -+ readl(UTIL_TSQ_MAX_CNT)); -+ -+ return len; -+} -+#endif -+ -+static ssize_t pfe_show_bmu(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ ssize_t len = 0; -+ -+ len += bmu(buf + len, 1, BMU1_BASE_ADDR); -+ len += bmu(buf + len, 2, BMU2_BASE_ADDR); -+ -+ return len; -+} -+ -+static ssize_t pfe_show_hif(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ ssize_t len = 0; -+ -+ len += sprintf(buf + len, "hif:\n "); -+ len += block_version(buf + len, HIF_VERSION); -+ -+ len += sprintf(buf + len, " tx curr bd: %x\n", -+ readl(HIF_TX_CURR_BD_ADDR)); -+ len += sprintf(buf + len, " tx status: %x\n", -+ readl(HIF_TX_STATUS)); -+ len += sprintf(buf + len, " tx dma status: %x\n", -+ readl(HIF_TX_DMA_STATUS)); -+ -+ len += sprintf(buf + len, " rx curr bd: %x\n", -+ readl(HIF_RX_CURR_BD_ADDR)); -+ len += sprintf(buf + len, " rx status: %x\n", -+ readl(HIF_RX_STATUS)); -+ len += sprintf(buf + len, " rx dma status: %x\n", -+ readl(HIF_RX_DMA_STATUS)); -+ -+ len += sprintf(buf + len, "hif nocopy:\n "); -+ len += block_version(buf + len, HIF_NOCPY_VERSION); -+ -+ len += sprintf(buf + len, " tx curr bd: %x\n", -+ readl(HIF_NOCPY_TX_CURR_BD_ADDR)); -+ len += sprintf(buf + len, " tx status: %x\n", -+ readl(HIF_NOCPY_TX_STATUS)); -+ len += sprintf(buf + len, " tx dma status: %x\n", -+ readl(HIF_NOCPY_TX_DMA_STATUS)); -+ -+ len += sprintf(buf + len, " rx curr bd: %x\n", -+ readl(HIF_NOCPY_RX_CURR_BD_ADDR)); -+ len += sprintf(buf + len, " rx status: %x\n", -+ readl(HIF_NOCPY_RX_STATUS)); -+ len += sprintf(buf + len, " rx dma status: %x\n", -+ readl(HIF_NOCPY_RX_DMA_STATUS)); -+ -+ return len; -+} -+ -+static ssize_t pfe_show_gpi(struct device *dev, struct device_attribute *attr, -+ char *buf) -+{ -+ ssize_t len = 0; -+ -+ len += gpi(buf + len, 0, EGPI1_BASE_ADDR); -+ len += gpi(buf + len, 1, EGPI2_BASE_ADDR); -+ len += gpi(buf + len, 3, HGPI_BASE_ADDR); -+ -+ return len; -+} -+ -+static ssize_t pfe_show_pfemem(struct device *dev, struct device_attribute -+ *attr, char *buf) -+{ -+ ssize_t len = 0; -+ struct pfe_memmon *memmon = &pfe->memmon; -+ -+ len += sprintf(buf + len, "Kernel Memory: %d Bytes (%d KB)\n", -+ memmon->kernel_memory_allocated, -+ (memmon->kernel_memory_allocated + 1023) / 1024); -+ -+ return len; -+} -+ -+static ssize_t pfe_show_crc_revalidated(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ u64 crc_validated = 0; -+ ssize_t len = 0; -+ int id, phyid; -+ -+ len += sprintf(buf + len, "FCS re-validated by PFE:\n"); -+ -+ for (phyid = 0; phyid < 2; phyid++) { -+ crc_validated = 0; -+ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) { -+ crc_validated += be32_to_cpu(pe_dmem_read(id, -+ CLASS_DM_CRC_VALIDATED + (phyid * 4), 4)); -+ } -+ len += sprintf(buf + len, "MAC %d:\n count:%10llu\n", -+ phyid, crc_validated); -+ } -+ -+ return len; -+} -+ -+#ifdef HIF_NAPI_STATS -+static ssize_t pfe_show_hif_napi_stats(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct pfe *pfe = platform_get_drvdata(pdev); -+ ssize_t len = 0; -+ -+ len += sprintf(buf + len, "sched: %u\n", -+ pfe->hif.napi_counters[NAPI_SCHED_COUNT]); -+ len += sprintf(buf + len, "poll: %u\n", -+ pfe->hif.napi_counters[NAPI_POLL_COUNT]); -+ len += sprintf(buf + len, "packet: %u\n", -+ pfe->hif.napi_counters[NAPI_PACKET_COUNT]); -+ len += sprintf(buf + len, "budget: %u\n", -+ pfe->hif.napi_counters[NAPI_FULL_BUDGET_COUNT]); -+ len += sprintf(buf + len, "desc: %u\n", -+ pfe->hif.napi_counters[NAPI_DESC_COUNT]); -+ len += sprintf(buf + len, "full: %u\n", -+ pfe->hif.napi_counters[NAPI_CLIENT_FULL_COUNT]); -+ -+ return len; -+} -+ -+static ssize_t pfe_set_hif_napi_stats(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct pfe *pfe = platform_get_drvdata(pdev); -+ -+ memset(pfe->hif.napi_counters, 0, sizeof(pfe->hif.napi_counters)); -+ -+ return count; -+} -+ -+static DEVICE_ATTR(hif_napi_stats, 0644, pfe_show_hif_napi_stats, -+ pfe_set_hif_napi_stats); -+#endif -+ -+static DEVICE_ATTR(class, 0644, pfe_show_class, pfe_set_class); -+static DEVICE_ATTR(tmu, 0644, pfe_show_tmu, pfe_set_tmu); -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+static DEVICE_ATTR(util, 0644, pfe_show_util, pfe_set_util); -+#endif -+static DEVICE_ATTR(bmu, 0444, pfe_show_bmu, NULL); -+static DEVICE_ATTR(hif, 0444, pfe_show_hif, NULL); -+static DEVICE_ATTR(gpi, 0444, pfe_show_gpi, NULL); -+static DEVICE_ATTR(drops, 0644, pfe_show_drops, pfe_set_drops); -+static DEVICE_ATTR(tmu0_queues, 0444, pfe_show_tmu0_queues, NULL); -+static DEVICE_ATTR(tmu1_queues, 0444, pfe_show_tmu1_queues, NULL); -+static DEVICE_ATTR(tmu2_queues, 0444, pfe_show_tmu2_queues, NULL); -+static DEVICE_ATTR(tmu3_queues, 0444, pfe_show_tmu3_queues, NULL); -+static DEVICE_ATTR(pfemem, 0444, pfe_show_pfemem, NULL); -+static DEVICE_ATTR(fcs_revalidated, 0444, pfe_show_crc_revalidated, NULL); -+ -+int pfe_sysfs_init(struct pfe *pfe) -+{ -+ if (device_create_file(pfe->dev, &dev_attr_class)) -+ goto err_class; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu)) -+ goto err_tmu; -+ -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ if (device_create_file(pfe->dev, &dev_attr_util)) -+ goto err_util; -+#endif -+ -+ if (device_create_file(pfe->dev, &dev_attr_bmu)) -+ goto err_bmu; -+ -+ if (device_create_file(pfe->dev, &dev_attr_hif)) -+ goto err_hif; -+ -+ if (device_create_file(pfe->dev, &dev_attr_gpi)) -+ goto err_gpi; -+ -+ if (device_create_file(pfe->dev, &dev_attr_drops)) -+ goto err_drops; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu0_queues)) -+ goto err_tmu0_queues; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu1_queues)) -+ goto err_tmu1_queues; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu2_queues)) -+ goto err_tmu2_queues; -+ -+ if (device_create_file(pfe->dev, &dev_attr_tmu3_queues)) -+ goto err_tmu3_queues; -+ -+ if (device_create_file(pfe->dev, &dev_attr_pfemem)) -+ goto err_pfemem; -+ -+ if (device_create_file(pfe->dev, &dev_attr_fcs_revalidated)) -+ goto err_crc_revalidated; -+ -+#ifdef HIF_NAPI_STATS -+ if (device_create_file(pfe->dev, &dev_attr_hif_napi_stats)) -+ goto err_hif_napi_stats; -+#endif -+ -+ return 0; -+ -+#ifdef HIF_NAPI_STATS -+err_hif_napi_stats: -+ device_remove_file(pfe->dev, &dev_attr_fcs_revalidated); -+#endif -+ -+err_crc_revalidated: -+ device_remove_file(pfe->dev, &dev_attr_pfemem); -+ -+err_pfemem: -+ device_remove_file(pfe->dev, &dev_attr_tmu3_queues); -+ -+err_tmu3_queues: -+ device_remove_file(pfe->dev, &dev_attr_tmu2_queues); -+ -+err_tmu2_queues: -+ device_remove_file(pfe->dev, &dev_attr_tmu1_queues); -+ -+err_tmu1_queues: -+ device_remove_file(pfe->dev, &dev_attr_tmu0_queues); -+ -+err_tmu0_queues: -+ device_remove_file(pfe->dev, &dev_attr_drops); -+ -+err_drops: -+ device_remove_file(pfe->dev, &dev_attr_gpi); -+ -+err_gpi: -+ device_remove_file(pfe->dev, &dev_attr_hif); -+ -+err_hif: -+ device_remove_file(pfe->dev, &dev_attr_bmu); -+ -+err_bmu: -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ device_remove_file(pfe->dev, &dev_attr_util); -+ -+err_util: -+#endif -+ device_remove_file(pfe->dev, &dev_attr_tmu); -+ -+err_tmu: -+ device_remove_file(pfe->dev, &dev_attr_class); -+ -+err_class: -+ return -1; -+} -+ -+void pfe_sysfs_exit(struct pfe *pfe) -+{ -+#ifdef HIF_NAPI_STATS -+ device_remove_file(pfe->dev, &dev_attr_hif_napi_stats); -+#endif -+ device_remove_file(pfe->dev, &dev_attr_fcs_revalidated); -+ device_remove_file(pfe->dev, &dev_attr_pfemem); -+ device_remove_file(pfe->dev, &dev_attr_tmu3_queues); -+ device_remove_file(pfe->dev, &dev_attr_tmu2_queues); -+ device_remove_file(pfe->dev, &dev_attr_tmu1_queues); -+ device_remove_file(pfe->dev, &dev_attr_tmu0_queues); -+ device_remove_file(pfe->dev, &dev_attr_drops); -+ device_remove_file(pfe->dev, &dev_attr_gpi); -+ device_remove_file(pfe->dev, &dev_attr_hif); -+ device_remove_file(pfe->dev, &dev_attr_bmu); -+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED) -+ device_remove_file(pfe->dev, &dev_attr_util); -+#endif -+ device_remove_file(pfe->dev, &dev_attr_tmu); -+ device_remove_file(pfe->dev, &dev_attr_class); -+} ---- /dev/null -+++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ */ -+ -+#ifndef _PFE_SYSFS_H_ -+#define _PFE_SYSFS_H_ -+ -+#include -+ -+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset); -+ -+int pfe_sysfs_init(struct pfe *pfe); -+void pfe_sysfs_exit(struct pfe *pfe); -+ -+#endif /* _PFE_SYSFS_H_ */ diff --git a/target/linux/layerscape/patches-5.10/702-phy-Add-2.5G-SGMII-interface-mode.patch b/target/linux/layerscape/patches-5.10/702-phy-Add-2.5G-SGMII-interface-mode.patch deleted file mode 100644 index 53677c0416..0000000000 --- a/target/linux/layerscape/patches-5.10/702-phy-Add-2.5G-SGMII-interface-mode.patch +++ /dev/null @@ -1,32 +0,0 @@ -From c918c472546afa83a619ae3cb1a9d7d346c6e288 Mon Sep 17 00:00:00 2001 -From: Bhaskar Upadhaya -Date: Wed, 29 Nov 2017 15:27:57 +0530 -Subject: [PATCH 154/173] phy: Add 2.5G SGMII interface mode - -Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII) -in existing phy_interface list - -Signed-off-by: Bhaskar Upadhaya ---- - include/linux/phy.h | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -146,6 +146,7 @@ typedef enum { - PHY_INTERFACE_MODE_USXGMII, - /* 10GBASE-KR - with Clause 73 AN */ - PHY_INTERFACE_MODE_10GKR, -+ PHY_INTERFACE_MODE_2500SGMII, - PHY_INTERFACE_MODE_MAX, - } phy_interface_t; - -@@ -221,6 +222,8 @@ static inline const char *phy_modes(phy_ - return "10gbase-kr"; - case PHY_INTERFACE_MODE_100BASEX: - return "100base-x"; -+ case PHY_INTERFACE_MODE_2500SGMII: -+ return "sgmii-2500"; - default: - return "unknown"; - } diff --git a/target/linux/malta/config-5.10 b/target/linux/malta/config-5.10 deleted file mode 100644 index e4f56229a9..0000000000 --- a/target/linux/malta/config-5.10 +++ /dev/null @@ -1,275 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ATA=y -CONFIG_ATA_PIIX=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -# CONFIG_BLK_DEV_DM is not set -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_MD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOARD_SCACHE=y -CONFIG_BOOT_ELF32=y -CONFIG_BOUNCE=y -CONFIG_BUILTIN_DTB=y -CONFIG_CEVT_R4K=y -CONFIG_CLKBLD_I8253=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_I8253=y -CONFIG_CLKSRC_I8253=y -CONFIG_CLKSRC_MIPS_GIC=y -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -# CONFIG_CPU_HAS_SMARTMIPS is not set -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_MICROMIPS is not set -# CONFIG_CPU_MIPS32 is not set -# CONFIG_CPU_MIPS32_3_5_FEATURES is not set -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS32_R5 is not set -# CONFIG_CPU_MIPS32_R5_FEATURES is not set -# CONFIG_CPU_MIPS32_R6 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_MIPS64_R6 is not set -# CONFIG_CPU_MIPSR2 is not set -# CONFIG_CPU_MIPSR2_IRQ_EI is not set -# CONFIG_CPU_MIPSR2_IRQ_VI is not set -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -# CONFIG_CPU_NEVADA is not set -CONFIG_CPU_R4K_CACHE_TLB=y -# CONFIG_CPU_RM7000 is not set -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_MAYBE_COHERENT=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HW_CONSOLE=y -CONFIG_I8253=y -CONFIG_I8253_LOCK=y -CONFIG_I8259=y -CONFIG_INPUT=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_ISA_DMA_API=y -CONFIG_JBD2=y -CONFIG_JFFS2_FS_POSIX_ACL=y -CONFIG_JFFS2_FS_SECURITY=y -CONFIG_KALLSYMS=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_XZ is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MD=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_BONITO64=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -CONFIG_MIPS_CM=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_MIPS_CMDLINE_FROM_DTB is not set -# CONFIG_MIPS_CMP is not set -CONFIG_MIPS_CPC=y -# CONFIG_MIPS_CPS is not set -CONFIG_MIPS_CPU_SCACHE=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_EXTERNAL_TIMER=y -CONFIG_MIPS_GIC=y -CONFIG_MIPS_L1_CACHE_SHIFT=6 -CONFIG_MIPS_L1_CACHE_SHIFT_6=y -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -CONFIG_MIPS_MALTA=y -CONFIG_MIPS_MSC=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NO_APPENDED_DTB=y -CONFIG_MIPS_NR_CPU_NR_MAP=2 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -# CONFIG_MIPS_RAW_APPENDED_DTB is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MTD_CFI_STAA=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_NET=y -CONFIG_PADATA=y -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PATA_LEGACY=y -CONFIG_PATA_TIMINGS=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PCI_GT64XXX_PCI0=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_PIIX4_POWEROFF=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_PROC_PAGE_MONITOR=y -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_QUOTA_TREE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RELAY=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SATA_HOST=y -CONFIG_SCSI=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SRCU=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_SYNC_R4K=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y -CONFIG_SYS_HAS_CPU_MIPS32_R5=y -CONFIG_SYS_HAS_CPU_MIPS32_R6=y -CONFIG_SYS_HAS_CPU_MIPS64_R1=y -CONFIG_SYS_HAS_CPU_MIPS64_R2=y -CONFIG_SYS_HAS_CPU_MIPS64_R6=y -CONFIG_SYS_HAS_CPU_NEVADA=y -CONFIG_SYS_HAS_CPU_RM7000=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MICROMIPS=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MIPS_CMP=y -CONFIG_SYS_SUPPORTS_MIPS_CPS=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_RELOCATABLE=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMARTMIPS=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_SYS_SUPPORTS_VPE_LOADER=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=1 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_VXFS_FS=y -CONFIG_WAR_ICACHE_REFILLS=y -CONFIG_XPS=y diff --git a/target/linux/mpc85xx/config-5.10 b/target/linux/mpc85xx/config-5.10 deleted file mode 100644 index c2044fabd0..0000000000 --- a/target/linux/mpc85xx/config-5.10 +++ /dev/null @@ -1,269 +0,0 @@ -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_ADVANCED_OPTIONS is not set -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_MMAP_RND_BITS=11 -CONFIG_ARCH_MMAP_RND_BITS_MAX=17 -CONFIG_ARCH_MMAP_RND_BITS_MIN=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y -CONFIG_ASN1=y -CONFIG_AUDIT_ARCH=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOOKE=y -CONFIG_BOOKE_WDT=y -# CONFIG_BSC9131_RDB is not set -# CONFIG_BSC9132_QDS is not set -# CONFIG_C293_PCIE is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_CMDLINE="console=ttyS0,115200" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_CMDLINE_OVERRIDE is not set -# CONFIG_COMMON_CLK is not set -CONFIG_COMPAT_32BIT_TIME=y -# CONFIG_CORENET_GENERIC is not set -# CONFIG_CPM2 is not set -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CRYPTO_AES_PPC_SPE is not set -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 -# CONFIG_CRYPTO_MD5_PPC is not set -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RSA=y -# CONFIG_CRYPTO_SHA1_PPC is not set -# CONFIG_CRYPTO_SHA1_PPC_SPE is not set -# CONFIG_CRYPTO_SHA256_PPC_SPE is not set -CONFIG_DATA_SHIFT=12 -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DNOTIFY=y -CONFIG_DTC=y -# CONFIG_E200 is not set -CONFIG_E500=y -CONFIG_E500_CPU=y -# CONFIG_E5500_CPU is not set -# CONFIG_E6500_CPU is not set -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -# CONFIG_EDAC_DEBUG is not set -CONFIG_EDAC_LEGACY_SYSFS=y -CONFIG_EDAC_MPC85XX=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FIXED_PHY=y -CONFIG_FSL_BOOKE=y -CONFIG_FSL_EMB_PERFMON=y -# CONFIG_FSL_FMAN is not set -CONFIG_FSL_LBC=y -CONFIG_FSL_PCI=y -CONFIG_FSL_PQ_MDIO=y -CONFIG_FSL_SOC=y -CONFIG_FSL_SOC_BOOKE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GEN_RTC=y -# CONFIG_GE_IMP3A is not set -CONFIG_GIANFAR=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MPC8XXX=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HIVEAP_330 is not set -CONFIG_HW_RANDOM=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_MPC=y -CONFIG_ILLEGAL_POINTER_VALUE=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_ISA_DMA_API=y -CONFIG_KERNEL_START=0xc0000000 -# CONFIG_KSI8560 is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOWMEM_CAM_NUM=3 -CONFIG_LOWMEM_SIZE=0x30000000 -CONFIG_LXT_PHY=y -# CONFIG_MATH_EMULATION is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MIGRATION=y -CONFIG_MMU_GATHER_PAGE_SIZE=y -CONFIG_MODULES_USE_ELF_RELA=y -# CONFIG_MPC8536_DS is not set -# CONFIG_MPC8540_ADS is not set -# CONFIG_MPC8560_ADS is not set -# CONFIG_MPC85xx_CDS is not set -# CONFIG_MPC85xx_DS is not set -# CONFIG_MPC85xx_MDS is not set -# CONFIG_MPC85xx_RDB is not set -CONFIG_MPIC=y -# CONFIG_MPIC_MSGR is not set -CONFIG_MPIC_TIMER=y -CONFIG_MPILIB=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -# CONFIG_MVME2500 is not set -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NLS=y -CONFIG_NR_IRQS=512 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DMA_DEFAULT_COHERENT=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND=y -# CONFIG_P1010_RDB is not set -# CONFIG_P1022_DS is not set -# CONFIG_P1022_RDK is not set -# CONFIG_P1023_RDB is not set -CONFIG_PAGE_OFFSET=0xc0000000 -# CONFIG_PANDA is not set -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYSICAL_ALIGN=0x04000000 -CONFIG_PHYSICAL_START=0x00000000 -# CONFIG_PHYS_64BIT is not set -# CONFIG_PMU_SYSFS is not set -# CONFIG_PPA8548 is not set -CONFIG_PPC=y -CONFIG_PPC32=y -# CONFIG_PPC64 is not set -CONFIG_PPC_85xx=y -# CONFIG_PPC_8xx is not set -CONFIG_PPC_ADV_DEBUG_DACS=2 -CONFIG_PPC_ADV_DEBUG_DVCS=0 -CONFIG_PPC_ADV_DEBUG_IACS=2 -CONFIG_PPC_ADV_DEBUG_REGS=y -CONFIG_PPC_BARRIER_NOSPEC=y -CONFIG_PPC_BOOK3E_MMU=y -# CONFIG_PPC_BOOK3S_6xx is not set -CONFIG_PPC_DOORBELL=y -# CONFIG_PPC_E500MC is not set -# CONFIG_PPC_EARLY_DEBUG is not set -CONFIG_PPC_FSL_BOOK3E=y -CONFIG_PPC_INDIRECT_PCI=y -# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set -CONFIG_PPC_MMU_NOHASH=y -CONFIG_PPC_MMU_NOHASH_32=y -CONFIG_PPC_PAGE_SHIFT=12 -# CONFIG_PPC_PTDUMP is not set -# CONFIG_PPC_QEMU_E500 is not set -CONFIG_PPC_SMP_MUXED_IPI=y -CONFIG_PPC_UDBG_16550=y -CONFIG_PPC_WERROR=y -CONFIG_QE_GPIO=y -CONFIG_QUICC_ENGINE=y -CONFIG_RAS=y -# CONFIG_RED_15W_REV1 is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_GENERIC=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_SBC8548 is not set -# CONFIG_SCOM_DEBUGFS is not set -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SERIAL_QE is not set -# CONFIG_SOCRATES is not set -CONFIG_SPARSE_IRQ=y -CONFIG_SPE=y -CONFIG_SPE_POSSIBLE=y -CONFIG_SPI=y -CONFIG_SPI_FSL_ESPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_STX_GP3 is not set -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_TARGET_CPU="8540" -CONFIG_TARGET_CPU_BOOL=y -CONFIG_TASK_SIZE=0xc0000000 -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_THREAD_SHIFT=13 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -# CONFIG_TL_WDR4900_V1 is not set -# CONFIG_FIREBOX_T10 is not set -# CONFIG_TOOLCHAIN_DEFAULT_CPU is not set -# CONFIG_TQM8540 is not set -# CONFIG_TQM8541 is not set -# CONFIG_TQM8548 is not set -# CONFIG_TQM8555 is not set -# CONFIG_TQM8560 is not set -# CONFIG_TWR_P102x is not set -CONFIG_UCC=y -CONFIG_UCC_FAST=y -CONFIG_UCC_GETH=y -# CONFIG_UGETH_TX_ON_DEMAND is not set -CONFIG_USB_SUPPORT=y -CONFIG_VDSO32=y -# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WS_AP3710I is not set -# CONFIG_WS_AP3825I is not set -# CONFIG_XES_MPC85xx is not set -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_POWERPC=y diff --git a/target/linux/mpc85xx/patches-5.10/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch b/target/linux/mpc85xx/patches-5.10/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch deleted file mode 100644 index 5e5ab10daf..0000000000 --- a/target/linux/mpc85xx/patches-5.10/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/common.c -+++ b/arch/powerpc/platforms/85xx/common.c -@@ -30,6 +30,7 @@ static const struct of_device_id mpc85xx - { .compatible = "fsl,mpc8548-guts", }, - /* Probably unnecessary? */ - { .compatible = "gpio-leds", }, -+ { .compatible = "gpio-keys", }, - /* For all PCI controllers */ - { .compatible = "fsl,mpc8540-pci", }, - { .compatible = "fsl,mpc8548-pcie", }, diff --git a/target/linux/mpc85xx/patches-5.10/100-powerpc-85xx-tl-wdr4900-v1-support.patch b/target/linux/mpc85xx/patches-5.10/100-powerpc-85xx-tl-wdr4900-v1-support.patch deleted file mode 100644 index 133364854a..0000000000 --- a/target/linux/mpc85xx/patches-5.10/100-powerpc-85xx-tl-wdr4900-v1-support.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 1d9f596e572917772b87a2a37e1680902964782f Mon Sep 17 00:00:00 2001 -From: Gabor Juhos -Date: Wed, 20 Feb 2013 08:40:33 +0100 -Subject: [PATCH] powerpc: 85xx: add support for the TP-Link TL-WDR4900 v1 - board - -This patch adds support for the TP-Link TL-WDR4900 v1 -concurrent dual-band wireless router. The devices uses -the Freescale P1014 SoC. - -Signed-off-by: Gabor Juhos -Signed-off-by: Pawel Dembicki ---- - arch/powerpc/boot/Makefile | 3 ++- - arch/powerpc/boot/wrapper | 5 +++++ - arch/powerpc/platforms/85xx/Kconfig | 12 ++++++++++++ - arch/powerpc/platforms/85xx/Makefile | 1 + - 4 files changed, 20 insertions(+), 1 deletion(-) - ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -158,6 +158,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie - src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S - src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S - src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c -+src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S - - src-wlib := $(sort $(src-wlib-y)) - src-plat := $(sort $(src-plat-y)) -@@ -337,7 +338,7 @@ image-$(CONFIG_TQM8555) += cuImage.tqm - image-$(CONFIG_TQM8560) += cuImage.tqm8560 - image-$(CONFIG_SBC8548) += cuImage.sbc8548 - image-$(CONFIG_KSI8560) += cuImage.ksi8560 -- -+image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1 - # Board ports in arch/powerpc/platform/86xx/Kconfig - image-$(CONFIG_MVME7100) += dtbImage.mvme7100 - ---- a/arch/powerpc/boot/wrapper -+++ b/arch/powerpc/boot/wrapper -@@ -324,6 +324,11 @@ adder875-redboot) - platformo="$object/fixed-head.o $object/redboot-8xx.o" - binary=y - ;; -+simpleboot-tl-wdr4900-v1) -+ platformo="$object/fixed-head.o $object/simpleboot.o" -+ link_address='0x1000000' -+ binary=y -+ ;; - simpleboot-*) - platformo="$object/fixed-head.o $object/simpleboot.o" - binary=y ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -170,6 +170,18 @@ config STX_GP3 - select CPM2 - select DEFAULT_UIMAGE - -+config TL_WDR4900_V1 -+ bool "TP-Link TL-WDR4900 v1" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ select SWIOTLB -+ help -+ This option enables support for the TP-Link TL-WDR4900 v1 board. -+ -+ This board is a Concurrent Dual-Band wireless router with a -+ Freescale P1014 SoC. -+ - config TQM8540 - bool "TQ Components TQM8540" - help ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -28,6 +28,7 @@ obj-$(CONFIG_CORENET_GENERIC) += coren - obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o - obj-$(CONFIG_STX_GP3) += stx_gp3.o - obj-$(CONFIG_TQM85xx) += tqm85xx.o -+obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o - obj-$(CONFIG_SBC8548) += sbc8548.o - obj-$(CONFIG_PPA8548) += ppa8548.o - obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o diff --git a/target/linux/mpc85xx/patches-5.10/101-powerpc-85xx-hiveap-330-support.patch b/target/linux/mpc85xx/patches-5.10/101-powerpc-85xx-hiveap-330-support.patch deleted file mode 100644 index da95cd2716..0000000000 --- a/target/linux/mpc85xx/patches-5.10/101-powerpc-85xx-hiveap-330-support.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -49,6 +49,17 @@ config BSC9132_QDS - and dual StarCore SC3850 DSP cores. - Manufacturer : Freescale Semiconductor, Inc - -+config HIVEAP_330 -+ bool "Aerohive HiveAP-330" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the Aerohive HiveAP-330 board. -+ -+ This board is a Concurrent Dual-Band wireless access point with a -+ Freescale P1020 SoC. -+ - config MPC8540_ADS - bool "Freescale MPC8540 ADS" - select DEFAULT_UIMAGE ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -12,6 +12,7 @@ obj-y += common.o - obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o - obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o - obj-$(CONFIG_C293_PCIE) += c293pcie.o -+obj-$(CONFIG_HIVEAP_330) += hiveap-330.o - obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o - obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o - obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o diff --git a/target/linux/mpc85xx/patches-5.10/102-powerpc-add-cmdline-override.patch b/target/linux/mpc85xx/patches-5.10/102-powerpc-add-cmdline-override.patch deleted file mode 100644 index 95ce5f2bb9..0000000000 --- a/target/linux/mpc85xx/patches-5.10/102-powerpc-add-cmdline-override.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/powerpc/Kconfig -+++ b/arch/powerpc/Kconfig -@@ -931,6 +931,14 @@ config CMDLINE_FORCE - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config EXTRA_TARGETS - string "Additional default image types" - help ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1058,6 +1058,17 @@ int __init early_init_dt_scan_chosen(uns - if (p != NULL && l > 0) - strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else - * managed to set the command line, unless CONFIG_CMDLINE_FORCE diff --git a/target/linux/mpc85xx/patches-5.10/103-powerpc-85xx-red-15w-rev1.patch b/target/linux/mpc85xx/patches-5.10/103-powerpc-85xx-red-15w-rev1.patch deleted file mode 100644 index 3c64b06847..0000000000 --- a/target/linux/mpc85xx/patches-5.10/103-powerpc-85xx-red-15w-rev1.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -173,6 +173,16 @@ config XES_MPC85xx - Manufacturer: Extreme Engineering Solutions, Inc. - URL: - -+config RED_15W_REV1 -+ bool "Sophos RED 15w Rev.1" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the Sophos RED 15w Rev.1 board. -+ -+ This board is a wireless VPN router with a Freescale P1010 SoC. -+ - config STX_GP3 - bool "Silicon Turnkey Express GP3" - help ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_P1023_RDB) += p1023_rdb.o - obj-$(CONFIG_TWR_P102x) += twr_p102x.o - obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o - obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o -+obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o - obj-$(CONFIG_STX_GP3) += stx_gp3.o - obj-$(CONFIG_TQM85xx) += tqm85xx.o - obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o diff --git a/target/linux/mpc85xx/patches-5.10/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch b/target/linux/mpc85xx/patches-5.10/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch deleted file mode 100644 index 94ed26c3df..0000000000 --- a/target/linux/mpc85xx/patches-5.10/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch +++ /dev/null @@ -1,170 +0,0 @@ -From 93514afd769c305182beeed1f9c4c46235879ef8 Mon Sep 17 00:00:00 2001 -From: Pawel Dembicki -Date: Sun, 30 Dec 2018 23:24:41 +0100 -Subject: [PATCH] powerpc: mpc85xx: change P2020RDB dts file for OpenWRT - -This patch apply chages for OpenWRT in P2020RDB -dts file. - -Signed-off-by: Pawel Dembicki ---- - arch/powerpc/boot/dts/fsl/p2020rdb.dts | 98 +++++++++++++++++--------- - 1 file changed, 63 insertions(+), 35 deletions(-) - ---- a/arch/powerpc/boot/dts/fsl/p2020rdb.dts -+++ b/arch/powerpc/boot/dts/fsl/p2020rdb.dts -@@ -5,10 +5,15 @@ - * Copyright 2009-2012 Freescale Semiconductor Inc. - */ - -+/dts-v1/; -+ - /include/ "p2020si-pre.dtsi" - -+#include -+#include -+ - / { -- model = "fsl,P2020RDB"; -+ model = "Freescale P2020RDB"; - compatible = "fsl,P2020RDB"; - - aliases { -@@ -34,48 +39,38 @@ - 0x2 0x0 0x0 0xffb00000 0x00020000>; - - nor@0,0 { -- #address-cells = <1>; -- #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x1000000>; - bank-width = <2>; - device-width = <1>; - -- partition@0 { -- /* This location must not be altered */ -- /* 256KB for Vitesse 7385 Switch firmware */ -- reg = <0x0 0x00040000>; -- label = "NOR (RO) Vitesse-7385 Firmware"; -- read-only; -- }; -- -- partition@40000 { -- /* 256KB for DTB Image */ -- reg = <0x00040000 0x00040000>; -- label = "NOR (RO) DTB Image"; -- read-only; -- }; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; - -- partition@80000 { -- /* 3.5 MB for Linux Kernel Image */ -- reg = <0x00080000 0x00380000>; -- label = "NOR (RO) Linux Kernel Image"; -- read-only; -- }; -+ partition@0 { -+ /* This location must not be altered */ -+ /* 256KB for Vitesse 7385 Switch firmware */ -+ reg = <0x0 0x00040000>; -+ label = "NOR (RO) Vitesse-7385 Firmware"; -+ read-only; -+ }; - -- partition@400000 { -- /* 11MB for JFFS2 based Root file System */ -- reg = <0x00400000 0x00b00000>; -- label = "NOR (RW) JFFS2 Root File System"; -- }; -+ partition@40000 { -+ compatible = "denx,fit"; -+ reg = <0x00040000 0x00ec0000>; -+ label = "firmware"; -+ }; - -- partition@f00000 { -- /* This location must not be altered */ -- /* 512KB for u-boot Bootloader Image */ -- /* 512KB for u-boot Environment Variables */ -- reg = <0x00f00000 0x00100000>; -- label = "NOR (RO) U-Boot Image"; -- read-only; -+ partition@f00000 { -+ /* This location must not be altered */ -+ /* 512KB for u-boot Bootloader Image */ -+ /* 512KB for u-boot Environment Variables */ -+ reg = <0x00f00000 0x00100000>; -+ label = "u-boot"; -+ read-only; -+ }; - }; - }; - -@@ -85,6 +80,7 @@ - compatible = "fsl,p2020-fcm-nand", - "fsl,elbc-fcm-nand"; - reg = <0x1 0x0 0x40000>; -+ nand-ecc-mode = "none"; - - partition@0 { - /* This location must not be altered */ -@@ -140,13 +136,43 @@ - soc: soc@ffe00000 { - ranges = <0x0 0x0 0xffe00000 0x100000>; - -+ gpio0: gpio-controller@fc00 { -+ }; -+ - i2c@3000 { -+ temperature-sensor@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ -+ eeprom@50 { -+ compatible = "atmel,24c256"; -+ reg = <0x50>; -+ }; -+ - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; - }; - -+ i2c@3100 { -+ pmic@11 { -+ compatible = "zl2006"; -+ reg = <0x11>; -+ }; -+ -+ gpio@18 { -+ compatible = "nxp,pca9557"; -+ reg = <0x18>; -+ }; -+ -+ eeprom@52 { -+ compatible = "atmel,24c01"; -+ reg = <0x52>; -+ }; -+ }; -+ - spi@7000 { - flash@0 { - #address-cells = <1>; -@@ -200,10 +226,12 @@ - phy0: ethernet-phy@0 { - interrupts = <3 1 0 0>; - reg = <0x0>; -+ reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - phy1: ethernet-phy@1 { - interrupts = <3 1 0 0>; - reg = <0x1>; -+ reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - }; - tbi-phy@2 { - device_type = "tbi-phy"; diff --git a/target/linux/mpc85xx/patches-5.10/105-powerpc-85xx-panda-support.patch b/target/linux/mpc85xx/patches-5.10/105-powerpc-85xx-panda-support.patch deleted file mode 100644 index 4913c614a8..0000000000 --- a/target/linux/mpc85xx/patches-5.10/105-powerpc-85xx-panda-support.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -60,6 +60,17 @@ config HIVEAP_330 - This board is a Concurrent Dual-Band wireless access point with a - Freescale P1020 SoC. - -+config PANDA -+ bool "OCEDO PANDA" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the OCEDO PANDA board. -+ -+ This board is a Concurrent Dual-Band wireless access point with a -+ Freescale P1020 SoC. -+ - config MPC8540_ADS - bool "Freescale MPC8540 ADS" - select DEFAULT_UIMAGE ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o - obj-$(CONFIG_P1022_DS) += p1022_ds.o - obj-$(CONFIG_P1022_RDK) += p1022_rdk.o - obj-$(CONFIG_P1023_RDB) += p1023_rdb.o -+obj-$(CONFIG_PANDA) += panda.o - obj-$(CONFIG_TWR_P102x) += twr_p102x.o - obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o - obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o diff --git a/target/linux/mpc85xx/patches-5.10/106-powerpc-85xx-ws-ap3710i-support.patch b/target/linux/mpc85xx/patches-5.10/106-powerpc-85xx-ws-ap3710i-support.patch deleted file mode 100644 index 124376ffd9..0000000000 --- a/target/linux/mpc85xx/patches-5.10/106-powerpc-85xx-ws-ap3710i-support.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -71,6 +71,17 @@ config PANDA - This board is a Concurrent Dual-Band wireless access point with a - Freescale P1020 SoC. - -+config WS_AP3710I -+ bool "Enterasys WS-AP3710i" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the Enterasys WS-AP3710i board. -+ -+ This board is a Concurrent Dual-Band wireless access point with a -+ Freescale P1020 SoC. -+ - config MPC8540_ADS - bool "Freescale MPC8540 ADS" - select DEFAULT_UIMAGE ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -26,6 +26,7 @@ obj-$(CONFIG_P1022_RDK) += p1022_rdk.o - obj-$(CONFIG_P1023_RDB) += p1023_rdb.o - obj-$(CONFIG_PANDA) += panda.o - obj-$(CONFIG_TWR_P102x) += twr_p102x.o -+obj-$(CONFIG_WS_AP3710I) += ws-ap3710i.o - obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o - obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o - obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o diff --git a/target/linux/mpc85xx/patches-5.10/107-powerpc-85xx-add-ws-ap3825i-support.patch b/target/linux/mpc85xx/patches-5.10/107-powerpc-85xx-add-ws-ap3825i-support.patch deleted file mode 100644 index 89c58078de..0000000000 --- a/target/linux/mpc85xx/patches-5.10/107-powerpc-85xx-add-ws-ap3825i-support.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 2fa1a7983ef30f3c7486f9b07c001bee87d1f6d6 Mon Sep 17 00:00:00 2001 -From: Martin Kennedy -Date: Sat, 1 Jan 2022 11:01:37 -0500 -Subject: [PATCH] PowerPC 85xx: Add WS-AP3825i support - -This patch adds support for building Linux for the Extreme Networks -WS-AP3825i AP. - ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -82,6 +82,16 @@ config WS_AP3710I - This board is a Concurrent Dual-Band wireless access point with a - Freescale P1020 SoC. - -+config WS_AP3825I -+ bool "Extreme Networks WS-AP3825i" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the Extreme Networks WS-AP3825i board. -+ This board is a Concurrent Dual-Band wireless access point with a -+ Freescale P1020 SoC. -+ - config MPC8540_ADS - bool "Freescale MPC8540 ADS" - select DEFAULT_UIMAGE ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_P1023_RDB) += p1023_rdb.o - obj-$(CONFIG_PANDA) += panda.o - obj-$(CONFIG_TWR_P102x) += twr_p102x.o - obj-$(CONFIG_WS_AP3710I) += ws-ap3710i.o -+obj-$(CONFIG_WS_AP3825I) += ws-ap3825i.o - obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o - obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o - obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -159,6 +159,7 @@ src-plat-$(CONFIG_PPC_POWERNV) += pserie - src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S - src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c - src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S -+src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S - - src-wlib := $(sort $(src-wlib-y)) - src-plat := $(sort $(src-plat-y)) -@@ -339,6 +340,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm - image-$(CONFIG_SBC8548) += cuImage.sbc8548 - image-$(CONFIG_KSI8560) += cuImage.ksi8560 - image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1 -+image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i - # Board ports in arch/powerpc/platform/86xx/Kconfig - image-$(CONFIG_MVME7100) += dtbImage.mvme7100 - ---- a/arch/powerpc/boot/wrapper -+++ b/arch/powerpc/boot/wrapper -@@ -324,6 +324,7 @@ adder875-redboot) - platformo="$object/fixed-head.o $object/redboot-8xx.o" - binary=y - ;; -+simpleboot-ws-ap3825i|\ - simpleboot-tl-wdr4900-v1) - platformo="$object/fixed-head.o $object/simpleboot.o" - link_address='0x1000000' diff --git a/target/linux/mpc85xx/patches-5.10/108-powerpc-85xx-firebox-t10-support.patch.patch b/target/linux/mpc85xx/patches-5.10/108-powerpc-85xx-firebox-t10-support.patch.patch deleted file mode 100644 index b074113eaa..0000000000 --- a/target/linux/mpc85xx/patches-5.10/108-powerpc-85xx-firebox-t10-support.patch.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -92,6 +92,16 @@ config WS_AP3825I - This board is a Concurrent Dual-Band wireless access point with a - Freescale P1020 SoC. - -+config FIREBOX_T10 -+ bool "Watchguard Firebox T10" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the Watchguard Firebox T10 board. -+ This board is a VPN Gateway-Router with a -+ Freescale P1010 SoC. -+ - config MPC8540_ADS - bool "Freescale MPC8540 ADS" - select DEFAULT_UIMAGE ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -28,6 +28,7 @@ obj-$(CONFIG_PANDA) += panda.o - obj-$(CONFIG_TWR_P102x) += twr_p102x.o - obj-$(CONFIG_WS_AP3710I) += ws-ap3710i.o - obj-$(CONFIG_WS_AP3825I) += ws-ap3825i.o -+obj-$(CONFIG_FIREBOX_T10) += firebox_t10.o - obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o - obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o - obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o diff --git a/target/linux/mpc85xx/patches-5.10/109-powerpc-85xx-add-ws-ap3715i-support.patch b/target/linux/mpc85xx/patches-5.10/109-powerpc-85xx-add-ws-ap3715i-support.patch deleted file mode 100644 index 10ba744897..0000000000 --- a/target/linux/mpc85xx/patches-5.10/109-powerpc-85xx-add-ws-ap3715i-support.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- a/arch/powerpc/platforms/85xx/Kconfig -+++ b/arch/powerpc/platforms/85xx/Kconfig -@@ -82,6 +82,17 @@ config WS_AP3710I - This board is a Concurrent Dual-Band wireless access point with a - Freescale P1020 SoC. - -+config WS_AP3715I -+ bool "Enterasys WS-AP3715i" -+ select DEFAULT_UIMAGE -+ select ARCH_REQUIRE_GPIOLIB -+ select GPIO_MPC8XXX -+ help -+ This option enables support for the Enterasys WS-AP3715i board. -+ -+ This board is a Concurrent Dual-Band wireless access point with a -+ Freescale P1010 SoC. -+ - config WS_AP3825I - bool "Extreme Networks WS-AP3825i" - select DEFAULT_UIMAGE ---- a/arch/powerpc/platforms/85xx/Makefile -+++ b/arch/powerpc/platforms/85xx/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_P1023_RDB) += p1023_rdb.o - obj-$(CONFIG_PANDA) += panda.o - obj-$(CONFIG_TWR_P102x) += twr_p102x.o - obj-$(CONFIG_WS_AP3710I) += ws-ap3710i.o -+obj-$(CONFIG_WS_AP3715I) += ws-ap3715i.o - obj-$(CONFIG_WS_AP3825I) += ws-ap3825i.o - obj-$(CONFIG_FIREBOX_T10) += firebox_t10.o - obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -340,6 +340,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm - image-$(CONFIG_SBC8548) += cuImage.sbc8548 - image-$(CONFIG_KSI8560) += cuImage.ksi8560 - image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1 -+image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i - image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i - # Board ports in arch/powerpc/platform/86xx/Kconfig - image-$(CONFIG_MVME7100) += dtbImage.mvme7100 ---- a/arch/powerpc/boot/wrapper -+++ b/arch/powerpc/boot/wrapper -@@ -324,6 +324,7 @@ adder875-redboot) - platformo="$object/fixed-head.o $object/redboot-8xx.o" - binary=y - ;; -+simpleboot-ws-ap3715i|\ - simpleboot-ws-ap3825i|\ - simpleboot-tl-wdr4900-v1) - platformo="$object/fixed-head.o $object/simpleboot.o" diff --git a/target/linux/mpc85xx/patches-5.10/900-powerpc-bootwrapper-disable-uImage-generation.patch b/target/linux/mpc85xx/patches-5.10/900-powerpc-bootwrapper-disable-uImage-generation.patch deleted file mode 100644 index 86a1ea902e..0000000000 --- a/target/linux/mpc85xx/patches-5.10/900-powerpc-bootwrapper-disable-uImage-generation.patch +++ /dev/null @@ -1,42 +0,0 @@ -From d43ab14605510d9d2bd257a8cd70f24ada4621b0 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sat, 29 Feb 2020 14:27:04 +0100 -Subject: [PATCH] powerpc: bootwrapper: disable uImage generation - -Due to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to -instruct the mkimage to use the xz compression, which isn't -supported. This disables the uImage generation, as OpenWrt -generates individual uImages for each board using it's own -toolchain. - -Signed-off-by: David Bauer ---- - arch/powerpc/boot/Makefile | 9 --------- - 1 file changed, 9 deletions(-) - ---- a/arch/powerpc/boot/Makefile -+++ b/arch/powerpc/boot/Makefile -@@ -266,7 +266,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp - image-$(CONFIG_PPC_EFIKA) += zImage.chrp - image-$(CONFIG_PPC_PMAC) += zImage.pmac - image-$(CONFIG_PPC_HOLLY) += dtbImage.holly --image-$(CONFIG_DEFAULT_UIMAGE) += uImage - image-$(CONFIG_EPAPR_BOOT) += zImage.epapr - - # -@@ -399,15 +398,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits - $(obj)/vmlinux.strip: vmlinux - $(STRIP) -s -R .comment $< -o $@ - --$(obj)/uImage: vmlinux $(wrapperbits) FORCE -- $(call if_changed,wrap,uboot) -- --$(obj)/uImage.initrd.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE -- $(call if_changed,wrap,uboot-$*,,$(obj)/dts/$*.dtb,$(obj)/ramdisk.image.gz) -- --$(obj)/uImage.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE -- $(call if_changed,wrap,uboot-$*,,$(obj)/dts/$*.dtb) -- - $(obj)/cuImage.initrd.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE - $(call if_changed,wrap,cuboot-$*,,$(obj)/dts/$*.dtb,$(obj)/ramdisk.image.gz) - diff --git a/target/linux/mvebu/config-5.10 b/target/linux/mvebu/config-5.10 deleted file mode 100644 index 6ad5635c17..0000000000 --- a/target/linux/mvebu/config-5.10 +++ /dev/null @@ -1,424 +0,0 @@ -CONFIG_AHCI_MVEBU=y -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_MVEBU=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARMADA_370_CLK=y -CONFIG_ARMADA_370_XP_IRQ=y -CONFIG_ARMADA_370_XP_TIMER=y -# CONFIG_ARMADA_37XX_WATCHDOG is not set -CONFIG_ARMADA_38X_CLK=y -CONFIG_ARMADA_THERMAL=y -CONFIG_ARMADA_XP_CLK=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set -# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set -CONFIG_ARM_ATAG_DTB_COMPAT=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GLOBAL_TIMER=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_MVEBU_V7_CPUIDLE=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_ATA_LEDS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_FEROCEON_L2 is not set -CONFIG_CACHE_L2X0=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PJ4B=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AES_ARM_BS=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_MARVELL=y -CONFIG_CRYPTO_DEV_MARVELL_CESA=y -CONFIG_CRYPTO_ESSIV=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM=y -CONFIG_CRYPTO_SHA1_ARM_NEON=y -CONFIG_CRYPTO_SHA256_ARM=y -CONFIG_CRYPTO_SHA512_ARM=y -CONFIG_CRYPTO_SIMD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MVEBU_UART0=y -# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set -# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0xd0012000 -CONFIG_DEBUG_UART_VIRT=0xfec12000 -CONFIG_DEBUG_UNCOMPRESS=y -CONFIG_DEBUG_USER=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_MVEBU=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWBM=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MV64XXX=y -# CONFIG_I2C_PXA is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_IWMMXT is not set -CONFIG_JBD2=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PCA963X=y -CONFIG_LEDS_TLC591XX=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACH_ARMADA_370=y -# CONFIG_MACH_ARMADA_375 is not set -CONFIG_MACH_ARMADA_38X=y -# CONFIG_MACH_ARMADA_39X is not set -CONFIG_MACH_ARMADA_XP=y -# CONFIG_MACH_DOVE is not set -CONFIG_MACH_MVEBU_ANY=y -CONFIG_MACH_MVEBU_V7=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MANGLE_BOOTARGS=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_I2C=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_MVSDIO=y -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_PXAV3=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MARVELL=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_MVEBU_CLK_COMMON=y -CONFIG_MVEBU_CLK_COREDIV=y -CONFIG_MVEBU_CLK_CPU=y -CONFIG_MVEBU_DEVBUS=y -CONFIG_MVEBU_MBUS=y -CONFIG_MVMDIO=y -CONFIG_MVNETA=y -CONFIG_MVNETA_BM=y -CONFIG_MVNETA_BM_ENABLE=y -# CONFIG_MVPP2 is not set -CONFIG_MV_XOR=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MV88E6XXX=y -CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y -CONFIG_NET_DSA_TAG_DSA=y -CONFIG_NET_DSA_TAG_EDSA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVME_CORE=y -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_MULTIPATH is not set -# CONFIG_NVME_TCP is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_ORION_WATCHDOG=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PCI=y -CONFIG_PCI_BRIDGE_EMUL=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_MVEBU=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MVEBU_A3700_COMPHY is not set -# CONFIG_PHY_MVEBU_A3700_UTMI is not set -# CONFIG_PHY_MVEBU_A38X_COMPHY is not set -# CONFIG_PHY_MVEBU_CP110_COMPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_ARMADA_370=y -CONFIG_PINCTRL_ARMADA_38X=y -CONFIG_PINCTRL_ARMADA_XP=y -CONFIG_PINCTRL_MVEBU=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PJ4B_ERRATA_4742=y -CONFIG_PL310_ERRATA_753970=y -CONFIG_PLAT_ORION=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=11 -CONFIG_PWM=y -CONFIG_PWM_SYSFS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_ARMADA38X=y -# CONFIG_RTC_DRV_MV is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_SATA_HOST=y -CONFIG_SATA_MV=y -CONFIG_SATA_PMP=y -CONFIG_SCSI=y -CONFIG_SENSORS_PWM_FAN=y -CONFIG_SENSORS_TMP421=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_MVEBU_CONSOLE=y -CONFIG_SERIAL_MVEBU_UART=y -CONFIG_SFP=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOC_BUS=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -# CONFIG_SPI_ARMADA_3700 is not set -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_ORION=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_ORION=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_LEDS_TRIGGER_USBPORT=y -CONFIG_USB_PHY=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MVEBU=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/mvebu/cortexa53/config-5.10 b/target/linux/mvebu/cortexa53/config-5.10 deleted file mode 100644 index fd58578405..0000000000 --- a/target/linux/mvebu/cortexa53/config-5.10 +++ /dev/null @@ -1,102 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARMADA_37XX_CLK=y -CONFIG_ARMADA_37XX_RWTM_MBOX=y -CONFIG_ARMADA_37XX_WATCHDOG=y -CONFIG_ARMADA_AP806_SYSCON=y -CONFIG_ARMADA_AP_CP_HELPER=y -CONFIG_ARMADA_CP110_SYSCON=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARMADA_37XX_CPUFREQ=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -# CONFIG_ARM_PL172_MPMC is not set -CONFIG_ARM_PSCI_FW=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64=y -CONFIG_CRYPTO_SHA512_ARM64_CE=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DMA_DIRECT_REMAP=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_FRAME_POINTER=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_PINCONF=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_DEVRES=y -CONFIG_MFD_SYSCON=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MVEBU_GICP=y -CONFIG_MVEBU_ICU=y -CONFIG_MVEBU_ODMI=y -CONFIG_MVEBU_PIC=y -CONFIG_MVEBU_SEI=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI_AARDVARK=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MVEBU_A3700_COMPHY=y -CONFIG_PHY_MVEBU_A3700_UTMI=y -CONFIG_PINCTRL_ARMADA_37XX=y -CONFIG_PINCTRL_ARMADA_AP806=y -CONFIG_PINCTRL_ARMADA_CP110=y -CONFIG_POWER_SUPPLY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_REGULATOR_GPIO=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPI_ARMADA_3700=y -CONFIG_SWIOTLB=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TURRIS_MOX_RWTM=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_VMAP_STACK=y -CONFIG_XXHASH=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mvebu/cortexa72/config-5.10 b/target/linux/mvebu/cortexa72/config-5.10 deleted file mode 100644 index 584c3fc9b8..0000000000 --- a/target/linux/mvebu/cortexa72/config-5.10 +++ /dev/null @@ -1,115 +0,0 @@ -CONFIG_64BIT=y -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -# CONFIG_ARM64_PTR_AUTH is not set -CONFIG_ARM64_SVE=y -# CONFIG_ARM64_TAGGED_ADDR_ABI is not set -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARMADA_37XX_CLK=y -CONFIG_ARMADA_AP806_SYSCON=y -CONFIG_ARMADA_AP_CPU_CLK=y -CONFIG_ARMADA_AP_CP_HELPER=y -CONFIG_ARMADA_CP110_SYSCON=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARMADA_8K_CPUFREQ=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -# CONFIG_ARM_PL172_MPMC is not set -CONFIG_ARM_PSCI_FW=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64=y -CONFIG_CRYPTO_SHA512_ARM64_CE=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DMA_DIRECT_REMAP=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_FRAME_POINTER=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_PINCONF=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_HW_RANDOM_OMAP=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_LEDS_IEI_WT61P803_PUZZLE=y -CONFIG_LEDS_IS31FL319X=y -CONFIG_MARVELL_10G_PHY=y -CONFIG_MDIO_DEVRES=y -CONFIG_MFD_CORE=y -CONFIG_MFD_IEI_WT61P803_PUZZLE=y -CONFIG_MFD_SYSCON=y -CONFIG_MMC_SDHCI_XENON=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MVEBU_GICP=y -CONFIG_MVEBU_ICU=y -CONFIG_MVEBU_ODMI=y -CONFIG_MVEBU_PIC=y -CONFIG_MVEBU_SEI=y -CONFIG_MVPP2=y -CONFIG_MV_XOR_V2=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_ARMADA_8K=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y -# CONFIG_PCI_AARDVARK is not set -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MVEBU_CP110_COMPHY=y -CONFIG_PINCTRL_ARMADA_37XX=y -CONFIG_PINCTRL_ARMADA_AP806=y -CONFIG_PINCTRL_ARMADA_CP110=y -CONFIG_POWER_SUPPLY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REGULATOR_GPIO=y -# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set -CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SWIOTLB=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_VMAP_STACK=y -CONFIG_XXHASH=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mvebu/cortexa9/config-5.10 b/target/linux/mvebu/cortexa9/config-5.10 deleted file mode 100644 index aff95995ce..0000000000 --- a/target/linux/mvebu/cortexa9/config-5.10 +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_PHY_MVEBU_A38X_COMPHY=y -CONFIG_RTC_DRV_MV=y diff --git a/target/linux/mvebu/patches-5.10/001-v5.11-arm64-dts-mcbin-singleshot-add-heartbeat-LED.patch b/target/linux/mvebu/patches-5.10/001-v5.11-arm64-dts-mcbin-singleshot-add-heartbeat-LED.patch deleted file mode 100644 index c3abae60a6..0000000000 --- a/target/linux/mvebu/patches-5.10/001-v5.11-arm64-dts-mcbin-singleshot-add-heartbeat-LED.patch +++ /dev/null @@ -1,65 +0,0 @@ -From da57203dc7fd556fbb3f0ec7d7d7c0b0e893b386 Mon Sep 17 00:00:00 2001 -From: Tomasz Maciej Nowak -Date: Tue, 10 Nov 2020 16:38:31 +0100 -Subject: [PATCH] arm64: dts: mcbin-singleshot: add heartbeat LED - -With board revision 1.3, SolidRun moved the power LED to the middle of -the board. In old place of power LED a GPIO controllable heartbeat LED -was added. This commit only touches Single Shot variant, since only this -variant is all revision 1.3. - -Note: -This is slightly modified patch. Some boards could be placed in an -enclosure, so the LED18 is enabled by default, since that'll be the only -visible indicator that the board is operating. - -Reported-by: Alexandra Alth -Signed-off-by: Tomasz Maciej Nowak -Signed-off-by: Gregory CLEMENT ---- - .../marvell/armada-8040-mcbin-singleshot.dts | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts -+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts -@@ -5,6 +5,8 @@ - * Device Tree file for MACCHIATOBin Armada 8040 community board platform - */ - -+#include -+ - #include "armada-8040-mcbin.dtsi" - - / { -@@ -12,6 +14,20 @@ - compatible = "marvell,armada8040-mcbin-singleshot", - "marvell,armada8040-mcbin", "marvell,armada8040", - "marvell,armada-ap806-quad", "marvell,armada-ap806"; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-0 = <&cp0_led18_pins>; -+ pinctrl-names = "default"; -+ -+ led18 { -+ gpios = <&cp0_gpio2 1 GPIO_ACTIVE_LOW>; -+ function = LED_FUNCTION_HEARTBEAT; -+ color = ; -+ linux,default-trigger = "heartbeat"; -+ default-state = "on"; -+ }; -+ }; - }; - - &cp0_eth0 { -@@ -27,3 +43,10 @@ - managed = "in-band-status"; - sfp = <&sfp_eth1>; - }; -+ -+&cp0_pinctrl { -+ cp0_led18_pins: led18-pins { -+ marvell,pins = "mpp33"; -+ marvell,function = "gpio"; -+ }; -+}; diff --git a/target/linux/mvebu/patches-5.10/002-v5.11-ARM-dts-turris-omnia-enable-HW-buffer-management.patch b/target/linux/mvebu/patches-5.10/002-v5.11-ARM-dts-turris-omnia-enable-HW-buffer-management.patch deleted file mode 100644 index 4ff0fe1e4c..0000000000 --- a/target/linux/mvebu/patches-5.10/002-v5.11-ARM-dts-turris-omnia-enable-HW-buffer-management.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 018b88eee1a2efda26ed2f09aab33ccdc40ef18f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Sun, 15 Nov 2020 14:59:17 +0100 -Subject: ARM: dts: turris-omnia: enable HW buffer management -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The buffer manager is available on Turris Omnia but needs to be -described in device-tree to be used. - -Signed-off-by: Marek Behún -Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") -Cc: linux-arm-kernel@lists.infradead.org -Cc: Uwe Kleine-König -Cc: Jason Cooper -Cc: Gregory CLEMENT -Cc: Andreas Färber -Cc: Andrew Lunn -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: Gregory CLEMENT ---- - arch/arm/boot/dts/armada-385-turris-omnia.dts | 17 +++++++++++++++++ - 1 file changed, 17 insertions(+) - -(limited to 'arch/arm/boot/dts/armada-385-turris-omnia.dts') - ---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts -+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts -@@ -90,12 +90,23 @@ - }; - }; - -+&bm { -+ status = "okay"; -+}; -+ -+&bm_bppi { -+ status = "okay"; -+}; -+ - /* Connected to 88E6176 switch, port 6 */ - ð0 { - pinctrl-names = "default"; - pinctrl-0 = <&ge0_rgmii_pins>; - status = "okay"; - phy-mode = "rgmii"; -+ buffer-manager = <&bm>; -+ bm,pool-long = <0>; -+ bm,pool-short = <3>; - - fixed-link { - speed = <1000>; -@@ -109,6 +120,9 @@ - pinctrl-0 = <&ge1_rgmii_pins>; - status = "okay"; - phy-mode = "rgmii"; -+ buffer-manager = <&bm>; -+ bm,pool-long = <1>; -+ bm,pool-short = <3>; - - fixed-link { - speed = <1000>; -@@ -121,6 +135,9 @@ - status = "okay"; - phy-mode = "sgmii"; - phy = <&phy1>; -+ buffer-manager = <&bm>; -+ bm,pool-long = <2>; -+ bm,pool-short = <3>; - }; - - &i2c0 { diff --git a/target/linux/mvebu/patches-5.10/003-v5.11-ARM-dts-turris-omnia-add-comphy-handle-to-eth2.patch b/target/linux/mvebu/patches-5.10/003-v5.11-ARM-dts-turris-omnia-add-comphy-handle-to-eth2.patch deleted file mode 100644 index 3c7ec2411b..0000000000 --- a/target/linux/mvebu/patches-5.10/003-v5.11-ARM-dts-turris-omnia-add-comphy-handle-to-eth2.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 9ec25ef84832209a8326f9a71fe3ba14f4bcf301 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Sun, 15 Nov 2020 14:59:18 +0100 -Subject: ARM: dts: turris-omnia: add comphy handle to eth2 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The eth2 controller on Turris Omnia is connected to SerDes. For SFP to -be able to switch between 1G and 2.5G modes the comphy link has to be -defined. - -Signed-off-by: Marek Behún -Fixes: f3a6a9f3704a ("ARM: dts: add description for Armada 38x ...") -Reviewed-by: Andrew Lunn -Reviewed-by: Andreas Färber -Cc: linux-arm-kernel@lists.infradead.org -Cc: Uwe Kleine-König -Cc: Jason Cooper -Cc: Gregory CLEMENT -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: Gregory CLEMENT ---- - arch/arm/boot/dts/armada-385-turris-omnia.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts -+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts -@@ -135,6 +135,7 @@ - status = "okay"; - phy-mode = "sgmii"; - phy = <&phy1>; -+ phys = <&comphy5 2>; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; diff --git a/target/linux/mvebu/patches-5.10/004-v5.11-ARM-dts-turris-omnia-describe-switch-interrupt.patch b/target/linux/mvebu/patches-5.10/004-v5.11-ARM-dts-turris-omnia-describe-switch-interrupt.patch deleted file mode 100644 index e4ecbef193..0000000000 --- a/target/linux/mvebu/patches-5.10/004-v5.11-ARM-dts-turris-omnia-describe-switch-interrupt.patch +++ /dev/null @@ -1,61 +0,0 @@ -From d29b67c220caf5f4905e1f1576e71bcb6de4af9e Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Sun, 15 Nov 2020 14:59:19 +0100 -Subject: ARM: dts: turris-omnia: describe switch interrupt -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Describe switch interrupt for Turris Omnia so that the CPU does not have -to poll the switch. We also need to to set mpp45 pin to gpio function -for this. - -Signed-off-by: Marek Behún -Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") -Cc: linux-arm-kernel@lists.infradead.org -Cc: Uwe Kleine-König -Cc: Jason Cooper -Cc: Gregory CLEMENT -Cc: Andreas Färber -Cc: Andrew Lunn -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: Gregory CLEMENT ---- - arch/arm/boot/dts/armada-385-turris-omnia.dts | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts -+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts -@@ -267,13 +267,18 @@ - - /* Switch MV88E6176 at address 0x10 */ - switch@10 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&swint_pins>; - compatible = "marvell,mv88e6085"; - #address-cells = <1>; - #size-cells = <0>; -- dsa,member = <0 0>; - -+ dsa,member = <0 0>; - reg = <0x10>; - -+ interrupt-parent = <&gpio1>; -+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>; -+ - ports { - #address-cells = <1>; - #size-cells = <0>; -@@ -336,6 +341,11 @@ - marvell,function = "gpio"; - }; - -+ swint_pins: swint-pins { -+ marvell,pins = "mpp45"; -+ marvell,function = "gpio"; -+ }; -+ - spi0cs0_pins: spi0cs0-pins { - marvell,pins = "mpp25"; - marvell,function = "spi0"; diff --git a/target/linux/mvebu/patches-5.10/005-v5.11-ARM-dts-turris-omnia-add-SFP-node.patch b/target/linux/mvebu/patches-5.10/005-v5.11-ARM-dts-turris-omnia-add-SFP-node.patch deleted file mode 100644 index db8d26d038..0000000000 --- a/target/linux/mvebu/patches-5.10/005-v5.11-ARM-dts-turris-omnia-add-SFP-node.patch +++ /dev/null @@ -1,90 +0,0 @@ -From add2d65962977caf23ca2fa21a2457d31b636574 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 16 Nov 2020 13:24:22 +0100 -Subject: ARM: dts: turris-omnia: add SFP node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Turris Omnia has an SFP cage that, together with WAN PHY, is connected -to eth2 SerDes via a SerDes multiplexor. When a SFP module is present, -the multiplexor switches the SerDes signal from PHY to SFP. - -Describe the SFP cage, but leave it disabled. Until phylink has support -for such configuration, we are leaving it to U-Boot to enable SFP and -disable WAN PHY at boot time depending on whether a SFP module is -present. - -Signed-off-by: Marek Behún -Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") -Reviewed-by: Andrew Lunn -Cc: Russell King - ARM Linux admin -Cc: linux-arm-kernel@lists.infradead.org -Cc: Uwe Kleine-König -Cc: Jason Cooper -Cc: Gregory CLEMENT -Cc: Andreas Färber -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: Gregory CLEMENT ---- - arch/arm/boot/dts/armada-385-turris-omnia.dts | 30 ++++++++++++++++++++++++++- - 1 file changed, 29 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts -+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts -@@ -88,6 +88,24 @@ - }; - }; - }; -+ -+ sfp: sfp { -+ compatible = "sff,sfp"; -+ i2c-bus = <&sfp_i2c>; -+ tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>; -+ tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>; -+ rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>; -+ los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>; -+ maximum-power-milliwatt = <3000>; -+ -+ /* -+ * For now this has to be enabled at boot time by U-Boot when -+ * a SFP module is present. Read more in the comment in the -+ * eth2 node below. -+ */ -+ status = "disabled"; -+ }; - }; - - &bm { -@@ -132,10 +150,20 @@ - - /* WAN port */ - ð2 { -+ /* -+ * eth2 is connected via a multiplexor to both the SFP cage and to -+ * ethernet-phy@1. The multiplexor switches the signal to SFP cage when -+ * a SFP module is present, as determined by the mode-def0 GPIO. -+ * -+ * Until kernel supports this configuration properly, in case SFP module -+ * is present, U-Boot has to enable the sfp node above, remove phy -+ * handle and add managed = "in-band-status" property. -+ */ - status = "okay"; - phy-mode = "sgmii"; - phy = <&phy1>; - phys = <&comphy5 2>; -+ sfp = <&sfp>; - buffer-manager = <&bm>; - bm,pool-long = <2>; - bm,pool-short = <3>; -@@ -201,7 +229,7 @@ - /* routed to PCIe2 connector (CN62A) */ - }; - -- i2c@4 { -+ sfp_i2c: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; diff --git a/target/linux/mvebu/patches-5.10/006-v5.11-ARM-dts-turris-omnia-add-LED-controller-node.patch b/target/linux/mvebu/patches-5.10/006-v5.11-ARM-dts-turris-omnia-add-LED-controller-node.patch deleted file mode 100644 index 2f9ae49669..0000000000 --- a/target/linux/mvebu/patches-5.10/006-v5.11-ARM-dts-turris-omnia-add-LED-controller-node.patch +++ /dev/null @@ -1,160 +0,0 @@ -From 91dd42d0e30fdbb250c61d1192af569f07e6ada4 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Sun, 15 Nov 2020 14:59:21 +0100 -Subject: ARM: dts: turris-omnia: add LED controller node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Linux now has incomplete support for the LED controller on Turris Omnia: -it can set brightness and colors for each LED. - -The controller can also put these LEDs into HW controlled mode, in which -the LEDs are controlled by HW: for example the WAN LED is connected via -MCU to the WAN PHY LED pin. - -The driver does not support these HW controlled modes yet, and on probe -puts the LEDs into SW controlled mode. - -Add node describing the LED controller, but disable it for now. - -Signed-off-by: Marek Behún -Cc: linux-arm-kernel@lists.infradead.org -Cc: Uwe Kleine-König -Cc: Jason Cooper -Cc: Gregory CLEMENT -Cc: Andreas Färber -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: Gregory CLEMENT ---- - arch/arm/boot/dts/armada-385-turris-omnia.dts | 111 +++++++++++++++++++++++++- - 1 file changed, 110 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts -+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts -@@ -12,6 +12,7 @@ - - #include - #include -+#include - #include "armada-385.dtsi" - - / { -@@ -187,7 +188,115 @@ - reg = <0>; - - /* STM32F0 command interface at address 0x2a */ -- /* leds device (in STM32F0) at address 0x2b */ -+ -+ led-controller@2b { -+ compatible = "cznic,turris-omnia-leds"; -+ reg = <0x2b>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* -+ * LEDs are controlled by MCU (STM32F0) at -+ * address 0x2b. -+ * -+ * The driver does not support HW control mode -+ * for the LEDs yet. Disable the LEDs for now. -+ * -+ * Also LED functions are not stable yet: -+ * - there are 3 LEDs connected via MCU to PCIe -+ * ports. One of these ports supports mSATA. -+ * There is no mSATA nor PCIe function. -+ * For now we use LED_FUNCTION_WLAN, since -+ * in most cases users have wifi cards in -+ * these slots -+ * - there are 2 LEDs dedicated for user: A and -+ * B. Again there is no such function defined. -+ * For now we use LED_FUNCTION_INDICATOR -+ */ -+ status = "disabled"; -+ -+ multi-led@0 { -+ reg = <0x0>; -+ color = ; -+ function = LED_FUNCTION_INDICATOR; -+ function-enumerator = <2>; -+ }; -+ -+ multi-led@1 { -+ reg = <0x1>; -+ color = ; -+ function = LED_FUNCTION_INDICATOR; -+ function-enumerator = <1>; -+ }; -+ -+ multi-led@2 { -+ reg = <0x2>; -+ color = ; -+ function = LED_FUNCTION_WLAN; -+ function-enumerator = <3>; -+ }; -+ -+ multi-led@3 { -+ reg = <0x3>; -+ color = ; -+ function = LED_FUNCTION_WLAN; -+ function-enumerator = <2>; -+ }; -+ -+ multi-led@4 { -+ reg = <0x4>; -+ color = ; -+ function = LED_FUNCTION_WLAN; -+ function-enumerator = <1>; -+ }; -+ -+ multi-led@5 { -+ reg = <0x5>; -+ color = ; -+ function = LED_FUNCTION_WAN; -+ }; -+ -+ multi-led@6 { -+ reg = <0x6>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <4>; -+ }; -+ -+ multi-led@7 { -+ reg = <0x7>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <3>; -+ }; -+ -+ multi-led@8 { -+ reg = <0x8>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <2>; -+ }; -+ -+ multi-led@9 { -+ reg = <0x9>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <1>; -+ }; -+ -+ multi-led@a { -+ reg = <0xa>; -+ color = ; -+ function = LED_FUNCTION_LAN; -+ function-enumerator = <0>; -+ }; -+ -+ multi-led@b { -+ reg = <0xb>; -+ color = ; -+ function = LED_FUNCTION_POWER; -+ }; -+ }; - - eeprom@54 { - compatible = "atmel,24c64"; diff --git a/target/linux/mvebu/patches-5.10/007-v5.11-ARM-dts-turris-omnia-update-ethernet-phy-node-and-handle-name.patch b/target/linux/mvebu/patches-5.10/007-v5.11-ARM-dts-turris-omnia-update-ethernet-phy-node-and-handle-name.patch deleted file mode 100644 index b20595f041..0000000000 --- a/target/linux/mvebu/patches-5.10/007-v5.11-ARM-dts-turris-omnia-update-ethernet-phy-node-and-handle-name.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 8ee4a5f4f40da60bb85e13d9dd218a3c9197e3e3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Sun, 15 Nov 2020 14:59:22 +0100 -Subject: ARM: dts: turris-omnia: update ethernet-phy node and handle name -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Use property name `phy-handle` instead of the deprecated `phy` to -connect eth2 to the PHY. -Rename the node from "phy@1" to "ethernet-phy@1", since "phy@1" is -incorrect according to device-tree bindings documentation. -Also remove the "ethernet-phy-id0141.0DD1" compatible string, it is not -needed. Kernel can read the PHY identifier itself. - -Signed-off-by: Marek Behún -Reviewed-by: Andrew Lunn -Cc: linux-arm-kernel@lists.infradead.org -Cc: Uwe Kleine-König -Cc: Jason Cooper -Cc: Gregory CLEMENT -Cc: Andreas Färber -Cc: Rob Herring -Cc: devicetree@vger.kernel.org -Signed-off-by: Gregory CLEMENT ---- - arch/arm/boot/dts/armada-385-turris-omnia.dts | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts -+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts -@@ -162,7 +162,7 @@ - */ - status = "okay"; - phy-mode = "sgmii"; -- phy = <&phy1>; -+ phy-handle = <&phy1>; - phys = <&comphy5 2>; - sfp = <&sfp>; - buffer-manager = <&bm>; -@@ -393,9 +393,9 @@ - pinctrl-0 = <&mdio_pins>; - status = "okay"; - -- phy1: phy@1 { -+ phy1: ethernet-phy@1 { - status = "okay"; -- compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22"; -+ compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - marvell,reg-init = <3 18 0 0x4985>; - diff --git a/target/linux/mvebu/patches-5.10/008-v5.12-ARM-dts-turris-omnia-fix-hardware-buffer-management.patch b/target/linux/mvebu/patches-5.10/008-v5.12-ARM-dts-turris-omnia-fix-hardware-buffer-management.patch deleted file mode 100644 index 9c49430d6f..0000000000 --- a/target/linux/mvebu/patches-5.10/008-v5.12-ARM-dts-turris-omnia-fix-hardware-buffer-management.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 5b2c7e0ae762fff2b172caf16b2766cc3e1ad859 Mon Sep 17 00:00:00 2001 -From: Rui Salvaterra -Date: Wed, 17 Feb 2021 15:30:38 +0000 -Subject: ARM: dts: turris-omnia: fix hardware buffer management -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Hardware buffer management has never worked on the Turris Omnia, as the -required MBus window hadn't been reserved. Fix thusly. - -Fixes: 018b88eee1a2 ("ARM: dts: turris-omnia: enable HW buffer management") - -Signed-off-by: Rui Salvaterra -Reviewed-by: Marek Behún -Tested-by: Klaus Kudielka -Signed-off-by: Gregory CLEMENT ---- - arch/arm/boot/dts/armada-385-turris-omnia.dts | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts -+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts -@@ -38,7 +38,8 @@ - ranges = ; -+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 -+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; - - internal-regs { - diff --git a/target/linux/mvebu/patches-5.10/100-mvebu-dt-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch b/target/linux/mvebu/patches-5.10/100-mvebu-dt-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch deleted file mode 100644 index b71dd72609..0000000000 --- a/target/linux/mvebu/patches-5.10/100-mvebu-dt-ARM-dts-turris-omnia-configure-LED-0-pin-function-to.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 81c0004a6433ff90fa6129418802c3c367e453c2 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 4 Jul 2022 13:36:21 +0200 -Subject: [PATCH] ARM: dts: turris-omnia: configure LED[0] pin function to - link/activity -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The marvell PHY driver changes the LED[0] pin function to "On - 1000 -Mbps Link, Off - Else". - -Turris Omnia expects that the function is "On - Link, Blink - Activity, -Off - No link". - -Use the `marvell,reg-init` DT property to change the function. - -In the future, once netdev trigger will support HW offloading, we will -be able to have this configured via the combination of PHY driver and -leds-turris-omnia driver. - -Signed-off-by: Marek Behún ---- - arch/arm/boot/dts/armada-385-turris-omnia.dts | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts -+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts -@@ -398,7 +398,8 @@ - status = "okay"; - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; -- marvell,reg-init = <3 18 0 0x4985>; -+ marvell,reg-init = <3 18 0 0x4985>, -+ <3 16 0xfff0 0x0001>; - - /* irq is connected to &pcawan pin 7 */ - }; diff --git a/target/linux/mvebu/patches-5.10/101-mvebu-dt-ARM-dts-turris-omnia-enable-LED-controller-node.patch b/target/linux/mvebu/patches-5.10/101-mvebu-dt-ARM-dts-turris-omnia-enable-LED-controller-node.patch deleted file mode 100644 index 8125f7a442..0000000000 --- a/target/linux/mvebu/patches-5.10/101-mvebu-dt-ARM-dts-turris-omnia-enable-LED-controller-node.patch +++ /dev/null @@ -1,48 +0,0 @@ -From fed7cef5e4f2df8c6a79bebf5da1fdd3783ff6f3 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 4 Jul 2022 13:36:22 +0200 -Subject: [PATCH] ARM: dts: turris-omnia: enable LED controller node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The LED controller node is disabled because the leds-turris-omnia driver -does not support setting the LED blinking to be controlled by the MCU. - -The patches for that have now been sent [1], so let's enable the node. - -[1] https://lore.kernel.org/linux-leds/20220704105955.15474-1-kabel@kernel.org/T/ - -Signed-off-by: Marek Behún ---- - arch/arm/boot/dts/armada-385-turris-omnia.dts | 7 ++----- - 1 file changed, 2 insertions(+), 5 deletions(-) - ---- a/arch/arm/boot/dts/armada-385-turris-omnia.dts -+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts -@@ -195,15 +195,13 @@ - reg = <0x2b>; - #address-cells = <1>; - #size-cells = <0>; -+ status = "okay"; - - /* - * LEDs are controlled by MCU (STM32F0) at - * address 0x2b. - * -- * The driver does not support HW control mode -- * for the LEDs yet. Disable the LEDs for now. -- * -- * Also LED functions are not stable yet: -+ * LED functions are not stable yet: - * - there are 3 LEDs connected via MCU to PCIe - * ports. One of these ports supports mSATA. - * There is no mSATA nor PCIe function. -@@ -214,7 +212,6 @@ - * B. Again there is no such function defined. - * For now we use LED_FUNCTION_INDICATOR - */ -- status = "disabled"; - - multi-led@0 { - reg = <0x0>; diff --git a/target/linux/mvebu/patches-5.10/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch b/target/linux/mvebu/patches-5.10/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch deleted file mode 100644 index 578124f94d..0000000000 --- a/target/linux/mvebu/patches-5.10/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 80e643510cb14f116f687e992210c0008a09d869 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 4 Jul 2022 12:59:53 +0200 -Subject: [PATCH] leds: turris-omnia: support HW controlled mode via - private trigger -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add support for enabling MCU controlled mode of the Turris Omnia LEDs -via a LED private trigger called "omnia-mcu". - -When in MCU controlled mode, the user can still set LED color, but the -blinking is done by MCU, which does different things for various LEDs: -- WAN LED is blinked according to the LED[0] pin of the WAN PHY -- LAN LEDs are blinked according to the LED[0] output of corresponding - port of the LAN switch -- PCIe LEDs are blinked according to the logical OR of the MiniPCIe port - LED pins - -For a long time I wanted to actually do this differently: I wanted to -make the netdev trigger to transparently offload the blinking to the HW -if user set compatible settings for the netdev trigger. -There was some work on this, and hopefully we will be able to complete -it sometime, but since there are various complications, it will probably -not be soon. - -In the meantime let's support HW controlled mode via this private LED -trigger. If, in the future, we manage to complete the netdev trigger -offloading, we can still keep this private trigger for backwards -compatiblity, if needed. - -We also set "omnia-mcu" to cdev->default_trigger, so that the MCU keeps -control until the user first wants to take over it. If a different -default trigger is specified in device-tree via the -`linux,default-trigger` property, LED class will overwrite -cdev->default_trigger, and so the DT property will be respected. - -Signed-off-by: Marek Behún ---- - drivers/leds/Kconfig | 1 + - drivers/leds/leds-turris-omnia.c | 41 ++++++++++++++++++++++++++++++++ - 2 files changed, 42 insertions(+) - ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -182,6 +182,7 @@ config LEDS_TURRIS_OMNIA - depends on I2C - depends on MACH_ARMADA_38X || COMPILE_TEST - depends on OF -+ select LEDS_TRIGGERS - help - This option enables basic support for the LEDs found on the front - side of CZ.NIC's Turris Omnia router. There are 12 RGB LEDs on the ---- a/drivers/leds/leds-turris-omnia.c -+++ b/drivers/leds/leds-turris-omnia.c -@@ -49,6 +49,39 @@ struct omnia_leds { - struct omnia_led leds[]; - }; - -+static struct led_hw_trigger_type omnia_hw_trigger_type; -+ -+static int omnia_hwtrig_activate(struct led_classdev *cdev) -+{ -+ struct omnia_leds *leds = dev_get_drvdata(cdev->dev->parent); -+ struct omnia_led *led = to_omnia_led(lcdev_to_mccdev(cdev)); -+ -+ /* put the LED into MCU controlled mode */ -+ return i2c_smbus_write_byte_data(leds->client, CMD_LED_MODE, -+ CMD_LED_MODE_LED(led->reg)); -+} -+ -+static void omnia_hwtrig_deactivate(struct led_classdev *cdev) -+{ -+ struct omnia_leds *leds = dev_get_drvdata(cdev->dev->parent); -+ struct omnia_led *led = to_omnia_led(lcdev_to_mccdev(cdev)); -+ int ret; -+ -+ /* put the LED into software mode */ -+ ret = i2c_smbus_write_byte_data(leds->client, CMD_LED_MODE, -+ CMD_LED_MODE_LED(led->reg) | -+ CMD_LED_MODE_USER); -+ if (ret < 0) -+ dev_err(cdev->dev, "Cannot put to software mode: %i\n", ret); -+} -+ -+static struct led_trigger omnia_hw_trigger = { -+ .name = "omnia-mcu", -+ .activate = omnia_hwtrig_activate, -+ .deactivate = omnia_hwtrig_deactivate, -+ .trigger_type = &omnia_hw_trigger_type, -+}; -+ - static int omnia_led_brightness_set_blocking(struct led_classdev *cdev, - enum led_brightness brightness) - { -@@ -120,6 +153,8 @@ static int omnia_led_register(struct i2c - cdev = &led->mc_cdev.led_cdev; - cdev->max_brightness = 255; - cdev->brightness_set_blocking = omnia_led_brightness_set_blocking; -+ cdev->trigger_type = &omnia_hw_trigger_type; -+ cdev->default_trigger = omnia_hw_trigger.name; - - /* put the LED into software mode */ - ret = i2c_smbus_write_byte_data(client, CMD_LED_MODE, -@@ -231,6 +266,12 @@ static int omnia_leds_probe(struct i2c_c - - mutex_init(&leds->lock); - -+ ret = devm_led_trigger_register(dev, &omnia_hw_trigger); -+ if (ret < 0) { -+ dev_err(dev, "Cannot register private LED trigger: %d\n", ret); -+ return ret; -+ } -+ - led = &leds->leds[0]; - for_each_available_child_of_node(np, child) { - ret = omnia_led_register(client, led, child); diff --git a/target/linux/mvebu/patches-5.10/103-leds-turris-omnia-initialize-multi-intensity-to-full.patch b/target/linux/mvebu/patches-5.10/103-leds-turris-omnia-initialize-multi-intensity-to-full.patch deleted file mode 100644 index 6f9aaf11db..0000000000 --- a/target/linux/mvebu/patches-5.10/103-leds-turris-omnia-initialize-multi-intensity-to-full.patch +++ /dev/null @@ -1,33 +0,0 @@ -From bda176cceb735b9b46c1900658b6486c34e13ae6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 4 Jul 2022 12:59:54 +0200 -Subject: [PATCH] leds: turris-omnia: initialize multi-intensity to full -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The default color of each LED before driver probe (255, 255, 255). -Initialize multi_intensity to this value, so that it corresponds to the -reality. - -Signed-off-by: Marek Behún ---- - drivers/leds/leds-turris-omnia.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/leds/leds-turris-omnia.c -+++ b/drivers/leds/leds-turris-omnia.c -@@ -139,10 +139,13 @@ static int omnia_led_register(struct i2c - } - - led->subled_info[0].color_index = LED_COLOR_ID_RED; -+ led->subled_info[0].intensity = 255; - led->subled_info[0].channel = 0; - led->subled_info[1].color_index = LED_COLOR_ID_GREEN; -+ led->subled_info[1].intensity = 255; - led->subled_info[1].channel = 1; - led->subled_info[2].color_index = LED_COLOR_ID_BLUE; -+ led->subled_info[2].intensity = 255; - led->subled_info[2].channel = 2; - - led->mc_cdev.subled_info = led->subled_info; diff --git a/target/linux/mvebu/patches-5.10/104-leds-turris-omnia-change-max-brightness-from-255-to-.patch b/target/linux/mvebu/patches-5.10/104-leds-turris-omnia-change-max-brightness-from-255-to-.patch deleted file mode 100644 index da4ad49b23..0000000000 --- a/target/linux/mvebu/patches-5.10/104-leds-turris-omnia-change-max-brightness-from-255-to-.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 349cbe949b9622cc05b148ecfa6268cbbae35b45 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= -Date: Mon, 4 Jul 2022 12:59:55 +0200 -Subject: [PATCH] leds: turris-omnia: change max brightness from 255 to 1 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Using binary brightness makes more sense for this controller, because -internally in the MCU it works that way: the LED has a color, and a -state whether it is ON or OFF. - -The resulting brightness computation with led_mc_calc_color_components() -will now always result in either (0, 0, 0) or the multi_intensity value. - -Signed-off-by: Marek Behún ---- - drivers/leds/leds-turris-omnia.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/leds/leds-turris-omnia.c -+++ b/drivers/leds/leds-turris-omnia.c -@@ -154,7 +154,7 @@ static int omnia_led_register(struct i2c - init_data.fwnode = &np->fwnode; - - cdev = &led->mc_cdev.led_cdev; -- cdev->max_brightness = 255; -+ cdev->max_brightness = 1; - cdev->brightness_set_blocking = omnia_led_brightness_set_blocking; - cdev->trigger_type = &omnia_hw_trigger_type; - cdev->default_trigger = omnia_hw_trigger.name; diff --git a/target/linux/mvebu/patches-5.10/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-5.10/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch deleted file mode 100644 index 04c80113c1..0000000000 --- a/target/linux/mvebu/patches-5.10/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch +++ /dev/null @@ -1,208 +0,0 @@ -From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 -From: Adrian Panella -Date: Thu, 9 Mar 2017 09:37:17 +0100 -Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments - -The command-line arguments provided by the boot loader will be -appended to a new device tree property: bootloader-args. -If there is a property "append-rootblock" in DT under /chosen -and a root= option in bootloaders command line it will be parsed -and added to DT bootargs with the form: XX. -Only command line ATAG will be processed, the rest of the ATAGs -sent by bootloader will be ignored. -This is usefull in dual boot systems, to get the current root partition -without afecting the rest of the system. - -Signed-off-by: Adrian Panella - -This patch has been modified to be mvebu specific. The original patch -did not pass the bootloader cmdline on if no append-rootblock stanza -was found, resulting in blank cmdline and failure to boot. - -Signed-off-by: Michael Gray ---- - arch/arm/Kconfig | 11 ++++ - arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++- - init/main.c | 16 +++++ - 3 files changed, 111 insertions(+), 1 deletion(-) - ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1777,6 +1777,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - The command-line arguments provided by the boot loader will be - appended to the the device tree bootargs property. - -+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ bool "Append rootblock parsing bootloader's kernel arguments" -+ help -+ The command-line arguments provided by the boot loader will be -+ appended to a new device tree property: bootloader-args. -+ If there is a property "append-rootblock" in DT under /chosen -+ and a root= option in bootloaders command line it will be parsed -+ and added to DT bootargs with the form: XX. -+ Only command line ATAG will be processed, the rest of the ATAGs -+ sent by bootloader will be ignored. -+ - endchoice - - config CMDLINE ---- a/arch/arm/boot/compressed/atags_to_fdt.c -+++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -5,6 +5,8 @@ - - #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) - #define do_extend_cmdline 1 -+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#define do_extend_cmdline 1 - #else - #define do_extend_cmdline 0 - #endif -@@ -69,6 +71,72 @@ static uint32_t get_cell_size(const void - return cell_size; - } - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ -+static char *append_rootblock(char *dest, const char *str, int len, void *fdt) -+{ -+ char *ptr, *end; -+ char *root="root="; -+ int i, l; -+ const char *rootblock; -+ -+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually -+ ptr = str - 1; -+ -+ do { -+ //first find an 'r' at the begining or after a space -+ do { -+ ptr++; -+ ptr = strchr(ptr, 'r'); -+ if (!ptr) -+ goto no_append; -+ -+ } while (ptr != str && *(ptr-1) != ' '); -+ -+ //then check for the rest -+ for(i = 1; i <= 4; i++) -+ if(*(ptr+i) != *(root+i)) break; -+ -+ } while (i != 5); -+ -+ end = strchr(ptr, ' '); -+ end = end ? (end - 1) : (strchr(ptr, 0) - 1); -+ -+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX ) -+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); -+ ptr = end + 1; -+ -+ /* if append-rootblock property is set use it to append to command line */ -+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); -+ if (rootblock == NULL) -+ goto no_append; -+ -+ if (*dest != ' ') { -+ *dest = ' '; -+ dest++; -+ len++; -+ } -+ -+ if (len + l + i <= COMMAND_LINE_SIZE) { -+ memcpy(dest, rootblock, l); -+ dest += l - 1; -+ memcpy(dest, ptr, i); -+ dest += i; -+ } -+ -+ return dest; -+ -+no_append: -+ len = strlen(str); -+ if (len + 1 < COMMAND_LINE_SIZE) { -+ memcpy(dest, str, len); -+ dest += len; -+ } -+ -+ return dest; -+} -+#endif -+ - static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) - { - char cmdline[COMMAND_LINE_SIZE]; -@@ -88,12 +156,21 @@ static void merge_fdt_bootargs(void *fdt - - /* and append the ATAG_CMDLINE */ - if (fdt_cmdline) { -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //save original bootloader args -+ //and append ubi.mtd with root partition number to current cmdline -+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); -+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); -+ -+#else - len = strlen(fdt_cmdline); - if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { - *ptr++ = ' '; - memcpy(ptr, fdt_cmdline, len); - ptr += len; - } -+#endif - } - *ptr = '\0'; - -@@ -168,7 +245,9 @@ int atags_to_fdt(void *atag_list, void * - else - setprop_string(fdt, "/chosen", "bootargs", - atag->u.cmdline.cmdline); -- } else if (atag->hdr.tag == ATAG_MEM) { -+ } -+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE -+ else if (atag->hdr.tag == ATAG_MEM) { - if (memcount >= sizeof(mem_reg_property)/4) - continue; - if (!atag->u.mem.size) -@@ -212,6 +291,10 @@ int atags_to_fdt(void *atag_list, void * - setprop(fdt, "/memory", "reg", mem_reg_property, - 4 * memcount * memsize); - } -+#else -+ -+ } -+#endif - - return fdt_pack(fdt); - } ---- a/init/main.c -+++ b/init/main.c -@@ -110,6 +110,10 @@ - - #include - -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+#include -+#endif -+ - static int kernel_init(void *); - - extern void init_IRQ(void); -@@ -904,6 +908,18 @@ asmlinkage __visible void __init __no_sa - page_alloc_init(); - - pr_notice("Kernel command line: %s\n", saved_command_line); -+ -+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) -+ //Show bootloader's original command line for reference -+ if(of_chosen) { -+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); -+ if(prop) -+ pr_notice("Bootloader command line (ignored): %s\n", prop); -+ else -+ pr_notice("Bootloader command line not present\n"); -+ } -+#endif -+ - /* parameters may set static keys */ - jump_label_init(); - parse_early_param(); diff --git a/target/linux/mvebu/patches-5.10/301-mvebu-armada-38x-enable-libata-leds.patch b/target/linux/mvebu/patches-5.10/301-mvebu-armada-38x-enable-libata-leds.patch deleted file mode 100644 index 615caac24f..0000000000 --- a/target/linux/mvebu/patches-5.10/301-mvebu-armada-38x-enable-libata-leds.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/mach-mvebu/Kconfig -+++ b/arch/arm/mach-mvebu/Kconfig -@@ -67,6 +67,7 @@ config MACH_ARMADA_38X - select HAVE_ARM_TWD if SMP - select MACH_MVEBU_V7 - select PINCTRL_ARMADA_38X -+ select ARCH_WANT_LIBATA_LEDS - help - Say 'Y' here if you want your kernel to support boards based - on the Marvell Armada 380/385 SoC with device tree. diff --git a/target/linux/mvebu/patches-5.10/302-add_powertables.patch b/target/linux/mvebu/patches-5.10/302-add_powertables.patch deleted file mode 100644 index efbbbc7d78..0000000000 --- a/target/linux/mvebu/patches-5.10/302-add_powertables.patch +++ /dev/null @@ -1,770 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -212,11 +212,19 @@ - &pcie1 { - /* Marvell 88W8864, 5GHz-only */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,2ghz = <0>; -+ }; - }; - - &pcie2 { - /* Marvell 88W8864, 2GHz-only */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,5ghz = <0>; -+ }; - }; - - &pinctrl { ---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts -@@ -142,3 +142,205 @@ - }; - }; - }; -+ -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <2 2>; -+ marvell,powertable { -+ AU = -+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>, -+ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>, -+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>; 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-+ CN = -+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>; -+ ETSI = -+ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>, -+ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>; -+ FCC = -+ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>, -+ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>; -+ }; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <2 2>; -+ marvell,powertable { -+ AU = -+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; -+ CA = -+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>, -+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>, -+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>; -+ CN = -+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; -+ ETSI = -+ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>; -+ FCC = -+ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts -@@ -142,3 +142,205 @@ - }; - }; - }; -+ -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>; -+ CA = -+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ CN = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>; -+ ETSI = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>; -+ FCC = -+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>, -+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ }; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ CA = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ CN = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ ETSI = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ FCC = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts -@@ -142,3 +142,205 @@ - }; - }; - }; -+ -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>, -+ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>; -+ CA = -+ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ CN = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>, -+ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>; -+ ETSI = -+ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>, -+ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>; -+ FCC = -+ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>, -+ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>, -+ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>, -+ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>, -+ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>; -+ }; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ AU = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ CA = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ CN = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ ETSI = -+ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>; -+ FCC = -+ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; -+}; ---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts -@@ -157,6 +157,18 @@ - }; - }; - -+&pcie1 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ }; -+}; -+ -+&pcie2 { -+ mwlwifi { -+ marvell,chainmask = <4 4>; -+ }; -+}; -+ - &sdhci { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci_pins>; ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -225,12 +225,100 @@ - pcie@2,0 { - /* Port 0, Lane 1 */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,5ghz = <0>; -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ FCC = -+ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>; -+ -+ ETSI = -+ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>, -+ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>; -+ }; -+ }; - }; - - /* Second mini-PCIe port */ - pcie@3,0 { - /* Port 0, Lane 3 */ - status = "okay"; -+ -+ mwlwifi { -+ marvell,2ghz = <0>; -+ marvell,chainmask = <4 4>; -+ marvell,powertable { -+ FCC = -+ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>, -+ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>, -+ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>, -+ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>, -+ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>; -+ -+ ETSI = -+ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>, -+ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>; -+ }; -+ }; - }; - }; - diff --git a/target/linux/mvebu/patches-5.10/303-linksys_hardcode_nand_ecc_settings.patch b/target/linux/mvebu/patches-5.10/303-linksys_hardcode_nand_ecc_settings.patch deleted file mode 100644 index 89a5e19803..0000000000 --- a/target/linux/mvebu/patches-5.10/303-linksys_hardcode_nand_ecc_settings.patch +++ /dev/null @@ -1,17 +0,0 @@ -Newer Linksys boards might come with a Winbond W29N02GV which can be -configured in different ways. Make sure we configure it the same way -as the older chips so everything keeps working. - -Signed-off-by: Imre Kaloz - ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -148,6 +148,8 @@ - reg = <0>; - label = "pxa3xx_nand-0"; - nand-rb = <0>; -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; - marvell,nand-keep-config; - nand-on-flash-bbt; - }; diff --git a/target/linux/mvebu/patches-5.10/304-revert_i2c_delay.patch b/target/linux/mvebu/patches-5.10/304-revert_i2c_delay.patch deleted file mode 100644 index 930c0f9494..0000000000 --- a/target/linux/mvebu/patches-5.10/304-revert_i2c_delay.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp.dtsi -+++ b/arch/arm/boot/dts/armada-xp.dtsi -@@ -237,12 +237,10 @@ - }; - - &i2c0 { -- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - &i2c1 { -- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - diff --git a/target/linux/mvebu/patches-5.10/305-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-5.10/305-armada-385-rd-mtd-partitions.patch deleted file mode 100644 index 31bd53b1f3..0000000000 --- a/target/linux/mvebu/patches-5.10/305-armada-385-rd-mtd-partitions.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/arch/arm/boot/dts/armada-388-rd.dts -+++ b/arch/arm/boot/dts/armada-388-rd.dts -@@ -103,6 +103,16 @@ - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; -+ -+ partition@0 { -+ label = "uboot"; -+ reg = <0 0x400000>; -+ }; -+ -+ partition@1 { -+ label = "firmware"; -+ reg = <0x400000 0xc00000>; -+ }; - }; - }; - diff --git a/target/linux/mvebu/patches-5.10/306-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-5.10/306-ARM-mvebu-385-ap-Add-partitions.patch deleted file mode 100644 index 2057e31c7e..0000000000 --- a/target/linux/mvebu/patches-5.10/306-ARM-mvebu-385-ap-Add-partitions.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Tue, 13 Jan 2015 11:14:09 +0100 -Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions - -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++ - 1 file changed, 15 insertions(+) - ---- a/arch/arm/boot/dts/armada-385-db-ap.dts -+++ b/arch/arm/boot/dts/armada-385-db-ap.dts -@@ -218,19 +218,19 @@ - #size-cells = <1>; - - partition@0 { -- label = "U-Boot"; -+ label = "u-boot"; - reg = <0x00000000 0x00800000>; - read-only; - }; - - partition@800000 { -- label = "uImage"; -+ label = "kernel"; - reg = <0x00800000 0x00400000>; - read-only; - }; - - partition@c00000 { -- label = "Root"; -+ label = "ubi"; - reg = <0x00c00000 0x3f400000>; - }; - }; diff --git a/target/linux/mvebu/patches-5.10/307-armada-xp-linksys-mamba-broken-idle.patch b/target/linux/mvebu/patches-5.10/307-armada-xp-linksys-mamba-broken-idle.patch deleted file mode 100644 index 16112d53fc..0000000000 --- a/target/linux/mvebu/patches-5.10/307-armada-xp-linksys-mamba-broken-idle.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -485,3 +485,7 @@ - }; - }; - }; -+ -+&coherencyfab { -+ broken-idle; -+}; diff --git a/target/linux/mvebu/patches-5.10/308-armada-xp-linksys-mamba-wan.patch b/target/linux/mvebu/patches-5.10/308-armada-xp-linksys-mamba-wan.patch deleted file mode 100644 index 4315abc7d2..0000000000 --- a/target/linux/mvebu/patches-5.10/308-armada-xp-linksys-mamba-wan.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -387,7 +387,7 @@ - - port@4 { - reg = <4>; -- label = "internet"; -+ label = "wan"; - }; - - port@5 { diff --git a/target/linux/mvebu/patches-5.10/309-linksys-status-led.patch b/target/linux/mvebu/patches-5.10/309-linksys-status-led.patch deleted file mode 100644 index e5e83572c9..0000000000 --- a/target/linux/mvebu/patches-5.10/309-linksys-status-led.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -14,6 +14,13 @@ - compatible = "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - -+ aliases { -+ led-boot = &led_power; -+ led-failsafe = &led_power; -+ led-running = &led_power; -+ led-upgrade = &led_power; -+ }; -+ - chosen { - stdout-path = "serial0:115200n8"; - }; -@@ -71,7 +78,7 @@ - pinctrl-0 = <&gpio_leds_pins>; - pinctrl-names = "default"; - -- power { -+ led_power: power { - gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -26,6 +26,13 @@ - compatible = "linksys,mamba", "marvell,armadaxp-mv78230", - "marvell,armadaxp", "marvell,armada-370-xp"; - -+ aliases { -+ led-boot = &led_power; -+ led-failsafe = &led_power; -+ led-running = &led_power; -+ led-upgrade = &led_power; -+ }; -+ - chosen { - bootargs = "console=ttyS0,115200"; - stdout-path = &uart0; -@@ -197,7 +204,7 @@ - pinctrl-0 = <&power_led_pin>; - pinctrl-names = "default"; - -- power { -+ led_power: power { - label = "mamba:white:power"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "on"; diff --git a/target/linux/mvebu/patches-5.10/310-linksys-use-eth0-as-cpu-port.patch b/target/linux/mvebu/patches-5.10/310-linksys-use-eth0-as-cpu-port.patch deleted file mode 100644 index 84d49a004b..0000000000 --- a/target/linux/mvebu/patches-5.10/310-linksys-use-eth0-as-cpu-port.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys.dtsi -+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi -@@ -116,7 +116,7 @@ - }; - - ð2 { -- status = "okay"; -+ status = "disabled"; - phy-mode = "sgmii"; - buffer-manager = <&bm>; - bm,pool-long = <2>; -@@ -200,10 +200,10 @@ - label = "wan"; - }; - -- port@5 { -- reg = <5>; -+ port@6 { -+ reg = <6>; - label = "cpu"; -- ethernet = <ð2>; -+ ethernet = <ð0>; - - fixed-link { - speed = <1000>; diff --git a/target/linux/mvebu/patches-5.10/311-adjust-compatible-for-linksys.patch b/target/linux/mvebu/patches-5.10/311-adjust-compatible-for-linksys.patch deleted file mode 100644 index a5d3e63810..0000000000 --- a/target/linux/mvebu/patches-5.10/311-adjust-compatible-for-linksys.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- a/arch/arm/boot/dts/armada-385-linksys-rango.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts -@@ -12,8 +12,8 @@ - - / { - model = "Linksys WRT3200ACM"; -- compatible = "linksys,rango", "linksys,armada385", "marvell,armada385", -- "marvell,armada380"; -+ compatible = "linksys,wrt3200acm", "linksys,rango", "linksys,armada385", -+ "marvell,armada385", "marvell,armada380"; - }; - - &expander0 { ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -22,9 +22,10 @@ - #include "armada-xp-mv78230.dtsi" - - / { -- model = "Linksys WRT1900AC"; -- compatible = "linksys,mamba", "marvell,armadaxp-mv78230", -- "marvell,armadaxp", "marvell,armada-370-xp"; -+ model = "Linksys WRT1900AC v1"; -+ compatible = "linksys,wrt1900ac-v1", "linksys,mamba", -+ "marvell,armadaxp-mv78230", "marvell,armadaxp", -+ "marvell,armada-370-xp"; - - aliases { - led-boot = &led_power; ---- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts -@@ -9,8 +9,9 @@ - #include "armada-385-linksys.dtsi" - - / { -- model = "Linksys WRT1900ACv2"; -- compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385", -+ model = "Linksys WRT1900AC v2"; -+ compatible = "linksys,wrt1900ac-v2", "linksys,cobra", -+ "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - }; - ---- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts -@@ -10,8 +10,8 @@ - - / { - model = "Linksys WRT1200AC"; -- compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385", -- "marvell,armada380"; -+ compatible = "linksys,wrt1200ac", "linksys,caiman", "linksys,armada385", -+ "marvell,armada385", "marvell,armada380"; - }; - - &expander0 { ---- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts -+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts -@@ -10,7 +10,8 @@ - - / { - model = "Linksys WRT1900ACS"; -- compatible = "linksys,shelby", "linksys,armada385", "marvell,armada385", -+ compatible = "linksys,wrt1900acs", "linksys,shelby", -+ "linksys,armada385", "marvell,armada385", - "marvell,armada380"; - }; - diff --git a/target/linux/mvebu/patches-5.10/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/target/linux/mvebu/patches-5.10/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch deleted file mode 100644 index dd2bef7f63..0000000000 --- a/target/linux/mvebu/patches-5.10/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Tue, 29 Nov 2016 10:15:45 +0000 -Subject: ARM: dts: armada388-clearfog: emmc on clearfog base - -Signed-off-by: Russell King ---- - arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 + - .../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++ - 2 files changed, 63 insertions(+) - create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi - ---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts -+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts -@@ -7,6 +7,7 @@ - - /dts-v1/; - #include "armada-388-clearfog.dtsi" -+#include "armada-38x-solidrun-microsom-emmc.dtsi" - - / { - model = "SolidRun Clearfog Base A1"; ---- /dev/null -+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi -@@ -0,0 +1,62 @@ -+/* -+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC -+ * -+ * Copyright (C) 2015 Russell King -+ * -+ * This board is in development; the contents of this file work with -+ * the A1 rev 2.0 of the board, which does not represent final -+ * production board. Things will change, don't expect this file to -+ * remain compatible info the future. -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+/ { -+ soc { -+ internal-regs { -+ sdhci@d8000 { -+ bus-width = <4>; -+ no-1-8-v; -+ non-removable; -+ pinctrl-0 = <µsom_sdhci_pins>; -+ pinctrl-names = "default"; -+ status = "okay"; -+ wp-inverted; -+ }; -+ }; -+ }; -+}; diff --git a/target/linux/mvebu/patches-5.10/313-helios4-dts-status-led-alias.patch b/target/linux/mvebu/patches-5.10/313-helios4-dts-status-led-alias.patch deleted file mode 100644 index 607f436297..0000000000 --- a/target/linux/mvebu/patches-5.10/313-helios4-dts-status-led-alias.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/arch/arm/boot/dts/armada-388-helios4.dts -+++ b/arch/arm/boot/dts/armada-388-helios4.dts -@@ -15,6 +15,13 @@ - model = "Helios4"; - compatible = "kobol,helios4", "marvell,armada388", - "marvell,armada385", "marvell,armada380"; -+ -+ aliases { -+ led-boot = &led_status; -+ led-failsafe = &led_status; -+ led-running = &led_status; -+ led-upgrade = &led_status; -+ }; - - memory { - device_type = "memory"; -@@ -73,10 +80,9 @@ - pinctrl-names = "default"; - pinctrl-0 = <&helios_system_led_pins>; - -- status-led { -+ led_status: status-led { - label = "helios4:green:status"; - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; -- linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - diff --git a/target/linux/mvebu/patches-5.10/315-armada-xp-linksys-mamba-resize-kernel.patch b/target/linux/mvebu/patches-5.10/315-armada-xp-linksys-mamba-resize-kernel.patch deleted file mode 100644 index f1fddceff4..0000000000 --- a/target/linux/mvebu/patches-5.10/315-armada-xp-linksys-mamba-resize-kernel.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 258233f00bcd013050efee00c5d9128ef8cd62dd Mon Sep 17 00:00:00 2001 -From: Tad -Date: Fri, 5 Feb 2021 22:32:11 -0500 -Subject: [PATCH] ARM: dts: armada-xp-linksys-mamba: Increase kernel - partition to 4MB - -Signed-off-by: Tad Davanzo ---- - arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts -@@ -456,9 +456,9 @@ - reg = <0xa00000 0x2800000>; /* 40MB */ - }; - -- partition@d00000 { -+ partition@e00000 { - label = "rootfs1"; -- reg = <0xd00000 0x2500000>; /* 37MB */ -+ reg = <0xe00000 0x2400000>; /* 36MB */ - }; - - /* kernel2 overlaps with rootfs2 by design */ -@@ -467,9 +467,9 @@ - reg = <0x3200000 0x2800000>; /* 40MB */ - }; - -- partition@3500000 { -+ partition@3600000 { - label = "rootfs2"; -- reg = <0x3500000 0x2500000>; /* 37MB */ -+ reg = <0x3600000 0x2400000>; /* 36MB */ - }; - - /* diff --git a/target/linux/mvebu/patches-5.10/316-armada-370-dts-fix-crypto-engine.patch b/target/linux/mvebu/patches-5.10/316-armada-370-dts-fix-crypto-engine.patch deleted file mode 100644 index 19378870ef..0000000000 --- a/target/linux/mvebu/patches-5.10/316-armada-370-dts-fix-crypto-engine.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/arm/boot/dts/armada-370.dtsi -+++ b/arch/arm/boot/dts/armada-370.dtsi -@@ -234,7 +234,7 @@ - clocks = <&gateclk 23>; - clock-names = "cesa0"; - marvell,crypto-srams = <&crypto_sram>; -- marvell,crypto-sram-size = <0x7e0>; -+ marvell,crypto-sram-size = <0x800>; - }; - }; - -@@ -255,12 +255,17 @@ - * cpuidle workaround. - */ - idle-sram@0 { -+ status = "disabled"; - reg = <0x0 0x20>; - }; - }; - }; - }; - -+&coherencyfab { -+ broken-idle; -+}; -+ - /* - * Default UART pinctrl setting without RTS/CTS, can be overwritten on - * board level if a different configuration is used. diff --git a/target/linux/mvebu/patches-5.10/400-find_active_root.patch b/target/linux/mvebu/patches-5.10/400-find_active_root.patch deleted file mode 100644 index 5582d20c68..0000000000 --- a/target/linux/mvebu/patches-5.10/400-find_active_root.patch +++ /dev/null @@ -1,60 +0,0 @@ -The WRT1900AC among other Linksys routers uses a dual-firmware layout. -Dynamically rename the active partition to "ubi". - -Signed-off-by: Imre Kaloz - ---- a/drivers/mtd/parsers/ofpart_core.c -+++ b/drivers/mtd/parsers/ofpart_core.c -@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d - return of_get_property(pp, "compatible", NULL); - } - -+static int mangled_rootblock; -+ - static int parse_fixed_partitions(struct mtd_info *master, - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) -@@ -48,6 +50,7 @@ static int parse_fixed_partitions(struct - struct device_node *mtd_node; - struct device_node *ofpart_node; - const char *partname; -+ const char *owrtpart = "ubi"; - struct device_node *pp; - int nr_parts, i, ret = 0; - bool dedicated = true; -@@ -133,9 +136,13 @@ static int parse_fixed_partitions(struct - parts[i].size = of_read_number(reg + a_cells, s_cells); - parts[i].of_node = pp; - -- partname = of_get_property(pp, "label", &len); -- if (!partname) -- partname = of_get_property(pp, "name", &len); -+ if (mangled_rootblock && (i == mangled_rootblock)) { -+ partname = owrtpart; -+ } else { -+ partname = of_get_property(pp, "label", &len); -+ if (!partname) -+ partname = of_get_property(pp, "name", &len); -+ } - parts[i].name = partname; - - if (of_get_property(pp, "read-only", &len)) -@@ -252,6 +259,18 @@ static int __init ofpart_parser_init(voi - return 0; - } - -+static int __init active_root(char *str) -+{ -+ get_option(&str, &mangled_rootblock); -+ -+ if (!mangled_rootblock) -+ return 1; -+ -+ return 1; -+} -+ -+__setup("mangled_rootblock=", active_root); -+ - static void __exit ofpart_parser_exit(void) - { - deregister_mtd_parser(&ofpart_parser); diff --git a/target/linux/mvebu/patches-5.10/700-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-5.10/700-mvneta-tx-queue-workaround.patch deleted file mode 100644 index a0f15681f5..0000000000 --- a/target/linux/mvebu/patches-5.10/700-mvneta-tx-queue-workaround.patch +++ /dev/null @@ -1,38 +0,0 @@ -The hardware queue scheduling is apparently configured with fixed -priorities, which creates a nasty fairness issue where traffic from one -CPU can starve traffic from all other CPUs. - -Work around this issue by forcing all tx packets to go through one CPU, -until this issue is fixed properly. - -Signed-off-by: Felix Fietkau ---- ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -4903,6 +4903,16 @@ static int mvneta_ethtool_set_eee(struct - return phylink_ethtool_set_eee(pp->phylink, eee); - } - -+#ifndef CONFIG_ARM64 -+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb, -+ struct net_device *sb_dev) -+{ -+ /* XXX: hardware queue scheduling is broken, -+ * use only one queue until it is fixed */ -+ return 0; -+} -+#endif -+ - static const struct net_device_ops mvneta_netdev_ops = { - .ndo_open = mvneta_open, - .ndo_stop = mvneta_stop, -@@ -4913,6 +4923,9 @@ static const struct net_device_ops mvnet - .ndo_fix_features = mvneta_fix_features, - .ndo_get_stats64 = mvneta_get_stats64, - .ndo_do_ioctl = mvneta_ioctl, -+#ifndef CONFIG_ARM64 -+ .ndo_select_queue = mvneta_select_queue, -+#endif - .ndo_bpf = mvneta_xdp, - .ndo_xdp_xmit = mvneta_xdp_xmit, - }; diff --git a/target/linux/mvebu/patches-5.10/701-v5.14-net-ethernet-marvell-mvnetaMQPrio.patch b/target/linux/mvebu/patches-5.10/701-v5.14-net-ethernet-marvell-mvnetaMQPrio.patch deleted file mode 100644 index 36d4942f8b..0000000000 --- a/target/linux/mvebu/patches-5.10/701-v5.14-net-ethernet-marvell-mvnetaMQPrio.patch +++ /dev/null @@ -1,109 +0,0 @@ -From 4906887a8ae5f1296f8079bcf4565a6092a8e402 Mon Sep 17 00:00:00 2001 -From: Maxime Chevallier -Date: Tue, 16 Feb 2021 10:25:36 +0100 -Subject: net: mvneta: Implement mqprio support - -Implement a basic MQPrio support, inserting rules in RX that translate -the TC to prio mapping into vlan prio to queues. - -The TX logic stays the same as when we don't offload the qdisc. - -Signed-off-by: Maxime Chevallier -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/marvell/mvneta.c | 61 +++++++++++++++++++++++++++++++++++ - 1 file changed, 61 insertions(+) - -(limited to 'drivers/net/ethernet/marvell/mvneta.c') - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -102,6 +102,8 @@ - #define MVNETA_TX_NO_DATA_SWAP BIT(5) - #define MVNETA_DESC_SWAP BIT(6) - #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) -+#define MVNETA_VLAN_PRIO_TO_RXQ 0x2440 -+#define MVNETA_VLAN_PRIO_RXQ_MAP(prio, rxq) ((rxq) << ((prio) * 3)) - #define MVNETA_PORT_STATUS 0x2444 - #define MVNETA_TX_IN_PRGRS BIT(0) - #define MVNETA_TX_FIFO_EMPTY BIT(8) -@@ -490,6 +492,7 @@ struct mvneta_port { - u8 mcast_count[256]; - u16 tx_ring_size; - u16 rx_ring_size; -+ u8 prio_tc_map[8]; - - phy_interface_t phy_interface; - struct device_node *dn; -@@ -4913,6 +4916,63 @@ static u16 mvneta_select_queue(struct ne - } - #endif - -+static void mvneta_clear_rx_prio_map(struct mvneta_port *pp) -+{ -+ mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0); -+} -+ -+static void mvneta_setup_rx_prio_map(struct mvneta_port *pp) -+{ -+ u32 val = 0; -+ int i; -+ -+ for (i = 0; i < rxq_number; i++) -+ val |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]); -+ -+ mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val); -+} -+ -+static int mvneta_setup_mqprio(struct net_device *dev, -+ struct tc_mqprio_qopt *qopt) -+{ -+ struct mvneta_port *pp = netdev_priv(dev); -+ u8 num_tc; -+ int i; -+ -+ qopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS; -+ num_tc = qopt->num_tc; -+ -+ if (num_tc > rxq_number) -+ return -EINVAL; -+ -+ if (!num_tc) { -+ mvneta_clear_rx_prio_map(pp); -+ netdev_reset_tc(dev); -+ return 0; -+ } -+ -+ memcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map)); -+ -+ mvneta_setup_rx_prio_map(pp); -+ -+ netdev_set_num_tc(dev, qopt->num_tc); -+ for (i = 0; i < qopt->num_tc; i++) -+ netdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]); -+ -+ return 0; -+} -+ -+static int mvneta_setup_tc(struct net_device *dev, enum tc_setup_type type, -+ void *type_data) -+{ -+ switch (type) { -+ case TC_SETUP_QDISC_MQPRIO: -+ return mvneta_setup_mqprio(dev, type_data); -+ default: -+ return -EOPNOTSUPP; -+ } -+} -+ - static const struct net_device_ops mvneta_netdev_ops = { - .ndo_open = mvneta_open, - .ndo_stop = mvneta_stop, -@@ -4928,6 +4988,7 @@ static const struct net_device_ops mvnet - #endif - .ndo_bpf = mvneta_xdp, - .ndo_xdp_xmit = mvneta_xdp_xmit, -+ .ndo_setup_tc = mvneta_setup_tc, - }; - - static const struct ethtool_ops mvneta_eth_tool_ops = { diff --git a/target/linux/mvebu/patches-5.10/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch b/target/linux/mvebu/patches-5.10/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch deleted file mode 100644 index 41f8c1fbfd..0000000000 --- a/target/linux/mvebu/patches-5.10/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 75fa71e3acadbb4ab5eda18505277eb9a1f69b23 Mon Sep 17 00:00:00 2001 -From: Maxime Chevallier -Date: Fri, 26 Nov 2021 12:20:53 +0100 -Subject: net: mvneta: Use struct tc_mqprio_qopt_offload for MQPrio - configuration - -The struct tc_mqprio_qopt_offload is a container for struct tc_mqprio_qopt, -that allows passing extra parameters, such as traffic shaping. This commit -converts the current mqprio code to that new struct. - -Signed-off-by: Maxime Chevallier -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/marvell/mvneta.c | 17 ++++++++++------- - 1 file changed, 10 insertions(+), 7 deletions(-) - -(limited to 'drivers/net/ethernet/marvell/mvneta.c') - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -38,6 +38,7 @@ - #include - #include - #include -+#include - #include - - /* Registers */ -@@ -4933,14 +4934,14 @@ static void mvneta_setup_rx_prio_map(str - } - - static int mvneta_setup_mqprio(struct net_device *dev, -- struct tc_mqprio_qopt *qopt) -+ struct tc_mqprio_qopt_offload *mqprio) - { - struct mvneta_port *pp = netdev_priv(dev); - u8 num_tc; - int i; - -- qopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS; -- num_tc = qopt->num_tc; -+ mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS; -+ num_tc = mqprio->qopt.num_tc; - - if (num_tc > rxq_number) - return -EINVAL; -@@ -4951,13 +4952,15 @@ static int mvneta_setup_mqprio(struct ne - return 0; - } - -- memcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map)); -+ memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map, -+ sizeof(pp->prio_tc_map)); - - mvneta_setup_rx_prio_map(pp); - -- netdev_set_num_tc(dev, qopt->num_tc); -- for (i = 0; i < qopt->num_tc; i++) -- netdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]); -+ netdev_set_num_tc(dev, mqprio->qopt.num_tc); -+ for (i = 0; i < mqprio->qopt.num_tc; i++) -+ netdev_set_tc_queue(dev, i, mqprio->qopt.count[i], -+ mqprio->qopt.offset[i]); - - return 0; - } diff --git a/target/linux/mvebu/patches-5.10/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch b/target/linux/mvebu/patches-5.10/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch deleted file mode 100644 index 8529b6ae5e..0000000000 --- a/target/linux/mvebu/patches-5.10/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch +++ /dev/null @@ -1,30 +0,0 @@ -From e7ca75fe6662f78bfeb0112671c812e4c7b8e214 Mon Sep 17 00:00:00 2001 -From: Maxime Chevallier -Date: Fri, 26 Nov 2021 12:20:54 +0100 -Subject: net: mvneta: Don't force-set the offloading flag - -The qopt->hw flag is set by the TC code according to the offloading mode -asked by user. Don't force-set it in the driver, but instead read it to -make sure we do what's asked. - -Signed-off-by: Maxime Chevallier -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/marvell/mvneta.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -(limited to 'drivers/net/ethernet/marvell/mvneta.c') - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -4940,7 +4940,9 @@ static int mvneta_setup_mqprio(struct ne - u8 num_tc; - int i; - -- mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS; -+ if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS) -+ return 0; -+ - num_tc = mqprio->qopt.num_tc; - - if (num_tc > rxq_number) diff --git a/target/linux/mvebu/patches-5.10/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch b/target/linux/mvebu/patches-5.10/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch deleted file mode 100644 index ed4f0441dd..0000000000 --- a/target/linux/mvebu/patches-5.10/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch +++ /dev/null @@ -1,97 +0,0 @@ -From e9f7099d0730341b24c057acbf545dd019581db6 Mon Sep 17 00:00:00 2001 -From: Maxime Chevallier -Date: Fri, 26 Nov 2021 12:20:55 +0100 -Subject: net: mvneta: Allow having more than one queue per TC - -The current mqprio implementation assumed that we are only using one -queue per TC. Use the offset and count parameters to allow using -multiple queues per TC. In that case, the controller will use a standard -round-robin algorithm to pick queues assigned to the same TC, with the -same priority. - -This only applies to VLAN priorities in ingress traffic, each TC -corresponding to a vlan priority. - -Signed-off-by: Maxime Chevallier -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/marvell/mvneta.c | 35 ++++++++++++++++++++--------------- - 1 file changed, 20 insertions(+), 15 deletions(-) - -(limited to 'drivers/net/ethernet/marvell/mvneta.c') - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -493,7 +493,6 @@ struct mvneta_port { - u8 mcast_count[256]; - u16 tx_ring_size; - u16 rx_ring_size; -- u8 prio_tc_map[8]; - - phy_interface_t phy_interface; - struct device_node *dn; -@@ -4922,13 +4921,12 @@ static void mvneta_clear_rx_prio_map(str - mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0); - } - --static void mvneta_setup_rx_prio_map(struct mvneta_port *pp) -+static void mvneta_map_vlan_prio_to_rxq(struct mvneta_port *pp, u8 pri, u8 rxq) - { -- u32 val = 0; -- int i; -+ u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ); - -- for (i = 0; i < rxq_number; i++) -- val |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]); -+ val &= ~MVNETA_VLAN_PRIO_RXQ_MAP(pri, 0x7); -+ val |= MVNETA_VLAN_PRIO_RXQ_MAP(pri, rxq); - - mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val); - } -@@ -4937,8 +4935,8 @@ static int mvneta_setup_mqprio(struct ne - struct tc_mqprio_qopt_offload *mqprio) - { - struct mvneta_port *pp = netdev_priv(dev); -+ int rxq, tc; - u8 num_tc; -- int i; - - if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS) - return 0; -@@ -4948,21 +4946,28 @@ static int mvneta_setup_mqprio(struct ne - if (num_tc > rxq_number) - return -EINVAL; - -+ mvneta_clear_rx_prio_map(pp); -+ - if (!num_tc) { -- mvneta_clear_rx_prio_map(pp); - netdev_reset_tc(dev); - return 0; - } - -- memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map, -- sizeof(pp->prio_tc_map)); -+ netdev_set_num_tc(dev, mqprio->qopt.num_tc); - -- mvneta_setup_rx_prio_map(pp); -+ for (tc = 0; tc < mqprio->qopt.num_tc; tc++) { -+ netdev_set_tc_queue(dev, tc, mqprio->qopt.count[tc], -+ mqprio->qopt.offset[tc]); -+ -+ for (rxq = mqprio->qopt.offset[tc]; -+ rxq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc]; -+ rxq++) { -+ if (rxq >= rxq_number) -+ return -EINVAL; - -- netdev_set_num_tc(dev, mqprio->qopt.num_tc); -- for (i = 0; i < mqprio->qopt.num_tc; i++) -- netdev_set_tc_queue(dev, i, mqprio->qopt.count[i], -- mqprio->qopt.offset[i]); -+ mvneta_map_vlan_prio_to_rxq(pp, tc, rxq); -+ } -+ } - - return 0; - } diff --git a/target/linux/mvebu/patches-5.10/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch b/target/linux/mvebu/patches-5.10/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch deleted file mode 100644 index 15a0ce6b58..0000000000 --- a/target/linux/mvebu/patches-5.10/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch +++ /dev/null @@ -1,182 +0,0 @@ -From 2551dc9e398c37a15e52122d385c29a8b06be45f Mon Sep 17 00:00:00 2001 -From: Maxime Chevallier -Date: Fri, 26 Nov 2021 12:20:56 +0100 -Subject: net: mvneta: Add TC traffic shaping offload - -The mvneta controller is able to do some tocken-bucket per-queue traffic -shaping. This commit adds support for setting these using the TC mqprio -interface. - -The token-bucket parameters are customisable, but the current -implementation configures them to have a 10kbps resolution for the -rate limitation, since it allows to cover the whole range of max_rate -values from 10kbps to 5Gbps with 10kbps increments. - -Signed-off-by: Maxime Chevallier -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/marvell/mvneta.c | 120 +++++++++++++++++++++++++++++++++- - 1 file changed, 119 insertions(+), 1 deletion(-) - -(limited to 'drivers/net/ethernet/marvell/mvneta.c') - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -248,12 +248,39 @@ - #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 - #define MVNETA_PORT_TX_RESET 0x3cf0 - #define MVNETA_PORT_TX_DMA_RESET BIT(0) -+#define MVNETA_TXQ_CMD1_REG 0x3e00 -+#define MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 BIT(3) -+#define MVNETA_TXQ_CMD1_BW_LIM_EN BIT(0) -+#define MVNETA_REFILL_NUM_CLK_REG 0x3e08 -+#define MVNETA_REFILL_MAX_NUM_CLK 0x0000ffff - #define MVNETA_TX_MTU 0x3e0c - #define MVNETA_TX_TOKEN_SIZE 0x3e14 - #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff -+#define MVNETA_TXQ_BUCKET_REFILL_REG(q) (0x3e20 + ((q) << 2)) -+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD_MASK 0x3ff00000 -+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT 20 -+#define MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX 0x0007ffff - #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) - #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff - -+/* The values of the bucket refill base period and refill period are taken from -+ * the reference manual, and adds up to a base resolution of 10Kbps. This allows -+ * to cover all rate-limit values from 10Kbps up to 5Gbps -+ */ -+ -+/* Base period for the rate limit algorithm */ -+#define MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS 100 -+ -+/* Number of Base Period to wait between each bucket refill */ -+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD 1000 -+ -+/* The base resolution for rate limiting, in bps. Any max_rate value should be -+ * a multiple of that value. -+ */ -+#define MVNETA_TXQ_RATE_LIMIT_RESOLUTION (NSEC_PER_SEC / \ -+ (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \ -+ MVNETA_TXQ_BUCKET_REFILL_PERIOD)) -+ - #define MVNETA_LPI_CTRL_0 0x2cc0 - #define MVNETA_LPI_CTRL_1 0x2cc4 - #define MVNETA_LPI_REQUEST_ENABLE BIT(0) -@@ -4931,11 +4958,74 @@ static void mvneta_map_vlan_prio_to_rxq( - mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val); - } - -+static int mvneta_enable_per_queue_rate_limit(struct mvneta_port *pp) -+{ -+ unsigned long core_clk_rate; -+ u32 refill_cycles; -+ u32 val; -+ -+ core_clk_rate = clk_get_rate(pp->clk); -+ if (!core_clk_rate) -+ return -EINVAL; -+ -+ refill_cycles = MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS / -+ (NSEC_PER_SEC / core_clk_rate); -+ -+ if (refill_cycles > MVNETA_REFILL_MAX_NUM_CLK) -+ return -EINVAL; -+ -+ /* Enable bw limit algorithm version 3 */ -+ val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG); -+ val &= ~(MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN); -+ mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val); -+ -+ /* Set the base refill rate */ -+ mvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles); -+ -+ return 0; -+} -+ -+static void mvneta_disable_per_queue_rate_limit(struct mvneta_port *pp) -+{ -+ u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG); -+ -+ val |= (MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN); -+ mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val); -+} -+ -+static int mvneta_setup_queue_rates(struct mvneta_port *pp, int queue, -+ u64 min_rate, u64 max_rate) -+{ -+ u32 refill_val, rem; -+ u32 val = 0; -+ -+ /* Convert to from Bps to bps */ -+ max_rate *= 8; -+ -+ if (min_rate) -+ return -EINVAL; -+ -+ refill_val = div_u64_rem(max_rate, MVNETA_TXQ_RATE_LIMIT_RESOLUTION, -+ &rem); -+ -+ if (rem || !refill_val || -+ refill_val > MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX) -+ return -EINVAL; -+ -+ val = refill_val; -+ val |= (MVNETA_TXQ_BUCKET_REFILL_PERIOD << -+ MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT); -+ -+ mvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val); -+ -+ return 0; -+} -+ - static int mvneta_setup_mqprio(struct net_device *dev, - struct tc_mqprio_qopt_offload *mqprio) - { - struct mvneta_port *pp = netdev_priv(dev); -- int rxq, tc; -+ int rxq, txq, tc, ret; - u8 num_tc; - - if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS) -@@ -4949,6 +5039,7 @@ static int mvneta_setup_mqprio(struct ne - mvneta_clear_rx_prio_map(pp); - - if (!num_tc) { -+ mvneta_disable_per_queue_rate_limit(pp); - netdev_reset_tc(dev); - return 0; - } -@@ -4969,6 +5060,33 @@ static int mvneta_setup_mqprio(struct ne - } - } - -+ if (mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE) { -+ mvneta_disable_per_queue_rate_limit(pp); -+ return 0; -+ } -+ -+ if (mqprio->qopt.num_tc > txq_number) -+ return -EINVAL; -+ -+ ret = mvneta_enable_per_queue_rate_limit(pp); -+ if (ret) -+ return ret; -+ -+ for (tc = 0; tc < mqprio->qopt.num_tc; tc++) { -+ for (txq = mqprio->qopt.offset[tc]; -+ txq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc]; -+ txq++) { -+ if (txq >= txq_number) -+ return -EINVAL; -+ -+ ret = mvneta_setup_queue_rates(pp, txq, -+ mqprio->min_rate[tc], -+ mqprio->max_rate[tc]); -+ if (ret) -+ return ret; -+ } -+ } -+ - return 0; - } - diff --git a/target/linux/mvebu/patches-5.10/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/target/linux/mvebu/patches-5.10/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch deleted file mode 100644 index 29f36be460..0000000000 --- a/target/linux/mvebu/patches-5.10/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch +++ /dev/null @@ -1,40 +0,0 @@ -From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Sat, 3 Oct 2015 09:13:05 +0100 -Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states - -The cpuidle ->enter method expects the return value to be the sleep -state we entered. Returning negative numbers or other codes is not -permissible since coupled CPU idle was merged. - -At least some of the mvebu_v7_cpu_suspend() implementations return the -value from cpu_suspend(), which returns zero if the CPU vectors back -into the kernel via cpu_resume() (the success case), or the non-zero -return value of the suspend actor, or one (failure cases). - -We do not want to be returning the failure case value back to CPU idle -as that indicates that we successfully entered one of the deeper idle -states. Always return zero instead, indicating that we slept for the -shortest amount of time. - -Signed-off-by: Russell King ---- - drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/cpuidle/cpuidle-mvebu-v7.c -+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c -@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp - ret = mvebu_v7_cpu_suspend(deepidle); - cpu_pm_exit(); - -+ /* -+ * If we failed to enter the desired state, indicate that we -+ * slept lightly. -+ */ - if (ret) -- return ret; -+ return 0; - - return index; - } diff --git a/target/linux/mvebu/patches-5.10/801-pci-mvebu-time-out-reset-on-link-up.patch b/target/linux/mvebu/patches-5.10/801-pci-mvebu-time-out-reset-on-link-up.patch deleted file mode 100644 index a5e49552e9..0000000000 --- a/target/linux/mvebu/patches-5.10/801-pci-mvebu-time-out-reset-on-link-up.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001 -From: Russell King -Date: Sat, 9 Jul 2016 10:58:16 +0100 -Subject: pci: mvebu: time out reset on link up - -If the port reports that the link is up while we are resetting, there's -little point in waiting for the full duration. - -Signed-off-by: Russell King ---- - drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------ - 1 file changed, 14 insertions(+), 6 deletions(-) - ---- a/drivers/pci/controller/pci-mvebu.c -+++ b/drivers/pci/controller/pci-mvebu.c -@@ -941,6 +941,7 @@ static int mvebu_pcie_powerup(struct mve - - if (port->reset_gpio) { - u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; -+ unsigned int i; - - of_property_read_u32(port->dn, "reset-delay-us", - &reset_udelay); -@@ -948,7 +949,13 @@ static int mvebu_pcie_powerup(struct mve - udelay(100); - - gpiod_set_value_cansleep(port->reset_gpio, 0); -- msleep(reset_udelay / 1000); -+ for (i = 0; i < reset_udelay; i += 1000) { -+ if (mvebu_pcie_link_up(port)) -+ break; -+ msleep(1); -+ } -+ -+ printk("%s: reset completed in %dus\n", port->name, i); - } - - return 0; -@@ -1108,15 +1115,16 @@ static int mvebu_pcie_probe(struct platf - if (!child) - continue; - -- ret = mvebu_pcie_powerup(port); -- if (ret < 0) -- continue; -- - port->base = mvebu_pcie_map_registers(pdev, child, port); - if (IS_ERR(port->base)) { - dev_err(dev, "%s: cannot map registers\n", port->name); - port->base = NULL; -- mvebu_pcie_powerdown(port); -+ continue; -+ } -+ -+ ret = mvebu_pcie_powerup(port); -+ if (ret < 0) { -+ port->base = NULL; - continue; - } - diff --git a/target/linux/mvebu/patches-5.10/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch b/target/linux/mvebu/patches-5.10/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch deleted file mode 100644 index 28b2b19499..0000000000 --- a/target/linux/mvebu/patches-5.10/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch +++ /dev/null @@ -1,218 +0,0 @@ -From aa4a0ccc41997f2da172165c92803abace43bd1c Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:32 +0000 -Subject: [PATCH 1/7] dt-bindings: Add IEI vendor prefix and IEI WT61P803 - PUZZLE driver bindings - -Add the IEI WT61P803 PUZZLE Device Tree bindings for MFD, HWMON and LED -drivers. A new vendor prefix is also added accordingly for -IEI Integration Corp. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - .../hwmon/iei,wt61p803-puzzle-hwmon.yaml | 53 ++++++++++++ - .../leds/iei,wt61p803-puzzle-leds.yaml | 39 +++++++++ - .../bindings/mfd/iei,wt61p803-puzzle.yaml | 82 +++++++++++++++++++ - .../devicetree/bindings/vendor-prefixes.yaml | 2 + - 4 files changed, 176 insertions(+) - create mode 100644 Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml - create mode 100644 Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml - create mode 100644 Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml -@@ -0,0 +1,53 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: IEI WT61P803 PUZZLE MCU HWMON module from IEI Integration Corp. -+ -+maintainers: -+ - Luka Kovacic -+ -+description: | -+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details -+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml. -+ -+ The HWMON module is a sub-node of the MCU node in the Device Tree. -+ -+properties: -+ compatible: -+ const: iei,wt61p803-puzzle-hwmon -+ -+ "#address-cells": -+ const: 1 -+ -+ "#size-cells": -+ const: 0 -+ -+patternProperties: -+ "^fan-group@[0-1]$": -+ type: object -+ properties: -+ reg: -+ minimum: 0 -+ maximum: 1 -+ description: -+ Fan group ID -+ -+ cooling-levels: -+ minItems: 1 -+ maxItems: 255 -+ description: -+ Cooling levels for the fans (PWM value mapping) -+ description: | -+ Properties for each fan group. -+ required: -+ - reg -+ -+required: -+ - compatible -+ - "#address-cells" -+ - "#size-cells" -+ -+additionalProperties: false ---- /dev/null -+++ b/Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml -@@ -0,0 +1,39 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/leds/iei,wt61p803-puzzle-leds.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: IEI WT61P803 PUZZLE MCU LED module from IEI Integration Corp. -+ -+maintainers: -+ - Luka Kovacic -+ -+description: | -+ This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details -+ see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml. -+ -+ The LED module is a sub-node of the MCU node in the Device Tree. -+ -+properties: -+ compatible: -+ const: iei,wt61p803-puzzle-leds -+ -+ "#address-cells": -+ const: 1 -+ -+ "#size-cells": -+ const: 0 -+ -+ led@0: -+ type: object -+ $ref: common.yaml -+ description: | -+ Properties for a single LED. -+ -+required: -+ - compatible -+ - "#address-cells" -+ - "#size-cells" -+ -+additionalProperties: false ---- /dev/null -+++ b/Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml -@@ -0,0 +1,82 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mfd/iei,wt61p803-puzzle.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: IEI WT61P803 PUZZLE MCU from IEI Integration Corp. -+ -+maintainers: -+ - Luka Kovacic -+ -+description: | -+ IEI WT61P803 PUZZLE MCU is embedded in some IEI Puzzle series boards. -+ It's used for controlling system power states, fans, LEDs and temperature -+ sensors. -+ -+ For Device Tree bindings of other sub-modules (HWMON, LEDs) refer to the -+ binding documents under the respective subsystem directories. -+ -+properties: -+ compatible: -+ const: iei,wt61p803-puzzle -+ -+ current-speed: -+ description: -+ Serial bus speed in bps -+ maxItems: 1 -+ -+ enable-beep: true -+ -+ hwmon: -+ $ref: /schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml -+ -+ leds: -+ $ref: /schemas/leds/iei,wt61p803-puzzle-leds.yaml -+ -+required: -+ - compatible -+ - current-speed -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ serial { -+ mcu { -+ compatible = "iei,wt61p803-puzzle"; -+ current-speed = <115200>; -+ enable-beep; -+ -+ leds { -+ compatible = "iei,wt61p803-puzzle-leds"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ led@0 { -+ reg = <0>; -+ function = LED_FUNCTION_POWER; -+ color = ; -+ }; -+ }; -+ -+ hwmon { -+ compatible = "iei,wt61p803-puzzle-hwmon"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ fan-group@0 { -+ #cooling-cells = <2>; -+ reg = <0x00>; -+ cooling-levels = <64 102 170 230 250>; -+ }; -+ -+ fan-group@1 { -+ #cooling-cells = <2>; -+ reg = <0x01>; -+ cooling-levels = <64 102 170 230 250>; -+ }; -+ }; -+ }; -+ }; ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -475,6 +475,8 @@ patternProperties: - description: IC Plus Corp. - "^idt,.*": - description: Integrated Device Technologies, Inc. -+ "^iei,.*": -+ description: IEI Integration Corp. - "^ifi,.*": - description: Ingenieurburo Fur Ic-Technologie (I/F/I) - "^ilitek,.*": diff --git a/target/linux/mvebu/patches-5.10/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch b/target/linux/mvebu/patches-5.10/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch deleted file mode 100644 index 01c2ecce0d..0000000000 --- a/target/linux/mvebu/patches-5.10/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch +++ /dev/null @@ -1,1034 +0,0 @@ -From 692cfa85272dd12995b427c0a7a585ced5d54f32 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:33 +0000 -Subject: [PATCH 2/7] drivers: mfd: Add a driver for IEI WT61P803 PUZZLE MCU - -Add a driver for the IEI WT61P803 PUZZLE microcontroller, used in some -IEI Puzzle series devices. The microcontroller controls system power, -temperature sensors, fans and LEDs. - -This driver implements the core functionality for device communication -over the system serial (serdev bus). It handles MCU messages and the -internal MCU properties. Some properties can be managed over sysfs. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - drivers/mfd/Kconfig | 8 + - drivers/mfd/Makefile | 1 + - drivers/mfd/iei-wt61p803-puzzle.c | 908 ++++++++++++++++++++++++ - include/linux/mfd/iei-wt61p803-puzzle.h | 66 ++ - 4 files changed, 983 insertions(+) - create mode 100644 drivers/mfd/iei-wt61p803-puzzle.c - create mode 100644 include/linux/mfd/iei-wt61p803-puzzle.h - ---- a/drivers/mfd/Kconfig -+++ b/drivers/mfd/Kconfig -@@ -2155,6 +2155,15 @@ config SGI_MFD_IOC3 - If you have an SGI Origin, Octane, or a PCI IOC3 card, - then say Y. Otherwise say N. - -+config MFD_IEI_WT61P803_PUZZLE -+ tristate "IEI WT61P803 PUZZLE MCU driver" -+ depends on SERIAL_DEV_BUS -+ select MFD_CORE -+ help -+ IEI WT61P803 PUZZLE is a system power management microcontroller -+ used for fan control, temperature sensor reading, LED control -+ and system identification. -+ - config MFD_INTEL_M10_BMC - tristate "Intel MAX 10 Board Management Controller" - depends on SPI_MASTER ---- a/drivers/mfd/Makefile -+++ b/drivers/mfd/Makefile -@@ -237,6 +237,7 @@ obj-$(CONFIG_MFD_HI655X_PMIC) += hi655 - obj-$(CONFIG_MFD_DLN2) += dln2.o - obj-$(CONFIG_MFD_RT5033) += rt5033.o - obj-$(CONFIG_MFD_SKY81452) += sky81452.o -+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE) += iei-wt61p803-puzzle.o - - intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o - obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o ---- /dev/null -+++ b/drivers/mfd/iei-wt61p803-puzzle.c -@@ -0,0 +1,908 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* IEI WT61P803 PUZZLE MCU Driver -+ * System management microcontroller for fan control, temperature sensor reading, -+ * LED control and system identification on IEI Puzzle series ARM-based appliances. -+ * -+ * Copyright (C) 2020 Sartura Ltd. -+ * Author: Luka Kovacic -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* start, payload and XOR checksum at end */ -+#define IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH (1 + 20 + 1) -+#define IEI_WT61P803_PUZZLE_RESP_BUF_SIZE 512 -+ -+#define IEI_WT61P803_PUZZLE_MAC_LENGTH 17 -+#define IEI_WT61P803_PUZZLE_SN_LENGTH 36 -+#define IEI_WT61P803_PUZZLE_VERSION_LENGTH 6 -+#define IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH 16 -+#define IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH 8 -+#define IEI_WT61P803_PUZZLE_NB_MAC 8 -+ -+/* Use HZ as a timeout value throughout the driver */ -+#define IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT HZ -+ -+enum iei_wt61p803_puzzle_attribute_type { -+ IEI_WT61P803_PUZZLE_VERSION, -+ IEI_WT61P803_PUZZLE_BUILD_INFO, -+ IEI_WT61P803_PUZZLE_BOOTLOADER_MODE, -+ IEI_WT61P803_PUZZLE_PROTOCOL_VERSION, -+ IEI_WT61P803_PUZZLE_SERIAL_NUMBER, -+ IEI_WT61P803_PUZZLE_MAC_ADDRESS, -+ IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS, -+ IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, -+ IEI_WT61P803_PUZZLE_POWER_STATUS, -+}; -+ -+struct iei_wt61p803_puzzle_device_attribute { -+ struct device_attribute dev_attr; -+ enum iei_wt61p803_puzzle_attribute_type type; -+ u8 index; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_mcu_status - MCU flags state -+ * @ac_recovery_status_flag: AC Recovery Status Flag -+ * @power_loss_recovery: System recovery after power loss -+ * @power_status: System Power-on Method -+ */ -+struct iei_wt61p803_puzzle_mcu_status { -+ u8 ac_recovery_status_flag; -+ u8 power_loss_recovery; -+ u8 power_status; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_reply - MCU reply -+ * @size: Size of the MCU reply -+ * @data: Full MCU reply buffer -+ * @state: Current state of the packet -+ * @received: Was the response fullfilled -+ */ -+struct iei_wt61p803_puzzle_reply { -+ size_t size; -+ unsigned char data[IEI_WT61P803_PUZZLE_RESP_BUF_SIZE]; -+ struct completion received; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_mcu_version - MCU version status -+ * @version: Primary firmware version -+ * @build_info: Build date and time -+ * @bootloader_mode: Status of the MCU operation -+ * @protocol_version: MCU communication protocol version -+ * @serial_number: Device factory serial number -+ * @mac_address: Device factory MAC addresses -+ * -+ * Last element of arrays is reserved for '\0'. -+ */ -+struct iei_wt61p803_puzzle_mcu_version { -+ char version[IEI_WT61P803_PUZZLE_VERSION_LENGTH + 1]; -+ char build_info[IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH + 1]; -+ bool bootloader_mode; -+ char protocol_version[IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH + 1]; -+ char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH + 1]; -+ char mac_address[IEI_WT61P803_PUZZLE_NB_MAC][IEI_WT61P803_PUZZLE_MAC_LENGTH + 1]; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle - IEI WT61P803 PUZZLE MCU Driver -+ * @serdev: Pointer to underlying serdev device -+ * @dev: Pointer to underlying dev device -+ * @reply_lock: Reply mutex lock -+ * @reply: Pointer to the iei_wt61p803_puzzle_reply struct -+ * @version: MCU version related data -+ * @status: MCU status related data -+ * @response_buffer Command response buffer allocation -+ * @lock General member mutex lock -+ */ -+struct iei_wt61p803_puzzle { -+ struct serdev_device *serdev; -+ struct device *dev; -+ struct mutex reply_lock; /* lock to prevent multiple firmware calls */ -+ struct iei_wt61p803_puzzle_reply *reply; -+ struct iei_wt61p803_puzzle_mcu_version version; -+ struct iei_wt61p803_puzzle_mcu_status status; -+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE]; -+ struct mutex lock; /* lock to protect response buffer */ -+}; -+ -+static unsigned char iei_wt61p803_puzzle_checksum(unsigned char *buf, size_t len) -+{ -+ unsigned char checksum = 0; -+ size_t i; -+ -+ for (i = 0; i < len; i++) -+ checksum ^= buf[i]; -+ return checksum; -+} -+ -+static int iei_wt61p803_puzzle_process_resp(struct iei_wt61p803_puzzle *mcu, -+ const unsigned char *raw_resp_data, size_t size) -+{ -+ unsigned char checksum; -+ -+ /* Check the incoming frame header */ -+ if (!(raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START || -+ raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER || -+ (raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM && -+ raw_resp_data[1] == IEI_WT61P803_PUZZLE_CMD_EEPROM_READ))) { -+ if (mcu->reply->size + size >= sizeof(mcu->reply->data)) -+ return -EIO; -+ -+ /* Append the frame to existing data */ -+ memcpy(mcu->reply->data + mcu->reply->size, raw_resp_data, size); -+ mcu->reply->size += size; -+ } else { -+ if (size >= sizeof(mcu->reply->data)) -+ return -EIO; -+ -+ /* Start processing a new frame */ -+ memcpy(mcu->reply->data, raw_resp_data, size); -+ mcu->reply->size = size; -+ } -+ -+ checksum = iei_wt61p803_puzzle_checksum(mcu->reply->data, mcu->reply->size - 1); -+ if (checksum != mcu->reply->data[mcu->reply->size - 1]) { -+ /* The checksum isn't matched yet, wait for new frames */ -+ return size; -+ } -+ -+ /* Received all the data */ -+ complete(&mcu->reply->received); -+ -+ return size; -+} -+ -+static int iei_wt61p803_puzzle_recv_buf(struct serdev_device *serdev, -+ const unsigned char *data, size_t size) -+{ -+ struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev); -+ int ret; -+ -+ ret = iei_wt61p803_puzzle_process_resp(mcu, data, size); -+ /* Return the number of processed bytes if function returns error, -+ * discard the remaining incoming data, since the frame this data -+ * belongs to is broken anyway -+ */ -+ if (ret < 0) -+ return size; -+ -+ return ret; -+} -+ -+static const struct serdev_device_ops iei_wt61p803_puzzle_serdev_device_ops = { -+ .receive_buf = iei_wt61p803_puzzle_recv_buf, -+ .write_wakeup = serdev_device_write_wakeup, -+}; -+ -+/** -+ * iei_wt61p803_puzzle_write_command_watchdog() - Watchdog of the normal cmd -+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct -+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor)) -+ * @size: Size of the cmd char array -+ * @reply_data: Pointer to the reply/response data array (should be allocated) -+ * @reply_size: Pointer to size_t (size of reply_data) -+ * @retry_count: Number of times to retry sending the command to the MCU -+ */ -+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu, -+ unsigned char *cmd, size_t size, -+ unsigned char *reply_data, -+ size_t *reply_size, int retry_count) -+{ -+ struct device *dev = &mcu->serdev->dev; -+ int ret, i; -+ -+ for (i = 0; i < retry_count; i++) { -+ ret = iei_wt61p803_puzzle_write_command(mcu, cmd, size, -+ reply_data, reply_size); -+ if (ret != -ETIMEDOUT) -+ return ret; -+ } -+ -+ dev_err(dev, "Command response timed out. Retries: %d\n", retry_count); -+ -+ return -ETIMEDOUT; -+} -+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command_watchdog); -+ -+/** -+ * iei_wt61p803_puzzle_write_command() - Send a structured command to the MCU -+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct -+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor)) -+ * @size: Size of the cmd char array -+ * @reply_data: Pointer to the reply/response data array (should be allocated) -+ * -+ * Sends a structured command to the MCU. -+ */ -+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu, -+ unsigned char *cmd, size_t size, -+ unsigned char *reply_data, -+ size_t *reply_size) -+{ -+ struct device *dev = &mcu->serdev->dev; -+ int ret; -+ -+ if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH) -+ return -EINVAL; -+ -+ mutex_lock(&mcu->reply_lock); -+ -+ cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1); -+ -+ /* Initialize reply struct */ -+ reinit_completion(&mcu->reply->received); -+ mcu->reply->size = 0; -+ usleep_range(2000, 10000); -+ serdev_device_write_flush(mcu->serdev); -+ ret = serdev_device_write_buf(mcu->serdev, cmd, size); -+ if (ret < 0) -+ goto exit; -+ -+ serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -+ ret = wait_for_completion_timeout(&mcu->reply->received, -+ IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -+ if (ret == 0) { -+ dev_err(dev, "Command reply receive timeout\n"); -+ ret = -ETIMEDOUT; -+ goto exit; -+ } -+ -+ *reply_size = mcu->reply->size; -+ /* Copy the received data, as it will not be available after a new frame is received */ -+ memcpy(reply_data, mcu->reply->data, mcu->reply->size); -+ ret = 0; -+exit: -+ mutex_unlock(&mcu->reply_lock); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command); -+ -+static int iei_wt61p803_puzzle_buzzer(struct iei_wt61p803_puzzle *mcu, bool long_beep) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char buzzer_cmd[4] = {}; -+ size_t reply_size; -+ int ret; -+ -+ buzzer_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ buzzer_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE; -+ buzzer_cmd[2] = long_beep ? '3' : '2'; /* Buzzer 1.5 / 0.5 second beep */ -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, buzzer_cmd, sizeof(buzzer_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto exit; -+ -+ if (reply_size != 3) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) { -+ ret = -EPROTO; -+ goto exit; -+ } -+exit: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_get_version(struct iei_wt61p803_puzzle *mcu) -+{ -+ unsigned char version_cmd[3] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION, -+ }; -+ unsigned char build_info_cmd[3] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD, -+ }; -+ unsigned char bootloader_mode_cmd[3] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE, -+ }; -+ unsigned char protocol_version_cmd[3] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION, -+ }; -+ unsigned char *rb = mcu->response_buffer; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu->lock); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, version_cmd, sizeof(version_cmd), -+ rb, &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size < 7) { -+ ret = -EIO; -+ goto err; -+ } -+ sprintf(mcu->version.version, "v%c.%.3s", rb[2], &rb[3]); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, build_info_cmd, -+ sizeof(build_info_cmd), rb, -+ &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size < 15) { -+ ret = -EIO; -+ goto err; -+ } -+ sprintf(mcu->version.build_info, "%c%c/%c%c/%.4s %c%c:%c%c", -+ rb[8], rb[9], rb[6], rb[7], &rb[2], rb[10], rb[11], -+ rb[12], rb[13]); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, bootloader_mode_cmd, -+ sizeof(bootloader_mode_cmd), rb, -+ &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size < 4) { -+ ret = -EIO; -+ goto err; -+ } -+ if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS) -+ mcu->version.bootloader_mode = false; -+ else if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER) -+ mcu->version.bootloader_mode = true; -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, protocol_version_cmd, -+ sizeof(protocol_version_cmd), rb, -+ &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size < 9) { -+ ret = -EIO; -+ goto err; -+ } -+ sprintf(mcu->version.protocol_version, "v%c.%c%c%c%c%c", -+ rb[7], rb[6], rb[5], rb[4], rb[3], rb[2]); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_get_mcu_status(struct iei_wt61p803_puzzle *mcu) -+{ -+ unsigned char mcu_status_cmd[5] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START, -+ IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER, -+ IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS, -+ IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS, -+ }; -+ unsigned char *resp_buf = mcu->response_buffer; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, mcu_status_cmd, sizeof(mcu_status_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto exit; -+ if (reply_size < 20) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ /* Response format: -+ * (IDX RESPONSE) -+ * 0 @ -+ * 1 O -+ * 2 S -+ * 3 S -+ * ... -+ * 5 AC Recovery Status Flag -+ * ... -+ * 10 Power Loss Recovery -+ * ... -+ * 19 Power Status (system power on method) -+ * 20 XOR checksum -+ */ -+ if (resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS && -+ resp_buf[3] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS) { -+ mcu->status.ac_recovery_status_flag = resp_buf[5]; -+ mcu->status.power_loss_recovery = resp_buf[10]; -+ mcu->status.power_status = resp_buf[19]; -+ } -+exit: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_get_serial_number(struct iei_wt61p803_puzzle *mcu) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char serial_number_cmd[5] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM, -+ IEI_WT61P803_PUZZLE_CMD_EEPROM_READ, -+ 0x00, /* EEPROM read address */ -+ 0x24, /* Data length */ -+ }; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd, -+ sizeof(serial_number_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto err; -+ -+ if (reply_size < IEI_WT61P803_PUZZLE_SN_LENGTH + 4) { -+ ret = -EIO; -+ goto err; -+ } -+ -+ sprintf(mcu->version.serial_number, "%.*s", -+ IEI_WT61P803_PUZZLE_SN_LENGTH, resp_buf + 4); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_write_serial_number(struct iei_wt61p803_puzzle *mcu, -+ unsigned char serial_number[36]) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char serial_number_header[4] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM, -+ IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE, -+ 0x00, /* EEPROM write address */ -+ 0xC, /* Data length */ -+ }; -+ unsigned char serial_number_cmd[4 + 12 + 1]; /* header, serial number, XOR checksum */ -+ int ret, sn_counter; -+ size_t reply_size; -+ -+ /* The MCU can only handle 22 byte messages, send the S/N in 12 byte chunks */ -+ mutex_lock(&mcu->lock); -+ for (sn_counter = 0; sn_counter < 3; sn_counter++) { -+ serial_number_header[2] = 0x0 + 0xC * sn_counter; -+ -+ memcpy(serial_number_cmd, serial_number_header, sizeof(serial_number_header)); -+ memcpy(serial_number_cmd + sizeof(serial_number_header), -+ serial_number + 0xC * sn_counter, 0xC); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd, -+ sizeof(serial_number_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size != 3) { -+ ret = -EIO; -+ goto err; -+ } -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) { -+ ret = -EPROTO; -+ goto err; -+ } -+ } -+ -+ sprintf(mcu->version.serial_number, "%.*s", -+ IEI_WT61P803_PUZZLE_SN_LENGTH, serial_number); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_get_mac_address(struct iei_wt61p803_puzzle *mcu, int index) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char mac_address_cmd[5] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM, -+ IEI_WT61P803_PUZZLE_CMD_EEPROM_READ, -+ 0x00, /* EEPROM read address */ -+ 0x11, /* Data length */ -+ }; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu->lock); -+ mac_address_cmd[2] = 0x24 + 0x11 * index; -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd, -+ sizeof(mac_address_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto err; -+ -+ if (reply_size < 22) { -+ ret = -EIO; -+ goto err; -+ } -+ -+ sprintf(mcu->version.mac_address[index], "%.*s", -+ IEI_WT61P803_PUZZLE_MAC_LENGTH, resp_buf + 4); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int -+iei_wt61p803_puzzle_write_mac_address(struct iei_wt61p803_puzzle *mcu, -+ unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH], -+ int mac_address_idx) -+{ -+ unsigned char mac_address_cmd[4 + IEI_WT61P803_PUZZLE_MAC_LENGTH + 1]; -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char mac_address_header[4] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM, -+ IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE, -+ 0x00, /* EEPROM write address */ -+ 0x11, /* Data length */ -+ }; -+ size_t reply_size; -+ int ret; -+ -+ if (mac_address_idx < 0 || mac_address_idx >= IEI_WT61P803_PUZZLE_NB_MAC) -+ return -EINVAL; -+ -+ mac_address_header[2] = 0x24 + 0x11 * mac_address_idx; -+ -+ /* Concat mac_address_header, mac_address to mac_address_cmd */ -+ memcpy(mac_address_cmd, mac_address_header, sizeof(mac_address_header)); -+ memcpy(mac_address_cmd + sizeof(mac_address_header), mac_address, -+ IEI_WT61P803_PUZZLE_MAC_LENGTH); -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd, -+ sizeof(mac_address_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto err; -+ if (reply_size != 3) { -+ ret = -EIO; -+ goto err; -+ } -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) { -+ ret = -EPROTO; -+ goto err; -+ } -+ -+ sprintf(mcu->version.mac_address[mac_address_idx], "%.*s", -+ IEI_WT61P803_PUZZLE_MAC_LENGTH, mac_address); -+err: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_write_power_loss_recovery(struct iei_wt61p803_puzzle *mcu, -+ int power_loss_recovery_action) -+{ -+ unsigned char *resp_buf = mcu->response_buffer; -+ unsigned char power_loss_recovery_cmd[5] = {}; -+ size_t reply_size; -+ int ret; -+ -+ if (power_loss_recovery_action < 0 || power_loss_recovery_action > 4) -+ return -EINVAL; -+ -+ power_loss_recovery_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ power_loss_recovery_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER; -+ power_loss_recovery_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS; -+ power_loss_recovery_cmd[3] = hex_asc[power_loss_recovery_action]; -+ -+ mutex_lock(&mcu->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu, power_loss_recovery_cmd, -+ sizeof(power_loss_recovery_cmd), -+ resp_buf, &reply_size); -+ if (ret) -+ goto exit; -+ mcu->status.power_loss_recovery = power_loss_recovery_action; -+exit: -+ mutex_unlock(&mcu->lock); -+ return ret; -+} -+ -+#define to_puzzle_dev_attr(_attr) \ -+ container_of(_attr, struct iei_wt61p803_puzzle_device_attribute, dev_attr) -+ -+static ssize_t show_output(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev); -+ struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr); -+ int ret; -+ -+ switch (pattr->type) { -+ case IEI_WT61P803_PUZZLE_VERSION: -+ return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.version); -+ case IEI_WT61P803_PUZZLE_BUILD_INFO: -+ return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.build_info); -+ case IEI_WT61P803_PUZZLE_BOOTLOADER_MODE: -+ return scnprintf(buf, PAGE_SIZE, "%d\n", mcu->version.bootloader_mode); -+ case IEI_WT61P803_PUZZLE_PROTOCOL_VERSION: -+ return scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.protocol_version); -+ case IEI_WT61P803_PUZZLE_SERIAL_NUMBER: -+ ret = iei_wt61p803_puzzle_get_serial_number(mcu); -+ if (!ret) -+ ret = scnprintf(buf, PAGE_SIZE, "%s\n", mcu->version.serial_number); -+ else -+ ret = 0; -+ return ret; -+ case IEI_WT61P803_PUZZLE_MAC_ADDRESS: -+ ret = iei_wt61p803_puzzle_get_mac_address(mcu, pattr->index); -+ if (!ret) -+ ret = scnprintf(buf, PAGE_SIZE, "%s\n", -+ mcu->version.mac_address[pattr->index]); -+ else -+ ret = 0; -+ return ret; -+ case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS: -+ case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY: -+ case IEI_WT61P803_PUZZLE_POWER_STATUS: -+ ret = iei_wt61p803_puzzle_get_mcu_status(mcu); -+ if (ret) -+ return ret; -+ -+ mutex_lock(&mcu->lock); -+ switch (pattr->type) { -+ case IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS: -+ ret = scnprintf(buf, PAGE_SIZE, "%x\n", -+ mcu->status.ac_recovery_status_flag); -+ break; -+ case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY: -+ ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_loss_recovery); -+ break; -+ case IEI_WT61P803_PUZZLE_POWER_STATUS: -+ ret = scnprintf(buf, PAGE_SIZE, "%x\n", mcu->status.power_status); -+ break; -+ default: -+ ret = 0; -+ break; -+ } -+ mutex_unlock(&mcu->lock); -+ return ret; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static ssize_t store_output(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t len) -+{ -+ unsigned char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH]; -+ unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH]; -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev); -+ struct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr); -+ int power_loss_recovery_action = 0; -+ int ret; -+ -+ switch (pattr->type) { -+ case IEI_WT61P803_PUZZLE_SERIAL_NUMBER: -+ if (len != (size_t)(IEI_WT61P803_PUZZLE_SN_LENGTH + 1)) -+ return -EINVAL; -+ memcpy(serial_number, buf, sizeof(serial_number)); -+ ret = iei_wt61p803_puzzle_write_serial_number(mcu, serial_number); -+ if (ret) -+ return ret; -+ return len; -+ case IEI_WT61P803_PUZZLE_MAC_ADDRESS: -+ if (len != (size_t)(IEI_WT61P803_PUZZLE_MAC_LENGTH + 1)) -+ return -EINVAL; -+ -+ memcpy(mac_address, buf, sizeof(mac_address)); -+ -+ if (strlen(attr->attr.name) != 13) -+ return -EIO; -+ -+ ret = iei_wt61p803_puzzle_write_mac_address(mcu, mac_address, pattr->index); -+ if (ret) -+ return ret; -+ return len; -+ case IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY: -+ ret = kstrtoint(buf, 10, &power_loss_recovery_action); -+ if (ret) -+ return ret; -+ ret = iei_wt61p803_puzzle_write_power_loss_recovery(mcu, -+ power_loss_recovery_action); -+ if (ret) -+ return ret; -+ return len; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+#define IEI_WT61P803_PUZZLE_ATTR(_name, _mode, _show, _store, _type, _index) \ -+ struct iei_wt61p803_puzzle_device_attribute dev_attr_##_name = \ -+ { .dev_attr = __ATTR(_name, _mode, _show, _store), \ -+ .type = _type, \ -+ .index = _index } -+ -+#define IEI_WT61P803_PUZZLE_ATTR_RO(_name, _type, _id) \ -+ IEI_WT61P803_PUZZLE_ATTR(_name, 0444, show_output, NULL, _type, _id) -+ -+#define IEI_WT61P803_PUZZLE_ATTR_RW(_name, _type, _id) \ -+ IEI_WT61P803_PUZZLE_ATTR(_name, 0644, show_output, store_output, _type, _id) -+ -+static IEI_WT61P803_PUZZLE_ATTR_RO(version, IEI_WT61P803_PUZZLE_VERSION, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RO(build_info, IEI_WT61P803_PUZZLE_BUILD_INFO, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RO(bootloader_mode, IEI_WT61P803_PUZZLE_BOOTLOADER_MODE, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RO(protocol_version, IEI_WT61P803_PUZZLE_PROTOCOL_VERSION, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RW(serial_number, IEI_WT61P803_PUZZLE_SERIAL_NUMBER, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_0, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_1, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 1); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_2, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 2); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_3, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 3); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_4, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 4); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_5, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 5); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_6, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 6); -+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_7, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 7); -+static IEI_WT61P803_PUZZLE_ATTR_RO(ac_recovery_status, IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RW(power_loss_recovery, IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, 0); -+static IEI_WT61P803_PUZZLE_ATTR_RO(power_status, IEI_WT61P803_PUZZLE_POWER_STATUS, 0); -+ -+static struct attribute *iei_wt61p803_puzzle_attrs[] = { -+ &dev_attr_version.dev_attr.attr, -+ &dev_attr_build_info.dev_attr.attr, -+ &dev_attr_bootloader_mode.dev_attr.attr, -+ &dev_attr_protocol_version.dev_attr.attr, -+ &dev_attr_serial_number.dev_attr.attr, -+ &dev_attr_mac_address_0.dev_attr.attr, -+ &dev_attr_mac_address_1.dev_attr.attr, -+ &dev_attr_mac_address_2.dev_attr.attr, -+ &dev_attr_mac_address_3.dev_attr.attr, -+ &dev_attr_mac_address_4.dev_attr.attr, -+ &dev_attr_mac_address_5.dev_attr.attr, -+ &dev_attr_mac_address_6.dev_attr.attr, -+ &dev_attr_mac_address_7.dev_attr.attr, -+ &dev_attr_ac_recovery_status.dev_attr.attr, -+ &dev_attr_power_loss_recovery.dev_attr.attr, -+ &dev_attr_power_status.dev_attr.attr, -+ NULL -+}; -+ATTRIBUTE_GROUPS(iei_wt61p803_puzzle); -+ -+static int iei_wt61p803_puzzle_sysfs_create(struct device *dev, -+ struct iei_wt61p803_puzzle *mcu) -+{ -+ int ret; -+ -+ ret = sysfs_create_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups); -+ if (ret) -+ mfd_remove_devices(mcu->dev); -+ -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_sysfs_remove(struct device *dev, -+ struct iei_wt61p803_puzzle *mcu) -+{ -+ /* Remove sysfs groups */ -+ sysfs_remove_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups); -+ mfd_remove_devices(mcu->dev); -+ -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_probe(struct serdev_device *serdev) -+{ -+ struct device *dev = &serdev->dev; -+ struct iei_wt61p803_puzzle *mcu; -+ u32 baud; -+ int ret; -+ -+ /* Read the baud rate from 'current-speed', because the MCU supports different rates */ -+ if (device_property_read_u32(dev, "current-speed", &baud)) { -+ dev_err(dev, -+ "'current-speed' is not specified in device node\n"); -+ return -EINVAL; -+ } -+ dev_dbg(dev, "Driver baud rate: %d\n", baud); -+ -+ /* Allocate the memory */ -+ mcu = devm_kzalloc(dev, sizeof(*mcu), GFP_KERNEL); -+ if (!mcu) -+ return -ENOMEM; -+ -+ mcu->reply = devm_kzalloc(dev, sizeof(*mcu->reply), GFP_KERNEL); -+ if (!mcu->reply) -+ return -ENOMEM; -+ -+ /* Initialize device struct data */ -+ mcu->serdev = serdev; -+ mcu->dev = dev; -+ init_completion(&mcu->reply->received); -+ mutex_init(&mcu->reply_lock); -+ mutex_init(&mcu->lock); -+ -+ /* Setup UART interface */ -+ serdev_device_set_drvdata(serdev, mcu); -+ serdev_device_set_client_ops(serdev, &iei_wt61p803_puzzle_serdev_device_ops); -+ ret = devm_serdev_device_open(dev, serdev); -+ if (ret) -+ return ret; -+ serdev_device_set_baudrate(serdev, baud); -+ serdev_device_set_flow_control(serdev, false); -+ ret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE); -+ if (ret) { -+ dev_err(dev, "Failed to set parity\n"); -+ return ret; -+ } -+ -+ ret = iei_wt61p803_puzzle_get_version(mcu); -+ if (ret) -+ return ret; -+ -+ dev_dbg(dev, "MCU version: %s\n", mcu->version.version); -+ dev_dbg(dev, "MCU firmware build info: %s\n", mcu->version.build_info); -+ dev_dbg(dev, "MCU in bootloader mode: %s\n", -+ mcu->version.bootloader_mode ? "true" : "false"); -+ dev_dbg(dev, "MCU protocol version: %s\n", mcu->version.protocol_version); -+ -+ if (device_property_read_bool(dev, "enable-beep")) { -+ ret = iei_wt61p803_puzzle_buzzer(mcu, false); -+ if (ret) -+ return ret; -+ } -+ -+ ret = iei_wt61p803_puzzle_sysfs_create(dev, mcu); -+ if (ret) -+ return ret; -+ -+ return devm_of_platform_populate(dev); -+} -+ -+static void iei_wt61p803_puzzle_remove(struct serdev_device *serdev) -+{ -+ struct device *dev = &serdev->dev; -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev); -+ -+ iei_wt61p803_puzzle_sysfs_remove(dev, mcu); -+} -+ -+static const struct of_device_id iei_wt61p803_puzzle_dt_ids[] = { -+ { .compatible = "iei,wt61p803-puzzle" }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_dt_ids); -+ -+static struct serdev_device_driver iei_wt61p803_puzzle_drv = { -+ .probe = iei_wt61p803_puzzle_probe, -+ .remove = iei_wt61p803_puzzle_remove, -+ .driver = { -+ .name = "iei-wt61p803-puzzle", -+ .of_match_table = iei_wt61p803_puzzle_dt_ids, -+ }, -+}; -+ -+module_serdev_device_driver(iei_wt61p803_puzzle_drv); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Luka Kovacic "); -+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU Driver"); ---- /dev/null -+++ b/include/linux/mfd/iei-wt61p803-puzzle.h -@@ -0,0 +1,66 @@ -+/* SPDX-License-Identifier: GPL-2.0-only */ -+/* IEI WT61P803 PUZZLE MCU Driver -+ * System management microcontroller for fan control, temperature sensor reading, -+ * LED control and system identification on IEI Puzzle series ARM-based appliances. -+ * -+ * Copyright (C) 2020 Sartura Ltd. -+ * Author: Luka Kovacic -+ */ -+ -+#ifndef _MFD_IEI_WT61P803_PUZZLE_H_ -+#define _MFD_IEI_WT61P803_PUZZLE_H_ -+ -+#define IEI_WT61P803_PUZZLE_BUF_SIZE 512 -+ -+/* Command magic numbers */ -+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START 0x40 /* @ */ -+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER 0x25 /* % */ -+#define IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM 0xF7 -+ -+#define IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK 0x30 /* 0 */ -+#define IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK 0x70 -+ -+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_READ 0xA1 -+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE 0xA0 -+ -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION 0x56 /* V */ -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD 0x42 /* B */ -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE 0x4D /* M */ -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER 0x30 -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS 0x31 -+#define IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION 0x50 /* P */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE 0x43 /* C */ -+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER 0x4F /* O */ -+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS 0x53 /* S */ -+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_LED 0x52 /* R */ -+#define IEI_WT61P803_PUZZLE_CMD_LED_POWER 0x31 /* 1 */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_TEMP 0x54 /* T */ -+#define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL 0x41 /* A */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_FAN 0x46 /* F */ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ 0x5A /* Z */ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE 0x57 /* W */ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE 0x30 -+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE 0x41 /* A */ -+ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE + (x)) /* 0 - 1 */ -+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE + (x)) /* 0 - 5 */ -+ -+struct iei_wt61p803_puzzle_mcu_version; -+struct iei_wt61p803_puzzle_reply; -+struct iei_wt61p803_puzzle; -+ -+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu, -+ unsigned char *cmd, size_t size, -+ unsigned char *reply_data, size_t *reply_size, -+ int retry_count); -+ -+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu, -+ unsigned char *cmd, size_t size, -+ unsigned char *reply_data, size_t *reply_size); -+ -+#endif /* _MFD_IEI_WT61P803_PUZZLE_H_ */ diff --git a/target/linux/mvebu/patches-5.10/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch b/target/linux/mvebu/patches-5.10/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch deleted file mode 100644 index d31709fd85..0000000000 --- a/target/linux/mvebu/patches-5.10/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch +++ /dev/null @@ -1,501 +0,0 @@ -From e3310a638cd310bfd93dbbc6d2732ab6aea18dd2 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:34 +0000 -Subject: [PATCH 3/7] drivers: hwmon: Add the IEI WT61P803 PUZZLE HWMON driver - -Add the IEI WT61P803 PUZZLE HWMON driver, that handles the fan speed -control via PWM, reading fan speed and reading on-board temperature -sensors. - -The driver registers a HWMON device and a simple thermal cooling device to -enable in-kernel fan management. - -This driver depends on the IEI WT61P803 PUZZLE MFD driver. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Acked-by: Guenter Roeck -Cc: Luka Perkov -Cc: Robert Marko ---- - drivers/hwmon/Kconfig | 8 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 413 ++++++++++++++++++++++ - 3 files changed, 422 insertions(+) - create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c - ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -722,6 +722,14 @@ config SENSORS_IBMPOWERNV - This driver can also be built as a module. If so, the module - will be called ibmpowernv. - -+config SENSORS_IEI_WT61P803_PUZZLE_HWMON -+ tristate "IEI WT61P803 PUZZLE MFD HWMON Driver" -+ depends on MFD_IEI_WT61P803_PUZZLE -+ help -+ The IEI WT61P803 PUZZLE MFD HWMON Driver handles reading fan speed -+ and writing fan PWM values. It also supports reading on-board -+ temperature sensors. -+ - config SENSORS_IIO_HWMON - tristate "Hwmon driver that uses channels specified via iio maps" - depends on IIO ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -83,6 +83,7 @@ obj-$(CONFIG_SENSORS_HIH6130) += hih6130 - obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o - obj-$(CONFIG_SENSORS_I5500) += i5500_temp.o - obj-$(CONFIG_SENSORS_I5K_AMB) += i5k_amb.o -+obj-$(CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON) += iei-wt61p803-puzzle-hwmon.o - obj-$(CONFIG_SENSORS_IBMAEM) += ibmaem.o - obj-$(CONFIG_SENSORS_IBMPEX) += ibmpex.o - obj-$(CONFIG_SENSORS_IBMPOWERNV)+= ibmpowernv.o ---- /dev/null -+++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c -@@ -0,0 +1,445 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* IEI WT61P803 PUZZLE MCU HWMON Driver -+ * -+ * Copyright (C) 2020 Sartura Ltd. -+ * Author: Luka Kovacic -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM 2 -+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL 255 -+ -+/** -+ * struct iei_wt61p803_puzzle_thermal_cooling_device - Thermal cooling device instance -+ * @mcu_hwmon: Parent driver struct pointer -+ * @tcdev: Thermal cooling device pointer -+ * @name: Thermal cooling device name -+ * @pwm_channel: Controlled PWM channel (0 or 1) -+ * @cooling_levels: Thermal cooling device cooling levels (DT) -+ * @cur_level: Current cooling level -+ * @num_levels: Number of cooling levels -+ */ -+struct iei_wt61p803_puzzle_thermal_cooling_device { -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon; -+ struct thermal_cooling_device *tcdev; -+ char name[THERMAL_NAME_LENGTH]; -+ int pwm_channel; -+ u32 *cooling_levels; -+ int cur_level; -+ u8 num_levels; -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_hwmon - MCU HWMON Driver -+ * @mcu: MCU struct pointer -+ * @response_buffer Global MCU response buffer -+ * @thermal_cooling_dev_present: Per-channel thermal cooling device control indicator -+ * @cdev: Per-channel thermal cooling device private structure -+ */ -+struct iei_wt61p803_puzzle_hwmon { -+ struct iei_wt61p803_puzzle *mcu; -+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE]; -+ bool thermal_cooling_dev_present[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM]; -+ struct iei_wt61p803_puzzle_thermal_cooling_device -+ *cdev[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM]; -+ struct mutex lock; /* mutex to protect response_buffer array */ -+}; -+ -+#define raw_temp_to_milidegree_celsius(x) (((x) - 0x80) * 1000) -+static int iei_wt61p803_puzzle_read_temp_sensor(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon, -+ int channel, long *value) -+{ -+ unsigned char *resp_buf = mcu_hwmon->response_buffer; -+ unsigned char temp_sensor_ntc_cmd[4] = { -+ IEI_WT61P803_PUZZLE_CMD_HEADER_START, -+ IEI_WT61P803_PUZZLE_CMD_TEMP, -+ IEI_WT61P803_PUZZLE_CMD_TEMP_ALL, -+ }; -+ size_t reply_size; -+ int ret; -+ -+ mutex_lock(&mcu_hwmon->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, temp_sensor_ntc_cmd, -+ sizeof(temp_sensor_ntc_cmd), resp_buf, -+ &reply_size); -+ if (ret) -+ goto exit; -+ -+ if (reply_size != 7) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ /* Check the number of NTC values */ -+ if (resp_buf[3] != '2') { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ *value = raw_temp_to_milidegree_celsius(resp_buf[4 + channel]); -+exit: -+ mutex_unlock(&mcu_hwmon->lock); -+ return ret; -+} -+ -+#define raw_fan_val_to_rpm(x, y) ((((x) << 8 | (y)) / 2) * 60) -+static int iei_wt61p803_puzzle_read_fan_speed(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon, -+ int channel, long *value) -+{ -+ unsigned char *resp_buf = mcu_hwmon->response_buffer; -+ unsigned char fan_speed_cmd[4] = {}; -+ size_t reply_size; -+ int ret; -+ -+ fan_speed_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ fan_speed_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN; -+ fan_speed_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_RPM(channel); -+ -+ mutex_lock(&mcu_hwmon->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, fan_speed_cmd, -+ sizeof(fan_speed_cmd), resp_buf, -+ &reply_size); -+ if (ret) -+ goto exit; -+ -+ if (reply_size != 7) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ *value = raw_fan_val_to_rpm(resp_buf[3], resp_buf[4]); -+exit: -+ mutex_unlock(&mcu_hwmon->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_write_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon, -+ int channel, long pwm_set_val) -+{ -+ unsigned char *resp_buf = mcu_hwmon->response_buffer; -+ unsigned char pwm_set_cmd[6] = {}; -+ size_t reply_size; -+ int ret; -+ -+ pwm_set_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ pwm_set_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN; -+ pwm_set_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE; -+ pwm_set_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel); -+ pwm_set_cmd[4] = pwm_set_val; -+ -+ mutex_lock(&mcu_hwmon->lock); -+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_set_cmd, -+ sizeof(pwm_set_cmd), resp_buf, -+ &reply_size); -+ if (ret) -+ goto exit; -+ -+ if (reply_size != 3) { -+ ret = -EIO; -+ goto exit; -+ } -+ -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) { -+ ret = -EIO; -+ goto exit; -+ } -+exit: -+ mutex_unlock(&mcu_hwmon->lock); -+ return ret; -+} -+ -+static int iei_wt61p803_puzzle_read_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon, -+ int channel, long *value) -+{ -+ unsigned char *resp_buf = mcu_hwmon->response_buffer; -+ unsigned char pwm_get_cmd[5] = {}; -+ size_t reply_size; -+ int ret; -+ -+ pwm_get_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ pwm_get_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN; -+ pwm_get_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ; -+ pwm_get_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel); -+ -+ ret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_get_cmd, -+ sizeof(pwm_get_cmd), resp_buf, -+ &reply_size); -+ if (ret) -+ return ret; -+ -+ if (reply_size != 5) -+ return -EIO; -+ -+ if (resp_buf[2] != IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ) -+ return -EIO; -+ -+ *value = resp_buf[3]; -+ -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *val) -+{ -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent); -+ -+ switch (type) { -+ case hwmon_pwm: -+ return iei_wt61p803_puzzle_read_pwm_channel(mcu_hwmon, channel, val); -+ case hwmon_fan: -+ return iei_wt61p803_puzzle_read_fan_speed(mcu_hwmon, channel, val); -+ case hwmon_temp: -+ return iei_wt61p803_puzzle_read_temp_sensor(mcu_hwmon, channel, val); -+ default: -+ return -EINVAL; -+ } -+} -+ -+static int iei_wt61p803_puzzle_write(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long val) -+{ -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent); -+ -+ return iei_wt61p803_puzzle_write_pwm_channel(mcu_hwmon, channel, val); -+} -+ -+static umode_t iei_wt61p803_puzzle_is_visible(const void *data, enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ const struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = data; -+ -+ switch (type) { -+ case hwmon_pwm: -+ if (mcu_hwmon->thermal_cooling_dev_present[channel]) -+ return 0444; -+ if (attr == hwmon_pwm_input) -+ return 0644; -+ break; -+ case hwmon_fan: -+ if (attr == hwmon_fan_input) -+ return 0444; -+ break; -+ case hwmon_temp: -+ if (attr == hwmon_temp_input) -+ return 0444; -+ break; -+ default: -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static const struct hwmon_ops iei_wt61p803_puzzle_hwmon_ops = { -+ .is_visible = iei_wt61p803_puzzle_is_visible, -+ .read = iei_wt61p803_puzzle_read, -+ .write = iei_wt61p803_puzzle_write, -+}; -+ -+static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = { -+ HWMON_CHANNEL_INFO(pwm, -+ HWMON_PWM_INPUT, -+ HWMON_PWM_INPUT), -+ HWMON_CHANNEL_INFO(fan, -+ HWMON_F_INPUT, -+ HWMON_F_INPUT, -+ HWMON_F_INPUT, -+ HWMON_F_INPUT, -+ HWMON_F_INPUT), -+ HWMON_CHANNEL_INFO(temp, -+ HWMON_T_INPUT, -+ HWMON_T_INPUT), -+ NULL -+}; -+ -+static const struct hwmon_chip_info iei_wt61p803_puzzle_chip_info = { -+ .ops = &iei_wt61p803_puzzle_hwmon_ops, -+ .info = iei_wt61p803_puzzle_info, -+}; -+ -+static int iei_wt61p803_puzzle_get_max_state(struct thermal_cooling_device *tcdev, -+ unsigned long *state) -+{ -+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata; -+ -+ if (!cdev) -+ return -EINVAL; -+ -+ *state = cdev->num_levels - 1; -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_get_cur_state(struct thermal_cooling_device *tcdev, -+ unsigned long *state) -+{ -+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata; -+ -+ if (!cdev) -+ return -EINVAL; -+ -+ if (cdev->cur_level < 0) -+ return -EAGAIN; -+ -+ *state = cdev->cur_level; -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_set_cur_state(struct thermal_cooling_device *tcdev, -+ unsigned long state) -+{ -+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata; -+ u8 pwm_level; -+ -+ if (!cdev) -+ return -EINVAL; -+ -+ if (state >= cdev->num_levels) -+ return -EINVAL; -+ -+ if (state == cdev->cur_level) -+ return 0; -+ -+ cdev->cur_level = state; -+ pwm_level = cdev->cooling_levels[state]; -+ -+ return iei_wt61p803_puzzle_write_pwm_channel(cdev->mcu_hwmon, cdev->pwm_channel, pwm_level); -+} -+ -+static const struct thermal_cooling_device_ops iei_wt61p803_puzzle_cooling_ops = { -+ .get_max_state = iei_wt61p803_puzzle_get_max_state, -+ .get_cur_state = iei_wt61p803_puzzle_get_cur_state, -+ .set_cur_state = iei_wt61p803_puzzle_set_cur_state, -+}; -+ -+static int -+iei_wt61p803_puzzle_enable_thermal_cooling_dev(struct device *dev, -+ struct fwnode_handle *child, -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon) -+{ -+ struct iei_wt61p803_puzzle_thermal_cooling_device *cdev; -+ u32 pwm_channel; -+ u8 num_levels; -+ int i, ret; -+ -+ ret = fwnode_property_read_u32(child, "reg", &pwm_channel); -+ if (ret) -+ return ret; -+ -+ mcu_hwmon->thermal_cooling_dev_present[pwm_channel] = true; -+ -+ num_levels = fwnode_property_count_u32(child, "cooling-levels"); -+ if (!num_levels) -+ return -EINVAL; -+ -+ cdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL); -+ if (!cdev) -+ return -ENOMEM; -+ -+ cdev->cooling_levels = devm_kmalloc_array(dev, num_levels, sizeof(u32), GFP_KERNEL); -+ if (!cdev->cooling_levels) -+ return -ENOMEM; -+ -+ ret = fwnode_property_read_u32_array(child, "cooling-levels", -+ cdev->cooling_levels, -+ num_levels); -+ if (ret) { -+ dev_err(dev, "Couldn't read property 'cooling-levels'\n"); -+ return ret; -+ } -+ -+ for (i = 0; i < num_levels; i++) { -+ if (cdev->cooling_levels[i] > -+ IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL) { -+ dev_err(dev, "iei_wt61p803_fan state[%d]:%d > %d\n", i, -+ cdev->cooling_levels[i], -+ IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL); -+ return -EINVAL; -+ } -+ } -+ -+ cdev->mcu_hwmon = mcu_hwmon; -+ cdev->pwm_channel = pwm_channel; -+ cdev->num_levels = num_levels; -+ cdev->cur_level = -1; -+ mcu_hwmon->cdev[pwm_channel] = cdev; -+ -+ snprintf(cdev->name, THERMAL_NAME_LENGTH, "wt61p803_puzzle_%d", pwm_channel); -+ cdev->tcdev = devm_thermal_of_cooling_device_register(dev, to_of_node(child), cdev->name, -+ cdev, &iei_wt61p803_puzzle_cooling_ops); -+ if (IS_ERR(cdev->tcdev)) -+ return PTR_ERR(cdev->tcdev); -+ -+ return 0; -+} -+ -+static int iei_wt61p803_puzzle_hwmon_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent); -+ struct iei_wt61p803_puzzle_hwmon *mcu_hwmon; -+ struct fwnode_handle *child; -+ struct device *hwmon_dev; -+ int ret; -+ -+ mcu_hwmon = devm_kzalloc(dev, sizeof(*mcu_hwmon), GFP_KERNEL); -+ if (!mcu_hwmon) -+ return -ENOMEM; -+ -+ mcu_hwmon->mcu = mcu; -+ platform_set_drvdata(pdev, mcu_hwmon); -+ mutex_init(&mcu_hwmon->lock); -+ -+ hwmon_dev = devm_hwmon_device_register_with_info(dev, "iei_wt61p803_puzzle", -+ mcu_hwmon, -+ &iei_wt61p803_puzzle_chip_info, -+ NULL); -+ if (IS_ERR(hwmon_dev)) -+ return PTR_ERR(hwmon_dev); -+ -+ /* Control fans via PWM lines via Linux Kernel */ -+ if (IS_ENABLED(CONFIG_THERMAL)) { -+ device_for_each_child_node(dev, child) { -+ ret = iei_wt61p803_puzzle_enable_thermal_cooling_dev(dev, child, mcu_hwmon); -+ if (ret) { -+ dev_err(dev, "Enabling the PWM fan failed\n"); -+ fwnode_handle_put(child); -+ return ret; -+ } -+ } -+ } -+ return 0; -+} -+ -+static const struct of_device_id iei_wt61p803_puzzle_hwmon_id_table[] = { -+ { .compatible = "iei,wt61p803-puzzle-hwmon" }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_hwmon_id_table); -+ -+static struct platform_driver iei_wt61p803_puzzle_hwmon_driver = { -+ .driver = { -+ .name = "iei-wt61p803-puzzle-hwmon", -+ .of_match_table = iei_wt61p803_puzzle_hwmon_id_table, -+ }, -+ .probe = iei_wt61p803_puzzle_hwmon_probe, -+}; -+ -+module_platform_driver(iei_wt61p803_puzzle_hwmon_driver); -+ -+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE MCU HWMON Driver"); -+MODULE_AUTHOR("Luka Kovacic "); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/mvebu/patches-5.10/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch b/target/linux/mvebu/patches-5.10/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch deleted file mode 100644 index 3ac2427b80..0000000000 --- a/target/linux/mvebu/patches-5.10/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch +++ /dev/null @@ -1,207 +0,0 @@ -From f3b44eb69cc561cf05d00506dcec0dd9be003ed8 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:35 +0000 -Subject: [PATCH 4/7] drivers: leds: Add the IEI WT61P803 PUZZLE LED driver - -Add support for the IEI WT61P803 PUZZLE LED driver. -Currently only the front panel power LED is supported, -since it is the only LED on this board wired through the -MCU. - -The LED is wired directly to the on-board MCU controller -and is toggled using an MCU command. - -Support for more LEDs is going to be added in case more -boards implement this microcontroller, as LEDs use many -different GPIOs. - -This driver depends on the IEI WT61P803 PUZZLE MFD driver. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - drivers/leds/Kconfig | 8 ++ - drivers/leds/Makefile | 1 + - drivers/leds/leds-iei-wt61p803-puzzle.c | 147 ++++++++++++++++++++++++ - 3 files changed, 156 insertions(+) - create mode 100644 drivers/leds/leds-iei-wt61p803-puzzle.c - ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -334,6 +334,14 @@ config LEDS_IPAQ_MICRO - Choose this option if you want to use the notification LED on - Compaq/HP iPAQ h3100 and h3600. - -+config LEDS_IEI_WT61P803_PUZZLE -+ tristate "LED Support for the IEI WT61P803 PUZZLE MCU" -+ depends on LEDS_CLASS -+ depends on MFD_IEI_WT61P803_PUZZLE -+ help -+ This option enables support for LEDs controlled by the IEI WT61P803 -+ M801 MCU. -+ - config LEDS_HP6XX - tristate "LED Support for the HP Jornada 6xx" - depends on LEDS_CLASS ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -35,6 +35,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx. - obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o - obj-$(CONFIG_LEDS_IP30) += leds-ip30.o - obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o -+obj-$(CONFIG_LEDS_IEI_WT61P803_PUZZLE) += leds-iei-wt61p803-puzzle.o - obj-$(CONFIG_LEDS_IS31FL319X) += leds-is31fl319x.o - obj-$(CONFIG_LEDS_IS31FL32XX) += leds-is31fl32xx.o - obj-$(CONFIG_LEDS_KTD2692) += leds-ktd2692.o ---- /dev/null -+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c -@@ -0,0 +1,147 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* IEI WT61P803 PUZZLE MCU LED Driver -+ * -+ * Copyright (C) 2020 Sartura Ltd. -+ * Author: Luka Kovacic -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+enum iei_wt61p803_puzzle_led_state { -+ IEI_LED_OFF = 0x30, -+ IEI_LED_ON = 0x31, -+ IEI_LED_BLINK_5HZ = 0x32, -+ IEI_LED_BLINK_1HZ = 0x33, -+}; -+ -+/** -+ * struct iei_wt61p803_puzzle_led - MCU LED Driver -+ * @cdev: LED classdev -+ * @mcu: MCU struct pointer -+ * @response_buffer Global MCU response buffer -+ * @lock: General mutex lock to protect simultaneous R/W access to led_power_state -+ * @led_power_state: State of the front panel power LED -+ */ -+struct iei_wt61p803_puzzle_led { -+ struct led_classdev cdev; -+ struct iei_wt61p803_puzzle *mcu; -+ unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE]; -+ struct mutex lock; /* mutex to protect led_power_state */ -+ int led_power_state; -+}; -+ -+static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led -+ (struct led_classdev *led_cdev) -+{ -+ return container_of(led_cdev, struct iei_wt61p803_puzzle_led, cdev); -+} -+ -+static int iei_wt61p803_puzzle_led_brightness_set_blocking(struct led_classdev *cdev, -+ enum led_brightness brightness) -+{ -+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev); -+ unsigned char *resp_buf = priv->response_buffer; -+ unsigned char led_power_cmd[5] = {}; -+ size_t reply_size; -+ int ret; -+ -+ led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED; -+ led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER; -+ led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON; -+ -+ ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd, -+ sizeof(led_power_cmd), -+ resp_buf, -+ &reply_size); -+ if (ret) -+ return ret; -+ -+ if (reply_size != 3) -+ return -EIO; -+ -+ if (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) -+ return -EIO; -+ -+ mutex_lock(&priv->lock); -+ priv->led_power_state = brightness; -+ mutex_unlock(&priv->lock); -+ -+ return 0; -+} -+ -+static enum led_brightness iei_wt61p803_puzzle_led_brightness_get(struct led_classdev *cdev) -+{ -+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev); -+ int led_state; -+ -+ mutex_lock(&priv->lock); -+ led_state = priv->led_power_state; -+ mutex_unlock(&priv->lock); -+ -+ return led_state; -+} -+ -+static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent); -+ struct iei_wt61p803_puzzle_led *priv; -+ struct led_init_data init_data = {}; -+ struct fwnode_handle *child; -+ int ret; -+ -+ if (device_get_child_node_count(dev) != 1) -+ return -EINVAL; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->mcu = mcu; -+ priv->led_power_state = 1; -+ mutex_init(&priv->lock); -+ dev_set_drvdata(dev, priv); -+ -+ child = device_get_next_child_node(dev, NULL); -+ init_data.fwnode = child; -+ -+ priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking; -+ priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get; -+ priv->cdev.max_brightness = 1; -+ -+ ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data); -+ if (ret) -+ dev_err(dev, "Could not register LED\n"); -+ -+ fwnode_handle_put(child); -+ return ret; -+} -+ -+static const struct of_device_id iei_wt61p803_puzzle_led_of_match[] = { -+ { .compatible = "iei,wt61p803-puzzle-leds" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_led_of_match); -+ -+static struct platform_driver iei_wt61p803_puzzle_led_driver = { -+ .driver = { -+ .name = "iei-wt61p803-puzzle-led", -+ .of_match_table = iei_wt61p803_puzzle_led_of_match, -+ }, -+ .probe = iei_wt61p803_puzzle_led_probe, -+}; -+module_platform_driver(iei_wt61p803_puzzle_led_driver); -+ -+MODULE_DESCRIPTION("IEI WT61P803 PUZZLE front panel LED driver"); -+MODULE_AUTHOR("Luka Kovacic "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:leds-iei-wt61p803-puzzle"); diff --git a/target/linux/mvebu/patches-5.10/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch b/target/linux/mvebu/patches-5.10/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch deleted file mode 100644 index b1d420ef0a..0000000000 --- a/target/linux/mvebu/patches-5.10/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 2fab3b4956c5b2f83c1e1abffc1df39de2933d83 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:36 +0000 -Subject: [PATCH 5/7] Documentation/ABI: Add iei-wt61p803-puzzle driver sysfs - interface documentation - -Add the iei-wt61p803-puzzle driver sysfs interface documentation to allow -monitoring and control of the microcontroller from user space. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - .../testing/sysfs-driver-iei-wt61p803-puzzle | 61 +++++++++++++++++++ - 1 file changed, 61 insertions(+) - create mode 100644 Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle - ---- /dev/null -+++ b/Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle -@@ -0,0 +1,61 @@ -+What: /sys/bus/serial/devices/.../mac_address_* -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RW) Internal factory assigned MAC address values -+ -+What: /sys/bus/serial/devices/.../serial_number -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RW) Internal factory assigned serial number -+ -+What: /sys/bus/serial/devices/.../version -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Internal MCU firmware version -+ -+What: /sys/bus/serial/devices/.../protocol_version -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Internal MCU communication protocol version -+ -+What: /sys/bus/serial/devices/.../power_loss_recovery -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RW) Host platform power loss recovery settings -+ Value mapping: 0 - Always-On, 1 - Always-Off, 2 - Always-AC, 3 - Always-WA -+ -+What: /sys/bus/serial/devices/.../bootloader_mode -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Internal MCU bootloader mode status -+ Value mapping: -+ 0 - normal mode -+ 1 - bootloader mode -+ -+What: /sys/bus/serial/devices/.../power_status -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Power status indicates the host platform power on method. -+ Value mapping (bitwise list): -+ 0x80 - Null -+ 0x40 - Firmware flag -+ 0x20 - Power loss detection flag (powered off) -+ 0x10 - Power loss detection flag (AC mode) -+ 0x08 - Button power on -+ 0x04 - Wake-on-LAN power on -+ 0x02 - RTC alarm power on -+ 0x01 - AC recover power on -+ -+What: /sys/bus/serial/devices/.../build_info -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Internal MCU firmware build date -+ Format: yyyy/mm/dd hh:mm -+ -+What: /sys/bus/serial/devices/.../ac_recovery_status -+Date: September 2020 -+Contact: Luka Kovacic -+Description: (RO) Host platform AC recovery status value -+ Value mapping: -+ 0 - board has not been recovered from power down -+ 1 - board has been recovered from power down diff --git a/target/linux/mvebu/patches-5.10/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch b/target/linux/mvebu/patches-5.10/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch deleted file mode 100644 index 345d4ca03b..0000000000 --- a/target/linux/mvebu/patches-5.10/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 0aff3e5923fecc6842473ad07a688d6e2f2c2d55 Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:37 +0000 -Subject: [PATCH 6/7] Documentation/hwmon: Add iei-wt61p803-puzzle hwmon driver - documentation - -Add the iei-wt61p803-puzzle driver hwmon driver interface documentation. - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - .../hwmon/iei-wt61p803-puzzle-hwmon.rst | 43 +++++++++++++++++++ - Documentation/hwmon/index.rst | 1 + - 2 files changed, 44 insertions(+) - create mode 100644 Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst - ---- /dev/null -+++ b/Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst -@@ -0,0 +1,43 @@ -+.. SPDX-License-Identifier: GPL-2.0-only -+ -+Kernel driver iei-wt61p803-puzzle-hwmon -+======================================= -+ -+Supported chips: -+ * IEI WT61P803 PUZZLE for IEI Puzzle M801 -+ -+ Prefix: 'iei-wt61p803-puzzle-hwmon' -+ -+Author: Luka Kovacic -+ -+ -+Description -+----------- -+ -+This driver adds fan and temperature sensor reading for some IEI Puzzle -+series boards. -+ -+Sysfs attributes -+---------------- -+ -+The following attributes are supported: -+ -+- IEI WT61P803 PUZZLE for IEI Puzzle M801 -+ -+/sys files in hwmon subsystem -+----------------------------- -+ -+================= == ===================================================== -+fan[1-5]_input RO files for fan speed (in RPM) -+pwm[1-2] RW files for fan[1-2] target duty cycle (0..255) -+temp[1-2]_input RO files for temperature sensors, in millidegree Celsius -+================= == ===================================================== -+ -+/sys files in thermal subsystem -+------------------------------- -+ -+================= == ===================================================== -+cur_state RW file for current cooling state of the cooling device -+ (0..max_state) -+max_state RO file for maximum cooling state of the cooling device -+================= == ===================================================== ---- a/Documentation/hwmon/index.rst -+++ b/Documentation/hwmon/index.rst -@@ -71,6 +71,7 @@ Hardware Monitoring Kernel Drivers - ibmaem - ibm-cffps - ibmpowernv -+ iei-wt61p803-puzzle-hwmon - ina209 - ina2xx - ina3221 diff --git a/target/linux/mvebu/patches-5.10/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch b/target/linux/mvebu/patches-5.10/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch deleted file mode 100644 index 577a9b40de..0000000000 --- a/target/linux/mvebu/patches-5.10/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 12479baad28d2a08c6cb9e83471057635fa1635c Mon Sep 17 00:00:00 2001 -From: Luka Kovacic -Date: Tue, 24 Aug 2021 12:44:38 +0000 -Subject: [PATCH 7/7] MAINTAINERS: Add an entry for the IEI WT61P803 PUZZLE - driver - -Add an entry for the IEI WT61P803 PUZZLE driver (MFD, HWMON, LED drivers). - -Signed-off-by: Luka Kovacic -Signed-off-by: Pavo Banicevic -Cc: Luka Perkov -Cc: Robert Marko ---- - MAINTAINERS | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -8538,6 +8538,22 @@ F: include/net/nl802154.h - F: net/ieee802154/ - F: net/mac802154/ - -+IEI WT61P803 M801 MFD DRIVER -+M: Luka Kovacic -+M: Luka Perkov -+M: Goran Medic -+L: linux-kernel@vger.kernel.org -+S: Maintained -+F: Documentation/ABI/stable/sysfs-driver-iei-wt61p803-puzzle -+F: Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml -+F: Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml -+F: Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml -+F: Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst -+F: drivers/hwmon/iei-wt61p803-puzzle-hwmon.c -+F: drivers/leds/leds-iei-wt61p803-puzzle.c -+F: drivers/mfd/iei-wt61p803-puzzle.c -+F: include/linux/mfd/iei-wt61p803-puzzle.h -+ - IFE PROTOCOL - M: Yotam Gigi - M: Jamal Hadi Salim diff --git a/target/linux/mvebu/patches-5.10/910-drivers-leds-wt61p803-puzzle-improvements.patch b/target/linux/mvebu/patches-5.10/910-drivers-leds-wt61p803-puzzle-improvements.patch deleted file mode 100644 index 150a65498c..0000000000 --- a/target/linux/mvebu/patches-5.10/910-drivers-leds-wt61p803-puzzle-improvements.patch +++ /dev/null @@ -1,271 +0,0 @@ ---- a/drivers/leds/leds-iei-wt61p803-puzzle.c -+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c -@@ -9,9 +9,13 @@ - #include - #include - #include -+#include - #include - #include - #include -+#include -+ -+#define IEI_LEDS_MAX 4 - - enum iei_wt61p803_puzzle_led_state { - IEI_LED_OFF = 0x30, -@@ -33,7 +37,11 @@ struct iei_wt61p803_puzzle_led { - struct iei_wt61p803_puzzle *mcu; - unsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE]; - struct mutex lock; /* mutex to protect led_power_state */ -+ struct work_struct work; - int led_power_state; -+ int id; -+ u8 blinking; -+ bool active_low; - }; - - static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led -@@ -51,10 +59,18 @@ static int iei_wt61p803_puzzle_led_brigh - size_t reply_size; - int ret; - -+ if (priv->blinking) { -+ if (brightness == LED_OFF) -+ priv->blinking = 0; -+ else -+ return 0; -+ } -+ - led_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; - led_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED; -- led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER; -- led_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON; -+ led_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id); -+ led_power_cmd[3] = ((brightness == LED_OFF) ^ priv->active_low) ? -+ IEI_LED_OFF : priv->blinking?priv->blinking:IEI_LED_ON; - - ret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd, - sizeof(led_power_cmd), -@@ -90,39 +106,166 @@ static enum led_brightness iei_wt61p803_ - return led_state; - } - -+static void iei_wt61p803_puzzle_led_apply_blink(struct work_struct *work) -+{ -+ struct iei_wt61p803_puzzle_led *priv = container_of(work, struct iei_wt61p803_puzzle_led, work); -+ unsigned char led_blink_cmd[5] = {}; -+ unsigned char resp_buf[IEI_WT61P803_PUZZLE_BUF_SIZE]; -+ size_t reply_size; -+ -+ led_blink_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START; -+ led_blink_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED; -+ led_blink_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id); -+ led_blink_cmd[3] = priv->blinking; -+ -+ iei_wt61p803_puzzle_write_command(priv->mcu, led_blink_cmd, -+ sizeof(led_blink_cmd), -+ resp_buf, -+ &reply_size); -+ -+ return; -+} -+ -+static int iei_wt61p803_puzzle_led_set_blink(struct led_classdev *cdev, -+ unsigned long *delay_on, -+ unsigned long *delay_off) -+{ -+ struct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev); -+ u8 blink_mode = 0; -+ int ret = 0; -+ -+ /* set defaults */ -+ if (!*delay_on && !*delay_off) { -+ *delay_on = 500; -+ *delay_off = 500; -+ } -+ -+ /* minimum delay for soft-driven blinking is 100ms to keep load low */ -+ if (*delay_on < 100) -+ *delay_on = 100; -+ -+ if (*delay_off < 100) -+ *delay_off = 100; -+ -+ /* offload blinking to hardware, if possible */ -+ if (*delay_on != *delay_off) { -+ ret = -EINVAL; -+ } else if (*delay_on == 100) { -+ blink_mode = IEI_LED_BLINK_5HZ; -+ *delay_on = 100; -+ *delay_off = 100; -+ } else if (*delay_on <= 500) { -+ blink_mode = IEI_LED_BLINK_1HZ; -+ *delay_on = 500; -+ *delay_off = 500; -+ } else { -+ ret = -EINVAL; -+ } -+ -+ mutex_lock(&priv->lock); -+ priv->blinking = blink_mode; -+ mutex_unlock(&priv->lock); -+ -+ if (blink_mode) -+ schedule_work(&priv->work); -+ -+ return ret; -+} -+ -+ -+static int iei_wt61p803_puzzle_led_set_dt_default(struct led_classdev *cdev, -+ struct device_node *np) -+{ -+ const char *state; -+ int ret = 0; -+ -+ state = of_get_property(np, "default-state", NULL); -+ if (state) { -+ if (!strcmp(state, "on")) { -+ ret = -+ iei_wt61p803_puzzle_led_brightness_set_blocking( -+ cdev, cdev->max_brightness); -+ } else { -+ ret = iei_wt61p803_puzzle_led_brightness_set_blocking( -+ cdev, LED_OFF); -+ } -+ } -+ -+ return ret; -+} -+ - static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -+ struct device_node *np = dev_of_node(dev); -+ struct device_node *child; - struct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent); - struct iei_wt61p803_puzzle_led *priv; -- struct led_init_data init_data = {}; -- struct fwnode_handle *child; - int ret; -+ u32 reg; - -- if (device_get_child_node_count(dev) != 1) -+ if (device_get_child_node_count(dev) > IEI_LEDS_MAX) - return -EINVAL; - -- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -- if (!priv) -- return -ENOMEM; -- -- priv->mcu = mcu; -- priv->led_power_state = 1; -- mutex_init(&priv->lock); -- dev_set_drvdata(dev, priv); -- -- child = device_get_next_child_node(dev, NULL); -- init_data.fwnode = child; -- -- priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking; -- priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get; -- priv->cdev.max_brightness = 1; -+ for_each_available_child_of_node(np, child) { -+ struct led_init_data init_data = {}; - -- ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data); -- if (ret) -- dev_err(dev, "Could not register LED\n"); -+ ret = of_property_read_u32(child, "reg", ®); -+ if (ret) { -+ dev_err(dev, "Failed to read led 'reg' property\n"); -+ goto put_child_node; -+ } -+ -+ if (reg > IEI_LEDS_MAX) { -+ dev_err(dev, "Invalid led reg %u\n", reg); -+ ret = -EINVAL; -+ goto put_child_node; -+ } -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) { -+ ret = -ENOMEM; -+ goto put_child_node; -+ } -+ -+ mutex_init(&priv->lock); -+ -+ dev_set_drvdata(dev, priv); -+ -+ if (of_property_read_bool(child, "active-low")) -+ priv->active_low = true; -+ -+ priv->mcu = mcu; -+ priv->id = reg; -+ priv->led_power_state = 1; -+ priv->blinking = 0; -+ init_data.fwnode = of_fwnode_handle(child); -+ -+ priv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking; -+ priv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get; -+ priv->cdev.blink_set = iei_wt61p803_puzzle_led_set_blink; -+ -+ priv->cdev.max_brightness = 1; -+ -+ INIT_WORK(&priv->work, iei_wt61p803_puzzle_led_apply_blink); -+ -+ ret = iei_wt61p803_puzzle_led_set_dt_default(&priv->cdev, child); -+ if (ret) { -+ dev_err(dev, "Could apply default from DT\n"); -+ goto put_child_node; -+ } -+ -+ ret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data); -+ if (ret) { -+ dev_err(dev, "Could not register LED\n"); -+ goto put_child_node; -+ } -+ } -+ -+ return ret; - -- fwnode_handle_put(child); -+put_child_node: -+ of_node_put(child); - return ret; - } - ---- a/include/linux/mfd/iei-wt61p803-puzzle.h -+++ b/include/linux/mfd/iei-wt61p803-puzzle.h -@@ -36,7 +36,7 @@ - #define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */ - - #define IEI_WT61P803_PUZZLE_CMD_LED 0x52 /* R */ --#define IEI_WT61P803_PUZZLE_CMD_LED_POWER 0x31 /* 1 */ -+#define IEI_WT61P803_PUZZLE_CMD_LED_SET(n) (0x30 | (n)) - - #define IEI_WT61P803_PUZZLE_CMD_TEMP 0x54 /* T */ - #define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL 0x41 /* A */ ---- a/drivers/mfd/iei-wt61p803-puzzle.c -+++ b/drivers/mfd/iei-wt61p803-puzzle.c -@@ -176,6 +176,9 @@ static int iei_wt61p803_puzzle_recv_buf( - struct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev); - int ret; - -+ print_hex_dump_debug("puzzle-mcu rx: ", DUMP_PREFIX_NONE, -+ 16, 1, data, size, false); -+ - ret = iei_wt61p803_puzzle_process_resp(mcu, data, size); - /* Return the number of processed bytes if function returns error, - * discard the remaining incoming data, since the frame this data -@@ -246,6 +249,9 @@ int iei_wt61p803_puzzle_write_command(st - - cmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1); - -+ print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE, -+ 16, 1, cmd, size, false); -+ - /* Initialize reply struct */ - reinit_completion(&mcu->reply->received); - mcu->reply->size = 0; diff --git a/target/linux/mvebu/patches-5.10/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch b/target/linux/mvebu/patches-5.10/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch deleted file mode 100644 index 2f0b1788ff..0000000000 --- a/target/linux/mvebu/patches-5.10/911-drivers-leds-wt61p803-puzzle-mcu-retry.patch +++ /dev/null @@ -1,63 +0,0 @@ ---- a/drivers/mfd/iei-wt61p803-puzzle.c -+++ b/drivers/mfd/iei-wt61p803-puzzle.c -@@ -241,6 +241,7 @@ int iei_wt61p803_puzzle_write_command(st - { - struct device *dev = &mcu->serdev->dev; - int ret; -+ int retries; - - if (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH) - return -EINVAL; -@@ -252,24 +253,36 @@ int iei_wt61p803_puzzle_write_command(st - print_hex_dump_debug("puzzle-mcu tx: ", DUMP_PREFIX_NONE, - 16, 1, cmd, size, false); - -+ retries = 3; - /* Initialize reply struct */ -- reinit_completion(&mcu->reply->received); -- mcu->reply->size = 0; -- usleep_range(2000, 10000); -- serdev_device_write_flush(mcu->serdev); -- ret = serdev_device_write_buf(mcu->serdev, cmd, size); -- if (ret < 0) -- goto exit; -- -- serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -- ret = wait_for_completion_timeout(&mcu->reply->received, -- IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -- if (ret == 0) { -- dev_err(dev, "Command reply receive timeout\n"); -- ret = -ETIMEDOUT; -- goto exit; -+ while (retries) { -+ reinit_completion(&mcu->reply->received); -+ mcu->reply->size = 0; -+ usleep_range(2000, 10000); -+ serdev_device_write_flush(mcu->serdev); -+ ret = serdev_device_write_buf(mcu->serdev, cmd, size); -+ if (ret < 0) -+ goto exit; -+ -+ serdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -+ ret = wait_for_completion_timeout(&mcu->reply->received, -+ IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT); -+ retries--; -+ if (ret == 0) { -+ if (retries == 0) { -+ dev_err(dev, "Command reply receive timeout\n"); -+ ret = -ETIMEDOUT; -+ goto exit; -+ } -+ } -+ else { -+ if (mcu->reply->data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START && -+ mcu->reply->data[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK && -+ mcu->reply->data[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK) { -+ break; -+ } -+ } - } -- - *reply_size = mcu->reply->size; - /* Copy the received data, as it will not be available after a new frame is received */ - memcpy(reply_data, mcu->reply->data, mcu->reply->size); diff --git a/target/linux/octeon/config-5.10 b/target/linux/octeon/config-5.10 deleted file mode 100644 index 58a02e6e6d..0000000000 --- a/target/linux/octeon/config-5.10 +++ /dev/null @@ -1,250 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS=12 -CONFIG_ARCH_MMAP_RND_BITS_MAX=18 -CONFIG_ARCH_MMAP_RND_BITS_MIN=12 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BUILTIN_DTB=y -CONFIG_CAVIUM_CN63XXP1=y -CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=0 -CONFIG_CAVIUM_OCTEON_LOCK_L2=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y -CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y -CONFIG_CAVIUM_OCTEON_SOC=y -CONFIG_CEVT_R4K=y -CONFIG_CLONE_BACKWARDS=y -# CONFIG_COMMON_CLK is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_CAVIUM_OCTEON=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS64=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_HUGEPAGES=y -CONFIG_CRAMFS=y -CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -# CONFIG_CRYPTO_MD5_OCTEON is not set -CONFIG_CRYPTO_RNG2=y -# CONFIG_CRYPTO_SHA1_OCTEON is not set -# CONFIG_CRYPTO_SHA256_OCTEON is not set -# CONFIG_CRYPTO_SHA512_OCTEON is not set -CONFIG_DNOTIFY=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -# CONFIG_EDAC_DEBUG is not set -CONFIG_EDAC_LEGACY_SYSFS=y -CONFIG_EDAC_OCTEON_L2C=y -CONFIG_EDAC_OCTEON_LMC=y -CONFIG_EDAC_OCTEON_PC=y -CONFIG_EDAC_OCTEON_PCI=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FAT_FS=y -CONFIG_FIXED_PHY=y -CONFIG_FRAME_WARN=2048 -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_OCTEON=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_OCTEON=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_OCTEON=y -CONFIG_IMAGE_CMDLINE_HACK=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_CAVIUM=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_OCTEON=y -CONFIG_MEMFD_CREATE=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -# CONFIG_MIPS32_N32 is not set -# CONFIG_MIPS32_O32 is not set -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_MIPS_CMDLINE_FROM_DTB is not set -CONFIG_MIPS_EBPF_JIT=y -CONFIG_MIPS_ELF_APPENDED_DTB=y -CONFIG_MIPS_L1_CACHE_SHIFT=7 -CONFIG_MIPS_L1_CACHE_SHIFT_7=y -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_NR_CPU_NR_MAP=1024 -CONFIG_MIPS_NR_CPU_NR_MAP_1024=y -CONFIG_MIPS_PGD_C0_CONTEXT=y -# CONFIG_MIPS_RAW_APPENDED_DTB is not set -CONFIG_MIPS_SPRAM=y -# CONFIG_MIPS_VA_BITS_48 is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CAVIUM_OCTEON=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MODULES_USE_ELF_RELA=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NR_CPUS=16 -CONFIG_NR_CPUS_DEFAULT_64=y -CONFIG_NVMEM=y -CONFIG_OCTEON_ETHERNET=y -CONFIG_OCTEON_ILM=y -CONFIG_OCTEON_MGMT_ETHERNET=y -CONFIG_OCTEON_USB=y -CONFIG_OCTEON_WDT=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PADATA=y -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -CONFIG_RELAY=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_SCSI=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_STATIC=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_OCTEON=y -CONFIG_SRCU=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_RELOCATABLE=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -# CONFIG_USB_OCTEON_EHCI is not set -# CONFIG_USB_OCTEON_OHCI is not set -CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_VFAT_FS=y -CONFIG_VITESSE_PHY=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WEAK_ORDERING=y -CONFIG_XPS=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/octeon/patches-5.10/100-mips_image_cmdline_hack.patch b/target/linux/octeon/patches-5.10/100-mips_image_cmdline_hack.patch deleted file mode 100644 index 4edf527246..0000000000 --- a/target/linux/octeon/patches-5.10/100-mips_image_cmdline_hack.patch +++ /dev/null @@ -1,38 +0,0 @@ -From: John Crispin -Subject: hack: kernel: add generic image_cmdline hack to MIPS targets - -lede-commit: d59f5b3a987a48508257a0ddbaeadc7909f9f976 -Signed-off-by: Gabor Juhos ---- - arch/mips/Kconfig | 4 ++++ - arch/mips/kernel/head.S | 6 ++++++ - 2 files changed, 10 insertions(+) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -1170,6 +1170,10 @@ config MIPS_MSC - config SYNC_R4K - bool - -+config IMAGE_CMDLINE_HACK -+ bool "OpenWrt specific image command line hack" -+ default n -+ - config NO_IOPORT_MAP - def_bool n - ---- a/arch/mips/kernel/head.S -+++ b/arch/mips/kernel/head.S -@@ -79,6 +79,12 @@ FEXPORT(__kernel_entry) - j kernel_entry - #endif /* CONFIG_BOOT_RAW */ - -+#ifdef CONFIG_IMAGE_CMDLINE_HACK -+ .ascii "CMDLINE:" -+EXPORT(__image_cmdline) -+ .fill 0x400 -+#endif /* CONFIG_IMAGE_CMDLINE_HACK */ -+ - __REF - - NESTED(kernel_entry, 16, sp) # kernel entry point diff --git a/target/linux/octeon/patches-5.10/100-ubnt_edgerouter2_support.patch b/target/linux/octeon/patches-5.10/100-ubnt_edgerouter2_support.patch deleted file mode 100644 index 606debda7f..0000000000 --- a/target/linux/octeon/patches-5.10/100-ubnt_edgerouter2_support.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c -+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c -@@ -174,6 +174,8 @@ int cvmx_helper_board_get_mii_address(in - return 7 - ipd_port; - else - return -1; -+ case CVMX_BOARD_TYPE_UBNT_E200: -+ return -1; - case CVMX_BOARD_TYPE_KONTRON_S1901: - if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) - return 1; diff --git a/target/linux/octeon/patches-5.10/110-er200-ethernet_probe_order.patch b/target/linux/octeon/patches-5.10/110-er200-ethernet_probe_order.patch deleted file mode 100644 index b816e9c430..0000000000 --- a/target/linux/octeon/patches-5.10/110-er200-ethernet_probe_order.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/staging/octeon/ethernet.c -+++ b/drivers/staging/octeon/ethernet.c -@@ -679,6 +679,7 @@ static int cvm_oct_probe(struct platform - int interface; - int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; - int qos; -+ int i; - struct device_node *pip; - int mtu_overhead = ETH_HLEN + ETH_FCS_LEN; - -@@ -800,13 +801,19 @@ static int cvm_oct_probe(struct platform - } - - num_interfaces = cvmx_helper_get_number_of_interfaces(); -- for (interface = 0; interface < num_interfaces; interface++) { -- cvmx_helper_interface_mode_t imode = -- cvmx_helper_interface_get_mode(interface); -- int num_ports = cvmx_helper_ports_on_interface(interface); -+ for (i = 0; i < num_interfaces; i++) { -+ cvmx_helper_interface_mode_t imode; -+ int interface; -+ int num_ports; - int port; - int port_index; - -+ interface = i; -+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E200) -+ interface = num_interfaces - (i + 1); -+ -+ num_ports = cvmx_helper_ports_on_interface(interface); -+ imode = cvmx_helper_interface_get_mode(interface); - for (port_index = 0, - port = cvmx_helper_get_ipd_port(interface, 0); - port < cvmx_helper_get_ipd_port(interface, num_ports); diff --git a/target/linux/octeon/patches-5.10/120-cmdline-hack.patch b/target/linux/octeon/patches-5.10/120-cmdline-hack.patch deleted file mode 100644 index 91b2936d99..0000000000 --- a/target/linux/octeon/patches-5.10/120-cmdline-hack.patch +++ /dev/null @@ -1,47 +0,0 @@ ---- a/arch/mips/cavium-octeon/setup.c -+++ b/arch/mips/cavium-octeon/setup.c -@@ -654,6 +654,35 @@ void octeon_user_io_init(void) - write_c0_derraddr1(0); - } - -+#ifdef CONFIG_IMAGE_CMDLINE_HACK -+extern char __image_cmdline[]; -+ -+static int __init octeon_use_image_cmdline(void) -+{ -+ char *p = __image_cmdline; -+ int replace = 0; -+ -+ if (*p == '-') { -+ replace = 1; -+ p++; -+ } -+ -+ if (*p == '\0') -+ return 0; -+ -+ if (replace) { -+ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); -+ } else { -+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); -+ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); -+ } -+ -+ return 1; -+} -+#else -+static inline int octeon_use_image_cmdline(void) { return 0; } -+#endif -+ - /** - * Early entry point for arch setup - */ -@@ -898,6 +927,8 @@ void __init prom_init(void) - } - } - -+ octeon_use_image_cmdline(); -+ - if (strstr(arcs_cmdline, "console=") == NULL) { - if (octeon_uart == 1) - strcat(arcs_cmdline, " console=ttyS1,115200"); diff --git a/target/linux/octeon/patches-5.10/130-itus_shield_support.patch b/target/linux/octeon/patches-5.10/130-itus_shield_support.patch deleted file mode 100644 index a041331c20..0000000000 --- a/target/linux/octeon/patches-5.10/130-itus_shield_support.patch +++ /dev/null @@ -1,42 +0,0 @@ ---- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h -+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h -@@ -297,7 +297,7 @@ enum cvmx_board_types_enum { - CVMX_BOARD_TYPE_UBNT_E100 = 20002, - CVMX_BOARD_TYPE_UBNT_E200 = 20003, - CVMX_BOARD_TYPE_UBNT_E220 = 20005, -- CVMX_BOARD_TYPE_CUST_DSR1000N = 20006, -+ CVMX_BOARD_TYPE_ITUS_SHIELD = 20006, - CVMX_BOARD_TYPE_KONTRON_S1901 = 21901, - CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, - -@@ -400,7 +400,7 @@ static inline const char *cvmx_board_typ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220) -- ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N) -+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) - } ---- a/arch/mips/cavium-octeon/octeon-platform.c -+++ b/arch/mips/cavium-octeon/octeon-platform.c -@@ -774,7 +774,7 @@ int __init octeon_prune_device_tree(void - if (fdt_check_header(initial_boot_params)) - panic("Corrupt Device Tree."); - -- WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N, -+ WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_ITUS_SHIELD, - "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.", - cvmx_board_type_to_string(octeon_bootinfo->board_type)); - ---- a/arch/mips/pci/pci-octeon.c -+++ b/arch/mips/pci/pci-octeon.c -@@ -211,8 +211,6 @@ const char *octeon_get_pci_interrupts(vo - return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; - case CVMX_BOARD_TYPE_BBGW_REF: - return "AABCD"; -- case CVMX_BOARD_TYPE_CUST_DSR1000N: -- return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC"; - case CVMX_BOARD_TYPE_THUNDER: - case CVMX_BOARD_TYPE_EBH3000: - default: diff --git a/target/linux/octeon/patches-5.10/140-octeon_e300_support.patch b/target/linux/octeon/patches-5.10/140-octeon_e300_support.patch deleted file mode 100644 index 7fe56a47d1..0000000000 --- a/target/linux/octeon/patches-5.10/140-octeon_e300_support.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h -+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h -@@ -298,6 +298,7 @@ enum cvmx_board_types_enum { - CVMX_BOARD_TYPE_UBNT_E200 = 20003, - CVMX_BOARD_TYPE_UBNT_E220 = 20005, - CVMX_BOARD_TYPE_ITUS_SHIELD = 20006, -+ CVMX_BOARD_TYPE_UBNT_E300 = 20300, - CVMX_BOARD_TYPE_KONTRON_S1901 = 21901, - CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000, - -@@ -401,6 +402,7 @@ static inline const char *cvmx_board_typ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD) -+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E300) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX) - } diff --git a/target/linux/octeon/patches-5.10/150-ubnt_usg_support.patch b/target/linux/octeon/patches-5.10/150-ubnt_usg_support.patch deleted file mode 100644 index 88aa1c406f..0000000000 --- a/target/linux/octeon/patches-5.10/150-ubnt_usg_support.patch +++ /dev/null @@ -1,46 +0,0 @@ ---- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h -+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h -@@ -296,6 +296,7 @@ enum cvmx_board_types_enum { - CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001, - CVMX_BOARD_TYPE_UBNT_E100 = 20002, - CVMX_BOARD_TYPE_UBNT_E200 = 20003, -+ CVMX_BOARD_TYPE_UBNT_USG = 20004, - CVMX_BOARD_TYPE_UBNT_E220 = 20005, - CVMX_BOARD_TYPE_ITUS_SHIELD = 20006, - CVMX_BOARD_TYPE_UBNT_E300 = 20300, -@@ -399,6 +400,7 @@ static inline const char *cvmx_board_typ - /* Customer private range */ - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100) -+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_USG) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220) - ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD) ---- a/arch/mips/cavium-octeon/octeon-platform.c -+++ b/arch/mips/cavium-octeon/octeon-platform.c -@@ -635,6 +635,7 @@ static void __init octeon_rx_tx_delay(in - } - break; - case CVMX_BOARD_TYPE_UBNT_E100: -+ case CVMX_BOARD_TYPE_UBNT_USG: - if (iface == 0 && port <= 2) { - _octeon_rx_tx_delay(eth, 0x0, 0x10); - return; ---- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c -+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c -@@ -170,6 +170,7 @@ int cvmx_helper_board_get_mii_address(in - else - return -1; - case CVMX_BOARD_TYPE_UBNT_E100: -+ case CVMX_BOARD_TYPE_UBNT_USG: - if (ipd_port >= 0 && ipd_port <= 2) - return 7 - ipd_port; - else -@@ -337,6 +338,7 @@ enum cvmx_helper_board_usb_clock_types _ - case CVMX_BOARD_TYPE_LANAI2_G: - case CVMX_BOARD_TYPE_NIC10E_66: - case CVMX_BOARD_TYPE_UBNT_E100: -+ case CVMX_BOARD_TYPE_UBNT_USG: - return USB_CLOCK_TYPE_CRYSTAL_12; - case CVMX_BOARD_TYPE_NIC10E: - return USB_CLOCK_TYPE_REF_12; diff --git a/target/linux/octeon/patches-5.10/700-allocate_interface_by_label.patch b/target/linux/octeon/patches-5.10/700-allocate_interface_by_label.patch deleted file mode 100644 index e4dc3f96e5..0000000000 --- a/target/linux/octeon/patches-5.10/700-allocate_interface_by_label.patch +++ /dev/null @@ -1,37 +0,0 @@ -From: Roman Kuzmitskii -Date: Wed, 28 Oct 2020 19:00:00 +0000 -Subject: [PATCH] staging: octeon: add net-labels support - -With this patch, device name can be set within dts file -in the same way as dsa port can. - -Add label to pip interface node to use this feature: -label = "lan0"; - -Tested-by: Johannes Kimmel -Signed-off-by: Roman Kuzmitskii ---- a/drivers/staging/octeon/ethernet.c -+++ b/drivers/staging/octeon/ethernet.c -@@ -407,8 +407,12 @@ static int cvm_oct_common_set_mac_addres - int cvm_oct_common_init(struct net_device *dev) - { - struct octeon_ethernet *priv = netdev_priv(dev); -+ const u8 *label = NULL; - int ret; - -+ if (priv->of_node) -+ label = of_get_property(priv->of_node, "label", NULL); -+ - ret = of_get_mac_address(priv->of_node, dev->dev_addr); - if (ret) - eth_hw_addr_random(dev); -@@ -441,6 +445,9 @@ int cvm_oct_common_init(struct net_devic - if (dev->netdev_ops->ndo_stop) - dev->netdev_ops->ndo_stop(dev); - -+ if (!IS_ERR_OR_NULL(label)) -+ dev_alloc_name(dev, label); -+ - return 0; - } - diff --git a/target/linux/octeon/patches-5.10/701-honor_sgmii_node_device_tree_status.patch b/target/linux/octeon/patches-5.10/701-honor_sgmii_node_device_tree_status.patch deleted file mode 100644 index 4185fcba70..0000000000 --- a/target/linux/octeon/patches-5.10/701-honor_sgmii_node_device_tree_status.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Roman Kuzmitskii -Date: Sun, 01 Nov 2020 19:00:00 +0000 -Subject: [PATCH] staging: octeon: sgmii to honor disabled dt node status - -With this patch, sgmii interface device tree node could be disabled and -that disabled interface will not be unnecessarily initialized. - -It solves the problem with Octeon boards that have 8 sgmii or more ports -initialized but have nothing connected to them. - -Tested-by: Johannes Kimmel -Signed-off-by: Roman Kuzmitskii ---- a/drivers/staging/octeon/ethernet.c -+++ b/drivers/staging/octeon/ethernet.c -@@ -880,8 +880,10 @@ static int cvm_oct_probe(struct platform - - case CVMX_HELPER_INTERFACE_MODE_SGMII: - priv->phy_mode = PHY_INTERFACE_MODE_SGMII; -- dev->netdev_ops = &cvm_oct_sgmii_netdev_ops; -- strscpy(dev->name, "eth%d", sizeof(dev->name)); -+ if (of_device_is_available(priv->of_node)) { -+ dev->netdev_ops = &cvm_oct_sgmii_netdev_ops; -+ strscpy(dev->name, "eth%d", sizeof(dev->name)); -+ } - break; - - case CVMX_HELPER_INTERFACE_MODE_SPI: diff --git a/target/linux/omap/config-5.10 b/target/linux/omap/config-5.10 deleted file mode 100644 index c3178b4702..0000000000 --- a/target/linux/omap/config-5.10 +++ /dev/null @@ -1,678 +0,0 @@ -# CONFIG_AHCI_DM816 is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_AM335X_CONTROL_USB=y -CONFIG_AM335X_PHY_USB=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_ARCH_OMAP2PLUS_TYPICAL=y -CONFIG_ARCH_OMAP3=y -CONFIG_ARCH_OMAP4=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_ERRATA_430973=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_754322=y -CONFIG_ARM_ERRATA_775420=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_OMAP2PLUS_CPUFREQ=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_TI_CPUFREQ=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_AT803X_PHY=y -CONFIG_ATA=y -CONFIG_AUDIT=y -CONFIG_AUDITSYSCALL=y -CONFIG_AUDIT_GENERIC=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_TPS65217 is not set -CONFIG_BCH=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_CACHE_L2X0=y -CONFIG_CEC_CORE=y -# CONFIG_CHARGER_TPS65217 is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLKSRC_TI_32K=y -CONFIG_CLK_TWL6040=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_PALMAS is not set -# CONFIG_COMMON_CLK_TI_ADPLL is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONNECTOR=y -CONFIG_CONTIG_ALLOC=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THERMAL=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRAMFS=y -CONFIG_CRC16=y -CONFIG_CRC7=y -CONFIG_CRC_CCITT=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC_T10DIF=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEV_OMAP=y -CONFIG_CRYPTO_DEV_OMAP_AES=y -CONFIG_CRYPTO_DEV_OMAP_DES=y -CONFIG_CRYPTO_DEV_OMAP_SHAM=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ENGINE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DDR=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DM9000=y -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OMAP=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DNS_RESOLVER=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_DISPLAY_CONNECTOR=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_OMAP=y -CONFIG_DRM_OMAP_PANEL_DSI_CM=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_LG_LB035Q02=y -CONFIG_DRM_PANEL_NEC_NL8048HL11=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_SHARP_LS037V7DW01=y -CONFIG_DRM_PANEL_SONY_ACX565AKM=y -CONFIG_DRM_PANEL_TPO_TD028TTEC1=y -CONFIG_DRM_PANEL_TPO_TD043MTEA1=y -CONFIG_DRM_SIMPLE_BRIDGE=y -CONFIG_DRM_TI_TFP410=y -CONFIG_DRM_TI_TPD12S015=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_93CX6=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_EXTCON_PALMAS=y -CONFIG_EXTCON_USB_GPIO=y -CONFIG_F2FS_FS=y -CONFIG_FANOTIFY=y -CONFIG_FAT_FS=y -CONFIG_FB_CMDLINE=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_OMAP=y -CONFIG_GPIO_PALMAS=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_PCF857X=y -# CONFIG_GPIO_TPS65218 is not set -CONFIG_GPIO_TPS65910=y -CONFIG_GPIO_TWL4030=y -CONFIG_GPIO_TWL6040=y -CONFIG_GRACE_PERIOD=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HSI=y -CONFIG_HSI_BOARDINFO=y -# CONFIG_HSI_CHAR is not set -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_OMAP=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_RARP=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -CONFIG_KCMP=y -CONFIG_KEYS=y -CONFIG_KPROBES=y -CONFIG_KRETPROBES=y -CONFIG_KS8851=y -CONFIG_KS8851_MLL=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LIBCRC32C=y -CONFIG_LIBFDT=y -CONFIG_LOCKD=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_OMAP3517EVM is not set -# CONFIG_MACH_OMAP3_PANDORA is not set -CONFIG_MACH_OMAP_GENERIC=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_CORE=y -CONFIG_MFD_PALMAS=y -CONFIG_MFD_SYSCON=y -CONFIG_MFD_TI_AM335X_TSCADC=y -CONFIG_MFD_TPS65217=y -CONFIG_MFD_TPS65218=y -CONFIG_MFD_TPS65910=y -CONFIG_MFD_TWL4030_AUDIO=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -# CONFIG_MMC_OMAP is not set -CONFIG_MMC_OMAP_HS=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_EXTERNAL_DMA=y -CONFIG_MMC_SDHCI_OMAP=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MSDOS_FS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_NAND_OMAP_BCH=y -CONFIG_MTD_NAND_OMAP_BCH_BUILD=y -CONFIG_MTD_ONENAND=y -# CONFIG_MTD_ONENAND_2X_PROGRAM is not set -# CONFIG_MTD_ONENAND_GENERIC is not set -CONFIG_MTD_ONENAND_OMAP2=y -# CONFIG_MTD_ONENAND_OTP is not set -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -CONFIG_MTD_OOPS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -# CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEON=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_FS=y -CONFIG_NFS_USE_KERNEL_DNS=y -# CONFIG_NFS_USE_LEGACY_DNS is not set -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OID_REGISTRY=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OMAP2_DSS=y -CONFIG_OMAP2_DSS_DPI=y -CONFIG_OMAP2_DSS_DSI=y -CONFIG_OMAP2_DSS_HDMI_COMMON=y -CONFIG_OMAP2_DSS_INIT=y -CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 -CONFIG_OMAP2_DSS_SDI=y -CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y -CONFIG_OMAP2_DSS_VENC=y -# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set -# CONFIG_OMAP3_SDRC_AC_TIMING is not set -CONFIG_OMAP3_THERMAL=y -CONFIG_OMAP4_DSS_HDMI=y -CONFIG_OMAP4_DSS_HDMI_CEC=y -CONFIG_OMAP4_THERMAL=y -CONFIG_OMAP5_DSS_HDMI=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_CONTROL_PHY=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_OMAP_DSS_BASE=y -CONFIG_OMAP_GPMC=y -# CONFIG_OMAP_GPMC_DEBUG is not set -CONFIG_OMAP_INTERCONNECT=y -CONFIG_OMAP_INTERCONNECT_BARRIER=y -CONFIG_OMAP_IRQCHIP=y -CONFIG_OMAP_OCP2SCP=y -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_SSI is not set -CONFIG_OMAP_USB2=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_OPROFILE=y -CONFIG_OPTPROBES=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -# CONFIG_PHY_DM816X_USB is not set -CONFIG_PHY_TI_GMII_SEL=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_PALMAS is not set -CONFIG_PL310_ERRATA_588369=y -CONFIG_PL310_ERRATA_727915=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -CONFIG_POWER_AVS_OMAP=y -CONFIG_POWER_AVS_OMAP_CLASS3=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -CONFIG_PRINTK_TIME=y -CONFIG_PRINT_QUOTA_WARNING=y -CONFIG_PROC_EVENTS=y -CONFIG_PROFILING=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PWM=y -# CONFIG_PWM_OMAP_DMTIMER is not set -CONFIG_PWM_SYSFS=y -CONFIG_PWM_TIECAP=y -CONFIG_PWM_TIEHRPWM=y -# CONFIG_PWM_TWL is not set -# CONFIG_PWM_TWL_LED is not set -# CONFIG_QFMT_V1 is not set -CONFIG_QFMT_V2=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_QUOTA_TREE=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_PALMAS=y -CONFIG_REGULATOR_PBIAS=y -CONFIG_REGULATOR_TI_ABB=y -CONFIG_REGULATOR_TPS62360=y -CONFIG_REGULATOR_TPS65023=y -CONFIG_REGULATOR_TPS6507X=y -CONFIG_REGULATOR_TPS65217=y -CONFIG_REGULATOR_TPS65218=y -CONFIG_REGULATOR_TPS65910=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RING_BUFFER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y -CONFIG_ROOT_NFS=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=y -CONFIG_RTC_DRV_OMAP=y -CONFIG_RTC_DRV_PALMAS=y -# CONFIG_RTC_DRV_TPS65910 is not set -CONFIG_RTC_DRV_TWL4030=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_SATA_HOST=y -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_INFO=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SDIO_UART=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -CONFIG_SENSORS_GPIO_FAN=y -CONFIG_SENSORS_LM75=y -CONFIG_SENSORS_TMP102=y -CONFIG_SENSORS_TSL2550=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_NR_UARTS=32 -# CONFIG_SERIAL_8250_OMAP is not set -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_OMAP=y -CONFIG_SERIAL_OMAP_CONSOLE=y -CONFIG_SERIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SG_SPLIT=y -CONFIG_SKB_EXTENSIONS=y -CONFIG_SMC91X=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SMSC911X=y -CONFIG_SMSC_PHY=y -CONFIG_SND=y -# CONFIG_SND_COMPRESS_OFFLOAD is not set -CONFIG_SND_DMAENGINE_PCM=y -CONFIG_SND_JACK=y -CONFIG_SND_PCM=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_SIMPLE_CARD=y -CONFIG_SND_SIMPLE_CARD_UTILS=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_DAVINCI_MCASP=y -CONFIG_SND_SOC_DMIC=y -CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_NOKIA_RX51 is not set -# CONFIG_SND_SOC_OMAP3_PANDORA is not set -CONFIG_SND_SOC_OMAP3_TWL4030=y -CONFIG_SND_SOC_OMAP_ABE_TWL6040=y -CONFIG_SND_SOC_OMAP_DMIC=y -CONFIG_SND_SOC_OMAP_HDMI=y -CONFIG_SND_SOC_OMAP_MCBSP=y -CONFIG_SND_SOC_OMAP_MCPDM=y -CONFIG_SND_SOC_TI_EDMA_PCM=y -CONFIG_SND_SOC_TI_SDMA_PCM=y -CONFIG_SND_SOC_TI_UDMA_PCM=y -CONFIG_SND_SOC_TLV320AIC3X=y -CONFIG_SND_SOC_TWL4030=y -CONFIG_SND_SOC_TWL6040=y -CONFIG_SND_VERBOSE_PRINTK=y -CONFIG_SOC_AM33XX=y -CONFIG_SOC_AM43XX=y -CONFIG_SOC_BUS=y -CONFIG_SOC_HAS_OMAP2_SDRC=y -CONFIG_SOC_OMAP3430=y -# CONFIG_SOC_TI81XX is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_OMAP24XX=y -CONFIG_SPI_TI_QSPI=y -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TI_CPPI41=y -CONFIG_TI_CPSW=y -CONFIG_TI_CPSW_PHY_SEL=y -CONFIG_TI_CPTS=y -CONFIG_TI_DAVINCI_EMAC=y -CONFIG_TI_DAVINCI_MDIO=y -CONFIG_TI_DMA_CROSSBAR=y -CONFIG_TI_EDMA=y -CONFIG_TI_EMIF=y -# CONFIG_TI_EMIF_SRAM is not set -CONFIG_TI_PIPE3=y -CONFIG_TI_PRUSS_INTC=y -CONFIG_TI_PWMSS=y -CONFIG_TI_SOC_THERMAL=y -CONFIG_TI_SYSC=y -CONFIG_TI_THERMAL=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TRACE_CLOCK=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -CONFIG_TWL4030_USB=y -CONFIG_TWL4030_WATCHDOG=y -# CONFIG_TWL6030_USB is not set -CONFIG_TWL6040_CORE=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -# CONFIG_USB_AUDIO is not set -CONFIG_USB_COMMON=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_DUAL_ROLE=y -# CONFIG_USB_DWC3_GADGET is not set -# CONFIG_USB_DWC3_HOST is not set -CONFIG_USB_DWC3_OMAP=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_OMAP=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -# CONFIG_USB_ETH is not set -CONFIG_USB_GADGET=y -CONFIG_USB_INVENTRA_DMA=y -CONFIG_USB_MUSB_AM35X=y -CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_MUSB_DUAL_ROLE=y -# CONFIG_USB_MUSB_GADGET is not set -CONFIG_USB_MUSB_HDRC=y -# CONFIG_USB_MUSB_HOST is not set -CONFIG_USB_MUSB_OMAP2PLUS=y -CONFIG_USB_MUSB_TUSB6010=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_TI_CPPI41_DMA=y -CONFIG_USB_TUSB_OMAP_DMA=y -CONFIG_USE_OF=y -CONFIG_VFAT_FS=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XFRM_ALGO=y -CONFIG_XFRM_MIGRATE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/pistachio/config-5.10 b/target/linux/pistachio/config-5.10 deleted file mode 100644 index 681607f65c..0000000000 --- a/target/linux/pistachio/config-5.10 +++ /dev/null @@ -1,313 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOARD_SCACHE=y -CONFIG_BOOT_ELF32=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MIPS_GIC=y -CONFIG_CLKSRC_PISTACHIO=y -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONNECTOR=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_PM=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRC16=y -CONFIG_CRC_CCITT=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CSRC_R4K=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_OF=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DWMAC_GENERIC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EARLY_PRINTK_8250=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_FIXED_PHY=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HOTPLUG_CPU=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_IMG=y -CONFIG_IMGPDC_WDT=y -CONFIG_IMG_MDC_DMA=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_PWM=y -CONFIG_LIBFDT=y -CONFIG_LKDTM=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOG_BUF_SHIFT=18 -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MACH_PISTACHIO=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0 -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MICREL_PHY=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -CONFIG_MIPS_CM=y -CONFIG_MIPS_CMDLINE_DTB_EXTEND=y -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -# CONFIG_MIPS_CMDLINE_FROM_DTB is not set -CONFIG_MIPS_CPC=y -CONFIG_MIPS_CPS=y -# CONFIG_MIPS_CPS_CPUIDLE is not set -# CONFIG_MIPS_CPS_NS16550_BOOL is not set -CONFIG_MIPS_CPS_PM=y -CONFIG_MIPS_CPU_SCACHE=y -CONFIG_MIPS_EBPF_JIT=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_EXTERNAL_TIMER=y -CONFIG_MIPS_GIC=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_NO_APPENDED_DTB=y -CONFIG_MIPS_NR_CPU_NR_MAP=4 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -# CONFIG_MIPS_RAW_APPENDED_DTB is not set -CONFIG_MIPS_SPRAM=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_DW=y -# CONFIG_MMC_DW_BLUEFIELD is not set -# CONFIG_MMC_DW_EXYNOS is not set -# CONFIG_MMC_DW_HI3798CV200 is not set -# CONFIG_MMC_DW_K3 is not set -CONFIG_MMC_DW_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NAMESPACES=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_NS=y -CONFIG_NET_PTP_CLASSIFY=y -CONFIG_NLS=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PCS_XPCS=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHY_PISTACHIO_USB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_PISTACHIO=y -CONFIG_PISTACHIO_GPTIMER_CLKSRC=y -CONFIG_POWER_SUPPLY=y -CONFIG_PPS=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_VOLUNTARY=y -CONFIG_PRINTK_TIME=y -CONFIG_PROC_EVENTS=y -CONFIG_PROFILING=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PWM=y -CONFIG_PWM_IMG=y -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_PISTACHIO=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_INFO=y -CONFIG_SCSI=y -CONFIG_SCSI_SPI_ATTRS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_SC16IS7XX=y -CONFIG_SERIAL_SC16IS7XX_CORE=y -# CONFIG_SERIAL_SC16IS7XX_I2C is not set -CONFIG_SERIAL_SC16IS7XX_SPI=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SPI=y -CONFIG_SPI_IMG_SPFI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRAM=y -CONFIG_SRCU=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -# CONFIG_STMMAC_SELFTESTS is not set -CONFIG_SWPHY=y -CONFIG_SYNC_R4K=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS_CPS=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_RELOCATABLE=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC2=y -CONFIG_USB_DWC2_DUAL_ROLE=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_GADGET=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USER_NS=y -CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WEAK_ORDERING=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSMALLOC=y -# CONFIG_ZSMALLOC_STAT is not set -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/pistachio/patches-5.10/101-dmaengine-img-mdc-Handle-early-status-read.patch b/target/linux/pistachio/patches-5.10/101-dmaengine-img-mdc-Handle-early-status-read.patch deleted file mode 100644 index 031a4e3e5e..0000000000 --- a/target/linux/pistachio/patches-5.10/101-dmaengine-img-mdc-Handle-early-status-read.patch +++ /dev/null @@ -1,68 +0,0 @@ -From a2dd154377c9aa6ddda00d39b8c7c334e4fa16ff Mon Sep 17 00:00:00 2001 -From: Damien Horsley -Date: Tue, 22 Mar 2016 12:46:09 +0000 -Subject: dmaengine: img-mdc: Handle early status read - -It is possible that mdc_tx_status may be called before the first -node has been read from memory. - -In this case, the residue value stored in the register is undefined. -Return the transfer size instead. - -Signed-off-by: Damien Horsley ---- - drivers/dma/img-mdc-dma.c | 40 ++++++++++++++++++++++++---------------- - 1 file changed, 24 insertions(+), 16 deletions(-) - ---- a/drivers/dma/img-mdc-dma.c -+++ b/drivers/dma/img-mdc-dma.c -@@ -618,25 +618,33 @@ static enum dma_status mdc_tx_status(str - (MDC_CMDS_PROCESSED_CMDS_DONE_MASK + 1); - - /* -- * If the command loaded event hasn't been processed yet, then -- * the difference above includes an extra command. -+ * If the first node has not yet been read from memory, -+ * the residue register value is undefined - */ -- if (!mdesc->cmd_loaded) -- cmds--; -- else -- cmds += mdesc->list_cmds_done; -- -- bytes = mdesc->list_xfer_size; -- ldesc = mdesc->list; -- for (i = 0; i < cmds; i++) { -- bytes -= ldesc->xfer_size + 1; -- ldesc = ldesc->next_desc; -- } -- if (ldesc) { -- if (residue != MDC_TRANSFER_SIZE_MASK) -- bytes -= ldesc->xfer_size - residue; -+ if (!mdesc->cmd_loaded && !cmds) { -+ bytes = mdesc->list_xfer_size; -+ } else { -+ /* -+ * If the command loaded event hasn't been processed yet, then -+ * the difference above includes an extra command. -+ */ -+ if (!mdesc->cmd_loaded) -+ cmds--; - else -+ cmds += mdesc->list_cmds_done; -+ -+ bytes = mdesc->list_xfer_size; -+ ldesc = mdesc->list; -+ for (i = 0; i < cmds; i++) { - bytes -= ldesc->xfer_size + 1; -+ ldesc = ldesc->next_desc; -+ } -+ if (ldesc) { -+ if (residue != MDC_TRANSFER_SIZE_MASK) -+ bytes -= ldesc->xfer_size - residue; -+ else -+ bytes -= ldesc->xfer_size + 1; -+ } - } - } - spin_unlock_irqrestore(&mchan->vc.lock, flags); diff --git a/target/linux/pistachio/patches-5.10/102-spi-img-spfi-Implement-dual-and-quad-mode.patch b/target/linux/pistachio/patches-5.10/102-spi-img-spfi-Implement-dual-and-quad-mode.patch deleted file mode 100644 index 83f21a5c0a..0000000000 --- a/target/linux/pistachio/patches-5.10/102-spi-img-spfi-Implement-dual-and-quad-mode.patch +++ /dev/null @@ -1,198 +0,0 @@ -From cd2a6af51553d38072cd31699b58d16ca6176ef5 Mon Sep 17 00:00:00 2001 -From: Ionela Voinescu -Date: Thu, 2 Feb 2017 16:46:14 +0000 -Subject: spi: img-spfi: Implement dual and quad mode - -For dual and quad modes to work the SPFI controller needs -to have information about command/address/dummy bytes in the -transaction register. This information is not relevant for -single mode, and therefore it can have any value in the -allowed range. Therefore, for any read or write transfers of less -than 8 bytes (cmd = 1 byte, addr up to 7 bytes), SPFI will be -configured, but not enabled (unless it is the last transfer in -the queue). The transfer will be enabled by the subsequent tranfer. -A pending transfer is determined by the content of the transaction -register: if command part is set and tsize is not. - -This way we ensure that for dual and quad transactions -the command request size will apear in the command/address part -of the transaction register, while the data size will be in -tsize, all data being sent/received in the same transaction (as -set up in the transaction register). - -Signed-off-by: Ionela Voinescu -Signed-off-by: Ezequiel Garcia ---- - drivers/spi/spi-img-spfi.c | 96 ++++++++++++++++++++++++++++++++++++++++------ - 1 file changed, 85 insertions(+), 11 deletions(-) - ---- a/drivers/spi/spi-img-spfi.c -+++ b/drivers/spi/spi-img-spfi.c -@@ -36,7 +36,8 @@ - #define SPFI_CONTROL_SOFT_RESET BIT(11) - #define SPFI_CONTROL_SEND_DMA BIT(10) - #define SPFI_CONTROL_GET_DMA BIT(9) --#define SPFI_CONTROL_SE BIT(8) -+#define SPFI_CONTROL_SE BIT(8) -+#define SPFI_CONTROL_TX_RX BIT(1) - #define SPFI_CONTROL_TMODE_SHIFT 5 - #define SPFI_CONTROL_TMODE_MASK 0x7 - #define SPFI_CONTROL_TMODE_SINGLE 0 -@@ -47,6 +48,10 @@ - #define SPFI_TRANSACTION 0x18 - #define SPFI_TRANSACTION_TSIZE_SHIFT 16 - #define SPFI_TRANSACTION_TSIZE_MASK 0xffff -+#define SPFI_TRANSACTION_CMD_SHIFT 13 -+#define SPFI_TRANSACTION_CMD_MASK 0x7 -+#define SPFI_TRANSACTION_ADDR_SHIFT 10 -+#define SPFI_TRANSACTION_ADDR_MASK 0x7 - - #define SPFI_PORT_STATE 0x1c - #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20 -@@ -83,6 +88,7 @@ - */ - #define SPFI_32BIT_FIFO_SIZE 64 - #define SPFI_8BIT_FIFO_SIZE 16 -+#define SPFI_DATA_REQUEST_MAX_SIZE 8 - - struct img_spfi { - struct device *dev; -@@ -99,6 +105,8 @@ struct img_spfi { - struct dma_chan *tx_ch; - bool tx_dma_busy; - bool rx_dma_busy; -+ -+ bool complete; - }; - - static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg) -@@ -115,9 +123,11 @@ static inline void spfi_start(struct img - { - u32 val; - -- val = spfi_readl(spfi, SPFI_CONTROL); -- val |= SPFI_CONTROL_SPFI_EN; -- spfi_writel(spfi, val, SPFI_CONTROL); -+ if (spfi->complete) { -+ val = spfi_readl(spfi, SPFI_CONTROL); -+ val |= SPFI_CONTROL_SPFI_EN; -+ spfi_writel(spfi, val, SPFI_CONTROL); -+ } - } - - static inline void spfi_reset(struct img_spfi *spfi) -@@ -130,12 +140,21 @@ static int spfi_wait_all_done(struct img - { - unsigned long timeout = jiffies + msecs_to_jiffies(50); - -+ if (!(spfi->complete)) -+ return 0; -+ - while (time_before(jiffies, timeout)) { - u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); - - if (status & SPFI_INTERRUPT_ALLDONETRIG) { - spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG, - SPFI_INTERRUPT_CLEAR); -+ /* -+ * Disable SPFI for it not to interfere with -+ * pending transactions -+ */ -+ spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL) -+ & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL); - return 0; - } - cpu_relax(); -@@ -441,9 +460,32 @@ static void img_spfi_config(struct spi_m - struct spi_transfer *xfer) - { - struct img_spfi *spfi = spi_master_get_devdata(spi->master); -- u32 val, div; -+ u32 val, div, transact; -+ bool is_pending; - - /* -+ * For read or write transfers of less than 8 bytes (cmd = 1 byte, -+ * addr up to 7 bytes), SPFI will be configured, but not enabled -+ * (unless it is the last transfer in the queue).The transfer will -+ * be enabled by the subsequent transfer. -+ * A pending transfer is determined by the content of the -+ * transaction register: if command part is set and tsize -+ * is not -+ */ -+ transact = spfi_readl(spfi, SPFI_TRANSACTION); -+ is_pending = ((transact >> SPFI_TRANSACTION_CMD_SHIFT) & -+ SPFI_TRANSACTION_CMD_MASK) && -+ (!((transact >> SPFI_TRANSACTION_TSIZE_SHIFT) & -+ SPFI_TRANSACTION_TSIZE_MASK)); -+ -+ /* If there are no pending transactions it's OK to soft reset */ -+ if (!is_pending) { -+ /* Start the transaction from a known (reset) state */ -+ spfi_reset(spfi); -+ } -+ -+ /* -+ * Before anything else, set up parameters. - * output = spfi_clk * (BITCLK / 512), where BITCLK must be a - * power of 2 up to 128 - */ -@@ -456,20 +498,52 @@ static void img_spfi_config(struct spi_m - val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; - spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); - -- spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT, -- SPFI_TRANSACTION); -+ if (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) && -+ /* -+ * For duplex mode (both the tx and rx buffers are !NULL) the -+ * CMD, ADDR, and DUMMY byte parts of the transaction register -+ * should always be 0 and therefore the pending transfer -+ * technique cannot be used. -+ */ -+ (xfer->tx_buf) && (!xfer->rx_buf) && -+ (xfer->len <= SPFI_DATA_REQUEST_MAX_SIZE) && !is_pending) { -+ transact = (1 & SPFI_TRANSACTION_CMD_MASK) << -+ SPFI_TRANSACTION_CMD_SHIFT; -+ transact |= ((xfer->len - 1) & SPFI_TRANSACTION_ADDR_MASK) << -+ SPFI_TRANSACTION_ADDR_SHIFT; -+ spfi->complete = false; -+ } else { -+ spfi->complete = true; -+ if (is_pending) { -+ /* Keep setup from pending transfer */ -+ transact |= ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) << -+ SPFI_TRANSACTION_TSIZE_SHIFT); -+ } else { -+ transact = ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) << -+ SPFI_TRANSACTION_TSIZE_SHIFT); -+ } -+ } -+ spfi_writel(spfi, transact, SPFI_TRANSACTION); - - val = spfi_readl(spfi, SPFI_CONTROL); - val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA); -- if (xfer->tx_buf) -+ /* -+ * We set up send DMA for pending transfers also, as -+ * those are always send transfers -+ */ -+ if ((xfer->tx_buf) || is_pending) - val |= SPFI_CONTROL_SEND_DMA; -- if (xfer->rx_buf) -+ if (xfer->tx_buf) -+ val |= SPFI_CONTROL_TX_RX; -+ if (xfer->rx_buf) { - val |= SPFI_CONTROL_GET_DMA; -+ val &= ~SPFI_CONTROL_TX_RX; -+ } - val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT); -- if (xfer->tx_nbits == SPI_NBITS_DUAL && -+ if (xfer->tx_nbits == SPI_NBITS_DUAL || - xfer->rx_nbits == SPI_NBITS_DUAL) - val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT; -- else if (xfer->tx_nbits == SPI_NBITS_QUAD && -+ else if (xfer->tx_nbits == SPI_NBITS_QUAD || - xfer->rx_nbits == SPI_NBITS_QUAD) - val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; - val |= SPFI_CONTROL_SE; diff --git a/target/linux/pistachio/patches-5.10/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch b/target/linux/pistachio/patches-5.10/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch deleted file mode 100644 index 2995b7dd88..0000000000 --- a/target/linux/pistachio/patches-5.10/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 905ee06a9966113fe51d6bad1819759cb30fd0bd Mon Sep 17 00:00:00 2001 -From: Ionela Voinescu -Date: Tue, 9 Feb 2016 10:18:31 +0000 -Subject: spi: img-spfi: use device 0 configuration for all devices - -Given that we control the chip select line externally -we can use only one parameter register (device 0 parameter -register) and one set of configuration bits (port configuration -bits for device 0) for all devices (all chip select lines). - -Signed-off-by: Ionela Voinescu ---- - drivers/spi/spi-img-spfi.c | 23 ++++++++++++++++------- - 1 file changed, 16 insertions(+), 7 deletions(-) - ---- a/drivers/spi/spi-img-spfi.c -+++ b/drivers/spi/spi-img-spfi.c -@@ -429,18 +429,23 @@ static int img_spfi_prepare(struct spi_m - struct img_spfi *spfi = spi_master_get_devdata(master); - u32 val; - -+ /* -+ * The chip select line is controlled externally so -+ * we can use the CS0 configuration for all devices -+ */ - val = spfi_readl(spfi, SPFI_PORT_STATE); -+ -+ /* 0 for device selection */ - val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << - SPFI_PORT_STATE_DEV_SEL_SHIFT); -- val |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT; - if (msg->spi->mode & SPI_CPHA) -- val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); -+ val |= SPFI_PORT_STATE_CK_PHASE(0); - else -- val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select); -+ val &= ~SPFI_PORT_STATE_CK_PHASE(0); - if (msg->spi->mode & SPI_CPOL) -- val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); -+ val |= SPFI_PORT_STATE_CK_POL(0); - else -- val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select); -+ val &= ~SPFI_PORT_STATE_CK_POL(0); - spfi_writel(spfi, val, SPFI_PORT_STATE); - - return 0; -@@ -492,11 +497,15 @@ static void img_spfi_config(struct spi_m - div = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz); - div = clamp(512 / (1 << get_count_order(div)), 1, 128); - -- val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select)); -+ /* -+ * The chip select line is controlled externally so -+ * we can use the CS0 parameters for all devices -+ */ -+ val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(0)); - val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK << - SPFI_DEVICE_PARAMETER_BITCLK_SHIFT); - val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT; -- spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select)); -+ spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(0)); - - if (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) && - /* diff --git a/target/linux/pistachio/patches-5.10/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch b/target/linux/pistachio/patches-5.10/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch deleted file mode 100644 index 5418503816..0000000000 --- a/target/linux/pistachio/patches-5.10/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 56466f505f58f44b69feb7eaed3b506842800456 Mon Sep 17 00:00:00 2001 -From: Ionela Voinescu -Date: Tue, 1 Mar 2016 17:49:45 +0000 -Subject: spi: img-spfi: RX maximum burst size for DMA is 8 - -The depth of the FIFOs is 16 bytes. The DMA request line is tied -to the half full/empty (depending on the use of the TX or RX FIFO) -threshold. For the TX FIFO, if you set a burst size of 8 (equal to -half the depth) the first burst goes into FIFO without any issues, -but due the latency involved (the time the data leaves the DMA -engine to the time it arrives at the FIFO), the DMA might trigger -another burst of 8. But given that there is no space for 2 additonal -bursts of 8, this would result in a failure. Therefore, we have to -keep the burst size for TX to 4 to accomodate for an extra burst. - -For the read (RX) scenario, the DMA request line goes high when -there is at least 8 entries in the FIFO (half full), and we can -program the burst size to be 8 because the risk of accidental burst -does not exist. The DMA engine will not trigger another read until -the read data for all the burst it has sent out has been received. - -While here, move the burst size setting outside of the if/else branches -as they have the same value for both 8 and 32 bit data widths. - -Signed-off-by: Ionela Voinescu ---- - drivers/spi/spi-img-spfi.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/spi/spi-img-spfi.c -+++ b/drivers/spi/spi-img-spfi.c -@@ -338,12 +338,11 @@ static int img_spfi_start_dma(struct spi - if (xfer->len % 4 == 0) { - rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA; - rxconf.src_addr_width = 4; -- rxconf.src_maxburst = 4; - } else { - rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA; - rxconf.src_addr_width = 1; -- rxconf.src_maxburst = 4; - } -+ rxconf.src_maxburst = 8; - dmaengine_slave_config(spfi->rx_ch, &rxconf); - - rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl, -@@ -362,12 +361,11 @@ static int img_spfi_start_dma(struct spi - if (xfer->len % 4 == 0) { - txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA; - txconf.dst_addr_width = 4; -- txconf.dst_maxburst = 4; - } else { - txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA; - txconf.dst_addr_width = 1; -- txconf.dst_maxburst = 4; - } -+ txconf.dst_maxburst = 4; - dmaengine_slave_config(spfi->tx_ch, &txconf); - - txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl, diff --git a/target/linux/pistachio/patches-5.10/106-spi-img-spfi-finish-every-transfer-cleanly.patch b/target/linux/pistachio/patches-5.10/106-spi-img-spfi-finish-every-transfer-cleanly.patch deleted file mode 100644 index ea1f9f28cc..0000000000 --- a/target/linux/pistachio/patches-5.10/106-spi-img-spfi-finish-every-transfer-cleanly.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 5fcca3fd4b621d7b5bdeca18d36dfc6ca6cfe383 Mon Sep 17 00:00:00 2001 -From: Ionela Voinescu -Date: Wed, 10 Aug 2016 11:42:26 +0100 -Subject: spi: img-spfi: finish every transfer cleanly - -Before this change, the interrupt status bit that signaled -the end of a tranfers was cleared in the wait_all_done -function. That functionality triggered issues for DMA -duplex transactions where the wait function was called -twice, in both the TX and RX callbacks. - -In order to fix the issue, clear all interrupt data bits -at the end of a PIO transfer or at the end of both TX and RX -duplex transfers, if the transfer is not a pending tranfer -(command waiting for data). After that, the status register -is checked for new incoming data or new data requests to be -signaled. If SPFI finished cleanly, no new interrupt data -bits should be set. - -Signed-off-by: Ionela Voinescu ---- - drivers/spi/spi-img-spfi.c | 49 +++++++++++++++++++++++++++++++++------------- - 1 file changed, 35 insertions(+), 14 deletions(-) - ---- a/drivers/spi/spi-img-spfi.c -+++ b/drivers/spi/spi-img-spfi.c -@@ -79,6 +79,14 @@ - #define SPFI_INTERRUPT_SDE BIT(1) - #define SPFI_INTERRUPT_SDTRIG BIT(0) - -+#define SPFI_INTERRUPT_DATA_BITS (SPFI_INTERRUPT_SDHF |\ -+ SPFI_INTERRUPT_SDFUL |\ -+ SPFI_INTERRUPT_GDEX32BIT |\ -+ SPFI_INTERRUPT_GDHF |\ -+ SPFI_INTERRUPT_GDFUL |\ -+ SPFI_INTERRUPT_ALLDONETRIG |\ -+ SPFI_INTERRUPT_GDEX8BIT) -+ - /* - * There are four parallel FIFOs of 16 bytes each. The word buffer - * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an -@@ -136,6 +144,23 @@ static inline void spfi_reset(struct img - spfi_writel(spfi, 0, SPFI_CONTROL); - } - -+static inline void spfi_finish(struct img_spfi *spfi) -+{ -+ if (!(spfi->complete)) -+ return; -+ -+ /* Clear data bits as all transfers(TX and RX) have finished */ -+ spfi_writel(spfi, SPFI_INTERRUPT_DATA_BITS, SPFI_INTERRUPT_CLEAR); -+ if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & SPFI_INTERRUPT_DATA_BITS) { -+ dev_err(spfi->dev, "SPFI did not finish transfer cleanly.\n"); -+ spfi_reset(spfi); -+ } -+ /* Disable SPFI for it not to interfere with pending transactions */ -+ spfi_writel(spfi, -+ spfi_readl(spfi, SPFI_CONTROL) & ~SPFI_CONTROL_SPFI_EN, -+ SPFI_CONTROL); -+} -+ - static int spfi_wait_all_done(struct img_spfi *spfi) - { - unsigned long timeout = jiffies + msecs_to_jiffies(50); -@@ -144,19 +169,9 @@ static int spfi_wait_all_done(struct img - return 0; - - while (time_before(jiffies, timeout)) { -- u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS); -- -- if (status & SPFI_INTERRUPT_ALLDONETRIG) { -- spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG, -- SPFI_INTERRUPT_CLEAR); -- /* -- * Disable SPFI for it not to interfere with -- * pending transactions -- */ -- spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL) -- & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL); -+ if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & -+ SPFI_INTERRUPT_ALLDONETRIG) - return 0; -- } - cpu_relax(); - } - -@@ -288,6 +303,8 @@ static int img_spfi_start_pio(struct spi - } - - ret = spfi_wait_all_done(spfi); -+ spfi_finish(spfi); -+ - if (ret < 0) - return ret; - -@@ -303,8 +320,10 @@ static void img_spfi_dma_rx_cb(void *dat - - spin_lock_irqsave(&spfi->lock, flags); - spfi->rx_dma_busy = false; -- if (!spfi->tx_dma_busy) -+ if (!spfi->tx_dma_busy) { -+ spfi_finish(spfi); - spi_finalize_current_transfer(spfi->master); -+ } - spin_unlock_irqrestore(&spfi->lock, flags); - } - -@@ -317,8 +336,10 @@ static void img_spfi_dma_tx_cb(void *dat - - spin_lock_irqsave(&spfi->lock, flags); - spfi->tx_dma_busy = false; -- if (!spfi->rx_dma_busy) -+ if (!spfi->rx_dma_busy) { -+ spfi_finish(spfi); - spi_finalize_current_transfer(spfi->master); -+ } - spin_unlock_irqrestore(&spfi->lock, flags); - } - diff --git a/target/linux/pistachio/patches-5.10/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch b/target/linux/pistachio/patches-5.10/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch deleted file mode 100644 index 6fddbe269a..0000000000 --- a/target/linux/pistachio/patches-5.10/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 3642843a06025ec333d7e92580cf52cb8db2a652 Mon Sep 17 00:00:00 2001 -From: Govindraj Raja -Date: Fri, 8 Jan 2016 16:36:07 +0000 -Subject: clk: pistachio: Fix wrong SDHost card speed - -The SDHost currently clocks the card 4x slower than it -should do, because there is fixed divide by 4 in the -sdhost wrapper that is not present in the clock tree. -To model this add a fixed divide by 4 clock node in -the SDHost clock path. - -This will ensure the right clock frequency is selected when -the mmc driver tries to configure frequency on card insert. - -Signed-off-by: Govindraj Raja ---- - drivers/clk/pistachio/clk-pistachio.c | 3 ++- - include/dt-bindings/clock/pistachio-clk.h | 1 + - 2 files changed, 3 insertions(+), 1 deletion(-) - ---- a/drivers/clk/pistachio/clk-pistachio.c -+++ b/drivers/clk/pistachio/clk-pistachio.c -@@ -41,7 +41,7 @@ static struct pistachio_gate pistachio_g - GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div", - 0x104, 22), - GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23), -- GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24), -+ GATE(CLK_SD_HOST, "sd_host", "sd_host_div4", 0x104, 24), - GATE(CLK_BT, "bt", "bt_div", 0x104, 25), - GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26), - GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27), -@@ -51,6 +51,7 @@ static struct pistachio_gate pistachio_g - static struct pistachio_fixed_factor pistachio_ffs[] __initdata = { - FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4), - FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8), -+ FIXED_FACTOR(CLK_SDHOST_DIV4, "sd_host_div4", "sd_host_div", 4), - }; - - static struct pistachio_div pistachio_divs[] __initdata = { ---- a/include/dt-bindings/clock/pistachio-clk.h -+++ b/include/dt-bindings/clock/pistachio-clk.h -@@ -18,6 +18,7 @@ - /* Fixed-factor clocks */ - #define CLK_WIFI_DIV4 16 - #define CLK_WIFI_DIV8 17 -+#define CLK_SDHOST_DIV4 18 - - /* Gate clocks */ - #define CLK_MIPS 32 diff --git a/target/linux/pistachio/patches-5.10/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch b/target/linux/pistachio/patches-5.10/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch deleted file mode 100644 index cec424a0ce..0000000000 --- a/target/linux/pistachio/patches-5.10/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 981c1d416af45eff207227aec106381ac23aac99 Mon Sep 17 00:00:00 2001 -From: Ian Pozella -Date: Mon, 20 Feb 2017 10:00:52 +0000 -Subject: MIPS: DTS: img: marduk: switch mmc to 1 bit mode - -The mmc block in Pistachio allows 1 to 8 data bits to be used. -Marduk uses 4 bits allowing the upper 4 bits to be allocated -to the Mikrobus ports. However these bits are still connected -internally meaning the mmc block recieves signals on all data lines -and seems the internal HW CRC checks get corrupted by this erroneous -data. - -We cannot control what data is sent on these lines because they go -to external ports. 1 bit mode does not exhibit the issue hence the -safe default is to use this. If a user knows that in their use case -they will not use the upper bits then they can set to 4 bit mode in -order to improve performance. - -Also make sure that the upper 4 bits don't get allocated to the mmc -driver (the default is to assign all 8 pins) so they can be allocated -to other drivers. Allocating all 4 despite setting 1 bit mode as this -matches what is there in hardware. - -Signed-off-by: Ian Pozella ---- - arch/mips/boot/dts/img/pistachio_marduk.dts | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/arch/mips/boot/dts/img/pistachio_marduk.dts -+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -117,7 +117,7 @@ - - &sdhost { - status = "okay"; -- bus-width = <4>; -+ bus-width = <1>; - disable-wp; - }; - -@@ -127,6 +127,7 @@ - - &pin_sdhost_data { - drive-strength = <2>; -+ pins = "mfio17", "mfio18", "mfio19", "mfio20"; - }; - - &pwm { diff --git a/target/linux/pistachio/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/pistachio/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch deleted file mode 100644 index 99985eba40..0000000000 --- a/target/linux/pistachio/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch +++ /dev/null @@ -1,54 +0,0 @@ -From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001 -From: Abhimanyu Vishwakarma -Date: Sat, 25 Feb 2017 16:42:50 +0000 -Subject: mtd: nor: support mtd name from device tree - -Signed-off-by: Abhimanyu Vishwakarma ---- - drivers/mtd/spi-nor/spi-nor.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -3152,6 +3152,7 @@ int spi_nor_scan(struct spi_nor *nor, co - struct device *dev = nor->dev; - struct mtd_info *mtd = &nor->mtd; - struct device_node *np = spi_nor_get_flash_node(nor); -+ const char __maybe_unused *of_mtd_name = NULL; - int ret; - int i; - -@@ -3206,7 +3207,12 @@ int spi_nor_scan(struct spi_nor *nor, co - if (ret) - return ret; - -- if (!mtd->name) -+#ifdef CONFIG_MTD_OF_PARTS -+ of_property_read_string(np, "linux,mtd-name", &of_mtd_name); -+#endif -+ if (of_mtd_name) -+ mtd->name = of_mtd_name; -+ else if (!mtd->name) - mtd->name = dev_name(dev); - mtd->priv = nor; - mtd->type = MTD_NORFLASH; ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -850,6 +850,17 @@ out_error: - */ - static void mtd_set_dev_defaults(struct mtd_info *mtd) - { -+#ifdef CONFIG_MTD_OF_PARTS -+ const char __maybe_unused *of_mtd_name = NULL; -+ struct device_node *np; -+ -+ np = mtd_get_of_node(mtd); -+ if (np && !mtd->name) { -+ of_property_read_string(np, "linux,mtd-name", &of_mtd_name); -+ if (of_mtd_name) -+ mtd->name = of_mtd_name; -+ } else -+#endif - if (mtd->dev.parent) { - if (!mtd->owner && mtd->dev.parent->driver) - mtd->owner = mtd->dev.parent->driver->owner; diff --git a/target/linux/pistachio/patches-5.10/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch b/target/linux/pistachio/patches-5.10/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch deleted file mode 100644 index cd97e38e00..0000000000 --- a/target/linux/pistachio/patches-5.10/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 0023c706f7e0f0f02bd48a63a2f3c04c839532ae Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sat, 15 Aug 2020 16:04:53 +0200 -Subject: [PATCH 901/904] MIPS: DTS: img: marduk: Add SPI NAND flash - -Add Gigadevice GD5F4GQ4UCYIGT SPI NAND flash to the device tree. - -The NAND flash chip is connected with quad SPI, but reading currently -fails in quad SPI mode. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/boot/dts/img/pistachio_marduk.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/mips/boot/dts/img/pistachio_marduk.dts -+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -88,6 +88,12 @@ - reg = <0>; - spi-max-frequency = <50000000>; - }; -+ -+ flash@1 { -+ compatible = "spi-nand"; -+ reg = <1>; -+ spi-max-frequency = <50000000>; -+ }; - }; - - &uart0 { diff --git a/target/linux/pistachio/patches-5.10/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch b/target/linux/pistachio/patches-5.10/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch deleted file mode 100644 index af1882e287..0000000000 --- a/target/linux/pistachio/patches-5.10/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch +++ /dev/null @@ -1,43 +0,0 @@ -From b7700154d75e8d7c9a2022f09c2d5430137606fa Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sat, 15 Aug 2020 16:05:25 +0200 -Subject: [PATCH 902/904] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN - -Add Cascoda CA8210 6LoWPAN controller to device tree. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/boot/dts/img/pistachio_marduk.dts | 22 +++++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/arch/mips/boot/dts/img/pistachio_marduk.dts -+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -75,6 +75,28 @@ - VDD-supply = <&internal_dac_supply>; - }; - -+&spfi0 { -+ status = "okay"; -+ pinctrl-0 = <&spim0_pins>, <&spim0_cs0_alt_pin>, <&spim0_cs2_alt_pin>, <&spim0_cs3_alt_pin>, <&spim0_cs4_alt_pin>; -+ pinctrl-names = "default"; -+ -+ cs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>, <&gpio0 2 GPIO_ACTIVE_HIGH>, -+ <&gpio1 12 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>; -+ -+ ca8210: ca8210@0 { -+ status = "okay"; -+ compatible = "cascoda,ca8210"; -+ reg = <0>; -+ spi-max-frequency = <4000000>; -+ spi-cpol; -+ reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; -+ irq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; -+ extclock-enable; -+ extclock-freq = <16000000>; -+ extclock-gpio = <2>; -+ }; -+}; -+ - &spfi1 { - status = "okay"; - diff --git a/target/linux/pistachio/patches-5.10/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch b/target/linux/pistachio/patches-5.10/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch deleted file mode 100644 index 0814658998..0000000000 --- a/target/linux/pistachio/patches-5.10/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch +++ /dev/null @@ -1,81 +0,0 @@ -From ad4eba0c36ce8af6ab9ea1bc163e4c1ac7c271c3 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Sat, 15 Aug 2020 16:09:02 +0200 -Subject: [PATCH 903/904] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW - -Add NXP SC16IS752IPW SPI-UART controller to device tree. - -This controller drives 2 UARTs and 7 LEDs on the board. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/boot/dts/img/pistachio_marduk.dts | 51 +++++++++++++++++++++ - 1 file changed, 51 insertions(+) - ---- a/arch/mips/boot/dts/img/pistachio_marduk.dts -+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -46,6 +46,46 @@ - regulator-max-microvolt = <1800000>; - }; - -+ /* EXT clock from ca8210 is fed to sc16is752 */ -+ ca8210_ext_clk: ca8210-ext-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <16000000>; -+ clock-output-names = "ca8210_ext_clock"; -+ }; -+ -+ gpioleds { -+ compatible = "gpio-leds"; -+ user1 { -+ label = "marduk:red:user1"; -+ gpios = <&sc16is752 0 GPIO_ACTIVE_LOW>; -+ }; -+ user2 { -+ label = "marduk:red:user2"; -+ gpios = <&sc16is752 1 GPIO_ACTIVE_LOW>; -+ }; -+ user3 { -+ label = "marduk:red:user3"; -+ gpios = <&sc16is752 2 GPIO_ACTIVE_LOW>; -+ }; -+ user4 { -+ label = "marduk:red:user4"; -+ gpios = <&sc16is752 3 GPIO_ACTIVE_LOW>; -+ }; -+ user5 { -+ label = "marduk:red:user5"; -+ gpios = <&sc16is752 4 GPIO_ACTIVE_LOW>; -+ }; -+ user6 { -+ label = "marduk:red:user6"; -+ gpios = <&sc16is752 5 GPIO_ACTIVE_LOW>; -+ }; -+ user7 { -+ label = "marduk:red:user7"; -+ gpios = <&sc16is752 6 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ - leds { - compatible = "pwm-leds"; - heartbeat { -@@ -95,6 +135,17 @@ - extclock-freq = <16000000>; - extclock-gpio = <2>; - }; -+ -+ sc16is752: sc16is752@1 { -+ compatible = "nxp,sc16is752"; -+ reg = <1>; -+ clocks = <&ca8210_ext_clk>; -+ spi-max-frequency = <4000000>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; - }; - - &spfi1 { diff --git a/target/linux/pistachio/patches-5.10/904-MIPS-DTS-img-marduk-Add-partition-name.patch b/target/linux/pistachio/patches-5.10/904-MIPS-DTS-img-marduk-Add-partition-name.patch deleted file mode 100644 index ce41c67461..0000000000 --- a/target/linux/pistachio/patches-5.10/904-MIPS-DTS-img-marduk-Add-partition-name.patch +++ /dev/null @@ -1,27 +0,0 @@ -From ff0e950b605047bf50d470023e0fb2fc2003a0f0 Mon Sep 17 00:00:00 2001 -From: Ian Pozella -Date: Mon, 20 Feb 2017 10:38:07 +0000 -Subject: [PATCH 904/904] MIPS: DTS: img: marduk: Add partition name - -Signed-off-by: Ian Pozella ---- - arch/mips/boot/dts/img/pistachio_marduk.dts | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/mips/boot/dts/img/pistachio_marduk.dts -+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -160,12 +160,14 @@ - compatible = "spansion,s25fl016k", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; -+ linux,mtd-name = "spi-nor"; - }; - - flash@1 { - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <50000000>; -+ linux,mtd-name = "spi-nand"; - }; - }; - diff --git a/target/linux/pistachio/patches-5.10/905-MIPS-DTS-img-marduk-Add-led-aliases.patch b/target/linux/pistachio/patches-5.10/905-MIPS-DTS-img-marduk-Add-led-aliases.patch deleted file mode 100644 index c6cf5acbb8..0000000000 --- a/target/linux/pistachio/patches-5.10/905-MIPS-DTS-img-marduk-Add-led-aliases.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/arch/mips/boot/dts/img/pistachio_marduk.dts -+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts -@@ -19,6 +19,11 @@ - ethernet0 = &enet; - spi0 = &spfi0; - spi1 = &spfi1; -+ -+ led-boot = &led_heartbeat; -+ led-failsafe = &led_heartbeat; -+ led-running = &led_heartbeat; -+ led-upgrade = &led_heartbeat; - }; - - chosen { -@@ -88,11 +93,10 @@ - - leds { - compatible = "pwm-leds"; -- heartbeat { -+ led_heartbeat: heartbeat { - label = "marduk:red:heartbeat"; - pwms = <&pwm 3 300000>; - max-brightness = <255>; -- linux,default-trigger = "heartbeat"; - }; - }; - diff --git a/target/linux/ramips/mt7620/config-5.10 b/target/linux/ramips/mt7620/config-5.10 deleted file mode 100644 index 4ee113facd..0000000000 --- a/target/linux/ramips/mt7620/config-5.10 +++ /dev/null @@ -1,197 +0,0 @@ -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_SYSTICK_QUIRK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_RT3352=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_MT7620A_EVAL is not set -# CONFIG_DTB_OMEGA2P is not set -CONFIG_DTB_RT_NONE=y -# CONFIG_DTB_VOCORE2 is not set -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -# CONFIG_GPIO_MT7621 is not set -CONFIG_GPIO_RALINK=y -CONFIG_GPIO_WATCHDOG=y -# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_ICPLUS_PHY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -# CONFIG_KERNEL_ZSTD is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MT7621_WDT is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_JIMAGE_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_GSW_MT7620=y -CONFIG_NET_RALINK_MDIO=y -CONFIG_NET_RALINK_MDIO_MT7620=y -CONFIG_NET_RALINK_MT7620=y -# CONFIG_NET_RALINK_RT3050 is not set -CONFIG_NET_RALINK_SOC=y -# CONFIG_NET_VENDOR_MEDIATEK is not set -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_RALINK=y -CONFIG_RALINK_WDT=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SOC_MT7620=y -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/mt7621/config-5.10 b/target/linux/ramips/mt7621/config-5.10 deleted file mode 100644 index 8c077d211d..0000000000 --- a/target/linux/ramips/mt7621/config-5.10 +++ /dev/null @@ -1,294 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BOARD_SCACHE=y -CONFIG_BOUNCE=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MIPS_GIC=y -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_IDLE=y -# CONFIG_CPU_IDLE_GOV_LADDER is not set -CONFIG_CPU_IDLE_GOV_TEO=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_PM=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DIMLIB=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_GNUBEE1 is not set -# CONFIG_DTB_GNUBEE2 is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MT7621=y -# CONFIG_GPIO_RALINK is not set -CONFIG_GPIO_WATCHDOG=y -# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HIGHMEM=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_MT7621=y -CONFIG_ICPLUS_PHY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -# CONFIG_KERNEL_ZSTD is not set -CONFIG_LED_TRIGGER_PHY=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIKROTIK=y -CONFIG_MIKROTIK_RB_SYSFS=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -CONFIG_MIPS_CM=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -CONFIG_MIPS_CPC=y -CONFIG_MIPS_CPS=y -CONFIG_MIPS_CPS_CPUIDLE=y -# CONFIG_MIPS_CPS_NS16550_BOOL is not set -CONFIG_MIPS_CPS_PM=y -CONFIG_MIPS_CPU_SCACHE=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_GIC=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_NR_CPU_NR_MAP=4 -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MT7621_WDT=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MT7621=y -CONFIG_MTD_NAND_MTK_BMT=y -# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_ROUTERBOOT_PARTS=y -CONFIG_MTD_SERCOMM_PARTS=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_SPLIT_MINOR_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_TRX_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_VIRT_CONCAT=y -# CONFIG_MTK_HSDMA is not set -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_RALINK is not set -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PADATA=y -CONFIG_PCI=y -CONFIG_PCI_DISABLE_COMMON_QUIRKS=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_DRIVERS_GENERIC=y -CONFIG_PCI_MT7621=y -CONFIG_PCI_MT7621_PHY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_RALINK_USB is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_AW9523=y -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_SX150X=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RALINK=y -# CONFIG_RALINK_WDT is not set -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_BQ32K=y -CONFIG_RTC_DRV_PCF8563=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SCHED_SMT=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SOC_BUS=y -# CONFIG_SOC_MT7620 is not set -CONFIG_SOC_MT7621=y -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT7621=y -# CONFIG_SPI_RT2880 is not set -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SYNC_R4K=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MIPS_CPS=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WEAK_ORDERING=y -CONFIG_WEAK_REORDERING_BEYOND_LLSC=y -CONFIG_XPS=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/ramips/mt76x8/config-5.10 b/target/linux/ramips/mt76x8/config-5.10 deleted file mode 100644 index 514c674615..0000000000 --- a/target/linux/ramips/mt76x8/config-5.10 +++ /dev/null @@ -1,194 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_SYSTICK_QUIRK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_RT3352=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_MT7620A_EVAL is not set -# CONFIG_DTB_OMEGA2P is not set -CONFIG_DTB_RT_NONE=y -# CONFIG_DTB_VOCORE2 is not set -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_MT7621=y -# CONFIG_GPIO_RALINK is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_ICPLUS_PHY=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -# CONFIG_KERNEL_ZSTD is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MT7621_WDT=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_ESW_RT3050=y -# CONFIG_NET_RALINK_MT7620 is not set -CONFIG_NET_RALINK_RT3050=y -CONFIG_NET_RALINK_SOC=y -# CONFIG_NET_VENDOR_MEDIATEK is not set -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_RALINK=y -# CONFIG_RALINK_WDT is not set -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SOC_MT7620=y -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT7621=y -# CONFIG_SPI_RT2880 is not set -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/patches-5.10/020-mips-ralink-manage-low-reset-lines.patch b/target/linux/ramips/patches-5.10/020-mips-ralink-manage-low-reset-lines.patch deleted file mode 100644 index bdf98f223c..0000000000 --- a/target/linux/ramips/patches-5.10/020-mips-ralink-manage-low-reset-lines.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 3f9ef7785a9cd69cb75f5e2ea4ca79a24752e496 Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Wed, 3 Feb 2021 10:21:41 +0100 -Subject: MIPS: ralink: manage low reset lines - -Reset lines with indices smaller than 8 are currently considered invalid -by the rt2880-reset reset controller. - -The MT7621 SoC uses a number of these low reset lines. The DTS defines -reset lines "hsdma", "fe", and "mcm" with respective values 5, 6, and 2. -As a result of the above restriction, these resets cannot be asserted or -de-asserted by the reset controller. In cases where the bootloader does -not de-assert these lines, this results in e.g. the MT7621's internal -switch staying in reset. - -Change the reset controller to only ignore the system reset, so all -reset lines with index greater than 0 are considered valid. - -Signed-off-by: Sander Vanheule -Acked-by: John Crispin -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/ralink/reset.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/ralink/reset.c -+++ b/arch/mips/ralink/reset.c -@@ -27,7 +27,7 @@ static int ralink_assert_device(struct r - { - u32 val; - -- if (id < 8) -+ if (id == 0) - return -1; - - val = rt_sysc_r32(SYSC_REG_RESET_CTRL); -@@ -42,7 +42,7 @@ static int ralink_deassert_device(struct - { - u32 val; - -- if (id < 8) -+ if (id == 0) - return -1; - - val = rt_sysc_r32(SYSC_REG_RESET_CTRL); diff --git a/target/linux/ramips/patches-5.10/108-PCI-mt7621-Delay-phy-ports-initialization.patch b/target/linux/ramips/patches-5.10/108-PCI-mt7621-Delay-phy-ports-initialization.patch deleted file mode 100644 index ef03b00444..0000000000 --- a/target/linux/ramips/patches-5.10/108-PCI-mt7621-Delay-phy-ports-initialization.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 0cb2a8f3456ff1cc51d571e287a48e8fddc98ec2 Mon Sep 17 00:00:00 2001 -From: Sergio Paracuellos -Date: Sat, 31 Dec 2022 08:40:41 +0100 -Subject: PCI: mt7621: Delay phy ports initialization - -Some devices like ZBT WE1326 and ZBT WF3526-P and some Netgear models need -to delay phy port initialization after calling the mt7621_pcie_init_port() -driver function to get into reliable boots for both warm and hard resets. - -The delay required to detect the ports seems to be in the range [75-100] -milliseconds. - -If the ports are not detected the controller is not functional. - -There is no datasheet or something similar to really understand why this -extra delay is needed only for these devices and it is not for most of -the boards that are built on mt7621 SoC. - -This issue has been reported by openWRT community and the complete -discussion is in [0]. The 100 milliseconds delay has been tested in all -devices to validate it. - -Add the extra 100 milliseconds delay to fix the issue. - -[0]: https://github.com/openwrt/openwrt/pull/11220 - -Link: https://lore.kernel.org/r/20221231074041.264738-1-sergio.paracuellos@gmail.com -Fixes: 2bdd5238e756 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver") -Signed-off-by: Sergio Paracuellos -Signed-off-by: Lorenzo Pieralisi ---- - drivers/staging/mt7621-pci/pci-mt7621.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/staging/mt7621-pci/pci-mt7621.c -+++ b/drivers/staging/mt7621-pci/pci-mt7621.c -@@ -86,6 +86,7 @@ - #define MEMORY_BASE 0x0 - #define PERST_MODE_MASK GENMASK(11, 10) - #define PERST_MODE_GPIO BIT(10) -+#define INIT_PORTS_DELAY_MS 100 - #define PERST_DELAY_MS 100 - - /** -@@ -521,6 +522,7 @@ static void mt7621_pcie_init_ports(struc - } - } - -+ msleep(INIT_PORTS_DELAY_MS); - mt7621_pcie_reset_ep_deassert(pcie); - - tmp = NULL; diff --git a/target/linux/ramips/patches-5.10/200-add-ralink-eth.patch b/target/linux/ramips/patches-5.10/200-add-ralink-eth.patch deleted file mode 100644 index 90ba6e6c57..0000000000 --- a/target/linux/ramips/patches-5.10/200-add-ralink-eth.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/net/ethernet/Kconfig -+++ b/drivers/net/ethernet/Kconfig -@@ -159,6 +159,7 @@ source "drivers/net/ethernet/pasemi/Kcon - source "drivers/net/ethernet/pensando/Kconfig" - source "drivers/net/ethernet/qlogic/Kconfig" - source "drivers/net/ethernet/qualcomm/Kconfig" -+source "drivers/net/ethernet/ralink/Kconfig" - source "drivers/net/ethernet/rdc/Kconfig" - source "drivers/net/ethernet/realtek/Kconfig" - source "drivers/net/ethernet/renesas/Kconfig" ---- a/drivers/net/ethernet/Makefile -+++ b/drivers/net/ethernet/Makefile -@@ -71,6 +71,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES) - obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/ - obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/ - obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/ -+obj-$(CONFIG_NET_VENDOR_RALINK) += ralink/ - obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/ - obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/ - obj-$(CONFIG_NET_VENDOR_RDC) += rdc/ diff --git a/target/linux/ramips/patches-5.10/201-MIPS-ralink-rt288x-select-MIPS_AUTO_PFN_OFFSET.patch b/target/linux/ramips/patches-5.10/201-MIPS-ralink-rt288x-select-MIPS_AUTO_PFN_OFFSET.patch deleted file mode 100644 index 2b6bfd2b7b..0000000000 --- a/target/linux/ramips/patches-5.10/201-MIPS-ralink-rt288x-select-MIPS_AUTO_PFN_OFFSET.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Sat, 3 Apr 2021 18:51:44 -0700 -Subject: [PATCH] MIPS: ralink: rt288x: select MIPS_AUTO_PFN_OFFSET - -RT288X systems may have a non-zero ramstart causing problems with memory -reservations and boot hangs, as well as messages like: - Wasting 1048576 bytes for tracking 32768 unused pages - -Both are alleviated by selecting MIPS_AUTO_PFN_OFFSET for such -platforms. - -Tested on a Belkin F5D8235 v1 RT2880 device. - -Link: https://lore.kernel.org/linux-mips/20180820233111.xww5232dxbuouf4n@pburton-laptop/ - -Signed-off-by: Ilya Lipnitskiy -Cc: Mike Rapoport ---- - arch/mips/ralink/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -26,6 +26,7 @@ choice - - config SOC_RT288X - bool "RT288x" -+ select MIPS_AUTO_PFN_OFFSET - select MIPS_L1_CACHE_SHIFT_4 - select HAVE_LEGACY_CLK - select HAVE_PCI diff --git a/target/linux/ramips/patches-5.10/203-staging-mt7621-pci-phy-kconfig-select-regmap-mmio.patch b/target/linux/ramips/patches-5.10/203-staging-mt7621-pci-phy-kconfig-select-regmap-mmio.patch deleted file mode 100644 index e6c5db4db7..0000000000 --- a/target/linux/ramips/patches-5.10/203-staging-mt7621-pci-phy-kconfig-select-regmap-mmio.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/staging/mt7621-pci-phy/Kconfig -+++ b/drivers/staging/mt7621-pci-phy/Kconfig -@@ -3,6 +3,7 @@ config PCI_MT7621_PHY - tristate "MediaTek MT7621 PCI PHY Driver" - depends on RALINK && OF - select GENERIC_PHY -+ select REGMAP_MMIO - help - Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver, - diff --git a/target/linux/ramips/patches-5.10/300-mt7620-export-chip-version-and-pkg.patch b/target/linux/ramips/patches-5.10/300-mt7620-export-chip-version-and-pkg.patch deleted file mode 100644 index 8b4335eb03..0000000000 --- a/target/linux/ramips/patches-5.10/300-mt7620-export-chip-version-and-pkg.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- a/arch/mips/include/asm/mach-ralink/mt7620.h -+++ b/arch/mips/include/asm/mach-ralink/mt7620.h -@@ -135,4 +135,16 @@ static inline int mt7620_get_eco(void) - return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK; - } - -+static inline int mt7620_get_chipver(void) -+{ -+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) & -+ CHIP_REV_VER_MASK; -+} -+ -+static inline int mt7620_get_pkg(void) -+{ -+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) & -+ CHIP_REV_PKG_MASK; -+} -+ - #endif diff --git a/target/linux/ramips/patches-5.10/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch b/target/linux/ramips/patches-5.10/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch deleted file mode 100644 index a0b81bc6c5..0000000000 --- a/target/linux/ramips/patches-5.10/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch +++ /dev/null @@ -1,100 +0,0 @@ -From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 14 Jul 2013 23:08:11 +0200 -Subject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k - irq - -Signed-off-by: John Crispin ---- - arch/mips/ralink/Kconfig | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -1,12 +1,17 @@ - # SPDX-License-Identifier: GPL-2.0 - if RALINK - -+config CEVT_SYSTICK_QUIRK -+ bool -+ default n -+ - config CLKEVT_RT3352 - bool - depends on SOC_RT305X || SOC_MT7620 - default y - select TIMER_OF - select CLKSRC_MMIO -+ select CEVT_SYSTICK_QUIRK - - config RALINK_ILL_ACC - bool ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -16,6 +16,31 @@ - #include - #include - -+#ifdef CONFIG_CEVT_SYSTICK_QUIRK -+static int mips_state_oneshot(struct clock_event_device *evt) -+{ -+ unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; -+ if (!cp0_timer_irq_installed) { -+ cp0_timer_irq_installed = 1; -+ if (request_irq(evt->irq, c0_compare_interrupt, flags, "timer", -+ c0_compare_interrupt)) -+ pr_err("Failed to request irq %d (timer)\n", evt->irq); -+ } -+ -+ return 0; -+} -+ -+static int mips_state_shutdown(struct clock_event_device *evt) -+{ -+ if (cp0_timer_irq_installed) { -+ cp0_timer_irq_installed = 0; -+ free_irq(evt->irq, NULL); -+ } -+ -+ return 0; -+} -+#endif -+ - static int mips_next_event(unsigned long delta, - struct clock_event_device *evt) - { -@@ -296,7 +321,9 @@ core_initcall(r4k_register_cpufreq_notif - - int r4k_clockevent_init(void) - { -+#ifndef CONFIG_CEVT_SYSTICK_QUIRK - unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED; -+#endif - unsigned int cpu = smp_processor_id(); - struct clock_event_device *cd; - unsigned int irq, min_delta; -@@ -326,11 +353,16 @@ int r4k_clockevent_init(void) - cd->rating = 300; - cd->irq = irq; - cd->cpumask = cpumask_of(cpu); -+#ifdef CONFIG_CEVT_SYSTICK_QUIRK -+ cd->set_state_shutdown = mips_state_shutdown; -+ cd->set_state_oneshot = mips_state_oneshot; -+#endif - cd->set_next_event = mips_next_event; - cd->event_handler = mips_event_handler; - - clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff); - -+#ifndef CONFIG_CEVT_SYSTICK_QUIRK - if (cp0_timer_irq_installed) - return 0; - -@@ -339,6 +371,7 @@ int r4k_clockevent_init(void) - if (request_irq(irq, c0_compare_interrupt, flags, "timer", - c0_compare_interrupt)) - pr_err("Failed to request irq %d (timer)\n", irq); -+#endif - - return 0; - } diff --git a/target/linux/ramips/patches-5.10/312-MIPS-ralink-add-cpu-frequency-scaling.patch b/target/linux/ramips/patches-5.10/312-MIPS-ralink-add-cpu-frequency-scaling.patch deleted file mode 100644 index 0d70770941..0000000000 --- a/target/linux/ramips/patches-5.10/312-MIPS-ralink-add-cpu-frequency-scaling.patch +++ /dev/null @@ -1,195 +0,0 @@ -From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 28 Jul 2013 16:26:41 +0200 -Subject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling - -This feature will break udelay() and cause the delay loop to have longer delays -when the frequency is scaled causing a performance hit. - -Signed-off-by: John Crispin ---- - arch/mips/ralink/cevt-rt3352.c | 38 ++++++++++++++++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - ---- a/arch/mips/ralink/cevt-rt3352.c -+++ b/arch/mips/ralink/cevt-rt3352.c -@@ -29,6 +29,10 @@ - /* enable the counter */ - #define CFG_CNT_EN 0x1 - -+/* mt7620 frequency scaling defines */ -+#define CLK_LUT_CFG 0x40 -+#define SLEEP_EN BIT(31) -+ - struct systick_device { - void __iomem *membase; - struct clock_event_device dev; -@@ -36,21 +40,53 @@ struct systick_device { - int freq_scale; - }; - -+static void (*systick_freq_scaling)(struct systick_device *sdev, int status); -+ - static int systick_set_oneshot(struct clock_event_device *evt); - static int systick_shutdown(struct clock_event_device *evt); - -+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status) -+{ -+ if (sdev->freq_scale == status) -+ return; -+ -+ sdev->freq_scale = status; -+ -+ pr_info("%s: %s autosleep mode\n", sdev->dev.name, -+ (status) ? ("enable") : ("disable")); -+ if (status) -+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG); -+ else -+ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG); -+} -+ -+static inline unsigned int read_count(struct systick_device *sdev) -+{ -+ return ioread32(sdev->membase + SYSTICK_COUNT); -+} -+ -+static inline unsigned int read_compare(struct systick_device *sdev) -+{ -+ return ioread32(sdev->membase + SYSTICK_COMPARE); -+} -+ -+static inline void write_compare(struct systick_device *sdev, unsigned int val) -+{ -+ iowrite32(val, sdev->membase + SYSTICK_COMPARE); -+} -+ - static int systick_next_event(unsigned long delta, - struct clock_event_device *evt) - { - struct systick_device *sdev; -- u32 count; -+ int res; - - sdev = container_of(evt, struct systick_device, dev); -- count = ioread32(sdev->membase + SYSTICK_COUNT); -- count = (count + delta) % SYSTICK_FREQ; -- iowrite32(count, sdev->membase + SYSTICK_COMPARE); -+ delta += read_count(sdev); -+ write_compare(sdev, delta); -+ res = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0; - -- return 0; -+ return res; - } - - static void systick_event_handler(struct clock_event_device *dev) -@@ -60,20 +96,25 @@ static void systick_event_handler(struct - - static irqreturn_t systick_interrupt(int irq, void *dev_id) - { -- struct clock_event_device *dev = (struct clock_event_device *) dev_id; -+ int ret = 0; -+ struct clock_event_device *cdev; -+ struct systick_device *sdev; - -- dev->event_handler(dev); -+ if (read_c0_cause() & STATUSF_IP7) { -+ cdev = (struct clock_event_device *) dev_id; -+ sdev = container_of(cdev, struct systick_device, dev); -+ -+ /* Clear Count/Compare Interrupt */ -+ write_compare(sdev, read_compare(sdev)); -+ cdev->event_handler(cdev); -+ ret = 1; -+ } - -- return IRQ_HANDLED; -+ return IRQ_RETVAL(ret); - } - - static struct systick_device systick = { - .dev = { -- /* -- * cevt-r4k uses 300, make sure systick -- * gets used if available -- */ -- .rating = 310, - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_next_event = systick_next_event, - .set_state_shutdown = systick_shutdown, -@@ -91,7 +132,13 @@ static int systick_shutdown(struct clock - if (sdev->irq_requested) - free_irq(systick.dev.irq, &systick.dev); - sdev->irq_requested = 0; -- iowrite32(0, systick.membase + SYSTICK_CONFIG); -+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG); -+ -+ if (systick_freq_scaling) -+ systick_freq_scaling(sdev, 0); -+ -+ if (systick_freq_scaling) -+ systick_freq_scaling(sdev, 1); - - return 0; - } -@@ -116,33 +163,46 @@ static int systick_set_oneshot(struct cl - return 0; - } - -+static const struct of_device_id systick_match[] = { -+ { .compatible = "ralink,mt7620a-systick", .data = mt7620_freq_scaling}, -+ {}, -+}; -+ - static int __init ralink_systick_init(struct device_node *np) - { -- int ret; -+ const struct of_device_id *match; -+ int rating = 200; - - systick.membase = of_iomap(np, 0); - if (!systick.membase) - return -ENXIO; - -- systick.dev.name = np->name; -- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60); -- systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev); -- systick.dev.max_delta_ticks = 0x7fff; -- systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev); -- systick.dev.min_delta_ticks = 0x3; -+ match = of_match_node(systick_match, np); -+ if (match) { -+ systick_freq_scaling = match->data; -+ /* -+ * cevt-r4k uses 300, make sure systick -+ * gets used if available -+ */ -+ rating = 310; -+ } -+ -+ /* enable counter than register clock source */ -+ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG); -+ clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name, -+ SYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up); -+ -+ /* register clock event */ - systick.dev.irq = irq_of_parse_and_map(np, 0); - if (!systick.dev.irq) { - pr_err("%pOFn: request_irq failed", np); - return -EINVAL; - } - -- ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name, -- SYSTICK_FREQ, 301, 16, -- clocksource_mmio_readl_up); -- if (ret) -- return ret; -- -- clockevents_register_device(&systick.dev); -+ systick.dev.name = np->name; -+ systick.dev.rating = rating; -+ systick.dev.cpumask = cpumask_of(0); -+ clockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff); - - pr_info("%pOFn: running - mult: %d, shift: %d\n", - np, systick.dev.mult, systick.dev.shift); diff --git a/target/linux/ramips/patches-5.10/314-MIPS-add-bootargs-override-property.patch b/target/linux/ramips/patches-5.10/314-MIPS-add-bootargs-override-property.patch deleted file mode 100644 index a5df046ba7..0000000000 --- a/target/linux/ramips/patches-5.10/314-MIPS-add-bootargs-override-property.patch +++ /dev/null @@ -1,63 +0,0 @@ -From f15d27f9c90ede4b16eb37f9ae573ef81c2b6996 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Thu, 31 Dec 2020 18:49:12 +0100 -Subject: [PATCH] MIPS: add bootargs-override property - -Add support for the bootargs-override property to the chosen node -similar to the one used on ipq806x or mpc85xx. - -This is necessary, as the U-Boot used on some boards, notably the -Ubiquiti UniFi 6 Lite, overwrite the bootargs property of the chosen -node leading to a kernel panic when loading OpenWrt. - -Signed-off-by: David Bauer ---- - arch/mips/kernel/setup.c | 30 ++++++++++++++++++++++++++++++ - 1 file changed, 30 insertions(+) - ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -542,8 +542,28 @@ static int __init bootcmdline_scan_chose - - #endif /* CONFIG_OF_EARLY_FLATTREE */ - -+static int __init bootcmdline_scan_chosen_override(unsigned long node, const char *uname, -+ int depth, void *data) -+{ -+ bool *dt_bootargs = data; -+ const char *p; -+ int l; -+ -+ if (depth != 1 || !data || strcmp(uname, "chosen") != 0) -+ return 0; -+ -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) { -+ strlcpy(boot_command_line, p, COMMAND_LINE_SIZE); -+ *dt_bootargs = true; -+ } -+ -+ return 1; -+} -+ - static void __init bootcmdline_init(void) - { -+ bool dt_bootargs_override = false; - bool dt_bootargs = false; - - /* -@@ -557,6 +577,14 @@ static void __init bootcmdline_init(void - } - - /* -+ * If bootargs-override in the chosen node is set, use this as the -+ * command line -+ */ -+ of_scan_flat_dt(bootcmdline_scan_chosen_override, &dt_bootargs_override); -+ if (dt_bootargs_override) -+ return; -+ -+ /* - * If the user specified a built-in command line & - * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is - * prepended to arguments from the bootloader or DT so we'll copy them diff --git a/target/linux/ramips/patches-5.10/315-owrt-hack-fix-mt7688-cache-issue.patch b/target/linux/ramips/patches-5.10/315-owrt-hack-fix-mt7688-cache-issue.patch deleted file mode 100644 index 59d4b3ce56..0000000000 --- a/target/linux/ramips/patches-5.10/315-owrt-hack-fix-mt7688-cache-issue.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:15:32 +0100 -Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue - -Signed-off-by: John Crispin ---- - arch/mips/kernel/setup.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/kernel/setup.c -+++ b/arch/mips/kernel/setup.c -@@ -694,8 +694,6 @@ static void __init arch_mem_init(char ** - if (crashk_res.start != crashk_res.end) - memblock_reserve(crashk_res.start, resource_size(&crashk_res)); - #endif -- device_tree_init(); -- - /* - * In order to reduce the possibility of kernel panic when failed to - * get IO TLB memory under CONFIG_SWIOTLB, it is better to allocate -@@ -815,6 +813,7 @@ void __init setup_arch(char **cmdline_p) - - cpu_cache_init(); - paging_init(); -+ device_tree_init(); - } - - unsigned long kernelsp[NR_CPUS]; diff --git a/target/linux/ramips/patches-5.10/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch b/target/linux/ramips/patches-5.10/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch deleted file mode 100644 index 1dc54ccf23..0000000000 --- a/target/linux/ramips/patches-5.10/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:18:05 +0100 -Subject: [PATCH 15/53] arch: mips: do not select illegal access driver by - default - -Signed-off-by: John Crispin ---- - arch/mips/ralink/Kconfig | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -14,9 +14,9 @@ config CLKEVT_RT3352 - select CEVT_SYSTICK_QUIRK - - config RALINK_ILL_ACC -- bool -+ bool "illegal access irq" - depends on SOC_RT305X -- default y -+ default n - - config IRQ_INTC - bool diff --git a/target/linux/ramips/patches-5.10/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch b/target/linux/ramips/patches-5.10/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch deleted file mode 100644 index 0eb6676414..0000000000 --- a/target/linux/ramips/patches-5.10/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Wed, 7 Apr 2021 13:07:38 -0700 -Subject: [PATCH] MIPS: add support for buggy MT7621S core detection - -Most MT7621 SoCs have 2 cores, which is detected and supported properly -by CPS. - -Unfortunately, MT7621 SoC has a less common S variant with only one core. -On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when -starting SMP. CPULAUNCH registers can be used in that case to detect the -absence of the second core and override the GCR_CONFIG PCORES field. - -Rework a long-standing OpenWrt patch to override the value of -mips_cps_numcores on single-core MT7621 systems. - -Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core -MT7621 device (Netgear R6220). - -Original 4.14 OpenWrt patch: -Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7 -Current 5.10 OpenWrt patch: -Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904 - -Suggested-by: Felix Fietkau -Signed-off-by: Ilya Lipnitskiy -Signed-off-by: Thomas Bogendoerfer ---- - arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) - ---- a/arch/mips/include/asm/mips-cps.h -+++ b/arch/mips/include/asm/mips-cps.h -@@ -10,6 +10,8 @@ - #include - #include - -+#include -+ - extern unsigned long __cps_access_bad_size(void) - __compiletime_error("Bad size for CPS accessor"); - -@@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_ - */ - static inline unsigned int mips_cps_numcores(unsigned int cluster) - { -+ unsigned int ncores; -+ - if (!mips_cm_present()) - return 0; - - /* Add one before masking to handle 0xff indicating no cores */ -- return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; -+ ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES; -+ -+ if (IS_ENABLED(CONFIG_SOC_MT7621)) { -+ struct cpulaunch *launch; -+ -+ /* -+ * Ralink MT7621S SoC is single core, but the GCR_CONFIG method -+ * always reports 2 cores. Check the second core's LAUNCH_FREADY -+ * flag to detect if the second core is missing. This method -+ * only works before the core has been started. -+ */ -+ launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); -+ launch += 2; /* MT7621 has 2 VPEs per core */ -+ if (!(launch->flags & LAUNCH_FREADY)) -+ ncores = 1; -+ } -+ -+ return ncores; - } - - /** diff --git a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch deleted file mode 100644 index 87f8081367..0000000000 --- a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch +++ /dev/null @@ -1,186 +0,0 @@ ---- a/arch/mips/include/asm/mach-ralink/mt7621.h -+++ b/arch/mips/include/asm/mach-ralink/mt7621.h -@@ -17,6 +17,10 @@ - #define SYSC_REG_CHIP_REV 0x0c - #define SYSC_REG_SYSTEM_CONFIG0 0x10 - #define SYSC_REG_SYSTEM_CONFIG1 0x14 -+#define SYSC_REG_CLKCFG0 0x2c -+#define SYSC_REG_CUR_CLK_STS 0x44 -+ -+#define MEMC_REG_CPU_PLL 0x648 - - #define CHIP_REV_PKG_MASK 0x1 - #define CHIP_REV_PKG_SHIFT 16 -@@ -24,6 +28,22 @@ - #define CHIP_REV_VER_SHIFT 8 - #define CHIP_REV_ECO_MASK 0xf - -+#define XTAL_MODE_SEL_MASK 0x7 -+#define XTAL_MODE_SEL_SHIFT 6 -+ -+#define CPU_CLK_SEL_MASK 0x3 -+#define CPU_CLK_SEL_SHIFT 30 -+ -+#define CUR_CPU_FDIV_MASK 0x1f -+#define CUR_CPU_FDIV_SHIFT 8 -+#define CUR_CPU_FFRAC_MASK 0x1f -+#define CUR_CPU_FFRAC_SHIFT 0 -+ -+#define CPU_PLL_PREDIV_MASK 0x3 -+#define CPU_PLL_PREDIV_SHIFT 12 -+#define CPU_PLL_FBDIV_MASK 0x7f -+#define CPU_PLL_FBDIV_SHIFT 4 -+ - #define MT7621_DRAM_BASE 0x0 - #define MT7621_DDR2_SIZE_MIN 32 - #define MT7621_DDR2_SIZE_MAX 256 ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -9,12 +9,17 @@ - #include - #include - #include -+#include -+#include -+#include -+#include - - #include - #include - #include - #include - #include -+#include - - #include - -@@ -105,11 +110,89 @@ static struct rt2880_pmx_group mt7621_pi - { 0 } - }; - -+static struct clk *clks[MT7621_CLK_MAX]; -+static struct clk_onecell_data clk_data = { -+ .clks = clks, -+ .clk_num = ARRAY_SIZE(clks), -+}; -+ - phys_addr_t mips_cpc_default_phys_base(void) - { - panic("Cannot detect cpc address"); - } - -+static struct clk *__init mt7621_add_sys_clkdev( -+ const char *id, unsigned long rate) -+{ -+ struct clk *clk; -+ int err; -+ -+ clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate); -+ if (IS_ERR(clk)) -+ panic("failed to allocate %s clock structure", id); -+ -+ err = clk_register_clkdev(clk, id, NULL); -+ if (err) -+ panic("unable to register %s clock device", id); -+ -+ return clk; -+} -+ -+void __init ralink_clk_init(void) -+{ -+ u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; -+ u32 pll, prediv, fbdiv; -+ u32 xtal_clk, cpu_clk, bus_clk; -+ const static u32 prediv_tbl[] = {0, 1, 2, 2}; -+ -+ syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); -+ xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; -+ -+ clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0); -+ clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK; -+ -+ curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); -+ ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK; -+ ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK; -+ -+ if (xtal_sel <= 2) -+ xtal_clk = 20 * 1000 * 1000; -+ else if (xtal_sel <= 5) -+ xtal_clk = 40 * 1000 * 1000; -+ else -+ xtal_clk = 25 * 1000 * 1000; -+ -+ switch (clk_sel) { -+ case 0: -+ cpu_clk = 500 * 1000 * 1000; -+ break; -+ case 1: -+ pll = rt_memc_r32(MEMC_REG_CPU_PLL); -+ fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK; -+ prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK; -+ cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; -+ break; -+ default: -+ cpu_clk = xtal_clk; -+ } -+ -+ cpu_clk = cpu_clk / ffiv * ffrac; -+ bus_clk = cpu_clk / 4; -+ -+ clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk); -+ clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk); -+ -+ pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000); -+ mips_hpt_frequency = cpu_clk / 2; -+} -+ -+static void __init mt7621_clocks_init_dt(struct device_node *np) -+{ -+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -+} -+ -+CLK_OF_DECLARE(mt7621, "mediatek,mt7621-pll", mt7621_clocks_init_dt); -+ - void __init ralink_of_remap(void) - { - rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); ---- a/arch/mips/ralink/timer-gic.c -+++ b/arch/mips/ralink/timer-gic.c -@@ -9,14 +9,14 @@ - - #include - #include --#include -+#include - - #include "common.h" - - void __init plat_time_init(void) - { - ralink_of_remap(); -- -+ ralink_clk_init(); - of_clk_init(NULL); - timer_probe(); - } ---- /dev/null -+++ b/include/dt-bindings/clock/mt7621-clk.h -@@ -0,0 +1,18 @@ -+/* -+ * Copyright (C) 2018 Weijie Gao -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __DT_BINDINGS_MT7621_CLK_H -+#define __DT_BINDINGS_MT7621_CLK_H -+ -+#define MT7621_CLK_CPU 0 -+#define MT7621_CLK_BUS 1 -+ -+#define MT7621_CLK_MAX 2 -+ -+#endif /* __DT_BINDINGS_MT7621_CLK_H */ diff --git a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch deleted file mode 100644 index 40fc5b71d9..0000000000 --- a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch +++ /dev/null @@ -1,129 +0,0 @@ -From b5a52351a66f3c2a7a207548aa87d78ff2d336c0 Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Wed, 10 Jul 2019 00:24:48 +0800 -Subject: [PATCH] MIPS: ralink: mt7621: add memory detection support - -mt7621 has the following memory map: -0x0-0x1c000000: lower 448m memory -0x1c000000-0x2000000: peripheral registers -0x20000000-0x2400000: higher 64m memory - -detect_memory_region in arch/mips/kernel/setup.c only add the first -memory region and isn't suitable for 512m memory detection because -it may accidentally read the memory area for peripheral registers. - -This commit adds memory detection capability for mt7621: -1. add the highmem area when 512m is detected. -2. guard memcmp from accessing peripheral registers: - This only happens when some weird user decided to change - kernel load address to 256m or higher address. Since this - is a quite unusual case, we just skip 512m testing and return - 256m as memory size. - -Signed-off-by: Chuanhong Guo ---- - arch/mips/include/asm/mach-ralink/mt7621.h | 7 ++--- - arch/mips/ralink/mt7621.c | 30 +++++++++++++++++++--- - 2 files changed, 30 insertions(+), 7 deletions(-) - ---- a/arch/mips/include/asm/mach-ralink/mt7621.h -+++ b/arch/mips/include/asm/mach-ralink/mt7621.h -@@ -44,9 +44,10 @@ - #define CPU_PLL_FBDIV_MASK 0x7f - #define CPU_PLL_FBDIV_SHIFT 4 - --#define MT7621_DRAM_BASE 0x0 --#define MT7621_DDR2_SIZE_MIN 32 --#define MT7621_DDR2_SIZE_MAX 256 -+#define MT7621_LOWMEM_BASE 0x0 -+#define MT7621_LOWMEM_MAX_SIZE 0x1C000000 -+#define MT7621_HIGHMEM_BASE 0x20000000 -+#define MT7621_HIGHMEM_SIZE 0x4000000 - - #define MT7621_CHIP_NAME0 0x3637544D - #define MT7621_CHIP_NAME1 0x20203132 ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -9,11 +9,13 @@ - #include - #include - #include -+#include - #include - #include - #include - #include - -+#include - #include - #include - #include -@@ -54,6 +56,8 @@ - #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 - #define MT7621_GPIO_MODE_SDHCI_GPIO 1 - -+static void *detect_magic __initdata = detect_memory_region; -+ - static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; - static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; - static struct rt2880_pmx_func uart3_grp[] = { -@@ -138,6 +142,26 @@ static struct clk *__init mt7621_add_sys - return clk; - } - -+void __init mt7621_memory_detect(void) -+{ -+ void *dm = &detect_magic; -+ phys_addr_t size; -+ -+ for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) { -+ if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic))) -+ break; -+ } -+ -+ if ((size == 256 * SZ_1M) && -+ (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) && -+ __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) { -+ memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE); -+ memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE); -+ } else { -+ memblock_add(MT7621_LOWMEM_BASE, size); -+ } -+} -+ - void __init ralink_clk_init(void) - { - u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; -@@ -277,10 +301,7 @@ void prom_soc_init(struct ralink_soc_inf - (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, - (rev & CHIP_REV_ECO_MASK)); - -- soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN; -- soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX; -- soc_info->mem_base = MT7621_DRAM_BASE; -- -+ soc_info->mem_detect = mt7621_memory_detect; - rt2880_pinmux_data = mt7621_pinmux_data; - - soc_dev_init(soc_info, rev); ---- a/arch/mips/ralink/common.h -+++ b/arch/mips/ralink/common.h -@@ -17,6 +17,7 @@ struct ralink_soc_info { - unsigned long mem_size; - unsigned long mem_size_min; - unsigned long mem_size_max; -+ void (*mem_detect)(void); - }; - extern struct ralink_soc_info soc_info; - ---- a/arch/mips/ralink/of.c -+++ b/arch/mips/ralink/of.c -@@ -85,6 +85,8 @@ void __init plat_mem_setup(void) - of_scan_flat_dt(early_init_dt_find_memory, NULL); - if (memory_dtb) - of_scan_flat_dt(early_init_dt_scan_memory, NULL); -+ else if (soc_info.mem_detect) -+ soc_info.mem_detect(); - else if (soc_info.mem_size) - memblock_add(soc_info.mem_base, soc_info.mem_size * SZ_1M); - else diff --git a/target/linux/ramips/patches-5.10/324-mt7621-perfctr-fix.patch b/target/linux/ramips/patches-5.10/324-mt7621-perfctr-fix.patch deleted file mode 100644 index dfeac7eb99..0000000000 --- a/target/linux/ramips/patches-5.10/324-mt7621-perfctr-fix.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/arch/mips/ralink/irq-gic.c -+++ b/arch/mips/ralink/irq-gic.c -@@ -13,6 +13,12 @@ - - int get_c0_perfcount_int(void) - { -+ /* -+ * Performance counter events are routed through GIC. -+ * Prevent them from firing on CPU IRQ7 as well -+ */ -+ clear_c0_status(IE_SW0 << 7); -+ - return gic_get_c0_perfcount_int(); - } - EXPORT_SYMBOL_GPL(get_c0_perfcount_int); diff --git a/target/linux/ramips/patches-5.10/325-mt7621-fix-memory-detect.patch b/target/linux/ramips/patches-5.10/325-mt7621-fix-memory-detect.patch deleted file mode 100644 index ad072ec54e..0000000000 --- a/target/linux/ramips/patches-5.10/325-mt7621-fix-memory-detect.patch +++ /dev/null @@ -1,58 +0,0 @@ ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -56,7 +56,9 @@ - #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 - #define MT7621_GPIO_MODE_SDHCI_GPIO 1 - --static void *detect_magic __initdata = detect_memory_region; -+#define MT7621_MEM_TEST_PATTERN 0xaa5555aa -+ -+static u32 detect_magic __initdata; - - static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; - static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; -@@ -142,24 +144,32 @@ static struct clk *__init mt7621_add_sys - return clk; - } - -+static bool __init mt7621_addr_wraparound_test(phys_addr_t size) -+{ -+ void *dm = (void *)KSEG1ADDR(&detect_magic); -+ if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE) -+ return true; -+ __raw_writel(MT7621_MEM_TEST_PATTERN, dm); -+ if (__raw_readl(dm) != __raw_readl(dm + size)) -+ return false; -+ __raw_writel(!MT7621_MEM_TEST_PATTERN, dm); -+ return __raw_readl(dm) == __raw_readl(dm + size); -+} -+ - void __init mt7621_memory_detect(void) - { -- void *dm = &detect_magic; - phys_addr_t size; - -- for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) { -- if (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic))) -- break; -+ for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) { -+ if (mt7621_addr_wraparound_test(size)) { -+ memblock_add(MT7621_LOWMEM_BASE, size); -+ return; -+ } - } - -- if ((size == 256 * SZ_1M) && -- (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) && -- __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) { -- memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE); -- memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE); -- } else { -- memblock_add(MT7621_LOWMEM_BASE, size); -- } -+ /* addr doesn't wrap around at dm + 256M, assume 512M memory. */ -+ memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE); -+ memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE); - } - - void __init ralink_clk_init(void) diff --git a/target/linux/ramips/patches-5.10/400-mtd-cfi-cmdset-0002-force-word-write.patch b/target/linux/ramips/patches-5.10/400-mtd-cfi-cmdset-0002-force-word-write.patch deleted file mode 100644 index 7011bbe50b..0000000000 --- a/target/linux/ramips/patches-5.10/400-mtd-cfi-cmdset-0002-force-word-write.patch +++ /dev/null @@ -1,20 +0,0 @@ -From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 15 Jul 2013 00:39:21 +0200 -Subject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write - ---- - drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++++-- - 1 file changed, 7 insertions(+), 2 deletions(-) - ---- a/drivers/mtd/chips/cfi_cmdset_0002.c -+++ b/drivers/mtd/chips/cfi_cmdset_0002.c -@@ -40,7 +40,7 @@ - #include - - #define AMD_BOOTLOC_BUG --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - #define MAX_RETRIES 3 - diff --git a/target/linux/ramips/patches-5.10/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch b/target/linux/ramips/patches-5.10/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch deleted file mode 100644 index dead8e7595..0000000000 --- a/target/linux/ramips/patches-5.10/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch +++ /dev/null @@ -1,75 +0,0 @@ -From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Thu, 6 May 2021 17:49:55 +0200 -Subject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as - -Add MTD support for the BoHong bh25q128as SPI NOR chip. -The chip has 16MB of total capacity, divided into a total of 256 -sectors, each 64KB sized. The chip also supports 4KB sectors. -Additionally, it supports dual and quad read modes. - -Functionality was verified on an Tenbay WR1800K / MTK MT7621 board. - -Signed-off-by: David Bauer ---- - drivers/mtd/spi-nor/Makefile | 1 + - drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++ - drivers/mtd/spi-nor/core.c | 1 + - drivers/mtd/spi-nor/core.h | 1 + - 4 files changed, 24 insertions(+) - create mode 100644 drivers/mtd/spi-nor/bohong.c - ---- a/drivers/mtd/spi-nor/Makefile -+++ b/drivers/mtd/spi-nor/Makefile -@@ -2,6 +2,7 @@ - - spi-nor-objs := core.o sfdp.o - spi-nor-objs += atmel.o -+spi-nor-objs += bohong.o - spi-nor-objs += catalyst.o - spi-nor-objs += eon.o - spi-nor-objs += esmt.o ---- /dev/null -+++ b/drivers/mtd/spi-nor/bohong.c -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2005, Intec Automation Inc. -+ * Copyright (C) 2014, Freescale Semiconductor, Inc. -+ */ -+ -+#include -+ -+#include "core.h" -+ -+static const struct flash_info bohong_parts[] = { -+ /* BoHong Microelectronics */ -+ { "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+}; -+ -+const struct spi_nor_manufacturer spi_nor_bohong = { -+ .name = "bohong", -+ .parts = bohong_parts, -+ .nparts = ARRAY_SIZE(bohong_parts), -+}; ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -2023,6 +2023,7 @@ int spi_nor_sr2_bit7_quad_enable(struct - - static const struct spi_nor_manufacturer *manufacturers[] = { - &spi_nor_atmel, -+ &spi_nor_bohong, - &spi_nor_catalyst, - &spi_nor_eon, - &spi_nor_esmt, ---- a/drivers/mtd/spi-nor/core.h -+++ b/drivers/mtd/spi-nor/core.h -@@ -382,6 +382,7 @@ struct spi_nor_manufacturer { - - /* Manufacturer drivers. */ - extern const struct spi_nor_manufacturer spi_nor_atmel; -+extern const struct spi_nor_manufacturer spi_nor_bohong; - extern const struct spi_nor_manufacturer spi_nor_catalyst; - extern const struct spi_nor_manufacturer spi_nor_eon; - extern const struct spi_nor_manufacturer spi_nor_esmt; diff --git a/target/linux/ramips/patches-5.10/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch b/target/linux/ramips/patches-5.10/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch deleted file mode 100644 index d0686a7051..0000000000 --- a/target/linux/ramips/patches-5.10/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch +++ /dev/null @@ -1,47 +0,0 @@ -From e84e2430ee0e483842b4ff013ae8a6e7e2fa2734 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 1 Apr 2020 02:07:58 +0800 -Subject: [PATCH 1/2] mtd: rawnand: add driver support for MT7621 nand - flash controller - -This patch adds NAND flash controller driver for MediaTek MT7621 SoC. - -The NAND flash controller is similar with controllers described in -mtk_nand.c, except that the controller from MT7621 doesn't support DMA -transmission, and some registers' offset and fields are different. - -Signed-off-by: Weijie Gao ---- - drivers/mtd/nand/raw/Kconfig | 8 + - drivers/mtd/nand/raw/Makefile | 1 + - drivers/mtd/nand/raw/mt7621_nand.c | 1348 ++++++++++++++++++++++++++++++++++++ - 3 files changed, 1357 insertions(+) - create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c - ---- a/drivers/mtd/nand/raw/Kconfig -+++ b/drivers/mtd/nand/raw/Kconfig -@@ -387,6 +387,14 @@ config MTD_NAND_QCOM - Enables support for NAND flash chips on SoCs containing the EBI2 NAND - controller. This controller is found on IPQ806x SoC. - -+config MTD_NAND_MT7621 -+ tristate "MT7621 NAND controller" -+ depends on SOC_MT7621 || COMPILE_TEST -+ depends on HAS_IOMEM -+ help -+ Enables support for NAND controller on MT7621 SoC. -+ This driver uses PIO mode for data transmission instead of DMA mode. -+ - config MTD_NAND_MTK - tristate "MTK NAND controller" - depends on ARCH_MEDIATEK || COMPILE_TEST ---- a/drivers/mtd/nand/raw/Makefile -+++ b/drivers/mtd/nand/raw/Makefile -@@ -51,6 +51,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n - obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o - obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ - obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o -+obj-$(CONFIG_MTD_NAND_MT7621) += mt7621_nand.o - obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o - obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o - obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o diff --git a/target/linux/ramips/patches-5.10/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch b/target/linux/ramips/patches-5.10/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch deleted file mode 100644 index 3d122c10c0..0000000000 --- a/target/linux/ramips/patches-5.10/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 1 Apr 2020 02:07:59 +0800 -Subject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver - -This patch adds documentation for MediaTek MT7621 NAND flash controller -driver. - -Signed-off-by: Weijie Gao ---- - .../bindings/mtd/mediatek,mt7621-nfc.yaml | 68 ++++++++++++++++++++++ - 1 file changed, 68 insertions(+) - create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml -@@ -0,0 +1,68 @@ -+# SPDX-License-Identifier: GPL-2.0 -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding -+ -+maintainers: -+ - Weijie Gao -+ -+description: | -+ This driver uses a single node to describe both NAND Flash controller -+ interface (NFI) and ECC engine for MT7621 SoC. -+ MT7621 supports only one chip select. -+ -+properties: -+ "#address-cells": false -+ "#size-cells": false -+ -+ compatible: -+ enum: -+ - mediatek,mt7621-nfc -+ -+ reg: -+ items: -+ - description: Register base of NFI core -+ - description: Register base of ECC engine -+ -+ reg-names: -+ items: -+ - const: nfi -+ - const: ecc -+ -+ clocks: -+ items: -+ - description: Source clock for NFI core, fixed 125MHz -+ -+ clock-names: -+ items: -+ - const: nfi_clk -+ -+required: -+ - compatible -+ - reg -+ - reg-names -+ - clocks -+ - clock-names -+ -+examples: -+ - | -+ nficlock: nficlock { -+ #clock-cells = <0>; -+ compatible = "fixed-clock"; -+ -+ clock-frequency = <125000000>; -+ }; -+ -+ nand@1e003000 { -+ compatible = "mediatek,mt7621-nfc"; -+ -+ reg = <0x1e003000 0x800 -+ 0x1e003800 0x800>; -+ reg-names = "nfi", "ecc"; -+ -+ clocks = <&nficlock>; -+ clock-names = "nfi_clk"; -+ }; diff --git a/target/linux/ramips/patches-5.10/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-5.10/700-net-ethernet-mediatek-support-net-labels.patch deleted file mode 100644 index 0b3dc00e54..0000000000 --- a/target/linux/ramips/patches-5.10/700-net-ethernet-mediatek-support-net-labels.patch +++ /dev/null @@ -1,34 +0,0 @@ -From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= -Date: Fri, 21 Jun 2019 10:04:05 +0200 -Subject: [PATCH] net: ethernet: mediatek: support net-labels - -With this patch, device name can be set within dts file in the same way as dsa -port can. -Add: label = "wan"; to GMAC node. - -Signed-off-by: René van Dorst ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2980,6 +2980,7 @@ static const struct net_device_ops mtk_n - - static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) - { -+ const char *name = of_get_property(np, "label", NULL); - const __be32 *_id = of_get_property(np, "reg", NULL); - phy_interface_t phy_mode; - struct phylink *phylink; -@@ -3075,6 +3076,9 @@ static int mtk_add_mac(struct mtk_eth *e - else - eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; - -+ if (name) -+ strlcpy(eth->netdev[id]->name, name, IFNAMSIZ); -+ - return 0; - - free_netdev: diff --git a/target/linux/ramips/patches-5.10/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-5.10/720-Revert-net-phy-simplify-phy_link_change-arguments.patch deleted file mode 100644 index f3df206f3e..0000000000 --- a/target/linux/ramips/patches-5.10/720-Revert-net-phy-simplify-phy_link_change-arguments.patch +++ /dev/null @@ -1,118 +0,0 @@ -From ffbb1b37a3e1ce1a5c574a6bd4f5aede8bc468ac Mon Sep 17 00:00:00 2001 -From: Ilya Lipnitskiy -Date: Sat, 27 Feb 2021 20:20:07 -0800 -Subject: [PATCH] Revert "net: phy: simplify phy_link_change arguments" - -This reverts commit a307593a644443db12888f45eed0dafb5869e2cc. - -This brings back the do_carrier flags used by the (hacky) next patch, -still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c ---- - drivers/net/phy/phy.c | 12 ++++++------ - drivers/net/phy/phy_device.c | 12 +++++++----- - drivers/net/phy/phylink.c | 3 ++- - include/linux/phy.h | 2 +- - 4 files changed, 16 insertions(+), 13 deletions(-) - ---- a/drivers/net/phy/phy.c -+++ b/drivers/net/phy/phy.c -@@ -70,13 +70,13 @@ static void phy_process_state_change(str - - static void phy_link_up(struct phy_device *phydev) - { -- phydev->phy_link_change(phydev, true); -+ phydev->phy_link_change(phydev, true, true); - phy_led_trigger_change_speed(phydev); - } - --static void phy_link_down(struct phy_device *phydev) -+static void phy_link_down(struct phy_device *phydev, bool do_carrier) - { -- phydev->phy_link_change(phydev, false); -+ phydev->phy_link_change(phydev, false, do_carrier); - phy_led_trigger_change_speed(phydev); - } - -@@ -584,7 +584,7 @@ int phy_start_cable_test(struct phy_devi - goto out; - - /* Mark the carrier down until the test is complete */ -- phy_link_down(phydev); -+ phy_link_down(phydev, true); - - netif_testing_on(dev); - err = phydev->drv->cable_test_start(phydev); -@@ -655,7 +655,7 @@ int phy_start_cable_test_tdr(struct phy_ - goto out; - - /* Mark the carrier down until the test is complete */ -- phy_link_down(phydev); -+ phy_link_down(phydev, true); - - netif_testing_on(dev); - err = phydev->drv->cable_test_tdr_start(phydev, config); -@@ -726,7 +726,7 @@ static int phy_check_link_status(struct - phy_link_up(phydev); - } else if (!phydev->link && phydev->state != PHY_NOLINK) { - phydev->state = PHY_NOLINK; -- phy_link_down(phydev); -+ phy_link_down(phydev, true); - } - - return 0; -@@ -1241,7 +1241,7 @@ void phy_state_machine(struct work_struc - case PHY_HALTED: - if (phydev->link) { - phydev->link = 0; -- phy_link_down(phydev); -+ phy_link_down(phydev, true); - } - do_suspend = true; - break; ---- a/drivers/net/phy/phy_device.c -+++ b/drivers/net/phy/phy_device.c -@@ -936,14 +936,16 @@ struct phy_device *phy_find_first(struct - } - EXPORT_SYMBOL(phy_find_first); - --static void phy_link_change(struct phy_device *phydev, bool up) -+static void phy_link_change(struct phy_device *phydev, bool up, bool do_carrier) - { - struct net_device *netdev = phydev->attached_dev; - -- if (up) -- netif_carrier_on(netdev); -- else -- netif_carrier_off(netdev); -+ if (do_carrier) { -+ if (up) -+ netif_carrier_on(netdev); -+ else -+ netif_carrier_off(netdev); -+ } - phydev->adjust_link(netdev); - if (phydev->mii_ts && phydev->mii_ts->link_state) - phydev->mii_ts->link_state(phydev->mii_ts, phydev); ---- a/drivers/net/phy/phylink.c -+++ b/drivers/net/phy/phylink.c -@@ -931,7 +931,8 @@ void phylink_destroy(struct phylink *pl) - } - EXPORT_SYMBOL_GPL(phylink_destroy); - --static void phylink_phy_change(struct phy_device *phydev, bool up) -+static void phylink_phy_change(struct phy_device *phydev, bool up, -+ bool do_carrier) - { - struct phylink *pl = phydev->phylink; - bool tx_pause, rx_pause; ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -642,7 +642,7 @@ struct phy_device { - u8 mdix; - u8 mdix_ctrl; - -- void (*phy_link_change)(struct phy_device *phydev, bool up); -+ void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier); - void (*adjust_link)(struct net_device *dev); - - #if IS_ENABLED(CONFIG_MACSEC) diff --git a/target/linux/ramips/patches-5.10/721-NET-no-auto-carrier-off-support.patch b/target/linux/ramips/patches-5.10/721-NET-no-auto-carrier-off-support.patch deleted file mode 100644 index 00a4192840..0000000000 --- a/target/linux/ramips/patches-5.10/721-NET-no-auto-carrier-off-support.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:38:50 +0100 -Subject: [PATCH 34/53] NET: multi phy support - -Signed-off-by: John Crispin ---- - drivers/net/phy/phy.c | 9 ++++++--- - include/linux/phy.h | 1 + - 2 files changed, 7 insertions(+), 3 deletions(-) - ---- a/drivers/net/phy/phy.c -+++ b/drivers/net/phy/phy.c -@@ -726,7 +726,10 @@ static int phy_check_link_status(struct - phy_link_up(phydev); - } else if (!phydev->link && phydev->state != PHY_NOLINK) { - phydev->state = PHY_NOLINK; -- phy_link_down(phydev, true); -+ if (!phydev->no_auto_carrier_off) -+ phy_link_down(phydev, true); -+ else -+ phy_link_down(phydev, false); - } - - return 0; -@@ -1241,7 +1244,10 @@ void phy_state_machine(struct work_struc - case PHY_HALTED: - if (phydev->link) { - phydev->link = 0; -- phy_link_down(phydev, true); -+ if (!phydev->no_auto_carrier_off) -+ phy_link_down(phydev, true); -+ else -+ phy_link_down(phydev, false); - } - do_suspend = true; - break; ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -561,6 +561,7 @@ struct phy_device { - unsigned sysfs_links:1; - unsigned loopback_enabled:1; - unsigned downshifted_rate:1; -+ unsigned no_auto_carrier_off:1; - - unsigned autoneg:1; - /* The most recently read link state */ diff --git a/target/linux/ramips/patches-5.10/801-DT-Add-documentation-for-gpio-ralink.patch b/target/linux/ramips/patches-5.10/801-DT-Add-documentation-for-gpio-ralink.patch deleted file mode 100644 index 93dabf8776..0000000000 --- a/target/linux/ramips/patches-5.10/801-DT-Add-documentation-for-gpio-ralink.patch +++ /dev/null @@ -1,59 +0,0 @@ -From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 28 Jul 2013 19:45:30 +0200 -Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink - -Describe gpio-ralink binding. - -Signed-off-by: John Crispin -Cc: linux-mips@linux-mips.org -Cc: devicetree@vger.kernel.org -Cc: linux-gpio@vger.kernel.org ---- - .../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++ - 1 file changed, 40 insertions(+) - create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt -@@ -0,0 +1,40 @@ -+Ralink SoC GPIO controller bindings -+ -+Required properties: -+- compatible: -+ - "ralink,rt2880-gpio" for Ralink controllers -+- #gpio-cells : Should be two. -+ - first cell is the pin number -+ - second cell is used to specify optional parameters (unused) -+- gpio-controller : Marks the device node as a GPIO controller -+- reg : Physical base address and length of the controller's registers -+- interrupt-parent: phandle to the INTC device node -+- interrupts : Specify the INTC interrupt number -+- ngpios : Specify the number of GPIOs -+- ralink,register-map : The register layout depends on the GPIO bank and actual -+ SoC type. Register offsets need to be in this order. -+ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ] -+ -+Optional properties: -+- ralink,gpio-base : Specify the GPIO chips base number -+ -+Example: -+ -+ gpio0: gpio@600 { -+ compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio"; -+ -+ #gpio-cells = <2>; -+ gpio-controller; -+ -+ reg = <0x600 0x34>; -+ -+ interrupt-parent = <&intc>; -+ interrupts = <6>; -+ -+ ngpios = <24>; -+ ralink,gpio-base = <0>; -+ ralink,register-map = [ 00 04 08 0c -+ 20 24 28 2c -+ 30 34 ]; -+ -+ }; diff --git a/target/linux/ramips/patches-5.10/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch b/target/linux/ramips/patches-5.10/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch deleted file mode 100644 index 52d40215f2..0000000000 --- a/target/linux/ramips/patches-5.10/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch +++ /dev/null @@ -1,416 +0,0 @@ -From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 4 Aug 2014 20:36:29 +0200 -Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC - -Add gpio driver for Ralink SoC. This driver makes the gpio core on -RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work. - -Signed-off-by: John Crispin -Cc: linux-mips@linux-mips.org -Cc: linux-gpio@vger.kernel.org ---- - arch/mips/include/asm/mach-ralink/gpio.h | 24 ++ - drivers/gpio/Kconfig | 6 + - drivers/gpio/Makefile | 1 + - drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++ - 4 files changed, 386 insertions(+) - create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h - create mode 100644 drivers/gpio/gpio-ralink.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-ralink/gpio.h -@@ -0,0 +1,24 @@ -+/* -+ * Ralink SoC GPIO API support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MACH_RALINK_GPIO_H -+#define __ASM_MACH_RALINK_GPIO_H -+ -+#define ARCH_NR_GPIOS 128 -+#include -+ -+#define gpio_get_value __gpio_get_value -+#define gpio_set_value __gpio_set_value -+#define gpio_cansleep __gpio_cansleep -+#define gpio_to_irq __gpio_to_irq -+ -+#endif /* __ASM_MACH_RALINK_GPIO_H */ ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -535,6 +535,12 @@ config GPIO_SNPS_CREG - where only several fields in register belong to GPIO lines and - each GPIO line owns a field with different length and on/off value. - -+config GPIO_RALINK -+ bool "Ralink GPIO Support" -+ depends on RALINK -+ help -+ Say yes here to support the Ralink SoC GPIO device -+ - config GPIO_SPEAR_SPICS - bool "ST SPEAr13xx SPI Chip Select as GPIO support" - depends on PLAT_SPEAR ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -120,6 +120,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisos - obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o - obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o - obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o -+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o - obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o - obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o - obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o ---- /dev/null -+++ b/drivers/gpio/gpio-ralink.c -@@ -0,0 +1,341 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2009-2011 Gabor Juhos -+ * Copyright (C) 2013 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+enum ralink_gpio_reg { -+ GPIO_REG_INT = 0, -+ GPIO_REG_EDGE, -+ GPIO_REG_RENA, -+ GPIO_REG_FENA, -+ GPIO_REG_DATA, -+ GPIO_REG_DIR, -+ GPIO_REG_POL, -+ GPIO_REG_SET, -+ GPIO_REG_RESET, -+ GPIO_REG_TOGGLE, -+ GPIO_REG_MAX -+}; -+ -+struct ralink_gpio_chip { -+ struct gpio_chip chip; -+ u8 regs[GPIO_REG_MAX]; -+ -+ spinlock_t lock; -+ void __iomem *membase; -+ struct irq_domain *domain; -+ int irq; -+ -+ u32 rising; -+ u32 falling; -+}; -+ -+#define MAP_MAX 4 -+static struct irq_domain *irq_map[MAP_MAX]; -+static int irq_map_count; -+static atomic_t irq_refcount = ATOMIC_INIT(0); -+ -+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip) -+{ -+ struct ralink_gpio_chip *rg; -+ -+ rg = container_of(chip, struct ralink_gpio_chip, chip); -+ -+ return rg; -+} -+ -+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val) -+{ -+ iowrite32(val, rg->membase + rg->regs[reg]); -+} -+ -+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg) -+{ -+ return ioread32(rg->membase + rg->regs[reg]); -+} -+ -+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ -+ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset)); -+} -+ -+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ -+ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset)); -+} -+ -+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ unsigned long flags; -+ u32 t; -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ t = rt_gpio_r32(rg, GPIO_REG_DIR); -+ t &= ~BIT(offset); -+ rt_gpio_w32(rg, GPIO_REG_DIR, t); -+ spin_unlock_irqrestore(&rg->lock, flags); -+ -+ return 0; -+} -+ -+static int ralink_gpio_direction_output(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ unsigned long flags; -+ u32 t; -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ ralink_gpio_set(chip, offset, value); -+ t = rt_gpio_r32(rg, GPIO_REG_DIR); -+ t |= BIT(offset); -+ rt_gpio_w32(rg, GPIO_REG_DIR, t); -+ spin_unlock_irqrestore(&rg->lock, flags); -+ -+ return 0; -+} -+ -+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin) -+{ -+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip); -+ -+ if (rg->irq < 1) -+ return -1; -+ -+ return irq_create_mapping(rg->domain, pin); -+} -+ -+static void ralink_gpio_irq_handler(struct irq_desc *desc) -+{ -+ int i; -+ -+ for (i = 0; i < irq_map_count; i++) { -+ struct irq_domain *domain = irq_map[i]; -+ struct ralink_gpio_chip *rg; -+ unsigned long pending; -+ int bit; -+ -+ rg = (struct ralink_gpio_chip *) domain->host_data; -+ pending = rt_gpio_r32(rg, GPIO_REG_INT); -+ -+ for_each_set_bit(bit, &pending, rg->chip.ngpio) { -+ u32 map = irq_find_mapping(domain, bit); -+ generic_handle_irq(map); -+ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit)); -+ } -+ } -+} -+ -+static void ralink_gpio_irq_unmask(struct irq_data *d) -+{ -+ struct ralink_gpio_chip *rg; -+ unsigned long flags; -+ u32 rise, fall; -+ -+ rg = (struct ralink_gpio_chip *) d->domain->host_data; -+ rise = rt_gpio_r32(rg, GPIO_REG_RENA); -+ fall = rt_gpio_r32(rg, GPIO_REG_FENA); -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising)); -+ rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling)); -+ spin_unlock_irqrestore(&rg->lock, flags); -+} -+ -+static void ralink_gpio_irq_mask(struct irq_data *d) -+{ -+ struct ralink_gpio_chip *rg; -+ unsigned long flags; -+ u32 rise, fall; -+ -+ rg = (struct ralink_gpio_chip *) d->domain->host_data; -+ rise = rt_gpio_r32(rg, GPIO_REG_RENA); -+ fall = rt_gpio_r32(rg, GPIO_REG_FENA); -+ -+ spin_lock_irqsave(&rg->lock, flags); -+ rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq)); -+ rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq)); -+ spin_unlock_irqrestore(&rg->lock, flags); -+} -+ -+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type) -+{ -+ struct ralink_gpio_chip *rg; -+ u32 mask = BIT(d->hwirq); -+ -+ rg = (struct ralink_gpio_chip *) d->domain->host_data; -+ -+ if (type == IRQ_TYPE_PROBE) { -+ if ((rg->rising | rg->falling) & mask) -+ return 0; -+ -+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; -+ } -+ -+ if (type & IRQ_TYPE_EDGE_RISING) -+ rg->rising |= mask; -+ else -+ rg->rising &= ~mask; -+ -+ if (type & IRQ_TYPE_EDGE_FALLING) -+ rg->falling |= mask; -+ else -+ rg->falling &= ~mask; -+ -+ return 0; -+} -+ -+static struct irq_chip ralink_gpio_irq_chip = { -+ .name = "GPIO", -+ .irq_unmask = ralink_gpio_irq_unmask, -+ .irq_mask = ralink_gpio_irq_mask, -+ .irq_mask_ack = ralink_gpio_irq_mask, -+ .irq_set_type = ralink_gpio_irq_type, -+}; -+ -+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -+{ -+ irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq); -+ irq_set_handler_data(irq, d); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops irq_domain_ops = { -+ .xlate = irq_domain_xlate_onecell, -+ .map = gpio_map, -+}; -+ -+static void ralink_gpio_irq_init(struct device_node *np, -+ struct ralink_gpio_chip *rg) -+{ -+ if (irq_map_count >= MAP_MAX) -+ return; -+ -+ rg->irq = irq_of_parse_and_map(np, 0); -+ if (!rg->irq) -+ return; -+ -+ rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, -+ &irq_domain_ops, rg); -+ if (!rg->domain) { -+ dev_err(rg->chip.parent, "irq_domain_add_linear failed\n"); -+ return; -+ } -+ -+ irq_map[irq_map_count++] = rg->domain; -+ -+ rt_gpio_w32(rg, GPIO_REG_RENA, 0x0); -+ rt_gpio_w32(rg, GPIO_REG_FENA, 0x0); -+ -+ if (!atomic_read(&irq_refcount)) -+ irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler); -+ atomic_inc(&irq_refcount); -+ -+ dev_info(rg->chip.parent, "registering %d irq handlers\n", rg->chip.ngpio); -+} -+ -+static int ralink_gpio_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ struct ralink_gpio_chip *rg; -+ const __be32 *ngpio, *gpiobase; -+ -+ if (!res) { -+ dev_err(&pdev->dev, "failed to find resource\n"); -+ return -ENOMEM; -+ } -+ -+ rg = devm_kzalloc(&pdev->dev, -+ sizeof(struct ralink_gpio_chip), GFP_KERNEL); -+ if (!rg) -+ return -ENOMEM; -+ -+ rg->membase = devm_ioremap_resource(&pdev->dev, res); -+ if (!rg->membase) { -+ dev_err(&pdev->dev, "cannot remap I/O memory region\n"); -+ return -ENOMEM; -+ } -+ -+ if (of_property_read_u8_array(np, "ralink,register-map", -+ rg->regs, GPIO_REG_MAX)) { -+ dev_err(&pdev->dev, "failed to read register definition\n"); -+ return -EINVAL; -+ } -+ -+ ngpio = of_get_property(np, "ngpios", NULL); -+ if (!ngpio) { -+ dev_err(&pdev->dev, "failed to read number of pins\n"); -+ return -EINVAL; -+ } -+ -+ gpiobase = of_get_property(np, "ralink,gpio-base", NULL); -+ if (gpiobase) -+ rg->chip.base = be32_to_cpu(*gpiobase); -+ else -+ rg->chip.base = -1; -+ -+ spin_lock_init(&rg->lock); -+ -+ rg->chip.parent = &pdev->dev; -+ rg->chip.label = dev_name(&pdev->dev); -+ rg->chip.of_node = np; -+ rg->chip.ngpio = be32_to_cpu(*ngpio); -+ rg->chip.direction_input = ralink_gpio_direction_input; -+ rg->chip.direction_output = ralink_gpio_direction_output; -+ rg->chip.get = ralink_gpio_get; -+ rg->chip.set = ralink_gpio_set; -+ rg->chip.request = gpiochip_generic_request; -+ rg->chip.to_irq = ralink_gpio_to_irq; -+ rg->chip.free = gpiochip_generic_free; -+ -+ /* set polarity to low for all lines */ -+ rt_gpio_w32(rg, GPIO_REG_POL, 0); -+ -+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio); -+ -+ ralink_gpio_irq_init(np, rg); -+ -+ return gpiochip_add(&rg->chip); -+} -+ -+static const struct of_device_id ralink_gpio_match[] = { -+ { .compatible = "ralink,rt2880-gpio" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ralink_gpio_match); -+ -+static struct platform_driver ralink_gpio_driver = { -+ .probe = ralink_gpio_probe, -+ .driver = { -+ .name = "rt2880_gpio", -+ .owner = THIS_MODULE, -+ .of_match_table = ralink_gpio_match, -+ }, -+}; -+ -+static int __init ralink_gpio_init(void) -+{ -+ return platform_driver_register(&ralink_gpio_driver); -+} -+ -+subsys_initcall(ralink_gpio_init); diff --git a/target/linux/ramips/patches-5.10/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch b/target/linux/ramips/patches-5.10/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch deleted file mode 100644 index 8520ce32ff..0000000000 --- a/target/linux/ramips/patches-5.10/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 57fa7f2f4ef6f78ce1d30509c0d111aa3791b524 Mon Sep 17 00:00:00 2001 -From: Daniel Santos -Date: Sun, 4 Nov 2018 20:24:32 -0600 -Subject: gpio-ralink: Add support for GPIO as interrupt-controller - -Signed-off-by: Daniel Santos ---- - Documentation/devicetree/bindings/gpio/gpio-ralink.txt | 6 ++++++ - drivers/gpio/gpio-ralink.c | 2 +- - 2 files changed, 7 insertions(+), 1 deletion(-) - ---- a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt -+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt -@@ -17,6 +17,9 @@ Required properties: - - Optional properties: - - ralink,gpio-base : Specify the GPIO chips base number -+- interrupt-controller : marks this as an interrupt controller -+- #interrupt-cells : a standard two-cell interrupt flag, see -+ interrupt-controller/interrupts.txt - - Example: - -@@ -28,6 +31,9 @@ Example: - - reg = <0x600 0x34>; - -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ - interrupt-parent = <&intc>; - interrupts = <6>; - ---- a/drivers/gpio/gpio-ralink.c -+++ b/drivers/gpio/gpio-ralink.c -@@ -220,7 +220,7 @@ static int gpio_map(struct irq_domain *d - } - - static const struct irq_domain_ops irq_domain_ops = { -- .xlate = irq_domain_xlate_onecell, -+ .xlate = irq_domain_xlate_twocell, - .map = gpio_map, - }; - diff --git a/target/linux/ramips/patches-5.10/804-staging-mt7621-pinctrl-use-ngpios-not-num-gpios.patch b/target/linux/ramips/patches-5.10/804-staging-mt7621-pinctrl-use-ngpios-not-num-gpios.patch deleted file mode 100644 index a15bf62b0b..0000000000 --- a/target/linux/ramips/patches-5.10/804-staging-mt7621-pinctrl-use-ngpios-not-num-gpios.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c -+++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c -@@ -356,7 +356,7 @@ static int rt2880_pinmux_probe(struct pl - if (!of_device_is_available(np)) - continue; - -- ngpio = of_get_property(np, "ralink,num-gpios", NULL); -+ ngpio = of_get_property(np, "ngpios", NULL); - gpiobase = of_get_property(np, "ralink,gpio-base", NULL); - if (!ngpio || !gpiobase) { - dev_err(&pdev->dev, "failed to load chip info\n"); diff --git a/target/linux/ramips/patches-5.10/805-pinctrl-AW9523.patch b/target/linux/ramips/patches-5.10/805-pinctrl-AW9523.patch deleted file mode 100644 index e80d0c9967..0000000000 --- a/target/linux/ramips/patches-5.10/805-pinctrl-AW9523.patch +++ /dev/null @@ -1,72 +0,0 @@ -From: AngeloGioacchino Del Regno - -To: linus.walleij@linaro.org -Cc: linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, - marijn.suijten@somainline.org, martin.botka@somainline.org, - phone-devel@vger.kernel.org, linux-gpio@vger.kernel.org, - devicetree@vger.kernel.org, robh+dt@kernel.org, - AngeloGioacchino Del Regno - -Subject: [PATCH v5 1/2] pinctrl: Add driver for Awinic AW9523/B I2C GPIO - Expander -Date: Mon, 25 Jan 2021 19:22:18 +0100 - -The Awinic AW9523(B) is a multi-function I2C gpio expander in a -TQFN-24L package, featuring PWM (max 37mA per pin, or total max -power 3.2Watts) for LED driving capability. - -It has two ports with 8 pins per port (for a total of 16 pins), -configurable as either PWM with 1/256 stepping or GPIO input/output, -1.8V logic input; each GPIO can be configured as input or output -independently from each other. - -This IC also has an internal interrupt controller, which is capable -of generating an interrupt for each GPIO, depending on the -configuration, and will raise an interrupt on the INTN pin to -advertise this to an external interrupt controller. - -Signed-off-by: AngeloGioacchino Del Regno ---- - drivers/pinctrl/Kconfig | 17 + - drivers/pinctrl/Makefile | 1 + - drivers/pinctrl/pinctrl-aw9523.c | 1122 ++++++++++++++++++++++++++++++ - 3 files changed, 1140 insertions(+) - create mode 100644 drivers/pinctrl/pinctrl-aw9523.c - ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -110,6 +110,24 @@ config PINCTRL_AMD - Requires ACPI/FDT device enumeration code to set up a platform - device. - -+config PINCTRL_AW9523 -+ bool "Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver" -+ depends on OF && I2C -+ select PINMUX -+ select PINCONF -+ select GENERIC_PINCONF -+ select GPIOLIB -+ select GPIOLIB_IRQCHIP -+ select REGMAP -+ select REGMAP_I2C -+ help -+ The Awinic AW9523/AW9523B is a multi-function I2C GPIO -+ expander with PWM functionality. This driver bundles a -+ pinctrl driver to select the function muxing and a GPIO -+ driver to handle GPIO, when the GPIO function is selected. -+ -+ Say yes to enable pinctrl and GPIO support for the AW9523(B). -+ - config PINCTRL_BM1880 - bool "Bitmain BM1880 Pinctrl driver" - depends on OF && (ARCH_BITMAIN || COMPILE_TEST) ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_AXP209) += pinctrl- - obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o - obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o - obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o -+obj-$(CONFIG_PINCTRL_AW9523) += pinctrl-aw9523.o - obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o - obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o - obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o diff --git a/target/linux/ramips/patches-5.10/810-uvc-add-iPassion-iP2970-support.patch b/target/linux/ramips/patches-5.10/810-uvc-add-iPassion-iP2970-support.patch deleted file mode 100644 index 86f73c6623..0000000000 --- a/target/linux/ramips/patches-5.10/810-uvc-add-iPassion-iP2970-support.patch +++ /dev/null @@ -1,245 +0,0 @@ -From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 19 Sep 2013 01:50:59 +0200 -Subject: [PATCH 31/53] uvc: add iPassion iP2970 support - -Signed-off-by: John Crispin ---- - drivers/media/usb/uvc/uvc_driver.c | 12 +++ - drivers/media/usb/uvc/uvc_status.c | 2 + - drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++ - drivers/media/usb/uvc/uvcvideo.h | 5 +- - 4 files changed, 165 insertions(+), 1 deletion(-) - ---- a/drivers/media/usb/uvc/uvc_driver.c -+++ b/drivers/media/usb/uvc/uvc_driver.c -@@ -3012,6 +3012,18 @@ static const struct usb_device_id uvc_id - .bInterfaceSubClass = 1, - .bInterfaceProtocol = 0, - .driver_info = UVC_INFO_META(V4L2_META_FMT_D4XX) }, -+ /* iPassion iP2970 */ -+ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE -+ | USB_DEVICE_ID_MATCH_INT_INFO, -+ .idVendor = 0x1B3B, -+ .idProduct = 0x2970, -+ .bInterfaceClass = USB_CLASS_VIDEO, -+ .bInterfaceSubClass = 1, -+ .bInterfaceProtocol = 0, -+ .driver_info = UVC_QUIRK_PROBE_MINMAX -+ | UVC_QUIRK_STREAM_NO_FID -+ | UVC_QUIRK_MOTION -+ | UVC_QUIRK_SINGLE_ISO }, - /* Generic USB Video Class */ - { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) }, - { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) }, ---- a/drivers/media/usb/uvc/uvc_status.c -+++ b/drivers/media/usb/uvc/uvc_status.c -@@ -225,6 +225,7 @@ static void uvc_status_complete(struct u - if (uvc_event_control(urb, status, len)) - /* The URB will be resubmitted in work context. */ - return; -+ dev->motion = 1; - break; - } - -@@ -273,6 +274,7 @@ int uvc_status_init(struct uvc_device *d - } - - pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress); -+ dev->motion = 0; - - /* For high-speed interrupt endpoints, the bInterval value is used as - * an exponent of two. Some developers forgot about it. ---- a/drivers/media/usb/uvc/uvc_video.c -+++ b/drivers/media/usb/uvc/uvc_video.c -@@ -16,6 +16,11 @@ - #include - #include - #include -+#include -+#include -+#include -+#include -+#include - - #include - -@@ -1188,9 +1193,149 @@ static void uvc_video_decode_data(struct - uvc_urb->async_operations++; - } - -+struct bh_priv { -+ unsigned long seen; -+}; -+ -+struct bh_event { -+ const char *name; -+ struct sk_buff *skb; -+ struct work_struct work; -+}; -+ -+#define BH_ERR(fmt, args...) printk(KERN_ERR "%s: " fmt, "webcam", ##args ) -+#define BH_DBG(fmt, args...) do {} while (0) -+#define BH_SKB_SIZE 2048 -+ -+extern u64 uevent_next_seqnum(void); -+static int seen = 0; -+ -+static int bh_event_add_var(struct bh_event *event, int argv, -+ const char *format, ...) -+{ -+ static char buf[128]; -+ char *s; -+ va_list args; -+ int len; -+ -+ if (argv) -+ return 0; -+ -+ va_start(args, format); -+ len = vsnprintf(buf, sizeof(buf), format, args); -+ va_end(args); -+ -+ if (len >= sizeof(buf)) { -+ BH_ERR("buffer size too small\n"); -+ WARN_ON(1); -+ return -ENOMEM; -+ } -+ -+ s = skb_put(event->skb, len + 1); -+ strcpy(s, buf); -+ -+ BH_DBG("added variable '%s'\n", s); -+ -+ return 0; -+} -+ -+static int motion_hotplug_fill_event(struct bh_event *event) -+{ -+ int s = jiffies; -+ int ret; -+ -+ if (!seen) -+ seen = jiffies; -+ -+ ret = bh_event_add_var(event, 0, "HOME=%s", "/"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "PATH=%s", -+ "/sbin:/bin:/usr/sbin:/usr/bin"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "SUBSYSTEM=usb"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "ACTION=motion"); -+ if (ret) -+ return ret; -+ -+ ret = bh_event_add_var(event, 0, "SEEN=%d", s - seen); -+ if (ret) -+ return ret; -+ seen = s; -+ -+ ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum()); -+ -+ return ret; -+} -+ -+static void motion_hotplug_work(struct work_struct *work) -+{ -+ struct bh_event *event = container_of(work, struct bh_event, work); -+ int ret = 0; -+ -+ event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL); -+ if (!event->skb) -+ goto out_free_event; -+ -+ ret = bh_event_add_var(event, 0, "%s@", "add"); -+ if (ret) -+ goto out_free_skb; -+ -+ ret = motion_hotplug_fill_event(event); -+ if (ret) -+ goto out_free_skb; -+ -+ NETLINK_CB(event->skb).dst_group = 1; -+ broadcast_uevent(event->skb, 0, 1, GFP_KERNEL); -+ -+out_free_skb: -+ if (ret) { -+ BH_ERR("work error %d\n", ret); -+ kfree_skb(event->skb); -+ } -+out_free_event: -+ kfree(event); -+} -+ -+static int motion_hotplug_create_event(void) -+{ -+ struct bh_event *event; -+ -+ event = kzalloc(sizeof(*event), GFP_KERNEL); -+ if (!event) -+ return -ENOMEM; -+ -+ event->name = "motion"; -+ -+ INIT_WORK(&event->work, (void *)(void *)motion_hotplug_work); -+ schedule_work(&event->work); -+ -+ return 0; -+} -+ -+#define MOTION_FLAG_OFFSET 4 - static void uvc_video_decode_end(struct uvc_streaming *stream, - struct uvc_buffer *buf, const u8 *data, int len) - { -+ if ((stream->dev->quirks & UVC_QUIRK_MOTION) && -+ (data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) { -+ u8 *mem; -+ buf->state = UVC_BUF_STATE_READY; -+ mem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET); -+ if ( stream->dev->motion ) { -+ stream->dev->motion = 0; -+ motion_hotplug_create_event(); -+ } else { -+ *mem &= 0x7f; -+ } -+ } -+ - /* Mark the buffer as done if the EOF marker is set. */ - if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) { - uvc_trace(UVC_TRACE_FRAME, "Frame complete (EOF found).\n"); -@@ -1749,6 +1894,8 @@ static int uvc_init_video_isoc(struct uv - if (npackets == 0) - return -ENOMEM; - -+ if (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO) -+ npackets = 1; - size = npackets * psize; - - for_each_uvc_urb(uvc_urb, stream) { ---- a/drivers/media/usb/uvc/uvcvideo.h -+++ b/drivers/media/usb/uvc/uvcvideo.h -@@ -204,7 +204,8 @@ - #define UVC_QUIRK_FORCE_Y8 0x00000800 - #define UVC_QUIRK_FORCE_BPP 0x00001000 - #define UVC_QUIRK_WAKE_AUTOSUSPEND 0x00002000 -- -+#define UVC_QUIRK_MOTION 0x00004000 -+#define UVC_QUIRK_SINGLE_ISO 0x00008000 - /* Format flags */ - #define UVC_FMT_FLAG_COMPRESSED 0x00000001 - #define UVC_FMT_FLAG_STREAM 0x00000002 -@@ -674,6 +675,7 @@ struct uvc_device { - u8 *status; - struct input_dev *input; - char input_phys[64]; -+ int motion; - - struct uvc_ctrl_work { - struct work_struct work; diff --git a/target/linux/ramips/patches-5.10/820-DT-Add-documentation-for-spi-rt2880.patch b/target/linux/ramips/patches-5.10/820-DT-Add-documentation-for-spi-rt2880.patch deleted file mode 100644 index e2643e3f25..0000000000 --- a/target/linux/ramips/patches-5.10/820-DT-Add-documentation-for-spi-rt2880.patch +++ /dev/null @@ -1,44 +0,0 @@ -From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 9 Aug 2013 20:12:59 +0200 -Subject: [PATCH 41/53] DT: Add documentation for spi-rt2880 - -Describe the SPI master found on the MIPS based Ralink RT2880 SoC. - -Signed-off-by: John Crispin ---- - .../devicetree/bindings/spi/spi-rt2880.txt | 28 ++++++++++++++++++++ - 1 file changed, 28 insertions(+) - create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt - ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt -@@ -0,0 +1,28 @@ -+Ralink SoC RT2880 SPI master controller. -+ -+This SPI controller is found on most wireless SoCs made by ralink. -+ -+Required properties: -+- compatible : "ralink,rt2880-spi" -+- reg : The register base for the controller. -+- #address-cells : <1>, as required by generic SPI binding. -+- #size-cells : <0>, also as required by generic SPI binding. -+ -+Child nodes as per the generic SPI binding. -+ -+Example: -+ -+ spi@b00 { -+ compatible = "ralink,rt2880-spi"; -+ reg = <0xb00 0x100>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ m25p80@0 { -+ compatible = "m25p80"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+ }; -+ diff --git a/target/linux/ramips/patches-5.10/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-5.10/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch deleted file mode 100644 index 56c8f58ce7..0000000000 --- a/target/linux/ramips/patches-5.10/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch +++ /dev/null @@ -1,574 +0,0 @@ -From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 11:15:12 +0100 -Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver - -Add the driver needed to make SPI work on Ralink SoC. - -Signed-off-by: Gabor Juhos -Acked-by: John Crispin ---- - drivers/spi/Kconfig | 6 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-rt2880.c | 530 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 537 insertions(+) - create mode 100644 drivers/spi/spi-rt2880.c - ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -688,6 +688,12 @@ config SPI_QCOM_GENI - This driver can also be built as a module. If so, the module - will be called spi-geni-qcom. - -+config SPI_RT2880 -+ tristate "Ralink RT288x SPI Controller" -+ depends on RALINK -+ help -+ This selects a driver for the Ralink RT288x/RT305x SPI Controller. -+ - config SPI_S3C24XX - tristate "Samsung S3C24XX series SPI" - depends on ARCH_S3C24XX ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -96,6 +96,7 @@ obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockc - obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o - obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o - obj-$(CONFIG_SPI_RSPI) += spi-rspi.o -+obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o - obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o - spi-s3c24xx-hw-y := spi-s3c24xx.o - obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o ---- /dev/null -+++ b/drivers/spi/spi-rt2880.c -@@ -0,0 +1,530 @@ -+/* -+ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver -+ * -+ * Copyright (C) 2011 Sergiy -+ * Copyright (C) 2011-2013 Gabor Juhos -+ * -+ * Some parts are based on spi-orion.c: -+ * Author: Shadi Ammouri -+ * Copyright (C) 2007-2008 Marvell Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRIVER_NAME "spi-rt2880" -+ -+#define RAMIPS_SPI_STAT 0x00 -+#define RAMIPS_SPI_CFG 0x10 -+#define RAMIPS_SPI_CTL 0x14 -+#define RAMIPS_SPI_DATA 0x20 -+#define RAMIPS_SPI_ADDR 0x24 -+#define RAMIPS_SPI_BS 0x28 -+#define RAMIPS_SPI_USER 0x2C -+#define RAMIPS_SPI_TXFIFO 0x30 -+#define RAMIPS_SPI_RXFIFO 0x34 -+#define RAMIPS_SPI_FIFO_STAT 0x38 -+#define RAMIPS_SPI_MODE 0x3C -+#define RAMIPS_SPI_DEV_OFFSET 0x40 -+#define RAMIPS_SPI_DMA 0x80 -+#define RAMIPS_SPI_DMASTAT 0x84 -+#define RAMIPS_SPI_ARBITER 0xF0 -+ -+/* SPISTAT register bit field */ -+#define SPISTAT_BUSY BIT(0) -+ -+/* SPICFG register bit field */ -+#define SPICFG_ADDRMODE BIT(12) -+#define SPICFG_RXENVDIS BIT(11) -+#define SPICFG_RXCAP BIT(10) -+#define SPICFG_SPIENMODE BIT(9) -+#define SPICFG_MSBFIRST BIT(8) -+#define SPICFG_SPICLKPOL BIT(6) -+#define SPICFG_RXCLKEDGE_FALLING BIT(5) -+#define SPICFG_TXCLKEDGE_FALLING BIT(4) -+#define SPICFG_HIZSPI BIT(3) -+#define SPICFG_SPICLK_PRESCALE_MASK 0x7 -+#define SPICFG_SPICLK_DIV2 0 -+#define SPICFG_SPICLK_DIV4 1 -+#define SPICFG_SPICLK_DIV8 2 -+#define SPICFG_SPICLK_DIV16 3 -+#define SPICFG_SPICLK_DIV32 4 -+#define SPICFG_SPICLK_DIV64 5 -+#define SPICFG_SPICLK_DIV128 6 -+#define SPICFG_SPICLK_DISABLE 7 -+ -+/* SPICTL register bit field */ -+#define SPICTL_START BIT(4) -+#define SPICTL_HIZSDO BIT(3) -+#define SPICTL_STARTWR BIT(2) -+#define SPICTL_STARTRD BIT(1) -+#define SPICTL_SPIENA BIT(0) -+ -+/* SPIUSER register bit field */ -+#define SPIUSER_USERMODE BIT(21) -+#define SPIUSER_INSTR_PHASE BIT(20) -+#define SPIUSER_ADDR_PHASE_MASK 0x7 -+#define SPIUSER_ADDR_PHASE_OFFSET 17 -+#define SPIUSER_MODE_PHASE BIT(16) -+#define SPIUSER_DUMMY_PHASE_MASK 0x3 -+#define SPIUSER_DUMMY_PHASE_OFFSET 14 -+#define SPIUSER_DATA_PHASE_MASK 0x3 -+#define SPIUSER_DATA_PHASE_OFFSET 12 -+#define SPIUSER_DATA_READ (BIT(0) << SPIUSER_DATA_PHASE_OFFSET) -+#define SPIUSER_DATA_WRITE (BIT(1) << SPIUSER_DATA_PHASE_OFFSET) -+#define SPIUSER_ADDR_TYPE_OFFSET 9 -+#define SPIUSER_MODE_TYPE_OFFSET 6 -+#define SPIUSER_DUMMY_TYPE_OFFSET 3 -+#define SPIUSER_DATA_TYPE_OFFSET 0 -+#define SPIUSER_TRANSFER_MASK 0x7 -+#define SPIUSER_TRANSFER_SINGLE BIT(0) -+#define SPIUSER_TRANSFER_DUAL BIT(1) -+#define SPIUSER_TRANSFER_QUAD BIT(2) -+ -+#define SPIUSER_TRANSFER_TYPE(type) ( \ -+ (type << SPIUSER_ADDR_TYPE_OFFSET) | \ -+ (type << SPIUSER_MODE_TYPE_OFFSET) | \ -+ (type << SPIUSER_DUMMY_TYPE_OFFSET) | \ -+ (type << SPIUSER_DATA_TYPE_OFFSET) \ -+) -+ -+/* SPIFIFOSTAT register bit field */ -+#define SPIFIFOSTAT_TXEMPTY BIT(19) -+#define SPIFIFOSTAT_RXEMPTY BIT(18) -+#define SPIFIFOSTAT_TXFULL BIT(17) -+#define SPIFIFOSTAT_RXFULL BIT(16) -+#define SPIFIFOSTAT_FIFO_MASK 0xff -+#define SPIFIFOSTAT_TX_OFFSET 8 -+#define SPIFIFOSTAT_RX_OFFSET 0 -+ -+#define SPI_FIFO_DEPTH 16 -+ -+/* SPIMODE register bit field */ -+#define SPIMODE_MODE_OFFSET 24 -+#define SPIMODE_DUMMY_OFFSET 0 -+ -+/* SPIARB register bit field */ -+#define SPICTL_ARB_EN BIT(31) -+#define SPICTL_CSCTL1 BIT(16) -+#define SPI1_POR BIT(1) -+#define SPI0_POR BIT(0) -+ -+#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \ -+ SPI_CS_HIGH) -+ -+static atomic_t hw_reset_count = ATOMIC_INIT(0); -+ -+struct rt2880_spi { -+ struct spi_master *master; -+ void __iomem *base; -+ u32 speed; -+ u16 wait_loops; -+ u16 mode; -+ struct clk *clk; -+}; -+ -+static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg) -+{ -+ return ioread32(rs->base + reg); -+} -+ -+static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, -+ const u32 val) -+{ -+ iowrite32(val, rs->base + reg); -+} -+ -+static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask) -+{ -+ void __iomem *addr = rs->base + reg; -+ -+ iowrite32((ioread32(addr) | mask), addr); -+} -+ -+static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask) -+{ -+ void __iomem *addr = rs->base + reg; -+ -+ iowrite32((ioread32(addr) & ~mask), addr); -+} -+ -+static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed) -+{ -+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi); -+ u32 rate; -+ u32 prescale; -+ -+ /* -+ * the supported rates are: 2, 4, 8, ... 128 -+ * round up as we look for equal or less speed -+ */ -+ rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed); -+ rate = roundup_pow_of_two(rate); -+ -+ /* Convert the rate to SPI clock divisor value. */ -+ prescale = ilog2(rate / 2); -+ -+ /* some tolerance. double and add 100 */ -+ rs->wait_loops = (8 * HZ * loops_per_jiffy) / -+ (clk_get_rate(rs->clk) / rate); -+ rs->wait_loops = (rs->wait_loops << 1) + 100; -+ rs->speed = speed; -+ -+ dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n", -+ clk_get_rate(rs->clk) / rate, speed, rate, prescale, -+ rs->wait_loops); -+ -+ return prescale; -+} -+ -+static u32 get_arbiter_offset(struct spi_master *master) -+{ -+ u32 offset; -+ -+ offset = RAMIPS_SPI_ARBITER; -+ if (master->bus_num == 1) -+ offset -= RAMIPS_SPI_DEV_OFFSET; -+ -+ return offset; -+} -+ -+static void rt2880_spi_set_cs(struct spi_device *spi, bool enable) -+{ -+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi); -+ -+ if (enable) -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); -+ else -+ rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA); -+} -+ -+static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len) -+{ -+ int loop = rs->wait_loops * len; -+ -+ while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop) -+ cpu_relax(); -+ -+ if (loop) -+ return 0; -+ -+ return -ETIMEDOUT; -+} -+ -+static void rt2880_dump_reg(struct spi_master *master) -+{ -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ -+ dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \ -+ "data: %08x, arb: %08x\n", -+ rt2880_spi_read(rs, RAMIPS_SPI_STAT), -+ rt2880_spi_read(rs, RAMIPS_SPI_CFG), -+ rt2880_spi_read(rs, RAMIPS_SPI_CTL), -+ rt2880_spi_read(rs, RAMIPS_SPI_DATA), -+ rt2880_spi_read(rs, get_arbiter_offset(master))); -+} -+ -+static int rt2880_spi_transfer_one(struct spi_master *master, -+ struct spi_device *spi, struct spi_transfer *xfer) -+{ -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ unsigned len; -+ const u8 *tx = xfer->tx_buf; -+ u8 *rx = xfer->rx_buf; -+ int err = 0; -+ -+ /* change clock speed */ -+ if (unlikely(rs->speed != xfer->speed_hz)) { -+ u32 reg; -+ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG); -+ reg &= ~SPICFG_SPICLK_PRESCALE_MASK; -+ reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz); -+ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg); -+ } -+ -+ if (tx) { -+ len = xfer->len; -+ while (len-- > 0) { -+ rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++); -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR); -+ err = rt2880_spi_wait_ready(rs, 1); -+ if (err) { -+ dev_err(&spi->dev, "TX failed, err=%d\n", err); -+ goto out; -+ } -+ } -+ } -+ -+ if (rx) { -+ len = xfer->len; -+ while (len-- > 0) { -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD); -+ err = rt2880_spi_wait_ready(rs, 1); -+ if (err) { -+ dev_err(&spi->dev, "RX failed, err=%d\n", err); -+ goto out; -+ } -+ *rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA); -+ } -+ } -+ -+out: -+ return err; -+} -+ -+/* copy from spi.c */ -+static void spi_set_cs(struct spi_device *spi, bool enable) -+{ -+ if (spi->mode & SPI_CS_HIGH) -+ enable = !enable; -+ -+ if (spi->cs_gpio >= 0) -+ gpio_set_value(spi->cs_gpio, !enable); -+ else if (spi->master->set_cs) -+ spi->master->set_cs(spi, !enable); -+} -+ -+static int rt2880_spi_setup(struct spi_device *spi) -+{ -+ struct spi_master *master = spi->master; -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ u32 reg, old_reg, arbit_off; -+ -+ if ((spi->max_speed_hz > master->max_speed_hz) || -+ (spi->max_speed_hz < master->min_speed_hz)) { -+ dev_err(&spi->dev, "invalide requested speed %d Hz\n", -+ spi->max_speed_hz); -+ return -EINVAL; -+ } -+ -+ if (!(master->bits_per_word_mask & -+ BIT(spi->bits_per_word - 1))) { -+ dev_err(&spi->dev, "invalide bits_per_word %d\n", -+ spi->bits_per_word); -+ return -EINVAL; -+ } -+ -+ /* the hardware seems can't work on mode0 force it to mode3 */ -+ if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) { -+ dev_warn(&spi->dev, "force spi mode3\n"); -+ spi->mode |= SPI_MODE_3; -+ } -+ -+ /* chip polarity */ -+ arbit_off = get_arbiter_offset(master); -+ reg = old_reg = rt2880_spi_read(rs, arbit_off); -+ if (spi->mode & SPI_CS_HIGH) { -+ switch (master->bus_num) { -+ case 1: -+ reg |= SPI1_POR; -+ break; -+ default: -+ reg |= SPI0_POR; -+ break; -+ } -+ } else { -+ switch (master->bus_num) { -+ case 1: -+ reg &= ~SPI1_POR; -+ break; -+ default: -+ reg &= ~SPI0_POR; -+ break; -+ } -+ } -+ -+ /* enable spi1 */ -+ if (master->bus_num == 1) -+ reg |= SPICTL_ARB_EN; -+ -+ if (reg != old_reg) -+ rt2880_spi_write(rs, arbit_off, reg); -+ -+ /* deselected the spi device */ -+ spi_set_cs(spi, false); -+ -+ rt2880_dump_reg(master); -+ -+ return 0; -+} -+ -+static int rt2880_spi_prepare_message(struct spi_master *master, -+ struct spi_message *msg) -+{ -+ struct rt2880_spi *rs = spi_master_get_devdata(master); -+ struct spi_device *spi = msg->spi; -+ u32 reg; -+ -+ if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz)) -+ return 0; -+ -+#if 0 -+ /* set spido to tri-state */ -+ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO); -+#endif -+ -+ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG); -+ -+ reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL | -+ SPICFG_RXCLKEDGE_FALLING | -+ SPICFG_TXCLKEDGE_FALLING | -+ SPICFG_SPICLK_PRESCALE_MASK); -+ -+ /* MSB */ -+ if (!(spi->mode & SPI_LSB_FIRST)) -+ reg |= SPICFG_MSBFIRST; -+ -+ /* spi mode */ -+ switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { -+ case SPI_MODE_0: -+ reg |= SPICFG_TXCLKEDGE_FALLING; -+ break; -+ case SPI_MODE_1: -+ reg |= SPICFG_RXCLKEDGE_FALLING; -+ break; -+ case SPI_MODE_2: -+ reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING; -+ break; -+ case SPI_MODE_3: -+ reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING; -+ break; -+ } -+ rs->mode = spi->mode; -+ -+#if 0 -+ /* set spiclk and spiena to tri-state */ -+ reg |= SPICFG_HIZSPI; -+#endif -+ -+ /* clock divide */ -+ reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz); -+ -+ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg); -+ -+ return 0; -+} -+ -+static int rt2880_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct rt2880_spi *rs; -+ void __iomem *base; -+ struct resource *r; -+ struct clk *clk; -+ int ret; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, r); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(clk)) { -+ dev_err(&pdev->dev, "unable to get SYS clock\n"); -+ return PTR_ERR(clk); -+ } -+ -+ ret = clk_prepare_enable(clk); -+ if (ret) -+ goto err_clk; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*rs)); -+ if (master == NULL) { -+ dev_dbg(&pdev->dev, "master allocation failed\n"); -+ ret = -ENOMEM; -+ goto err_clk; -+ } -+ -+ master->dev.of_node = pdev->dev.of_node; -+ master->mode_bits = RT2880_SPI_MODE_BITS; -+ master->bits_per_word_mask = SPI_BPW_MASK(8); -+ master->min_speed_hz = clk_get_rate(clk) / 128; -+ master->max_speed_hz = clk_get_rate(clk) / 2; -+ master->flags = SPI_MASTER_HALF_DUPLEX; -+ master->setup = rt2880_spi_setup; -+ master->prepare_message = rt2880_spi_prepare_message; -+ master->set_cs = rt2880_spi_set_cs; -+ master->transfer_one = rt2880_spi_transfer_one, -+ -+ dev_set_drvdata(&pdev->dev, master); -+ -+ rs = spi_master_get_devdata(master); -+ rs->master = master; -+ rs->base = base; -+ rs->clk = clk; -+ -+ if (atomic_inc_return(&hw_reset_count) == 1) -+ device_reset(&pdev->dev); -+ -+ ret = devm_spi_register_master(&pdev->dev, master); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "devm_spi_register_master error.\n"); -+ goto err_master; -+ } -+ -+ return ret; -+ -+err_master: -+ spi_master_put(master); -+ kfree(master); -+err_clk: -+ clk_disable_unprepare(clk); -+ -+ return ret; -+} -+ -+static int rt2880_spi_remove(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct rt2880_spi *rs; -+ -+ master = dev_get_drvdata(&pdev->dev); -+ rs = spi_master_get_devdata(master); -+ -+ clk_disable_unprepare(rs->clk); -+ atomic_dec(&hw_reset_count); -+ -+ return 0; -+} -+ -+MODULE_ALIAS("platform:" DRIVER_NAME); -+ -+static const struct of_device_id rt2880_spi_match[] = { -+ { .compatible = "ralink,rt2880-spi" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, rt2880_spi_match); -+ -+static struct platform_driver rt2880_spi_driver = { -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = rt2880_spi_match, -+ }, -+ .probe = rt2880_spi_probe, -+ .remove = rt2880_spi_remove, -+}; -+ -+module_platform_driver(rt2880_spi_driver); -+ -+MODULE_DESCRIPTION("Ralink SPI driver"); -+MODULE_AUTHOR("Sergiy "); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/ramips/patches-5.10/825-i2c-MIPS-adds-ralink-I2C-driver.patch b/target/linux/ramips/patches-5.10/825-i2c-MIPS-adds-ralink-I2C-driver.patch deleted file mode 100644 index 7fdbceac09..0000000000 --- a/target/linux/ramips/patches-5.10/825-i2c-MIPS-adds-ralink-I2C-driver.patch +++ /dev/null @@ -1,507 +0,0 @@ -From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:52:56 +0100 -Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver - -Signed-off-by: John Crispin ---- - .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++ - drivers/i2c/busses/Kconfig | 4 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++ - 4 files changed, 359 insertions(+) - create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt - create mode 100644 drivers/i2c/busses/i2c-ralink.c - ---- /dev/null -+++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt -@@ -0,0 +1,27 @@ -+I2C for Ralink platforms -+ -+Required properties : -+- compatible : Must be "link,rt3052-i2c" -+- reg: physical base address of the controller and length of memory mapped -+ region. -+- #address-cells = <1>; -+- #size-cells = <0>; -+ -+Optional properties: -+- Child nodes conforming to i2c bus binding -+ -+Example : -+ -+palmbus@10000000 { -+ i2c@900 { -+ compatible = "link,rt3052-i2c"; -+ reg = <0x900 0x100>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hwmon@4b { -+ compatible = "national,lm92"; -+ reg = <0x4b>; -+ }; -+ }; -+}; ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -954,6 +954,11 @@ config I2C_RK3X - This driver can also be built as a module. If so, the module will - be called i2c-rk3x. - -+config I2C_RALINK -+ tristate "Ralink I2C Controller" -+ depends on RALINK && !SOC_MT7621 -+ select OF_I2C -+ - config HAVE_S3C2410_I2C - bool - help ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -90,6 +90,7 @@ obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o - obj-$(CONFIG_I2C_PNX) += i2c-pnx.o - obj-$(CONFIG_I2C_PXA) += i2c-pxa.o - obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o -+obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o - obj-$(CONFIG_I2C_QCOM_CCI) += i2c-qcom-cci.o - obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o - obj-$(CONFIG_I2C_QUP) += i2c-qup.o ---- /dev/null -+++ b/drivers/i2c/busses/i2c-ralink.c -@@ -0,0 +1,435 @@ -+/* -+ * drivers/i2c/busses/i2c-ralink.c -+ * -+ * Copyright (C) 2013 Steven Liu -+ * Copyright (C) 2016 Michael Lee -+ * -+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus. -+ * (C) 2014 Sittisak -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define REG_CONFIG_REG 0x00 -+#define REG_CLKDIV_REG 0x04 -+#define REG_DEVADDR_REG 0x08 -+#define REG_ADDR_REG 0x0C -+#define REG_DATAOUT_REG 0x10 -+#define REG_DATAIN_REG 0x14 -+#define REG_STATUS_REG 0x18 -+#define REG_STARTXFR_REG 0x1C -+#define REG_BYTECNT_REG 0x20 -+ -+/* REG_CONFIG_REG */ -+#define I2C_ADDRLEN_OFFSET 5 -+#define I2C_DEVADLEN_OFFSET 2 -+#define I2C_ADDRLEN_MASK 0x3 -+#define I2C_ADDR_DIS BIT(1) -+#define I2C_DEVADDR_DIS BIT(0) -+#define I2C_ADDRLEN_8 (7 << I2C_ADDRLEN_OFFSET) -+#define I2C_DEVADLEN_7 (6 << I2C_DEVADLEN_OFFSET) -+#define I2C_CONF_DEFAULT (I2C_ADDRLEN_8 | I2C_DEVADLEN_7) -+ -+/* REG_CLKDIV_REG */ -+#define I2C_CLKDIV_MASK 0xffff -+ -+/* REG_DEVADDR_REG */ -+#define I2C_DEVADDR_MASK 0x7f -+ -+/* REG_ADDR_REG */ -+#define I2C_ADDR_MASK 0xff -+ -+/* REG_STATUS_REG */ -+#define I2C_STARTERR BIT(4) -+#define I2C_ACKERR BIT(3) -+#define I2C_DATARDY BIT(2) -+#define I2C_SDOEMPTY BIT(1) -+#define I2C_BUSY BIT(0) -+ -+/* REG_STARTXFR_REG */ -+#define NOSTOP_CMD BIT(2) -+#define NODATA_CMD BIT(1) -+#define READ_CMD BIT(0) -+ -+/* REG_BYTECNT_REG */ -+#define BYTECNT_MAX 64 -+#define SET_BYTECNT(x) (x - 1) -+ -+/* timeout waiting for I2C devices to respond (clock streching) */ -+#define TIMEOUT_MS 1000 -+#define DELAY_INTERVAL_US 100 -+ -+struct rt_i2c { -+ void __iomem *base; -+ struct clk *clk; -+ struct device *dev; -+ struct i2c_adapter adap; -+ u32 cur_clk; -+ u32 clk_div; -+ u32 flags; -+}; -+ -+static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg) -+{ -+ iowrite32(val, i2c->base + reg); -+} -+ -+static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg) -+{ -+ return ioread32(i2c->base + reg); -+} -+ -+static int poll_down_timeout(void __iomem *addr, u32 mask) -+{ -+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); -+ -+ do { -+ if (!(readl_relaxed(addr) & mask)) -+ return 0; -+ -+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); -+ } while (time_before(jiffies, timeout)); -+ -+ return (readl_relaxed(addr) & mask) ? -EAGAIN : 0; -+} -+ -+static int rt_i2c_wait_idle(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY); -+ if (ret < 0) -+ dev_dbg(i2c->dev, "idle err(%d)\n", ret); -+ -+ return ret; -+} -+ -+static int poll_up_timeout(void __iomem *addr, u32 mask) -+{ -+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS); -+ u32 status; -+ -+ do { -+ status = readl_relaxed(addr); -+ -+ /* check error status */ -+ if (status & I2C_STARTERR) -+ return -EAGAIN; -+ else if (status & I2C_ACKERR) -+ return -ENXIO; -+ else if (status & mask) -+ return 0; -+ -+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50); -+ } while (time_before(jiffies, timeout)); -+ -+ return -ETIMEDOUT; -+} -+ -+static int rt_i2c_wait_rx_done(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY); -+ if (ret < 0) -+ dev_dbg(i2c->dev, "rx err(%d)\n", ret); -+ -+ return ret; -+} -+ -+static int rt_i2c_wait_tx_done(struct rt_i2c *i2c) -+{ -+ int ret; -+ -+ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY); -+ if (ret < 0) -+ dev_dbg(i2c->dev, "tx err(%d)\n", ret); -+ -+ return ret; -+} -+ -+static void rt_i2c_reset(struct rt_i2c *i2c) -+{ -+ device_reset(i2c->adap.dev.parent); -+ barrier(); -+ rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG); -+} -+ -+static void rt_i2c_dump_reg(struct rt_i2c *i2c) -+{ -+ dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \ -+ "addr %08x, dataout %08x, datain %08x, " \ -+ "status %08x, startxfr %08x, bytecnt %08x\n", -+ rt_i2c_r32(i2c, REG_CONFIG_REG), -+ rt_i2c_r32(i2c, REG_CLKDIV_REG), -+ rt_i2c_r32(i2c, REG_DEVADDR_REG), -+ rt_i2c_r32(i2c, REG_ADDR_REG), -+ rt_i2c_r32(i2c, REG_DATAOUT_REG), -+ rt_i2c_r32(i2c, REG_DATAIN_REG), -+ rt_i2c_r32(i2c, REG_STATUS_REG), -+ rt_i2c_r32(i2c, REG_STARTXFR_REG), -+ rt_i2c_r32(i2c, REG_BYTECNT_REG)); -+} -+ -+static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, -+ int num) -+{ -+ struct rt_i2c *i2c; -+ struct i2c_msg *pmsg; -+ unsigned char addr; -+ int i, j, ret; -+ u32 cmd; -+ -+ i2c = i2c_get_adapdata(adap); -+ -+ for (i = 0; i < num; i++) { -+ pmsg = &msgs[i]; -+ if (i == (num - 1)) -+ cmd = 0; -+ else -+ cmd = NOSTOP_CMD; -+ -+ dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n", -+ pmsg->addr, pmsg->len, pmsg->flags, -+ (cmd == 0)? 1 : 0); -+ -+ /* wait hardware idle */ -+ if ((ret = rt_i2c_wait_idle(i2c))) -+ goto err_timeout; -+ -+ if (pmsg->flags & I2C_M_TEN) { -+ rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG); -+ /* 10 bits address */ -+ addr = 0x78 | ((pmsg->addr >> 8) & 0x03); -+ rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK, -+ REG_DEVADDR_REG); -+ rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK, -+ REG_ADDR_REG); -+ } else { -+ rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS, -+ REG_CONFIG_REG); -+ /* 7 bits address */ -+ rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK, -+ REG_DEVADDR_REG); -+ } -+ -+ /* buffer length */ -+ if (pmsg->len == 0) -+ cmd |= NODATA_CMD; -+ else -+ rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len), -+ REG_BYTECNT_REG); -+ -+ j = 0; -+ if (pmsg->flags & I2C_M_RD) { -+ cmd |= READ_CMD; -+ /* start transfer */ -+ barrier(); -+ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG); -+ do { -+ /* wait */ -+ if ((ret = rt_i2c_wait_rx_done(i2c))) -+ goto err_timeout; -+ /* read data */ -+ if (pmsg->len) -+ pmsg->buf[j] = rt_i2c_r32(i2c, -+ REG_DATAIN_REG); -+ j++; -+ } while (j < pmsg->len); -+ } else { -+ do { -+ /* write data */ -+ if (pmsg->len) -+ rt_i2c_w32(i2c, pmsg->buf[j], -+ REG_DATAOUT_REG); -+ /* start transfer */ -+ if (j == 0) { -+ barrier(); -+ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG); -+ } -+ /* wait */ -+ if ((ret = rt_i2c_wait_tx_done(i2c))) -+ goto err_timeout; -+ j++; -+ } while (j < pmsg->len); -+ } -+ } -+ /* the return value is number of executed messages */ -+ ret = i; -+ -+ return ret; -+ -+err_timeout: -+ rt_i2c_dump_reg(i2c); -+ rt_i2c_reset(i2c); -+ return ret; -+} -+ -+static u32 rt_i2c_func(struct i2c_adapter *a) -+{ -+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -+} -+ -+static const struct i2c_algorithm rt_i2c_algo = { -+ .master_xfer = rt_i2c_master_xfer, -+ .functionality = rt_i2c_func, -+}; -+ -+static const struct of_device_id i2c_rt_dt_ids[] = { -+ { .compatible = "ralink,rt2880-i2c" }, -+ { /* sentinel */ } -+}; -+ -+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids); -+ -+static struct i2c_adapter_quirks rt_i2c_quirks = { -+ .max_write_len = BYTECNT_MAX, -+ .max_read_len = BYTECNT_MAX, -+}; -+ -+static int rt_i2c_init(struct rt_i2c *i2c) -+{ -+ u32 reg; -+ -+ /* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */ -+ i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) / -+ (2 * i2c->cur_clk); -+ if (i2c->clk_div < 8) -+ i2c->clk_div = 8; -+ if (i2c->clk_div > I2C_CLKDIV_MASK) -+ i2c->clk_div = I2C_CLKDIV_MASK; -+ -+ /* check support combinde/repeated start message */ -+ rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG); -+ reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD; -+ -+ rt_i2c_reset(i2c); -+ -+ return reg; -+} -+ -+static int rt_i2c_probe(struct platform_device *pdev) -+{ -+ struct resource *res; -+ struct rt_i2c *i2c; -+ struct i2c_adapter *adap; -+ const struct of_device_id *match; -+ int ret, restart; -+ -+ match = of_match_device(i2c_rt_dt_ids, &pdev->dev); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "no memory resource found\n"); -+ return -ENODEV; -+ } -+ -+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL); -+ if (!i2c) { -+ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n"); -+ return -ENOMEM; -+ } -+ -+ i2c->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(i2c->base)) -+ return PTR_ERR(i2c->base); -+ -+ i2c->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(i2c->clk)) { -+ dev_err(&pdev->dev, "no clock defined\n"); -+ return -ENODEV; -+ } -+ clk_prepare_enable(i2c->clk); -+ i2c->dev = &pdev->dev; -+ -+ if (of_property_read_u32(pdev->dev.of_node, -+ "clock-frequency", &i2c->cur_clk)) -+ i2c->cur_clk = 100000; -+ -+ adap = &i2c->adap; -+ adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; -+ adap->algo = &rt_i2c_algo; -+ adap->retries = 3; -+ adap->dev.parent = &pdev->dev; -+ i2c_set_adapdata(adap, i2c); -+ adap->dev.of_node = pdev->dev.of_node; -+ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); -+ adap->quirks = &rt_i2c_quirks; -+ -+ platform_set_drvdata(pdev, i2c); -+ -+ restart = rt_i2c_init(i2c); -+ -+ ret = i2c_add_adapter(adap); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "failed to add adapter\n"); -+ clk_disable_unprepare(i2c->clk); -+ return ret; -+ } -+ -+ dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n", -+ i2c->cur_clk/1000, restart ? "" : "not "); -+ -+ return ret; -+} -+ -+static int rt_i2c_remove(struct platform_device *pdev) -+{ -+ struct rt_i2c *i2c = platform_get_drvdata(pdev); -+ -+ i2c_del_adapter(&i2c->adap); -+ clk_disable_unprepare(i2c->clk); -+ -+ return 0; -+} -+ -+static struct platform_driver rt_i2c_driver = { -+ .probe = rt_i2c_probe, -+ .remove = rt_i2c_remove, -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "i2c-ralink", -+ .of_match_table = i2c_rt_dt_ids, -+ }, -+}; -+ -+static int __init i2c_rt_init (void) -+{ -+ return platform_driver_register(&rt_i2c_driver); -+} -+subsys_initcall(i2c_rt_init); -+ -+static void __exit i2c_rt_exit (void) -+{ -+ platform_driver_unregister(&rt_i2c_driver); -+} -+module_exit(i2c_rt_exit); -+ -+MODULE_AUTHOR("Steven Liu "); -+MODULE_DESCRIPTION("Ralink I2c host driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:Ralink-I2C"); diff --git a/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch deleted file mode 100644 index 544b1d267e..0000000000 --- a/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 13 Nov 2014 19:08:40 +0100 -Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC - -Signed-off-by: John Crispin ---- - drivers/mmc/host/Kconfig | 2 + - drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/mtk-mmc/Kconfig | 16 + - drivers/mmc/host/mtk-mmc/Makefile | 42 + - drivers/mmc/host/mtk-mmc/board.h | 137 ++ - drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++ - drivers/mmc/host/mtk-mmc/dbg.h | 156 ++ - drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++ - drivers/mmc/host/mtk-mmc/sd.c | 3060 ++++++++++++++++++++++++++++++++++ - 9 files changed, 4762 insertions(+) - create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig - create mode 100644 drivers/mmc/host/mtk-mmc/Makefile - create mode 100644 drivers/mmc/host/mtk-mmc/board.h - create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c - create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h - create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h - create mode 100644 drivers/mmc/host/mtk-mmc/sd.c - ---- a/drivers/mmc/host/Kconfig -+++ b/drivers/mmc/host/Kconfig -@@ -1102,3 +1102,5 @@ config MMC_OWL - - config MMC_SDHCI_EXTERNAL_DMA - bool -+ -+source "drivers/mmc/host/mtk-mmc/Kconfig" ---- a/drivers/mmc/host/Makefile -+++ b/drivers/mmc/host/Makefile -@@ -3,6 +3,7 @@ - # Makefile for MMC/SD host controller drivers - # - -+obj-$(CONFIG_MTK_MMC) += mtk-mmc/ - obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o - armmmci-y := mmci.o - armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o diff --git a/target/linux/ramips/patches-5.10/835-asoc-add-mt7620-support.patch b/target/linux/ramips/patches-5.10/835-asoc-add-mt7620-support.patch deleted file mode 100644 index 680b678168..0000000000 --- a/target/linux/ramips/patches-5.10/835-asoc-add-mt7620-support.patch +++ /dev/null @@ -1,1029 +0,0 @@ -From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:31:47 +0100 -Subject: [PATCH 48/53] asoc: add mt7620 support - -Signed-off-by: John Crispin ---- - arch/mips/ralink/of.c | 2 + - sound/soc/Kconfig | 1 + - sound/soc/Makefile | 1 + - sound/soc/ralink/Kconfig | 15 ++ - sound/soc/ralink/Makefile | 11 + - sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++ - sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++ - 7 files changed, 699 insertions(+) - create mode 100644 sound/soc/ralink/Kconfig - create mode 100644 sound/soc/ralink/Makefile - create mode 100644 sound/soc/ralink/mt7620-i2s.c - create mode 100644 sound/soc/ralink/mt7620-wm8960.c - ---- a/sound/soc/Kconfig -+++ b/sound/soc/Kconfig -@@ -60,6 +60,7 @@ source "sound/soc/mxs/Kconfig" - source "sound/soc/pxa/Kconfig" - source "sound/soc/qcom/Kconfig" - source "sound/soc/rockchip/Kconfig" -+source "sound/soc/ralink/Kconfig" - source "sound/soc/samsung/Kconfig" - source "sound/soc/sh/Kconfig" - source "sound/soc/sirf/Kconfig" ---- a/sound/soc/Makefile -+++ b/sound/soc/Makefile -@@ -43,6 +43,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/ - obj-$(CONFIG_SND_SOC) += pxa/ - obj-$(CONFIG_SND_SOC) += qcom/ - obj-$(CONFIG_SND_SOC) += rockchip/ -+obj-$(CONFIG_SND_SOC) += ralink/ - obj-$(CONFIG_SND_SOC) += samsung/ - obj-$(CONFIG_SND_SOC) += sh/ - obj-$(CONFIG_SND_SOC) += sirf/ ---- /dev/null -+++ b/sound/soc/ralink/Kconfig -@@ -0,0 +1,8 @@ -+config SND_RALINK_SOC_I2S -+ depends on RALINK && SND_SOC && !SOC_RT288X -+ select SND_SOC_GENERIC_DMAENGINE_PCM -+ select REGMAP_MMIO -+ tristate "SoC Audio (I2S protocol) for Ralink SoC" -+ help -+ Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek -+ based boards. ---- /dev/null -+++ b/sound/soc/ralink/Makefile -@@ -0,0 +1,6 @@ -+# -+# Ralink/MediaTek Platform Support -+# -+snd-soc-ralink-i2s-objs := ralink-i2s.o -+ -+obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o ---- /dev/null -+++ b/sound/soc/ralink/ralink-i2s.c -@@ -0,0 +1,966 @@ -+/* -+ * Copyright (C) 2010, Lars-Peter Clausen -+ * Copyright (C) 2016 Michael Lee -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "ralink-i2s" -+ -+#define I2S_REG_CFG0 0x00 -+#define I2S_REG_INT_STATUS 0x04 -+#define I2S_REG_INT_EN 0x08 -+#define I2S_REG_FF_STATUS 0x0c -+#define I2S_REG_WREG 0x10 -+#define I2S_REG_RREG 0x14 -+#define I2S_REG_CFG1 0x18 -+#define I2S_REG_DIVCMP 0x20 -+#define I2S_REG_DIVINT 0x24 -+ -+/* I2S_REG_CFG0 */ -+#define I2S_REG_CFG0_EN BIT(31) -+#define I2S_REG_CFG0_DMA_EN BIT(30) -+#define I2S_REG_CFG0_BYTE_SWAP BIT(28) -+#define I2S_REG_CFG0_TX_EN BIT(24) -+#define I2S_REG_CFG0_RX_EN BIT(20) -+#define I2S_REG_CFG0_SLAVE BIT(16) -+#define I2S_REG_CFG0_RX_THRES 12 -+#define I2S_REG_CFG0_TX_THRES 4 -+#define I2S_REG_CFG0_THRES_MASK (0xf << I2S_REG_CFG0_RX_THRES) | \ -+ (4 << I2S_REG_CFG0_TX_THRES) -+#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \ -+ (4 << I2S_REG_CFG0_TX_THRES) -+/* RT305x */ -+#define I2S_REG_CFG0_CLK_DIS BIT(8) -+#define I2S_REG_CFG0_TXCH_SWAP BIT(3) -+#define I2S_REG_CFG0_TXCH1_OFF BIT(2) -+#define I2S_REG_CFG0_TXCH0_OFF BIT(1) -+#define I2S_REG_CFG0_SLAVE_EN BIT(0) -+/* RT3883 */ -+#define I2S_REG_CFG0_RXCH_SWAP BIT(11) -+#define I2S_REG_CFG0_RXCH1_OFF BIT(10) -+#define I2S_REG_CFG0_RXCH0_OFF BIT(9) -+#define I2S_REG_CFG0_WS_INV BIT(0) -+/* MT7628 */ -+#define I2S_REG_CFG0_FMT_LE BIT(29) -+#define I2S_REG_CFG0_SYS_BE BIT(28) -+#define I2S_REG_CFG0_NORM_24 BIT(18) -+#define I2S_REG_CFG0_DATA_24 BIT(17) -+ -+/* I2S_REG_INT_STATUS */ -+#define I2S_REG_INT_RX_FAULT BIT(7) -+#define I2S_REG_INT_RX_OVRUN BIT(6) -+#define I2S_REG_INT_RX_UNRUN BIT(5) -+#define I2S_REG_INT_RX_THRES BIT(4) -+#define I2S_REG_INT_TX_FAULT BIT(3) -+#define I2S_REG_INT_TX_OVRUN BIT(2) -+#define I2S_REG_INT_TX_UNRUN BIT(1) -+#define I2S_REG_INT_TX_THRES BIT(0) -+#define I2S_REG_INT_TX_MASK 0xf -+#define I2S_REG_INT_RX_MASK 0xf0 -+ -+/* I2S_REG_INT_STATUS */ -+#define I2S_RX_AVCNT(x) ((x >> 4) & 0xf) -+#define I2S_TX_AVCNT(x) (x & 0xf) -+/* MT7628 */ -+#define MT7628_I2S_RX_AVCNT(x) ((x >> 8) & 0x1f) -+#define MT7628_I2S_TX_AVCNT(x) (x & 0x1f) -+ -+/* I2S_REG_CFG1 */ -+#define I2S_REG_CFG1_LBK BIT(31) -+#define I2S_REG_CFG1_EXTLBK BIT(30) -+/* RT3883 */ -+#define I2S_REG_CFG1_LEFT_J BIT(0) -+#define I2S_REG_CFG1_RIGHT_J BIT(1) -+#define I2S_REG_CFG1_FMT_MASK 0x3 -+ -+/* I2S_REG_DIVCMP */ -+#define I2S_REG_DIVCMP_CLKEN BIT(31) -+#define I2S_REG_DIVCMP_DIVCOMP_MASK 0x1ff -+ -+/* I2S_REG_DIVINT */ -+#define I2S_REG_DIVINT_MASK 0x3ff -+ -+/* BCLK dividers */ -+#define RALINK_I2S_DIVCMP 0 -+#define RALINK_I2S_DIVINT 1 -+ -+/* FIFO */ -+#define RALINK_I2S_FIFO_SIZE 32 -+ -+/* feature flags */ -+#define RALINK_FLAGS_TXONLY BIT(0) -+#define RALINK_FLAGS_LEFT_J BIT(1) -+#define RALINK_FLAGS_RIGHT_J BIT(2) -+#define RALINK_FLAGS_ENDIAN BIT(3) -+#define RALINK_FLAGS_24BIT BIT(4) -+ -+#define RALINK_I2S_INT_EN 0 -+ -+struct ralink_i2s_stats { -+ u32 dmafault; -+ u32 overrun; -+ u32 underrun; -+ u32 belowthres; -+}; -+ -+struct ralink_i2s { -+ struct device *dev; -+ void __iomem *regs; -+ struct clk *clk; -+ struct regmap *regmap; -+ u32 flags; -+ unsigned int fmt; -+ u16 txdma_req; -+ u16 rxdma_req; -+ -+ struct snd_dmaengine_dai_dma_data playback_dma_data; -+ struct snd_dmaengine_dai_dma_data capture_dma_data; -+ -+ struct dentry *dbg_dir; -+ struct dentry *dbg_stats; -+ struct ralink_i2s_stats txstats; -+ struct ralink_i2s_stats rxstats; -+}; -+ -+static void ralink_i2s_dump_regs(struct ralink_i2s *i2s) -+{ -+ u32 buf[10]; -+ int ret; -+ -+ ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0, -+ buf, ARRAY_SIZE(buf)); -+ -+ dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \ -+ "FFSTAT: %08x, WREG: %08x, RREG: %08x, " \ -+ "CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n", -+ buf[0], buf[1], buf[2], buf[3], buf[4], -+ buf[5], buf[6], buf[8], buf[9]); -+} -+ -+static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai, -+ int clk_id, unsigned int freq, int dir) -+{ -+ return 0; -+} -+ -+static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned long clk = clk_get_rate(i2s->clk); -+ int div; -+ uint32_t data; -+ -+ /* disable clock at slave mode */ -+ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) == -+ SND_SOC_DAIFMT_CBM_CFM) { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_CLK_DIS, -+ I2S_REG_CFG0_CLK_DIS); -+ return 0; -+ } -+ -+ /* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */ -+ div = (clk / rate ) - 1; -+ -+ data = rt_sysc_r32(0x30); -+ data &= (0xff << 8); -+ data |= (0x1 << 15) | (div << 8); -+ rt_sysc_w32(data, 0x30); -+ -+ /* enable clock */ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0); -+ -+ dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n", -+ clk, rate, div); -+ -+ return 0; -+} -+ -+static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned long clk = clk_get_rate(i2s->clk); -+ int divint, divcomp; -+ -+ /* disable clock at slave mode */ -+ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) == -+ SND_SOC_DAIFMT_CBM_CFM) { -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, -+ I2S_REG_DIVCMP_CLKEN, 0); -+ return 0; -+ } -+ -+ /* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */ -+ clk = clk / (2 * 2 * width); -+ divint = clk / rate; -+ divcomp = ((clk % rate) * 512) / rate; -+ -+ if ((divint > I2S_REG_DIVINT_MASK) || -+ (divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK)) -+ return -EINVAL; -+ -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVINT, -+ I2S_REG_DIVINT_MASK, divint); -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, -+ I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp); -+ -+ /* enable clock */ -+ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN, -+ I2S_REG_DIVCMP_CLKEN); -+ -+ dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n", -+ clk_get_rate(i2s->clk), rate, divint, divcomp); -+ -+ return 0; -+} -+ -+static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned int cfg0 = 0, cfg1 = 0; -+ -+ /* set master/slave audio interface */ -+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBM_CFM: -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ cfg0 |= I2S_REG_CFG0_SLAVE_EN; -+ else -+ cfg0 |= I2S_REG_CFG0_SLAVE; -+ break; -+ case SND_SOC_DAIFMT_CBS_CFS: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* interface format */ -+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_I2S: -+ break; -+ case SND_SOC_DAIFMT_RIGHT_J: -+ if (i2s->flags & RALINK_FLAGS_RIGHT_J) { -+ cfg1 |= I2S_REG_CFG1_RIGHT_J; -+ break; -+ } -+ return -EINVAL; -+ case SND_SOC_DAIFMT_LEFT_J: -+ if (i2s->flags & RALINK_FLAGS_LEFT_J) { -+ cfg1 |= I2S_REG_CFG1_LEFT_J; -+ break; -+ } -+ return -EINVAL; -+ default: -+ return -EINVAL; -+ } -+ -+ /* clock inversion */ -+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { -+ case SND_SOC_DAIFMT_NB_NF: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SLAVE_EN, cfg0); -+ } else { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SLAVE, cfg0); -+ } -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG1, -+ I2S_REG_CFG1_FMT_MASK, cfg1); -+ i2s->fmt = fmt; -+ -+ return 0; -+} -+ -+static int ralink_i2s_startup(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ if (snd_soc_dai_active(dai)) -+ return 0; -+ -+ /* setup status interrupt */ -+#if (RALINK_I2S_INT_EN) -+ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff); -+#else -+ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0); -+#endif -+ -+ /* enable */ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN | -+ I2S_REG_CFG0_THRES_MASK, -+ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN | -+ I2S_REG_CFG0_DFT_THRES); -+ -+ return 0; -+} -+ -+static void ralink_i2s_shutdown(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ /* If both streams are stopped, disable module and clock */ -+ if (snd_soc_dai_active(dai)) -+ return; -+ -+ /* -+ * datasheet mention when disable all control regs are cleared -+ * to initial values. need reinit at startup. -+ */ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0); -+} -+ -+static int ralink_i2s_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ int width; -+ int ret; -+ -+ width = params_width(params); -+ switch (width) { -+ case 16: -+ if (i2s->flags & RALINK_FLAGS_24BIT) -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_DATA_24, 0); -+ break; -+ case 24: -+ if (i2s->flags & RALINK_FLAGS_24BIT) { -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_DATA_24, -+ I2S_REG_CFG0_DATA_24); -+ break; -+ } -+ return -EINVAL; -+ default: -+ return -EINVAL; -+ } -+ -+ switch (params_channels(params)) { -+ case 2: -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (i2s->flags & RALINK_FLAGS_ENDIAN) { -+ /* system endian */ -+#ifdef SNDRV_LITTLE_ENDIAN -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SYS_BE, 0); -+#else -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_SYS_BE, -+ I2S_REG_CFG0_SYS_BE); -+#endif -+ -+ /* data endian */ -+ switch (params_format(params)) { -+ case SNDRV_PCM_FORMAT_S16_LE: -+ case SNDRV_PCM_FORMAT_S24_LE: -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_FMT_LE, -+ I2S_REG_CFG0_FMT_LE); -+ break; -+ case SNDRV_PCM_FORMAT_S16_BE: -+ case SNDRV_PCM_FORMAT_S24_BE: -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, -+ I2S_REG_CFG0_FMT_LE, 0); -+ break; -+ default: -+ return -EINVAL; -+ } -+ } -+ -+ /* setup bclk rate */ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params)); -+ else -+ ret = ralink_i2s_set_bclk(dai, width, params_rate(params)); -+ -+ return ret; -+} -+ -+static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd, -+ struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ unsigned int mask, val; -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) -+ mask = I2S_REG_CFG0_TX_EN; -+ else -+ mask = I2S_REG_CFG0_RX_EN; -+ -+ switch (cmd) { -+ case SNDRV_PCM_TRIGGER_START: -+ case SNDRV_PCM_TRIGGER_RESUME: -+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: -+ val = mask; -+ break; -+ case SNDRV_PCM_TRIGGER_STOP: -+ case SNDRV_PCM_TRIGGER_SUSPEND: -+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: -+ val = 0; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val); -+ -+ return 0; -+} -+ -+static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s, -+ struct resource *res) -+{ -+ struct snd_dmaengine_dai_dma_data *dma_data; -+ -+ /* Playback */ -+ dma_data = &i2s->playback_dma_data; -+ dma_data->addr = res->start + I2S_REG_WREG; -+ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ dma_data->maxburst = 1; -+ dma_data->slave_id = i2s->txdma_req; -+ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ return; -+ -+ /* Capture */ -+ dma_data = &i2s->capture_dma_data; -+ dma_data->addr = res->start + I2S_REG_RREG; -+ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ dma_data->maxburst = 1; -+ dma_data->slave_id = i2s->rxdma_req; -+} -+ -+static int ralink_i2s_dai_probe(struct snd_soc_dai *dai) -+{ -+ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai); -+ -+ snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, -+ &i2s->capture_dma_data); -+ -+ return 0; -+} -+ -+static int ralink_i2s_dai_remove(struct snd_soc_dai *dai) -+{ -+ return 0; -+} -+ -+static const struct snd_soc_dai_ops ralink_i2s_dai_ops = { -+ .set_sysclk = ralink_i2s_set_sysclk, -+ .set_fmt = ralink_i2s_set_fmt, -+ .startup = ralink_i2s_startup, -+ .shutdown = ralink_i2s_shutdown, -+ .hw_params = ralink_i2s_hw_params, -+ .trigger = ralink_i2s_trigger, -+}; -+ -+static struct snd_soc_dai_driver ralink_i2s_dai = { -+ .name = DRV_NAME, -+ .probe = ralink_i2s_dai_probe, -+ .remove = ralink_i2s_dai_remove, -+ .ops = &ralink_i2s_dai_ops, -+ .capture = { -+ .stream_name = "I2S Capture", -+ .channels_min = 2, -+ .channels_max = 2, -+ .rate_min = 5512, -+ .rate_max = 192000, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ }, -+ .playback = { -+ .stream_name = "I2S Playback", -+ .channels_min = 2, -+ .channels_max = 2, -+ .rate_min = 5512, -+ .rate_max = 192000, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ }, -+ .symmetric_rates = 1, -+}; -+ -+static struct snd_pcm_hardware ralink_pcm_hardware = { -+ .info = SNDRV_PCM_INFO_MMAP | -+ SNDRV_PCM_INFO_MMAP_VALID | -+ SNDRV_PCM_INFO_INTERLEAVED | -+ SNDRV_PCM_INFO_BLOCK_TRANSFER, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ .channels_min = 2, -+ .channels_max = 2, -+ .period_bytes_min = PAGE_SIZE, -+ .period_bytes_max = PAGE_SIZE * 2, -+ .periods_min = 2, -+ .periods_max = 128, -+ .buffer_bytes_max = 128 * 1024, -+ .fifo_size = RALINK_I2S_FIFO_SIZE, -+}; -+ -+static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = { -+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, -+ .pcm_hardware = &ralink_pcm_hardware, -+ .prealloc_buffer_size = 256 * PAGE_SIZE, -+}; -+ -+static const struct snd_soc_component_driver ralink_i2s_component = { -+ .name = DRV_NAME, -+}; -+ -+static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg) -+{ -+ return true; -+} -+ -+static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case I2S_REG_INT_STATUS: -+ case I2S_REG_FF_STATUS: -+ return true; -+ } -+ return false; -+} -+ -+static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case I2S_REG_FF_STATUS: -+ case I2S_REG_RREG: -+ return false; -+ } -+ return true; -+} -+ -+static const struct regmap_config ralink_i2s_regmap_config = { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .writeable_reg = ralink_i2s_writeable_reg, -+ .readable_reg = ralink_i2s_readable_reg, -+ .volatile_reg = ralink_i2s_volatile_reg, -+ .max_register = I2S_REG_DIVINT, -+}; -+ -+#if (RALINK_I2S_INT_EN) -+static irqreturn_t ralink_i2s_irq(int irq, void *devid) -+{ -+ struct ralink_i2s *i2s = devid; -+ u32 status; -+ -+ regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status); -+ if (unlikely(!status)) -+ return IRQ_NONE; -+ -+ /* tx stats */ -+ if (status & I2S_REG_INT_TX_MASK) { -+ if (status & I2S_REG_INT_TX_THRES) -+ i2s->txstats.belowthres++; -+ if (status & I2S_REG_INT_TX_UNRUN) -+ i2s->txstats.underrun++; -+ if (status & I2S_REG_INT_TX_OVRUN) -+ i2s->txstats.overrun++; -+ if (status & I2S_REG_INT_TX_FAULT) -+ i2s->txstats.dmafault++; -+ } -+ -+ /* rx stats */ -+ if (status & I2S_REG_INT_RX_MASK) { -+ if (status & I2S_REG_INT_RX_THRES) -+ i2s->rxstats.belowthres++; -+ if (status & I2S_REG_INT_RX_UNRUN) -+ i2s->rxstats.underrun++; -+ if (status & I2S_REG_INT_RX_OVRUN) -+ i2s->rxstats.overrun++; -+ if (status & I2S_REG_INT_RX_FAULT) -+ i2s->rxstats.dmafault++; -+ } -+ -+ /* clean status bits */ -+ regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status); -+ -+ return IRQ_HANDLED; -+} -+#endif -+ -+#if IS_ENABLED(CONFIG_DEBUG_FS) -+static int ralink_i2s_stats_show(struct seq_file *s, void *unused) -+{ -+ struct ralink_i2s *i2s = s->private; -+ -+ seq_printf(s, "tx stats\n"); -+ seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres); -+ seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun); -+ seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun); -+ seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault); -+ -+ seq_printf(s, "rx stats\n"); -+ seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres); -+ seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun); -+ seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun); -+ seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault); -+ -+ ralink_i2s_dump_regs(i2s); -+ -+ return 0; -+} -+ -+static int ralink_i2s_stats_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, ralink_i2s_stats_show, inode->i_private); -+} -+ -+static const struct file_operations ralink_i2s_stats_ops = { -+ .open = ralink_i2s_stats_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s) -+{ -+ i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL); -+ if (!i2s->dbg_dir) -+ return -ENOMEM; -+ -+ i2s->dbg_stats = debugfs_create_file("stats", S_IRUGO, -+ i2s->dbg_dir, i2s, &ralink_i2s_stats_ops); -+ if (!i2s->dbg_stats) { -+ debugfs_remove(i2s->dbg_dir); -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s) -+{ -+ debugfs_remove(i2s->dbg_stats); -+ debugfs_remove(i2s->dbg_dir); -+} -+#else -+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s) -+{ -+ return 0; -+} -+ -+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s) -+{ -+} -+#endif -+ -+/* -+ * TODO: these refclk setup functions should use -+ * clock framework instead. hardcode it now. -+ */ -+static void rt3350_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data |= (0x1 << 8); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void rt3883_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x3 << 13); -+ data |= (0x1 << 13); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void rt3552_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0xf << 8); -+ data |= (0x3 << 8); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void mt7620_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x7 << 9); -+ data |= 0x1 << 9; -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void mt7621_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x1f << 18); -+ data |= (0x19 << 18); -+ data &= ~(0x1f << 12); -+ data |= (0x1 << 12); -+ data &= ~(0x7 << 9); -+ data |= (0x5 << 9); -+ rt_sysc_w32(data, 0x2c); -+} -+ -+static void mt7628_refclk_setup(void) -+{ -+ uint32_t data; -+ -+ /* set i2s and refclk digital pad */ -+ data = rt_sysc_r32(0x3c); -+ data |= 0x1f; -+ rt_sysc_w32(data, 0x3c); -+ -+ /* Adjust REFCLK0's driving strength */ -+ data = rt_sysc_r32(0x1354); -+ data &= ~(0x1 << 5); -+ rt_sysc_w32(data, 0x1354); -+ data = rt_sysc_r32(0x1364); -+ data |= ~(0x1 << 5); -+ rt_sysc_w32(data, 0x1364); -+ -+ /* set refclk output 12Mhz clock */ -+ data = rt_sysc_r32(0x2c); -+ data &= ~(0x7 << 9); -+ data |= 0x1 << 9; -+ rt_sysc_w32(data, 0x2c); -+} -+ -+struct rt_i2s_data { -+ u32 flags; -+ void (*refclk_setup)(void); -+}; -+ -+struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY }; -+struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY, -+ .refclk_setup = rt3350_refclk_setup }; -+struct rt_i2s_data rt3883_i2s_data = { -+ .flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J), -+ .refclk_setup = rt3883_refclk_setup }; -+struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup}; -+struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup}; -+struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup}; -+struct rt_i2s_data mt7628_i2s_data = { -+ .flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT | -+ RALINK_FLAGS_LEFT_J), -+ .refclk_setup = mt7628_refclk_setup}; -+ -+static const struct of_device_id ralink_i2s_match_table[] = { -+ { .compatible = "ralink,rt3050-i2s", -+ .data = (void *)&rt3050_i2s_data }, -+ { .compatible = "ralink,rt3350-i2s", -+ .data = (void *)&rt3350_i2s_data }, -+ { .compatible = "ralink,rt3883-i2s", -+ .data = (void *)&rt3883_i2s_data }, -+ { .compatible = "ralink,rt3352-i2s", -+ .data = (void *)&rt3352_i2s_data }, -+ { .compatible = "mediatek,mt7620-i2s", -+ .data = (void *)&mt7620_i2s_data }, -+ { .compatible = "mediatek,mt7621-i2s", -+ .data = (void *)&mt7621_i2s_data }, -+ { .compatible = "mediatek,mt7628-i2s", -+ .data = (void *)&mt7628_i2s_data }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ralink_i2s_match_table); -+ -+static int ralink_i2s_probe(struct platform_device *pdev) -+{ -+ const struct of_device_id *match; -+ struct device_node *np = pdev->dev.of_node; -+ struct ralink_i2s *i2s; -+ struct resource *res; -+ int irq, ret; -+ u32 dma_req; -+ struct rt_i2s_data *data; -+ -+ i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); -+ if (!i2s) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, i2s); -+ i2s->dev = &pdev->dev; -+ -+ match = of_match_device(ralink_i2s_match_table, &pdev->dev); -+ if (!match) -+ return -EINVAL; -+ data = (struct rt_i2s_data *)match->data; -+ i2s->flags = data->flags; -+ /* setup out 12Mhz refclk to codec as mclk */ -+ if (data->refclk_setup) -+ data->refclk_setup(); -+ -+ if (of_property_read_u32(np, "txdma-req", &dma_req)) { -+ dev_err(&pdev->dev, "no txdma-req define\n"); -+ return -EINVAL; -+ } -+ i2s->txdma_req = (u16)dma_req; -+ if (!(i2s->flags & RALINK_FLAGS_TXONLY)) { -+ if (of_property_read_u32(np, "rxdma-req", &dma_req)) { -+ dev_err(&pdev->dev, "no rxdma-req define\n"); -+ return -EINVAL; -+ } -+ i2s->rxdma_req = (u16)dma_req; -+ } -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ i2s->regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(i2s->regs)) -+ return PTR_ERR(i2s->regs); -+ -+ i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs, -+ &ralink_i2s_regmap_config); -+ if (IS_ERR(i2s->regmap)) { -+ dev_err(&pdev->dev, "regmap init failed\n"); -+ return PTR_ERR(i2s->regmap); -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ dev_err(&pdev->dev, "failed to get irq\n"); -+ return -EINVAL; -+ } -+ -+#if (RALINK_I2S_INT_EN) -+ ret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq, -+ 0, dev_name(&pdev->dev), i2s); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request irq\n"); -+ return ret; -+ } -+#endif -+ -+ i2s->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(i2s->clk)) { -+ dev_err(&pdev->dev, "no clock defined\n"); -+ return PTR_ERR(i2s->clk); -+ } -+ -+ ret = clk_prepare_enable(i2s->clk); -+ if (ret) -+ return ret; -+ -+ ralink_i2s_init_dma_data(i2s, res); -+ -+ device_reset(&pdev->dev); -+ -+ ret = ralink_i2s_debugfs_create(i2s); -+ if (ret) { -+ dev_err(&pdev->dev, "create debugfs failed\n"); -+ goto err_clk_disable; -+ } -+ -+ /* enable 24bits support */ -+ if (i2s->flags & RALINK_FLAGS_24BIT) { -+ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE; -+ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE; -+ } -+ -+ /* enable big endian support */ -+ if (i2s->flags & RALINK_FLAGS_ENDIAN) { -+ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE; -+ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE; -+ ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE; -+ if (i2s->flags & RALINK_FLAGS_24BIT) { -+ ralink_i2s_dai.capture.formats |= -+ SNDRV_PCM_FMTBIT_S24_BE; -+ ralink_i2s_dai.playback.formats |= -+ SNDRV_PCM_FMTBIT_S24_BE; -+ ralink_pcm_hardware.formats |= -+ SNDRV_PCM_FMTBIT_S24_BE; -+ } -+ } -+ -+ /* disable capture support */ -+ if (i2s->flags & RALINK_FLAGS_TXONLY) -+ memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture), -+ 0); -+ -+ ret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component, -+ &ralink_i2s_dai, 1); -+ if (ret) -+ goto err_debugfs; -+ -+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, -+ &ralink_dmaengine_pcm_config, -+ SND_DMAENGINE_PCM_FLAG_COMPAT); -+ if (ret) -+ goto err_debugfs; -+ -+ dev_info(i2s->dev, "mclk %luMHz\n", clk_get_rate(i2s->clk) / 1000000); -+ -+ return 0; -+ -+err_debugfs: -+ ralink_i2s_debugfs_remove(i2s); -+ -+err_clk_disable: -+ clk_disable_unprepare(i2s->clk); -+ -+ return ret; -+} -+ -+static int ralink_i2s_remove(struct platform_device *pdev) -+{ -+ struct ralink_i2s *i2s = platform_get_drvdata(pdev); -+ -+ ralink_i2s_debugfs_remove(i2s); -+ clk_disable_unprepare(i2s->clk); -+ -+ return 0; -+} -+ -+static struct platform_driver ralink_i2s_driver = { -+ .probe = ralink_i2s_probe, -+ .remove = ralink_i2s_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .of_match_table = ralink_i2s_match_table, -+ }, -+}; -+module_platform_driver(ralink_i2s_driver); -+ -+MODULE_AUTHOR("Lars-Peter Clausen, "); -+MODULE_DESCRIPTION("Ralink/MediaTek I2S driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:" DRV_NAME); diff --git a/target/linux/ramips/patches-5.10/840-serial-add-ugly-custom-baud-rate-hack.patch b/target/linux/ramips/patches-5.10/840-serial-add-ugly-custom-baud-rate-hack.patch deleted file mode 100644 index 37f0504b55..0000000000 --- a/target/linux/ramips/patches-5.10/840-serial-add-ugly-custom-baud-rate-hack.patch +++ /dev/null @@ -1,22 +0,0 @@ -From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:31:08 +0100 -Subject: [PATCH 51/53] serial: add ugly custom baud rate hack - -Signed-off-by: John Crispin ---- - drivers/tty/serial/serial_core.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/tty/serial/serial_core.c -+++ b/drivers/tty/serial/serial_core.c -@@ -417,6 +417,9 @@ uart_get_baud_rate(struct uart_port *por - break; - } - -+ if (tty_termios_baud_rate(termios) == 2500000) -+ return 250000; -+ - for (try = 0; try < 2; try++) { - baud = tty_termios_baud_rate(termios); - diff --git a/target/linux/ramips/patches-5.10/845-pwm-add-mediatek-support.patch b/target/linux/ramips/patches-5.10/845-pwm-add-mediatek-support.patch deleted file mode 100644 index 794e3360fb..0000000000 --- a/target/linux/ramips/patches-5.10/845-pwm-add-mediatek-support.patch +++ /dev/null @@ -1,217 +0,0 @@ -From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 7 Dec 2015 17:16:50 +0100 -Subject: [PATCH 52/53] pwm: add mediatek support - -Signed-off-by: John Crispin ---- - drivers/pwm/Kconfig | 9 +++ - drivers/pwm/Makefile | 1 + - drivers/pwm/pwm-mediatek.c | 173 ++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 183 insertions(+) - create mode 100644 drivers/pwm/pwm-mediatek.c - ---- a/drivers/pwm/Kconfig -+++ b/drivers/pwm/Kconfig -@@ -339,6 +339,15 @@ config PWM_MEDIATEK - To compile this driver as a module, choose M here: the module - will be called pwm-mediatek. - -+config PWM_MEDIATEK_RAMIPS -+ tristate "Mediatek PWM support" -+ depends on RALINK && OF -+ help -+ Generic PWM framework driver for Mediatek ARM SoC. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called pwm-mxs. -+ - config PWM_MXS - tristate "Freescale MXS PWM support" - depends on OF ---- a/drivers/pwm/Makefile -+++ b/drivers/pwm/Makefile -@@ -30,6 +30,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p - obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o - obj-$(CONFIG_PWM_MESON) += pwm-meson.o - obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o -+obj-$(CONFIG_PWM_MEDIATEK_RAMIPS) += pwm-mediatek-ramips.o - obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o - obj-$(CONFIG_PWM_MXS) += pwm-mxs.o - obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o ---- /dev/null -+++ b/drivers/pwm/pwm-mediatek-ramips.c -@@ -0,0 +1,173 @@ -+/* -+ * Mediatek Pulse Width Modulator driver -+ * -+ * Copyright (C) 2015 John Crispin -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define NUM_PWM 4 -+ -+/* PWM registers and bits definitions */ -+#define PWMCON 0x00 -+#define PWMHDUR 0x04 -+#define PWMLDUR 0x08 -+#define PWMGDUR 0x0c -+#define PWMWAVENUM 0x28 -+#define PWMDWIDTH 0x2c -+#define PWMTHRES 0x30 -+ -+/** -+ * struct mtk_pwm_chip - struct representing pwm chip -+ * -+ * @mmio_base: base address of pwm chip -+ * @chip: linux pwm chip representation -+ */ -+struct mtk_pwm_chip { -+ void __iomem *mmio_base; -+ struct pwm_chip chip; -+}; -+ -+static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) -+{ -+ return container_of(chip, struct mtk_pwm_chip, chip); -+} -+ -+static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, -+ unsigned long offset) -+{ -+ return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset); -+} -+ -+static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, -+ unsigned int num, unsigned long offset, -+ unsigned long val) -+{ -+ iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset); -+} -+ -+static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, -+ int duty_ns, int period_ns) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 resolution = 100 / 4; -+ u32 clkdiv = 0; -+ -+ while (period_ns / resolution > 8191) { -+ clkdiv++; -+ resolution *= 2; -+ } -+ -+ if (clkdiv > 7) -+ return -1; -+ -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv); -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); -+ mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution); -+ return 0; -+} -+ -+static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 val; -+ -+ val = ioread32(pc->mmio_base); -+ val |= BIT(pwm->hwpwm); -+ iowrite32(val, pc->mmio_base); -+ -+ return 0; -+} -+ -+static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) -+{ -+ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); -+ u32 val; -+ -+ val = ioread32(pc->mmio_base); -+ val &= ~BIT(pwm->hwpwm); -+ iowrite32(val, pc->mmio_base); -+} -+ -+static const struct pwm_ops mtk_pwm_ops = { -+ .config = mtk_pwm_config, -+ .enable = mtk_pwm_enable, -+ .disable = mtk_pwm_disable, -+ .owner = THIS_MODULE, -+}; -+ -+static int mtk_pwm_probe(struct platform_device *pdev) -+{ -+ struct mtk_pwm_chip *pc; -+ struct resource *r; -+ int ret; -+ -+ pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); -+ if (!pc) -+ return -ENOMEM; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); -+ if (IS_ERR(pc->mmio_base)) -+ return PTR_ERR(pc->mmio_base); -+ -+ platform_set_drvdata(pdev, pc); -+ -+ pc->chip.dev = &pdev->dev; -+ pc->chip.ops = &mtk_pwm_ops; -+ pc->chip.base = -1; -+ pc->chip.npwm = NUM_PWM; -+ -+ ret = pwmchip_add(&pc->chip); -+ if (ret < 0) -+ dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); -+ -+ return ret; -+} -+ -+static int mtk_pwm_remove(struct platform_device *pdev) -+{ -+ struct mtk_pwm_chip *pc = platform_get_drvdata(pdev); -+ int i; -+ -+ for (i = 0; i < NUM_PWM; i++) -+ pwm_disable(&pc->chip.pwms[i]); -+ -+ return pwmchip_remove(&pc->chip); -+} -+ -+static const struct of_device_id mtk_pwm_of_match[] = { -+ { .compatible = "mediatek,mt7628-pwm" }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); -+ -+static struct platform_driver mtk_pwm_driver = { -+ .driver = { -+ .name = "mtk-pwm", -+ .owner = THIS_MODULE, -+ .of_match_table = mtk_pwm_of_match, -+ }, -+ .probe = mtk_pwm_probe, -+ .remove = mtk_pwm_remove, -+}; -+ -+module_platform_driver(mtk_pwm_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("John Crispin "); -+MODULE_ALIAS("platform:mtk-pwm"); diff --git a/target/linux/ramips/patches-5.10/850-awake-rt305x-dwc2-controller.patch b/target/linux/ramips/patches-5.10/850-awake-rt305x-dwc2-controller.patch deleted file mode 100644 index 5c87298f36..0000000000 --- a/target/linux/ramips/patches-5.10/850-awake-rt305x-dwc2-controller.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/drivers/usb/dwc2/platform.c -+++ b/drivers/usb/dwc2/platform.c -@@ -465,6 +465,12 @@ static int dwc2_driver_probe(struct plat - if (retval) - return retval; - -+ /* Enable USB port before any regs access */ -+ if (readl(hsotg->regs + PCGCTL) & 0x0f) { -+ writel(0x00, hsotg->regs + PCGCTL); -+ /* TODO: mdelay(25) here? vendor driver don't use it */ -+ } -+ - hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); - - retval = dwc2_get_dr_mode(hsotg); diff --git a/target/linux/ramips/patches-5.10/855-linkit_bootstrap.patch b/target/linux/ramips/patches-5.10/855-linkit_bootstrap.patch deleted file mode 100644 index 379aa28ae2..0000000000 --- a/target/linux/ramips/patches-5.10/855-linkit_bootstrap.patch +++ /dev/null @@ -1,97 +0,0 @@ ---- a/drivers/misc/Makefile -+++ b/drivers/misc/Makefile -@@ -50,6 +50,7 @@ obj-$(CONFIG_GENWQE) += genwqe/ - obj-$(CONFIG_ECHO) += echo/ - obj-$(CONFIG_CXL_BASE) += cxl/ - obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o -+obj-$(CONFIG_SOC_MT7620) += linkit.o - obj-$(CONFIG_OCXL) += ocxl/ - obj-y += cardreader/ - obj-$(CONFIG_PVPANIC) += pvpanic.o ---- /dev/null -+++ b/drivers/misc/linkit.c -@@ -0,0 +1,84 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * publishhed by the Free Software Foundation. -+ * -+ * Copyright (C) 2015 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define LINKIT_LATCH_GPIO 11 -+ -+struct linkit_hw_data { -+ char board[16]; -+ char rev[16]; -+}; -+ -+static void sanify_string(char *s) -+{ -+ int i; -+ -+ for (i = 0; i < 15; i++) -+ if (s[i] <= 0x20) -+ s[i] = '\0'; -+ s[15] = '\0'; -+} -+ -+static int linkit_probe(struct platform_device *pdev) -+{ -+ struct linkit_hw_data hw; -+ struct mtd_info *mtd; -+ size_t retlen; -+ int ret; -+ -+ mtd = get_mtd_device_nm("factory"); -+ if (IS_ERR(mtd)) -+ return PTR_ERR(mtd); -+ -+ ret = mtd_read(mtd, 0x400, sizeof(hw), &retlen, (u_char *) &hw); -+ put_mtd_device(mtd); -+ -+ sanify_string(hw.board); -+ sanify_string(hw.rev); -+ -+ dev_info(&pdev->dev, "Version : %s\n", hw.board); -+ dev_info(&pdev->dev, "Revision : %s\n", hw.rev); -+ -+ if (!strcmp(hw.board, "LINKITS7688")) { -+ dev_info(&pdev->dev, "setting up bootstrap latch\n"); -+ -+ if (devm_gpio_request(&pdev->dev, LINKIT_LATCH_GPIO, "bootstrap")) { -+ dev_err(&pdev->dev, "failed to setup bootstrap gpio\n"); -+ return -1; -+ } -+ gpio_direction_output(LINKIT_LATCH_GPIO, 0); -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id linkit_match[] = { -+ { .compatible = "mediatek,linkit" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, linkit_match); -+ -+static struct platform_driver linkit_driver = { -+ .probe = linkit_probe, -+ .driver = { -+ .name = "mtk-linkit", -+ .owner = THIS_MODULE, -+ .of_match_table = linkit_match, -+ }, -+}; -+ -+int __init linkit_init(void) -+{ -+ return platform_driver_register(&linkit_driver); -+} -+late_initcall_sync(linkit_init); diff --git a/target/linux/ramips/rt288x/config-5.10 b/target/linux/ramips/rt288x/config-5.10 deleted file mode 100644 index 8aff187cb6..0000000000 --- a/target/linux/ramips/rt288x/config-5.10 +++ /dev/null @@ -1,178 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_RT2880_EVAL is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_RALINK=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IP17XX_PHY=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -# CONFIG_KERNEL_ZSTD is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=4 -CONFIG_MIPS_L1_CACHE_SHIFT_4=y -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_LZMA_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_SPLIT_WRGG_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_MDIO=y -CONFIG_NET_RALINK_MDIO_RT2880=y -CONFIG_NET_RALINK_RT2880=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NLS=m -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -# CONFIG_PHY_RALINK_USB is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_RALINK=y -CONFIG_RALINK_WDT=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set -CONFIG_SOC_RT288X=y -# CONFIG_SOC_RT305X is not set -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB=m -CONFIG_USB_COMMON=m -CONFIG_USB_EHCI_HCD=m -CONFIG_USB_EHCI_HCD_PLATFORM=m -CONFIG_USB_OHCI_HCD=m -CONFIG_USB_OHCI_HCD_PLATFORM=m -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/rt305x/config-5.10 b/target/linux/ramips/rt305x/config-5.10 deleted file mode 100644 index ba36912718..0000000000 --- a/target/linux/ramips/rt305x/config-5.10 +++ /dev/null @@ -1,178 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_CEVT_R4K=y -CONFIG_CEVT_SYSTICK_QUIRK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_RT3352=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_RT305X_EVAL is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_RALINK=y -CONFIG_GPIO_WATCHDOG=y -# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -# CONFIG_KERNEL_ZSTD is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_JIMAGE_FW=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_ESW_RT3050=y -CONFIG_NET_RALINK_RT3050=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_RALINK=y -# CONFIG_RALINK_ILL_ACC is not set -CONFIG_RALINK_WDT=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -CONFIG_SOC_RT305X=y -# CONFIG_SOC_RT3883 is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/ramips/rt3883/config-5.10 b/target/linux/ramips/rt3883/config-5.10 deleted file mode 100644 index aaccbddefd..0000000000 --- a/target/linux/ramips/rt3883/config-5.10 +++ /dev/null @@ -1,178 +0,0 @@ -CONFIG_AR8216_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_BOOL=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_PINCTRL=y -CONFIG_DMA_NONCOHERENT=y -# CONFIG_DTB_RT3883_EVAL is not set -CONFIG_DTB_RT_NONE=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIO_RALINK=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_INTC=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -# CONFIG_KERNEL_ZSTD is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_SEAMA_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_RALINK_MDIO=y -CONFIG_NET_RALINK_MDIO_RT2880=y -CONFIG_NET_RALINK_RT3883=y -CONFIG_NET_RALINK_SOC=y -CONFIG_NET_VENDOR_RALINK=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DRIVERS_LEGACY=y -# CONFIG_PCI_MT7621 is not set -# CONFIG_PCI_MT7621_PHY is not set -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHY_RALINK_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_AW9523 is not set -CONFIG_PINCTRL_RT2880=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_RALINK=y -CONFIG_RALINK_WDT=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RTL8366_SMI=y -CONFIG_RTL8367B_PHY=y -CONFIG_RTL8367_PHY=y -CONFIG_SERIAL_8250_RT288X=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_SOC_MT7620 is not set -# CONFIG_SOC_MT7621 is not set -# CONFIG_SOC_RT288X is not set -# CONFIG_SOC_RT305X is not set -CONFIG_SOC_RT3883=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_MT7621 is not set -CONFIG_SPI_RT2880=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_USB_SUPPORT=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y diff --git a/target/linux/realtek/dts-5.10/rtl8380_d-link_dgs-1210-10mp-f.dts b/target/linux/realtek/dts-5.10/rtl8380_d-link_dgs-1210-10mp-f.dts deleted file mode 100644 index 664cab5999..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_d-link_dgs-1210-10mp-f.dts +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl83xx_d-link_dgs-1210_common.dtsi" -#include "rtl83xx_d-link_dgs-1210_gpio.dtsi" - -/ { - compatible = "d-link,dgs-1210-10mp-f", "realtek,rtl8382-soc", "realtek,rtl838x-soc"; - - model = "D-Link DGS-1210-10MP F"; - - /* i2c for sfp port9 */ - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-p9 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - - /* i2c for sfp port10 */ - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-p10 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; -}; - -&leds { - link_act { - label = "green:link_act"; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; - - poe { - label = "green:poe"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - - poe_max { - label = "yellow:poe_max"; - gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - }; -}; - -&keys { - mode { - label = "mode"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; -}; - -&uart1 { - status = "okay"; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - INTERNAL_PHY(24) - INTERNAL_PHY(26) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - port@24 { - reg = <24>; - label = "lan9"; - phy-handle = <&phy24>; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp0>; - }; - - port@26 { - reg = <26>; - label = "lan10"; - phy-handle = <&phy26>; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp1>; - }; - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_engenius_ews2910p.dts b/target/linux/realtek/dts-5.10/rtl8380_engenius_ews2910p.dts deleted file mode 100644 index 9b5ddb5ed4..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_engenius_ews2910p.dts +++ /dev/null @@ -1,229 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl838x.dtsi" - -#include -#include - -/ { - compatible = "engenius,ews2910p", "realtek,rtl838x-soc"; - model = "EnGenius EWS2910P"; - - aliases { - led-boot = &led_power; - led-failsafe = &led_fault; - led-running = &led_power; - led-upgrade = &led_power; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - led_mode { - label = "led-mode"; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - gpio-controller; - indirect-access-bus-id = <0>; - - poe_enable { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "poe-enable"; - }; - - sff_p9_gpios { - gpio-hog; - gpios = < 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, - < 11 GPIO_ACTIVE_HIGH>, /* los-gpio */ - < 12 GPIO_ACTIVE_LOW>; /* mod-def0-gpio */ - input; - line-name = "sff-p9-gpios"; - }; - }; - - gpio-export { - compatible = "gpio-export"; - - sff-p9-tx-disable { - gpio-export,name = "sff-p9-tx-disable"; - gpio-export,output = <1>; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - led_power: led-0 { - label = "green:power"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - }; - - led_lan_mode: led-1 { - label = "green:lan-mode"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - - led_fault: led-2 { - label = "amber:fault"; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - led_poe_max: led-3 { - label = "amber:poe-max"; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - }; - - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - sfp1: sfp-p10 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - partition@80000 { - label = "u-boot-env"; - reg = <0x80000 0x10000>; - read-only; - }; - partition@90000 { - label = "u-boot-env2"; - reg = <0x90000 0x10000>; - }; - partition@a0000 { - label = "rootfs_data"; - reg = <0xa0000 0xd60000>; - }; - partition@e00000 { - label = "jffs2-log"; - reg = <0xe00000 0x200000>; - }; - partition@1000000 { - compatible = "openwrt,uimage"; - label = "firmware"; - reg = <0x1000000 0x800000>; - openwrt,ih-magic = <0x03802910>; - }; - partition@1800000 { - label = "firmware2"; - reg = <0x1800000 0x800000>; - }; - }; - }; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - INTERNAL_PHY(24) - INTERNAL_PHY(26) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - SWITCH_SFP_PORT(24, 9, 1000base-x) - - port@26 { - reg = <26>; - label = "lan10"; - phy-mode = "1000base-x"; - phy-handle = <&phy26>; - managed = "in-band-status"; - sfp = <&sfp1>; - }; - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; - -&uart1 { - status = "okay"; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_hpe_1920-8g.dts b/target/linux/realtek/dts-5.10/rtl8380_hpe_1920-8g.dts deleted file mode 100644 index 6ddb2d8dcc..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_hpe_1920-8g.dts +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl838x_hpe_1920.dtsi" - -/ { - compatible = "hpe,1920-8g", "realtek,rtl838x-soc"; - model = "HPE 1920-8G (JG920A)"; - - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - gpio-controller; - indirect-access-bus-id = <0>; - }; - - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>; - // tx-fault and tx-disable unconnected - }; - - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>; - // tx-fault and tx-disable unconnected - }; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - INTERNAL_PHY(24) - INTERNAL_PHY(26) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - port@24 { - reg = <24>; - label = "lan9"; - phy-handle = <&phy24>; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp0>; - }; - - port@26 { - reg = <26>; - label = "lan10"; - phy-handle = <&phy26>; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp1>; - }; - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit.dtsi b/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit.dtsi deleted file mode 100644 index 5e587f278d..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit.dtsi +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl838x.dtsi" - -#include -#include - -/ { - compatible = "realtek,rtl838x-soc"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - - compatible = "gpio-keys"; - - mode { - label = "reset"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - open-source; - }; - - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - gpio-controller; - indirect-access-bus-id = <31>; - }; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_1xx.dtsi b/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_1xx.dtsi deleted file mode 100644 index fd44543bb4..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_1xx.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_netgear_gigabit.dtsi" - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x00e0000>; - read-only; - }; - - partition@e0000 { - label = "u-boot-env"; - reg = <0x00e0000 0x0010000>; - }; - - partition@f0000 { - label = "u-boot-env2"; - reg = <0x00f0000 0x0010000>; - }; - - partition@100000 { - label = "jffs"; - reg = <0x0100000 0x0100000>; - read-only; - }; - - partition@200000 { - label = "jffs2"; - reg = <0x0200000 0x0100000>; - read-only; - }; - - partition@300000 { - label = "firmware"; - compatible = "openwrt,uimage", "denx,uimage"; - openwrt,ih-magic = <0x4e474520>; - reg = <0x0300000 0x0e80000>; - }; - - partition@1180000 { - label = "runtime2"; - reg = <0x1180000 0x0e80000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_3xx.dtsi b/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_3xx.dtsi deleted file mode 100644 index 0ade665c98..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_3xx.dtsi +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_netgear_gigabit.dtsi" - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x00e0000>; - read-only; - }; - - partition@e0000 { - label = "u-boot-env"; - reg = <0x00e0000 0x0010000>; - }; - - partition@f0000 { - label = "u-boot-env2"; - reg = <0x00f0000 0x0010000>; - }; - - partition@100000 { - label = "jffs"; - reg = <0x0100000 0x0100000>; - read-only; - }; - - partition@200000 { - label = "jffs2"; - reg = <0x0200000 0x0100000>; - read-only; - }; - - partition@300000 { - label = "firmware"; - compatible = "openwrt,uimage", "denx,uimage"; - openwrt,ih-magic = <0x4e474335>; - reg = <0x0300000 0x0e80000>; - }; - - partition@1180000 { - label = "runtime2"; - reg = <0x1180000 0x0e80000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_netgear_gs108t-v3.dts b/target/linux/realtek/dts-5.10/rtl8380_netgear_gs108t-v3.dts deleted file mode 100644 index e149834d44..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_netgear_gs108t-v3.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_netgear_gigabit_1xx.dtsi" - -#include - -/ { - compatible = "netgear,gs108t-v3", "realtek,rtl838x-soc"; - model = "Netgear GS108T v3"; - - aliases { - led-boot = &led_power_green; - led-failsafe = &led_power_amber; - led-running = &led_power_green; - led-upgrade = &led_power_amber; - }; - - leds { - compatible = "gpio-leds"; - - led_power_amber: led-0 { - label = "amber:power"; - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio1 32 GPIO_ACTIVE_LOW>; - }; - - led_power_green: led-1 { - label = "green:power"; - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_netgear_gs110tpp-v1.dts b/target/linux/realtek/dts-5.10/rtl8380_netgear_gs110tpp-v1.dts deleted file mode 100644 index b61af62ea5..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_netgear_gs110tpp-v1.dts +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_netgear_gigabit_1xx.dtsi" -#include - -/ { - compatible = "netgear,gs110tpp-v1", "realtek,rtl838x-soc"; - model = "Netgear GS110TPP v1"; - - aliases { - led-boot = &led_status_green; - led-failsafe = &led_status_red; - led-running = &led_status_green; - led-upgrade = &led_status_blue; - }; - - leds { - compatible = "gpio-leds"; - - led_status_red: led-0 { - label = "red:status"; - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - - led_status_green: led-1 { - label = "green:status"; - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 32 GPIO_ACTIVE_LOW>; - }; - - led_status_blue: led-2 { - label = "blue:status"; - color = ; - function = LED_FUNCTION_STATUS; - gpios = <&gpio1 34 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&uart1 { - status = "okay"; -}; - -&mdio { - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) -}; - -&switch0 { - ports { - SWITCH_PORT(16, 9, qsgmii) - SWITCH_PORT(17, 10, qsgmii) - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_netgear_gs308t-v1.dts b/target/linux/realtek/dts-5.10/rtl8380_netgear_gs308t-v1.dts deleted file mode 100644 index cd69e80186..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_netgear_gs308t-v1.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_netgear_gigabit_3xx.dtsi" - -#include - -/ { - compatible = "netgear,gs308t-v1", "realtek,rtl838x-soc"; - model = "Netgear GS308T v1"; - - aliases { - led-boot = &led_power_green; - led-failsafe = &led_power_amber; - led-running = &led_power_green; - led-upgrade = &led_power_amber; - }; - - leds { - compatible = "gpio-leds"; - - led_power_amber: led-0 { - label = "amber:power"; - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio1 32 GPIO_ACTIVE_LOW>; - }; - - led_power_green: led-1 { - label = "green:power"; - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_netgear_gs310tp-v1.dts b/target/linux/realtek/dts-5.10/rtl8380_netgear_gs310tp-v1.dts deleted file mode 100644 index dacd504ac4..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_netgear_gs310tp-v1.dts +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_netgear_gigabit_3xx.dtsi" - -/ { - compatible = "netgear,gs310tp-v1", "realtek,rtl838x-soc"; - model = "Netgear GS310TP v1"; - -}; - -&uart1 { - status = "okay"; -}; - -&mdio { - INTERNAL_PHY(24) - INTERNAL_PHY(26) -}; - -&switch0 { - ports { - SWITCH_SFP_PORT(24, 9, rgmii-id) - SWITCH_SFP_PORT(26, 10, rgmii-id) - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_panasonic_m8eg-pn28080k.dts b/target/linux/realtek/dts-5.10/rtl8380_panasonic_m8eg-pn28080k.dts deleted file mode 100644 index f9d58f5b66..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_panasonic_m8eg-pn28080k.dts +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi" - -#include - -/ { - compatible = "panasonic,m8eg-pn28080k", "realtek,rtl8380-soc"; - model = "Panasonic Switch-M8eG PN28080K"; - - aliases { - led-boot = &led_status_eco_green; - led-failsafe = &led_status_eco_amber; - led-running = &led_status_eco_green; - led-upgrade = &led_status_eco_green; - }; - - sfp0: sfp-p9 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; -}; - -&leds { - led_status_eco_amber: led-5 { - label = "amber:status_eco"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_STATUS; - function-enumerator = <1>; - }; - - led_status_eco_green: led-6 { - label = "green:status_eco"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_STATUS; - function-enumerator = <2>; - }; -}; - -&i2c_gpio_0 { - scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&i2c_gpio_1 { - scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&gpio1 { - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; -}; - -&gpio2 { - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; -}; - -&i2c_switch { - i2c0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; -}; - -ðernet0 { - mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - INTERNAL_PHY(24) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - port@24 { - reg = <24>; - label = "lan9"; - phy-mode = "1000base-x"; - phy-handle = <&phy24>; - managed = "in-band-status"; - sfp = <&sfp0>; - }; - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_tplink_sg2008p-v1.dts b/target/linux/realtek/dts-5.10/rtl8380_tplink_sg2008p-v1.dts deleted file mode 100644 index bf43e412b1..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_tplink_sg2008p-v1.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_tplink_sg2xxx.dtsi" - -/ { - compatible = "tplink,sg2008p-v1", "realtek,rtl838x-soc"; - model = "TP-Link SG2008P v1"; -}; - -&tps23861_20 { - status = "disabled"; -}; - -&phy24 { - status = "disabled"; -}; - -&phy26 { - status = "disabled"; -}; - -&port24 { - status = "disabled"; -}; - -&port26 { - status = "disabled"; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_tplink_sg2210p-v3.dts b/target/linux/realtek/dts-5.10/rtl8380_tplink_sg2210p-v3.dts deleted file mode 100644 index 4b0022c388..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_tplink_sg2210p-v3.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_tplink_sg2xxx.dtsi" - -/ { - compatible = "tplink,sg2210p-v3", "realtek,rtl838x-soc"; - model = "TP-Link SG2210P v3"; -}; - -&port24 { - label = "lan-sfp2"; -}; - -&port26 { - label = "lan-sfp1"; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_tplink_sg2xxx.dtsi b/target/linux/realtek/dts-5.10/rtl8380_tplink_sg2xxx.dtsi deleted file mode 100644 index e727a9405a..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_tplink_sg2xxx.dtsi +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl838x.dtsi" - -#include -#include - -/ { - aliases { - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - label-mac-device = ðernet0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - - led_power: led-0 { - label = "green:power"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; - }; - - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - tps23861_20: tps23861@20 { - compatible = "ti,tps23861"; - reg = <0x20>; - shunt-resistor-micro-ohms = <255000>; - }; - - tps23861_28: tps23861@28 { - compatible = "ti,tps23861"; - reg = <0x28>; - shunt-resistor-micro-ohms = <255000>; - }; - }; - - watchdog { - compatible = "linux,wdt-gpio"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - hw_algo = "toggle"; - /* SGM706 specs: typical 1.6s, but minimum 1.0s. */ - hw_margin_ms = <1000>; - }; -}; - -&gpio0 { - watchdog-enable { - gpio-hog; - gpios = <14 GPIO_ACTIVE_LOW>; - output-low; - line-name = "watchdog-enable"; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0xe0000>; - read-only; - }; - partition@e0000 { - label = "u-boot-env"; - reg = <0xe0000 0x20000>; - }; - partition@100000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0x100000 0x1a00000>; - }; - partition@1b00000 { - label = "usrappfs"; - reg = <0x1b00000 0x400000>; - }; - partition@1f00000 { - compatible = "nvmem-cells"; - label = "para"; - reg = <0x1f00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - - factory_macaddr: macaddr@fdff4 { - reg = <0xfdff4 0x6>; - }; - }; - }; - }; -}; - -ðernet0 { - nvmem-cells = <&factory_macaddr>; - nvmem-cell-names = "mac-address"; - - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - INTERNAL_PHY(24) - INTERNAL_PHY(26) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(15, 1, internal) - SWITCH_PORT(14, 2, internal) - SWITCH_PORT(13, 3, internal) - SWITCH_PORT(12, 4, internal) - SWITCH_PORT(11, 5, internal) - SWITCH_PORT(10, 6, internal) - SWITCH_PORT(9, 7, internal) - SWITCH_PORT(8, 8, internal) - - SWITCH_SFP_PORT(24, 9, 1000base-x) - SWITCH_SFP_PORT(26, 10, 1000base-x) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-10hp.dts b/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-10hp.dts deleted file mode 100644 index 82df6789a9..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-10hp.dts +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_zyxel_gs1900.dtsi" - -/ { - compatible = "zyxel,gs1900-10hp", "realtek,rtl838x-soc"; - model = "ZyXEL GS1900-10HP Switch"; - - /* i2c of the left SFP cage: port 9 */ - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-p9 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - /* i2c of the right SFP cage: port 10 */ - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-p10 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&mdio { - INTERNAL_PHY(24) - INTERNAL_PHY(26) -}; - -&switch0 { - ports { - port@24 { - reg = <24>; - label = "lan9"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp0>; - }; - - port@26 { - reg = <26>; - label = "lan10"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp1>; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8.dts b/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8.dts deleted file mode 100644 index e9c5efe603..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_zyxel_gs1900.dtsi" - -/ { - compatible = "zyxel,gs1900-8", "realtek,rtl838x-soc"; - model = "ZyXEL GS1900-8 Switch"; -}; - -&gpio1 { - /delete-node/ poe_enable; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8hp-v1.dts b/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8hp-v1.dts deleted file mode 100644 index 5ee340eac6..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8hp-v1.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_zyxel_gs1900.dtsi" - -/ { - compatible = "zyxel,gs1900-8hp-v1", "realtek,rtl838x-soc"; - model = "ZyXEL GS1900-8HP v1 Switch"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8hp-v2.dts b/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8hp-v2.dts deleted file mode 100644 index 0768462255..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8hp-v2.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_zyxel_gs1900.dtsi" - -/ { - compatible = "zyxel,gs1900-8hp-v2", "realtek,rtl838x-soc"; - model = "ZyXEL GS1900-8HP v2 Switch"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900.dtsi b/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900.dtsi deleted file mode 100644 index 5993c1b798..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl838x.dtsi" - -#include -#include - -/ { - aliases { - led-boot = &led_sys; - led-failsafe = &led_sys; - led-running = &led_sys; - led-upgrade = &led_sys; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - compatible = "gpio-leds"; - - led_sys: sys { - label = "green:sys"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - gpio-controller; - indirect-access-bus-id = <0>; - - poe_enable { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>; - output-high; - }; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x40000>; - read-only; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x10000>; - read-only; - }; - partition@50000 { - label = "u-boot-env2"; - reg = <0x50000 0x10000>; - }; - partition@60000 { - label = "jffs"; - reg = <0x60000 0x100000>; - }; - partition@160000 { - label = "jffs2"; - reg = <0x160000 0x100000>; - }; - partition@b260000 { - label = "firmware"; - reg = <0x260000 0x6d0000>; - compatible = "openwrt,uimage", "denx,uimage"; - openwrt,ih-magic = <0x83800000>; - }; - partition@930000 { - label = "runtime2"; - reg = <0x930000 0x6d0000>; - }; - }; - }; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_allnet_all-sg8208m.dts b/target/linux/realtek/dts-5.10/rtl8382_allnet_all-sg8208m.dts deleted file mode 100644 index 320cb08ac7..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_allnet_all-sg8208m.dts +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl838x.dtsi" - -#include -#include - -/ { - compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc"; - model = "ALLNET ALL-SG8208M"; - - aliases { - led-boot = &led_sys; - led-failsafe = &led_sys; - led-running = &led_sys; - led-upgrade = &led_sys; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - /* is this pin 3 on the external RTL8231 (&gpio1)? */ - /*reset { - label = "reset"; - gpios = <&gpio0 67 GPIO_ACTIVE_LOW>; - linux,code = ; - };*/ - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - compatible = "gpio-leds"; - - led_sys: sys { - label = "green:sys"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - // GPIO 25: power on/off all port leds - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u-boot-env"; - reg = <0x80000 0x10000>; - read-only; - }; - - partition@90000 { - label = "u-boot-env2"; - reg = <0x90000 0x10000>; - }; - - partition@a0000 { - label = "jffs"; - reg = <0xa0000 0x100000>; - }; - - partition@1a0000 { - label = "jffs2"; - reg = <0x1a0000 0x100000>; - }; - - partition@2a0000 { - label = "firmware"; - reg = <0x2a0000 0xd60000>; - compatible = "openwrt,uimage", "denx,uimage"; - openwrt,ih-magic = <0x00000006>; - }; - }; - }; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_apresia_aplgs120gtss.dts b/target/linux/realtek/dts-5.10/rtl8382_apresia_aplgs120gtss.dts deleted file mode 100644 index 15120265c9..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_apresia_aplgs120gtss.dts +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" - -#include -#include -#include - -/ { - compatible = "apresia,aplgs120gtss", "realtek,rtl8382-soc"; - model = "APRESIA ApresiaLightGS120GT-SS"; - - aliases { - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - leds { - compatible = "gpio-leds"; - - led_power: led-0 { - label = "green:pwr"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_POWER; - }; - - led-1 { - label = "red:loop"; - gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_FAULT; - }; - - /* LED chip is soldered, but no hole on the case */ - led-2 { - label = "green:unused"; - gpios = <&gpio1 36 GPIO_ACTIVE_LOW>; - color = ; - }; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio1 33 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio1 34 GPIO_ACTIVE_LOW>; - open-source; - }; - - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - gpio-controller; - indirect-access-bus-id = <0>; - }; - - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c-gpio-2 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c-gpio-3 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* 4x TX-Disable lines are provided by RTL8214FC */ - sfp0: sfp-p17 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; - }; - - sfp1: sfp-p18 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - }; - - sfp2: sfp-p19 { - compatible = "sff,sfp"; - i2c-bus = <&i2c3>; - los-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 24 GPIO_ACTIVE_LOW>; - }; - - sfp3: sfp-p20 { - compatible = "sff,sfp"; - i2c-bus = <&i2c2>; - los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; -}; - -&gpio0 { - rtl8231_reset { - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "rtl8231-reset"; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u-boot-env"; - reg = <0x80000 0x40000>; - }; - - partition@c0000 { - label = "u-boot-env2"; - reg = <0xc0000 0x40000>; - }; - - partition@100000 { - compatible = "openwrt,uimage", "denx,uimage"; - label = "firmware"; - reg = <0x100000 0xe80000>; - openwrt,ih-magic = <0x12345000>; - }; - - partition@f80000 { - label = "firmware2"; - reg = <0xf80000 0xe80000>; - }; - - partition@1e00000 { - label = "jffs2"; - reg = <0x1e00000 0x200000>; - read-only; - }; - }; - }; -}; - -ðernet0 { - mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - EXTERNAL_SFP_PHY_FULL(24, 0) - EXTERNAL_SFP_PHY_FULL(25, 1) - EXTERNAL_SFP_PHY_FULL(26, 2) - EXTERNAL_SFP_PHY_FULL(27, 3) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(24, 17, qsgmii) - SWITCH_PORT(25, 18, qsgmii) - SWITCH_PORT(26, 19, qsgmii) - SWITCH_PORT(27, 20, qsgmii) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-10p.dts b/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-10p.dts deleted file mode 100644 index 16934ede3b..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-10p.dts +++ /dev/null @@ -1,102 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl83xx_d-link_dgs-1210_common.dtsi" - -/ { - compatible = "d-link,dgs-1210-10p", "realtek,rtl838x-soc"; - model = "D-Link DGS-1210-10P"; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - mode { - label = "mode"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&gpio1 33 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - leds { - link_act { - label = "green:link_act"; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; - - poe { - label = "green:poe"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - - poe_max { - label = "yellow:poe_max"; - gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - }; - }; - - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - gpio-controller; - indirect-access-bus-id = <0>; - }; -}; - -&uart1 { - status = "okay"; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - INTERNAL_PHY(24) - INTERNAL_PHY(26) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - SWITCH_SFP_PORT(24, 9, rgmii-id) - SWITCH_SFP_PORT(26, 10, rgmii-id) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-16.dts b/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-16.dts deleted file mode 100644 index 35f41b9e4d..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-16.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl83xx_d-link_dgs-1210_common.dtsi" - -/ { - compatible = "d-link,dgs-1210-16", "realtek,rtl838x-soc"; - model = "D-Link DGS-1210-16"; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - EXTERNAL_SFP_PHY(24) - EXTERNAL_SFP_PHY(25) - EXTERNAL_SFP_PHY(26) - EXTERNAL_SFP_PHY(27) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(24, 17, qsgmii) - SWITCH_PORT(25, 18, qsgmii) - SWITCH_PORT(26, 19, qsgmii) - SWITCH_PORT(27, 20, qsgmii) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-20.dts b/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-20.dts deleted file mode 100644 index dacc50676d..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-20.dts +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl83xx_d-link_dgs-1210_common.dtsi" -#include "rtl83xx_d-link_dgs-1210_gpio.dtsi" - -/ { - compatible = "d-link,dgs-1210-20", "realtek,rtl838x-soc"; - model = "D-Link DGS-1210-20"; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - EXTERNAL_SFP_PHY(24) - EXTERNAL_SFP_PHY(25) - EXTERNAL_SFP_PHY(26) - EXTERNAL_SFP_PHY(27) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(24, 17, qsgmii) - SWITCH_PORT(25, 18, qsgmii) - SWITCH_PORT(26, 19, qsgmii) - SWITCH_PORT(27, 20, qsgmii) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28.dts b/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28.dts deleted file mode 100644 index 0bcb196b7c..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl83xx_d-link_dgs-1210_common.dtsi" -#include "rtl83xx_d-link_dgs-1210_gpio.dtsi" -#include "rtl8382_d-link_dgs-1210-28_common.dtsi" - -/ { - compatible = "d-link,dgs-1210-28", "realtek,rtl838x-soc"; - model = "D-Link DGS-1210-28"; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28_common.dtsi b/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28_common.dtsi deleted file mode 100644 index 17866d5f03..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28_common.dtsi +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - EXTERNAL_SFP_PHY(24) - EXTERNAL_SFP_PHY(25) - EXTERNAL_SFP_PHY(26) - EXTERNAL_SFP_PHY(27) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - SWITCH_PORT(24, 25, qsgmii) - SWITCH_PORT(25, 26, qsgmii) - SWITCH_PORT(26, 27, qsgmii) - SWITCH_PORT(27, 28, qsgmii) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28mp-f.dts b/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28mp-f.dts deleted file mode 100644 index ce008229b3..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28mp-f.dts +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl83xx_d-link_dgs-1210_common.dtsi" -#include "rtl83xx_d-link_dgs-1210_gpio.dtsi" -#include "rtl8382_d-link_dgs-1210-28_common.dtsi" - -/ { - compatible = "d-link,dgs-1210-28mp-f", "realtek,rtl8382-soc", "realtek,rtl838x-soc"; - model = "D-Link DGS-1210-28MP F"; -}; - -&leds { - link_act { - label = "green:link_act"; - gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; - }; - - poe { - label = "green:poe"; - gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - }; - - poe_max { - label = "yellow:poe_max"; - gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - }; -}; - -&keys { - mode { - label = "mode"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; -}; - -&uart1 { - status = "okay"; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-16g.dts b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-16g.dts deleted file mode 100644 index 59043b2f6f..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-16g.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl8382_hpe_1920.dtsi" - -/ { - compatible = "hpe,1920-16g", "realtek,rtl838x-soc"; - model = "HPE 1920-16G (JG923A)"; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - SWITCH_PORT(16, 9, qsgmii) - SWITCH_PORT(17, 10, qsgmii) - SWITCH_PORT(18, 11, qsgmii) - SWITCH_PORT(19, 12, qsgmii) - SWITCH_PORT(20, 13, qsgmii) - SWITCH_PORT(21, 14, qsgmii) - SWITCH_PORT(22, 15, qsgmii) - SWITCH_PORT(23, 16, qsgmii) - - SWITCH_PORT(24, 17, qsgmii) - SWITCH_PORT(25, 18, qsgmii) - SWITCH_PORT(26, 19, qsgmii) - SWITCH_PORT(27, 20, qsgmii) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts deleted file mode 100644 index 61781c708e..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920-24g.dts +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl8382_hpe_1920.dtsi" - -/ { - compatible = "hpe,1920-24g", "realtek,rtl838x-soc"; - model = "HPE 1920-24G (JG924A)"; -}; - -&mdio { - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - SWITCH_PORT(24, 25, qsgmii) - SWITCH_PORT(25, 26, qsgmii) - SWITCH_PORT(26, 27, qsgmii) - SWITCH_PORT(27, 28, qsgmii) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920.dtsi b/target/linux/realtek/dts-5.10/rtl8382_hpe_1920.dtsi deleted file mode 100644 index 5368b41c27..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_hpe_1920.dtsi +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl838x_hpe_1920.dtsi" - -/ { - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - gpio-controller; - indirect-access-bus-id = <0>; - }; - - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-0 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>; - // tx-fault unconnected - // tx-disable connected to RTL8214FC - }; - - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-1 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>; - // tx-fault unconnected - // tx-disable connected to RTL8214FC - }; - - i2c2: i2c-gpio-2 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp2: sfp-2 { - compatible = "sff,sfp"; - i2c-bus = <&i2c2>; - los-gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; - // tx-fault unconnected - // tx-disable connected to RTL8214FC - }; - - i2c3: i2c-gpio-3 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp3: sfp-3 { - compatible = "sff,sfp"; - i2c-bus = <&i2c3>; - los-gpio = <&gpio1 34 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 33 GPIO_ACTIVE_LOW>; - // tx-fault unconnected - // tx-disable connected to RTL8214FC - }; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - EXTERNAL_SFP_PHY_FULL(24, 0) - EXTERNAL_SFP_PHY_FULL(25, 1) - EXTERNAL_SFP_PHY_FULL(26, 2) - EXTERNAL_SFP_PHY_FULL(27, 3) - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_inaba_aml2-17gp.dts b/target/linux/realtek/dts-5.10/rtl8382_inaba_aml2-17gp.dts deleted file mode 100644 index 4808141494..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_inaba_aml2-17gp.dts +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" - -#include -#include - -/ { - compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc"; - model = "INABA Abaniact AML2-17GP"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u-boot-env"; - reg = <0x80000 0x10000>; - read-only; - }; - - partition@90000 { - label = "u-boot-env2"; - reg = <0x90000 0x10000>; - }; - - partition@a0000 { - label = "jffs2_cfg"; - reg = <0xa0000 0x400000>; - read-only; - }; - - partition@4a0000 { - label = "jffs2_log"; - reg = <0x4a0000 0x100000>; - read-only; - }; - - partition@5a0000 { - compatible = "openwrt,uimage", "denx,uimage"; - label = "firmware"; - reg = <0x5a0000 0xd30000>; - openwrt,ih-magic = <0x83800000>; - }; - - partition@12d0000 { - label = "runtime2"; - reg = <0x12d0000 0xd30000>; - }; - }; - }; -}; - -ðernet0 { - mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - EXTERNAL_PHY(24) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - SWITCH_PORT(16, 9, qsgmii) - SWITCH_PORT(17, 10, qsgmii) - SWITCH_PORT(18, 11, qsgmii) - SWITCH_PORT(19, 12, qsgmii) - SWITCH_PORT(20, 13, qsgmii) - SWITCH_PORT(21, 14, qsgmii) - SWITCH_PORT(22, 15, qsgmii) - SWITCH_PORT(23, 16, qsgmii) - - port@24 { - reg = <24>; - label = "wan"; - phy-handle = <&phy24>; - phy-mode = "qsgmii"; - }; - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_iodata_bsh-g24mb.dts b/target/linux/realtek/dts-5.10/rtl8382_iodata_bsh-g24mb.dts deleted file mode 100644 index d19960c108..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_iodata_bsh-g24mb.dts +++ /dev/null @@ -1,197 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" - -#include -#include -#include - -/ { - compatible = "iodata,bsh-g24mb", "realtek,rtl838x-soc"; - model = "I-O DATA BSH-G24MB"; - - aliases { - led-boot = &led_sys_loop; - led-failsafe = &led_sys_loop; - led-upgrade = &led_sys_loop; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - compatible = "gpio-leds"; - - led_sys_loop: led { - label = "red:sys_loop"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; - }; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - gpio-controller; - indirect-access-bus-id = <0>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u-boot-env"; - reg = <0x80000 0x10000>; - read-only; - }; - - partition@90000 { - label = "u-boot-env2"; - reg = <0x90000 0x10000>; - }; - - partition@a0000 { - label = "jffs2_cfg"; - reg = <0xa0000 0x100000>; - read-only; - }; - - partition@1a0000 { - label = "jffs2_log"; - reg = <0x1a0000 0x100000>; - read-only; - }; - - /* - * use 2x OS partitions in OpenWrt - * - * 0x2A0000-0x94FFFF: RUNTIME - * 0x950000-0xFFFFFF: RUNTIME2 (not used in stock) - */ - partition@2a0000 { - compatible = "openwrt,uimage", "denx,uimage"; - label = "firmware"; - reg = <0x2a0000 0xd60000>; - openwrt,ih-magic = <0x83800013>; - }; - }; - }; -}; - -ðernet0 { - mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_panasonic_m16eg-pn28160k.dts b/target/linux/realtek/dts-5.10/rtl8382_panasonic_m16eg-pn28160k.dts deleted file mode 100644 index c3b29a87ff..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_panasonic_m16eg-pn28160k.dts +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi" - -#include - -/ { - compatible = "panasonic,m16eg-pn28160k", "realtek,rtl8382-soc"; - model = "Panasonic Switch-M16eG PN28160K"; - - aliases { - led-boot = &led_status_eco_green; - led-failsafe = &led_status_eco_amber; - led-running = &led_status_eco_green; - led-upgrade = &led_status_eco_green; - }; - - /* - * sfp0/1 are "combo" port with each TP port (23/24), and they are - * connected to the RTL8218FB. Currently, there is no support for - * the chip and only TP ports work by the RTL8218D support. - */ - sfp0: sfp-p23 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - sfp1: sfp-p24 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; -}; - -&leds { - led_status_eco_amber: led-5 { - label = "amber:status_eco"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_STATUS; - function-enumerator = <1>; - }; - - led_status_eco_green: led-6 { - label = "green:status_eco"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_STATUS; - function-enumerator = <2>; - }; -}; - -&i2c_gpio_0 { - scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&i2c_gpio_1 { - scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&gpio2 { - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - - /* - * GPIO12 (IO1_4): RTL8218FB - * - * This GPIO pin should be specified as "reset-gpio" in mdio node, but - * RTL8218FB phy won't be configured on RTL8218D support in the current - * phy driver. So, ethernet ports on the phy will be broken after hard- - * resetting. - * (RTL8218FB phy will be detected as RTL8218D by the phy driver) - * At the moment, configure this GPIO pin as gpio-hog to avoid breaking - * by resetting. - */ - ext_switch_reset { - gpio-hog; - gpios = <12 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "ext-switch-reset"; - }; -}; - -&i2c_switch { - i2c0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; -}; - -ðernet0 { - mdio-bus { - compatible = "realtek,rtl838x-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - /* RTL8218FB */ - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(8, 1, internal) - SWITCH_PORT(9, 2, internal) - SWITCH_PORT(10, 3, internal) - SWITCH_PORT(11, 4, internal) - SWITCH_PORT(12, 5, internal) - SWITCH_PORT(13, 6, internal) - SWITCH_PORT(14, 7, internal) - SWITCH_PORT(15, 8, internal) - - SWITCH_PORT(16, 9, qsgmii) - SWITCH_PORT(17, 10, qsgmii) - SWITCH_PORT(18, 11, qsgmii) - SWITCH_PORT(19, 12, qsgmii) - SWITCH_PORT(20, 13, qsgmii) - SWITCH_PORT(21, 14, qsgmii) - SWITCH_PORT(22, 15, qsgmii) - SWITCH_PORT(23, 16, qsgmii) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_panasonic_m24eg-pn28240k.dts b/target/linux/realtek/dts-5.10/rtl8382_panasonic_m24eg-pn28240k.dts deleted file mode 100644 index 1fa9d2cdc7..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_panasonic_m24eg-pn28240k.dts +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl838x.dtsi" -#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi" - -#include - -/ { - compatible = "panasonic,m24eg-pn28240k", "realtek,rtl8382-soc"; - model = "Panasonic Switch-M24eG PN28240K"; - - aliases { - led-boot = &led_status_eco_green; - led-failsafe = &led_status_eco_amber; - led-running = &led_status_eco_green; - led-upgrade = &led_status_eco_green; - }; - - /* - * sfp0/1 are "combo" port with each TP port (23/24), and they are - * connected to the RTL8218FB. Currently, there is no support for - * the chip and only TP ports work by the RTL8218D support. - */ - sfp0: sfp-p23 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - sfp1: sfp-p24 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; -}; - -&leds { - led_status_eco_amber: led-5 { - label = "amber:status_eco"; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_STATUS; - function-enumerator = <1>; - }; - - led_status_eco_green: led-6 { - label = "green:status_eco"; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_STATUS; - function-enumerator = <2>; - }; -}; - -&i2c_gpio_0 { - scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&i2c_gpio_1 { - scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&gpio2 { - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - - /* - * GPIO12 (IO1_4): RTL8218B + RTL8218FB - * - * This GPIO pin should be specified as "reset-gpio" in mdio node, - * but the current configuration of RTL8218B phy in the phy driver - * seems to be incomplete and RTL8218FB phy won't be configured on - * RTL8218D support. So, ethernet ports on these phys will be broken - * after hard-resetting. - * (RTL8218FB phy will be detected as RTL8218D by the phy driver) - * At the moment, configure this GPIO pin as gpio-hog to avoid breaking - * by resetting. - */ - ext_switch_reset { - gpio-hog; - gpios = <12 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "ext-switch-reset"; - }; -}; - -&i2c_switch { - i2c0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; -}; - -ðernet0 { - mdio-bus { - compatible = "realtek,rtl838x-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - INTERNAL_PHY(8) - INTERNAL_PHY(9) - INTERNAL_PHY(10) - INTERNAL_PHY(11) - INTERNAL_PHY(12) - INTERNAL_PHY(13) - INTERNAL_PHY(14) - INTERNAL_PHY(15) - - /* RTL8218FB */ - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-16.dts b/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-16.dts deleted file mode 100644 index ac2eea7015..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-16.dts +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_zyxel_gs1900.dtsi" - -/ { - compatible = "zyxel,gs1900-16", "realtek,rtl838x-soc"; - model = "ZyXEL GS1900-16"; -}; - -&mdio { - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) -}; - -&switch0 { - ports { - SWITCH_PORT(16, 9, qsgmii) - SWITCH_PORT(17, 10, qsgmii) - SWITCH_PORT(18, 11, qsgmii) - SWITCH_PORT(19, 12, qsgmii) - SWITCH_PORT(20, 13, qsgmii) - SWITCH_PORT(21, 14, qsgmii) - SWITCH_PORT(22, 15, qsgmii) - SWITCH_PORT(23, 16, qsgmii) - }; -}; - -&gpio1 { - /delete-node/ poe_enable; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24-v1.dts b/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24-v1.dts deleted file mode 100644 index 81482dde10..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24-v1.dts +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_zyxel_gs1900.dtsi" - -/ { - compatible = "zyxel,gs1900-24-v1", "realtek,rtl838x-soc"; - model = "ZyXEL GS1900-24 v1"; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - /* i2c of the left SFP cage: port 25 */ - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-p25 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - /* i2c of the right SFP cage: port 26 */ - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-p26 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&mdio { - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - INTERNAL_PHY(24) - INTERNAL_PHY(26) -}; - -&switch0 { - ports { - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - port@24 { - reg = <24>; - label = "lan25"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp0>; - }; - - port@26 { - reg = <26>; - label = "lan26"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp1>; - }; - }; -}; - -&gpio1 { - /delete-node/ poe_enable; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24e.dts b/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24e.dts deleted file mode 100644 index 3d00034a3b..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24e.dts +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_zyxel_gs1900.dtsi" - -/ { - compatible = "zyxel,gs1900-24e", "realtek,rtl838x-soc"; - model = "ZyXEL GS1900-24E"; -}; - -&mdio { - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) -}; - -&switch0 { - ports { - SWITCH_PORT(1, 1, qsgmii) - SWITCH_PORT(0, 2, qsgmii) - SWITCH_PORT(3, 3, qsgmii) - SWITCH_PORT(2, 4, qsgmii) - SWITCH_PORT(5, 5, qsgmii) - SWITCH_PORT(4, 6, qsgmii) - SWITCH_PORT(7, 7, qsgmii) - SWITCH_PORT(6, 8, qsgmii) - - SWITCH_PORT(9, 9, internal) - SWITCH_PORT(8, 10, internal) - SWITCH_PORT(11, 11, internal) - SWITCH_PORT(10, 12, internal) - SWITCH_PORT(13, 13, internal) - SWITCH_PORT(12, 14, internal) - SWITCH_PORT(15, 15, internal) - SWITCH_PORT(14, 16, internal) - - SWITCH_PORT(17, 17, qsgmii) - SWITCH_PORT(16, 18, qsgmii) - SWITCH_PORT(19, 19, qsgmii) - SWITCH_PORT(18, 20, qsgmii) - SWITCH_PORT(21, 21, qsgmii) - SWITCH_PORT(20, 22, qsgmii) - SWITCH_PORT(23, 23, qsgmii) - SWITCH_PORT(22, 24, qsgmii) - }; -}; - -&gpio1 { - /delete-node/ poe_enable; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24hp-v1.dts b/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24hp-v1.dts deleted file mode 100644 index 7bb3410a31..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24hp-v1.dts +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_zyxel_gs1900.dtsi" - -/ { - compatible = "zyxel,gs1900-24hp-v1", "realtek,rtl838x-soc"; - model = "ZyXEL GS1900-24HP v1"; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - /* i2c of the left SFP cage: port 25 */ - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-p25 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - /* i2c of the right SFP cage: port 26 */ - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-p26 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&mdio { - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - INTERNAL_PHY(24) - INTERNAL_PHY(26) -}; - -&switch0 { - ports { - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - port@24 { - reg = <24>; - label = "lan25"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp0>; - }; - - port@26 { - reg = <26>; - label = "lan26"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp1>; - }; - }; -}; - diff --git a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24hp-v2.dts b/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24hp-v2.dts deleted file mode 100644 index 7b6a9a1e7f..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24hp-v2.dts +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include "rtl8380_zyxel_gs1900.dtsi" - -/ { - compatible = "zyxel,gs1900-24hp-v2", "realtek,rtl838x-soc"; - model = "ZyXEL GS1900-24HP v2 Switch"; - - /* i2c of the left SFP cage: port 25 */ - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-p25 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - /* i2c of the right SFP cage: port 26 */ - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-p26 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&mdio { - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - INTERNAL_PHY(24) - INTERNAL_PHY(26) -}; - -&switch0 { - ports { - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, internal) - SWITCH_PORT(9, 10, internal) - SWITCH_PORT(10, 11, internal) - SWITCH_PORT(11, 12, internal) - SWITCH_PORT(12, 13, internal) - SWITCH_PORT(13, 14, internal) - SWITCH_PORT(14, 15, internal) - SWITCH_PORT(15, 16, internal) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - - port@24 { - reg = <24>; - label = "lan25"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp0>; - }; - - port@26 { - reg = <26>; - label = "lan26"; - phy-mode = "1000base-x"; - managed = "in-band-status"; - sfp = <&sfp1>; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl838x.dtsi b/target/linux/realtek/dts-5.10/rtl838x.dtsi deleted file mode 100644 index 64e13e1ff3..0000000000 --- a/target/linux/realtek/dts-5.10/rtl838x.dtsi +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include - -/dts-v1/; - -#define STRINGIZE(s) #s -#define LAN_LABEL(p, s) STRINGIZE(p ## s) -#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n) - -#define INTERNAL_PHY(n) \ - phy##n: ethernet-phy@##n { \ - reg = <##n>; \ - compatible = "ethernet-phy-ieee802.3-c22"; \ - phy-is-integrated; \ - }; - -#define EXTERNAL_PHY(n) \ - phy##n: ethernet-phy@##n { \ - reg = <##n>; \ - compatible = "ethernet-phy-ieee802.3-c22"; \ - }; - -#define EXTERNAL_SFP_PHY(n) \ - phy##n: ethernet-phy@##n { \ - compatible = "ethernet-phy-ieee802.3-c22"; \ - sfp; \ - media = "fibre"; \ - reg = <##n>; \ - }; - -#define EXTERNAL_SFP_PHY_FULL(n, s) \ - phy##n: ethernet-phy@##n { \ - compatible = "ethernet-phy-ieee802.3-c22"; \ - sfp = <&sfp##s>; \ - reg = <##n>; \ - }; - -#define SWITCH_PORT(n, s, m) \ - port##n: port@##n { \ - reg = <##n>; \ - label = SWITCH_PORT_LABEL(s) ; \ - phy-handle = <&phy##n>; \ - phy-mode = #m ; \ - }; - -#define SWITCH_SFP_PORT(n, s, m) \ - port##n: port@##n { \ - reg = <##n>; \ - label = SWITCH_PORT_LABEL(s) ; \ - phy-handle = <&phy##n>; \ - phy-mode = #m ; \ - fixed-link { \ - speed = <1000>; \ - full-duplex; \ - }; \ - }; - -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "realtek,rtl838x-soc"; - - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - ccu: clock-controller { - compatible = "realtek,rtl8380-clock"; - #clock-cells = <1>; - clocks = <&osc>; - clock-names = "ref_clk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "mips,mips4KEc"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - operating-points-v2 = <&cpu_opp_table>; - }; - }; - - cpu_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <325000000>; - }; - opp01 { - opp-hz = /bits/ 64 <350000000>; - }; - opp02 { - opp-hz = /bits/ 64 <375000000>; - }; - opp03 { - opp-hz = /bits/ 64 <400000000>; - }; - opp04 { - opp-hz = /bits/ 64 <425000000>; - }; - opp05 { - opp-hz = /bits/ 64 <450000000>; - }; - opp06 { - opp-hz = /bits/ 64 <475000000>; - }; - opp07 { - opp-hz = /bits/ 64 <500000000>; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - cpuintc: cpuintc { - compatible = "mti,cpu-interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000000 0x10000>; - - intc: interrupt-controller@3000 { - compatible = "realtek,rtl8380-intc", "realtek,rtl-intc"; - reg = <0x3000 0x18>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>, <3>, <4>, <5>, <6>; - }; - - spi0: spi@1200 { - compatible = "realtek,rtl8380-spi"; - reg = <0x1200 0x100>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - timer0: timer@3100 { - compatible = "realtek,rtl8380-timer", "realtek,otto-timer"; - reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, - <0x3130 0x10>, <0x3140 0x10>; - - interrupt-parent = <&intc>; - interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; - clocks = <&ccu CLK_LXB>; - }; - - uart0: uart@2000 { - compatible = "ns16550a"; - reg = <0x2000 0x100>; - - clocks = <&ccu CLK_LXB>; - - interrupt-parent = <&intc>; - interrupts = <31 1>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - }; - - uart1: uart@2100 { - pinctrl-names = "default"; - pinctrl-0 = <&enable_uart1>; - - compatible = "ns16550a"; - reg = <0x2100 0x100>; - - clocks = <&ccu CLK_LXB>; - - interrupt-parent = <&intc>; - interrupts = <30 0>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - - status = "disabled"; - }; - - watchdog0: watchdog@3150 { - compatible = "realtek,rtl8380-wdt"; - reg = <0x3150 0xc>; - - realtek,reset-mode = "soc"; - - clocks = <&ccu CLK_LXB>; - timeout-sec = <30>; - - interrupt-parent = <&intc>; - interrupt-names = "phase1", "phase2"; - interrupts = <19 3>, <18 4>; - }; - - gpio0: gpio-controller@3500 { - compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio"; - reg = <0x3500 0x20>; - - gpio-controller; - #gpio-cells = <2>; - ngpios = <24>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <23 3>; - }; - }; - - pinmux: pinmux@1b001000 { - compatible = "pinctrl-single"; - reg = <0x1b001000 0x4>; - - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x1>; - #pinctrl-cells = <2>; - - enable_uart1: pinmux_enable_uart1 { - pinctrl-single,bits = <0x0 0x10 0x10>; - }; - }; - - /* LED_GLB_CTRL */ - pinmux_led: pinmux@1b00a000 { - compatible = "pinctrl-single"; - reg = <0x1b00a000 0x4>; - - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x1>; - #pinctrl-cells = <2>; - - /* enable GPIO 0 */ - pinmux_disable_sys_led: disable_sys_led { - pinctrl-single,bits = <0x0 0x0 0x8000>; - }; - }; - - ethernet0: ethernet@1b00a300 { - compatible = "realtek,rtl838x-eth"; - reg = <0x1b00a300 0x100>; - interrupt-parent = <&intc>; - interrupts = <24 3>; - #interrupt-cells = <1>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - sram0: sram@9f000000 { - compatible = "mmio-sram"; - reg = <0x9f000000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x9f000000 0x10000>; - }; - - switch0: switch@1b000000 { - compatible = "realtek,rtl83xx-switch"; - - interrupt-parent = <&intc>; - interrupts = <20 2>; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl838x_hpe_1920.dtsi b/target/linux/realtek/dts-5.10/rtl838x_hpe_1920.dtsi deleted file mode 100644 index 8e29af62bb..0000000000 --- a/target/linux/realtek/dts-5.10/rtl838x_hpe_1920.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include -#include - -/ { - chosen { - bootargs = "console=ttyS0,38400"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - watchdog1: watchdog { - // PT7A7514 - compatible = "linux,wdt-gpio"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - hw_algo = "toggle"; - hw_margin_ms = <1000>; - always-running; - - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - }; -}; - -&watchdog0 { - status = "disabled"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootware_basic"; - reg = <0x0 0x50000>; - read-only; - }; - - partition@0x60000 { - label = "bootware_data"; - reg = <0x60000 0x30000>; - read-only; - }; - - partition@0x90000 { - label = "bootware_extend"; - reg = <0x90000 0x40000>; - read-only; - }; - - partition@0x100000 { - label = "bootware_basic_backup"; - reg = <0x100000 0x50000>; - read-only; - }; - - partition@0x160000 { - label = "bootware_data_backup"; - reg = <0x160000 0x30000>; - read-only; - }; - - partition@0x190000 { - label = "bootware_extend_backup"; - reg = <0x190000 0x40000>; - read-only; - }; - - partition@0x300000 { - label = "firmware"; - compatible = "h3c,vfs-firmware"; - reg = <0x300000 0x1cf0000>; - }; - - partition@0x1ff0000 { - label = "factory"; - reg = <0x1ff0000 0x10000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8393_d-link_dgs-1210-52.dts b/target/linux/realtek/dts-5.10/rtl8393_d-link_dgs-1210-52.dts deleted file mode 100644 index 5b876e7c43..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8393_d-link_dgs-1210-52.dts +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl839x.dtsi" -#include "rtl83xx_d-link_dgs-1210_common.dtsi" -#include "rtl83xx_d-link_dgs-1210_gpio.dtsi" -#include "rtl839x_d-link_dgs-1210_gpio.dtsi" - -/ { - compatible = "d-link,dgs-1210-52", "realtek,rtl8393-soc"; - model = "D-Link DGS-1210-52"; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - /* External phy RTL8218B #1 */ - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - /* External phy RTL8218B #2 */ - EXTERNAL_PHY(8) - EXTERNAL_PHY(9) - EXTERNAL_PHY(10) - EXTERNAL_PHY(11) - EXTERNAL_PHY(12) - EXTERNAL_PHY(13) - EXTERNAL_PHY(14) - EXTERNAL_PHY(15) - - /* External phy RTL8218B #3 */ - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - /* External phy RTL8218B #4 */ - EXTERNAL_PHY(24) - EXTERNAL_PHY(25) - EXTERNAL_PHY(26) - EXTERNAL_PHY(27) - EXTERNAL_PHY(28) - EXTERNAL_PHY(29) - EXTERNAL_PHY(30) - EXTERNAL_PHY(31) - - /* External phy RTL8218B #5 */ - EXTERNAL_PHY(32) - EXTERNAL_PHY(33) - EXTERNAL_PHY(34) - EXTERNAL_PHY(35) - EXTERNAL_PHY(36) - EXTERNAL_PHY(37) - EXTERNAL_PHY(38) - EXTERNAL_PHY(39) - - /* External phy RTL8218B #6 */ - EXTERNAL_PHY(40) - EXTERNAL_PHY(41) - EXTERNAL_PHY(42) - EXTERNAL_PHY(43) - EXTERNAL_PHY(44) - EXTERNAL_PHY(45) - EXTERNAL_PHY(46) - EXTERNAL_PHY(47) - - /* External phy RTL8214FC */ - EXTERNAL_SFP_PHY_FULL(48, 0) - EXTERNAL_SFP_PHY_FULL(49, 1) - EXTERNAL_SFP_PHY_FULL(50, 2) - EXTERNAL_SFP_PHY_FULL(51, 3) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, qsgmii) - SWITCH_PORT(9, 10, qsgmii) - SWITCH_PORT(10, 11, qsgmii) - SWITCH_PORT(11, 12, qsgmii) - SWITCH_PORT(12, 13, qsgmii) - SWITCH_PORT(13, 14, qsgmii) - SWITCH_PORT(14, 15, qsgmii) - SWITCH_PORT(15, 16, qsgmii) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - SWITCH_PORT(24, 25, qsgmii) - SWITCH_PORT(25, 26, qsgmii) - SWITCH_PORT(26, 27, qsgmii) - SWITCH_PORT(27, 28, qsgmii) - SWITCH_PORT(28, 29, qsgmii) - SWITCH_PORT(29, 30, qsgmii) - SWITCH_PORT(30, 31, qsgmii) - SWITCH_PORT(31, 32, qsgmii) - - SWITCH_PORT(32, 33, qsgmii) - SWITCH_PORT(33, 34, qsgmii) - SWITCH_PORT(34, 35, qsgmii) - SWITCH_PORT(35, 36, qsgmii) - SWITCH_PORT(36, 37, qsgmii) - SWITCH_PORT(37, 38, qsgmii) - SWITCH_PORT(38, 39, qsgmii) - SWITCH_PORT(39, 40, qsgmii) - - SWITCH_PORT(40, 41, qsgmii) - SWITCH_PORT(41, 42, qsgmii) - SWITCH_PORT(42, 43, qsgmii) - SWITCH_PORT(43, 44, qsgmii) - SWITCH_PORT(44, 45, qsgmii) - SWITCH_PORT(45, 46, qsgmii) - SWITCH_PORT(46, 47, qsgmii) - SWITCH_PORT(47, 48, qsgmii) - - SWITCH_PORT(48, 49, qsgmii) - SWITCH_PORT(49, 50, qsgmii) - SWITCH_PORT(50, 51, qsgmii) - SWITCH_PORT(51, 52, qsgmii) - - /* CPU-Port */ - port@52 { - ethernet = <ðernet0>; - reg = <52>; - phy-mode = "qsgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8393_netgear_gs750e.dts b/target/linux/realtek/dts-5.10/rtl8393_netgear_gs750e.dts deleted file mode 100644 index 750af3e94f..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8393_netgear_gs750e.dts +++ /dev/null @@ -1,252 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl839x.dtsi" - -#include -#include - -/ { - compatible = "netgear,gs750e", "realtek,rtl8393-soc"; - model = "Netgear GS750E"; - - aliases { - label-mac-device = ðernet0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - }; - - virtual_flash { - compatible = "mtd-concat"; - - devices = <&fwconcat0>, <&fwconcat1>, <&fwconcat2>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "firmware"; - reg = <0x0 0x760000>; - compatible = "openwrt,uimage", "denx,uimage"; - openwrt,ih-magic = <0x174e4741>; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u-boot-env"; - reg = <0x80000 0x10000>; - read-only; - }; - - partition@90000 { - label = "u-boot-env2"; - reg = <0x90000 0x10000>; - read-only; - }; - - fwconcat1: partition@a0000 { - label = "jffs2_cfg"; - reg = <0xa0000 0x80000>; - }; - - fwconcat2: partition@120000 { - label = "jffs2_log"; - reg = <0x120000 0x80000>; - }; - - fwconcat0: partition@1a0000 { - label = "runtime"; - reg = <0x1a0000 0x660000>; - }; - }; - }; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - - /* External phy RTL8218B #1 */ - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - /* External phy RTL8218B #2 */ - EXTERNAL_PHY(8) - EXTERNAL_PHY(9) - EXTERNAL_PHY(10) - EXTERNAL_PHY(11) - EXTERNAL_PHY(12) - EXTERNAL_PHY(13) - EXTERNAL_PHY(14) - EXTERNAL_PHY(15) - - /* External phy RTL8218B #3 */ - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - /* External phy RTL8218B #4 */ - EXTERNAL_PHY(24) - EXTERNAL_PHY(25) - EXTERNAL_PHY(26) - EXTERNAL_PHY(27) - EXTERNAL_PHY(28) - EXTERNAL_PHY(29) - EXTERNAL_PHY(30) - EXTERNAL_PHY(31) - - /* External phy RTL8218B #5 */ - EXTERNAL_PHY(32) - EXTERNAL_PHY(33) - EXTERNAL_PHY(34) - EXTERNAL_PHY(35) - EXTERNAL_PHY(36) - EXTERNAL_PHY(37) - EXTERNAL_PHY(38) - EXTERNAL_PHY(39) - - /* External phy RTL8218B #6 */ - EXTERNAL_PHY(40) - EXTERNAL_PHY(41) - EXTERNAL_PHY(42) - EXTERNAL_PHY(43) - EXTERNAL_PHY(44) - EXTERNAL_PHY(45) - EXTERNAL_PHY(46) - EXTERNAL_PHY(47) - - /* RTL8393 Internal SerDes */ - INTERNAL_PHY(48) - INTERNAL_PHY(49) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, qsgmii) - SWITCH_PORT(9, 0, qsgmii) - SWITCH_PORT(10, 11, qsgmii) - SWITCH_PORT(11, 12, qsgmii) - SWITCH_PORT(12, 13, qsgmii) - SWITCH_PORT(13, 14, qsgmii) - SWITCH_PORT(14, 15, qsgmii) - SWITCH_PORT(15, 16, qsgmii) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - SWITCH_PORT(24, 25, qsgmii) - SWITCH_PORT(25, 26, qsgmii) - SWITCH_PORT(26, 27, qsgmii) - SWITCH_PORT(27, 28, qsgmii) - SWITCH_PORT(28, 29, qsgmii) - SWITCH_PORT(29, 30, qsgmii) - SWITCH_PORT(30, 31, qsgmii) - SWITCH_PORT(31, 32, qsgmii) - - SWITCH_PORT(32, 33, qsgmii) - SWITCH_PORT(33, 34, qsgmii) - SWITCH_PORT(34, 35, qsgmii) - SWITCH_PORT(35, 36, qsgmii) - SWITCH_PORT(36, 37, qsgmii) - SWITCH_PORT(37, 38, qsgmii) - SWITCH_PORT(38, 39, qsgmii) - SWITCH_PORT(39, 40, qsgmii) - - SWITCH_PORT(40, 41, qsgmii) - SWITCH_PORT(41, 42, qsgmii) - SWITCH_PORT(42, 43, qsgmii) - SWITCH_PORT(43, 44, qsgmii) - SWITCH_PORT(44, 45, qsgmii) - SWITCH_PORT(45, 46, qsgmii) - SWITCH_PORT(46, 47, qsgmii) - SWITCH_PORT(47, 48, qsgmii) - - /* SFP cages */ - SWITCH_SFP_PORT(48, 49, sgmii) - SWITCH_SFP_PORT(49, 50, sgmii) - - /* CPU-Port */ - port@52 { - ethernet = <ðernet0>; - reg = <52>; - phy-mode = "qsgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8393_panasonic_m48eg-pn28480k.dts b/target/linux/realtek/dts-5.10/rtl8393_panasonic_m48eg-pn28480k.dts deleted file mode 100644 index 6a7eb6eb81..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8393_panasonic_m48eg-pn28480k.dts +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl839x.dtsi" -#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi" - -#include - -/ { - compatible = "panasonic,m48eg-pn28480k", "realtek,rtl8393-soc"; - model = "Panasonic Switch-M48eG PN28480K"; - - aliases { - led-boot = &led_status_eco_green; - led-failsafe = &led_status_eco_amber; - led-running = &led_status_eco_green; - led-upgrade = &led_status_eco_green; - }; - - fan: gpio-fan { - compatible = "gpio-fan"; - gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - /* the actual speeds (rpm) are unknown, just use dummy values */ - gpio-fan,speed-map = <1 0>, <2 1>; - #cooling-cells = <2>; - }; - - /* - * sfp0/1/2/3 are "combo" port with each TP port (45/46/47/48), - * and they are connected to the RTL8218FB. Currently, there is - * no support for the chip and only TP ports work by the RTL8218B - * support. - */ - sfp0: sfp-p45 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; - }; - - sfp1: sfp-p46 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; - - sfp2: sfp-p47 { - compatible = "sff,sfp"; - i2c-bus = <&i2c2>; - tx-fault-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; - }; - - sfp3: sfp-p48 { - compatible = "sff,sfp"; - i2c-bus = <&i2c3>; - tx-fault-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>; - los-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - - thermal-zones { - /* - * Zone for SoC temperature - * - * Fan speed: - * - * - 0-44 celsius: Low - * - 45-54 celsius: High - */ - cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <2000>; - - thermal-sensors = <&tsens_soc>; - - trips { - cpu_alert: trip-point { - temperature = <45000>; - hysteresis = <4000>; - type = "active"; - }; - - cpu_crit { - temperature = <55000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map { - trip = <&cpu_alert>; - cooling-device = <&fan 0 1>; - }; - }; - }; - - /* - * Zone for system temperature - * - * Fan speed: - * - * - 0-39 celsius: Low - * - 40-49 celsius: High - * - * Note: official recommended ranges of temperature on each - * fan speed setting: - * - * - Low speed : 0-40 celsius - * - High speed: 0-50 celsius - * - * (stock firmware doesn't support auto-selection of - * speed and need to be selected manually by user) - */ - sys-thermal { - polling-delay-passive = <1000>; - polling-delay = <2000>; - - thermal-sensors = <&tsens_sys>; - - trips { - sys_alert: trip-point { - temperature = <40000>; - hysteresis = <4000>; - type = "active"; - }; - - sys_crit { - temperature = <50000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map { - trip = <&sys_alert>; - cooling-device = <&fan 0 1>; - }; - }; - }; - }; -}; - -&leds { - led_status_eco_amber: led-5 { - label = "amber:status_eco"; - gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; - function-enumerator = <1>; - }; - - led_status_eco_green: led-6 { - label = "green:status_eco"; - gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; - function-enumerator = <2>; - }; -}; - -&i2c_gpio_0 { - scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - - /* Microchip TCN75A (for SoC) */ - tsens_soc: sensor@48 { - compatible = "microchip,tcn75"; - reg = <0x48>; - #thermal-sensor-cells = <0>; - }; - - /* Microchip TCN75A (for System) */ - tsens_sys: sensor@49 { - compatible = "microchip,tcn75"; - reg = <0x49>; - #thermal-sensor-cells = <0>; - }; -}; - -&i2c_gpio_1 { - scl-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -&gpio2 { - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - - /* - * GPIO12 (IO1_4): 5x RTL8218B + RTL8218FB - * - * This GPIO pin should be specified as "reset-gpio" in mdio node, - * but the current configuration of RTL8218B phy in the phy driver - * seems to be incomplete and RTL8218FB phy won't be configured on - * RTL8218D support. So, ethernet ports on these phys will be broken - * after hard-resetting. - * (RTL8218FB phy will be detected as RTL8218D by the phy driver) - * At the moment, configure this GPIO pin as gpio-hog to avoid breaking - * by resetting. - */ - ext_switch_reset { - gpio-hog; - gpios = <12 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "ext-switch-reset"; - }; -}; - -&i2c_switch { - i2c0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; -}; - -ðernet0 { - mdio-bus { - compatible = "realtek,rtl838x-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - EXTERNAL_PHY(8) - EXTERNAL_PHY(9) - EXTERNAL_PHY(10) - EXTERNAL_PHY(11) - EXTERNAL_PHY(12) - EXTERNAL_PHY(13) - EXTERNAL_PHY(14) - EXTERNAL_PHY(15) - - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - EXTERNAL_PHY(24) - EXTERNAL_PHY(25) - EXTERNAL_PHY(26) - EXTERNAL_PHY(27) - EXTERNAL_PHY(28) - EXTERNAL_PHY(29) - EXTERNAL_PHY(30) - EXTERNAL_PHY(31) - - EXTERNAL_PHY(32) - EXTERNAL_PHY(33) - EXTERNAL_PHY(34) - EXTERNAL_PHY(35) - EXTERNAL_PHY(36) - EXTERNAL_PHY(37) - EXTERNAL_PHY(38) - EXTERNAL_PHY(39) - - /* RTL8218FB */ - EXTERNAL_PHY(40) - EXTERNAL_PHY(41) - EXTERNAL_PHY(42) - EXTERNAL_PHY(43) - EXTERNAL_PHY(44) - EXTERNAL_PHY(45) - EXTERNAL_PHY(46) - EXTERNAL_PHY(47) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 1, qsgmii) - SWITCH_PORT(1, 2, qsgmii) - SWITCH_PORT(2, 3, qsgmii) - SWITCH_PORT(3, 4, qsgmii) - SWITCH_PORT(4, 5, qsgmii) - SWITCH_PORT(5, 6, qsgmii) - SWITCH_PORT(6, 7, qsgmii) - SWITCH_PORT(7, 8, qsgmii) - - SWITCH_PORT(8, 9, qsgmii) - SWITCH_PORT(9, 10, qsgmii) - SWITCH_PORT(10, 11, qsgmii) - SWITCH_PORT(11, 12, qsgmii) - SWITCH_PORT(12, 13, qsgmii) - SWITCH_PORT(13, 14, qsgmii) - SWITCH_PORT(14, 15, qsgmii) - SWITCH_PORT(15, 16, qsgmii) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - SWITCH_PORT(24, 25, qsgmii) - SWITCH_PORT(25, 26, qsgmii) - SWITCH_PORT(26, 27, qsgmii) - SWITCH_PORT(27, 28, qsgmii) - SWITCH_PORT(28, 29, qsgmii) - SWITCH_PORT(29, 30, qsgmii) - SWITCH_PORT(30, 31, qsgmii) - SWITCH_PORT(31, 32, qsgmii) - - SWITCH_PORT(32, 33, qsgmii) - SWITCH_PORT(33, 34, qsgmii) - SWITCH_PORT(34, 35, qsgmii) - SWITCH_PORT(35, 36, qsgmii) - SWITCH_PORT(36, 37, qsgmii) - SWITCH_PORT(37, 38, qsgmii) - SWITCH_PORT(38, 39, qsgmii) - SWITCH_PORT(39, 40, qsgmii) - - SWITCH_PORT(40, 41, qsgmii) - SWITCH_PORT(41, 42, qsgmii) - SWITCH_PORT(42, 43, qsgmii) - SWITCH_PORT(43, 44, qsgmii) - SWITCH_PORT(44, 45, qsgmii) - SWITCH_PORT(45, 46, qsgmii) - SWITCH_PORT(46, 47, qsgmii) - SWITCH_PORT(47, 48, qsgmii) - - port@52 { - ethernet = <ðernet0>; - reg = <52>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8393_tplink_sg2452p-v4.dts b/target/linux/realtek/dts-5.10/rtl8393_tplink_sg2452p-v4.dts deleted file mode 100644 index b7300cfcbe..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8393_tplink_sg2452p-v4.dts +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include "rtl839x.dtsi" - -#include -#include -#include - -/ { - compatible = "tplink,sg2452p-v4", "realtek,rtl8393-soc"; - model = "TP-Link SG2452P v4"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - aliases { - led-boot = &led_sys; - led-failsafe = &led_sys; - led-running = &led_sys; - led-upgrade = &led_sys; - label-mac-device = ðernet0; - }; - - chosen { - bootargs = "console=ttyS0,38400"; - }; - - keys { - compatible = "gpio-keys"; - - reset { - label = "reset"; - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - speed { - label = "speed"; - gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio_fan_sys { - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - }; - - gpio_fan_psu_1 { - pinctrl-names = "default"; - pinctrl-0 = <&disable_jtag>; - compatible = "gpio-fan"; - - alarm-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - /* the actual speeds (rpm) are unknown, just use dummy values */ - gpio-fan,speed-map = <1 0>, <2 1>; - #cooling-cells = <2>; - }; - - gpio_fan_psu_2 { - /* This fan runs in parallel to PSU1 fan, but has a separate - * alarm GPIO. This is not (yet) supported by the gpio-fan driver, - * so a separate instance is added - */ - compatible = "gpio-fan"; - alarm-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - }; - - leds { - pinctrl-names = "default"; - compatible = "gpio-leds"; - - led-0 { - label = "green:speed"; - gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - }; - - led-1 { - label = "green:poe"; - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - }; - - led_sys: led-2 { - label = "green:sys"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; - }; - - led-3 { - label = "green:fan"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; - }; - - led-4 { - label = "amber:fan"; - gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - color = ; - function = "fault-fan"; - }; - - led-5 { - label = "green:poe-max"; - gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; - color = ; - function = "alarm-poe"; - }; - }; - - i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - /* LAN9 - LAN12 */ - tps23861@5 { - compatible = "ti,tps23861"; - reg = <0x05>; - }; - - /* LAN17 - LAN20 */ - tps23861@6 { - compatible = "ti,tps23861"; - reg = <0x06>; - }; - - /* LAN45 - LAN48 */ - tps23861@9 { - compatible = "ti,tps23861"; - reg = <0x09>; - }; - - /* LAN37 - LAN40 */ - tps23861@a { - compatible = "ti,tps23861"; - reg = <0x0a>; - }; - - /* LAN1 - LAN4 */ - tps23861@14 { - compatible = "ti,tps23861"; - reg = <0x14>; - }; - - /* LAN25 - LAN28 */ - tps23861@24 { - compatible = "ti,tps23861"; - reg = <0x24>; - }; - - /* LAN33 - LAN 36 */ - tps23861@25 { - compatible = "ti,tps23861"; - reg = <0x25>; - }; - - /* LAN41 - LAN44 */ - tps23861@26 { - compatible = "ti,tps23861"; - reg = <0x26>; - }; - - /* LAN13 - LAN16 */ - tps23861@29 { - compatible = "ti,tps23861"; - reg = <0x29>; - }; - - /* LAN29 - LAN32 */ - tps23861@2c { - compatible = "ti,tps23861"; - reg = <0x2c>; - }; - - /* LAN5 - LAN8 */ - tps23861@48 { - compatible = "ti,tps23861"; - reg = <0x48>; - }; - - /* LAN21 - LAN24 */ - tps23861@49 { - compatible = "ti,tps23861"; - reg = <0x49>; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; -}; - -&gpio0 { - poe-enable { - gpio-hog; - gpios = <23 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "poe-enable"; - }; -}; - -&spi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0xe0000>; - read-only; - }; - partition@e0000 { - label = "u-boot-env"; - reg = <0xe0000 0x20000>; - }; - - /* We use the "sys", "usrimg1" and "usrimg2" partitions - * as firmware since the kernel needs to be in "sys", but the - * partition is too small to hold the "rootfs" as well. - * The original partition map contains: - * - * partition@100000 { - * label = "sys"; - * reg = <0x100000 0x600000>; - * }; - * partition@700000 { - * label = "usrimg1"; - * reg = <0x700000 0xa00000>; - * }; - * partition@1100000 { - * label = "usrimg2"; - * reg = <0x1100000 0xa00000>; - * }; - */ - - partition@100000 { - label = "firmware"; - reg = <0x100000 0x1a00000>; - }; - partition@1b00000 { - label = "usrappfs"; - reg = <0x1b00000 0x400000>; - }; - partition@1f00000 { - compatible = "nvmem-cells"; - label = "para"; - reg = <0x1f00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - - factory_macaddr: macaddr@fdff4 { - reg = <0xfdff4 0x6>; - }; - }; - }; - }; -}; - -ðernet0 { - nvmem-cells = <&factory_macaddr>; - nvmem-cell-names = "mac-address"; - - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - /* External phy RTL8218B #1 */ - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - /* External phy RTL8218B #2 */ - EXTERNAL_PHY(8) - EXTERNAL_PHY(9) - EXTERNAL_PHY(10) - EXTERNAL_PHY(11) - EXTERNAL_PHY(12) - EXTERNAL_PHY(13) - EXTERNAL_PHY(14) - EXTERNAL_PHY(15) - - /* External phy RTL8218B #3 */ - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - /* External phy RTL8218B #4 */ - EXTERNAL_PHY(24) - EXTERNAL_PHY(25) - EXTERNAL_PHY(26) - EXTERNAL_PHY(27) - EXTERNAL_PHY(28) - EXTERNAL_PHY(29) - EXTERNAL_PHY(30) - EXTERNAL_PHY(31) - - /* External phy RTL8218B #5 */ - EXTERNAL_PHY(32) - EXTERNAL_PHY(33) - EXTERNAL_PHY(34) - EXTERNAL_PHY(35) - EXTERNAL_PHY(36) - EXTERNAL_PHY(37) - EXTERNAL_PHY(38) - EXTERNAL_PHY(39) - - /* External phy RTL8218B #6 */ - EXTERNAL_PHY(40) - EXTERNAL_PHY(41) - EXTERNAL_PHY(42) - EXTERNAL_PHY(43) - EXTERNAL_PHY(44) - EXTERNAL_PHY(45) - EXTERNAL_PHY(46) - EXTERNAL_PHY(47) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 01, qsgmii) - SWITCH_PORT(1, 02, qsgmii) - SWITCH_PORT(2, 03, qsgmii) - SWITCH_PORT(3, 04, qsgmii) - SWITCH_PORT(4, 05, qsgmii) - SWITCH_PORT(5, 06, qsgmii) - SWITCH_PORT(6, 07, qsgmii) - SWITCH_PORT(7, 08, qsgmii) - - SWITCH_PORT(8, 09, qsgmii) - SWITCH_PORT(9, 10, qsgmii) - SWITCH_PORT(10, 11, qsgmii) - SWITCH_PORT(11, 12, qsgmii) - SWITCH_PORT(12, 13, qsgmii) - SWITCH_PORT(13, 14, qsgmii) - SWITCH_PORT(14, 15, qsgmii) - SWITCH_PORT(15, 16, qsgmii) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - SWITCH_PORT(24, 25, qsgmii) - SWITCH_PORT(25, 26, qsgmii) - SWITCH_PORT(26, 27, qsgmii) - SWITCH_PORT(27, 28, qsgmii) - SWITCH_PORT(28, 29, qsgmii) - SWITCH_PORT(29, 30, qsgmii) - SWITCH_PORT(30, 31, qsgmii) - SWITCH_PORT(31, 32, qsgmii) - - SWITCH_PORT(32, 33, qsgmii) - SWITCH_PORT(33, 34, qsgmii) - SWITCH_PORT(34, 35, qsgmii) - SWITCH_PORT(35, 36, qsgmii) - SWITCH_PORT(36, 37, qsgmii) - SWITCH_PORT(37, 38, qsgmii) - SWITCH_PORT(38, 39, qsgmii) - SWITCH_PORT(39, 40, qsgmii) - - SWITCH_PORT(40, 41, qsgmii) - SWITCH_PORT(41, 42, qsgmii) - SWITCH_PORT(42, 43, qsgmii) - SWITCH_PORT(43, 44, qsgmii) - SWITCH_PORT(44, 45, qsgmii) - SWITCH_PORT(45, 46, qsgmii) - SWITCH_PORT(46, 47, qsgmii) - SWITCH_PORT(47, 48, qsgmii) - - /* CPU-Port */ - port@52 { - ethernet = <ðernet0>; - reg = <52>; - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts b/target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts deleted file mode 100644 index c7ddd8313a..0000000000 --- a/target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts +++ /dev/null @@ -1,320 +0,0 @@ -/dts-v1/; - -#include "rtl839x.dtsi" - -#include -#include - -/ { - compatible = "zyxel,gs1900-48", "realtek,rtl8393-soc"; - model = "Zyxel GS1900-48"; - - aliases { - led-boot = &led_sys; - led-failsafe = &led_sys; - led-running = &led_sys; - led-upgrade = &led_sys; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - compatible = "gpio-leds"; - - led_sys: sys { - label = "green:sys"; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - indirect-access-bus-id = <3>; - gpio-controller; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - - keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - mode { - label = "reset"; - gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - /* i2c of the left SFP cage: port 49 */ - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-p9 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - }; - - /* i2c of the right SFP cage: port 50 */ - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-p10 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; - }; -}; - -&spi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x40000>; - read-only; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x10000>; - read-only; - }; - partition@50000 { - label = "u-boot-env2"; - reg = <0x50000 0x10000>; - read-only; - }; - partition@60000 { - label = "jffs"; - reg = <0x60000 0x100000>; - }; - partition@160000 { - label = "jffs2"; - reg = <0x160000 0x100000>; - }; - partition@260000 { - label = "firmware"; - reg = <0x260000 0x6d0000>; - compatible = "openwrt,uimage", "denx,uimage"; - openwrt,ih-magic = <0x83800000>; - }; - partition@930000 { - label = "runtime2"; - reg = <0x930000 0x6d0000>; - }; - }; - }; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - /* External phy RTL8218B #1 */ - EXTERNAL_PHY(0) - EXTERNAL_PHY(1) - EXTERNAL_PHY(2) - EXTERNAL_PHY(3) - EXTERNAL_PHY(4) - EXTERNAL_PHY(5) - EXTERNAL_PHY(6) - EXTERNAL_PHY(7) - - /* External phy RTL8218B #2 */ - EXTERNAL_PHY(8) - EXTERNAL_PHY(9) - EXTERNAL_PHY(10) - EXTERNAL_PHY(11) - EXTERNAL_PHY(12) - EXTERNAL_PHY(13) - EXTERNAL_PHY(14) - EXTERNAL_PHY(15) - - /* External phy RTL8218B #3 */ - EXTERNAL_PHY(16) - EXTERNAL_PHY(17) - EXTERNAL_PHY(18) - EXTERNAL_PHY(19) - EXTERNAL_PHY(20) - EXTERNAL_PHY(21) - EXTERNAL_PHY(22) - EXTERNAL_PHY(23) - - /* External phy RTL8218B #4 */ - EXTERNAL_PHY(24) - EXTERNAL_PHY(25) - EXTERNAL_PHY(26) - EXTERNAL_PHY(27) - EXTERNAL_PHY(28) - EXTERNAL_PHY(29) - EXTERNAL_PHY(30) - EXTERNAL_PHY(31) - - /* External phy RTL8218B #5 */ - EXTERNAL_PHY(32) - EXTERNAL_PHY(33) - EXTERNAL_PHY(34) - EXTERNAL_PHY(35) - EXTERNAL_PHY(36) - EXTERNAL_PHY(37) - EXTERNAL_PHY(38) - EXTERNAL_PHY(39) - - /* External phy RTL8218B #6 */ - EXTERNAL_PHY(40) - EXTERNAL_PHY(41) - EXTERNAL_PHY(42) - EXTERNAL_PHY(43) - EXTERNAL_PHY(44) - EXTERNAL_PHY(45) - EXTERNAL_PHY(46) - EXTERNAL_PHY(47) - - /* RTL8393 Internal SerDes */ - INTERNAL_PHY(48) - INTERNAL_PHY(49) - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - SWITCH_PORT(0, 01, qsgmii) - SWITCH_PORT(1, 02, qsgmii) - SWITCH_PORT(2, 03, qsgmii) - SWITCH_PORT(3, 04, qsgmii) - SWITCH_PORT(4, 05, qsgmii) - SWITCH_PORT(5, 06, qsgmii) - SWITCH_PORT(6, 07, qsgmii) - SWITCH_PORT(7, 08, qsgmii) - - SWITCH_PORT(8, 09, qsgmii) - SWITCH_PORT(9, 10, qsgmii) - SWITCH_PORT(10, 11, qsgmii) - SWITCH_PORT(11, 12, qsgmii) - SWITCH_PORT(12, 13, qsgmii) - SWITCH_PORT(13, 14, qsgmii) - SWITCH_PORT(14, 15, qsgmii) - SWITCH_PORT(15, 16, qsgmii) - - SWITCH_PORT(16, 17, qsgmii) - SWITCH_PORT(17, 18, qsgmii) - SWITCH_PORT(18, 19, qsgmii) - SWITCH_PORT(19, 20, qsgmii) - SWITCH_PORT(20, 21, qsgmii) - SWITCH_PORT(21, 22, qsgmii) - SWITCH_PORT(22, 23, qsgmii) - SWITCH_PORT(23, 24, qsgmii) - - SWITCH_PORT(24, 25, qsgmii) - SWITCH_PORT(25, 26, qsgmii) - SWITCH_PORT(26, 27, qsgmii) - SWITCH_PORT(27, 28, qsgmii) - SWITCH_PORT(28, 29, qsgmii) - SWITCH_PORT(29, 30, qsgmii) - SWITCH_PORT(30, 31, qsgmii) - SWITCH_PORT(31, 32, qsgmii) - - SWITCH_PORT(32, 33, qsgmii) - SWITCH_PORT(33, 34, qsgmii) - SWITCH_PORT(34, 35, qsgmii) - SWITCH_PORT(35, 36, qsgmii) - SWITCH_PORT(36, 37, qsgmii) - SWITCH_PORT(37, 38, qsgmii) - SWITCH_PORT(38, 39, qsgmii) - SWITCH_PORT(39, 40, qsgmii) - - SWITCH_PORT(40, 41, qsgmii) - SWITCH_PORT(41, 42, qsgmii) - SWITCH_PORT(42, 43, qsgmii) - SWITCH_PORT(43, 44, qsgmii) - SWITCH_PORT(44, 45, qsgmii) - SWITCH_PORT(45, 46, qsgmii) - SWITCH_PORT(46, 47, qsgmii) - SWITCH_PORT(47, 48, qsgmii) - - /* SFP cages */ - port@48 { - reg = <48>; - label = "lan49"; - phy-mode = "sgmii"; - phy-handle = <&phy48>; - sfp = <&sfp0>; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - - }; - - port@49 { - reg = <49>; - label = "lan50"; - phy-mode = "sgmii"; - phy-handle = <&phy49>; - sfp = <&sfp1>; - - fixed-link { - speed = <1000>; - full-duplex; - pause; - }; - - }; - - /* CPU-Port */ - port@52 { - ethernet = <ðernet0>; - reg = <52>; - phy-mode = "qsgmii"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl839x.dtsi b/target/linux/realtek/dts-5.10/rtl839x.dtsi deleted file mode 100644 index 91d6e17a9e..0000000000 --- a/target/linux/realtek/dts-5.10/rtl839x.dtsi +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include - -/dts-v1/; - -#define STRINGIZE(s) #s -#define LAN_LABEL(p, s) STRINGIZE(p ## s) -#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n) - -#define INTERNAL_PHY(n) \ - phy##n: ethernet-phy@##n { \ - reg = <##n>; \ - compatible = "ethernet-phy-ieee802.3-c22"; \ - phy-is-integrated; \ - }; - -#define EXTERNAL_PHY(n) \ - phy##n: ethernet-phy@##n { \ - reg = <##n>; \ - compatible = "ethernet-phy-ieee802.3-c22"; \ - }; - -#define EXTERNAL_SFP_PHY(n) \ - phy##n: ethernet-phy@##n { \ - compatible = "ethernet-phy-ieee802.3-c22"; \ - sfp; \ - media = "fibre"; \ - reg = <##n>; \ - }; - -#define EXTERNAL_SFP_PHY_FULL(n, s) \ - phy##n: ethernet-phy@##n { \ - compatible = "ethernet-phy-ieee802.3-c22"; \ - sfp = <&sfp##s>; \ - reg = <##n>; \ - }; - -#define SWITCH_PORT(n, s, m) \ - port@##n { \ - reg = <##n>; \ - label = SWITCH_PORT_LABEL(s) ; \ - phy-handle = <&phy##n>; \ - phy-mode = #m ; \ - }; - -#define SWITCH_SFP_PORT(n, s, m) \ - port@##n { \ - reg = <##n>; \ - label = SWITCH_PORT_LABEL(s) ; \ - phy-handle = <&phy##n>; \ - phy-mode = #m ; \ - fixed-link { \ - speed = <1000>; \ - full-duplex; \ - }; \ - }; - -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "realtek,rtl839x-soc"; - - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - ccu: clock-controller { - compatible = "realtek,rtl8390-clock"; - #clock-cells = <1>; - clocks = <&osc>; - clock-names = "ref_clk"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "mips,mips34Kc"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - operating-points-v2 = <&cpu_opp_table>; - }; - - cpu@1 { - compatible = "mips,mips34Kc"; - reg = <1>; - clocks = <&ccu CLK_CPU>; - operating-points-v2 = <&cpu_opp_table>; - }; - }; - - cpu_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp00 { - opp-hz = /bits/ 64 <425000000>; - }; - opp01 { - opp-hz = /bits/ 64 <450000000>; - }; - opp02 { - opp-hz = /bits/ 64 <475000000>; - }; - opp03 { - opp-hz = /bits/ 64 <500000000>; - }; - opp04 { - opp-hz = /bits/ 64 <525000000>; - }; - opp05 { - opp-hz = /bits/ 64 <550000000>; - }; - opp06 { - opp-hz = /bits/ 64 <575000000>; - }; - opp07 { - opp-hz = /bits/ 64 <600000000>; - }; - opp08 { - opp-hz = /bits/ 64 <625000000>; - }; - opp09 { - opp-hz = /bits/ 64 <650000000>; - }; - opp10 { - opp-hz = /bits/ 64 <675000000>; - }; - opp11 { - opp-hz = /bits/ 64 <700000000>; - }; - opp12 { - opp-hz = /bits/ 64 <725000000>; - }; - opp13 { - opp-hz = /bits/ 64 <750000000>; - }; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - cpuintc: cpuintc { - compatible = "mti,cpu-interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000000 0x10000>; - - intc: interrupt-controller@3000 { - compatible = "realtek,rtl8390-intc", "realtek,rtl-intc"; - reg = <0x3000 0x18>, <0x3018 0x18>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>, <3>, <4>, <5>, <6>; - }; - - spi0: spi@1200 { - compatible = "realtek,rtl8380-spi"; - reg = <0x1200 0x100>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - timer0: timer@3100 { - compatible = "realtek,rtl8390-timer", "realtek,otto-timer"; - reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, - <0x3130 0x10>, <0x3140 0x10>; - - interrupt-parent = <&intc>; - interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; - clocks = <&ccu CLK_LXB>; - }; - - uart0: uart@2000 { - compatible = "ns16550a"; - reg = <0x2000 0x100>; - - clocks = <&ccu CLK_LXB>; - - interrupt-parent = <&intc>; - interrupts = <31 1>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - }; - - uart1: uart@2100 { - pinctrl-names = "default"; - pinctrl-0 = <&enable_uart1>; - - compatible = "ns16550a"; - reg = <0x2100 0x100>; - - clocks = <&ccu CLK_LXB>; - - interrupt-parent = <&intc>; - interrupts = <30 2>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - - status = "disabled"; - }; - - gpio0: gpio-controller@3500 { - compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio"; - reg = <0x3500 0x20>; - - gpio-controller; - #gpio-cells = <2>; - ngpios = <24>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <23 2>; - }; - - watchdog0: watchdog@3150 { - compatible = "realtek,rtl8390-wdt"; - reg = <0x3150 0xc>; - - realtek,reset-mode = "soc"; - - clocks = <&ccu CLK_LXB>; - timeout-sec = <30>; - - interrupt-parent = <&intc>; - interrupt-names = "phase1", "phase2"; - interrupts = <19 4>, <18 4>; - }; - - }; - - pinmux@1b000004 { - compatible = "pinctrl-single"; - reg = <0x1b000004 0x4>; - - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x1>; - #pinctrl-cells = <2>; - - enable_uart1: pinmux_enable_uart1 { - pinctrl-single,bits = <0x0 0x1 0x3>; - }; - - disable_jtag: pinmux_disable_jtag { - pinctrl-single,bits = <0x0 0x2 0x3>; - }; - }; - - /* LED_GLB_CTRL */ - pinmux@1b0000e4 { - compatible = "pinctrl-single"; - reg = <0x1b0000e4 0x4>; - - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x1>; - #pinctrl-cells = <2>; - - /* enable GPIO 0 */ - pinmux_disable_sys_led: disable_sys_led { - pinctrl-single,bits = <0x0 0x0 0x4000>; - }; - }; - - ethernet0: ethernet@1b00a300 { - compatible = "realtek,rtl838x-eth"; - reg = <0x1b00a300 0x100>; - - interrupt-parent = <&intc>; - interrupts = <24 3>; - - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - sram0: sram@9f000000 { - compatible = "mmio-sram"; - reg = <0x9f000000 0x18000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x9f000000 0x18000>; - }; - - switch0: switch@1b000000 { - status = "okay"; - compatible = "realtek,rtl83xx-switch"; - - interrupt-parent = <&intc>; - interrupts = <20 2>; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl839x_d-link_dgs-1210_gpio.dtsi b/target/linux/realtek/dts-5.10/rtl839x_d-link_dgs-1210_gpio.dtsi deleted file mode 100644 index 260ab67ef3..0000000000 --- a/target/linux/realtek/dts-5.10/rtl839x_d-link_dgs-1210_gpio.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/ { - /* Lan 49 */ - i2c0: i2c-gpio-0 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp0: sfp-p49 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; - /* tx-disable-gpio handled by RTL8214FC based on media setting */ - }; - - /* Lan 50 */ - i2c1: i2c-gpio-1 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp1: sfp-p50 { - compatible = "sff,sfp"; - i2c-bus = <&i2c1>; - los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; - /* tx-disable-gpio handled by RTL8214FC based on media setting */ - }; - - /* Lan 51 */ - i2c2: i2c-gpio-2 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp2: sfp-p51 { - compatible = "sff,sfp"; - i2c-bus = <&i2c2>; - los-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 24 GPIO_ACTIVE_LOW>; - /* tx-disable-gpio handled by RTL8214FC based on media setting */ - }; - - /* Lan 52 */ - i2c3: i2c-gpio-3 { - compatible = "i2c-gpio"; - sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - - sfp3: sfp-p52 { - compatible = "sff,sfp"; - i2c-bus = <&i2c3>; - los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; - /* tx-disable-gpio handled by RTL8214FC based on media setting */ - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl83xx_d-link_dgs-1210_common.dtsi b/target/linux/realtek/dts-5.10/rtl83xx_d-link_dgs-1210_common.dtsi deleted file mode 100644 index 1e3cafa938..0000000000 --- a/target/linux/realtek/dts-5.10/rtl83xx_d-link_dgs-1210_common.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include -#include - -/ { - aliases { - led-boot = &led_power; - led-failsafe = &led_power; - led-running = &led_power; - led-upgrade = &led_power; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - leds: leds { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - compatible = "gpio-leds"; - - led_power: power { - label = "green:power"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio0 { - indirect-access-bus-id = <0>; -}; - -&spi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x00000000 0x80000>; - read-only; - }; - partition@80000 { - label = "u-boot-env"; - reg = <0x00080000 0x40000>; - }; - partition@c0000 { - label = "board-name"; - reg = <0x000c0000 0x40000>; - }; - partition@280000 { - label = "firmware"; - compatible = "denx,uimage"; - reg = <0x00100000 0xd80000>; - }; - partition@be80000 { - label = "kernel2"; - reg = <0x00e80000 0x180000>; - }; - partition@1000000 { - label = "sysinfo"; - reg = <0x01000000 0x40000>; - }; - partition@1040000 { - label = "rootfs2"; - reg = <0x01040000 0xc00000>; - }; - partition@1c40000 { - label = "jffs2"; - reg = <0x01c40000 0x3c0000>; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl83xx_d-link_dgs-1210_gpio.dtsi b/target/linux/realtek/dts-5.10/rtl83xx_d-link_dgs-1210_gpio.dtsi deleted file mode 100644 index b1477aa182..0000000000 --- a/target/linux/realtek/dts-5.10/rtl83xx_d-link_dgs-1210_gpio.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/ { - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio1 34 GPIO_ACTIVE_LOW>; - open-source; - }; - - keys: keys { - compatible = "gpio-keys-polled"; - poll-interval = <20>; - - reset { - label = "reset"; - gpios = <&gpio1 33 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio1: rtl8231-gpio { - compatible = "realtek,rtl8231-gpio"; - #gpio-cells = <2>; - gpio-controller; - indirect-access-bus-id = <0>; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi b/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi deleted file mode 100644 index fb2aa18d21..0000000000 --- a/target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi +++ /dev/null @@ -1,196 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include -#include -#include - -/ { - chosen { - bootargs = "console=ttyS0,9600"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - leds: leds { - compatible = "gpio-leds"; - - led-0 { - label = "amber:any_col"; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_FAULT; - }; - - led-1 { - label = "green:giga"; - gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - }; - - led-2 { - label = "green:100m"; - gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - }; - - led-3 { - label = "green:full"; - gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - }; - - led-4 { - label = "green:loop_history"; - gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <4>; - }; - }; - - keys { - compatible = "gpio-keys"; - - led_mode { - label = "led-mode"; - gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; - }; - - i2c_gpio_0: i2c-gpio-0 { - compatible = "i2c-gpio"; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - gpio1: gpio@20 { - compatible = "nxp,pca9555"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio2: gpio@75 { - compatible = "nxp,pca9539"; - reg = <0x75>; - gpio-controller; - #gpio-cells = <2>; - - /* - * GPIO14 (IO1_6): Shift Register RESET (port LED) - * - Switch-M8eG PN28080K: 3x 74HC164 - * - Switch-M16eG PN28160K: 4x 74HC164 - * - Switch-M24eG PN28240K: 6x 74HC164 - * - Switch-M48eG PN28480K: 12x 74HC164 - */ - portled_sregister_reset { - gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "portled-sregister-reset"; - }; - }; - }; - - i2c_gpio_1: i2c-gpio-1 { - compatible = "i2c-gpio"; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - - i2c_switch: i2c-switch@70 { - compatible = "nxp,pca9545"; - reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "u-boot-env"; - reg = <0x80000 0x10000>; - }; - - partition@90000 { - label = "u-boot-env2"; - reg = <0x90000 0x10000>; - }; - - partition@a0000 { - label = "sysinfo"; - reg = <0xa0000 0x60000>; - read-only; - }; - - /* - * Filesystem area in stock firmware - * (0x100000-0x1DFFFFF) - * - * stock firmware images are required to pass - * the checking by the U-Boot, also for OpenWrt - * - * in OpenWrt: - * - 0x100000-0xDFFFFF (13M): stock images - * - 0xE00000-0x1DFFFFF(16M): OpenWrt image - */ - partition@100000 { - label = "fs_reserved"; - reg = <0x100000 0xd00000>; - }; - - partition@e00000 { - compatible = "denx,uimage"; - label = "firmware"; - reg = <0xe00000 0x1000000>; - }; - - partition@1e00000 { - label = "vlog_data"; - reg = <0x1e00000 0x100000>; - read-only; - }; - - partition@1f00000 { - label = "elog_data"; - reg = <0x1f00000 0x100000>; - read-only; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl9302_zyxel_xgs1250-12.dts b/target/linux/realtek/dts-5.10/rtl9302_zyxel_xgs1250-12.dts deleted file mode 100644 index a57fc00c6e..0000000000 --- a/target/linux/realtek/dts-5.10/rtl9302_zyxel_xgs1250-12.dts +++ /dev/null @@ -1,324 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/dts-v1/; - -#include "rtl930x.dtsi" - -#include -#include -#include - -/ { - compatible = "zyxel,xgs1250-12", "realtek,rtl838x-soc"; - model = "Zyxel XGS1250-12 Switch"; - - aliases { - led-boot = &led_pwr_sys; - led-failsafe = &led_pwr_sys; - led-running = &led_pwr_sys; - led-upgrade = &led_pwr_sys; - }; - - keys { - compatible = "gpio-keys"; - - mode { - label = "reset"; - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - /* i2c of the SFP cage: port 12 */ - i2c0: i2c-rtl9300 { - compatible = "realtek,rtl9300-i2c"; - reg = <0x1b00036c 0x3c>; - #address-cells = <1>; - #size-cells = <0>; - sda-pin = <10>; - scl-pin = <8>; - clock-frequency = <100000>; - }; - - leds { - compatible = "gpio-leds"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_disable_sys_led>; - - led_pwr_sys: led-0 { - label = "green:power"; - color = ; - function = LED_FUNCTION_POWER; - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - }; - }; - - sfp0: sfp-p12 { - compatible = "sff,sfp"; - i2c-bus = <&i2c0>; - los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; - tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; - mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; - }; - - led_set: led_set@0 { - compatible = "realtek,rtl9300-leds"; - led_set0 = <0x0000 0xffff 0x0a20 0x0b80>; // LED set 0: 1000Mbps, 10/100Mbps - led_set1 = <0x0a0b 0x0a28 0x0a82 0x0a0b>; // LED set 1: (10G, 5G, 2.5G) (2.5G, 1G) - // (5G, 10/100) (10G, 5G, 2.5G) - led_set2 = <0x0000 0xffff 0x0a20 0x0a01>; // LED set 2: 1000MBit, 10GBit - }; -}; - -&spi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0xe0000>; - read-only; - }; - partition@e0000 { - label = "u-boot-env"; - reg = <0xe0000 0x10000>; - }; - partition@f0000 { - label = "u-boot-env2"; - reg = <0xf0000 0x10000>; - read-only; - }; - partition@100000 { - label = "jffs"; - reg = <0x100000 0x100000>; - }; - partition@200000 { - label = "jffs2"; - reg = <0x200000 0x100000>; - }; - partition@b300000 { - label = "firmware"; - reg = <0x300000 0xce0000>; - compatible = "openwrt,uimage", "denx,uimage"; - openwrt,ih-magic = <0x93001250>; - }; - partition@fe0000 { - label = "log"; - reg = <0xfe0000 0x20000>; - }; - }; - }; -}; - -ðernet0 { - mdio: mdio-bus { - compatible = "realtek,rtl838x-mdio"; - regmap = <ðernet0>; - #address-cells = <1>; - #size-cells = <0>; - - /* External RTL8218D PHY */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c22"; - rtl9300,smi-address = <0 0>; - sds = < 2 >; - // Disabled because we do not know how to bring up again - // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - phy1: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c22"; - rtl9300,smi-address = <0 1>; - }; - phy2: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c22"; - rtl9300,smi-address = <0 2>; - }; - phy3: ethernet-phy@3 { - reg = <3>; - compatible = "ethernet-phy-ieee802.3-c22"; - rtl9300,smi-address = <0 3>; - }; - phy4: ethernet-phy@4 { - reg = <4>; - compatible = "ethernet-phy-ieee802.3-c22"; - rtl9300,smi-address = <0 4>; - }; - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c22"; - rtl9300,smi-address = <0 5>; - }; - phy6: ethernet-phy@6 { - reg = <6>; - compatible = "ethernet-phy-ieee802.3-c22"; - rtl9300,smi-address = <0 6>; - }; - phy7: ethernet-phy@7 { - reg = <7>; - compatible = "ethernet-phy-ieee802.3-c22"; - rtl9300,smi-address = <0 7>; - }; - - /* External Aquantia 113C PHYs */ - phy24: ethernet-phy@24 { - reg = <24>; - compatible = "ethernet-phy-ieee802.3-c45"; - rtl9300,smi-address = <1 8>; - sds = < 6 >; - // Disabled because we do not know how to bring up again - // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - phy25: ethernet-phy@25 { - reg = <25>; - compatible = "ethernet-phy-ieee802.3-c45"; - rtl9300,smi-address = <2 8>; - sds = < 7 >; - // Disabled because we do not know how to bring up again - // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - phy26: ethernet-phy@26 { - reg = <26>; - compatible = "ethernet-phy-ieee802.3-c45"; - rtl9300,smi-address = <3 8>; - sds = < 8 >; - // Disabled because we do not know how to bring up again - // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - }; - - /* SFP Ports */ - phy27: ethernet-phy@27 { - compatible = "ethernet-phy-ieee802.3-c22"; - phy-is-integrated; - reg = <27>; - rtl9300,smi-address = <4 0>; - sds = < 9 >; - }; - - }; -}; - -&switch0 { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - phy-handle = <&phy0>; - phy-mode = "xgmii"; - led-set = <0>; - }; - port@1 { - reg = <1>; - label = "lan2"; - phy-handle = <&phy1>; - phy-mode = "xgmii"; - led-set = <0>; - }; - port@2 { - reg = <2>; - label = "lan3"; - phy-handle = <&phy2>; - phy-mode = "xgmii"; - led-set = <0>; - }; - port@3 { - reg = <3>; - label = "lan4"; - phy-handle = <&phy3>; - phy-mode = "xgmii"; - led-set = <0>; - }; - port@4 { - reg = <4>; - label = "lan5"; - phy-handle = <&phy4>; - phy-mode = "xgmii"; - led-set = <0>; - }; - port@5 { - reg = <5>; - label = "lan6"; - phy-handle = <&phy5>; - phy-mode = "xgmii"; - led-set = <0>; - }; - port@6 { - reg = <6>; - label = "lan7"; - phy-handle = <&phy6>; - phy-mode = "xgmii"; - led-set = <0>; - }; - port@7 { - reg = <7>; - label = "lan8"; - phy-handle = <&phy7>; - phy-mode = "xgmii"; - led-set = <0>; - }; - - port@24 { - reg = <24>; - label = "lan9"; - phy-mode = "usxgmii"; - phy-handle = <&phy24>; - led-set = <1>; - }; - port@25 { - reg = <25>; - label = "lan10"; - phy-mode = "usxgmii"; - phy-handle = <&phy25>; - led-set = <1>; - }; - port@26 { - reg = <26>; - label = "lan11"; - phy-mode = "usxgmii"; - phy-handle = <&phy26>; - led-set = <1>; - }; - - port@27 { - reg = <27>; - label = "lan12"; - phy-mode = "10gbase-r"; - phy-handle = <&phy27>; - sfp = <&sfp0>; - led-set = <2>; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - - }; - - port@28 { - ethernet = <ðernet0>; - reg = <28>; - phy-mode = "internal"; - fixed-link { - speed = <10000>; - full-duplex; - }; - }; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl930x.dtsi b/target/linux/realtek/dts-5.10/rtl930x.dtsi deleted file mode 100644 index c2a992a174..0000000000 --- a/target/linux/realtek/dts-5.10/rtl930x.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -/dts-v1/; - -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "realtek,rtl838x-soc"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - frequency = <800000000>; - - cpu@0 { - compatible = "mips,mips34Kc"; - reg = <0>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x8000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - cpuintc: cpuintc { - compatible = "mti,cpu-interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - lx_clk: lx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <175000000>; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000000 0x10000>; - - intc: interrupt-controller@3000 { - compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; - reg = <0x3000 0x18>, <0x3018 0x18>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>, <3>, <4>, <5>, <6>, <7>; - }; - - rtl9300clock: rtl9300clock@3200 { - compatible = "realtek,rtl9300clock"; - reg = <0x3200 0x10>, <0x3210 0x10>; - - interrupt-parent = <&intc>; - interrupts = <7 5>, <8 5>; - }; - - spi0: spi@1200 { - compatible = "realtek,rtl8380-spi"; - reg = <0x1200 0x100>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: uart@2000 { - compatible = "ns16550a"; - reg = <0x2000 0x100>; - - clocks = <&lx_clk>; - - interrupt-parent = <&intc>; - interrupts = <30 1>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - }; - - uart1: uart@2100 { - compatible = "ns16550a"; - reg = <0x2100 0x100>; - - clocks = <&lx_clk>; - - interrupt-parent = <&intc>; - interrupts = <31 0>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - - status = "disabled"; - }; - - watchdog0: watchdog@3260 { - compatible = "realtek,rtl9300-wdt"; - reg = <0x3260 0xc>; - - realtek,reset-mode = "soc"; - - clocks = <&lx_clk>; - timeout-sec = <30>; - - interrupt-parent = <&intc>; - interrupt-names = "phase1", "phase2"; - interrupts = <5 4>, <6 4>; - }; - - gpio0: gpio-controller@3300 { - compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio"; - reg = <0x3300 0x1c>, <0x3338 0x8>; - - gpio-controller; - #gpio-cells = <2>; - ngpios = <24>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupts = <13 1>; - }; - - }; - - pinmux_led: pinmux@1b00cc00 { - compatible = "pinctrl-single"; - reg = <0x1b00cc00 0x4>; - - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x1>; - #pinctrl-cells = <2>; - - /* enable GPIO 0 */ - pinmux_disable_sys_led: disable_sys_led { - pinctrl-single,bits = <0x0 0x0 0x1000>; - }; - }; - - ethernet0: ethernet@1b00a300 { - compatible = "realtek,rtl838x-eth"; - reg = <0x1b00a300 0x100>; - - interrupt-parent = <&intc>; - interrupts = <24 3>; - - phy-mode = "internal"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - switch0: switch@1b000000 { - compatible = "realtek,rtl83xx-switch"; - status = "okay"; - - interrupt-parent = <&intc>; - interrupts = <23 2>; - }; -}; diff --git a/target/linux/realtek/dts-5.10/rtl931x.dtsi b/target/linux/realtek/dts-5.10/rtl931x.dtsi deleted file mode 100644 index fd932c8be1..0000000000 --- a/target/linux/realtek/dts-5.10/rtl931x.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT - -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "realtek,rtl838x-soc"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - frequency = <1000000000>; - - cpu@0 { - compatible = "mti,interaptive"; - reg = <0>; - }; - - cpu@1 { - compatible = "mti,interaptive"; - reg = <1>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x10000000>; - }; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - lx_clk: lx_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - cpuclock: cpuclock@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <1000000000>; - }; - - cpuintc: cpuintc { - compatible = "mti,cpu-interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - gic: interrupt-controller@1ddc0000 { - compatible = "mti,gic"; - reg = <0x1ddc0000 0x20000>; - - interrupt-controller; - #interrupt-cells = <3>; - - /* - * Declare the interrupt-parent even though the mti,gic - * binding doesn't require it, such that the kernel can - * figure out that cpu_intc is the root interrupt - * controller & should be probed first. - */ - interrupt-parent = <&cpuintc>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - clocks = <&cpuclock>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000000 0x10000>; - - spi0: spi@1200 { - status = "okay"; - - compatible = "realtek,rtl8380-spi"; - reg = <0x1200 0x100>; - - #address-cells = <1>; - #size-cells = <0>; - }; - - watchdog0: watchdog@3260 { - compatible = "realtek,rtl9310-wdt"; - reg = <0x3260 0xc>; - - realtek,reset-mode = "soc"; - - clocks = <&lx_clk>; - timeout-sec = <30>; - - interrupt-parent = <&gic>; - interrupt-names = "phase1", "phase2"; - interrupts = , ; - }; - - gpio0: gpio-controller@3300 { - compatible = "realtek,rtl9310-gpio", "realtek,otto-gpio"; - reg = <0x3300 0x1c>; - - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - uart0: uart@2000 { - compatible = "ns16550a"; - reg = <0x2000 0x100>; - - clock-frequency = <200000000>; - - interrupt-parent = <&gic>; - #interrupt-cells = <3>; - interrupts = ; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - }; - - uart1: uart@2100 { - compatible = "ns16550a"; - reg = <0x2100 0x100>; - - clock-frequency = <200000000>; - - interrupt-parent = <&gic>; - #interrupt-cells = <3>; - interrupts = ; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - - status = "disabled"; - }; - }; - - pinmux: pinmux@1b001358 { - compatible = "pinctrl-single"; - reg = <0x1b001358 0x4>; - - pinctrl-single,bit-per-mux; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x1>; - #pinctrl-cells = <2>; - - /* Enable GPIO6 and GPIO7, possibly unknown others */ - pinmux_disable_jtag: disable_jtag { - pinctrl-single,bits = <0x0 0x0 0x8000>; - }; - - /* Controls GPIO0 */ - pinmux_disable_sys_led: disable_sys_led { - pinctrl-single,bits = <0x0 0x0 0x100>; - }; - }; - - ethernet0: ethernet@1b00a300 { - status = "okay"; - compatible = "realtek,rtl838x-eth"; - reg = <0x1b00a300 0x100>; - interrupt-parent = <&gic>; - #interrupt-cells = <3>; - interrupts = ; - phy-mode = "internal"; - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - switch0: switch@1b000000 { - compatible = "realtek,rtl83xx-switch"; - status = "okay"; - - interrupt-parent = <&gic>; - #interrupt-cells = <3>; - interrupts = ; - }; -}; diff --git a/target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml b/target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml deleted file mode 100644 index b508362a72..0000000000 --- a/target/linux/realtek/files-5.10/Documentation/devicetree/bindings/realtek,otto-timer.yaml +++ /dev/null @@ -1,85 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/timer/realtek,rtl8300-timer.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Realtek Timer Device Tree Bindings - -maintainers: - - Markus Stockhausen - -description: | - The Realtek SOCs of the RTL83XX and RTL93XX series have at least 5 known - timers with corresponding interrupt lines . Their speed is derived from the - Lexra Bus (LXB) by dividers. Each timer has a block of 4 control registers in - the address range 0xb800xxxx with following start offsets. - - RTL83XX: 0x3100, 0x3110, 0x3120, 0x3130, 0x3140 - RTL93XX: 0x3200, 0x3210, 0x3220, 0x3230, 0x3240 - -properties: - compatible: - items: - - enum: - - realtek,rtl8380-timer - - realtek,rtl8390-timer - - realtek,rtl9300-timer - - const: realtek,otto-timer - - reg: - minItems: 5 - maxItems: 5 - description: - List of timer register addresses. - - interrupts: - minItems: 5 - maxItems: 5 - description: - List of timer interrupts. - - clocks: - maxItems: 1 - -required: - - compatible - - reg - - interrupts - - clocks - -additionalProperties: false - -examples: - - | - timer0: timer@3100 { - compatible = "realtek,rtl8380-timer", "realtek,otto-timer"; - reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, - <0x3130 0x10>, <0x3140 0x10>; - - interrupt-parent = <&intc>; - interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; - clocks = <&ccu CLK_LXB>; - }; - - | - timer0: timer@3100 { - compatible = "realtek,rtl8390-timer", "realtek,otto-timer"; - reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>, - <0x3130 0x10>, <0x3140 0x10>; - - interrupt-parent = <&intc>; - interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>; - clocks = <&ccu CLK_LXB>; - }; - - | - timer0: timer@3200 { - compatible = "realtek,rtl9300-timer", "realtek,otto-timer"; - reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, - <0x3230 0x10>, <0x3240 0x10>; - - interrupt-parent = <&intc>; - interrupts = <7 4>, <8 4>, <9 4>, <10 4>, <11 4>; - clocks = <&ccu CLK_LXB>; - }; - -... diff --git a/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/ioremap.h b/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/ioremap.h deleted file mode 100644 index c49a095792..0000000000 --- a/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/ioremap.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef RTL838X_IOREMAP_H_ -#define RTL838X_IOREMAP_H_ - -static inline int is_rtl838x_internal_registers(phys_addr_t offset) -{ - /* IO-Block */ - if (offset >= 0xb8000000 && offset < 0xb9000000) - return 1; - /* Switch block */ - if (offset >= 0xbb000000 && offset < 0xbc000000) - return 1; - return 0; -} - -static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, - unsigned long flags) -{ - if (is_rtl838x_internal_registers(offset)) - return (void __iomem *)offset; - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return is_rtl838x_internal_registers((unsigned long)addr); -} - -#endif diff --git a/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h b/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h deleted file mode 100644 index d95e5fb098..0000000000 --- a/target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h +++ /dev/null @@ -1,416 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) - * Copyright (C) 2020 B. Koblitz - */ -#ifndef _MACH_RTL838X_H_ -#define _MACH_RTL838X_H_ - -#include -/* - * Register access macros - */ - -#define RTL838X_SW_BASE ((volatile void *) 0xBB000000) - -#define rtl83xx_r32(reg) readl(reg) -#define rtl83xx_w32(val, reg) writel(val, reg) -#define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg) - -#define rtl83xx_r8(reg) readb(reg) -#define rtl83xx_w8(val, reg) writeb(val, reg) - -#define sw_r32(reg) readl(RTL838X_SW_BASE + reg) -#define sw_w32(val, reg) writel(val, RTL838X_SW_BASE + reg) -#define sw_w32_mask(clear, set, reg) \ - sw_w32((sw_r32(reg) & ~(clear)) | (set), reg) -#define sw_r64(reg) ((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \ - readl(RTL838X_SW_BASE + reg + 4)) - -#define sw_w64(val, reg) do { \ - writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \ - writel((u32)((val) & 0xffffffff), \ - RTL838X_SW_BASE + reg + 4); \ - } while (0) - -/* - * SPRAM - */ -#define RTL838X_ISPRAM_BASE 0x0 -#define RTL838X_DSPRAM_BASE 0x0 - -/* - * IRQ Controller - */ -#define RTL838X_IRQ_CPU_BASE 0 -#define RTL838X_IRQ_CPU_NUM 8 -#define RTL838X_IRQ_ICTL_BASE (RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM) -#define RTL838X_IRQ_ICTL_NUM 32 - -#define RTL83XX_IRQ_UART0 31 -#define RTL83XX_IRQ_UART1 30 -#define RTL83XX_IRQ_TC0 29 -#define RTL83XX_IRQ_TC1 28 -#define RTL83XX_IRQ_OCPTO 27 -#define RTL83XX_IRQ_HLXTO 26 -#define RTL83XX_IRQ_SLXTO 25 -#define RTL83XX_IRQ_NIC 24 -#define RTL83XX_IRQ_GPIO_ABCD 23 -#define RTL83XX_IRQ_GPIO_EFGH 22 -#define RTL83XX_IRQ_RTC 21 -#define RTL83XX_IRQ_SWCORE 20 -#define RTL83XX_IRQ_WDT_IP1 19 -#define RTL83XX_IRQ_WDT_IP2 18 - -#define RTL9300_UART1_IRQ 31 -#define RTL9300_UART0_IRQ 30 -#define RTL9300_USB_H2_IRQ 28 -#define RTL9300_NIC_IRQ 24 -#define RTL9300_SWCORE_IRQ 23 -#define RTL9300_GPIO_ABC_IRQ 13 -#define RTL9300_TC4_IRQ 11 -#define RTL9300_TC3_IRQ 10 -#define RTL9300_TC2_IRQ 9 -#define RTL9300_TC1_IRQ 8 -#define RTL9300_TC0_IRQ 7 - - -/* - * MIPS32R2 counter - */ -#define RTL838X_COMPARE_IRQ (RTL838X_IRQ_CPU_BASE + 7) - -/* - * ICTL - * Base address 0xb8003000UL - */ -#define RTL838X_ICTL1_IRQ (RTL838X_IRQ_CPU_BASE + 2) -#define RTL838X_ICTL2_IRQ (RTL838X_IRQ_CPU_BASE + 3) -#define RTL838X_ICTL3_IRQ (RTL838X_IRQ_CPU_BASE + 4) -#define RTL838X_ICTL4_IRQ (RTL838X_IRQ_CPU_BASE + 5) -#define RTL838X_ICTL5_IRQ (RTL838X_IRQ_CPU_BASE + 6) - -#define GIMR (0x00) -#define UART0_IE (1 << 31) -#define UART1_IE (1 << 30) -#define TC0_IE (1 << 29) -#define TC1_IE (1 << 28) -#define OCPTO_IE (1 << 27) -#define HLXTO_IE (1 << 26) -#define SLXTO_IE (1 << 25) -#define NIC_IE (1 << 24) -#define GPIO_ABCD_IE (1 << 23) -#define GPIO_EFGH_IE (1 << 22) -#define RTC_IE (1 << 21) -#define WDT_IP1_IE (1 << 19) -#define WDT_IP2_IE (1 << 18) - -#define GISR (0x04) -#define UART0_IP (1 << 31) -#define UART1_IP (1 << 30) -#define TC0_IP (1 << 29) -#define TC1_IP (1 << 28) -#define OCPTO_IP (1 << 27) -#define HLXTO_IP (1 << 26) -#define SLXTO_IP (1 << 25) -#define NIC_IP (1 << 24) -#define GPIO_ABCD_IP (1 << 23) -#define GPIO_EFGH_IP (1 << 22) -#define RTC_IP (1 << 21) -#define WDT_IP1_IP (1 << 19) -#define WDT_IP2_IP (1 << 18) - - -/* Interrupt Routing Selection */ -#define UART0_RS 2 -#define UART1_RS 1 -#define TC0_RS 5 -#define TC1_RS 1 -#define OCPTO_RS 1 -#define HLXTO_RS 1 -#define SLXTO_RS 1 -#define NIC_RS 4 -#define GPIO_ABCD_RS 4 -#define GPIO_EFGH_RS 4 -#define RTC_RS 4 -#define SWCORE_RS 3 -#define WDT_IP1_RS 4 -#define WDT_IP2_RS 5 - -/* Interrupt IRQ Assignments */ -#define UART0_IRQ 31 -#define UART1_IRQ 30 -#define TC0_IRQ 29 -#define TC1_IRQ 28 -#define OCPTO_IRQ 27 -#define HLXTO_IRQ 26 -#define SLXTO_IRQ 25 -#define NIC_IRQ 24 -#define GPIO_ABCD_IRQ 23 -#define GPIO_EFGH_IRQ 22 -#define RTC_IRQ 21 -#define SWCORE_IRQ 20 -#define WDT_IP1_IRQ 19 -#define WDT_IP2_IRQ 18 - -#define SYSTEM_FREQ 200000000 -#define RTL838X_UART0_BASE ((volatile void *)(0xb8002000UL)) -#define RTL838X_UART0_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */ -#define RTL838X_UART0_FREQ (SYSTEM_FREQ - RTL838X_UART0_BAUD * 24) -#define RTL838X_UART0_MAPBASE 0x18002000UL -#define RTL838X_UART0_MAPSIZE 0x100 -#define RTL838X_UART0_IRQ UART0_IRQ - -#define RTL838X_UART1_BASE ((volatile void *)(0xb8002100UL)) -#define RTL838X_UART1_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */ -#define RTL838X_UART1_FREQ (SYSTEM_FREQ - RTL838X_UART1_BAUD * 24) -#define RTL838X_UART1_MAPBASE 0x18002100UL -#define RTL838X_UART1_MAPSIZE 0x100 -#define RTL838X_UART1_IRQ UART1_IRQ - -#define UART0_RBR (RTL838X_UART0_BASE + 0x000) -#define UART0_THR (RTL838X_UART0_BASE + 0x000) -#define UART0_DLL (RTL838X_UART0_BASE + 0x000) -#define UART0_IER (RTL838X_UART0_BASE + 0x004) -#define UART0_DLM (RTL838X_UART0_BASE + 0x004) -#define UART0_IIR (RTL838X_UART0_BASE + 0x008) -#define UART0_FCR (RTL838X_UART0_BASE + 0x008) -#define UART0_LCR (RTL838X_UART0_BASE + 0x00C) -#define UART0_MCR (RTL838X_UART0_BASE + 0x010) -#define UART0_LSR (RTL838X_UART0_BASE + 0x014) - -#define UART1_RBR (RTL838X_UART1_BASE + 0x000) -#define UART1_THR (RTL838X_UART1_BASE + 0x000) -#define UART1_DLL (RTL838X_UART1_BASE + 0x000) -#define UART1_IER (RTL838X_UART1_BASE + 0x004) -#define UART1_DLM (RTL838X_UART1_BASE + 0x004) -#define UART1_IIR (RTL838X_UART1_BASE + 0x008) -#define UART1_FCR (RTL838X_UART1_BASE + 0x008) -#define UART1_LCR (RTL838X_UART1_BASE + 0x00C) -#define UART1_MCR (RTL838X_UART1_BASE + 0x010) -#define UART1_LSR (RTL838X_UART1_BASE + 0x014) - -/* - * Memory Controller - */ -#define MC_MCR 0xB8001000 -#define MC_MCR_VAL 0x00000000 - -#define MC_DCR 0xB8001004 -#define MC_DCR0_VAL 0x54480000 - -#define MC_DTCR 0xB8001008 -#define MC_DTCR_VAL 0xFFFF05C0 - -/* - * GPIO - */ -#define GPIO_CTRL_REG_BASE ((volatile void *) 0xb8003500) -#define RTL838X_GPIO_PABC_CNR (GPIO_CTRL_REG_BASE + 0x0) -#define RTL838X_GPIO_PABC_TYPE (GPIO_CTRL_REG_BASE + 0x04) -#define RTL838X_GPIO_PABC_DIR (GPIO_CTRL_REG_BASE + 0x8) -#define RTL838X_GPIO_PABC_DATA (GPIO_CTRL_REG_BASE + 0xc) -#define RTL838X_GPIO_PABC_ISR (GPIO_CTRL_REG_BASE + 0x10) -#define RTL838X_GPIO_PAB_IMR (GPIO_CTRL_REG_BASE + 0x14) -#define RTL838X_GPIO_PC_IMR (GPIO_CTRL_REG_BASE + 0x18) - -#define RTL930X_GPIO_CTRL_REG_BASE ((volatile void *) 0xb8003300) -#define RTL930X_GPIO_PABCD_DIR (RTL930X_GPIO_CTRL_REG_BASE + 0x8) -#define RTL930X_GPIO_PABCD_DAT (RTL930X_GPIO_CTRL_REG_BASE + 0xc) -#define RTL930X_GPIO_PABCD_ISR (RTL930X_GPIO_CTRL_REG_BASE + 0x10) -#define RTL930X_GPIO_PAB_IMR (RTL930X_GPIO_CTRL_REG_BASE + 0x14) -#define RTL930X_GPIO_PCD_IMR (RTL930X_GPIO_CTRL_REG_BASE + 0x18) - -#define RTL838X_MODEL_NAME_INFO (0x00D4) -#define RTL839X_MODEL_NAME_INFO (0x0FF0) -#define RTL93XX_MODEL_NAME_INFO (0x0004) -#define RTL931X_CHIP_INFO_ADDR (0x0008) - -#define RTL838X_LED_GLB_CTRL (0xA000) -#define RTL839X_LED_GLB_CTRL (0x00E4) -#define RTL9302_LED_GLB_CTRL (0xcc00) -#define RTL930X_LED_GLB_CTRL (0xCC00) -#define RTL931X_LED_GLB_CTRL (0x0600) - -#define RTL838X_EXT_GPIO_DIR (0xA08C) -#define RTL839X_EXT_GPIO_DIR (0x0214) -#define RTL838X_EXT_GPIO_DATA (0xA094) -#define RTL839X_EXT_GPIO_DATA (0x021c) -#define RTL838X_EXT_GPIO_INDRT_ACCESS (0xA09C) -#define RTL839X_EXT_GPIO_INDRT_ACCESS (0x0224) -#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0) -#define RTL838X_DMY_REG5 (0x0144) -#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0) - -#define RTL838X_GMII_INTF_SEL (0x1000) -#define RTL838X_IO_DRIVING_ABILITY_CTRL (0x1010) - -#define RTL838X_GPIO_A7 31 -#define RTL838X_GPIO_A6 30 -#define RTL838X_GPIO_A5 29 -#define RTL838X_GPIO_A4 28 -#define RTL838X_GPIO_A3 27 -#define RTL838X_GPIO_A2 26 -#define RTL838X_GPIO_A1 25 -#define RTL838X_GPIO_A0 24 -#define RTL838X_GPIO_B7 23 -#define RTL838X_GPIO_B6 22 -#define RTL838X_GPIO_B5 21 -#define RTL838X_GPIO_B4 20 -#define RTL838X_GPIO_B3 19 -#define RTL838X_GPIO_B2 18 -#define RTL838X_GPIO_B1 17 -#define RTL838X_GPIO_B0 16 -#define RTL838X_GPIO_C7 15 -#define RTL838X_GPIO_C6 14 -#define RTL838X_GPIO_C5 13 -#define RTL838X_GPIO_C4 12 -#define RTL838X_GPIO_C3 11 -#define RTL838X_GPIO_C2 10 -#define RTL838X_GPIO_C1 9 -#define RTL838X_GPIO_C0 8 - -#define RTL838X_INT_RW_CTRL (0x0058) -#define RTL838X_EXT_VERSION (0x00D0) -#define RTL838X_PLL_CML_CTRL (0x0FF8) -#define RTL838X_STRAP_DBG (0x100C) - -/* - * Reset - */ -#define RGCR (0x1E70) -#define RTL838X_RST_GLB_CTRL_0 (0x003c) -#define RTL838X_RST_GLB_CTRL_1 (0x0040) -#define RTL839X_RST_GLB_CTRL (0x0014) -#define RTL930X_RST_GLB_CTRL_0 (0x000c) -#define RTL931X_RST_GLB_CTRL (0x0400) - -/* LED control by switch */ -#define RTL838X_LED_MODE_SEL (0x1004) -#define RTL838X_LED_MODE_CTRL (0xA004) -#define RTL838X_LED_P_EN_CTRL (0xA008) - -/* LED control by software */ -#define RTL838X_LED_SW_CTRL (0x0128) -#define RTL839X_LED_SW_CTRL (0xA00C) -#define RTL838X_LED_SW_P_EN_CTRL (0xA010) -#define RTL839X_LED_SW_P_EN_CTRL (0x012C) -#define RTL838X_LED0_SW_P_EN_CTRL (0xA010) -#define RTL839X_LED0_SW_P_EN_CTRL (0x012C) -#define RTL838X_LED1_SW_P_EN_CTRL (0xA014) -#define RTL839X_LED1_SW_P_EN_CTRL (0x0130) -#define RTL838X_LED2_SW_P_EN_CTRL (0xA018) -#define RTL839X_LED2_SW_P_EN_CTRL (0x0134) -#define RTL838X_LED_SW_P_CTRL (0xA01C) -#define RTL839X_LED_SW_P_CTRL (0x0144) - -#define RTL839X_MAC_EFUSE_CTRL (0x02ac) - -/* - * MDIO via Realtek's SMI interface - */ -#define RTL838X_SMI_GLB_CTRL (0xa100) -#define RTL838X_SMI_ACCESS_PHY_CTRL_0 (0xa1b8) -#define RTL838X_SMI_ACCESS_PHY_CTRL_1 (0xa1bc) -#define RTL838X_SMI_ACCESS_PHY_CTRL_2 (0xa1c0) -#define RTL838X_SMI_ACCESS_PHY_CTRL_3 (0xa1c4) -#define RTL838X_SMI_PORT0_5_ADDR_CTRL (0xa1c8) -#define RTL838X_SMI_POLL_CTRL (0xa17c) - -#define RTL839X_SMI_GLB_CTRL (0x03f8) -#define RTL839X_SMI_PORT_POLLING_CTRL (0x03fc) -#define RTL839X_PHYREG_ACCESS_CTRL (0x03DC) -#define RTL839X_PHYREG_CTRL (0x03E0) -#define RTL839X_PHYREG_PORT_CTRL (0x03E4) -#define RTL839X_PHYREG_DATA_CTRL (0x03F0) -#define RTL839X_PHYREG_MMD_CTRL (0x3F4) - -#define RTL930X_SMI_GLB_CTRL (0xCA00) -#define RTL930X_SMI_POLL_CTRL (0xca90) -#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08) -#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C) -#define RTL930X_SMI_PORT0_5_ADDR (0xCB80) -#define RTL930X_SMI_ACCESS_PHY_CTRL_0 (0xCB70) -#define RTL930X_SMI_ACCESS_PHY_CTRL_1 (0xCB74) -#define RTL930X_SMI_ACCESS_PHY_CTRL_2 (0xCB78) -#define RTL930X_SMI_ACCESS_PHY_CTRL_3 (0xCB7C) - -#define RTL931X_SMI_GLB_CTRL1 (0x0CBC) -#define RTL931X_SMI_GLB_CTRL0 (0x0CC0) -#define RTL931X_SMI_PORT_POLLING_CTRL (0x0CCC) -#define RTL931X_SMI_PORT_ADDR (0x0C74) -#define RTL931X_SMI_PORT_POLLING_SEL (0x0C9C) -#define RTL9310_SMI_PORT_POLLING_CTRL (0x0CCC) -#define RTL931X_SMI_INDRT_ACCESS_CTRL_0 (0x0C00) -#define RTL931X_SMI_INDRT_ACCESS_CTRL_1 (0x0C04) -#define RTL931X_SMI_INDRT_ACCESS_CTRL_2 (0x0C08) -#define RTL931X_SMI_INDRT_ACCESS_CTRL_3 (0x0C10) -#define RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL (0x0C14) -#define RTL931X_SMI_INDRT_ACCESS_MMD_CTRL (0xC18) -#define RTL931X_MAC_L2_GLOBAL_CTRL2 (0x1358) -#define RTL931X_MAC_L2_GLOBAL_CTRL1 (0x5548) - -/* - * Switch interrupts - */ -#define RTL838X_IMR_GLB (0x1100) -#define RTL838X_IMR_PORT_LINK_STS_CHG (0x1104) -#define RTL838X_ISR_GLB_SRC (0x1148) -#define RTL838X_ISR_PORT_LINK_STS_CHG (0x114C) - -#define RTL839X_IMR_GLB (0x0064) -#define RTL839X_IMR_PORT_LINK_STS_CHG (0x0068) -#define RTL839X_ISR_GLB_SRC (0x009c) -#define RTL839X_ISR_PORT_LINK_STS_CHG (0x00a0) - -#define RTL930X_IMR_GLB (0xC628) -#define RTL930X_IMR_PORT_LINK_STS_CHG (0xC62C) -#define RTL930X_ISR_GLB (0xC658) -#define RTL930X_ISR_PORT_LINK_STS_CHG (0xC660) - -// IMR_GLB does not exit on RTL931X -#define RTL931X_IMR_PORT_LINK_STS_CHG (0x126C) -#define RTL931X_ISR_GLB_SRC (0x12B4) -#define RTL931X_ISR_PORT_LINK_STS_CHG (0x12B8) - -/* Definition of family IDs */ -#define RTL8389_FAMILY_ID (0x8389) -#define RTL8328_FAMILY_ID (0x8328) -#define RTL8390_FAMILY_ID (0x8390) -#define RTL8350_FAMILY_ID (0x8350) -#define RTL8380_FAMILY_ID (0x8380) -#define RTL8330_FAMILY_ID (0x8330) -#define RTL9300_FAMILY_ID (0x9300) -#define RTL9310_FAMILY_ID (0x9310) - -/* SPI Support */ -#define RTL931X_SPI_CTRL0 (0x103C) - -/* Basic SoC Features */ -#define RTL838X_CPU_PORT 28 -#define RTL839X_CPU_PORT 52 -#define RTL930X_CPU_PORT 28 -#define RTL931X_CPU_PORT 56 - -struct rtl83xx_soc_info { - unsigned char *name; - unsigned int id; - unsigned int family; - unsigned char *compatible; - volatile void *sw_base; - volatile void *icu_base; - int cpu_port; -}; - -/* rtl83xx-related functions used across subsystems */ -int rtl838x_smi_wait_op(int timeout); -int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val); - -#endif /* _MACH_RTL838X_H_ */ diff --git a/target/linux/realtek/files-5.10/arch/mips/kernel/cevt-rtl9300.c b/target/linux/realtek/files-5.10/arch/mips/kernel/cevt-rtl9300.c deleted file mode 100644 index 1c8c30de5d..0000000000 --- a/target/linux/realtek/files-5.10/arch/mips/kernel/cevt-rtl9300.c +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* - * Timer registers - * the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart - */ -#define RTL9300_TC_DATA 0x0 -#define RTL9300_TC_CNT 0x4 -#define RTL9300_TC_CTRL 0x8 -#define RTL9300_TC_CTRL_MODE BIT(24) -#define RTL9300_TC_CTRL_EN BIT(28) -#define RTL9300_TC_INT 0xc -#define RTL9300_TC_INT_IP BIT(16) -#define RTL9300_TC_INT_IE BIT(20) - -// Timer modes -#define TIMER_MODE_REPEAT 1 -#define TIMER_MODE_ONCE 0 - -// Minimum divider is 2 -#define DIVISOR_RTL9300 2 - -#define N_BITS 28 - -#define RTL9300_CLOCK_RATE 87500000 - -struct rtl9300_clk_dev { - struct clock_event_device clkdev; - void __iomem *base; -}; - -static void __iomem *rtl9300_tc_base(struct clock_event_device *clk) -{ - struct rtl9300_clk_dev *rtl_clk = container_of(clk, struct rtl9300_clk_dev, clkdev); - - return rtl_clk->base; -} - -static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id) -{ - struct rtl9300_clk_dev *rtl_clk = dev_id; - struct clock_event_device *clk = &rtl_clk->clkdev; - - u32 v = readl(rtl_clk->base + RTL9300_TC_INT); - - // Acknowledge the IRQ - v |= RTL9300_TC_INT_IP; - writel(v, rtl_clk->base + RTL9300_TC_INT); - - clk->event_handler(clk); - return IRQ_HANDLED; -} - -static void rtl9300_clock_stop(void __iomem *base) -{ - u32 v; - - writel(0, base + RTL9300_TC_CTRL); - - // Acknowledge possibly pending IRQ - v = readl(base + RTL9300_TC_INT); - writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT); -} - -static void rtl9300_timer_start(void __iomem *base, bool periodic) -{ - u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300; - - writel(0, base + RTL9300_TC_CNT); - pr_debug("------------- starting timer base %08x\n", (u32)base); - writel(v, base + RTL9300_TC_CTRL); -} - -static int rtl9300_next_event(unsigned long delta, struct clock_event_device *clk) -{ - void __iomem *base = rtl9300_tc_base(clk); - - rtl9300_clock_stop(base); - writel(delta, base + RTL9300_TC_DATA); - rtl9300_timer_start(base, TIMER_MODE_ONCE); - - return 0; -} - -static int rtl9300_state_periodic(struct clock_event_device *clk) -{ - void __iomem *base = rtl9300_tc_base(clk); - - pr_debug("------------- rtl9300_state_periodic %08x\n", (u32)base); - rtl9300_clock_stop(base); - writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA); - rtl9300_timer_start(base, TIMER_MODE_REPEAT); - return 0; -} - -static int rtl9300_state_oneshot(struct clock_event_device *clk) -{ - void __iomem *base = rtl9300_tc_base(clk); - - pr_debug("------------- rtl9300_state_oneshot %08x\n", (u32)base); - rtl9300_clock_stop(base); - writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA); - rtl9300_timer_start(base, TIMER_MODE_ONCE); - return 0; -} - -static int rtl9300_shutdown(struct clock_event_device *clk) -{ - void __iomem *base = rtl9300_tc_base(clk); - - pr_debug("------------- rtl9300_shutdown %08x\n", (u32)base); - rtl9300_clock_stop(base); - return 0; -} - -static void rtl9300_clock_setup(void __iomem *base) -{ - u32 v; - - // Disable timer - writel(0, base + RTL9300_TC_CTRL); - - // Acknowledge possibly pending IRQ - v = readl(base + RTL9300_TC_INT); - writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT); - - // Setup maximum period (for use as clock-source) - writel(0x0fffffff, base + RTL9300_TC_DATA); -} - -static DEFINE_PER_CPU(struct rtl9300_clk_dev, rtl9300_clockevent); -static DEFINE_PER_CPU(char [18], rtl9300_clock_name); - -void rtl9300_clockevent_init(void) -{ - int cpu = smp_processor_id(); - int irq; - struct rtl9300_clk_dev *rtl_clk = &per_cpu(rtl9300_clockevent, cpu); - struct clock_event_device *cd = &rtl_clk->clkdev; - unsigned char *name = per_cpu(rtl9300_clock_name, cpu); - unsigned long flags = IRQF_PERCPU | IRQF_TIMER; - struct device_node *node; - - pr_info("%s called for cpu%d\n", __func__, cpu); - BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ - - node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300clock"); - if (!node) { - pr_err("No DT entry found for realtek,rtl9300clock\n"); - return; - } - - irq = irq_of_parse_and_map(node, cpu); - pr_info("%s using IRQ %d\n", __func__, irq); - - rtl_clk->base = of_iomap(node, cpu); - if (!rtl_clk->base) { - pr_err("cannot map timer for cpu %d", cpu); - return; - } - - rtl9300_clock_setup(rtl_clk->base); - - sprintf(name, "rtl9300-counter-%d", cpu); - cd->name = name; - cd->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - - clockevent_set_clock(cd, RTL9300_CLOCK_RATE); - - cd->max_delta_ns = clockevent_delta2ns(0x0fffffff, cd); - cd->max_delta_ticks = 0x0fffffff; - cd->min_delta_ns = clockevent_delta2ns(0x20, cd); - cd->min_delta_ticks = 0x20; - cd->rating = 300; - cd->irq = irq; - cd->cpumask = cpumask_of(cpu); - cd->set_next_event = rtl9300_next_event; - cd->set_state_shutdown = rtl9300_shutdown; - cd->set_state_periodic = rtl9300_state_periodic; - cd->set_state_oneshot = rtl9300_state_oneshot; - clockevents_register_device(cd); - - irq_set_affinity(irq, cd->cpumask); - - if (request_irq(irq, rtl9300_timer_interrupt, flags, name, rtl_clk)) - pr_err("Failed to request irq %d (%s)\n", irq, name); - - writel(RTL9300_TC_INT_IE, rtl_clk->base + RTL9300_TC_INT); -} diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/Makefile b/target/linux/realtek/files-5.10/arch/mips/rtl838x/Makefile deleted file mode 100644 index a9d1666d46..0000000000 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the rtl838x specific parts of the kernel -# - -obj-y := setup.o prom.o diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/Platform b/target/linux/realtek/files-5.10/arch/mips/rtl838x/Platform deleted file mode 100644 index 98f18cac1b..0000000000 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/Platform +++ /dev/null @@ -1,5 +0,0 @@ -# -# Realtek RTL838x SoCs -# -cflags-$(CONFIG_RTL83XX) += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/ -load-$(CONFIG_RTL83XX) += 0xffffffff80100000 diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c b/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c deleted file mode 100644 index dd1b2b170d..0000000000 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c +++ /dev/null @@ -1,216 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * prom.c - * Early intialization code for the Realtek RTL838X SoC - * - * based on the original BSP by - * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) - * Copyright (C) 2020 B. Koblitz - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -extern char arcs_cmdline[]; -extern const char __appended_dtb; - -struct rtl83xx_soc_info soc_info; -const void *fdt; - -#ifdef CONFIG_MIPS_MT_SMP -extern const struct plat_smp_ops vsmp_smp_ops; -static struct plat_smp_ops rtl_smp_ops; - -static void rtl_init_secondary(void) -{ -#ifndef CONFIG_CEVT_R4K -/* - * These devices are low on resources. There might be the chance that CEVT_R4K - * is not enabled in kernel build. Nevertheless the timer and interrupt 7 might - * be active by default after startup of secondary VPE. With no registered - * handler that leads to continuous unhandeled interrupts. In this case disable - * counting (DC) in the core and confirm a pending interrupt. - */ - write_c0_cause(read_c0_cause() | CAUSEF_DC); - write_c0_compare(0); -#endif /* CONFIG_CEVT_R4K */ -/* - * Enable all CPU interrupts, as everything is managed by the external - * controller. TODO: Standard vsmp_init_secondary() has special treatment for - * Malta if external GIC is available. Maybe we need this too. - */ - if (mips_gic_present()) - pr_warn("%s: GIC present. Maybe interrupt enabling required.\n", __func__); - else - set_c0_status(ST0_IM); -} -#endif /* CONFIG_MIPS_MT_SMP */ - -const char *get_system_type(void) -{ - return soc_info.name; -} - -void __init prom_free_prom_memory(void) -{ - -} - -void __init device_tree_init(void) -{ - if (!fdt_check_header(&__appended_dtb)) { - fdt = &__appended_dtb; - pr_info("Using appended Device Tree.\n"); - } - initial_boot_params = (void *)fdt; - unflatten_and_copy_device_tree(); -} - -void __init identify_rtl9302(void) -{ - switch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) { - case 0x93020810: - soc_info.name = "RTL9302A 12x2.5G"; - break; - case 0x93021010: - soc_info.name = "RTL9302B 8x2.5G"; - break; - case 0x93021810: - soc_info.name = "RTL9302C 16x2.5G"; - break; - case 0x93022010: - soc_info.name = "RTL9302D 24x2.5G"; - break; - case 0x93020800: - soc_info.name = "RTL9302A"; - break; - case 0x93021000: - soc_info.name = "RTL9302B"; - break; - case 0x93021800: - soc_info.name = "RTL9302C"; - break; - case 0x93022000: - soc_info.name = "RTL9302D"; - break; - case 0x93023001: - soc_info.name = "RTL9302F"; - break; - default: - soc_info.name = "RTL9302"; - } -} - -void __init prom_init(void) -{ - uint32_t model; - - /* uart0 */ - setup_8250_early_printk_port(0xb8002000, 2, 0); - - model = sw_r32(RTL838X_MODEL_NAME_INFO); - pr_info("RTL838X model is %x\n", model); - model = model >> 16 & 0xFFFF; - - if ((model != 0x8328) && (model != 0x8330) && (model != 0x8332) - && (model != 0x8380) && (model != 0x8382)) { - model = sw_r32(RTL839X_MODEL_NAME_INFO); - pr_info("RTL839X model is %x\n", model); - model = model >> 16 & 0xFFFF; - } - - if ((model & 0x8390) != 0x8380 && (model & 0x8390) != 0x8390) { - model = sw_r32(RTL93XX_MODEL_NAME_INFO); - pr_info("RTL93XX model is %x\n", model); - model = model >> 16 & 0xFFFF; - } - - soc_info.id = model; - - switch (model) { - case 0x8328: - soc_info.name = "RTL8328"; - soc_info.family = RTL8328_FAMILY_ID; - break; - case 0x8332: - soc_info.name = "RTL8332"; - soc_info.family = RTL8380_FAMILY_ID; - break; - case 0x8380: - soc_info.name = "RTL8380"; - soc_info.family = RTL8380_FAMILY_ID; - break; - case 0x8382: - soc_info.name = "RTL8382"; - soc_info.family = RTL8380_FAMILY_ID; - break; - case 0x8390: - soc_info.name = "RTL8390"; - soc_info.family = RTL8390_FAMILY_ID; - break; - case 0x8391: - soc_info.name = "RTL8391"; - soc_info.family = RTL8390_FAMILY_ID; - break; - case 0x8392: - soc_info.name = "RTL8392"; - soc_info.family = RTL8390_FAMILY_ID; - break; - case 0x8393: - soc_info.name = "RTL8393"; - soc_info.family = RTL8390_FAMILY_ID; - break; - case 0x9301: - soc_info.name = "RTL9301"; - soc_info.family = RTL9300_FAMILY_ID; - break; - case 0x9302: - identify_rtl9302(); - soc_info.family = RTL9300_FAMILY_ID; - break; - case 0x9303: - soc_info.name = "RTL9303"; - soc_info.family = RTL9300_FAMILY_ID; - break; - case 0x9313: - soc_info.name = "RTL9313"; - soc_info.family = RTL9310_FAMILY_ID; - break; - default: - soc_info.name = "DEFAULT"; - soc_info.family = 0; - } - - pr_info("SoC Type: %s\n", get_system_type()); - - fw_init_cmdline(); - - mips_cpc_probe(); - - if (!register_cps_smp_ops()) - return; - -#ifdef CONFIG_MIPS_MT_SMP - if (cpu_has_mipsmt) { - rtl_smp_ops = vsmp_smp_ops; - rtl_smp_ops.init_secondary = rtl_init_secondary; - register_smp_ops(&rtl_smp_ops); - return; - } -#endif - - register_up_smp_ops(); -} diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c b/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c deleted file mode 100644 index b4d415ab44..0000000000 --- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Setup for the Realtek RTL838X SoC: - * Memory, Timer and Serial - * - * Copyright (C) 2020 B. Koblitz - * based on the original BSP by - * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com) - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "mach-rtl83xx.h" - -extern struct rtl83xx_soc_info soc_info; - -void __init plat_mem_setup(void) -{ - void *dtb; - - set_io_port_base(KSEG1); - - if (fw_passed_dtb) /* UHI interface */ - dtb = (void *)fw_passed_dtb; - else if (&__dtb_start[0] != &__dtb_end[0]) - dtb = (void *)__dtb_start; - else - panic("no dtb found"); - - /* - * Load the devicetree. This causes the chosen node to be - * parsed resulting in our memory appearing - */ - __dt_setup_arch(dtb); -} - -void plat_time_init_fallback(void) -{ - struct device_node *np; - u32 freq = 500000000; - - np = of_find_node_by_name(NULL, "cpus"); - if (!np) { - pr_err("Missing 'cpus' DT node, using default frequency."); - } else { - if (of_property_read_u32(np, "frequency", &freq) < 0) - pr_err("No 'frequency' property in DT, using default."); - else - pr_info("CPU frequency from device tree: %dMHz", freq / 1000000); - of_node_put(np); - } - mips_hpt_frequency = freq / 2; -} - -void __init plat_time_init(void) -{ -/* - * Initialization routine resembles generic MIPS plat_time_init() with - * lazy error handling. The final fallback is only needed until we have - * converted all device trees to new clock syntax. - */ - struct device_node *np; - struct clk *clk; - - of_clk_init(NULL); - - mips_hpt_frequency = 0; - np = of_get_cpu_node(0, NULL); - if (!np) { - pr_err("Failed to get CPU node\n"); - } else { - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); - } else { - mips_hpt_frequency = clk_get_rate(clk) / 2; - clk_put(clk); - } - } - - if (!mips_hpt_frequency) - plat_time_init_fallback(); - - timer_probe(); -} - -void __init arch_init_irq(void) -{ - irqchip_init(); -} diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/Kconfig b/target/linux/realtek/files-5.10/drivers/clk/realtek/Kconfig deleted file mode 100644 index 4cf3cd9633..0000000000 --- a/target/linux/realtek/files-5.10/drivers/clk/realtek/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -menuconfig COMMON_CLK_REALTEK - bool "Support for Realtek's clock controllers" - depends on RTL83XX - -if COMMON_CLK_REALTEK - -config COMMON_CLK_RTL83XX - bool "Clock driver for Realtek RTL83XX" - depends on RTL83XX - select SRAM - help - This driver adds support for the Realtek RTL83xx series basic clocks. - This includes chips in the RTL838x series, such as RTL8380, RTL8381, - RTL832, as well as chips from the RTL839x series, such as RTL8390, - RT8391, RTL8392, RTL8393 and RTL8396. - -endif diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/Makefile b/target/linux/realtek/files-5.10/drivers/clk/realtek/Makefile deleted file mode 100644 index 7bc4ed910c..0000000000 --- a/target/linux/realtek/files-5.10/drivers/clk/realtek/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_COMMON_CLK_RTL83XX) += clk-rtl83xx.o clk-rtl838x-sram.o clk-rtl839x-sram.o diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl838x-sram.S b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl838x-sram.S deleted file mode 100644 index 527436bbab..0000000000 --- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl838x-sram.S +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Realtek RTL838X SRAM clock setters - * Copyright (C) 2022 Markus Stockhausen - */ - -#include - -#include "clk-rtl83xx.h" - -#define rGLB $t0 -#define rCTR $t1 -#define rMSK $t2 -#define rSLP $t3 -#define rTMP $t4 - -.set noreorder - -.globl rtcl_838x_dram_start -rtcl_838x_dram_start: - -/* - * Functions start here and should avoid access to normal memory. REMARK! Do not forget about - * stack pointer and dirty caches that might interfere. - */ - -.globl rtcl_838x_dram_set_rate -.ent rtcl_838x_dram_set_rate -rtcl_838x_dram_set_rate: - -#ifdef CONFIG_RTL838X - - li rCTR, RTL_SW_CORE_BASE - addiu rGLB, rCTR, RTL838X_PLL_GLB_CTRL - ori rTMP, $0, CLK_CPU - beq $a0, rTMP, pre_cpu - ori rTMP, $0, CLK_MEM - beq $a0, rTMP, pre_mem - nop -pre_lxb: - ori rSLP, $0, RTL838X_GLB_CTRL_LXB_PLL_READY_MASK - addiu rCTR, rCTR, RTL838X_PLL_LXB_CTRL0 - b main_set - ori rMSK, $0, RTL838X_GLB_CTRL_EN_LXB_PLL_MASK -pre_mem: - /* simple 64K data cache flush to avoid unexpected memory access */ - li rMSK, RTL_SRAM_BASE - li rTMP, 2048 -pre_flush: - lw $0, 0(rMSK) - addiu rMSK, rMSK, 32 - addiu rTMP, rTMP, -1 - bne rTMP, $0, pre_flush - lw $0, -4(rMSK) - - ori rSLP, $0, RTL838X_GLB_CTRL_MEM_PLL_READY_MASK - addiu rCTR, rCTR, RTL838X_PLL_MEM_CTRL0 - b main_set - ori rMSK, $0, RTL838X_GLB_CTRL_EN_MEM_PLL_MASK -pre_cpu: - /* switch CPU to LXB clock */ - ori rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK - nor rMSK, rMSK, $0 - sync - lw rTMP, 0(rGLB) - and rTMP, rTMP, rMSK - sw rTMP, 0(rGLB) - sync - - ori rSLP, $0, RTL838X_GLB_CTRL_CPU_PLL_READY_MASK - addiu rCTR, rCTR, RTL838X_PLL_CPU_CTRL0 - ori rMSK, $0, RTL838X_GLB_CTRL_EN_CPU_PLL_MASK -main_set: - /* disable PLL */ - nor rMSK, rMSK, 0 - sync - lw rTMP, 0(rGLB) - sync - and rTMP, rTMP, rMSK - sync - sw rTMP, 0(rGLB) - - /* set new PLL values */ - sync - sw $a1, 0(rCTR) - sw $a2, 4(rCTR) - sync - - /* enable PLL (will reset it and clear ready status) */ - nor rMSK, rMSK, 0 - sync - lw rTMP, 0(rGLB) - sync - or rTMP, rTMP, rMSK - sync - sw rTMP, 0(rGLB) - - /* wait for PLL to become ready */ -wait_ready: - lw rTMP, 0(rGLB) - and rTMP, rTMP, rSLP - bne rTMP, $0, wait_ready - sync - - /* branch to post processing */ - ori rTMP, $0, CLK_CPU - beq $a0, rTMP, post_cpu - ori rTMP, $0, CLK_MEM - beq $a0, rTMP, post_mem - nop -post_lxb: - jr $ra - nop -post_mem: - jr $ra - nop -post_cpu: - /* stabilize clock to avoid crash, empirically determined */ - ori rSLP, $0, 0x3000 -wait_cpu: - bnez rSLP, wait_cpu - addiu rSLP, rSLP, -1 - - /* switch CPU to PLL clock */ - ori rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK - sync - lw rTMP, 0(rGLB) - or rTMP, rTMP, rMSK - sw rTMP, 0(rGLB) - sync - jr $ra - nop - -#else /* !CONFIG_RTL838X */ - - jr $ra - nop - -#endif - -.end rtcl_838x_dram_set_rate - -/* - * End marker. Do not delete. - */ - .word RTL_SRAM_MARKER -.globl rtcl_838x_dram_size -rtcl_838x_dram_size: - .word .-rtcl_838x_dram_start - diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl839x-sram.S b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl839x-sram.S deleted file mode 100644 index cd43dfaabd..0000000000 --- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl839x-sram.S +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Realtek RTL839X SRAM clock setters - * Copyright (C) 2022 Markus Stockhausen - */ - -#include -#include - -#include "clk-rtl83xx.h" - -#define rGLB $t0 -#define rCTR $t1 -#define rMSK $t2 -#define rSLP1 $t3 -#define rSLP2 $t4 -#define rSLP3 $t5 -#define rTMP $t6 -#define rCP0 $t7 - -.set noreorder - -.globl rtcl_839x_dram_start -rtcl_839x_dram_start: - -/* - * Functions start here and should avoid access to normal memory. REMARK! Do not forget about - * stack pointer and dirty caches that might interfere. - */ - -.globl rtcl_839x_dram_set_rate -.ent rtcl_839x_dram_set_rate -rtcl_839x_dram_set_rate: - -#ifdef CONFIG_RTL839X - - /* disable MIPS 34K branch and return prediction */ - mfc0 rCP0, CP0_CONFIG, 7 - ori rTMP, rCP0, 0xc - mtc0 rTMP, CP0_CONFIG, 7 - - li rCTR, RTL_SW_CORE_BASE - addiu rGLB, rCTR, RTL839X_PLL_GLB_CTRL - ori rTMP, $0, CLK_CPU - beq $a0, rTMP, pre_cpu - ori rTMP, $0, CLK_MEM - beq $a0, rTMP, pre_mem - nop -pre_lxb: - li rSLP1, 0x400000 - li rSLP2, 0x400000 - li rSLP3, 0x400000 - addiu rCTR, rCTR, RTL839X_PLL_LXB_CTRL0 - b main_set - ori rMSK, $0, RTL839X_GLB_CTRL_LXB_CLKSEL_MASK -pre_mem: - /* try to avoid memory access with simple 64K data cache flush */ - li rMSK, RTL_SRAM_BASE - li rTMP, 2048 -pre_flush: - lw $0, 0(rMSK) - addiu rMSK, rMSK, 32 - addiu rTMP, rTMP, -1 - bne rTMP, $0, pre_flush - lw $0, -4(rMSK) - - li rSLP1, 0x10000 - li rSLP2, 0x10000 - li rSLP3, 0x10000 - addiu rCTR, rCTR, RTL839X_PLL_MEM_CTRL0 - b main_set - ori rMSK, $0, RTL839X_GLB_CTRL_MEM_CLKSEL_MASK -pre_cpu: - li rSLP1, 0x1000 - li rSLP2, 0x1000 - li rSLP3, 0x200 - addiu rCTR, rCTR, RTL839X_PLL_CPU_CTRL0 - ori rMSK, $0, RTL839X_GLB_CTRL_CPU_CLKSEL_MASK -main_set: - /* switch to fixed clock */ - sync - lw rTMP, 0(rGLB) - sync - or rTMP, rTMP, rMSK - sync - sw rTMP, 0(rGLB) - - /* wait until fixed clock in use */ - or rTMP, rSLP1, $0 -wait_fixclock: - bnez rTMP, wait_fixclock - addiu rTMP, rTMP, -1 - - /* set new PLL values */ - sync - sw $a1, 0(rCTR) - sw $a2, 4(rCTR) - sync - - /* wait for value takeover */ - or rTMP, rSLP2, $0 -wait_pll: - bnez rTMP, wait_pll - addiu rTMP, rTMP, -1 - - /* switch back to PLL clock*/ - nor rMSK, rMSK, $0 - sync - lw rTMP, 0(rGLB) - sync - and rTMP, rTMP, rMSK - sync - sw rTMP, 0(rGLB) - - /* wait until PLL clock in use */ - or rTMP, rSLP3, $0 -wait_pllclock: - bnez rTMP, wait_pllclock - addiu rTMP, rTMP, -1 - - /* restore branch prediction */ - mtc0 rCP0, CP0_CONFIG, 7 - jr $ra - nop - -#else /* !CONFIG_RTL839X */ - - jr $ra - nop - -#endif - -.end rtcl_839x_dram_set_rate - -/* - * End marker. Do not delete. - */ - .word RTL_SRAM_MARKER -.globl rtcl_839x_dram_size -rtcl_839x_dram_size: - .word .-rtcl_839x_dram_start - diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c deleted file mode 100644 index 9b8183fbeb..0000000000 --- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c +++ /dev/null @@ -1,766 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Realtek RTL83XX clock driver - * Copyright (C) 2022 Markus Stockhausen - * - * This driver provides basic clock support for the central core clock unit (CCU) and its PLLs - * inside the RTL838X and RTL8389X SOC. Currently CPU, memory and LXB clock information can be - * accessed. To make use of the driver add the following devices and configurations at the - * appropriate locations to the DT. - * - * #include - * - * sram0: sram@9f000000 { - * compatible = "mmio-sram"; - * reg = <0x9f000000 0x18000>; - * #address-cells = <1>; - * #size-cells = <1>; - * ranges = <0 0x9f000000 0x18000>; - * }; - * - * osc: oscillator { - * compatible = "fixed-clock"; - * #clock-cells = <0>; - * clock-frequency = <25000000>; - * }; - * - * ccu: clock-controller { - * compatible = "realtek,rtl8380-clock"; - * #clock-cells = <1>; - * clocks = <&osc>; - * clock-names = "ref_clk"; - * }; - * - * - * The SRAM part is needed to be able to set clocks. When changing clocks the code must not run - * from DRAM. Otherwise system might freeze. Take care to adjust CCU compatibility, SRAM address - * and size to the target SOC device. Afterwards one can access/identify the clocks in the other - * DT devices with <&ccu CLK_CPU>, <&ccu CLK_MEM> or <&ccu CLK_LXB>. Additionally the clocks can - * be used inside the kernel with - * - * cpu_clk = clk_get(NULL, "cpu_clk"); - * mem_clk = clk_get(NULL, "mem_clk"); - * lxb_clk = clk_get(NULL, "lxb_clk"); - * - * This driver can be directly used by the DT based cpufreq driver (CONFIG_CPUFREQ_DT) if CPU - * references the right clock and sane operating points (OPP) are provided. E.g. - * - * cpu@0 { - * compatible = "mips,mips4KEc"; - * reg = <0>; - * clocks = <&ccu CLK_CPU>; - * operating-points-v2 = <&cpu_opp_table>; - * }; - * - * cpu_opp_table: opp-table-0 { - * compatible = "operating-points-v2"; - * opp-shared; - * opp00 { - * opp-hz = /bits/ 64 <425000000>; - * }; - * ... - * } - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk-rtl83xx.h" - -#define read_sw(reg) ioread32(((void *)RTL_SW_CORE_BASE) + reg) -#define read_soc(reg) ioread32(((void *)RTL_SOC_BASE) + reg) - -#define write_sw(val, reg) iowrite32(val, ((void *)RTL_SW_CORE_BASE) + reg) -#define write_soc(val, reg) iowrite32(val, ((void *)RTL_SOC_BASE) + reg) - -/* - * some hardware specific definitions - */ - -#define SOC_RTL838X 0 -#define SOC_RTL839X 1 -#define SOC_COUNT 2 - -#define MEM_DDR1 1 -#define MEM_DDR2 2 -#define MEM_DDR3 3 - -#define REG_CTRL0 0 -#define REG_CTRL1 1 -#define REG_COUNT 2 - -#define OSC_RATE 25000000 - -static const int rtcl_regs[SOC_COUNT][REG_COUNT][CLK_COUNT] = { - { - { RTL838X_PLL_CPU_CTRL0, RTL838X_PLL_MEM_CTRL0, RTL838X_PLL_LXB_CTRL0 }, - { RTL838X_PLL_CPU_CTRL1, RTL838X_PLL_MEM_CTRL1, RTL838X_PLL_LXB_CTRL1 }, - }, { - { RTL839X_PLL_CPU_CTRL0, RTL839X_PLL_MEM_CTRL0, RTL839X_PLL_LXB_CTRL0 }, - { RTL839X_PLL_CPU_CTRL1, RTL839X_PLL_MEM_CTRL1, RTL839X_PLL_LXB_CTRL1 }, - } -}; - -#define RTCL_REG_SET(_rate, _ctrl0, _ctrl1) \ - { \ - .rate = _rate, \ - .ctrl0 = _ctrl0, \ - .ctrl1 = _ctrl1, \ - } - -struct rtcl_reg_set { - unsigned int rate; - unsigned int ctrl0; - unsigned int ctrl1; -}; - -/* - * The following configuration tables are valid operation points for their corresponding PLLs. - * The magic numbers are precalculated mulitpliers and dividers to keep the driver simple. They - * also provide rates outside the allowed physical specifications. E.g. DDR3 memory has a lower - * limit of 303 MHz or the CPU might get unstable if set to anything above its startup frequency. - * Additionally the Realtek SOCs tend to expect CPU speed > MEM speed > LXB speed. The caller or - * DT configuration must take care that only valid operating points are selected. - */ - -static const struct rtcl_reg_set rtcl_838x_cpu_reg_set[] = { - RTCL_REG_SET(300000000, 0x045c8, 0x1414530e), - RTCL_REG_SET(325000000, 0x04648, 0x1414530e), - RTCL_REG_SET(350000000, 0x046c8, 0x1414530e), - RTCL_REG_SET(375000000, 0x04748, 0x1414530e), - RTCL_REG_SET(400000000, 0x045c8, 0x0c14530e), - RTCL_REG_SET(425000000, 0x04628, 0x0c14530e), - RTCL_REG_SET(450000000, 0x04688, 0x0c14530e), - RTCL_REG_SET(475000000, 0x046e8, 0x0c14530e), - RTCL_REG_SET(500000000, 0x04748, 0x0c14530e), - RTCL_REG_SET(525000000, 0x047a8, 0x0c14530e), - RTCL_REG_SET(550000000, 0x04808, 0x0c14530e), - RTCL_REG_SET(575000000, 0x04868, 0x0c14530e), - RTCL_REG_SET(600000000, 0x048c8, 0x0c14530e), - RTCL_REG_SET(625000000, 0x04928, 0x0c14530e) -}; - -static const struct rtcl_reg_set rtcl_838x_mem_reg_set[] = { - RTCL_REG_SET(200000000, 0x041bc, 0x14018C80), - RTCL_REG_SET(225000000, 0x0417c, 0x0c018C80), - RTCL_REG_SET(250000000, 0x041ac, 0x0c018C80), - RTCL_REG_SET(275000000, 0x0412c, 0x04018C80), - RTCL_REG_SET(300000000, 0x0414c, 0x04018c80), - RTCL_REG_SET(325000000, 0x0416c, 0x04018c80), - RTCL_REG_SET(350000000, 0x0418c, 0x04018c80), - RTCL_REG_SET(375000000, 0x041ac, 0x04018c80) -}; - -static const struct rtcl_reg_set rtcl_838x_lxb_reg_set[] = { - RTCL_REG_SET(100000000, 0x043c8, 0x001ad30e), - RTCL_REG_SET(125000000, 0x043c8, 0x001ad30e), - RTCL_REG_SET(150000000, 0x04508, 0x1c1ad30e), - RTCL_REG_SET(175000000, 0x04508, 0x1c1ad30e), - RTCL_REG_SET(200000000, 0x047c8, 0x001ad30e) -}; - -static const struct rtcl_reg_set rtcl_839x_cpu_reg_set[] = { - RTCL_REG_SET(400000000, 0x0414c, 0x00000005), - RTCL_REG_SET(425000000, 0x041ec, 0x00000006), - RTCL_REG_SET(450000000, 0x0417c, 0x00000005), - RTCL_REG_SET(475000000, 0x0422c, 0x00000006), - RTCL_REG_SET(500000000, 0x041ac, 0x00000005), - RTCL_REG_SET(525000000, 0x0426c, 0x00000006), - RTCL_REG_SET(550000000, 0x0412c, 0x00000004), - RTCL_REG_SET(575000000, 0x042ac, 0x00000006), - RTCL_REG_SET(600000000, 0x0414c, 0x00000004), - RTCL_REG_SET(625000000, 0x042ec, 0x00000006), - RTCL_REG_SET(650000000, 0x0416c, 0x00000004), - RTCL_REG_SET(675000000, 0x04324, 0x00000006), - RTCL_REG_SET(700000000, 0x0418c, 0x00000004), - RTCL_REG_SET(725000000, 0x0436c, 0x00000006), - RTCL_REG_SET(750000000, 0x0438c, 0x00000006), - RTCL_REG_SET(775000000, 0x043ac, 0x00000006), - RTCL_REG_SET(800000000, 0x043cc, 0x00000006), - RTCL_REG_SET(825000000, 0x043ec, 0x00000006), - RTCL_REG_SET(850000000, 0x0440c, 0x00000006) -}; - -static const struct rtcl_reg_set rtcl_839x_mem_reg_set[] = { - RTCL_REG_SET(100000000, 0x041cc, 0x00000000), - RTCL_REG_SET(125000000, 0x041ac, 0x00000007), - RTCL_REG_SET(150000000, 0x0414c, 0x00000006), - RTCL_REG_SET(175000000, 0x0418c, 0x00000006), - RTCL_REG_SET(200000000, 0x041cc, 0x00000006), - RTCL_REG_SET(225000000, 0x0417c, 0x00000005), - RTCL_REG_SET(250000000, 0x041ac, 0x00000005), - RTCL_REG_SET(275000000, 0x0412c, 0x00000004), - RTCL_REG_SET(300000000, 0x0414c, 0x00000004), - RTCL_REG_SET(325000000, 0x0416c, 0x00000004), - RTCL_REG_SET(350000000, 0x0418c, 0x00000004), - RTCL_REG_SET(375000000, 0x041ac, 0x00000004), - RTCL_REG_SET(400000000, 0x041cc, 0x00000004) -}; - -static const struct rtcl_reg_set rtcl_839x_lxb_reg_set[] = { - RTCL_REG_SET(50000000, 0x1414c, 0x00000003), - RTCL_REG_SET(100000000, 0x0814c, 0x00000003), - RTCL_REG_SET(150000000, 0x0414c, 0x00000003), - RTCL_REG_SET(200000000, 0x0414c, 0x00000007) -}; - -struct rtcl_rtab_set { - int count; - const struct rtcl_reg_set *rset; -}; - -#define RTCL_RTAB_SET(_rset) \ - { \ - .count = ARRAY_SIZE(_rset), \ - .rset = _rset, \ - } - -static const struct rtcl_rtab_set rtcl_rtab_set[SOC_COUNT][CLK_COUNT] = { - { - RTCL_RTAB_SET(rtcl_838x_cpu_reg_set), - RTCL_RTAB_SET(rtcl_838x_mem_reg_set), - RTCL_RTAB_SET(rtcl_838x_lxb_reg_set) - }, { - RTCL_RTAB_SET(rtcl_839x_cpu_reg_set), - RTCL_RTAB_SET(rtcl_839x_mem_reg_set), - RTCL_RTAB_SET(rtcl_839x_lxb_reg_set) - } -}; - -#define RTCL_ROUND_SET(_min, _max, _step) \ - { \ - .min = _min, \ - .max = _max, \ - .step = _step, \ - } - -struct rtcl_round_set { - unsigned long min; - unsigned long max; - unsigned long step; -}; - -static const struct rtcl_round_set rtcl_round_set[SOC_COUNT][CLK_COUNT] = { - { - RTCL_ROUND_SET(300000000, 625000000, 25000000), - RTCL_ROUND_SET(200000000, 375000000, 25000000), - RTCL_ROUND_SET(100000000, 200000000, 25000000) - }, { - RTCL_ROUND_SET(400000000, 850000000, 25000000), - RTCL_ROUND_SET(100000000, 400000000, 25000000), - RTCL_ROUND_SET(50000000, 200000000, 50000000) - } -}; - -static const int rtcl_divn3[] = { 2, 3, 4, 6 }; -static const int rtcl_xdiv[] = { 2, 4, 2 }; - -/* - * module data structures - */ - -#define RTCL_CLK_INFO(_idx, _name, _pname, _dname) \ - { \ - .idx = _idx, \ - .name = _name, \ - .parent_name = _pname, \ - .display_name = _dname, \ - } - -struct rtcl_clk_info { - unsigned int idx; - const char *name; - const char *parent_name; - const char *display_name; -}; - -struct rtcl_clk { - struct clk_hw hw; - unsigned int idx; - unsigned long min; - unsigned long max; - unsigned long rate; - unsigned long startup; -}; - -static const struct rtcl_clk_info rtcl_clk_info[CLK_COUNT] = { - RTCL_CLK_INFO(CLK_CPU, "cpu_clk", "ref_clk", "CPU"), - RTCL_CLK_INFO(CLK_MEM, "mem_clk", "ref_clk", "MEM"), - RTCL_CLK_INFO(CLK_LXB, "lxb_clk", "ref_clk", "LXB") -}; - -struct rtcl_dram { - int type; - int buswidth; -}; - -struct rtcl_sram { - int *pmark; - unsigned long vbase; -}; - -struct rtcl_ccu { - spinlock_t lock; - unsigned int soc; - struct rtcl_sram sram; - struct rtcl_dram dram; - struct device_node *np; - struct platform_device *pdev; - struct rtcl_clk clks[CLK_COUNT]; -}; - -struct rtcl_ccu *rtcl_ccu; - -#define rtcl_hw_to_clk(_hw) container_of(_hw, struct rtcl_clk, hw) - -/* - * SRAM relocatable assembler functions. The dram() parts point to normal kernel memory while - * the sram() parts are the same functions but relocated to SRAM. - */ - -extern void rtcl_838x_dram_start(void); -extern int rtcl_838x_dram_size; - -extern void (*rtcl_838x_dram_set_rate)(int clk_idx, int ctrl0, int ctrl1); -static void (*rtcl_838x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1); - -extern void rtcl_839x_dram_start(void); -extern int rtcl_839x_dram_size; - -extern void (*rtcl_839x_dram_set_rate)(int clk_idx, int ctrl0, int ctrl1); -static void (*rtcl_839x_sram_set_rate)(int clk_idx, int ctrl0, int ctrl1); - -/* - * clock setter/getter functions - */ - -static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - struct rtcl_clk *clk = rtcl_hw_to_clk(hw); - unsigned int ctrl0, ctrl1, div1, div2, cmu_ncode_in; - unsigned int cmu_sel_prediv, cmu_sel_div4, cmu_divn2, cmu_divn2_selb, cmu_divn3_sel; - - if ((clk->idx >= CLK_COUNT) || (!rtcl_ccu) || (rtcl_ccu->soc >= SOC_COUNT)) - return 0; - - ctrl0 = read_sw(rtcl_regs[rtcl_ccu->soc][REG_CTRL0][clk->idx]); - ctrl1 = read_sw(rtcl_regs[rtcl_ccu->soc][REG_CTRL1][clk->idx]); - - cmu_sel_prediv = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(ctrl0); - cmu_sel_div4 = RTL_PLL_CTRL0_CMU_SEL_DIV4(ctrl0) ? 4 : 1; - cmu_ncode_in = RTL_PLL_CTRL0_CMU_NCODE_IN(ctrl0) + 4; - cmu_divn2 = RTL_PLL_CTRL0_CMU_DIVN2(ctrl0) + 4; - - switch (rtcl_ccu->soc) { - case SOC_RTL838X: - if ((ctrl0 == 0) && (ctrl1 == 0) && (clk->idx == CLK_LXB)) - return 200000000; - - cmu_divn2_selb = RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1); - cmu_divn3_sel = rtcl_divn3[RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)]; - break; - case SOC_RTL839X: - cmu_divn2_selb = RTL839X_PLL_CTRL1_CMU_DIVN2_SELB(ctrl1); - cmu_divn3_sel = rtcl_divn3[RTL839X_PLL_CTRL1_CMU_DIVN3_SEL(ctrl1)]; - break; - } - div1 = cmu_divn2_selb ? cmu_divn3_sel : cmu_divn2; - div2 = rtcl_xdiv[clk->idx]; - - return (((parent_rate / 16) * cmu_ncode_in) / (div1 * div2)) * - cmu_sel_prediv * cmu_sel_div4 * 16; -} - -static int rtcl_838x_set_rate(int clk_idx, const struct rtcl_reg_set *reg) -{ - unsigned long irqflags; -/* - * Runtime of this function (including locking) - * CPU: up to 14000 cycles / up to 56 us at 250 MHz (half default speed) - */ - spin_lock_irqsave(&rtcl_ccu->lock, irqflags); - rtcl_838x_sram_set_rate(clk_idx, reg->ctrl0, reg->ctrl1); - spin_unlock_irqrestore(&rtcl_ccu->lock, irqflags); - - return 0; -} - -static int rtcl_839x_set_rate(int clk_idx, const struct rtcl_reg_set *reg) -{ - unsigned long vpflags; - unsigned long irqflags; -/* - * Runtime of this function (including locking) - * CPU: up to 31000 cycles / up to 89 us at 350 MHz (half default speed) - */ - spin_lock_irqsave(&rtcl_ccu->lock, irqflags); - vpflags = dvpe(); - rtcl_839x_sram_set_rate(clk_idx, reg->ctrl0, reg->ctrl1); - evpe(vpflags); - spin_unlock_irqrestore(&rtcl_ccu->lock, irqflags); - - return 0; -} - -static int rtcl_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) -{ - int tab_idx; - struct rtcl_clk *clk = rtcl_hw_to_clk(hw); - const struct rtcl_rtab_set *rtab = &rtcl_rtab_set[rtcl_ccu->soc][clk->idx]; - const struct rtcl_round_set *round = &rtcl_round_set[rtcl_ccu->soc][clk->idx]; - - if ((parent_rate != OSC_RATE) || (!rtcl_ccu->sram.vbase)) - return -EINVAL; -/* - * Currently we do not know if SRAM is stable on these devices. Maybe someone changes memory in - * this region and does not care about proper allocation. So check if something might go wrong. - */ - if (unlikely(*rtcl_ccu->sram.pmark != RTL_SRAM_MARKER)) { - dev_err(&rtcl_ccu->pdev->dev, "SRAM code lost\n"); - return -EINVAL; - } - - tab_idx = (rate - round->min) / round->step; - if ((tab_idx < 0) || (tab_idx >= rtab->count) || (rtab->rset[tab_idx].rate != rate)) - return -EINVAL; - - rtcl_ccu->clks[clk->idx].rate = rate; - - switch (rtcl_ccu->soc) { - case SOC_RTL838X: - return rtcl_838x_set_rate(clk->idx, &rtab->rset[tab_idx]); - case SOC_RTL839X: - return rtcl_839x_set_rate(clk->idx, &rtab->rset[tab_idx]); - } - - return -ENXIO; -} - -static long rtcl_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) -{ - struct rtcl_clk *clk = rtcl_hw_to_clk(hw); - unsigned long rrate = max(clk->min, min(clk->max, rate)); - const struct rtcl_round_set *round = &rtcl_round_set[rtcl_ccu->soc][clk->idx]; - - rrate = ((rrate + (round->step >> 1)) / round->step) * round->step; - rrate -= (rrate > clk->max) ? round->step : 0; - rrate += (rrate < clk->min) ? round->step : 0; - - return rrate; -} - -/* - * Initialization functions to register the CCU and its clocks - */ - -#define RTCL_SRAM_FUNC(SOC, PBASE, FN) ({ \ - rtcl_##SOC##_sram_##FN = ((void *)&rtcl_##SOC##_dram_##FN \ - - (void *)&rtcl_##SOC##_dram_start) \ - + (void *)PBASE; }) - -static const struct clk_ops rtcl_clk_ops = { - .set_rate = rtcl_set_rate, - .round_rate = rtcl_round_rate, - .recalc_rate = rtcl_recalc_rate, -}; - -static int rtcl_ccu_create(struct device_node *np) -{ - int soc; - - if (of_device_is_compatible(np, "realtek,rtl8380-clock")) - soc = SOC_RTL838X; - else if (of_device_is_compatible(np, "realtek,rtl8390-clock")) - soc = SOC_RTL839X; - else - return -ENXIO; - - rtcl_ccu = kzalloc(sizeof(*rtcl_ccu), GFP_KERNEL); - if (IS_ERR(rtcl_ccu)) - return -ENOMEM; - - rtcl_ccu->np = np; - rtcl_ccu->soc = soc; - rtcl_ccu->dram.type = RTL_MC_MCR_DRAMTYPE(read_soc(RTL_MC_MCR)); - rtcl_ccu->dram.buswidth = RTL_MC_DCR_BUSWIDTH(read_soc(RTL_MC_DCR)); - spin_lock_init(&rtcl_ccu->lock); - - return 0; -} - -int rtcl_register_clkhw(int clk_idx) -{ - int ret; - struct clk *clk; - struct clk_init_data hw_init = { }; - struct rtcl_clk *rclk = &rtcl_ccu->clks[clk_idx]; - struct clk_parent_data parent_data = { .fw_name = rtcl_clk_info[clk_idx].parent_name }; - - rclk->idx = clk_idx; - rclk->hw.init = &hw_init; - - hw_init.num_parents = 1; - hw_init.ops = &rtcl_clk_ops; - hw_init.parent_data = &parent_data; - hw_init.name = rtcl_clk_info[clk_idx].name; - - ret = of_clk_hw_register(rtcl_ccu->np, &rclk->hw); - if (ret) - return ret; - - clk_hw_register_clkdev(&rclk->hw, rtcl_clk_info[clk_idx].name, NULL); - - clk = clk_get(NULL, rtcl_clk_info[clk_idx].name); - rclk->startup = clk_get_rate(clk); - clk_put(clk); - - switch (clk_idx) { - case CLK_CPU: - rclk->min = rtcl_round_set[rtcl_ccu->soc][clk_idx].min; - rclk->max = rtcl_round_set[rtcl_ccu->soc][clk_idx].max; - break; - default: -/* - * TODO: This driver supports PLL reclocking and nothing else. Additional required steps for non - * CPU PLLs are missing. E.g. if we want to change memory clocks the right way we must adapt a lot - * of other settings like MCR and DTRx timing registers (0xb80001000, 0xb8001008, ...) and initiate - * a DLL reset so that hardware operates in the allowed limits. This is far too complex without - * official support. Avoid this for now. - */ - rclk->min = rclk->max = rclk->startup; - break; - } - - return 0; -} - -static struct clk_hw *rtcl_get_clkhw(struct of_phandle_args *clkspec, void *prv) -{ - unsigned int idx = clkspec->args[0]; - - if (idx >= CLK_COUNT) { - pr_err("%s: Invalid index %u\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - return &rtcl_ccu->clks[idx].hw; -} - -static int rtcl_ccu_register_clocks(void) -{ - int clk_idx, ret; - - for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { - ret = rtcl_register_clkhw(clk_idx); - if (ret) { - pr_err("%s: Couldn't register %s clock\n", - __func__, rtcl_clk_info[clk_idx].display_name); - goto err_hw_unregister; - } - } - - ret = of_clk_add_hw_provider(rtcl_ccu->np, rtcl_get_clkhw, rtcl_ccu); - if (ret) { - pr_err("%s: Couldn't register clock provider of %s\n", - __func__, of_node_full_name(rtcl_ccu->np)); - goto err_hw_unregister; - } - - return 0; - -err_hw_unregister: - for (--clk_idx; clk_idx >= 0; --clk_idx) - clk_hw_unregister(&rtcl_ccu->clks[clk_idx].hw); - - return ret; -} - -int rtcl_init_sram(void) -{ - struct gen_pool *sram_pool; - phys_addr_t sram_pbase; - unsigned long sram_vbase; - struct device_node *node; - struct platform_device *pdev = NULL; - void *dram_start; - int dram_size; - const char *wrn = ", rate setting disabled.\n"; - - switch (rtcl_ccu->soc) { - case SOC_RTL838X: - dram_start = &rtcl_838x_dram_start; - dram_size = rtcl_838x_dram_size; - break; - case SOC_RTL839X: - dram_start = &rtcl_839x_dram_start; - dram_size = rtcl_839x_dram_size; - break; - default: - return -ENXIO; - } - - for_each_compatible_node(node, NULL, "mmio-sram") { - pdev = of_find_device_by_node(node); - if (pdev) { - of_node_put(node); - break; - } - } - - if (!pdev) { - dev_warn(&rtcl_ccu->pdev->dev, "no SRAM device found%s", wrn); - return -ENXIO; - } - - sram_pool = gen_pool_get(&pdev->dev, NULL); - if (!sram_pool) { - dev_warn(&rtcl_ccu->pdev->dev, "SRAM pool unavailable%s", wrn); - goto err_put_device; - } - - sram_vbase = gen_pool_alloc(sram_pool, dram_size); - if (!sram_vbase) { - dev_warn(&rtcl_ccu->pdev->dev, "can not allocate SRAM%s", wrn); - goto err_put_device; - } - - sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_vbase); - memcpy((void *)sram_pbase, dram_start, dram_size); - flush_icache_range((unsigned long)sram_pbase, (unsigned long)(sram_pbase + dram_size)); - - switch (rtcl_ccu->soc) { - case SOC_RTL838X: - RTCL_SRAM_FUNC(838x, sram_pbase, set_rate); - break; - case SOC_RTL839X: - RTCL_SRAM_FUNC(839x, sram_pbase, set_rate); - break; - } - - rtcl_ccu->sram.pmark = (int *)((void *)sram_pbase + (dram_size - 4)); - rtcl_ccu->sram.vbase = sram_vbase; - - return 0; - -err_put_device: - put_device(&pdev->dev); - - return -ENXIO; -} - -void rtcl_ccu_log_early(void) -{ - int clk_idx; - char meminfo[80], clkinfo[255], msg[255] = "rtl83xx-clk: initialized"; - - sprintf(meminfo, " (%d Bit DDR%d)", rtcl_ccu->dram.buswidth, rtcl_ccu->dram.type); - for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { - sprintf(clkinfo, ", %s %lu MHz", rtcl_clk_info[clk_idx].display_name, - rtcl_ccu->clks[clk_idx].startup / 1000000); - if (clk_idx == CLK_MEM) - strcat(clkinfo, meminfo); - strcat(msg, clkinfo); - } - pr_info("%s\n", msg); -} - -void rtcl_ccu_log_late(void) -{ - int clk_idx; - struct rtcl_clk *rclk; - bool overclock = false; - char clkinfo[80], msg[255] = "rate setting enabled"; - - for (clk_idx = 0; clk_idx < CLK_COUNT; clk_idx++) { - rclk = &rtcl_ccu->clks[clk_idx]; - overclock |= rclk->max > rclk->startup; - sprintf(clkinfo, ", %s %lu-%lu MHz", rtcl_clk_info[clk_idx].display_name, - rclk->min / 1000000, rclk->max / 1000000); - strcat(msg, clkinfo); - } - if (overclock) - strcat(msg, ", OVERCLOCK AT OWN RISK"); - - dev_info(&rtcl_ccu->pdev->dev, "%s\n", msg); -} - -/* - * Early registration: This module provides core startup clocks that are needed for generic SOC - * init and for further builtin devices (e.g. UART). Register asap via clock framework. - */ - -static void __init rtcl_probe_early(struct device_node *np) -{ - if (rtcl_ccu_create(np)) - return; - - if (rtcl_ccu_register_clocks()) - kfree(rtcl_ccu); - else - rtcl_ccu_log_early(); -} - -CLK_OF_DECLARE_DRIVER(rtl838x_clk, "realtek,rtl8380-clock", rtcl_probe_early); -CLK_OF_DECLARE_DRIVER(rtl839x_clk, "realtek,rtl8390-clock", rtcl_probe_early); - -/* - * Late registration: Finally register as normal platform driver. At this point we can make use - * of other modules like SRAM. - */ - -static const struct of_device_id rtcl_dt_ids[] = { - { .compatible = "realtek,rtl8380-clock" }, - { .compatible = "realtek,rtl8390-clock" }, - {} -}; - -static int rtcl_probe_late(struct platform_device *pdev) -{ - int ret; - - if (!rtcl_ccu) { - dev_err(&pdev->dev, "early initialization not run"); - return -ENXIO; - } - rtcl_ccu->pdev = pdev; - ret = rtcl_init_sram(); - if (ret) - return ret; - - rtcl_ccu_log_late(); - - return 0; -} - -static struct platform_driver rtcl_platform_driver = { - .driver = { - .name = "rtl83xx-clk", - .of_match_table = rtcl_dt_ids, - }, - .probe = rtcl_probe_late, -}; - -static int __init rtcl_init_subsys(void) -{ - return platform_driver_register(&rtcl_platform_driver); -} - -/* - * The driver does not know when SRAM module has finally loaded. With an arch_initcall() we might - * overtake SRAM initialization. Be polite and give the system a little more time. - */ - -subsys_initcall(rtcl_init_subsys); diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h deleted file mode 100644 index a69b16b475..0000000000 --- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Realtek RTL83XX clock headers - * Copyright (C) 2022 Markus Stockhausen - */ - -/* - * Switch registers (e.g. PLL) - */ - -#define RTL_SW_CORE_BASE (0xbb000000) - -#define RTL838X_PLL_GLB_CTRL (0x0fc0) -#define RTL838X_PLL_CPU_CTRL0 (0x0fc4) -#define RTL838X_PLL_CPU_CTRL1 (0x0fc8) -#define RTL838X_PLL_LXB_CTRL0 (0x0fd0) -#define RTL838X_PLL_LXB_CTRL1 (0x0fd4) -#define RTL838X_PLL_MEM_CTRL0 (0x0fdc) -#define RTL838X_PLL_MEM_CTRL1 (0x0fe0) - -#define RTL839X_PLL_GLB_CTRL (0x0024) -#define RTL839X_PLL_CPU_CTRL0 (0x0028) -#define RTL839X_PLL_CPU_CTRL1 (0x002c) -#define RTL839X_PLL_LXB_CTRL0 (0x0038) -#define RTL839X_PLL_LXB_CTRL1 (0x003c) -#define RTL839X_PLL_MEM_CTRL0 (0x0048) -#define RTL839X_PLL_MEM_CTRL1 (0x004c) - -#define RTL_PLL_CTRL0_CMU_SEL_PREDIV(v) (((v) >> 0) & 0x3) -#define RTL_PLL_CTRL0_CMU_SEL_DIV4(v) (((v) >> 2) & 0x1) -#define RTL_PLL_CTRL0_CMU_NCODE_IN(v) (((v) >> 4) & 0xff) -#define RTL_PLL_CTRL0_CMU_DIVN2(v) (((v) >> 12) & 0xff) - -#define RTL838X_GLB_CTRL_EN_CPU_PLL_MASK (1 << 0) -#define RTL838X_GLB_CTRL_EN_LXB_PLL_MASK (1 << 1) -#define RTL838X_GLB_CTRL_EN_MEM_PLL_MASK (1 << 2) -#define RTL838X_GLB_CTRL_CPU_PLL_READY_MASK (1 << 8) -#define RTL838X_GLB_CTRL_LXB_PLL_READY_MASK (1 << 9) -#define RTL838X_GLB_CTRL_MEM_PLL_READY_MASK (1 << 10) -#define RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK (1 << 12) - -#define RTL838X_PLL_CTRL1_CMU_DIVN2_SELB(v) (((v) >> 26) & 0x1) -#define RTL838X_PLL_CTRL1_CMU_DIVN3_SEL(v) (((v) >> 27) & 0x3) - -#define RTL839X_GLB_CTRL_CPU_CLKSEL_MASK (1 << 11) -#define RTL839X_GLB_CTRL_MEM_CLKSEL_MASK (1 << 12) -#define RTL839X_GLB_CTRL_LXB_CLKSEL_MASK (1 << 13) - -#define RTL839X_PLL_CTRL1_CMU_DIVN2_SELB(v) (((v) >> 2) & 0x1) -#define RTL839X_PLL_CTRL1_CMU_DIVN3_SEL(v) (((v) >> 0) & 0x3) - -/* - * Core registers (e.g. memory controller) - */ - -#define RTL_SOC_BASE (0xB8000000) - -#define RTL_MC_MCR (0x1000) -#define RTL_MC_DCR (0x1004) -#define RTL_MC_DTR0 (0x1008) -#define RTL_MC_DTR1 (0x100c) -#define RTL_MC_DTR2 (0x1010) -#define RTL_MC_DMCR (0x101c) -#define RTL_MC_DACCR (0x1500) -#define RTL_MC_DCDR (0x1060) - -#define RTL_MC_MCR_DRAMTYPE(v) ((((v) >> 28) & 0xf) + 1) -#define RTL_MC_DCR_BUSWIDTH(v) (8 << (((v) >> 24) & 0xf)) - -/* - * Other stuff - */ - -#define RTL_SRAM_MARKER (0x5eaf00d5) -#define RTL_SRAM_BASE (0x9f000000) diff --git a/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c b/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c deleted file mode 100644 index 0395cf29e5..0000000000 --- a/target/linux/realtek/files-5.10/drivers/clocksource/timer-rtl-otto.c +++ /dev/null @@ -1,299 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -#include "timer-of.h" - -#define RTTM_DATA 0x0 -#define RTTM_CNT 0x4 -#define RTTM_CTRL 0x8 -#define RTTM_INT 0xc - -#define RTTM_CTRL_ENABLE BIT(28) -#define RTTM_INT_PENDING BIT(16) -#define RTTM_INT_ENABLE BIT(20) - -/* - * The Otto platform provides multiple 28 bit timers/counters with the following - * operating logic. If enabled the timer counts up. Per timer one can set a - * maximum counter value as an end marker. If end marker is reached the timer - * fires an interrupt. If the timer "overflows" by reaching the end marker or - * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and - * the timer is in operating mode COUNTER it stops. In mode TIMER it will - * continue to count up. - */ - -#define RTTM_CTRL_COUNTER 0 -#define RTTM_CTRL_TIMER BIT(24) - -#define RTTM_BIT_COUNT 28 -#define RTTM_MIN_DELTA 8 -#define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28) - -/* - * Timers are derived from the LXB clock frequency. Usually this is a fixed - * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that. - * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its - * base. The only meaningful frequencies we can achieve from that are 175.000 - * MHz and 153.125 MHz. The greatest common divisor of all explained possible - * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency. - */ - -#define RTTM_TICKS_PER_SEC 3125000 - -struct rttm_cs { - struct timer_of to; - struct clocksource cs; -}; - -/* - * Simple internal register functions - */ - -static inline void rttm_set_counter(void __iomem *base, unsigned int counter) -{ - iowrite32(counter, base + RTTM_CNT); -} - -static inline unsigned int rttm_get_counter(void __iomem *base) -{ - return ioread32(base + RTTM_CNT); -} - -static inline void rttm_set_period(void __iomem *base, unsigned int period) -{ - iowrite32(period, base + RTTM_DATA); -} - -static inline void rttm_disable_timer(void __iomem *base) -{ - iowrite32(0, base + RTTM_CTRL); -} - -static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor) -{ - iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL); -} - -static inline void rttm_ack_irq(void __iomem *base) -{ - iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT); -} - -static inline void rttm_enable_irq(void __iomem *base) -{ - iowrite32(RTTM_INT_ENABLE, base + RTTM_INT); -} - -static inline void rttm_disable_irq(void __iomem *base) -{ - iowrite32(0, base + RTTM_INT); -} - -/* - * Aggregated control functions for kernel clock framework - */ - -#define RTTM_DEBUG(base) \ - pr_debug("------------- %s %d %08x\n", __func__, \ - smp_processor_id(), (u32)base) - -static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *clkevt = dev_id; - struct timer_of *to = to_timer_of(clkevt); - - rttm_ack_irq(to->of_base.base); - RTTM_DEBUG(to->of_base.base); - clkevt->event_handler(clkevt); - - return IRQ_HANDLED; -} - -static void rttm_stop_timer(void __iomem *base) -{ - rttm_disable_timer(base); - rttm_ack_irq(base); -} - -static void rttm_start_timer(struct timer_of *to, u32 mode) -{ - rttm_set_counter(to->of_base.base, 0); - rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC); -} - -static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt) -{ - struct timer_of *to = to_timer_of(clkevt); - - RTTM_DEBUG(to->of_base.base); - rttm_stop_timer(to->of_base.base); - rttm_set_period(to->of_base.base, delta); - rttm_start_timer(to, RTTM_CTRL_COUNTER); - - return 0; -} - -static int rttm_state_oneshot(struct clock_event_device *clkevt) -{ - struct timer_of *to = to_timer_of(clkevt); - - RTTM_DEBUG(to->of_base.base); - rttm_stop_timer(to->of_base.base); - rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); - rttm_start_timer(to, RTTM_CTRL_COUNTER); - - return 0; -} - -static int rttm_state_periodic(struct clock_event_device *clkevt) -{ - struct timer_of *to = to_timer_of(clkevt); - - RTTM_DEBUG(to->of_base.base); - rttm_stop_timer(to->of_base.base); - rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); - rttm_start_timer(to, RTTM_CTRL_TIMER); - - return 0; -} - -static int rttm_state_shutdown(struct clock_event_device *clkevt) -{ - struct timer_of *to = to_timer_of(clkevt); - - RTTM_DEBUG(to->of_base.base); - rttm_stop_timer(to->of_base.base); - - return 0; -} - -static void rttm_setup_timer(void __iomem *base) -{ - RTTM_DEBUG(base); - rttm_stop_timer(base); - rttm_set_period(base, 0); -} - -static u64 rttm_read_clocksource(struct clocksource *cs) -{ - struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); - - return (u64)rttm_get_counter(rcs->to.of_base.base); -} - -/* - * Module initialization part. - */ - -static DEFINE_PER_CPU(struct timer_of, rttm_to) = { - .flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ, - .of_irq = { - .flags = IRQF_PERCPU | IRQF_TIMER, - .handler = rttm_timer_interrupt, - }, - .clkevt = { - .rating = 400, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_state_periodic = rttm_state_periodic, - .set_state_shutdown = rttm_state_shutdown, - .set_state_oneshot = rttm_state_oneshot, - .set_next_event = rttm_next_event - }, -}; - -static int rttm_enable_clocksource(struct clocksource *cs) -{ - struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); - - rttm_disable_irq(rcs->to.of_base.base); - rttm_setup_timer(rcs->to.of_base.base); - rttm_enable_timer(rcs->to.of_base.base, RTTM_CTRL_TIMER, - rcs->to.of_clk.rate / RTTM_TICKS_PER_SEC); - - return 0; -} - -struct rttm_cs rttm_cs = { - .to = { - .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, - }, - .cs = { - .name = "realtek_otto_timer", - .rating = 400, - .mask = CLOCKSOURCE_MASK(RTTM_BIT_COUNT), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .read = rttm_read_clocksource, - } -}; - -static u64 notrace rttm_read_clock(void) -{ - return (u64)rttm_get_counter(rttm_cs.to.of_base.base); -} - -static int rttm_cpu_starting(unsigned int cpu) -{ - struct timer_of *to = per_cpu_ptr(&rttm_to, cpu); - - RTTM_DEBUG(to->of_base.base); - to->clkevt.cpumask = cpumask_of(cpu); - irq_force_affinity(to->of_irq.irq, to->clkevt.cpumask); - clockevents_config_and_register(&to->clkevt, RTTM_TICKS_PER_SEC, - RTTM_MIN_DELTA, RTTM_MAX_DELTA); - rttm_enable_irq(to->of_base.base); - - return 0; -} - -static int __init rttm_probe(struct device_node *np) -{ - int cpu, cpu_rollback; - struct timer_of *to; - int clkidx = num_possible_cpus(); -/* - * Use the first n timers as per CPU clock event generators - */ - for_each_possible_cpu(cpu) { - to = per_cpu_ptr(&rttm_to, cpu); - to->of_irq.index = to->of_base.index = cpu; - if (timer_of_init(np, to)) { - pr_err("%s: setup of timer %d failed\n", __func__, cpu); - goto rollback; - } - rttm_setup_timer(to->of_base.base); - } -/* - * Activate the n'th+1 timer as a stable CPU clocksource. - */ - to = &rttm_cs.to; - to->of_base.index = clkidx; - timer_of_init(np, to); - if (rttm_cs.to.of_base.base && rttm_cs.to.of_clk.rate) { - rttm_enable_clocksource(&rttm_cs.cs); - clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC); - sched_clock_register(rttm_read_clock, RTTM_BIT_COUNT, RTTM_TICKS_PER_SEC); - } else - pr_err("%s: setup of timer %d as clocksoure failed", __func__, clkidx); - - return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING, - "timer/realtek:online", - rttm_cpu_starting, NULL); -rollback: - pr_err("%s: timer registration failed\n", __func__); - for_each_possible_cpu(cpu_rollback) { - if (cpu_rollback == cpu) - break; - to = per_cpu_ptr(&rttm_to, cpu_rollback); - timer_of_cleanup(to); - } - - return -EINVAL; -} - -TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe); diff --git a/target/linux/realtek/files-5.10/drivers/gpio/gpio-rtl8231.c b/target/linux/realtek/files-5.10/drivers/gpio/gpio-rtl8231.c deleted file mode 100644 index 368c4fa60f..0000000000 --- a/target/linux/realtek/files-5.10/drivers/gpio/gpio-rtl8231.c +++ /dev/null @@ -1,355 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include -#include -#include - -/* RTL8231 registers for LED control */ -#define RTL8231_LED_FUNC0 0x0000 -#define RTL8231_LED_FUNC1 0x0001 -#define RTL8231_READY_MASK 0x03f0 -#define RTL8231_READY_VALUE 0x0370 -#define RTL8231_GPIO_PIN_SEL(gpio) ((0x0002) + ((gpio) >> 4)) -#define RTL8231_GPIO_DIR(gpio) ((0x0005) + ((gpio) >> 4)) -#define RTL8231_GPIO_DATA(gpio) ((0x001C) + ((gpio) >> 4)) - -#define USEC_TIMEOUT 5000 - -#define RTL8231_SMI_BUS_ID_MAX 0x1F - -struct rtl8231_gpios { - struct gpio_chip gc; - struct device *dev; - u32 id; - u32 smi_bus_id; - u16 reg_shadow[0x20]; - u32 reg_cached; - int ext_gpio_indrt_access; -}; - -extern struct rtl83xx_soc_info soc_info; - -DEFINE_MUTEX(miim_lock); - -static u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg) -{ - u32 t = 0, n = 0; - - reg &= 0x1f; - - /* Calculate read register address */ - t = (gpios->smi_bus_id << 2) | (reg << 7); - - /* Set execution bit: cleared when operation completed */ - t |= 1; - - // Start execution - sw_w32(t, gpios->ext_gpio_indrt_access); - do { - udelay(1); - t = sw_r32(gpios->ext_gpio_indrt_access); - n++; - } while ((t & 1) && (n < USEC_TIMEOUT)); - - if (n >= USEC_TIMEOUT) - return 0x80000000; - - pr_debug("%s: %x, %x, %x\n", __func__, gpios->smi_bus_id, - reg, (t & 0xffff0000) >> 16); - - return (t & 0xffff0000) >> 16; -} - -static int rtl8231_write(struct rtl8231_gpios *gpios, u32 reg, u32 data) -{ - u32 t = 0, n = 0; - - pr_debug("%s: %x, %x, %x\n", __func__, gpios->smi_bus_id, reg, data); - reg &= 0x1f; - - t = (gpios->smi_bus_id << 2) | (reg << 7) | (data << 16); - /* Set write bit */ - t |= 2; - - /* Set execution bit: cleared when operation completed */ - t |= 1; - - // Start execution - sw_w32(t, gpios->ext_gpio_indrt_access); - do { - udelay(1); - t = sw_r32(gpios->ext_gpio_indrt_access); - } while ((t & 1) && (n < USEC_TIMEOUT)); - - if (n >= USEC_TIMEOUT) - return -1; - - return 0; -} - -static u32 rtl8231_read_cached(struct rtl8231_gpios *gpios, u32 reg) -{ - if (reg > 0x1f) - return 0; - - if (gpios->reg_cached & (1 << reg)) - return gpios->reg_shadow[reg]; - - return rtl8231_read(gpios, reg); -} - -/* Set Direction of the RTL8231 pin: - * dir 1: input - * dir 0: output - */ -static int rtl8231_pin_dir(struct rtl8231_gpios *gpios, u32 gpio, u32 dir) -{ - u32 v; - int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio); - int pin_dir_addr = RTL8231_GPIO_DIR(gpio); - int dpin = gpio % 16; - - if (gpio > 31) { - pr_debug("WARNING: HIGH pin\n"); - dpin += 5; - pin_dir_addr = pin_sel_addr; - } - - v = rtl8231_read_cached(gpios, pin_dir_addr); - if (v & 0x80000000) { - pr_err("Error reading RTL8231\n"); - return -1; - } - - v = (v & ~(1 << dpin)) | (dir << dpin); - rtl8231_write(gpios, pin_dir_addr, v); - gpios->reg_shadow[pin_dir_addr] = v; - gpios->reg_cached |= 1 << pin_dir_addr; - return 0; -} - -static int rtl8231_pin_dir_get(struct rtl8231_gpios *gpios, u32 gpio, u32 *dir) -{ - /* dir 1: input - * dir 0: output - */ - - u32 v; - int pin_dir_addr = RTL8231_GPIO_DIR(gpio); - int pin = gpio % 16; - - if (gpio > 31) { - pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio); - pin += 5; - } - - v = rtl8231_read(gpios, pin_dir_addr); - if (v & (1 << pin)) - *dir = 1; - else - *dir = 0; - return 0; -} - -static int rtl8231_pin_set(struct rtl8231_gpios *gpios, u32 gpio, u32 data) -{ - u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio)); - - pr_debug("%s: %d to %d\n", __func__, gpio, data); - if (v & 0x80000000) { - pr_err("Error reading RTL8231\n"); - return -1; - } - v = (v & ~(1 << (gpio % 16))) | (data << (gpio % 16)); - rtl8231_write(gpios, RTL8231_GPIO_DATA(gpio), v); - gpios->reg_shadow[RTL8231_GPIO_DATA(gpio)] = v; - gpios->reg_cached |= 1 << RTL8231_GPIO_DATA(gpio); - return 0; -} - -static int rtl8231_pin_get(struct rtl8231_gpios *gpios, u32 gpio, u16 *state) -{ - u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio)); - - if (v & 0x80000000) { - pr_err("Error reading RTL8231\n"); - return -1; - } - - *state = v & 0xffff; - return 0; -} - -static int rtl8231_direction_input(struct gpio_chip *gc, unsigned int offset) -{ - int err; - struct rtl8231_gpios *gpios = gpiochip_get_data(gc); - - pr_debug("%s: %d\n", __func__, offset); - mutex_lock(&miim_lock); - err = rtl8231_pin_dir(gpios, offset, 1); - mutex_unlock(&miim_lock); - return err; -} - -static int rtl8231_direction_output(struct gpio_chip *gc, unsigned int offset, int value) -{ - int err; - struct rtl8231_gpios *gpios = gpiochip_get_data(gc); - - pr_debug("%s: %d\n", __func__, offset); - mutex_lock(&miim_lock); - err = rtl8231_pin_dir(gpios, offset, 0); - mutex_unlock(&miim_lock); - if (!err) - err = rtl8231_pin_set(gpios, offset, value); - return err; -} - -static int rtl8231_get_direction(struct gpio_chip *gc, unsigned int offset) -{ - u32 v = 0; - struct rtl8231_gpios *gpios = gpiochip_get_data(gc); - - pr_debug("%s: %d\n", __func__, offset); - mutex_lock(&miim_lock); - rtl8231_pin_dir_get(gpios, offset, &v); - mutex_unlock(&miim_lock); - return v; -} - -static int rtl8231_gpio_get(struct gpio_chip *gc, unsigned int offset) -{ - u16 state = 0; - struct rtl8231_gpios *gpios = gpiochip_get_data(gc); - - mutex_lock(&miim_lock); - rtl8231_pin_get(gpios, offset, &state); - mutex_unlock(&miim_lock); - if (state & (1 << (offset % 16))) - return 1; - return 0; -} - -void rtl8231_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) -{ - struct rtl8231_gpios *gpios = gpiochip_get_data(gc); - - rtl8231_pin_set(gpios, offset, value); -} - -int rtl8231_init(struct rtl8231_gpios *gpios) -{ - u32 ret; - - pr_info("%s called, MDIO bus ID: %d\n", __func__, gpios->smi_bus_id); - - gpios->reg_cached = 0; - - if (soc_info.family == RTL8390_FAMILY_ID) { - // RTL8390: Enable external gpio in global led control register - sw_w32_mask(0x7 << 18, 0x4 << 18, RTL839X_LED_GLB_CTRL); - } else if (soc_info.family == RTL8380_FAMILY_ID) { - // RTL8380: Enable RTL8231 indirect access mode - sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL); - sw_w32_mask(3, 1, RTL838X_DMY_REG5); - } - - ret = rtl8231_read(gpios, RTL8231_LED_FUNC1); - if ((ret & 0x80000000) || ((ret & RTL8231_READY_MASK) != RTL8231_READY_VALUE)) - return -ENXIO; - - /* Select GPIO functionality and force input direction for pins 0-36 */ - rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(0), 0xffff); - rtl8231_write(gpios, RTL8231_GPIO_DIR(0), 0xffff); - rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(16), 0xffff); - rtl8231_write(gpios, RTL8231_GPIO_DIR(16), 0xffff); - rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(32), 0x03ff); - - /* Set LED_Start to enable drivers for output mode */ - rtl8231_write(gpios, RTL8231_LED_FUNC0, 1 << 1); - - return 0; -} - -static const struct of_device_id rtl8231_gpio_of_match[] = { - { .compatible = "realtek,rtl8231-gpio" }, - {}, -}; - -MODULE_DEVICE_TABLE(of, rtl8231_gpio_of_match); - -static int rtl8231_gpio_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - struct rtl8231_gpios *gpios; - int err; - - pr_info("Probing RTL8231 GPIOs\n"); - - if (!np) { - dev_err(&pdev->dev, "No DT found\n"); - return -EINVAL; - } - - gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL); - if (!gpios) - return -ENOMEM; - - gpios->id = soc_info.id; - if (soc_info.family == RTL8380_FAMILY_ID) { - gpios->ext_gpio_indrt_access = RTL838X_EXT_GPIO_INDRT_ACCESS; - } - - if (soc_info.family == RTL8390_FAMILY_ID) { - gpios->ext_gpio_indrt_access = RTL839X_EXT_GPIO_INDRT_ACCESS; - } - - err = of_property_read_u32(np, "indirect-access-bus-id", &gpios->smi_bus_id); - if (!err && gpios->smi_bus_id > RTL8231_SMI_BUS_ID_MAX) - err = -EINVAL; - - if (err) { - dev_err(dev, "invalid or missing indirect-access-bus-id\n"); - return err; - } - - err = rtl8231_init(gpios); - if (err) { - dev_err(dev, "no device found at bus address %d\n", gpios->smi_bus_id); - return err; - } - - gpios->dev = dev; - gpios->gc.base = -1; - gpios->gc.ngpio = 37; - gpios->gc.label = "rtl8231"; - gpios->gc.parent = dev; - gpios->gc.owner = THIS_MODULE; - gpios->gc.can_sleep = true; - - gpios->gc.direction_input = rtl8231_direction_input; - gpios->gc.direction_output = rtl8231_direction_output; - gpios->gc.set = rtl8231_gpio_set; - gpios->gc.get = rtl8231_gpio_get; - gpios->gc.get_direction = rtl8231_get_direction; - - err = devm_gpiochip_add_data(dev, &gpios->gc, gpios); - return err; -} - -static struct platform_driver rtl8231_gpio_driver = { - .driver = { - .name = "rtl8231-gpio", - .of_match_table = rtl8231_gpio_of_match, - }, - .probe = rtl8231_gpio_probe, -}; - -module_platform_driver(rtl8231_gpio_driver); - -MODULE_DESCRIPTION("Realtek RTL8231 GPIO expansion chip support"); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/realtek/files-5.10/drivers/i2c/busses/i2c-rtl9300.c b/target/linux/realtek/files-5.10/drivers/i2c/busses/i2c-rtl9300.c deleted file mode 100644 index 382dfd4010..0000000000 --- a/target/linux/realtek/files-5.10/drivers/i2c/busses/i2c-rtl9300.c +++ /dev/null @@ -1,488 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include "i2c-rtl9300.h" - -#define REG(i, x) (i->base + x + (i->scl_num ? i->mst2_offset : 0)) -#define REG_MASK(i, clear, set, reg) \ - writel((readl(REG(i, reg)) & ~(clear)) | (set), REG(i, reg)) - -struct i2c_drv_data { - int scl0_pin; - int scl1_pin; - int sda0_pin; - struct i2c_algorithm *algo; - int (*read)(struct rtl9300_i2c *i2c, u8 *buf, int len); - int (*write)(struct rtl9300_i2c *i2c, u8 *buf, int len); - void (*reg_addr_set)(struct rtl9300_i2c *i2c, u32 reg, u16 len); - int (*config_xfer)(struct rtl9300_i2c *i2c, u16 addr, u16 len); - int (*execute_xfer)(struct rtl9300_i2c *i2c, char read_write, int size, - union i2c_smbus_data * data, int len); - void (*writel)(struct rtl9300_i2c *i2c, u32 data); - void (*config_io)(struct rtl9300_i2c *i2c, int scl_num, int sda_num); - u32 mst2_offset; -}; - -DEFINE_MUTEX(i2c_lock); - -static void rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) -{ - // Set register address width - REG_MASK(i2c, 0x3 << RTL9300_I2C_CTRL2_MADDR_WIDTH, len << RTL9300_I2C_CTRL2_MADDR_WIDTH, - RTL9300_I2C_CTRL2); - - // Set register address - REG_MASK(i2c, 0xffffff << RTL9300_I2C_CTRL1_MEM_ADDR, reg << RTL9300_I2C_CTRL1_MEM_ADDR, - RTL9300_I2C_CTRL1); -} - -static void rtl9310_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len) -{ - // Set register address width - REG_MASK(i2c, 0x3 << RTL9310_I2C_CTRL_MADDR_WIDTH, len << RTL9310_I2C_CTRL_MADDR_WIDTH, - RTL9310_I2C_CTRL); - - // Set register address - writel(reg, REG(i2c, RTL9310_I2C_MEMADDR)); -} - -static void rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, int scl_num, int sda_num) -{ - u32 v; - - // Set SCL pin - REG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_GPIO8_SCL_SEL), RTL9300_I2C_CTRL1); - - // Set SDA pin - REG_MASK(i2c, 0x7 << RTL9300_I2C_CTRL1_SDA_OUT_SEL, - i2c->sda_num << RTL9300_I2C_CTRL1_SDA_OUT_SEL, RTL9300_I2C_CTRL1); - - // Set SDA pin to I2C functionality - v = readl(i2c->base + RTL9300_I2C_MST_GLB_CTRL); - v |= BIT(i2c->sda_num); - writel(v, i2c->base + RTL9300_I2C_MST_GLB_CTRL); -} - -static void rtl9310_i2c_config_io(struct rtl9300_i2c *i2c, int scl_num, int sda_num) -{ - u32 v; - - // Set SCL pin - REG_MASK(i2c, 0, BIT(RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL + scl_num), RTL9310_I2C_MST_IF_SEL); - - // Set SDA pin - REG_MASK(i2c, 0x7 << RTL9310_I2C_CTRL_SDA_OUT_SEL, - i2c->sda_num << RTL9310_I2C_CTRL_SDA_OUT_SEL, RTL9310_I2C_CTRL); - - // Set SDA pin to I2C functionality - v = readl(i2c->base + RTL9310_I2C_MST_IF_SEL); - v |= BIT(i2c->sda_num); - writel(v, i2c->base + RTL9310_I2C_MST_IF_SEL); -} - -static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len) -{ - // Set bus frequency - REG_MASK(i2c, 0x3 << RTL9300_I2C_CTRL2_SCL_FREQ, - i2c->bus_freq << RTL9300_I2C_CTRL2_SCL_FREQ, RTL9300_I2C_CTRL2); - - // Set slave device address - REG_MASK(i2c, 0x7f << RTL9300_I2C_CTRL2_DEV_ADDR, - addr << RTL9300_I2C_CTRL2_DEV_ADDR, RTL9300_I2C_CTRL2); - - // Set data length - REG_MASK(i2c, 0xf << RTL9300_I2C_CTRL2_DATA_WIDTH, - ((len - 1) & 0xf) << RTL9300_I2C_CTRL2_DATA_WIDTH, RTL9300_I2C_CTRL2); - - // Set read mode to random - REG_MASK(i2c, 0x1 << RTL9300_I2C_CTRL2_READ_MODE, 0, RTL9300_I2C_CTRL2); - - return 0; -} - -static int rtl9310_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len) -{ - // Set bus frequency - REG_MASK(i2c, 0x3 << RTL9310_I2C_CTRL_SCL_FREQ, - i2c->bus_freq << RTL9310_I2C_CTRL_SCL_FREQ, RTL9310_I2C_CTRL); - - // Set slave device address - REG_MASK(i2c, 0x7f << RTL9310_I2C_CTRL_DEV_ADDR, - addr << RTL9310_I2C_CTRL_DEV_ADDR, RTL9310_I2C_CTRL); - - // Set data length - REG_MASK(i2c, 0xf << RTL9310_I2C_CTRL_DATA_WIDTH, - ((len - 1) & 0xf) << RTL9310_I2C_CTRL_DATA_WIDTH, RTL9310_I2C_CTRL); - - // Set read mode to random - REG_MASK(i2c, 0x1 << RTL9310_I2C_CTRL_READ_MODE, 0, RTL9310_I2C_CTRL); - - return 0; -} - -static int i2c_read(void __iomem *r0, u8 *buf, int len) -{ - int i; - u32 v; - - if (len > 16) - return -EIO; - - for (i = 0; i < len; i++) { - if (i % 4 == 0) - v = readl(r0 + i); - buf[i] = v; - v >>= 8; - } - - return len; -} - -static int i2c_write(void __iomem *r0, u8 *buf, int len) -{ - u32 v; - int i; - - if (len > 16) - return -EIO; - - for (i = 0; i < len; i++) { - if (! (i % 4)) - v = 0; - v <<= 8; - v |= buf[i]; - if (i % 4 == 3 || i == len - 1) - writel(v, r0 + (i / 4) * 4); - } - - return len; -} - -static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) -{ - return i2c_read(REG(i2c, RTL9300_I2C_DATA_WORD0), buf, len); -} - -static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len) -{ - return i2c_write(REG(i2c, RTL9300_I2C_DATA_WORD0), buf, len); -} - -static int rtl9310_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len) -{ - return i2c_read(REG(i2c, RTL9310_I2C_DATA), buf, len); -} - -static int rtl9310_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len) -{ - return i2c_write(REG(i2c, RTL9310_I2C_DATA), buf, len); -} - -static void rtl9300_writel(struct rtl9300_i2c *i2c, u32 data) -{ - writel(data, REG(i2c, RTL9300_I2C_DATA_WORD0)); -} - -static void rtl9310_writel(struct rtl9300_i2c *i2c, u32 data) -{ - writel(data, REG(i2c, RTL9310_I2C_DATA)); -} - - -static int rtl9300_execute_xfer(struct rtl9300_i2c *i2c, char read_write, - int size, union i2c_smbus_data * data, int len) -{ - u32 v; - - if (read_write == I2C_SMBUS_READ) - REG_MASK(i2c, BIT(RTL9300_I2C_CTRL1_RWOP), 0, RTL9300_I2C_CTRL1); - else - REG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_RWOP), RTL9300_I2C_CTRL1); - - REG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_I2C_TRIG), RTL9300_I2C_CTRL1); - do { - v = readl(REG(i2c, RTL9300_I2C_CTRL1)); - } while (v & BIT(RTL9300_I2C_CTRL1_I2C_TRIG)); - - if (v & BIT(RTL9300_I2C_CTRL1_I2C_FAIL)) - return -EIO; - - if (read_write == I2C_SMBUS_READ) { - if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA){ - data->byte = readl(REG(i2c, RTL9300_I2C_DATA_WORD0)); - } else if (size == I2C_SMBUS_WORD_DATA) { - data->word = readl(REG(i2c, RTL9300_I2C_DATA_WORD0)); - } else if (len > 0) { - rtl9300_i2c_read(i2c, &data->block[0], len); - } - } - - return 0; -} - -static int rtl9310_execute_xfer(struct rtl9300_i2c *i2c, char read_write, - int size, union i2c_smbus_data * data, int len) -{ - u32 v; - - if (read_write == I2C_SMBUS_READ) - REG_MASK(i2c, BIT(RTL9310_I2C_CTRL_RWOP), 0, RTL9310_I2C_CTRL); - else - REG_MASK(i2c, 0, BIT(RTL9310_I2C_CTRL_RWOP), RTL9310_I2C_CTRL); - - REG_MASK(i2c, 0, BIT(RTL9310_I2C_CTRL_I2C_TRIG), RTL9310_I2C_CTRL); - do { - v = readl(REG(i2c, RTL9310_I2C_CTRL)); - } while (v & BIT(RTL9310_I2C_CTRL_I2C_TRIG)); - - if (v & BIT(RTL9310_I2C_CTRL_I2C_FAIL)) - return -EIO; - - if (read_write == I2C_SMBUS_READ) { - if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA){ - data->byte = readl(REG(i2c, RTL9310_I2C_DATA)); - } else if (size == I2C_SMBUS_WORD_DATA) { - data->word = readl(REG(i2c, RTL9310_I2C_DATA)); - } else if (len > 0) { - rtl9310_i2c_read(i2c, &data->block[0], len); - } - } - - return 0; -} - -static int rtl9300_i2c_smbus_xfer(struct i2c_adapter * adap, u16 addr, - unsigned short flags, char read_write, - u8 command, int size, union i2c_smbus_data * data) -{ - struct rtl9300_i2c *i2c = i2c_get_adapdata(adap); - struct i2c_drv_data *drv_data = (struct i2c_drv_data *)device_get_match_data(i2c->dev); - int len = 0, ret; - - mutex_lock(&i2c_lock); - switch (size) { - case I2C_SMBUS_QUICK: - drv_data->config_xfer(i2c, addr, 0); - drv_data->reg_addr_set(i2c, 0, 0); - break; - - case I2C_SMBUS_BYTE: - if (read_write == I2C_SMBUS_WRITE) { - drv_data->config_xfer(i2c, addr, 0); - drv_data->reg_addr_set(i2c, command, 1); - } else { - drv_data->config_xfer(i2c, addr, 1); - drv_data->reg_addr_set(i2c, 0, 0); - } - break; - - case I2C_SMBUS_BYTE_DATA: - pr_debug("I2C_SMBUS_BYTE_DATA %02x, read %d cmd %02x\n", addr, read_write, command); - drv_data->reg_addr_set(i2c, command, 1); - drv_data->config_xfer(i2c, addr, 1); - - if (read_write == I2C_SMBUS_WRITE) { - pr_debug("--> data %02x\n", data->byte); - drv_data->writel(i2c, data->byte); - } - break; - - case I2C_SMBUS_WORD_DATA: - pr_debug("I2C_SMBUS_WORD %02x, read %d\n", addr, read_write); - drv_data->reg_addr_set(i2c, command, 1); - drv_data->config_xfer(i2c, addr, 2); - if (read_write == I2C_SMBUS_WRITE) - drv_data->writel(i2c, data->word); - break; - - case I2C_SMBUS_BLOCK_DATA: - pr_debug("I2C_SMBUS_BLOCK_DATA %02x, read %d, len %d\n", - addr, read_write, data->block[0]); - drv_data->reg_addr_set(i2c, command, 1); - drv_data->config_xfer(i2c, addr, data->block[0]); - if (read_write == I2C_SMBUS_WRITE) - drv_data->write(i2c, &data->block[1], data->block[0]); - len = data->block[0]; - break; - - default: - dev_warn(&adap->dev, "Unsupported transaction %d\n", size); - return -EOPNOTSUPP; - } - - ret = drv_data->execute_xfer(i2c, read_write, size, data, len); - - mutex_unlock(&i2c_lock); - - return ret; -} - -static u32 rtl9300_i2c_func(struct i2c_adapter *a) -{ - return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | - I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | - I2C_FUNC_SMBUS_BLOCK_DATA; -} - -static const struct i2c_algorithm rtl9300_i2c_algo = { - .smbus_xfer = rtl9300_i2c_smbus_xfer, - .functionality = rtl9300_i2c_func, -}; - -struct i2c_adapter_quirks rtl9300_i2c_quirks = { - .flags = I2C_AQ_NO_CLK_STRETCH, - .max_read_len = 16, - .max_write_len = 16, -}; - -static int rtl9300_i2c_probe(struct platform_device *pdev) -{ - struct resource *res; - struct rtl9300_i2c *i2c; - struct i2c_adapter *adap; - struct i2c_drv_data *drv_data; - struct device_node *node = pdev->dev.of_node; - u32 clock_freq, pin; - int ret = 0; - - pr_info("%s probing I2C adapter\n", __func__); - - if (!node) { - dev_err(i2c->dev, "No DT found\n"); - return -EINVAL; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - drv_data = (struct i2c_drv_data *) device_get_match_data(&pdev->dev); - - i2c = devm_kzalloc(&pdev->dev, sizeof(struct rtl9300_i2c), GFP_KERNEL); - if (!i2c) - return -ENOMEM; - - i2c->base = devm_ioremap_resource(&pdev->dev, res); - i2c->mst2_offset = drv_data->mst2_offset; - if (IS_ERR(i2c->base)) - return PTR_ERR(i2c->base); - - pr_debug("%s base memory %08x\n", __func__, (u32)i2c->base); - i2c->dev = &pdev->dev; - - if (of_property_read_u32(node, "clock-frequency", &clock_freq)) { - clock_freq = I2C_MAX_STANDARD_MODE_FREQ; - } - switch(clock_freq) { - case I2C_MAX_STANDARD_MODE_FREQ: - i2c->bus_freq = RTL9300_I2C_STD_FREQ; - break; - - case I2C_MAX_FAST_MODE_FREQ: - i2c->bus_freq = RTL9300_I2C_FAST_FREQ; - break; - default: - dev_warn(i2c->dev, "clock-frequency %d not supported\n", clock_freq); - return -EINVAL; - } - - dev_info(&pdev->dev, "SCL speed %d, mode is %d\n", clock_freq, i2c->bus_freq); - - if (of_property_read_u32(node, "scl-pin", &pin)) { - dev_warn(i2c->dev, "SCL pin not found in DT, using default\n"); - pin = drv_data->scl0_pin; - } - if (!(pin == drv_data->scl0_pin || pin == drv_data->scl1_pin)) { - dev_warn(i2c->dev, "SCL pin %d not supported\n", pin); - return -EINVAL; - } - i2c->scl_num = pin == drv_data->scl0_pin ? 0 : 1; - pr_info("%s scl_num %d\n", __func__, i2c->scl_num); - - if (of_property_read_u32(node, "sda-pin", &pin)) { - dev_warn(i2c->dev, "SDA pin not found in DT, using default \n"); - pin = drv_data->sda0_pin; - } - i2c->sda_num = pin - drv_data->sda0_pin; - if (i2c->sda_num < 0 || i2c->sda_num > 7) { - dev_warn(i2c->dev, "SDA pin %d not supported\n", pin); - return -EINVAL; - } - pr_info("%s sda_num %d\n", __func__, i2c->sda_num); - - adap = &i2c->adap; - adap->owner = THIS_MODULE; - adap->algo = &rtl9300_i2c_algo; - adap->retries = 3; - adap->dev.parent = &pdev->dev; - i2c_set_adapdata(adap, i2c); - adap->dev.of_node = node; - strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); - - platform_set_drvdata(pdev, i2c); - - drv_data->config_io(i2c, i2c->scl_num, i2c->sda_num); - - ret = i2c_add_adapter(adap); - - return ret; -} - -static int rtl9300_i2c_remove(struct platform_device *pdev) -{ - struct rtl9300_i2c *i2c = platform_get_drvdata(pdev); - - i2c_del_adapter(&i2c->adap); - - return 0; -} - -struct i2c_drv_data rtl9300_i2c_drv_data = { - .scl0_pin = 8, - .scl1_pin = 17, - .sda0_pin = 9, - .read = rtl9300_i2c_read, - .read = rtl9300_i2c_write, - .reg_addr_set = rtl9300_i2c_reg_addr_set, - .config_xfer = rtl9300_i2c_config_xfer, - .execute_xfer = rtl9300_execute_xfer, - .writel = rtl9300_writel, - .config_io = rtl9300_i2c_config_io, - .mst2_offset = 0x1c, -}; - -struct i2c_drv_data rtl9310_i2c_drv_data = { - .scl0_pin = 13, - .scl1_pin = 14, - .sda0_pin = 0, - .read = rtl9310_i2c_read, - .read = rtl9310_i2c_write, - .reg_addr_set = rtl9310_i2c_reg_addr_set, - .config_xfer = rtl9310_i2c_config_xfer, - .execute_xfer = rtl9310_execute_xfer, - .writel = rtl9310_writel, - .config_io = rtl9310_i2c_config_io, - .mst2_offset = 0x18, -}; - -static const struct of_device_id i2c_rtl9300_dt_ids[] = { - { .compatible = "realtek,rtl9300-i2c", .data = (void *) &rtl9300_i2c_drv_data }, - { .compatible = "realtek,rtl9310-i2c", .data = (void *) &rtl9310_i2c_drv_data }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids); - -static struct platform_driver rtl9300_i2c_driver = { - .probe = rtl9300_i2c_probe, - .remove = rtl9300_i2c_remove, - .driver = { - .name = "i2c-rtl9300", - .pm = NULL, - .of_match_table = i2c_rtl9300_dt_ids, - }, -}; - -module_platform_driver(rtl9300_i2c_driver); - -MODULE_AUTHOR("Birger Koblitz"); -MODULE_DESCRIPTION("RTL9300 I2C host driver"); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/realtek/files-5.10/drivers/i2c/busses/i2c-rtl9300.h b/target/linux/realtek/files-5.10/drivers/i2c/busses/i2c-rtl9300.h deleted file mode 100644 index b10c38c91c..0000000000 --- a/target/linux/realtek/files-5.10/drivers/i2c/busses/i2c-rtl9300.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef I2C_RTL9300_H -#define I2C_RTL9300_H - -#include - -#define RTL9300_I2C_CTRL1 0x00 -#define RTL9300_I2C_CTRL1_MEM_ADDR 8 -#define RTL9300_I2C_CTRL1_SDA_OUT_SEL 4 -#define RTL9300_I2C_CTRL1_GPIO8_SCL_SEL 3 -#define RTL9300_I2C_CTRL1_RWOP 2 -#define RTL9300_I2C_CTRL1_I2C_FAIL 1 -#define RTL9300_I2C_CTRL1_I2C_TRIG 0 - -#define RTL9300_I2C_CTRL2 0x04 -#define RTL9300_I2C_CTRL2_DRIVE_ACK_DELAY 20 -#define RTL9300_I2C_CTRL2_CHECK_ACK_DELAY 16 -#define RTL9300_I2C_CTRL2_READ_MODE 15 -#define RTL9300_I2C_CTRL2_DEV_ADDR 8 -#define RTL9300_I2C_CTRL2_DATA_WIDTH 4 -#define RTL9300_I2C_CTRL2_MADDR_WIDTH 2 -#define RTL9300_I2C_CTRL2_SCL_FREQ 0 - -#define RTL9300_I2C_DATA_WORD0 0x08 - -#define RTL9300_I2C_MST_GLB_CTRL 0x18 - -#define RTL9310_I2C_MST_IF_CTRL 0x00 - -#define RTL9310_I2C_MST_IF_SEL 0x04 -#define RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL 12 - -#define RTL9310_I2C_CTRL 0x08 -#define RTL9310_I2C_CTRL_SCL_FREQ 30 -#define RTL9310_I2C_CTRL_CHECK_ACK_DELAY 26 -#define RTL9310_I2C_CTRL_DRIVE_ACK_DELAY 22 -#define RTL9310_I2C_CTRL_SDA_OUT_SEL 18 -#define RTL9310_I2C_CTRL_DEV_ADDR 11 -#define RTL9310_I2C_CTRL_MADDR_WIDTH 9 -#define RTL9310_I2C_CTRL_DATA_WIDTH 5 -#define RTL9310_I2C_CTRL_READ_MODE 4 -#define RTL9310_I2C_CTRL_RWOP 2 -#define RTL9310_I2C_CTRL_I2C_FAIL 1 -#define RTL9310_I2C_CTRL_I2C_TRIG 0 - -#define RTL9310_I2C_MEMADDR 0x0c - -#define RTL9310_I2C_DATA 0x10 - -#define RTL9300_I2C_STD_FREQ 0 -#define RTL9300_I2C_FAST_FREQ 1 - -struct rtl9300_i2c { - void __iomem *base; - u32 mst2_offset; - struct device *dev; - struct i2c_adapter adap; - u8 bus_freq; - u8 sda_num; // SDA channel number - u8 scl_num; // SCL channel, mapping to master 1 or 2 -}; - -#endif diff --git a/target/linux/realtek/files-5.10/drivers/i2c/muxes/i2c-mux-rtl9300.c b/target/linux/realtek/files-5.10/drivers/i2c/muxes/i2c-mux-rtl9300.c deleted file mode 100644 index 2f45b0a3cc..0000000000 --- a/target/linux/realtek/files-5.10/drivers/i2c/muxes/i2c-mux-rtl9300.c +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * I2C multiplexer for the 2 I2C Masters of the RTL9300 - * with up to 8 channels each, but which are not entirely - * independent of each other - */ -#include -#include -#include -#include -#include -#include - -#include "../busses/i2c-rtl9300.h" - -#define NUM_MASTERS 2 -#define NUM_BUSSES 8 - -#define REG(mst, x) (mux->base + x + (mst ? mux->i2c->mst2_offset : 0)) -#define REG_MASK(mst, clear, set, reg) \ - writel((readl(REG((mst),(reg))) & ~(clear)) | (set), REG((mst),(reg))) - -struct channel { - u8 sda_num; - u8 scl_num; -}; - -static struct channel channels[NUM_MASTERS * NUM_BUSSES]; - -struct rtl9300_mux { - void __iomem *base; - struct device *dev; - struct i2c_adapter *parent; - struct rtl9300_i2c * i2c; -}; - -struct i2c_mux_data { - int scl0_pin; - int scl1_pin; - int sda0_pin; - int sda_pins; - int (*i2c_mux_select)(struct i2c_mux_core *muxc, u32 chan); - int (*i2c_mux_deselect)(struct i2c_mux_core *muxc, u32 chan); - void (*sda_sel)(struct i2c_mux_core *muxc, int pin); -}; - -static int rtl9300_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan) -{ - struct rtl9300_mux *mux = i2c_mux_priv(muxc); - - // Set SCL pin - REG_MASK(channels[chan].scl_num, 0, - BIT(RTL9300_I2C_CTRL1_GPIO8_SCL_SEL), RTL9300_I2C_CTRL1); - - // Set SDA pin - REG_MASK(channels[chan].scl_num, 0x7 << RTL9300_I2C_CTRL1_SDA_OUT_SEL, - channels[chan].sda_num << RTL9300_I2C_CTRL1_SDA_OUT_SEL, RTL9300_I2C_CTRL1); - - mux->i2c->sda_num = channels[chan].sda_num; - mux->i2c->scl_num = channels[chan].scl_num; - - return 0; -} - -static int rtl9310_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan) -{ - struct rtl9300_mux *mux = i2c_mux_priv(muxc); - - // Set SCL pin - REG_MASK(0, 0, BIT(RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL + channels[chan].scl_num), - RTL9310_I2C_MST_IF_SEL); - - // Set SDA pin - REG_MASK(channels[chan].scl_num, 0xf << RTL9310_I2C_CTRL_SDA_OUT_SEL, - channels[chan].sda_num << RTL9310_I2C_CTRL_SDA_OUT_SEL, RTL9310_I2C_CTRL); - - mux->i2c->sda_num = channels[chan].sda_num; - mux->i2c->scl_num = channels[chan].scl_num; - - return 0; -} - -static int rtl9300_i2c_mux_deselect(struct i2c_mux_core *muxc, u32 chan) -{ - return 0; -} - -static void rtl9300_sda_sel(struct i2c_mux_core *muxc, int pin) -{ - struct rtl9300_mux *mux = i2c_mux_priv(muxc); - u32 v; - - // Set SDA pin to I2C functionality - v = readl(REG(0, RTL9300_I2C_MST_GLB_CTRL)); - v |= BIT(pin); - writel(v, REG(0, RTL9300_I2C_MST_GLB_CTRL)); -} - -static void rtl9310_sda_sel(struct i2c_mux_core *muxc, int pin) -{ - struct rtl9300_mux *mux = i2c_mux_priv(muxc); - u32 v; - - // Set SDA pin to I2C functionality - v = readl(REG(0, RTL9310_I2C_MST_IF_SEL)); - v |= BIT(pin); - writel(v, REG(0, RTL9310_I2C_MST_IF_SEL)); -} - -static struct device_node *mux_parent_adapter(struct device *dev, struct rtl9300_mux *mux) -{ - struct device_node *node = dev->of_node; - struct device_node *parent_np; - struct i2c_adapter *parent; - - parent_np = of_parse_phandle(node, "i2c-parent", 0); - if (!parent_np) { - dev_err(dev, "Cannot parse i2c-parent\n"); - return ERR_PTR(-ENODEV); - } - parent = of_find_i2c_adapter_by_node(parent_np); - of_node_put(parent_np); - if (!parent) - return ERR_PTR(-EPROBE_DEFER); - - if (!(of_device_is_compatible(parent_np, "realtek,rtl9300-i2c") - || of_device_is_compatible(parent_np, "realtek,rtl9310-i2c"))){ - dev_err(dev, "I2C parent not an RTL9300 I2C controller\n"); - return ERR_PTR(-ENODEV); - } - - mux->parent = parent; - mux->i2c = (struct rtl9300_i2c *)i2c_get_adapdata(parent); - mux->base = mux->i2c->base; - - return parent_np; -} - -struct i2c_mux_data rtl9300_i2c_mux_data = { - .scl0_pin = 8, - .scl1_pin = 17, - .sda0_pin = 9, - .sda_pins = 8, - .i2c_mux_select = rtl9300_i2c_mux_select, - .i2c_mux_deselect = rtl9300_i2c_mux_deselect, - .sda_sel = rtl9300_sda_sel, -}; - -struct i2c_mux_data rtl9310_i2c_mux_data = { - .scl0_pin = 13, - .scl1_pin = 14, - .sda0_pin = 0, - .sda_pins = 16, - .i2c_mux_select = rtl9310_i2c_mux_select, - .i2c_mux_deselect = rtl9300_i2c_mux_deselect, - .sda_sel = rtl9310_sda_sel, -}; - -static const struct of_device_id rtl9300_i2c_mux_of_match[] = { - { .compatible = "realtek,i2c-mux-rtl9300", .data = (void *) &rtl9300_i2c_mux_data}, - { .compatible = "realtek,i2c-mux-rtl9310", .data = (void *) &rtl9310_i2c_mux_data}, - {}, -}; - -MODULE_DEVICE_TABLE(of, rtl9300_i2c_mux_of_match); - -static int rtl9300_i2c_mux_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct device_node *node = dev->of_node; - struct device_node *parent_np; - struct device_node *child; - struct i2c_mux_core *muxc; - struct rtl9300_mux *mux; - struct i2c_mux_data *mux_data; - int children; - int ret; - - pr_info("%s probing I2C adapter\n", __func__); - - if (!node) { - dev_err(dev, "No DT found\n"); - return -EINVAL; - } - - mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); - if (!mux) - return -ENOMEM; - - mux->dev = dev; - - mux_data = (struct i2c_mux_data *) device_get_match_data(dev); - - parent_np = mux_parent_adapter(dev, mux); - if (IS_ERR(parent_np)) - return dev_err_probe(dev, PTR_ERR(parent_np), "i2c-parent adapter not found\n"); - - pr_info("%s base memory %08x\n", __func__, (u32)mux->base); - - children = of_get_child_count(node); - - muxc = i2c_mux_alloc(mux->parent, dev, children, 0, 0, - mux_data->i2c_mux_select, mux_data->i2c_mux_deselect); - if (!muxc) { - ret = -ENOMEM; - goto err_parent; - } - muxc->priv = mux; - - platform_set_drvdata(pdev, muxc); - - for_each_child_of_node(node, child) { - u32 chan; - u32 pin; - - ret = of_property_read_u32(child, "reg", &chan); - if (ret < 0) { - dev_err(dev, "no reg property for node '%pOFn'\n", - child); - goto err_children; - } - - if (chan >= NUM_MASTERS * NUM_BUSSES) { - dev_err(dev, "invalid reg %u\n", chan); - ret = -EINVAL; - goto err_children; - } - - if (of_property_read_u32(child, "scl-pin", &pin)) { - dev_warn(dev, "SCL pin not found in DT, using default\n"); - pin = mux_data->scl0_pin; - } - if (!(pin == mux_data->scl0_pin || pin == mux_data->scl1_pin)) { - dev_warn(dev, "SCL pin %d not supported\n", pin); - ret = -EINVAL; - goto err_children; - } - channels[chan].scl_num = pin == mux_data->scl0_pin ? 0 : 1; - pr_info("%s channel %d scl_num %d\n", __func__, chan, channels[chan].scl_num); - - if (of_property_read_u32(child, "sda-pin", &pin)) { - dev_warn(dev, "SDA pin not found in DT, using default \n"); - pin = mux_data->sda0_pin; - } - channels[chan].sda_num = pin - mux_data->sda0_pin; - if (channels[chan].sda_num < 0 || channels[chan].sda_num >= mux_data->sda_pins) { - dev_warn(dev, "SDA pin %d not supported\n", pin); - return -EINVAL; - } - pr_info("%s channel %d sda_num %d\n", __func__, chan, channels[chan].sda_num); - - mux_data->sda_sel(muxc, channels[chan].sda_num); - - ret = i2c_mux_add_adapter(muxc, 0, chan, 0); - if (ret) - goto err_children; - } - - dev_info(dev, "%d-port mux on %s adapter\n", children, mux->parent->name); - - return 0; - -err_children: - i2c_mux_del_adapters(muxc); -err_parent: - i2c_put_adapter(mux->parent); - - return ret; -} - -static int rtl9300_i2c_mux_remove(struct platform_device *pdev) -{ - struct i2c_mux_core *muxc = platform_get_drvdata(pdev); - - i2c_mux_del_adapters(muxc); - i2c_put_adapter(muxc->parent); - - return 0; -} - -static struct platform_driver i2c_mux_driver = { - .probe = rtl9300_i2c_mux_probe, - .remove = rtl9300_i2c_mux_remove, - .driver = { - .name = "i2c-mux-rtl9300", - .of_match_table = rtl9300_i2c_mux_of_match, - }, -}; -module_platform_driver(i2c_mux_driver); - -MODULE_DESCRIPTION("RTL9300 I2C multiplexer driver"); -MODULE_AUTHOR("Birger Koblitz"); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/Kconfig b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/Kconfig deleted file mode 100644 index 281f08054f..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -config NET_DSA_RTL83XX - tristate "Realtek RTL838x/RTL839x switch support" - depends on RTL83XX - select NET_DSA_TAG_TRAILER - help - This driver adds support for Realtek RTL83xx series switching. - diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/Makefile b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/Makefile deleted file mode 100644 index 8752c79700..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_NET_DSA_RTL83XX) += common.o dsa.o \ - rtl838x.o rtl839x.o rtl930x.o rtl931x.o debugfs.o qos.o tc.o diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c deleted file mode 100644 index d2d6772300..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c +++ /dev/null @@ -1,1708 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "rtl83xx.h" - -extern struct rtl83xx_soc_info soc_info; - -extern const struct rtl838x_reg rtl838x_reg; -extern const struct rtl838x_reg rtl839x_reg; -extern const struct rtl838x_reg rtl930x_reg; -extern const struct rtl838x_reg rtl931x_reg; - -extern const struct dsa_switch_ops rtl83xx_switch_ops; -extern const struct dsa_switch_ops rtl930x_switch_ops; - -DEFINE_MUTEX(smi_lock); - -int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port) -{ - u32 msti = 0; - u32 port_state[4]; - int index, bit; - int pos = port; - int n = priv->port_width << 1; - - /* Ports above or equal CPU port can never be configured */ - if (port >= priv->cpu_port) - return -1; - - mutex_lock(&priv->reg_mutex); - - /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */ - if (priv->family_id == RTL8390_FAMILY_ID) - pos += 12; - if (priv->family_id == RTL9300_FAMILY_ID) - pos += 3; - if (priv->family_id == RTL9310_FAMILY_ID) - pos += 8; - - index = n - (pos >> 4) - 1; - bit = (pos << 1) % 32; - - priv->r->stp_get(priv, msti, port_state); - - mutex_unlock(&priv->reg_mutex); - - return (port_state[index] >> bit) & 3; -} - -static struct table_reg rtl838x_tbl_regs[] = { - TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2 - TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0 - TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1 - - TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2 - TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0 - TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1 - TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2 - - TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2 - TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0 - TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1 - TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2 - TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB - TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA - - TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0 - TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1 - TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2 - TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3 - TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4 - TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5 -}; - -void rtl_table_init(void) -{ - int i; - - for (i = 0; i < RTL_TBL_END; i++) - mutex_init(&rtl838x_tbl_regs[i].lock); -} - -/* - * Request access to table t in table access register r - * Returns a handle to a lock for that table - */ -struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t) -{ - if (r >= RTL_TBL_END) - return NULL; - - if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit)) - return NULL; - - mutex_lock(&rtl838x_tbl_regs[r].lock); - rtl838x_tbl_regs[r].tbl = t; - - return &rtl838x_tbl_regs[r]; -} - -/* - * Release a table r, unlock the corresponding lock - */ -void rtl_table_release(struct table_reg *r) -{ - if (!r) - return; - -// pr_info("Unlocking %08x\n", (u32)r); - mutex_unlock(&r->lock); -// pr_info("Unlock done\n"); -} - -static int rtl_table_exec(struct table_reg *r, bool is_write, int idx) -{ - int ret = 0; - u32 cmd, val; - - /* Read/write bit has inverted meaning on RTL838x */ - if (r->rmode) - cmd = is_write ? 0 : BIT(r->c_bit); - else - cmd = is_write ? BIT(r->c_bit) : 0; - - cmd |= BIT(r->c_bit + 1); /* Execute bit */ - cmd |= r->tbl << r->t_bit; /* Table type */ - cmd |= idx & (BIT(r->t_bit) - 1); /* Index */ - - sw_w32(cmd, r->addr); - - ret = readx_poll_timeout(sw_r32, r->addr, val, - !(val & BIT(r->c_bit + 1)), 20, 10000); - if (ret) - pr_err("%s: timeout\n", __func__); - - return ret; -} - -/* - * Reads table index idx into the data registers of the table - */ -int rtl_table_read(struct table_reg *r, int idx) -{ - return rtl_table_exec(r, false, idx); -} - -/* - * Writes the content of the table data registers into the table at index idx - */ -int rtl_table_write(struct table_reg *r, int idx) -{ - return rtl_table_exec(r, true, idx); -} - -/* - * Returns the address of the ith data register of table register r - * the address is relative to the beginning of the Switch-IO block at 0xbb000000 - */ -inline u16 rtl_table_data(struct table_reg *r, int i) -{ - if (i >= r->max_data) - i = r->max_data - 1; - return r->data + i * 4; -} - -inline u32 rtl_table_data_r(struct table_reg *r, int i) -{ - return sw_r32(rtl_table_data(r, i)); -} - -inline void rtl_table_data_w(struct table_reg *r, u32 v, int i) -{ - sw_w32(v, rtl_table_data(r, i)); -} - -/* Port register accessor functions for the RTL838x and RTL930X SoCs */ -void rtl838x_mask_port_reg(u64 clear, u64 set, int reg) -{ - sw_w32_mask((u32)clear, (u32)set, reg); -} - -void rtl838x_set_port_reg(u64 set, int reg) -{ - sw_w32((u32)set, reg); -} - -u64 rtl838x_get_port_reg(int reg) -{ - return ((u64) sw_r32(reg)); -} - -/* Port register accessor functions for the RTL839x and RTL931X SoCs */ -void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg) -{ - sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg); - sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4); -} - -u64 rtl839x_get_port_reg_be(int reg) -{ - u64 v = sw_r32(reg); - - v <<= 32; - v |= sw_r32(reg + 4); - return v; -} - -void rtl839x_set_port_reg_be(u64 set, int reg) -{ - sw_w32(set >> 32, reg); - sw_w32(set & 0xffffffff, reg + 4); -} - -void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg) -{ - sw_w32_mask((u32)clear, (u32)set, reg); - sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4); -} - -void rtl839x_set_port_reg_le(u64 set, int reg) -{ - sw_w32(set, reg); - sw_w32(set >> 32, reg + 4); -} - -u64 rtl839x_get_port_reg_le(int reg) -{ - u64 v = sw_r32(reg + 4); - - v <<= 32; - v |= sw_r32(reg); - return v; -} - -int read_phy(u32 port, u32 page, u32 reg, u32 *val) -{ - switch (soc_info.family) { - case RTL8380_FAMILY_ID: - return rtl838x_read_phy(port, page, reg, val); - case RTL8390_FAMILY_ID: - return rtl839x_read_phy(port, page, reg, val); - case RTL9300_FAMILY_ID: - return rtl930x_read_phy(port, page, reg, val); - case RTL9310_FAMILY_ID: - return rtl931x_read_phy(port, page, reg, val); - } - return -1; -} - -int write_phy(u32 port, u32 page, u32 reg, u32 val) -{ - switch (soc_info.family) { - case RTL8380_FAMILY_ID: - return rtl838x_write_phy(port, page, reg, val); - case RTL8390_FAMILY_ID: - return rtl839x_write_phy(port, page, reg, val); - case RTL9300_FAMILY_ID: - return rtl930x_write_phy(port, page, reg, val); - case RTL9310_FAMILY_ID: - return rtl931x_write_phy(port, page, reg, val); - } - return -1; -} - -static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) -{ - struct device *dev = priv->dev; - struct device_node *dn, *phy_node, *mii_np = dev->of_node; - struct mii_bus *bus; - int ret; - u32 pn; - - pr_debug("In %s\n", __func__); - mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio"); - if (mii_np) { - pr_debug("Found compatible MDIO node!\n"); - } else { - dev_err(priv->dev, "no %s child node found", "mdio-bus"); - return -ENODEV; - } - - priv->mii_bus = of_mdio_find_bus(mii_np); - if (!priv->mii_bus) { - pr_debug("Deferring probe of mdio bus\n"); - return -EPROBE_DEFER; - } - if (!of_device_is_available(mii_np)) - ret = -ENODEV; - - bus = devm_mdiobus_alloc(priv->ds->dev); - if (!bus) - return -ENOMEM; - - bus->name = "rtl838x slave mii"; - - /* - * Since the NIC driver is loaded first, we can use the mdio rw functions - * assigned there. - */ - bus->read = priv->mii_bus->read; - bus->write = priv->mii_bus->write; - bus->read_paged = priv->mii_bus->read_paged; - bus->write_paged = priv->mii_bus->write_paged; - snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id); - - bus->parent = dev; - priv->ds->slave_mii_bus = bus; - priv->ds->slave_mii_bus->priv = priv->mii_bus->priv; - priv->ds->slave_mii_bus->access_capabilities = priv->mii_bus->access_capabilities; - - ret = mdiobus_register(priv->ds->slave_mii_bus); - if (ret && mii_np) { - of_node_put(dn); - return ret; - } - - dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch"); - if (!dn) { - dev_err(priv->dev, "No RTL switch node in DTS\n"); - return -ENODEV; - } - - for_each_node_by_name(dn, "port") { - phy_interface_t interface; - u32 led_set; - - if (!of_device_is_available(dn)) - continue; - - if (of_property_read_u32(dn, "reg", &pn)) - continue; - - phy_node = of_parse_phandle(dn, "phy-handle", 0); - if (!phy_node) { - if (pn != priv->cpu_port) - dev_err(priv->dev, "Port node %d misses phy-handle\n", pn); - continue; - } - - if (of_property_read_u32(phy_node, "sds", &priv->ports[pn].sds_num)) - priv->ports[pn].sds_num = -1; - pr_debug("%s port %d has SDS %d\n", __func__, pn, priv->ports[pn].sds_num); - - if (of_get_phy_mode(dn, &interface)) - interface = PHY_INTERFACE_MODE_NA; - if (interface == PHY_INTERFACE_MODE_HSGMII) - priv->ports[pn].is2G5 = true; - if (interface == PHY_INTERFACE_MODE_USXGMII) - priv->ports[pn].is2G5 = priv->ports[pn].is10G = true; - if (interface == PHY_INTERFACE_MODE_10GBASER) - priv->ports[pn].is10G = true; - - if (of_property_read_u32(dn, "led-set", &led_set)) - led_set = 0; - priv->ports[pn].led_set = led_set; - - // Check for the integrated SerDes of the RTL8380M first - if (of_property_read_bool(phy_node, "phy-is-integrated") - && priv->id == 0x8380 && pn >= 24) { - pr_debug("----> FÓUND A SERDES\n"); - priv->ports[pn].phy = PHY_RTL838X_SDS; - continue; - } - - if (priv->id >= 0x9300) { - priv->ports[pn].phy_is_integrated = false; - if (of_property_read_bool(phy_node, "phy-is-integrated")) { - priv->ports[pn].phy_is_integrated = true; - priv->ports[pn].phy = PHY_RTL930X_SDS; - } - } else { - if (of_property_read_bool(phy_node, "phy-is-integrated") - && !of_property_read_bool(phy_node, "sfp")) { - priv->ports[pn].phy = PHY_RTL8218B_INT; - continue; - } - } - - if (!of_property_read_bool(phy_node, "phy-is-integrated") - && of_property_read_bool(phy_node, "sfp")) { - priv->ports[pn].phy = PHY_RTL8214FC; - continue; - } - - if (!of_property_read_bool(phy_node, "phy-is-integrated") - && !of_property_read_bool(phy_node, "sfp")) { - priv->ports[pn].phy = PHY_RTL8218B_EXT; - continue; - } - } - - /* Disable MAC polling the PHY so that we can start configuration */ - priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl); - - /* Enable PHY control via SoC */ - if (priv->family_id == RTL8380_FAMILY_ID) { - /* Enable SerDes NWAY and PHY control via SoC */ - sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL); - } else if (priv->family_id == RTL8390_FAMILY_ID) { - /* Disable PHY polling via SoC */ - sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL); - } - - /* Power on fibre ports and reset them if necessary */ - if (priv->ports[24].phy == PHY_RTL838X_SDS) { - pr_debug("Powering on fibre ports & reset\n"); - rtl8380_sds_power(24, 1); - rtl8380_sds_power(26, 1); - } - - pr_debug("%s done\n", __func__); - return 0; -} - -static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv) -{ - int t = sw_r32(priv->r->l2_ctrl_1); - - t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF; - - if (priv->family_id == RTL8380_FAMILY_ID) - t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */ - else - t = (t * 3) / 5; - - pr_debug("L2 AGING time: %d sec\n", t); - pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out)); - return t; -} - -/* Caller must hold priv->reg_mutex */ -int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info) -{ - struct rtl838x_switch_priv *priv = ds->priv; - int i; - u32 algomsk = 0; - u32 algoidx = 0; - - if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { - pr_err("%s: Only mode LACP 802.3ad (4) allowed.\n", __func__); - return -EINVAL; - } - - if (group >= priv->n_lags) { - pr_err("%s: LAG %d invalid.\n", __func__, group); - return -EINVAL; - } - - if (port >= priv->cpu_port) { - pr_err("%s: Port %d invalid.\n", __func__, port); - return -EINVAL; - } - - for (i = 0; i < priv->n_lags; i++) { - if (priv->lags_port_members[i] & BIT_ULL(port)) - break; - } - if (i != priv->n_lags) { - pr_err("%s: Port %d already member of LAG %d.\n", __func__, port, i); - return -ENOSPC; - } - switch(info->hash_type) { - case NETDEV_LAG_HASH_L2: - algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT; - algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT; - break; - case NETDEV_LAG_HASH_L23: - algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT; - algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT; - algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip - algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip - algoidx = 1; - break; - case NETDEV_LAG_HASH_L34: - algomsk |= TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT; //sport - algomsk |= TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT; //dport - algomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip - algomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip - algoidx = 2; - break; - default: - algomsk |= 0x7f; - } - priv->r->set_distribution_algorithm(group, algoidx, algomsk); - priv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group)); - priv->lags_port_members[group] |= BIT_ULL(port); - - pr_info("%s: Added port %d to LAG %d. Members now %016llx.\n", - __func__, port, group, priv->lags_port_members[group]); - return 0; -} - -/* Caller must hold priv->reg_mutex */ -int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - if (group >= priv->n_lags) { - pr_err("%s: LAG %d invalid.\n", __func__, group); - return -EINVAL; - } - - if (port >= priv->cpu_port) { - pr_err("%s: Port %d invalid.\n", __func__, port); - return -EINVAL; - } - - if (!(priv->lags_port_members[group] & BIT_ULL(port))) { - pr_err("%s: Port %d not member of LAG %d.\n", __func__, port, group); - return -ENOSPC; - } - - // 0x7f algo mask all - priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group)); - priv->lags_port_members[group] &= ~BIT_ULL(port); - - pr_info("%s: Removed port %d from LAG %d. Members now %016llx.\n", - __func__, port, group, priv->lags_port_members[group]); - return 0; -} - -/* - * Allocate a 64 bit octet counter located in the LOG HW table - */ -static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv) -{ - int idx; - - mutex_lock(&priv->reg_mutex); - - idx = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS); - if (idx >= priv->n_counters) { - mutex_unlock(&priv->reg_mutex); - return -1; - } - - set_bit(idx, priv->octet_cntr_use_bm); - mutex_unlock(&priv->reg_mutex); - - return idx; -} - -/* - * Allocate a 32-bit packet counter - * 2 32-bit packet counters share the location of a 64-bit octet counter - * Initially there are no free packet counters and 2 new ones need to be freed - * by allocating the corresponding octet counter - */ -int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv) -{ - int idx, j; - - mutex_lock(&priv->reg_mutex); - - /* Because initially no packet counters are free, the logic is reversed: - * a 0-bit means the counter is already allocated (for octets) - */ - idx = find_first_bit(priv->packet_cntr_use_bm, MAX_COUNTERS * 2); - if (idx >= priv->n_counters * 2) { - j = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS); - if (j >= priv->n_counters) { - mutex_unlock(&priv->reg_mutex); - return -1; - } - set_bit(j, priv->octet_cntr_use_bm); - idx = j * 2; - set_bit(j * 2 + 1, priv->packet_cntr_use_bm); - - } else { - clear_bit(idx, priv->packet_cntr_use_bm); - } - - mutex_unlock(&priv->reg_mutex); - - return idx; -} - -/* - * Add an L2 nexthop entry for the L3 routing system / PIE forwarding in the SoC - * Use VID and MAC in rtl838x_l2_entry to identify either a free slot in the L2 hash table - * or mark an existing entry as a nexthop by setting it's nexthop bit - * Called from the L3 layer - * The index in the L2 hash table is filled into nh->l2_id; - */ -int rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh) -{ - struct rtl838x_l2_entry e; - u64 seed = priv->r->l2_hash_seed(nh->mac, nh->rvid); - u32 key = priv->r->l2_hash_key(priv, seed); - int i, idx = -1; - u64 entry; - - pr_debug("%s searching for %08llx vid %d with key %d, seed: %016llx\n", - __func__, nh->mac, nh->rvid, key, seed); - - e.type = L2_UNICAST; - u64_to_ether_addr(nh->mac, &e.mac[0]); - e.port = nh->port; - - // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs - for (i = 0; i < priv->l2_bucket_size; i++) { - entry = priv->r->read_l2_entry_using_hash(key, i, &e); - - if (!e.valid || ((entry & 0x0fffffffffffffffULL) == seed)) { - idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 - : ((key << 2) | i) & 0xffff; - break; - } - } - - if (idx < 0) { - pr_err("%s: No more L2 forwarding entries available\n", __func__); - return -1; - } - - // Found an existing (e->valid is true) or empty entry, make it a nexthop entry - nh->l2_id = idx; - if (e.valid) { - nh->port = e.port; - nh->vid = e.vid; // Save VID - nh->rvid = e.rvid; - nh->dev_id = e.stack_dev; - // If the entry is already a valid next hop entry, don't change it - if (e.next_hop) - return 0; - } else { - e.valid = true; - e.is_static = true; - e.rvid = nh->rvid; - e.is_ip_mc = false; - e.is_ipv6_mc = false; - e.block_da = false; - e.block_sa = false; - e.suspended = false; - e.age = 0; // With port-ignore - e.port = priv->port_ignore; - u64_to_ether_addr(nh->mac, &e.mac[0]); - } - e.next_hop = true; - e.nh_route_id = nh->id; // NH route ID takes place of VID - e.nh_vlan_target = false; - - priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); - - return 0; -} - -/* - * Removes a Layer 2 next hop entry in the forwarding database - * If it was static, the entire entry is removed, otherwise the nexthop bit is cleared - * and we wait until the entry ages out - */ -int rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh) -{ - struct rtl838x_l2_entry e; - u32 key = nh->l2_id >> 2; - int i = nh->l2_id & 0x3; - u64 entry = entry = priv->r->read_l2_entry_using_hash(key, i, &e); - - pr_debug("%s: id %d, key %d, index %d\n", __func__, nh->l2_id, key, i); - if (!e.valid) { - dev_err(priv->dev, "unknown nexthop, id %x\n", nh->l2_id); - return -1; - } - - if (e.is_static) - e.valid = false; - e.next_hop = false; - e.vid = nh->vid; // Restore VID - e.rvid = nh->rvid; - - priv->r->write_l2_entry_using_hash(key, i, &e); - - return 0; -} - -static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv, - struct net_device *ndev, - struct netdev_notifier_changeupper_info *info) -{ - struct net_device *upper = info->upper_dev; - struct netdev_lag_upper_info *lag_upper_info = NULL; - int i, j, err; - - if (!netif_is_lag_master(upper)) - return 0; - - mutex_lock(&priv->reg_mutex); - - for (i = 0; i < priv->n_lags; i++) { - if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper)) - break; - } - for (j = 0; j < priv->cpu_port; j++) { - if (priv->ports[j].dp->slave == ndev) - break; - } - if (j >= priv->cpu_port) { - err = -EINVAL; - goto out; - } - - if (info->linking) { - lag_upper_info = info->upper_info; - if (!priv->lag_devs[i]) - priv->lag_devs[i] = upper; - err = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index, lag_upper_info); - if (err) { - err = -EINVAL; - goto out; - } - } else { - if (!priv->lag_devs[i]) - err = -EINVAL; - err = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index); - if (err) { - err = -EINVAL; - goto out; - } - if (!priv->lags_port_members[i]) - priv->lag_devs[i] = NULL; - } - -out: - mutex_unlock(&priv->reg_mutex); - return 0; -} - -/* - * Is the lower network device a DSA slave network device of our RTL930X-switch? - * Unfortunately we cannot just follow dev->dsa_prt as this is only set for the - * DSA master device. - */ -int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv) -{ - int i; - -// TODO: On 5.12: -// if(!dsa_slave_dev_check(dev)) { -// netdev_info(dev, "%s: not a DSA device.\n", __func__); -// return -EINVAL; -// } - - for (i = 0; i < priv->cpu_port; i++) { - if (!priv->ports[i].dp) - continue; - if (priv->ports[i].dp->slave == dev) - return i; - } - return -EINVAL; -} - -static int rtl83xx_netdevice_event(struct notifier_block *this, - unsigned long event, void *ptr) -{ - struct net_device *ndev = netdev_notifier_info_to_dev(ptr); - struct rtl838x_switch_priv *priv; - int err; - - pr_debug("In: %s, event: %lu\n", __func__, event); - - if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE)) - return NOTIFY_DONE; - - priv = container_of(this, struct rtl838x_switch_priv, nb); - switch (event) { - case NETDEV_CHANGEUPPER: - err = rtl83xx_handle_changeupper(priv, ndev, ptr); - break; - } - - if (err) - return err; - - return NOTIFY_DONE; -} - -const static struct rhashtable_params route_ht_params = { - .key_len = sizeof(u32), - .key_offset = offsetof(struct rtl83xx_route, gw_ip), - .head_offset = offsetof(struct rtl83xx_route, linkage), -}; - -/* - * Updates an L3 next hop entry in the ROUTING table - */ -static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv, __be32 ip_addr, u64 mac) -{ - struct rtl83xx_route *r; - struct rhlist_head *tmp, *list; - - rcu_read_lock(); - list = rhltable_lookup(&priv->routes, &ip_addr, route_ht_params); - if (!list) { - rcu_read_unlock(); - return -ENOENT; - } - - rhl_for_each_entry_rcu(r, tmp, list, linkage) { - pr_info("%s: Setting up fwding: ip %pI4, GW mac %016llx\n", - __func__, &ip_addr, mac); - - // Reads the ROUTING table entry associated with the route - priv->r->route_read(r->id, r); - pr_info("Route with id %d to %pI4 / %d\n", r->id, &r->dst_ip, r->prefix_len); - - r->nh.mac = r->nh.gw = mac; - r->nh.port = priv->port_ignore; - r->nh.id = r->id; - - // Do we need to explicitly add a DMAC entry with the route's nh index? - if (priv->r->set_l3_egress_mac) - priv->r->set_l3_egress_mac(r->id, mac); - - // Update ROUTING table: map gateway-mac and switch-mac id to route id - rtl83xx_l2_nexthop_add(priv, &r->nh); - - r->attr.valid = true; - r->attr.action = ROUTE_ACT_FORWARD; - r->attr.type = 0; - r->attr.hit = false; // Reset route-used indicator - - // Add PIE entry with dst_ip and prefix_len - r->pr.dip = r->dst_ip; - r->pr.dip_m = inet_make_mask(r->prefix_len); - - if (r->is_host_route) { - int slot = priv->r->find_l3_slot(r, false); - - pr_info("%s: Got slot for route: %d\n", __func__, slot); - priv->r->host_route_write(slot, r); - } else { - priv->r->route_write(r->id, r); - r->pr.fwd_sel = true; - r->pr.fwd_data = r->nh.l2_id; - r->pr.fwd_act = PIE_ACT_ROUTE_UC; - } - - if (priv->r->set_l3_nexthop) - priv->r->set_l3_nexthop(r->nh.id, r->nh.l2_id, r->nh.if_id); - - if (r->pr.id < 0) { - r->pr.packet_cntr = rtl83xx_packet_cntr_alloc(priv); - if (r->pr.packet_cntr >= 0) { - pr_info("Using packet counter %d\n", r->pr.packet_cntr); - r->pr.log_sel = true; - r->pr.log_data = r->pr.packet_cntr; - } - priv->r->pie_rule_add(priv, &r->pr); - } else { - int pkts = priv->r->packet_cntr_read(r->pr.packet_cntr); - pr_info("%s: total packets: %d\n", __func__, pkts); - - priv->r->pie_rule_write(priv, r->pr.id, &r->pr); - } - } - rcu_read_unlock(); - return 0; -} - -static int rtl83xx_port_ipv4_resolve(struct rtl838x_switch_priv *priv, - struct net_device *dev, __be32 ip_addr) -{ - struct neighbour *n = neigh_lookup(&arp_tbl, &ip_addr, dev); - int err = 0; - u64 mac; - - if (!n) { - n = neigh_create(&arp_tbl, &ip_addr, dev); - if (IS_ERR(n)) - return PTR_ERR(n); - } - - /* If the neigh is already resolved, then go ahead and - * install the entry, otherwise start the ARP process to - * resolve the neigh. - */ - if (n->nud_state & NUD_VALID) { - mac = ether_addr_to_u64(n->ha); - pr_info("%s: resolved mac: %016llx\n", __func__, mac); - rtl83xx_l3_nexthop_update(priv, ip_addr, mac); - } else { - pr_info("%s: need to wait\n", __func__); - neigh_event_send(n, NULL); - } - - neigh_release(n); - return err; -} - -struct rtl83xx_walk_data { - struct rtl838x_switch_priv *priv; - int port; -}; - -static int rtl83xx_port_lower_walk(struct net_device *lower, struct netdev_nested_priv *_priv) -{ - struct rtl83xx_walk_data *data = (struct rtl83xx_walk_data *)_priv->data; - struct rtl838x_switch_priv *priv = data->priv; - int ret = 0; - int index; - - index = rtl83xx_port_is_under(lower, priv); - data->port = index; - if (index >= 0) { - pr_debug("Found DSA-port, index %d\n", index); - ret = 1; - } - - return ret; -} - -int rtl83xx_port_dev_lower_find(struct net_device *dev, struct rtl838x_switch_priv *priv) -{ - struct rtl83xx_walk_data data; - struct netdev_nested_priv _priv; - - data.priv = priv; - data.port = 0; - _priv.data = (void *)&data; - - netdev_walk_all_lower_dev(dev, rtl83xx_port_lower_walk, &_priv); - - return data.port; -} - -static struct rtl83xx_route *rtl83xx_route_alloc(struct rtl838x_switch_priv *priv, u32 ip) -{ - struct rtl83xx_route *r; - int idx = 0, err; - - mutex_lock(&priv->reg_mutex); - - idx = find_first_zero_bit(priv->route_use_bm, MAX_ROUTES); - pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip); - - r = kzalloc(sizeof(*r), GFP_KERNEL); - if (!r) { - mutex_unlock(&priv->reg_mutex); - return r; - } - - r->id = idx; - r->gw_ip = ip; - r->pr.id = -1; // We still need to allocate a rule in HW - r->is_host_route = false; - - err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params); - if (err) { - pr_err("Could not insert new rule\n"); - mutex_unlock(&priv->reg_mutex); - goto out_free; - } - - set_bit(idx, priv->route_use_bm); - - mutex_unlock(&priv->reg_mutex); - - return r; - -out_free: - kfree(r); - return NULL; -} - - -static struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv *priv, u32 ip) -{ - struct rtl83xx_route *r; - int idx = 0, err; - - mutex_lock(&priv->reg_mutex); - - idx = find_first_zero_bit(priv->host_route_use_bm, MAX_HOST_ROUTES); - pr_debug("%s id: %d, ip %pI4\n", __func__, idx, &ip); - - r = kzalloc(sizeof(*r), GFP_KERNEL); - if (!r) { - mutex_unlock(&priv->reg_mutex); - return r; - } - - /* We require a unique route ID irrespective of whether it is a prefix or host - * route (on RTL93xx) as we use this ID to associate a DMAC and next-hop entry */ - r->id = idx + MAX_ROUTES; - - r->gw_ip = ip; - r->pr.id = -1; // We still need to allocate a rule in HW - r->is_host_route = true; - - err = rhltable_insert(&priv->routes, &r->linkage, route_ht_params); - if (err) { - pr_err("Could not insert new rule\n"); - mutex_unlock(&priv->reg_mutex); - goto out_free; - } - - set_bit(idx, priv->host_route_use_bm); - - mutex_unlock(&priv->reg_mutex); - - return r; - -out_free: - kfree(r); - return NULL; -} - - - -static void rtl83xx_route_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_route *r) -{ - int id; - - if (rhltable_remove(&priv->routes, &r->linkage, route_ht_params)) - dev_warn(priv->dev, "Could not remove route\n"); - - if (r->is_host_route) { - id = priv->r->find_l3_slot(r, false); - pr_debug("%s: Got id for host route: %d\n", __func__, id); - r->attr.valid = false; - priv->r->host_route_write(id, r); - clear_bit(r->id - MAX_ROUTES, priv->host_route_use_bm); - } else { - // If there is a HW representation of the route, delete it - if (priv->r->route_lookup_hw) { - id = priv->r->route_lookup_hw(r); - pr_info("%s: Got id for prefix route: %d\n", __func__, id); - r->attr.valid = false; - priv->r->route_write(id, r); - } - clear_bit(r->id, priv->route_use_bm); - } - - kfree(r); -} - -static int rtl83xx_fib4_del(struct rtl838x_switch_priv *priv, - struct fib_entry_notifier_info *info) -{ - struct fib_nh *nh = fib_info_nh(info->fi, 0); - struct rtl83xx_route *r; - struct rhlist_head *tmp, *list; - - pr_debug("In %s, ip %pI4, len %d\n", __func__, &info->dst, info->dst_len); - rcu_read_lock(); - list = rhltable_lookup(&priv->routes, &nh->fib_nh_gw4, route_ht_params); - if (!list) { - rcu_read_unlock(); - pr_err("%s: no such gateway: %pI4\n", __func__, &nh->fib_nh_gw4); - return -ENOENT; - } - rhl_for_each_entry_rcu(r, tmp, list, linkage) { - if (r->dst_ip == info->dst && r->prefix_len == info->dst_len) { - pr_info("%s: found a route with id %d, nh-id %d\n", - __func__, r->id, r->nh.id); - break; - } - } - rcu_read_unlock(); - - rtl83xx_l2_nexthop_rm(priv, &r->nh); - - pr_debug("%s: Releasing packet counter %d\n", __func__, r->pr.packet_cntr); - set_bit(r->pr.packet_cntr, priv->packet_cntr_use_bm); - priv->r->pie_rule_rm(priv, &r->pr); - - rtl83xx_route_rm(priv, r); - - nh->fib_nh_flags &= ~RTNH_F_OFFLOAD; - - return 0; -} - -/* - * On the RTL93xx, an L3 termination endpoint MAC address on which the router waits - * for packets to be routed needs to be allocated. - */ -static int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac) -{ - int i, free_mac = -1; - struct rtl93xx_rt_mac m; - - mutex_lock(&priv->reg_mutex); - for (i = 0; i < MAX_ROUTER_MACS; i++) { - priv->r->get_l3_router_mac(i, &m); - if (free_mac < 0 && !m.valid) { - free_mac = i; - continue; - } - if (m.valid && m.mac == mac) { - free_mac = i; - break; - } - } - - if (free_mac < 0) { - pr_err("No free router MACs, cannot offload\n"); - mutex_unlock(&priv->reg_mutex); - return -1; - } - - m.valid = true; - m.mac = mac; - m.p_type = 0; // An individual port, not a trunk port - m.p_id = 0x3f; // Listen on any port - m.p_id_mask = 0; - m.vid = 0; // Listen on any VLAN... - m.vid_mask = 0; // ... so mask needs to be 0 - m.mac_mask = 0xffffffffffffULL; // We want an exact match of the interface MAC - m.action = L3_FORWARD; // Route the packet - priv->r->set_l3_router_mac(free_mac, &m); - - mutex_unlock(&priv->reg_mutex); - - return 0; -} - -static int rtl83xx_alloc_egress_intf(struct rtl838x_switch_priv *priv, u64 mac, int vlan) -{ - int i, free_mac = -1; - struct rtl838x_l3_intf intf; - u64 m; - - mutex_lock(&priv->reg_mutex); - for (i = 0; i < MAX_SMACS; i++) { - m = priv->r->get_l3_egress_mac(L3_EGRESS_DMACS + i); - if (free_mac < 0 && !m) { - free_mac = i; - continue; - } - if (m == mac) { - mutex_unlock(&priv->reg_mutex); - return i; - } - } - - if (free_mac < 0) { - pr_err("No free egress interface, cannot offload\n"); - return -1; - } - - // Set up default egress interface 1 - intf.vid = vlan; - intf.smac_idx = free_mac; - intf.ip4_mtu_id = 1; - intf.ip6_mtu_id = 1; - intf.ttl_scope = 1; // TTL - intf.hl_scope = 1; // Hop Limit - intf.ip4_icmp_redirect = intf.ip6_icmp_redirect = 2; // FORWARD - intf.ip4_pbr_icmp_redirect = intf.ip6_pbr_icmp_redirect = 2; // FORWARD; - priv->r->set_l3_egress_intf(free_mac, &intf); - - priv->r->set_l3_egress_mac(L3_EGRESS_DMACS + free_mac, mac); - - mutex_unlock(&priv->reg_mutex); - - return free_mac; -} - -static int rtl83xx_fib4_add(struct rtl838x_switch_priv *priv, - struct fib_entry_notifier_info *info) -{ - struct fib_nh *nh = fib_info_nh(info->fi, 0); - struct net_device *dev = fib_info_nh(info->fi, 0)->fib_nh_dev; - int port; - struct rtl83xx_route *r; - bool to_localhost; - int vlan = is_vlan_dev(dev) ? vlan_dev_vlan_id(dev) : 0; - - pr_debug("In %s, ip %pI4, len %d\n", __func__, &info->dst, info->dst_len); - if (!info->dst) { - pr_info("Not offloading default route for now\n"); - return 0; - } - - pr_debug("GW: %pI4, interface name %s, mac %016llx, vlan %d\n", &nh->fib_nh_gw4, dev->name, - ether_addr_to_u64(dev->dev_addr), vlan - ); - - port = rtl83xx_port_dev_lower_find(dev, priv); - if (port < 0) - return -1; - - // For now we only work with routes that have a gateway and are not ourself -// if ((!nh->fib_nh_gw4) && (info->dst_len != 32)) -// return 0; - - if ((info->dst & 0xff) == 0xff) - return 0; - - // Do not offload routes to 192.168.100.x - if ((info->dst & 0xffffff00) == 0xc0a86400) - return 0; - - // Do not offload routes to 127.x.x.x - if ((info->dst & 0xff000000) == 0x7f000000) - return 0; - - // Allocate route or host-route (entry if hardware supports this) - if (info->dst_len == 32 && priv->r->host_route_write) - r = rtl83xx_host_route_alloc(priv, nh->fib_nh_gw4); - else - r = rtl83xx_route_alloc(priv, nh->fib_nh_gw4); - - if (!r) { - pr_err("%s: No more free route entries\n", __func__); - return -1; - } - - r->dst_ip = info->dst; - r->prefix_len = info->dst_len; - r->nh.rvid = vlan; - to_localhost = !nh->fib_nh_gw4; - - if (priv->r->set_l3_router_mac) { - u64 mac = ether_addr_to_u64(dev->dev_addr); - - pr_debug("Local route and router mac %016llx\n", mac); - - if (rtl83xx_alloc_router_mac(priv, mac)) - goto out_free_rt; - - // vid = 0: Do not care about VID - r->nh.if_id = rtl83xx_alloc_egress_intf(priv, mac, vlan); - if (r->nh.if_id < 0) - goto out_free_rmac; - - if (to_localhost) { - int slot; - - r->nh.mac = mac; - r->nh.port = priv->port_ignore; - r->attr.valid = true; - r->attr.action = ROUTE_ACT_TRAP2CPU; - r->attr.type = 0; - - slot = priv->r->find_l3_slot(r, false); - pr_debug("%s: Got slot for route: %d\n", __func__, slot); - priv->r->host_route_write(slot, r); - } - } - - // We need to resolve the mac address of the GW - if (!to_localhost) - rtl83xx_port_ipv4_resolve(priv, dev, nh->fib_nh_gw4); - - nh->fib_nh_flags |= RTNH_F_OFFLOAD; - - return 0; - -out_free_rmac: -out_free_rt: - return 0; -} - -static int rtl83xx_fib6_add(struct rtl838x_switch_priv *priv, - struct fib6_entry_notifier_info *info) -{ - pr_debug("In %s\n", __func__); -// nh->fib_nh_flags |= RTNH_F_OFFLOAD; - return 0; -} - -struct net_event_work { - struct work_struct work; - struct rtl838x_switch_priv *priv; - u64 mac; - u32 gw_addr; -}; - -static void rtl83xx_net_event_work_do(struct work_struct *work) -{ - struct net_event_work *net_work = - container_of(work, struct net_event_work, work); - struct rtl838x_switch_priv *priv = net_work->priv; - - rtl83xx_l3_nexthop_update(priv, net_work->gw_addr, net_work->mac); - - kfree(net_work); -} - -static int rtl83xx_netevent_event(struct notifier_block *this, - unsigned long event, void *ptr) -{ - struct rtl838x_switch_priv *priv; - struct net_device *dev; - struct neighbour *n = ptr; - int err, port; - struct net_event_work *net_work; - - priv = container_of(this, struct rtl838x_switch_priv, ne_nb); - - switch (event) { - case NETEVENT_NEIGH_UPDATE: - if (n->tbl != &arp_tbl) - return NOTIFY_DONE; - dev = n->dev; - port = rtl83xx_port_dev_lower_find(dev, priv); - if (port < 0 || !(n->nud_state & NUD_VALID)) { - pr_debug("%s: Neigbour invalid, not updating\n", __func__); - return NOTIFY_DONE; - } - - net_work = kzalloc(sizeof(*net_work), GFP_ATOMIC); - if (!net_work) - return NOTIFY_BAD; - - INIT_WORK(&net_work->work, rtl83xx_net_event_work_do); - net_work->priv = priv; - - net_work->mac = ether_addr_to_u64(n->ha); - net_work->gw_addr = *(__be32 *) n->primary_key; - - pr_debug("%s: updating neighbour on port %d, mac %016llx\n", - __func__, port, net_work->mac); - schedule_work(&net_work->work); - if (err) - netdev_warn(dev, "failed to handle neigh update (err %d)\n", err); - break; - } - - return NOTIFY_DONE; -} - -struct rtl83xx_fib_event_work { - struct work_struct work; - union { - struct fib_entry_notifier_info fen_info; - struct fib6_entry_notifier_info fen6_info; - struct fib_rule_notifier_info fr_info; - }; - struct rtl838x_switch_priv *priv; - bool is_fib6; - unsigned long event; -}; - -static void rtl83xx_fib_event_work_do(struct work_struct *work) -{ - struct rtl83xx_fib_event_work *fib_work = - container_of(work, struct rtl83xx_fib_event_work, work); - struct rtl838x_switch_priv *priv = fib_work->priv; - struct fib_rule *rule; - int err; - - /* Protect internal structures from changes */ - rtnl_lock(); - pr_debug("%s: doing work, event %ld\n", __func__, fib_work->event); - switch (fib_work->event) { - case FIB_EVENT_ENTRY_ADD: - case FIB_EVENT_ENTRY_REPLACE: - case FIB_EVENT_ENTRY_APPEND: - if (fib_work->is_fib6) { - err = rtl83xx_fib6_add(priv, &fib_work->fen6_info); - } else { - err = rtl83xx_fib4_add(priv, &fib_work->fen_info); - fib_info_put(fib_work->fen_info.fi); - } - if (err) - pr_err("%s: FIB4 failed\n", __func__); - break; - case FIB_EVENT_ENTRY_DEL: - rtl83xx_fib4_del(priv, &fib_work->fen_info); - fib_info_put(fib_work->fen_info.fi); - break; - case FIB_EVENT_RULE_ADD: - case FIB_EVENT_RULE_DEL: - rule = fib_work->fr_info.rule; - if (!fib4_rule_default(rule)) - pr_err("%s: FIB4 default rule failed\n", __func__); - fib_rule_put(rule); - break; - } - rtnl_unlock(); - kfree(fib_work); -} - -/* Called with rcu_read_lock() */ -static int rtl83xx_fib_event(struct notifier_block *this, unsigned long event, void *ptr) -{ - struct fib_notifier_info *info = ptr; - struct rtl838x_switch_priv *priv; - struct rtl83xx_fib_event_work *fib_work; - - if ((info->family != AF_INET && info->family != AF_INET6 && - info->family != RTNL_FAMILY_IPMR && - info->family != RTNL_FAMILY_IP6MR)) - return NOTIFY_DONE; - - priv = container_of(this, struct rtl838x_switch_priv, fib_nb); - - fib_work = kzalloc(sizeof(*fib_work), GFP_ATOMIC); - if (!fib_work) - return NOTIFY_BAD; - - INIT_WORK(&fib_work->work, rtl83xx_fib_event_work_do); - fib_work->priv = priv; - fib_work->event = event; - fib_work->is_fib6 = false; - - switch (event) { - case FIB_EVENT_ENTRY_ADD: - case FIB_EVENT_ENTRY_REPLACE: - case FIB_EVENT_ENTRY_APPEND: - case FIB_EVENT_ENTRY_DEL: - pr_debug("%s: FIB_ENTRY ADD/DEL, event %ld\n", __func__, event); - if (info->family == AF_INET) { - struct fib_entry_notifier_info *fen_info = ptr; - - if (fen_info->fi->fib_nh_is_v6) { - NL_SET_ERR_MSG_MOD(info->extack, - "IPv6 gateway with IPv4 route is not supported"); - kfree(fib_work); - return notifier_from_errno(-EINVAL); - } - - memcpy(&fib_work->fen_info, ptr, sizeof(fib_work->fen_info)); - /* Take referece on fib_info to prevent it from being - * freed while work is queued. Release it afterwards. - */ - fib_info_hold(fib_work->fen_info.fi); - - } else if (info->family == AF_INET6) { - struct fib6_entry_notifier_info *fen6_info = ptr; - pr_warn("%s: FIB_RULE ADD/DEL for IPv6 not supported\n", __func__); - kfree(fib_work); - return NOTIFY_DONE; - } - break; - - case FIB_EVENT_RULE_ADD: - case FIB_EVENT_RULE_DEL: - pr_debug("%s: FIB_RULE ADD/DEL, event: %ld\n", __func__, event); - memcpy(&fib_work->fr_info, ptr, sizeof(fib_work->fr_info)); - fib_rule_get(fib_work->fr_info.rule); - break; - } - - schedule_work(&fib_work->work); - - return NOTIFY_DONE; -} - -static int __init rtl83xx_sw_probe(struct platform_device *pdev) -{ - int err = 0, i; - struct rtl838x_switch_priv *priv; - struct device *dev = &pdev->dev; - u64 bpdu_mask; - - pr_debug("Probing RTL838X switch device\n"); - if (!pdev->dev.of_node) { - dev_err(dev, "No DT found\n"); - return -EINVAL; - } - - // Initialize access to RTL switch tables - rtl_table_init(); - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); - - if (!priv->ds) - return -ENOMEM; - priv->ds->dev = dev; - priv->ds->priv = priv; - priv->ds->ops = &rtl83xx_switch_ops; - priv->dev = dev; - - mutex_init(&priv->reg_mutex); - - priv->family_id = soc_info.family; - priv->id = soc_info.id; - switch(soc_info.family) { - case RTL8380_FAMILY_ID: - priv->ds->ops = &rtl83xx_switch_ops; - priv->cpu_port = RTL838X_CPU_PORT; - priv->port_mask = 0x1f; - priv->port_width = 1; - priv->irq_mask = 0x0FFFFFFF; - priv->r = &rtl838x_reg; - priv->ds->num_ports = 29; - priv->fib_entries = 8192; - rtl8380_get_version(priv); - priv->n_lags = 8; - priv->l2_bucket_size = 4; - priv->n_pie_blocks = 12; - priv->port_ignore = 0x1f; - priv->n_counters = 128; - break; - case RTL8390_FAMILY_ID: - priv->ds->ops = &rtl83xx_switch_ops; - priv->cpu_port = RTL839X_CPU_PORT; - priv->port_mask = 0x3f; - priv->port_width = 2; - priv->irq_mask = 0xFFFFFFFFFFFFFULL; - priv->r = &rtl839x_reg; - priv->ds->num_ports = 53; - priv->fib_entries = 16384; - rtl8390_get_version(priv); - priv->n_lags = 16; - priv->l2_bucket_size = 4; - priv->n_pie_blocks = 18; - priv->port_ignore = 0x3f; - priv->n_counters = 1024; - break; - case RTL9300_FAMILY_ID: - priv->ds->ops = &rtl930x_switch_ops; - priv->cpu_port = RTL930X_CPU_PORT; - priv->port_mask = 0x1f; - priv->port_width = 1; - priv->irq_mask = 0x0FFFFFFF; - priv->r = &rtl930x_reg; - priv->ds->num_ports = 29; - priv->fib_entries = 16384; - priv->version = RTL8390_VERSION_A; - priv->n_lags = 16; - sw_w32(1, RTL930X_ST_CTRL); - priv->l2_bucket_size = 8; - priv->n_pie_blocks = 16; - priv->port_ignore = 0x3f; - priv->n_counters = 2048; - break; - case RTL9310_FAMILY_ID: - priv->ds->ops = &rtl930x_switch_ops; - priv->cpu_port = RTL931X_CPU_PORT; - priv->port_mask = 0x3f; - priv->port_width = 2; - priv->irq_mask = 0xFFFFFFFFFFFFFULL; - priv->r = &rtl931x_reg; - priv->ds->num_ports = 57; - priv->fib_entries = 16384; - priv->version = RTL8390_VERSION_A; - priv->n_lags = 16; - priv->l2_bucket_size = 8; - break; - } - pr_debug("Chip version %c\n", priv->version); - - err = rtl83xx_mdio_probe(priv); - if (err) { - /* Probing fails the 1st time because of missing ethernet driver - * initialization. Use this to disable traffic in case the bootloader left if on - */ - return err; - } - err = dsa_register_switch(priv->ds); - if (err) { - dev_err(dev, "Error registering switch: %d\n", err); - return err; - } - - /* - * dsa_to_port returns dsa_port from the port list in - * dsa_switch_tree, the tree is built when the switch - * is registered by dsa_register_switch - */ - for (i = 0; i <= priv->cpu_port; i++) - priv->ports[i].dp = dsa_to_port(priv->ds, i); - - /* Enable link and media change interrupts. Are the SERDES masks needed? */ - sw_w32_mask(0, 3, priv->r->isr_glb_src); - - priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg); - priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg); - - priv->link_state_irq = platform_get_irq(pdev, 0); - pr_info("LINK state irq: %d\n", priv->link_state_irq); - switch (priv->family_id) { - case RTL8380_FAMILY_ID: - err = request_irq(priv->link_state_irq, rtl838x_switch_irq, - IRQF_SHARED, "rtl838x-link-state", priv->ds); - break; - case RTL8390_FAMILY_ID: - err = request_irq(priv->link_state_irq, rtl839x_switch_irq, - IRQF_SHARED, "rtl839x-link-state", priv->ds); - break; - case RTL9300_FAMILY_ID: - err = request_irq(priv->link_state_irq, rtl930x_switch_irq, - IRQF_SHARED, "rtl930x-link-state", priv->ds); - break; - case RTL9310_FAMILY_ID: - err = request_irq(priv->link_state_irq, rtl931x_switch_irq, - IRQF_SHARED, "rtl931x-link-state", priv->ds); - break; - } - if (err) { - dev_err(dev, "Error setting up switch interrupt.\n"); - /* Need to free allocated switch here */ - } - - /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */ - if (soc_info.family != RTL9310_FAMILY_ID) - sw_w32(0x1, priv->r->imr_glb); - - rtl83xx_get_l2aging(priv); - - rtl83xx_setup_qos(priv); - - priv->r->l3_setup(priv); - - /* Clear all destination ports for mirror groups */ - for (i = 0; i < 4; i++) - priv->mirror_group_ports[i] = -1; - - /* - * Register netdevice event callback to catch changes in link aggregation groups - */ - priv->nb.notifier_call = rtl83xx_netdevice_event; - if (register_netdevice_notifier(&priv->nb)) { - priv->nb.notifier_call = NULL; - dev_err(dev, "Failed to register LAG netdev notifier\n"); - goto err_register_nb; - } - - // Initialize hash table for L3 routing - rhltable_init(&priv->routes, &route_ht_params); - - /* - * Register netevent notifier callback to catch notifications about neighboring - * changes to update nexthop entries for L3 routing. - */ - priv->ne_nb.notifier_call = rtl83xx_netevent_event; - if (register_netevent_notifier(&priv->ne_nb)) { - priv->ne_nb.notifier_call = NULL; - dev_err(dev, "Failed to register netevent notifier\n"); - goto err_register_ne_nb; - } - - priv->fib_nb.notifier_call = rtl83xx_fib_event; - - /* - * Register Forwarding Information Base notifier to offload routes where - * where possible - * Only FIBs pointing to our own netdevs are programmed into - * the device, so no need to pass a callback. - */ - err = register_fib_notifier(&init_net, &priv->fib_nb, NULL, NULL); - if (err) - goto err_register_fib_nb; - - // TODO: put this into l2_setup() - // Flood BPDUs to all ports including cpu-port - if (soc_info.family != RTL9300_FAMILY_ID) { - bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF; - priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask); - - // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs - sw_w32(7, priv->r->spcl_trap_eapol_ctrl); - - rtl838x_dbgfs_init(priv); - } else { - rtl930x_dbgfs_init(priv); - } - - return 0; - -err_register_fib_nb: - unregister_netevent_notifier(&priv->ne_nb); -err_register_ne_nb: - unregister_netdevice_notifier(&priv->nb); -err_register_nb: - return err; -} - -static int rtl83xx_sw_remove(struct platform_device *pdev) -{ - // TODO: - pr_debug("Removing platform driver for rtl83xx-sw\n"); - return 0; -} - -static const struct of_device_id rtl83xx_switch_of_ids[] = { - { .compatible = "realtek,rtl83xx-switch"}, - { /* sentinel */ } -}; - - -MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids); - -static struct platform_driver rtl83xx_switch_driver = { - .probe = rtl83xx_sw_probe, - .remove = rtl83xx_sw_remove, - .driver = { - .name = "rtl83xx-switch", - .pm = NULL, - .of_match_table = rtl83xx_switch_of_ids, - }, -}; - -module_platform_driver(rtl83xx_switch_driver); - -MODULE_AUTHOR("B. Koblitz"); -MODULE_DESCRIPTION("RTL83XX SoC Switch Driver"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c deleted file mode 100644 index 3c935f629a..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c +++ /dev/null @@ -1,730 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include - -#include -#include "rtl83xx.h" - -#define RTL838X_DRIVER_NAME "rtl838x" - -#define RTL8380_LED_GLB_CTRL (0xA000) -#define RTL8380_LED_MODE_SEL (0x1004) -#define RTL8380_LED_MODE_CTRL (0xA004) -#define RTL8380_LED_P_EN_CTRL (0xA008) -#define RTL8380_LED_SW_CTRL (0xA00C) -#define RTL8380_LED0_SW_P_EN_CTRL (0xA010) -#define RTL8380_LED1_SW_P_EN_CTRL (0xA014) -#define RTL8380_LED2_SW_P_EN_CTRL (0xA018) -#define RTL8380_LED_SW_P_CTRL(p) (0xA01C + (((p) << 2))) - -#define RTL8390_LED_GLB_CTRL (0x00E4) -#define RTL8390_LED_SET_2_3_CTRL (0x00E8) -#define RTL8390_LED_SET_0_1_CTRL (0x00EC) -#define RTL8390_LED_COPR_SET_SEL_CTRL(p) (0x00F0 + (((p >> 4) << 2))) -#define RTL8390_LED_FIB_SET_SEL_CTRL(p) (0x0100 + (((p >> 4) << 2))) -#define RTL8390_LED_COPR_PMASK_CTRL(p) (0x0110 + (((p >> 5) << 2))) -#define RTL8390_LED_FIB_PMASK_CTRL(p) (0x00118 + (((p >> 5) << 2))) -#define RTL8390_LED_COMBO_CTRL(p) (0x0120 + (((p >> 5) << 2))) -#define RTL8390_LED_SW_CTRL (0x0128) -#define RTL8390_LED_SW_P_EN_CTRL(p) (0x012C + (((p / 10) << 2))) -#define RTL8390_LED_SW_P_CTRL(p) (0x0144 + (((p) << 2))) - -#define RTL838X_MIR_QID_CTRL(grp) (0xAD44 + (((grp) << 2))) -#define RTL838X_MIR_RSPAN_VLAN_CTRL(grp) (0xA340 + (((grp) << 2))) -#define RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(grp) (0xAA70 + (((grp) << 2))) -#define RTL838X_MIR_RSPAN_TX_CTRL (0xA350) -#define RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL (0xAA80) -#define RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL (0xAA84) -#define RTL839X_MIR_RSPAN_VLAN_CTRL(grp) (0xA340 + (((grp) << 2))) -#define RTL839X_MIR_RSPAN_TX_CTRL (0x69b0) -#define RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL (0x2550) -#define RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL (0x2554) -#define RTL839X_MIR_SAMPLE_RATE_CTRL (0x2558) - -#define RTL838X_STAT_PRVTE_DROP_COUNTERS (0x6A00) -#define RTL839X_STAT_PRVTE_DROP_COUNTERS (0x3E00) -#define RTL930X_STAT_PRVTE_DROP_COUNTERS (0xB5B8) -#define RTL931X_STAT_PRVTE_DROP_COUNTERS (0xd800) - -int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port); -void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); -void rtl83xx_fast_age(struct dsa_switch *ds, int port); -u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); -u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port); -int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); -int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate); - - -const char *rtl838x_drop_cntr[] = { - "ALE_TX_GOOD_PKTS", "MAC_RX_DROP", "ACL_FWD_DROP", "HW_ATTACK_PREVENTION_DROP", - "RMA_DROP", "VLAN_IGR_FLTR_DROP", "INNER_OUTER_CFI_EQUAL_1_DROP", "PORT_MOVE_DROP", - "NEW_SA_DROP", "MAC_LIMIT_SYS_DROP", "MAC_LIMIT_VLAN_DROP", "MAC_LIMIT_PORT_DROP", - "SWITCH_MAC_DROP", "ROUTING_EXCEPTION_DROP", "DA_LKMISS_DROP", "RSPAN_DROP", - "ACL_LKMISS_DROP", "ACL_DROP", "INBW_DROP", "IGR_METER_DROP", - "ACCEPT_FRAME_TYPE_DROP", "STP_IGR_DROP", "INVALID_SA_DROP", "SA_BLOCKING_DROP", - "DA_BLOCKING_DROP", "L2_INVALID_DPM_DROP", "MCST_INVALID_DPM_DROP", "RX_FLOW_CONTROL_DROP", - "STORM_SPPRS_DROP", "LALS_DROP", "VLAN_EGR_FILTER_DROP", "STP_EGR_DROP", - "SRC_PORT_FILTER_DROP", "PORT_ISOLATION_DROP", "ACL_FLTR_DROP", "MIRROR_FLTR_DROP", - "TX_MAX_DROP", "LINK_DOWN_DROP", "FLOW_CONTROL_DROP", "BRIDGE .1d discards" -}; - -const char *rtl839x_drop_cntr[] = { - "ALE_TX_GOOD_PKTS", "ERROR_PKTS", "EGR_ACL_DROP", "EGR_METER_DROP", - "OAM", "CFM" "VLAN_IGR_FLTR", "VLAN_ERR", - "INNER_OUTER_CFI_EQUAL_1", "VLAN_TAG_FORMAT", "SRC_PORT_SPENDING_TREE", "INBW", - "RMA", "HW_ATTACK_PREVENTION", "PROTO_STORM", "MCAST_SA", - "IGR_ACL_DROP", "IGR_METER_DROP", "DFLT_ACTION_FOR_MISS_ACL_AND_C2SC", "NEW_SA", - "PORT_MOVE", "SA_BLOCKING", "ROUTING_EXCEPTION", "SRC_PORT_SPENDING_TREE_NON_FWDING", - "MAC_LIMIT", "UNKNOW_STORM", "MISS_DROP", "CPU_MAC_DROP", - "DA_BLOCKING", "SRC_PORT_FILTER_BEFORE_EGR_ACL", "VLAN_EGR_FILTER", "SPANNING_TRE", - "PORT_ISOLATION", "OAM_EGRESS_DROP", "MIRROR_ISOLATION", "MAX_LEN_BEFORE_EGR_ACL", - "SRC_PORT_FILTER_BEFORE_MIRROR", "MAX_LEN_BEFORE_MIRROR", "SPECIAL_CONGEST_BEFORE_MIRROR", - "LINK_STATUS_BEFORE_MIRROR", - "WRED_BEFORE_MIRROR", "MAX_LEN_AFTER_MIRROR", "SPECIAL_CONGEST_AFTER_MIRROR", - "LINK_STATUS_AFTER_MIRROR", - "WRED_AFTER_MIRROR" -}; - -const char *rtl930x_drop_cntr[] = { - "OAM_PARSER", "UC_RPF", "DEI_CFI", "MAC_IP_SUBNET_BASED_VLAN", "VLAN_IGR_FILTER", - "L2_UC_MC", "IPV_IP6_MC_BRIDGE", "PTP", "USER_DEF_0_3", "RESERVED", - "RESERVED1", "RESERVED2", "BPDU_RMA", "LACP", "LLDP", - "EAPOL", "XX_RMA", "L3_IPUC_NON_IP", "IP4_IP6_HEADER_ERROR", "L3_BAD_IP", - "L3_DIP_DMAC_MISMATCH", "IP4_IP_OPTION", "IP_UC_MC_ROUTING_LOOK_UP_MISS", "L3_DST_NULL_INTF", - "L3_PBR_NULL_INTF", - "HOST_NULL_INTF", "ROUTE_NULL_INTF", "BRIDGING_ACTION", "ROUTING_ACTION", "IPMC_RPF", - "L2_NEXTHOP_AGE_OUT", "L3_UC_TTL_FAIL", "L3_MC_TTL_FAIL", "L3_UC_MTU_FAIL", "L3_MC_MTU_FAIL", - "L3_UC_ICMP_REDIR", "IP6_MLD_OTHER_ACT", "ND", "IP_MC_RESERVED", "IP6_HBH", - "INVALID_SA", "L2_HASH_FULL", "NEW_SA", "PORT_MOVE_FORBID", "STATIC_PORT_MOVING", - "DYNMIC_PORT_MOVING", "L3_CRC", "MAC_LIMIT", "ATTACK_PREVENT", "ACL_FWD_ACTION", - "OAMPDU", "OAM_MUX", "TRUNK_FILTER", "ACL_DROP", "IGR_BW", - "ACL_METER", "VLAN_ACCEPT_FRAME_TYPE", "MSTP_SRC_DROP_DISABLED_BLOCKING", "SA_BLOCK", "DA_BLOCK", - "STORM_CONTROL", "VLAN_EGR_FILTER", "MSTP_DESTINATION_DROP", "SRC_PORT_FILTER", "PORT_ISOLATION", - "TX_MAX_FRAME_SIZE", "EGR_LINK_STATUS", "MAC_TX_DISABLE", "MAC_PAUSE_FRAME", "MAC_RX_DROP", - "MIRROR_ISOLATE", "RX_FC", "EGR_QUEUE", "HSM_RUNOUT", "ROUTING_DISABLE", "INVALID_L2_NEXTHOP_ENTRY", - "L3_MC_SRC_FLT", "CPUTAG_FLT", "FWD_PMSK_NULL", "IPUC_ROUTING_LOOKUP_MISS", "MY_DEV_DROP", - "STACK_NONUC_BLOCKING_PMSK", "STACK_PORT_NOT_FOUND", "ACL_LOOPBACK_DROP", "IP6_ROUTING_EXT_HEADER" -}; - -const char *rtl931x_drop_cntr[] = { - "ALE_RX_GOOD_PKTS", "RX_MAX_FRAME_SIZE", "MAC_RX_DROP", "OPENFLOW_IP_MPLS_TTL", "OPENFLOW_TBL_MISS", - "IGR_BW", "SPECIAL_CONGEST", "EGR_QUEUE", "RESERVED", "EGR_LINK_STATUS", "STACK_UCAST_NONUCAST_TTL", // 10 - "STACK_NONUC_BLOCKING_PMSK", "L2_CRC", "SRC_PORT_FILTER", "PARSER_PACKET_TOO_LONG", "PARSER_MALFORM_PACKET", - "MPLS_OVER_2_LBL", "EACL_METER", "IACL_METER", "PROTO_STORM", "INVALID_CAPWAP_HEADER", // 20 - "MAC_IP_SUBNET_BASED_VLAN", "OAM_PARSER", "UC_MC_RPF", "IP_MAC_BINDING_MATCH_MISMATCH", "SA_BLOCK", - "TUNNEL_IP_ADDRESS_CHECK", "EACL_DROP", "IACL_DROP", "ATTACK_PREVENT", "SYSTEM_PORT_LIMIT_LEARN", // 30, - "OAMPDU", "CCM_RX", "CFM_UNKNOWN_TYPE", "LBM_LBR_LTM_LTR", "Y_1731", "VLAN_LIMIT_LEARN", - "VLAN_ACCEPT_FRAME_TYPE", "CFI_1", "STATIC_DYNAMIC_PORT_MOVING", "PORT_MOVE_FORBID", // 40 - "L3_CRC", "BPDU_PTP_LLDP_EAPOL_RMA", "MSTP_SRC_DROP_DISABLED_BLOCKING", "INVALID_SA", "NEW_SA", - "VLAN_IGR_FILTER", "IGR_VLAN_CONVERT", "GRATUITOUS_ARP", "MSTP_SRC_DROP", "L2_HASH_FULL", // 50 - "MPLS_UNKNOWN_LBL", "L3_IPUC_NON_IP", "TTL", "MTU", "ICMP_REDIRECT", "STORM_CONTROL", "L3_DIP_DMAC_MISMATCH", - "IP4_IP_OPTION", "IP6_HBH_EXT_HEADER", "IP4_IP6_HEADER_ERROR", // 60 - "ROUTING_IP_ADDR_CHECK", "ROUTING_EXCEPTION", "DA_BLOCK", "OAM_MUX", "PORT_ISOLATION", "VLAN_EGR_FILTER", - "MIRROR_ISOLATE", "MSTP_DESTINATION_DROP", "L2_MC_BRIDGE", "IP_UC_MC_ROUTING_LOOK_UP_MISS", // 70 - "L2_UC", "L2_MC", "IP4_MC", "IP6_MC", "L3_UC_MC_ROUTE", "UNKNOWN_L2_UC_FLPM", "BC_FLPM", - "VLAN_PRO_UNKNOWN_L2_MC_FLPM", "VLAN_PRO_UNKNOWN_IP4_MC_FLPM", "VLAN_PROFILE_UNKNOWN_IP6_MC_FLPM" // 80, -}; - -static ssize_t rtl838x_common_read(char __user *buffer, size_t count, - loff_t *ppos, unsigned int value) -{ - char *buf; - ssize_t len; - - if (*ppos != 0) - return 0; - - buf = kasprintf(GFP_KERNEL, "0x%08x\n", value); - if (!buf) - return -ENOMEM; - - if (count < strlen(buf)) { - kfree(buf); - return -ENOSPC; - } - - len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf)); - kfree(buf); - - return len; -} - -static ssize_t rtl838x_common_write(const char __user *buffer, size_t count, - loff_t *ppos, unsigned int *value) -{ - char b[32]; - ssize_t len; - int ret; - - if (*ppos != 0) - return -EINVAL; - - if (count >= sizeof(b)) - return -ENOSPC; - - len = simple_write_to_buffer(b, sizeof(b) - 1, ppos, - buffer, count); - if (len < 0) - return len; - - b[len] = '\0'; - ret = kstrtouint(b, 16, value); - if (ret) - return -EIO; - - return len; -} - -static ssize_t stp_state_read(struct file *filp, char __user *buffer, size_t count, - loff_t *ppos) -{ - struct rtl838x_port *p = filp->private_data; - struct dsa_switch *ds = p->dp->ds; - int value = rtl83xx_port_get_stp_state(ds->priv, p->dp->index); - - if (value < 0) - return -EINVAL; - - return rtl838x_common_read(buffer, count, ppos, (u32)value); -} - -static ssize_t stp_state_write(struct file *filp, const char __user *buffer, - size_t count, loff_t *ppos) -{ - struct rtl838x_port *p = filp->private_data; - u32 value; - size_t res = rtl838x_common_write(buffer, count, ppos, &value); - if (res < 0) - return res; - - rtl83xx_port_stp_state_set(p->dp->ds, p->dp->index, (u8)value); - - return res; -} - -static const struct file_operations stp_state_fops = { - .owner = THIS_MODULE, - .open = simple_open, - .read = stp_state_read, - .write = stp_state_write, -}; - -static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t count, - loff_t *ppos) -{ - struct rtl838x_switch_priv *priv = filp->private_data; - int i; - const char **d; - u32 v; - char *buf; - int n = 0, len, offset; - int num; - - switch (priv->family_id) { - case RTL8380_FAMILY_ID: - d = rtl838x_drop_cntr; - offset = RTL838X_STAT_PRVTE_DROP_COUNTERS; - num = 40; - break; - case RTL8390_FAMILY_ID: - d = rtl839x_drop_cntr; - offset = RTL839X_STAT_PRVTE_DROP_COUNTERS; - num = 45; - break; - case RTL9300_FAMILY_ID: - d = rtl930x_drop_cntr; - offset = RTL930X_STAT_PRVTE_DROP_COUNTERS; - num = 85; - break; - case RTL9310_FAMILY_ID: - d = rtl931x_drop_cntr; - offset = RTL931X_STAT_PRVTE_DROP_COUNTERS; - num = 81; - break; - } - - buf = kmalloc(30 * num, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - for (i = 0; i < num; i++) { - v = sw_r32(offset + (i << 2)) & 0xffff; - n += sprintf(buf + n, "%s: %d\n", d[i], v); - } - - if (count < strlen(buf)) { - kfree(buf); - return -ENOSPC; - } - - len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf)); - kfree(buf); - - return len; -} - -static const struct file_operations drop_counter_fops = { - .owner = THIS_MODULE, - .open = simple_open, - .read = drop_counter_read, -}; - -static void l2_table_print_entry(struct seq_file *m, struct rtl838x_switch_priv *priv, - struct rtl838x_l2_entry *e) -{ - u64 portmask; - int i; - - if (e->type == L2_UNICAST) { - seq_puts(m, "L2_UNICAST\n"); - - seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n", - e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], - e->vid, e->rvid); - - seq_printf(m, " port %d age %d", e->port, e->age); - if (e->is_static) - seq_puts(m, " static"); - if (e->block_da) - seq_puts(m, " block_da"); - if (e->block_sa) - seq_puts(m, " block_sa"); - if (e->suspended) - seq_puts(m, " suspended"); - if (e->next_hop) - seq_printf(m, " next_hop route_id %u", e->nh_route_id); - seq_puts(m, "\n"); - - } else { - if (e->type == L2_MULTICAST) { - seq_puts(m, "L2_MULTICAST\n"); - - seq_printf(m, " mac %02x:%02x:%02x:%02x:%02x:%02x vid %u rvid %u\n", - e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5], - e->vid, e->rvid); - } - - if (e->type == IP4_MULTICAST || e->type == IP6_MULTICAST) { - seq_puts(m, (e->type == IP4_MULTICAST) ? - "IP4_MULTICAST\n" : "IP6_MULTICAST\n"); - - seq_printf(m, " gip %08x sip %08x vid %u rvid %u\n", - e->mc_gip, e->mc_sip, e->vid, e->rvid); - } - - portmask = priv->r->read_mcast_pmask(e->mc_portmask_index); - seq_printf(m, " index %u ports", e->mc_portmask_index); - for (i = 0; i < 64; i++) { - if (portmask & BIT_ULL(i)) - seq_printf(m, " %d", i); - } - seq_puts(m, "\n"); - } - - seq_puts(m, "\n"); -} - -static int l2_table_show(struct seq_file *m, void *v) -{ - struct rtl838x_switch_priv *priv = m->private; - struct rtl838x_l2_entry e; - int i, bucket, index; - - mutex_lock(&priv->reg_mutex); - - for (i = 0; i < priv->fib_entries; i++) { - bucket = i >> 2; - index = i & 0x3; - priv->r->read_l2_entry_using_hash(bucket, index, &e); - - if (!e.valid) - continue; - - seq_printf(m, "Hash table bucket %d index %d ", bucket, index); - l2_table_print_entry(m, priv, &e); - - if (!((i + 1) % 64)) - cond_resched(); - } - - for (i = 0; i < 64; i++) { - priv->r->read_cam(i, &e); - - if (!e.valid) - continue; - - seq_printf(m, "CAM index %d ", i); - l2_table_print_entry(m, priv, &e); - } - - mutex_unlock(&priv->reg_mutex); - - return 0; -} - -static int l2_table_open(struct inode *inode, struct file *filp) -{ - return single_open(filp, l2_table_show, inode->i_private); -} - -static const struct file_operations l2_table_fops = { - .owner = THIS_MODULE, - .open = l2_table_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count, - loff_t *ppos) -{ - struct rtl838x_port *p = filp->private_data; - struct dsa_switch *ds = p->dp->ds; - struct rtl838x_switch_priv *priv = ds->priv; - int value = sw_r32(priv->r->l2_port_aging_out); - - if (value < 0) - return -EINVAL; - - return rtl838x_common_read(buffer, count, ppos, (u32)value); -} - -static ssize_t age_out_write(struct file *filp, const char __user *buffer, - size_t count, loff_t *ppos) -{ - struct rtl838x_port *p = filp->private_data; - u32 value; - size_t res = rtl838x_common_write(buffer, count, ppos, &value); - if (res < 0) - return res; - - rtl83xx_fast_age(p->dp->ds, p->dp->index); - - return res; -} - -static const struct file_operations age_out_fops = { - .owner = THIS_MODULE, - .open = simple_open, - .read = age_out_read, - .write = age_out_write, -}; - -static ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, size_t count, - loff_t *ppos) -{ - struct rtl838x_port *p = filp->private_data; - struct dsa_switch *ds = p->dp->ds; - struct rtl838x_switch_priv *priv = ds->priv; - int value; - if (priv->family_id == RTL8380_FAMILY_ID) - value = rtl838x_get_egress_rate(priv, p->dp->index); - else - value = rtl839x_get_egress_rate(priv, p->dp->index); - - if (value < 0) - return -EINVAL; - - return rtl838x_common_read(buffer, count, ppos, (u32)value); -} - -static ssize_t port_egress_rate_write(struct file *filp, const char __user *buffer, - size_t count, loff_t *ppos) -{ - struct rtl838x_port *p = filp->private_data; - struct dsa_switch *ds = p->dp->ds; - struct rtl838x_switch_priv *priv = ds->priv; - u32 value; - size_t res = rtl838x_common_write(buffer, count, ppos, &value); - if (res < 0) - return res; - - if (priv->family_id == RTL8380_FAMILY_ID) - rtl838x_set_egress_rate(priv, p->dp->index, value); - else - rtl839x_set_egress_rate(priv, p->dp->index, value); - - return res; -} - -static const struct file_operations port_egress_fops = { - .owner = THIS_MODULE, - .open = simple_open, - .read = port_egress_rate_read, - .write = port_egress_rate_write, -}; - - -static const struct debugfs_reg32 port_ctrl_regs[] = { - { .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), }, - { .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, }, -}; - -void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv) -{ - debugfs_remove_recursive(priv->dbgfs_dir); - -// kfree(priv->dbgfs_entries); -} - -static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv, - int port) -{ - struct dentry *port_dir; - struct debugfs_regset32 *port_ctrl_regset; - - port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent); - - if (priv->family_id == RTL8380_FAMILY_ID) { - debugfs_create_x32("storm_rate_uc", 0644, port_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port))); - - debugfs_create_x32("storm_rate_mc", 0644, port_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port))); - - debugfs_create_x32("storm_rate_bc", 0644, port_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port))); - } else { - debugfs_create_x32("storm_rate_uc", 0644, port_dir, - (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port))); - - debugfs_create_x32("storm_rate_mc", 0644, port_dir, - (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port))); - - debugfs_create_x32("storm_rate_bc", 0644, port_dir, - (u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port))); - } - - debugfs_create_u32("id", 0444, port_dir, (u32 *)&priv->ports[port].dp->index); - - port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL); - if (!port_ctrl_regset) - return -ENOMEM; - - port_ctrl_regset->regs = port_ctrl_regs; - port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs); - port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (port << 2)); - debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset); - - debugfs_create_file("stp_state", 0600, port_dir, &priv->ports[port], &stp_state_fops); - debugfs_create_file("age_out", 0600, port_dir, &priv->ports[port], &age_out_fops); - debugfs_create_file("port_egress_rate", 0600, port_dir, &priv->ports[port], - &port_egress_fops); - return 0; -} - -static int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv *priv) -{ - struct dentry *led_dir; - int p; - char led_sw_p_ctrl_name[20]; - char port_led_name[20]; - - led_dir = debugfs_create_dir("led", parent); - - if (priv->family_id == RTL8380_FAMILY_ID) { - debugfs_create_x32("led_glb_ctrl", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8380_LED_GLB_CTRL)); - debugfs_create_x32("led_mode_sel", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_SEL)); - debugfs_create_x32("led_mode_ctrl", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_CTRL)); - debugfs_create_x32("led_p_en_ctrl", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8380_LED_P_EN_CTRL)); - debugfs_create_x32("led_sw_ctrl", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_CTRL)); - debugfs_create_x32("led0_sw_p_en_ctrl", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8380_LED0_SW_P_EN_CTRL)); - debugfs_create_x32("led1_sw_p_en_ctrl", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8380_LED1_SW_P_EN_CTRL)); - debugfs_create_x32("led2_sw_p_en_ctrl", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8380_LED2_SW_P_EN_CTRL)); - for (p = 0; p < 28; p++) { - snprintf(led_sw_p_ctrl_name, sizeof(led_sw_p_ctrl_name), - "led_sw_p_ctrl.%02d", p); - debugfs_create_x32(led_sw_p_ctrl_name, 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_P_CTRL(p))); - } - } else if (priv->family_id == RTL8390_FAMILY_ID) { - debugfs_create_x32("led_glb_ctrl", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL)); - debugfs_create_x32("led_set_2_3", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL)); - debugfs_create_x32("led_set_0_1", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL)); - for (p = 0; p < 4; p++) { - snprintf(port_led_name, sizeof(port_led_name), "led_copr_set_sel.%1d", p); - debugfs_create_x32(port_led_name, 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4))); - snprintf(port_led_name, sizeof(port_led_name), "led_fib_set_sel.%1d", p); - debugfs_create_x32(port_led_name, 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_SET_SEL_CTRL(p << 4))); - } - debugfs_create_x32("led_copr_pmask_ctrl_0", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(0))); - debugfs_create_x32("led_copr_pmask_ctrl_1", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(32))); - debugfs_create_x32("led_fib_pmask_ctrl_0", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(0))); - debugfs_create_x32("led_fib_pmask_ctrl_1", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(32))); - debugfs_create_x32("led_combo_ctrl_0", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(0))); - debugfs_create_x32("led_combo_ctrl_1", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32))); - debugfs_create_x32("led_sw_ctrl", 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL)); - for (p = 0; p < 5; p++) { - snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_en_ctrl.%1d", p); - debugfs_create_x32(port_led_name, 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10))); - } - for (p = 0; p < 28; p++) { - snprintf(port_led_name, sizeof(port_led_name), "led_sw_p_ctrl.%02d", p); - debugfs_create_x32(port_led_name, 0644, led_dir, - (u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p))); - } - } - return 0; -} - -void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) -{ - struct dentry *rtl838x_dir; - struct dentry *port_dir; - struct dentry *mirror_dir; - struct debugfs_regset32 *port_ctrl_regset; - int ret, i; - char lag_name[10]; - char mirror_name[10]; - - pr_info("%s called\n", __func__); - rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL); - if (!rtl838x_dir) - rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL); - - priv->dbgfs_dir = rtl838x_dir; - - debugfs_create_u32("soc", 0444, rtl838x_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO)); - - /* Create one directory per port */ - for (i = 0; i < priv->cpu_port; i++) { - if (priv->ports[i].phy) { - ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i); - if (ret) - goto err; - } - } - - /* Create directory for CPU-port */ - port_dir = debugfs_create_dir("cpu_port", rtl838x_dir); - port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL); - if (!port_ctrl_regset) { - ret = -ENOMEM; - goto err; - } - - port_ctrl_regset->regs = port_ctrl_regs; - port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs); - port_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (priv->cpu_port << 2)); - debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset); - debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port); - - /* Create entries for LAGs */ - for (i = 0; i < priv->n_lags; i++) { - snprintf(lag_name, sizeof(lag_name), "lag.%02d", i); - if (priv->family_id == RTL8380_FAMILY_ID) - debugfs_create_x32(lag_name, 0644, rtl838x_dir, - (u32 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i))); - else - debugfs_create_x64(lag_name, 0644, rtl838x_dir, - (u64 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i))); - } - - /* Create directories for mirror groups */ - for (i = 0; i < 4; i++) { - snprintf(mirror_name, sizeof(mirror_name), "mirror.%1d", i); - mirror_dir = debugfs_create_dir(mirror_name, rtl838x_dir); - if (priv->family_id == RTL8380_FAMILY_ID) { - debugfs_create_x32("ctrl", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_CTRL + i * 4)); - debugfs_create_x32("ingress_pm", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 4)); - debugfs_create_x32("egress_pm", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 4)); - debugfs_create_x32("qid", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_QID_CTRL(i))); - debugfs_create_x32("rspan_vlan", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL(i))); - debugfs_create_x32("rspan_vlan_mac", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i))); - debugfs_create_x32("rspan_tx", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_CTRL)); - debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL)); - debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL)); - } else { - debugfs_create_x32("ctrl", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_CTRL + i * 4)); - debugfs_create_x64("ingress_pm", 0644, mirror_dir, - (u64 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 8)); - debugfs_create_x64("egress_pm", 0644, mirror_dir, - (u64 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 8)); - debugfs_create_x32("rspan_vlan", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_VLAN_CTRL(i))); - debugfs_create_x32("rspan_tx", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_CTRL)); - debugfs_create_x32("rspan_tx_tag_rm", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL)); - debugfs_create_x32("rspan_tx_tag_en", 0644, mirror_dir, - (u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL)); - debugfs_create_x64("sample_rate", 0644, mirror_dir, - (u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SAMPLE_RATE_CTRL)); - } - } - - if (priv->family_id == RTL8380_FAMILY_ID) - debugfs_create_x32("bpdu_flood_mask", 0644, rtl838x_dir, - (u32 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask)); - else - debugfs_create_x64("bpdu_flood_mask", 0644, rtl838x_dir, - (u64 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask)); - - if (priv->family_id == RTL8380_FAMILY_ID) - debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir, - (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_CTRL)); - else - debugfs_create_x32("vlan_ctrl", 0644, rtl838x_dir, - (u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_CTRL)); - - ret = rtl838x_dbgfs_leds(rtl838x_dir, priv); - if (ret) - goto err; - - debugfs_create_file("drop_counters", 0400, rtl838x_dir, priv, &drop_counter_fops); - - debugfs_create_file("l2_table", 0400, rtl838x_dir, priv, &l2_table_fops); - - return; -err: - rtl838x_dbgfs_cleanup(priv); -} - -void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv) -{ - struct dentry *dbg_dir; - - pr_info("%s called\n", __func__); - dbg_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL); - if (!dbg_dir) - dbg_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL); - - priv->dbgfs_dir = dbg_dir; - - debugfs_create_file("drop_counters", 0400, dbg_dir, priv, &drop_counter_fops); - - debugfs_create_file("l2_table", 0400, dbg_dir, priv, &l2_table_fops); -} diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c deleted file mode 100644 index bff42b088a..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c +++ /dev/null @@ -1,2234 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include - -#include -#include "rtl83xx.h" - - -extern struct rtl83xx_soc_info soc_info; - - -static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv) -{ - mutex_lock(&priv->reg_mutex); - - /* Enable statistics module: all counters plus debug. - * On RTL839x all counters are enabled by default - */ - if (priv->family_id == RTL8380_FAMILY_ID) - sw_w32_mask(0, 3, RTL838X_STAT_CTRL); - - /* Reset statistics counters */ - sw_w32_mask(0, 1, priv->r->stat_rst); - - mutex_unlock(&priv->reg_mutex); -} - -static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv) -{ - int i; - u64 v = 0; - - msleep(1000); - /* Enable all ports with a PHY, including the SFP-ports */ - for (i = 0; i < priv->cpu_port; i++) { - if (priv->ports[i].phy) - v |= BIT_ULL(i); - } - - pr_info("%s: %16llx\n", __func__, v); - priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl); - - /* PHY update complete, there is no global PHY polling enable bit on the 9300 */ - if (priv->family_id == RTL8390_FAMILY_ID) - sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL); - else if(priv->family_id == RTL9300_FAMILY_ID) - sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL); -} - -const struct rtl83xx_mib_desc rtl83xx_mib[] = { - MIB_DESC(2, 0xf8, "ifInOctets"), - MIB_DESC(2, 0xf0, "ifOutOctets"), - MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"), - MIB_DESC(1, 0xe8, "ifInUcastPkts"), - MIB_DESC(1, 0xe4, "ifInMulticastPkts"), - MIB_DESC(1, 0xe0, "ifInBroadcastPkts"), - MIB_DESC(1, 0xdc, "ifOutUcastPkts"), - MIB_DESC(1, 0xd8, "ifOutMulticastPkts"), - MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"), - MIB_DESC(1, 0xd0, "ifOutDiscards"), - MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"), - MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"), - MIB_DESC(1, 0xc4, ".3DeferredTransmissions"), - MIB_DESC(1, 0xc0, ".3LateCollisions"), - MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"), - MIB_DESC(1, 0xb8, ".3SymbolErrors"), - MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"), - MIB_DESC(1, 0xb0, ".3InPauseFrames"), - MIB_DESC(1, 0xac, ".3OutPauseFrames"), - MIB_DESC(1, 0xa8, "DropEvents"), - MIB_DESC(1, 0xa4, "tx_BroadcastPkts"), - MIB_DESC(1, 0xa0, "tx_MulticastPkts"), - MIB_DESC(1, 0x9c, "CRCAlignErrors"), - MIB_DESC(1, 0x98, "tx_UndersizePkts"), - MIB_DESC(1, 0x94, "rx_UndersizePkts"), - MIB_DESC(1, 0x90, "rx_UndersizedropPkts"), - MIB_DESC(1, 0x8c, "tx_OversizePkts"), - MIB_DESC(1, 0x88, "rx_OversizePkts"), - MIB_DESC(1, 0x84, "Fragments"), - MIB_DESC(1, 0x80, "Jabbers"), - MIB_DESC(1, 0x7c, "Collisions"), - MIB_DESC(1, 0x78, "tx_Pkts64Octets"), - MIB_DESC(1, 0x74, "rx_Pkts64Octets"), - MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"), - MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"), - MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"), - MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"), - MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"), - MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"), - MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"), - MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"), - MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"), - MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"), - MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"), - MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"), - MIB_DESC(1, 0x40, "rxMacDiscards") -}; - - -/* DSA callbacks */ - - -static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, - int port, - enum dsa_tag_protocol mprot) -{ - /* The switch does not tag the frames, instead internally the header - * structure for each packet is tagged accordingly. - */ - return DSA_TAG_PROTO_TRAILER; -} - -/* - * Initialize all VLANS - */ -static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv) -{ - struct rtl838x_vlan_info info; - int i; - - pr_info("In %s\n", __func__); - - priv->r->vlan_profile_setup(0); - priv->r->vlan_profile_setup(1); - pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK)); - priv->r->vlan_profile_dump(0); - - info.fid = 0; // Default Forwarding ID / MSTI - info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID - info.hash_mc_fid = false; // Do the same for Multicast packets - info.profile_id = 0; // Use default Vlan Profile 0 - info.tagged_ports = 0; // Initially no port members - if (priv->family_id == RTL9310_FAMILY_ID) { - info.if_id = 0; - info.multicast_grp_mask = 0; - info.l2_tunnel_list_id = -1; - } - - // Initialize all vlans 0-4095 - for (i = 0; i < MAX_VLANS; i ++) - priv->r->vlan_set_tagged(i, &info); - - // reset PVIDs; defaults to 1 on reset - for (i = 0; i <= priv->ds->num_ports; i++) { - priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0); - priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0); - priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG); - priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG); - } - - // Set forwarding action based on inner VLAN tag - for (i = 0; i < priv->cpu_port; i++) - priv->r->vlan_fwd_on_inner(i, true); -} - -static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv) -{ - int i; - - for (i = 0; i < priv->cpu_port; i++) - priv->r->set_receive_management_action(i, BPDU, COPY2CPU); -} - -static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv, - int port, bool enable) -{ - int shift = SALRN_PORT_SHIFT(port); - int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED; - - sw_w32_mask(SALRN_MODE_MASK << shift, val << shift, - priv->r->l2_port_new_salrn(port)); -} - -static int rtl83xx_setup(struct dsa_switch *ds) -{ - int i; - struct rtl838x_switch_priv *priv = ds->priv; - - pr_debug("%s called\n", __func__); - - /* Disable MAC polling the PHY so that we can start configuration */ - priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl); - - for (i = 0; i < ds->num_ports; i++) - priv->ports[i].enable = false; - priv->ports[priv->cpu_port].enable = true; - - /* Configure ports so they are disabled by default, but once enabled - * they will work in isolated mode (only traffic between port and CPU). - */ - for (i = 0; i < priv->cpu_port; i++) { - if (priv->ports[i].phy) { - priv->ports[i].pm = BIT_ULL(priv->cpu_port); - priv->r->traffic_set(i, BIT_ULL(i)); - } - } - priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port)); - - /* For standalone ports, forward packets even if a static fdb - * entry for the source address exists on another port. - */ - if (priv->r->set_static_move_action) { - for (i = 0; i <= priv->cpu_port; i++) - priv->r->set_static_move_action(i, true); - } - - if (priv->family_id == RTL8380_FAMILY_ID) - rtl838x_print_matrix(); - else - rtl839x_print_matrix(); - - rtl83xx_init_stats(priv); - - rtl83xx_vlan_setup(priv); - - rtl83xx_setup_bpdu_traps(priv); - - ds->configure_vlan_while_not_filtering = true; - - priv->r->l2_learning_setup(); - - rtl83xx_port_set_salrn(priv, priv->cpu_port, false); - ds->assisted_learning_on_cpu_port = true; - - /* - * Make sure all frames sent to the switch's MAC are trapped to the CPU-port - * 0: FWD, 1: DROP, 2: TRAP2CPU - */ - if (priv->family_id == RTL8380_FAMILY_ID) - sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL); - else - sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL); - - /* Enable MAC Polling PHY again */ - rtl83xx_enable_phy_polling(priv); - pr_debug("Please wait until PHY is settled\n"); - msleep(1000); - priv->r->pie_init(priv); - - return 0; -} - -static int rtl93xx_setup(struct dsa_switch *ds) -{ - int i; - struct rtl838x_switch_priv *priv = ds->priv; - - pr_info("%s called\n", __func__); - - /* Disable MAC polling the PHY so that we can start configuration */ - if (priv->family_id == RTL9300_FAMILY_ID) - sw_w32(0, RTL930X_SMI_POLL_CTRL); - - if (priv->family_id == RTL9310_FAMILY_ID) { - sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL); - sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4); - } - - // Disable all ports except CPU port - for (i = 0; i < ds->num_ports; i++) - priv->ports[i].enable = false; - priv->ports[priv->cpu_port].enable = true; - - /* Configure ports so they are disabled by default, but once enabled - * they will work in isolated mode (only traffic between port and CPU). - */ - for (i = 0; i < priv->cpu_port; i++) { - if (priv->ports[i].phy) { - priv->ports[i].pm = BIT_ULL(priv->cpu_port); - priv->r->traffic_set(i, BIT_ULL(i)); - } - } - priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port)); - - rtl930x_print_matrix(); - - // TODO: Initialize statistics - - rtl83xx_vlan_setup(priv); - - ds->configure_vlan_while_not_filtering = true; - - priv->r->l2_learning_setup(); - - rtl83xx_port_set_salrn(priv, priv->cpu_port, false); - ds->assisted_learning_on_cpu_port = true; - - rtl83xx_enable_phy_polling(priv); - - priv->r->pie_init(priv); - - priv->r->led_init(priv); - - return 0; -} - -static int rtl93xx_get_sds(struct phy_device *phydev) -{ - struct device *dev = &phydev->mdio.dev; - struct device_node *dn; - u32 sds_num; - - if (!dev) - return -1; - if (dev->of_node) { - dn = dev->of_node; - if (of_property_read_u32(dn, "sds", &sds_num)) - sds_num = -1; - } else { - dev_err(dev, "No DT node.\n"); - return -1; - } - - return sds_num; -} - -static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port, - unsigned long *supported, - struct phylink_link_state *state) -{ - struct rtl838x_switch_priv *priv = ds->priv; - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - - pr_debug("In %s port %d, state is %d", __func__, port, state->interface); - - if (!phy_interface_mode_is_rgmii(state->interface) && - state->interface != PHY_INTERFACE_MODE_NA && - state->interface != PHY_INTERFACE_MODE_1000BASEX && - state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII && - state->interface != PHY_INTERFACE_MODE_GMII && - state->interface != PHY_INTERFACE_MODE_QSGMII && - state->interface != PHY_INTERFACE_MODE_INTERNAL && - state->interface != PHY_INTERFACE_MODE_SGMII) { - bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); - dev_err(ds->dev, - "Unsupported interface: %d for port %d\n", - state->interface, port); - return; - } - - /* Allow all the expected bits */ - phylink_set(mask, Autoneg); - phylink_set_port_modes(mask); - phylink_set(mask, Pause); - phylink_set(mask, Asym_Pause); - - /* With the exclusion of MII and Reverse MII, we support Gigabit, - * including Half duplex - */ - if (state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseT_Half); - } - - /* On both the 8380 and 8382, ports 24-27 are SFP ports */ - if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID) - phylink_set(mask, 1000baseX_Full); - - /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */ - if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID) - phylink_set(mask, 1000baseX_Full); - - phylink_set(mask, 10baseT_Half); - phylink_set(mask, 10baseT_Full); - phylink_set(mask, 100baseT_Half); - phylink_set(mask, 100baseT_Full); - - bitmap_and(supported, supported, mask, - __ETHTOOL_LINK_MODE_MASK_NBITS); - bitmap_and(state->advertising, state->advertising, mask, - __ETHTOOL_LINK_MODE_MASK_NBITS); -} - -static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port, - unsigned long *supported, - struct phylink_link_state *state) -{ - struct rtl838x_switch_priv *priv = ds->priv; - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - - pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface, - phy_modes(state->interface)); - - if (!phy_interface_mode_is_rgmii(state->interface) && - state->interface != PHY_INTERFACE_MODE_NA && - state->interface != PHY_INTERFACE_MODE_1000BASEX && - state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII && - state->interface != PHY_INTERFACE_MODE_GMII && - state->interface != PHY_INTERFACE_MODE_QSGMII && - state->interface != PHY_INTERFACE_MODE_XGMII && - state->interface != PHY_INTERFACE_MODE_HSGMII && - state->interface != PHY_INTERFACE_MODE_10GBASER && - state->interface != PHY_INTERFACE_MODE_10GKR && - state->interface != PHY_INTERFACE_MODE_USXGMII && - state->interface != PHY_INTERFACE_MODE_INTERNAL && - state->interface != PHY_INTERFACE_MODE_SGMII) { - bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); - dev_err(ds->dev, - "Unsupported interface: %d for port %d\n", - state->interface, port); - return; - } - - /* Allow all the expected bits */ - phylink_set(mask, Autoneg); - phylink_set_port_modes(mask); - phylink_set(mask, Pause); - phylink_set(mask, Asym_Pause); - - /* With the exclusion of MII and Reverse MII, we support Gigabit, - * including Half duplex - */ - if (state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseT_Half); - } - - // Internal phys of the RTL93xx family provide 10G - if (priv->ports[port].phy_is_integrated - && state->interface == PHY_INTERFACE_MODE_1000BASEX) { - phylink_set(mask, 1000baseX_Full); - } else if (priv->ports[port].phy_is_integrated) { - phylink_set(mask, 1000baseX_Full); - phylink_set(mask, 10000baseKR_Full); - phylink_set(mask, 10000baseSR_Full); - phylink_set(mask, 10000baseCR_Full); - } - if (state->interface == PHY_INTERFACE_MODE_INTERNAL) { - phylink_set(mask, 1000baseX_Full); - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 10000baseKR_Full); - phylink_set(mask, 10000baseT_Full); - phylink_set(mask, 10000baseSR_Full); - phylink_set(mask, 10000baseCR_Full); - } - - if (state->interface == PHY_INTERFACE_MODE_USXGMII) - phylink_set(mask, 10000baseT_Full); - - phylink_set(mask, 10baseT_Half); - phylink_set(mask, 10baseT_Full); - phylink_set(mask, 100baseT_Half); - phylink_set(mask, 100baseT_Full); - - bitmap_and(supported, supported, mask, - __ETHTOOL_LINK_MODE_MASK_NBITS); - bitmap_and(state->advertising, state->advertising, mask, - __ETHTOOL_LINK_MODE_MASK_NBITS); - pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported); -} - -static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port, - struct phylink_link_state *state) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 speed; - u64 link; - - if (port < 0 || port > priv->cpu_port) - return -EINVAL; - - state->link = 0; - link = priv->r->get_port_reg_le(priv->r->mac_link_sts); - if (link & BIT_ULL(port)) - state->link = 1; - pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port)); - - state->duplex = 0; - if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port)) - state->duplex = 1; - - speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port)); - speed >>= (port % 16) << 1; - switch (speed & 0x3) { - case 0: - state->speed = SPEED_10; - break; - case 1: - state->speed = SPEED_100; - break; - case 2: - state->speed = SPEED_1000; - break; - case 3: - if (priv->family_id == RTL9300_FAMILY_ID - && (port == 24 || port == 26)) /* Internal serdes */ - state->speed = SPEED_2500; - else - state->speed = SPEED_100; /* Is in fact 500Mbit */ - } - - state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); - if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port)) - state->pause |= MLO_PAUSE_RX; - if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port)) - state->pause |= MLO_PAUSE_TX; - return 1; -} - -static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port, - struct phylink_link_state *state) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 speed; - u64 link; - u64 media; - - if (port < 0 || port > priv->cpu_port) - return -EINVAL; - - /* - * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link - * state needs to be read twice in order to read a correct result. - * This would not be necessary for ports connected e.g. to RTL8218D - * PHYs. - */ - state->link = 0; - link = priv->r->get_port_reg_le(priv->r->mac_link_sts); - link = priv->r->get_port_reg_le(priv->r->mac_link_sts); - if (link & BIT_ULL(port)) - state->link = 1; - - if (priv->family_id == RTL9310_FAMILY_ID) - media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS); - - if (priv->family_id == RTL9300_FAMILY_ID) - media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS); - - if (media & BIT_ULL(port)) - state->link = 1; - - pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port, - link & BIT_ULL(port), media); - - state->duplex = 0; - if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port)) - state->duplex = 1; - - speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port)); - speed >>= (port % 8) << 2; - switch (speed & 0xf) { - case 0: - state->speed = SPEED_10; - break; - case 1: - state->speed = SPEED_100; - break; - case 2: - case 7: - state->speed = SPEED_1000; - break; - case 4: - state->speed = SPEED_10000; - break; - case 5: - case 8: - state->speed = SPEED_2500; - break; - case 6: - state->speed = SPEED_5000; - break; - default: - pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf); - } - - if (priv->family_id == RTL9310_FAMILY_ID - && (port >= 52 || port <= 55)) { /* Internal serdes */ - state->speed = SPEED_10000; - state->link = 1; - state->duplex = 1; - } - - pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed); - state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); - if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port)) - state->pause |= MLO_PAUSE_RX; - if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port)) - state->pause |= MLO_PAUSE_TX; - return 1; -} - -static void rtl83xx_config_interface(int port, phy_interface_t interface) -{ - u32 old, int_shift, sds_shift; - - switch (port) { - case 24: - int_shift = 0; - sds_shift = 5; - break; - case 26: - int_shift = 3; - sds_shift = 0; - break; - default: - return; - } - - old = sw_r32(RTL838X_SDS_MODE_SEL); - switch (interface) { - case PHY_INTERFACE_MODE_1000BASEX: - if ((old >> sds_shift & 0x1f) == 4) - return; - sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL); - sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL); - break; - case PHY_INTERFACE_MODE_SGMII: - if ((old >> sds_shift & 0x1f) == 2) - return; - sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL); - sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL); - break; - default: - return; - } - pr_debug("configured port %d for interface %s\n", port, phy_modes(interface)); -} - -static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port, - unsigned int mode, - const struct phylink_link_state *state) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u32 reg; - int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3; - - pr_debug("%s port %d, mode %x\n", __func__, port, mode); - - if (port == priv->cpu_port) { - /* Set Speed, duplex, flow control - * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL - * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN - * | MEDIA_SEL - */ - if (priv->family_id == RTL8380_FAMILY_ID) { - sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port)); - /* allow CRC errors on CPU-port */ - sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port)); - } else { - sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port)); - } - return; - } - - reg = sw_r32(priv->r->mac_force_mode_ctrl(port)); - /* Auto-Negotiation does not work for MAC in RTL8390 */ - if (priv->family_id == RTL8380_FAMILY_ID) { - if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) { - pr_debug("PHY autonegotiates\n"); - reg |= RTL838X_NWAY_EN; - sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); - rtl83xx_config_interface(port, state->interface); - return; - } - } - - if (mode != MLO_AN_FIXED) - pr_debug("Fixed state.\n"); - - /* Clear id_mode_dis bit, and the existing port mode, let - * RGMII_MODE_EN bet set by mac_link_{up,down} */ - if (priv->family_id == RTL8380_FAMILY_ID) { - reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN); - if (state->pause & MLO_PAUSE_TXRX_MASK) { - if (state->pause & MLO_PAUSE_TX) - reg |= RTL838X_TX_PAUSE_EN; - reg |= RTL838X_RX_PAUSE_EN; - } - } else if (priv->family_id == RTL8390_FAMILY_ID) { - reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN); - if (state->pause & MLO_PAUSE_TXRX_MASK) { - if (state->pause & MLO_PAUSE_TX) - reg |= RTL839X_TX_PAUSE_EN; - reg |= RTL839X_RX_PAUSE_EN; - } - } - - - reg &= ~(3 << speed_bit); - switch (state->speed) { - case SPEED_1000: - reg |= 2 << speed_bit; - break; - case SPEED_100: - reg |= 1 << speed_bit; - break; - default: - break; // Ignore, including 10MBit which has a speed value of 0 - } - - if (priv->family_id == RTL8380_FAMILY_ID) { - reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN); - if (state->link) - reg |= RTL838X_FORCE_LINK_EN; - if (state->duplex == RTL838X_DUPLEX_MODE) - reg |= RTL838X_DUPLEX_MODE; - } else if (priv->family_id == RTL8390_FAMILY_ID) { - reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN); - if (state->link) - reg |= RTL839X_FORCE_LINK_EN; - if (state->duplex == RTL839X_DUPLEX_MODE) - reg |= RTL839X_DUPLEX_MODE; - } - - // LAG members must use DUPLEX and we need to enable the link - if (priv->lagmembers & BIT_ULL(port)) { - switch(priv->family_id) { - case RTL8380_FAMILY_ID: - reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN); - break; - case RTL8390_FAMILY_ID: - reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN); - break; - } - } - - // Disable AN - if (priv->family_id == RTL8380_FAMILY_ID) - reg &= ~RTL838X_NWAY_EN; - sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); -} - -static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port, - unsigned int mode, - const struct phylink_link_state *state) -{ - struct rtl838x_switch_priv *priv = ds->priv; - int sds_num; - u32 reg, band; - - sds_num = priv->ports[port].sds_num; - pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num); - - switch (state->interface) { - case PHY_INTERFACE_MODE_HSGMII: - pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__); - band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII); - rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII); - band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII); - break; - case PHY_INTERFACE_MODE_1000BASEX: - band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX); - rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX); - break; - case PHY_INTERFACE_MODE_XGMII: - band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII); - rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII); - break; - case PHY_INTERFACE_MODE_10GBASER: - case PHY_INTERFACE_MODE_10GKR: - band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER); - rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER); - break; - case PHY_INTERFACE_MODE_USXGMII: - // Translates to MII_USXGMII_10GSXGMII - band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII); - rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII); - break; - case PHY_INTERFACE_MODE_SGMII: - pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__); - band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII); - rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII); - band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII); - break; - case PHY_INTERFACE_MODE_QSGMII: - band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII); - rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII); - break; - default: - pr_err("%s: unknown serdes mode: %s\n", - __func__, phy_modes(state->interface)); - return; - } - - reg = sw_r32(priv->r->mac_force_mode_ctrl(port)); - pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg); - - reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN); - - reg &= ~(0xf << 12); - reg |= 0x2 << 12; // Set SMI speed to 0x2 - - reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN; - - if (priv->lagmembers & BIT_ULL(port)) - reg |= RTL931X_DUPLEX_MODE; - - if (state->duplex == DUPLEX_FULL) - reg |= RTL931X_DUPLEX_MODE; - - sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); - -} - -static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port, - unsigned int mode, - const struct phylink_link_state *state) -{ - struct rtl838x_switch_priv *priv = ds->priv; - int sds_num, sds_mode; - u32 reg; - - pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__, - port, mode, phy_modes(state->interface), state->speed, state->link); - - // Nothing to be done for the CPU-port - if (port == priv->cpu_port) - return; - - if (priv->family_id == RTL9310_FAMILY_ID) - return rtl931x_phylink_mac_config(ds, port, mode, state); - - sds_num = priv->ports[port].sds_num; - pr_info("%s SDS is %d\n", __func__, sds_num); - if (sds_num >= 0) { - switch (state->interface) { - case PHY_INTERFACE_MODE_HSGMII: - sds_mode = 0x12; - break; - case PHY_INTERFACE_MODE_1000BASEX: - sds_mode = 0x04; - break; - case PHY_INTERFACE_MODE_XGMII: - sds_mode = 0x10; - break; - case PHY_INTERFACE_MODE_10GBASER: - case PHY_INTERFACE_MODE_10GKR: - sds_mode = 0x1b; // 10G 1000X Auto - break; - case PHY_INTERFACE_MODE_USXGMII: - sds_mode = 0x0d; - break; - default: - pr_err("%s: unknown serdes mode: %s\n", - __func__, phy_modes(state->interface)); - return; - } - if (state->interface == PHY_INTERFACE_MODE_10GBASER) - rtl9300_serdes_setup(sds_num, state->interface); - } - - reg = sw_r32(priv->r->mac_force_mode_ctrl(port)); - reg &= ~(0xf << 3); - - switch (state->speed) { - case SPEED_10000: - reg |= 4 << 3; - break; - case SPEED_5000: - reg |= 6 << 3; - break; - case SPEED_2500: - reg |= 5 << 3; - break; - case SPEED_1000: - reg |= 2 << 3; - break; - default: - reg |= 2 << 3; - break; - } - - if (state->link) - reg |= RTL930X_FORCE_LINK_EN; - - if (priv->lagmembers & BIT_ULL(port)) - reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN; - - if (state->duplex == DUPLEX_FULL) - reg |= RTL930X_DUPLEX_MODE; - - if (priv->ports[port].phy_is_integrated) - reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link - else - reg |= RTL930X_FORCE_EN; - - sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); -} - -static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port, - unsigned int mode, - phy_interface_t interface) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - /* Stop TX/RX to port */ - sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); - - // No longer force link - sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port)); -} - -static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port, - unsigned int mode, - phy_interface_t interface) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u32 v = 0; - - /* Stop TX/RX to port */ - sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); - - // No longer force link - if (priv->family_id == RTL9300_FAMILY_ID) - v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN; - else if (priv->family_id == RTL9310_FAMILY_ID) - v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN; - sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port)); -} - -static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port, - unsigned int mode, - phy_interface_t interface, - struct phy_device *phydev, - int speed, int duplex, - bool tx_pause, bool rx_pause) -{ - struct rtl838x_switch_priv *priv = ds->priv; - /* Restart TX/RX to port */ - sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port)); - // TODO: Set speed/duplex/pauses -} - -static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port, - unsigned int mode, - phy_interface_t interface, - struct phy_device *phydev, - int speed, int duplex, - bool tx_pause, bool rx_pause) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - /* Restart TX/RX to port */ - sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port)); - // TODO: Set speed/duplex/pauses -} - -static void rtl83xx_get_strings(struct dsa_switch *ds, - int port, u32 stringset, u8 *data) -{ - int i; - - if (stringset != ETH_SS_STATS) - return; - - for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) - strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name, - ETH_GSTRING_LEN); -} - -static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port, - uint64_t *data) -{ - struct rtl838x_switch_priv *priv = ds->priv; - const struct rtl83xx_mib_desc *mib; - int i; - u64 h; - - for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) { - mib = &rtl83xx_mib[i]; - - data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset); - if (mib->size == 2) { - h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset); - data[i] |= h << 32; - } - } -} - -static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset) -{ - if (sset != ETH_SS_STATS) - return 0; - - return ARRAY_SIZE(rtl83xx_mib); -} - -static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port) -{ - int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1); - u64 portmask; - - if (mc_group >= MAX_MC_GROUPS - 1) - return -1; - - set_bit(mc_group, priv->mc_group_bm); - portmask = BIT_ULL(port); - priv->r->write_mcast_pmask(mc_group, portmask); - - return mc_group; -} - -static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port) -{ - u64 portmask = priv->r->read_mcast_pmask(mc_group); - - pr_debug("%s: %d\n", __func__, port); - - portmask |= BIT_ULL(port); - priv->r->write_mcast_pmask(mc_group, portmask); - - return portmask; -} - -static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port) -{ - u64 portmask = priv->r->read_mcast_pmask(mc_group); - - pr_debug("%s: %d\n", __func__, port); - - portmask &= ~BIT_ULL(port); - priv->r->write_mcast_pmask(mc_group, portmask); - if (!portmask) - clear_bit(mc_group, priv->mc_group_bm); - - return portmask; -} - -static int rtl83xx_port_enable(struct dsa_switch *ds, int port, - struct phy_device *phydev) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 v; - - pr_debug("%s: %x %d", __func__, (u32) priv, port); - priv->ports[port].enable = true; - - /* enable inner tagging on egress, do not keep any tags */ - priv->r->vlan_port_keep_tag_set(port, 0, 1); - - if (dsa_is_cpu_port(ds, port)) - return 0; - - /* add port to switch mask of CPU_PORT */ - priv->r->traffic_enable(priv->cpu_port, port); - - if (priv->is_lagmember[port]) { - pr_debug("%s: %d is lag slave. ignore\n", __func__, port); - return 0; - } - - /* add all other ports in the same bridge to switch mask of port */ - v = priv->r->traffic_get(port); - v |= priv->ports[port].pm; - priv->r->traffic_set(port, v); - - // TODO: Figure out if this is necessary - if (priv->family_id == RTL9300_FAMILY_ID) { - sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL); - sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL); - } - - if (priv->ports[port].sds_num < 0) - priv->ports[port].sds_num = rtl93xx_get_sds(phydev); - - return 0; -} - -static void rtl83xx_port_disable(struct dsa_switch *ds, int port) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 v; - - pr_debug("%s %x: %d", __func__, (u32)priv, port); - /* you can only disable user ports */ - if (!dsa_is_user_port(ds, port)) - return; - - // BUG: This does not work on RTL931X - /* remove port from switch mask of CPU_PORT */ - priv->r->traffic_disable(priv->cpu_port, port); - - /* remove all other ports in the same bridge from switch mask of port */ - v = priv->r->traffic_get(port); - v &= ~priv->ports[port].pm; - priv->r->traffic_set(port, v); - - priv->ports[port].enable = false; -} - -static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port, - struct ethtool_eee *e) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - if (e->eee_enabled && !priv->eee_enabled) { - pr_info("Globally enabling EEE\n"); - priv->r->init_eee(priv, true); - } - - priv->r->port_eee_set(priv, port, e->eee_enabled); - - if (e->eee_enabled) - pr_info("Enabled EEE for port %d\n", port); - else - pr_info("Disabled EEE for port %d\n", port); - return 0; -} - -static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port, - struct ethtool_eee *e) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full; - - priv->r->eee_port_ability(priv, e, port); - - e->eee_enabled = priv->ports[port].eee_enabled; - - e->eee_active = !!(e->advertised & e->lp_advertised); - - return 0; -} - -static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port, - struct ethtool_eee *e) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full - | SUPPORTED_2500baseX_Full; - - priv->r->eee_port_ability(priv, e, port); - - e->eee_enabled = priv->ports[port].eee_enabled; - - e->eee_active = !!(e->advertised & e->lp_advertised); - - return 0; -} - -static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - priv->r->set_ageing_time(msec); - return 0; -} - -static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port, - struct net_device *bridge) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 port_bitmap = BIT_ULL(priv->cpu_port), v; - int i; - - pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap); - - if (priv->is_lagmember[port]) { - pr_debug("%s: %d is lag slave. ignore\n", __func__, port); - return 0; - } - - mutex_lock(&priv->reg_mutex); - for (i = 0; i < ds->num_ports; i++) { - /* Add this port to the port matrix of the other ports in the - * same bridge. If the port is disabled, port matrix is kept - * and not being setup until the port becomes enabled. - */ - if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) { - if (dsa_to_port(ds, i)->bridge_dev != bridge) - continue; - if (priv->ports[i].enable) - priv->r->traffic_enable(i, port); - - priv->ports[i].pm |= BIT_ULL(port); - port_bitmap |= BIT_ULL(i); - } - } - - /* Add all other ports to this port matrix. */ - if (priv->ports[port].enable) { - priv->r->traffic_enable(priv->cpu_port, port); - v = priv->r->traffic_get(port); - v |= port_bitmap; - priv->r->traffic_set(port, v); - } - priv->ports[port].pm |= port_bitmap; - - if (priv->r->set_static_move_action) - priv->r->set_static_move_action(port, false); - - mutex_unlock(&priv->reg_mutex); - - return 0; -} - -static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port, - struct net_device *bridge) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 port_bitmap = 0, v; - int i; - - pr_debug("%s %x: %d", __func__, (u32)priv, port); - mutex_lock(&priv->reg_mutex); - for (i = 0; i < ds->num_ports; i++) { - /* Remove this port from the port matrix of the other ports - * in the same bridge. If the port is disabled, port matrix - * is kept and not being setup until the port becomes enabled. - * And the other port's port matrix cannot be broken when the - * other port is still a VLAN-aware port. - */ - if (dsa_is_user_port(ds, i) && i != port) { - if (dsa_to_port(ds, i)->bridge_dev != bridge) - continue; - if (priv->ports[i].enable) - priv->r->traffic_disable(i, port); - - priv->ports[i].pm &= ~BIT_ULL(port); - port_bitmap |= BIT_ULL(i); - } - } - - /* Remove all other ports from this port matrix. */ - if (priv->ports[port].enable) { - v = priv->r->traffic_get(port); - v &= ~port_bitmap; - priv->r->traffic_set(port, v); - } - priv->ports[port].pm &= ~port_bitmap; - - if (priv->r->set_static_move_action) - priv->r->set_static_move_action(port, true); - - mutex_unlock(&priv->reg_mutex); -} - -void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) -{ - u32 msti = 0; - u32 port_state[4]; - int index, bit; - int pos = port; - struct rtl838x_switch_priv *priv = ds->priv; - int n = priv->port_width << 1; - - /* Ports above or equal CPU port can never be configured */ - if (port >= priv->cpu_port) - return; - - mutex_lock(&priv->reg_mutex); - - /* For the RTL839x and following, the bits are left-aligned, 838x and 930x - * have 64 bit fields, 839x and 931x have 128 bit fields - */ - if (priv->family_id == RTL8390_FAMILY_ID) - pos += 12; - if (priv->family_id == RTL9300_FAMILY_ID) - pos += 3; - if (priv->family_id == RTL9310_FAMILY_ID) - pos += 8; - - index = n - (pos >> 4) - 1; - bit = (pos << 1) % 32; - - priv->r->stp_get(priv, msti, port_state); - - pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3); - port_state[index] &= ~(3 << bit); - - switch (state) { - case BR_STATE_DISABLED: /* 0 */ - port_state[index] |= (0 << bit); - break; - case BR_STATE_BLOCKING: /* 4 */ - case BR_STATE_LISTENING: /* 1 */ - port_state[index] |= (1 << bit); - break; - case BR_STATE_LEARNING: /* 2 */ - port_state[index] |= (2 << bit); - break; - case BR_STATE_FORWARDING: /* 3*/ - port_state[index] |= (3 << bit); - default: - break; - } - - priv->r->stp_set(priv, msti, port_state); - - mutex_unlock(&priv->reg_mutex); -} - -void rtl83xx_fast_age(struct dsa_switch *ds, int port) -{ - struct rtl838x_switch_priv *priv = ds->priv; - int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0; - - pr_debug("FAST AGE port %d\n", port); - mutex_lock(&priv->reg_mutex); - /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger - * port fields: - * 0-4: Replacing port - * 5-9: Flushed/replaced port - * 10-21: FVID - * 22: Entry types: 1: dynamic, 0: also static - * 23: Match flush port - * 24: Match FVID - * 25: Flush (0) or replace (1) L2 entries - * 26: Status of action (1: Start, 0: Done) - */ - sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl); - - do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s)); - - mutex_unlock(&priv->reg_mutex); -} - -void rtl931x_fast_age(struct dsa_switch *ds, int port) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - pr_info("%s port %d\n", __func__, port); - mutex_lock(&priv->reg_mutex); - sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4); - - sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL); - - do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28)); - - mutex_unlock(&priv->reg_mutex); -} - -void rtl930x_fast_age(struct dsa_switch *ds, int port) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - if (priv->family_id == RTL9310_FAMILY_ID) - return rtl931x_fast_age(ds, port); - - pr_debug("FAST AGE port %d\n", port); - mutex_lock(&priv->reg_mutex); - sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4); - - sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL); - - do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30)); - - mutex_unlock(&priv->reg_mutex); -} - -static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port, - bool vlan_filtering, - struct switchdev_trans *trans) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - pr_debug("%s: port %d\n", __func__, port); - mutex_lock(&priv->reg_mutex); - - if (vlan_filtering) { - /* Enable ingress and egress filtering - * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define - * the filter action: - * 0: Always Forward - * 1: Drop packet - * 2: Trap packet to CPU port - * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED) - */ - if (port != priv->cpu_port) - priv->r->set_vlan_igr_filter(port, IGR_DROP); - - priv->r->set_vlan_egr_filter(port, EGR_ENABLE); - } else { - /* Disable ingress and egress filtering */ - if (port != priv->cpu_port) - priv->r->set_vlan_igr_filter(port, IGR_FORWARD); - - priv->r->set_vlan_egr_filter(port, EGR_DISABLE); - } - - /* Do we need to do something to the CPU-Port, too? */ - mutex_unlock(&priv->reg_mutex); - - return 0; -} - -static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan) -{ - struct rtl838x_vlan_info info; - struct rtl838x_switch_priv *priv = ds->priv; - - priv->r->vlan_tables_read(0, &info); - - pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n", - info.tagged_ports, info.untagged_ports, info.profile_id, - info.hash_mc_fid, info.hash_uc_fid, info.fid); - - priv->r->vlan_tables_read(1, &info); - pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n", - info.tagged_ports, info.untagged_ports, info.profile_id, - info.hash_mc_fid, info.hash_uc_fid, info.fid); - priv->r->vlan_set_untagged(1, info.untagged_ports); - pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports); - - priv->r->vlan_set_tagged(1, &info); - pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports); - - return 0; -} - -static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv, - int port, int pvid) -{ - /* Set both inner and outer PVID of the port */ - priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid); - priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid); - priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER, - PBVLAN_MODE_UNTAG_AND_PRITAG); - priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER, - PBVLAN_MODE_UNTAG_AND_PRITAG); - - priv->ports[port].pvid = pvid; -} - -static void rtl83xx_vlan_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan) -{ - struct rtl838x_vlan_info info; - struct rtl838x_switch_priv *priv = ds->priv; - int v; - - pr_debug("%s port %d, vid_begin %d, vid_end %d, flags %x\n", __func__, - port, vlan->vid_begin, vlan->vid_end, vlan->flags); - - if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) { - dev_err(priv->dev, "VLAN out of range: %d - %d", - vlan->vid_begin, vlan->vid_end); - return; - } - - mutex_lock(&priv->reg_mutex); - - for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { - if (vlan->flags & BRIDGE_VLAN_INFO_PVID) - rtl83xx_vlan_set_pvid(priv, port, v); - else if (priv->ports[port].pvid == v) - rtl83xx_vlan_set_pvid(priv, port, 0); - } - - for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { - /* Get port memberships of this vlan */ - priv->r->vlan_tables_read(v, &info); - - /* new VLAN? */ - if (!info.tagged_ports) { - info.fid = 0; - info.hash_mc_fid = false; - info.hash_uc_fid = false; - info.profile_id = 0; - } - - /* sanitize untagged_ports - must be a subset */ - if (info.untagged_ports & ~info.tagged_ports) - info.untagged_ports = 0; - - info.tagged_ports |= BIT_ULL(port); - if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) - info.untagged_ports |= BIT_ULL(port); - else - info.untagged_ports &= ~BIT_ULL(port); - - priv->r->vlan_set_untagged(v, info.untagged_ports); - pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports); - - priv->r->vlan_set_tagged(v, &info); - pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports); - } - - mutex_unlock(&priv->reg_mutex); -} - -static int rtl83xx_vlan_del(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan) -{ - struct rtl838x_vlan_info info; - struct rtl838x_switch_priv *priv = ds->priv; - int v; - u16 pvid; - - pr_debug("%s: port %d, vid_begin %d, vid_end %d, flags %x\n", __func__, - port, vlan->vid_begin, vlan->vid_end, vlan->flags); - - if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) { - dev_err(priv->dev, "VLAN out of range: %d - %d", - vlan->vid_begin, vlan->vid_end); - return -ENOTSUPP; - } - - mutex_lock(&priv->reg_mutex); - pvid = priv->ports[port].pvid; - - for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { - /* Reset to default if removing the current PVID */ - if (v == pvid) { - rtl83xx_vlan_set_pvid(priv, port, 0); - } - /* Get port memberships of this vlan */ - priv->r->vlan_tables_read(v, &info); - - /* remove port from both tables */ - info.untagged_ports &= (~BIT_ULL(port)); - info.tagged_ports &= (~BIT_ULL(port)); - - priv->r->vlan_set_untagged(v, info.untagged_ports); - pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports); - - priv->r->vlan_set_tagged(v, &info); - pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports); - } - mutex_unlock(&priv->reg_mutex); - - return 0; -} - -static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac) -{ - memset(e, 0, sizeof(*e)); - - e->type = L2_UNICAST; - e->valid = true; - - e->age = 3; - e->is_static = true; - - e->port = port; - - e->rvid = e->vid = vid; - e->is_ip_mc = e->is_ipv6_mc = false; - u64_to_ether_addr(mac, e->mac); -} - -static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group) -{ - memset(e, 0, sizeof(*e)); - - e->type = L2_MULTICAST; - e->valid = true; - - e->mc_portmask_index = mc_group; - - e->rvid = e->vid = vid; - e->is_ip_mc = e->is_ipv6_mc = false; - u64_to_ether_addr(mac, e->mac); -} - -/* - * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops - * over the entries in the bucket until either a matching entry is found or an empty slot - * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found - * when an empty slot was found and must exist is false, the index of the slot is returned - * when no slots are available returns -1 - */ -static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed, - bool must_exist, struct rtl838x_l2_entry *e) -{ - int i, idx = -1; - u32 key = priv->r->l2_hash_key(priv, seed); - u64 entry; - - pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed); - // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs - for (i = 0; i < priv->l2_bucket_size; i++) { - entry = priv->r->read_l2_entry_using_hash(key, i, e); - pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0])); - if (must_exist && !e->valid) - continue; - if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) { - idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff; - break; - } - } - - return idx; -} - -/* - * Uses the seed to identify an entry in the CAM by looping over all its entries - * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found - * when an empty slot was found the index of the slot is returned - * when no slots are available returns -1 - */ -static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed, - bool must_exist, struct rtl838x_l2_entry *e) -{ - int i, idx = -1; - u64 entry; - - for (i = 0; i < 64; i++) { - entry = priv->r->read_cam(i, e); - if (!must_exist && !e->valid) { - if (idx < 0) /* First empty entry? */ - idx = i; - break; - } else if ((entry & 0x0fffffffffffffffULL) == seed) { - pr_debug("Found entry in CAM\n"); - idx = i; - break; - } - } - return idx; -} - -static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port, - const unsigned char *addr, u16 vid) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 mac = ether_addr_to_u64(addr); - struct rtl838x_l2_entry e; - int err = 0, idx; - u64 seed = priv->r->l2_hash_seed(mac, vid); - - if (priv->is_lagmember[port]) { - pr_debug("%s: %d is lag slave. ignore\n", __func__, port); - return 0; - } - - mutex_lock(&priv->reg_mutex); - - idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e); - - // Found an existing or empty entry - if (idx >= 0) { - rtl83xx_setup_l2_uc_entry(&e, port, vid, mac); - priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); - goto out; - } - - // Hash buckets full, try CAM - idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e); - - if (idx >= 0) { - rtl83xx_setup_l2_uc_entry(&e, port, vid, mac); - priv->r->write_cam(idx, &e); - goto out; - } - - err = -ENOTSUPP; -out: - mutex_unlock(&priv->reg_mutex); - return err; -} - -static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port, - const unsigned char *addr, u16 vid) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 mac = ether_addr_to_u64(addr); - struct rtl838x_l2_entry e; - int err = 0, idx; - u64 seed = priv->r->l2_hash_seed(mac, vid); - - pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid); - mutex_lock(&priv->reg_mutex); - - idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e); - - if (idx >= 0) { - pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); - e.valid = false; - priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); - goto out; - } - - /* Check CAM for spillover from hash buckets */ - idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e); - - if (idx >= 0) { - e.valid = false; - priv->r->write_cam(idx, &e); - goto out; - } - err = -ENOENT; -out: - mutex_unlock(&priv->reg_mutex); - return err; -} - -static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, - dsa_fdb_dump_cb_t *cb, void *data) -{ - struct rtl838x_l2_entry e; - struct rtl838x_switch_priv *priv = ds->priv; - int i; - - mutex_lock(&priv->reg_mutex); - - for (i = 0; i < priv->fib_entries; i++) { - priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e); - - if (!e.valid) - continue; - - if (e.port == port || e.port == RTL930X_PORT_IGNORE) - cb(e.mac, e.vid, e.is_static, data); - - if (!((i + 1) % 64)) - cond_resched(); - } - - for (i = 0; i < 64; i++) { - priv->r->read_cam(i, &e); - - if (!e.valid) - continue; - - if (e.port == port) - cb(e.mac, e.vid, e.is_static, data); - } - - mutex_unlock(&priv->reg_mutex); - return 0; -} - -static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_mdb *mdb) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - if (priv->id >= 0x9300) - return -EOPNOTSUPP; - - return 0; -} - -static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_mdb *mdb) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 mac = ether_addr_to_u64(mdb->addr); - struct rtl838x_l2_entry e; - int err = 0, idx; - int vid = mdb->vid; - u64 seed = priv->r->l2_hash_seed(mac, vid); - int mc_group; - - pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid); - - if (priv->is_lagmember[port]) { - pr_debug("%s: %d is lag slave. ignore\n", __func__, port); - return; - } - - mutex_lock(&priv->reg_mutex); - - idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e); - - // Found an existing or empty entry - if (idx >= 0) { - if (e.valid) { - pr_debug("Found an existing entry %016llx, mc_group %d\n", - ether_addr_to_u64(e.mac), e.mc_portmask_index); - rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port); - } else { - pr_debug("New entry for seed %016llx\n", seed); - mc_group = rtl83xx_mc_group_alloc(priv, port); - if (mc_group < 0) { - err = -ENOTSUPP; - goto out; - } - rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group); - priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); - } - goto out; - } - - // Hash buckets full, try CAM - idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e); - - if (idx >= 0) { - if (e.valid) { - pr_debug("Found existing CAM entry %016llx, mc_group %d\n", - ether_addr_to_u64(e.mac), e.mc_portmask_index); - rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port); - } else { - pr_debug("New entry\n"); - mc_group = rtl83xx_mc_group_alloc(priv, port); - if (mc_group < 0) { - err = -ENOTSUPP; - goto out; - } - rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group); - priv->r->write_cam(idx, &e); - } - goto out; - } - - err = -ENOTSUPP; -out: - mutex_unlock(&priv->reg_mutex); - if (err) - dev_err(ds->dev, "failed to add MDB entry\n"); -} - -int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_mdb *mdb) -{ - struct rtl838x_switch_priv *priv = ds->priv; - u64 mac = ether_addr_to_u64(mdb->addr); - struct rtl838x_l2_entry e; - int err = 0, idx; - int vid = mdb->vid; - u64 seed = priv->r->l2_hash_seed(mac, vid); - u64 portmask; - - pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid); - - if (priv->is_lagmember[port]) { - pr_info("%s: %d is lag slave. ignore\n", __func__, port); - return 0; - } - - mutex_lock(&priv->reg_mutex); - - idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e); - - if (idx >= 0) { - pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3); - portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port); - if (!portmask) { - e.valid = false; - priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e); - } - goto out; - } - - /* Check CAM for spillover from hash buckets */ - idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e); - - if (idx >= 0) { - portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port); - if (!portmask) { - e.valid = false; - priv->r->write_cam(idx, &e); - } - goto out; - } - // TODO: Re-enable with a newer kernel: err = -ENOENT; -out: - mutex_unlock(&priv->reg_mutex); - return err; -} - -static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port, - struct dsa_mall_mirror_tc_entry *mirror, - bool ingress) -{ - /* We support 4 mirror groups, one destination port per group */ - int group; - struct rtl838x_switch_priv *priv = ds->priv; - int ctrl_reg, dpm_reg, spm_reg; - - pr_debug("In %s\n", __func__); - - for (group = 0; group < 4; group++) { - if (priv->mirror_group_ports[group] == mirror->to_local_port) - break; - } - if (group >= 4) { - for (group = 0; group < 4; group++) { - if (priv->mirror_group_ports[group] < 0) - break; - } - } - - if (group >= 4) - return -ENOSPC; - - ctrl_reg = priv->r->mir_ctrl + group * 4; - dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width; - spm_reg = priv->r->mir_spm + group * 4 * priv->port_width; - - pr_debug("Using group %d\n", group); - mutex_lock(&priv->reg_mutex); - - if (priv->family_id == RTL8380_FAMILY_ID) { - /* Enable mirroring to port across VLANs (bit 11) */ - sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg); - } else { - /* Enable mirroring to destination port */ - sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg); - } - - if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) { - mutex_unlock(&priv->reg_mutex); - return -EEXIST; - } - if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) { - mutex_unlock(&priv->reg_mutex); - return -EEXIST; - } - - if (ingress) - priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg); - else - priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg); - - priv->mirror_group_ports[group] = mirror->to_local_port; - mutex_unlock(&priv->reg_mutex); - return 0; -} - -static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port, - struct dsa_mall_mirror_tc_entry *mirror) -{ - int group = 0; - struct rtl838x_switch_priv *priv = ds->priv; - int ctrl_reg, dpm_reg, spm_reg; - - pr_debug("In %s\n", __func__); - for (group = 0; group < 4; group++) { - if (priv->mirror_group_ports[group] == mirror->to_local_port) - break; - } - if (group >= 4) - return; - - ctrl_reg = priv->r->mir_ctrl + group * 4; - dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width; - spm_reg = priv->r->mir_spm + group * 4 * priv->port_width; - - mutex_lock(&priv->reg_mutex); - if (mirror->ingress) { - /* Ingress, clear source port matrix */ - priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg); - } else { - /* Egress, clear destination port matrix */ - priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg); - } - - if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) { - priv->mirror_group_ports[group] = -1; - sw_w32(0, ctrl_reg); - } - - mutex_unlock(&priv->reg_mutex); -} - -static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack) -{ - struct rtl838x_switch_priv *priv = ds->priv; - unsigned long features = 0; - pr_debug("%s: %d %lX\n", __func__, port, flags); - if (priv->r->enable_learning) - features |= BR_LEARNING; - if (priv->r->enable_flood) - features |= BR_FLOOD; - if (priv->r->enable_mcast_flood) - features |= BR_MCAST_FLOOD; - if (priv->r->enable_bcast_flood) - features |= BR_BCAST_FLOOD; - if (flags & ~(features)) - return -EINVAL; - - return 0; -} - -static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - pr_debug("%s: %d %lX\n", __func__, port, flags); - if (priv->r->enable_learning) - priv->r->enable_learning(port, !!(flags & BR_LEARNING)); - - if (priv->r->enable_flood) - priv->r->enable_flood(port, !!(flags & BR_FLOOD)); - - if (priv->r->enable_mcast_flood) - priv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD)); - - if (priv->r->enable_bcast_flood) - priv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD)); - - return 0; -} - -static bool rtl83xx_lag_can_offload(struct dsa_switch *ds, - struct net_device *lag, - struct netdev_lag_upper_info *info) -{ - int id; - - id = dsa_lag_id(ds->dst, lag); - if (id < 0 || id >= ds->num_lag_ids) - return false; - - if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { - return false; - } - if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23) - return false; - - return true; -} - -static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port) -{ - struct rtl838x_switch_priv *priv = ds->priv; - - pr_debug("%s: %d\n", __func__, port); - // Nothing to be done... - - return 0; -} - -static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port, - struct net_device *lag, - struct netdev_lag_upper_info *info) -{ - struct rtl838x_switch_priv *priv = ds->priv; - int i, err = 0; - - if (!rtl83xx_lag_can_offload(ds, lag, info)) - return -EOPNOTSUPP; - - mutex_lock(&priv->reg_mutex); - - for (i = 0; i < priv->n_lags; i++) { - if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag)) - break; - } - if (port >= priv->cpu_port) { - err = -EINVAL; - goto out; - } - pr_info("port_lag_join: group %d, port %d\n",i, port); - if (!priv->lag_devs[i]) - priv->lag_devs[i] = lag; - - if (priv->lag_primary[i]==-1) { - priv->lag_primary[i]=port; - } else - priv->is_lagmember[port] = 1; - - priv->lagmembers |= (1ULL << port); - - pr_debug("lag_members = %llX\n", priv->lagmembers); - err = rtl83xx_lag_add(priv->ds, i, port, info); - if (err) { - err = -EINVAL; - goto out; - } - -out: - mutex_unlock(&priv->reg_mutex); - return err; - -} - -static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port, - struct net_device *lag) -{ - int i, group = -1, err; - struct rtl838x_switch_priv *priv = ds->priv; - - mutex_lock(&priv->reg_mutex); - for (i=0;in_lags;i++) { - if (priv->lags_port_members[i] & BIT_ULL(port)) { - group = i; - break; - } - } - - if (group == -1) { - pr_info("port_lag_leave: port %d is not a member\n", port); - err = -EINVAL; - goto out; - } - - if (port >= priv->cpu_port) { - err = -EINVAL; - goto out; - } - pr_info("port_lag_del: group %d, port %d\n",group, port); - priv->lagmembers &=~ (1ULL << port); - priv->lag_primary[i] = -1; - priv->is_lagmember[port] = 0; - pr_debug("lag_members = %llX\n", priv->lagmembers); - err = rtl83xx_lag_del(priv->ds, group, port); - if (err) { - err = -EINVAL; - goto out; - } - if (!priv->lags_port_members[i]) - priv->lag_devs[i] = NULL; - -out: - mutex_unlock(&priv->reg_mutex); - return 0; -} - -int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg) -{ - u32 val; - u32 offset = 0; - struct rtl838x_switch_priv *priv = ds->priv; - - if (phy_addr >= 24 && phy_addr <= 27 - && priv->ports[24].phy == PHY_RTL838X_SDS) { - if (phy_addr == 26) - offset = 0x100; - val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff; - return val; - } - - read_phy(phy_addr, 0, phy_reg, &val); - return val; -} - -int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val) -{ - u32 offset = 0; - struct rtl838x_switch_priv *priv = ds->priv; - - if (phy_addr >= 24 && phy_addr <= 27 - && priv->ports[24].phy == PHY_RTL838X_SDS) { - if (phy_addr == 26) - offset = 0x100; - sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)); - return 0; - } - return write_phy(phy_addr, 0, phy_reg, val); -} - -const struct dsa_switch_ops rtl83xx_switch_ops = { - .get_tag_protocol = rtl83xx_get_tag_protocol, - .setup = rtl83xx_setup, - - .phy_read = dsa_phy_read, - .phy_write = dsa_phy_write, - - .phylink_validate = rtl83xx_phylink_validate, - .phylink_mac_link_state = rtl83xx_phylink_mac_link_state, - .phylink_mac_config = rtl83xx_phylink_mac_config, - .phylink_mac_link_down = rtl83xx_phylink_mac_link_down, - .phylink_mac_link_up = rtl83xx_phylink_mac_link_up, - - .get_strings = rtl83xx_get_strings, - .get_ethtool_stats = rtl83xx_get_ethtool_stats, - .get_sset_count = rtl83xx_get_sset_count, - - .port_enable = rtl83xx_port_enable, - .port_disable = rtl83xx_port_disable, - - .get_mac_eee = rtl83xx_get_mac_eee, - .set_mac_eee = rtl83xx_set_mac_eee, - - .set_ageing_time = rtl83xx_set_ageing_time, - .port_bridge_join = rtl83xx_port_bridge_join, - .port_bridge_leave = rtl83xx_port_bridge_leave, - .port_stp_state_set = rtl83xx_port_stp_state_set, - .port_fast_age = rtl83xx_fast_age, - - .port_vlan_filtering = rtl83xx_vlan_filtering, - .port_vlan_prepare = rtl83xx_vlan_prepare, - .port_vlan_add = rtl83xx_vlan_add, - .port_vlan_del = rtl83xx_vlan_del, - - .port_fdb_add = rtl83xx_port_fdb_add, - .port_fdb_del = rtl83xx_port_fdb_del, - .port_fdb_dump = rtl83xx_port_fdb_dump, - - .port_mdb_prepare = rtl83xx_port_mdb_prepare, - .port_mdb_add = rtl83xx_port_mdb_add, - .port_mdb_del = rtl83xx_port_mdb_del, - - .port_mirror_add = rtl83xx_port_mirror_add, - .port_mirror_del = rtl83xx_port_mirror_del, - - .port_lag_change = rtl83xx_port_lag_change, - .port_lag_join = rtl83xx_port_lag_join, - .port_lag_leave = rtl83xx_port_lag_leave, - - .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags, - .port_bridge_flags = rtl83xx_port_bridge_flags, -}; - -const struct dsa_switch_ops rtl930x_switch_ops = { - .get_tag_protocol = rtl83xx_get_tag_protocol, - .setup = rtl93xx_setup, - - .phy_read = dsa_phy_read, - .phy_write = dsa_phy_write, - - .phylink_validate = rtl93xx_phylink_validate, - .phylink_mac_link_state = rtl93xx_phylink_mac_link_state, - .phylink_mac_config = rtl93xx_phylink_mac_config, - .phylink_mac_link_down = rtl93xx_phylink_mac_link_down, - .phylink_mac_link_up = rtl93xx_phylink_mac_link_up, - - .get_strings = rtl83xx_get_strings, - .get_ethtool_stats = rtl83xx_get_ethtool_stats, - .get_sset_count = rtl83xx_get_sset_count, - - .port_enable = rtl83xx_port_enable, - .port_disable = rtl83xx_port_disable, - - .get_mac_eee = rtl93xx_get_mac_eee, - .set_mac_eee = rtl83xx_set_mac_eee, - - .set_ageing_time = rtl83xx_set_ageing_time, - .port_bridge_join = rtl83xx_port_bridge_join, - .port_bridge_leave = rtl83xx_port_bridge_leave, - .port_stp_state_set = rtl83xx_port_stp_state_set, - .port_fast_age = rtl930x_fast_age, - - .port_vlan_filtering = rtl83xx_vlan_filtering, - .port_vlan_prepare = rtl83xx_vlan_prepare, - .port_vlan_add = rtl83xx_vlan_add, - .port_vlan_del = rtl83xx_vlan_del, - - .port_fdb_add = rtl83xx_port_fdb_add, - .port_fdb_del = rtl83xx_port_fdb_del, - .port_fdb_dump = rtl83xx_port_fdb_dump, - - .port_mdb_prepare = rtl83xx_port_mdb_prepare, - .port_mdb_add = rtl83xx_port_mdb_add, - .port_mdb_del = rtl83xx_port_mdb_del, - - .port_lag_change = rtl83xx_port_lag_change, - .port_lag_join = rtl83xx_port_lag_join, - .port_lag_leave = rtl83xx_port_lag_leave, - - .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags, - .port_bridge_flags = rtl83xx_port_bridge_flags, -}; diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/qos.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/qos.c deleted file mode 100644 index 2fc8d37f3e..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/qos.c +++ /dev/null @@ -1,576 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include - -#include -#include "rtl83xx.h" - -static struct rtl838x_switch_priv *switch_priv; -extern struct rtl83xx_soc_info soc_info; - -enum scheduler_type { - WEIGHTED_FAIR_QUEUE = 0, - WEIGHTED_ROUND_ROBIN, -}; - -int max_available_queue[] = {0, 1, 2, 3, 4, 5, 6, 7}; -int default_queue_weights[] = {1, 1, 1, 1, 1, 1, 1, 1}; -int dot1p_priority_remapping[] = {0, 1, 2, 3, 4, 5, 6, 7}; - -static void rtl839x_read_scheduling_table(int port) -{ - u32 cmd = 1 << 9 /* Execute cmd */ - | 0 << 8 /* Read */ - | 0 << 6 /* Table type 0b00 */ - | (port & 0x3f); - rtl839x_exec_tbl2_cmd(cmd); -} - -static void rtl839x_write_scheduling_table(int port) -{ - u32 cmd = 1 << 9 /* Execute cmd */ - | 1 << 8 /* Write */ - | 0 << 6 /* Table type 0b00 */ - | (port & 0x3f); - rtl839x_exec_tbl2_cmd(cmd); -} - -static void rtl839x_read_out_q_table(int port) -{ - u32 cmd = 1 << 9 /* Execute cmd */ - | 0 << 8 /* Read */ - | 2 << 6 /* Table type 0b10 */ - | (port & 0x3f); - rtl839x_exec_tbl2_cmd(cmd); -} - -static void rtl838x_storm_enable(struct rtl838x_switch_priv *priv, int port, bool enable) -{ - // Enable Storm control for that port for UC, MC, and BC - if (enable) - sw_w32(0x7, RTL838X_STORM_CTRL_LB_CTRL(port)); - else - sw_w32(0x0, RTL838X_STORM_CTRL_LB_CTRL(port)); -} - -u32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port) -{ - u32 rate; - - if (port > priv->cpu_port) - return 0; - rate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)) & 0x3fff; - return rate; -} - -/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */ -int rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate) -{ - u32 old_rate; - - if (port > priv->cpu_port) - return -1; - - old_rate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)); - sw_w32(rate, RTL838X_SCHED_P_EGR_RATE_CTRL(port)); - - return old_rate; -} - -/* Set the rate limit for a particular queue in Bits/s - * units of the rate is 16Kbps - */ -void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port, - int queue, u32 rate) -{ - if (port > priv->cpu_port) - return; - if (queue > 7) - return; - sw_w32(rate, RTL838X_SCHED_Q_EGR_RATE_CTRL(port, queue)); -} - -static void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv) -{ - int i; - - pr_info("Enabling Storm control\n"); - // TICK_PERIOD_PPS - if (priv->id == 0x8380) - sw_w32_mask(0x3ff << 20, 434 << 20, RTL838X_SCHED_LB_TICK_TKN_CTRL_0); - - // Set burst rate - sw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); // UC - sw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); // MC and BC - - // Set burst Packets per Second to 32 - sw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); // UC - sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); // MC and BC - - // Include IFG in storm control, rate based on bytes/s (0 = packets) - sw_w32_mask(0, 1 << 6 | 1 << 5, RTL838X_STORM_CTRL); - // Bandwidth control includes preamble and IFG (10 Bytes) - sw_w32_mask(0, 1, RTL838X_SCHED_CTRL); - - // On SoCs except RTL8382M, set burst size of port egress - if (priv->id != 0x8382) - sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR); - - /* Enable storm control on all ports with a PHY and limit rates, - * for UC and MC for both known and unknown addresses */ - for (i = 0; i < priv->cpu_port; i++) { - if (priv->ports[i].phy) { - sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i)); - sw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i)); - sw_w32(0x8000, RTL838X_STORM_CTRL_PORT_BC(i)); - rtl838x_storm_enable(priv, i, true); - } - } - - // Attack prevention, enable all attack prevention measures - //sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL); - /* Attack prevention, drop (bit = 0) problematic packets on all ports. - * Setting bit = 1 means: trap to CPU - */ - //sw_w32(0, RTL838X_ATK_PRVNT_ACT); - // Enable attack prevention on all ports - //sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN); -} - -/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */ -u32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port) -{ - u32 rate; - - pr_debug("%s: Getting egress rate on port %d to %d\n", __func__, port, rate); - if (port >= priv->cpu_port) - return 0; - - mutex_lock(&priv->reg_mutex); - - rtl839x_read_scheduling_table(port); - - rate = sw_r32(RTL839X_TBL_ACCESS_DATA_2(7)); - rate <<= 12; - rate |= sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)) >> 20; - - mutex_unlock(&priv->reg_mutex); - - return rate; -} - -/* Sets the rate limit, 10MBit/s is equal to a rate value of 625, returns previous rate */ -int rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate) -{ - u32 old_rate; - - pr_debug("%s: Setting egress rate on port %d to %d\n", __func__, port, rate); - if (port >= priv->cpu_port) - return -1; - - mutex_lock(&priv->reg_mutex); - - rtl839x_read_scheduling_table(port); - - old_rate = sw_r32(RTL839X_TBL_ACCESS_DATA_2(7)) & 0xff; - old_rate <<= 12; - old_rate |= sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)) >> 20; - sw_w32_mask(0xff, (rate >> 12) & 0xff, RTL839X_TBL_ACCESS_DATA_2(7)); - sw_w32_mask(0xfff << 20, rate << 20, RTL839X_TBL_ACCESS_DATA_2(8)); - - rtl839x_write_scheduling_table(port); - - mutex_unlock(&priv->reg_mutex); - - return old_rate; -} - -/* Set the rate limit for a particular queue in Bits/s - * units of the rate is 16Kbps - */ -void rtl839x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port, - int queue, u32 rate) -{ - int lsb = 128 + queue * 20; - int low_byte = 8 - (lsb >> 5); - int start_bit = lsb - (low_byte << 5); - u32 high_mask = 0xfffff >> (32 - start_bit); - - pr_debug("%s: Setting egress rate on port %d, queue %d to %d\n", - __func__, port, queue, rate); - if (port >= priv->cpu_port) - return; - if (queue > 7) - return; - - mutex_lock(&priv->reg_mutex); - - rtl839x_read_scheduling_table(port); - - sw_w32_mask(0xfffff << start_bit, (rate & 0xfffff) << start_bit, - RTL839X_TBL_ACCESS_DATA_2(low_byte)); - if (high_mask) - sw_w32_mask(high_mask, (rate & 0xfffff) >> (32- start_bit), - RTL839X_TBL_ACCESS_DATA_2(low_byte - 1)); - - rtl839x_write_scheduling_table(port); - - mutex_unlock(&priv->reg_mutex); -} - -static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv) -{ - int p, q; - - pr_info("%s: enabling rate control\n", __func__); - /* Tick length and token size settings for SoC with 250MHz, - * RTL8350 family would use 50MHz - */ - // Set the special tick period - sw_w32(976563, RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL); - // Ingress tick period and token length 10G - sw_w32(18 << 11 | 151, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0); - // Ingress tick period and token length 1G - sw_w32(245 << 11 | 129, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1); - // Egress tick period 10G, bytes/token 10G and tick period 1G, bytes/token 1G - sw_w32(18 << 24 | 151 << 16 | 185 << 8 | 97, RTL839X_SCHED_LB_TICK_TKN_CTRL); - // Set the tick period of the CPU and the Token Len - sw_w32(3815 << 8 | 1, RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL); - - // Set the Weighted Fair Queueing burst size - sw_w32_mask(0xffff, 4500, RTL839X_SCHED_LB_THR); - - // Storm-rate calculation is based on bytes/sec (bit 5), include IFG (bit 6) - sw_w32_mask(0, 1 << 5 | 1 << 6, RTL839X_STORM_CTRL); - - /* Based on the rate control mode being bytes/s - * set tick period and token length for 10G - */ - sw_w32(18 << 10 | 151, RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0); - /* and for 1G ports */ - sw_w32(246 << 10 | 129, RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1); - - /* Set default burst rates on all ports (the same for 1G / 10G) with a PHY - * for UC, MC and BC - * For 1G port, the minimum burst rate is 1700, maximum 65535, - * For 10G ports it is 2650 and 1048575 respectively */ - for (p = 0; p < priv->cpu_port; p++) { - if (priv->ports[p].phy && !priv->ports[p].is10G) { - sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_UC_1(p)); - sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_MC_1(p)); - sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_BC_1(p)); - } - } - - /* Setup ingress/egress per-port rate control */ - for (p = 0; p < priv->cpu_port; p++) { - if (!priv->ports[p].phy) - continue; - - if (priv->ports[p].is10G) - rtl839x_set_egress_rate(priv, p, 625000); // 10GB/s - else - rtl839x_set_egress_rate(priv, p, 62500); // 1GB/s - - // Setup queues: all RTL83XX SoCs have 8 queues, maximum rate - for (q = 0; q < 8; q++) - rtl839x_egress_rate_queue_limit(priv, p, q, 0xfffff); - - if (priv->ports[p].is10G) { - // Set high threshold to maximum - sw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p)); - } else { - // Set high threshold to maximum - sw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_1(p)); - } - } - - // Set global ingress low watermark rate - sw_w32(65532, RTL839X_IGR_BWCTRL_CTRL_LB_THR); -} - - - -void rtl838x_setup_prio2queue_matrix(int *min_queues) -{ - int i; - u32 v; - - pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL838X_QM_INTPRI2QID_CTRL)); - for (i = 0; i < MAX_PRIOS; i++) - v |= i << (min_queues[i] * 3); - sw_w32(v, RTL838X_QM_INTPRI2QID_CTRL); -} - -void rtl839x_setup_prio2queue_matrix(int *min_queues) -{ - int i, q; - - pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL839X_QM_INTPRI2QID_CTRL(0))); - for (i = 0; i < MAX_PRIOS; i++) { - q = min_queues[i]; - sw_w32(i << (q * 3), RTL839X_QM_INTPRI2QID_CTRL(q)); - } -} - -/* Sets the CPU queue depending on the internal priority of a packet */ -void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues) -{ - int reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP - : RTL839X_QM_PKT2CPU_INTPRI_MAP; - int i; - u32 v; - - pr_info("QM_PKT2CPU_INTPRI_MAP: %08x\n", sw_r32(reg)); - for (i = 0; i < MAX_PRIOS; i++) - v |= max_queues[i] << (i * 3); - sw_w32(v, reg); -} - -void rtl83xx_setup_default_prio2queue(void) -{ - if (soc_info.family == RTL8380_FAMILY_ID) { - rtl838x_setup_prio2queue_matrix(max_available_queue); - } else { - rtl839x_setup_prio2queue_matrix(max_available_queue); - } - rtl83xx_setup_prio2queue_cpu_matrix(max_available_queue); -} - -/* Sets the output queue assigned to a port, the port can be the CPU-port */ -void rtl839x_set_egress_queue(int port, int queue) -{ - sw_w32(queue << ((port % 10) *3), RTL839X_QM_PORT_QNUM(port)); -} - -/* Sets the priority assigned of an ingress port, the port can be the CPU-port */ -void rtl83xx_set_ingress_priority(int port, int priority) -{ - if (soc_info.family == RTL8380_FAMILY_ID) - sw_w32(priority << ((port % 10) *3), RTL838X_PRI_SEL_PORT_PRI(port)); - else - sw_w32(priority << ((port % 10) *3), RTL839X_PRI_SEL_PORT_PRI(port)); - -} - -int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port) -{ - u32 v; - - mutex_lock(&priv->reg_mutex); - - rtl839x_read_scheduling_table(port); - v = sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)); - - mutex_unlock(&priv->reg_mutex); - - if (v & BIT(19)) - return WEIGHTED_ROUND_ROBIN; - return WEIGHTED_FAIR_QUEUE; -} - -void rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port, - enum scheduler_type sched) -{ - enum scheduler_type t = rtl839x_get_scheduling_algorithm(priv, port); - u32 v, oam_state, oam_port_state; - u32 count; - int i, egress_rate; - - mutex_lock(&priv->reg_mutex); - /* Check whether we need to empty the egress queue of that port due to Errata E0014503 */ - if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) { - // Read Operations, Adminstatrion and Management control register - oam_state = sw_r32(RTL839X_OAM_CTRL); - - // Get current OAM state - oam_port_state = sw_r32(RTL839X_OAM_PORT_ACT_CTRL(port)); - - // Disable OAM to block traffice - v = sw_r32(RTL839X_OAM_CTRL); - sw_w32_mask(0, 1, RTL839X_OAM_CTRL); - v = sw_r32(RTL839X_OAM_CTRL); - - // Set to trap action OAM forward (bits 1, 2) and OAM Mux Action Drop (bit 0) - sw_w32(0x2, RTL839X_OAM_PORT_ACT_CTRL(port)); - - // Set port egress rate to unlimited - egress_rate = rtl839x_set_egress_rate(priv, port, 0xFFFFF); - - // Wait until the egress used page count of that port is 0 - i = 0; - do { - usleep_range(100, 200); - rtl839x_read_out_q_table(port); - count = sw_r32(RTL839X_TBL_ACCESS_DATA_2(6)); - count >>= 20; - i++; - } while (i < 3500 && count > 0); - } - - // Actually set the scheduling algorithm - rtl839x_read_scheduling_table(port); - sw_w32_mask(BIT(19), sched ? BIT(19) : 0, RTL839X_TBL_ACCESS_DATA_2(8)); - rtl839x_write_scheduling_table(port); - - if (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) { - // Restore OAM state to control register - sw_w32(oam_state, RTL839X_OAM_CTRL); - - // Restore trap action state - sw_w32(oam_port_state, RTL839X_OAM_PORT_ACT_CTRL(port)); - - // Restore port egress rate - rtl839x_set_egress_rate(priv, port, egress_rate); - } - - mutex_unlock(&priv->reg_mutex); -} - -void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int port, - int *queue_weights) -{ - int i, lsb, low_byte, start_bit, high_mask; - - mutex_lock(&priv->reg_mutex); - - rtl839x_read_scheduling_table(port); - - for (i = 0; i < 8; i++) { - lsb = 48 + i * 8; - low_byte = 8 - (lsb >> 5); - start_bit = lsb - (low_byte << 5); - high_mask = 0x3ff >> (32 - start_bit); - sw_w32_mask(0x3ff << start_bit, (queue_weights[i] & 0x3ff) << start_bit, - RTL839X_TBL_ACCESS_DATA_2(low_byte)); - if (high_mask) - sw_w32_mask(high_mask, (queue_weights[i] & 0x3ff) >> (32- start_bit), - RTL839X_TBL_ACCESS_DATA_2(low_byte - 1)); - } - - rtl839x_write_scheduling_table(port); - mutex_unlock(&priv->reg_mutex); -} - -void rtl838x_config_qos(void) -{ - int i, p; - u32 v; - - pr_info("Setting up RTL838X QoS\n"); - pr_info("RTL838X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL838X_PRI_SEL_TBL_CTRL(0))); - rtl83xx_setup_default_prio2queue(); - - // Enable inner (bit 12) and outer (bit 13) priority remapping from DSCP - sw_w32_mask(0, BIT(12) | BIT(13), RTL838X_PRI_DSCP_INVLD_CTRL0); - - /* Set default weight for calculating internal priority, in prio selection group 0 - * Port based (prio 3), Port outer-tag (4), DSCP (5), Inner Tag (6), Outer Tag (7) - */ - v = 3 | (4 << 3) | (5 << 6) | (6 << 9) | (7 << 12); - sw_w32(v, RTL838X_PRI_SEL_TBL_CTRL(0)); - - // Set the inner and outer priority one-to-one to re-marked outer dot1p priority - v = 0; - for (p = 0; p < 8; p++) - v |= p << (3 * p); - sw_w32(v, RTL838X_RMK_OPRI_CTRL); - sw_w32(v, RTL838X_RMK_IPRI_CTRL); - - v = 0; - for (p = 0; p < 8; p++) - v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3); - sw_w32(v, RTL838X_PRI_SEL_IPRI_REMAP); - - // On all ports set scheduler type to WFQ - for (i = 0; i <= soc_info.cpu_port; i++) - sw_w32(0, RTL838X_SCHED_P_TYPE_CTRL(i)); - - // Enable egress scheduler for CPU-Port - sw_w32_mask(0, BIT(8), RTL838X_SCHED_LB_CTRL(soc_info.cpu_port)); - - // Enable egress drop allways on - sw_w32_mask(0, BIT(11), RTL838X_FC_P_EGR_DROP_CTRL(soc_info.cpu_port)); - - // Give special trap frames priority 7 (BPDUs) and routing exceptions: - sw_w32_mask(0, 7 << 3 | 7, RTL838X_QM_PKT2CPU_INTPRI_2); - // Give RMA frames priority 7: - sw_w32_mask(0, 7, RTL838X_QM_PKT2CPU_INTPRI_1); -} - -void rtl839x_config_qos(void) -{ - int port, p, q; - u32 v; - struct rtl838x_switch_priv *priv = switch_priv; - - pr_info("Setting up RTL839X QoS\n"); - pr_info("RTL839X_PRI_SEL_TBL_CTRL(i): %08x\n", sw_r32(RTL839X_PRI_SEL_TBL_CTRL(0))); - rtl83xx_setup_default_prio2queue(); - - for (port = 0; port < soc_info.cpu_port; port++) - sw_w32(7, RTL839X_QM_PORT_QNUM(port)); - - // CPU-port gets queue number 7 - sw_w32(7, RTL839X_QM_PORT_QNUM(soc_info.cpu_port)); - - for (port = 0; port <= soc_info.cpu_port; port++) { - rtl83xx_set_ingress_priority(port, 0); - rtl839x_set_scheduling_algorithm(priv, port, WEIGHTED_FAIR_QUEUE); - rtl839x_set_scheduling_queue_weights(priv, port, default_queue_weights); - // Do re-marking based on outer tag - sw_w32_mask(0, BIT(port % 32), RTL839X_RMK_PORT_DEI_TAG_CTRL(port)); - } - - // Remap dot1p priorities to internal priority, for this the outer tag needs be re-marked - v = 0; - for (p = 0; p < 8; p++) - v |= (dot1p_priority_remapping[p] & 0x7) << (p * 3); - sw_w32(v, RTL839X_PRI_SEL_IPRI_REMAP); - - /* Configure Drop Precedence for Drop Eligible Indicator (DEI) - * Index 0: 0 - * Index 1: 2 - * Each indicator is 2 bits long - */ - sw_w32(2 << 2, RTL839X_PRI_SEL_DEI2DP_REMAP); - - // Re-mark DEI: 4 bit-fields of 2 bits each, field 0 is bits 0-1, ... - sw_w32((0x1 << 2) | (0x1 << 4), RTL839X_RMK_DEI_CTRL); - - /* Set Congestion avoidance drop probability to 0 for drop precedences 0-2 (bits 24-31) - * low threshold (bits 0-11) to 4095 and high threshold (bits 12-23) to 4095 - * Weighted Random Early Detection (WRED) is used - */ - sw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(0)); - sw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(1)); - sw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(2)); - - /* Set queue-based congestion avoidance properties, register fields are as - * for forward RTL839X_WRED_PORT_THR_CTRL - */ - for (q = 0; q < 8; q++) { - sw_w32(255 << 24 | 78 << 12 | 68, RTL839X_WRED_QUEUE_THR_CTRL(q, 0)); - sw_w32(255 << 24 | 74 << 12 | 64, RTL839X_WRED_QUEUE_THR_CTRL(q, 0)); - sw_w32(255 << 24 | 70 << 12 | 60, RTL839X_WRED_QUEUE_THR_CTRL(q, 0)); - } -} - -void __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv) -{ - switch_priv = priv; - - pr_info("In %s\n", __func__); - - if (priv->family_id == RTL8380_FAMILY_ID) - return rtl838x_config_qos(); - else if (priv->family_id == RTL8390_FAMILY_ID) - return rtl839x_config_qos(); - - if (priv->family_id == RTL8380_FAMILY_ID) - rtl838x_rate_control_init(priv); - else if (priv->family_id == RTL8390_FAMILY_ID) - rtl839x_rate_control_init(priv); - -} diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c deleted file mode 100644 index 74ad031276..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c +++ /dev/null @@ -1,2064 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include - -#include "rtl83xx.h" - -#define RTL838X_VLAN_PORT_TAG_STS_UNTAG 0x0 -#define RTL838X_VLAN_PORT_TAG_STS_TAGGED 0x1 -#define RTL838X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2 - -#define RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE 0xA530 -/* port 0-28 */ -#define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) \ - RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2) - -#define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(11,10) -#define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(9,8) -#define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(7,6) -#define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(5,4) -#define RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(3,2) -#define RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(1,0) - -extern struct mutex smi_lock; - -// see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c -/* Definition of the RTL838X-specific template field IDs as used in the PIE */ -enum template_field_id { - TEMPLATE_FIELD_SPMMASK = 0, - TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15 - TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-28 - TEMPLATE_FIELD_RANGE_CHK = 3, - TEMPLATE_FIELD_DMAC0 = 4, // Destination MAC [15:0] - TEMPLATE_FIELD_DMAC1 = 5, // Destination MAC [31:16] - TEMPLATE_FIELD_DMAC2 = 6, // Destination MAC [47:32] - TEMPLATE_FIELD_SMAC0 = 7, // Source MAC [15:0] - TEMPLATE_FIELD_SMAC1 = 8, // Source MAC [31:16] - TEMPLATE_FIELD_SMAC2 = 9, // Source MAC [47:32] - TEMPLATE_FIELD_ETHERTYPE = 10, // Ethernet typ - TEMPLATE_FIELD_OTAG = 11, // Outer VLAN tag - TEMPLATE_FIELD_ITAG = 12, // Inner VLAN tag - TEMPLATE_FIELD_SIP0 = 13, // IPv4 or IPv6 source IP[15:0] or ARP/RARP - // source protocol address in header - TEMPLATE_FIELD_SIP1 = 14, // IPv4 or IPv6 source IP[31:16] or ARP/RARP - TEMPLATE_FIELD_DIP0 = 15, // IPv4 or IPv6 destination IP[15:0] - TEMPLATE_FIELD_DIP1 = 16, // IPv4 or IPv6 destination IP[31:16] - TEMPLATE_FIELD_IP_TOS_PROTO = 17, // IPv4 TOS/IPv6 traffic class and - // IPv4 proto/IPv6 next header fields - TEMPLATE_FIELD_L34_HEADER = 18, // packet with extra tag and IPv6 with auth, dest, - // frag, route, hop-by-hop option header, - // IGMP type, TCP flag - TEMPLATE_FIELD_L4_SPORT = 19, // TCP/UDP source port - TEMPLATE_FIELD_L4_DPORT = 20, // TCP/UDP destination port - TEMPLATE_FIELD_ICMP_IGMP = 21, - TEMPLATE_FIELD_IP_RANGE = 22, - TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, // Field selector mask - TEMPLATE_FIELD_FIELD_SELECTOR_0 = 24, - TEMPLATE_FIELD_FIELD_SELECTOR_1 = 25, - TEMPLATE_FIELD_FIELD_SELECTOR_2 = 26, - TEMPLATE_FIELD_FIELD_SELECTOR_3 = 27, - TEMPLATE_FIELD_SIP2 = 28, // IPv6 source IP[47:32] - TEMPLATE_FIELD_SIP3 = 29, // IPv6 source IP[63:48] - TEMPLATE_FIELD_SIP4 = 30, // IPv6 source IP[79:64] - TEMPLATE_FIELD_SIP5 = 31, // IPv6 source IP[95:80] - TEMPLATE_FIELD_SIP6 = 32, // IPv6 source IP[111:96] - TEMPLATE_FIELD_SIP7 = 33, // IPv6 source IP[127:112] - TEMPLATE_FIELD_DIP2 = 34, // IPv6 destination IP[47:32] - TEMPLATE_FIELD_DIP3 = 35, // IPv6 destination IP[63:48] - TEMPLATE_FIELD_DIP4 = 36, // IPv6 destination IP[79:64] - TEMPLATE_FIELD_DIP5 = 37, // IPv6 destination IP[95:80] - TEMPLATE_FIELD_DIP6 = 38, // IPv6 destination IP[111:96] - TEMPLATE_FIELD_DIP7 = 39, // IPv6 destination IP[127:112] - TEMPLATE_FIELD_FWD_VID = 40, // Forwarding VLAN-ID - TEMPLATE_FIELD_FLOW_LABEL = 41, -}; - -/* - * The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to - * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet - * Inspection Engine's buffer. The following defines the field contents for each of the fixed - * templates. Additionally, 3 user-definable templates can be set up via the definitions - * in RTL838X_ACL_TMPLTE_CTRL control registers. - * TODO: See all src/app/diag_v2/src/diag_pie.c - */ -#define N_FIXED_TEMPLATES 5 -static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = -{ - { - TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG, - TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2, - TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, - TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK - }, { - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, - TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT, - TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG, - TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1 - }, { - TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, - TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO, - TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0, - TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1 - }, { - TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2, - TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5, - TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT, - TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO - }, { - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2, - TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5, - TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_ITAG, - TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1 - }, -}; - -void rtl838x_print_matrix(void) -{ - unsigned volatile int *ptr8; - int i; - - ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0); - for (i = 0; i < 28; i += 8) - pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n", - ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3], - ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]); - pr_debug("CPU_PORT> %8x\n", ptr8[28]); -} - -static inline int rtl838x_port_iso_ctrl(int p) -{ - return RTL838X_PORT_ISO_CTRL(p); -} - -static inline void rtl838x_exec_tbl0_cmd(u32 cmd) -{ - sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0); - do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15)); -} - -static inline void rtl838x_exec_tbl1_cmd(u32 cmd) -{ - sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1); - do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15)); -} - -static inline int rtl838x_tbl_access_data_0(int i) -{ - return RTL838X_TBL_ACCESS_DATA_0(i); -} - -static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) -{ - u32 v; - // Read VLAN table (0) via register 0 - struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0); - - rtl_table_read(r, vlan); - info->tagged_ports = sw_r32(rtl_table_data(r, 0)); - v = sw_r32(rtl_table_data(r, 1)); - pr_debug("VLAN_READ %d: %016llx %08x\n", vlan, info->tagged_ports, v); - rtl_table_release(r); - - info->profile_id = v & 0x7; - info->hash_mc_fid = !!(v & 0x8); - info->hash_uc_fid = !!(v & 0x10); - info->fid = (v >> 5) & 0x3f; - - // Read UNTAG table (0) via table register 1 - r = rtl_table_get(RTL8380_TBL_1, 0); - rtl_table_read(r, vlan); - info->untagged_ports = sw_r32(rtl_table_data(r, 0)); - rtl_table_release(r); -} - -static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) -{ - u32 v; - // Access VLAN table (0) via register 0 - struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0); - - sw_w32(info->tagged_ports, rtl_table_data(r, 0)); - - v = info->profile_id; - v |= info->hash_mc_fid ? 0x8 : 0; - v |= info->hash_uc_fid ? 0x10 : 0; - v |= ((u32)info->fid) << 5; - sw_w32(v, rtl_table_data(r, 1)); - - rtl_table_write(r, vlan); - rtl_table_release(r); -} - -static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask) -{ - // Access UNTAG table (0) via register 1 - struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0); - - sw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0)); - rtl_table_write(r, vlan); - rtl_table_release(r); -} - -/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer - */ -static void rtl838x_vlan_fwd_on_inner(int port, bool is_set) -{ - if (is_set) - sw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD); - else - sw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD); -} - -static u64 rtl838x_l2_hash_seed(u64 mac, u32 vid) -{ - return mac << 12 | vid; -} - -/* - * Applies the same hash algorithm as the one used currently by the ASIC to the seed - * and returns a key into the L2 hash table - */ -static u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) -{ - u32 h1, h2, h3, h; - - if (sw_r32(priv->r->l2_ctrl_0) & 1) { - h1 = (seed >> 11) & 0x7ff; - h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); - - h2 = (seed >> 33) & 0x7ff; - h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f); - - h3 = (seed >> 44) & 0x7ff; - h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf); - - h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff); - h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff); - } else { - h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) - ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) - ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff); - } - - return h; -} - -static inline int rtl838x_mac_force_mode_ctrl(int p) -{ - return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2); -} - -static inline int rtl838x_mac_port_ctrl(int p) -{ - return RTL838X_MAC_PORT_CTRL(p); -} - -static inline int rtl838x_l2_port_new_salrn(int p) -{ - return RTL838X_L2_PORT_NEW_SALRN(p); -} - -static inline int rtl838x_l2_port_new_sa_fwd(int p) -{ - return RTL838X_L2_PORT_NEW_SA_FWD(p); -} - -static inline int rtl838x_mac_link_spd_sts(int p) -{ - return RTL838X_MAC_LINK_SPD_STS(p); -} - -inline static int rtl838x_trk_mbr_ctr(int group) -{ - return RTL838X_TRK_MBR_CTR + (group << 2); -} - -/* - * Fills an L2 entry structure from the SoC registers - */ -static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) -{ - /* Table contains different entry types, we need to identify the right one: - * Check for MC entries, first - * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to - * identify valid entries - */ - e->is_ip_mc = !!(r[0] & BIT(22)); - e->is_ipv6_mc = !!(r[0] & BIT(21)); - e->type = L2_INVALID; - - if (!e->is_ip_mc && !e->is_ipv6_mc) { - e->mac[0] = (r[1] >> 20); - e->mac[1] = (r[1] >> 12); - e->mac[2] = (r[1] >> 4); - e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); - e->mac[4] = (r[2] >> 20); - e->mac[5] = (r[2] >> 12); - - e->rvid = r[2] & 0xfff; - e->vid = r[0] & 0xfff; - - /* Is it a unicast entry? check multicast bit */ - if (!(e->mac[0] & 1)) { - e->is_static = !!((r[0] >> 19) & 1); - e->port = (r[0] >> 12) & 0x1f; - e->block_da = !!(r[1] & BIT(30)); - e->block_sa = !!(r[1] & BIT(31)); - e->suspended = !!(r[1] & BIT(29)); - e->next_hop = !!(r[1] & BIT(28)); - if (e->next_hop) { - pr_debug("Found next hop entry, need to read extra data\n"); - e->nh_vlan_target = !!(r[0] & BIT(9)); - e->nh_route_id = r[0] & 0x1ff; - e->vid = e->rvid; - } - e->age = (r[0] >> 17) & 0x3; - e->valid = true; - - /* A valid entry has one of mutli-cast, aging, sa/da-blocking, - * next-hop or static entry bit set */ - if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000)) - e->valid = false; - else - e->type = L2_UNICAST; - } else { // L2 multicast - pr_debug("Got L2 MC entry: %08x %08x %08x\n", r[0], r[1], r[2]); - e->valid = true; - e->type = L2_MULTICAST; - e->mc_portmask_index = (r[0] >> 12) & 0x1ff; - } - } else { // IPv4 and IPv6 multicast - e->valid = true; - e->mc_portmask_index = (r[0] >> 12) & 0x1ff; - e->mc_gip = (r[1] << 20) | (r[2] >> 12); - e->rvid = r[2] & 0xfff; - } - if (e->is_ip_mc) - e->type = IP4_MULTICAST; - if (e->is_ipv6_mc) - e->type = IP6_MULTICAST; -} - -/* - * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry - */ -static void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) -{ - u64 mac = ether_addr_to_u64(e->mac); - - if (!e->valid) { - r[0] = r[1] = r[2] = 0; - return; - } - - r[0] = e->is_ip_mc ? BIT(22) : 0; - r[0] |= e->is_ipv6_mc ? BIT(21) : 0; - - if (!e->is_ip_mc && !e->is_ipv6_mc) { - r[1] = mac >> 20; - r[2] = (mac & 0xfffff) << 12; - - /* Is it a unicast entry? check multicast bit */ - if (!(e->mac[0] & 1)) { - r[0] |= e->is_static ? BIT(19) : 0; - r[0] |= (e->port & 0x3f) << 12; - r[0] |= e->vid; - r[1] |= e->block_da ? BIT(30) : 0; - r[1] |= e->block_sa ? BIT(31) : 0; - r[1] |= e->suspended ? BIT(29) : 0; - r[2] |= e->rvid & 0xfff; - if (e->next_hop) { - r[1] |= BIT(28); - r[0] |= e->nh_vlan_target ? BIT(9) : 0; - r[0] |= e->nh_route_id & 0x1ff; - } - r[0] |= (e->age & 0x3) << 17; - } else { // L2 Multicast - r[0] |= (e->mc_portmask_index & 0x1ff) << 12; - r[2] |= e->rvid & 0xfff; - r[0] |= e->vid & 0xfff; - pr_debug("FILL MC: %08x %08x %08x\n", r[0], r[1], r[2]); - } - } else { // IPv4 and IPv6 multicast - r[0] |= (e->mc_portmask_index & 0x1ff) << 12; - r[1] = e->mc_gip >> 20; - r[2] = e->mc_gip << 12; - r[2] |= e->rvid; - } -} - -/* - * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table - * hash is the id of the bucket and pos is the position of the entry in that bucket - * The data read from the SoC is filled into rtl838x_l2_entry - */ -static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) -{ - u64 entry; - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); // Access L2 Table 0 - u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket - int i; - - rtl_table_read(q, idx); - for (i= 0; i < 3; i++) - r[i] = sw_r32(rtl_table_data(q, i)); - - rtl_table_release(q); - - rtl838x_fill_l2_entry(r, e); - if (!e->valid) - return 0; - - entry = (((u64) r[1]) << 32) | (r[2]); // mac and vid concatenated as hash seed - return entry; -} - -static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); - int i; - - u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket - - rtl838x_fill_l2_row(r, e); - - for (i= 0; i < 3; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); -} - -static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e) -{ - u64 entry; - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1 - int i; - - rtl_table_read(q, idx); - for (i= 0; i < 3; i++) - r[i] = sw_r32(rtl_table_data(q, i)); - - rtl_table_release(q); - - rtl838x_fill_l2_entry(r, e); - if (!e->valid) - return 0; - - pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); - - // Return MAC with concatenated VID ac concatenated ID - entry = (((u64) r[1]) << 32) | r[2]; - return entry; -} - -static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1 - int i; - - rtl838x_fill_l2_row(r, e); - - for (i= 0; i < 3; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); -} - -static u64 rtl838x_read_mcast_pmask(int idx) -{ - u32 portmask; - // Read MC_PMSK (2) via register RTL8380_TBL_L2 - struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2); - - rtl_table_read(q, idx); - portmask = sw_r32(rtl_table_data(q, 0)); - rtl_table_release(q); - - return portmask; -} - -static void rtl838x_write_mcast_pmask(int idx, u64 portmask) -{ - // Access MC_PMSK (2) via register RTL8380_TBL_L2 - struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2); - - sw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0)); - rtl_table_write(q, idx); - rtl_table_release(q); -} - -static void rtl838x_vlan_profile_setup(int profile) -{ - u32 pmask_id = UNKNOWN_MC_PMASK; - // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding - u32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19; - - sw_w32(p, RTL838X_VLAN_PROFILE(profile)); - - /* RTL8380 and RTL8390 use an index into the portmask table to set the - * unknown multicast portmask, setup a default at a safe location - * On RTL93XX, the portmask is directly set in the profile, - * see e.g. rtl9300_vlan_profile_setup - */ - rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff); -} - -static void rtl838x_l2_learning_setup(void) -{ - /* Set portmask for broadcast traffic and unknown unicast address flooding - * to the reserved entry in the portmask table used also for - * multicast flooding */ - sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK); - - /* Enable learning constraint system-wide (bit 0), per-port (bit 1) - * and per vlan (bit 2) */ - sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN); - - // Limit learning to maximum: 16k entries, after that just flood (bits 0-1) - sw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT); - - // Do not trap ARP packets to CPU_PORT - sw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL); -} - -static void rtl838x_enable_learning(int port, bool enable) -{ - // Limit learning to maximum: 16k entries - - sw_w32_mask(0x3fff << 2, enable ? (0x3fff << 2) : 0, - RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); -} - -static void rtl838x_enable_flood(int port, bool enable) -{ - /* - * 0: Forward - * 1: Disable - * 2: to CPU - * 3: Copy to CPU - */ - sw_w32_mask(0x3, enable ? 0 : 1, - RTL838X_L2_PORT_LRN_CONSTRT + (port << 2)); -} - -static void rtl838x_enable_mcast_flood(int port, bool enable) -{ - -} - -static void rtl838x_enable_bcast_flood(int port, bool enable) -{ - -} - -static void rtl838x_set_static_move_action(int port, bool forward) -{ - int shift = MV_ACT_PORT_SHIFT(port); - u32 val = forward ? MV_ACT_FORWARD : MV_ACT_DROP; - - sw_w32_mask(MV_ACT_MASK << shift, val << shift, - RTL838X_L2_PORT_STATIC_MV_ACT(port)); -} - -static void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) -{ - int i; - u32 cmd = 1 << 15 /* Execute cmd */ - | 1 << 14 /* Read */ - | 2 << 12 /* Table type 0b10 */ - | (msti & 0xfff); - priv->r->exec_tbl0_cmd(cmd); - - for (i = 0; i < 2; i++) - port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); -} - -static void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) -{ - int i; - u32 cmd = 1 << 15 /* Execute cmd */ - | 0 << 14 /* Write */ - | 2 << 12 /* Table type 0b10 */ - | (msti & 0xfff); - - for (i = 0; i < 2; i++) - sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); - priv->r->exec_tbl0_cmd(cmd); -} - -u64 rtl838x_traffic_get(int source) -{ - return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source)); -} - -void rtl838x_traffic_set(int source, u64 dest_matrix) -{ - rtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source)); -} - -void rtl838x_traffic_enable(int source, int dest) -{ - rtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source)); -} - -void rtl838x_traffic_disable(int source, int dest) -{ - rtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source)); -} - -/* - * Enables or disables the EEE/EEEP capability of a port - */ -static void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) -{ - u32 v; - - // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP - if (port >= 24) - return; - - pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); - v = enable ? 0x3 : 0x0; - - // Set EEE state for 100 (bit 9) & 1000MBit (bit 10) - sw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port)); - - // Set TX/RX EEE state - if (enable) { - sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN); - sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN); - } else { - sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN); - sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN); - } - priv->ports[port].eee_enabled = enable; -} - - -/* - * Get EEE own capabilities and negotiation result - */ -static int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv, - struct ethtool_eee *e, int port) -{ - u64 link; - - if (port >= 24) - return 0; - - link = rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS); - if (!(link & BIT(port))) - return 0; - - if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(9)) - e->advertised |= ADVERTISED_100baseT_Full; - - if (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(10)) - e->advertised |= ADVERTISED_1000baseT_Full; - - if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) { - e->lp_advertised = ADVERTISED_100baseT_Full; - e->lp_advertised |= ADVERTISED_1000baseT_Full; - return 1; - } - - return 0; -} - -static void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable) -{ - int i; - - pr_info("Setting up EEE, state: %d\n", enable); - sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL); - - /* Set timers for EEE */ - sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL); - sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL); - - // Enable EEE MAC support on ports - for (i = 0; i < priv->cpu_port; i++) { - if (priv->ports[i].phy) - rtl838x_port_eee_set(priv, i, enable); - } - priv->eee_enabled = enable; -} - -static void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index) -{ - int block = index / PIE_BLOCK_SIZE; - u32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL); - - // Make sure rule-lookup is enabled in the block - if (!(block_state & BIT(block))) - sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL); -} - -static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) -{ - int block_from = index_from / PIE_BLOCK_SIZE; - int block_to = index_to / PIE_BLOCK_SIZE; - u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0); - int block; - u32 block_state; - - pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); - mutex_lock(&priv->reg_mutex); - - // Remember currently active blocks - block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL); - - // Make sure rule-lookup is disabled in the relevant blocks - for (block = block_from; block <= block_to; block++) { - if (block_state & BIT(block)) - sw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL); - } - - // Write from-to and execute bit into control register - sw_w32(v, RTL838X_ACL_CLR_CTRL); - - // Wait until command has completed - do { - } while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0)); - - // Re-enable rule lookup - for (block = block_from; block <= block_to; block++) { - if (!(block_state & BIT(block))) - sw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL); - } - - mutex_unlock(&priv->reg_mutex); -} - -/* - * Reads the intermediate representation of the templated match-fields of the - * PIE rule in the pie_rule structure and fills in the raw data fields in the - * raw register space r[]. - * The register space configuration size is identical for the RTL8380/90 and RTL9300, - * however the RTL9310 has 2 more registers / fields and the physical field-ids - * are specific to every platform. - */ -static void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) -{ - int i; - enum template_field_id field_type; - u16 data, data_m; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - field_type = t[i]; - data = data_m = 0; - - switch (field_type) { - case TEMPLATE_FIELD_SPM0: - data = pr->spm; - data_m = pr->spm_m; - break; - case TEMPLATE_FIELD_SPM1: - data = pr->spm >> 16; - data_m = pr->spm_m >> 16; - break; - case TEMPLATE_FIELD_OTAG: - data = pr->otag; - data_m = pr->otag_m; - break; - case TEMPLATE_FIELD_SMAC0: - data = pr->smac[4]; - data = (data << 8) | pr->smac[5]; - data_m = pr->smac_m[4]; - data_m = (data_m << 8) | pr->smac_m[5]; - break; - case TEMPLATE_FIELD_SMAC1: - data = pr->smac[2]; - data = (data << 8) | pr->smac[3]; - data_m = pr->smac_m[2]; - data_m = (data_m << 8) | pr->smac_m[3]; - break; - case TEMPLATE_FIELD_SMAC2: - data = pr->smac[0]; - data = (data << 8) | pr->smac[1]; - data_m = pr->smac_m[0]; - data_m = (data_m << 8) | pr->smac_m[1]; - break; - case TEMPLATE_FIELD_DMAC0: - data = pr->dmac[4]; - data = (data << 8) | pr->dmac[5]; - data_m = pr->dmac_m[4]; - data_m = (data_m << 8) | pr->dmac_m[5]; - break; - case TEMPLATE_FIELD_DMAC1: - data = pr->dmac[2]; - data = (data << 8) | pr->dmac[3]; - data_m = pr->dmac_m[2]; - data_m = (data_m << 8) | pr->dmac_m[3]; - break; - case TEMPLATE_FIELD_DMAC2: - data = pr->dmac[0]; - data = (data << 8) | pr->dmac[1]; - data_m = pr->dmac_m[0]; - data_m = (data_m << 8) | pr->dmac_m[1]; - break; - case TEMPLATE_FIELD_ETHERTYPE: - data = pr->ethertype; - data_m = pr->ethertype_m; - break; - case TEMPLATE_FIELD_ITAG: - data = pr->itag; - data_m = pr->itag_m; - break; - case TEMPLATE_FIELD_RANGE_CHK: - data = pr->field_range_check; - data_m = pr->field_range_check_m; - break; - case TEMPLATE_FIELD_SIP0: - if (pr->is_ipv6) { - data = pr->sip6.s6_addr16[7]; - data_m = pr->sip6_m.s6_addr16[7]; - } else { - data = pr->sip; - data_m = pr->sip_m; - } - break; - case TEMPLATE_FIELD_SIP1: - if (pr->is_ipv6) { - data = pr->sip6.s6_addr16[6]; - data_m = pr->sip6_m.s6_addr16[6]; - } else { - data = pr->sip >> 16; - data_m = pr->sip_m >> 16; - } - break; - - case TEMPLATE_FIELD_SIP2: - case TEMPLATE_FIELD_SIP3: - case TEMPLATE_FIELD_SIP4: - case TEMPLATE_FIELD_SIP5: - case TEMPLATE_FIELD_SIP6: - case TEMPLATE_FIELD_SIP7: - data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; - data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; - break; - - case TEMPLATE_FIELD_DIP0: - if (pr->is_ipv6) { - data = pr->dip6.s6_addr16[7]; - data_m = pr->dip6_m.s6_addr16[7]; - } else { - data = pr->dip; - data_m = pr->dip_m; - } - break; - - case TEMPLATE_FIELD_DIP1: - if (pr->is_ipv6) { - data = pr->dip6.s6_addr16[6]; - data_m = pr->dip6_m.s6_addr16[6]; - } else { - data = pr->dip >> 16; - data_m = pr->dip_m >> 16; - } - break; - - case TEMPLATE_FIELD_DIP2: - case TEMPLATE_FIELD_DIP3: - case TEMPLATE_FIELD_DIP4: - case TEMPLATE_FIELD_DIP5: - case TEMPLATE_FIELD_DIP6: - case TEMPLATE_FIELD_DIP7: - data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; - data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; - break; - - case TEMPLATE_FIELD_IP_TOS_PROTO: - data = pr->tos_proto; - data_m = pr->tos_proto_m; - break; - case TEMPLATE_FIELD_L4_SPORT: - data = pr->sport; - data_m = pr->sport_m; - break; - case TEMPLATE_FIELD_L4_DPORT: - data = pr->dport; - data_m = pr->dport_m; - break; - case TEMPLATE_FIELD_ICMP_IGMP: - data = pr->icmp_igmp; - data_m = pr->icmp_igmp_m; - break; - default: - pr_info("%s: unknown field %d\n", __func__, field_type); - continue; - } - if (!(i % 2)) { - r[5 - i / 2] = data; - r[12 - i / 2] = data_m; - } else { - r[5 - i / 2] |= ((u32)data) << 16; - r[12 - i / 2] |= ((u32)data_m) << 16; - } - } -} - -/* - * Creates the intermediate representation of the templated match-fields of the - * PIE rule in the pie_rule structure by reading the raw data fields in the - * raw register space r[]. - * The register space configuration size is identical for the RTL8380/90 and RTL9300, - * however the RTL9310 has 2 more registers / fields and the physical field-ids - */ -static void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) -{ - int i; - enum template_field_id field_type; - u16 data, data_m; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - field_type = t[i]; - if (!(i % 2)) { - data = r[5 - i / 2]; - data_m = r[12 - i / 2]; - } else { - data = r[5 - i / 2] >> 16; - data_m = r[12 - i / 2] >> 16; - } - - switch (field_type) { - case TEMPLATE_FIELD_SPM0: - pr->spm = (pr->spn << 16) | data; - pr->spm_m = (pr->spn << 16) | data_m; - break; - case TEMPLATE_FIELD_SPM1: - pr->spm = data; - pr->spm_m = data_m; - break; - case TEMPLATE_FIELD_OTAG: - pr->otag = data; - pr->otag_m = data_m; - break; - case TEMPLATE_FIELD_SMAC0: - pr->smac[4] = data >> 8; - pr->smac[5] = data; - pr->smac_m[4] = data >> 8; - pr->smac_m[5] = data; - break; - case TEMPLATE_FIELD_SMAC1: - pr->smac[2] = data >> 8; - pr->smac[3] = data; - pr->smac_m[2] = data >> 8; - pr->smac_m[3] = data; - break; - case TEMPLATE_FIELD_SMAC2: - pr->smac[0] = data >> 8; - pr->smac[1] = data; - pr->smac_m[0] = data >> 8; - pr->smac_m[1] = data; - break; - case TEMPLATE_FIELD_DMAC0: - pr->dmac[4] = data >> 8; - pr->dmac[5] = data; - pr->dmac_m[4] = data >> 8; - pr->dmac_m[5] = data; - break; - case TEMPLATE_FIELD_DMAC1: - pr->dmac[2] = data >> 8; - pr->dmac[3] = data; - pr->dmac_m[2] = data >> 8; - pr->dmac_m[3] = data; - break; - case TEMPLATE_FIELD_DMAC2: - pr->dmac[0] = data >> 8; - pr->dmac[1] = data; - pr->dmac_m[0] = data >> 8; - pr->dmac_m[1] = data; - break; - case TEMPLATE_FIELD_ETHERTYPE: - pr->ethertype = data; - pr->ethertype_m = data_m; - break; - case TEMPLATE_FIELD_ITAG: - pr->itag = data; - pr->itag_m = data_m; - break; - case TEMPLATE_FIELD_RANGE_CHK: - pr->field_range_check = data; - pr->field_range_check_m = data_m; - break; - case TEMPLATE_FIELD_SIP0: - pr->sip = data; - pr->sip_m = data_m; - break; - case TEMPLATE_FIELD_SIP1: - pr->sip = (pr->sip << 16) | data; - pr->sip_m = (pr->sip << 16) | data_m; - break; - case TEMPLATE_FIELD_SIP2: - pr->is_ipv6 = true; - // Make use of limitiations on the position of the match values - ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2], - r[4 - i / 2], r[3 - i / 2]); - ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2], - r[4 - i / 2], r[3 - i / 2]); - case TEMPLATE_FIELD_SIP3: - case TEMPLATE_FIELD_SIP4: - case TEMPLATE_FIELD_SIP5: - case TEMPLATE_FIELD_SIP6: - case TEMPLATE_FIELD_SIP7: - break; - - case TEMPLATE_FIELD_DIP0: - pr->dip = data; - pr->dip_m = data_m; - break; - case TEMPLATE_FIELD_DIP1: - pr->dip = (pr->dip << 16) | data; - pr->dip_m = (pr->dip << 16) | data_m; - break; - case TEMPLATE_FIELD_DIP2: - pr->is_ipv6 = true; - ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2], - r[4 - i / 2], r[3 - i / 2]); - ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2], - r[4 - i / 2], r[3 - i / 2]); - case TEMPLATE_FIELD_DIP3: - case TEMPLATE_FIELD_DIP4: - case TEMPLATE_FIELD_DIP5: - case TEMPLATE_FIELD_DIP6: - case TEMPLATE_FIELD_DIP7: - break; - case TEMPLATE_FIELD_IP_TOS_PROTO: - pr->tos_proto = data; - pr->tos_proto_m = data_m; - break; - case TEMPLATE_FIELD_L4_SPORT: - pr->sport = data; - pr->sport_m = data_m; - break; - case TEMPLATE_FIELD_L4_DPORT: - pr->dport = data; - pr->dport_m = data_m; - break; - case TEMPLATE_FIELD_ICMP_IGMP: - pr->icmp_igmp = data; - pr->icmp_igmp_m = data_m; - break; - default: - pr_info("%s: unknown field %d\n", __func__, field_type); - } - } -} - -static void rtl838x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr) -{ - pr->spmmask_fix = (r[6] >> 22) & 0x3; - pr->spn = (r[6] >> 16) & 0x3f; - pr->mgnt_vlan = (r[6] >> 15) & 1; - pr->dmac_hit_sw = (r[6] >> 14) & 1; - pr->not_first_frag = (r[6] >> 13) & 1; - pr->frame_type_l4 = (r[6] >> 10) & 7; - pr->frame_type = (r[6] >> 8) & 3; - pr->otag_fmt = (r[6] >> 7) & 1; - pr->itag_fmt = (r[6] >> 6) & 1; - pr->otag_exist = (r[6] >> 5) & 1; - pr->itag_exist = (r[6] >> 4) & 1; - pr->frame_type_l2 = (r[6] >> 2) & 3; - pr->tid = r[6] & 3; - - pr->spmmask_fix_m = (r[13] >> 22) & 0x3; - pr->spn_m = (r[13] >> 16) & 0x3f; - pr->mgnt_vlan_m = (r[13] >> 15) & 1; - pr->dmac_hit_sw_m = (r[13] >> 14) & 1; - pr->not_first_frag_m = (r[13] >> 13) & 1; - pr->frame_type_l4_m = (r[13] >> 10) & 7; - pr->frame_type_m = (r[13] >> 8) & 3; - pr->otag_fmt_m = (r[13] >> 7) & 1; - pr->itag_fmt_m = (r[13] >> 6) & 1; - pr->otag_exist_m = (r[13] >> 5) & 1; - pr->itag_exist_m = (r[13] >> 4) & 1; - pr->frame_type_l2_m = (r[13] >> 2) & 3; - pr->tid_m = r[13] & 3; - - pr->valid = r[14] & BIT(31); - pr->cond_not = r[14] & BIT(30); - pr->cond_and1 = r[14] & BIT(29); - pr->cond_and2 = r[14] & BIT(28); - pr->ivalid = r[14] & BIT(27); - - pr->drop = (r[17] >> 14) & 3; - pr->fwd_sel = r[17] & BIT(13); - pr->ovid_sel = r[17] & BIT(12); - pr->ivid_sel = r[17] & BIT(11); - pr->flt_sel = r[17] & BIT(10); - pr->log_sel = r[17] & BIT(9); - pr->rmk_sel = r[17] & BIT(8); - pr->meter_sel = r[17] & BIT(7); - pr->tagst_sel = r[17] & BIT(6); - pr->mir_sel = r[17] & BIT(5); - pr->nopri_sel = r[17] & BIT(4); - pr->cpupri_sel = r[17] & BIT(3); - pr->otpid_sel = r[17] & BIT(2); - pr->itpid_sel = r[17] & BIT(1); - pr->shaper_sel = r[17] & BIT(0); -} - -static void rtl838x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) -{ - r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 22; - r[6] |= ((u32) (pr->spn & 0x3f)) << 16; - r[6] |= pr->mgnt_vlan ? BIT(15) : 0; - r[6] |= pr->dmac_hit_sw ? BIT(14) : 0; - r[6] |= pr->not_first_frag ? BIT(13) : 0; - r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 10; - r[6] |= ((u32) (pr->frame_type & 0x3)) << 8; - r[6] |= pr->otag_fmt ? BIT(7) : 0; - r[6] |= pr->itag_fmt ? BIT(6) : 0; - r[6] |= pr->otag_exist ? BIT(5) : 0; - r[6] |= pr->itag_exist ? BIT(4) : 0; - r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 2; - r[6] |= ((u32) (pr->tid & 0x3)); - - r[13] = ((u32) (pr->spmmask_fix_m & 0x3)) << 22; - r[13] |= ((u32) (pr->spn_m & 0x3f)) << 16; - r[13] |= pr->mgnt_vlan_m ? BIT(15) : 0; - r[13] |= pr->dmac_hit_sw_m ? BIT(14) : 0; - r[13] |= pr->not_first_frag_m ? BIT(13) : 0; - r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10; - r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 8; - r[13] |= pr->otag_fmt_m ? BIT(7) : 0; - r[13] |= pr->itag_fmt_m ? BIT(6) : 0; - r[13] |= pr->otag_exist_m ? BIT(5) : 0; - r[13] |= pr->itag_exist_m ? BIT(4) : 0; - r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2; - r[13] |= ((u32) (pr->tid_m & 0x3)); - - r[14] = pr->valid ? BIT(31) : 0; - r[14] |= pr->cond_not ? BIT(30) : 0; - r[14] |= pr->cond_and1 ? BIT(29) : 0; - r[14] |= pr->cond_and2 ? BIT(28) : 0; - r[14] |= pr->ivalid ? BIT(27) : 0; - - if (pr->drop) - r[17] = 0x1 << 14; // Standard drop action - else - r[17] = 0; - r[17] |= pr->fwd_sel ? BIT(13) : 0; - r[17] |= pr->ovid_sel ? BIT(12) : 0; - r[17] |= pr->ivid_sel ? BIT(11) : 0; - r[17] |= pr->flt_sel ? BIT(10) : 0; - r[17] |= pr->log_sel ? BIT(9) : 0; - r[17] |= pr->rmk_sel ? BIT(8) : 0; - r[17] |= pr->meter_sel ? BIT(7) : 0; - r[17] |= pr->tagst_sel ? BIT(6) : 0; - r[17] |= pr->mir_sel ? BIT(5) : 0; - r[17] |= pr->nopri_sel ? BIT(4) : 0; - r[17] |= pr->cpupri_sel ? BIT(3) : 0; - r[17] |= pr->otpid_sel ? BIT(2) : 0; - r[17] |= pr->itpid_sel ? BIT(1) : 0; - r[17] |= pr->shaper_sel ? BIT(0) : 0; -} - -static int rtl838x_write_pie_action(u32 r[], struct pie_rule *pr) -{ - u16 *aif = (u16 *)&r[17]; - u16 data; - int fields_used = 0; - - aif--; - - pr_debug("%s, at %08x\n", __func__, (u32)aif); - /* Multiple actions can be linked to a match of a PIE rule, - * they have different precedence depending on their type and this precedence - * defines which Action Information Field (0-4) in the IACL table stores - * the additional data of the action (like e.g. the port number a packet is - * forwarded to) */ - // TODO: count bits in selectors to limit to a maximum number of actions - if (pr->fwd_sel) { // Forwarding action - data = pr->fwd_act << 13; - data |= pr->fwd_data; - data |= pr->bypass_all ? BIT(12) : 0; - data |= pr->bypass_ibc_sc ? BIT(11) : 0; - data |= pr->bypass_igr_stp ? BIT(10) : 0; - *aif-- = data; - fields_used++; - } - - if (pr->ovid_sel) { // Outer VID action - data = (pr->ovid_act & 0x3) << 12; - data |= pr->ovid_data; - *aif-- = data; - fields_used++; - } - - if (pr->ivid_sel) { // Inner VID action - data = (pr->ivid_act & 0x3) << 12; - data |= pr->ivid_data; - *aif-- = data; - fields_used++; - } - - if (pr->flt_sel) { // Filter action - *aif-- = pr->flt_data; - fields_used++; - } - - if (pr->log_sel) { // Log action - if (fields_used >= 4) - return -1; - *aif-- = pr->log_data; - fields_used++; - } - - if (pr->rmk_sel) { // Remark action - if (fields_used >= 4) - return -1; - *aif-- = pr->rmk_data; - fields_used++; - } - - if (pr->meter_sel) { // Meter action - if (fields_used >= 4) - return -1; - *aif-- = pr->meter_data; - fields_used++; - } - - if (pr->tagst_sel) { // Egress Tag Status action - if (fields_used >= 4) - return -1; - *aif-- = pr->tagst_data; - fields_used++; - } - - if (pr->mir_sel) { // Mirror action - if (fields_used >= 4) - return -1; - *aif-- = pr->mir_data; - fields_used++; - } - - if (pr->nopri_sel) { // Normal Priority action - if (fields_used >= 4) - return -1; - *aif-- = pr->nopri_data; - fields_used++; - } - - if (pr->cpupri_sel) { // CPU Priority action - if (fields_used >= 4) - return -1; - *aif-- = pr->nopri_data; - fields_used++; - } - - if (pr->otpid_sel) { // OTPID action - if (fields_used >= 4) - return -1; - *aif-- = pr->otpid_data; - fields_used++; - } - - if (pr->itpid_sel) { // ITPID action - if (fields_used >= 4) - return -1; - *aif-- = pr->itpid_data; - fields_used++; - } - - if (pr->shaper_sel) { // Traffic shaper action - if (fields_used >= 4) - return -1; - *aif-- = pr->shaper_data; - fields_used++; - } - - return 0; -} - -static void rtl838x_read_pie_action(u32 r[], struct pie_rule *pr) -{ - u16 *aif = (u16 *)&r[17]; - - aif--; - - pr_debug("%s, at %08x\n", __func__, (u32)aif); - if (pr->drop) - pr_debug("%s: Action Drop: %d", __func__, pr->drop); - - if (pr->fwd_sel){ // Forwarding action - pr->fwd_act = *aif >> 13; - pr->fwd_data = *aif--; - pr->bypass_all = pr->fwd_data & BIT(12); - pr->bypass_ibc_sc = pr->fwd_data & BIT(11); - pr->bypass_igr_stp = pr->fwd_data & BIT(10); - if (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp) - pr->bypass_sel = true; - } - if (pr->ovid_sel) // Outer VID action - pr->ovid_data = *aif--; - if (pr->ivid_sel) // Inner VID action - pr->ivid_data = *aif--; - if (pr->flt_sel) // Filter action - pr->flt_data = *aif--; - if (pr->log_sel) // Log action - pr->log_data = *aif--; - if (pr->rmk_sel) // Remark action - pr->rmk_data = *aif--; - if (pr->meter_sel) // Meter action - pr->meter_data = *aif--; - if (pr->tagst_sel) // Egress Tag Status action - pr->tagst_data = *aif--; - if (pr->mir_sel) // Mirror action - pr->mir_data = *aif--; - if (pr->nopri_sel) // Normal Priority action - pr->nopri_data = *aif--; - if (pr->cpupri_sel) // CPU Priority action - pr->nopri_data = *aif--; - if (pr->otpid_sel) // OTPID action - pr->otpid_data = *aif--; - if (pr->itpid_sel) // ITPID action - pr->itpid_data = *aif--; - if (pr->shaper_sel) // Traffic shaper action - pr->shaper_data = *aif--; -} - -static void rtl838x_pie_rule_dump_raw(u32 r[]) -{ - pr_info("Raw IACL table entry:\n"); - pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]); - pr_info("Fixed : %08x\n", r[6]); - pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", r[7], r[8], r[9], r[10], r[11], r[12]); - pr_info("Fixed M: %08x\n", r[13]); - pr_info("AIF : %08x %08x %08x\n", r[14], r[15], r[16]); - pr_info("Sel : %08x\n", r[17]); -} - -static void rtl838x_pie_rule_dump(struct pie_rule *pr) -{ - pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n", - pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel, - pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel); - if (pr->fwd_sel) - pr_info("FWD: %08x\n", pr->fwd_data); - pr_info("TID: %x, %x\n", pr->tid, pr->tid_m); -} - -static int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) -{ - // Read IACL table (1) via register 0 - struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1); - u32 r[18]; - int i; - int block = idx / PIE_BLOCK_SIZE; - u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)); - - memset(pr, 0, sizeof(*pr)); - rtl_table_read(q, idx); - for (i = 0; i < 18; i++) - r[i] = sw_r32(rtl_table_data(q, i)); - - rtl_table_release(q); - - rtl838x_read_pie_fixed_fields(r, pr); - if (!pr->valid) - return 0; - - pr_info("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid); - rtl838x_pie_rule_dump_raw(r); - - rtl838x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]); - - rtl838x_read_pie_action(r, pr); - - return 0; -} - -static int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) -{ - // Access IACL table (1) via register 0 - struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1); - u32 r[18]; - int i, err = 0; - int block = idx / PIE_BLOCK_SIZE; - u32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)); - - pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); - - for (i = 0; i < 18; i++) - r[i] = 0; - - if (!pr->valid) - goto err_out; - - rtl838x_write_pie_fixed_fields(r, pr); - - pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7); - rtl838x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]); - - if (rtl838x_write_pie_action(r, pr)) { - pr_err("Rule actions too complex\n"); - goto err_out; - } - -// rtl838x_pie_rule_dump_raw(r); - - for (i = 0; i < 18; i++) - sw_w32(r[i], rtl_table_data(q, i)); - -err_out: - rtl_table_write(q, idx); - rtl_table_release(q); - - return err; -} - -static bool rtl838x_pie_templ_has(int t, enum template_field_id field_type) -{ - int i; - enum template_field_id ft; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - ft = fixed_templates[t][i]; - if (field_type == ft) - return true; - } - - return false; -} - -static int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv, - struct pie_rule *pr, int t, int block) -{ - int i; - - if (!pr->is_ipv6 && pr->sip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP0)) - return -1; - - if (!pr->is_ipv6 && pr->dip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP0)) - return -1; - - if (pr->is_ipv6) { - if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1] - || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3]) - && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) - return -1; - if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1] - || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3]) - && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) - return -1; - } - - if (ether_addr_to_u64(pr->smac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0)) - return -1; - - if (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) - return -1; - - // TODO: Check more - - i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); - - if (i >= PIE_BLOCK_SIZE) - return -1; - - return i + PIE_BLOCK_SIZE * block; -} - -static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) -{ - int idx, block, j, t; - - pr_debug("In %s\n", __func__); - - mutex_lock(&priv->pie_mutex); - - for (block = 0; block < priv->n_pie_blocks; block++) { - for (j = 0; j < 3; j++) { - t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7; - pr_debug("Testing block %d, template %d, template id %d\n", block, j, t); - idx = rtl838x_pie_verify_template(priv, pr, t, block); - if (idx >= 0) - break; - } - if (j < 3) - break; - } - - if (block >= priv->n_pie_blocks) { - mutex_unlock(&priv->pie_mutex); - return -EOPNOTSUPP; - } - - pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j); - set_bit(idx, priv->pie_use_bm); - - pr->valid = true; - pr->tid = j; // Mapped to template number - pr->tid_m = 0x3; - pr->id = idx; - - rtl838x_pie_lookup_enable(priv, idx); - rtl838x_pie_rule_write(priv, idx, pr); - - mutex_unlock(&priv->pie_mutex); - return 0; -} - -static void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr) -{ - int idx = pr->id; - - rtl838x_pie_rule_del(priv, idx, idx); - clear_bit(idx, priv->pie_use_bm); -} - -/* - * Initializes the Packet Inspection Engine: - * powers it up, enables default matching templates for all blocks - * and clears all rules possibly installed by u-boot - */ -static void rtl838x_pie_init(struct rtl838x_switch_priv *priv) -{ - int i; - u32 template_selectors; - - mutex_init(&priv->pie_mutex); - - // Enable ACL lookup on all ports, including CPU_PORT - for (i = 0; i <= priv->cpu_port; i++) - sw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i)); - - // Power on all PIE blocks - for (i = 0; i < priv->n_pie_blocks; i++) - sw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL); - - // Include IPG in metering - sw_w32(1, RTL838X_METER_GLB_CTRL); - - // Delete all present rules - rtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1); - - // Routing bypasses source port filter: disable write-protection, first - sw_w32_mask(0, 3, RTL838X_INT_RW_CTRL); - sw_w32_mask(0, 1, RTL838X_DMY_REG27); - sw_w32_mask(3, 0, RTL838X_INT_RW_CTRL); - - // Enable predefined templates 0, 1 and 2 for even blocks - template_selectors = 0 | (1 << 3) | (2 << 6); - for (i = 0; i < 6; i += 2) - sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks - template_selectors = 0 | (3 << 3) | (4 << 6); - for (i = 1; i < priv->n_pie_blocks; i += 2) - sw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i)); - - // Group each pair of physical blocks together to a logical block - sw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL); -} - -static u32 rtl838x_packet_cntr_read(int counter) -{ - u32 v; - - // Read LOG table (3) via register RTL8380_TBL_0 - struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3); - - pr_debug("In %s, id %d\n", __func__, counter); - rtl_table_read(r, counter / 2); - - pr_debug("Registers: %08x %08x\n", - sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1))); - // The table has a size of 2 registers - if (counter % 2) - v = sw_r32(rtl_table_data(r, 0)); - else - v = sw_r32(rtl_table_data(r, 1)); - - rtl_table_release(r); - - return v; -} - -static void rtl838x_packet_cntr_clear(int counter) -{ - // Access LOG table (3) via register RTL8380_TBL_0 - struct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3); - - pr_debug("In %s, id %d\n", __func__, counter); - // The table has a size of 2 registers - if (counter % 2) - sw_w32(0, rtl_table_data(r, 0)); - else - sw_w32(0, rtl_table_data(r, 1)); - - rtl_table_write(r, counter / 2); - - rtl_table_release(r); -} - -static void rtl838x_route_read(int idx, struct rtl83xx_route *rt) -{ - // Read ROUTING table (2) via register RTL8380_TBL_1 - struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2); - - pr_debug("In %s, id %d\n", __func__, idx); - rtl_table_read(r, idx); - - // The table has a size of 2 registers - rt->nh.gw = sw_r32(rtl_table_data(r, 0)); - rt->nh.gw <<= 32; - rt->nh.gw |= sw_r32(rtl_table_data(r, 1)); - - rtl_table_release(r); -} - -static void rtl838x_route_write(int idx, struct rtl83xx_route *rt) -{ - // Access ROUTING table (2) via register RTL8380_TBL_1 - struct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2); - - pr_debug("In %s, id %d, gw: %016llx\n", __func__, idx, rt->nh.gw); - sw_w32(rt->nh.gw >> 32, rtl_table_data(r, 0)); - sw_w32(rt->nh.gw, rtl_table_data(r, 1)); - rtl_table_write(r, idx); - - rtl_table_release(r); -} - -static int rtl838x_l3_setup(struct rtl838x_switch_priv *priv) -{ - // Nothing to be done - return 0; -} - -void rtl838x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) -{ - sw_w32(FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK, - keep_outer ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG) | - FIELD_PREP(RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK, - keep_inner ? RTL838X_VLAN_PORT_TAG_STS_TAGGED : RTL838X_VLAN_PORT_TAG_STS_UNTAG), - RTL838X_VLAN_PORT_TAG_STS_CTRL(port)); -} - -void rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) -{ - if (type == PBVLAN_TYPE_INNER) - sw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); - else - sw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); -} - -void rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) -{ - if (type == PBVLAN_TYPE_INNER) - sw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); - else - sw_w32_mask(0xfff << 16, pvid << 16, RTL838X_VLAN_PORT_PB_VLAN + (port << 2)); -} - -static int rtl838x_set_ageing_time(unsigned long msec) -{ - int t = sw_r32(RTL838X_L2_CTRL_1); - - t &= 0x7FFFFF; - t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */ - pr_debug("L2 AGING time: %d sec\n", t); - - t = (msec * 625 + 127000) / 128000; - t = t > 0x7FFFFF ? 0x7FFFFF : t; - sw_w32_mask(0x7FFFFF, t, RTL838X_L2_CTRL_1); - pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL838X_L2_PORT_AGING_OUT)); - - return 0; -} - -static void rtl838x_set_igr_filter(int port, enum igr_filter state) -{ - sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1), - RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); -} - -static void rtl838x_set_egr_filter(int port, enum egr_filter state) -{ - sw_w32_mask(0x1 << (port % 0x1d), state << (port % 0x1d), - RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2))); -} - -void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) -{ - algoidx &= 1; // RTL838X only supports 2 concurrent algorithms - sw_w32_mask(1 << (group % 8), algoidx << (group % 8), - RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2)); - sw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2)); -} - -void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action) -{ - switch(type) { - case BPDU: - sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), - RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2)); - break; - case PTP: - sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), - RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2)); - break; - case LLTP: - sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), - RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2)); - break; - default: - break; - } -} - -const struct rtl838x_reg rtl838x_reg = { - .mask_port_reg_be = rtl838x_mask_port_reg, - .set_port_reg_be = rtl838x_set_port_reg, - .get_port_reg_be = rtl838x_get_port_reg, - .mask_port_reg_le = rtl838x_mask_port_reg, - .set_port_reg_le = rtl838x_set_port_reg, - .get_port_reg_le = rtl838x_get_port_reg, - .stat_port_rst = RTL838X_STAT_PORT_RST, - .stat_rst = RTL838X_STAT_RST, - .stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB, - .port_iso_ctrl = rtl838x_port_iso_ctrl, - .traffic_enable = rtl838x_traffic_enable, - .traffic_disable = rtl838x_traffic_disable, - .traffic_get = rtl838x_traffic_get, - .traffic_set = rtl838x_traffic_set, - .l2_ctrl_0 = RTL838X_L2_CTRL_0, - .l2_ctrl_1 = RTL838X_L2_CTRL_1, - .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT, - .set_ageing_time = rtl838x_set_ageing_time, - .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL, - .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL, - .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd, - .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd, - .tbl_access_data_0 = rtl838x_tbl_access_data_0, - .isr_glb_src = RTL838X_ISR_GLB_SRC, - .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG, - .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG, - .imr_glb = RTL838X_IMR_GLB, - .vlan_tables_read = rtl838x_vlan_tables_read, - .vlan_set_tagged = rtl838x_vlan_set_tagged, - .vlan_set_untagged = rtl838x_vlan_set_untagged, - .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl, - .vlan_profile_dump = rtl838x_vlan_profile_dump, - .vlan_profile_setup = rtl838x_vlan_profile_setup, - .vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner, - .set_vlan_igr_filter = rtl838x_set_igr_filter, - .set_vlan_egr_filter = rtl838x_set_egr_filter, - .enable_learning = rtl838x_enable_learning, - .enable_flood = rtl838x_enable_flood, - .enable_mcast_flood = rtl838x_enable_mcast_flood, - .enable_bcast_flood = rtl838x_enable_bcast_flood, - .set_static_move_action = rtl838x_set_static_move_action, - .stp_get = rtl838x_stp_get, - .stp_set = rtl838x_stp_set, - .mac_port_ctrl = rtl838x_mac_port_ctrl, - .l2_port_new_salrn = rtl838x_l2_port_new_salrn, - .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd, - .mir_ctrl = RTL838X_MIR_CTRL, - .mir_dpm = RTL838X_MIR_DPM_CTRL, - .mir_spm = RTL838X_MIR_SPM_CTRL, - .mac_link_sts = RTL838X_MAC_LINK_STS, - .mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS, - .mac_link_spd_sts = rtl838x_mac_link_spd_sts, - .mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS, - .mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS, - .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash, - .write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash, - .read_cam = rtl838x_read_cam, - .write_cam = rtl838x_write_cam, - .vlan_port_keep_tag_set = rtl838x_vlan_port_keep_tag_set, - .vlan_port_pvidmode_set = rtl838x_vlan_port_pvidmode_set, - .vlan_port_pvid_set = rtl838x_vlan_port_pvid_set, - .trk_mbr_ctr = rtl838x_trk_mbr_ctr, - .rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK, - .spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL, - .init_eee = rtl838x_init_eee, - .port_eee_set = rtl838x_port_eee_set, - .eee_port_ability = rtl838x_eee_port_ability, - .l2_hash_seed = rtl838x_l2_hash_seed, - .l2_hash_key = rtl838x_l2_hash_key, - .read_mcast_pmask = rtl838x_read_mcast_pmask, - .write_mcast_pmask = rtl838x_write_mcast_pmask, - .pie_init = rtl838x_pie_init, - .pie_rule_read = rtl838x_pie_rule_read, - .pie_rule_write = rtl838x_pie_rule_write, - .pie_rule_add = rtl838x_pie_rule_add, - .pie_rule_rm = rtl838x_pie_rule_rm, - .l2_learning_setup = rtl838x_l2_learning_setup, - .packet_cntr_read = rtl838x_packet_cntr_read, - .packet_cntr_clear = rtl838x_packet_cntr_clear, - .route_read = rtl838x_route_read, - .route_write = rtl838x_route_write, - .l3_setup = rtl838x_l3_setup, - .set_distribution_algorithm = rtl838x_set_distribution_algorithm, - .set_receive_management_action = rtl838x_set_receive_management_action, -}; - -irqreturn_t rtl838x_switch_irq(int irq, void *dev_id) -{ - struct dsa_switch *ds = dev_id; - u32 status = sw_r32(RTL838X_ISR_GLB_SRC); - u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG); - u32 link; - int i; - - /* Clear status */ - sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG); - pr_info("RTL8380 Link change: status: %x, ports %x\n", status, ports); - - for (i = 0; i < 28; i++) { - if (ports & BIT(i)) { - link = sw_r32(RTL838X_MAC_LINK_STS); - if (link & BIT(i)) - dsa_port_phylink_mac_change(ds, i, true); - else - dsa_port_phylink_mac_change(ds, i, false); - } - } - return IRQ_HANDLED; -} - -int rtl838x_smi_wait_op(int timeout) -{ - int ret = 0; - u32 val; - - ret = readx_poll_timeout(sw_r32, RTL838X_SMI_ACCESS_PHY_CTRL_1, - val, !(val & 0x1), 20, timeout); - if (ret) - pr_err("%s: timeout\n", __func__); - - return ret; -} - -/* - * Reads a register in a page from the PHY - */ -int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val) -{ - u32 v; - u32 park_page; - - if (port > 31) { - *val = 0xffff; - return 0; - } - - if (page > 4095 || reg > 31) - return -ENOTSUPP; - - mutex_lock(&smi_lock); - - if (rtl838x_smi_wait_op(100000)) - goto timeout; - - sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); - - park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2); - v = reg << 20 | page << 3; - sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1); - sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1); - - if (rtl838x_smi_wait_op(100000)) - goto timeout; - - *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff; - - mutex_unlock(&smi_lock); - return 0; - -timeout: - mutex_unlock(&smi_lock); - return -ETIMEDOUT; -} - -/* - * Write to a register in a page of the PHY - */ -int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val) -{ - u32 v; - u32 park_page; - - val &= 0xffff; - if (port > 31 || page > 4095 || reg > 31) - return -ENOTSUPP; - - mutex_lock(&smi_lock); - if (rtl838x_smi_wait_op(100000)) - goto timeout; - - sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0); - mdelay(10); - - sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); - - park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2); - v = reg << 20 | page << 3 | 0x4; - sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1); - sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1); - - if (rtl838x_smi_wait_op(100000)) - goto timeout; - - mutex_unlock(&smi_lock); - return 0; - -timeout: - mutex_unlock(&smi_lock); - return -ETIMEDOUT; -} - -/* - * Read an mmd register of a PHY - */ -int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val) -{ - u32 v; - - mutex_lock(&smi_lock); - - if (rtl838x_smi_wait_op(100000)) - goto timeout; - - sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0); - mdelay(10); - - sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); - - v = addr << 16 | reg; - sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3); - - /* mmd-access | read | cmd-start */ - v = 1 << 1 | 0 << 2 | 1; - sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1); - - if (rtl838x_smi_wait_op(100000)) - goto timeout; - - *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff; - - mutex_unlock(&smi_lock); - return 0; - -timeout: - mutex_unlock(&smi_lock); - return -ETIMEDOUT; -} - -/* - * Write to an mmd register of a PHY - */ -int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val) -{ - u32 v; - - pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val); - val &= 0xffff; - mutex_lock(&smi_lock); - - if (rtl838x_smi_wait_op(100000)) - goto timeout; - - sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0); - mdelay(10); - - sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); - - sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3); - sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3); - /* mmd-access | write | cmd-start */ - v = 1 << 1 | 1 << 2 | 1; - sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1); - - if (rtl838x_smi_wait_op(100000)) - goto timeout; - - mutex_unlock(&smi_lock); - return 0; - -timeout: - mutex_unlock(&smi_lock); - return -ETIMEDOUT; -} - -void rtl8380_get_version(struct rtl838x_switch_priv *priv) -{ - u32 rw_save, info_save; - u32 info; - - rw_save = sw_r32(RTL838X_INT_RW_CTRL); - sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL); - - info_save = sw_r32(RTL838X_CHIP_INFO); - sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO); - - info = sw_r32(RTL838X_CHIP_INFO); - sw_w32(info_save, RTL838X_CHIP_INFO); - sw_w32(rw_save, RTL838X_INT_RW_CTRL); - - if ((info & 0xFFFF) == 0x6275) { - if (((info >> 16) & 0x1F) == 0x1) - priv->version = RTL8380_VERSION_A; - else if (((info >> 16) & 0x1F) == 0x2) - priv->version = RTL8380_VERSION_B; - else - priv->version = RTL8380_VERSION_B; - } else { - priv->version = '-'; - } -} - -void rtl838x_vlan_profile_dump(int profile) -{ - u32 p; - - if (profile < 0 || profile > 7) - return; - - p = sw_r32(RTL838X_VLAN_PROFILE(profile)); - - pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \ - UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d", - profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff); -} - -void rtl8380_sds_rst(int mac) -{ - u32 offset = (mac == 24) ? 0 : 0x100; - - sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset); - sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset); - sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset); - sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset); - sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset); - pr_debug("SERDES reset: %d\n", mac); -} - -int rtl8380_sds_power(int mac, int val) -{ - u32 mode = (val == 1) ? 0x4 : 0x9; - u32 offset = (mac == 24) ? 5 : 0; - - if ((mac != 24) && (mac != 26)) { - pr_err("%s: not a fibre port: %d\n", __func__, mac); - return -1; - } - - sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL); - - rtl8380_sds_rst(mac); - - return 0; -} diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h deleted file mode 100644 index 81656799a7..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h +++ /dev/null @@ -1,1106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _RTL838X_H -#define _RTL838X_H - -#include - -/* - * Register definition - */ -#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7))) -#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7))) -#define RTL930X_MAC_PORT_CTRL(port) (0x3260 + (((port) << 6))) -#define RTL931X_MAC_PORT_CTRL (0x6004) - -#define RTL930X_MAC_L2_PORT_CTRL(port) (0x3268 + (((port) << 6))) -#define RTL931X_MAC_L2_PORT_CTRL (0x6000) - -#define RTL838X_RST_GLB_CTRL_0 (0x003c) - -#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) -#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) -#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) -#define RTL931X_MAC_FORCE_MODE_CTRL (0x0DCC) - -#define RTL838X_DMY_REG31 (0x3b28) -#define RTL838X_SDS_MODE_SEL (0x0028) -#define RTL838X_SDS_CFG_REG (0x0034) -#define RTL838X_INT_MODE_CTRL (0x005c) -#define RTL838X_CHIP_INFO (0x00d8) -#define RTL839X_CHIP_INFO (0x0ff4) -#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) -#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3)) - -/* Packet statistics */ -#define RTL838X_STAT_PORT_STD_MIB (0x1200) -#define RTL839X_STAT_PORT_STD_MIB (0xC000) -#define RTL930X_STAT_PORT_MIB_CNTR (0x0664) -#define RTL838X_STAT_RST (0x3100) -#define RTL839X_STAT_RST (0xF504) -#define RTL930X_STAT_RST (0x3240) -#define RTL931X_STAT_RST (0x7ef4) -#define RTL838X_STAT_PORT_RST (0x3104) -#define RTL839X_STAT_PORT_RST (0xF508) -#define RTL930X_STAT_PORT_RST (0x3244) -#define RTL931X_STAT_PORT_RST (0x7ef8) -#define RTL838X_STAT_CTRL (0x3108) -#define RTL839X_STAT_CTRL (0x04cc) -#define RTL930X_STAT_CTRL (0x3248) -#define RTL931X_STAT_CTRL (0x5720) - -/* Registers of the internal Serdes of the 8390 */ -#define RTL8390_SDS0_1_XSG0 (0xA000) -#define RTL8390_SDS0_1_XSG1 (0xA100) -#define RTL839X_SDS12_13_XSG0 (0xB800) -#define RTL839X_SDS12_13_XSG1 (0xB900) -#define RTL839X_SDS12_13_PWR0 (0xb880) -#define RTL839X_SDS12_13_PWR1 (0xb980) - -/* Registers of the internal Serdes of the 8380 */ -#define RTL838X_SDS4_FIB_REG0 (0xF800) -#define RTL838X_SDS4_REG28 (0xef80) -#define RTL838X_SDS4_DUMMY0 (0xef8c) -#define RTL838X_SDS5_EXT_REG6 (0xf18c) - -/* VLAN registers */ -#define RTL838X_VLAN_CTRL (0x3A74) -#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) -#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) -#define RTL838X_VLAN_PORT_PB_VLAN (0x3C00) -#define RTL838X_VLAN_PORT_IGR_FLTR (0x3A7C) - -#define RTL839X_VLAN_PROFILE(idx) (0x25C0 + (((idx) << 3))) -#define RTL839X_VLAN_CTRL (0x26D4) -#define RTL839X_VLAN_PORT_PB_VLAN (0x26D8) -#define RTL839X_VLAN_PORT_IGR_FLTR (0x27B4) -#define RTL839X_VLAN_PORT_EGR_FLTR (0x27C4) - -#define RTL930X_VLAN_PROFILE_SET(idx) (0x9c60 + (((idx) * 20))) -#define RTL930X_VLAN_CTRL (0x82D4) -#define RTL930X_VLAN_PORT_PB_VLAN (0x82D8) -#define RTL930X_VLAN_PORT_IGR_FLTR (0x83C0) -#define RTL930X_VLAN_PORT_EGR_FLTR (0x83C8) - -#define RTL931X_VLAN_PROFILE_SET(idx) (0x9800 + (((idx) * 28))) -#define RTL931X_VLAN_CTRL (0x94E4) -#define RTL931X_VLAN_PORT_IGR_CTRL (0x94E8) -#define RTL931X_VLAN_PORT_IGR_FLTR (0x96B4) -#define RTL931X_VLAN_PORT_EGR_FLTR (0x96C4) - -/* Table access registers */ -#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) -#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) -#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) -#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) - -#define RTL839X_TBL_ACCESS_CTRL_0 (0x1190) -#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2)) -#define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80) -#define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2)) -#define RTL839X_TBL_ACCESS_CTRL_2 (0x611C) -#define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2))) - -#define RTL930X_TBL_ACCESS_CTRL_0 (0xB340) -#define RTL930X_TBL_ACCESS_DATA_0(idx) (0xB344 + ((idx) << 2)) -#define RTL930X_TBL_ACCESS_CTRL_1 (0xB3A0) -#define RTL930X_TBL_ACCESS_DATA_1(idx) (0xB3A4 + ((idx) << 2)) -#define RTL930X_TBL_ACCESS_CTRL_2 (0xCE04) -#define RTL930X_TBL_ACCESS_DATA_2(i) (0xCE08 + (((i) << 2))) - -#define RTL931X_TBL_ACCESS_CTRL_0 (0x8500) -#define RTL931X_TBL_ACCESS_DATA_0(idx) (0x8508 + ((idx) << 2)) -#define RTL931X_TBL_ACCESS_CTRL_1 (0x40C0) -#define RTL931X_TBL_ACCESS_DATA_1(idx) (0x40C4 + ((idx) << 2)) -#define RTL931X_TBL_ACCESS_CTRL_2 (0x8528) -#define RTL931X_TBL_ACCESS_DATA_2(i) (0x852C + (((i) << 2))) -#define RTL931X_TBL_ACCESS_CTRL_3 (0x0200) -#define RTL931X_TBL_ACCESS_DATA_3(i) (0x0204 + (((i) << 2))) -#define RTL931X_TBL_ACCESS_CTRL_4 (0x20DC) -#define RTL931X_TBL_ACCESS_DATA_4(i) (0x20E0 + (((i) << 2))) -#define RTL931X_TBL_ACCESS_CTRL_5 (0x7E1C) -#define RTL931X_TBL_ACCESS_DATA_5(i) (0x7E20 + (((i) << 2))) - -/* MAC handling */ -#define RTL838X_MAC_LINK_STS (0xa188) -#define RTL839X_MAC_LINK_STS (0x0390) -#define RTL930X_MAC_LINK_STS (0xCB10) -#define RTL931X_MAC_LINK_STS (0x0EC0) -#define RTL838X_MAC_LINK_SPD_STS(p) (0xa190 + (((p >> 4) << 2))) -#define RTL839X_MAC_LINK_SPD_STS(p) (0x03a0 + (((p >> 4) << 2))) -#define RTL930X_MAC_LINK_SPD_STS(p) (0xCB18 + (((p >> 3) << 2))) -#define RTL931X_MAC_LINK_SPD_STS (0x0ED0) -#define RTL838X_MAC_LINK_DUP_STS (0xa19c) -#define RTL839X_MAC_LINK_DUP_STS (0x03b0) -#define RTL930X_MAC_LINK_DUP_STS (0xCB28) -#define RTL931X_MAC_LINK_DUP_STS (0x0EF0) -#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) -#define RTL839X_MAC_TX_PAUSE_STS (0x03b8) -#define RTL930X_MAC_TX_PAUSE_STS (0xCB2C) -#define RTL931X_MAC_TX_PAUSE_STS (0x0EF8) -#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) -#define RTL839X_MAC_RX_PAUSE_STS (0x03c0) -#define RTL930X_MAC_RX_PAUSE_STS (0xCB30) -#define RTL931X_MAC_RX_PAUSE_STS (0x0F00) -#define RTL930X_MAC_LINK_MEDIA_STS (0xCB14) -#define RTL931X_MAC_LINK_MEDIA_STS (0x0EC8) - -/* MAC link state bits */ -#define RTL838X_FORCE_EN (1 << 0) -#define RTL838X_FORCE_LINK_EN (1 << 1) -#define RTL838X_NWAY_EN (1 << 2) -#define RTL838X_DUPLEX_MODE (1 << 3) -#define RTL838X_TX_PAUSE_EN (1 << 6) -#define RTL838X_RX_PAUSE_EN (1 << 7) -#define RTL838X_MAC_FORCE_FC_EN (1 << 8) - -#define RTL839X_FORCE_EN (1 << 0) -#define RTL839X_FORCE_LINK_EN (1 << 1) -#define RTL839X_DUPLEX_MODE (1 << 2) -#define RTL839X_TX_PAUSE_EN (1 << 5) -#define RTL839X_RX_PAUSE_EN (1 << 6) -#define RTL839X_MAC_FORCE_FC_EN (1 << 7) - -#define RTL930X_FORCE_EN (1 << 0) -#define RTL930X_FORCE_LINK_EN (1 << 1) -#define RTL930X_DUPLEX_MODE (1 << 2) -#define RTL930X_TX_PAUSE_EN (1 << 7) -#define RTL930X_RX_PAUSE_EN (1 << 8) -#define RTL930X_MAC_FORCE_FC_EN (1 << 9) - -#define RTL931X_FORCE_EN (1 << 9) -#define RTL931X_FORCE_LINK_EN (1 << 0) -#define RTL931X_DUPLEX_MODE (1 << 2) -#define RTL931X_MAC_FORCE_FC_EN (1 << 4) -#define RTL931X_TX_PAUSE_EN (1 << 16) -#define RTL931X_RX_PAUSE_EN (1 << 17) - -/* EEE */ -#define RTL838X_MAC_EEE_ABLTY (0xa1a8) -#define RTL838X_EEE_PORT_TX_EN (0x014c) -#define RTL838X_EEE_PORT_RX_EN (0x0150) -#define RTL838X_EEE_CLK_STOP_CTRL (0x0148) -#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) -#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) - -#define RTL839X_EEE_TX_TIMER_GELITE_CTRL (0x042C) -#define RTL839X_EEE_TX_TIMER_GIGA_CTRL (0x0430) -#define RTL839X_EEE_TX_TIMER_10G_CTRL (0x0434) -#define RTL839X_EEE_CTRL(p) (0x8008 + ((p) << 7)) -#define RTL839X_MAC_EEE_ABLTY (0x03C8) - -#define RTL930X_MAC_EEE_ABLTY (0xCB34) -#define RTL930X_EEE_CTRL(p) (0x3274 + ((p) << 6)) -#define RTL930X_EEEP_PORT_CTRL(p) (0x3278 + ((p) << 6)) - -/* L2 functionality */ -#define RTL838X_L2_CTRL_0 (0x3200) -#define RTL839X_L2_CTRL_0 (0x3800) -#define RTL930X_L2_CTRL (0x8FD8) -#define RTL931X_L2_CTRL (0xC800) -#define RTL838X_L2_CTRL_1 (0x3204) -#define RTL839X_L2_CTRL_1 (0x3804) -#define RTL930X_L2_AGE_CTRL (0x8FDC) -#define RTL931X_L2_AGE_CTRL (0xC804) -#define RTL838X_L2_PORT_AGING_OUT (0x3358) -#define RTL839X_L2_PORT_AGING_OUT (0x3b74) -#define RTL930X_L2_PORT_AGE_CTRL (0x8FE0) -#define RTL931X_L2_PORT_AGE_CTRL (0xc808) -#define RTL838X_TBL_ACCESS_L2_CTRL (0x6900) -#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) -#define RTL930X_TBL_ACCESS_L2_CTRL (0xB320) -#define RTL930X_TBL_ACCESS_L2_METHOD_CTRL (0xB324) -#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) -#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) -#define RTL930X_TBL_ACCESS_L2_DATA(idx) (0xab08 + ((idx) << 2)) - -#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) -#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) -#define RTL930X_L2_TBL_FLUSH_CTRL (0x9404) -#define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C) - -#define RTL838X_L2_LRN_CONSTRT (0x329C) -#define RTL839X_L2_LRN_CONSTRT (0x3910) -#define RTL930X_L2_LRN_CONSTRT_CTRL (0x909c) -#define RTL931X_L2_LRN_CONSTRT_CTRL (0xC964) - -#define RTL838X_L2_FLD_PMSK (0x3288) -#define RTL839X_L2_FLD_PMSK (0x38EC) -#define RTL930X_L2_BC_FLD_PMSK (0x9068) -#define RTL931X_L2_BC_FLD_PMSK (0xC8FC) - -#define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064) -#define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4) - -#define RTL838X_L2_LRN_CONSTRT_EN (0x3368) -#define RTL838X_L2_PORT_LRN_CONSTRT (0x32A0) -#define RTL839X_L2_PORT_LRN_CONSTRT (0x3914) - -#define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2))) -#define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2))) -#define RTL930X_L2_PORT_SALRN(p) (0x8FEC + (((p >> 4) << 2))) -#define RTL931X_L2_PORT_NEW_SALRN(p) (0xC820 + (((p >> 4) << 2))) - -#define SALRN_PORT_SHIFT(p) ((p % 16) * 2) -#define SALRN_MODE_MASK 0x3 -#define SALRN_MODE_HARDWARE 0 -#define SALRN_MODE_DISABLED 2 - -#define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2))) -#define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2))) -#define RTL930X_L2_PORT_NEW_SA_FWD(p) (0x8FF4 + (((p / 10) << 2))) -#define RTL931X_L2_PORT_NEW_SA_FWD(p) (0xC830 + (((p / 10) << 2))) - -#define RTL838X_L2_PORT_MV_ACT(p) (0x335c + (((p >> 4) << 2))) -#define RTL839X_L2_PORT_MV_ACT(p) (0x3b80 + (((p >> 4) << 2))) - -#define RTL838X_L2_PORT_STATIC_MV_ACT(p) (0x327c + (((p >> 4) << 2))) -#define RTL839X_L2_PORT_STATIC_MV_ACT(p) (0x38dc + (((p >> 4) << 2))) - -#define MV_ACT_PORT_SHIFT(p) ((p % 16) * 2) -#define MV_ACT_MASK 0x3 -#define MV_ACT_FORWARD 0 -#define MV_ACT_DROP 1 -#define MV_ACT_TRAP2CPU 2 -#define MV_ACT_COPY2CPU 3 - -#define RTL930X_ST_CTRL (0x8798) - -#define RTL930X_L2_PORT_SABLK_CTRL (0x905c) -#define RTL930X_L2_PORT_DABLK_CTRL (0x9060) - -#define RTL838X_L2_PORT_LM_ACT(p) (0x3208 + ((p) << 2)) -#define RTL838X_VLAN_PORT_FWD (0x3A78) -#define RTL839X_VLAN_PORT_FWD (0x27AC) -#define RTL930X_VLAN_PORT_FWD (0x834C) -#define RTL931X_VLAN_PORT_FWD (0x95CC) -#define RTL838X_VLAN_FID_CTRL (0x3aa8) - -/* Port Mirroring */ -#define RTL838X_MIR_CTRL (0x5D00) -#define RTL838X_MIR_DPM_CTRL (0x5D20) -#define RTL838X_MIR_SPM_CTRL (0x5D10) - -#define RTL839X_MIR_CTRL (0x2500) -#define RTL839X_MIR_DPM_CTRL (0x2530) -#define RTL839X_MIR_SPM_CTRL (0x2510) - -#define RTL930X_MIR_CTRL (0xA2A0) -#define RTL930X_MIR_DPM_CTRL (0xA2C0) -#define RTL930X_MIR_SPM_CTRL (0xA2B0) - -#define RTL931X_MIR_CTRL (0xAF00) -#define RTL931X_MIR_DPM_CTRL (0xAF30) -#define RTL931X_MIR_SPM_CTRL (0xAF10) - -/* Storm/rate control and scheduling */ -#define RTL838X_STORM_CTRL (0x4700) -#define RTL839X_STORM_CTRL (0x1800) -#define RTL838X_STORM_CTRL_LB_CTRL(p) (0x4884 + (((p) << 2))) -#define RTL838X_STORM_CTRL_BURST_PPS_0 (0x4874) -#define RTL838X_STORM_CTRL_BURST_PPS_1 (0x4878) -#define RTL838X_STORM_CTRL_BURST_0 (0x487c) -#define RTL838X_STORM_CTRL_BURST_1 (0x4880) -#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0 (0x1804) -#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1 (0x1808) -#define RTL838X_SCHED_CTRL (0xB980) -#define RTL839X_SCHED_CTRL (0x60F4) -#define RTL838X_SCHED_LB_TICK_TKN_CTRL_0 (0xAD58) -#define RTL838X_SCHED_LB_TICK_TKN_CTRL_1 (0xAD5C) -#define RTL839X_SCHED_LB_TICK_TKN_CTRL_0 (0x1804) -#define RTL839X_SCHED_LB_TICK_TKN_CTRL_1 (0x1808) -#define RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL (0x2000) -#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0 (0x1604) -#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1 (0x1608) -#define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60F8) -#define RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL (0x6200) -#define RTL838X_SCHED_LB_THR (0xB984) -#define RTL839X_SCHED_LB_THR (0x60FC) -#define RTL838X_SCHED_P_EGR_RATE_CTRL(p) (0xC008 + (((p) << 7))) -#define RTL838X_SCHED_Q_EGR_RATE_CTRL(p, q) (0xC00C + (p << 7) + (((q) << 2))) -#define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C) -#define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710) -#define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714) -#define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p) (0x180c + (((p >> 5) << 2))) -#define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p) (0x1814 + (((p >> 5) << 2))) -#define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p) (0x181c + (((p >> 5) << 2))) -#define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2))) -#define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2))) -#define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2))) -#define RTL839X_STORM_CTRL_PORT_UC_0(p) (0x185C + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_UC_1(p) (0x1860 + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_MC_0(p) (0x19FC + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_MC_1(p) (0x1a00 + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_BC_0(p) (0x1B9C + (((p) << 3))) -#define RTL839X_STORM_CTRL_PORT_BC_1(p) (0x1BA0 + (((p) << 3))) -#define RTL839X_TBL_ACCESS_CTRL_2 (0x611C) -#define RTL839X_TBL_ACCESS_DATA_2(i) (0x6120 + (((i) << 2))) -#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p) (0x1618 + (((p) << 3))) -#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_1(p) (0x161C + (((p) << 3))) -#define RTL839X_IGR_BWCTRL_PORT_CTRL_0(p) (0x1640 + (((p) << 3))) -#define RTL839X_IGR_BWCTRL_PORT_CTRL_1(p) (0x1644 + (((p) << 3))) -#define RTL839X_IGR_BWCTRL_CTRL_LB_THR (0x1614) - -/* Link aggregation (Trunking) */ -#define TRUNK_DISTRIBUTION_ALGO_SPA_BIT 0x01 -#define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT 0x02 -#define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT 0x04 -#define TRUNK_DISTRIBUTION_ALGO_SIP_BIT 0x08 -#define TRUNK_DISTRIBUTION_ALGO_DIP_BIT 0x10 -#define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT 0x20 -#define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT 0x40 -#define TRUNK_DISTRIBUTION_ALGO_MASKALL 0x7F - -#define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT 0x01 -#define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT 0x02 -#define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT 0x04 -#define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT 0x08 -#define TRUNK_DISTRIBUTION_ALGO_L2_MASKALL 0xF - -#define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT 0x01 -#define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT 0x02 -#define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT 0x04 -#define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT 0x08 -#define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT 0x10 -#define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT 0x20 -#define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT 0x40 -#define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT 0x80 -#define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT 0x100 -#define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT 0x200 -#define TRUNK_DISTRIBUTION_ALGO_L3_MASKALL 0x3FF - -#define RTL838X_TRK_MBR_CTR (0x3E00) -#define RTL838X_TRK_HASH_IDX_CTRL (0x3E20) -#define RTL838X_TRK_HASH_CTRL (0x3E24) - -#define RTL839X_TRK_MBR_CTR (0x2200) -#define RTL839X_TRK_HASH_IDX_CTRL (0x2280) -#define RTL839X_TRK_HASH_CTRL (0x2284) - -#define RTL930X_TRK_MBR_CTRL (0xA41C) -#define RTL930X_TRK_HASH_CTRL (0x9F80) - -#define RTL931X_TRK_MBR_CTRL (0xB8D0) -#define RTL931X_TRK_HASH_CTRL (0xBA70) - -/* Attack prevention */ -#define RTL838X_ATK_PRVNT_PORT_EN (0x5B00) -#define RTL838X_ATK_PRVNT_CTRL (0x5B04) -#define RTL838X_ATK_PRVNT_ACT (0x5B08) -#define RTL838X_ATK_PRVNT_STS (0x5B1C) - -/* 802.1X */ -#define RTL838X_RMA_BPDU_FLD_PMSK (0x4348) -#define RTL930X_RMA_BPDU_FLD_PMSK (0x9F18) -#define RTL931X_RMA_BPDU_FLD_PMSK (0x8950) -#define RTL839X_RMA_BPDU_FLD_PMSK (0x125C) - -#define RTL838X_SPCL_TRAP_CTRL (0x6980) -#define RTL838X_SPCL_TRAP_EAPOL_CTRL (0x6988) -#define RTL838X_SPCL_TRAP_ARP_CTRL (0x698C) -#define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984) -#define RTL838X_SPCL_TRAP_IPV6_CTRL (0x6994) -#define RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL (0x6998) - -#define RTL839X_SPCL_TRAP_CTRL (0x1054) -#define RTL839X_SPCL_TRAP_EAPOL_CTRL (0x105C) -#define RTL839X_SPCL_TRAP_ARP_CTRL (0x1060) -#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058) -#define RTL839X_SPCL_TRAP_IPV6_CTRL (0x1064) -#define RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL (0x1068) -#define RTL839X_SPCL_TRAP_SWITCH_IPV4_ADDR_CTRL (0x106C) -#define RTL839X_SPCL_TRAP_CRC_CTRL (0x1070) -/* special port action controls */ -/* - values: - 0 = FORWARD (default) - 1 = DROP - 2 = TRAP2CPU - 3 = FLOOD IN ALL PORT - - Register encoding. - offset = CTRL + (port >> 4) << 2 - value/mask = 3 << ((port&0xF) << 1) -*/ - -typedef enum { - BPDU = 0, - PTP, - PTP_UDP, - PTP_ETH2, - LLTP, - EAPOL, - GRATARP, -} rma_ctrl_t; - -typedef enum { - FORWARD = 0, - DROP, - TRAP2CPU, - FLOODALL, - TRAP2MASTERCPU, - COPY2CPU, -} action_type_t; - -#define RTL838X_RMA_BPDU_CTRL (0x4330) -#define RTL839X_RMA_BPDU_CTRL (0x122C) -#define RTL930X_RMA_BPDU_CTRL (0x9E7C) -#define RTL931X_RMA_BPDU_CTRL (0x881C) - -#define RTL838X_RMA_PTP_CTRL (0x4338) -#define RTL839X_RMA_PTP_CTRL (0x123C) -#define RTL930X_RMA_PTP_CTRL (0x9E88) -#define RTL931X_RMA_PTP_CTRL (0x8834) - -#define RTL838X_RMA_LLTP_CTRL (0x4340) -#define RTL839X_RMA_LLTP_CTRL (0x124C) -#define RTL930X_RMA_LLTP_CTRL (0x9EFC) -#define RTL931X_RMA_LLTP_CTRL (0x8918) - -#define RTL930X_RMA_EAPOL_CTRL (0x9F08) -#define RTL931X_RMA_EAPOL_CTRL (0x8930) -#define RTL931X_TRAP_ARP_GRAT_PORT_ACT (0x8C04) - -/* QoS */ -#define RTL838X_QM_INTPRI2QID_CTRL (0x5F00) -#define RTL839X_QM_INTPRI2QID_CTRL(q) (0x1110 + (q << 2)) -#define RTL839X_QM_PORT_QNUM(p) (0x1130 + (((p / 10) << 2))) -#define RTL838X_PRI_SEL_PORT_PRI(p) (0x5FB8 + (((p / 10) << 2))) -#define RTL839X_PRI_SEL_PORT_PRI(p) (0x10A8 + (((p / 10) << 2))) -#define RTL838X_QM_PKT2CPU_INTPRI_MAP (0x5F10) -#define RTL839X_QM_PKT2CPU_INTPRI_MAP (0x1154) -#define RTL838X_PRI_SEL_CTRL (0x10E0) -#define RTL839X_PRI_SEL_CTRL (0x10E0) -#define RTL838X_PRI_SEL_TBL_CTRL(i) (0x5FD8 + (((i) << 2))) -#define RTL839X_PRI_SEL_TBL_CTRL(i) (0x10D0 + (((i) << 2))) -#define RTL838X_QM_PKT2CPU_INTPRI_0 (0x5F04) -#define RTL838X_QM_PKT2CPU_INTPRI_1 (0x5F08) -#define RTL838X_QM_PKT2CPU_INTPRI_2 (0x5F0C) -#define RTL839X_OAM_CTRL (0x2100) -#define RTL839X_OAM_PORT_ACT_CTRL(p) (0x2104 + (((p) << 2))) -#define RTL839X_RMK_PORT_DEI_TAG_CTRL(p) (0x6A9C + (((p >> 5) << 2))) -#define RTL839X_PRI_SEL_IPRI_REMAP (0x1080) -#define RTL838X_PRI_SEL_IPRI_REMAP (0x5F8C) -#define RTL839X_PRI_SEL_DEI2DP_REMAP (0x10EC) -#define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i) (0x10F0 + (((i >> 4) << 2))) -#define RTL839X_RMK_DEI_CTRL (0x6AA4) -#define RTL839X_WRED_PORT_THR_CTRL(i) (0x6084 + ((i) << 2)) -#define RTL839X_WRED_QUEUE_THR_CTRL(q, i) (0x6090 + ((q) * 12) + ((i) << 2)) -#define RTL838X_PRI_DSCP_INVLD_CTRL0 (0x5FE8) -#define RTL838X_RMK_IPRI_CTRL (0xA460) -#define RTL838X_RMK_OPRI_CTRL (0xA464) -#define RTL838X_SCHED_P_TYPE_CTRL(p) (0xC04C + (((p) << 7))) -#define RTL838X_SCHED_LB_CTRL(p) (0xC004 + (((p) << 7))) -#define RTL838X_FC_P_EGR_DROP_CTRL(p) (0x6B1C + (((p) << 2))) - -/* Debug features */ -#define RTL930X_STAT_PRVTE_DROP_COUNTER0 (0xB5B8) - -/* Packet Inspection Engine */ -#define RTL838X_METER_GLB_CTRL (0x4B08) -#define RTL839X_METER_GLB_CTRL (0x1300) -#define RTL930X_METER_GLB_CTRL (0xa0a0) -#define RTL931X_METER_GLB_CTRL (0x411C) - -#define RTL839X_ACL_CTRL (0x1288) - -#define RTL838X_ACL_BLK_LOOKUP_CTRL (0x6100) -#define RTL839X_ACL_BLK_LOOKUP_CTRL (0x1280) -#define RTL930X_PIE_BLK_LOOKUP_CTRL (0xa5a0) -#define RTL931X_PIE_BLK_LOOKUP_CTRL (0x4180) - -#define RTL838X_ACL_BLK_PWR_CTRL (0x6104) -#define RTL839X_PS_ACL_PWR_CTRL (0x049c) - -#define RTL838X_ACL_BLK_TMPLTE_CTRL(block) (0x6108 + ((block) << 2)) -#define RTL839X_ACL_BLK_TMPLTE_CTRL(block) (0x128c + ((block) << 2)) -#define RTL930X_PIE_BLK_TMPLTE_CTRL(block) (0xa624 + ((block) << 2)) -#define RTL931X_PIE_BLK_TMPLTE_CTRL(block) (0x4214 + ((block) << 2)) - -#define RTL838X_ACL_BLK_GROUP_CTRL (0x615C) -#define RTL839X_ACL_BLK_GROUP_CTRL (0x12ec) - -#define RTL838X_ACL_CLR_CTRL (0x6168) -#define RTL839X_ACL_CLR_CTRL (0x12fc) -#define RTL930X_PIE_CLR_CTRL (0xa66c) -#define RTL931X_PIE_CLR_CTRL (0x42D8) - -#define RTL838X_DMY_REG27 (0x3378) - -#define RTL838X_ACL_PORT_LOOKUP_CTRL(p) (0x616C + (((p) << 2))) -#define RTL930X_ACL_PORT_LOOKUP_CTRL(p) (0xA784 + (((p) << 2))) -#define RTL931X_ACL_PORT_LOOKUP_CTRL(p) (0x44F8 + (((p) << 2))) - -#define RTL930X_PIE_BLK_PHASE_CTRL (0xA5A4) -#define RTL931X_PIE_BLK_PHASE_CTRL (0x4184) - -// PIE actions -#define PIE_ACT_COPY_TO_PORT 2 -#define PIE_ACT_REDIRECT_TO_PORT 4 -#define PIE_ACT_ROUTE_UC 6 -#define PIE_ACT_VID_ASSIGN 0 - -// L3 actions -#define L3_FORWARD 0 -#define L3_DROP 1 -#define L3_TRAP2CPU 2 -#define L3_COPY2CPU 3 -#define L3_TRAP2MASTERCPU 4 -#define L3_COPY2MASTERCPU 5 -#define L3_HARDDROP 6 - -// Route actions -#define ROUTE_ACT_FORWARD 0 -#define ROUTE_ACT_TRAP2CPU 1 -#define ROUTE_ACT_COPY2CPU 2 -#define ROUTE_ACT_DROP 3 - -/* L3 Routing */ -#define RTL839X_ROUTING_SA_CTRL 0x6afc -#define RTL930X_L3_HOST_TBL_CTRL (0xAB48) -#define RTL930X_L3_IPUC_ROUTE_CTRL (0xAB4C) -#define RTL930X_L3_IP6UC_ROUTE_CTRL (0xAB50) -#define RTL930X_L3_IPMC_ROUTE_CTRL (0xAB54) -#define RTL930X_L3_IP6MC_ROUTE_CTRL (0xAB58) -#define RTL930X_L3_IP_MTU_CTRL(i) (0xAB5C + ((i >> 1) << 2)) -#define RTL930X_L3_IP6_MTU_CTRL(i) (0xAB6C + ((i >> 1) << 2)) -#define RTL930X_L3_HW_LU_KEY_CTRL (0xAC9C) -#define RTL930X_L3_HW_LU_KEY_IP_CTRL (0xACA0) -#define RTL930X_L3_HW_LU_CTRL (0xACC0) -#define RTL930X_L3_IP_ROUTE_CTRL 0xab44 - -/* Port LED Control */ -#define RTL930X_LED_PORT_NUM_CTRL(p) (0xCC04 + (((p >> 4) << 2))) -#define RTL930X_LED_SET0_0_CTRL (0xCC28) -#define RTL930X_LED_PORT_COPR_SET_SEL_CTRL(p) (0xCC2C + (((p >> 4) << 2))) -#define RTL930X_LED_PORT_FIB_SET_SEL_CTRL(p) (0xCC34 + (((p >> 4) << 2))) -#define RTL930X_LED_PORT_COPR_MASK_CTRL (0xCC3C) -#define RTL930X_LED_PORT_FIB_MASK_CTRL (0xCC40) -#define RTL930X_LED_PORT_COMBO_MASK_CTRL (0xCC44) - -#define RTL931X_LED_PORT_NUM_CTRL(p) (0x0604 + (((p >> 4) << 2))) -#define RTL931X_LED_SET0_0_CTRL (0x0630) -#define RTL931X_LED_PORT_COPR_SET_SEL_CTRL(p) (0x0634 + (((p >> 4) << 2))) -#define RTL931X_LED_PORT_FIB_SET_SEL_CTRL(p) (0x0644 + (((p >> 4) << 2))) -#define RTL931X_LED_PORT_COPR_MASK_CTRL (0x0654) -#define RTL931X_LED_PORT_FIB_MASK_CTRL (0x065c) -#define RTL931X_LED_PORT_COMBO_MASK_CTRL (0x0664) - -#define MAX_VLANS 4096 -#define MAX_LAGS 16 -#define MAX_PRIOS 8 -#define RTL930X_PORT_IGNORE 0x3f -#define MAX_MC_GROUPS 512 -#define UNKNOWN_MC_PMASK (MAX_MC_GROUPS - 1) -#define PIE_BLOCK_SIZE 128 -#define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE) -#define N_FIXED_FIELDS 12 -#define N_FIXED_FIELDS_RTL931X 14 -#define MAX_COUNTERS 2048 -#define MAX_ROUTES 512 -#define MAX_HOST_ROUTES 1536 -#define MAX_INTF_MTUS 8 -#define DEFAULT_MTU 1536 -#define MAX_INTERFACES 100 -#define MAX_ROUTER_MACS 64 -#define L3_EGRESS_DMACS 2048 -#define MAX_SMACS 64 - -enum phy_type { - PHY_NONE = 0, - PHY_RTL838X_SDS = 1, - PHY_RTL8218B_INT = 2, - PHY_RTL8218B_EXT = 3, - PHY_RTL8214FC = 4, - PHY_RTL839X_SDS = 5, - PHY_RTL930X_SDS = 6, -}; - -enum pbvlan_type { - PBVLAN_TYPE_INNER = 0, - PBVLAN_TYPE_OUTER, -}; - -enum pbvlan_mode { - PBVLAN_MODE_UNTAG_AND_PRITAG = 0, - PBVLAN_MODE_UNTAG_ONLY, - PBVLAN_MODE_ALL_PKT, -}; - -struct rtl838x_port { - bool enable; - u64 pm; - u16 pvid; - bool eee_enabled; - enum phy_type phy; - bool phy_is_integrated; - bool is10G; - bool is2G5; - int sds_num; - int led_set; - const struct dsa_port *dp; -}; - -struct rtl838x_vlan_info { - u64 untagged_ports; - u64 tagged_ports; - u8 profile_id; - bool hash_mc_fid; - bool hash_uc_fid; - u8 fid; // AKA MSTI - - // The following fields are used only by the RTL931X - int if_id; // Interface (index in L3_EGR_INTF_IDX) - u16 multicast_grp_mask; - int l2_tunnel_list_id; -}; - -enum l2_entry_type { - L2_INVALID = 0, - L2_UNICAST = 1, - L2_MULTICAST = 2, - IP4_MULTICAST = 3, - IP6_MULTICAST = 4, -}; - -struct rtl838x_l2_entry { - u8 mac[6]; - u16 vid; - u16 rvid; - u8 port; - bool valid; - enum l2_entry_type type; - bool is_static; - bool is_ip_mc; - bool is_ipv6_mc; - bool block_da; - bool block_sa; - bool suspended; - bool next_hop; - int age; - u8 trunk; - bool is_trunk; - u8 stack_dev; - u16 mc_portmask_index; - u32 mc_gip; - u32 mc_sip; - u16 mc_mac_index; - u16 nh_route_id; - bool nh_vlan_target; // Only RTL83xx: VLAN used for next hop - - // The following is only valid on RTL931x - bool is_open_flow; - bool is_pe_forward; - bool is_local_forward; - bool is_remote_forward; - bool is_l2_tunnel; - int l2_tunnel_id; - int l2_tunnel_list_id; -}; - -enum fwd_rule_action { - FWD_RULE_ACTION_NONE = 0, - FWD_RULE_ACTION_FWD = 1, -}; - -enum pie_phase { - PHASE_VACL = 0, - PHASE_IACL = 1, -}; - -enum igr_filter { - IGR_FORWARD = 0, - IGR_DROP = 1, - IGR_TRAP = 2, -}; - -enum egr_filter { - EGR_DISABLE = 0, - EGR_ENABLE = 1, -}; - -/* Intermediate representation of a Packet Inspection Engine Rule - * as suggested by the Kernel's tc flower offload subsystem - * Field meaning is universal across SoC families, but data content is specific - * to SoC family (e.g. because of different port ranges) */ -struct pie_rule { - int id; - enum pie_phase phase; // Phase in which this template is applied - int packet_cntr; // ID of a packet counter assigned to this rule - int octet_cntr; // ID of a byte counter assigned to this rule - u32 last_packet_cnt; - u64 last_octet_cnt; - - // The following are requirements for the pie template - bool is_egress; - bool is_ipv6; // This is a rule with IPv6 fields - - // Fixed fields that are always matched against on RTL8380 - u8 spmmask_fix; - u8 spn; // Source port number - bool stacking_port; // Source port is stacking port - bool mgnt_vlan; // Packet arrived on management VLAN - bool dmac_hit_sw; // The packet's destination MAC matches one of the device's - bool content_too_deep; // The content of the packet cannot be parsed: too many layers - bool not_first_frag; // Not the first IP fragment - u8 frame_type_l4; // 0: UDP, 1: TCP, 2: ICMP/ICMPv6, 3: IGMP - u8 frame_type; // 0: ARP, 1: L2 only, 2: IPv4, 3: IPv6 - bool otag_fmt; // 0: outer tag packet, 1: outer priority tag or untagged - bool itag_fmt; // 0: inner tag packet, 1: inner priority tag or untagged - bool otag_exist; // packet with outer tag - bool itag_exist; // packet with inner tag - bool frame_type_l2; // 0: Ethernet, 1: LLC_SNAP, 2: LLC_Other, 3: Reserved - bool igr_normal_port; // Ingress port is not cpu or stacking port - u8 tid; // The template ID defining the what the templated fields mean - - // Masks for the fields that are always matched against on RTL8380 - u8 spmmask_fix_m; - u8 spn_m; - bool stacking_port_m; - bool mgnt_vlan_m; - bool dmac_hit_sw_m; - bool content_too_deep_m; - bool not_first_frag_m; - u8 frame_type_l4_m; - u8 frame_type_m; - bool otag_fmt_m; - bool itag_fmt_m; - bool otag_exist_m; - bool itag_exist_m; - bool frame_type_l2_m; - bool igr_normal_port_m; - u8 tid_m; - - // Logical operations between rules, special rules for rule numbers apply - bool valid; - bool cond_not; // Matches when conditions not match - bool cond_and1; // And this rule 2n with the next rule 2n+1 in same block - bool cond_and2; // And this rule m in block 2n with rule m in block 2n+1 - bool ivalid; - - // Actions to be performed - bool drop; // Drop the packet - bool fwd_sel; // Forward packet: to port, portmask, dest route, next rule, drop - bool ovid_sel; // So something to outer vlan-id: shift, re-assign - bool ivid_sel; // Do something to inner vlan-id: shift, re-assign - bool flt_sel; // Filter the packet when sending to certain ports - bool log_sel; // Log the packet in one of the LOG-table counters - bool rmk_sel; // Re-mark the packet, i.e. change the priority-tag - bool meter_sel; // Meter the packet, i.e. limit rate of this type of packet - bool tagst_sel; // Change the ergress tag - bool mir_sel; // Mirror the packet to a Link Aggregation Group - bool nopri_sel; // Change the normal priority - bool cpupri_sel; // Change the CPU priority - bool otpid_sel; // Change Outer Tag Protocol Identifier (802.1q) - bool itpid_sel; // Change Inner Tag Protocol Identifier (802.1q) - bool shaper_sel; // Apply traffic shaper - bool mpls_sel; // MPLS actions - bool bypass_sel; // Bypass actions - bool fwd_sa_lrn; // Learn the source address when forwarding - bool fwd_mod_to_cpu; // Forward the modified VLAN tag format to CPU-port - - // Fields used in predefined templates 0-2 on RTL8380 / 90 / 9300 - u64 spm; // Source Port Matrix - u16 otag; // Outer VLAN-ID - u8 smac[ETH_ALEN]; // Source MAC address - u8 dmac[ETH_ALEN]; // Destination MAC address - u16 ethertype; // Ethernet frame type field in ethernet header - u16 itag; // Inner VLAN-ID - u16 field_range_check; - u32 sip; // Source IP - struct in6_addr sip6; // IPv6 Source IP - u32 dip; // Destination IP - struct in6_addr dip6; // IPv6 Destination IP - u16 tos_proto; // IPv4: TOS + Protocol fields, IPv6: Traffic class + next header - u16 sport; // TCP/UDP source port - u16 dport; // TCP/UDP destination port - u16 icmp_igmp; - u16 tcp_info; - u16 dsap_ssap; // Destination / Source Service Access Point bytes (802.3) - - u64 spm_m; - u16 otag_m; - u8 smac_m[ETH_ALEN]; - u8 dmac_m[ETH_ALEN]; - u8 ethertype_m; - u16 itag_m; - u16 field_range_check_m; - u32 sip_m; - struct in6_addr sip6_m; // IPv6 Source IP mask - u32 dip_m; - struct in6_addr dip6_m; // IPv6 Destination IP mask - u16 tos_proto_m; - u16 sport_m; - u16 dport_m; - u16 icmp_igmp_m; - u16 tcp_info_m; - u16 dsap_ssap_m; - - // Data associated with actions - u8 fwd_act; // Type of forwarding action - // 0: permit, 1: drop, 2: copy to port id, 4: copy to portmask - // 4: redirect to portid, 5: redirect to portmask - // 6: route, 7: vlan leaky (only 8380) - u16 fwd_data; // Additional data for forwarding action, e.g. destination port - u8 ovid_act; - u16 ovid_data; // Outer VLAN ID - u8 ivid_act; - u16 ivid_data; // Inner VLAN ID - u16 flt_data; // Filtering data - u16 log_data; // ID of packet or octet counter in LOG table, on RTL93xx - // unnecessary since PIE-Rule-ID == LOG-counter-ID - bool log_octets; - u8 mpls_act; // MPLS action type - u16 mpls_lib_idx; // MPLS action data - - u16 rmk_data; // Data for remarking - u16 meter_data; // ID of meter for bandwidth control - u16 tagst_data; - u16 mir_data; - u16 nopri_data; - u16 cpupri_data; - u16 otpid_data; - u16 itpid_data; - u16 shaper_data; - - // Bypass actions, ignored on RTL8380 - bool bypass_all; // Not clear - bool bypass_igr_stp; // Bypass Ingress STP state - bool bypass_ibc_sc; // Bypass Ingress Bandwidth Control and Storm Control -}; - -struct rtl838x_l3_intf { - u16 vid; - u8 smac_idx; - u8 ip4_mtu_id; - u8 ip6_mtu_id; - u16 ip4_mtu; - u16 ip6_mtu; - u8 ttl_scope; - u8 hl_scope; - u8 ip4_icmp_redirect; - u8 ip6_icmp_redirect; - u8 ip4_pbr_icmp_redirect; - u8 ip6_pbr_icmp_redirect; -}; - -/* - * An entry in the RTL93XX SoC's ROUTER_MAC tables setting up a termination point - * for the L3 routing system. Packets arriving and matching an entry in this table - * will be considered for routing. - * Mask fields state whether the corresponding data fields matter for matching - */ -struct rtl93xx_rt_mac { - bool valid; // Valid or not - bool p_type; // Individual (0) or trunk (1) port - bool p_mask; // Whether the port type is used - u8 p_id; - u8 p_id_mask; // Mask for the port - u8 action; // Routing action performed: 0: FORWARD, 1: DROP, 2: TRAP2CPU - // 3: COPY2CPU, 4: TRAP2MASTERCPU, 5: COPY2MASTERCPU, 6: HARDDROP - u16 vid; - u16 vid_mask; - u64 mac; // MAC address used as source MAC in the routed packet - u64 mac_mask; -}; - -struct rtl83xx_nexthop { - u16 id; // ID: L3_NEXT_HOP table-index or route-index set in L2_NEXT_HOP - u32 dev_id; - u16 port; - u16 vid; // VLAN-ID for L2 table entry (saved from L2-UC entry) - u16 rvid; // Relay VID/FID for the L2 table entry - u64 mac; // The MAC address of the entry in the L2_NEXT_HOP table - u16 mac_id; - u16 l2_id; // Index of this next hop forwarding entry in L2 FIB table - u64 gw; // The gateway MAC address packets are forwarded to - int if_id; // Interface (into L3_EGR_INTF_IDX) -}; - -struct rtl838x_switch_priv; - -struct rtl83xx_flow { - unsigned long cookie; - struct rhash_head node; - struct rcu_head rcu_head; - struct rtl838x_switch_priv *priv; - struct pie_rule rule; - u32 flags; -}; - -struct rtl93xx_route_attr { - bool valid; - bool hit; - bool ttl_dec; - bool ttl_check; - bool dst_null; - bool qos_as; - u8 qos_prio; - u8 type; - u8 action; -}; - -struct rtl83xx_route { - u32 gw_ip; // IP of the route's gateway - u32 dst_ip; // IP of the destination net - struct in6_addr dst_ip6; - int prefix_len; // Network prefix len of the destination net - bool is_host_route; - int id; // ID number of this route - struct rhlist_head linkage; - u16 switch_mac_id; // Index into switch's own MACs, RTL839X only - struct rtl83xx_nexthop nh; - struct pie_rule pr; - struct rtl93xx_route_attr attr; -}; - -struct rtl838x_reg { - void (*mask_port_reg_be)(u64 clear, u64 set, int reg); - void (*set_port_reg_be)(u64 set, int reg); - u64 (*get_port_reg_be)(int reg); - void (*mask_port_reg_le)(u64 clear, u64 set, int reg); - void (*set_port_reg_le)(u64 set, int reg); - u64 (*get_port_reg_le)(int reg); - int stat_port_rst; - int stat_rst; - int stat_port_std_mib; - int (*port_iso_ctrl)(int p); - void (*traffic_enable)(int source, int dest); - void (*traffic_disable)(int source, int dest); - void (*traffic_set)(int source, u64 dest_matrix); - u64 (*traffic_get)(int source); - int l2_ctrl_0; - int l2_ctrl_1; - int smi_poll_ctrl; - u32 l2_port_aging_out; - int l2_tbl_flush_ctrl; - void (*exec_tbl0_cmd)(u32 cmd); - void (*exec_tbl1_cmd)(u32 cmd); - int (*tbl_access_data_0)(int i); - int isr_glb_src; - int isr_port_link_sts_chg; - int imr_port_link_sts_chg; - int imr_glb; - void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info); - void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info); - void (*vlan_set_untagged)(u32 vlan, u64 portmask); - void (*vlan_profile_dump)(int index); - void (*vlan_profile_setup)(int profile); - void (*vlan_port_pvidmode_set)(int port, enum pbvlan_type type, enum pbvlan_mode mode); - void (*vlan_port_pvid_set)(int port, enum pbvlan_type type, int pvid); - void (*vlan_port_keep_tag_set)(int port, bool keep_outer, bool keep_inner); - void (*set_vlan_igr_filter)(int port, enum igr_filter state); - void (*set_vlan_egr_filter)(int port, enum egr_filter state); - void (*enable_learning)(int port, bool enable); - void (*enable_flood)(int port, bool enable); - void (*enable_mcast_flood)(int port, bool enable); - void (*enable_bcast_flood)(int port, bool enable); - void (*set_static_move_action)(int port, bool forward); - void (*stp_get)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]); - void (*stp_set)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]); - int (*mac_force_mode_ctrl)(int port); - int (*mac_port_ctrl)(int port); - int (*l2_port_new_salrn)(int port); - int (*l2_port_new_sa_fwd)(int port); - int (*set_ageing_time)(unsigned long msec); - int mir_ctrl; - int mir_dpm; - int mir_spm; - int mac_link_sts; - int mac_link_dup_sts; - int (*mac_link_spd_sts)(int port); - int mac_rx_pause_sts; - int mac_tx_pause_sts; - u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e); - void (*write_l2_entry_using_hash)(u32 hash, u32 pos, struct rtl838x_l2_entry *e); - u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e); - void (*write_cam)(int idx, struct rtl838x_l2_entry *e); - int (*trk_mbr_ctr)(int group); - int rma_bpdu_fld_pmask; - int spcl_trap_eapol_ctrl; - void (*init_eee)(struct rtl838x_switch_priv *priv, bool enable); - void (*port_eee_set)(struct rtl838x_switch_priv *priv, int port, bool enable); - int (*eee_port_ability)(struct rtl838x_switch_priv *priv, - struct ethtool_eee *e, int port); - u64 (*l2_hash_seed)(u64 mac, u32 vid); - u32 (*l2_hash_key)(struct rtl838x_switch_priv *priv, u64 seed); - u64 (*read_mcast_pmask)(int idx); - void (*write_mcast_pmask)(int idx, u64 portmask); - void (*vlan_fwd_on_inner)(int port, bool is_set); - void (*pie_init)(struct rtl838x_switch_priv *priv); - int (*pie_rule_read)(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr); - int (*pie_rule_write)(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr); - int (*pie_rule_add)(struct rtl838x_switch_priv *priv, struct pie_rule *rule); - void (*pie_rule_rm)(struct rtl838x_switch_priv *priv, struct pie_rule *rule); - void (*l2_learning_setup)(void); - u32 (*packet_cntr_read)(int counter); - void (*packet_cntr_clear)(int counter); - void (*route_read)(int idx, struct rtl83xx_route *rt); - void (*route_write)(int idx, struct rtl83xx_route *rt); - void (*host_route_write)(int idx, struct rtl83xx_route *rt); - int (*l3_setup)(struct rtl838x_switch_priv *priv); - void (*set_l3_nexthop)(int idx, u16 dmac_id, u16 interface); - void (*get_l3_nexthop)(int idx, u16 *dmac_id, u16 *interface); - u64 (*get_l3_egress_mac)(u32 idx); - void (*set_l3_egress_mac)(u32 idx, u64 mac); - int (*find_l3_slot)(struct rtl83xx_route *rt, bool must_exist); - int (*route_lookup_hw)(struct rtl83xx_route *rt); - void (*get_l3_router_mac)(u32 idx, struct rtl93xx_rt_mac *m); - void (*set_l3_router_mac)(u32 idx, struct rtl93xx_rt_mac *m); - void (*set_l3_egress_intf)(int idx, struct rtl838x_l3_intf *intf); - void (*set_distribution_algorithm)(int group, int algoidx, u32 algomask); - void (*set_receive_management_action)(int port, rma_ctrl_t type, action_type_t action); - void (*led_init)(struct rtl838x_switch_priv *priv); -}; - -struct rtl838x_switch_priv { - /* Switch operation */ - struct dsa_switch *ds; - struct device *dev; - u16 id; - u16 family_id; - char version; - struct rtl838x_port ports[57]; - struct mutex reg_mutex; // Mutex for individual register manipulations - struct mutex pie_mutex; // Mutex for Packet Inspection Engine - int link_state_irq; - int mirror_group_ports[4]; - struct mii_bus *mii_bus; - const struct rtl838x_reg *r; - u8 cpu_port; - u8 port_mask; - u8 port_width; - u8 port_ignore; - u64 irq_mask; - u32 fib_entries; - int l2_bucket_size; - struct dentry *dbgfs_dir; - int n_lags; - u64 lags_port_members[MAX_LAGS]; - struct net_device *lag_devs[MAX_LAGS]; - u32 lag_primary[MAX_LAGS]; - u32 is_lagmember[57]; - u64 lagmembers; - struct notifier_block nb; // TODO: change to different name - struct notifier_block ne_nb; - struct notifier_block fib_nb; - bool eee_enabled; - unsigned long int mc_group_bm[MAX_MC_GROUPS >> 5]; - int n_pie_blocks; - struct rhashtable tc_ht; - unsigned long int pie_use_bm[MAX_PIE_ENTRIES >> 5]; - int n_counters; - unsigned long int octet_cntr_use_bm[MAX_COUNTERS >> 5]; - unsigned long int packet_cntr_use_bm[MAX_COUNTERS >> 4]; - struct rhltable routes; - unsigned long int route_use_bm[MAX_ROUTES >> 5]; - unsigned long int host_route_use_bm[MAX_HOST_ROUTES >> 5]; - struct rtl838x_l3_intf *interfaces[MAX_INTERFACES]; - u16 intf_mtus[MAX_INTF_MTUS]; - int intf_mtu_count[MAX_INTF_MTUS]; -}; - -void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv); -void rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv); - -#endif /* _RTL838X_H */ diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c deleted file mode 100644 index c34bff78d7..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c +++ /dev/null @@ -1,1948 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include "rtl83xx.h" - -#define RTL839X_VLAN_PORT_TAG_STS_UNTAG 0x0 -#define RTL839X_VLAN_PORT_TAG_STS_TAGGED 0x1 -#define RTL839X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2 - -#define RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE 0x6828 -/* port 0-52 */ -#define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) \ - RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2) -#define RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(7,6) -#define RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(5,4) -#define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3) -#define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2) -#define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1) -#define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0) - -extern struct mutex smi_lock; -extern struct rtl83xx_soc_info soc_info; - -/* Definition of the RTL839X-specific template field IDs as used in the PIE */ -enum template_field_id { - TEMPLATE_FIELD_SPMMASK = 0, - TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15 - TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-31 - TEMPLATE_FIELD_SPM2 = 3, // Source portmask ports 32-47 - TEMPLATE_FIELD_SPM3 = 4, // Source portmask ports 48-56 - TEMPLATE_FIELD_DMAC0 = 5, // Destination MAC [15:0] - TEMPLATE_FIELD_DMAC1 = 6, // Destination MAC [31:16] - TEMPLATE_FIELD_DMAC2 = 7, // Destination MAC [47:32] - TEMPLATE_FIELD_SMAC0 = 8, // Source MAC [15:0] - TEMPLATE_FIELD_SMAC1 = 9, // Source MAC [31:16] - TEMPLATE_FIELD_SMAC2 = 10, // Source MAC [47:32] - TEMPLATE_FIELD_ETHERTYPE = 11, // Ethernet frame type field - // Field-ID 12 is not used - TEMPLATE_FIELD_OTAG = 13, - TEMPLATE_FIELD_ITAG = 14, - TEMPLATE_FIELD_SIP0 = 15, - TEMPLATE_FIELD_SIP1 = 16, - TEMPLATE_FIELD_DIP0 = 17, - TEMPLATE_FIELD_DIP1 = 18, - TEMPLATE_FIELD_IP_TOS_PROTO = 19, - TEMPLATE_FIELD_IP_FLAG = 20, - TEMPLATE_FIELD_L4_SPORT = 21, - TEMPLATE_FIELD_L4_DPORT = 22, - TEMPLATE_FIELD_L34_HEADER = 23, - TEMPLATE_FIELD_ICMP_IGMP = 24, - TEMPLATE_FIELD_VID_RANG0 = 25, - TEMPLATE_FIELD_VID_RANG1 = 26, - TEMPLATE_FIELD_L4_PORT_RANG = 27, - TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 28, - TEMPLATE_FIELD_FIELD_SELECTOR_0 = 29, - TEMPLATE_FIELD_FIELD_SELECTOR_1 = 30, - TEMPLATE_FIELD_FIELD_SELECTOR_2 = 31, - TEMPLATE_FIELD_FIELD_SELECTOR_3 = 32, - TEMPLATE_FIELD_FIELD_SELECTOR_4 = 33, - TEMPLATE_FIELD_FIELD_SELECTOR_5 = 34, - TEMPLATE_FIELD_SIP2 = 35, - TEMPLATE_FIELD_SIP3 = 36, - TEMPLATE_FIELD_SIP4 = 37, - TEMPLATE_FIELD_SIP5 = 38, - TEMPLATE_FIELD_SIP6 = 39, - TEMPLATE_FIELD_SIP7 = 40, - TEMPLATE_FIELD_OLABEL = 41, - TEMPLATE_FIELD_ILABEL = 42, - TEMPLATE_FIELD_OILABEL = 43, - TEMPLATE_FIELD_DPMMASK = 44, - TEMPLATE_FIELD_DPM0 = 45, - TEMPLATE_FIELD_DPM1 = 46, - TEMPLATE_FIELD_DPM2 = 47, - TEMPLATE_FIELD_DPM3 = 48, - TEMPLATE_FIELD_L2DPM0 = 49, - TEMPLATE_FIELD_L2DPM1 = 50, - TEMPLATE_FIELD_L2DPM2 = 51, - TEMPLATE_FIELD_L2DPM3 = 52, - TEMPLATE_FIELD_IVLAN = 53, - TEMPLATE_FIELD_OVLAN = 54, - TEMPLATE_FIELD_FWD_VID = 55, - TEMPLATE_FIELD_DIP2 = 56, - TEMPLATE_FIELD_DIP3 = 57, - TEMPLATE_FIELD_DIP4 = 58, - TEMPLATE_FIELD_DIP5 = 59, - TEMPLATE_FIELD_DIP6 = 60, - TEMPLATE_FIELD_DIP7 = 61, -}; - -// Number of fixed templates predefined in the SoC -#define N_FIXED_TEMPLATES 5 -static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = -{ - { - TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG, - TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2, - TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, - TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 - }, { - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, - TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT, - TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_SPM0, - TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 - }, { - TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, - TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO, - TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0, - TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1 - }, { - TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2, - TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5, - TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT, - TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO - }, { - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2, - TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5, - TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_SPM0, - TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 - }, -}; - -void rtl839x_print_matrix(void) -{ - volatile u64 *ptr9; - int i; - - ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); - for (i = 0; i < 52; i += 4) - pr_debug("> %16llx %16llx %16llx %16llx\n", - ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]); - pr_debug("CPU_PORT> %16llx\n", ptr9[52]); -} - -static inline int rtl839x_port_iso_ctrl(int p) -{ - return RTL839X_PORT_ISO_CTRL(p); -} - -static inline void rtl839x_exec_tbl0_cmd(u32 cmd) -{ - sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0); - do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16)); -} - -static inline void rtl839x_exec_tbl1_cmd(u32 cmd) -{ - sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1); - do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16)); -} - -inline void rtl839x_exec_tbl2_cmd(u32 cmd) -{ - sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2); - do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9)); -} - -static inline int rtl839x_tbl_access_data_0(int i) -{ - return RTL839X_TBL_ACCESS_DATA_0(i); -} - -static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) -{ - u32 u, v, w; - // Read VLAN table (0) via register 0 - struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0); - - rtl_table_read(r, vlan); - u = sw_r32(rtl_table_data(r, 0)); - v = sw_r32(rtl_table_data(r, 1)); - w = sw_r32(rtl_table_data(r, 2)); - rtl_table_release(r); - - info->tagged_ports = u; - info->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff); - info->profile_id = w >> 30 | ((v & 1) << 2); - info->hash_mc_fid = !!(w & BIT(2)); - info->hash_uc_fid = !!(w & BIT(3)); - info->fid = (v >> 3) & 0xff; - - // Read UNTAG table (0) via table register 1 - r = rtl_table_get(RTL8390_TBL_1, 0); - rtl_table_read(r, vlan); - u = sw_r32(rtl_table_data(r, 0)); - v = sw_r32(rtl_table_data(r, 1)); - rtl_table_release(r); - - info->untagged_ports = u; - info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff); -} - -static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) -{ - u32 u, v, w; - // Access VLAN table (0) via register 0 - struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0); - - u = info->tagged_ports >> 21; - v = info->tagged_ports << 11; - v |= ((u32)info->fid) << 3; - v |= info->hash_uc_fid ? BIT(2) : 0; - v |= info->hash_mc_fid ? BIT(1) : 0; - v |= (info->profile_id & 0x4) ? 1 : 0; - w = ((u32)(info->profile_id & 3)) << 30; - - sw_w32(u, rtl_table_data(r, 0)); - sw_w32(v, rtl_table_data(r, 1)); - sw_w32(w, rtl_table_data(r, 2)); - - rtl_table_write(r, vlan); - rtl_table_release(r); -} - -static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask) -{ - u32 u, v; - - // Access UNTAG table (0) via table register 1 - struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0); - - u = portmask >> 21; - v = portmask << 11; - - sw_w32(u, rtl_table_data(r, 0)); - sw_w32(v, rtl_table_data(r, 1)); - rtl_table_write(r, vlan); - - rtl_table_release(r); -} - -/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer - */ -static void rtl839x_vlan_fwd_on_inner(int port, bool is_set) -{ - if (is_set) - rtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD); - else - rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD); -} - -/* - * Hash seed is vid (actually rvid) concatenated with the MAC address - */ -static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid) -{ - u64 v = vid; - - v <<= 48; - v |= mac; - - return v; -} - -/* - * Applies the same hash algorithm as the one used currently by the ASIC to the seed - * and returns a key into the L2 hash table - */ -static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) -{ - u32 h1, h2, h; - - if (sw_r32(priv->r->l2_ctrl_0) & 1) { - h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) - ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) - ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f)); - h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) - ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) - ^ (seed & 0x3f)); - h = (h1 << 6) | h2; - } else { - h = (seed >> 60) - ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f)) - ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff) - ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff); - } - - return h; -} - -static inline int rtl839x_mac_force_mode_ctrl(int p) -{ - return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2); -} - -static inline int rtl839x_mac_port_ctrl(int p) -{ - return RTL839X_MAC_PORT_CTRL(p); -} - -static inline int rtl839x_l2_port_new_salrn(int p) -{ - return RTL839X_L2_PORT_NEW_SALRN(p); -} - -static inline int rtl839x_l2_port_new_sa_fwd(int p) -{ - return RTL839X_L2_PORT_NEW_SA_FWD(p); -} - -static inline int rtl839x_mac_link_spd_sts(int p) -{ - return RTL839X_MAC_LINK_SPD_STS(p); -} - -static inline int rtl839x_trk_mbr_ctr(int group) -{ - return RTL839X_TRK_MBR_CTR + (group << 3); -} - -static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) -{ - /* Table contains different entry types, we need to identify the right one: - * Check for MC entries, first - */ - e->is_ip_mc = !!(r[2] & BIT(31)); - e->is_ipv6_mc = !!(r[2] & BIT(30)); - e->type = L2_INVALID; - if (!e->is_ip_mc && !e->is_ipv6_mc) { - e->mac[0] = (r[0] >> 12); - e->mac[1] = (r[0] >> 4); - e->mac[2] = ((r[1] >> 28) | (r[0] << 4)); - e->mac[3] = (r[1] >> 20); - e->mac[4] = (r[1] >> 12); - e->mac[5] = (r[1] >> 4); - - e->vid = (r[2] >> 4) & 0xfff; - e->rvid = (r[0] >> 20) & 0xfff; - - /* Is it a unicast entry? check multicast bit */ - if (!(e->mac[0] & 1)) { - e->is_static = !!((r[2] >> 18) & 1); - e->port = (r[2] >> 24) & 0x3f; - e->block_da = !!(r[2] & (1 << 19)); - e->block_sa = !!(r[2] & (1 << 20)); - e->suspended = !!(r[2] & (1 << 17)); - e->next_hop = !!(r[2] & (1 << 16)); - if (e->next_hop) { - pr_debug("Found next hop entry, need to read data\n"); - e->nh_vlan_target = !!(r[2] & BIT(15)); - e->nh_route_id = (r[2] >> 4) & 0x1ff; - e->vid = e->rvid; - } - e->age = (r[2] >> 21) & 3; - e->valid = true; - if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */ - e->valid = false; - else - e->type = L2_UNICAST; - } else { - e->valid = true; - e->type = L2_MULTICAST; - e->mc_portmask_index = (r[2] >> 6) & 0xfff; - e->vid = e->rvid; - } - } else { // IPv4 and IPv6 multicast - e->vid = e->rvid = (r[0] << 20) & 0xfff; - e->mc_gip = r[1]; - e->mc_portmask_index = (r[2] >> 6) & 0xfff; - } - if (e->is_ip_mc) { - e->valid = true; - e->type = IP4_MULTICAST; - } - if (e->is_ipv6_mc) { - e->valid = true; - e->type = IP6_MULTICAST; - } - // pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid); -} - -/* - * Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry - */ -static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) -{ - if (!e->valid) { - r[0] = r[1] = r[2] = 0; - return; - } - - r[2] = e->is_ip_mc ? BIT(31) : 0; - r[2] |= e->is_ipv6_mc ? BIT(30) : 0; - - if (!e->is_ip_mc && !e->is_ipv6_mc) { - r[0] = ((u32)e->mac[0]) << 12; - r[0] |= ((u32)e->mac[1]) << 4; - r[0] |= ((u32)e->mac[2]) >> 4; - r[1] = ((u32)e->mac[2]) << 28; - r[1] |= ((u32)e->mac[3]) << 20; - r[1] |= ((u32)e->mac[4]) << 12; - r[1] |= ((u32)e->mac[5]) << 4; - - if (!(e->mac[0] & 1)) { // Not multicast - r[2] |= e->is_static ? BIT(18) : 0; - r[0] |= ((u32)e->rvid) << 20; - r[2] |= e->port << 24; - r[2] |= e->block_da ? BIT(19) : 0; - r[2] |= e->block_sa ? BIT(20) : 0; - r[2] |= e->suspended ? BIT(17) : 0; - r[2] |= ((u32)e->age) << 21; - if (e->next_hop) { - r[2] |= BIT(16); - r[2] |= e->nh_vlan_target ? BIT(15) : 0; - r[2] |= (e->nh_route_id & 0x7ff) << 4; - } else { - r[2] |= e->vid << 4; - } - pr_debug("Write L2 NH: %08x %08x %08x\n", r[0], r[1], r[2]); - } else { // L2 Multicast - r[0] |= ((u32)e->rvid) << 20; - r[2] |= ((u32)e->mc_portmask_index) << 6; - } - } else { // IPv4 or IPv6 MC entry - r[0] = ((u32)e->rvid) << 20; - r[1] = e->mc_gip; - r[2] |= ((u32)e->mc_portmask_index) << 6; - } -} - -/* - * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table - * hash is the id of the bucket and pos is the position of the entry in that bucket - * The data read from the SoC is filled into rtl838x_l2_entry - */ -static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0); - u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket - int i; - - rtl_table_read(q, idx); - for (i= 0; i < 3; i++) - r[i] = sw_r32(rtl_table_data(q, i)); - - rtl_table_release(q); - - rtl839x_fill_l2_entry(r, e); - if (!e->valid) - return 0; - - return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid); -} - -static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0); - int i; - - u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket - - rtl839x_fill_l2_row(r, e); - - for (i= 0; i < 3; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); -} - -static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1 - int i; - - rtl_table_read(q, idx); - for (i= 0; i < 3; i++) - r[i] = sw_r32(rtl_table_data(q, i)); - - rtl_table_release(q); - - rtl839x_fill_l2_entry(r, e); - if (!e->valid) - return 0; - - pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); - - // Return MAC with concatenated VID ac concatenated ID - return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid); -} - -static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1 - int i; - - rtl839x_fill_l2_row(r, e); - - for (i= 0; i < 3; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); -} - -static u64 rtl839x_read_mcast_pmask(int idx) -{ - u64 portmask; - // Read MC_PMSK (2) via register RTL8390_TBL_L2 - struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2); - - rtl_table_read(q, idx); - portmask = sw_r32(rtl_table_data(q, 0)); - portmask <<= 32; - portmask |= sw_r32(rtl_table_data(q, 1)); - portmask >>= 11; // LSB is bit 11 in data registers - rtl_table_release(q); - - return portmask; -} - -static void rtl839x_write_mcast_pmask(int idx, u64 portmask) -{ - // Access MC_PMSK (2) via register RTL8380_TBL_L2 - struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2); - - portmask <<= 11; // LSB is bit 11 in data registers - sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0)); - sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1)); - rtl_table_write(q, idx); - rtl_table_release(q); -} - -static void rtl839x_vlan_profile_setup(int profile) -{ - u32 p[2]; - u32 pmask_id = UNKNOWN_MC_PMASK; - - p[0] = pmask_id; // Use portmaks 0xfff for unknown IPv6 MC flooding - // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding - p[1] = 1 | pmask_id << 1 | pmask_id << 13; - - sw_w32(p[0], RTL839X_VLAN_PROFILE(profile)); - sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4); - - rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff); -} - -u64 rtl839x_traffic_get(int source) -{ - return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source)); -} - -void rtl839x_traffic_set(int source, u64 dest_matrix) -{ - rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source)); -} - -void rtl839x_traffic_enable(int source, int dest) -{ - rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source)); -} - -void rtl839x_traffic_disable(int source, int dest) -{ - rtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source)); -} - -static void rtl839x_l2_learning_setup(void) -{ - /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0) - * address flooding to the reserved entry in the portmask table used - * also for multicast flooding */ - sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK); - - // Limit learning to maximum: 32k entries, after that just flood (bits 0-1) - sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT); - - // Do not trap ARP packets to CPU_PORT - sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL); -} - -static void rtl839x_enable_learning(int port, bool enable) -{ - // Limit learning to maximum: 32k entries - - sw_w32_mask(0x7fff << 2, enable ? (0x7fff << 2) : 0, - RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); -} - -static void rtl839x_enable_flood(int port, bool enable) -{ - /* - * 0: Forward - * 1: Disable - * 2: to CPU - * 3: Copy to CPU - */ - sw_w32_mask(0x3, enable ? 0 : 1, - RTL839X_L2_PORT_LRN_CONSTRT + (port << 2)); -} - -static void rtl839x_enable_mcast_flood(int port, bool enable) -{ - -} - -static void rtl839x_enable_bcast_flood(int port, bool enable) -{ - -} - -static void rtl839x_set_static_move_action(int port, bool forward) -{ - int shift = MV_ACT_PORT_SHIFT(port); - u32 val = forward ? MV_ACT_FORWARD : MV_ACT_DROP; - - sw_w32_mask(MV_ACT_MASK << shift, val << shift, - RTL839X_L2_PORT_STATIC_MV_ACT(port)); -} - -irqreturn_t rtl839x_switch_irq(int irq, void *dev_id) -{ - struct dsa_switch *ds = dev_id; - u32 status = sw_r32(RTL839X_ISR_GLB_SRC); - u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG); - u64 link; - int i; - - /* Clear status */ - rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG); - pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports); - - for (i = 0; i < RTL839X_CPU_PORT; i++) { - if (ports & BIT_ULL(i)) { - link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS); - if (link & BIT_ULL(i)) - dsa_port_phylink_mac_change(ds, i, true); - else - dsa_port_phylink_mac_change(ds, i, false); - } - } - return IRQ_HANDLED; -} - -// TODO: unused -int rtl8390_sds_power(int mac, int val) -{ - u32 offset = (mac == 48) ? 0x0 : 0x100; - u32 mode = val ? 0 : 1; - - pr_debug("In %s: mac %d, set %d\n", __func__, mac, val); - - if ((mac != 48) && (mac != 49)) { - pr_err("%s: not an SFP port: %d\n", __func__, mac); - return -1; - } - - // Set bit 1003. 1000 starts at 7c - sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset); - - return 0; -} - -static int rtl839x_smi_wait_op(int timeout) -{ - int ret = 0; - u32 val; - - ret = readx_poll_timeout(sw_r32, RTL839X_PHYREG_ACCESS_CTRL, - val, !(val & 0x1), 20, timeout); - if (ret) - pr_err("%s: timeout\n", __func__); - - return ret; -} - -int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) -{ - u32 v; - int err = 0; - - if (port > 63 || page > 4095 || reg > 31) - return -ENOTSUPP; - - // Take bug on RTL839x Rev <= C into account - if (port >= RTL839X_CPU_PORT) - return -EIO; - - mutex_lock(&smi_lock); - - sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL); - v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23; - sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - - sw_w32(0x1ff, RTL839X_PHYREG_CTRL); - - v |= 1; - sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - - err = rtl839x_smi_wait_op(100000); - if (err) - goto errout; - - *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff; - -errout: - mutex_unlock(&smi_lock); - return err; -} - -int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) -{ - u32 v; - int err = 0; - - val &= 0xffff; - if (port > 63 || page > 4095 || reg > 31) - return -ENOTSUPP; - - // Take bug on RTL839x Rev <= C into account - if (port >= RTL839X_CPU_PORT) - return -EIO; - - mutex_lock(&smi_lock); - - // Set PHY to access - rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL); - - sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL); - - v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23; - sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - - sw_w32(0x1ff, RTL839X_PHYREG_CTRL); - - v |= BIT(3) | 1; /* Write operation and execute */ - sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - - err = rtl839x_smi_wait_op(100000); - if (err) - goto errout; - - if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2) - err = -EIO; - -errout: - mutex_unlock(&smi_lock); - return err; -} - -/* - * Read an mmd register of the PHY - */ -int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) -{ - int err = 0; - u32 v; - - // Take bug on RTL839x Rev <= C into account - if (port >= RTL839X_CPU_PORT) - return -EIO; - - mutex_lock(&smi_lock); - - // Set PHY to access - sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL); - - // Set MMD device number and register to write to - sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL); - - v = BIT(2) | BIT(0); // MMD-access | EXEC - sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - - err = rtl839x_smi_wait_op(100000); - if (err) - goto errout; - - // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly - *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff); - pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err); - -errout: - mutex_unlock(&smi_lock); - return err; -} - -/* - * Write to an mmd register of the PHY - */ -int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) -{ - int err = 0; - u32 v; - - // Take bug on RTL839x Rev <= C into account - if (port >= RTL839X_CPU_PORT) - return -EIO; - - mutex_lock(&smi_lock); - - // Set PHY to access - rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL); - - // Set data to write - sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL); - - // Set MMD device number and register to write to - sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL); - - v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC - sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); - - err = rtl839x_smi_wait_op(100000); - if (err) - goto errout; - - pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err); - -errout: - mutex_unlock(&smi_lock); - return err; -} - -void rtl8390_get_version(struct rtl838x_switch_priv *priv) -{ - u32 info, model; - - sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO); - info = sw_r32(RTL839X_CHIP_INFO); - - model = sw_r32(RTL839X_MODEL_NAME_INFO); - priv->version = RTL8390_VERSION_A + ((model & 0x3f) >> 1); - - pr_info("RTL839X Chip-Info: %x, version %c\n", info, priv->version); -} - -void rtl839x_vlan_profile_dump(int profile) -{ - u32 p[2]; - - if (profile < 0 || profile > 7) - return; - - p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile)); - p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4); - - pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \ - UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d", - profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff, - (p[0]) & 0xfff); - pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]); -} - -static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) -{ - int i; - u32 cmd = 1 << 16 /* Execute cmd */ - | 0 << 15 /* Read */ - | 5 << 12 /* Table type 0b101 */ - | (msti & 0xfff); - priv->r->exec_tbl0_cmd(cmd); - - for (i = 0; i < 4; i++) - port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); -} - -static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) -{ - int i; - u32 cmd = 1 << 16 /* Execute cmd */ - | 1 << 15 /* Write */ - | 5 << 12 /* Table type 0b101 */ - | (msti & 0xfff); - for (i = 0; i < 4; i++) - sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); - priv->r->exec_tbl0_cmd(cmd); -} - -/* - * Enables or disables the EEE/EEEP capability of a port - */ -void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) -{ - u32 v; - - // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP - if (port >= 48) - return; - - enable = true; - pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); - v = enable ? 0xf : 0x0; - - // Set EEE for 100, 500, 1000MBit and 10GBit - sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port)); - - // Set TX/RX EEE state - v = enable ? 0x3 : 0x0; - sw_w32(v, RTL839X_EEE_CTRL(port)); - - priv->ports[port].eee_enabled = enable; -} - -/* - * Get EEE own capabilities and negotiation result - */ -int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port) -{ - u64 link, a; - - if (port >= 48) - return 0; - - link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS); - if (!(link & BIT_ULL(port))) - return 0; - - if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8)) - e->advertised |= ADVERTISED_100baseT_Full; - - if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10)) - e->advertised |= ADVERTISED_1000baseT_Full; - - a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY); - pr_info("Link partner: %016llx\n", a); - if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) { - e->lp_advertised = ADVERTISED_100baseT_Full; - e->lp_advertised |= ADVERTISED_1000baseT_Full; - return 1; - } - - return 0; -} - -static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable) -{ - int i; - - pr_info("Setting up EEE, state: %d\n", enable); - - // Set wake timer for TX and pause timer both to 0x21 - sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL); - // Set pause wake timer for GIGA-EEE to 0x11 - sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL); - // Set pause wake timer for 10GBit ports to 0x11 - sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL); - - // Setup EEE on all ports - for (i = 0; i < priv->cpu_port; i++) { - if (priv->ports[i].phy) - rtl839x_port_eee_set(priv, i, enable); - } - priv->eee_enabled = enable; -} - -static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index) -{ - int block = index / PIE_BLOCK_SIZE; - - sw_w32_mask(0, BIT(block), RTL839X_ACL_BLK_LOOKUP_CTRL); -} - -/* - * Delete a range of Packet Inspection Engine rules - */ -static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) -{ - u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0); - - pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); - mutex_lock(&priv->reg_mutex); - - // Write from-to and execute bit into control register - sw_w32(v, RTL839X_ACL_CLR_CTRL); - - // Wait until command has completed - do { - } while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0)); - - mutex_unlock(&priv->reg_mutex); - return 0; -} - -/* - * Reads the intermediate representation of the templated match-fields of the - * PIE rule in the pie_rule structure and fills in the raw data fields in the - * raw register space r[]. - * The register space configuration size is identical for the RTL8380/90 and RTL9300, - * however the RTL9310 has 2 more registers / fields and the physical field-ids are different - * on all SoCs - * On the RTL8390 the template mask registers are not word-aligned! - */ -static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) -{ - int i; - enum template_field_id field_type; - u16 data, data_m; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - field_type = t[i]; - data = data_m = 0; - - switch (field_type) { - case TEMPLATE_FIELD_SPM0: - data = pr->spm; - data_m = pr->spm_m; - break; - case TEMPLATE_FIELD_SPM1: - data = pr->spm >> 16; - data_m = pr->spm_m >> 16; - break; - case TEMPLATE_FIELD_SPM2: - data = pr->spm >> 32; - data_m = pr->spm_m >> 32; - break; - case TEMPLATE_FIELD_SPM3: - data = pr->spm >> 48; - data_m = pr->spm_m >> 48; - break; - case TEMPLATE_FIELD_OTAG: - data = pr->otag; - data_m = pr->otag_m; - break; - case TEMPLATE_FIELD_SMAC0: - data = pr->smac[4]; - data = (data << 8) | pr->smac[5]; - data_m = pr->smac_m[4]; - data_m = (data_m << 8) | pr->smac_m[5]; - break; - case TEMPLATE_FIELD_SMAC1: - data = pr->smac[2]; - data = (data << 8) | pr->smac[3]; - data_m = pr->smac_m[2]; - data_m = (data_m << 8) | pr->smac_m[3]; - break; - case TEMPLATE_FIELD_SMAC2: - data = pr->smac[0]; - data = (data << 8) | pr->smac[1]; - data_m = pr->smac_m[0]; - data_m = (data_m << 8) | pr->smac_m[1]; - break; - case TEMPLATE_FIELD_DMAC0: - data = pr->dmac[4]; - data = (data << 8) | pr->dmac[5]; - data_m = pr->dmac_m[4]; - data_m = (data_m << 8) | pr->dmac_m[5]; - break; - case TEMPLATE_FIELD_DMAC1: - data = pr->dmac[2]; - data = (data << 8) | pr->dmac[3]; - data_m = pr->dmac_m[2]; - data_m = (data_m << 8) | pr->dmac_m[3]; - break; - case TEMPLATE_FIELD_DMAC2: - data = pr->dmac[0]; - data = (data << 8) | pr->dmac[1]; - data_m = pr->dmac_m[0]; - data_m = (data_m << 8) | pr->dmac_m[1]; - break; - case TEMPLATE_FIELD_ETHERTYPE: - data = pr->ethertype; - data_m = pr->ethertype_m; - break; - case TEMPLATE_FIELD_ITAG: - data = pr->itag; - data_m = pr->itag_m; - break; - case TEMPLATE_FIELD_SIP0: - if (pr->is_ipv6) { - data = pr->sip6.s6_addr16[7]; - data_m = pr->sip6_m.s6_addr16[7]; - } else { - data = pr->sip; - data_m = pr->sip_m; - } - break; - case TEMPLATE_FIELD_SIP1: - if (pr->is_ipv6) { - data = pr->sip6.s6_addr16[6]; - data_m = pr->sip6_m.s6_addr16[6]; - } else { - data = pr->sip >> 16; - data_m = pr->sip_m >> 16; - } - break; - - case TEMPLATE_FIELD_SIP2: - case TEMPLATE_FIELD_SIP3: - case TEMPLATE_FIELD_SIP4: - case TEMPLATE_FIELD_SIP5: - case TEMPLATE_FIELD_SIP6: - case TEMPLATE_FIELD_SIP7: - data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; - data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; - break; - - case TEMPLATE_FIELD_DIP0: - if (pr->is_ipv6) { - data = pr->dip6.s6_addr16[7]; - data_m = pr->dip6_m.s6_addr16[7]; - } else { - data = pr->dip; - data_m = pr->dip_m; - } - break; - - case TEMPLATE_FIELD_DIP1: - if (pr->is_ipv6) { - data = pr->dip6.s6_addr16[6]; - data_m = pr->dip6_m.s6_addr16[6]; - } else { - data = pr->dip >> 16; - data_m = pr->dip_m >> 16; - } - break; - - case TEMPLATE_FIELD_DIP2: - case TEMPLATE_FIELD_DIP3: - case TEMPLATE_FIELD_DIP4: - case TEMPLATE_FIELD_DIP5: - case TEMPLATE_FIELD_DIP6: - case TEMPLATE_FIELD_DIP7: - data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; - data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; - break; - - case TEMPLATE_FIELD_IP_TOS_PROTO: - data = pr->tos_proto; - data_m = pr->tos_proto_m; - break; - case TEMPLATE_FIELD_L4_SPORT: - data = pr->sport; - data_m = pr->sport_m; - break; - case TEMPLATE_FIELD_L4_DPORT: - data = pr->dport; - data_m = pr->dport_m; - break; - case TEMPLATE_FIELD_ICMP_IGMP: - data = pr->icmp_igmp; - data_m = pr->icmp_igmp_m; - break; - default: - pr_info("%s: unknown field %d\n", __func__, field_type); - } - - // On the RTL8390, the mask fields are not word aligned! - if (!(i % 2)) { - r[5 - i / 2] = data; - r[12 - i / 2] |= ((u32)data_m << 8); - } else { - r[5 - i / 2] |= ((u32)data) << 16; - r[12 - i / 2] |= ((u32)data_m) << 24; - r[11 - i / 2] |= ((u32)data_m) >> 8; - } - } -} - -/* - * Creates the intermediate representation of the templated match-fields of the - * PIE rule in the pie_rule structure by reading the raw data fields in the - * raw register space r[]. - * The register space configuration size is identical for the RTL8380/90 and RTL9300, - * however the RTL9310 has 2 more registers / fields and the physical field-ids - * On the RTL8390 the template mask registers are not word-aligned! - */ -void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) -{ - int i; - enum template_field_id field_type; - u16 data, data_m; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - field_type = t[i]; - if (!(i % 2)) { - data = r[5 - i / 2]; - data_m = r[12 - i / 2]; - } else { - data = r[5 - i / 2] >> 16; - data_m = r[12 - i / 2] >> 16; - } - - switch (field_type) { - case TEMPLATE_FIELD_SPM0: - pr->spm = (pr->spn << 16) | data; - pr->spm_m = (pr->spn << 16) | data_m; - break; - case TEMPLATE_FIELD_SPM1: - pr->spm = data; - pr->spm_m = data_m; - break; - case TEMPLATE_FIELD_OTAG: - pr->otag = data; - pr->otag_m = data_m; - break; - case TEMPLATE_FIELD_SMAC0: - pr->smac[4] = data >> 8; - pr->smac[5] = data; - pr->smac_m[4] = data >> 8; - pr->smac_m[5] = data; - break; - case TEMPLATE_FIELD_SMAC1: - pr->smac[2] = data >> 8; - pr->smac[3] = data; - pr->smac_m[2] = data >> 8; - pr->smac_m[3] = data; - break; - case TEMPLATE_FIELD_SMAC2: - pr->smac[0] = data >> 8; - pr->smac[1] = data; - pr->smac_m[0] = data >> 8; - pr->smac_m[1] = data; - break; - case TEMPLATE_FIELD_DMAC0: - pr->dmac[4] = data >> 8; - pr->dmac[5] = data; - pr->dmac_m[4] = data >> 8; - pr->dmac_m[5] = data; - break; - case TEMPLATE_FIELD_DMAC1: - pr->dmac[2] = data >> 8; - pr->dmac[3] = data; - pr->dmac_m[2] = data >> 8; - pr->dmac_m[3] = data; - break; - case TEMPLATE_FIELD_DMAC2: - pr->dmac[0] = data >> 8; - pr->dmac[1] = data; - pr->dmac_m[0] = data >> 8; - pr->dmac_m[1] = data; - break; - case TEMPLATE_FIELD_ETHERTYPE: - pr->ethertype = data; - pr->ethertype_m = data_m; - break; - case TEMPLATE_FIELD_ITAG: - pr->itag = data; - pr->itag_m = data_m; - break; - case TEMPLATE_FIELD_SIP0: - pr->sip = data; - pr->sip_m = data_m; - break; - case TEMPLATE_FIELD_SIP1: - pr->sip = (pr->sip << 16) | data; - pr->sip_m = (pr->sip << 16) | data_m; - break; - case TEMPLATE_FIELD_SIP2: - pr->is_ipv6 = true; - // Make use of limitiations on the position of the match values - ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2], - r[4 - i / 2], r[3 - i / 2]); - ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2], - r[4 - i / 2], r[3 - i / 2]); - case TEMPLATE_FIELD_SIP3: - case TEMPLATE_FIELD_SIP4: - case TEMPLATE_FIELD_SIP5: - case TEMPLATE_FIELD_SIP6: - case TEMPLATE_FIELD_SIP7: - break; - - case TEMPLATE_FIELD_DIP0: - pr->dip = data; - pr->dip_m = data_m; - break; - - case TEMPLATE_FIELD_DIP1: - pr->dip = (pr->dip << 16) | data; - pr->dip_m = (pr->dip << 16) | data_m; - break; - - case TEMPLATE_FIELD_DIP2: - pr->is_ipv6 = true; - ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2], - r[4 - i / 2], r[3 - i / 2]); - ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2], - r[4 - i / 2], r[3 - i / 2]); - case TEMPLATE_FIELD_DIP3: - case TEMPLATE_FIELD_DIP4: - case TEMPLATE_FIELD_DIP5: - case TEMPLATE_FIELD_DIP6: - case TEMPLATE_FIELD_DIP7: - break; - case TEMPLATE_FIELD_IP_TOS_PROTO: - pr->tos_proto = data; - pr->tos_proto_m = data_m; - break; - case TEMPLATE_FIELD_L4_SPORT: - pr->sport = data; - pr->sport_m = data_m; - break; - case TEMPLATE_FIELD_L4_DPORT: - pr->dport = data; - pr->dport_m = data_m; - break; - case TEMPLATE_FIELD_ICMP_IGMP: - pr->icmp_igmp = data; - pr->icmp_igmp_m = data_m; - break; - default: - pr_info("%s: unknown field %d\n", __func__, field_type); - } - } -} - -static void rtl839x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr) -{ - pr->spmmask_fix = (r[6] >> 30) & 0x3; - pr->spn = (r[6] >> 24) & 0x3f; - pr->mgnt_vlan = (r[6] >> 23) & 1; - pr->dmac_hit_sw = (r[6] >> 22) & 1; - pr->not_first_frag = (r[6] >> 21) & 1; - pr->frame_type_l4 = (r[6] >> 18) & 7; - pr->frame_type = (r[6] >> 16) & 3; - pr->otag_fmt = (r[6] >> 15) & 1; - pr->itag_fmt = (r[6] >> 14) & 1; - pr->otag_exist = (r[6] >> 13) & 1; - pr->itag_exist = (r[6] >> 12) & 1; - pr->frame_type_l2 = (r[6] >> 10) & 3; - pr->tid = (r[6] >> 8) & 3; - - pr->spmmask_fix_m = (r[12] >> 6) & 0x3; - pr->spn_m = r[12] & 0x3f; - pr->mgnt_vlan_m = (r[13] >> 31) & 1; - pr->dmac_hit_sw_m = (r[13] >> 30) & 1; - pr->not_first_frag_m = (r[13] >> 29) & 1; - pr->frame_type_l4_m = (r[13] >> 26) & 7; - pr->frame_type_m = (r[13] >> 24) & 3; - pr->otag_fmt_m = (r[13] >> 23) & 1; - pr->itag_fmt_m = (r[13] >> 22) & 1; - pr->otag_exist_m = (r[13] >> 21) & 1; - pr->itag_exist_m = (r[13] >> 20) & 1; - pr->frame_type_l2_m = (r[13] >> 18) & 3; - pr->tid_m = (r[13] >> 16) & 3; - - pr->valid = r[13] & BIT(15); - pr->cond_not = r[13] & BIT(14); - pr->cond_and1 = r[13] & BIT(13); - pr->cond_and2 = r[13] & BIT(12); -} - -static void rtl839x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) -{ - r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 30; - r[6] |= ((u32) (pr->spn & 0x3f)) << 24; - r[6] |= pr->mgnt_vlan ? BIT(23) : 0; - r[6] |= pr->dmac_hit_sw ? BIT(22) : 0; - r[6] |= pr->not_first_frag ? BIT(21) : 0; - r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18; - r[6] |= ((u32) (pr->frame_type & 0x3)) << 16; - r[6] |= pr->otag_fmt ? BIT(15) : 0; - r[6] |= pr->itag_fmt ? BIT(14) : 0; - r[6] |= pr->otag_exist ? BIT(13) : 0; - r[6] |= pr->itag_exist ? BIT(12) : 0; - r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10; - r[6] |= ((u32) (pr->tid & 0x3)) << 8; - - r[12] |= ((u32) (pr->spmmask_fix_m & 0x3)) << 6; - r[12] |= (u32) (pr->spn_m & 0x3f); - r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0; - r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0; - r[13] |= pr->not_first_frag_m ? BIT(29) : 0; - r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26; - r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24; - r[13] |= pr->otag_fmt_m ? BIT(23) : 0; - r[13] |= pr->itag_fmt_m ? BIT(22) : 0; - r[13] |= pr->otag_exist_m ? BIT(21) : 0; - r[13] |= pr->itag_exist_m ? BIT(20) : 0; - r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18; - r[13] |= ((u32) (pr->tid_m & 0x3)) << 16; - - r[13] |= pr->valid ? BIT(15) : 0; - r[13] |= pr->cond_not ? BIT(14) : 0; - r[13] |= pr->cond_and1 ? BIT(13) : 0; - r[13] |= pr->cond_and2 ? BIT(12) : 0; -} - -static void rtl839x_write_pie_action(u32 r[], struct pie_rule *pr) -{ - if (pr->drop) { - r[13] |= 0x9; // Set ACT_MASK_FWD & FWD_ACT = DROP - r[13] |= BIT(3); - } else { - r[13] |= pr->fwd_sel ? BIT(3) : 0; - r[13] |= pr->fwd_act; - } - r[13] |= pr->bypass_sel ? BIT(11) : 0; - r[13] |= pr->mpls_sel ? BIT(10) : 0; - r[13] |= pr->nopri_sel ? BIT(9) : 0; - r[13] |= pr->ovid_sel ? BIT(8) : 0; - r[13] |= pr->ivid_sel ? BIT(7) : 0; - r[13] |= pr->meter_sel ? BIT(6) : 0; - r[13] |= pr->mir_sel ? BIT(5) : 0; - r[13] |= pr->log_sel ? BIT(4) : 0; - - r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 18; - r[14] |= pr->log_octets ? BIT(17) : 0; - r[14] |= ((u32)(pr->log_data & 0x7ff)) << 4; - r[14] |= (pr->mir_data & 0x3) << 3; - r[14] |= ((u32)(pr->meter_data >> 7)) & 0x7; - r[15] |= (u32)(pr->meter_data) << 26; - r[15] |= ((u32)(pr->ivid_act) << 23) & 0x3; - r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff; - r[15] |= ((u32)(pr->ovid_act) << 6) & 0x3; - r[15] |= ((u32)(pr->ovid_data) >> 4) & 0xff; - r[16] |= ((u32)(pr->ovid_data) & 0xf) << 28; - r[16] |= ((u32)(pr->nopri_data) & 0x7) << 20; - r[16] |= ((u32)(pr->mpls_act) & 0x7) << 20; - r[16] |= ((u32)(pr->mpls_lib_idx) & 0x7) << 20; - r[16] |= pr->bypass_all ? BIT(9) : 0; - r[16] |= pr->bypass_igr_stp ? BIT(8) : 0; - r[16] |= pr->bypass_ibc_sc ? BIT(7) : 0; -} - -static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr) -{ - if (r[13] & BIT(3)) { // ACT_MASK_FWD set, is it a drop? - if ((r[14] & 0x7) == 1) { - pr->drop = true; - } else { - pr->fwd_sel = true; - pr->fwd_act = r[14] & 0x7; - } - } - - pr->bypass_sel = r[13] & BIT(11); - pr->mpls_sel = r[13] & BIT(10); - pr->nopri_sel = r[13] & BIT(9); - pr->ovid_sel = r[13] & BIT(8); - pr->ivid_sel = r[13] & BIT(7); - pr->meter_sel = r[13] & BIT(6); - pr->mir_sel = r[13] & BIT(5); - pr->log_sel = r[13] & BIT(4); - - // TODO: Read in data fields - - pr->bypass_all = r[16] & BIT(9); - pr->bypass_igr_stp = r[16] & BIT(8); - pr->bypass_ibc_sc = r[16] & BIT(7); -} - -void rtl839x_pie_rule_dump_raw(u32 r[]) -{ - pr_info("Raw IACL table entry:\n"); - pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]); - pr_info("Fixed : %06x\n", r[6] >> 8); - pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", - (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8), - (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8), - (r[11] << 24) | (r[12] >> 8)); - pr_info("R[13]: %08x\n", r[13]); - pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff); - pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf); - pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]); -} - -void rtl839x_pie_rule_dump(struct pie_rule *pr) -{ - pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n", - pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel, - pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel); - if (pr->fwd_sel) - pr_info("FWD: %08x\n", pr->fwd_data); - pr_info("TID: %x, %x\n", pr->tid, pr->tid_m); -} - -static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) -{ - // Read IACL table (2) via register 0 - struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2); - u32 r[17]; - int i; - int block = idx / PIE_BLOCK_SIZE; - u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)); - - memset(pr, 0, sizeof(*pr)); - rtl_table_read(q, idx); - for (i = 0; i < 17; i++) - r[i] = sw_r32(rtl_table_data(q, i)); - - rtl_table_release(q); - - rtl839x_read_pie_fixed_fields(r, pr); - if (!pr->valid) - return 0; - - pr_debug("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid); - rtl839x_pie_rule_dump_raw(r); - - rtl839x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]); - - rtl839x_read_pie_action(r, pr); - - return 0; -} - -static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) -{ - // Access IACL table (2) via register 0 - struct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2); - u32 r[17]; - int i; - int block = idx / PIE_BLOCK_SIZE; - u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)); - - pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); - - for (i = 0; i < 17; i++) - r[i] = 0; - - if (!pr->valid) { - rtl_table_write(q, idx); - rtl_table_release(q); - return 0; - } - rtl839x_write_pie_fixed_fields(r, pr); - - pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7); - rtl839x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]); - - rtl839x_write_pie_action(r, pr); - -// rtl839x_pie_rule_dump_raw(r); - - for (i = 0; i < 17; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); - - return 0; -} - -static bool rtl839x_pie_templ_has(int t, enum template_field_id field_type) -{ - int i; - enum template_field_id ft; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - ft = fixed_templates[t][i]; - if (field_type == ft) - return true; - } - - return false; -} - -static int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv, - struct pie_rule *pr, int t, int block) -{ - int i; - - if (!pr->is_ipv6 && pr->sip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP0)) - return -1; - - if (!pr->is_ipv6 && pr->dip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP0)) - return -1; - - if (pr->is_ipv6) { - if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1] - || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3]) - && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) - return -1; - if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1] - || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3]) - && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) - return -1; - } - - if (ether_addr_to_u64(pr->smac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0)) - return -1; - - if (ether_addr_to_u64(pr->dmac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) - return -1; - - // TODO: Check more - - i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); - - if (i >= PIE_BLOCK_SIZE) - return -1; - - return i + PIE_BLOCK_SIZE * block; -} - -static int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) -{ - int idx, block, j, t; - int min_block = 0; - int max_block = priv->n_pie_blocks / 2; - - if (pr->is_egress) { - min_block = max_block; - max_block = priv->n_pie_blocks; - } - - mutex_lock(&priv->pie_mutex); - - for (block = min_block; block < max_block; block++) { - for (j = 0; j < 2; j++) { - t = (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7; - idx = rtl839x_pie_verify_template(priv, pr, t, block); - if (idx >= 0) - break; - } - if (j < 2) - break; - } - - if (block >= priv->n_pie_blocks) { - mutex_unlock(&priv->pie_mutex); - return -EOPNOTSUPP; - } - - set_bit(idx, priv->pie_use_bm); - - pr->valid = true; - pr->tid = j; // Mapped to template number - pr->tid_m = 0x3; - pr->id = idx; - - rtl839x_pie_lookup_enable(priv, idx); - rtl839x_pie_rule_write(priv, idx, pr); - - mutex_unlock(&priv->pie_mutex); - return 0; -} - -static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr) -{ - int idx = pr->id; - - rtl839x_pie_rule_del(priv, idx, idx); - clear_bit(idx, priv->pie_use_bm); -} - -static void rtl839x_pie_init(struct rtl838x_switch_priv *priv) -{ - int i; - u32 template_selectors; - - mutex_init(&priv->pie_mutex); - - // Power on all PIE blocks - for (i = 0; i < priv->n_pie_blocks; i++) - sw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL); - - // Set ingress and egress ACL blocks to 50/50: first Egress block is 9 - sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL); // Writes 9 to cutline field - - // Include IPG in metering - sw_w32(1, RTL839X_METER_GLB_CTRL); - - // Delete all present rules - rtl839x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1); - - // Enable predefined templates 0, 1 for blocks 0-2 - template_selectors = 0 | (1 << 3); - for (i = 0; i < 3; i++) - sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 2, 3 for blocks 3-5 - template_selectors = 2 | (3 << 3); - for (i = 3; i < 6; i++) - sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 1, 4 for blocks 6-8 - template_selectors = 2 | (3 << 3); - for (i = 6; i < 9; i++) - sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 0, 1 for blocks 9-11 - template_selectors = 0 | (1 << 3); - for (i = 9; i < 12; i++) - sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 2, 3 for blocks 12-14 - template_selectors = 2 | (3 << 3); - for (i = 12; i < 15; i++) - sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 1, 4 for blocks 15-17 - template_selectors = 2 | (3 << 3); - for (i = 15; i < 18; i++) - sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i)); -} - -static u32 rtl839x_packet_cntr_read(int counter) -{ - u32 v; - - // Read LOG table (4) via register RTL8390_TBL_0 - struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4); - - pr_debug("In %s, id %d\n", __func__, counter); - rtl_table_read(r, counter / 2); - - // The table has a size of 2 registers - if (counter % 2) - v = sw_r32(rtl_table_data(r, 0)); - else - v = sw_r32(rtl_table_data(r, 1)); - - rtl_table_release(r); - - return v; -} - -static void rtl839x_packet_cntr_clear(int counter) -{ - // Access LOG table (4) via register RTL8390_TBL_0 - struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4); - - pr_debug("In %s, id %d\n", __func__, counter); - // The table has a size of 2 registers - if (counter % 2) - sw_w32(0, rtl_table_data(r, 0)); - else - sw_w32(0, rtl_table_data(r, 1)); - - rtl_table_write(r, counter / 2); - - rtl_table_release(r); -} - -static void rtl839x_route_read(int idx, struct rtl83xx_route *rt) -{ - u64 v; - // Read ROUTING table (2) via register RTL8390_TBL_1 - struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2); - - pr_debug("In %s\n", __func__); - rtl_table_read(r, idx); - - // The table has a size of 2 registers - v = sw_r32(rtl_table_data(r, 0)); - v <<= 32; - v |= sw_r32(rtl_table_data(r, 1)); - rt->switch_mac_id = (v >> 12) & 0xf; - rt->nh.gw = v >> 16; - - rtl_table_release(r); -} - -static void rtl839x_route_write(int idx, struct rtl83xx_route *rt) -{ - u32 v; - - // Read ROUTING table (2) via register RTL8390_TBL_1 - struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2); - - pr_debug("In %s\n", __func__); - sw_w32(rt->nh.gw >> 16, rtl_table_data(r, 0)); - v = rt->nh.gw << 16; - v |= rt->switch_mac_id << 12; - sw_w32(v, rtl_table_data(r, 1)); - rtl_table_write(r, idx); - - rtl_table_release(r); -} - -/* - * Configure the switch's own MAC addresses used when routing packets - */ -static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv) -{ - int i; - struct net_device *dev; - u64 mac; - - pr_debug("%s: got port %08x\n", __func__, (u32)priv->ports[priv->cpu_port].dp); - dev = priv->ports[priv->cpu_port].dp->slave; - mac = ether_addr_to_u64(dev->dev_addr); - - for (i = 0; i < 15; i++) { - mac++; // BUG: VRRP for testing - sw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8); - sw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4); - } -} - -int rtl839x_l3_setup(struct rtl838x_switch_priv *priv) -{ - rtl839x_setup_port_macs(priv); - - return 0; -} - -void rtl839x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) -{ - sw_w32(FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK, - keep_outer ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG) | - FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK, - keep_inner ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG), - RTL839X_VLAN_PORT_TAG_STS_CTRL(port)); -} - -void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) -{ - if (type == PBVLAN_TYPE_INNER) - sw_w32_mask(0x3, mode, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); - else - sw_w32_mask(0x3 << 14, mode << 14, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); -} - -void rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) -{ - if (type == PBVLAN_TYPE_INNER) - sw_w32_mask(0xfff << 2, pvid << 2, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); - else - sw_w32_mask(0xfff << 16, pvid << 16, RTL839X_VLAN_PORT_PB_VLAN + (port << 2)); -} - -static int rtl839x_set_ageing_time(unsigned long msec) -{ - int t = sw_r32(RTL839X_L2_CTRL_1); - - t &= 0x1FFFFF; - t = t * 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */ - pr_debug("L2 AGING time: %d sec\n", t); - - t = (msec * 5 + 2000) / 3000; - t = t > 0x1FFFFF ? 0x1FFFFF : t; - sw_w32_mask(0x1FFFFF, t, RTL839X_L2_CTRL_1); - pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL839X_L2_PORT_AGING_OUT)); - - return 0; -} - -static void rtl839x_set_igr_filter(int port, enum igr_filter state) -{ - sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1), - RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); -} - -static void rtl839x_set_egr_filter(int port, enum egr_filter state) -{ - sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20), - RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2))); -} - -void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) -{ - sw_w32_mask(3 << ((group & 0xf) << 1), algoidx << ((group & 0xf) << 1), - RTL839X_TRK_HASH_IDX_CTRL + ((group >> 4) << 2)); - sw_w32(algomsk, RTL839X_TRK_HASH_CTRL + (algoidx << 2)); -} - -void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action) -{ - switch(type) { - case BPDU: - sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), - RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2)); - break; - case PTP: - sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), - RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2)); - break; - case LLTP: - sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1), - RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2)); - break; - default: - break; - } -} - -const struct rtl838x_reg rtl839x_reg = { - .mask_port_reg_be = rtl839x_mask_port_reg_be, - .set_port_reg_be = rtl839x_set_port_reg_be, - .get_port_reg_be = rtl839x_get_port_reg_be, - .mask_port_reg_le = rtl839x_mask_port_reg_le, - .set_port_reg_le = rtl839x_set_port_reg_le, - .get_port_reg_le = rtl839x_get_port_reg_le, - .stat_port_rst = RTL839X_STAT_PORT_RST, - .stat_rst = RTL839X_STAT_RST, - .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB, - .traffic_enable = rtl839x_traffic_enable, - .traffic_disable = rtl839x_traffic_disable, - .traffic_get = rtl839x_traffic_get, - .traffic_set = rtl839x_traffic_set, - .port_iso_ctrl = rtl839x_port_iso_ctrl, - .l2_ctrl_0 = RTL839X_L2_CTRL_0, - .l2_ctrl_1 = RTL839X_L2_CTRL_1, - .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT, - .set_ageing_time = rtl839x_set_ageing_time, - .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL, - .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, - .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd, - .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd, - .tbl_access_data_0 = rtl839x_tbl_access_data_0, - .isr_glb_src = RTL839X_ISR_GLB_SRC, - .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG, - .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG, - .imr_glb = RTL839X_IMR_GLB, - .vlan_tables_read = rtl839x_vlan_tables_read, - .vlan_set_tagged = rtl839x_vlan_set_tagged, - .vlan_set_untagged = rtl839x_vlan_set_untagged, - .vlan_profile_dump = rtl839x_vlan_profile_dump, - .vlan_profile_setup = rtl839x_vlan_profile_setup, - .vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner, - .vlan_port_keep_tag_set = rtl839x_vlan_port_keep_tag_set, - .vlan_port_pvidmode_set = rtl839x_vlan_port_pvidmode_set, - .vlan_port_pvid_set = rtl839x_vlan_port_pvid_set, - .set_vlan_igr_filter = rtl839x_set_igr_filter, - .set_vlan_egr_filter = rtl839x_set_egr_filter, - .enable_learning = rtl839x_enable_learning, - .enable_flood = rtl839x_enable_flood, - .enable_mcast_flood = rtl839x_enable_mcast_flood, - .enable_bcast_flood = rtl839x_enable_bcast_flood, - .set_static_move_action = rtl839x_set_static_move_action, - .stp_get = rtl839x_stp_get, - .stp_set = rtl839x_stp_set, - .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl, - .mac_port_ctrl = rtl839x_mac_port_ctrl, - .l2_port_new_salrn = rtl839x_l2_port_new_salrn, - .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd, - .mir_ctrl = RTL839X_MIR_CTRL, - .mir_dpm = RTL839X_MIR_DPM_CTRL, - .mir_spm = RTL839X_MIR_SPM_CTRL, - .mac_link_sts = RTL839X_MAC_LINK_STS, - .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS, - .mac_link_spd_sts = rtl839x_mac_link_spd_sts, - .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS, - .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS, - .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash, - .write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash, - .read_cam = rtl839x_read_cam, - .write_cam = rtl839x_write_cam, - .trk_mbr_ctr = rtl839x_trk_mbr_ctr, - .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK, - .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL, - .init_eee = rtl839x_init_eee, - .port_eee_set = rtl839x_port_eee_set, - .eee_port_ability = rtl839x_eee_port_ability, - .l2_hash_seed = rtl839x_l2_hash_seed, - .l2_hash_key = rtl839x_l2_hash_key, - .read_mcast_pmask = rtl839x_read_mcast_pmask, - .write_mcast_pmask = rtl839x_write_mcast_pmask, - .pie_init = rtl839x_pie_init, - .pie_rule_read = rtl839x_pie_rule_read, - .pie_rule_write = rtl839x_pie_rule_write, - .pie_rule_add = rtl839x_pie_rule_add, - .pie_rule_rm = rtl839x_pie_rule_rm, - .l2_learning_setup = rtl839x_l2_learning_setup, - .packet_cntr_read = rtl839x_packet_cntr_read, - .packet_cntr_clear = rtl839x_packet_cntr_clear, - .route_read = rtl839x_route_read, - .route_write = rtl839x_route_write, - .l3_setup = rtl839x_l3_setup, - .set_distribution_algorithm = rtl839x_set_distribution_algorithm, - .set_receive_management_action = rtl839x_set_receive_management_action, -}; diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h deleted file mode 100644 index 485d0e8a7e..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _NET_DSA_RTL83XX_H -#define _NET_DSA_RTL83XX_H - -#include -#include "rtl838x.h" - - -#define RTL8380_VERSION_A 'A' -#define RTL8390_VERSION_A 'A' -#define RTL8380_VERSION_B 'B' - -struct fdb_update_work { - struct work_struct work; - struct net_device *ndev; - u64 macs[]; -}; - -#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} -struct rtl83xx_mib_desc { - unsigned int size; - unsigned int offset; - const char *name; -}; - -/* API for switch table access */ -struct table_reg { - u16 addr; - u16 data; - u8 max_data; - u8 c_bit; - u8 t_bit; - u8 rmode; - u8 tbl; - struct mutex lock; -}; - -#define TBL_DESC(_addr, _data, _max_data, _c_bit, _t_bit, _rmode) \ - { .addr = _addr, .data = _data, .max_data = _max_data, .c_bit = _c_bit, \ - .t_bit = _t_bit, .rmode = _rmode \ - } - -typedef enum { - RTL8380_TBL_L2 = 0, - RTL8380_TBL_0, - RTL8380_TBL_1, - RTL8390_TBL_L2, - RTL8390_TBL_0, - RTL8390_TBL_1, - RTL8390_TBL_2, - RTL9300_TBL_L2, - RTL9300_TBL_0, - RTL9300_TBL_1, - RTL9300_TBL_2, - RTL9300_TBL_HSB, - RTL9300_TBL_HSA, - RTL9310_TBL_0, - RTL9310_TBL_1, - RTL9310_TBL_2, - RTL9310_TBL_3, - RTL9310_TBL_4, - RTL9310_TBL_5, - RTL_TBL_END -} rtl838x_tbl_reg_t; - -void rtl_table_init(void); -struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t); -void rtl_table_release(struct table_reg *r); -int rtl_table_read(struct table_reg *r, int idx); -int rtl_table_write(struct table_reg *r, int idx); -inline u16 rtl_table_data(struct table_reg *r, int i); -inline u32 rtl_table_data_r(struct table_reg *r, int i); -inline void rtl_table_data_w(struct table_reg *r, u32 v, int i); - -void __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv); - -int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv); - -int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv); - -int read_phy(u32 port, u32 page, u32 reg, u32 *val); -int write_phy(u32 port, u32 page, u32 reg, u32 val); - -/* Port register accessor functions for the RTL839x and RTL931X SoCs */ -void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg); -u64 rtl839x_get_port_reg_be(int reg); -void rtl839x_set_port_reg_be(u64 set, int reg); -void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg); -void rtl839x_set_port_reg_le(u64 set, int reg); -u64 rtl839x_get_port_reg_le(int reg); - -/* Port register accessor functions for the RTL838x and RTL930X SoCs */ -void rtl838x_mask_port_reg(u64 clear, u64 set, int reg); -void rtl838x_set_port_reg(u64 set, int reg); -u64 rtl838x_get_port_reg(int reg); - -/* RTL838x-specific */ -u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed); -irqreturn_t rtl838x_switch_irq(int irq, void *dev_id); -void rtl8380_get_version(struct rtl838x_switch_priv *priv); -void rtl838x_vlan_profile_dump(int index); -int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg); -void rtl8380_sds_rst(int mac); -int rtl8380_sds_power(int mac, int val); -void rtl838x_print_matrix(void); - -/* RTL839x-specific */ -u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed); -irqreturn_t rtl839x_switch_irq(int irq, void *dev_id); -void rtl8390_get_version(struct rtl838x_switch_priv *priv); -void rtl839x_vlan_profile_dump(int index); -int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val); -void rtl839x_exec_tbl2_cmd(u32 cmd); -void rtl839x_print_matrix(void); - -/* RTL930x-specific */ -u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed); -irqreturn_t rtl930x_switch_irq(int irq, void *dev_id); -irqreturn_t rtl839x_switch_irq(int irq, void *dev_id); -void rtl930x_vlan_profile_dump(int index); -int rtl9300_sds_power(int mac, int val); -void rtl9300_sds_rst(int sds_num, u32 mode); -int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode); -void rtl930x_print_matrix(void); - -/* RTL931x-specific */ -irqreturn_t rtl931x_switch_irq(int irq, void *dev_id); -int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode); -int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode); -void rtl931x_sds_init(u32 sds, phy_interface_t mode); - -int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info); -int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port); - -#endif /* _NET_DSA_RTL83XX_H */ - diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c deleted file mode 100644 index 5dde8353e2..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c +++ /dev/null @@ -1,2560 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include - -#include "rtl83xx.h" - -#define RTL930X_VLAN_PORT_TAG_STS_INTERNAL 0x0 -#define RTL930X_VLAN_PORT_TAG_STS_UNTAG 0x1 -#define RTL930X_VLAN_PORT_TAG_STS_TAGGED 0x2 -#define RTL930X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3 - -#define RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE 0xCE24 -/* port 0-28 */ -#define RTL930X_VLAN_PORT_TAG_STS_CTRL(port) \ - RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2) -#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK GENMASK(7,6) -#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK GENMASK(5,4) -#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3) -#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2) -#define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1) -#define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0) - -extern struct mutex smi_lock; -extern struct rtl83xx_soc_info soc_info; - -/* Definition of the RTL930X-specific template field IDs as used in the PIE */ -enum template_field_id { - TEMPLATE_FIELD_SPM0 = 0, // Source portmask ports 0-15 - TEMPLATE_FIELD_SPM1 = 1, // Source portmask ports 16-31 - TEMPLATE_FIELD_DMAC0 = 2, // Destination MAC [15:0] - TEMPLATE_FIELD_DMAC1 = 3, // Destination MAC [31:16] - TEMPLATE_FIELD_DMAC2 = 4, // Destination MAC [47:32] - TEMPLATE_FIELD_SMAC0 = 5, // Source MAC [15:0] - TEMPLATE_FIELD_SMAC1 = 6, // Source MAC [31:16] - TEMPLATE_FIELD_SMAC2 = 7, // Source MAC [47:32] - TEMPLATE_FIELD_ETHERTYPE = 8, // Ethernet frame type field - TEMPLATE_FIELD_OTAG = 9, - TEMPLATE_FIELD_ITAG = 10, - TEMPLATE_FIELD_SIP0 = 11, - TEMPLATE_FIELD_SIP1 = 12, - TEMPLATE_FIELD_DIP0 = 13, - TEMPLATE_FIELD_DIP1 = 14, - TEMPLATE_FIELD_IP_TOS_PROTO = 15, - TEMPLATE_FIELD_L4_SPORT = 16, - TEMPLATE_FIELD_L4_DPORT = 17, - TEMPLATE_FIELD_L34_HEADER = 18, - TEMPLATE_FIELD_TCP_INFO = 19, - TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20, - TEMPLATE_FIELD_FIELD_SELECTOR_0 = 21, - TEMPLATE_FIELD_FIELD_SELECTOR_1 = 22, - TEMPLATE_FIELD_FIELD_SELECTOR_2 = 23, - TEMPLATE_FIELD_FIELD_SELECTOR_3 = 24, - TEMPLATE_FIELD_FIELD_SELECTOR_4 = 25, - TEMPLATE_FIELD_FIELD_SELECTOR_5 = 26, - TEMPLATE_FIELD_SIP2 = 27, - TEMPLATE_FIELD_SIP3 = 28, - TEMPLATE_FIELD_SIP4 = 29, - TEMPLATE_FIELD_SIP5 = 30, - TEMPLATE_FIELD_SIP6 = 31, - TEMPLATE_FIELD_SIP7 = 32, - TEMPLATE_FIELD_DIP2 = 33, - TEMPLATE_FIELD_DIP3 = 34, - TEMPLATE_FIELD_DIP4 = 35, - TEMPLATE_FIELD_DIP5 = 36, - TEMPLATE_FIELD_DIP6 = 37, - TEMPLATE_FIELD_DIP7 = 38, - TEMPLATE_FIELD_PKT_INFO = 39, - TEMPLATE_FIELD_FLOW_LABEL = 40, - TEMPLATE_FIELD_DSAP_SSAP = 41, - TEMPLATE_FIELD_SNAP_OUI = 42, - TEMPLATE_FIELD_FWD_VID = 43, - TEMPLATE_FIELD_RANGE_CHK = 44, - TEMPLATE_FIELD_VLAN_GMSK = 45, // VLAN Group Mask/IP range check - TEMPLATE_FIELD_DLP = 46, - TEMPLATE_FIELD_META_DATA = 47, - TEMPLATE_FIELD_SRC_FWD_VID = 48, - TEMPLATE_FIELD_SLP = 49, -}; - -/* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in - * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag: - */ -#define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG - -// Number of fixed templates predefined in the RTL9300 SoC -#define N_FIXED_TEMPLATES 5 -// RTL9300 specific predefined templates -static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = -{ - { - TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, - TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2, - TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP, - TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1 - }, { - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, - TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO, - TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN, - TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1 - }, { - TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, - TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO, - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, - TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT - }, { - TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2, - TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5, - TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO, - TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT - }, { - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2, - TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5, - TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN, - TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1 - }, -}; - -void rtl930x_print_matrix(void) -{ - int i; - struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); - - for (i = 0; i < 29; i++) { - rtl_table_read(r, i); - pr_debug("> %08x\n", sw_r32(rtl_table_data(r, 0))); - } - rtl_table_release(r); -} - -inline void rtl930x_exec_tbl0_cmd(u32 cmd) -{ - sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0); - do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17)); -} - -inline void rtl930x_exec_tbl1_cmd(u32 cmd) -{ - sw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1); - do { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17)); -} - -inline int rtl930x_tbl_access_data_0(int i) -{ - return RTL930X_TBL_ACCESS_DATA_0(i); -} - -static inline int rtl930x_l2_port_new_salrn(int p) -{ - return RTL930X_L2_PORT_SALRN(p); -} - -static inline int rtl930x_l2_port_new_sa_fwd(int p) -{ - // TODO: The definition of the fields changed, because of the master-cpu in a stack - return RTL930X_L2_PORT_NEW_SA_FWD(p); -} - -inline static int rtl930x_trk_mbr_ctr(int group) -{ - return RTL930X_TRK_MBR_CTRL + (group << 2); -} - -static void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) -{ - u32 v, w; - // Read VLAN table (1) via register 0 - struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); - - rtl_table_read(r, vlan); - v = sw_r32(rtl_table_data(r, 0)); - w = sw_r32(rtl_table_data(r, 1)); - pr_debug("VLAN_READ %d: %08x %08x\n", vlan, v, w); - rtl_table_release(r); - - info->tagged_ports = v >> 3; - info->profile_id = (w >> 24) & 7; - info->hash_mc_fid = !!(w & BIT(27)); - info->hash_uc_fid = !!(w & BIT(28)); - info->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7); - - // Read UNTAG table via table register 2 - r = rtl_table_get(RTL9300_TBL_2, 0); - rtl_table_read(r, vlan); - v = sw_r32(rtl_table_data(r, 0)); - rtl_table_release(r); - - info->untagged_ports = v >> 3; -} - -static void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) -{ - u32 v, w; - // Access VLAN table (1) via register 0 - struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1); - - v = info->tagged_ports << 3; - v |= ((u32)info->fid) >> 3; - - w = ((u32)info->fid) << 29; - w |= info->hash_mc_fid ? BIT(27) : 0; - w |= info->hash_uc_fid ? BIT(28) : 0; - w |= info->profile_id << 24; - - sw_w32(v, rtl_table_data(r, 0)); - sw_w32(w, rtl_table_data(r, 1)); - - rtl_table_write(r, vlan); - rtl_table_release(r); -} - -void rtl930x_vlan_profile_dump(int profile) -{ - u32 p[5]; - - if (profile < 0 || profile > 7) - return; - - p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile)); - p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4); - p[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF; - p[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF; - p[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF; - - pr_info("VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x", - profile, p[0] & (3 << 21), p[2], p[3], p[4]); - pr_info(" Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\n", - p[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n', - p[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n'); - pr_info(" Bridge enabled: IPv4 MC %c, IPv6 MC %c,\n", - p[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n'); - pr_info("VLAN profile %d: raw %08x %08x %08x %08x %08x\n", - profile, p[0], p[1], p[2], p[3], p[4]); -} - -static void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask) -{ - struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0); - - sw_w32(portmask << 3, rtl_table_data(r, 0)); - rtl_table_write(r, vlan); - rtl_table_release(r); -} - -/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer - */ -static void rtl930x_vlan_fwd_on_inner(int port, bool is_set) -{ - // Always set all tag modes to fwd based on either inner or outer tag - if (is_set) - sw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2)); - else - sw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2)); -} - -static void rtl930x_vlan_profile_setup(int profile) -{ - u32 p[5]; - - pr_info("In %s\n", __func__); - p[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile)); - p[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4); - - // Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic - p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); - p[2] = 0x1fffffff; // L2 unknown MC flooding portmask all ports, including the CPU-port - p[3] = 0x1fffffff; // IPv4 unknown MC flooding portmask - p[4] = 0x1fffffff; // IPv6 unknown MC flooding portmask - - sw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile)); - sw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4); - sw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8); - sw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12); - sw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16); -} - -static void rtl930x_l2_learning_setup(void) -{ - // Portmask for flooding broadcast traffic - sw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK); - - // Portmask for flooding unicast traffic with unknown destination - sw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK); - - // Limit learning to maximum: 32k entries, after that just flood (bits 0-1) - sw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL); -} - -static void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) -{ - int i; - u32 cmd = 1 << 17 /* Execute cmd */ - | 0 << 16 /* Read */ - | 4 << 12 /* Table type 0b10 */ - | (msti & 0xfff); - priv->r->exec_tbl0_cmd(cmd); - - for (i = 0; i < 2; i++) - port_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i)); - pr_debug("MSTI: %d STATE: %08x, %08x\n", msti, port_state[0], port_state[1]); -} - -static void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) -{ - int i; - u32 cmd = 1 << 17 /* Execute cmd */ - | 1 << 16 /* Write */ - | 4 << 12 /* Table type 4 */ - | (msti & 0xfff); - - for (i = 0; i < 2; i++) - sw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i)); - priv->r->exec_tbl0_cmd(cmd); -} - -static inline int rtl930x_mac_force_mode_ctrl(int p) -{ - return RTL930X_MAC_FORCE_MODE_CTRL + (p << 2); -} - -static inline int rtl930x_mac_port_ctrl(int p) -{ - return RTL930X_MAC_L2_PORT_CTRL(p); -} - -static inline int rtl930x_mac_link_spd_sts(int p) -{ - return RTL930X_MAC_LINK_SPD_STS(p); -} - -static u64 rtl930x_l2_hash_seed(u64 mac, u32 vid) -{ - u64 v = vid; - - v <<= 48; - v |= mac; - - return v; -} - -/* - * Calculate both the block 0 and the block 1 hash by applyingthe same hash - * algorithm as the one used currently by the ASIC to the seed, and return - * both hashes in the lower and higher word of the return value since only 12 bit of - * the hash are significant - */ -static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) -{ - u32 k0, k1, h1, h2, h; - - k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) - ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) - ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff)); - - h1 = (seed >> 11) & 0x7ff; - h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); - - h2 = (seed >> 33) & 0x7ff; - h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f); - - k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2 - ^ ((seed >> 22) & 0x7ff) ^ h1 - ^ (seed & 0x7ff)); - - // Algorithm choice for block 0 - if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) - h = k1; - else - h = k0; - - /* Algorithm choice for block 1 - * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second - * half of hash-space - * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket - * divided by 2 to divide the hash space in 2 - */ - if (sw_r32(RTL930X_L2_CTRL) & BIT(1)) - h |= (k1 + 2048) << 16; - else - h |= (k0 + 2048) << 16; - - return h; -} - -/* - * Fills an L2 entry structure from the SoC registers - */ -static void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) -{ - pr_debug("In %s valid?\n", __func__); - e->valid = !!(r[2] & BIT(31)); - if (!e->valid) - return; - - pr_debug("In %s is valid\n", __func__); - e->is_ip_mc = false; - e->is_ipv6_mc = false; - - // TODO: Is there not a function to copy directly MAC memory? - e->mac[0] = (r[0] >> 24); - e->mac[1] = (r[0] >> 16); - e->mac[2] = (r[0] >> 8); - e->mac[3] = r[0]; - e->mac[4] = (r[1] >> 24); - e->mac[5] = (r[1] >> 16); - - e->next_hop = !!(r[2] & BIT(12)); - e->rvid = r[1] & 0xfff; - - /* Is it a unicast entry? check multicast bit */ - if (!(e->mac[0] & 1)) { - e->type = L2_UNICAST; - e->is_static = !!(r[2] & BIT(14)); - e->port = (r[2] >> 20) & 0x3ff; - // Check for trunk port - if (r[2] & BIT(30)) { - e->is_trunk = true; - e->stack_dev = (e->port >> 9) & 1; - e->trunk = e->port & 0x3f; - } else { - e->is_trunk = false; - e->stack_dev = (e->port >> 6) & 0xf; - e->port = e->port & 0x3f; - } - - e->block_da = !!(r[2] & BIT(15)); - e->block_sa = !!(r[2] & BIT(16)); - e->suspended = !!(r[2] & BIT(13)); - e->age = (r[2] >> 17) & 3; - e->valid = true; - // the UC_VID field in hardware is used for the VID or for the route id - if (e->next_hop) { - e->nh_route_id = r[2] & 0x7ff; - e->vid = 0; - } else { - e->vid = r[2] & 0xfff; - e->nh_route_id = 0; - } - } else { - e->valid = true; - e->type = L2_MULTICAST; - e->mc_portmask_index = (r[2] >> 16) & 0x3ff; - } -} - -/* - * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry - */ -static void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) -{ - u32 port; - - if (!e->valid) { - r[0] = r[1] = r[2] = 0; - return; - } - - r[2] = BIT(31); // Set valid bit - - r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16 - | ((u32)e->mac[2]) << 8 | ((u32)e->mac[3]); - r[1] = ((u32)e->mac[4]) << 24 | ((u32)e->mac[5]) << 16; - - r[2] |= e->next_hop ? BIT(12) : 0; - - if (e->type == L2_UNICAST) { - r[2] |= e->is_static ? BIT(14) : 0; - r[1] |= e->rvid & 0xfff; - r[2] |= (e->port & 0x3ff) << 20; - if (e->is_trunk) { - r[2] |= BIT(30); - port = e->stack_dev << 9 | (e->port & 0x3f); - } else { - port = (e->stack_dev & 0xf) << 6; - port |= e->port & 0x3f; - } - r[2] |= port << 20; - r[2] |= e->block_da ? BIT(15) : 0; - r[2] |= e->block_sa ? BIT(17) : 0; - r[2] |= e->suspended ? BIT(13) : 0; - r[2] |= (e->age & 0x3) << 17; - // the UC_VID field in hardware is used for the VID or for the route id - if (e->next_hop) - r[2] |= e->nh_route_id & 0x7ff; - else - r[2] |= e->vid & 0xfff; - } else { // L2_MULTICAST - r[2] |= (e->mc_portmask_index & 0x3ff) << 16; - r[2] |= e->mc_mac_index & 0x7ff; - } -} - -/* - * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table - * hash is the id of the bucket and pos is the position of the entry in that bucket - * The data read from the SoC is filled into rtl838x_l2_entry - */ -static u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0); - u32 idx; - int i; - u64 mac; - u64 seed; - - pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos); - - /* On the RTL93xx, 2 different hash algorithms are used making it a total of - * 8 buckets that need to be searched, 4 for each hash-half - * Use second hash space when bucket is between 4 and 8 */ - if (pos >= 4) { - pos -= 4; - hash >>= 16; - } else { - hash &= 0xffff; - } - - idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket - pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos); - - rtl_table_read(q, idx); - for (i = 0; i < 3; i++) - r[i] = sw_r32(rtl_table_data(q, i)); - - rtl_table_release(q); - - rtl930x_fill_l2_entry(r, e); - - pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop); - if (!e->valid) - return 0; - - mac = ((u64)e->mac[0]) << 40 | ((u64)e->mac[1]) << 32 | ((u64)e->mac[2]) << 24 - | ((u64)e->mac[3]) << 16 | ((u64)e->mac[4]) << 8 | ((u64)e->mac[5]); - - seed = rtl930x_l2_hash_seed(mac, e->rvid); - pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed); - // return vid with concatenated mac as unique id - return seed; -} - -static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0); - u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket - int i; - - pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos); - pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx, - e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]); - - rtl930x_fill_l2_row(r, e); - - for (i= 0; i < 3; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); -} - -static u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); - int i; - - rtl_table_read(q, idx); - for (i= 0; i < 3; i++) - r[i] = sw_r32(rtl_table_data(q, i)); - - rtl_table_release(q); - - rtl930x_fill_l2_entry(r, e); - if (!e->valid) - return 0; - - // return mac with concatenated vid as unique id - return ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid; -} - -static void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e) -{ - u32 r[3]; - struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); // Access L2 Table 1 - int i; - - rtl930x_fill_l2_row(r, e); - - for (i= 0; i < 3; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); -} - -static u64 rtl930x_read_mcast_pmask(int idx) -{ - u32 portmask; - // Read MC_PORTMASK (2) via register RTL9300_TBL_L2 - struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2); - - rtl_table_read(q, idx); - portmask = sw_r32(rtl_table_data(q, 0)); - portmask >>= 3; - rtl_table_release(q); - - pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, portmask); - return portmask; -} - -static void rtl930x_write_mcast_pmask(int idx, u64 portmask) -{ - u32 pm = portmask; - - // Access MC_PORTMASK (2) via register RTL9300_TBL_L2 - struct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2); - - pr_debug("%s: Index idx %d has portmask %08x\n", __func__, idx, pm); - pm <<= 3; - sw_w32(pm, rtl_table_data(q, 0)); - rtl_table_write(q, idx); - rtl_table_release(q); -} - -u64 rtl930x_traffic_get(int source) -{ - u32 v; - struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); - - rtl_table_read(r, source); - v = sw_r32(rtl_table_data(r, 0)); - rtl_table_release(r); - return v >> 3; -} - -/* - * Enable traffic between a source port and a destination port matrix - */ -void rtl930x_traffic_set(int source, u64 dest_matrix) -{ - struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); - - sw_w32((dest_matrix << 3), rtl_table_data(r, 0)); - rtl_table_write(r, source); - rtl_table_release(r); -} - -void rtl930x_traffic_enable(int source, int dest) -{ - struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); - rtl_table_read(r, source); - sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0)); - rtl_table_write(r, source); - rtl_table_release(r); -} - -void rtl930x_traffic_disable(int source, int dest) -{ - struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6); - rtl_table_read(r, source); - sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0)); - rtl_table_write(r, source); - rtl_table_release(r); -} - -void rtl9300_dump_debug(void) -{ - int i; - u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0; - - for (i = 0; i < 10; i ++) { - pr_info("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8, - sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), - sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28)); - r += 32; - } - pr_info("# %08x %08x %08x %08x %08x\n", - sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16)); - rtl930x_print_matrix(); - pr_info("RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\n", - sw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL) - - ); -} - -irqreturn_t rtl930x_switch_irq(int irq, void *dev_id) -{ - struct dsa_switch *ds = dev_id; - u32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG); - u32 link; - int i; - - /* Clear status */ - sw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG); - - for (i = 0; i < 28; i++) { - if (ports & BIT(i)) { - /* Read the register twice because of issues with latency at least - * with the external RTL8226 PHY on the XGS1210 */ - link = sw_r32(RTL930X_MAC_LINK_STS); - link = sw_r32(RTL930X_MAC_LINK_STS); - if (link & BIT(i)) - dsa_port_phylink_mac_change(ds, i, true); - else - dsa_port_phylink_mac_change(ds, i, false); - } - } - - return IRQ_HANDLED; -} - -int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val) -{ - u32 v; - int err = 0; - - pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, val); - - if (port > 63 || page > 4095 || reg > 31) - return -ENOTSUPP; - - val &= 0xffff; - mutex_lock(&smi_lock); - - sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0); - sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); - v = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0); - sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); - - do { - v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); - } while (v & 0x1); - - if (v & 0x2) - err = -EIO; - - mutex_unlock(&smi_lock); - - return err; -} - -int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val) -{ - u32 v; - int err = 0; - - if (port > 63 || page > 4095 || reg > 31) - return -ENOTSUPP; - - mutex_lock(&smi_lock); - - sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); - v = reg << 20 | page << 3 | 0x1f << 15 | 1; - sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); - - do { - v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); - } while ( v & 0x1); - - if (v & BIT(25)) { - pr_debug("Error reading phy %d, register %d\n", port, reg); - err = -EIO; - } - *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff); - - pr_debug("%s: port %d, page: %d, reg: %x, val: %x\n", __func__, port, page, reg, *val); - - mutex_unlock(&smi_lock); - - return err; -} - -/* - * Write to an mmd register of the PHY - */ -int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) -{ - int err = 0; - u32 v; - - mutex_lock(&smi_lock); - - // Set PHY to access - sw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0); - - // Set data to write - sw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); - - // Set MMD device number and register to write to - sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3); - - v = BIT(2) | BIT(1) | BIT(0); // WRITE | MMD-access | EXEC - sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); - - do { - v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); - } while (v & BIT(0)); - - pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err); - mutex_unlock(&smi_lock); - return err; -} - -/* - * Read an mmd register of the PHY - */ -int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) -{ - int err = 0; - u32 v; - - mutex_lock(&smi_lock); - - // Set PHY to access - sw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2); - - // Set MMD device number and register to write to - sw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3); - - v = BIT(1) | BIT(0); // MMD-access | EXEC - sw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1); - - do { - v = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1); - } while (v & BIT(0)); - // There is no error-checking via BIT 25 of v, as it does not seem to be set correctly - *val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff); - pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err); - - mutex_unlock(&smi_lock); - - return err; -} - -/* - * Calculate both the block 0 and the block 1 hash, and return in - * lower and higher word of the return value since only 12 bit of - * the hash are significant - */ -u32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed) -{ - u32 k0, k1, h1, h2, h; - - k0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) - ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) - ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff)); - - h1 = (seed >> 11) & 0x7ff; - h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); - - h2 = (seed >> 33) & 0x7ff; - h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f); - - k1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2 - ^ ((seed >> 22) & 0x7ff) ^ h1 - ^ (seed & 0x7ff)); - - // Algorithm choice for block 0 - if (sw_r32(RTL930X_L2_CTRL) & BIT(0)) - h = k1; - else - h = k0; - - /* Algorithm choice for block 1 - * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second - * half of hash-space - * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket - * divided by 2 to divide the hash space in 2 - */ - if (sw_r32(RTL930X_L2_CTRL) & BIT(1)) - h |= (k1 + 2048) << 16; - else - h |= (k0 + 2048) << 16; - - return h; -} - -/* - * Enables or disables the EEE/EEEP capability of a port - */ -void rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable) -{ - u32 v; - - // This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP - if (port >= 26) - return; - - pr_debug("In %s: setting port %d to %d\n", __func__, port, enable); - v = enable ? 0x3f : 0x0; - - // Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit - sw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port)); - - // Set TX/RX EEE state - v = enable ? 0x3 : 0x0; - sw_w32(v, RTL930X_EEE_CTRL(port)); - - priv->ports[port].eee_enabled = enable; -} - -/* - * Get EEE own capabilities and negotiation result - */ -int rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port) -{ - u32 link, a; - - if (port >= 26) - return -ENOTSUPP; - - pr_info("In %s, port %d\n", __func__, port); - link = sw_r32(RTL930X_MAC_LINK_STS); - link = sw_r32(RTL930X_MAC_LINK_STS); - if (!(link & BIT(port))) - return 0; - - pr_info("Setting advertised\n"); - if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10)) - e->advertised |= ADVERTISED_100baseT_Full; - - if (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(12)) - e->advertised |= ADVERTISED_1000baseT_Full; - - if (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) { - pr_info("ADVERTISING 2.5G EEE\n"); - e->advertised |= ADVERTISED_2500baseX_Full; - } - - if (priv->ports[port].is10G && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(15)) - e->advertised |= ADVERTISED_10000baseT_Full; - - a = sw_r32(RTL930X_MAC_EEE_ABLTY); - a = sw_r32(RTL930X_MAC_EEE_ABLTY); - pr_info("Link partner: %08x\n", a); - if (a & BIT(port)) { - e->lp_advertised = ADVERTISED_100baseT_Full; - e->lp_advertised |= ADVERTISED_1000baseT_Full; - if (priv->ports[port].is2G5) - e->lp_advertised |= ADVERTISED_2500baseX_Full; - if (priv->ports[port].is10G) - e->lp_advertised |= ADVERTISED_10000baseT_Full; - } - - // Read 2x to clear latched state - a = sw_r32(RTL930X_EEEP_PORT_CTRL(port)); - a = sw_r32(RTL930X_EEEP_PORT_CTRL(port)); - pr_info("%s RTL930X_EEEP_PORT_CTRL: %08x\n", __func__, a); - - return 0; -} - -static void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable) -{ - int i; - - pr_info("Setting up EEE, state: %d\n", enable); - - // Setup EEE on all ports - for (i = 0; i < priv->cpu_port; i++) { - if (priv->ports[i].phy) - rtl930x_port_eee_set(priv, i, enable); - } - - priv->eee_enabled = enable; -} -#define HASH_PICK(val, lsb, len) ((val & (((1 << len) - 1) << lsb)) >> lsb) - -static u32 rtl930x_l3_hash4(u32 ip, int algorithm, bool move_dip) -{ - u32 rows[4]; - u32 hash; - u32 s0, s1, pH; - - memset(rows, 0, sizeof(rows)); - - rows[0] = HASH_PICK(ip, 27, 5); - rows[1] = HASH_PICK(ip, 18, 9); - rows[2] = HASH_PICK(ip, 9, 9); - - if (!move_dip) - rows[3] = HASH_PICK(ip, 0, 9); - - if (!algorithm) { - hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3]; - } else { - s0 = rows[0] + rows[1] + rows[2]; - s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9); - pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9); - hash = pH ^ rows[3]; - } - return hash; -} - -static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip) -{ - u32 rows[16]; - u32 hash; - u32 s0, s1, pH; - - rows[0] = (HASH_PICK(ip6->s6_addr[0], 6, 2) << 0); - rows[1] = (HASH_PICK(ip6->s6_addr[0], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[1], 5, 3); - rows[2] = (HASH_PICK(ip6->s6_addr[1], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[2], 4, 4); - rows[3] = (HASH_PICK(ip6->s6_addr[2], 0, 4) << 5) | HASH_PICK(ip6->s6_addr[3], 3, 5); - rows[4] = (HASH_PICK(ip6->s6_addr[3], 0, 3) << 6) | HASH_PICK(ip6->s6_addr[4], 2, 6); - rows[5] = (HASH_PICK(ip6->s6_addr[4], 0, 2) << 7) | HASH_PICK(ip6->s6_addr[5], 1, 7); - rows[6] = (HASH_PICK(ip6->s6_addr[5], 0, 1) << 8) | HASH_PICK(ip6->s6_addr[6], 0, 8); - rows[7] = (HASH_PICK(ip6->s6_addr[7], 0, 8) << 1) | HASH_PICK(ip6->s6_addr[8], 7, 1); - rows[8] = (HASH_PICK(ip6->s6_addr[8], 0, 7) << 2) | HASH_PICK(ip6->s6_addr[9], 6, 2); - rows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3); - rows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4); - if (!algorithm) { - rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5) - | (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0); - rows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) - | (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0); - rows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) - | (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0); - if (!move_dip) { - rows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) - | (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0); - } - hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6] - ^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ rows[12] - ^ rows[13] ^ rows[14]; - } else { - rows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5); - rows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0); - rows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6) - | HASH_PICK(ip6->s6_addr[13], 2, 6); - rows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7) - | HASH_PICK(ip6->s6_addr[14], 1, 7); - if (!move_dip) { - rows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8) - | (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0); - } - s0 = rows[12] + rows[13] + rows[14]; - s1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9); - pH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9); - hash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6] - ^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ pH ^ rows[15]; - } - return hash; -} - -/* - * Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table - * We currently only support IPv4 and IPv6 unicast route - */ -static void rtl930x_route_read(int idx, struct rtl83xx_route *rt) -{ - u32 v, ip4_m; - bool host_route, default_route; - struct in6_addr ip6_m; - - // Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 - struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2); - - rtl_table_read(r, idx); - // The table has a size of 11 registers - rt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31)); - if (!rt->attr.valid) - goto out; - - rt->attr.type = (sw_r32(rtl_table_data(r, 0)) >> 29) & 0x3; - - v = sw_r32(rtl_table_data(r, 10)); - host_route = !!(v & BIT(21)); - default_route = !!(v & BIT(20)); - rt->prefix_len = -1; - pr_info("%s: host route %d, default_route %d\n", __func__, host_route, default_route); - - switch (rt->attr.type) { - case 0: // IPv4 Unicast route - rt->dst_ip = sw_r32(rtl_table_data(r, 4)); - ip4_m = sw_r32(rtl_table_data(r, 9)); - pr_info("%s: Read ip4 mask: %08x\n", __func__, ip4_m); - rt->prefix_len = host_route ? 32 : -1; - rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1; - if (rt->prefix_len < 0) - rt->prefix_len = inet_mask_len(ip4_m); - break; - case 2: // IPv6 Unicast route - ipv6_addr_set(&rt->dst_ip6, - sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)), - sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4))); - ipv6_addr_set(&ip6_m, - sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), - sw_r32(rtl_table_data(r, 8)), sw_r32(rtl_table_data(r, 9))); - rt->prefix_len = host_route ? 128 : 0; - rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1; - if (rt->prefix_len < 0) - rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32, - 128); - break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route - pr_warn("%s: route type not supported\n", __func__); - goto out; - } - - rt->attr.hit = !!(v & BIT(22)); - rt->attr.action = (v >> 18) & 3; - rt->nh.id = (v >> 7) & 0x7ff; - rt->attr.ttl_dec = !!(v & BIT(6)); - rt->attr.ttl_check = !!(v & BIT(5)); - rt->attr.dst_null = !!(v & BIT(4)); - rt->attr.qos_as = !!(v & BIT(3)); - rt->attr.qos_prio = v & 0x7; - pr_info("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); - pr_info("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n", - __func__, rt->nh.id, rt->attr.hit, rt->attr.action, - rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null); - pr_info("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len); -out: - rtl_table_release(r); -} - -static void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m) -{ - int o, b; - // Define network mask - o = prefix_len >> 3; - b = prefix_len & 0x7; - memset(ip6_m->s6_addr, 0xff, o); - ip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00; -} - -/* - * Read a host route entry from the table using its index - * We currently only support IPv4 and IPv6 unicast route - */ -static void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt) -{ - u32 v; - // Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 - struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1); - - idx = ((idx / 6) * 8) + (idx % 6); - - pr_debug("In %s, physical index %d\n", __func__, idx); - rtl_table_read(r, idx); - // The table has a size of 5 (for UC, 11 for MC) registers - v = sw_r32(rtl_table_data(r, 0)); - rt->attr.valid = !!(v & BIT(31)); - if (!rt->attr.valid) - goto out; - rt->attr.type = (v >> 29) & 0x3; - switch (rt->attr.type) { - case 0: // IPv4 Unicast route - rt->dst_ip = sw_r32(rtl_table_data(r, 4)); - break; - case 2: // IPv6 Unicast route - ipv6_addr_set(&rt->dst_ip6, - sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)), - sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0))); - break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route - pr_warn("%s: route type not supported\n", __func__); - goto out; - } - - rt->attr.hit = !!(v & BIT(20)); - rt->attr.dst_null = !!(v & BIT(19)); - rt->attr.action = (v >> 17) & 3; - rt->nh.id = (v >> 6) & 0x7ff; - rt->attr.ttl_dec = !!(v & BIT(5)); - rt->attr.ttl_check = !!(v & BIT(4)); - rt->attr.qos_as = !!(v & BIT(3)); - rt->attr.qos_prio = v & 0x7; - pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); - pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n", - __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check, - rt->attr.dst_null); - pr_debug("%s: Destination: %pI4\n", __func__, &rt->dst_ip); - -out: - rtl_table_release(r); -} - -/* - * Write a host route entry from the table using its index - * We currently only support IPv4 and IPv6 unicast route - */ -static void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt) -{ - u32 v; - // Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1 - struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1); - // The table has a size of 5 (for UC, 11 for MC) registers - - idx = ((idx / 6) * 8) + (idx % 6); - - pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); - pr_debug("%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n", - __func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check, - rt->attr.dst_null); - pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len); - - v = BIT(31); // Entry is valid - v |= (rt->attr.type & 0x3) << 29; - v |= rt->attr.hit ? BIT(20) : 0; - v |= rt->attr.dst_null ? BIT(19) : 0; - v |= (rt->attr.action & 0x3) << 17; - v |= (rt->nh.id & 0x7ff) << 6; - v |= rt->attr.ttl_dec ? BIT(5) : 0; - v |= rt->attr.ttl_check ? BIT(4) : 0; - v |= rt->attr.qos_as ? BIT(3) : 0; - v |= rt->attr.qos_prio & 0x7; - - sw_w32(v, rtl_table_data(r, 0)); - switch (rt->attr.type) { - case 0: // IPv4 Unicast route - sw_w32(0, rtl_table_data(r, 1)); - sw_w32(0, rtl_table_data(r, 2)); - sw_w32(0, rtl_table_data(r, 3)); - sw_w32(rt->dst_ip, rtl_table_data(r, 4)); - break; - case 2: // IPv6 Unicast route - sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1)); - sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2)); - sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3)); - sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4)); - break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route - pr_warn("%s: route type not supported\n", __func__); - goto out; - } - - rtl_table_write(r, idx); - -out: - rtl_table_release(r); -} - -/* - * Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes - * using hardware offload. - */ -static int rtl930x_route_lookup_hw(struct rtl83xx_route *rt) -{ - u32 ip4_m, v; - struct in6_addr ip6_m; - int i; - - if (rt->attr.type == 1 || rt->attr.type == 3) // Hardware only supports UC routes - return -1; - - sw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL); - if (rt->attr.type) { // IPv6 - rtl930x_net6_mask(rt->prefix_len, &ip6_m); - for (i = 0; i < 4; i++) - sw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0], - RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2)); - } else { // IPv4 - ip4_m = inet_make_mask(rt->prefix_len); - sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL); - sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4); - sw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8); - v = rt->dst_ip & ip4_m; - pr_info("%s: searching for %pI4\n", __func__, &v); - sw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12); - } - - // Execute CAM lookup in SoC - sw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL); - - // Wait until execute bit clears and result is ready - do { - v = sw_r32(RTL930X_L3_HW_LU_CTRL); - } while (v & BIT(15)); - - pr_info("%s: found: %d, index: %d\n", __func__, !!(v & BIT(14)), v & 0x1ff); - - // Test if search successful (BIT 14 set) - if (v & BIT(14)) - return v & 0x1ff; - - return -1; -} - -static int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist) -{ - int t, s, slot_width, algorithm, addr, idx; - u32 hash; - struct rtl83xx_route route_entry; - - // IPv6 entries take up 3 slots - slot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3; - - for (t = 0; t < 2; t++) { - algorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1; - hash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false); - - pr_debug("%s: table %d, algorithm %d, hash %04x\n", __func__, t, algorithm, hash); - - for (s = 0; s < 6; s += slot_width) { - addr = (t << 12) | ((hash & 0x1ff) << 3) | s; - pr_debug("%s physical address %d\n", __func__, addr); - idx = ((addr / 8) * 6) + (addr % 8); - pr_debug("%s logical address %d\n", __func__, idx); - - rtl930x_host_route_read(idx, &route_entry); - pr_debug("%s route valid %d, route dest: %pI4, hit %d\n", __func__, - rt->attr.valid, &rt->dst_ip, rt->attr.hit); - if (!must_exist && rt->attr.valid) - return idx; - if (must_exist && route_entry.dst_ip == rt->dst_ip) - return idx; - } - } - - return -1; -} - -/* - * Write a prefix route into the routing table CAM at position idx - * Currently only IPv4 and IPv6 unicast routes are supported - */ -static void rtl930x_route_write(int idx, struct rtl83xx_route *rt) -{ - u32 v, ip4_m; - struct in6_addr ip6_m; - // Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1 - // The table has a size of 11 registers (20 for MC) - struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2); - - pr_debug("%s: index %d is valid: %d\n", __func__, idx, rt->attr.valid); - pr_debug("%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\n", - __func__, rt->nh.id, rt->attr.hit, rt->attr.action, - rt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null); - pr_debug("%s: GW: %pI4, prefix_len: %d\n", __func__, &rt->dst_ip, rt->prefix_len); - - v = rt->attr.valid ? BIT(31) : 0; - v |= (rt->attr.type & 0x3) << 29; - sw_w32(v, rtl_table_data(r, 0)); - - v = rt->attr.hit ? BIT(22) : 0; - v |= (rt->attr.action & 0x3) << 18; - v |= (rt->nh.id & 0x7ff) << 7; - v |= rt->attr.ttl_dec ? BIT(6) : 0; - v |= rt->attr.ttl_check ? BIT(5) : 0; - v |= rt->attr.dst_null ? BIT(6) : 0; - v |= rt->attr.qos_as ? BIT(6) : 0; - v |= rt->attr.qos_prio & 0x7; - v |= rt->prefix_len == 0 ? BIT(20) : 0; // set default route bit - - // set bit mask for entry type always to 0x3 - sw_w32(0x3 << 29, rtl_table_data(r, 5)); - - switch (rt->attr.type) { - case 0: // IPv4 Unicast route - sw_w32(0, rtl_table_data(r, 1)); - sw_w32(0, rtl_table_data(r, 2)); - sw_w32(0, rtl_table_data(r, 3)); - sw_w32(rt->dst_ip, rtl_table_data(r, 4)); - - v |= rt->prefix_len == 32 ? BIT(21) : 0; // set host-route bit - ip4_m = inet_make_mask(rt->prefix_len); - sw_w32(0, rtl_table_data(r, 6)); - sw_w32(0, rtl_table_data(r, 7)); - sw_w32(0, rtl_table_data(r, 8)); - sw_w32(ip4_m, rtl_table_data(r, 9)); - break; - case 2: // IPv6 Unicast route - sw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1)); - sw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2)); - sw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3)); - sw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4)); - - v |= rt->prefix_len == 128 ? BIT(21) : 0; // set host-route bit - - rtl930x_net6_mask(rt->prefix_len, &ip6_m); - - sw_w32(ip6_m.s6_addr32[0], rtl_table_data(r, 6)); - sw_w32(ip6_m.s6_addr32[1], rtl_table_data(r, 7)); - sw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8)); - sw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9)); - break; - case 1: // IPv4 Multicast route - case 3: // IPv6 Multicast route - pr_warn("%s: route type not supported\n", __func__); - rtl_table_release(r); - return; - } - sw_w32(v, rtl_table_data(r, 10)); - - pr_debug("%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n", __func__, - sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)), - sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)), - sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)), - sw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10))); - - rtl_table_write(r, idx); - rtl_table_release(r); -} - - -/* - * Get the destination MAC and L3 egress interface ID of a nexthop entry from - * the SoC's L3_NEXTHOP table - */ -static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface) -{ - u32 v; - // Read L3_NEXTHOP table (3) via register RTL9300_TBL_1 - struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3); - - rtl_table_read(r, idx); - // The table has a size of 1 register - v = sw_r32(rtl_table_data(r, 0)); - rtl_table_release(r); - - *dmac_id = (v >> 7) & 0x7fff; - *interface = v & 0x7f; -} - -static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu) -{ - int i; - - for (i = 0; i < MAX_INTF_MTUS; i++) { - if (mtu == priv->intf_mtus[i]) - break; - } - if (i >= MAX_INTF_MTUS || !priv->intf_mtu_count[i]) { - pr_err("%s: No MTU slot found for MTU: %d\n", __func__, mtu); - return -EINVAL; - } - - priv->intf_mtu_count[i]--; -} - -static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu) -{ - int i, free_mtu; - int mtu_id; - - // Try to find an existing mtu-value or a free slot - free_mtu = MAX_INTF_MTUS; - for (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) { - if ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS)) - free_mtu = i; - } - i = (i < MAX_INTF_MTUS) ? i : free_mtu; - if (i < MAX_INTF_MTUS) { - mtu_id = i; - } else { - pr_err("%s: No free MTU slot available!\n", __func__); - return -EINVAL; - } - - priv->intf_mtus[i] = mtu; - pr_info("Writing MTU %d to slot %d\n", priv->intf_mtus[i], i); - // Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots - sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16), - RTL930X_L3_IP_MTU_CTRL(i)); - sw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16), - RTL930X_L3_IP6_MTU_CTRL(i)); - - priv->intf_mtu_count[i]++; - - return mtu_id; -} - -/* - * Creates an interface for a route by setting up the HW tables in the SoC - */ -static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf) -{ - int i, intf_id, mtu_id; - // number of MTU-values < 16384 - - // Use the same IPv6 mtu as the ip4 mtu for this route if unset - intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu; - - mtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu); - pr_info("%s: added mtu %d with mtu-id %d\n", __func__, intf->ip4_mtu, mtu_id); - if (mtu_id < 0) - return -ENOSPC; - intf->ip4_mtu_id = mtu_id; - intf->ip6_mtu_id = mtu_id; - - for (i = 0; i < MAX_INTERFACES; i++) { - if (!priv->interfaces[i]) - break; - } - if (i >= MAX_INTERFACES) { - pr_err("%s: cannot find free interface entry\n", __func__); - return -EINVAL; - } - intf_id = i; - priv->interfaces[i] = kzalloc(sizeof(struct rtl838x_l3_intf), GFP_KERNEL); - if (!priv->interfaces[i]) { - pr_err("%s: no memory to allocate new interface\n", __func__); - return -ENOMEM; - } -} - -/* - * Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's - * L3_NEXTHOP table. The nexthop entry is identified by idx. - * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are - * 0x7ffe: TRAP2CPU - * 0x7ffd: TRAP2MASTERCPU - * 0x7fff: DMAC_ID_DROP - */ -static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface) -{ - // Access L3_NEXTHOP table (3) via register RTL9300_TBL_1 - struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3); - - pr_info("%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\n", - __func__, idx, dmac_id, interface); - sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0)); - - pr_info("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0))); - rtl_table_write(r, idx); - rtl_table_release(r); -} - -static void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index) -{ - int block = index / PIE_BLOCK_SIZE; - - sw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL); -} - -/* - * Reads the intermediate representation of the templated match-fields of the - * PIE rule in the pie_rule structure and fills in the raw data fields in the - * raw register space r[]. - * The register space configuration size is identical for the RTL8380/90 and RTL9300, - * however the RTL9310 has 2 more registers / fields and the physical field-ids are different - * on all SoCs - * On the RTL9300 the mask fields are not word-aligend! - */ -static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) -{ - int i; - enum template_field_id field_type; - u16 data, data_m; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - field_type = t[i]; - data = data_m = 0; - - switch (field_type) { - case TEMPLATE_FIELD_SPM0: - data = pr->spm; - data_m = pr->spm_m; - break; - case TEMPLATE_FIELD_SPM1: - data = pr->spm >> 16; - data_m = pr->spm_m >> 16; - break; - case TEMPLATE_FIELD_OTAG: - data = pr->otag; - data_m = pr->otag_m; - break; - case TEMPLATE_FIELD_SMAC0: - data = pr->smac[4]; - data = (data << 8) | pr->smac[5]; - data_m = pr->smac_m[4]; - data_m = (data_m << 8) | pr->smac_m[5]; - break; - case TEMPLATE_FIELD_SMAC1: - data = pr->smac[2]; - data = (data << 8) | pr->smac[3]; - data_m = pr->smac_m[2]; - data_m = (data_m << 8) | pr->smac_m[3]; - break; - case TEMPLATE_FIELD_SMAC2: - data = pr->smac[0]; - data = (data << 8) | pr->smac[1]; - data_m = pr->smac_m[0]; - data_m = (data_m << 8) | pr->smac_m[1]; - break; - case TEMPLATE_FIELD_DMAC0: - data = pr->dmac[4]; - data = (data << 8) | pr->dmac[5]; - data_m = pr->dmac_m[4]; - data_m = (data_m << 8) | pr->dmac_m[5]; - break; - case TEMPLATE_FIELD_DMAC1: - data = pr->dmac[2]; - data = (data << 8) | pr->dmac[3]; - data_m = pr->dmac_m[2]; - data_m = (data_m << 8) | pr->dmac_m[3]; - break; - case TEMPLATE_FIELD_DMAC2: - data = pr->dmac[0]; - data = (data << 8) | pr->dmac[1]; - data_m = pr->dmac_m[0]; - data_m = (data_m << 8) | pr->dmac_m[1]; - break; - case TEMPLATE_FIELD_ETHERTYPE: - data = pr->ethertype; - data_m = pr->ethertype_m; - break; - case TEMPLATE_FIELD_ITAG: - data = pr->itag; - data_m = pr->itag_m; - break; - case TEMPLATE_FIELD_SIP0: - if (pr->is_ipv6) { - data = pr->sip6.s6_addr16[7]; - data_m = pr->sip6_m.s6_addr16[7]; - } else { - data = pr->sip; - data_m = pr->sip_m; - } - break; - case TEMPLATE_FIELD_SIP1: - if (pr->is_ipv6) { - data = pr->sip6.s6_addr16[6]; - data_m = pr->sip6_m.s6_addr16[6]; - } else { - data = pr->sip >> 16; - data_m = pr->sip_m >> 16; - } - break; - - case TEMPLATE_FIELD_SIP2: - case TEMPLATE_FIELD_SIP3: - case TEMPLATE_FIELD_SIP4: - case TEMPLATE_FIELD_SIP5: - case TEMPLATE_FIELD_SIP6: - case TEMPLATE_FIELD_SIP7: - data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; - data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; - break; - - case TEMPLATE_FIELD_DIP0: - if (pr->is_ipv6) { - data = pr->dip6.s6_addr16[7]; - data_m = pr->dip6_m.s6_addr16[7]; - } else { - data = pr->dip; - data_m = pr->dip_m; - } - break; - - case TEMPLATE_FIELD_DIP1: - if (pr->is_ipv6) { - data = pr->dip6.s6_addr16[6]; - data_m = pr->dip6_m.s6_addr16[6]; - } else { - data = pr->dip >> 16; - data_m = pr->dip_m >> 16; - } - break; - - case TEMPLATE_FIELD_DIP2: - case TEMPLATE_FIELD_DIP3: - case TEMPLATE_FIELD_DIP4: - case TEMPLATE_FIELD_DIP5: - case TEMPLATE_FIELD_DIP6: - case TEMPLATE_FIELD_DIP7: - data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; - data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; - break; - - case TEMPLATE_FIELD_IP_TOS_PROTO: - data = pr->tos_proto; - data_m = pr->tos_proto_m; - break; - case TEMPLATE_FIELD_L4_SPORT: - data = pr->sport; - data_m = pr->sport_m; - break; - case TEMPLATE_FIELD_L4_DPORT: - data = pr->dport; - data_m = pr->dport_m; - break; - case TEMPLATE_FIELD_DSAP_SSAP: - data = pr->dsap_ssap; - data_m = pr->dsap_ssap_m; - break; - case TEMPLATE_FIELD_TCP_INFO: - data = pr->tcp_info; - data_m = pr->tcp_info_m; - break; - case TEMPLATE_FIELD_RANGE_CHK: - pr_warn("Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\n"); - break; - default: - pr_info("%s: unknown field %d\n", __func__, field_type); - } - - // On the RTL9300, the mask fields are not word aligned! - if (!(i % 2)) { - r[5 - i / 2] = data; - r[12 - i / 2] |= ((u32)data_m << 8); - } else { - r[5 - i / 2] |= ((u32)data) << 16; - r[12 - i / 2] |= ((u32)data_m) << 24; - r[11 - i / 2] |= ((u32)data_m) >> 8; - } - } -} - -static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr) -{ - pr->stacking_port = r[6] & BIT(31); - pr->spn = (r[6] >> 24) & 0x7f; - pr->mgnt_vlan = r[6] & BIT(23); - if (pr->phase == PHASE_IACL) - pr->dmac_hit_sw = r[6] & BIT(22); - else - pr->content_too_deep = r[6] & BIT(22); - pr->not_first_frag = r[6] & BIT(21); - pr->frame_type_l4 = (r[6] >> 18) & 7; - pr->frame_type = (r[6] >> 16) & 3; - pr->otag_fmt = (r[6] >> 15) & 1; - pr->itag_fmt = (r[6] >> 14) & 1; - pr->otag_exist = (r[6] >> 13) & 1; - pr->itag_exist = (r[6] >> 12) & 1; - pr->frame_type_l2 = (r[6] >> 10) & 3; - pr->igr_normal_port = (r[6] >> 9) & 1; - pr->tid = (r[6] >> 8) & 1; - - pr->stacking_port_m = r[12] & BIT(7); - pr->spn_m = r[12] & 0x7f; - pr->mgnt_vlan_m = r[13] & BIT(31); - if (pr->phase == PHASE_IACL) - pr->dmac_hit_sw_m = r[13] & BIT(30); - else - pr->content_too_deep_m = r[13] & BIT(30); - pr->not_first_frag_m = r[13] & BIT(29); - pr->frame_type_l4_m = (r[13] >> 26) & 7; - pr->frame_type_m = (r[13] >> 24) & 3; - pr->otag_fmt_m = r[13] & BIT(23); - pr->itag_fmt_m = r[13] & BIT(22); - pr->otag_exist_m = r[13] & BIT(21); - pr->itag_exist_m = r[13] & BIT (20); - pr->frame_type_l2_m = (r[13] >> 18) & 3; - pr->igr_normal_port_m = r[13] & BIT(17); - pr->tid_m = (r[13] >> 16) & 1; - - pr->valid = r[13] & BIT(15); - pr->cond_not = r[13] & BIT(14); - pr->cond_and1 = r[13] & BIT(13); - pr->cond_and2 = r[13] & BIT(12); -} - -static void rtl930x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) -{ - r[6] = pr->stacking_port ? BIT(31) : 0; - r[6] |= ((u32) (pr->spn & 0x7f)) << 24; - r[6] |= pr->mgnt_vlan ? BIT(23) : 0; - if (pr->phase == PHASE_IACL) - r[6] |= pr->dmac_hit_sw ? BIT(22) : 0; - else - r[6] |= pr->content_too_deep ? BIT(22) : 0; - r[6] |= pr->not_first_frag ? BIT(21) : 0; - r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18; - r[6] |= ((u32) (pr->frame_type & 0x3)) << 16; - r[6] |= pr->otag_fmt ? BIT(15) : 0; - r[6] |= pr->itag_fmt ? BIT(14) : 0; - r[6] |= pr->otag_exist ? BIT(13) : 0; - r[6] |= pr->itag_exist ? BIT(12) : 0; - r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10; - r[6] |= pr->igr_normal_port ? BIT(9) : 0; - r[6] |= ((u32) (pr->tid & 0x1)) << 8; - - r[12] |= pr->stacking_port_m ? BIT(7) : 0; - r[12] |= (u32) (pr->spn_m & 0x7f); - r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0; - if (pr->phase == PHASE_IACL) - r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0; - else - r[13] |= pr->content_too_deep_m ? BIT(30) : 0; - r[13] |= pr->not_first_frag_m ? BIT(29) : 0; - r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26; - r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24; - r[13] |= pr->otag_fmt_m ? BIT(23) : 0; - r[13] |= pr->itag_fmt_m ? BIT(22) : 0; - r[13] |= pr->otag_exist_m ? BIT(21) : 0; - r[13] |= pr->itag_exist_m ? BIT(20) : 0; - r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18; - r[13] |= pr->igr_normal_port_m ? BIT(17) : 0; - r[13] |= ((u32) (pr->tid_m & 0x1)) << 16; - - r[13] |= pr->valid ? BIT(15) : 0; - r[13] |= pr->cond_not ? BIT(14) : 0; - r[13] |= pr->cond_and1 ? BIT(13) : 0; - r[13] |= pr->cond_and2 ? BIT(12) : 0; -} - -static void rtl930x_write_pie_action(u32 r[], struct pie_rule *pr) -{ - // Either drop or forward - if (pr->drop) { - r[14] |= BIT(24) | BIT(25) | BIT(26); // Do Green, Yellow and Red drops - // Actually DROP, not PERMIT in Green / Yellow / Red - r[14] |= BIT(23) | BIT(22) | BIT(20); - } else { - r[14] |= pr->fwd_sel ? BIT(27) : 0; - r[14] |= pr->fwd_act << 18; - r[14] |= BIT(14); // We overwrite any drop - } - if (pr->phase == PHASE_VACL) - r[14] |= pr->fwd_sa_lrn ? BIT(15) : 0; - r[13] |= pr->bypass_sel ? BIT(5) : 0; - r[13] |= pr->nopri_sel ? BIT(4) : 0; - r[13] |= pr->tagst_sel ? BIT(3) : 0; - r[13] |= pr->ovid_sel ? BIT(1) : 0; - r[14] |= pr->ivid_sel ? BIT(31) : 0; - r[14] |= pr->meter_sel ? BIT(30) : 0; - r[14] |= pr->mir_sel ? BIT(29) : 0; - r[14] |= pr->log_sel ? BIT(28) : 0; - - r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3; - r[15] |= pr->log_octets ? BIT(31) : 0; - r[15] |= (u32)(pr->meter_data) << 23; - - r[15] |= ((u32)(pr->ivid_act) << 21) & 0x3; - r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff; - r[16] |= ((u32)(pr->ovid_act) << 30) & 0x3; - r[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16; - r[16] |= (pr->mir_data & 0x3) << 6; - r[17] |= ((u32)(pr->tagst_data) & 0xf) << 28; - r[17] |= ((u32)(pr->nopri_data) & 0x7) << 25; - r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0; -} - -void rtl930x_pie_rule_dump_raw(u32 r[]) -{ - pr_info("Raw IACL table entry:\n"); - pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n", - r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]); - pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n", - r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]); - pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]); - pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]); - pr_info("Fixed : %06x\n", r[6] >> 8); - pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", - (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8), - (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8), - (r[11] << 24) | (r[12] >> 8)); - pr_info("R[13]: %08x\n", r[13]); - pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff); - pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf); - pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]); -} - -static int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) -{ - // Access IACL table (2) via register 0 - struct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2); - u32 r[19]; - int i; - int block = idx / PIE_BLOCK_SIZE; - u32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)); - - pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select); - - for (i = 0; i < 19; i++) - r[i] = 0; - - if (!pr->valid) { - rtl_table_write(q, idx); - rtl_table_release(q); - return 0; - } - rtl930x_write_pie_fixed_fields(r, pr); - - pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf); - rtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]); - - rtl930x_write_pie_action(r, pr); - -// rtl930x_pie_rule_dump_raw(r); - - for (i = 0; i < 19; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); - - return 0; -} - -static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type) -{ - int i; - enum template_field_id ft; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - ft = fixed_templates[t][i]; - if (field_type == ft) - return true; - } - - return false; -} - -/* - * Verify that the rule pr is compatible with a given template t in block block - * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0 - * depend on the SoC - */ -static int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv, - struct pie_rule *pr, int t, int block) -{ - int i; - - if (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0)) - return -1; - - if (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0)) - return -1; - - if (pr->is_ipv6) { - if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1] - || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3]) - && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) - return -1; - if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1] - || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3]) - && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) - return -1; - } - - if (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0)) - return -1; - - if (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) - return -1; - - // TODO: Check more - - i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); - - if (i >= PIE_BLOCK_SIZE) - return -1; - - return i + PIE_BLOCK_SIZE * block; -} - -static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) -{ - int idx, block, j, t; - int min_block = 0; - int max_block = priv->n_pie_blocks / 2; - - if (pr->is_egress) { - min_block = max_block; - max_block = priv->n_pie_blocks; - } - pr_debug("In %s\n", __func__); - - mutex_lock(&priv->pie_mutex); - - for (block = min_block; block < max_block; block++) { - for (j = 0; j < 2; j++) { - t = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf; - pr_debug("Testing block %d, template %d, template id %d\n", block, j, t); - pr_debug("%s: %08x\n", - __func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block))); - idx = rtl930x_pie_verify_template(priv, pr, t, block); - if (idx >= 0) - break; - } - if (j < 2) - break; - } - - if (block >= priv->n_pie_blocks) { - mutex_unlock(&priv->pie_mutex); - return -EOPNOTSUPP; - } - - pr_debug("Using block: %d, index %d, template-id %d\n", block, idx, j); - set_bit(idx, priv->pie_use_bm); - - pr->valid = true; - pr->tid = j; // Mapped to template number - pr->tid_m = 0x1; - pr->id = idx; - - rtl930x_pie_lookup_enable(priv, idx); - rtl930x_pie_rule_write(priv, idx, pr); - - mutex_unlock(&priv->pie_mutex); - return 0; -} - -/* - * Delete a range of Packet Inspection Engine rules - */ -static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) -{ - u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0); - - pr_debug("%s: from %d to %d\n", __func__, index_from, index_to); - mutex_lock(&priv->reg_mutex); - - // Write from-to and execute bit into control register - sw_w32(v, RTL930X_PIE_CLR_CTRL); - - // Wait until command has completed - do { - } while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0)); - - mutex_unlock(&priv->reg_mutex); - return 0; -} - -static void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr) -{ - int idx = pr->id; - - rtl930x_pie_rule_del(priv, idx, idx); - clear_bit(idx, priv->pie_use_bm); -} - -static void rtl930x_pie_init(struct rtl838x_switch_priv *priv) -{ - int i; - u32 template_selectors; - - mutex_init(&priv->pie_mutex); - - pr_info("%s\n", __func__); - // Enable ACL lookup on all ports, including CPU_PORT - for (i = 0; i <= priv->cpu_port; i++) - sw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i)); - - // Include IPG in metering - sw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL); - - // Delete all present rules, block size is 128 on all SoC families - rtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1); - - // Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1) - sw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL); - - // Enable predefined templates 0, 1 for first quarter of all blocks - template_selectors = 0 | (1 << 4); - for (i = 0; i < priv->n_pie_blocks / 4; i++) - sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 2, 3 for second quarter of all blocks - template_selectors = 2 | (3 << 4); - for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++) - sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 0, 1 for third half of all blocks - template_selectors = 0 | (1 << 4); - for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++) - sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 2, 3 for fourth quater of all blocks - template_selectors = 2 | (3 << 4); - for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++) - sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i)); - -} - -/* - * Sets up an egress interface for L3 actions - * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are: - * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU - * 6: HARDDROP - * idx is the index in the HW interface table: idx < 0x80 - */ -static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf) -{ - u32 u, v; - // Read L3_EGR_INTF table (4) via register RTL9300_TBL_1 - struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4); - - // The table has 2 registers - u = (intf->vid & 0xfff) << 9; - u |= (intf->smac_idx & 0x3f) << 3; - u |= (intf->ip4_mtu_id & 0x7); - - v = (intf->ip6_mtu_id & 0x7) << 28; - v |= (intf->ttl_scope & 0xff) << 20; - v |= (intf->hl_scope & 0xff) << 12; - v |= (intf->ip4_icmp_redirect & 0x7) << 9; - v |= (intf->ip6_icmp_redirect & 0x7)<< 6; - v |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3; - v |= (intf->ip6_pbr_icmp_redirect & 0x7); - - sw_w32(u, rtl_table_data(r, 0)); - sw_w32(v, rtl_table_data(r, 1)); - - pr_info("%s writing to index %d: %08x %08x\n", __func__, idx, u, v); - rtl_table_write(r, idx & 0x7f); - rtl_table_release(r); -} - -/* - * Reads a MAC entry for L3 termination as entry point for routing - * from the hardware table - * idx is the index into the L3_ROUTER_MAC table - */ -static void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) -{ - u32 v, w; - // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 - struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0); - - rtl_table_read(r, idx); - // The table has a size of 7 registers, 64 entries - v = sw_r32(rtl_table_data(r, 0)); - w = sw_r32(rtl_table_data(r, 3)); - m->valid = !!(v & BIT(20)); - if (!m->valid) - goto out; - - m->p_type = !!(v & BIT(19)); - m->p_id = (v >> 13) & 0x3f; // trunk id of port - m->vid = v & 0xfff; - m->vid_mask = w & 0xfff; - m->action = sw_r32(rtl_table_data(r, 6)) & 0x7; - m->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL) - | (sw_r32(rtl_table_data(r, 4))); - m->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL) - | (sw_r32(rtl_table_data(r, 2))); - // Bits L3_INTF and BMSK_L3_INTF are 0 - -out: - rtl_table_release(r); -} - -/* - * Writes a MAC entry for L3 termination as entry point for routing - * into the hardware table - * idx is the index into the L3_ROUTER_MAC table - */ -static void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m) -{ - u32 v, w; - // Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1 - struct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0); - - // The table has a size of 7 registers, 64 entries - v = BIT(20); // mac entry valid, port type is 0: individual - v |= (m->p_id & 0x3f) << 13; - v |= (m->vid & 0xfff); // Set the interface_id to the vlan id - - w = m->vid_mask; - w |= (m->p_id_mask & 0x3f) << 13; - - sw_w32(v, rtl_table_data(r, 0)); - sw_w32(w, rtl_table_data(r, 3)); - - // Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0 - sw_w32((u32)(m->mac), rtl_table_data(r, 2)); - sw_w32(m->mac >> 32, rtl_table_data(r, 1)); - - // Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0 - sw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4)); - sw_w32((u32)m->mac_mask, rtl_table_data(r, 5)); - - sw_w32(m->action & 0x7, rtl_table_data(r, 6)); - - pr_debug("%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\n", __func__, idx, - sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)), - sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)), - sw_r32(rtl_table_data(r, 6)) - ); - rtl_table_write(r, idx); - rtl_table_release(r); -} - -/* - * Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets - * from the SoC's L3_EGR_INTF_MAC table - * Indexes 0-2047 are DMACs, 2048+ are SMACs - */ -static u64 rtl930x_get_l3_egress_mac(u32 idx) -{ - u64 mac; - // Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 - struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2); - - rtl_table_read(r, idx); - // The table has a size of 2 registers - mac = sw_r32(rtl_table_data(r, 0)); - mac <<= 32; - mac |= sw_r32(rtl_table_data(r, 1)); - rtl_table_release(r); - - return mac; -} -/* - * Set the Destination-MAC of a route or the Source MAC of an L3 egress interface - * in the SoC's L3_EGR_INTF_MAC table - * Indexes 0-2047 are DMACs, 2048+ are SMACs - */ -static void rtl930x_set_l3_egress_mac(u32 idx, u64 mac) -{ - // Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2 - struct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2); - - // The table has a size of 2 registers - sw_w32(mac >> 32, rtl_table_data(r, 0)); - sw_w32(mac, rtl_table_data(r, 1)); - - pr_debug("%s: setting index %d to %016llx\n", __func__, idx, mac); - rtl_table_write(r, idx); - rtl_table_release(r); -} - -/* - * Configure L3 routing settings of the device: - * - MTUs - * - Egress interface - * - The router's MAC address on which routed packets are expected - * - MAC addresses used as source macs of routed packets - */ -int rtl930x_l3_setup(struct rtl838x_switch_priv *priv) -{ - int i; - - // Setup MTU with id 0 for default interface - for (i = 0; i < MAX_INTF_MTUS; i++) - priv->intf_mtu_count[i] = priv->intf_mtus[i] = 0; - - priv->intf_mtu_count[0] = 0; // Needs to stay forever - priv->intf_mtus[0] = DEFAULT_MTU; - sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0)); - sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0)); - priv->intf_mtus[1] = DEFAULT_MTU; - sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(0)); - sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(0)); - - sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(1)); - sw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(1)); - sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1)); - sw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1)); - - // Clear all source port MACs - for (i = 0; i < MAX_SMACS; i++) - rtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL); - - // Configure the default L3 hash algorithm - sw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 0 = 0 - sw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL); // Algorithm selection 1 = 1 - - pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n", - sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL), - sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL)); - sw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL); - sw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL); - sw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL); - sw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL); - - sw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL); - sw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL); - sw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL); - sw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL); - - pr_info("L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\n", - sw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL), - sw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL)); - - // Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable) - sw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL); - pr_info("L3_IP_ROUTE_CTRL %08x\n", sw_r32(RTL930X_L3_IP_ROUTE_CTRL)); - - // PORT_ISO_RESTRICT_ROUTE_CTRL ? - - // Do not use prefix route 0 because of HW limitations - set_bit(0, priv->route_use_bm); - - return 0; -} - -static u32 rtl930x_packet_cntr_read(int counter) -{ - u32 v; - - // Read LOG table (3) via register RTL9300_TBL_0 - struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3); - - pr_debug("In %s, id %d\n", __func__, counter); - rtl_table_read(r, counter / 2); - - pr_debug("Registers: %08x %08x\n", - sw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1))); - // The table has a size of 2 registers - if (counter % 2) - v = sw_r32(rtl_table_data(r, 0)); - else - v = sw_r32(rtl_table_data(r, 1)); - - rtl_table_release(r); - - return v; -} - -static void rtl930x_packet_cntr_clear(int counter) -{ - // Access LOG table (3) via register RTL9300_TBL_0 - struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3); - - pr_info("In %s, id %d\n", __func__, counter); - // The table has a size of 2 registers - if (counter % 2) - sw_w32(0, rtl_table_data(r, 0)); - else - sw_w32(0, rtl_table_data(r, 1)); - - rtl_table_write(r, counter / 2); - - rtl_table_release(r); -} - -void rtl930x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) -{ - sw_w32(FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK, - keep_outer ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG) | - FIELD_PREP(RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK, - keep_inner ? RTL930X_VLAN_PORT_TAG_STS_TAGGED : RTL930X_VLAN_PORT_TAG_STS_UNTAG), - RTL930X_VLAN_PORT_TAG_STS_CTRL(port)); -} - -void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) -{ - if (type == PBVLAN_TYPE_INNER) - sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); - else - sw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); -} - -void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) -{ - if (type == PBVLAN_TYPE_INNER) - sw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); - else - sw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2)); -} - -static int rtl930x_set_ageing_time(unsigned long msec) -{ - int t = sw_r32(RTL930X_L2_AGE_CTRL); - - t &= 0x1FFFFF; - t = (t * 7) / 10; - pr_debug("L2 AGING time: %d sec\n", t); - - t = (msec / 100 + 6) / 7; - t = t > 0x1FFFFF ? 0x1FFFFF : t; - sw_w32_mask(0x1FFFFF, t, RTL930X_L2_AGE_CTRL); - pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL930X_L2_PORT_AGE_CTRL)); - - return 0; -} - -static void rtl930x_set_igr_filter(int port, enum igr_filter state) -{ - sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1), - RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); -} - -static void rtl930x_set_egr_filter(int port, enum egr_filter state) -{ - sw_w32_mask(0x1 << (port % 0x1D), state << (port % 0x1D), - RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2))); -} - -void rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) -{ - u32 l3shift = 0; - u32 newmask = 0; - - /* TODO: for now we set algoidx to 0 */ - algoidx = 0; - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) { - l3shift = 4; - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT; - } - if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) { - l3shift = 4; - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT; - } - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) { - l3shift = 4; - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT; - } - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) { - l3shift = 4; - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT; - } - - if (l3shift == 4) { - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT) - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT; - - if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT) - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT; - } else { - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT) - newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT; - if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT) - newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT; - } - - sw_w32(newmask << l3shift, RTL930X_TRK_HASH_CTRL + (algoidx << 2)); -} - -static void rtl930x_led_init(struct rtl838x_switch_priv *priv) -{ - int i, pos; - u32 v, pm = 0, set; - u32 setlen; - const __be32 *led_set; - char set_name[9]; - struct device_node *node; - - pr_info("%s called\n", __func__); - node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds"); - if (!node) { - pr_info("%s No compatible LED node found\n", __func__); - return; - } - - for (i= 0; i < priv->cpu_port; i++) { - pos = (i << 1) % 32; - sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i)); - sw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i)); - - if (!priv->ports[i].phy) - continue; - - v = 0x1; - if (priv->ports[i].is10G) - v = 0x3; - if (priv->ports[i].phy_is_integrated) - v = 0x1; - sw_w32_mask(0x3 << pos, v << pos, RTL930X_LED_PORT_NUM_CTRL(i)); - - pm |= BIT(i); - - set = priv->ports[i].led_set; - sw_w32_mask(0, set << pos, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i)); - sw_w32_mask(0, set << pos, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i)); - } - - for (i = 0; i < 4; i++) { - sprintf(set_name, "led_set%d", i); - led_set = of_get_property(node, set_name, &setlen); - if (!led_set || setlen != 16) - break; - v = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1); - sw_w32(v, RTL930X_LED_SET0_0_CTRL - 4 - i * 8); - v = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3); - sw_w32(v, RTL930X_LED_SET0_0_CTRL - i * 8); - } - - // Set LED mode to serial (0x1) - sw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL); - - // Set port type masks - sw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL); - sw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL); - sw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL); - - for (i = 0; i < 24; i++) - pr_info("%s %08x: %08x\n",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4)); -} - -const struct rtl838x_reg rtl930x_reg = { - .mask_port_reg_be = rtl838x_mask_port_reg, - .set_port_reg_be = rtl838x_set_port_reg, - .get_port_reg_be = rtl838x_get_port_reg, - .mask_port_reg_le = rtl838x_mask_port_reg, - .set_port_reg_le = rtl838x_set_port_reg, - .get_port_reg_le = rtl838x_get_port_reg, - .stat_port_rst = RTL930X_STAT_PORT_RST, - .stat_rst = RTL930X_STAT_RST, - .stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR, - .traffic_enable = rtl930x_traffic_enable, - .traffic_disable = rtl930x_traffic_disable, - .traffic_get = rtl930x_traffic_get, - .traffic_set = rtl930x_traffic_set, - .l2_ctrl_0 = RTL930X_L2_CTRL, - .l2_ctrl_1 = RTL930X_L2_AGE_CTRL, - .l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL, - .set_ageing_time = rtl930x_set_ageing_time, - .smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, // TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL - .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL, - .exec_tbl0_cmd = rtl930x_exec_tbl0_cmd, - .exec_tbl1_cmd = rtl930x_exec_tbl1_cmd, - .tbl_access_data_0 = rtl930x_tbl_access_data_0, - .isr_glb_src = RTL930X_ISR_GLB, - .isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG, - .imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG, - .imr_glb = RTL930X_IMR_GLB, - .vlan_tables_read = rtl930x_vlan_tables_read, - .vlan_set_tagged = rtl930x_vlan_set_tagged, - .vlan_set_untagged = rtl930x_vlan_set_untagged, - .vlan_profile_dump = rtl930x_vlan_profile_dump, - .vlan_profile_setup = rtl930x_vlan_profile_setup, - .vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner, - .set_vlan_igr_filter = rtl930x_set_igr_filter, - .set_vlan_egr_filter = rtl930x_set_egr_filter, - .stp_get = rtl930x_stp_get, - .stp_set = rtl930x_stp_set, - .mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl, - .mac_port_ctrl = rtl930x_mac_port_ctrl, - .l2_port_new_salrn = rtl930x_l2_port_new_salrn, - .l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd, - .mir_ctrl = RTL930X_MIR_CTRL, - .mir_dpm = RTL930X_MIR_DPM_CTRL, - .mir_spm = RTL930X_MIR_SPM_CTRL, - .mac_link_sts = RTL930X_MAC_LINK_STS, - .mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS, - .mac_link_spd_sts = rtl930x_mac_link_spd_sts, - .mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS, - .mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS, - .read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash, - .write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash, - .read_cam = rtl930x_read_cam, - .write_cam = rtl930x_write_cam, - .vlan_port_keep_tag_set = rtl930x_vlan_port_keep_tag_set, - .vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set, - .vlan_port_pvid_set = rtl930x_vlan_port_pvid_set, - .trk_mbr_ctr = rtl930x_trk_mbr_ctr, - .rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK, - .init_eee = rtl930x_init_eee, - .port_eee_set = rtl930x_port_eee_set, - .eee_port_ability = rtl930x_eee_port_ability, - .l2_hash_seed = rtl930x_l2_hash_seed, - .l2_hash_key = rtl930x_l2_hash_key, - .read_mcast_pmask = rtl930x_read_mcast_pmask, - .write_mcast_pmask = rtl930x_write_mcast_pmask, - .pie_init = rtl930x_pie_init, - .pie_rule_write = rtl930x_pie_rule_write, - .pie_rule_add = rtl930x_pie_rule_add, - .pie_rule_rm = rtl930x_pie_rule_rm, - .l2_learning_setup = rtl930x_l2_learning_setup, - .packet_cntr_read = rtl930x_packet_cntr_read, - .packet_cntr_clear = rtl930x_packet_cntr_clear, - .route_read = rtl930x_route_read, - .route_write = rtl930x_route_write, - .host_route_write = rtl930x_host_route_write, - .l3_setup = rtl930x_l3_setup, - .set_l3_nexthop = rtl930x_set_l3_nexthop, - .get_l3_nexthop = rtl930x_get_l3_nexthop, - .get_l3_egress_mac = rtl930x_get_l3_egress_mac, - .set_l3_egress_mac = rtl930x_set_l3_egress_mac, - .find_l3_slot = rtl930x_find_l3_slot, - .route_lookup_hw = rtl930x_route_lookup_hw, - .get_l3_router_mac = rtl930x_get_l3_router_mac, - .set_l3_router_mac = rtl930x_set_l3_router_mac, - .set_l3_egress_intf = rtl930x_set_l3_egress_intf, - .set_distribution_algorithm = rtl930x_set_distribution_algorithm, - .led_init = rtl930x_led_init, -}; diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c deleted file mode 100644 index ee8d6c2c73..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c +++ /dev/null @@ -1,1701 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include "rtl83xx.h" - -#define RTL931X_VLAN_PORT_TAG_STS_INTERNAL 0x0 -#define RTL931X_VLAN_PORT_TAG_STS_UNTAG 0x1 -#define RTL931X_VLAN_PORT_TAG_STS_TAGGED 0x2 -#define RTL931X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x3 - -#define RTL931X_VLAN_PORT_TAG_CTRL_BASE 0x4860 -/* port 0-56 */ -#define RTL931X_VLAN_PORT_TAG_CTRL(port) \ - RTL931X_VLAN_PORT_TAG_CTRL_BASE + (port << 2) -#define RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK GENMASK(13,12) -#define RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK GENMASK(11,10) -#define RTL931X_VLAN_PORT_TAG_EGR_OTAG_KEEP_MASK GENMASK(9,9) -#define RTL931X_VLAN_PORT_TAG_EGR_ITAG_KEEP_MASK GENMASK(8,8) -#define RTL931X_VLAN_PORT_TAG_IGR_OTAG_KEEP_MASK GENMASK(7,7) -#define RTL931X_VLAN_PORT_TAG_IGR_ITAG_KEEP_MASK GENMASK(6,6) -#define RTL931X_VLAN_PORT_TAG_OTPID_IDX_MASK GENMASK(5,4) -#define RTL931X_VLAN_PORT_TAG_OTPID_KEEP_MASK GENMASK(3,3) -#define RTL931X_VLAN_PORT_TAG_ITPID_IDX_MASK GENMASK(2,1) -#define RTL931X_VLAN_PORT_TAG_ITPID_KEEP_MASK GENMASK(0,0) - -extern struct mutex smi_lock; -extern struct rtl83xx_soc_info soc_info; - -/* Definition of the RTL931X-specific template field IDs as used in the PIE */ -enum template_field_id { - TEMPLATE_FIELD_SPM0 = 1, - TEMPLATE_FIELD_SPM1 = 2, - TEMPLATE_FIELD_SPM2 = 3, - TEMPLATE_FIELD_SPM3 = 4, - TEMPLATE_FIELD_DMAC0 = 9, - TEMPLATE_FIELD_DMAC1 = 10, - TEMPLATE_FIELD_DMAC2 = 11, - TEMPLATE_FIELD_SMAC0 = 12, - TEMPLATE_FIELD_SMAC1 = 13, - TEMPLATE_FIELD_SMAC2 = 14, - TEMPLATE_FIELD_ETHERTYPE = 15, - TEMPLATE_FIELD_OTAG = 16, - TEMPLATE_FIELD_ITAG = 17, - TEMPLATE_FIELD_SIP0 = 18, - TEMPLATE_FIELD_SIP1 = 19, - TEMPLATE_FIELD_DIP0 = 20, - TEMPLATE_FIELD_DIP1 = 21, - TEMPLATE_FIELD_IP_TOS_PROTO = 22, - TEMPLATE_FIELD_L4_SPORT = 23, - TEMPLATE_FIELD_L4_DPORT = 24, - TEMPLATE_FIELD_L34_HEADER = 25, - TEMPLATE_FIELD_TCP_INFO = 26, - TEMPLATE_FIELD_SIP2 = 34, - TEMPLATE_FIELD_SIP3 = 35, - TEMPLATE_FIELD_SIP4 = 36, - TEMPLATE_FIELD_SIP5 = 37, - TEMPLATE_FIELD_SIP6 = 38, - TEMPLATE_FIELD_SIP7 = 39, - TEMPLATE_FIELD_DIP2 = 42, - TEMPLATE_FIELD_DIP3 = 43, - TEMPLATE_FIELD_DIP4 = 44, - TEMPLATE_FIELD_DIP5 = 45, - TEMPLATE_FIELD_DIP6 = 46, - TEMPLATE_FIELD_DIP7 = 47, - TEMPLATE_FIELD_FLOW_LABEL = 49, - TEMPLATE_FIELD_DSAP_SSAP = 50, - TEMPLATE_FIELD_FWD_VID = 52, - TEMPLATE_FIELD_RANGE_CHK = 53, - TEMPLATE_FIELD_SLP = 55, - TEMPLATE_FIELD_DLP = 56, - TEMPLATE_FIELD_META_DATA = 57, - TEMPLATE_FIELD_FIRST_MPLS1 = 60, - TEMPLATE_FIELD_FIRST_MPLS2 = 61, - TEMPLATE_FIELD_DPM3 = 8, -}; - -/* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in - * RTL931X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag: - */ -#define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG - -// Number of fixed templates predefined in the RTL9300 SoC -#define N_FIXED_TEMPLATES 5 -// RTL931x specific predefined templates -static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] = -{ - { - TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, - TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2, - TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP, - TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, - TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 - }, { - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, - TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO, - TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN, - TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, - TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 - }, { - TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2, - TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO, - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, - TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, - TEMPLATE_FIELD_META_DATA, TEMPLATE_FIELD_SLP - }, { - TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2, - TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5, - TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO, - TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, - TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SLP - }, { - TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2, - TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5, - TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_META_DATA, - TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, - TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3 - }, -}; - -inline void rtl931x_exec_tbl0_cmd(u32 cmd) -{ - sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_0); - do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_0) & (1 << 20)); -} - -inline void rtl931x_exec_tbl1_cmd(u32 cmd) -{ - sw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_1); - do { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_1) & (1 << 17)); -} - -inline int rtl931x_tbl_access_data_0(int i) -{ - return RTL931X_TBL_ACCESS_DATA_0(i); -} - -void rtl931x_vlan_profile_dump(int index) -{ - u64 profile[4]; - - if (index < 0 || index > 15) - return; - - profile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index)); - profile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32 - | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF); - profile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0x1FFFFFFFULL) << 32 - | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0xFFFFFFFF); - profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 - | (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF); - - pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \ - IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx", - index, (u32) (profile[0] & (3 << 14)), profile[1], profile[2], profile[3]); -} - -static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) -{ - int i; - u32 cmd = 1 << 20 /* Execute cmd */ - | 0 << 19 /* Read */ - | 5 << 15 /* Table type 0b101 */ - | (msti & 0x3fff); - priv->r->exec_tbl0_cmd(cmd); - - for (i = 0; i < 4; i++) - port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); -} - -static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]) -{ - int i; - u32 cmd = 1 << 20 /* Execute cmd */ - | 1 << 19 /* Write */ - | 5 << 15 /* Table type 0b101 */ - | (msti & 0x3fff); - for (i = 0; i < 4; i++) - sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); - priv->r->exec_tbl0_cmd(cmd); -} - -inline static int rtl931x_trk_mbr_ctr(int group) -{ - return RTL931X_TRK_MBR_CTRL + (group << 2); -} - -static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) -{ - u32 v, w, x, y; - // Read VLAN table (3) via register 0 - struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3); - - rtl_table_read(r, vlan); - v = sw_r32(rtl_table_data(r, 0)); - w = sw_r32(rtl_table_data(r, 1)); - x = sw_r32(rtl_table_data(r, 2)); - y = sw_r32(rtl_table_data(r, 3)); - rtl_table_release(r); - - pr_debug("VLAN_READ %d: %08x %08x %08x %08x\n", vlan, v, w, x, y); - info->tagged_ports = ((u64) v) << 25 | (w >> 7); - info->profile_id = (x >> 16) & 0xf; - info->fid = w & 0x7f; // AKA MSTI depending on context - info->hash_uc_fid = !!(x & BIT(31)); - info->hash_mc_fid = !!(x & BIT(30)); - info->if_id = (x >> 20) & 0x3ff; - info->profile_id = (x >> 16) & 0xf; - info->multicast_grp_mask = x & 0xffff; - if (x & BIT(31)) - info->l2_tunnel_list_id = y >> 18; - else - info->l2_tunnel_list_id = -1; - pr_debug("%s read tagged %016llx, profile-id %d, uc %d, mc %d, intf-id %d\n", __func__, - info->tagged_ports, info->profile_id, info->hash_uc_fid, info->hash_mc_fid, - info->if_id); - - // Read UNTAG table via table register 3 - r = rtl_table_get(RTL9310_TBL_3, 0); - rtl_table_read(r, vlan); - v = ((u64)sw_r32(rtl_table_data(r, 0))) << 25; - v |= sw_r32(rtl_table_data(r, 1)) >> 7; - rtl_table_release(r); - - info->untagged_ports = v; -} - -static void rtl931x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) -{ - u32 v, w, x, y; - // Access VLAN table (1) via register 0 - struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3); - - v = info->tagged_ports >> 25; - w = (info->tagged_ports & 0x1fffff) << 7; - w |= info->fid & 0x7f; - x = info->hash_uc_fid ? BIT(31) : 0; - x |= info->hash_mc_fid ? BIT(30) : 0; - x |= info->if_id & 0x3ff << 20; - x |= (info->profile_id & 0xf) << 16; - x |= info->multicast_grp_mask & 0xffff; - if (info->l2_tunnel_list_id >= 0) { - y = info->l2_tunnel_list_id << 18; - y |= BIT(31); - } else { - y = 0; - } - - sw_w32(v, rtl_table_data(r, 0)); - sw_w32(w, rtl_table_data(r, 1)); - sw_w32(x, rtl_table_data(r, 2)); - sw_w32(y, rtl_table_data(r, 3)); - - rtl_table_write(r, vlan); - rtl_table_release(r); -} - -static void rtl931x_vlan_set_untagged(u32 vlan, u64 portmask) -{ - struct table_reg *r = rtl_table_get(RTL9310_TBL_3, 0); - - rtl839x_set_port_reg_be(portmask << 7, rtl_table_data(r, 0)); - rtl_table_write(r, vlan); - rtl_table_release(r); -} - -static inline int rtl931x_mac_force_mode_ctrl(int p) -{ - return RTL931X_MAC_FORCE_MODE_CTRL + (p << 2); -} - -static inline int rtl931x_mac_link_spd_sts(int p) -{ - return RTL931X_MAC_LINK_SPD_STS + (((p >> 3) << 2)); -} - -static inline int rtl931x_mac_port_ctrl(int p) -{ - return RTL931X_MAC_L2_PORT_CTRL + (p << 7); -} - -static inline int rtl931x_l2_port_new_salrn(int p) -{ - return RTL931X_L2_PORT_NEW_SALRN(p); -} - -static inline int rtl931x_l2_port_new_sa_fwd(int p) -{ - return RTL931X_L2_PORT_NEW_SA_FWD(p); -} - -irqreturn_t rtl931x_switch_irq(int irq, void *dev_id) -{ - struct dsa_switch *ds = dev_id; - u32 status = sw_r32(RTL931X_ISR_GLB_SRC); - u64 ports = rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG); - u64 link; - int i; - - /* Clear status */ - rtl839x_set_port_reg_le(ports, RTL931X_ISR_PORT_LINK_STS_CHG); - pr_debug("RTL931X Link change: status: %x, ports %016llx\n", status, ports); - - link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS); - // Must re-read this to get correct status - link = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS); - pr_debug("RTL931X Link change: status: %x, link status %016llx\n", status, link); - - for (i = 0; i < 56; i++) { - if (ports & BIT_ULL(i)) { - if (link & BIT_ULL(i)) { - pr_info("%s port %d up\n", __func__, i); - dsa_port_phylink_mac_change(ds, i, true); - } else { - pr_info("%s port %d down\n", __func__, i); - dsa_port_phylink_mac_change(ds, i, false); - } - } - } - return IRQ_HANDLED; -} - -int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val) -{ - u32 v; - int err = 0; - - val &= 0xffff; - if (port > 63 || page > 4095 || reg > 31) - return -ENOTSUPP; - - mutex_lock(&smi_lock); - pr_debug("%s: writing to phy %d %d %d %d\n", __func__, port, page, reg, val); - /* Clear both port registers */ - sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2); - sw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4); - sw_w32_mask(0, BIT(port % 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + (port / 32) * 4); - - sw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3); - - v = reg << 6 | page << 11 ; - sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); - - sw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1); - - v |= BIT(4) | 1; /* Write operation and execute */ - sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); - - do { - } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1); - - if (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x2) - err = -EIO; - - mutex_unlock(&smi_lock); - return err; -} - -int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val) -{ - u32 v; - - if (port > 63 || page > 4095 || reg > 31) - return -ENOTSUPP; - - mutex_lock(&smi_lock); - - sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL); - - v = reg << 6 | page << 11 | 1; - sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); - - do { - } while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1); - - v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0); - *val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3); - *val = (*val & 0xffff0000) >> 16; - - pr_debug("%s: port %d, page: %d, reg: %x, val: %x, v: %08x\n", - __func__, port, page, reg, *val, v); - - mutex_unlock(&smi_lock); - return 0; -} - -/* - * Read an mmd register of the PHY - */ -int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val) -{ - int err = 0; - u32 v; - /* Select PHY register type - * If select 1G/10G MMD register type, registers EXT_PAGE, MAIN_PAGE and REG settings are don’t care. - * 0x0 Normal register (Clause 22) - * 0x1: 1G MMD register (MMD via Clause 22 registers 13 and 14) - * 0x2: 10G MMD register (MMD via Clause 45) - */ - int type = (regnum & MII_ADDR_C45)?2:1; - - mutex_lock(&smi_lock); - - // Set PHY to access via port-number - sw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL); - - // Set MMD device number and register to write to - sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL); - - v = type << 2 | BIT(0); // MMD-access-type | EXEC - sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); - - do { - v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0); - } while (v & BIT(0)); - - // Check for error condition - if (v & BIT(1)) - err = -EIO; - - *val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) >> 16; - - pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__, - port, devnum, mdiobus_c45_regad(regnum), *val, err); - - mutex_unlock(&smi_lock); - - return err; -} - -/* - * Write to an mmd register of the PHY - */ -int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val) -{ - int err = 0; - u32 v; - int type = (regnum & MII_ADDR_C45)?2:1; - u64 pm; - - mutex_lock(&smi_lock); - - // Set PHY to access via port-mask - pm = (u64)1 << port; - sw_w32((u32)pm, RTL931X_SMI_INDRT_ACCESS_CTRL_2); - sw_w32((u32)(pm >> 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4); - - // Set data to write - sw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3); - - // Set MMD device number and register to write to - sw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL); - - v = BIT(4) | type << 2 | BIT(0); // WRITE | MMD-access-type | EXEC - sw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0); - - do { - v = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0); - } while (v & BIT(0)); - - pr_debug("%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\n", __func__, - port, devnum, mdiobus_c45_regad(regnum), val, err); - mutex_unlock(&smi_lock); - return err; -} - -void rtl931x_print_matrix(void) -{ - volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); - int i; - - for (i = 0; i < 52; i += 4) - pr_info("> %16llx %16llx %16llx %16llx\n", - ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]); - pr_info("CPU_PORT> %16llx\n", ptr[52]); -} - -void rtl931x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action) -{ - u32 value = 0; - - /* hack for value mapping */ - if (type == GRATARP && action == COPY2CPU) - action = TRAP2MASTERCPU; - - switch(action) { - case FORWARD: - value = 0; - break; - case DROP: - value = 1; - break; - case TRAP2CPU: - value = 2; - break; - case TRAP2MASTERCPU: - value = 3; - break; - case FLOODALL: - value = 4; - break; - default: - break; - } - - switch(type) { - case BPDU: - sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_BPDU_CTRL + ((port / 10) << 2)); - break; - case PTP: - //udp - sw_w32_mask(3 << 2, value << 2, RTL931X_RMA_PTP_CTRL + (port << 2)); - //eth2 - sw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2)); - break; - case PTP_UDP: - sw_w32_mask(3 << 2, value << 2, RTL931X_RMA_PTP_CTRL + (port << 2)); - break; - case PTP_ETH2: - sw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2)); - break; - case LLTP: - sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_LLTP_CTRL + ((port / 10) << 2)); - break; - case EAPOL: - sw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_EAPOL_CTRL + ((port / 10) << 2)); - break; - case GRATARP: - sw_w32_mask(3 << ((port & 0xf) << 1), value << ((port & 0xf) << 1), RTL931X_TRAP_ARP_GRAT_PORT_ACT + ((port >> 4) << 2)); - break; - } -} - -u64 rtl931x_traffic_get(int source) -{ - u32 v; - struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6); - - rtl_table_read(r, source); - v = sw_r32(rtl_table_data(r, 0)); - rtl_table_release(r); - return v >> 3; -} - -/* - * Enable traffic between a source port and a destination port matrix - */ -void rtl931x_traffic_set(int source, u64 dest_matrix) -{ - struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6); - - sw_w32((dest_matrix << 3), rtl_table_data(r, 0)); - rtl_table_write(r, source); - rtl_table_release(r); -} - -void rtl931x_traffic_enable(int source, int dest) -{ - struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6); - rtl_table_read(r, source); - sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0)); - rtl_table_write(r, source); - rtl_table_release(r); -} - -void rtl931x_traffic_disable(int source, int dest) -{ - struct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6); - rtl_table_read(r, source); - sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0)); - rtl_table_write(r, source); - rtl_table_release(r); -} - -static u64 rtl931x_l2_hash_seed(u64 mac, u32 vid) -{ - u64 v = vid; - - v <<= 48; - v |= mac; - - return v; -} - -/* - * Calculate both the block 0 and the block 1 hash by applyingthe same hash - * algorithm as the one used currently by the ASIC to the seed, and return - * both hashes in the lower and higher word of the return value since only 12 bit of - * the hash are significant. - */ -static u32 rtl931x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed) -{ - u32 h, h0, h1, h2, h3, h4, k0, k1; - - h0 = seed & 0xfff; - h1 = (seed >> 12) & 0xfff; - h2 = (seed >> 24) & 0xfff; - h3 = (seed >> 36) & 0xfff; - h4 = (seed >> 48) & 0xfff; - h4 = ((h4 & 0x7) << 9) | ((h4 >> 3) & 0x1ff); - k0 = h0 ^ h1 ^ h2 ^ h3 ^ h4; - - h0 = seed & 0xfff; - h0 = ((h0 & 0x1ff) << 3) | ((h0 >> 9) & 0x7); - h1 = (seed >> 12) & 0xfff; - h1 = ((h1 & 0x3f) << 6) | ((h1 >> 6) & 0x3f); - h2 = (seed >> 24) & 0xfff; - h3 = (seed >> 36) & 0xfff; - h3 = ((h3 & 0x3f) << 6) | ((h3 >> 6) & 0x3f); - h4 = (seed >> 48) & 0xfff; - k1 = h0 ^ h1 ^ h2 ^ h3 ^ h4; - - // Algorithm choice for block 0 - if (sw_r32(RTL931X_L2_CTRL) & BIT(0)) - h = k1; - else - h = k0; - - /* Algorithm choice for block 1 - * Since k0 and k1 are < 4096, adding 4096 will offset the hash into the second - * half of hash-space - * 4096 is in fact the hash-table size 32768 divided by 4 hashes per bucket - * divided by 2 to divide the hash space in 2 - */ - if (sw_r32(RTL931X_L2_CTRL) & BIT(1)) - h |= (k1 + 4096) << 16; - else - h |= (k0 + 4096) << 16; - - return h; -} - -/* - * Fills an L2 entry structure from the SoC registers - */ -static void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e) -{ - pr_debug("In %s valid?\n", __func__); - e->valid = !!(r[0] & BIT(31)); - if (!e->valid) - return; - - pr_debug("%s: entry valid, raw: %08x %08x %08x %08x\n", __func__, r[0], r[1], r[2], r[3]); - e->is_ip_mc = false; - e->is_ipv6_mc = false; - - e->mac[0] = r[0] >> 8; - e->mac[1] = r[0]; - e->mac[2] = r[1] >> 24; - e->mac[3] = r[1] >> 16; - e->mac[4] = r[1] >> 8; - e->mac[5] = r[1]; - - e->is_open_flow = !!(r[0] & BIT(30)); - e->is_pe_forward = !!(r[0] & BIT(29)); - e->next_hop = !!(r[2] & BIT(30)); - e->rvid = (r[0] >> 16) & 0xfff; - - /* Is it a unicast entry? check multicast bit */ - if (!(e->mac[0] & 1)) { - e->type = L2_UNICAST; - e->is_l2_tunnel = !!(r[2] & BIT(31)); - e->is_static = !!(r[2] & BIT(13)); - e->port = (r[2] >> 19) & 0x3ff; - // Check for trunk port - if (r[2] & BIT(29)) { - e->is_trunk = true; - e->stack_dev = (e->port >> 9) & 1; - e->trunk = e->port & 0x3f; - } else { - e->is_trunk = false; - e->stack_dev = (e->port >> 6) & 0xf; - e->port = e->port & 0x3f; - } - - e->block_da = !!(r[2] & BIT(14)); - e->block_sa = !!(r[2] & BIT(15)); - e->suspended = !!(r[2] & BIT(12)); - e->age = (r[2] >> 16) & 3; - - // the UC_VID field in hardware is used for the VID or for the route id - if (e->next_hop) { - e->nh_route_id = r[2] & 0x7ff; - e->vid = 0; - } else { - e->vid = r[2] & 0xfff; - e->nh_route_id = 0; - } - if (e->is_l2_tunnel) - e->l2_tunnel_id = ((r[2] & 0xff) << 4) | (r[3] >> 28); - // TODO: Implement VLAN conversion - } else { - e->type = L2_MULTICAST; - e->is_local_forward = !!(r[2] & BIT(31)); - e->is_remote_forward = !!(r[2] & BIT(17)); - e->mc_portmask_index = (r[2] >> 18) & 0xfff; - e->l2_tunnel_list_id = (r[2] >> 4) & 0x1fff; - } -} - -/* - * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry - */ -static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e) -{ - u32 port; - - if (!e->valid) { - r[0] = r[1] = r[2] = 0; - return; - } - - r[2] = BIT(31); // Set valid bit - - r[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16 - | ((u32)e->mac[2]) << 8 | ((u32)e->mac[3]); - r[1] = ((u32)e->mac[4]) << 24 | ((u32)e->mac[5]) << 16; - - r[2] |= e->next_hop ? BIT(12) : 0; - - if (e->type == L2_UNICAST) { - r[2] |= e->is_static ? BIT(14) : 0; - r[1] |= e->rvid & 0xfff; - r[2] |= (e->port & 0x3ff) << 20; - if (e->is_trunk) { - r[2] |= BIT(30); - port = e->stack_dev << 9 | (e->port & 0x3f); - } else { - port = (e->stack_dev & 0xf) << 6; - port |= e->port & 0x3f; - } - r[2] |= port << 20; - r[2] |= e->block_da ? BIT(15) : 0; - r[2] |= e->block_sa ? BIT(17) : 0; - r[2] |= e->suspended ? BIT(13) : 0; - r[2] |= (e->age & 0x3) << 17; - // the UC_VID field in hardware is used for the VID or for the route id - if (e->next_hop) - r[2] |= e->nh_route_id & 0x7ff; - else - r[2] |= e->vid & 0xfff; - } else { // L2_MULTICAST - r[2] |= (e->mc_portmask_index & 0x3ff) << 16; - r[2] |= e->mc_mac_index & 0x7ff; - } -} - -/* - * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table - * hash is the id of the bucket and pos is the position of the entry in that bucket - * The data read from the SoC is filled into rtl838x_l2_entry - */ -static u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) -{ - u32 r[4]; - struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0); - u32 idx; - int i; - u64 mac; - u64 seed; - - pr_debug("%s: hash %08x, pos: %d\n", __func__, hash, pos); - - /* On the RTL93xx, 2 different hash algorithms are used making it a total of - * 8 buckets that need to be searched, 4 for each hash-half - * Use second hash space when bucket is between 4 and 8 */ - if (pos >= 4) { - pos -= 4; - hash >>= 16; - } else { - hash &= 0xffff; - } - - idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket - pr_debug("%s: NOW hash %08x, pos: %d\n", __func__, hash, pos); - - rtl_table_read(q, idx); - for (i = 0; i < 4; i++) - r[i] = sw_r32(rtl_table_data(q, i)); - - rtl_table_release(q); - - rtl931x_fill_l2_entry(r, e); - - pr_debug("%s: valid: %d, nh: %d\n", __func__, e->valid, e->next_hop); - if (!e->valid) - return 0; - - mac = ((u64)e->mac[0]) << 40 | ((u64)e->mac[1]) << 32 | ((u64)e->mac[2]) << 24 - | ((u64)e->mac[3]) << 16 | ((u64)e->mac[4]) << 8 | ((u64)e->mac[5]); - - seed = rtl931x_l2_hash_seed(mac, e->rvid); - pr_debug("%s: mac %016llx, seed %016llx\n", __func__, mac, seed); - // return vid with concatenated mac as unique id - return seed; -} - -static u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e) -{ - return 0; -} - -static void rtl931x_write_cam(int idx, struct rtl838x_l2_entry *e) -{ -} - -static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e) -{ - u32 r[4]; - struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0); - u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket - int i; - - pr_info("%s: hash %d, pos %d\n", __func__, hash, pos); - pr_info("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx, - e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]); - - rtl931x_fill_l2_row(r, e); - pr_info("%s: %d: %08x %08x %08x\n", __func__, idx, r[0], r[1], r[2]); - - for (i= 0; i < 4; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); - -} - -static void rtl931x_vlan_fwd_on_inner(int port, bool is_set) -{ - // Always set all tag modes to fwd based on either inner or outer tag - if (is_set) - sw_w32_mask(0, 0xf, RTL931X_VLAN_PORT_FWD + (port << 2)); - else - sw_w32_mask(0xf, 0, RTL931X_VLAN_PORT_FWD + (port << 2)); -} - -static void rtl931x_vlan_profile_setup(int profile) -{ - u32 p[7]; - int i; - - pr_info("In %s\n", __func__); - - if (profile > 15) - return; - - p[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(profile)); - - // Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic - //p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12); - p[0] |= 0x3 << 11; // COPY2CPU - - p[1] = 0x1FFFFFF; // L2 unknwon MC flooding portmask all ports, including the CPU-port - p[2] = 0xFFFFFFFF; - p[3] = 0x1FFFFFF; // IPv4 unknwon MC flooding portmask - p[4] = 0xFFFFFFFF; - p[5] = 0x1FFFFFF; // IPv6 unknwon MC flooding portmask - p[6] = 0xFFFFFFFF; - - for (i = 0; i < 7; i++) - sw_w32(p[i], RTL931X_VLAN_PROFILE_SET(profile) + i * 4); - pr_info("Leaving %s\n", __func__); -} - -static void rtl931x_l2_learning_setup(void) -{ - // Portmask for flooding broadcast traffic - rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_BC_FLD_PMSK); - - // Portmask for flooding unicast traffic with unknown destination - rtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_UNKN_UC_FLD_PMSK); - - // Limit learning to maximum: 64k entries, after that just flood (bits 0-2) - sw_w32((0xffff << 3) | FORWARD, RTL931X_L2_LRN_CONSTRT_CTRL); -} - -static u64 rtl931x_read_mcast_pmask(int idx) -{ - u64 portmask; - // Read MC_PMSK (2) via register RTL9310_TBL_0 - struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2); - - rtl_table_read(q, idx); - portmask = sw_r32(rtl_table_data(q, 0)); - portmask <<= 32; - portmask |= sw_r32(rtl_table_data(q, 1)); - portmask >>= 7; - rtl_table_release(q); - - pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, portmask); - return portmask; -} - -static void rtl931x_write_mcast_pmask(int idx, u64 portmask) -{ - u64 pm = portmask; - - // Access MC_PMSK (2) via register RTL9310_TBL_0 - struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2); - - pr_debug("%s: Index idx %d has portmask %016llx\n", __func__, idx, pm); - pm <<= 7; - sw_w32((u32)(pm >> 32), rtl_table_data(q, 0)); - sw_w32((u32)pm, rtl_table_data(q, 1)); - rtl_table_write(q, idx); - rtl_table_release(q); -} - - -static int rtl931x_set_ageing_time(unsigned long msec) -{ - int t = sw_r32(RTL931X_L2_AGE_CTRL); - - t &= 0x1FFFFF; - t = (t * 8) / 10; - pr_debug("L2 AGING time: %d sec\n", t); - - t = (msec / 100 + 7) / 8; - t = t > 0x1FFFFF ? 0x1FFFFF : t; - sw_w32_mask(0x1FFFFF, t, RTL931X_L2_AGE_CTRL); - pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL931X_L2_PORT_AGE_CTRL)); - return 0; -} -void rtl931x_sw_init(struct rtl838x_switch_priv *priv) -{ -// rtl931x_sds_init(priv); -} - -static void rtl931x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index) -{ - int block = index / PIE_BLOCK_SIZE; - - sw_w32_mask(0, BIT(block), RTL931X_PIE_BLK_LOOKUP_CTRL); -} - -/* - * Fills the data in the intermediate representation in the pie_rule structure - * into a data field for a given template field field_type - * TODO: This function looks very similar to the function of the rtl9300, but - * since it uses the physical template_field_id, which are different for each - * SoC and there are other field types, it is actually not. If we would also use - * an intermediate representation for a field type, we would could have one - * pie_data_fill function for all SoCs, provided we have also for each SoC a - * function to map between physical and intermediate field type - */ -int rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr, u16 *data, u16 *data_m) -{ - *data = *data_m = 0; - - switch (field_type) { - case TEMPLATE_FIELD_SPM0: - *data = pr->spm; - *data_m = pr->spm_m; - break; - case TEMPLATE_FIELD_SPM1: - *data = pr->spm >> 16; - *data_m = pr->spm_m >> 16; - break; - case TEMPLATE_FIELD_OTAG: - *data = pr->otag; - *data_m = pr->otag_m; - break; - case TEMPLATE_FIELD_SMAC0: - *data = pr->smac[4]; - *data = (*data << 8) | pr->smac[5]; - *data_m = pr->smac_m[4]; - *data_m = (*data_m << 8) | pr->smac_m[5]; - break; - case TEMPLATE_FIELD_SMAC1: - *data = pr->smac[2]; - *data = (*data << 8) | pr->smac[3]; - *data_m = pr->smac_m[2]; - *data_m = (*data_m << 8) | pr->smac_m[3]; - break; - case TEMPLATE_FIELD_SMAC2: - *data = pr->smac[0]; - *data = (*data << 8) | pr->smac[1]; - *data_m = pr->smac_m[0]; - *data_m = (*data_m << 8) | pr->smac_m[1]; - break; - case TEMPLATE_FIELD_DMAC0: - *data = pr->dmac[4]; - *data = (*data << 8) | pr->dmac[5]; - *data_m = pr->dmac_m[4]; - *data_m = (*data_m << 8) | pr->dmac_m[5]; - break; - case TEMPLATE_FIELD_DMAC1: - *data = pr->dmac[2]; - *data = (*data << 8) | pr->dmac[3]; - *data_m = pr->dmac_m[2]; - *data_m = (*data_m << 8) | pr->dmac_m[3]; - break; - case TEMPLATE_FIELD_DMAC2: - *data = pr->dmac[0]; - *data = (*data << 8) | pr->dmac[1]; - *data_m = pr->dmac_m[0]; - *data_m = (*data_m << 8) | pr->dmac_m[1]; - break; - case TEMPLATE_FIELD_ETHERTYPE: - *data = pr->ethertype; - *data_m = pr->ethertype_m; - break; - case TEMPLATE_FIELD_ITAG: - *data = pr->itag; - *data_m = pr->itag_m; - break; - case TEMPLATE_FIELD_SIP0: - if (pr->is_ipv6) { - *data = pr->sip6.s6_addr16[7]; - *data_m = pr->sip6_m.s6_addr16[7]; - } else { - *data = pr->sip; - *data_m = pr->sip_m; - } - break; - case TEMPLATE_FIELD_SIP1: - if (pr->is_ipv6) { - *data = pr->sip6.s6_addr16[6]; - *data_m = pr->sip6_m.s6_addr16[6]; - } else { - *data = pr->sip >> 16; - *data_m = pr->sip_m >> 16; - } - break; - case TEMPLATE_FIELD_SIP2: - case TEMPLATE_FIELD_SIP3: - case TEMPLATE_FIELD_SIP4: - case TEMPLATE_FIELD_SIP5: - case TEMPLATE_FIELD_SIP6: - case TEMPLATE_FIELD_SIP7: - *data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; - *data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)]; - break; - - case TEMPLATE_FIELD_DIP0: - if (pr->is_ipv6) { - *data = pr->dip6.s6_addr16[7]; - *data_m = pr->dip6_m.s6_addr16[7]; - } else { - *data = pr->dip; - *data_m = pr->dip_m; - } - break; - case TEMPLATE_FIELD_DIP1: - if (pr->is_ipv6) { - *data = pr->dip6.s6_addr16[6]; - *data_m = pr->dip6_m.s6_addr16[6]; - } else { - *data = pr->dip >> 16; - *data_m = pr->dip_m >> 16; - } - break; - - case TEMPLATE_FIELD_DIP2: - case TEMPLATE_FIELD_DIP3: - case TEMPLATE_FIELD_DIP4: - case TEMPLATE_FIELD_DIP5: - case TEMPLATE_FIELD_DIP6: - case TEMPLATE_FIELD_DIP7: - *data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; - *data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)]; - break; - - case TEMPLATE_FIELD_IP_TOS_PROTO: - *data = pr->tos_proto; - *data_m = pr->tos_proto_m; - break; - case TEMPLATE_FIELD_L4_SPORT: - *data = pr->sport; - *data_m = pr->sport_m; - break; - case TEMPLATE_FIELD_L4_DPORT: - *data = pr->dport; - *data_m = pr->dport_m; - break; - case TEMPLATE_FIELD_DSAP_SSAP: - *data = pr->dsap_ssap; - *data_m = pr->dsap_ssap_m; - break; - case TEMPLATE_FIELD_TCP_INFO: - *data = pr->tcp_info; - *data_m = pr->tcp_info_m; - break; - case TEMPLATE_FIELD_RANGE_CHK: - pr_info("TEMPLATE_FIELD_RANGE_CHK: not configured\n"); - break; - default: - pr_info("%s: unknown field %d\n", __func__, field_type); - return -1; - } - - return 0; -} - -/* - * Reads the intermediate representation of the templated match-fields of the - * PIE rule in the pie_rule structure and fills in the raw data fields in the - * raw register space r[]. - * The register space configuration size is identical for the RTL8380/90 and RTL9300, - * however the RTL931X has 2 more registers / fields and the physical field-ids are different - * on all SoCs - * On the RTL9300 the mask fields are not word-aligend! - */ -static void rtl931x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[]) -{ - int i; - u16 data, data_m; - - for (i = 0; i < N_FIXED_FIELDS; i++) { - rtl931x_pie_data_fill(t[i], pr, &data, &data_m); - - // On the RTL9300, the mask fields are not word aligned! - if (!(i % 2)) { - r[5 - i / 2] = data; - r[12 - i / 2] |= ((u32)data_m << 8); - } else { - r[5 - i / 2] |= ((u32)data) << 16; - r[12 - i / 2] |= ((u32)data_m) << 24; - r[11 - i / 2] |= ((u32)data_m) >> 8; - } - } -} - -static void rtl931x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr) -{ - pr->mgnt_vlan = r[7] & BIT(31); - if (pr->phase == PHASE_IACL) - pr->dmac_hit_sw = r[7] & BIT(30); - else // TODO: EACL/VACL phase handling - pr->content_too_deep = r[7] & BIT(30); - pr->not_first_frag = r[7] & BIT(29); - pr->frame_type_l4 = (r[7] >> 26) & 7; - pr->frame_type = (r[7] >> 24) & 3; - pr->otag_fmt = (r[7] >> 23) & 1; - pr->itag_fmt = (r[7] >> 22) & 1; - pr->otag_exist = (r[7] >> 21) & 1; - pr->itag_exist = (r[7] >> 20) & 1; - pr->frame_type_l2 = (r[7] >> 18) & 3; - pr->igr_normal_port = (r[7] >> 17) & 1; - pr->tid = (r[7] >> 16) & 1; - - pr->mgnt_vlan_m = r[14] & BIT(15); - if (pr->phase == PHASE_IACL) - pr->dmac_hit_sw_m = r[14] & BIT(14); - else - pr->content_too_deep_m = r[14] & BIT(14); - pr->not_first_frag_m = r[14] & BIT(13); - pr->frame_type_l4_m = (r[14] >> 10) & 7; - pr->frame_type_m = (r[14] >> 8) & 3; - pr->otag_fmt_m = r[14] & BIT(7); - pr->itag_fmt_m = r[14] & BIT(6); - pr->otag_exist_m = r[14] & BIT(5); - pr->itag_exist_m = r[14] & BIT (4); - pr->frame_type_l2_m = (r[14] >> 2) & 3; - pr->igr_normal_port_m = r[14] & BIT(1); - pr->tid_m = r[14] & 1; - - pr->valid = r[15] & BIT(31); - pr->cond_not = r[15] & BIT(30); - pr->cond_and1 = r[15] & BIT(29); - pr->cond_and2 = r[15] & BIT(28); -} - -static void rtl931x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr) -{ - r[7] |= pr->mgnt_vlan ? BIT(31) : 0; - if (pr->phase == PHASE_IACL) - r[7] |= pr->dmac_hit_sw ? BIT(30) : 0; - else - r[7] |= pr->content_too_deep ? BIT(30) : 0; - r[7] |= pr->not_first_frag ? BIT(29) : 0; - r[7] |= ((u32) (pr->frame_type_l4 & 0x7)) << 26; - r[7] |= ((u32) (pr->frame_type & 0x3)) << 24; - r[7] |= pr->otag_fmt ? BIT(23) : 0; - r[7] |= pr->itag_fmt ? BIT(22) : 0; - r[7] |= pr->otag_exist ? BIT(21) : 0; - r[7] |= pr->itag_exist ? BIT(20) : 0; - r[7] |= ((u32) (pr->frame_type_l2 & 0x3)) << 18; - r[7] |= pr->igr_normal_port ? BIT(17) : 0; - r[7] |= ((u32) (pr->tid & 0x1)) << 16; - - r[14] |= pr->mgnt_vlan_m ? BIT(15) : 0; - if (pr->phase == PHASE_IACL) - r[14] |= pr->dmac_hit_sw_m ? BIT(14) : 0; - else - r[14] |= pr->content_too_deep_m ? BIT(14) : 0; - r[14] |= pr->not_first_frag_m ? BIT(13) : 0; - r[14] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10; - r[14] |= ((u32) (pr->frame_type_m & 0x3)) << 8; - r[14] |= pr->otag_fmt_m ? BIT(7) : 0; - r[14] |= pr->itag_fmt_m ? BIT(6) : 0; - r[14] |= pr->otag_exist_m ? BIT(5) : 0; - r[14] |= pr->itag_exist_m ? BIT(4) : 0; - r[14] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2; - r[14] |= pr->igr_normal_port_m ? BIT(1) : 0; - r[14] |= (u32) (pr->tid_m & 0x1); - - r[15] |= pr->valid ? BIT(31) : 0; - r[15] |= pr->cond_not ? BIT(30) : 0; - r[15] |= pr->cond_and1 ? BIT(29) : 0; - r[15] |= pr->cond_and2 ? BIT(28) : 0; -} - -static void rtl931x_write_pie_action(u32 r[], struct pie_rule *pr) -{ - // Either drop or forward - if (pr->drop) { - r[15] |= BIT(11) | BIT(12) | BIT(13); // Do Green, Yellow and Red drops - // Actually DROP, not PERMIT in Green / Yellow / Red - r[16] |= BIT(27) | BIT(28) | BIT(29); - } else { - r[15] |= pr->fwd_sel ? BIT(14) : 0; - r[16] |= pr->fwd_act << 24; - r[16] |= BIT(21); // We overwrite any drop - } - if (pr->phase == PHASE_VACL) - r[16] |= pr->fwd_sa_lrn ? BIT(22) : 0; - r[15] |= pr->bypass_sel ? BIT(10) : 0; - r[15] |= pr->nopri_sel ? BIT(21) : 0; - r[15] |= pr->tagst_sel ? BIT(20) : 0; - r[15] |= pr->ovid_sel ? BIT(18) : 0; - r[15] |= pr->ivid_sel ? BIT(16) : 0; - r[15] |= pr->meter_sel ? BIT(27) : 0; - r[15] |= pr->mir_sel ? BIT(15) : 0; - r[15] |= pr->log_sel ? BIT(26) : 0; - - r[16] |= ((u32)(pr->fwd_data & 0xfff)) << 9; -// r[15] |= pr->log_octets ? BIT(31) : 0; - r[15] |= (u32)(pr->meter_data) >> 2; - r[16] |= (((u32)(pr->meter_data) >> 7) & 0x3) << 29; - - r[16] |= ((u32)(pr->ivid_act & 0x3)) << 21; - r[15] |= ((u32)(pr->ivid_data & 0xfff)) << 9; - r[16] |= ((u32)(pr->ovid_act & 0x3)) << 30; - r[16] |= ((u32)(pr->ovid_data & 0xfff)) << 16; - r[16] |= ((u32)(pr->mir_data & 0x3)) << 6; - r[17] |= ((u32)(pr->tagst_data & 0xf)) << 28; - r[17] |= ((u32)(pr->nopri_data & 0x7)) << 25; - r[17] |= pr->bypass_ibc_sc ? BIT(16) : 0; -} - -void rtl931x_pie_rule_dump_raw(u32 r[]) -{ - pr_info("Raw IACL table entry:\n"); - pr_info("r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\n", - r[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]); - pr_info("r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\n", - r[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]); - pr_info("r 16 - 18: %08x %08x %08x\n", r[16], r[17], r[18]); - pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]); - pr_info("Fixed : %06x\n", r[6] >> 8); - pr_info("Match M: %08x %08x %08x %08x %08x %08x\n", - (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8), - (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8), - (r[11] << 24) | (r[12] >> 8)); - pr_info("R[13]: %08x\n", r[13]); - pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff); - pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf); - pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]); -} - -static int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr) -{ - // Access IACL table (0) via register 1, the table size is 4096 - struct table_reg *q = rtl_table_get(RTL9310_TBL_1, 0); - u32 r[22]; - int i; - int block = idx / PIE_BLOCK_SIZE; - u32 t_select = sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)); - - pr_info("%s: %d, t_select: %08x\n", __func__, idx, t_select); - - for (i = 0; i < 22; i++) - r[i] = 0; - - if (!pr->valid) { - rtl_table_write(q, idx); - rtl_table_release(q); - return 0; - } - rtl931x_write_pie_fixed_fields(r, pr); - - pr_info("%s: template %d\n", __func__, (t_select >> (pr->tid * 4)) & 0xf); - rtl931x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]); - - rtl931x_write_pie_action(r, pr); - - rtl931x_pie_rule_dump_raw(r); - - for (i = 0; i < 22; i++) - sw_w32(r[i], rtl_table_data(q, i)); - - rtl_table_write(q, idx); - rtl_table_release(q); - - return 0; -} - -static bool rtl931x_pie_templ_has(int t, enum template_field_id field_type) -{ - int i; - enum template_field_id ft; - - for (i = 0; i < N_FIXED_FIELDS_RTL931X; i++) { - ft = fixed_templates[t][i]; - if (field_type == ft) - return true; - } - - return false; -} - -/* - * Verify that the rule pr is compatible with a given template t in block block - * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0 - * depend on the SoC - */ -static int rtl931x_pie_verify_template(struct rtl838x_switch_priv *priv, - struct pie_rule *pr, int t, int block) -{ - int i; - - if (!pr->is_ipv6 && pr->sip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP0)) - return -1; - - if (!pr->is_ipv6 && pr->dip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP0)) - return -1; - - if (pr->is_ipv6) { - if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1] - || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3]) - && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP2)) - return -1; - if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1] - || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3]) - && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP2)) - return -1; - } - - if (ether_addr_to_u64(pr->smac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0)) - return -1; - - if (ether_addr_to_u64(pr->dmac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0)) - return -1; - - // TODO: Check more - - i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE); - - if (i >= PIE_BLOCK_SIZE) - return -1; - - return i + PIE_BLOCK_SIZE * block; -} - -static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr) -{ - int idx, block, j, t; - int min_block = 0; - int max_block = priv->n_pie_blocks / 2; - - if (pr->is_egress) { - min_block = max_block; - max_block = priv->n_pie_blocks; - } - pr_info("In %s\n", __func__); - - mutex_lock(&priv->pie_mutex); - - for (block = min_block; block < max_block; block++) { - for (j = 0; j < 2; j++) { - t = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf; - pr_info("Testing block %d, template %d, template id %d\n", block, j, t); - pr_info("%s: %08x\n", - __func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block))); - idx = rtl931x_pie_verify_template(priv, pr, t, block); - if (idx >= 0) - break; - } - if (j < 2) - break; - } - - if (block >= priv->n_pie_blocks) { - mutex_unlock(&priv->pie_mutex); - return -EOPNOTSUPP; - } - - pr_info("Using block: %d, index %d, template-id %d\n", block, idx, j); - set_bit(idx, priv->pie_use_bm); - - pr->valid = true; - pr->tid = j; // Mapped to template number - pr->tid_m = 0x1; - pr->id = idx; - - rtl931x_pie_lookup_enable(priv, idx); - rtl931x_pie_rule_write(priv, idx, pr); - - mutex_unlock(&priv->pie_mutex); - return 0; -} - -/* - * Delete a range of Packet Inspection Engine rules - */ -static int rtl931x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to) -{ - u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0); - - pr_info("%s: from %d to %d\n", __func__, index_from, index_to); - mutex_lock(&priv->reg_mutex); - - // Write from-to and execute bit into control register - sw_w32(v, RTL931X_PIE_CLR_CTRL); - - // Wait until command has completed - do { - } while (sw_r32(RTL931X_PIE_CLR_CTRL) & BIT(0)); - - mutex_unlock(&priv->reg_mutex); - return 0; -} - -static void rtl931x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr) -{ - int idx = pr->id; - - rtl931x_pie_rule_del(priv, idx, idx); - clear_bit(idx, priv->pie_use_bm); -} - -static void rtl931x_pie_init(struct rtl838x_switch_priv *priv) -{ - int i; - u32 template_selectors; - - mutex_init(&priv->pie_mutex); - - pr_info("%s\n", __func__); - // Enable ACL lookup on all ports, including CPU_PORT - for (i = 0; i <= priv->cpu_port; i++) - sw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i)); - - // Include IPG in metering - sw_w32_mask(0, 1, RTL931X_METER_GLB_CTRL); - - // Delete all present rules, block size is 128 on all SoC families - rtl931x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1); - - // Assign first half blocks 0-7 to VACL phase, second half to IACL - // 3 bits are used for each block, values for PIE blocks are - // 6: Disabled, 0: VACL, 1: IACL, 2: EACL - // And for OpenFlow Flow blocks: 3: Ingress Flow table 0, - // 4: Ingress Flow Table 3, 5: Egress flow table 0 - for (i = 0; i < priv->n_pie_blocks; i++) { - int pos = (i % 10) * 3; - u32 r = RTL931X_PIE_BLK_PHASE_CTRL + 4 * (i / 10); - - if (i < priv->n_pie_blocks / 2) - sw_w32_mask(0x7 << pos, 0, r); - else - sw_w32_mask(0x7 << pos, 1 << pos, r); - } - - // Enable predefined templates 0, 1 for first quarter of all blocks - template_selectors = 0 | (1 << 4); - for (i = 0; i < priv->n_pie_blocks / 4; i++) - sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 2, 3 for second quarter of all blocks - template_selectors = 2 | (3 << 4); - for (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++) - sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 0, 1 for third quater of all blocks - template_selectors = 0 | (1 << 4); - for (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++) - sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); - - // Enable predefined templates 2, 3 for fourth quater of all blocks - template_selectors = 2 | (3 << 4); - for (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++) - sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i)); - -} - -int rtl931x_l3_setup(struct rtl838x_switch_priv *priv) -{ - return 0; -} - -void rtl931x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner) -{ - sw_w32(FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK, - keep_outer ? RTL931X_VLAN_PORT_TAG_STS_TAGGED : RTL931X_VLAN_PORT_TAG_STS_UNTAG) | - FIELD_PREP(RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK, - keep_inner ? RTL931X_VLAN_PORT_TAG_STS_TAGGED : RTL931X_VLAN_PORT_TAG_STS_UNTAG), - RTL931X_VLAN_PORT_TAG_CTRL(port)); -} - -void rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode) -{ - if (type == PBVLAN_TYPE_INNER) - sw_w32_mask(0x3 << 12, mode << 12, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); - else - sw_w32_mask(0x3 << 26, mode << 26, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); -} - -void rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid) -{ - if (type == PBVLAN_TYPE_INNER) - sw_w32_mask(0xfff, pvid, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); - else - sw_w32_mask(0xfff << 14, pvid << 14, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2)); -} - -static void rtl931x_set_igr_filter(int port, enum igr_filter state) -{ - sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1), - RTL931X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2))); -} - -static void rtl931x_set_egr_filter(int port, enum egr_filter state) -{ - sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20), - RTL931X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2))); -} - -void rtl931x_set_distribution_algorithm(int group, int algoidx, u32 algomsk) -{ - u32 l3shift = 0; - u32 newmask = 0; - - /* TODO: for now we set algoidx to 0 */ - algoidx=0; - - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) { - l3shift = 4; - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT; - } - if (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) { - l3shift = 4; - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT; - } - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) { - l3shift = 4; - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT; - } - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) { - l3shift = 4; - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT; - } - - if (l3shift == 4) { - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT) - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT; - if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT) - newmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT; - } else { - if (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT) - newmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT; - if (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT) - newmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT; - } - - sw_w32(newmask << l3shift, RTL931X_TRK_HASH_CTRL + (algoidx << 2)); -} - -static void rtl931x_led_init(struct rtl838x_switch_priv *priv) -{ - int i, pos; - u32 v, set; - u64 pm_copper = 0, pm_fiber = 0; - u32 setlen; - const __be32 *led_set; - char set_name[9]; - struct device_node *node; - - pr_info("%s called\n", __func__); - node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300-leds"); - if (!node) { - pr_info("%s No compatible LED node found\n", __func__); - return; - } - - for (i= 0; i < priv->cpu_port; i++) { - pos = (i << 1) % 32; - sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i)); - sw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i)); - - if (!priv->ports[i].phy) - continue; - - v = 0x1; // Found on the EdgeCore, but we do not have any HW description - sw_w32_mask(0x3 << pos, v << pos, RTL931X_LED_PORT_NUM_CTRL(i)); - - if (priv->ports[i].phy_is_integrated) - pm_fiber |= BIT_ULL(i); - else - pm_copper |= BIT_ULL(i); - - set = priv->ports[i].led_set; - sw_w32_mask(0, set << pos, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i)); - sw_w32_mask(0, set << pos, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i)); - } - - for (i = 0; i < 4; i++) { - sprintf(set_name, "led_set%d", i); - pr_info(">%s<\n", set_name); - led_set = of_get_property(node, set_name, &setlen); - if (!led_set || setlen != 16) - break; - v = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1); - sw_w32(v, RTL931X_LED_SET0_0_CTRL - 4 - i * 8); - v = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3); - sw_w32(v, RTL931X_LED_SET0_0_CTRL - i * 8); - } - - // Set LED mode to serial (0x1) - sw_w32_mask(0x3, 0x1, RTL931X_LED_GLB_CTRL); - - rtl839x_set_port_reg_le(pm_copper, RTL931X_LED_PORT_COPR_MASK_CTRL); - rtl839x_set_port_reg_le(pm_fiber, RTL931X_LED_PORT_FIB_MASK_CTRL); - rtl839x_set_port_reg_le(pm_copper | pm_fiber, RTL931X_LED_PORT_COMBO_MASK_CTRL); - - for (i = 0; i < 32; i++) - pr_info("%s %08x: %08x\n",__func__, 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4)); - -} - -const struct rtl838x_reg rtl931x_reg = { - .mask_port_reg_be = rtl839x_mask_port_reg_be, - .set_port_reg_be = rtl839x_set_port_reg_be, - .get_port_reg_be = rtl839x_get_port_reg_be, - .mask_port_reg_le = rtl839x_mask_port_reg_le, - .set_port_reg_le = rtl839x_set_port_reg_le, - .get_port_reg_le = rtl839x_get_port_reg_le, - .stat_port_rst = RTL931X_STAT_PORT_RST, - .stat_rst = RTL931X_STAT_RST, - .stat_port_std_mib = 0, // Not defined - .traffic_enable = rtl931x_traffic_enable, - .traffic_disable = rtl931x_traffic_disable, - .traffic_get = rtl931x_traffic_get, - .traffic_set = rtl931x_traffic_set, - .l2_ctrl_0 = RTL931X_L2_CTRL, - .l2_ctrl_1 = RTL931X_L2_AGE_CTRL, - .l2_port_aging_out = RTL931X_L2_PORT_AGE_CTRL, - .set_ageing_time = rtl931x_set_ageing_time, - // .smi_poll_ctrl does not exist - .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL, - .exec_tbl0_cmd = rtl931x_exec_tbl0_cmd, - .exec_tbl1_cmd = rtl931x_exec_tbl1_cmd, - .tbl_access_data_0 = rtl931x_tbl_access_data_0, - .isr_glb_src = RTL931X_ISR_GLB_SRC, - .isr_port_link_sts_chg = RTL931X_ISR_PORT_LINK_STS_CHG, - .imr_port_link_sts_chg = RTL931X_IMR_PORT_LINK_STS_CHG, - // imr_glb does not exist on RTL931X - .vlan_tables_read = rtl931x_vlan_tables_read, - .vlan_set_tagged = rtl931x_vlan_set_tagged, - .vlan_set_untagged = rtl931x_vlan_set_untagged, - .vlan_profile_dump = rtl931x_vlan_profile_dump, - .vlan_profile_setup = rtl931x_vlan_profile_setup, - .vlan_fwd_on_inner = rtl931x_vlan_fwd_on_inner, - .stp_get = rtl931x_stp_get, - .stp_set = rtl931x_stp_set, - .mac_force_mode_ctrl = rtl931x_mac_force_mode_ctrl, - .mac_port_ctrl = rtl931x_mac_port_ctrl, - .l2_port_new_salrn = rtl931x_l2_port_new_salrn, - .l2_port_new_sa_fwd = rtl931x_l2_port_new_sa_fwd, - .mir_ctrl = RTL931X_MIR_CTRL, - .mir_dpm = RTL931X_MIR_DPM_CTRL, - .mir_spm = RTL931X_MIR_SPM_CTRL, - .mac_link_sts = RTL931X_MAC_LINK_STS, - .mac_link_dup_sts = RTL931X_MAC_LINK_DUP_STS, - .mac_link_spd_sts = rtl931x_mac_link_spd_sts, - .mac_rx_pause_sts = RTL931X_MAC_RX_PAUSE_STS, - .mac_tx_pause_sts = RTL931X_MAC_TX_PAUSE_STS, - .read_l2_entry_using_hash = rtl931x_read_l2_entry_using_hash, - .write_l2_entry_using_hash = rtl931x_write_l2_entry_using_hash, - .read_cam = rtl931x_read_cam, - .write_cam = rtl931x_write_cam, - .vlan_port_keep_tag_set = rtl931x_vlan_port_keep_tag_set, - .vlan_port_pvidmode_set = rtl931x_vlan_port_pvidmode_set, - .vlan_port_pvid_set = rtl931x_vlan_port_pvid_set, - .trk_mbr_ctr = rtl931x_trk_mbr_ctr, - .set_vlan_igr_filter = rtl931x_set_igr_filter, - .set_vlan_egr_filter = rtl931x_set_egr_filter, - .set_distribution_algorithm = rtl931x_set_distribution_algorithm, - .l2_hash_key = rtl931x_l2_hash_key, - .read_mcast_pmask = rtl931x_read_mcast_pmask, - .write_mcast_pmask = rtl931x_write_mcast_pmask, - .pie_init = rtl931x_pie_init, - .pie_rule_write = rtl931x_pie_rule_write, - .pie_rule_add = rtl931x_pie_rule_add, - .pie_rule_rm = rtl931x_pie_rule_rm, - .l2_learning_setup = rtl931x_l2_learning_setup, - .l3_setup = rtl931x_l3_setup, - .led_init = rtl931x_led_init, -}; - diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/tc.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/tc.c deleted file mode 100644 index d0a8ee8cfe..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/tc.c +++ /dev/null @@ -1,409 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include -#include -#include -#include - -#include -#include "rtl83xx.h" -#include "rtl838x.h" - -/* - * Parse the flow rule for the matching conditions - */ -static int rtl83xx_parse_flow_rule(struct rtl838x_switch_priv *priv, - struct flow_rule *rule, struct rtl83xx_flow *flow) -{ - struct flow_dissector *dissector = rule->match.dissector; - - pr_debug("In %s\n", __func__); - /* KEY_CONTROL and KEY_BASIC are needed for forming a meaningful key */ - if ((dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_CONTROL)) == 0 || - (dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_BASIC)) == 0) { - pr_err("Cannot form TC key: used_keys = 0x%x\n", dissector->used_keys); - return -EOPNOTSUPP; - } - - if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { - struct flow_match_basic match; - - pr_debug("%s: BASIC\n", __func__); - flow_rule_match_basic(rule, &match); - if (match.key->n_proto == htons(ETH_P_ARP)) - flow->rule.frame_type = 0; - if (match.key->n_proto == htons(ETH_P_IP)) - flow->rule.frame_type = 2; - if (match.key->n_proto == htons(ETH_P_IPV6)) - flow->rule.frame_type = 3; - if ((match.key->n_proto == htons(ETH_P_ARP)) || flow->rule.frame_type) - flow->rule.frame_type_m = 3; - if (flow->rule.frame_type >= 2) { - if (match.key->ip_proto == IPPROTO_UDP) - flow->rule.frame_type_l4 = 0; - if (match.key->ip_proto == IPPROTO_TCP) - flow->rule.frame_type_l4 = 1; - if (match.key->ip_proto == IPPROTO_ICMP - || match.key->ip_proto ==IPPROTO_ICMPV6) - flow->rule.frame_type_l4 = 2; - if (match.key->ip_proto == IPPROTO_TCP) - flow->rule.frame_type_l4 = 3; - if ((match.key->ip_proto == IPPROTO_UDP) || flow->rule.frame_type_l4) - flow->rule.frame_type_l4_m = 7; - } - } - - if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { - struct flow_match_eth_addrs match; - - pr_debug("%s: ETH_ADDR\n", __func__); - flow_rule_match_eth_addrs(rule, &match); - ether_addr_copy(flow->rule.dmac, match.key->dst); - ether_addr_copy(flow->rule.dmac_m, match.mask->dst); - ether_addr_copy(flow->rule.smac, match.key->src); - ether_addr_copy(flow->rule.smac_m, match.mask->src); - } - - if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { - struct flow_match_vlan match; - - pr_debug("%s: VLAN\n", __func__); - flow_rule_match_vlan(rule, &match); - flow->rule.itag = match.key->vlan_id; - flow->rule.itag_m = match.mask->vlan_id; - // TODO: What about match.key->vlan_priority ? - } - - if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) { - struct flow_match_ipv4_addrs match; - - pr_debug("%s: IPV4\n", __func__); - flow_rule_match_ipv4_addrs(rule, &match); - flow->rule.is_ipv6 = false; - flow->rule.dip = match.key->dst; - flow->rule.dip_m = match.mask->dst; - flow->rule.sip = match.key->src; - flow->rule.sip_m = match.mask->src; - } else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV6_ADDRS)) { - struct flow_match_ipv6_addrs match; - - pr_debug("%s: IPV6\n", __func__); - flow->rule.is_ipv6 = true; - flow_rule_match_ipv6_addrs(rule, &match); - flow->rule.dip6 = match.key->dst; - flow->rule.dip6_m = match.mask->dst; - flow->rule.sip6 = match.key->src; - flow->rule.sip6_m = match.mask->src; - } - - if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { - struct flow_match_ports match; - - pr_debug("%s: PORTS\n", __func__); - flow_rule_match_ports(rule, &match); - flow->rule.dport = match.key->dst; - flow->rule.dport_m = match.mask->dst; - flow->rule.sport = match.key->src; - flow->rule.sport_m = match.mask->src; - } - - // TODO: ICMP - return 0; -} - -static void rtl83xx_flow_bypass_all(struct rtl83xx_flow *flow) -{ - flow->rule.bypass_sel = true; - flow->rule.bypass_all = true; - flow->rule.bypass_igr_stp = true; - flow->rule.bypass_ibc_sc = true; -} - -static int rtl83xx_parse_fwd(struct rtl838x_switch_priv *priv, - const struct flow_action_entry *act, struct rtl83xx_flow *flow) -{ - struct net_device *dev = act->dev; - int port; - - port = rtl83xx_port_is_under(dev, priv); - if (port < 0) { - netdev_info(dev, "%s: not a DSA device.\n", __func__); - return -EINVAL; - } - - flow->rule.fwd_sel = true; - flow->rule.fwd_data = port; - pr_debug("Using port index: %d\n", port); - rtl83xx_flow_bypass_all(flow); - - return 0; -} - -static int rtl83xx_add_flow(struct rtl838x_switch_priv *priv, struct flow_cls_offload *f, - struct rtl83xx_flow *flow) -{ - struct flow_rule *rule = flow_cls_offload_flow_rule(f); - const struct flow_action_entry *act; - int i, err; - - pr_debug("%s\n", __func__); - - rtl83xx_parse_flow_rule(priv, rule, flow); - - flow_action_for_each(i, act, &rule->action) { - switch (act->id) { - case FLOW_ACTION_DROP: - pr_debug("%s: DROP\n", __func__); - flow->rule.drop = true; - rtl83xx_flow_bypass_all(flow); - return 0; - - case FLOW_ACTION_TRAP: - pr_debug("%s: TRAP\n", __func__); - flow->rule.fwd_data = priv->cpu_port; - flow->rule.fwd_act = PIE_ACT_REDIRECT_TO_PORT; - rtl83xx_flow_bypass_all(flow); - break; - - case FLOW_ACTION_MANGLE: - pr_err("%s: FLOW_ACTION_MANGLE not supported\n", __func__); - return -EOPNOTSUPP; - - case FLOW_ACTION_ADD: - pr_err("%s: FLOW_ACTION_ADD not supported\n", __func__); - return -EOPNOTSUPP; - - case FLOW_ACTION_VLAN_PUSH: - pr_debug("%s: VLAN_PUSH\n", __func__); -// TODO: act->vlan.proto - flow->rule.ivid_act = PIE_ACT_VID_ASSIGN; - flow->rule.ivid_sel = true; - flow->rule.ivid_data = htons(act->vlan.vid); - flow->rule.ovid_act = PIE_ACT_VID_ASSIGN; - flow->rule.ovid_sel = true; - flow->rule.ovid_data = htons(act->vlan.vid); - flow->rule.fwd_mod_to_cpu = true; - break; - - case FLOW_ACTION_VLAN_POP: - pr_debug("%s: VLAN_POP\n", __func__); - flow->rule.ivid_act = PIE_ACT_VID_ASSIGN; - flow->rule.ivid_data = 0; - flow->rule.ivid_sel = true; - flow->rule.ovid_act = PIE_ACT_VID_ASSIGN; - flow->rule.ovid_data = 0; - flow->rule.ovid_sel = true; - flow->rule.fwd_mod_to_cpu = true; - break; - - case FLOW_ACTION_CSUM: - pr_err("%s: FLOW_ACTION_CSUM not supported\n", __func__); - return -EOPNOTSUPP; - - case FLOW_ACTION_REDIRECT: - pr_debug("%s: REDIRECT\n", __func__); - err = rtl83xx_parse_fwd(priv, act, flow); - if (err) - return err; - flow->rule.fwd_act = PIE_ACT_REDIRECT_TO_PORT; - break; - - case FLOW_ACTION_MIRRED: - pr_debug("%s: MIRRED\n", __func__); - err = rtl83xx_parse_fwd(priv, act, flow); - if (err) - return err; - flow->rule.fwd_act = PIE_ACT_COPY_TO_PORT; - break; - - default: - pr_err("%s: Flow action not supported: %d\n", __func__, act->id); - return -EOPNOTSUPP; - } - } - - return 0; -} - -static const struct rhashtable_params tc_ht_params = { - .head_offset = offsetof(struct rtl83xx_flow, node), - .key_offset = offsetof(struct rtl83xx_flow, cookie), - .key_len = sizeof(((struct rtl83xx_flow *)0)->cookie), - .automatic_shrinking = true, -}; - -static int rtl83xx_configure_flower(struct rtl838x_switch_priv *priv, - struct flow_cls_offload *f) -{ - struct rtl83xx_flow *flow; - int err = 0; - - pr_debug("In %s\n", __func__); - - rcu_read_lock(); - pr_debug("Cookie %08lx\n", f->cookie); - flow = rhashtable_lookup(&priv->tc_ht, &f->cookie, tc_ht_params); - if (flow) { - pr_info("%s: Got flow\n", __func__); - err = -EEXIST; - goto rcu_unlock; - } - -rcu_unlock: - rcu_read_unlock(); - if (flow) - goto out; - pr_debug("%s: New flow\n", __func__); - - flow = kzalloc(sizeof(*flow), GFP_KERNEL); - if (!flow) { - err = -ENOMEM; - goto out; - } - - flow->cookie = f->cookie; - flow->priv = priv; - - err = rhashtable_insert_fast(&priv->tc_ht, &flow->node, tc_ht_params); - if (err) { - pr_err("Could not insert add new rule\n"); - goto out_free; - } - - rtl83xx_add_flow(priv, f, flow); // TODO: check error - - // Add log action to flow - flow->rule.packet_cntr = rtl83xx_packet_cntr_alloc(priv); - if (flow->rule.packet_cntr >= 0) { - pr_debug("Using packet counter %d\n", flow->rule.packet_cntr); - flow->rule.log_sel = true; - flow->rule.log_data = flow->rule.packet_cntr; - } - - err = priv->r->pie_rule_add(priv, &flow->rule); - return err; - -out_free: - kfree(flow); -out: - pr_err("%s: error %d\n", __func__, err); - return err; -} - -static int rtl83xx_delete_flower(struct rtl838x_switch_priv *priv, - struct flow_cls_offload * cls_flower) -{ - struct rtl83xx_flow *flow; - - pr_debug("In %s\n", __func__); - rcu_read_lock(); - flow = rhashtable_lookup_fast(&priv->tc_ht, &cls_flower->cookie, tc_ht_params); - if (!flow) { - rcu_read_unlock(); - return -EINVAL; - } - - priv->r->pie_rule_rm(priv, &flow->rule); - - rhashtable_remove_fast(&priv->tc_ht, &flow->node, tc_ht_params); - - kfree_rcu(flow, rcu_head); - - rcu_read_unlock(); - return 0; -} - -static int rtl83xx_stats_flower(struct rtl838x_switch_priv *priv, - struct flow_cls_offload * cls_flower) -{ - struct rtl83xx_flow *flow; - unsigned long lastused = 0; - int total_packets, new_packets; - - pr_debug("%s: \n", __func__); - flow = rhashtable_lookup_fast(&priv->tc_ht, &cls_flower->cookie, tc_ht_params); - if (!flow) - return -1; - - if (flow->rule.packet_cntr >= 0) { - total_packets = priv->r->packet_cntr_read(flow->rule.packet_cntr); - pr_debug("Total packets: %d\n", total_packets); - new_packets = total_packets - flow->rule.last_packet_cnt; - flow->rule.last_packet_cnt = total_packets; - } - - // TODO: We need a second PIE rule to count the bytes - flow_stats_update(&cls_flower->stats, 100 * new_packets, new_packets, 0, lastused, - FLOW_ACTION_HW_STATS_IMMEDIATE); - return 0; -} - -static int rtl83xx_setup_tc_cls_flower(struct rtl838x_switch_priv *priv, - struct flow_cls_offload *cls_flower) -{ - pr_debug("%s: %d\n", __func__, cls_flower->command); - switch (cls_flower->command) { - case FLOW_CLS_REPLACE: - return rtl83xx_configure_flower(priv, cls_flower); - case FLOW_CLS_DESTROY: - return rtl83xx_delete_flower(priv, cls_flower); - case FLOW_CLS_STATS: - return rtl83xx_stats_flower(priv, cls_flower); - default: - return -EOPNOTSUPP; - } -} - - -static int rtl83xx_setup_tc_block_cb(enum tc_setup_type type, void *type_data, - void *cb_priv) -{ - struct rtl838x_switch_priv *priv = cb_priv; - - switch (type) { - case TC_SETUP_CLSFLOWER: - pr_debug("%s: TC_SETUP_CLSFLOWER\n", __func__); - return rtl83xx_setup_tc_cls_flower(priv, type_data); - default: - return -EOPNOTSUPP; - } -} - -static LIST_HEAD(rtl83xx_block_cb_list); - -int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data) -{ - struct rtl838x_switch_priv *priv; - struct flow_block_offload *f = type_data; - static bool first_time = true; - int err; - - pr_debug("%s: %d\n", __func__, type); - - if(!netdev_uses_dsa(dev)) { - pr_err("%s: no DSA\n", __func__); - return 0; - } - priv = dev->dsa_ptr->ds->priv; - - switch (type) { - case TC_SETUP_BLOCK: - if (first_time) { - first_time = false; - err = rhashtable_init(&priv->tc_ht, &tc_ht_params); - if (err) - pr_err("%s: Could not initialize hash table\n", __func__); - } - - f->unlocked_driver_cb = true; - return flow_block_cb_setup_simple(type_data, - &rtl83xx_block_cb_list, - rtl83xx_setup_tc_block_cb, - priv, priv, true); - default: - return -EOPNOTSUPP; - } - - return 0; -} diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c deleted file mode 100644 index 16a846c8d7..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c +++ /dev/null @@ -1,2588 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/drivers/net/ethernet/rtl838x_eth.c - * Copyright (C) 2020 B. Koblitz - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "rtl838x_eth.h" - -extern struct rtl83xx_soc_info soc_info; - -/* - * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX - * The ring is assigned by switch based on packet/port priortity - * Maximum number of TX rings is 2, Ring 2 being the high priority - * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length - * for an RX ring, MAX_ENTRIES the maximum number of entries - * available in total for all queues. - */ -#define MAX_RXRINGS 32 -#define MAX_RXLEN 300 -#define MAX_ENTRIES (300 * 8) -#define TXRINGS 2 -#define TXRINGLEN 160 -#define NOTIFY_EVENTS 10 -#define NOTIFY_BLOCKS 10 -#define TX_EN 0x8 -#define RX_EN 0x4 -#define TX_EN_93XX 0x20 -#define RX_EN_93XX 0x10 -#define TX_DO 0x2 -#define WRAP 0x2 -#define MAX_PORTS 57 -#define MAX_SMI_BUSSES 4 - -#define RING_BUFFER 1600 - -struct p_hdr { - uint8_t *buf; - uint16_t reserved; - uint16_t size; /* buffer size */ - uint16_t offset; - uint16_t len; /* pkt len */ - /* cpu_tag[0] is a reserved uint16_t on RTL83xx */ - uint16_t cpu_tag[10]; -} __packed __aligned(1); - -struct n_event { - uint32_t type:2; - uint32_t fidVid:12; - uint64_t mac:48; - uint32_t slp:6; - uint32_t valid:1; - uint32_t reserved:27; -} __packed __aligned(1); - -struct ring_b { - uint32_t rx_r[MAX_RXRINGS][MAX_RXLEN]; - uint32_t tx_r[TXRINGS][TXRINGLEN]; - struct p_hdr rx_header[MAX_RXRINGS][MAX_RXLEN]; - struct p_hdr tx_header[TXRINGS][TXRINGLEN]; - uint32_t c_rx[MAX_RXRINGS]; - uint32_t c_tx[TXRINGS]; - uint8_t tx_space[TXRINGS * TXRINGLEN * RING_BUFFER]; - uint8_t *rx_space; -}; - -struct notify_block { - struct n_event events[NOTIFY_EVENTS]; -}; - -struct notify_b { - struct notify_block blocks[NOTIFY_BLOCKS]; - u32 reserved1[8]; - u32 ring[NOTIFY_BLOCKS]; - u32 reserved2[8]; -}; - -static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) -{ - // cpu_tag[0] is reserved on the RTL83XX SoCs - h->cpu_tag[1] = 0x0400; // BIT 10: RTL8380_CPU_TAG - h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings below - h->cpu_tag[3] = 0x0000; - h->cpu_tag[4] = BIT(dest_port) >> 16; - h->cpu_tag[5] = BIT(dest_port) & 0xffff; - - /* Set internal priority (PRI) and enable (AS_PRI) */ - if (prio >= 0) - h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12; -} - -static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) -{ - // cpu_tag[0] is reserved on the RTL83XX SoCs - h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker - h->cpu_tag[2] = BIT(4); /* AS_DPM flag */ - h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0; - // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2 - if (dest_port >= 32) { - dest_port -= 32; - h->cpu_tag[2] |= (BIT(dest_port) >> 16) & 0xf; - h->cpu_tag[3] = BIT(dest_port) & 0xffff; - } else { - h->cpu_tag[4] = BIT(dest_port) >> 16; - h->cpu_tag[5] = BIT(dest_port) & 0xffff; - } - - /* Set internal priority (PRI) and enable (AS_PRI) */ - if (prio >= 0) - h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8; -} - -static void rtl930x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) -{ - h->cpu_tag[0] = 0x8000; // CPU tag marker - h->cpu_tag[1] = h->cpu_tag[2] = 0; - h->cpu_tag[3] = 0; - h->cpu_tag[4] = 0; - h->cpu_tag[5] = 0; - h->cpu_tag[6] = BIT(dest_port) >> 16; - h->cpu_tag[7] = BIT(dest_port) & 0xffff; - - /* Enable (AS_QID) and set priority queue (QID) */ - if (prio >= 0) - h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8; -} - -static void rtl931x_create_tx_header(struct p_hdr *h, unsigned int dest_port, int prio) -{ - h->cpu_tag[0] = 0x8000; // CPU tag marker - h->cpu_tag[1] = h->cpu_tag[2] = 0; - h->cpu_tag[3] = 0; - h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0; - if (dest_port >= 32) { - dest_port -= 32; - h->cpu_tag[4] = BIT(dest_port) >> 16; - h->cpu_tag[5] = BIT(dest_port) & 0xffff; - } else { - h->cpu_tag[6] = BIT(dest_port) >> 16; - h->cpu_tag[7] = BIT(dest_port) & 0xffff; - } - - /* Enable (AS_QID) and set priority queue (QID) */ - if (prio >= 0) - h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8; -} - -static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan) -{ - h->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload - h->cpu_tag[2] |= (vlan >> 8) & 0xf; - h->cpu_tag[3] |= (vlan & 0xff) << 8; -} - -struct rtl838x_rx_q { - int id; - struct rtl838x_eth_priv *priv; - struct napi_struct napi; -}; - -struct rtl838x_eth_priv { - struct net_device *netdev; - struct platform_device *pdev; - void *membase; - spinlock_t lock; - struct mii_bus *mii_bus; - struct rtl838x_rx_q rx_qs[MAX_RXRINGS]; - struct phylink *phylink; - struct phylink_config phylink_config; - u16 id; - u16 family_id; - const struct rtl838x_eth_reg *r; - u8 cpu_port; - u32 lastEvent; - u16 rxrings; - u16 rxringlen; - u8 smi_bus[MAX_PORTS]; - u8 smi_addr[MAX_PORTS]; - u32 sds_id[MAX_PORTS]; - bool smi_bus_isc45[MAX_SMI_BUSSES]; - bool phy_is_internal[MAX_PORTS]; - phy_interface_t interfaces[MAX_PORTS]; -}; - -extern int rtl838x_phy_init(struct rtl838x_eth_priv *priv); -extern int rtl838x_read_sds_phy(int phy_addr, int phy_reg); -extern int rtl839x_read_sds_phy(int phy_addr, int phy_reg); -extern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v); -extern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg); -extern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v); -extern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg); -extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v); -extern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); -extern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); -extern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); -extern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); - -/* - * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of - * the rings. Writing x into these registers substracts x from its content. - * When the content reaches the ring size, the ASIC no longer adds - * packets to this receive queue. - */ -void rtl838x_update_cntr(int r, int released) -{ - // This feature is not available on RTL838x SoCs -} - -void rtl839x_update_cntr(int r, int released) -{ - // This feature is not available on RTL839x SoCs -} - -void rtl930x_update_cntr(int r, int released) -{ - int pos = (r % 3) * 10; - u32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2); - u32 v = sw_r32(reg); - - v = (v >> pos) & 0x3ff; - pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released, v, pos, reg); - sw_w32_mask(0x3ff << pos, released << pos, reg); - sw_w32(v, reg); -} - -void rtl931x_update_cntr(int r, int released) -{ - int pos = (r % 3) * 10; - u32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2); - u32 v = sw_r32(reg); - - v = (v >> pos) & 0x3ff; - sw_w32_mask(0x3ff << pos, released << pos, reg); - sw_w32(v, reg); -} - -struct dsa_tag { - u8 reason; - u8 queue; - u16 port; - u8 l2_offloaded; - u8 prio; - bool crc_error; -}; - -bool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t) -{ - /* cpu_tag[0] is reserved. Fields are off-by-one */ - t->reason = h->cpu_tag[4] & 0xf; - t->queue = (h->cpu_tag[1] & 0xe0) >> 5; - t->port = h->cpu_tag[1] & 0x1f; - t->crc_error = t->reason == 13; - - pr_debug("Reason: %d\n", t->reason); - if (t->reason != 6) // NIC_RX_REASON_SPECIAL_TRAP - t->l2_offloaded = 1; - else - t->l2_offloaded = 0; - - return t->l2_offloaded; -} - -bool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t) -{ - /* cpu_tag[0] is reserved. Fields are off-by-one */ - t->reason = h->cpu_tag[5] & 0x1f; - t->queue = (h->cpu_tag[4] & 0xe000) >> 13; - t->port = h->cpu_tag[1] & 0x3f; - t->crc_error = h->cpu_tag[4] & BIT(6); - - pr_debug("Reason: %d\n", t->reason); - if ((t->reason >= 7 && t->reason <= 13) || // NIC_RX_REASON_RMA - (t->reason >= 23 && t->reason <= 25)) // NIC_RX_REASON_SPECIAL_TRAP - t->l2_offloaded = 0; - else - t->l2_offloaded = 1; - - return t->l2_offloaded; -} - -bool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t) -{ - t->reason = h->cpu_tag[7] & 0x3f; - t->queue = (h->cpu_tag[2] >> 11) & 0x1f; - t->port = (h->cpu_tag[0] >> 8) & 0x1f; - t->crc_error = h->cpu_tag[1] & BIT(6); - - pr_debug("Reason %d, port %d, queue %d\n", t->reason, t->port, t->queue); - if (t->reason >= 19 && t->reason <= 27) - t->l2_offloaded = 0; - else - t->l2_offloaded = 1; - - return t->l2_offloaded; -} - -bool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t) -{ - t->reason = h->cpu_tag[7] & 0x3f; - t->queue = (h->cpu_tag[2] >> 11) & 0x1f; - t->port = (h->cpu_tag[0] >> 8) & 0x3f; - t->crc_error = h->cpu_tag[1] & BIT(6); - - if (t->reason != 63) - pr_info("%s: Reason %d, port %d, queue %d\n", __func__, t->reason, t->port, t->queue); - if (t->reason >= 19 && t->reason <= 27) // NIC_RX_REASON_RMA - t->l2_offloaded = 0; - else - t->l2_offloaded = 1; - - return t->l2_offloaded; -} - -/* - * Discard the RX ring-buffers, called as part of the net-ISR - * when the buffer runs over - */ -static void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status) -{ - int r; - u32 *last; - struct p_hdr *h; - struct ring_b *ring = priv->membase; - - for (r = 0; r < priv->rxrings; r++) { - pr_debug("In %s working on r: %d\n", __func__, r); - last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4)); - do { - if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) - break; - pr_debug("Got something: %d\n", ring->c_rx[r]); - h = &ring->rx_header[r][ring->c_rx[r]]; - memset(h, 0, sizeof(struct p_hdr)); - h->buf = (u8 *)KSEG1ADDR(ring->rx_space - + r * priv->rxringlen * RING_BUFFER - + ring->c_rx[r] * RING_BUFFER); - h->size = RING_BUFFER; - /* make sure the header is visible to the ASIC */ - mb(); - - ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 - | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1); - ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen; - } while (&ring->rx_r[r][ring->c_rx[r]] != last); - } -} - -struct fdb_update_work { - struct work_struct work; - struct net_device *ndev; - u64 macs[NOTIFY_EVENTS + 1]; -}; - -void rtl838x_fdb_sync(struct work_struct *work) -{ - const struct fdb_update_work *uw = - container_of(work, struct fdb_update_work, work); - struct switchdev_notifier_fdb_info info; - u8 addr[ETH_ALEN]; - int i = 0; - int action; - - while (uw->macs[i]) { - action = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE - : SWITCHDEV_FDB_DEL_TO_BRIDGE; - u64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr); - info.addr = &addr[0]; - info.vid = 0; - info.offloaded = 1; - pr_debug("FDB entry %d: %llx, action %d\n", i, uw->macs[0], action); - call_switchdev_notifiers(action, uw->ndev, &info.info, NULL); - i++; - } - kfree(work); -} - -static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv) -{ - struct notify_b *nb = priv->membase + sizeof(struct ring_b); - u32 e = priv->lastEvent; - struct n_event *event; - int i; - u64 mac; - struct fdb_update_work *w; - - while (!(nb->ring[e] & 1)) { - w = kzalloc(sizeof(*w), GFP_ATOMIC); - if (!w) { - pr_err("Out of memory: %s", __func__); - return; - } - INIT_WORK(&w->work, rtl838x_fdb_sync); - - for (i = 0; i < NOTIFY_EVENTS; i++) { - event = &nb->blocks[e].events[i]; - if (!event->valid) - continue; - mac = event->mac; - if (event->type) - mac |= 1ULL << 63; - w->ndev = priv->netdev; - w->macs[i] = mac; - } - - /* Hand the ring entry back to the switch */ - nb->ring[e] = nb->ring[e] | 1; - e = (e + 1) % NOTIFY_BLOCKS; - - w->macs[i] = 0ULL; - schedule_work(&w->work); - } - priv->lastEvent = e; -} - -static irqreturn_t rtl83xx_net_irq(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - struct rtl838x_eth_priv *priv = netdev_priv(dev); - u32 status = sw_r32(priv->r->dma_if_intr_sts); - int i; - - pr_debug("IRQ: %08x\n", status); - - /* Ignore TX interrupt */ - if ((status & 0xf0000)) { - /* Clear ISR */ - sw_w32(0x000f0000, priv->r->dma_if_intr_sts); - } - - /* RX interrupt */ - if (status & 0x0ff00) { - /* ACK and disable RX interrupt for this ring */ - sw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk); - sw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts); - for (i = 0; i < priv->rxrings; i++) { - if (status & BIT(i + 8)) { - pr_debug("Scheduling queue: %d\n", i); - napi_schedule(&priv->rx_qs[i].napi); - } - } - } - - /* RX buffer overrun */ - if (status & 0x000ff) { - pr_debug("RX buffer overrun: status %x, mask: %x\n", - status, sw_r32(priv->r->dma_if_intr_msk)); - sw_w32(status, priv->r->dma_if_intr_sts); - rtl838x_rb_cleanup(priv, status & 0xff); - } - - if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) { - sw_w32(0x00100000, priv->r->dma_if_intr_sts); - rtl839x_l2_notification_handler(priv); - } - - if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) { - sw_w32(0x00200000, priv->r->dma_if_intr_sts); - rtl839x_l2_notification_handler(priv); - } - - if (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) { - sw_w32(0x00400000, priv->r->dma_if_intr_sts); - rtl839x_l2_notification_handler(priv); - } - - return IRQ_HANDLED; -} - -static irqreturn_t rtl93xx_net_irq(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - struct rtl838x_eth_priv *priv = netdev_priv(dev); - u32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts); - u32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts); - u32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts); - int i; - - pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n", - __func__, status_tx, status_rx, status_rx_r); - - /* Ignore TX interrupt */ - if (status_tx) { - /* Clear ISR */ - pr_debug("TX done\n"); - sw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts); - } - - /* RX interrupt */ - if (status_rx) { - pr_debug("RX IRQ\n"); - /* ACK and disable RX interrupt for given rings */ - sw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts); - sw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk); - for (i = 0; i < priv->rxrings; i++) { - if (status_rx & BIT(i)) { - pr_debug("Scheduling queue: %d\n", i); - napi_schedule(&priv->rx_qs[i].napi); - } - } - } - - /* RX buffer overrun */ - if (status_rx_r) { - pr_debug("RX buffer overrun: status %x, mask: %x\n", - status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk)); - sw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts); - rtl838x_rb_cleanup(priv, status_rx_r); - } - - return IRQ_HANDLED; -} - -static const struct rtl838x_eth_reg rtl838x_reg = { - .net_irq = rtl83xx_net_irq, - .mac_port_ctrl = rtl838x_mac_port_ctrl, - .dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS, - .dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK, - .dma_if_ctrl = RTL838X_DMA_IF_CTRL, - .mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL, - .dma_rx_base = RTL838X_DMA_RX_BASE, - .dma_tx_base = RTL838X_DMA_TX_BASE, - .dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size, - .dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr, - .dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR, - .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0, - .get_mac_link_sts = rtl838x_get_mac_link_sts, - .get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts, - .get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts, - .get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts, - .get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts, - .mac = RTL838X_MAC, - .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL, - .update_cntr = rtl838x_update_cntr, - .create_tx_header = rtl838x_create_tx_header, - .decode_tag = rtl838x_decode_tag, -}; - -static const struct rtl838x_eth_reg rtl839x_reg = { - .net_irq = rtl83xx_net_irq, - .mac_port_ctrl = rtl839x_mac_port_ctrl, - .dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS, - .dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK, - .dma_if_ctrl = RTL839X_DMA_IF_CTRL, - .mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL, - .dma_rx_base = RTL839X_DMA_RX_BASE, - .dma_tx_base = RTL839X_DMA_TX_BASE, - .dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size, - .dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr, - .dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR, - .rst_glb_ctrl = RTL839X_RST_GLB_CTRL, - .get_mac_link_sts = rtl839x_get_mac_link_sts, - .get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts, - .get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts, - .get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts, - .get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts, - .mac = RTL839X_MAC, - .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, - .update_cntr = rtl839x_update_cntr, - .create_tx_header = rtl839x_create_tx_header, - .decode_tag = rtl839x_decode_tag, -}; - -static const struct rtl838x_eth_reg rtl930x_reg = { - .net_irq = rtl93xx_net_irq, - .mac_port_ctrl = rtl930x_mac_port_ctrl, - .dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS, - .dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS, - .dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS, - .dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK, - .dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK, - .dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK, - .l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS, - .l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK, - .dma_if_ctrl = RTL930X_DMA_IF_CTRL, - .mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL, - .dma_rx_base = RTL930X_DMA_RX_BASE, - .dma_tx_base = RTL930X_DMA_TX_BASE, - .dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size, - .dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr, - .dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR, - .rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0, - .get_mac_link_sts = rtl930x_get_mac_link_sts, - .get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts, - .get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts, - .get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts, - .get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts, - .mac = RTL930X_MAC_L2_ADDR_CTRL, - .l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL, - .update_cntr = rtl930x_update_cntr, - .create_tx_header = rtl930x_create_tx_header, - .decode_tag = rtl930x_decode_tag, -}; - -static const struct rtl838x_eth_reg rtl931x_reg = { - .net_irq = rtl93xx_net_irq, - .mac_port_ctrl = rtl931x_mac_port_ctrl, - .dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS, - .dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS, - .dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS, - .dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK, - .dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK, - .dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK, - .l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS, - .l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK, - .dma_if_ctrl = RTL931X_DMA_IF_CTRL, - .mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL, - .dma_rx_base = RTL931X_DMA_RX_BASE, - .dma_tx_base = RTL931X_DMA_TX_BASE, - .dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size, - .dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr, - .dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR, - .rst_glb_ctrl = RTL931X_RST_GLB_CTRL, - .get_mac_link_sts = rtl931x_get_mac_link_sts, - .get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts, - .get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts, - .get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts, - .get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts, - .mac = RTL931X_MAC_L2_ADDR_CTRL, - .l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL, - .update_cntr = rtl931x_update_cntr, - .create_tx_header = rtl931x_create_tx_header, - .decode_tag = rtl931x_decode_tag, -}; - -static void rtl838x_hw_reset(struct rtl838x_eth_priv *priv) -{ - u32 int_saved, nbuf; - u32 reset_mask; - int i, pos; - - pr_info("RESETTING %x, CPU_PORT %d\n", priv->family_id, priv->cpu_port); - sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port)); - mdelay(100); - - /* Disable and clear interrupts */ - if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) { - sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk); - sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts); - sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk); - sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts); - sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk); - sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts); - } else { - sw_w32(0x00000000, priv->r->dma_if_intr_msk); - sw_w32(0xffffffff, priv->r->dma_if_intr_sts); - } - - if (priv->family_id == RTL8390_FAMILY_ID) { - /* Preserve L2 notification and NBUF settings */ - int_saved = sw_r32(priv->r->dma_if_intr_msk); - nbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL); - - /* Disable link change interrupt on RTL839x */ - sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG); - sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4); - - sw_w32(0x00000000, priv->r->dma_if_intr_msk); - sw_w32(0xffffffff, priv->r->dma_if_intr_sts); - } - - /* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */ - if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) - reset_mask = 0x6; - else - reset_mask = 0xc; - - sw_w32_mask(0, reset_mask, priv->r->rst_glb_ctrl); - - do { /* Wait for reset of NIC and Queues done */ - udelay(20); - } while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask); - mdelay(100); - - /* Setup Head of Line */ - if (priv->family_id == RTL8380_FAMILY_ID) - sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE); // Disabled on RTL8380 - if (priv->family_id == RTL8390_FAMILY_ID) - sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR); - if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) { - for (i = 0; i < priv->rxrings; i++) { - pos = (i % 3) * 10; - sw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i)); - sw_w32_mask(0x3ff << pos, priv->rxringlen, - priv->r->dma_if_rx_ring_cntr(i)); - } - } - - /* Re-enable link change interrupt */ - if (priv->family_id == RTL8390_FAMILY_ID) { - sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG); - sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4); - sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG); - sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4); - - /* Restore notification settings: on RTL838x these bits are null */ - sw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk); - sw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL); - } -} - -static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv) -{ - int i; - struct ring_b *ring = priv->membase; - - for (i = 0; i < priv->rxrings; i++) - sw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4); - - for (i = 0; i < TXRINGS; i++) - sw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4); -} - -static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv) -{ - /* Disable Head of Line features for all RX rings */ - sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0)); - - /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */ - sw_w32(0x06400020, priv->r->dma_if_ctrl); - - /* Enable RX done, RX overflow and TX done interrupts */ - sw_w32(0xfffff, priv->r->dma_if_intr_msk); - - /* Enable DMA, engine expects empty FCS field */ - sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl); - - /* Restart TX/RX to CPU port */ - sw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port)); - /* Set Speed, duplex, flow control - * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL - * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN - * | MEDIA_SEL - */ - sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4); - - /* Enable CRC checks on CPU-port */ - sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port)); -} - -static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv) -{ - /* Setup CPU-Port: RX Buffer */ - sw_w32(0x0000c808, priv->r->dma_if_ctrl); - - /* Enable Notify, RX done, RX overflow and TX done interrupts */ - sw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ! - - /* Enable DMA */ - sw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl); - - /* Restart TX/RX to CPU port, enable CRC checking */ - sw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port)); - - /* CPU port joins Lookup Miss Flooding Portmask */ - // TODO: The code below should also work for the RTL838x - sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL); - sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0)); - sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL); - - /* Force CPU port link up */ - sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4); -} - -static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv) -{ - int i, pos; - u32 v; - - /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */ - sw_w32(0x06400040, priv->r->dma_if_ctrl); - - for (i = 0; i < priv->rxrings; i++) { - pos = (i % 3) * 10; - sw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i)); - - // Some SoCs have issues with missing underflow protection - v = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff; - sw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i)); - } - - /* Enable Notify, RX done, RX overflow and TX done interrupts */ - sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk); - sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk); - sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk); - - /* Enable DMA */ - sw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl); - - /* Restart TX/RX to CPU port, enable CRC checking */ - sw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port)); - - if (priv->family_id == RTL9300_FAMILY_ID) - sw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK); - else - sw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK); - - if (priv->family_id == RTL9300_FAMILY_ID) - sw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4); - else - sw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4); -} - -static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring) -{ - int i, j; - - struct p_hdr *h; - - for (i = 0; i < priv->rxrings; i++) { - for (j = 0; j < priv->rxringlen; j++) { - h = &ring->rx_header[i][j]; - memset(h, 0, sizeof(struct p_hdr)); - h->buf = (u8 *)KSEG1ADDR(ring->rx_space - + i * priv->rxringlen * RING_BUFFER - + j * RING_BUFFER); - h->size = RING_BUFFER; - /* All rings owned by switch, last one wraps */ - ring->rx_r[i][j] = KSEG1ADDR(h) | 1 - | (j == (priv->rxringlen - 1) ? WRAP : 0); - } - ring->c_rx[i] = 0; - } - - for (i = 0; i < TXRINGS; i++) { - for (j = 0; j < TXRINGLEN; j++) { - h = &ring->tx_header[i][j]; - memset(h, 0, sizeof(struct p_hdr)); - h->buf = (u8 *)KSEG1ADDR(ring->tx_space - + i * TXRINGLEN * RING_BUFFER - + j * RING_BUFFER); - h->size = RING_BUFFER; - ring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]); - } - /* Last header is wrapping around */ - ring->tx_r[i][j-1] |= WRAP; - ring->c_tx[i] = 0; - } -} - -static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv) -{ - int i; - struct notify_b *b = priv->membase + sizeof(struct ring_b); - - for (i = 0; i < NOTIFY_BLOCKS; i++) - b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0); - - sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL); - sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL); - - /* Setup notification events */ - sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN - sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN - - /* Enable Notification */ - sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL); - priv->lastEvent = 0; -} - -static int rtl838x_eth_open(struct net_device *ndev) -{ - unsigned long flags; - struct rtl838x_eth_priv *priv = netdev_priv(ndev); - struct ring_b *ring = priv->membase; - int i; - - pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n", - __func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN); - - spin_lock_irqsave(&priv->lock, flags); - rtl838x_hw_reset(priv); - rtl838x_setup_ring_buffer(priv, ring); - if (priv->family_id == RTL8390_FAMILY_ID) { - rtl839x_setup_notify_ring_buffer(priv); - /* Make sure the ring structure is visible to the ASIC */ - mb(); - flush_cache_all(); - } - - rtl838x_hw_ring_setup(priv); - phylink_start(priv->phylink); - - for (i = 0; i < priv->rxrings; i++) - napi_enable(&priv->rx_qs[i].napi); - - switch (priv->family_id) { - case RTL8380_FAMILY_ID: - rtl838x_hw_en_rxtx(priv); - /* Trap IGMP/MLD traffic to CPU-Port */ - sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL); - /* Flush learned FDB entries on link down of a port */ - sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0); - break; - - case RTL8390_FAMILY_ID: - rtl839x_hw_en_rxtx(priv); - // Trap MLD and IGMP messages to CPU_PORT - sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL); - /* Flush learned FDB entries on link down of a port */ - sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0); - break; - - case RTL9300_FAMILY_ID: - rtl93xx_hw_en_rxtx(priv); - /* Flush learned FDB entries on link down of a port */ - sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL); - // Trap MLD and IGMP messages to CPU_PORT - sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL); - break; - - case RTL9310_FAMILY_ID: - rtl93xx_hw_en_rxtx(priv); - - // Trap MLD and IGMP messages to CPU_PORT - sw_w32((0x2 << 3) | 0x2, RTL931X_VLAN_APP_PKT_CTRL); - - // Disable External CPU access to switch, clear EXT_CPU_EN - sw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2); - - // Set PCIE_PWR_DOWN - sw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL); - break; - } - - netif_tx_start_all_queues(ndev); - - spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv) -{ - u32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75; - u32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff; - int i; - - // Disable RX/TX from/to CPU-port - sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port)); - - /* Disable traffic */ - if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) - sw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl); - else - sw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl); - mdelay(200); // Test, whether this is needed - - /* Block all ports */ - if (priv->family_id == RTL8380_FAMILY_ID) { - sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0)); - sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1)); - sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0); - } - - /* Flush L2 address cache */ - if (priv->family_id == RTL8380_FAMILY_ID) { - for (i = 0; i <= priv->cpu_port; i++) { - sw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl); - do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26)); - } - } else if (priv->family_id == RTL8390_FAMILY_ID) { - for (i = 0; i <= priv->cpu_port; i++) { - sw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl); - do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28)); - } - } - // TODO: L2 flush register is 64 bit on RTL931X and 930X - - /* CPU-Port: Link down */ - if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID) - sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4); - else if (priv->family_id == RTL9300_FAMILY_ID) - sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4); - else if (priv->family_id == RTL9310_FAMILY_ID) - sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4); - mdelay(100); - - /* Disable all TX/RX interrupts */ - if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) { - sw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk); - sw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts); - sw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk); - sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts); - sw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk); - sw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts); - } else { - sw_w32(0x00000000, priv->r->dma_if_intr_msk); - sw_w32(clear_irq, priv->r->dma_if_intr_sts); - } - - /* Disable TX/RX DMA */ - sw_w32(0x00000000, priv->r->dma_if_ctrl); - mdelay(200); -} - -static int rtl838x_eth_stop(struct net_device *ndev) -{ - unsigned long flags; - int i; - struct rtl838x_eth_priv *priv = netdev_priv(ndev); - - pr_info("in %s\n", __func__); - - phylink_stop(priv->phylink); - rtl838x_hw_stop(priv); - - for (i = 0; i < priv->rxrings; i++) - napi_disable(&priv->rx_qs[i].napi); - - netif_tx_stop_all_queues(ndev); - - return 0; -} - -static void rtl838x_eth_set_multicast_list(struct net_device *ndev) -{ - /* - * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) - * CTRL_0_FULL = GENMASK(21, 0) = 0x3FFFFF - */ - if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { - sw_w32(0x0, RTL838X_RMA_CTRL_0); - sw_w32(0x0, RTL838X_RMA_CTRL_1); - } - if (ndev->flags & IFF_ALLMULTI) - sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0); - if (ndev->flags & IFF_PROMISC) { - sw_w32(GENMASK(21, 0), RTL838X_RMA_CTRL_0); - sw_w32(0x7fff, RTL838X_RMA_CTRL_1); - } -} - -static void rtl839x_eth_set_multicast_list(struct net_device *ndev) -{ - /* - * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) - * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC - * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 - * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) - */ - if (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) { - sw_w32(0x0, RTL839X_RMA_CTRL_0); - sw_w32(0x0, RTL839X_RMA_CTRL_1); - sw_w32(0x0, RTL839X_RMA_CTRL_2); - sw_w32(0x0, RTL839X_RMA_CTRL_3); - } - if (ndev->flags & IFF_ALLMULTI) { - sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0); - sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1); - sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2); - } - if (ndev->flags & IFF_PROMISC) { - sw_w32(GENMASK(31, 2), RTL839X_RMA_CTRL_0); - sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_1); - sw_w32(GENMASK(31, 0), RTL839X_RMA_CTRL_2); - sw_w32(0x3ff, RTL839X_RMA_CTRL_3); - } -} - -static void rtl930x_eth_set_multicast_list(struct net_device *ndev) -{ - /* - * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) - * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC - * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00 - * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) - */ - if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) { - sw_w32(GENMASK(31, 2), RTL930X_RMA_CTRL_0); - sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_1); - sw_w32(GENMASK(31, 0), RTL930X_RMA_CTRL_2); - } else { - sw_w32(0x0, RTL930X_RMA_CTRL_0); - sw_w32(0x0, RTL930X_RMA_CTRL_1); - sw_w32(0x0, RTL930X_RMA_CTRL_2); - } -} - -static void rtl931x_eth_set_multicast_list(struct net_device *ndev) -{ - /* - * Flood all classes of RMA addresses (01-80-C2-00-00-{01..2F}) - * CTRL_0_FULL = GENMASK(31, 2) = 0xFFFFFFFC - * Lower two bits are reserved, corresponding to RMA 01-80-C2-00-00-00. - * CTRL_1_FULL = CTRL_2_FULL = GENMASK(31, 0) - */ - if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC)) { - sw_w32(GENMASK(31, 2), RTL931X_RMA_CTRL_0); - sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_1); - sw_w32(GENMASK(31, 0), RTL931X_RMA_CTRL_2); - } else { - sw_w32(0x0, RTL931X_RMA_CTRL_0); - sw_w32(0x0, RTL931X_RMA_CTRL_1); - sw_w32(0x0, RTL931X_RMA_CTRL_2); - } -} - -static void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue) -{ - unsigned long flags; - struct rtl838x_eth_priv *priv = netdev_priv(ndev); - - pr_warn("%s\n", __func__); - spin_lock_irqsave(&priv->lock, flags); - rtl838x_hw_stop(priv); - rtl838x_hw_ring_setup(priv); - rtl838x_hw_en_rxtx(priv); - netif_trans_update(ndev); - netif_start_queue(ndev); - spin_unlock_irqrestore(&priv->lock, flags); -} - -static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev) -{ - int len, i; - struct rtl838x_eth_priv *priv = netdev_priv(dev); - struct ring_b *ring = priv->membase; - uint32_t val; - int ret; - unsigned long flags; - struct p_hdr *h; - int dest_port = -1; - int q = skb_get_queue_mapping(skb) % TXRINGS; - - if (q) // Check for high prio queue - pr_debug("SKB priority: %d\n", skb->priority); - - spin_lock_irqsave(&priv->lock, flags); - len = skb->len; - - /* Check for DSA tagging at the end of the buffer */ - if (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 - && skb->data[len-3] < priv->cpu_port - && skb->data[len-2] == 0x10 - && skb->data[len-1] == 0x00) { - /* Reuse tag space for CRC if possible */ - dest_port = skb->data[len-3]; - skb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00; - len -= 4; - } - - len += 4; // Add space for CRC - - if (skb_padto(skb, len)) { - ret = NETDEV_TX_OK; - goto txdone; - } - - /* We can send this packet if CPU owns the descriptor */ - if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) { - - /* Set descriptor for tx */ - h = &ring->tx_header[q][ring->c_tx[q]]; - h->size = len; - h->len = len; - // On RTL8380 SoCs, small packet lengths being sent need adjustments - if (priv->family_id == RTL8380_FAMILY_ID) { - if (len < ETH_ZLEN - 4) - h->len -= 4; - } - - if (dest_port >= 0) - priv->r->create_tx_header(h, dest_port, skb->priority >> 1); - - /* Copy packet data to tx buffer */ - memcpy((void *)KSEG1ADDR(h->buf), skb->data, len); - /* Make sure packet data is visible to ASIC */ - wmb(); - - /* Hand over to switch */ - ring->tx_r[q][ring->c_tx[q]] |= 1; - - // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs - if (priv->family_id == RTL8380_FAMILY_ID) { - for (i = 0; i < 10; i++) { - val = sw_r32(priv->r->dma_if_ctrl); - if ((val & 0xc) == 0xc) - break; - } - } - - /* Tell switch to send data */ - if (priv->family_id == RTL9310_FAMILY_ID - || priv->family_id == RTL9300_FAMILY_ID) { - // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue - if (!q) - sw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl); - else - sw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl); - } else { - sw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl); - } - - dev->stats.tx_packets++; - dev->stats.tx_bytes += len; - dev_kfree_skb(skb); - ring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN; - ret = NETDEV_TX_OK; - } else { - dev_warn(&priv->pdev->dev, "Data is owned by switch\n"); - ret = NETDEV_TX_BUSY; - } -txdone: - spin_unlock_irqrestore(&priv->lock, flags); - return ret; -} - -/* - * Return queue number for TX. On the RTL83XX, these queues have equal priority - * so we do round-robin - */ -u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, - struct net_device *sb_dev) -{ - static u8 last = 0; - - last++; - return last % TXRINGS; -} - -/* - * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue - */ -u16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb, - struct net_device *sb_dev) -{ - if (skb->priority >= TC_PRIO_CONTROL) - return 1; - return 0; -} - -static int rtl838x_hw_receive(struct net_device *dev, int r, int budget) -{ - struct rtl838x_eth_priv *priv = netdev_priv(dev); - struct ring_b *ring = priv->membase; - struct sk_buff *skb; - LIST_HEAD(rx_list); - unsigned long flags; - int i, len, work_done = 0; - u8 *data, *skb_data; - unsigned int val; - u32 *last; - struct p_hdr *h; - bool dsa = netdev_uses_dsa(dev); - struct dsa_tag tag; - - pr_debug("---------------------------------------------------------- RX - %d\n", r); - spin_lock_irqsave(&priv->lock, flags); - last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4)); - - do { - if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) { - if (&ring->rx_r[r][ring->c_rx[r]] != last) { - netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n", - r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]); - } - break; - } - - h = &ring->rx_header[r][ring->c_rx[r]]; - data = (u8 *)KSEG1ADDR(h->buf); - len = h->len; - if (!len) - break; - work_done++; - - len -= 4; /* strip the CRC */ - /* Add 4 bytes for cpu_tag */ - if (dsa) - len += 4; - - skb = netdev_alloc_skb(dev, len + 4); - skb_reserve(skb, NET_IP_ALIGN); - - if (likely(skb)) { - /* BUG: Prevent bug on RTL838x SoCs*/ - if (priv->family_id == RTL8380_FAMILY_ID) { - sw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0)); - for (i = 0; i < priv->rxrings; i++) { - /* Update each ring cnt */ - val = sw_r32(priv->r->dma_if_rx_ring_cntr(i)); - sw_w32(val, priv->r->dma_if_rx_ring_cntr(i)); - } - } - - skb_data = skb_put(skb, len); - /* Make sure data is visible */ - mb(); - memcpy(skb->data, (u8 *)KSEG1ADDR(data), len); - /* Overwrite CRC with cpu_tag */ - if (dsa) { - priv->r->decode_tag(h, &tag); - skb->data[len-4] = 0x80; - skb->data[len-3] = tag.port; - skb->data[len-2] = 0x10; - skb->data[len-1] = 0x00; - if (tag.l2_offloaded) - skb->data[len-3] |= 0x40; - } - - if (tag.queue >= 0) - pr_debug("Queue: %d, len: %d, reason %d port %d\n", - tag.queue, len, tag.reason, tag.port); - - skb->protocol = eth_type_trans(skb, dev); - if (dev->features & NETIF_F_RXCSUM) { - if (tag.crc_error) - skb_checksum_none_assert(skb); - else - skb->ip_summed = CHECKSUM_UNNECESSARY; - } - dev->stats.rx_packets++; - dev->stats.rx_bytes += len; - - list_add_tail(&skb->list, &rx_list); - } else { - if (net_ratelimit()) - dev_warn(&dev->dev, "low on memory - packet dropped\n"); - dev->stats.rx_dropped++; - } - - /* Reset header structure */ - memset(h, 0, sizeof(struct p_hdr)); - h->buf = data; - h->size = RING_BUFFER; - - ring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 - | (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1); - ring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen; - last = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4)); - } while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget); - - netif_receive_skb_list(&rx_list); - - // Update counters - priv->r->update_cntr(r, 0); - - spin_unlock_irqrestore(&priv->lock, flags); - - return work_done; -} - -static int rtl838x_poll_rx(struct napi_struct *napi, int budget) -{ - struct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi); - struct rtl838x_eth_priv *priv = rx_q->priv; - int work_done = 0; - int r = rx_q->id; - int work; - - while (work_done < budget) { - work = rtl838x_hw_receive(priv->netdev, r, budget - work_done); - if (!work) - break; - work_done += work; - } - - if (work_done < budget) { - napi_complete_done(napi, work_done); - - /* Enable RX interrupt */ - if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) - sw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk); - else - sw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk); - } - return work_done; -} - - -static void rtl838x_validate(struct phylink_config *config, - unsigned long *supported, - struct phylink_link_state *state) -{ - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - - pr_debug("In %s\n", __func__); - - if (!phy_interface_mode_is_rgmii(state->interface) && - state->interface != PHY_INTERFACE_MODE_1000BASEX && - state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII && - state->interface != PHY_INTERFACE_MODE_GMII && - state->interface != PHY_INTERFACE_MODE_QSGMII && - state->interface != PHY_INTERFACE_MODE_INTERNAL && - state->interface != PHY_INTERFACE_MODE_SGMII) { - bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); - pr_err("Unsupported interface: %d\n", state->interface); - return; - } - - /* Allow all the expected bits */ - phylink_set(mask, Autoneg); - phylink_set_port_modes(mask); - phylink_set(mask, Pause); - phylink_set(mask, Asym_Pause); - - /* With the exclusion of MII and Reverse MII, we support Gigabit, - * including Half duplex - */ - if (state->interface != PHY_INTERFACE_MODE_MII && - state->interface != PHY_INTERFACE_MODE_REVMII) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseT_Half); - } - - phylink_set(mask, 10baseT_Half); - phylink_set(mask, 10baseT_Full); - phylink_set(mask, 100baseT_Half); - phylink_set(mask, 100baseT_Full); - - bitmap_and(supported, supported, mask, - __ETHTOOL_LINK_MODE_MASK_NBITS); - bitmap_and(state->advertising, state->advertising, mask, - __ETHTOOL_LINK_MODE_MASK_NBITS); -} - - -static void rtl838x_mac_config(struct phylink_config *config, - unsigned int mode, - const struct phylink_link_state *state) -{ - /* This is only being called for the master device, - * i.e. the CPU-Port. We don't need to do anything. - */ - - pr_info("In %s, mode %x\n", __func__, mode); -} - -static void rtl838x_mac_an_restart(struct phylink_config *config) -{ - struct net_device *dev = container_of(config->dev, struct net_device, dev); - struct rtl838x_eth_priv *priv = netdev_priv(dev); - - /* This works only on RTL838x chips */ - if (priv->family_id != RTL8380_FAMILY_ID) - return; - - pr_debug("In %s\n", __func__); - /* Restart by disabling and re-enabling link */ - sw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4); - mdelay(20); - sw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4); -} - -static void rtl838x_mac_pcs_get_state(struct phylink_config *config, - struct phylink_link_state *state) -{ - u32 speed; - struct net_device *dev = container_of(config->dev, struct net_device, dev); - struct rtl838x_eth_priv *priv = netdev_priv(dev); - int port = priv->cpu_port; - - pr_info("In %s\n", __func__); - - state->link = priv->r->get_mac_link_sts(port) ? 1 : 0; - state->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0; - - pr_info("%s link status is %d\n", __func__, state->link); - speed = priv->r->get_mac_link_spd_sts(port); - switch (speed) { - case 0: - state->speed = SPEED_10; - break; - case 1: - state->speed = SPEED_100; - break; - case 2: - state->speed = SPEED_1000; - break; - case 5: - state->speed = SPEED_2500; - break; - case 6: - state->speed = SPEED_5000; - break; - case 4: - state->speed = SPEED_10000; - break; - default: - state->speed = SPEED_UNKNOWN; - break; - } - - state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); - if (priv->r->get_mac_rx_pause_sts(port)) - state->pause |= MLO_PAUSE_RX; - if (priv->r->get_mac_tx_pause_sts(port)) - state->pause |= MLO_PAUSE_TX; -} - -static void rtl838x_mac_link_down(struct phylink_config *config, - unsigned int mode, - phy_interface_t interface) -{ - struct net_device *dev = container_of(config->dev, struct net_device, dev); - struct rtl838x_eth_priv *priv = netdev_priv(dev); - - pr_debug("In %s\n", __func__); - /* Stop TX/RX to port */ - sw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port)); -} - -static void rtl838x_mac_link_up(struct phylink_config *config, - struct phy_device *phy, unsigned int mode, - phy_interface_t interface, int speed, int duplex, - bool tx_pause, bool rx_pause) -{ - struct net_device *dev = container_of(config->dev, struct net_device, dev); - struct rtl838x_eth_priv *priv = netdev_priv(dev); - - pr_debug("In %s\n", __func__); - /* Restart TX/RX to port */ - sw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port)); -} - -static void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac) -{ - struct rtl838x_eth_priv *priv = netdev_priv(dev); - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - pr_debug("In %s\n", __func__); - sw_w32((mac[0] << 8) | mac[1], priv->r->mac); - sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4); - - if (priv->family_id == RTL8380_FAMILY_ID) { - /* 2 more registers, ALE/MAC block */ - sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE); - sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], - (RTL838X_MAC_ALE + 4)); - - sw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2); - sw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], - RTL838X_MAC2 + 4); - } - spin_unlock_irqrestore(&priv->lock, flags); -} - -static int rtl838x_set_mac_address(struct net_device *dev, void *p) -{ - struct rtl838x_eth_priv *priv = netdev_priv(dev); - const struct sockaddr *addr = p; - u8 *mac = (u8 *) (addr->sa_data); - - if (!is_valid_ether_addr(addr->sa_data)) - return -EADDRNOTAVAIL; - - memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); - rtl838x_set_mac_hw(dev, mac); - - pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4)); - return 0; -} - -static int rtl8390_init_mac(struct rtl838x_eth_priv *priv) -{ - // We will need to set-up EEE and the egress-rate limitation - return 0; -} - -static int rtl8380_init_mac(struct rtl838x_eth_priv *priv) -{ - int i; - - if (priv->family_id == 0x8390) - return rtl8390_init_mac(priv); - - // At present we do not know how to set up EEE on any other SoC than RTL8380 - if (priv->family_id != 0x8380) - return 0; - - pr_info("%s\n", __func__); - /* fix timer for EEE */ - sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL); - sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL); - - /* Init VLAN. TODO: Understand what is being done, here */ - if (priv->id == 0x8382) { - for (i = 0; i <= 28; i++) - sw_w32(0, 0xd57c + i * 0x80); - } - if (priv->id == 0x8380) { - for (i = 8; i <= 28; i++) - sw_w32(0, 0xd57c + i * 0x80); - } - return 0; -} - -static int rtl838x_get_link_ksettings(struct net_device *ndev, - struct ethtool_link_ksettings *cmd) -{ - struct rtl838x_eth_priv *priv = netdev_priv(ndev); - - pr_debug("%s called\n", __func__); - return phylink_ethtool_ksettings_get(priv->phylink, cmd); -} - -static int rtl838x_set_link_ksettings(struct net_device *ndev, - const struct ethtool_link_ksettings *cmd) -{ - struct rtl838x_eth_priv *priv = netdev_priv(ndev); - - pr_debug("%s called\n", __func__); - return phylink_ethtool_ksettings_set(priv->phylink, cmd); -} - -static int rtl838x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum) -{ - u32 val; - int err; - struct rtl838x_eth_priv *priv = bus->priv; - - if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) - return rtl838x_read_sds_phy(mii_id, regnum); - - if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { - err = rtl838x_read_mmd_phy(mii_id, - mdiobus_c45_devad(regnum), - regnum, &val); - pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id, - mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum), - val, err); - } else { - pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err); - err = rtl838x_read_phy(mii_id, page, regnum, &val); - } - if (err) - return err; - return val; -} - -static int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -{ - return rtl838x_mdio_read_paged(bus, mii_id, 0, regnum); -} - -static int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum) -{ - u32 val; - int err; - struct rtl838x_eth_priv *priv = bus->priv; - - if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393) - return rtl839x_read_sds_phy(mii_id, regnum); - - if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { - err = rtl839x_read_mmd_phy(mii_id, - mdiobus_c45_devad(regnum), - regnum, &val); - pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id, - mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum), - val, err); - } else { - err = rtl839x_read_phy(mii_id, page, regnum, &val); - pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err); - } - if (err) - return err; - return val; -} - -static int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -{ - return rtl839x_mdio_read_paged(bus, mii_id, 0, regnum); -} - -static int rtl930x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum) -{ - u32 val; - int err; - struct rtl838x_eth_priv *priv = bus->priv; - - if (priv->phy_is_internal[mii_id]) - return rtl930x_read_sds_phy(priv->sds_id[mii_id], page, regnum); - - if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { - err = rtl930x_read_mmd_phy(mii_id, - mdiobus_c45_devad(regnum), - regnum, &val); - pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id, - mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum), - val, err); - } else { - err = rtl930x_read_phy(mii_id, page, regnum, &val); - pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err); - } - if (err) - return err; - return val; -} - -static int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -{ - return rtl930x_mdio_read_paged(bus, mii_id, 0, regnum); -} - -static int rtl931x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum) -{ - u32 val; - int err, v; - struct rtl838x_eth_priv *priv = bus->priv; - - pr_debug("%s: In here, port %d\n", __func__, mii_id); - if (priv->phy_is_internal[mii_id]) { - v = rtl931x_read_sds_phy(priv->sds_id[mii_id], page, regnum); - if (v < 0) { - err = v; - } else { - err = 0; - val = v; - } - } else { - if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { - err = rtl931x_read_mmd_phy(mii_id, - mdiobus_c45_devad(regnum), - regnum, &val); - pr_debug("MMD: %d dev %x register %x read %x, err %d\n", mii_id, - mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum), - val, err); - } else { - err = rtl931x_read_phy(mii_id, page, regnum, &val); - pr_debug("PHY: %d register %x read %x, err %d\n", mii_id, regnum, val, err); - } - } - - if (err) - return err; - return val; -} - -static int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -{ - return rtl931x_mdio_read_paged(bus, mii_id, 0, regnum); -} - -static int rtl838x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, - int regnum, u16 value) -{ - u32 offset = 0; - struct rtl838x_eth_priv *priv = bus->priv; - int err; - - if (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) { - if (mii_id == 26) - offset = 0x100; - sw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2)); - return 0; - } - - if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { - err = rtl838x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum), - regnum, value); - pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id, - mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum), - value, err); - - return err; - } - err = rtl838x_write_phy(mii_id, page, regnum, value); - pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err); - return err; -} - -static int rtl838x_mdio_write(struct mii_bus *bus, int mii_id, - int regnum, u16 value) -{ - return rtl838x_mdio_write_paged(bus, mii_id, 0, regnum, value); -} - -static int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, - int regnum, u16 value) -{ - struct rtl838x_eth_priv *priv = bus->priv; - int err; - - if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393) - return rtl839x_write_sds_phy(mii_id, regnum, value); - - if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { - err = rtl839x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum), - regnum, value); - pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id, - mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum), - value, err); - - return err; - } - - err = rtl839x_write_phy(mii_id, page, regnum, value); - pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err); - return err; -} - -static int rtl839x_mdio_write(struct mii_bus *bus, int mii_id, - int regnum, u16 value) -{ - return rtl839x_mdio_write_paged(bus, mii_id, 0, regnum, value); -} - -static int rtl930x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, - int regnum, u16 value) -{ - struct rtl838x_eth_priv *priv = bus->priv; - int err; - - if (priv->phy_is_internal[mii_id]) - return rtl930x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value); - - if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) - return rtl930x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum), - regnum, value); - - err = rtl930x_write_phy(mii_id, page, regnum, value); - pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err); - return err; -} - -static int rtl930x_mdio_write(struct mii_bus *bus, int mii_id, - int regnum, u16 value) -{ - return rtl930x_mdio_write_paged(bus, mii_id, 0, regnum, value); -} - -static int rtl931x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page, - int regnum, u16 value) -{ - struct rtl838x_eth_priv *priv = bus->priv; - int err; - - if (priv->phy_is_internal[mii_id]) - return rtl931x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value); - - if (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) { - err = rtl931x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum), - regnum, value); - pr_debug("MMD: %d dev %x register %x write %x, err %d\n", mii_id, - mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum), - value, err); - - return err; - } - - err = rtl931x_write_phy(mii_id, page, regnum, value); - pr_debug("PHY: %d register %x write %x, err %d\n", mii_id, regnum, value, err); - return err; -} - -static int rtl931x_mdio_write(struct mii_bus *bus, int mii_id, - int regnum, u16 value) -{ - return rtl931x_mdio_write_paged(bus, mii_id, 0, regnum, value); -} - -static int rtl838x_mdio_reset(struct mii_bus *bus) -{ - pr_debug("%s called\n", __func__); - /* Disable MAC polling the PHY so that we can start configuration */ - sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL); - - /* Enable PHY control via SoC */ - sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL); - - // Probably should reset all PHYs here... - return 0; -} - -static int rtl839x_mdio_reset(struct mii_bus *bus) -{ - return 0; - - pr_debug("%s called\n", __func__); - /* BUG: The following does not work, but should! */ - /* Disable MAC polling the PHY so that we can start configuration */ - sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL); - sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4); - /* Disable PHY polling via SoC */ - sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL); - - // Probably should reset all PHYs here... - return 0; -} - -u8 mac_type_bit[RTL930X_CPU_PORT] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6, 6, - 8, 8, 8, 8, 10, 10, 10, 10, 12, 15, 18, 21}; - -static int rtl930x_mdio_reset(struct mii_bus *bus) -{ - int i; - int pos; - struct rtl838x_eth_priv *priv = bus->priv; - u32 c45_mask = 0; - u32 poll_sel[2]; - u32 poll_ctrl = 0; - u32 private_poll_mask = 0; - u32 v; - bool uses_usxgmii = false; // For the Aquantia PHYs - bool uses_hisgmii = false; // For the RTL8221/8226 - - // Mapping of port to phy-addresses on an SMI bus - poll_sel[0] = poll_sel[1] = 0; - for (i = 0; i < RTL930X_CPU_PORT; i++) { - if (priv->smi_bus[i] > 3) - continue; - pos = (i % 6) * 5; - sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, - RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4); - - pos = (i * 2) % 32; - poll_sel[i / 16] |= priv->smi_bus[i] << pos; - poll_ctrl |= BIT(20 + priv->smi_bus[i]); - } - - // Configure which SMI bus is behind which port number - sw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL); - sw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL); - - // Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+) - sw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL); - - // Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus - for (i = 0; i < 4; i++) - if (priv->smi_bus_isc45[i]) - c45_mask |= BIT(i + 16); - - pr_info("c45_mask: %08x\n", c45_mask); - sw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL); - - // Set the MAC type of each port according to the PHY-interface - // Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0 - v = 0; - for (i = 0; i < RTL930X_CPU_PORT; i++) { - switch (priv->interfaces[i]) { - case PHY_INTERFACE_MODE_10GBASER: - break; // Serdes: Value = 0 - - case PHY_INTERFACE_MODE_HSGMII: - private_poll_mask |= BIT(i); - // fallthrough - case PHY_INTERFACE_MODE_USXGMII: - v |= BIT(mac_type_bit[i]); - uses_usxgmii = true; - break; - - case PHY_INTERFACE_MODE_QSGMII: - private_poll_mask |= BIT(i); - v |= 3 << mac_type_bit[i]; - break; - - default: - break; - } - } - sw_w32(v, RTL930X_SMI_MAC_TYPE_CTRL); - - // Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones) - sw_w32(private_poll_mask, RTL930X_SMI_PRVTE_POLLING_CTRL); - - /* The following magic values are found in the port configuration, they seem to - * define different ways of polling a PHY. The below is for the Aquantia PHYs of - * the XGS1250 and the RTL8226 of the XGS1210 */ - if (uses_usxgmii) { - sw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG); - sw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG); - sw_w32(0x01E7E820, RTL930X_SMI_10GPHY_POLLING_REG10_CFG); - } - if (uses_hisgmii) { - sw_w32(0x011FA400, RTL930X_SMI_10GPHY_POLLING_REG0_CFG); - sw_w32(0x013FA412, RTL930X_SMI_10GPHY_POLLING_REG9_CFG); - sw_w32(0x017FA414, RTL930X_SMI_10GPHY_POLLING_REG10_CFG); - } - - pr_debug("%s: RTL930X_SMI_GLB_CTRL %08x\n", __func__, - sw_r32(RTL930X_SMI_GLB_CTRL)); - pr_debug("%s: RTL930X_SMI_PORT0_15_POLLING_SEL %08x\n", __func__, - sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL)); - pr_debug("%s: RTL930X_SMI_PORT16_27_POLLING_SEL %08x\n", __func__, - sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL)); - pr_debug("%s: RTL930X_SMI_MAC_TYPE_CTRL %08x\n", __func__, - sw_r32(RTL930X_SMI_MAC_TYPE_CTRL)); - pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG0_CFG %08x\n", __func__, - sw_r32(RTL930X_SMI_10GPHY_POLLING_REG0_CFG)); - pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG9_CFG %08x\n", __func__, - sw_r32(RTL930X_SMI_10GPHY_POLLING_REG9_CFG)); - pr_debug("%s: RTL930X_SMI_10GPHY_POLLING_REG10_CFG %08x\n", __func__, - sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG)); - pr_debug("%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\n", __func__, - sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL)); - return 0; -} - -static int rtl931x_mdio_reset(struct mii_bus *bus) -{ - int i; - int pos; - struct rtl838x_eth_priv *priv = bus->priv; - u32 c45_mask = 0; - u32 poll_sel[4]; - u32 poll_ctrl = 0; - bool mdc_on[4]; - - pr_info("%s called\n", __func__); - // Disable port polling for configuration purposes - sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL); - sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4); - msleep(100); - - mdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false; - // Mapping of port to phy-addresses on an SMI bus - poll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0; - for (i = 0; i < 56; i++) { - pos = (i % 6) * 5; - sw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4); - pos = (i * 2) % 32; - poll_sel[i / 16] |= priv->smi_bus[i] << pos; - poll_ctrl |= BIT(20 + priv->smi_bus[i]); - mdc_on[priv->smi_bus[i]] = true; - } - - // Configure which SMI bus is behind which port number - for (i = 0; i < 4; i++) { - pr_info("poll sel %d, %08x\n", i, poll_sel[i]); - sw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4)); - } - - // Configure which SMI busses - pr_info("%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2)); - pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0)); - for (i = 0; i < 4; i++) { - // bus is polled in c45 - if (priv->smi_bus_isc45[i]) - c45_mask |= 0x2 << (i * 2); // Std. C45, non-standard is 0x3 - // Enable bus access via MDC - if (mdc_on[i]) - sw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2); - } - - pr_info("%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\n", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2)); - pr_info("c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0)); - - /* We have a 10G PHY enable polling - sw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2); - sw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3); - sw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4); -*/ - sw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1); - - return 0; -} - -static int rtl931x_chip_init(struct rtl838x_eth_priv *priv) -{ - pr_info("In %s\n", __func__); - - // Initialize Encapsulation memory and wait until finished - sw_w32(0x1, RTL931X_MEM_ENCAP_INIT); - do { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1); - pr_info("%s: init ENCAP done\n", __func__); - - // Initialize Managemen Information Base memory and wait until finished - sw_w32(0x1, RTL931X_MEM_MIB_INIT); - do { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1); - pr_info("%s: init MIB done\n", __func__); - - // Initialize ACL (PIE) memory and wait until finished - sw_w32(0x1, RTL931X_MEM_ACL_INIT); - do { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1); - pr_info("%s: init ACL done\n", __func__); - - // Initialize ALE memory and wait until finished - sw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0); - do { } while (sw_r32(RTL931X_MEM_ALE_INIT_0)); - sw_w32(0x7F, RTL931X_MEM_ALE_INIT_1); - sw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2); - do { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff); - pr_info("%s: init ALE done\n", __func__); - - // Enable ESD auto recovery - sw_w32(0x1, RTL931X_MDX_CTRL_RSVD); - - // Init SPI, is this for thermal control or what? - sw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0); - - return 0; -} - -static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv) -{ - struct device_node *mii_np, *dn; - u32 pn; - int ret; - - pr_debug("%s called\n", __func__); - mii_np = of_get_child_by_name(priv->pdev->dev.of_node, "mdio-bus"); - - if (!mii_np) { - dev_err(&priv->pdev->dev, "no %s child node found", "mdio-bus"); - return -ENODEV; - } - - if (!of_device_is_available(mii_np)) { - ret = -ENODEV; - goto err_put_node; - } - - priv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev); - if (!priv->mii_bus) { - ret = -ENOMEM; - goto err_put_node; - } - - switch(priv->family_id) { - case RTL8380_FAMILY_ID: - priv->mii_bus->name = "rtl838x-eth-mdio"; - priv->mii_bus->read = rtl838x_mdio_read; - priv->mii_bus->read_paged = rtl838x_mdio_read_paged; - priv->mii_bus->write = rtl838x_mdio_write; - priv->mii_bus->write_paged = rtl838x_mdio_write_paged; - priv->mii_bus->reset = rtl838x_mdio_reset; - break; - case RTL8390_FAMILY_ID: - priv->mii_bus->name = "rtl839x-eth-mdio"; - priv->mii_bus->read = rtl839x_mdio_read; - priv->mii_bus->read_paged = rtl839x_mdio_read_paged; - priv->mii_bus->write = rtl839x_mdio_write; - priv->mii_bus->write_paged = rtl839x_mdio_write_paged; - priv->mii_bus->reset = rtl839x_mdio_reset; - break; - case RTL9300_FAMILY_ID: - priv->mii_bus->name = "rtl930x-eth-mdio"; - priv->mii_bus->read = rtl930x_mdio_read; - priv->mii_bus->read_paged = rtl930x_mdio_read_paged; - priv->mii_bus->write = rtl930x_mdio_write; - priv->mii_bus->write_paged = rtl930x_mdio_write_paged; - priv->mii_bus->reset = rtl930x_mdio_reset; - priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; - break; - case RTL9310_FAMILY_ID: - priv->mii_bus->name = "rtl931x-eth-mdio"; - priv->mii_bus->read = rtl931x_mdio_read; - priv->mii_bus->read_paged = rtl931x_mdio_read_paged; - priv->mii_bus->write = rtl931x_mdio_write; - priv->mii_bus->write_paged = rtl931x_mdio_write_paged; - priv->mii_bus->reset = rtl931x_mdio_reset; - priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; - break; - } - priv->mii_bus->access_capabilities = MDIOBUS_ACCESS_C22_MMD; - priv->mii_bus->priv = priv; - priv->mii_bus->parent = &priv->pdev->dev; - - for_each_node_by_name(dn, "ethernet-phy") { - u32 smi_addr[2]; - - if (of_property_read_u32(dn, "reg", &pn)) - continue; - - if (of_property_read_u32_array(dn, "rtl9300,smi-address", &smi_addr[0], 2)) { - smi_addr[0] = 0; - smi_addr[1] = pn; - } - - if (of_property_read_u32(dn, "sds", &priv->sds_id[pn])) - priv->sds_id[pn] = -1; - else { - pr_info("set sds port %d to %d\n", pn, priv->sds_id[pn]); - } - - if (pn < MAX_PORTS) { - priv->smi_bus[pn] = smi_addr[0]; - priv->smi_addr[pn] = smi_addr[1]; - } else { - pr_err("%s: illegal port number %d\n", __func__, pn); - } - - if (of_device_is_compatible(dn, "ethernet-phy-ieee802.3-c45")) - priv->smi_bus_isc45[smi_addr[0]] = true; - - if (of_property_read_bool(dn, "phy-is-integrated")) { - priv->phy_is_internal[pn] = true; - } - } - - dn = of_find_compatible_node(NULL, NULL, "realtek,rtl83xx-switch"); - if (!dn) { - dev_err(&priv->pdev->dev, "No RTL switch node in DTS\n"); - return -ENODEV; - } - - for_each_node_by_name(dn, "port") { - if (of_property_read_u32(dn, "reg", &pn)) - continue; - pr_debug("%s Looking at port %d\n", __func__, pn); - if (pn > priv->cpu_port) - continue; - if (of_get_phy_mode(dn, &priv->interfaces[pn])) - priv->interfaces[pn] = PHY_INTERFACE_MODE_NA; - pr_debug("%s phy mode of port %d is %s\n", __func__, pn, phy_modes(priv->interfaces[pn])); - } - - snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); - ret = of_mdiobus_register(priv->mii_bus, mii_np); - -err_put_node: - of_node_put(mii_np); - return ret; -} - -static int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv) -{ - pr_debug("%s called\n", __func__); - if (!priv->mii_bus) - return 0; - - mdiobus_unregister(priv->mii_bus); - mdiobus_free(priv->mii_bus); - - return 0; -} - -static netdev_features_t rtl838x_fix_features(struct net_device *dev, - netdev_features_t features) -{ - return features; -} - -static int rtl83xx_set_features(struct net_device *dev, netdev_features_t features) -{ - struct rtl838x_eth_priv *priv = netdev_priv(dev); - - if ((features ^ dev->features) & NETIF_F_RXCSUM) { - if (!(features & NETIF_F_RXCSUM)) - sw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port)); - else - sw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port)); - } - - return 0; -} - -static int rtl93xx_set_features(struct net_device *dev, netdev_features_t features) -{ - struct rtl838x_eth_priv *priv = netdev_priv(dev); - - if ((features ^ dev->features) & NETIF_F_RXCSUM) { - if (!(features & NETIF_F_RXCSUM)) - sw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port)); - else - sw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port)); - } - - return 0; -} - -static const struct net_device_ops rtl838x_eth_netdev_ops = { - .ndo_open = rtl838x_eth_open, - .ndo_stop = rtl838x_eth_stop, - .ndo_start_xmit = rtl838x_eth_tx, - .ndo_select_queue = rtl83xx_pick_tx_queue, - .ndo_set_mac_address = rtl838x_set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_set_rx_mode = rtl838x_eth_set_multicast_list, - .ndo_tx_timeout = rtl838x_eth_tx_timeout, - .ndo_set_features = rtl83xx_set_features, - .ndo_fix_features = rtl838x_fix_features, - .ndo_setup_tc = rtl83xx_setup_tc, -}; - -static const struct net_device_ops rtl839x_eth_netdev_ops = { - .ndo_open = rtl838x_eth_open, - .ndo_stop = rtl838x_eth_stop, - .ndo_start_xmit = rtl838x_eth_tx, - .ndo_select_queue = rtl83xx_pick_tx_queue, - .ndo_set_mac_address = rtl838x_set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_set_rx_mode = rtl839x_eth_set_multicast_list, - .ndo_tx_timeout = rtl838x_eth_tx_timeout, - .ndo_set_features = rtl83xx_set_features, - .ndo_fix_features = rtl838x_fix_features, - .ndo_setup_tc = rtl83xx_setup_tc, -}; - -static const struct net_device_ops rtl930x_eth_netdev_ops = { - .ndo_open = rtl838x_eth_open, - .ndo_stop = rtl838x_eth_stop, - .ndo_start_xmit = rtl838x_eth_tx, - .ndo_select_queue = rtl93xx_pick_tx_queue, - .ndo_set_mac_address = rtl838x_set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_set_rx_mode = rtl930x_eth_set_multicast_list, - .ndo_tx_timeout = rtl838x_eth_tx_timeout, - .ndo_set_features = rtl93xx_set_features, - .ndo_fix_features = rtl838x_fix_features, - .ndo_setup_tc = rtl83xx_setup_tc, -}; - -static const struct net_device_ops rtl931x_eth_netdev_ops = { - .ndo_open = rtl838x_eth_open, - .ndo_stop = rtl838x_eth_stop, - .ndo_start_xmit = rtl838x_eth_tx, - .ndo_select_queue = rtl93xx_pick_tx_queue, - .ndo_set_mac_address = rtl838x_set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_set_rx_mode = rtl931x_eth_set_multicast_list, - .ndo_tx_timeout = rtl838x_eth_tx_timeout, - .ndo_set_features = rtl93xx_set_features, - .ndo_fix_features = rtl838x_fix_features, -}; - -static const struct phylink_mac_ops rtl838x_phylink_ops = { - .validate = rtl838x_validate, - .mac_pcs_get_state = rtl838x_mac_pcs_get_state, - .mac_an_restart = rtl838x_mac_an_restart, - .mac_config = rtl838x_mac_config, - .mac_link_down = rtl838x_mac_link_down, - .mac_link_up = rtl838x_mac_link_up, -}; - -static const struct ethtool_ops rtl838x_ethtool_ops = { - .get_link_ksettings = rtl838x_get_link_ksettings, - .set_link_ksettings = rtl838x_set_link_ksettings, -}; - -static int __init rtl838x_eth_probe(struct platform_device *pdev) -{ - struct net_device *dev; - struct device_node *dn = pdev->dev.of_node; - struct rtl838x_eth_priv *priv; - struct resource *res, *mem; - phy_interface_t phy_mode; - struct phylink *phylink; - int err = 0, i, rxrings, rxringlen; - struct ring_b *ring; - - pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n", - (u32)pdev, (u32)(&(pdev->dev))); - - if (!dn) { - dev_err(&pdev->dev, "No DT found\n"); - return -EINVAL; - } - - rxrings = (soc_info.family == RTL8380_FAMILY_ID - || soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32; - rxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings; - rxringlen = MAX_ENTRIES / rxrings; - rxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen; - - dev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings); - if (!dev) { - err = -ENOMEM; - goto err_free; - } - SET_NETDEV_DEV(dev, &pdev->dev); - priv = netdev_priv(dev); - - /* obtain buffer memory space */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res) { - mem = devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), res->name); - if (!mem) { - dev_err(&pdev->dev, "cannot request memory space\n"); - err = -ENXIO; - goto err_free; - } - - dev->mem_start = mem->start; - dev->mem_end = mem->end; - } else { - dev_err(&pdev->dev, "cannot request IO resource\n"); - err = -ENXIO; - goto err_free; - } - - /* Allocate buffer memory */ - priv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER - + sizeof(struct ring_b) + sizeof(struct notify_b), - (void *)&dev->mem_start, GFP_KERNEL); - if (!priv->membase) { - dev_err(&pdev->dev, "cannot allocate DMA buffer\n"); - err = -ENOMEM; - goto err_free; - } - - // Allocate ring-buffer space at the end of the allocated memory - ring = priv->membase; - ring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b); - - spin_lock_init(&priv->lock); - - dev->ethtool_ops = &rtl838x_ethtool_ops; - dev->min_mtu = ETH_ZLEN; - dev->max_mtu = 1536; - dev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM; - dev->hw_features = NETIF_F_RXCSUM; - - priv->id = soc_info.id; - priv->family_id = soc_info.family; - if (priv->id) { - pr_info("Found SoC ID: %4x: %s, family %x\n", - priv->id, soc_info.name, priv->family_id); - } else { - pr_err("Unknown chip id (%04x)\n", priv->id); - return -ENODEV; - } - - switch (priv->family_id) { - case RTL8380_FAMILY_ID: - priv->cpu_port = RTL838X_CPU_PORT; - priv->r = &rtl838x_reg; - dev->netdev_ops = &rtl838x_eth_netdev_ops; - break; - case RTL8390_FAMILY_ID: - priv->cpu_port = RTL839X_CPU_PORT; - priv->r = &rtl839x_reg; - dev->netdev_ops = &rtl839x_eth_netdev_ops; - break; - case RTL9300_FAMILY_ID: - priv->cpu_port = RTL930X_CPU_PORT; - priv->r = &rtl930x_reg; - dev->netdev_ops = &rtl930x_eth_netdev_ops; - break; - case RTL9310_FAMILY_ID: - priv->cpu_port = RTL931X_CPU_PORT; - priv->r = &rtl931x_reg; - dev->netdev_ops = &rtl931x_eth_netdev_ops; - rtl931x_chip_init(priv); - break; - default: - pr_err("Unknown SoC family\n"); - return -ENODEV; - } - priv->rxringlen = rxringlen; - priv->rxrings = rxrings; - - /* Obtain device IRQ number */ - dev->irq = platform_get_irq(pdev, 0); - if (dev->irq < 0) { - dev_err(&pdev->dev, "cannot obtain network-device IRQ\n"); - goto err_free; - } - - err = devm_request_irq(&pdev->dev, dev->irq, priv->r->net_irq, - IRQF_SHARED, dev->name, dev); - if (err) { - dev_err(&pdev->dev, "%s: could not acquire interrupt: %d\n", - __func__, err); - goto err_free; - } - - rtl8380_init_mac(priv); - - /* try to get mac address in the following order: - * 1) from device tree data - * 2) from internal registers set by bootloader - */ - of_get_mac_address(pdev->dev.of_node, dev->dev_addr); - if (is_valid_ether_addr(dev->dev_addr)) { - rtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr); - } else { - dev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff; - dev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff; - dev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff; - dev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff; - dev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff; - dev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff; - } - /* if the address is invalid, use a random value */ - if (!is_valid_ether_addr(dev->dev_addr)) { - struct sockaddr sa = { AF_UNSPEC }; - - netdev_warn(dev, "Invalid MAC address, using random\n"); - eth_hw_addr_random(dev); - memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN); - if (rtl838x_set_mac_address(dev, &sa)) - netdev_warn(dev, "Failed to set MAC address.\n"); - } - pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac), - sw_r32(priv->r->mac + 4)); - strcpy(dev->name, "eth%d"); - priv->pdev = pdev; - priv->netdev = dev; - - err = rtl838x_mdio_init(priv); - if (err) - goto err_free; - - err = register_netdev(dev); - if (err) - goto err_free; - - for (i = 0; i < priv->rxrings; i++) { - priv->rx_qs[i].id = i; - priv->rx_qs[i].priv = priv; - netif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64); - } - - platform_set_drvdata(pdev, dev); - - phy_mode = PHY_INTERFACE_MODE_NA; - err = of_get_phy_mode(dn, &phy_mode); - if (err < 0) { - dev_err(&pdev->dev, "incorrect phy-mode\n"); - err = -EINVAL; - goto err_free; - } - priv->phylink_config.dev = &dev->dev; - priv->phylink_config.type = PHYLINK_NETDEV; - - phylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode, - phy_mode, &rtl838x_phylink_ops); - - if (IS_ERR(phylink)) { - err = PTR_ERR(phylink); - goto err_free; - } - priv->phylink = phylink; - - return 0; - -err_free: - pr_err("Error setting up netdev, freeing it again.\n"); - free_netdev(dev); - return err; -} - -static int rtl838x_eth_remove(struct platform_device *pdev) -{ - struct net_device *dev = platform_get_drvdata(pdev); - struct rtl838x_eth_priv *priv = netdev_priv(dev); - int i; - - if (dev) { - pr_info("Removing platform driver for rtl838x-eth\n"); - rtl838x_mdio_remove(priv); - rtl838x_hw_stop(priv); - - netif_tx_stop_all_queues(dev); - - for (i = 0; i < priv->rxrings; i++) - netif_napi_del(&priv->rx_qs[i].napi); - - unregister_netdev(dev); - free_netdev(dev); - } - return 0; -} - -static const struct of_device_id rtl838x_eth_of_ids[] = { - { .compatible = "realtek,rtl838x-eth"}, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids); - -static struct platform_driver rtl838x_eth_driver = { - .probe = rtl838x_eth_probe, - .remove = rtl838x_eth_remove, - .driver = { - .name = "rtl838x-eth", - .pm = NULL, - .of_match_table = rtl838x_eth_of_ids, - }, -}; - -module_platform_driver(rtl838x_eth_driver); - -MODULE_AUTHOR("B. Koblitz"); -MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h deleted file mode 100644 index d00d11d0c8..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h +++ /dev/null @@ -1,457 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _RTL838X_ETH_H -#define _RTL838X_ETH_H - -/* - * Register definition - */ - -/* Per port MAC control */ -#define RTL838X_MAC_PORT_CTRL (0xd560) -#define RTL839X_MAC_PORT_CTRL (0x8004) -#define RTL930X_MAC_L2_PORT_CTRL (0x3268) -#define RTL930X_MAC_PORT_CTRL (0x3260) -#define RTL931X_MAC_L2_PORT_CTRL (0x6000) -#define RTL931X_MAC_PORT_CTRL (0x6004) - -/* DMA interrupt control and status registers */ -#define RTL838X_DMA_IF_CTRL (0x9f58) -#define RTL838X_DMA_IF_INTR_STS (0x9f54) -#define RTL838X_DMA_IF_INTR_MSK (0x9f50) - -#define RTL839X_DMA_IF_CTRL (0x786c) -#define RTL839X_DMA_IF_INTR_STS (0x7868) -#define RTL839X_DMA_IF_INTR_MSK (0x7864) - -#define RTL930X_DMA_IF_CTRL (0xe028) -#define RTL930X_DMA_IF_INTR_RX_RUNOUT_STS (0xe01C) -#define RTL930X_DMA_IF_INTR_RX_DONE_STS (0xe020) -#define RTL930X_DMA_IF_INTR_TX_DONE_STS (0xe024) -#define RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK (0xe010) -#define RTL930X_DMA_IF_INTR_RX_DONE_MSK (0xe014) -#define RTL930X_DMA_IF_INTR_TX_DONE_MSK (0xe018) -#define RTL930X_L2_NTFY_IF_INTR_MSK (0xe04C) -#define RTL930X_L2_NTFY_IF_INTR_STS (0xe050) - -/* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */ -#define RTL931X_DMA_IF_CTRL (0x0928) -#define RTL931X_DMA_IF_INTR_RX_RUNOUT_STS (0x091c) -#define RTL931X_DMA_IF_INTR_RX_DONE_STS (0x0920) -#define RTL931X_DMA_IF_INTR_TX_DONE_STS (0x0924) -#define RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK (0x0910) -#define RTL931X_DMA_IF_INTR_RX_DONE_MSK (0x0914) -#define RTL931X_DMA_IF_INTR_TX_DONE_MSK (0x0918) -#define RTL931X_L2_NTFY_IF_INTR_MSK (0x09E4) -#define RTL931X_L2_NTFY_IF_INTR_STS (0x09E8) - -#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) -#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) -#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) -#define RTL931X_MAC_FORCE_MODE_CTRL (0x0ddc) - -/* MAC address settings */ -#define RTL838X_MAC (0xa9ec) -#define RTL839X_MAC (0x02b4) -#define RTL838X_MAC_ALE (0x6b04) -#define RTL838X_MAC2 (0xa320) -#define RTL930X_MAC_L2_ADDR_CTRL (0xC714) -#define RTL931X_MAC_L2_ADDR_CTRL (0x135c) - -/* Ringbuffer setup */ -#define RTL838X_DMA_RX_BASE (0x9f00) -#define RTL839X_DMA_RX_BASE (0x780c) -#define RTL930X_DMA_RX_BASE (0xdf00) -#define RTL931X_DMA_RX_BASE (0x0800) - -#define RTL838X_DMA_TX_BASE (0x9f40) -#define RTL839X_DMA_TX_BASE (0x784c) -#define RTL930X_DMA_TX_BASE (0xe000) -#define RTL931X_DMA_TX_BASE (0x0900) - -#define RTL838X_DMA_IF_RX_RING_SIZE (0xB7E4) -#define RTL839X_DMA_IF_RX_RING_SIZE (0x6038) -#define RTL930X_DMA_IF_RX_RING_SIZE (0x7C60) -#define RTL931X_DMA_IF_RX_RING_SIZE (0x2080) - -#define RTL838X_DMA_IF_RX_RING_CNTR (0xB7E8) -#define RTL839X_DMA_IF_RX_RING_CNTR (0x603c) -#define RTL930X_DMA_IF_RX_RING_CNTR (0x7C8C) -#define RTL931X_DMA_IF_RX_RING_CNTR (0x20AC) - -#define RTL838X_DMA_IF_RX_CUR (0x9F20) -#define RTL839X_DMA_IF_RX_CUR (0x782c) -#define RTL930X_DMA_IF_RX_CUR (0xdf80) -#define RTL931X_DMA_IF_RX_CUR (0x0880) - -#define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0x9F48) -#define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0xE008) - -#define RTL838X_DMY_REG31 (0x3b28) -#define RTL838X_SDS_MODE_SEL (0x0028) -#define RTL838X_SDS_CFG_REG (0x0034) -#define RTL838X_INT_MODE_CTRL (0x005c) -#define RTL838X_CHIP_INFO (0x00d8) -#define RTL838X_SDS4_REG28 (0xef80) -#define RTL838X_SDS4_DUMMY0 (0xef8c) -#define RTL838X_SDS5_EXT_REG6 (0xf18c) - -/* L2 features */ -#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) -#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) -#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) -#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) - -/* MAC-side link state handling */ -#define RTL838X_MAC_LINK_STS (0xa188) -#define RTL839X_MAC_LINK_STS (0x0390) -#define RTL930X_MAC_LINK_STS (0xCB10) -#define RTL931X_MAC_LINK_STS (0x0ec0) - -#define RTL838X_MAC_LINK_SPD_STS (0xa190) -#define RTL839X_MAC_LINK_SPD_STS (0x03a0) -#define RTL930X_MAC_LINK_SPD_STS (0xCB18) -#define RTL931X_MAC_LINK_SPD_STS (0x0ed0) - -#define RTL838X_MAC_LINK_DUP_STS (0xa19c) -#define RTL839X_MAC_LINK_DUP_STS (0x03b0) -#define RTL930X_MAC_LINK_DUP_STS (0xCB28) -#define RTL931X_MAC_LINK_DUP_STS (0x0ef0) - -// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ??? - -#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) -#define RTL839X_MAC_TX_PAUSE_STS (0x03b8) -#define RTL930X_MAC_TX_PAUSE_STS (0xCB2C) -#define RTL931X_MAC_TX_PAUSE_STS (0x0ef8) - -#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) -#define RTL839X_MAC_RX_PAUSE_STS (0xCB30) -#define RTL930X_MAC_RX_PAUSE_STS (0xC2F8) -#define RTL931X_MAC_RX_PAUSE_STS (0x0f00) - -#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) -#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) - -#define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064) -#define RTL931X_L2_UNKN_UC_FLD_PMSK (0xC8F4) - -#define RTL839X_MAC_GLB_CTRL (0x02a8) -#define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60f8) - -#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) -#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) -#define RTL930X_L2_TBL_FLUSH_CTRL (0x9404) -#define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C) - -#define RTL930X_L2_PORT_SABLK_CTRL (0x905c) -#define RTL930X_L2_PORT_DABLK_CTRL (0x9060) - -/* MAC link state bits */ -#define FORCE_EN (1 << 0) -#define FORCE_LINK_EN (1 << 1) -#define NWAY_EN (1 << 2) -#define DUPLX_MODE (1 << 3) -#define TX_PAUSE_EN (1 << 6) -#define RX_PAUSE_EN (1 << 7) - -/* L2 Notification DMA interface */ -#define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL (0x785C) -#define RTL839X_L2_NOTIFICATION_CTRL (0x7808) -#define RTL931X_L2_NTFY_RING_BASE_ADDR (0x09DC) -#define RTL931X_L2_NTFY_RING_CUR_ADDR (0x09E0) -#define RTL839X_L2_NOTIFICATION_CTRL (0x7808) -#define RTL931X_L2_NTFY_CTRL (0xCDC8) -#define RTL838X_L2_CTRL_0 (0x3200) -#define RTL839X_L2_CTRL_0 (0x3800) -#define RTL930X_L2_CTRL (0x8FD8) -#define RTL931X_L2_CTRL (0xC800) - -/* TRAPPING to CPU-PORT */ -#define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984) -#define RTL838X_RMA_CTRL_0 (0x4300) -#define RTL838X_RMA_CTRL_1 (0x4304) -#define RTL839X_RMA_CTRL_0 (0x1200) - -#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058) -#define RTL839X_RMA_CTRL_1 (0x1204) -#define RTL839X_RMA_CTRL_2 (0x1208) -#define RTL839X_RMA_CTRL_3 (0x120C) - -#define RTL930X_VLAN_APP_PKT_CTRL (0xA23C) -#define RTL930X_RMA_CTRL_0 (0x9E60) -#define RTL930X_RMA_CTRL_1 (0x9E64) -#define RTL930X_RMA_CTRL_2 (0x9E68) - -#define RTL931X_VLAN_APP_PKT_CTRL (0x96b0) -#define RTL931X_RMA_CTRL_0 (0x8800) -#define RTL931X_RMA_CTRL_1 (0x8804) -#define RTL931X_RMA_CTRL_2 (0x8808) - -/* Advanced SMI control for clause 45 PHYs */ -#define RTL930X_SMI_MAC_TYPE_CTRL (0xCA04) -#define RTL930X_SMI_PORT24_27_ADDR_CTRL (0xCB90) -#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08) -#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C) - -#define RTL930X_SMI_10GPHY_POLLING_REG0_CFG (0xCBB4) -#define RTL930X_SMI_10GPHY_POLLING_REG9_CFG (0xCBB8) -#define RTL930X_SMI_10GPHY_POLLING_REG10_CFG (0xCBBC) -#define RTL930X_SMI_PRVTE_POLLING_CTRL (0xCA10) - -/* Registers of the internal Serdes of the 8390 */ -#define RTL839X_SDS12_13_XSG0 (0xB800) - -/* Chip configuration registers of the RTL9310 */ -#define RTL931X_MEM_ENCAP_INIT (0x4854) -#define RTL931X_MEM_MIB_INIT (0x7E18) -#define RTL931X_MEM_ACL_INIT (0x40BC) -#define RTL931X_MEM_ALE_INIT_0 (0x83F0) -#define RTL931X_MEM_ALE_INIT_1 (0x83F4) -#define RTL931X_MEM_ALE_INIT_2 (0x82E4) -#define RTL931X_MDX_CTRL_RSVD (0x0fcc) -#define RTL931X_PS_SOC_CTRL (0x13f8) -#define RTL931X_SMI_10GPHY_POLLING_SEL2 (0xCF8) -#define RTL931X_SMI_10GPHY_POLLING_SEL3 (0xCFC) -#define RTL931X_SMI_10GPHY_POLLING_SEL4 (0xD00) - -/* Registers of the internal Serdes of the 8380 */ -#define RTL838X_SDS4_FIB_REG0 (0xF800) - -inline int rtl838x_mac_port_ctrl(int p) -{ - return RTL838X_MAC_PORT_CTRL + (p << 7); -} - -inline int rtl839x_mac_port_ctrl(int p) -{ - return RTL839X_MAC_PORT_CTRL + (p << 7); -} - -/* On the RTL931XX, the functionality of the MAC port control register is split up - * into RTL931X_MAC_L2_PORT_CTRL and RTL931X_MAC_PORT_CTRL the functionality used - * by the Ethernet driver is in the same bits now in RTL931X_MAC_L2_PORT_CTRL - */ - -inline int rtl930x_mac_port_ctrl(int p) -{ - return RTL930X_MAC_L2_PORT_CTRL + (p << 6); -} - -inline int rtl931x_mac_port_ctrl(int p) -{ - return RTL931X_MAC_L2_PORT_CTRL + (p << 7); -} - -inline int rtl838x_dma_if_rx_ring_size(int i) -{ - return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); -} - -inline int rtl839x_dma_if_rx_ring_size(int i) -{ - return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2); -} - -inline int rtl930x_dma_if_rx_ring_size(int i) -{ - return RTL930X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2); -} - -inline int rtl931x_dma_if_rx_ring_size(int i) -{ - return RTL931X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2); -} - -inline int rtl838x_dma_if_rx_ring_cntr(int i) -{ - return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2); -} - -inline int rtl839x_dma_if_rx_ring_cntr(int i) -{ - return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2); -} - -inline int rtl930x_dma_if_rx_ring_cntr(int i) -{ - return RTL930X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2); -} - -inline int rtl931x_dma_if_rx_ring_cntr(int i) -{ - return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2); -} - -inline u32 rtl838x_get_mac_link_sts(int port) -{ - return (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port)); -} - -inline u32 rtl839x_get_mac_link_sts(int p) -{ - return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl930x_get_mac_link_sts(int port) -{ - u32 link = sw_r32(RTL930X_MAC_LINK_STS); - - link = sw_r32(RTL930X_MAC_LINK_STS); - pr_info("%s link state is %08x\n", __func__, link); - return link & BIT(port); -} - -inline u32 rtl931x_get_mac_link_sts(int p) -{ - return (sw_r32(RTL931X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl838x_get_mac_link_dup_sts(int port) -{ - return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port)); -} - -inline u32 rtl839x_get_mac_link_dup_sts(int p) -{ - return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl930x_get_mac_link_dup_sts(int port) -{ - return (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port)); -} - -inline u32 rtl931x_get_mac_link_dup_sts(int p) -{ - return (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl838x_get_mac_link_spd_sts(int port) -{ - int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2); - u32 speed = sw_r32(r); - - speed >>= (port % 16) << 1; - return (speed & 0x3); -} - -inline u32 rtl839x_get_mac_link_spd_sts(int port) -{ - int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2); - u32 speed = sw_r32(r); - - speed >>= (port % 16) << 1; - return (speed & 0x3); -} - - -inline u32 rtl930x_get_mac_link_spd_sts(int port) -{ - int r = RTL930X_MAC_LINK_SPD_STS + ((port >> 3) << 2); - u32 speed = sw_r32(r); - - speed >>= (port % 8) << 2; - return (speed & 0xf); -} - -inline u32 rtl931x_get_mac_link_spd_sts(int port) -{ - int r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2); - u32 speed = sw_r32(r); - - speed >>= (port % 8) << 2; - return (speed & 0xf); -} - -inline u32 rtl838x_get_mac_rx_pause_sts(int port) -{ - return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port)); -} - -inline u32 rtl839x_get_mac_rx_pause_sts(int p) -{ - return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl930x_get_mac_rx_pause_sts(int port) -{ - return (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port)); -} - -inline u32 rtl931x_get_mac_rx_pause_sts(int p) -{ - return (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl838x_get_mac_tx_pause_sts(int port) -{ - return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port)); -} - -inline u32 rtl839x_get_mac_tx_pause_sts(int p) -{ - return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -inline u32 rtl930x_get_mac_tx_pause_sts(int port) -{ - return (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port)); -} - -inline u32 rtl931x_get_mac_tx_pause_sts(int p) -{ - return (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32)); -} - -struct p_hdr; -struct dsa_tag; - -struct rtl838x_eth_reg { - irqreturn_t (*net_irq)(int irq, void *dev_id); - int (*mac_port_ctrl)(int port); - int dma_if_intr_sts; - int dma_if_intr_msk; - int dma_if_intr_rx_runout_sts; - int dma_if_intr_rx_done_sts; - int dma_if_intr_tx_done_sts; - int dma_if_intr_rx_runout_msk; - int dma_if_intr_rx_done_msk; - int dma_if_intr_tx_done_msk; - int l2_ntfy_if_intr_sts; - int l2_ntfy_if_intr_msk; - int dma_if_ctrl; - int mac_force_mode_ctrl; - int dma_rx_base; - int dma_tx_base; - int (*dma_if_rx_ring_size)(int ring); - int (*dma_if_rx_ring_cntr)(int ring); - int dma_if_rx_cur; - int rst_glb_ctrl; - u32 (*get_mac_link_sts)(int port); - u32 (*get_mac_link_dup_sts)(int port); - u32 (*get_mac_link_spd_sts)(int port); - u32 (*get_mac_rx_pause_sts)(int port); - u32 (*get_mac_tx_pause_sts)(int port); - int mac; - int l2_tbl_flush_ctrl; - void (*update_cntr)(int r, int work_done); - void (*create_tx_header)(struct p_hdr *h, unsigned int dest_port, int prio); - bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag); -}; - -int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val); -int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val); -int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val); -int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val); -int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val); -int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val); -int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data); - -#endif /* _RTL838X_ETH_H */ diff --git a/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c b/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c deleted file mode 100644 index 491ceb48b6..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c +++ /dev/null @@ -1,4018 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Realtek RTL838X Ethernet MDIO interface driver - * - * Copyright (C) 2020 B. Koblitz - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "rtl83xx-phy.h" - -extern struct rtl83xx_soc_info soc_info; -extern struct mutex smi_lock; - -#define PHY_CTRL_REG 0 -#define PHY_POWER_BIT 11 - -#define PHY_PAGE_2 2 -#define PHY_PAGE_4 4 - -/* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */ -#define RTL8XXX_PAGE_SELECT 0x1f - -#define RTL8XXX_PAGE_MAIN 0x0000 -#define RTL821X_PAGE_PORT 0x0266 -#define RTL821X_PAGE_POWER 0x0a40 -#define RTL821X_PAGE_GPHY 0x0a42 -#define RTL821X_PAGE_MAC 0x0a43 -#define RTL821X_PAGE_STATE 0x0b80 -#define RTL821X_PAGE_PATCH 0x0b82 - -/* - * Using the special page 0xfff with the MDIO controller found in - * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing - * the cache and paging engine of the MDIO controller. - */ -#define RTL83XX_PAGE_RAW 0x0fff - -/* internal RTL821X PHY uses register 0x1d to select media page */ -#define RTL821XINT_MEDIA_PAGE_SELECT 0x1d -/* external RTL821X PHY uses register 0x1e to select media page */ -#define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e - -#define RTL821X_MEDIA_PAGE_AUTO 0 -#define RTL821X_MEDIA_PAGE_COPPER 1 -#define RTL821X_MEDIA_PAGE_FIBRE 3 -#define RTL821X_MEDIA_PAGE_INTERNAL 8 - -#define RTL9300_PHY_ID_MASK 0xf0ffffff - -/* - * This lock protects the state of the SoC automatically polling the PHYs over the SMI - * bus to detect e.g. link and media changes. For operations on the PHYs such as - * patching or other configuration changes such as EEE, polling needs to be disabled - * since otherwise these operations may fails or lead to unpredictable results. - */ -DEFINE_MUTEX(poll_lock); - -static const struct firmware rtl838x_8380_fw; -static const struct firmware rtl838x_8214fc_fw; -static const struct firmware rtl838x_8218b_fw; - -static u64 disable_polling(int port) -{ - u64 saved_state; - - mutex_lock(&poll_lock); - - switch (soc_info.family) { - case RTL8380_FAMILY_ID: - saved_state = sw_r32(RTL838X_SMI_POLL_CTRL); - sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL); - break; - case RTL8390_FAMILY_ID: - saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4); - saved_state <<= 32; - saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL); - sw_w32_mask(BIT(port % 32), 0, - RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2)); - break; - case RTL9300_FAMILY_ID: - saved_state = sw_r32(RTL930X_SMI_POLL_CTRL); - sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL); - break; - case RTL9310_FAMILY_ID: - pr_warn("%s not implemented for RTL931X\n", __func__); - break; - } - - mutex_unlock(&poll_lock); - - return saved_state; -} - -static int resume_polling(u64 saved_state) -{ - mutex_lock(&poll_lock); - - switch (soc_info.family) { - case RTL8380_FAMILY_ID: - sw_w32(saved_state, RTL838X_SMI_POLL_CTRL); - break; - case RTL8390_FAMILY_ID: - sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4); - sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL); - break; - case RTL9300_FAMILY_ID: - sw_w32(saved_state, RTL930X_SMI_POLL_CTRL); - break; - case RTL9310_FAMILY_ID: - pr_warn("%s not implemented for RTL931X\n", __func__); - break; - } - - mutex_unlock(&poll_lock); - - return 0; -} - -static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on) -{ - phy_modify(phydev, 0, BIT(11), on?0:BIT(11)); -} - -static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on) -{ - /* fiber ports */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE); - phy_modify(phydev, 0x10, BIT(11), on?0:BIT(11)); - - /* copper ports */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), on?0:BIT(11)); -} - -static void rtl8380_phy_reset(struct phy_device *phydev) -{ - phy_modify(phydev, 0, BIT(15), BIT(15)); -} - -// The access registers for SDS_MODE_SEL and the LSB for each SDS within -u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0, - 0x02A4, 0x02A4, 0x0198, 0x0198 }; -u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6}; - -/* - * Reset the SerDes by powering it off and set a new operations mode - * of the SerDes. 0x1f is off. Other modes are - * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100 - * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII - * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X - * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R - * 0x1b: 10GR1000BX_AUTO 0x1f: OFF - */ -void rtl9300_sds_rst(int sds_num, u32 mode) -{ - pr_info("%s %d\n", __func__, mode); - if (sds_num < 0 || sds_num > 11) { - pr_err("Wrong SerDes number: %d\n", sds_num); - return; - } - - sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num], - rtl9300_sds_regs[sds_num]); - mdelay(10); - - sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num], - rtl9300_sds_regs[sds_num]); - mdelay(10); - - pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__, - sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4)); -} - -void rtl9300_sds_set(int sds_num, u32 mode) -{ - pr_info("%s %d\n", __func__, mode); - if (sds_num < 0 || sds_num > 11) { - pr_err("Wrong SerDes number: %d\n", sds_num); - return; - } - - sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num], - rtl9300_sds_regs[sds_num]); - mdelay(10); - - pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__, - sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4)); -} - -u32 rtl9300_sds_mode_get(int sds_num) -{ - u32 v; - - if (sds_num < 0 || sds_num > 11) { - pr_err("Wrong SerDes number: %d\n", sds_num); - return 0; - } - - v = sw_r32(rtl9300_sds_regs[sds_num]); - v >>= rtl9300_sds_lsb[sds_num]; - - return v & 0x1f; -} - -/* - * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through - * a 2048 bit register that holds the contents of the PHY being simulated by the SoC. - */ -int rtl839x_read_sds_phy(int phy_addr, int phy_reg) -{ - int offset = 0; - int reg; - u32 val; - - if (phy_addr == 49) - offset = 0x100; - - /* - * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3 - * which would otherwise read as 0. - */ - if (soc_info.id == 0x8393) { - if (phy_reg == 2) - return 0x1c; - if (phy_reg == 3) - return 0x8393; - } - - /* - * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the - * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16 - * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in - * one 32 bit register. - */ - reg = (phy_reg << 1) & 0xfc; - val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg); - - if (phy_reg & 1) - val = (val >> 16) & 0xffff; - else - val &= 0xffff; - return val; -} - -/* - * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO - * register which simulates commands to an internal MDIO bus. - */ -int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg) -{ - int i; - u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1; - - sw_w32(cmd, RTL930X_SDS_INDACS_CMD); - - for (i = 0; i < 100; i++) { - if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1)) - break; - mdelay(1); - } - - if (i >= 100) - return -EIO; - - return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff; -} - -int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v) -{ - int i; - u32 cmd; - - sw_w32(v, RTL930X_SDS_INDACS_DATA); - cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3; - - for (i = 0; i < 100; i++) { - if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1)) - break; - mdelay(1); - } - - - if (i >= 100) { - pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__); - return -EIO; - } - - return 0; -} - -int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg) -{ - int i; - u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1; - - pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg); - sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL); - - for (i = 0; i < 100; i++) { - if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1)) - break; - mdelay(1); - } - - if (i >= 100) - return -EIO; - - pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff); - return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff; -} - -int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v) -{ - int i; - u32 cmd; - - cmd = phy_addr << 2 | page << 7 | phy_reg << 13; - sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL); - - sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL); - - cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3; - sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL); - - for (i = 0; i < 100; i++) { - if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1)) - break; - mdelay(1); - } - - if (i >= 100) - return -EIO; - - return 0; -} - -/* - * On the RTL838x SoCs, the internal SerDes is accessed through direct access to - * standard PHY registers, where a 32 bit register holds a 16 bit word as found - * in a standard page 0 of a PHY - */ -int rtl838x_read_sds_phy(int phy_addr, int phy_reg) -{ - int offset = 0; - u32 val; - - if (phy_addr == 26) - offset = 0x100; - val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff; - - return val; -} - -int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v) -{ - int offset = 0; - int reg; - u32 val; - - if (phy_addr == 49) - offset = 0x100; - - reg = (phy_reg << 1) & 0xfc; - val = v; - if (phy_reg & 1) { - val = val << 16; - sw_w32_mask(0xffff0000, val, - RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg); - } else { - sw_w32_mask(0xffff, val, - RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg); - } - - return 0; -} - -/* Read the link and speed status of the 2 internal SGMII/1000Base-X - * ports of the RTL838x SoCs - */ -static int rtl8380_read_status(struct phy_device *phydev) -{ - int err; - - err = genphy_read_status(phydev); - - if (phydev->link) { - phydev->speed = SPEED_1000; - phydev->duplex = DUPLEX_FULL; - } - - return err; -} - -/* Read the link and speed status of the 2 internal SGMII/1000Base-X - * ports of the RTL8393 SoC - */ -static int rtl8393_read_status(struct phy_device *phydev) -{ - int offset = 0; - int err; - int phy_addr = phydev->mdio.addr; - u32 v; - - err = genphy_read_status(phydev); - if (phy_addr == 49) - offset = 0x100; - - if (phydev->link) { - phydev->speed = SPEED_100; - /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal - * PHY registers - */ - v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80); - if (!(v & (1 << 13)) && (v & (1 << 6))) - phydev->speed = SPEED_1000; - phydev->duplex = DUPLEX_FULL; - } - - return err; -} - -static int rtl8226_read_page(struct phy_device *phydev) -{ - return __phy_read(phydev, RTL8XXX_PAGE_SELECT); -} - -static int rtl8226_write_page(struct phy_device *phydev, int page) -{ - return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page); -} - -static int rtl8226_read_status(struct phy_device *phydev) -{ - int ret = 0, i; - u32 val; - -// TODO: ret = genphy_read_status(phydev); -// if (ret < 0) { -// pr_info("%s: genphy_read_status failed\n", __func__); -// return ret; -// } - - // Link status must be read twice - for (i = 0; i < 2; i++) { - val = phy_read_mmd(phydev, MMD_VEND2, 0xA402); - } - phydev->link = val & BIT(2) ? 1 : 0; - if (!phydev->link) - goto out; - - // Read duplex status - val = phy_read_mmd(phydev, MMD_VEND2, 0xA434); - if (val < 0) - goto out; - phydev->duplex = !!(val & BIT(3)); - - // Read speed - val = phy_read_mmd(phydev, MMD_VEND2, 0xA434); - switch (val & 0x0630) { - case 0x0000: - phydev->speed = SPEED_10; - break; - case 0x0010: - phydev->speed = SPEED_100; - break; - case 0x0020: - phydev->speed = SPEED_1000; - break; - case 0x0200: - phydev->speed = SPEED_10000; - break; - case 0x0210: - phydev->speed = SPEED_2500; - break; - case 0x0220: - phydev->speed = SPEED_5000; - break; - default: - break; - } -out: - return ret; -} - -static int rtl8226_advertise_aneg(struct phy_device *phydev) -{ - int ret = 0; - u32 v; - - pr_info("In %s\n", __func__); - - v = phy_read_mmd(phydev, MMD_AN, 16); - if (v < 0) - goto out; - - v |= BIT(5); // HD 10M - v |= BIT(6); // FD 10M - v |= BIT(7); // HD 100M - v |= BIT(8); // FD 100M - - ret = phy_write_mmd(phydev, MMD_AN, 16, v); - - // Allow 1GBit - v = phy_read_mmd(phydev, MMD_VEND2, 0xA412); - if (v < 0) - goto out; - v |= BIT(9); // FD 1000M - - ret = phy_write_mmd(phydev, MMD_VEND2, 0xA412, v); - if (ret < 0) - goto out; - - // Allow 2.5G - v = phy_read_mmd(phydev, MMD_AN, 32); - if (v < 0) - goto out; - - v |= BIT(7); - ret = phy_write_mmd(phydev, MMD_AN, 32, v); - -out: - return ret; -} - -static int rtl8226_config_aneg(struct phy_device *phydev) -{ - int ret = 0; - u32 v; - - pr_debug("In %s\n", __func__); - if (phydev->autoneg == AUTONEG_ENABLE) { - ret = rtl8226_advertise_aneg(phydev); - if (ret) - goto out; - // AutoNegotiationEnable - v = phy_read_mmd(phydev, MMD_AN, 0); - if (v < 0) - goto out; - - v |= BIT(12); // Enable AN - ret = phy_write_mmd(phydev, MMD_AN, 0, v); - if (ret < 0) - goto out; - - // RestartAutoNegotiation - v = phy_read_mmd(phydev, MMD_VEND2, 0xA400); - if (v < 0) - goto out; - v |= BIT(9); - - ret = phy_write_mmd(phydev, MMD_VEND2, 0xA400, v); - } - -// TODO: ret = __genphy_config_aneg(phydev, ret); - -out: - return ret; -} - -static int rtl8226_get_eee(struct phy_device *phydev, - struct ethtool_eee *e) -{ - u32 val; - int addr = phydev->mdio.addr; - - pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled); - - val = phy_read_mmd(phydev, MMD_AN, 60); - if (e->eee_enabled) { - e->eee_enabled = !!(val & BIT(1)); - if (!e->eee_enabled) { - val = phy_read_mmd(phydev, MMD_AN, 62); - e->eee_enabled = !!(val & BIT(0)); - } - } - pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled); - - return 0; -} - -static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e) -{ - int port = phydev->mdio.addr; - u64 poll_state; - bool an_enabled; - u32 val; - - pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled); - - poll_state = disable_polling(port); - - // Remember aneg state - val = phy_read_mmd(phydev, MMD_AN, 0); - an_enabled = !!(val & BIT(12)); - - // Setup 100/1000MBit - val = phy_read_mmd(phydev, MMD_AN, 60); - if (e->eee_enabled) - val |= 0x6; - else - val &= 0x6; - phy_write_mmd(phydev, MMD_AN, 60, val); - - // Setup 2.5GBit - val = phy_read_mmd(phydev, MMD_AN, 62); - if (e->eee_enabled) - val |= 0x1; - else - val &= 0x1; - phy_write_mmd(phydev, MMD_AN, 62, val); - - // RestartAutoNegotiation - val = phy_read_mmd(phydev, MMD_VEND2, 0xA400); - val |= BIT(9); - phy_write_mmd(phydev, MMD_VEND2, 0xA400, val); - - resume_polling(poll_state); - - return 0; -} - -static struct fw_header *rtl838x_request_fw(struct phy_device *phydev, - const struct firmware *fw, - const char *name) -{ - struct device *dev = &phydev->mdio.dev; - int err; - struct fw_header *h; - uint32_t checksum, my_checksum; - - err = request_firmware(&fw, name, dev); - if (err < 0) - goto out; - - if (fw->size < sizeof(struct fw_header)) { - pr_err("Firmware size too small.\n"); - err = -EINVAL; - goto out; - } - - h = (struct fw_header *) fw->data; - pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic); - - if (h->magic != 0x83808380) { - pr_err("Wrong firmware file: MAGIC mismatch.\n"); - goto out; - } - - checksum = h->checksum; - h->checksum = 0; - my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size); - if (checksum != my_checksum) { - pr_err("Firmware checksum mismatch.\n"); - err = -EINVAL; - goto out; - } - h->checksum = checksum; - - return h; -out: - dev_err(dev, "Unable to load firmware %s (%d)\n", name, err); - return NULL; -} - -static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable) -{ - int mac = phydev->mdio.addr; - - /* select main page 0 */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); - /* write to 0x8 to register 0x1d on main page 0 */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL); - /* select page 0x266 */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT); - /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac); - /* return to main page 0 */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); - /* write to 0x0 to register 0x1d on main page 0 */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); - mdelay(1); -} - -static int rtl8390_configure_generic(struct phy_device *phydev) -{ - int mac = phydev->mdio.addr; - u32 val, phy_id; - - val = phy_read(phydev, 2); - phy_id = val << 16; - val = phy_read(phydev, 3); - phy_id |= val; - pr_debug("Phy on MAC %d: %x\n", mac, phy_id); - - /* Read internal PHY ID */ - phy_write_paged(phydev, 31, 27, 0x0002); - val = phy_read_paged(phydev, 31, 28); - - /* Internal RTL8218B, version 2 */ - phydev_info(phydev, "Detected unknown %x\n", val); - return 0; -} - -static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev) -{ - u32 val, phy_id; - int i, p, ipd_flag; - int mac = phydev->mdio.addr; - struct fw_header *h; - u32 *rtl838x_6275B_intPhy_perport; - u32 *rtl8218b_6276B_hwEsd_perport; - - val = phy_read(phydev, 2); - phy_id = val << 16; - val = phy_read(phydev, 3); - phy_id |= val; - pr_debug("Phy on MAC %d: %x\n", mac, phy_id); - - /* Read internal PHY ID */ - phy_write_paged(phydev, 31, 27, 0x0002); - val = phy_read_paged(phydev, 31, 28); - if (val != 0x6275) { - phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val); - return -1; - } - - /* Internal RTL8218B, version 2 */ - phydev_info(phydev, "Detected internal RTL8218B\n"); - - h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1); - if (!h) - return -1; - - if (h->phy != 0x83800000) { - phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n"); - return -1; - } - - rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) - + h->parts[8].start; - - rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) - + h->parts[9].start; - - if (sw_r32(RTL838X_DMY_REG31) == 0x1) - ipd_flag = 1; - - val = phy_read(phydev, 0); - if (val & BIT(11)) - rtl8380_int_phy_on_off(phydev, true); - else - rtl8380_phy_reset(phydev); - msleep(100); - - /* Ready PHY for patch */ - for (p = 0; p < 8; p++) { - phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH); - phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010); - } - msleep(500); - for (p = 0; p < 8; p++) { - for (i = 0; i < 100 ; i++) { - val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10); - if (val & 0x40) - break; - } - if (i >= 100) { - phydev_err(phydev, - "ERROR: Port %d not ready for patch.\n", - mac + p); - return -1; - } - } - for (p = 0; p < 8; p++) { - i = 0; - while (rtl838x_6275B_intPhy_perport[i * 2]) { - phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, - rtl838x_6275B_intPhy_perport[i * 2], - rtl838x_6275B_intPhy_perport[i * 2 + 1]); - i++; - } - i = 0; - while (rtl8218b_6276B_hwEsd_perport[i * 2]) { - phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, - rtl8218b_6276B_hwEsd_perport[i * 2], - rtl8218b_6276B_hwEsd_perport[i * 2 + 1]); - i++; - } - } - return 0; -} - -static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev) -{ - u32 val, ipd, phy_id; - int i, l; - int mac = phydev->mdio.addr; - struct fw_header *h; - u32 *rtl8380_rtl8218b_perchip; - u32 *rtl8218B_6276B_rtl8380_perport; - u32 *rtl8380_rtl8218b_perport; - - if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) { - phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n"); - return -1; - } - val = phy_read(phydev, 2); - phy_id = val << 16; - val = phy_read(phydev, 3); - phy_id |= val; - pr_info("Phy on MAC %d: %x\n", mac, phy_id); - - /* Read internal PHY ID */ - phy_write_paged(phydev, 31, 27, 0x0002); - val = phy_read_paged(phydev, 31, 28); - if (val != 0x6276) { - phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val); - return -1; - } - phydev_info(phydev, "Detected external RTL8218B\n"); - - h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1); - if (!h) - return -1; - - if (h->phy != 0x8218b000) { - phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n"); - return -1; - } - - rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) - + h->parts[0].start; - - rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) - + h->parts[1].start; - - rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) - + h->parts[2].start; - - val = phy_read(phydev, 0); - if (val & (1 << 11)) - rtl8380_int_phy_on_off(phydev, true); - else - rtl8380_phy_reset(phydev); - - msleep(100); - - /* Get Chip revision */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); - phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4); - val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c); - - phydev_info(phydev, "Detected chip revision %04x\n", val); - - i = 0; - while (rtl8380_rtl8218b_perchip[i * 3] - && rtl8380_rtl8218b_perchip[i * 3 + 1]) { - phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3], - RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1], - rtl8380_rtl8218b_perchip[i * 3 + 2]); - i++; - } - - /* Enable PHY */ - for (i = 0; i < 8; i++) { - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140); - } - mdelay(100); - - /* Request patch */ - for (i = 0; i < 8; i++) { - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH); - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010); - } - - mdelay(300); - - /* Verify patch readiness */ - for (i = 0; i < 8; i++) { - for (l = 0; l < 100; l++) { - val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10); - if (val & 0x40) - break; - } - if (l >= 100) { - phydev_err(phydev, "Could not patch PHY\n"); - return -1; - } - } - - /* Use Broadcast ID method for patching */ - rtl821x_phy_setup_package_broadcast(phydev, true); - - phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8); - phy_write_paged(phydev, 0x26e, 17, 0xb); - phy_write_paged(phydev, 0x26e, 16, 0x2); - mdelay(1); - ipd = phy_read_paged(phydev, 0x26e, 19); - phy_write_paged(phydev, 0, 30, 0); - ipd = (ipd >> 4) & 0xf; /* unused ? */ - - i = 0; - while (rtl8218B_6276B_rtl8380_perport[i * 2]) { - phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2], - rtl8218B_6276B_rtl8380_perport[i * 2 + 1]); - i++; - } - - /*Disable broadcast ID*/ - rtl821x_phy_setup_package_broadcast(phydev, false); - - return 0; -} - -static int rtl8218b_ext_match_phy_device(struct phy_device *phydev) -{ - int addr = phydev->mdio.addr; - - /* Both the RTL8214FC and the external RTL8218B have the same - * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev - * at PHY IDs 0-7, while the RTL8214FC must be attached via - * the pair of SGMII/1000Base-X with higher PHY-IDs - */ - if (soc_info.family == RTL8380_FAMILY_ID) - return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8; - else - return phydev->phy_id == PHY_ID_RTL8218B_E; -} - -static bool rtl8214fc_media_is_fibre(struct phy_device *phydev) -{ - int mac = phydev->mdio.addr; - - static int reg[] = {16, 19, 20, 21}; - u32 val; - - phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL); - val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]); - phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); - - if (val & BIT(11)) - return false; - - return true; -} - -static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on) -{ - char *state = on ? "on" : "off"; - - if (port == PORT_FIBRE) { - pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr); - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE); - } else { - pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr); - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - } - - if (on) { - phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), 0); - } else { - phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BIT(11)); - } - - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); -} - -static int rtl8214fc_suspend(struct phy_device *phydev) -{ - rtl8214fc_power_set(phydev, PORT_MII, false); - rtl8214fc_power_set(phydev, PORT_FIBRE, false); - - return 0; -} - -static int rtl8214fc_resume(struct phy_device *phydev) -{ - if (rtl8214fc_media_is_fibre(phydev)) { - rtl8214fc_power_set(phydev, PORT_MII, false); - rtl8214fc_power_set(phydev, PORT_FIBRE, true); - } else { - rtl8214fc_power_set(phydev, PORT_FIBRE, false); - rtl8214fc_power_set(phydev, PORT_MII, true); - } - - return 0; -} - -static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre) -{ - int mac = phydev->mdio.addr; - - static int reg[] = {16, 19, 20, 21}; - int val; - - pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre); - phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL); - val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]); - - val |= BIT(10); - if (set_fibre) { - val &= ~BIT(11); - } else { - val |= BIT(11); - } - - phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL); - phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val); - phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); - - if (!phydev->suspended) { - if (set_fibre) { - rtl8214fc_power_set(phydev, PORT_MII, false); - rtl8214fc_power_set(phydev, PORT_FIBRE, true); - } else { - rtl8214fc_power_set(phydev, PORT_FIBRE, false); - rtl8214fc_power_set(phydev, PORT_MII, true); - } - } -} - -static int rtl8214fc_set_port(struct phy_device *phydev, int port) -{ - bool is_fibre = (port == PORT_FIBRE ? true : false); - int addr = phydev->mdio.addr; - - pr_debug("%s port %d to %d\n", __func__, addr, port); - - rtl8214fc_media_set(phydev, is_fibre); - return 0; -} - -static int rtl8214fc_get_port(struct phy_device *phydev) -{ - int addr = phydev->mdio.addr; - - pr_debug("%s: port %d\n", __func__, addr); - if (rtl8214fc_media_is_fibre(phydev)) - return PORT_FIBRE; - return PORT_MII; -} - -/* - * Enable EEE on the RTL8218B PHYs - * The method used is not the preferred way (which would be based on the MAC-EEE state, - * but the only way that works since the kernel first enables EEE in the MAC - * and then sets up the PHY. The MAC-based approach would require the oppsite. - */ -void rtl8218d_eee_set(struct phy_device *phydev, bool enable) -{ - u32 val; - bool an_enabled; - - pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable); - /* Set GPHY page to copper */ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - - val = phy_read(phydev, 0); - an_enabled = val & BIT(12); - - /* Enable 100M (bit 1) / 1000M (bit 2) EEE */ - val = phy_read_mmd(phydev, 7, 60); - val |= BIT(2) | BIT(1); - phy_write_mmd(phydev, 7, 60, enable ? 0x6 : 0); - - /* 500M EEE ability */ - val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20); - if (enable) - val |= BIT(7); - else - val &= ~BIT(7); - phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val); - - /* Restart AN if enabled */ - if (an_enabled) { - val = phy_read(phydev, 0); - val |= BIT(9); - phy_write(phydev, 0, val); - } - - /* GPHY page back to auto*/ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); -} - -static int rtl8218b_get_eee(struct phy_device *phydev, - struct ethtool_eee *e) -{ - u32 val; - int addr = phydev->mdio.addr; - - pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled); - - /* Set GPHY page to copper */ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - - val = phy_read_paged(phydev, 7, 60); - if (e->eee_enabled) { - // Verify vs MAC-based EEE - e->eee_enabled = !!(val & BIT(7)); - if (!e->eee_enabled) { - val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25); - e->eee_enabled = !!(val & BIT(4)); - } - } - pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled); - - /* GPHY page to auto */ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); - - return 0; -} - -static int rtl8218d_get_eee(struct phy_device *phydev, - struct ethtool_eee *e) -{ - u32 val; - int addr = phydev->mdio.addr; - - pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled); - - /* Set GPHY page to copper */ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - - val = phy_read_paged(phydev, 7, 60); - if (e->eee_enabled) - e->eee_enabled = !!(val & BIT(7)); - pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled); - - /* GPHY page to auto */ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); - - return 0; -} - -static int rtl8214fc_set_eee(struct phy_device *phydev, - struct ethtool_eee *e) -{ - u32 poll_state; - int port = phydev->mdio.addr; - bool an_enabled; - u32 val; - - pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled); - - if (rtl8214fc_media_is_fibre(phydev)) { - netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port); - return -ENOTSUPP; - } - - poll_state = disable_polling(port); - - /* Set GPHY page to copper */ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - - // Get auto-negotiation status - val = phy_read(phydev, 0); - an_enabled = val & BIT(12); - - pr_info("%s: aneg: %d\n", __func__, an_enabled); - val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25); - val &= ~BIT(5); // Use MAC-based EEE - phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val); - - /* Enable 100M (bit 1) / 1000M (bit 2) EEE */ - phy_write_paged(phydev, 7, 60, e->eee_enabled ? 0x6 : 0); - - /* 500M EEE ability */ - val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20); - if (e->eee_enabled) - val |= BIT(7); - else - val &= ~BIT(7); - - phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val); - - /* Restart AN if enabled */ - if (an_enabled) { - pr_info("%s: doing aneg\n", __func__); - val = phy_read(phydev, 0); - val |= BIT(9); - phy_write(phydev, 0, val); - } - - /* GPHY page back to auto*/ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); - - resume_polling(poll_state); - - return 0; -} - -static int rtl8214fc_get_eee(struct phy_device *phydev, - struct ethtool_eee *e) -{ - int addr = phydev->mdio.addr; - - pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled); - if (rtl8214fc_media_is_fibre(phydev)) { - netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr); - return -ENOTSUPP; - } - - return rtl8218b_get_eee(phydev, e); -} - -static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e) -{ - int port = phydev->mdio.addr; - u64 poll_state; - u32 val; - bool an_enabled; - - pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled); - - poll_state = disable_polling(port); - - /* Set GPHY page to copper */ - phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - val = phy_read(phydev, 0); - an_enabled = val & BIT(12); - - if (e->eee_enabled) { - /* 100/1000M EEE Capability */ - phy_write(phydev, 13, 0x0007); - phy_write(phydev, 14, 0x003C); - phy_write(phydev, 13, 0x4007); - phy_write(phydev, 14, 0x0006); - - val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25); - val |= BIT(4); - phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val); - } else { - /* 100/1000M EEE Capability */ - phy_write(phydev, 13, 0x0007); - phy_write(phydev, 14, 0x003C); - phy_write(phydev, 13, 0x0007); - phy_write(phydev, 14, 0x0000); - - val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25); - val &= ~BIT(4); - phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val); - } - - /* Restart AN if enabled */ - if (an_enabled) { - val = phy_read(phydev, 0); - val |= BIT(9); - phy_write(phydev, 0, val); - } - - /* GPHY page back to auto*/ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); - - pr_info("%s done\n", __func__); - resume_polling(poll_state); - - return 0; -} - -static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e) -{ - int addr = phydev->mdio.addr; - u64 poll_state; - - pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled); - - poll_state = disable_polling(addr); - - rtl8218d_eee_set(phydev, (bool) e->eee_enabled); - - resume_polling(poll_state); - - return 0; -} - -static int rtl8214c_match_phy_device(struct phy_device *phydev) -{ - return phydev->phy_id == PHY_ID_RTL8214C; -} - -static int rtl8380_configure_rtl8214c(struct phy_device *phydev) -{ - u32 phy_id, val; - int mac = phydev->mdio.addr; - - val = phy_read(phydev, 2); - phy_id = val << 16; - val = phy_read(phydev, 3); - phy_id |= val; - pr_debug("Phy on MAC %d: %x\n", mac, phy_id); - - phydev_info(phydev, "Detected external RTL8214C\n"); - - /* GPHY auto conf */ - phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); - return 0; -} - -static int rtl8380_configure_rtl8214fc(struct phy_device *phydev) -{ - u32 phy_id, val, page = 0; - int i, l; - int mac = phydev->mdio.addr; - struct fw_header *h; - u32 *rtl8380_rtl8214fc_perchip; - u32 *rtl8380_rtl8214fc_perport; - - val = phy_read(phydev, 2); - phy_id = val << 16; - val = phy_read(phydev, 3); - phy_id |= val; - pr_debug("Phy on MAC %d: %x\n", mac, phy_id); - - /* Read internal PHY id */ - phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - phy_write_paged(phydev, 0x1f, 0x1b, 0x0002); - val = phy_read_paged(phydev, 0x1f, 0x1c); - if (val != 0x6276) { - phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val); - return -1; - } - phydev_info(phydev, "Detected external RTL8214FC\n"); - - h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1); - if (!h) - return -1; - - if (h->phy != 0x8214fc00) { - phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n"); - return -1; - } - - rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) - + h->parts[0].start; - - rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) - + h->parts[1].start; - - /* detect phy version */ - phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004); - val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28); - - val = phy_read(phydev, 16); - if (val & (1 << 11)) - rtl8380_rtl8214fc_on_off(phydev, true); - else - rtl8380_phy_reset(phydev); - - msleep(100); - phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - - i = 0; - while (rtl8380_rtl8214fc_perchip[i * 3] - && rtl8380_rtl8214fc_perchip[i * 3 + 1]) { - if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f) - page = rtl8380_rtl8214fc_perchip[i * 3 + 2]; - if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) { - val = phy_read_paged(phydev, 0x260, 13); - val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] - & 0xe0ff); - phy_write_paged(phydev, RTL83XX_PAGE_RAW, - rtl8380_rtl8214fc_perchip[i * 3 + 1], val); - } else { - phy_write_paged(phydev, RTL83XX_PAGE_RAW, - rtl8380_rtl8214fc_perchip[i * 3 + 1], - rtl8380_rtl8214fc_perchip[i * 3 + 2]); - } - i++; - } - - /* Force copper medium */ - for (i = 0; i < 4; i++) { - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER); - } - - /* Enable PHY */ - for (i = 0; i < 4; i++) { - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140); - } - mdelay(100); - - /* Disable Autosensing */ - for (i = 0; i < 4; i++) { - for (l = 0; l < 100; l++) { - val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10); - if ((val & 0x7) >= 3) - break; - } - if (l >= 100) { - phydev_err(phydev, "Could not disable autosensing\n"); - return -1; - } - } - - /* Request patch */ - for (i = 0; i < 4; i++) { - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH); - phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010); - } - mdelay(300); - - /* Verify patch readiness */ - for (i = 0; i < 4; i++) { - for (l = 0; l < 100; l++) { - val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10); - if (val & 0x40) - break; - } - if (l >= 100) { - phydev_err(phydev, "Could not patch PHY\n"); - return -1; - } - } - /* Use Broadcast ID method for patching */ - rtl821x_phy_setup_package_broadcast(phydev, true); - - i = 0; - while (rtl8380_rtl8214fc_perport[i * 2]) { - phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2], - rtl8380_rtl8214fc_perport[i * 2 + 1]); - i++; - } - - /*Disable broadcast ID*/ - rtl821x_phy_setup_package_broadcast(phydev, false); - - /* Auto medium selection */ - for (i = 0; i < 4; i++) { - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN); - phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO); - } - - return 0; -} - -static int rtl8214fc_match_phy_device(struct phy_device *phydev) -{ - int addr = phydev->mdio.addr; - - return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24; -} - -static int rtl8380_configure_serdes(struct phy_device *phydev) -{ - u32 v; - u32 sds_conf_value; - int i; - struct fw_header *h; - u32 *rtl8380_sds_take_reset; - u32 *rtl8380_sds_common; - u32 *rtl8380_sds01_qsgmii_6275b; - u32 *rtl8380_sds23_qsgmii_6275b; - u32 *rtl8380_sds4_fiber_6275b; - u32 *rtl8380_sds5_fiber_6275b; - u32 *rtl8380_sds_reset; - u32 *rtl8380_sds_release_reset; - - phydev_info(phydev, "Detected internal RTL8380 SERDES\n"); - - h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1); - if (!h) - return -1; - - if (h->magic != 0x83808380) { - phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n"); - return -1; - } - - rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) - + h->parts[0].start; - - rtl8380_sds_common = (void *)h + sizeof(struct fw_header) - + h->parts[1].start; - - rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) - + h->parts[2].start; - - rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) - + h->parts[3].start; - - rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) - + h->parts[4].start; - - rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) - + h->parts[5].start; - - rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) - + h->parts[6].start; - - rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) - + h->parts[7].start; - - /* Back up serdes power off value */ - sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG); - pr_info("SDS power down value: %x\n", sds_conf_value); - - /* take serdes into reset */ - i = 0; - while (rtl8380_sds_take_reset[2 * i]) { - sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]); - i++; - udelay(1000); - } - - /* apply common serdes patch */ - i = 0; - while (rtl8380_sds_common[2 * i]) { - sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]); - i++; - udelay(1000); - } - - /* internal R/W enable */ - sw_w32(3, RTL838X_INT_RW_CTRL); - - /* SerDes ports 4 and 5 are FIBRE ports */ - sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL); - - /* SerDes module settings, SerDes 0-3 are QSGMII */ - v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10; - /* SerDes 4 and 5 are 1000BX FIBRE */ - v |= 0x4 << 5 | 0x4; - sw_w32(v, RTL838X_SDS_MODE_SEL); - - pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL)); - sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL); - i = 0; - while (rtl8380_sds01_qsgmii_6275b[2 * i]) { - sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1], - rtl8380_sds01_qsgmii_6275b[2 * i]); - i++; - } - - i = 0; - while (rtl8380_sds23_qsgmii_6275b[2 * i]) { - sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]); - i++; - } - - i = 0; - while (rtl8380_sds4_fiber_6275b[2 * i]) { - sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]); - i++; - } - - i = 0; - while (rtl8380_sds5_fiber_6275b[2 * i]) { - sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]); - i++; - } - - i = 0; - while (rtl8380_sds_reset[2 * i]) { - sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]); - i++; - } - - i = 0; - while (rtl8380_sds_release_reset[2 * i]) { - sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]); - i++; - } - - pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG)); - sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG); - - pr_info("Configuration of SERDES done\n"); - return 0; -} - -static int rtl8390_configure_serdes(struct phy_device *phydev) -{ - phydev_info(phydev, "Detected internal RTL8390 SERDES\n"); - - /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */ - sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a); - - /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G, - * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G - * and FRE16_EEE_QUIET_FIB1G - */ - sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0); - - return 0; -} - -void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v) -{ - int l = end_bit - start_bit + 1; - u32 data = v; - - if (l < 32) { - u32 mask = BIT(l) - 1; - - data = rtl930x_read_sds_phy(sds, page, reg); - data &= ~(mask << start_bit); - data |= (v & mask) << start_bit; - } - - rtl930x_write_sds_phy(sds, page, reg, data); -} - -u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit) -{ - int l = end_bit - start_bit + 1; - u32 v = rtl930x_read_sds_phy(sds, page, reg); - - if (l >= 32) - return v; - - return (v >> start_bit) & (BIT(l) - 1); -} - -/* Read the link and speed status of the internal SerDes of the RTL9300 - */ -static int rtl9300_read_status(struct phy_device *phydev) -{ - struct device *dev = &phydev->mdio.dev; - int phy_addr = phydev->mdio.addr; - struct device_node *dn; - u32 sds_num = 0, status, latch_status, mode; - - if (dev->of_node) { - dn = dev->of_node; - - if (of_property_read_u32(dn, "sds", &sds_num)) - sds_num = -1; - pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num); - } else { - dev_err(dev, "No DT node.\n"); - return -EINVAL; - } - - if (sds_num < 0) - return 0; - - mode = rtl9300_sds_mode_get(sds_num); - pr_info("%s got SDS mode %02x\n", __func__, mode); - if (mode == 0x1a) { // 10GR mode - status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12); - latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2); - status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12); - latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2); - } else { - status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0); - latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0); - status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0); - latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0); - } - - pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status); - - if (latch_status) { - phydev->link = true; - if (mode == 0x1a) - phydev->speed = SPEED_10000; - else - phydev->speed = SPEED_1000; - - phydev->duplex = DUPLEX_FULL; - } - - return 0; -} - -void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if) -{ - int page = 0x2e; // 10GR and USXGMII - - if (phy_if == PHY_INTERFACE_MODE_1000BASEX) - page = 0x24; - - rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1); - mdelay(5); - rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0); -} - -/* - * Force PHY modes on 10GBit Serdes - */ -void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if) -{ - int sds_mode; - bool lc_on; - int i, lc_value; - int lane_0 = (sds % 2) ? sds - 1 : sds; - u32 v, cr_0, cr_1, cr_2; - u32 m_bit, l_bit; - - pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if); - switch (phy_if) { - case PHY_INTERFACE_MODE_SGMII: - sds_mode = 0x2; - lc_on = false; - lc_value = 0x1; - break; - - case PHY_INTERFACE_MODE_HSGMII: - sds_mode = 0x12; - lc_value = 0x3; - // Configure LC - break; - - case PHY_INTERFACE_MODE_1000BASEX: - sds_mode = 0x04; - lc_on = false; - break; - - case PHY_INTERFACE_MODE_2500BASEX: - sds_mode = 0x16; - lc_value = 0x3; - // Configure LC - break; - - case PHY_INTERFACE_MODE_10GBASER: - sds_mode = 0x1a; - lc_on = true; - lc_value = 0x5; - break; - - case PHY_INTERFACE_MODE_NA: - // This will disable SerDes - sds_mode = 0x1f; - break; - - default: - pr_err("%s: unknown serdes mode: %s\n", - __func__, phy_modes(phy_if)); - return; - } - - pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode); - // Power down SerDes - rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3); - if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0)); - - if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9)); - // Force mode enable - rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1); - if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9)); - - /* SerDes off */ - rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f); - - if (phy_if == PHY_INTERFACE_MODE_NA) - return; - - if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18)); - // Enable LC and ring - rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf); - - if (sds == lane_0) - rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1); - else - rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1); - - rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3); - - if (lc_on) - rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value); - else - rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value); - - // Force analog LC & ring on - rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf); - - v = lc_on ? 0x3 : 0x1; - - if (sds == lane_0) - rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v); - else - rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v); - - // Force SerDes mode - rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1); - rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode); - - // Toggle LC or Ring - for (i = 0; i < 20; i++) { - mdelay(200); - - rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53); - - m_bit = (lane_0 == sds) ? (4) : (5); - l_bit = (lane_0 == sds) ? (4) : (5); - - cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit); - mdelay(10); - cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit); - mdelay(10); - cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit); - - if (cr_0 && cr_1 && cr_2) { - u32 t; - if (phy_if != PHY_INTERFACE_MODE_10GBASER) - break; - - t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2); - rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1); - - // Reset FSM - rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1); - mdelay(10); - rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0); - mdelay(10); - - // Need to read this twice - v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12); - v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12); - - rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t); - - // Reset FSM again - rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1); - mdelay(10); - rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0); - mdelay(10); - - if (v == 1) - break; - } - - m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1; - l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0; - - rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2); - mdelay(10); - rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3); - } - - rtl930x_sds_rx_rst(sds, phy_if); - - // Re-enable power - rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0); - - pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode); -} - -void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if) -{ - // parameters: rtl9303_80G_txParam_s2 - int impedance = 0x8; - int pre_amp = 0x2; - int main_amp = 0x9; - int post_amp = 0x2; - int pre_en = 0x1; - int post_en = 0x1; - int page; - - switch(phy_if) { - case PHY_INTERFACE_MODE_1000BASEX: - page = 0x25; - break; - case PHY_INTERFACE_MODE_HSGMII: - case PHY_INTERFACE_MODE_2500BASEX: - page = 0x29; - break; - case PHY_INTERFACE_MODE_10GBASER: - page = 0x2f; - break; - default: - pr_err("%s: unsupported PHY mode\n", __func__); - return; - } - - rtl9300_sds_field_w(sds, page, 0x1, 15, 11, pre_amp); - rtl9300_sds_field_w(sds, page, 0x7, 0, 0, pre_en); - rtl9300_sds_field_w(sds, page, 0x7, 8, 4, main_amp); - rtl9300_sds_field_w(sds, page, 0x6, 4, 0, post_amp); - rtl9300_sds_field_w(sds, page, 0x7, 3, 3, post_en); - rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance); -} - -/* - * Wait for clock ready, this assumes the SerDes is in XGMII mode - * timeout is in ms - */ -int rtl9300_sds_clock_wait(int timeout) -{ - u32 v; - unsigned long start = jiffies; - - do { - rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53); - v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4); - if (v == 3) - return 0; - } while (jiffies < start + (HZ / 1000) * timeout); - - return 1; -} - -void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal) -{ - u32 v10, v1; - - v10 = rtl930x_read_sds_phy(sds, 6, 2); // 10GBit, page 6, reg 2 - v1 = rtl930x_read_sds_phy(sds, 0, 0); // 1GBit, page 0, reg 0 - pr_info("%s: registers before %08x %08x\n", __func__, v10, v1); - - v10 &= ~(BIT(13) | BIT(14)); - v1 &= ~(BIT(8) | BIT(9)); - - v10 |= rx_normal ? 0 : BIT(13); - v1 |= rx_normal ? 0 : BIT(9); - - v10 |= tx_normal ? 0 : BIT(14); - v1 |= tx_normal ? 0 : BIT(8); - - rtl930x_write_sds_phy(sds, 6, 2, v10); - rtl930x_write_sds_phy(sds, 0, 0, v1); - - v10 = rtl930x_read_sds_phy(sds, 6, 2); - v1 = rtl930x_read_sds_phy(sds, 0, 0); - pr_info("%s: registers after %08x %08x\n", __func__, v10, v1); -} - -void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[]) -{ - if (manual) { - switch(dcvs_id) { - case 0: - rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1); - rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]); - break; - case 1: - rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]); - break; - case 2: - rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]); - break; - case 3: - rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]); - break; - case 4: - rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]); - break; - case 5: - rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]); - break; - default: - break; - } - } else { - switch(dcvs_id) { - case 0: - rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0); - break; - case 1: - rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0); - break; - case 2: - rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0); - break; - case 3: - rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0); - break; - case 4: - rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0); - break; - case 5: - rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0); - break; - default: - break; - } - mdelay(1); - } -} - -void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[]) -{ - u32 dcvs_sign_out = 0, dcvs_coef_bin = 0; - bool dcvs_manual; - - if (!(sds_num % 2)) - rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f); - else - rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31); - - // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] - rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - - // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] - rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20); - - switch(dcvs_id) { - case 0: - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22); - mdelay(1); - - // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); - dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14); - break; - - case 1: - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23); - mdelay(1); - - // ##DCVS0 Read Out - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); - dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13); - break; - - case 2: - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24); - mdelay(1); - - // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); - dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12); - break; - case 3: - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25); - mdelay(1); - - // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); - dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11); - break; - - case 4: - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c); - mdelay(1); - - // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); - dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15); - break; - - case 5: - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d); - mdelay(1); - - // ##DCVS0 Read Out - dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4); - dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0); - dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11); - break; - - default: - break; - } - - if (dcvs_sign_out) - pr_info("%s DCVS %u Sign: -", __func__, dcvs_id); - else - pr_info("%s DCVS %u Sign: +", __func__, dcvs_id); - - pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin); - pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual); - - dcvs_list[0] = dcvs_sign_out; - dcvs_list[1] = dcvs_coef_bin; -} - -void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray) -{ - if (manual) { - rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray); - } else { - rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0); - mdelay(100); - } -} - -void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset) -{ - if (manual) { - rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset); - } else { - rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset); - mdelay(1); - } -} - -#define GRAY_BITS 5 -u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code) -{ - int i, j, m; - u32 g[GRAY_BITS]; - u32 c[GRAY_BITS]; - u32 leq_binary = 0; - - for(i = 0; i < GRAY_BITS; i++) - g[i] = (gray_code & BIT(i)) >> i; - - m = GRAY_BITS - 1; - - c[m] = g[m]; - - for(i = 0; i < m; i++) { - c[i] = g[i]; - for(j = i + 1; j < GRAY_BITS; j++) - c[i] = c[i] ^ g[j]; - } - - for(i = 0; i < GRAY_BITS; i++) - leq_binary += c[i] << i; - - return leq_binary; -} - -u32 rtl9300_sds_rxcal_leq_read(int sds_num) -{ - u32 leq_gray, leq_bin; - bool leq_manual; - - if (!(sds_num % 2)) - rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f); - else - rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31); - - // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] - rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - - // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] - rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10); - mdelay(1); - - // ##LEQ Read Out - leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3); - leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15); - leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray); - - pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin); - pr_info("LEQ manual: %u", leq_manual); - - return leq_bin; -} - -void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[]) -{ - if (manual) { - rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]); - } else { - rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0); - mdelay(10); - } -} - -void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[]) -{ - u32 vth_manual; - - //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; //Lane0 - //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; //Lane1 - if (!(sds_num % 2)) - rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f); - else - rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31); - - //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] - rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] - rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20); - //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc); - - mdelay(1); - - //##VthP & VthN Read Out - vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); // v_thp set bin - vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); // v_thn set bin - - pr_info("vth_set_bin = %d", vth_list[0]); - pr_info("vth_set_bin = %d", vth_list[1]); - - vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13); - pr_info("Vth Maunal = %d", vth_manual); -} - -void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[]) -{ - if (manual) { - switch(tap_id) { - case 0: - //##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value - rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); - rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]); - rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]); - break; - case 1: - rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); - rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]); - rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]); - rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]); - break; - case 2: - rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]); - break; - case 3: - rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); - rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]); - break; - case 4: - rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1); - rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]); - rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]); - rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]); - break; - default: - break; - } - } else { - rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0); - mdelay(10); - } -} - -void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[]) -{ - u32 tap0_sign_out; - u32 tap0_coef_bin; - u32 tap_sign_out_even; - u32 tap_coef_bin_even; - u32 tap_sign_out_odd; - u32 tap_coef_bin_odd; - bool tap_manual; - - if (!(sds_num % 2)) - rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f); - else - rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31); - - //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] - rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] - rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20); - - if (!tap_id) { - //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0); - //##Tap1 Even Read Out - mdelay(1); - tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5); - tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0); - - if (tap0_sign_out == 1) - pr_info("Tap0 Sign : -"); - else - pr_info("Tap0 Sign : +"); - - pr_info("tap0_coef_bin = %d", tap0_coef_bin); - - tap_list[0] = tap0_sign_out; - tap_list[1] = tap0_coef_bin; - - tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7); - pr_info("tap0 manual = %u",tap_manual); - } else { - //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id); - mdelay(1); - //##Tap1 Even Read Out - tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5); - tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0); - - //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5)); - //##Tap1 Odd Read Out - tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5); - tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0); - - if (tap_sign_out_even == 1) - pr_info("Tap %u even sign: -", tap_id); - else - pr_info("Tap %u even sign: +", tap_id); - - pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even); - - if (tap_sign_out_odd == 1) - pr_info("Tap %u odd sign: -", tap_id); - else - pr_info("Tap %u odd sign: +", tap_id); - - pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd); - - tap_list[0] = tap_sign_out_even; - tap_list[1] = tap_coef_bin_even; - tap_list[2] = tap_sign_out_odd; - tap_list[3] = tap_coef_bin_odd; - - tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7); - pr_info("tap %u manual = %d",tap_id, tap_manual); - } -} - -void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode) -{ - // From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam - int tap0_init_val = 0x1f; // Initial Decision Fed Equalizer 0 tap - int vth_min = 0x0; - - pr_info("start_1.1.1 initial value for sds %d\n", sds); - rtl930x_write_sds_phy(sds, 6, 0, 0); - - // FGCAL - rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20); - rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x1); - - // DCVS - rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0xf); - rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x1); - rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x1); - - // LEQ (Long Term Equivalent signal level) - rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x0); - - // DFE (Decision Fed Equalizer) - rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val); - rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0); - - // Vth - rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x7); - rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x7); - rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min); - - pr_info("end_1.1.1 --\n"); - - pr_info("start_1.1.2 Load DFE init. value\n"); - - rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f); - - pr_info("end_1.1.2\n"); - - pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n"); - - rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x0); - rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x1); - rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x0); - rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x0); - - pr_info("end_1.1.3 --\n"); - - pr_info("start_1.1.4 offset cali setting\n"); - - rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x3); - - pr_info("end_1.1.4\n"); - - pr_info("start_1.1.5 LEQ and DFE setting\n"); - - // TODO: make this work for DAC cables of different lengths - // For a 10GBit serdes wit Fibre, SDS 8 or 9 - if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX) - rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2); - else - pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__); - - // No serdes, check for Aquantia PHYs - rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2); - - rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f); - rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f); - rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f); - rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c); - rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x3); - - pr_info("end_1.1.5\n"); -} - -void rtl9300_do_rx_calibration_2_1(u32 sds_num) -{ - pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n"); - - // Gray config endis to 1 - rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x1); - - // ForegroundOffsetCal_Manual(auto mode) - rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x0); - - pr_info("end_1.2.1"); -} - -void rtl9300_do_rx_calibration_2_2(int sds_num) -{ - //Force Rx-Run = 0 - rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0); - - rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER); -} - -void rtl9300_do_rx_calibration_2_3(int sds_num) -{ - u32 fgcal_binary, fgcal_gray; - u32 offset_range; - - pr_info("start_1.2.3 Foreground Calibration\n"); - - while(1) { - if (!(sds_num % 2)) - rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f); - else - rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31); - - // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] - rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1); - // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] - rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20); - // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf); - // ##FGCAL read gray - fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0); - // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] - rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe); - // ##FGCAL read binary - fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0); - - pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n", - __func__, fgcal_gray, fgcal_binary); - - offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14); - - if (fgcal_binary > 60 || fgcal_binary < 3) { - if (offset_range == 3) { - pr_info("%s: Foreground Calibration result marginal!", __func__); - break; - } else { - offset_range++; - rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range); - rtl9300_do_rx_calibration_2_2(sds_num); - } - } else { - break; - } - } - pr_info("%s: end_1.2.3\n", __func__); -} - -void rtl9300_do_rx_calibration_2(int sds) -{ - rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER); - rtl9300_do_rx_calibration_2_1(sds); - rtl9300_do_rx_calibration_2_2(sds); - rtl9300_do_rx_calibration_2_3(sds); -} - -void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode) -{ - pr_info("start_1.3.1"); - - // ##1.3.1 - if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX) - rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0); - - rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0); - rtl9300_sds_rxcal_leq_manual(sds_num, false, 0); - - pr_info("end_1.3.1"); -} - -void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode) -{ - u32 sum10 = 0, avg10, int10; - int dac_long_cable_offset; - bool eq_hold_enabled; - int i; - - if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) { - // rtl9300_rxCaliConf_serdes_myParam - dac_long_cable_offset = 3; - eq_hold_enabled = true; - } else { - // rtl9300_rxCaliConf_phy_myParam - dac_long_cable_offset = 0; - eq_hold_enabled = false; - } - - if (phy_mode == PHY_INTERFACE_MODE_1000BASEX) - pr_warn("%s: LEQ only valid for 10GR!\n", __func__); - - pr_info("start_1.3.2"); - - for(i = 0; i < 10; i++) { - sum10 += rtl9300_sds_rxcal_leq_read(sds_num); - mdelay(10); - } - - avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0); - int10 = sum10 / 10; - - pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10); - - if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) { - if (dac_long_cable_offset) { - rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset); - rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled); - if (phy_mode == PHY_INTERFACE_MODE_10GBASER) - rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10); - } else { - if (sum10 >= 5) { - rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3); - rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1); - if (phy_mode == PHY_INTERFACE_MODE_10GBASER) - rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10); - } else { - rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0); - rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1); - if (phy_mode == PHY_INTERFACE_MODE_10GBASER) - rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10); - } - } - } - - pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num)); - - pr_info("end_1.3.2"); -} - -void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode) -{ - rtl9300_sds_rxcal_3_1(sds_num, phy_mode); - - if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) - rtl9300_sds_rxcal_3_2(sds_num, phy_mode); -} - -void rtl9300_do_rx_calibration_4_1(int sds_num) -{ - u32 vth_list[2] = {0, 0}; - u32 tap0_list[4] = {0, 0, 0, 0}; - - pr_info("start_1.4.1"); - - // ##1.4.1 - rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list); - rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list); - mdelay(200); - - pr_info("end_1.4.1"); -} - -void rtl9300_do_rx_calibration_4_2(u32 sds_num) -{ - u32 vth_list[2]; - u32 tap_list[4]; - - pr_info("start_1.4.2"); - - rtl9300_sds_rxcal_vth_get(sds_num, vth_list); - rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list); - - mdelay(100); - - rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list); - rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list); - - pr_info("end_1.4.2"); -} - -void rtl9300_do_rx_calibration_4(u32 sds_num) -{ - rtl9300_do_rx_calibration_4_1(sds_num); - rtl9300_do_rx_calibration_4_2(sds_num); -} - -void rtl9300_do_rx_calibration_5_2(u32 sds_num) -{ - u32 tap1_list[4] = {0}; - u32 tap2_list[4] = {0}; - u32 tap3_list[4] = {0}; - u32 tap4_list[4] = {0}; - - pr_info("start_1.5.2"); - - rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list); - rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list); - rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list); - rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list); - - mdelay(30); - - pr_info("end_1.5.2"); -} - -void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode) -{ - if (phy_mode == PHY_INTERFACE_MODE_10GBASER) // dfeTap1_4Enable true - rtl9300_do_rx_calibration_5_2(sds_num); -} - - -void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num) -{ - u32 tap1_list[4] = {0}; - u32 tap2_list[4] = {0}; - u32 tap3_list[4] = {0}; - u32 tap4_list[4] = {0}; - - rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list); - rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list); - rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list); - rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list); - - mdelay(10); -} - -void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode) -{ - u32 latch_sts; - - rtl9300_do_rx_calibration_1(sds, phy_mode); - rtl9300_do_rx_calibration_2(sds); - rtl9300_do_rx_calibration_4(sds); - rtl9300_do_rx_calibration_5(sds, phy_mode); - mdelay(20); - - // Do this only for 10GR mode, SDS active in mode 0x1a - if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) { - pr_info("%s: SDS enabled\n", __func__); - latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2); - mdelay(1); - latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2); - if (latch_sts) { - rtl9300_do_rx_calibration_dfe_disable(sds); - rtl9300_do_rx_calibration_4(sds); - rtl9300_do_rx_calibration_5(sds, phy_mode); - } - } -} - -int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode) -{ - switch (phy_mode) { - case PHY_INTERFACE_MODE_XGMII: - break; - - case PHY_INTERFACE_MODE_10GBASER: - // Read twice to clear - rtl930x_read_sds_phy(sds_num, 5, 1); - rtl930x_read_sds_phy(sds_num, 5, 1); - break; - - case PHY_INTERFACE_MODE_1000BASEX: - rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0); - rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0); - rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0); - break; - - default: - pr_info("%s unsupported phy mode\n", __func__); - return -1; - } - - return 0; -} - -u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode) -{ - u32 v = 0; - - switch (phy_mode) { - case PHY_INTERFACE_MODE_XGMII: - break; - - case PHY_INTERFACE_MODE_10GBASER: - v = rtl930x_read_sds_phy(sds_num, 5, 1); - return v & 0xff; - - default: - pr_info("%s unsupported PHY-mode\n", __func__); - } - - return v; -} - -int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode) -{ - u32 errors1, errors2; - - rtl9300_sds_sym_err_reset(sds_num, phy_mode); - rtl9300_sds_sym_err_reset(sds_num, phy_mode); - - // Count errors during 1ms - errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode); - mdelay(1); - errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode); - - switch (phy_mode) { - case PHY_INTERFACE_MODE_XGMII: - - if ((errors2 - errors1 > 100) - || (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) { - pr_info("%s XSGMII error rate too high\n", __func__); - return 1; - } - break; - case PHY_INTERFACE_MODE_10GBASER: - if (errors2 > 0) { - pr_info("%s 10GBASER error rate too high\n", __func__); - return 1; - } - break; - default: - return 1; - } - return 0; -} - -void rtl9300_phy_enable_10g_1g(int sds_num) -{ - u32 v; - - // Enable 1GBit PHY - v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG); - pr_info("%s 1gbit phy: %08x\n", __func__, v); - v &= ~BIT(PHY_POWER_BIT); - rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG, v); - pr_info("%s 1gbit phy enabled: %08x\n", __func__, v); - - // Enable 10GBit PHY - v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG); - pr_info("%s 10gbit phy: %08x\n", __func__, v); - v &= ~BIT(PHY_POWER_BIT); - rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG, v); - pr_info("%s 10gbit phy after: %08x\n", __func__, v); - - // dal_longan_construct_mac_default_10gmedia_fiber - v = rtl930x_read_sds_phy(sds_num, 0x1f, 11); - pr_info("%s set medium: %08x\n", __func__, v); - v |= BIT(1); - rtl930x_write_sds_phy(sds_num, 0x1f, 11, v); - pr_info("%s set medium after: %08x\n", __func__, v); -} - -#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) -// phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a -int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode) -{ - int sds_mode; - int calib_tries = 0; - - switch (phy_mode) { - case PHY_INTERFACE_MODE_HSGMII: - sds_mode = 0x12; - break; - case PHY_INTERFACE_MODE_1000BASEX: - sds_mode = 0x04; - break; - case PHY_INTERFACE_MODE_XGMII: - sds_mode = 0x10; - break; - case PHY_INTERFACE_MODE_10GBASER: - sds_mode = 0x1a; - break; - case PHY_INTERFACE_MODE_USXGMII: - sds_mode = 0x0d; - break; - default: - pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode)); - return -EINVAL; - } - - // Maybe use dal_longan_sds_init - - // dal_longan_construct_serdesConfig_init // Serdes Construct - rtl9300_phy_enable_10g_1g(sds_num); - - // Set Serdes Mode - rtl9300_sds_set(sds_num, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO - - // Do RX calibration - do { - rtl9300_do_rx_calibration(sds_num, phy_mode); - calib_tries++; - mdelay(50); - } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3); - - - return 0; -} - -typedef struct { - u8 page; - u8 reg; - u16 data; -} sds_config; - -sds_config rtl9300_a_sds_10gr_lane0[] = -{ - /*1G*/ - {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206}, - {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, - {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000}, - {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020}, - {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF}, - {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311}, - {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001}, - {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, - {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, - {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, - {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, - {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, - {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, - {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641}, - {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902}, - {0x2F, 0x1D, 0x66E1}, - /*3.125G*/ - {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000}, - {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4}, - {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9}, - {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400}, - {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF}, - {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001}, - {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F}, - {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840}, - /*10G*/ - {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800}, - {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, - {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, - {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, - {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, - {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, - {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, - {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300}, - {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C}, - {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4}, - {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, - {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008}, - {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902}, - {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109}, - {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109}, - {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, - {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1}, -}; - -sds_config rtl9300_a_sds_10gr_lane1[] = -{ - /*1G*/ - {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206}, - {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, - {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, - {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, - {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, - {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, - {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, - {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F}, - {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF}, - {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001}, - {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F}, - {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840}, - {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, - {0x2D, 0x14, 0x1808}, - /*3.125G*/ - {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000}, - {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4}, - {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9}, - {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400}, - {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, - {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, - {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F}, - {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840}, - /*10G*/ - {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800}, - {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, - {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005}, - {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000}, - {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020}, - {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF}, - {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F}, - {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001}, - {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300}, - {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C}, - {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4}, - {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, - {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87}, - {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808}, -}; - -int rtl9300_sds_cmu_band_get(int sds) -{ - u32 page; - u32 en; - u32 cmu_band; - -// page = rtl9300_sds_cmu_page_get(sds); - page = 0x25; // 10GR and 1000BX - sds = (sds % 2) ? (sds - 1) : (sds); - - rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1); - rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1); - - en = rtl9300_sds_field_r(sds, page, 27, 1, 1); - if(!en) { // Auto mode - rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31); - - cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1); - } else { - cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0); - } - - return cmu_band; -} - -int rtl9300_configure_serdes(struct phy_device *phydev) -{ - struct device *dev = &phydev->mdio.dev; - int phy_addr = phydev->mdio.addr; - struct device_node *dn; - u32 sds_num = 0; - int sds_mode, calib_tries = 0, phy_mode = PHY_INTERFACE_MODE_10GBASER, i; - - if (dev->of_node) { - dn = dev->of_node; - - if (of_property_read_u32(dn, "sds", &sds_num)) - sds_num = -1; - pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num); - } else { - dev_err(dev, "No DT node.\n"); - return -EINVAL; - } - - if (sds_num < 0) - return 0; - - if (phy_mode != PHY_INTERFACE_MODE_10GBASER) // TODO: for now we only patch 10GR SerDes - return 0; - - switch (phy_mode) { - case PHY_INTERFACE_MODE_HSGMII: - sds_mode = 0x12; - break; - case PHY_INTERFACE_MODE_1000BASEX: - sds_mode = 0x04; - break; - case PHY_INTERFACE_MODE_XGMII: - sds_mode = 0x10; - break; - case PHY_INTERFACE_MODE_10GBASER: - sds_mode = 0x1a; - break; - case PHY_INTERFACE_MODE_USXGMII: - sds_mode = 0x0d; - break; - default: - pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode)); - return -EINVAL; - } - - pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num)); - - // Turn Off Serdes - rtl9300_sds_rst(sds_num, 0x1f); - - pr_info("%s PATCHING SerDes %d\n", __func__, sds_num); - if (sds_num % 2) { - for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) { - rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page, - rtl9300_a_sds_10gr_lane1[i].reg, - rtl9300_a_sds_10gr_lane1[i].data); - } - } else { - for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) { - rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page, - rtl9300_a_sds_10gr_lane0[i].reg, - rtl9300_a_sds_10gr_lane0[i].data); - } - } - - rtl9300_phy_enable_10g_1g(sds_num); - - // Disable MAC - sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL); - mdelay(20); - - // ----> dal_longan_sds_mode_set - pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode); - - // Configure link to MAC - rtl9300_serdes_mac_link_config(sds_num, true, true); // MAC Construct - - // Disable MAC - sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL); - mdelay(20); - - rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA); - - // Re-Enable MAC - sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL); - - rtl9300_force_sds_mode(sds_num, phy_mode); - - // Do RX calibration - do { - rtl9300_do_rx_calibration(sds_num, phy_mode); - calib_tries++; - mdelay(50); - } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3); - - if (calib_tries >= 3) - pr_err("%s CALIBTRATION FAILED\n", __func__); - - rtl9300_sds_tx_config(sds_num, phy_mode); - - // The clock needs only to be configured on the FPGA implementation - - return 0; -} - -void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v) -{ - int l = end_bit - start_bit + 1; - u32 data = v; - - if (l < 32) { - u32 mask = BIT(l) - 1; - - data = rtl930x_read_sds_phy(sds, page, reg); - data &= ~(mask << start_bit); - data |= (v & mask) << start_bit; - } - - rtl931x_write_sds_phy(sds, page, reg, data); -} - - -u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit) -{ - int l = end_bit - start_bit + 1; - u32 v = rtl931x_read_sds_phy(sds, page, reg); - - if (l >= 32) - return v; - - return (v >> start_bit) & (BIT(l) - 1); -} - -static void rtl931x_sds_rst(u32 sds) -{ - u32 o, v, o_mode; - int shift = ((sds & 0x3) << 3); - - // TODO: We need to lock this! - - o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); - v = o | BIT(sds); - sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); - - o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2)); - v = BIT(7) | 0x1F; - sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2)); - sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2)); - - sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); -} - -static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode) -{ - u32 i; - u32 xsg_sdsid_0, xsg_sdsid_1; - - switch (mode) { - case PHY_INTERFACE_MODE_NA: - break; - case PHY_INTERFACE_MODE_XGMII: - if (sds < 2) - xsg_sdsid_0 = sds; - else - xsg_sdsid_0 = (sds - 1) * 2; - xsg_sdsid_1 = xsg_sdsid_0 + 1; - - for (i = 0; i < 4; ++i) { - rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i); - rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0); - rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0); - } - - for (i = 0; i < 4; ++i) { - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i); - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0); - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0); - } - - rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0); - rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0); - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0); - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0); - break; - default: - break; - } - - return; -} - -static u32 rtl931x_get_analog_sds(u32 sds) -{ - u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 }; - - if (sds < 14) - return sds_map[sds]; - return sds; -} - -void rtl931x_sds_fiber_disable(u32 sds) -{ - u32 v = 0x3F; - u32 asds = rtl931x_get_analog_sds(sds); - - rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v); -} - -static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode) -{ - u32 val, asds = rtl931x_get_analog_sds(sds); - - /* clear symbol error count before changing mode */ - rtl931x_symerr_clear(sds, mode); - - val = 0x9F; - sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2)); - - switch (mode) { - case PHY_INTERFACE_MODE_SGMII: - val = 0x5; - break; - - case PHY_INTERFACE_MODE_1000BASEX: - /* serdes mode FIBER1G */ - val = 0x9; - break; - - case PHY_INTERFACE_MODE_10GBASER: - case PHY_INTERFACE_MODE_10GKR: - val = 0x35; - break; -/* case MII_10GR1000BX_AUTO: - val = 0x39; - break; */ - - - case PHY_INTERFACE_MODE_USXGMII: - val = 0x1B; - break; - default: - val = 0x25; - } - - pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val); - rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val); - - return; -} - -static int rtl931x_sds_cmu_page_get(phy_interface_t mode) -{ - switch (mode) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO - return 0x24; - case PHY_INTERFACE_MODE_HSGMII: - case PHY_INTERFACE_MODE_2500BASEX: // MII_2500Base_X: - return 0x28; -// case MII_HISGMII_5G: -// return 0x2a; - case PHY_INTERFACE_MODE_QSGMII: - return 0x2a; // Code also has 0x34 - case PHY_INTERFACE_MODE_XAUI: // MII_RXAUI_LITE: - return 0x2c; - case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII - case PHY_INTERFACE_MODE_10GKR: - case PHY_INTERFACE_MODE_10GBASER: // MII_10GR - return 0x2e; - default: - return -1; - } - return -1; -} - -static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype) -{ - int cmu_type = 0; // Clock Management Unit - u32 cmu_page = 0; - u32 frc_cmu_spd; - u32 evenSds; - u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum; - - switch (mode) { - case PHY_INTERFACE_MODE_NA: - case PHY_INTERFACE_MODE_10GKR: - case PHY_INTERFACE_MODE_XGMII: - case PHY_INTERFACE_MODE_10GBASER: - case PHY_INTERFACE_MODE_USXGMII: - return; - -/* case MII_10GR1000BX_AUTO: - if (chiptype) - rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0); - return; */ - - case PHY_INTERFACE_MODE_QSGMII: - cmu_type = 1; - frc_cmu_spd = 0; - break; - - case PHY_INTERFACE_MODE_HSGMII: - cmu_type = 1; - frc_cmu_spd = 1; - break; - - case PHY_INTERFACE_MODE_1000BASEX: - cmu_type = 1; - frc_cmu_spd = 0; - break; - -/* case MII_1000BX100BX_AUTO: - cmu_type = 1; - frc_cmu_spd = 0; - break; */ - - case PHY_INTERFACE_MODE_SGMII: - cmu_type = 1; - frc_cmu_spd = 0; - break; - - case PHY_INTERFACE_MODE_2500BASEX: - cmu_type = 1; - frc_cmu_spd = 1; - break; - - default: - pr_info("SerDes %d mode is invalid\n", asds); - return; - } - - if (cmu_type == 1) - cmu_page = rtl931x_sds_cmu_page_get(mode); - - lane = asds % 2; - - if (!lane) { - frc_lc_mode_bitnum = 4; - frc_lc_mode_val_bitnum = 5; - } else { - frc_lc_mode_bitnum = 6; - frc_lc_mode_val_bitnum = 7; - } - - evenSds = asds - lane; - - pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n", - __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds); - - if (cmu_type == 1) { - pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7)); - rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0); - pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7)); - if (chiptype) { - rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0); - } - - rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3); - rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1); - rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0); - rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1); - rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd); - } - - pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7)); - return; -} - -static void rtl931x_sds_rx_rst(u32 sds) -{ - u32 asds = rtl931x_get_analog_sds(sds); - - if (sds < 2) - return; - - rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740); - rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0); - rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010); - rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10); - - rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0); - rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000); - rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010); - rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30); - - mdelay(50); -} - -static void rtl931x_sds_disable(u32 sds) -{ - u32 v = 0x1f; - - v |= BIT(7); - sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4); -} - -static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode) -{ - u32 val; - - switch (mode) { - case PHY_INTERFACE_MODE_QSGMII: - val = 0x6; - break; - case PHY_INTERFACE_MODE_XGMII: - val = 0x10; // serdes mode XSGMII - break; - case PHY_INTERFACE_MODE_USXGMII: - case PHY_INTERFACE_MODE_2500BASEX: - val = 0xD; - break; - case PHY_INTERFACE_MODE_HSGMII: - val = 0x12; - break; - case PHY_INTERFACE_MODE_SGMII: - val = 0x2; - break; - default: - return; - } - - val |= (1 << 7); - - sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2)); -} - -static sds_config sds_config_10p3125g_type1[] = { - { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 }, - { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E }, - { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 }, - { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 }, - { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 }, - { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 }, - { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 }, - { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 }, - { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 }, - { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 }, - { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 }, - { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 }, - { 0x2F, 0x13, 0x0000 } -}; - -static sds_config sds_config_10p3125g_cmu_type1[] = { - { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 }, - { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 }, - { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 }, - { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 }, - { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B } -}; - -void rtl931x_sds_init(u32 sds, phy_interface_t mode) -{ - - u32 board_sds_tx_type1[] = { 0x1C3, 0x1C3, 0x1C3, 0x1A3, 0x1A3, - 0x1A3, 0x143, 0x143, 0x143, 0x143, 0x163, 0x163 - }; - - u32 board_sds_tx[] = { 0x1A00, 0x1A00, 0x200, 0x200, 0x200, - 0x200, 0x1A3, 0x1A3, 0x1A3, 0x1A3, 0x1E3, 0x1E3 - }; - - u32 board_sds_tx2[] = { 0xDC0, 0x1C0, 0x200, 0x180, 0x160, - 0x123, 0x123, 0x163, 0x1A3, 0x1A0, 0x1C3, 0x9C3 - }; - - u32 asds, dSds, ori, model_info, val; - int chiptype = 0; - - asds = rtl931x_get_analog_sds(sds); - - if (sds > 13) - return; - - pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode); - val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6); - - pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__, - rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds); - pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__, - rtl931x_read_sds_phy(asds, 0x24, 0x9), asds); - pr_info("%s: CMU mode %08X stored even SDS %d", __func__, - rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1); - pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2)); - pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7)); - pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7)); - pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7)); - pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe)); - pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe)); - - model_info = sw_r32(RTL93XX_MODEL_NAME_INFO); - if ((model_info >> 4) & 0x1) { - pr_info("detected chiptype 1\n"); - chiptype = 1; - } else { - pr_info("detected chiptype 0\n"); - } - - if (sds < 2) - dSds = sds; - else - dSds = (sds - 1) * 2; - - pr_info("%s: 2.5gbit %08X dsds %d", __func__, - rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds); - - pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR)); - ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); - val = ori | (1 << sds); - sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); - - switch (mode) { - case PHY_INTERFACE_MODE_NA: - break; - - case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII - - if (chiptype) { - u32 xsg_sdsid_1; - xsg_sdsid_1 = dSds + 1; - //fifo inv clk - rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf); - rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf); - - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf); - rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf); - - } - - rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1); - rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1); - break; - - case PHY_INTERFACE_MODE_USXGMII: // MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: - u32 i, evenSds; - u32 op_code = 0x6003; - - if (chiptype) { - rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1); - - for (i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) { - rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data); - } - - evenSds = asds - (asds % 2); - - for (i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) { - rtl931x_write_sds_phy(evenSds, - sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data); - } - - rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0); - } else { - - rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0); - rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1); - - rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E); - rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00); - rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00); - rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00); - rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00); - - rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F); - rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa); - - rtl931x_sds_rx_rst(sds); - - rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code); - rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480); - rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400); - } - break; - - case PHY_INTERFACE_MODE_10GBASER: // MII_10GR / MII_10GR1000BX_AUTO: - // configure 10GR fiber mode=1 - rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1); - - // init fiber_1g - rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0); - - rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1); - rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1); - rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0); - - // init auto - rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e); - rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8); - rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f); - break; - - case PHY_INTERFACE_MODE_HSGMII: - rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1); - break; - - case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER - rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0); - - rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1); - rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1); - rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0); - break; - - case PHY_INTERFACE_MODE_SGMII: - rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0); - break; - - case PHY_INTERFACE_MODE_2500BASEX: - rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1); - break; - - case PHY_INTERFACE_MODE_QSGMII: - default: - pr_info("%s: PHY mode %s not supported by SerDes %d\n", - __func__, phy_modes(mode), sds); - return; - } - - rtl931x_cmu_type_set(asds, mode, chiptype); - - if (sds >= 2 && sds <= 13) { - if (chiptype) - rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]); - else { - val = 0xa0000; - sw_w32(val, RTL931X_CHIP_INFO_ADDR); - val = sw_r32(RTL931X_CHIP_INFO_ADDR); - if (val & BIT(28)) // consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) - { - rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]); - } else { - rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]); - } - val = 0; - sw_w32(val, RTL931X_CHIP_INFO_ADDR); - } - } - - val = ori & ~BIT(sds); - sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR); - pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR)); - - if (mode == PHY_INTERFACE_MODE_XGMII || mode == PHY_INTERFACE_MODE_QSGMII - || mode == PHY_INTERFACE_MODE_HSGMII || mode == PHY_INTERFACE_MODE_SGMII - || mode == PHY_INTERFACE_MODE_USXGMII) { - if (mode == PHY_INTERFACE_MODE_XGMII) - rtl931x_sds_mii_mode_set(sds, mode); - else - rtl931x_sds_fiber_mode_set(sds, mode); - } -} - -int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode) -{ - u32 asds; - int page = rtl931x_sds_cmu_page_get(mode); - - sds -= (sds % 2); - sds = sds & ~1; - asds = rtl931x_get_analog_sds(sds); - page += 1; - - if (enable) { - rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0); - rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0); - } else { - rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0); - rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0); - } - - rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band); - - rtl931x_sds_rst(sds); - - return 0; -} - -int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode) -{ - int page = rtl931x_sds_cmu_page_get(mode); - u32 asds, band; - - sds -= (sds % 2); - asds = rtl931x_get_analog_sds(sds); - page += 1; - rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73); - - rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1); - band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3); - pr_info("%s band is: %d\n", __func__, band); - - return band; -} - - -int rtl931x_link_sts_get(u32 sds) -{ - u32 sts, sts1, latch_sts, latch_sts1; - if (0){ - u32 xsg_sdsid_0, xsg_sdsid_1; - - xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2; - xsg_sdsid_1 = xsg_sdsid_0 + 1; - - sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0); - sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0); - latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0); - latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0); - } else { - u32 asds, dsds; - - asds = rtl931x_get_analog_sds(sds); - sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12); - latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2); - - dsds = sds < 2 ? sds : (sds - 1) * 2; - latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2); - sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2); - } - - pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__, - sds, sts, sts1, latch_sts, latch_sts1); - return sts1; -} - -static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) -{ - struct phy_device *phydev = upstream; - - rtl8214fc_media_set(phydev, true); - - return 0; -} - -static void rtl8214fc_sfp_remove(void *upstream) -{ - struct phy_device *phydev = upstream; - - rtl8214fc_media_set(phydev, false); -} - -static const struct sfp_upstream_ops rtl8214fc_sfp_ops = { - .attach = phy_sfp_attach, - .detach = phy_sfp_detach, - .module_insert = rtl8214fc_sfp_insert, - .module_remove = rtl8214fc_sfp_remove, -}; - -static int rtl8214fc_phy_probe(struct phy_device *phydev) -{ - struct device *dev = &phydev->mdio.dev; - int addr = phydev->mdio.addr; - int ret = 0; - - /* 839x has internal SerDes */ - if (soc_info.id == 0x8393) - return -ENODEV; - - /* All base addresses of the PHYs start at multiples of 8 */ - devm_phy_package_join(dev, phydev, addr & (~7), - sizeof(struct rtl83xx_shared_private)); - - if (!(addr % 8)) { - struct rtl83xx_shared_private *shared = phydev->shared->priv; - shared->name = "RTL8214FC"; - /* Configuration must be done while patching still possible */ - ret = rtl8380_configure_rtl8214fc(phydev); - if (ret) - return ret; - } - - return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops); -} - -static int rtl8214c_phy_probe(struct phy_device *phydev) -{ - struct device *dev = &phydev->mdio.dev; - int addr = phydev->mdio.addr; - - /* All base addresses of the PHYs start at multiples of 8 */ - devm_phy_package_join(dev, phydev, addr & (~7), - sizeof(struct rtl83xx_shared_private)); - - if (!(addr % 8)) { - struct rtl83xx_shared_private *shared = phydev->shared->priv; - shared->name = "RTL8214C"; - /* Configuration must be done whil patching still possible */ - return rtl8380_configure_rtl8214c(phydev); - } - return 0; -} - -static int rtl8218b_ext_phy_probe(struct phy_device *phydev) -{ - struct device *dev = &phydev->mdio.dev; - int addr = phydev->mdio.addr; - - /* All base addresses of the PHYs start at multiples of 8 */ - devm_phy_package_join(dev, phydev, addr & (~7), - sizeof(struct rtl83xx_shared_private)); - - if (!(addr % 8)) { - struct rtl83xx_shared_private *shared = phydev->shared->priv; - shared->name = "RTL8218B (external)"; - if (soc_info.family == RTL8380_FAMILY_ID) { - /* Configuration must be done while patching still possible */ - return rtl8380_configure_ext_rtl8218b(phydev); - } - } - - return 0; -} - -static int rtl8218b_int_phy_probe(struct phy_device *phydev) -{ - struct device *dev = &phydev->mdio.dev; - int addr = phydev->mdio.addr; - - if (soc_info.family != RTL8380_FAMILY_ID) - return -ENODEV; - if (addr >= 24) - return -ENODEV; - - pr_debug("%s: id: %d\n", __func__, addr); - /* All base addresses of the PHYs start at multiples of 8 */ - devm_phy_package_join(dev, phydev, addr & (~7), - sizeof(struct rtl83xx_shared_private)); - - if (!(addr % 8)) { - struct rtl83xx_shared_private *shared = phydev->shared->priv; - shared->name = "RTL8218B (internal)"; - /* Configuration must be done while patching still possible */ - return rtl8380_configure_int_rtl8218b(phydev); - } - - return 0; -} - -static int rtl8218d_phy_probe(struct phy_device *phydev) -{ - struct device *dev = &phydev->mdio.dev; - int addr = phydev->mdio.addr; - - pr_debug("%s: id: %d\n", __func__, addr); - /* All base addresses of the PHYs start at multiples of 8 */ - devm_phy_package_join(dev, phydev, addr & (~7), - sizeof(struct rtl83xx_shared_private)); - - /* All base addresses of the PHYs start at multiples of 8 */ - if (!(addr % 8)) { - struct rtl83xx_shared_private *shared = phydev->shared->priv; - shared->name = "RTL8218D"; - /* Configuration must be done while patching still possible */ -// TODO: return configure_rtl8218d(phydev); - } - return 0; -} - -static int rtl838x_serdes_probe(struct phy_device *phydev) -{ - int addr = phydev->mdio.addr; - - if (soc_info.family != RTL8380_FAMILY_ID) - return -ENODEV; - if (addr < 24) - return -ENODEV; - - /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */ - if (soc_info.id == 0x8380) { - if (addr == 24) - return rtl8380_configure_serdes(phydev); - return 0; - } - return -ENODEV; -} - -static int rtl8393_serdes_probe(struct phy_device *phydev) -{ - int addr = phydev->mdio.addr; - - pr_info("%s: id: %d\n", __func__, addr); - if (soc_info.family != RTL8390_FAMILY_ID) - return -ENODEV; - - if (addr < 24) - return -ENODEV; - - return rtl8390_configure_serdes(phydev); -} - -static int rtl8390_serdes_probe(struct phy_device *phydev) -{ - int addr = phydev->mdio.addr; - - if (soc_info.family != RTL8390_FAMILY_ID) - return -ENODEV; - - if (addr < 24) - return -ENODEV; - - return rtl8390_configure_generic(phydev); -} - -static int rtl9300_serdes_probe(struct phy_device *phydev) -{ - if (soc_info.family != RTL9300_FAMILY_ID) - return -ENODEV; - - phydev_info(phydev, "Detected internal RTL9300 Serdes\n"); - - return rtl9300_configure_serdes(phydev); -} - -static struct phy_driver rtl83xx_phy_driver[] = { - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C), - .name = "Realtek RTL8214C", - .features = PHY_GBIT_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .match_phy_device = rtl8214c_match_phy_device, - .probe = rtl8214c_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC), - .name = "Realtek RTL8214FC", - .features = PHY_GBIT_FIBRE_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .match_phy_device = rtl8214fc_match_phy_device, - .probe = rtl8214fc_phy_probe, - .suspend = rtl8214fc_suspend, - .resume = rtl8214fc_resume, - .set_loopback = genphy_loopback, - .set_port = rtl8214fc_set_port, - .get_port = rtl8214fc_get_port, - .set_eee = rtl8214fc_set_eee, - .get_eee = rtl8214fc_get_eee, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E), - .name = "Realtek RTL8218B (external)", - .features = PHY_GBIT_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .match_phy_device = rtl8218b_ext_match_phy_device, - .probe = rtl8218b_ext_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - .set_eee = rtl8218b_set_eee, - .get_eee = rtl8218b_get_eee, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D), - .name = "REALTEK RTL8218D", - .features = PHY_GBIT_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .probe = rtl8218d_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - .set_eee = rtl8218d_set_eee, - .get_eee = rtl8218d_get_eee, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B), - .name = "REALTEK RTL8221B", - .features = PHY_GBIT_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - .read_page = rtl8226_read_page, - .write_page = rtl8226_write_page, - .read_status = rtl8226_read_status, - .config_aneg = rtl8226_config_aneg, - .set_eee = rtl8226_set_eee, - .get_eee = rtl8226_get_eee, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8226), - .name = "REALTEK RTL8226", - .features = PHY_GBIT_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - .read_page = rtl8226_read_page, - .write_page = rtl8226_write_page, - .read_status = rtl8226_read_status, - .config_aneg = rtl8226_config_aneg, - .set_eee = rtl8226_set_eee, - .get_eee = rtl8226_get_eee, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I), - .name = "Realtek RTL8218B (internal)", - .features = PHY_GBIT_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .probe = rtl8218b_int_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - .set_eee = rtl8218b_set_eee, - .get_eee = rtl8218b_get_eee, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I), - .name = "Realtek RTL8380 SERDES", - .features = PHY_GBIT_FIBRE_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .probe = rtl838x_serdes_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - .read_status = rtl8380_read_status, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I), - .name = "Realtek RTL8393 SERDES", - .features = PHY_GBIT_FIBRE_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .probe = rtl8393_serdes_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - .read_status = rtl8393_read_status, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC), - .name = "Realtek RTL8390 Generic", - .features = PHY_GBIT_FIBRE_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .probe = rtl8390_serdes_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - }, - { - PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I), - .name = "REALTEK RTL9300 SERDES", - .features = PHY_GBIT_FIBRE_FEATURES, - .flags = PHY_HAS_REALTEK_PAGES, - .probe = rtl9300_serdes_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .set_loopback = genphy_loopback, - .read_status = rtl9300_read_status, - }, -}; - -module_phy_driver(rtl83xx_phy_driver); - -static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = { - { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) }, - { } -}; - -MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl); - -MODULE_AUTHOR("B. Koblitz"); -MODULE_DESCRIPTION("RTL83xx PHY driver"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.h b/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.h deleted file mode 100644 index 553d9a1575..0000000000 --- a/target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.h +++ /dev/null @@ -1,68 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -struct rtl83xx_shared_private { - char *name; -}; - -struct __attribute__ ((__packed__)) part { - uint16_t start; - uint8_t wordsize; - uint8_t words; -}; - -struct __attribute__ ((__packed__)) fw_header { - uint32_t magic; - uint32_t phy; - uint32_t checksum; - uint32_t version; - struct part parts[10]; -}; - -// TODO: fixed path? -#define FIRMWARE_838X_8380_1 "rtl838x_phy/rtl838x_8380.fw" -#define FIRMWARE_838X_8214FC_1 "rtl838x_phy/rtl838x_8214fc.fw" -#define FIRMWARE_838X_8218b_1 "rtl838x_phy/rtl838x_8218b.fw" - -/* External RTL8218B and RTL8214FC IDs are identical */ -#define PHY_ID_RTL8214C 0x001cc942 -#define PHY_ID_RTL8214FC 0x001cc981 -#define PHY_ID_RTL8218B_E 0x001cc981 -#define PHY_ID_RTL8218D 0x001cc983 -#define PHY_ID_RTL8218B_I 0x001cca40 -#define PHY_ID_RTL8221B 0x001cc849 -#define PHY_ID_RTL8226 0x001cc838 -#define PHY_ID_RTL8390_GENERIC 0x001ccab0 -#define PHY_ID_RTL8393_I 0x001c8393 -#define PHY_ID_RTL9300_I 0x70d03106 - -// PHY MMD devices -#define MMD_AN 7 -#define MMD_VEND2 31 - -/* Registers of the internal Serdes of the 8380 */ -#define RTL838X_SDS_MODE_SEL (0x0028) -#define RTL838X_SDS_CFG_REG (0x0034) -#define RTL838X_INT_MODE_CTRL (0x005c) -#define RTL838X_DMY_REG31 (0x3b28) - -#define RTL8380_SDS4_FIB_REG0 (0xF800) -#define RTL838X_SDS4_REG28 (0xef80) -#define RTL838X_SDS4_DUMMY0 (0xef8c) -#define RTL838X_SDS5_EXT_REG6 (0xf18c) -#define RTL838X_SDS4_FIB_REG0 (RTL838X_SDS4_REG28 + 0x880) -#define RTL838X_SDS5_FIB_REG0 (RTL838X_SDS4_REG28 + 0x980) - -/* Registers of the internal SerDes of the RTL8390 */ -#define RTL839X_SDS12_13_XSG0 (0xB800) - -/* Registers of the internal Serdes of the 9300 */ -#define RTL930X_SDS_INDACS_CMD (0x03B0) -#define RTL930X_SDS_INDACS_DATA (0x03B4) -#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C) - -/*Registers of the internal SerDes of the 9310 */ -#define RTL931X_SERDES_INDRT_ACCESS_CTRL (0x5638) -#define RTL931X_SERDES_INDRT_DATA_CTRL (0x563C) -#define RTL931X_SERDES_MODE_CTRL (0x13cc) -#define RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR (0x13F4) -#define RTL931X_MAC_SERDES_MODE_CTRL(sds) (0x136C + (((sds) << 2))) diff --git a/target/linux/realtek/files-5.10/include/dt-bindings/clock/rtl83xx-clk.h b/target/linux/realtek/files-5.10/include/dt-bindings/clock/rtl83xx-clk.h deleted file mode 100644 index 3937052cc5..0000000000 --- a/target/linux/realtek/files-5.10/include/dt-bindings/clock/rtl83xx-clk.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2022 Markus Stockhausen - * - * RTL83XX clock indices - */ -#ifndef __DT_BINDINGS_CLOCK_RTL83XX_H -#define __DT_BINDINGS_CLOCK_RTL83XX_H - -#define CLK_CPU 0 -#define CLK_MEM 1 -#define CLK_LXB 2 -#define CLK_COUNT 3 - -#endif /* __DT_BINDINGS_CLOCK_RTL83XX_H */ diff --git a/target/linux/realtek/patches-5.10/001-5.13-dt-bindings-gpio-binding-for-realtek-otto-gpio.patch b/target/linux/realtek/patches-5.10/001-5.13-dt-bindings-gpio-binding-for-realtek-otto-gpio.patch deleted file mode 100644 index 80b806d89f..0000000000 --- a/target/linux/realtek/patches-5.10/001-5.13-dt-bindings-gpio-binding-for-realtek-otto-gpio.patch +++ /dev/null @@ -1,103 +0,0 @@ -From a362c0ce64866939c3daa17c76943cfed555b065 Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Tue, 30 Mar 2021 19:48:42 +0200 -Subject: dt-bindings: gpio: Binding for Realtek Otto GPIO - -Add a binding description for Realtek's GPIO controller found on several -of their MIPS-based SoCs (codenamed Otto), such as the RTL838x and -RTL839x series of switch SoCs. - -A fallback binding 'realtek,otto-gpio' is provided for cases where the -actual port ordering is not known yet, and enabling the interrupt -controller may result in uncaught interrupts. - -Signed-off-by: Sander Vanheule -Reviewed-by: Linus Walleij -Reviewed-by: Rob Herring -Signed-off-by: Bartosz Golaszewski ---- - .../bindings/gpio/realtek,otto-gpio.yaml | 78 ++++++++++++++++++++++ - 1 file changed, 78 insertions(+) - create mode 100644 Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml -@@ -0,0 +1,78 @@ -+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Realtek Otto GPIO controller -+ -+maintainers: -+ - Sander Vanheule -+ - Bert Vermeulen -+ -+description: | -+ Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists -+ of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts. -+ Each bank's interrupts are cascased into one interrupt line on the parent -+ interrupt controller, if provided. -+ This binding allows defining a single bank in the devicetree. The interrupt -+ controller is not supported on the fallback compatible name, which only -+ allows for GPIO port use. -+ -+properties: -+ $nodename: -+ pattern: "^gpio@[0-9a-f]+$" -+ -+ compatible: -+ items: -+ - enum: -+ - realtek,rtl8380-gpio -+ - realtek,rtl8390-gpio -+ - const: realtek,otto-gpio -+ -+ reg: -+ maxItems: 1 -+ -+ "#gpio-cells": -+ const: 2 -+ -+ gpio-controller: true -+ -+ ngpios: -+ minimum: 1 -+ maximum: 32 -+ -+ interrupt-controller: true -+ -+ "#interrupt-cells": -+ const: 2 -+ -+ interrupts: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ - "#gpio-cells" -+ - gpio-controller -+ -+additionalProperties: false -+ -+dependencies: -+ interrupt-controller: [ interrupts ] -+ -+examples: -+ - | -+ gpio@3500 { -+ compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio"; -+ reg = <0x3500 0x1c>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ ngpios = <24>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ interrupt-parent = <&rtlintc>; -+ interrupts = <23>; -+ }; -+ -+... diff --git a/target/linux/realtek/patches-5.10/002-5.13-gpio-add-realtek-otto-gpio-support.patch b/target/linux/realtek/patches-5.10/002-5.13-gpio-add-realtek-otto-gpio-support.patch deleted file mode 100644 index 62e4338cbb..0000000000 --- a/target/linux/realtek/patches-5.10/002-5.13-gpio-add-realtek-otto-gpio-support.patch +++ /dev/null @@ -1,394 +0,0 @@ -From f0f7d662e8514169c90d3d84cd6df773b2983088 Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Tue, 30 Mar 2021 19:48:43 +0200 -Subject: gpio: Add Realtek Otto GPIO support - -Realtek MIPS SoCs (platform name Otto) have GPIO controllers with up to -64 GPIOs, divided over two banks. Each bank has a set of registers for -32 GPIOs, with support for edge-triggered interrupts. - -Each GPIO bank consists of four 8-bit GPIO ports (ABCD and EFGH). Most -registers pack one bit per GPIO, except for the IMR register, which -packs two bits per GPIO (AB-CD). - -Although the byte order is currently assumed to have port A..D at offset -0x0..0x3, this has been observed to be reversed on other, Lexra-based, -SoCs (e.g. RTL8196E/97D/97F). - -Interrupt support is disabled for the fallback devicetree-compatible -'realtek,otto-gpio'. This allows for quick support of GPIO banks in -which the byte order would be unknown. In this case, the port ordering -in the IMR registers may not match the reversed order in the other -registers (DCBA, and BA-DC or DC-BA). - -Signed-off-by: Sander Vanheule -Reviewed-by: Linus Walleij -Reviewed-by: Andy Shevchenko -Signed-off-by: Bartosz Golaszewski ---- - drivers/gpio/Kconfig | 13 ++ - drivers/gpio/Makefile | 1 + - drivers/gpio/gpio-realtek-otto.c | 325 +++++++++++++++++++++++++++++++++++++++ - 3 files changed, 339 insertions(+) - create mode 100644 drivers/gpio/gpio-realtek-otto.c - ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -489,6 +489,19 @@ config GPIO_RDA - help - Say Y here to support RDA Micro GPIO controller. - -+config GPIO_REALTEK_OTTO -+ tristate "Realtek Otto GPIO support" -+ depends on MACH_REALTEK_RTL -+ default MACH_REALTEK_RTL -+ select GPIO_GENERIC -+ select GPIOLIB_IRQCHIP -+ help -+ The GPIO controller on the Otto MIPS platform supports up to two -+ banks of 32 GPIOs, with edge triggered interrupts. The 32 GPIOs -+ are grouped in four 8-bit wide ports. -+ -+ When built as a module, the module will be called realtek_otto_gpio. -+ - config GPIO_REG - bool - help ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -125,6 +125,7 @@ obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t - obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o - obj-$(CONFIG_GPIO_RDA) += gpio-rda.o - obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o -+obj-$(CONFIG_GPIO_REALTEK_OTTO) += gpio-realtek-otto.o - obj-$(CONFIG_GPIO_REG) += gpio-reg.o - obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o - obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o ---- /dev/null -+++ b/drivers/gpio/gpio-realtek-otto.c -@@ -0,0 +1,325 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * Total register block size is 0x1C for one bank of four ports (A, B, C, D). -+ * An optional second bank, with ports E, F, G, and H, may be present, starting -+ * at register offset 0x1C. -+ */ -+ -+/* -+ * Pin select: (0) "normal", (1) "dedicate peripheral" -+ * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits -+ * in the peripheral registers. -+ */ -+#define REALTEK_GPIO_REG_CNR 0x00 -+/* Clear bit (0) for input, set bit (1) for output */ -+#define REALTEK_GPIO_REG_DIR 0x08 -+#define REALTEK_GPIO_REG_DATA 0x0C -+/* Read bit for IRQ status, write 1 to clear IRQ */ -+#define REALTEK_GPIO_REG_ISR 0x10 -+/* Two bits per GPIO in IMR registers */ -+#define REALTEK_GPIO_REG_IMR 0x14 -+#define REALTEK_GPIO_REG_IMR_AB 0x14 -+#define REALTEK_GPIO_REG_IMR_CD 0x18 -+#define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0) -+#define REALTEK_GPIO_IRQ_EDGE_FALLING 1 -+#define REALTEK_GPIO_IRQ_EDGE_RISING 2 -+#define REALTEK_GPIO_IRQ_EDGE_BOTH 3 -+ -+#define REALTEK_GPIO_MAX 32 -+#define REALTEK_GPIO_PORTS_PER_BANK 4 -+ -+/** -+ * realtek_gpio_ctrl - Realtek Otto GPIO driver data -+ * -+ * @gc: Associated gpio_chip instance -+ * @base: Base address of the register block for a GPIO bank -+ * @lock: Lock for accessing the IRQ registers and values -+ * @intr_mask: Mask for interrupts lines -+ * @intr_type: Interrupt type selection -+ * -+ * Because the interrupt mask register (IMR) combines the function of IRQ type -+ * selection and masking, two extra values are stored. @intr_mask is used to -+ * mask/unmask the interrupts for a GPIO port, and @intr_type is used to store -+ * the selected interrupt types. The logical AND of these values is written to -+ * IMR on changes. -+ */ -+struct realtek_gpio_ctrl { -+ struct gpio_chip gc; -+ void __iomem *base; -+ raw_spinlock_t lock; -+ u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; -+ u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; -+}; -+ -+/* Expand with more flags as devices with other quirks are added */ -+enum realtek_gpio_flags { -+ /* -+ * Allow disabling interrupts, for cases where the port order is -+ * unknown. This may result in a port mismatch between ISR and IMR. -+ * An interrupt would appear to come from a different line than the -+ * line the IRQ handler was assigned to, causing uncaught interrupts. -+ */ -+ GPIO_INTERRUPTS_DISABLED = BIT(0), -+}; -+ -+static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) -+{ -+ struct gpio_chip *gc = irq_data_get_irq_chip_data(data); -+ -+ return container_of(gc, struct realtek_gpio_ctrl, gc); -+} -+ -+/* -+ * Normal port order register access -+ * -+ * Port information is stored with the first port at offset 0, followed by the -+ * second, etc. Most registers store one bit per GPIO and use a u8 value per -+ * port. The two interrupt mask registers store two bits per GPIO, so use u16 -+ * values. -+ */ -+static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl, -+ unsigned int port, u16 irq_type, u16 irq_mask) -+{ -+ iowrite16(irq_type & irq_mask, ctrl->base + REALTEK_GPIO_REG_IMR + 2 * port); -+} -+ -+static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, -+ unsigned int port, u8 mask) -+{ -+ iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + port); -+} -+ -+static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port) -+{ -+ return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + port); -+} -+ -+/* Set the rising and falling edge mask bits for a GPIO port pin */ -+static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value) -+{ -+ return (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin; -+} -+ -+static void realtek_gpio_irq_ack(struct irq_data *data) -+{ -+ struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); -+ irq_hw_number_t line = irqd_to_hwirq(data); -+ unsigned int port = line / 8; -+ unsigned int port_pin = line % 8; -+ -+ realtek_gpio_clear_isr(ctrl, port, BIT(port_pin)); -+} -+ -+static void realtek_gpio_irq_unmask(struct irq_data *data) -+{ -+ struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); -+ unsigned int line = irqd_to_hwirq(data); -+ unsigned int port = line / 8; -+ unsigned int port_pin = line % 8; -+ unsigned long flags; -+ u16 m; -+ -+ raw_spin_lock_irqsave(&ctrl->lock, flags); -+ m = ctrl->intr_mask[port]; -+ m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); -+ ctrl->intr_mask[port] = m; -+ realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); -+ raw_spin_unlock_irqrestore(&ctrl->lock, flags); -+} -+ -+static void realtek_gpio_irq_mask(struct irq_data *data) -+{ -+ struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); -+ unsigned int line = irqd_to_hwirq(data); -+ unsigned int port = line / 8; -+ unsigned int port_pin = line % 8; -+ unsigned long flags; -+ u16 m; -+ -+ raw_spin_lock_irqsave(&ctrl->lock, flags); -+ m = ctrl->intr_mask[port]; -+ m &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); -+ ctrl->intr_mask[port] = m; -+ realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); -+ raw_spin_unlock_irqrestore(&ctrl->lock, flags); -+} -+ -+static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) -+{ -+ struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); -+ unsigned int line = irqd_to_hwirq(data); -+ unsigned int port = line / 8; -+ unsigned int port_pin = line % 8; -+ unsigned long flags; -+ u16 type, t; -+ -+ switch (flow_type & IRQ_TYPE_SENSE_MASK) { -+ case IRQ_TYPE_EDGE_FALLING: -+ type = REALTEK_GPIO_IRQ_EDGE_FALLING; -+ break; -+ case IRQ_TYPE_EDGE_RISING: -+ type = REALTEK_GPIO_IRQ_EDGE_RISING; -+ break; -+ case IRQ_TYPE_EDGE_BOTH: -+ type = REALTEK_GPIO_IRQ_EDGE_BOTH; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ irq_set_handler_locked(data, handle_edge_irq); -+ -+ raw_spin_lock_irqsave(&ctrl->lock, flags); -+ t = ctrl->intr_type[port]; -+ t &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); -+ t |= realtek_gpio_imr_bits(port_pin, type); -+ ctrl->intr_type[port] = t; -+ realtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]); -+ raw_spin_unlock_irqrestore(&ctrl->lock, flags); -+ -+ return 0; -+} -+ -+static void realtek_gpio_irq_handler(struct irq_desc *desc) -+{ -+ struct gpio_chip *gc = irq_desc_get_handler_data(desc); -+ struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); -+ struct irq_chip *irq_chip = irq_desc_get_chip(desc); -+ unsigned int lines_done; -+ unsigned int port_pin_count; -+ unsigned int irq; -+ unsigned long status; -+ int offset; -+ -+ chained_irq_enter(irq_chip, desc); -+ -+ for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) { -+ status = realtek_gpio_read_isr(ctrl, lines_done / 8); -+ port_pin_count = min(gc->ngpio - lines_done, 8U); -+ for_each_set_bit(offset, &status, port_pin_count) { -+ irq = irq_find_mapping(gc->irq.domain, offset); -+ generic_handle_irq(irq); -+ } -+ } -+ -+ chained_irq_exit(irq_chip, desc); -+} -+ -+static int realtek_gpio_irq_init(struct gpio_chip *gc) -+{ -+ struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); -+ unsigned int port; -+ -+ for (port = 0; (port * 8) < gc->ngpio; port++) { -+ realtek_gpio_write_imr(ctrl, port, 0, 0); -+ realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0)); -+ } -+ -+ return 0; -+} -+ -+static struct irq_chip realtek_gpio_irq_chip = { -+ .name = "realtek-otto-gpio", -+ .irq_ack = realtek_gpio_irq_ack, -+ .irq_mask = realtek_gpio_irq_mask, -+ .irq_unmask = realtek_gpio_irq_unmask, -+ .irq_set_type = realtek_gpio_irq_set_type, -+}; -+ -+static const struct of_device_id realtek_gpio_of_match[] = { -+ { -+ .compatible = "realtek,otto-gpio", -+ .data = (void *)GPIO_INTERRUPTS_DISABLED, -+ }, -+ { -+ .compatible = "realtek,rtl8380-gpio", -+ }, -+ { -+ .compatible = "realtek,rtl8390-gpio", -+ }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); -+ -+static int realtek_gpio_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ unsigned int dev_flags; -+ struct gpio_irq_chip *girq; -+ struct realtek_gpio_ctrl *ctrl; -+ u32 ngpios; -+ int err, irq; -+ -+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); -+ if (!ctrl) -+ return -ENOMEM; -+ -+ dev_flags = (unsigned int) device_get_match_data(dev); -+ -+ ngpios = REALTEK_GPIO_MAX; -+ device_property_read_u32(dev, "ngpios", &ngpios); -+ -+ if (ngpios > REALTEK_GPIO_MAX) { -+ dev_err(&pdev->dev, "invalid ngpios (max. %d)\n", -+ REALTEK_GPIO_MAX); -+ return -EINVAL; -+ } -+ -+ ctrl->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ctrl->base)) -+ return PTR_ERR(ctrl->base); -+ -+ raw_spin_lock_init(&ctrl->lock); -+ -+ err = bgpio_init(&ctrl->gc, dev, 4, -+ ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL, -+ ctrl->base + REALTEK_GPIO_REG_DIR, NULL, -+ BGPIOF_BIG_ENDIAN_BYTE_ORDER); -+ if (err) { -+ dev_err(dev, "unable to init generic GPIO"); -+ return err; -+ } -+ -+ ctrl->gc.ngpio = ngpios; -+ ctrl->gc.owner = THIS_MODULE; -+ -+ irq = platform_get_irq_optional(pdev, 0); -+ if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) { -+ girq = &ctrl->gc.irq; -+ girq->chip = &realtek_gpio_irq_chip; -+ girq->default_type = IRQ_TYPE_NONE; -+ girq->handler = handle_bad_irq; -+ girq->parent_handler = realtek_gpio_irq_handler; -+ girq->num_parents = 1; -+ girq->parents = devm_kcalloc(dev, girq->num_parents, -+ sizeof(*girq->parents), GFP_KERNEL); -+ if (!girq->parents) -+ return -ENOMEM; -+ girq->parents[0] = irq; -+ girq->init_hw = realtek_gpio_irq_init; -+ } -+ -+ return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); -+} -+ -+static struct platform_driver realtek_gpio_driver = { -+ .driver = { -+ .name = "realtek-otto-gpio", -+ .of_match_table = realtek_gpio_of_match, -+ }, -+ .probe = realtek_gpio_probe, -+}; -+module_platform_driver(realtek_gpio_driver); -+ -+MODULE_DESCRIPTION("Realtek Otto GPIO support"); -+MODULE_AUTHOR("Sander Vanheule "); -+MODULE_LICENSE("GPL v2"); diff --git a/target/linux/realtek/patches-5.10/003-5.12-spi-realtek-rtl838x-rtl839x-spi-controller.patch b/target/linux/realtek/patches-5.10/003-5.12-spi-realtek-rtl838x-rtl839x-spi-controller.patch deleted file mode 100644 index 325e904994..0000000000 --- a/target/linux/realtek/patches-5.10/003-5.12-spi-realtek-rtl838x-rtl839x-spi-controller.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 6acbd614c2c8d3b8de5fb7605d6e24b9b3a8a17b Mon Sep 17 00:00:00 2001 -From: Bert Vermeulen -Date: Wed, 20 Jan 2021 14:59:27 +0100 -Subject: spi: Realtek RTL838x/RTL839x SPI controller - -Signed-off-by: Bert Vermeulen -Link: https://lore.kernel.org/r/20210120135928.246054-2-bert@biot.com -Signed-off-by: Mark Brown ---- - .../devicetree/bindings/spi/realtek,rtl-spi.yaml | 41 ++++++++++++++++++++++ - 1 file changed, 41 insertions(+) - create mode 100644 Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml -@@ -0,0 +1,41 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/spi/realtek,rtl-spi.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Realtek RTL838x/RTL839x SPI controller -+ -+maintainers: -+ - Bert Vermeulen -+ - Birger Koblitz -+ -+allOf: -+ - $ref: "spi-controller.yaml#" -+ -+properties: -+ compatible: -+ oneOf: -+ - const: realtek,rtl8380-spi -+ - const: realtek,rtl8382-spi -+ - const: realtek,rtl8391-spi -+ - const: realtek,rtl8392-spi -+ - const: realtek,rtl8393-spi -+ -+ reg: -+ maxItems: 1 -+ -+required: -+ - compatible -+ - reg -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ spi: spi@1200 { -+ compatible = "realtek,rtl8382-spi"; -+ reg = <0x1200 0x100>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; diff --git a/target/linux/realtek/patches-5.10/004-5.12-spi-realtek-rtl-add-support-for-realtek-rtl838x-rtl839x-spi-controllers.patch b/target/linux/realtek/patches-5.10/004-5.12-spi-realtek-rtl-add-support-for-realtek-rtl838x-rtl839x-spi-controllers.patch deleted file mode 100644 index 090847baad..0000000000 --- a/target/linux/realtek/patches-5.10/004-5.12-spi-realtek-rtl-add-support-for-realtek-rtl838x-rtl839x-spi-controllers.patch +++ /dev/null @@ -1,248 +0,0 @@ -From a8af5cc2ff1e804694629a8ef320935629dd15ba Mon Sep 17 00:00:00 2001 -From: Bert Vermeulen -Date: Wed, 20 Jan 2021 14:59:28 +0100 -Subject: spi: realtek-rtl: Add support for Realtek RTL838x/RTL839x SPI - controllers - -This driver likely also supports earlier (RTL8196) and later (RTL93xx) -SoCs. - -The SPI hardware in these SoCs is specifically intended for connecting NOR -bootflash chips, and only used for that in dozens of examined devices. -However boiled down to basics, it's really just a half-duplex SPI -controller. - -The hardware appears to have a vestigial second chip-select control, but -it hasn't been seen in the wild and is thus not supported. - -Signed-off-by: Bert Vermeulen -Link: https://lore.kernel.org/r/20210120135928.246054-3-bert@biot.com -Signed-off-by: Mark Brown ---- - drivers/spi/Makefile | 1 + - drivers/spi/spi-realtek-rtl.c | 209 ++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 210 insertions(+) - create mode 100644 drivers/spi/spi-realtek-rtl.c - ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -94,6 +94,7 @@ obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom - obj-$(CONFIG_SPI_QUP) += spi-qup.o - obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o - obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o -+obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o - obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o - obj-$(CONFIG_SPI_RSPI) += spi-rspi.o - obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o ---- /dev/null -+++ b/drivers/spi/spi-realtek-rtl.c -@@ -0,0 +1,209 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+#include -+#include -+#include -+#include -+ -+struct rtspi { -+ void __iomem *base; -+}; -+ -+/* SPI Flash Configuration Register */ -+#define RTL_SPI_SFCR 0x00 -+#define RTL_SPI_SFCR_RBO BIT(28) -+#define RTL_SPI_SFCR_WBO BIT(27) -+ -+/* SPI Flash Control and Status Register */ -+#define RTL_SPI_SFCSR 0x08 -+#define RTL_SPI_SFCSR_CSB0 BIT(31) -+#define RTL_SPI_SFCSR_CSB1 BIT(30) -+#define RTL_SPI_SFCSR_RDY BIT(27) -+#define RTL_SPI_SFCSR_CS BIT(24) -+#define RTL_SPI_SFCSR_LEN_MASK ~(0x03 << 28) -+#define RTL_SPI_SFCSR_LEN1 (0x00 << 28) -+#define RTL_SPI_SFCSR_LEN4 (0x03 << 28) -+ -+/* SPI Flash Data Register */ -+#define RTL_SPI_SFDR 0x0c -+ -+#define REG(x) (rtspi->base + x) -+ -+ -+static void rt_set_cs(struct spi_device *spi, bool active) -+{ -+ struct rtspi *rtspi = spi_controller_get_devdata(spi->controller); -+ u32 value; -+ -+ /* CS0 bit is active low */ -+ value = readl(REG(RTL_SPI_SFCSR)); -+ if (active) -+ value |= RTL_SPI_SFCSR_CSB0; -+ else -+ value &= ~RTL_SPI_SFCSR_CSB0; -+ writel(value, REG(RTL_SPI_SFCSR)); -+} -+ -+static void set_size(struct rtspi *rtspi, int size) -+{ -+ u32 value; -+ -+ value = readl(REG(RTL_SPI_SFCSR)); -+ value &= RTL_SPI_SFCSR_LEN_MASK; -+ if (size == 4) -+ value |= RTL_SPI_SFCSR_LEN4; -+ else if (size == 1) -+ value |= RTL_SPI_SFCSR_LEN1; -+ writel(value, REG(RTL_SPI_SFCSR)); -+} -+ -+static inline void wait_ready(struct rtspi *rtspi) -+{ -+ while (!(readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY)) -+ cpu_relax(); -+} -+static void send4(struct rtspi *rtspi, const u32 *buf) -+{ -+ wait_ready(rtspi); -+ set_size(rtspi, 4); -+ writel(*buf, REG(RTL_SPI_SFDR)); -+} -+ -+static void send1(struct rtspi *rtspi, const u8 *buf) -+{ -+ wait_ready(rtspi); -+ set_size(rtspi, 1); -+ writel(buf[0] << 24, REG(RTL_SPI_SFDR)); -+} -+ -+static void rcv4(struct rtspi *rtspi, u32 *buf) -+{ -+ wait_ready(rtspi); -+ set_size(rtspi, 4); -+ *buf = readl(REG(RTL_SPI_SFDR)); -+} -+ -+static void rcv1(struct rtspi *rtspi, u8 *buf) -+{ -+ wait_ready(rtspi); -+ set_size(rtspi, 1); -+ *buf = readl(REG(RTL_SPI_SFDR)) >> 24; -+} -+ -+static int transfer_one(struct spi_controller *ctrl, struct spi_device *spi, -+ struct spi_transfer *xfer) -+{ -+ struct rtspi *rtspi = spi_controller_get_devdata(ctrl); -+ void *rx_buf; -+ const void *tx_buf; -+ int cnt; -+ -+ tx_buf = xfer->tx_buf; -+ rx_buf = xfer->rx_buf; -+ cnt = xfer->len; -+ if (tx_buf) { -+ while (cnt >= 4) { -+ send4(rtspi, tx_buf); -+ tx_buf += 4; -+ cnt -= 4; -+ } -+ while (cnt) { -+ send1(rtspi, tx_buf); -+ tx_buf++; -+ cnt--; -+ } -+ } else if (rx_buf) { -+ while (cnt >= 4) { -+ rcv4(rtspi, rx_buf); -+ rx_buf += 4; -+ cnt -= 4; -+ } -+ while (cnt) { -+ rcv1(rtspi, rx_buf); -+ rx_buf++; -+ cnt--; -+ } -+ } -+ -+ spi_finalize_current_transfer(ctrl); -+ -+ return 0; -+} -+ -+static void init_hw(struct rtspi *rtspi) -+{ -+ u32 value; -+ -+ /* Turn on big-endian byte ordering */ -+ value = readl(REG(RTL_SPI_SFCR)); -+ value |= RTL_SPI_SFCR_RBO | RTL_SPI_SFCR_WBO; -+ writel(value, REG(RTL_SPI_SFCR)); -+ -+ value = readl(REG(RTL_SPI_SFCSR)); -+ /* Permanently disable CS1, since it's never used */ -+ value |= RTL_SPI_SFCSR_CSB1; -+ /* Select CS0 for use */ -+ value &= RTL_SPI_SFCSR_CS; -+ writel(value, REG(RTL_SPI_SFCSR)); -+} -+ -+static int realtek_rtl_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_controller *ctrl; -+ struct rtspi *rtspi; -+ int err; -+ -+ ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*rtspi)); -+ if (!ctrl) { -+ dev_err(&pdev->dev, "Error allocating SPI controller\n"); -+ return -ENOMEM; -+ } -+ platform_set_drvdata(pdev, ctrl); -+ rtspi = spi_controller_get_devdata(ctrl); -+ -+ rtspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); -+ if (IS_ERR(rtspi->base)) { -+ dev_err(&pdev->dev, "Could not map SPI register address"); -+ return -ENOMEM; -+ } -+ -+ init_hw(rtspi); -+ -+ ctrl->dev.of_node = pdev->dev.of_node; -+ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX; -+ ctrl->set_cs = rt_set_cs; -+ ctrl->transfer_one = transfer_one; -+ -+ err = devm_spi_register_controller(&pdev->dev, ctrl); -+ if (err) { -+ dev_err(&pdev->dev, "Could not register SPI controller\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+ -+static const struct of_device_id realtek_rtl_spi_of_ids[] = { -+ { .compatible = "realtek,rtl8380-spi" }, -+ { .compatible = "realtek,rtl8382-spi" }, -+ { .compatible = "realtek,rtl8391-spi" }, -+ { .compatible = "realtek,rtl8392-spi" }, -+ { .compatible = "realtek,rtl8393-spi" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, realtek_rtl_spi_of_ids); -+ -+static struct platform_driver realtek_rtl_spi_driver = { -+ .probe = realtek_rtl_spi_probe, -+ .driver = { -+ .name = "realtek-rtl-spi", -+ .of_match_table = realtek_rtl_spi_of_ids, -+ }, -+}; -+ -+module_platform_driver(realtek_rtl_spi_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Bert Vermeulen "); -+MODULE_DESCRIPTION("Realtek RTL SPI driver"); diff --git a/target/linux/realtek/patches-5.10/005-5.12-dt-bindings-interrupt-controller-add-realtek-rtl838x-rtl839x-support.patch b/target/linux/realtek/patches-5.10/005-5.12-dt-bindings-interrupt-controller-add-realtek-rtl838x-rtl839x-support.patch deleted file mode 100644 index 165545a220..0000000000 --- a/target/linux/realtek/patches-5.10/005-5.12-dt-bindings-interrupt-controller-add-realtek-rtl838x-rtl839x-support.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 4a2b92a5d3519fc2c1edda4d4aa0e05bff41e8de Mon Sep 17 00:00:00 2001 -From: Bert Vermeulen -Date: Fri, 22 Jan 2021 21:42:23 +0100 -Subject: dt-bindings: interrupt-controller: Add Realtek RTL838x/RTL839x - support - -Document the binding for the Realtek RTL838x/RTL839x interrupt controller. - -Reviewed-by: Rob Herring -Signed-off-by: Bert Vermeulen -[maz: Add a commit message, as the author couldn't be bothered...] -Signed-off-by: Marc Zyngier -Link: https://lore.kernel.org/r/20210122204224.509124-2-bert@biot.com ---- - .../interrupt-controller/realtek,rtl-intc.yaml | 57 ++++++++++++++++++++++ - 1 file changed, 57 insertions(+) - create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml - ---- /dev/null -+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml -@@ -0,0 +1,57 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Realtek RTL SoC interrupt controller devicetree bindings -+ -+maintainers: -+ - Birger Koblitz -+ - Bert Vermeulen -+ - John Crispin -+ -+properties: -+ compatible: -+ const: realtek,rtl-intc -+ -+ "#interrupt-cells": -+ const: 1 -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-controller: true -+ -+ "#address-cells": -+ const: 0 -+ -+ interrupt-map: -+ description: Describes mapping from SoC interrupts to CPU interrupts -+ -+required: -+ - compatible -+ - reg -+ - "#interrupt-cells" -+ - interrupt-controller -+ - "#address-cells" -+ - interrupt-map -+ -+additionalProperties: false -+ -+examples: -+ - | -+ intc: interrupt-controller@3000 { -+ compatible = "realtek,rtl-intc"; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ reg = <0x3000 0x20>; -+ #address-cells = <0>; -+ interrupt-map = -+ <31 &cpuintc 2>, -+ <30 &cpuintc 1>, -+ <29 &cpuintc 5>; -+ }; diff --git a/target/linux/realtek/patches-5.10/006-5.12-irqchip-add-support-for-realtek-rtl838x-rtl839x-interrupt-controller.patch b/target/linux/realtek/patches-5.10/006-5.12-irqchip-add-support-for-realtek-rtl838x-rtl839x-interrupt-controller.patch deleted file mode 100644 index 753c41eb2f..0000000000 --- a/target/linux/realtek/patches-5.10/006-5.12-irqchip-add-support-for-realtek-rtl838x-rtl839x-interrupt-controller.patch +++ /dev/null @@ -1,211 +0,0 @@ -From 9f3a0f34b84ad1b9a8f2bdae44b66f16685b2143 Mon Sep 17 00:00:00 2001 -From: Bert Vermeulen -Date: Fri, 22 Jan 2021 21:42:24 +0100 -Subject: irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller - -This is a standard IRQ driver with only status and mask registers. - -The mapping from SoC interrupts (18-31) to MIPS core interrupts is -done via an interrupt-map in device tree. - -Signed-off-by: Bert Vermeulen -Signed-off-by: Birger Koblitz -Acked-by: John Crispin -Signed-off-by: Marc Zyngier -Link: https://lore.kernel.org/r/20210122204224.509124-3-bert@biot.com ---- - drivers/irqchip/Makefile | 1 + - drivers/irqchip/irq-realtek-rtl.c | 180 ++++++++++++++++++++++++++++++++++++++ - 2 files changed, 181 insertions(+) - create mode 100644 drivers/irqchip/irq-realtek-rtl.c - ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -114,3 +114,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-l - obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o - obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o - obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o -+obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o ---- /dev/null -+++ b/drivers/irqchip/irq-realtek-rtl.c -@@ -0,0 +1,180 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Copyright (C) 2020 Birger Koblitz -+ * Copyright (C) 2020 Bert Vermeulen -+ * Copyright (C) 2020 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+/* Global Interrupt Mask Register */ -+#define RTL_ICTL_GIMR 0x00 -+/* Global Interrupt Status Register */ -+#define RTL_ICTL_GISR 0x04 -+/* Interrupt Routing Registers */ -+#define RTL_ICTL_IRR0 0x08 -+#define RTL_ICTL_IRR1 0x0c -+#define RTL_ICTL_IRR2 0x10 -+#define RTL_ICTL_IRR3 0x14 -+ -+#define REG(x) (realtek_ictl_base + x) -+ -+static DEFINE_RAW_SPINLOCK(irq_lock); -+static void __iomem *realtek_ictl_base; -+ -+static void realtek_ictl_unmask_irq(struct irq_data *i) -+{ -+ unsigned long flags; -+ u32 value; -+ -+ raw_spin_lock_irqsave(&irq_lock, flags); -+ -+ value = readl(REG(RTL_ICTL_GIMR)); -+ value |= BIT(i->hwirq); -+ writel(value, REG(RTL_ICTL_GIMR)); -+ -+ raw_spin_unlock_irqrestore(&irq_lock, flags); -+} -+ -+static void realtek_ictl_mask_irq(struct irq_data *i) -+{ -+ unsigned long flags; -+ u32 value; -+ -+ raw_spin_lock_irqsave(&irq_lock, flags); -+ -+ value = readl(REG(RTL_ICTL_GIMR)); -+ value &= ~BIT(i->hwirq); -+ writel(value, REG(RTL_ICTL_GIMR)); -+ -+ raw_spin_unlock_irqrestore(&irq_lock, flags); -+} -+ -+static struct irq_chip realtek_ictl_irq = { -+ .name = "realtek-rtl-intc", -+ .irq_mask = realtek_ictl_mask_irq, -+ .irq_unmask = realtek_ictl_unmask_irq, -+}; -+ -+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -+{ -+ irq_set_chip_and_handler(hw, &realtek_ictl_irq, handle_level_irq); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops irq_domain_ops = { -+ .map = intc_map, -+ .xlate = irq_domain_xlate_onecell, -+}; -+ -+static void realtek_irq_dispatch(struct irq_desc *desc) -+{ -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct irq_domain *domain; -+ unsigned int pending; -+ -+ chained_irq_enter(chip, desc); -+ pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR)); -+ if (unlikely(!pending)) { -+ spurious_interrupt(); -+ goto out; -+ } -+ domain = irq_desc_get_handler_data(desc); -+ generic_handle_irq(irq_find_mapping(domain, __ffs(pending))); -+ -+out: -+ chained_irq_exit(chip, desc); -+} -+ -+/* -+ * SoC interrupts are cascaded to MIPS CPU interrupts according to the -+ * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for -+ * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts -+ * thus go into 4 IRRs. -+ */ -+static int __init map_interrupts(struct device_node *node, struct irq_domain *domain) -+{ -+ struct device_node *cpu_ictl; -+ const __be32 *imap; -+ u32 imaplen, soc_int, cpu_int, tmp, regs[4]; -+ int ret, i, irr_regs[] = { -+ RTL_ICTL_IRR3, -+ RTL_ICTL_IRR2, -+ RTL_ICTL_IRR1, -+ RTL_ICTL_IRR0, -+ }; -+ u8 mips_irqs_set; -+ -+ ret = of_property_read_u32(node, "#address-cells", &tmp); -+ if (ret || tmp) -+ return -EINVAL; -+ -+ imap = of_get_property(node, "interrupt-map", &imaplen); -+ if (!imap || imaplen % 3) -+ return -EINVAL; -+ -+ mips_irqs_set = 0; -+ memset(regs, 0, sizeof(regs)); -+ for (i = 0; i < imaplen; i += 3 * sizeof(u32)) { -+ soc_int = be32_to_cpup(imap); -+ if (soc_int > 31) -+ return -EINVAL; -+ -+ cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1)); -+ if (!cpu_ictl) -+ return -EINVAL; -+ ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp); -+ if (ret || tmp != 1) -+ return -EINVAL; -+ of_node_put(cpu_ictl); -+ -+ cpu_int = be32_to_cpup(imap + 2); -+ if (cpu_int > 7) -+ return -EINVAL; -+ -+ if (!(mips_irqs_set & BIT(cpu_int))) { -+ irq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch, -+ domain); -+ mips_irqs_set |= BIT(cpu_int); -+ } -+ -+ regs[(soc_int * 4) / 32] |= cpu_int << (soc_int * 4) % 32; -+ imap += 3; -+ } -+ -+ for (i = 0; i < 4; i++) -+ writel(regs[i], REG(irr_regs[i])); -+ -+ return 0; -+} -+ -+static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent) -+{ -+ struct irq_domain *domain; -+ int ret; -+ -+ realtek_ictl_base = of_iomap(node, 0); -+ if (!realtek_ictl_base) -+ return -ENXIO; -+ -+ /* Disable all cascaded interrupts */ -+ writel(0, REG(RTL_ICTL_GIMR)); -+ -+ domain = irq_domain_add_simple(node, 32, 0, -+ &irq_domain_ops, NULL); -+ -+ ret = map_interrupts(node, domain); -+ if (ret) { -+ pr_err("invalid interrupt map\n"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+IRQCHIP_DECLARE(realtek_rtl_intc, "realtek,rtl-intc", realtek_rtl_of_init); diff --git a/target/linux/realtek/patches-5.10/007-5.16-gpio-realtek-realtek-otto-fix-gpio-line-irq-offset.patch b/target/linux/realtek/patches-5.10/007-5.16-gpio-realtek-realtek-otto-fix-gpio-line-irq-offset.patch deleted file mode 100644 index 9935c57257..0000000000 --- a/target/linux/realtek/patches-5.10/007-5.16-gpio-realtek-realtek-otto-fix-gpio-line-irq-offset.patch +++ /dev/null @@ -1,22 +0,0 @@ -From: Sander Vanheule -Subject: gpio: realtek-otto: fix GPIO line IRQ offset - -The irqchip uses one domain for all GPIO lines, so th line offset should be -determined w.r.t. the first line of the first port, not the first line of the -triggered port. - -Fixes: 0d82fb1127fb ("gpio: Add Realtek Otto GPIO support") -Signed-off-by: Sander Vanheule -Link: https://lore.kernel.org/linux-gpio/20211028085243.34360-1-sander@svanheule.net/ - ---- a/drivers/gpio/gpio-realtek-otto.c -+++ b/drivers/gpio/gpio-realtek-otto.c -@@ -206,7 +206,7 @@ static void realtek_gpio_irq_handler(str - status = realtek_gpio_read_isr(ctrl, lines_done / 8); - port_pin_count = min(gc->ngpio - lines_done, 8U); - for_each_set_bit(offset, &status, port_pin_count) { -- irq = irq_find_mapping(gc->irq.domain, offset); -+ irq = irq_find_mapping(gc->irq.domain, offset + lines_done); - generic_handle_irq(irq); - } - } diff --git a/target/linux/realtek/patches-5.10/008-5.17-watchdog-add-realtek-otto-watchdog-timer.patch b/target/linux/realtek/patches-5.10/008-5.17-watchdog-add-realtek-otto-watchdog-timer.patch deleted file mode 100644 index cf93d28f0a..0000000000 --- a/target/linux/realtek/patches-5.10/008-5.17-watchdog-add-realtek-otto-watchdog-timer.patch +++ /dev/null @@ -1,467 +0,0 @@ -From 293903b9dfe43520f01374dc1661be11d6838c49 Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Thu, 18 Nov 2021 17:29:52 +0100 -Subject: watchdog: Add Realtek Otto watchdog timer - -Realtek MIPS SoCs (platform name Otto) have a watchdog timer with -pretimeout notifitication support. The WDT can (partially) hard reset, -or soft reset the SoC. - -This driver implements all features as described in the devicetree -binding, except the phase2 interrupt, and also functions as a restart -handler. The cpu reset mode is considered to be a "warm" restart, since -this mode does not reset all peripherals. Being an embedded system -though, the "cpu" and "software" modes will still cause the bootloader -to run on restart. - -It is not known how a forced system reset can be disabled on the -supported platforms. This means that the phase2 interrupt will only fire -at the same time as reset, so implementing phase2 is of little use. - -Signed-off-by: Sander Vanheule -Reviewed-by: Guenter Roeck -Link: https://lore.kernel.org/r/6d060bccbdcc709cfa79203485db85aad3c3beb5.1637252610.git.sander@svanheule.net -Signed-off-by: Guenter Roeck ---- - MAINTAINERS | 7 + - drivers/watchdog/Kconfig | 13 ++ - drivers/watchdog/Makefile | 1 + - drivers/watchdog/realtek_otto_wdt.c | 384 ++++++++++++++++++++++++++++++++++++ - 4 files changed, 405 insertions(+) - create mode 100644 drivers/watchdog/realtek_otto_wdt.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -14824,6 +14824,13 @@ S: Maintained - F: include/sound/rt*.h - F: sound/soc/codecs/rt* - -+REALTEK OTTO WATCHDOG -+M: Sander Vanheule -+L: linux-watchdog@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml -+F: driver/watchdog/realtek_otto_wdt.c -+ - REALTEK RTL83xx SMI DSA ROUTER CHIPS - M: Linus Walleij - S: Maintained ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -995,6 +995,19 @@ config RTD119X_WATCHDOG - Say Y here to include support for the watchdog timer in - Realtek RTD1295 SoCs. - -+config REALTEK_OTTO_WDT -+ tristate "Realtek Otto MIPS watchdog support" -+ depends on MACH_REALTEK_RTL || COMPILE_TEST -+ depends on COMMON_CLK -+ select WATCHDOG_CORE -+ default MACH_REALTEK_RTL -+ help -+ Say Y here to include support for the watchdog timer on Realtek -+ RTL838x, RTL839x, RTL930x SoCs. This watchdog has pretimeout -+ notifications and system reset on timeout. -+ -+ When built as a module this will be called realtek_otto_wdt. -+ - config SPRD_WATCHDOG - tristate "Spreadtrum watchdog support" - depends on ARCH_SPRD || COMPILE_TEST ---- a/drivers/watchdog/Makefile -+++ b/drivers/watchdog/Makefile -@@ -174,6 +174,7 @@ obj-$(CONFIG_IMGPDC_WDT) += imgpdc_wdt.o - obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o - obj-$(CONFIG_PIC32_WDT) += pic32-wdt.o - obj-$(CONFIG_PIC32_DMT) += pic32-dmt.o -+obj-$(CONFIG_REALTEK_OTTO_WDT) += realtek_otto_wdt.o - - # PARISC Architecture - ---- /dev/null -+++ b/drivers/watchdog/realtek_otto_wdt.c -@@ -0,0 +1,384 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+ -+/* -+ * Realtek Otto MIPS platform watchdog -+ * -+ * Watchdog timer that will reset the system after timeout, using the selected -+ * reset mode. -+ * -+ * Counter scaling and timeouts: -+ * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz -+ * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8} -+ * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0 -+ * Generates an interrupt, WDT cannot be stopped after phase 1 -+ * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0 -+ * Resets the system according to RST_MODE -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define OTTO_WDT_REG_CNTR 0x0 -+#define OTTO_WDT_CNTR_PING BIT(31) -+ -+#define OTTO_WDT_REG_INTR 0x4 -+#define OTTO_WDT_INTR_PHASE_1 BIT(31) -+#define OTTO_WDT_INTR_PHASE_2 BIT(30) -+ -+#define OTTO_WDT_REG_CTRL 0x8 -+#define OTTO_WDT_CTRL_ENABLE BIT(31) -+#define OTTO_WDT_CTRL_PRESCALE GENMASK(30, 29) -+#define OTTO_WDT_CTRL_PHASE1 GENMASK(26, 22) -+#define OTTO_WDT_CTRL_PHASE2 GENMASK(19, 15) -+#define OTTO_WDT_CTRL_RST_MODE GENMASK(1, 0) -+#define OTTO_WDT_MODE_SOC 0 -+#define OTTO_WDT_MODE_CPU 1 -+#define OTTO_WDT_MODE_SOFTWARE 2 -+#define OTTO_WDT_CTRL_DEFAULT OTTO_WDT_MODE_CPU -+ -+#define OTTO_WDT_PRESCALE_MAX 3 -+ -+/* -+ * One higher than the max values contained in PHASE{1,2}, since a value of 0 -+ * corresponds to one tick. -+ */ -+#define OTTO_WDT_PHASE_TICKS_MAX 32 -+ -+/* -+ * The maximum reset delay is actually 2×32 ticks, but that would require large -+ * pretimeout values for timeouts longer than 32 ticks. Limit the maximum timeout -+ * to 32 + 1 to ensure small pretimeout values can be configured as expected. -+ */ -+#define OTTO_WDT_TIMEOUT_TICKS_MAX (OTTO_WDT_PHASE_TICKS_MAX + 1) -+ -+struct otto_wdt_ctrl { -+ struct watchdog_device wdev; -+ struct device *dev; -+ void __iomem *base; -+ unsigned int clk_rate_khz; -+ int irq_phase1; -+}; -+ -+static int otto_wdt_start(struct watchdog_device *wdev) -+{ -+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); -+ u32 v; -+ -+ v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); -+ v |= OTTO_WDT_CTRL_ENABLE; -+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); -+ -+ return 0; -+} -+ -+static int otto_wdt_stop(struct watchdog_device *wdev) -+{ -+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); -+ u32 v; -+ -+ v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); -+ v &= ~OTTO_WDT_CTRL_ENABLE; -+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); -+ -+ return 0; -+} -+ -+static int otto_wdt_ping(struct watchdog_device *wdev) -+{ -+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); -+ -+ iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR); -+ -+ return 0; -+} -+ -+static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale) -+{ -+ return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz); -+} -+ -+/* -+ * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds -+ * the value stored in those fields. This means each phase will run for at least -+ * one tick, so small values need to be clamped to correctly reflect the timeout. -+ */ -+static inline unsigned int div_round_ticks(unsigned int val, unsigned int tick_duration, -+ unsigned int min_ticks) -+{ -+ return max(min_ticks, DIV_ROUND_UP(val, tick_duration)); -+} -+ -+static int otto_wdt_determine_timeouts(struct watchdog_device *wdev, unsigned int timeout, -+ unsigned int pretimeout) -+{ -+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); -+ unsigned int pretimeout_ms = pretimeout * 1000; -+ unsigned int timeout_ms = timeout * 1000; -+ unsigned int prescale_next = 0; -+ unsigned int phase1_ticks; -+ unsigned int phase2_ticks; -+ unsigned int total_ticks; -+ unsigned int prescale; -+ unsigned int tick_ms; -+ u32 v; -+ -+ do { -+ prescale = prescale_next; -+ if (prescale > OTTO_WDT_PRESCALE_MAX) -+ return -EINVAL; -+ -+ tick_ms = otto_wdt_tick_ms(ctrl, prescale); -+ total_ticks = div_round_ticks(timeout_ms, tick_ms, 2); -+ phase1_ticks = div_round_ticks(timeout_ms - pretimeout_ms, tick_ms, 1); -+ phase2_ticks = total_ticks - phase1_ticks; -+ -+ prescale_next++; -+ } while (phase1_ticks > OTTO_WDT_PHASE_TICKS_MAX -+ || phase2_ticks > OTTO_WDT_PHASE_TICKS_MAX); -+ -+ v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); -+ -+ v &= ~(OTTO_WDT_CTRL_PRESCALE | OTTO_WDT_CTRL_PHASE1 | OTTO_WDT_CTRL_PHASE2); -+ v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE1, phase1_ticks - 1); -+ v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE2, phase2_ticks - 1); -+ v |= FIELD_PREP(OTTO_WDT_CTRL_PRESCALE, prescale); -+ -+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); -+ -+ timeout_ms = total_ticks * tick_ms; -+ ctrl->wdev.timeout = timeout_ms / 1000; -+ -+ pretimeout_ms = phase2_ticks * tick_ms; -+ ctrl->wdev.pretimeout = pretimeout_ms / 1000; -+ -+ return 0; -+} -+ -+static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val) -+{ -+ return otto_wdt_determine_timeouts(wdev, val, min(wdev->pretimeout, val - 1)); -+} -+ -+static int otto_wdt_set_pretimeout(struct watchdog_device *wdev, unsigned int val) -+{ -+ return otto_wdt_determine_timeouts(wdev, wdev->timeout, val); -+} -+ -+static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode, -+ void *data) -+{ -+ struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); -+ u32 reset_mode; -+ u32 v; -+ -+ disable_irq(ctrl->irq_phase1); -+ -+ switch (reboot_mode) { -+ case REBOOT_SOFT: -+ reset_mode = OTTO_WDT_MODE_SOFTWARE; -+ break; -+ case REBOOT_WARM: -+ reset_mode = OTTO_WDT_MODE_CPU; -+ break; -+ default: -+ reset_mode = OTTO_WDT_MODE_SOC; -+ break; -+ } -+ -+ /* Configure for shortest timeout and wait for reset to occur */ -+ v = FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, reset_mode) | OTTO_WDT_CTRL_ENABLE; -+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); -+ -+ mdelay(3 * otto_wdt_tick_ms(ctrl, 0)); -+ -+ return 0; -+} -+ -+static irqreturn_t otto_wdt_phase1_isr(int irq, void *dev_id) -+{ -+ struct otto_wdt_ctrl *ctrl = dev_id; -+ -+ iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base + OTTO_WDT_REG_INTR); -+ dev_crit(ctrl->dev, "phase 1 timeout\n"); -+ watchdog_notify_pretimeout(&ctrl->wdev); -+ -+ return IRQ_HANDLED; -+} -+ -+static const struct watchdog_ops otto_wdt_ops = { -+ .owner = THIS_MODULE, -+ .start = otto_wdt_start, -+ .stop = otto_wdt_stop, -+ .ping = otto_wdt_ping, -+ .set_timeout = otto_wdt_set_timeout, -+ .set_pretimeout = otto_wdt_set_pretimeout, -+ .restart = otto_wdt_restart, -+}; -+ -+static const struct watchdog_info otto_wdt_info = { -+ .identity = "Realtek Otto watchdog timer", -+ .options = WDIOF_KEEPALIVEPING | -+ WDIOF_MAGICCLOSE | -+ WDIOF_SETTIMEOUT | -+ WDIOF_PRETIMEOUT, -+}; -+ -+static void otto_wdt_clock_action(void *data) -+{ -+ clk_disable_unprepare(data); -+} -+ -+static int otto_wdt_probe_clk(struct otto_wdt_ctrl *ctrl) -+{ -+ struct clk *clk = devm_clk_get(ctrl->dev, NULL); -+ int ret; -+ -+ if (IS_ERR(clk)) -+ return dev_err_probe(ctrl->dev, PTR_ERR(clk), "Failed to get clock\n"); -+ -+ ret = clk_prepare_enable(clk); -+ if (ret) -+ return dev_err_probe(ctrl->dev, ret, "Failed to enable clock\n"); -+ -+ ret = devm_add_action_or_reset(ctrl->dev, otto_wdt_clock_action, clk); -+ if (ret) -+ return ret; -+ -+ ctrl->clk_rate_khz = clk_get_rate(clk) / 1000; -+ if (ctrl->clk_rate_khz == 0) -+ return dev_err_probe(ctrl->dev, -ENXIO, "Failed to get clock rate\n"); -+ -+ return 0; -+} -+ -+static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl) -+{ -+ static const char *mode_property = "realtek,reset-mode"; -+ const struct fwnode_handle *node = ctrl->dev->fwnode; -+ int mode_count; -+ u32 mode; -+ u32 v; -+ -+ if (!node) -+ return -ENXIO; -+ -+ mode_count = fwnode_property_string_array_count(node, mode_property); -+ if (mode_count < 0) -+ return mode_count; -+ else if (mode_count == 0) -+ return 0; -+ else if (mode_count != 1) -+ return -EINVAL; -+ -+ if (fwnode_property_match_string(node, mode_property, "soc") == 0) -+ mode = OTTO_WDT_MODE_SOC; -+ else if (fwnode_property_match_string(node, mode_property, "cpu") == 0) -+ mode = OTTO_WDT_MODE_CPU; -+ else if (fwnode_property_match_string(node, mode_property, "software") == 0) -+ mode = OTTO_WDT_MODE_SOFTWARE; -+ else -+ return -EINVAL; -+ -+ v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); -+ v &= ~OTTO_WDT_CTRL_RST_MODE; -+ v |= FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, mode); -+ iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); -+ -+ return 0; -+} -+ -+static int otto_wdt_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct otto_wdt_ctrl *ctrl; -+ unsigned int max_tick_ms; -+ int ret; -+ -+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); -+ if (!ctrl) -+ return -ENOMEM; -+ -+ ctrl->dev = dev; -+ ctrl->base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(ctrl->base)) -+ return PTR_ERR(ctrl->base); -+ -+ /* Clear any old interrupts and reset initial state */ -+ iowrite32(OTTO_WDT_INTR_PHASE_1 | OTTO_WDT_INTR_PHASE_2, -+ ctrl->base + OTTO_WDT_REG_INTR); -+ iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL); -+ -+ ret = otto_wdt_probe_clk(ctrl); -+ if (ret) -+ return ret; -+ -+ ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1"); -+ if (ctrl->irq_phase1 < 0) -+ return ctrl->irq_phase1; -+ -+ ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0, -+ "realtek-otto-wdt", ctrl); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to get IRQ for phase1\n"); -+ -+ ret = otto_wdt_probe_reset_mode(ctrl); -+ if (ret) -+ return dev_err_probe(dev, ret, "Invalid reset mode specified\n"); -+ -+ ctrl->wdev.parent = dev; -+ ctrl->wdev.info = &otto_wdt_info; -+ ctrl->wdev.ops = &otto_wdt_ops; -+ -+ /* -+ * Since pretimeout cannot be disabled, min. timeout is twice the -+ * subsystem resolution. Max. timeout is ca. 43s at a bus clock of 200MHz. -+ */ -+ ctrl->wdev.min_timeout = 2; -+ max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX); -+ ctrl->wdev.max_hw_heartbeat_ms = max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX; -+ ctrl->wdev.timeout = min(30U, ctrl->wdev.max_hw_heartbeat_ms / 1000); -+ -+ watchdog_set_drvdata(&ctrl->wdev, ctrl); -+ watchdog_init_timeout(&ctrl->wdev, 0, dev); -+ watchdog_stop_on_reboot(&ctrl->wdev); -+ watchdog_set_restart_priority(&ctrl->wdev, 128); -+ -+ ret = otto_wdt_determine_timeouts(&ctrl->wdev, ctrl->wdev.timeout, 1); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to set timeout\n"); -+ -+ return devm_watchdog_register_device(dev, &ctrl->wdev); -+} -+ -+static const struct of_device_id otto_wdt_ids[] = { -+ { .compatible = "realtek,rtl8380-wdt" }, -+ { .compatible = "realtek,rtl8390-wdt" }, -+ { .compatible = "realtek,rtl9300-wdt" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, otto_wdt_ids); -+ -+static struct platform_driver otto_wdt_driver = { -+ .probe = otto_wdt_probe, -+ .driver = { -+ .name = "realtek-otto-watchdog", -+ .of_match_table = otto_wdt_ids, -+ }, -+}; -+module_platform_driver(otto_wdt_driver); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Sander Vanheule "); -+MODULE_DESCRIPTION("Realtek Otto watchdog timer driver"); diff --git a/target/linux/realtek/patches-5.10/020-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch b/target/linux/realtek/patches-5.10/020-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch deleted file mode 100644 index ef2e225717..0000000000 --- a/target/linux/realtek/patches-5.10/020-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch +++ /dev/null @@ -1,53 +0,0 @@ -From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Tue, 4 Jan 2022 12:07:00 +0000 -Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and - devad fields - -Add a couple of helpers and definitions to extract the clause 45 regad -and devad fields from the regnum passed into MDIO drivers. - -Tested-by: Daniel Golle -Reviewed-by: Andrew Lunn -Signed-off-by: Russell King (Oracle) -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - include/linux/mdio.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/include/linux/mdio.h -+++ b/include/linux/mdio.h -@@ -7,6 +7,7 @@ - #define __LINUX_MDIO_H__ - - #include -+#include - #include - - /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit -@@ -14,6 +15,7 @@ - */ - #define MII_ADDR_C45 (1<<30) - #define MII_DEVADDR_C45_SHIFT 16 -+#define MII_DEVADDR_C45_MASK GENMASK(20, 16) - #define MII_REGADDR_C45_MASK GENMASK(15, 0) - - struct gpio_desc; -@@ -342,6 +344,16 @@ static inline u32 mdiobus_c45_addr(int d - return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; - } - -+static inline u16 mdiobus_c45_regad(u32 regnum) -+{ -+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum); -+} -+ -+static inline u16 mdiobus_c45_devad(u32 regnum) -+{ -+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); -+} -+ - static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad, - u16 regnum) - { diff --git a/target/linux/realtek/patches-5.10/021-v5.19-02-gpio-realtek-otto-Support-reversed-port-layouts.patch b/target/linux/realtek/patches-5.10/021-v5.19-02-gpio-realtek-otto-Support-reversed-port-layouts.patch deleted file mode 100644 index 8f35351438..0000000000 --- a/target/linux/realtek/patches-5.10/021-v5.19-02-gpio-realtek-otto-Support-reversed-port-layouts.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 512c5be35223d9baa2629efa1084cf5210eaee80 Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Sat, 9 Apr 2022 21:55:47 +0200 -Subject: [PATCH 2/6] gpio: realtek-otto: Support reversed port layouts - -The GPIO port layout on the RTL930x SoC series is reversed compared to -the RTL838x and RTL839x SoC series. Add new port offset calculator -functions to ensure the correct order is used when reading port IRQ -data, and ensure bgpio uses the right byte ordering. - -Signed-off-by: Sander Vanheule -Signed-off-by: Bartosz Golaszewski ---- - drivers/gpio/gpio-realtek-otto.c | 55 +++++++++++++++++++++++++++++--- - 1 file changed, 51 insertions(+), 4 deletions(-) - ---- a/drivers/gpio/gpio-realtek-otto.c -+++ b/drivers/gpio/gpio-realtek-otto.c -@@ -58,6 +58,8 @@ struct realtek_gpio_ctrl { - raw_spinlock_t lock; - u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; - u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; -+ unsigned int (*port_offset_u8)(unsigned int port); -+ unsigned int (*port_offset_u16)(unsigned int port); - }; - - /* Expand with more flags as devices with other quirks are added */ -@@ -69,6 +71,11 @@ enum realtek_gpio_flags { - * line the IRQ handler was assigned to, causing uncaught interrupts. - */ - GPIO_INTERRUPTS_DISABLED = BIT(0), -+ /* -+ * Port order is reversed, meaning DCBA register layout for 1-bit -+ * fields, and [BA, DC] for 2-bit fields. -+ */ -+ GPIO_PORTS_REVERSED = BIT(1), - }; - - static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) -@@ -86,21 +93,50 @@ static struct realtek_gpio_ctrl *irq_dat - * port. The two interrupt mask registers store two bits per GPIO, so use u16 - * values. - */ -+static unsigned int realtek_gpio_port_offset_u8(unsigned int port) -+{ -+ return port; -+} -+ -+static unsigned int realtek_gpio_port_offset_u16(unsigned int port) -+{ -+ return 2 * port; -+} -+ -+/* -+ * Reversed port order register access -+ * -+ * For registers with one bit per GPIO, all ports are stored as u8-s in one -+ * register in reversed order. The two interrupt mask registers store two bits -+ * per GPIO, so use u16 values. The first register contains ports 1 and 0, the -+ * second ports 3 and 2. -+ */ -+static unsigned int realtek_gpio_port_offset_u8_rev(unsigned int port) -+{ -+ return 3 - port; -+} -+ -+static unsigned int realtek_gpio_port_offset_u16_rev(unsigned int port) -+{ -+ return 2 * (port ^ 1); -+} -+ - static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl, - unsigned int port, u16 irq_type, u16 irq_mask) - { -- iowrite16(irq_type & irq_mask, ctrl->base + REALTEK_GPIO_REG_IMR + 2 * port); -+ iowrite16(irq_type & irq_mask, -+ ctrl->base + REALTEK_GPIO_REG_IMR + ctrl->port_offset_u16(port)); - } - - static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, - unsigned int port, u8 mask) - { -- iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + port); -+ iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); - } - - static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port) - { -- return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + port); -+ return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); - } - - /* Set the rising and falling edge mask bits for a GPIO port pin */ -@@ -253,6 +289,7 @@ MODULE_DEVICE_TABLE(of, realtek_gpio_of_ - static int realtek_gpio_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -+ unsigned long bgpio_flags; - unsigned int dev_flags; - struct gpio_irq_chip *girq; - struct realtek_gpio_ctrl *ctrl; -@@ -280,10 +317,20 @@ static int realtek_gpio_probe(struct pla - - raw_spin_lock_init(&ctrl->lock); - -+ if (dev_flags & GPIO_PORTS_REVERSED) { -+ bgpio_flags = 0; -+ ctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev; -+ ctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev; -+ } else { -+ bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; -+ ctrl->port_offset_u8 = realtek_gpio_port_offset_u8; -+ ctrl->port_offset_u16 = realtek_gpio_port_offset_u16; -+ } -+ - err = bgpio_init(&ctrl->gc, dev, 4, - ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL, - ctrl->base + REALTEK_GPIO_REG_DIR, NULL, -- BGPIOF_BIG_ENDIAN_BYTE_ORDER); -+ bgpio_flags); - if (err) { - dev_err(dev, "unable to init generic GPIO"); - return err; diff --git a/target/linux/realtek/patches-5.10/021-v5.19-03-gpio-realtek-otto-Support-per-cpu-interrupts.patch b/target/linux/realtek/patches-5.10/021-v5.19-03-gpio-realtek-otto-Support-per-cpu-interrupts.patch deleted file mode 100644 index 8f5d571ea2..0000000000 --- a/target/linux/realtek/patches-5.10/021-v5.19-03-gpio-realtek-otto-Support-per-cpu-interrupts.patch +++ /dev/null @@ -1,153 +0,0 @@ -From 95fa6dbe58f286a8f87cb37b7516232eb678de2d Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Sat, 9 Apr 2022 21:55:48 +0200 -Subject: [PATCH 3/6] gpio: realtek-otto: Support per-cpu interrupts - -On SoCs with multiple cores, it is possible that the GPIO interrupt -controller supports assigning specific pins to one or more cores. - -IRQ balancing can be performed on a line-by-line basis if the parent -interrupt is routed to all available cores, which is the default upon -initialisation. - -Signed-off-by: Sander Vanheule -Signed-off-by: Bartosz Golaszewski ---- - drivers/gpio/gpio-realtek-otto.c | 75 +++++++++++++++++++++++++++++++- - 1 file changed, 74 insertions(+), 1 deletion(-) - ---- a/drivers/gpio/gpio-realtek-otto.c -+++ b/drivers/gpio/gpio-realtek-otto.c -@@ -1,6 +1,7 @@ - // SPDX-License-Identifier: GPL-2.0-only - - #include -+#include - #include - #include - #include -@@ -55,6 +56,8 @@ - struct realtek_gpio_ctrl { - struct gpio_chip gc; - void __iomem *base; -+ void __iomem *cpumask_base; -+ struct cpumask cpu_irq_maskable; - raw_spinlock_t lock; - u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; - u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; -@@ -76,6 +79,11 @@ enum realtek_gpio_flags { - * fields, and [BA, DC] for 2-bit fields. - */ - GPIO_PORTS_REVERSED = BIT(1), -+ /* -+ * Interrupts can be enabled per cpu. This requires a secondary IO -+ * range, where the per-cpu enable masks are located. -+ */ -+ GPIO_INTERRUPTS_PER_CPU = BIT(2), - }; - - static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) -@@ -250,14 +258,61 @@ static void realtek_gpio_irq_handler(str - chained_irq_exit(irq_chip, desc); - } - -+static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, -+ unsigned int port, int cpu) -+{ -+ return ctrl->cpumask_base + ctrl->port_offset_u8(port) + -+ REALTEK_GPIO_PORTS_PER_BANK * cpu; -+} -+ -+static int realtek_gpio_irq_set_affinity(struct irq_data *data, -+ const struct cpumask *dest, bool force) -+{ -+ struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); -+ unsigned int line = irqd_to_hwirq(data); -+ unsigned int port = line / 8; -+ unsigned int port_pin = line % 8; -+ void __iomem *irq_cpu_mask; -+ unsigned long flags; -+ int cpu; -+ u8 v; -+ -+ if (!ctrl->cpumask_base) -+ return -ENXIO; -+ -+ raw_spin_lock_irqsave(&ctrl->lock, flags); -+ -+ for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { -+ irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu); -+ v = ioread8(irq_cpu_mask); -+ -+ if (cpumask_test_cpu(cpu, dest)) -+ v |= BIT(port_pin); -+ else -+ v &= ~BIT(port_pin); -+ -+ iowrite8(v, irq_cpu_mask); -+ } -+ -+ raw_spin_unlock_irqrestore(&ctrl->lock, flags); -+ -+ irq_data_update_effective_affinity(data, dest); -+ -+ return 0; -+} -+ - static int realtek_gpio_irq_init(struct gpio_chip *gc) - { - struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); - unsigned int port; -+ int cpu; - - for (port = 0; (port * 8) < gc->ngpio; port++) { - realtek_gpio_write_imr(ctrl, port, 0, 0); - realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0)); -+ -+ for_each_cpu(cpu, &ctrl->cpu_irq_maskable) -+ iowrite8(GENMASK(7, 0), realtek_gpio_irq_cpu_mask(ctrl, port, cpu)); - } - - return 0; -@@ -269,6 +324,7 @@ static struct irq_chip realtek_gpio_irq_ - .irq_mask = realtek_gpio_irq_mask, - .irq_unmask = realtek_gpio_irq_unmask, - .irq_set_type = realtek_gpio_irq_set_type, -+ .irq_set_affinity = realtek_gpio_irq_set_affinity, - }; - - static const struct of_device_id realtek_gpio_of_match[] = { -@@ -293,8 +349,10 @@ static int realtek_gpio_probe(struct pla - unsigned int dev_flags; - struct gpio_irq_chip *girq; - struct realtek_gpio_ctrl *ctrl; -+ struct resource *res; - u32 ngpios; -- int err, irq; -+ unsigned int nr_cpus; -+ int cpu, err, irq; - - ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); - if (!ctrl) -@@ -355,6 +413,21 @@ static int realtek_gpio_probe(struct pla - girq->init_hw = realtek_gpio_irq_init; - } - -+ cpumask_clear(&ctrl->cpu_irq_maskable); -+ -+ if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) { -+ ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); -+ if (IS_ERR(ctrl->cpumask_base)) -+ return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base), -+ "missing CPU IRQ mask registers"); -+ -+ nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK; -+ nr_cpus = min(nr_cpus, num_present_cpus()); -+ -+ for (cpu = 0; cpu < nr_cpus; cpu++) -+ cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable); -+ } -+ - return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); - } - diff --git a/target/linux/realtek/patches-5.10/021-v5.19-04-gpio-realtek-otto-Add-RTL930x-support.patch b/target/linux/realtek/patches-5.10/021-v5.19-04-gpio-realtek-otto-Add-RTL930x-support.patch deleted file mode 100644 index 536c85740a..0000000000 --- a/target/linux/realtek/patches-5.10/021-v5.19-04-gpio-realtek-otto-Add-RTL930x-support.patch +++ /dev/null @@ -1,29 +0,0 @@ -From deaf1cecdeb052cdb5e92fd642016198724b44a4 Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Sat, 9 Apr 2022 21:55:49 +0200 -Subject: [PATCH 4/6] gpio: realtek-otto: Add RTL930x support - -The RTL930x SoC series has support for 24 GPIOs, with the port order -reversed compared to RTL838x and RTL839x. The RTL930x series also has -two CPUs (VPEs) and can distribute individual GPIO interrupts between -them. - -Signed-off-by: Sander Vanheule -Signed-off-by: Bartosz Golaszewski ---- - drivers/gpio/gpio-realtek-otto.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/gpio/gpio-realtek-otto.c -+++ b/drivers/gpio/gpio-realtek-otto.c -@@ -338,6 +338,10 @@ static const struct of_device_id realtek - { - .compatible = "realtek,rtl8390-gpio", - }, -+ { -+ .compatible = "realtek,rtl9300-gpio", -+ .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU) -+ }, - {} - }; - MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); diff --git a/target/linux/realtek/patches-5.10/021-v5.19-06-gpio-realtek-otto-Add-RTL931x-support.patch b/target/linux/realtek/patches-5.10/021-v5.19-06-gpio-realtek-otto-Add-RTL931x-support.patch deleted file mode 100644 index 16990ce053..0000000000 --- a/target/linux/realtek/patches-5.10/021-v5.19-06-gpio-realtek-otto-Add-RTL931x-support.patch +++ /dev/null @@ -1,30 +0,0 @@ -From d3bf3dc4bbbf6109bd9b4bd60089d36205ec4a37 Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Sat, 9 Apr 2022 21:55:51 +0200 -Subject: [PATCH 6/6] gpio: realtek-otto: Add RTL931x support - -The RTL931x SoC series has support for 32 GPIOs, although not all lines -may be broken out to a physical pad. - -The GPIO bank's parent interrupt can be routed to either or both of the -SoC's CPU cores by the GIC. Line-by-line IRQ balancing is not possible -on these SoCs. - -Signed-off-by: Sander Vanheule -Signed-off-by: Bartosz Golaszewski ---- - drivers/gpio/gpio-realtek-otto.c | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/drivers/gpio/gpio-realtek-otto.c -+++ b/drivers/gpio/gpio-realtek-otto.c -@@ -342,6 +342,9 @@ static const struct of_device_id realtek - .compatible = "realtek,rtl9300-gpio", - .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU) - }, -+ { -+ .compatible = "realtek,rtl9310-gpio", -+ }, - {} - }; - MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); diff --git a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch b/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch deleted file mode 100644 index fce26133fc..0000000000 --- a/target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch +++ /dev/null @@ -1,97 +0,0 @@ -From fce11f68491b46b93df69de0630cd9edb90bc772 Mon Sep 17 00:00:00 2001 -From: Birger Koblitz -Date: Wed, 29 Dec 2021 21:54:21 +0100 -Subject: [PATCH] realtek: Create 4 different Realtek Platforms - -Creates RTL83XX as a basic kernel config parameter for the -RTL838X, RTL839x, RTL930X and RTL931X platforms with respective -configurations for the SoCs, which are introduced in addition. - -Submitted-by: Birger Koblitz ---- - arch/mips/Kbuild.platforms | 1 + - arch/mips/Kconfig | 57 ++++++++++++++ - 2 files changed, 58 insertions(+) - ---- a/arch/mips/Kbuild.platforms -+++ b/arch/mips/Kbuild.platforms -@@ -23,6 +23,7 @@ platform-$(CONFIG_PIC32MZDA) += pic32/ - platform-$(CONFIG_MACH_PISTACHIO) += pistachio/ - platform-$(CONFIG_RALINK) += ralink/ - platform-$(CONFIG_MIKROTIK_RB532) += rb532/ -+platform-$(CONFIG_RTL83XX) += rtl838x/ - platform-$(CONFIG_SGI_IP22) += sgi-ip22/ - platform-$(CONFIG_SGI_IP27) += sgi-ip27/ - platform-$(CONFIG_SGI_IP28) += sgi-ip22/ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -1037,8 +1037,59 @@ config NLM_XLP_BOARD - This board is based on Netlogic XLP Processor. - Say Y here if you have a XLP based board. - -+config RTL83XX -+ bool "Realtek based platforms" -+ select DMA_NONCOHERENT -+ select IRQ_MIPS_CPU -+ select NO_EXCEPT_FILL -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_HIGHMEM -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_MIPS16 -+ select SYS_HAS_EARLY_PRINTK -+ select SYS_HAS_EARLY_PRINTK_8250 -+ select USE_GENERIC_EARLY_PRINTK_8250 -+ select BOOT_RAW -+ select PINCTRL -+ select ARCH_HAS_RESET_CONTROLLER -+ select RESET_CONTROLLER -+ select USE_OF -+ - endchoice - -+config RTL838X -+ bool "Realtek RTL838X based platforms" -+ depends on RTL83XX -+ select CPU_SUPPORTS_CPUFREQ -+ select MIPS_EXTERNAL_TIMER -+ -+config RTL839X -+ bool "Realtek RTL839X based platforms" -+ depends on RTL83XX -+ select CPU_SUPPORTS_CPUFREQ -+ select MIPS_EXTERNAL_TIMER -+ select SYS_SUPPORTS_MULTITHREADING -+ -+config RTL930X -+ bool "Realtek RTL930X based platforms" -+ depends on RTL83XX -+ select MIPS_CPU_SCACHE -+ select CSRC_R4K -+ select CEVT_RTL9300 -+ select SYS_SUPPORTS_MULTITHREADING -+ -+config RTL931X -+ bool "Realtek RTL931X based platforms" -+ depends on RTL930X -+ select MIPS_GIC -+ select COMMON_CLK -+ select CLKSRC_MIPS_GIC -+ select SYS_SUPPORTS_VPE_LOADER -+ select SYS_SUPPORTS_SMP -+ select SYS_SUPPORTS_MIPS_CPS -+ - source "arch/mips/alchemy/Kconfig" - source "arch/mips/ath25/Kconfig" - source "arch/mips/ath79/Kconfig" -@@ -1097,6 +1148,9 @@ config CEVT_GT641XX - config CEVT_R4K - bool - -+config CEVT_RTL9300 -+ bool -+ - config CEVT_SB1250 - bool - diff --git a/target/linux/realtek/patches-5.10/301-gpio-add-rtl8231-driver.patch b/target/linux/realtek/patches-5.10/301-gpio-add-rtl8231-driver.patch deleted file mode 100644 index 2725651243..0000000000 --- a/target/linux/realtek/patches-5.10/301-gpio-add-rtl8231-driver.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: [PATCH] realtek: update the tree to the latest refactored version -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - drivers/gpio/Kconfig | 6 ++++++ - drivers/gpio/Makefile | 1 + - 2 files changed, 7 insertions(+) - ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -508,6 +508,12 @@ config GPIO_REG - A 32-bit single register GPIO fixed in/out implementation. This - can be used to represent any register as a set of GPIO signals. - -+config GPIO_RTL8231 -+ tristate "RTL8231 GPIO" -+ depends on RTL83XX -+ help -+ Say yes here to support Realtek RTL8231 GPIO expansion chips. -+ - config GPIO_SAMA5D2_PIOBU - tristate "SAMA5D2 PIOBU GPIO support" - depends on MFD_SYSCON ---- a/drivers/gpio/Makefile -+++ b/drivers/gpio/Makefile -@@ -127,6 +127,7 @@ obj-$(CONFIG_GPIO_RDA) += gpio-rda.o - obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o - obj-$(CONFIG_GPIO_REALTEK_OTTO) += gpio-realtek-otto.o - obj-$(CONFIG_GPIO_REG) += gpio-reg.o -+obj-$(CONFIG_GPIO_RTL8231) += gpio-rtl8231.o - obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o - obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o - obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o diff --git a/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch b/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch deleted file mode 100644 index 81dff89f82..0000000000 --- a/target/linux/realtek/patches-5.10/302-clocksource-add-otto-driver.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 3cc8011171186d906c547bc6f0c1f8e350edc7cf Mon Sep 17 00:00:00 2001 -From: Markus Stockhausen -Date: Mon, 3 Oct 2022 14:45:21 +0200 -Subject: [PATCH] realtek: resurrect timer driver - -Now that we provide a clock driver for the Reltek SOCs the CPU frequency might -change on demand. This has direct visible effects during operation - -- the CEVT 4K timer is no longer a stable clocksource -- after CPU frequencies changes time calculation works wrong -- sched_clock falls back to kernel default interval (100 Hz) -- timestamps in dmesg have only 2 digits left - -[ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ... -[ 0.060000] pid_max: default: 32768 minimum: 301 -[ 0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) -[ 0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) -[ 0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build -[ 0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ... - -Looking around where we can start the CEVT timer for RTL930X is a good basis. -Initially it was developed as a clocksource driver for the broken timer in that -specific SOC series. Afterwards it was shifted around to the CEVT location, -got SMP enablement and lost its clocksource feature. So we at least have -something to copy from. As the timers on these devices are well understood -the implementation follows this way: - -- leave the RTL930X implementation as is -- provide a new driver for RTL83XX devices only -- swap RTL930X driver at a later time - -Like the clock driver this patch contains a self contained module that is SOC -independet and already provides full support for the RTL838X, RTL839X and -RTL930X devices. Some of the new (or reestablished) features are: - -- simplified initialization routines -- SMP setup with CPU hotplug framework -- derived from LXB clock speed -- supplied clocksource -- dedicated register functions for better readability -- documentation about some caveats - -Signed-off-by: Markus Stockhausen -[remove unused header includes, remove old CONFIG_MIPS dependency, add -REALTEK_ prefix to driver symbol] -Signed-off-by: Sander Vanheule - ---- - drivers/clocksource/Kconfig | 12 +++ - drivers/clocksource/Makefile | 1 + - include/linux/cpuhotplug.h | 1 + - 3 files changed, 14 insertions(+) - ---- a/drivers/clocksource/Kconfig -+++ b/drivers/clocksource/Kconfig -@@ -127,6 +127,17 @@ config RDA_TIMER - help - Enables the support for the RDA Micro timer driver. - -+config REALTEK_OTTO_TIMER -+ bool "Clocksource/timer for the Realtek Otto platform" -+ select COMMON_CLK -+ select TIMER_OF -+ help -+ This driver adds support for the timers found in the Realtek RTL83xx -+ and RTL93xx SoCs series. This includes chips such as RTL8380, RTL8381 -+ and RTL832, as well as chips from the RTL839x series, such as RTL8390 -+ RT8391, RTL8392, RTL8393 and RTL8396 and chips of the RTL930x series -+ such as RTL9301, RTL9302 or RTL9303. -+ - config SUN4I_TIMER - bool "Sun4i timer driver" if COMPILE_TEST - depends on HAS_IOMEM ---- a/drivers/clocksource/Makefile -+++ b/drivers/clocksource/Makefile -@@ -63,6 +63,7 @@ obj-$(CONFIG_MILBEAUT_TIMER) += timer-mi - obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o - obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o - obj-$(CONFIG_RDA_TIMER) += timer-rda.o -+obj-$(CONFIG_REALTEK_OTTO_TIMER) += timer-rtl-otto.o - - obj-$(CONFIG_ARC_TIMERS) += arc_timer.o - obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o ---- a/include/linux/cpuhotplug.h -+++ b/include/linux/cpuhotplug.h -@@ -133,6 +133,7 @@ enum cpuhp_state { - CPUHP_AP_MARCO_TIMER_STARTING, - CPUHP_AP_MIPS_GIC_TIMER_STARTING, - CPUHP_AP_ARC_TIMER_STARTING, -+ CPUHP_AP_REALTEK_TIMER_STARTING, - CPUHP_AP_RISCV_TIMER_STARTING, - CPUHP_AP_CLINT_TIMER_STARTING, - CPUHP_AP_CSKY_TIMER_STARTING, diff --git a/target/linux/realtek/patches-5.10/303-gpio-update-dependencies-for-gpio-realtek-otto.patch b/target/linux/realtek/patches-5.10/303-gpio-update-dependencies-for-gpio-realtek-otto.patch deleted file mode 100644 index 1763d31fb0..0000000000 --- a/target/linux/realtek/patches-5.10/303-gpio-update-dependencies-for-gpio-realtek-otto.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 9bac1c20b8f39f2e0e342b087add5093b94feaed Mon Sep 17 00:00:00 2001 -From: INAGAKI Hiroshi -Date: Wed, 5 May 2021 22:05:39 +0900 -Subject: realtek: fix gpio-realtek-otto driver dependency - -"MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X" -is used in OpenWrt, so fix the dependency by renaming it. - -Submitted-by: INAGAKI Hiroshi ---- - drivers/gpio/Kconfig | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -491,8 +491,8 @@ config GPIO_RDA - - config GPIO_REALTEK_OTTO - tristate "Realtek Otto GPIO support" -- depends on MACH_REALTEK_RTL -- default MACH_REALTEK_RTL -+ depends on RTL83XX -+ default RTL838X - select GPIO_GENERIC - select GPIOLIB_IRQCHIP - help diff --git a/target/linux/realtek/patches-5.10/304-spi-update-dependency-for-spi-realtek-rtl.patch b/target/linux/realtek/patches-5.10/304-spi-update-dependency-for-spi-realtek-rtl.patch deleted file mode 100644 index 23c5448aa2..0000000000 --- a/target/linux/realtek/patches-5.10/304-spi-update-dependency-for-spi-realtek-rtl.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0b000cbfe0aa0323bffa855ef8449c0687a4c071 Mon Sep 17 00:00:00 2001 -From: INAGAKI Hiroshi -Date: Thu, 6 May 2021 19:30:58 +0900 -Subject: realtek: backport spi-realtek-rtl driver from 5.12 to 5.10 - -This patch backports "spi-realtek-rtl" driver to Kernel 5.10 from 5.12. -"MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X" -is used in OpenWrt, so update the dependency by the additional patch. - -Submitted-by: INAGAKI Hiroshi ---- - drivers/spi/Makefile | 2 +- - 1 files changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -94,7 +94,7 @@ obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom - obj-$(CONFIG_SPI_QUP) += spi-qup.o - obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o - obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o --obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o -+obj-$(CONFIG_RTL83XX) += spi-realtek-rtl.o - obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o - obj-$(CONFIG_SPI_RSPI) += spi-rspi.o - obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o diff --git a/target/linux/realtek/patches-5.10/305-irqchip-update-dependency-for-irq-realtek-rtl.patch b/target/linux/realtek/patches-5.10/305-irqchip-update-dependency-for-irq-realtek-rtl.patch deleted file mode 100644 index 0c1cc4235e..0000000000 --- a/target/linux/realtek/patches-5.10/305-irqchip-update-dependency-for-irq-realtek-rtl.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 2cd00b51470a30198b048a5fca48a04db77e29cc Mon Sep 17 00:00:00 2001 -From: INAGAKI Hiroshi -Date: Fri, 21 May 2021 23:16:37 +0900 -Subject: [PATCH] realtek: backport irq-realtek-rtl driver from 5.12 to 5.10 - -This patch backports "irq-realtek-rtl" driver to Kernel 5.10 from 5.12. -"MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X" -is used in OpenWrt, so update the dependency by the additional patch. - -Submitted-by: INAGAKI Hiroshi ---- - drivers/irqchip/Makefile | 2 +- - 1 files changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -114,4 +114,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC) += irq-l - obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o - obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o - obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o --obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o -+obj-$(CONFIG_RTL83XX) += irq-realtek-rtl.o diff --git a/target/linux/realtek/patches-5.10/307-wdt-update-dependency-for-realtek-otto-wdt.patch b/target/linux/realtek/patches-5.10/307-wdt-update-dependency-for-realtek-otto-wdt.patch deleted file mode 100644 index f92981340b..0000000000 --- a/target/linux/realtek/patches-5.10/307-wdt-update-dependency-for-realtek-otto-wdt.patch +++ /dev/null @@ -1,32 +0,0 @@ -From b8fc5eecdc5d33cf261986436597b5482ab856da Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Sun, 14 Nov 2021 19:45:32 +0100 -Subject: [PATCH] realtek: Backport Realtek Otto WDT driver - -Add patch submitted upstream to linux-watchdog and replace the MIPS -architecture symbols. Requires one extra patch for the DIV_ROUND_* -macros, which have moved to a different header since 5.10. - -Submitted-by: Sander Vanheule -Tested-by: Stijn Segers -Tested-by: Paul Fertser -Tested-by: Stijn Tintel ---- - drivers/watchdog/Kconfig | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/watchdog/Kconfig -+++ b/drivers/watchdog/Kconfig -@@ -997,10 +997,10 @@ config RTD119X_WATCHDOG - - config REALTEK_OTTO_WDT - tristate "Realtek Otto MIPS watchdog support" -- depends on MACH_REALTEK_RTL || COMPILE_TEST -+ depends on RTL83XX - depends on COMMON_CLK - select WATCHDOG_CORE -- default MACH_REALTEK_RTL -+ default RTL83XX - help - Say Y here to include support for the watchdog timer on Realtek - RTL838x, RTL839x, RTL930x SoCs. This watchdog has pretimeout diff --git a/target/linux/realtek/patches-5.10/308-otto-wdt-fix-missing-math-header.patch b/target/linux/realtek/patches-5.10/308-otto-wdt-fix-missing-math-header.patch deleted file mode 100644 index 78b145617f..0000000000 --- a/target/linux/realtek/patches-5.10/308-otto-wdt-fix-missing-math-header.patch +++ /dev/null @@ -1,28 +0,0 @@ -From b8fc5eecdc5d33cf261986436597b5482ab856da Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Sun, 14 Nov 2021 19:45:32 +0100 -Subject: [PATCH] realtek: Backport Realtek Otto WDT driver - -Add patch submitted upstream to linux-watchdog and replace the MIPS -architecture symbols. Requires one extra patch for the DIV_ROUND_* -macros, which have moved to a different header since 5.10. - -Submitted-by: Sander Vanheule -Tested-by: Stijn Segers -Tested-by: Paul Fertser -Tested-by: Stijn Tintel ---- - drivers/watchdog/realtek_otto_wdt.c | 2 +- - 1 files changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/watchdog/realtek_otto_wdt.c -+++ b/drivers/watchdog/realtek_otto_wdt.c -@@ -21,7 +21,7 @@ - #include - #include - #include --#include -+#include - #include - #include - #include diff --git a/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch b/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch deleted file mode 100644 index 93d69c07cf..0000000000 --- a/target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 775d903216a08c2a8009863d2f9c33f62657ba94 Mon Sep 17 00:00:00 2001 -From: Birger Koblitz -Date: Thu, 6 Jan 2022 20:27:01 +0100 -Subject: [PATCH] realtek: Replace the RTL9300 generic timer with a CEVT timer - -The RTL9300 has a broken R4K MIPS timer interrupt, however, the -R4K clocksource works. We replace the RTL9300 timer with a -Clock Event Timer (CEVT), which is VSMP aware and can be instantiated -as part of brining a VSMTP cpu up instead of the R4K CEVT source. -For this we place the RTL9300 CEVT timer in arch/mips/kernel -together with other MIPS CEVT timers, initialize the SoC IRQs -from a modified smp-mt.c and instantiate each timer as part -of the MIPS time setup in arch/mips/include/asm/time.h instead -of the R4K CEVT, similarly as is done by other MIPS CEVT timers. - -Submitted-by: Birger Koblitz ---- - arch/mips/kernel/Makefile | 1 + - arch/mips/include/asm/time.h | 7 +++++++ - 2 files changed, 8 insertions(+) - ---- a/arch/mips/kernel/Makefile -+++ b/arch/mips/kernel/Makefile -@@ -27,6 +27,7 @@ obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm14 - obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o - obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o - obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o -+obj-$(CONFIG_CEVT_RTL9300) += cevt-rtl9300.o - obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o - obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o - obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o ---- a/arch/mips/include/asm/time.h -+++ b/arch/mips/include/asm/time.h -@@ -15,6 +15,8 @@ - #include - #include - -+extern void rtl9300_clockevent_init(void); -+ - extern spinlock_t rtc_lock; - - /* -@@ -43,6 +45,11 @@ extern int r4k_clockevent_init(void); - - static inline int mips_clockevent_init(void) - { -+#ifdef CONFIG_CEVT_RTL9300 -+ rtl9300_clockevent_init(); -+ return 0; -+#endif -+ - #ifdef CONFIG_CEVT_R4K - return r4k_clockevent_init(); - #else diff --git a/target/linux/realtek/patches-5.10/310-add-i2c-rtl9300-support.patch b/target/linux/realtek/patches-5.10/310-add-i2c-rtl9300-support.patch deleted file mode 100644 index 4df9bf043b..0000000000 --- a/target/linux/realtek/patches-5.10/310-add-i2c-rtl9300-support.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 63a0a4d85bc900464c5b046b13808a582345f8c8 Mon Sep 17 00:00:00 2001 -From: Birger Koblitz -Date: Sat, 11 Dec 2021 20:14:47 +0100 -Subject: [PATCH] realtek: Add support for RTL9300/RTL9310 I2C controller - -This adds support for the RTL9300 and RTL9310 I2C controller. -The controller implements the SMBus protocol for SMBus transfers -over an I2C bus. The driver supports selecting one of the 2 possible -SCL pins and any of the 8 possible SDA pins. Bus speeds of -100kHz (standard speed) and 400kHz (high speed I2C) are supported. - -Submitted-by: Birger Koblitz ---- - drivers/i2c/busses/Kconfig | 10 +++++++++ - drivers/i2c/busses/Makefile | 1 + - 2 files changed, 11 insertions(+) - ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -954,6 +954,16 @@ config I2C_RK3X - This driver can also be built as a module. If so, the module will - be called i2c-rk3x. - -+config I2C_RTL9300 -+ tristate "Realtek RTL9300 I2C adapter" -+ depends on OF -+ help -+ Say Y here to include support for the I2C adapter in Realtek RTL9300 -+ and RTL9310 SoCs. -+ -+ This driver can also be built as a module. If so, the module will -+ be called i2c-rtl9300. -+ - config HAVE_S3C2410_I2C - bool - help ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -95,6 +95,7 @@ obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom- - obj-$(CONFIG_I2C_QUP) += i2c-qup.o - obj-$(CONFIG_I2C_RIIC) += i2c-riic.o - obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o -+obj-$(CONFIG_I2C_RTL9300) += i2c-rtl9300.o - obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o - obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o - obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o diff --git a/target/linux/realtek/patches-5.10/311-add-i2c-mux-rtl9300-support.patch b/target/linux/realtek/patches-5.10/311-add-i2c-mux-rtl9300-support.patch deleted file mode 100644 index d0bfba4538..0000000000 --- a/target/linux/realtek/patches-5.10/311-add-i2c-mux-rtl9300-support.patch +++ /dev/null @@ -1,46 +0,0 @@ -From f4bdb7fdccdfe3fa382abe77f72a16c2f2e6add0 Mon Sep 17 00:00:00 2001 -From: Birger Koblitz -Date: Sat, 11 Dec 2021 20:25:37 +0100 -Subject: [PATCH] realtek: Add support for RTL9300/RTL9310 I2C multiplexing - -The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C -masters, each with a fixed SCL pin, that cannot be changed. Each of these -masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA. -This multiplexer directly controls the two masters and their shared -IO configuration registers to allow multiplexing between any of these -busses. The two masters cannot be used in parallel as the multiplex -is protected by a standard multiplex lock. - -Submitted-by: Birger Koblitz ---- - drivers/i2c/muxes/Kconfig | 9 +++++++ - drivers/i2c/muxes/Makefile | 1 + - 2 files changed, 10 insertions(+) - ---- a/drivers/i2c/muxes/Kconfig -+++ b/drivers/i2c/muxes/Kconfig -@@ -99,6 +99,15 @@ config I2C_MUX_REG - This driver can also be built as a module. If so, the module - will be called i2c-mux-reg. - -+config I2C_MUX_RTL9300 -+ tristate "RTL9300 based I2C multiplexer" -+ help -+ If you say yes to this option, support will be included for a -+ RTL9300 based I2C multiplexer. -+ -+ This driver can also be built as a module. If so, the module -+ will be called i2c-mux-reg. -+ - config I2C_DEMUX_PINCTRL - tristate "pinctrl-based I2C demultiplexer" - depends on PINCTRL && OF ---- a/drivers/i2c/muxes/Makefile -+++ b/drivers/i2c/muxes/Makefile -@@ -14,5 +14,6 @@ obj-$(CONFIG_I2C_MUX_PCA9541) += i2c-mux - obj-$(CONFIG_I2C_MUX_PCA954x) += i2c-mux-pca954x.o - obj-$(CONFIG_I2C_MUX_PINCTRL) += i2c-mux-pinctrl.o - obj-$(CONFIG_I2C_MUX_REG) += i2c-mux-reg.o -+obj-$(CONFIG_I2C_MUX_RTL9300) += i2c-mux-rtl9300.o - - ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG diff --git a/target/linux/realtek/patches-5.10/315-irqchip-irq-realtek-rtl-add-VPE-support.patch b/target/linux/realtek/patches-5.10/315-irqchip-irq-realtek-rtl-add-VPE-support.patch deleted file mode 100644 index 26c36302c2..0000000000 --- a/target/linux/realtek/patches-5.10/315-irqchip-irq-realtek-rtl-add-VPE-support.patch +++ /dev/null @@ -1,407 +0,0 @@ -From 6c18e9c491959ac0674ebe36b09f9ddc3f2c9bce Mon Sep 17 00:00:00 2001 -From: Birger Koblitz -Date: Fri, 31 Dec 2021 11:56:49 +0100 -Subject: [PATCH] realtek: Add VPE support for the IRQ driver - -In order to support VSMP, enable support for both VPEs -of the RTL839X and RTL930X SoCs in the irq-realtek-rtl -driver. Add support for IRQ affinity setting. - -Submitted-by: Birger Koblitz ---- - drivers/irqchip/irq-realtek-rtl.c | 152 +++++++++++++++--- - 1 file changed, 73 insertions(+), 76 deletions(-) - ---- a/drivers/irqchip/irq-realtek-rtl.c -+++ b/drivers/irqchip/irq-realtek-rtl.c -@@ -21,21 +21,63 @@ - #define RTL_ICTL_IRR2 0x10 - #define RTL_ICTL_IRR3 0x14 - --#define REG(x) (realtek_ictl_base + x) -+#define RTL_ICTL_NUM_INPUTS 32 -+#define RTL_ICTL_NUM_OUTPUTS 15 - - static DEFINE_RAW_SPINLOCK(irq_lock); --static void __iomem *realtek_ictl_base; -+ -+#define REG(offset, cpu) (realtek_ictl_base[cpu] + offset) -+ -+static void __iomem *realtek_ictl_base[NR_CPUS]; -+static cpumask_t realtek_ictl_cpu_configurable; -+ -+struct realtek_ictl_output { -+ /* IRQ controller data */ -+ struct fwnode_handle *fwnode; -+ /* Output specific data */ -+ unsigned int output_index; -+ struct irq_domain *domain; -+ u32 child_mask; -+}; -+ -+/* -+ * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numbering, -+ * placing IRQ 31 in the first four bits. A routing value of '0' means the -+ * interrupt is left disconnected. Routing values {1..15} connect to output -+ * lines {0..14}. -+ */ -+#define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) -+#define IRR_SHIFT(idx) ((idx * 4) % 32) -+ -+static inline u32 read_irr(void __iomem *irr0, int idx) -+{ -+ return (readl(irr0 + IRR_OFFSET(idx)) >> IRR_SHIFT(idx)) & 0xf; -+} -+ -+static inline void write_irr(void __iomem *irr0, int idx, u32 value) -+{ -+ unsigned int offset = IRR_OFFSET(idx); -+ unsigned int shift = IRR_SHIFT(idx); -+ u32 irr; -+ -+ irr = readl(irr0 + offset) & ~(0xf << shift); -+ irr |= (value & 0xf) << shift; -+ writel(irr, irr0 + offset); -+} - - static void realtek_ictl_unmask_irq(struct irq_data *i) - { - unsigned long flags; - u32 value; -+ int cpu; - - raw_spin_lock_irqsave(&irq_lock, flags); - -- value = readl(REG(RTL_ICTL_GIMR)); -- value |= BIT(i->hwirq); -- writel(value, REG(RTL_ICTL_GIMR)); -+ for_each_cpu(cpu, &realtek_ictl_cpu_configurable) { -+ value = readl(REG(RTL_ICTL_GIMR, cpu)); -+ value |= BIT(i->hwirq); -+ writel(value, REG(RTL_ICTL_GIMR, cpu)); -+ } - - raw_spin_unlock_irqrestore(&irq_lock, flags); - } -@@ -44,137 +86,247 @@ static void realtek_ictl_mask_irq(struct - { - unsigned long flags; - u32 value; -+ int cpu; - - raw_spin_lock_irqsave(&irq_lock, flags); - -- value = readl(REG(RTL_ICTL_GIMR)); -- value &= ~BIT(i->hwirq); -- writel(value, REG(RTL_ICTL_GIMR)); -+ for_each_cpu(cpu, &realtek_ictl_cpu_configurable) { -+ value = readl(REG(RTL_ICTL_GIMR, cpu)); -+ value &= ~BIT(i->hwirq); -+ writel(value, REG(RTL_ICTL_GIMR, cpu)); -+ } - - raw_spin_unlock_irqrestore(&irq_lock, flags); - } - -+static int __maybe_unused realtek_ictl_irq_affinity(struct irq_data *i, -+ const struct cpumask *dest, bool force) -+{ -+ struct realtek_ictl_output *output = i->domain->host_data; -+ cpumask_t cpu_configure; -+ cpumask_t cpu_disable; -+ cpumask_t cpu_enable; -+ unsigned long flags; -+ int cpu; -+ -+ raw_spin_lock_irqsave(&irq_lock, flags); -+ -+ cpumask_and(&cpu_configure, cpu_present_mask, &realtek_ictl_cpu_configurable); -+ -+ cpumask_and(&cpu_enable, &cpu_configure, dest); -+ cpumask_andnot(&cpu_disable, &cpu_configure, dest); -+ -+ for_each_cpu(cpu, &cpu_disable) -+ write_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, 0); -+ -+ for_each_cpu(cpu, &cpu_enable) -+ write_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, output->output_index + 1); -+ -+ irq_data_update_effective_affinity(i, &cpu_enable); -+ -+ raw_spin_unlock_irqrestore(&irq_lock, flags); -+ -+ return IRQ_SET_MASK_OK; -+} -+ - static struct irq_chip realtek_ictl_irq = { - .name = "realtek-rtl-intc", - .irq_mask = realtek_ictl_mask_irq, - .irq_unmask = realtek_ictl_unmask_irq, -+#ifdef CONFIG_SMP -+ .irq_set_affinity = realtek_ictl_irq_affinity, -+#endif - }; - - static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) - { -- irq_set_chip_and_handler(hw, &realtek_ictl_irq, handle_level_irq); -+ struct realtek_ictl_output *output = d->host_data; -+ unsigned long flags; -+ -+ irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq); -+ -+ raw_spin_lock_irqsave(&irq_lock, flags); -+ -+ output->child_mask |= BIT(hw); -+ write_irr(REG(RTL_ICTL_IRR0, 0), hw, output->output_index + 1); -+ -+ raw_spin_unlock_irqrestore(&irq_lock, flags); - - return 0; - } - -+static int intc_select(struct irq_domain *d, struct irq_fwspec *fwspec, -+ enum irq_domain_bus_token bus_token) -+{ -+ struct realtek_ictl_output *output = d->host_data; -+ bool routed_elsewhere; -+ unsigned long flags; -+ u32 routing_old; -+ int cpu; -+ -+ if (fwspec->fwnode != output->fwnode) -+ return false; -+ -+ /* Original specifiers had only one parameter */ -+ if (fwspec->param_count < 2) -+ return true; -+ -+ raw_spin_lock_irqsave(&irq_lock, flags); -+ -+ /* -+ * Inputs can only be routed to one output, so they shouldn't be -+ * allowed to end up in multiple domains. -+ */ -+ for_each_cpu(cpu, &realtek_ictl_cpu_configurable) { -+ routing_old = read_irr(REG(RTL_ICTL_IRR0, cpu), fwspec->param[0]); -+ routed_elsewhere = routing_old && fwspec->param[1] != routing_old - 1; -+ if (routed_elsewhere) { -+ pr_warn("soc int %d already routed to output %d\n", -+ fwspec->param[0], routing_old - 1); -+ break; -+ } -+ } -+ -+ raw_spin_unlock_irqrestore(&irq_lock, flags); -+ -+ return !routed_elsewhere && fwspec->param[1] == output->output_index; -+} -+ - static const struct irq_domain_ops irq_domain_ops = { - .map = intc_map, -+ .select = intc_select, - .xlate = irq_domain_xlate_onecell, - }; - - static void realtek_irq_dispatch(struct irq_desc *desc) - { -+ struct realtek_ictl_output *output = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); -- struct irq_domain *domain; -- unsigned int pending; -+ int cpu = smp_processor_id(); -+ unsigned long pending; -+ unsigned int soc_int; - - chained_irq_enter(chip, desc); -- pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR)); -+ pending = readl(REG(RTL_ICTL_GIMR, cpu)) & readl(REG(RTL_ICTL_GISR, cpu)) -+ & output->child_mask; -+ - if (unlikely(!pending)) { - spurious_interrupt(); - goto out; - } -- domain = irq_desc_get_handler_data(desc); -- generic_handle_irq(irq_find_mapping(domain, __ffs(pending))); -+ -+ for_each_set_bit(soc_int, &pending, RTL_ICTL_NUM_INPUTS) -+ generic_handle_irq(irq_find_mapping(output->domain, soc_int)); -+// generic_handle_domain_irq(output->domain, soc_int); - - out: - chained_irq_exit(chip, desc); - } - --/* -- * SoC interrupts are cascaded to MIPS CPU interrupts according to the -- * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for -- * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts -- * thus go into 4 IRRs. -- */ --static int __init map_interrupts(struct device_node *node, struct irq_domain *domain) -+static int __init setup_parent_interrupts(struct device_node *node, int *parents, -+ unsigned int num_parents) - { -- struct device_node *cpu_ictl; -- const __be32 *imap; -- u32 imaplen, soc_int, cpu_int, tmp, regs[4]; -- int ret, i, irr_regs[] = { -- RTL_ICTL_IRR3, -- RTL_ICTL_IRR2, -- RTL_ICTL_IRR1, -- RTL_ICTL_IRR0, -- }; -- u8 mips_irqs_set; -+ struct realtek_ictl_output *outputs; -+ struct realtek_ictl_output *output; -+ struct irq_domain *domain; -+ unsigned int p; - -- ret = of_property_read_u32(node, "#address-cells", &tmp); -- if (ret || tmp) -- return -EINVAL; -+ outputs = kcalloc(num_parents, sizeof(*outputs), GFP_KERNEL); -+ if (!outputs) -+ return -ENOMEM; - -- imap = of_get_property(node, "interrupt-map", &imaplen); -- if (!imap || imaplen % 3) -- return -EINVAL; -+ for (p = 0; p < num_parents; p++) { -+ output = outputs + p; - -- mips_irqs_set = 0; -- memset(regs, 0, sizeof(regs)); -- for (i = 0; i < imaplen; i += 3 * sizeof(u32)) { -- soc_int = be32_to_cpup(imap); -- if (soc_int > 31) -- return -EINVAL; -- -- cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1)); -- if (!cpu_ictl) -- return -EINVAL; -- ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp); -- if (ret || tmp != 1) -- return -EINVAL; -- of_node_put(cpu_ictl); -- -- cpu_int = be32_to_cpup(imap + 2); -- if (cpu_int > 7) -- return -EINVAL; -- -- if (!(mips_irqs_set & BIT(cpu_int))) { -- irq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch, -- domain); -- mips_irqs_set |= BIT(cpu_int); -- } -+ domain = irq_domain_add_linear(node, RTL_ICTL_NUM_INPUTS, &irq_domain_ops, output); -+ if (!domain) -+ goto domain_err; - -- regs[(soc_int * 4) / 32] |= cpu_int << (soc_int * 4) % 32; -- imap += 3; -- } -+ output->fwnode = of_node_to_fwnode(node); -+ output->output_index = p; -+ output->domain = domain; - -- for (i = 0; i < 4; i++) -- writel(regs[i], REG(irr_regs[i])); -+ irq_set_chained_handler_and_data(parents[p], realtek_irq_dispatch, output); -+ } - - return 0; -+ -+domain_err: -+ while (p--) { -+ irq_set_chained_handler_and_data(parents[p], NULL, NULL); -+ irq_domain_remove(outputs[p].domain); -+ } -+ -+ kfree(outputs); -+ -+ return -ENOMEM; - } - - static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent) - { -- struct irq_domain *domain; -- int ret; -+ int parent_irqs[RTL_ICTL_NUM_OUTPUTS]; -+ struct of_phandle_args oirq; -+ unsigned int num_parents; -+ unsigned int soc_irq; -+ unsigned int p; -+ int cpu; -+ -+ cpumask_clear(&realtek_ictl_cpu_configurable); -+ -+ for (cpu = 0; cpu < NR_CPUS; cpu++) { -+ realtek_ictl_base[cpu] = of_iomap(node, cpu); -+ if (realtek_ictl_base[cpu]) { -+ cpumask_set_cpu(cpu, &realtek_ictl_cpu_configurable); -+ -+ /* Disable all cascaded interrupts and clear routing */ -+ writel(0, REG(RTL_ICTL_GIMR, cpu)); -+ for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) -+ write_irr(REG(RTL_ICTL_IRR0, cpu), soc_irq, 0); -+ } -+ } - -- realtek_ictl_base = of_iomap(node, 0); -- if (!realtek_ictl_base) -+ if (cpumask_empty(&realtek_ictl_cpu_configurable)) - return -ENXIO; - -- /* Disable all cascaded interrupts */ -- writel(0, REG(RTL_ICTL_GIMR)); -+ num_parents = of_irq_count(node); -+ if (num_parents > RTL_ICTL_NUM_OUTPUTS) { -+ pr_err("too many parent interrupts\n"); -+ return -EINVAL; -+ } - -- domain = irq_domain_add_simple(node, 32, 0, -- &irq_domain_ops, NULL); -+ for (p = 0; p < num_parents; p++) -+ parent_irqs[p] = of_irq_get(node, p); - -- ret = map_interrupts(node, domain); -- if (ret) { -- pr_err("invalid interrupt map\n"); -- return ret; -+ if (WARN_ON(!num_parents)) { -+ /* -+ * If DT contains no parent interrupts, assume MIPS CPU IRQ 2 -+ * (HW0) is connected to the first output. This is the case for -+ * all known hardware anyway. "interrupt-map" is deprecated, so -+ * don't bother trying to parse that. -+ * Since this is to account for old devicetrees with one-cell -+ * interrupt specifiers, only one output domain is needed. -+ */ -+ oirq.np = of_find_compatible_node(NULL, NULL, "mti,cpu-interrupt-controller"); -+ if (oirq.np) { -+ oirq.args_count = 1; -+ oirq.args[0] = 2; -+ -+ parent_irqs[0] = irq_create_of_mapping(&oirq); -+ num_parents = 1; -+ } -+ -+ of_node_put(oirq.np); - } - -- return 0; -+ /* Ensure we haven't collected any errors before proceeding */ -+ for (p = 0; p < num_parents; p++) { -+ if (parent_irqs[p] < 0) -+ return parent_irqs[p]; -+ if (!parent_irqs[p]) -+ return -ENODEV; -+ } -+ -+ return setup_parent_interrupts(node, &parent_irqs[0], num_parents); - } - - IRQCHIP_DECLARE(realtek_rtl_intc, "realtek,rtl-intc", realtek_rtl_of_init); diff --git a/target/linux/realtek/patches-5.10/316-otto-gpio-uniprocessor-irq-mask.patch b/target/linux/realtek/patches-5.10/316-otto-gpio-uniprocessor-irq-mask.patch deleted file mode 100644 index 3980875dd4..0000000000 --- a/target/linux/realtek/patches-5.10/316-otto-gpio-uniprocessor-irq-mask.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bde6311569ef25a00c3beaeabfd6b78b19651872 Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Sun, 29 May 2022 19:38:09 +0200 -Subject: [PATCH] realtek: don't unmask non-maskable GPIO IRQs - -On uniprocessor builds, for_each_cpu(cpu, mask) will assume 'mask' -always contains exactly one CPU, and ignore the actual mask contents. -This causes the loop to run, even when it shouldn't on an empty mask, -and tries to access an uninitialised pointer. - -Fix this by wrapping the loop in a cpumask_empty() check, to ensure it -will not run on uniprocessor builds if the CPU mask is empty. - -Fixes: af6cd37f42f3 ("realtek: replace RTL93xx GPIO patches") -Reported-by: INAGAKI Hiroshi -Reported-by: Robert Marko -Tested-by: Robert Marko -Submitted-by: Sander Vanheule ---- - drivers/gpio/gpio-realtek-otto.c | 9 +++++++++++-- - 1 file changed, 11 insertions(+), 2 deletions(-) - ---- a/drivers/gpio/gpio-realtek-otto.c -+++ b/drivers/gpio/gpio-realtek-otto.c -@@ -304,6 +304,7 @@ static int realtek_gpio_irq_set_affinity - static int realtek_gpio_irq_init(struct gpio_chip *gc) - { - struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); -+ void __iomem *irq_cpu_mask; - unsigned int port; - int cpu; - -@@ -311,8 +312,16 @@ static int realtek_gpio_irq_init(struct - realtek_gpio_write_imr(ctrl, port, 0, 0); - realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0)); - -- for_each_cpu(cpu, &ctrl->cpu_irq_maskable) -- iowrite8(GENMASK(7, 0), realtek_gpio_irq_cpu_mask(ctrl, port, cpu)); -+ /* -+ * Uniprocessor builds assume a mask always contains one CPU, -+ * so only start the loop if we have at least one maskable CPU. -+ */ -+ if(!cpumask_empty(&ctrl->cpu_irq_maskable)) { -+ for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { -+ irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu); -+ iowrite8(GENMASK(7, 0), irq_cpu_mask); -+ } -+ } - } - - return 0; diff --git a/target/linux/realtek/patches-5.10/317-gpio-realtek-otto-switch-to-32-bit-I-O.patch b/target/linux/realtek/patches-5.10/317-gpio-realtek-otto-switch-to-32-bit-I-O.patch deleted file mode 100644 index 9c043b7126..0000000000 --- a/target/linux/realtek/patches-5.10/317-gpio-realtek-otto-switch-to-32-bit-I-O.patch +++ /dev/null @@ -1,373 +0,0 @@ -From ee0175b3b44288c74d5292c2a9c2c154f6c0317e Mon Sep 17 00:00:00 2001 -From: Sander Vanheule -Date: Sun, 7 Aug 2022 21:21:15 +0200 -Subject: [PATCH] gpio: realtek-otto: switch to 32-bit I/O - -By using 16-bit I/O on the GPIO peripheral, which is apparently not safe -on MIPS, the IMR can end up containing garbage. This then results in -interrupt triggers for lines that don't have an interrupt handler -associated. The irq_desc lookup fails, and the ISR will not be cleared, -keeping the CPU busy until reboot, or until another IMR operation -restores the correct value. This situation appears to happen very -rarely, for < 0.5% of IMR writes. - -Instead of using 8-bit or 16-bit I/O operations on the 32-bit memory -mapped peripheral registers, switch to using 32-bit I/O only, operating -on the entire bank for all single bit line settings. For 2-bit line -settings, with 16-bit port values, stick to manual (un)packing. - -This issue has been seen on RTL8382M (HPE 1920-16G), RTL8391M (Netgear -GS728TP v2), and RTL8393M (D-Link DGS-1210-52 F3, Zyxel GS1900-48). - -Reported-by: Luiz Angelo Daros de Luca # DGS-1210-52 -Reported-by: Birger Koblitz # GS728TP -Reported-by: Jan Hoffmann # 1920-16G -Fixes: 0d82fb1127fb ("gpio: Add Realtek Otto GPIO support") -Signed-off-by: Sander Vanheule -Cc: Paul Cercueil -Reviewed-by: Linus Walleij -Signed-off-by: Bartosz Golaszewski - -Update patch for missing upstream changes: - - commit a01a40e33499 ("gpio: realtek-otto: Make the irqchip immutable") - - commit dbd1c54fc820 ("gpio: Bulk conversion to generic_handle_domain_irq()") -Signed-off-by: Sander Vanheule - ---- - drivers/gpio/gpio-realtek-otto.c | 166 ++++++++++++++++--------------- - 1 file changed, 85 insertions(+), 81 deletions(-) - ---- a/drivers/gpio/gpio-realtek-otto.c -+++ b/drivers/gpio/gpio-realtek-otto.c -@@ -46,10 +46,20 @@ - * @lock: Lock for accessing the IRQ registers and values - * @intr_mask: Mask for interrupts lines - * @intr_type: Interrupt type selection -+ * @bank_read: Read a bank setting as a single 32-bit value -+ * @bank_write: Write a bank setting as a single 32-bit value -+ * @imr_line_pos: Bit shift of an IRQ line's IMR value. -+ * -+ * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed -+ * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign) -+ * a value from (to) these registers. The IMR register consists of four 16-bit -+ * port values, packed into two 32-bit registers. Use @imr_line_pos to get the -+ * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than -+ * 32 overflow into the second register. - * - * Because the interrupt mask register (IMR) combines the function of IRQ type - * selection and masking, two extra values are stored. @intr_mask is used to -- * mask/unmask the interrupts for a GPIO port, and @intr_type is used to store -+ * mask/unmask the interrupts for a GPIO line, and @intr_type is used to store - * the selected interrupt types. The logical AND of these values is written to - * IMR on changes. - */ -@@ -59,10 +69,11 @@ struct realtek_gpio_ctrl { - void __iomem *cpumask_base; - struct cpumask cpu_irq_maskable; - raw_spinlock_t lock; -- u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; -- u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; -- unsigned int (*port_offset_u8)(unsigned int port); -- unsigned int (*port_offset_u16)(unsigned int port); -+ u8 intr_mask[REALTEK_GPIO_MAX]; -+ u8 intr_type[REALTEK_GPIO_MAX]; -+ u32 (*bank_read)(void __iomem *reg); -+ void (*bank_write)(void __iomem *reg, u32 value); -+ unsigned int (*line_imr_pos)(unsigned int line); - }; - - /* Expand with more flags as devices with other quirks are added */ -@@ -101,14 +112,22 @@ static struct realtek_gpio_ctrl *irq_dat - * port. The two interrupt mask registers store two bits per GPIO, so use u16 - * values. - */ --static unsigned int realtek_gpio_port_offset_u8(unsigned int port) -+static u32 realtek_gpio_bank_read_swapped(void __iomem *reg) -+{ -+ return ioread32be(reg); -+} -+ -+static void realtek_gpio_bank_write_swapped(void __iomem *reg, u32 value) - { -- return port; -+ iowrite32be(value, reg); - } - --static unsigned int realtek_gpio_port_offset_u16(unsigned int port) -+static unsigned int realtek_gpio_line_imr_pos_swapped(unsigned int line) - { -- return 2 * port; -+ unsigned int port_pin = line % 8; -+ unsigned int port = line / 8; -+ -+ return 2 * (8 * (port ^ 1) + port_pin); - } - - /* -@@ -119,64 +138,65 @@ static unsigned int realtek_gpio_port_of - * per GPIO, so use u16 values. The first register contains ports 1 and 0, the - * second ports 3 and 2. - */ --static unsigned int realtek_gpio_port_offset_u8_rev(unsigned int port) -+static u32 realtek_gpio_bank_read(void __iomem *reg) - { -- return 3 - port; -+ return ioread32(reg); - } - --static unsigned int realtek_gpio_port_offset_u16_rev(unsigned int port) -+static void realtek_gpio_bank_write(void __iomem *reg, u32 value) - { -- return 2 * (port ^ 1); -+ iowrite32(value, reg); - } - --static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl, -- unsigned int port, u16 irq_type, u16 irq_mask) -+static unsigned int realtek_gpio_line_imr_pos(unsigned int line) - { -- iowrite16(irq_type & irq_mask, -- ctrl->base + REALTEK_GPIO_REG_IMR + ctrl->port_offset_u16(port)); -+ return 2 * line; - } - --static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, -- unsigned int port, u8 mask) -+static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, u32 mask) - { -- iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); -+ ctrl->bank_write(ctrl->base + REALTEK_GPIO_REG_ISR, mask); - } - --static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port) -+static u32 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl) - { -- return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port)); -+ return ctrl->bank_read(ctrl->base + REALTEK_GPIO_REG_ISR); - } - --/* Set the rising and falling edge mask bits for a GPIO port pin */ --static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value) -+/* Set the rising and falling edge mask bits for a GPIO pin */ -+static void realtek_gpio_update_line_imr(struct realtek_gpio_ctrl *ctrl, unsigned int line) - { -- return (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin; -+ void __iomem *reg = ctrl->base + REALTEK_GPIO_REG_IMR; -+ unsigned int line_shift = ctrl->line_imr_pos(line); -+ unsigned int shift = line_shift % 32; -+ u32 irq_type = ctrl->intr_type[line]; -+ u32 irq_mask = ctrl->intr_mask[line]; -+ u32 reg_val; -+ -+ reg += 4 * (line_shift / 32); -+ reg_val = ioread32(reg); -+ reg_val &= ~(REALTEK_GPIO_IMR_LINE_MASK << shift); -+ reg_val |= (irq_type & irq_mask & REALTEK_GPIO_IMR_LINE_MASK) << shift; -+ iowrite32(reg_val, reg); - } - - static void realtek_gpio_irq_ack(struct irq_data *data) - { - struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); - irq_hw_number_t line = irqd_to_hwirq(data); -- unsigned int port = line / 8; -- unsigned int port_pin = line % 8; - -- realtek_gpio_clear_isr(ctrl, port, BIT(port_pin)); -+ realtek_gpio_clear_isr(ctrl, BIT(line)); - } - - static void realtek_gpio_irq_unmask(struct irq_data *data) - { - struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); - unsigned int line = irqd_to_hwirq(data); -- unsigned int port = line / 8; -- unsigned int port_pin = line % 8; - unsigned long flags; -- u16 m; - - raw_spin_lock_irqsave(&ctrl->lock, flags); -- m = ctrl->intr_mask[port]; -- m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); -- ctrl->intr_mask[port] = m; -- realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); -+ ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK; -+ realtek_gpio_update_line_imr(ctrl, line); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); - } - -@@ -184,16 +204,11 @@ static void realtek_gpio_irq_mask(struct - { - struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); - unsigned int line = irqd_to_hwirq(data); -- unsigned int port = line / 8; -- unsigned int port_pin = line % 8; - unsigned long flags; -- u16 m; - - raw_spin_lock_irqsave(&ctrl->lock, flags); -- m = ctrl->intr_mask[port]; -- m &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); -- ctrl->intr_mask[port] = m; -- realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); -+ ctrl->intr_mask[line] = 0; -+ realtek_gpio_update_line_imr(ctrl, line); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); - } - -@@ -201,10 +216,8 @@ static int realtek_gpio_irq_set_type(str - { - struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); - unsigned int line = irqd_to_hwirq(data); -- unsigned int port = line / 8; -- unsigned int port_pin = line % 8; - unsigned long flags; -- u16 type, t; -+ u8 type; - - switch (flow_type & IRQ_TYPE_SENSE_MASK) { - case IRQ_TYPE_EDGE_FALLING: -@@ -223,11 +236,8 @@ static int realtek_gpio_irq_set_type(str - irq_set_handler_locked(data, handle_edge_irq); - - raw_spin_lock_irqsave(&ctrl->lock, flags); -- t = ctrl->intr_type[port]; -- t &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); -- t |= realtek_gpio_imr_bits(port_pin, type); -- ctrl->intr_type[port] = t; -- realtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]); -+ ctrl->intr_type[line] = type; -+ realtek_gpio_update_line_imr(ctrl, line); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); - - return 0; -@@ -238,31 +248,24 @@ static void realtek_gpio_irq_handler(str - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); - struct irq_chip *irq_chip = irq_desc_get_chip(desc); -- unsigned int lines_done; -- unsigned int port_pin_count; - unsigned int irq; - unsigned long status; - int offset; - - chained_irq_enter(irq_chip, desc); - -- for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) { -- status = realtek_gpio_read_isr(ctrl, lines_done / 8); -- port_pin_count = min(gc->ngpio - lines_done, 8U); -- for_each_set_bit(offset, &status, port_pin_count) { -- irq = irq_find_mapping(gc->irq.domain, offset + lines_done); -- generic_handle_irq(irq); -- } -+ status = realtek_gpio_read_isr(ctrl); -+ for_each_set_bit(offset, &status, gc->ngpio) { -+ irq = irq_find_mapping(gc->irq.domain, offset); -+ generic_handle_irq(irq); - } - - chained_irq_exit(irq_chip, desc); - } - --static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, -- unsigned int port, int cpu) -+static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, int cpu) - { -- return ctrl->cpumask_base + ctrl->port_offset_u8(port) + -- REALTEK_GPIO_PORTS_PER_BANK * cpu; -+ return ctrl->cpumask_base + REALTEK_GPIO_PORTS_PER_BANK * cpu; - } - - static int realtek_gpio_irq_set_affinity(struct irq_data *data, -@@ -270,12 +273,10 @@ static int realtek_gpio_irq_set_affinity - { - struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); - unsigned int line = irqd_to_hwirq(data); -- unsigned int port = line / 8; -- unsigned int port_pin = line % 8; - void __iomem *irq_cpu_mask; - unsigned long flags; - int cpu; -- u8 v; -+ u32 v; - - if (!ctrl->cpumask_base) - return -ENXIO; -@@ -283,15 +284,15 @@ static int realtek_gpio_irq_set_affinity - raw_spin_lock_irqsave(&ctrl->lock, flags); - - for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { -- irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu); -- v = ioread8(irq_cpu_mask); -+ irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu); -+ v = ctrl->bank_read(irq_cpu_mask); - - if (cpumask_test_cpu(cpu, dest)) -- v |= BIT(port_pin); -+ v |= BIT(line); - else -- v &= ~BIT(port_pin); -+ v &= ~BIT(line); - -- iowrite8(v, irq_cpu_mask); -+ ctrl->bank_write(irq_cpu_mask, v); - } - - raw_spin_unlock_irqrestore(&ctrl->lock, flags); -@@ -305,22 +306,23 @@ static int realtek_gpio_irq_init(struct - { - struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); - void __iomem *irq_cpu_mask; -- unsigned int port; -+ u32 mask_all = GENMASK(gc->ngpio - 1, 0); -+ unsigned int line; - int cpu; - -- for (port = 0; (port * 8) < gc->ngpio; port++) { -- realtek_gpio_write_imr(ctrl, port, 0, 0); -- realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0)); -- -- /* -- * Uniprocessor builds assume a mask always contains one CPU, -- * so only start the loop if we have at least one maskable CPU. -- */ -- if(!cpumask_empty(&ctrl->cpu_irq_maskable)) { -- for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { -- irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, port, cpu); -- iowrite8(GENMASK(7, 0), irq_cpu_mask); -- } -+ for (line = 0; line < gc->ngpio; line++) -+ realtek_gpio_update_line_imr(ctrl, line); -+ -+ realtek_gpio_clear_isr(ctrl, mask_all); -+ -+ /* -+ * Uniprocessor builds assume a mask always contains one CPU, -+ * so only start the loop if we have at least one maskable CPU. -+ */ -+ if(!cpumask_empty(&ctrl->cpu_irq_maskable)) { -+ for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { -+ irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu); -+ ctrl->bank_write(irq_cpu_mask, mask_all); - } - } - -@@ -393,12 +395,14 @@ static int realtek_gpio_probe(struct pla - - if (dev_flags & GPIO_PORTS_REVERSED) { - bgpio_flags = 0; -- ctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev; -- ctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev; -+ ctrl->bank_read = realtek_gpio_bank_read; -+ ctrl->bank_write = realtek_gpio_bank_write; -+ ctrl->line_imr_pos = realtek_gpio_line_imr_pos; - } else { - bgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; -- ctrl->port_offset_u8 = realtek_gpio_port_offset_u8; -- ctrl->port_offset_u16 = realtek_gpio_port_offset_u16; -+ ctrl->bank_read = realtek_gpio_bank_read_swapped; -+ ctrl->bank_write = realtek_gpio_bank_write_swapped; -+ ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped; - } - - err = bgpio_init(&ctrl->gc, dev, 4, diff --git a/target/linux/realtek/patches-5.10/318-add-rtl83xx-clk-support.patch b/target/linux/realtek/patches-5.10/318-add-rtl83xx-clk-support.patch deleted file mode 100644 index 94c4230835..0000000000 --- a/target/linux/realtek/patches-5.10/318-add-rtl83xx-clk-support.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 800d5fb3c6a16661932c932bacd660e38d06b727 Mon Sep 17 00:00:00 2001 -From: Markus Stockhausen -Date: Thu, 25 Aug 2022 08:22:36 +0200 -Subject: [PATCH] realtek: add patch to enable new clock driver in kernel - -Allow building the clock driver with kernel config options. - -Submitted-by: Markus Stockhausen ---- - drivers/clk/Kconfig | 1 + - drivers/clk/Makefile | 1 + - 2 files changed, 2 insertions(+) - ---- a/drivers/clk/Kconfig -+++ b/drivers/clk/Kconfig -@@ -372,6 +372,7 @@ source "drivers/clk/mediatek/Kconfig" - source "drivers/clk/meson/Kconfig" - source "drivers/clk/mvebu/Kconfig" - source "drivers/clk/qcom/Kconfig" -+source "drivers/clk/realtek/Kconfig" - source "drivers/clk/renesas/Kconfig" - source "drivers/clk/rockchip/Kconfig" - source "drivers/clk/samsung/Kconfig" ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_NXP) += nxp/ - obj-$(CONFIG_MACH_PISTACHIO) += pistachio/ - obj-$(CONFIG_COMMON_CLK_PXA) += pxa/ - obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ -+obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/ - obj-y += renesas/ - obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ - obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ diff --git a/target/linux/realtek/patches-5.10/319-irqchip-irq-realtek-rtl-fix-VPE-affinity.patch b/target/linux/realtek/patches-5.10/319-irqchip-irq-realtek-rtl-fix-VPE-affinity.patch deleted file mode 100644 index bb95e7103a..0000000000 --- a/target/linux/realtek/patches-5.10/319-irqchip-irq-realtek-rtl-fix-VPE-affinity.patch +++ /dev/null @@ -1,159 +0,0 @@ -From 2cd00b51470a30198b048a5fca48a04db77e29cc Mon Sep 17 00:00:00 2001 -From: INAGAKI Hiroshi -Date: Fri, 21 May 2021 23:16:37 +0900 -Subject: [PATCH] realtek: backport irq-realtek-rtl driver from 5.12 to 5.10 - -This patch backports "irq-realtek-rtl" driver to Kernel 5.10 from 5.12. -"MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X" -is used in OpenWrt, so update the dependency by the additional patch. - -Submitted-by: INAGAKI Hiroshi ---- - drivers/irqchip/irq-realtek-rtl.c | 38 +++++++++++------ - 1 files changed, 58 insertions(+), 20 deletions(-) - ---- a/drivers/irqchip/irq-realtek-rtl.c -+++ b/drivers/irqchip/irq-realtek-rtl.c -@@ -28,6 +28,7 @@ static DEFINE_RAW_SPINLOCK(irq_lock); - - #define REG(offset, cpu) (realtek_ictl_base[cpu] + offset) - -+static u32 realtek_ictl_unmask[NR_CPUS]; - static void __iomem *realtek_ictl_base[NR_CPUS]; - static cpumask_t realtek_ictl_cpu_configurable; - -@@ -41,11 +42,29 @@ struct realtek_ictl_output { - }; - - /* -- * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numbering, -- * placing IRQ 31 in the first four bits. A routing value of '0' means the -- * interrupt is left disconnected. Routing values {1..15} connect to output -- * lines {0..14}. -+ * Per CPU we have a set of 5 registers that determine interrupt handling for -+ * 32 external interrupts. GIMR (enable/disable interrupt) plus IRR0-IRR3 that -+ * contain "routing" or "priority" values. GIMR uses one bit for each interrupt -+ * and IRRx store 4 bits per interrupt. Realtek uses inverted numbering, -+ * placing IRQ 31 in the first four bits. The register combinations give the -+ * following results for a single interrupt in the wild: -+ * -+ * a) GIMR = 0 / IRRx > 0 -> no interrupts -+ * b) GIMR = 0 / IRRx = 0 -> no interrupts -+ * c) GIMR = 1 / IRRx > 0 -> interrupts -+ * d) GIMR = 1 / IRRx = 0 -> rare interrupts in SMP environment -+ * -+ * Combination d) seems to trigger interrupts only on a VPE if the other VPE -+ * has GIMR = 0 and IRRx > 0. E.g. busy without interrupts allowed. To provide -+ * IRQ balancing features in SMP this driver will handle the registers as -+ * follows: -+ * -+ * 1) set IRRx > 0 for VPE where the interrupt is desired -+ * 2) set IRRx = 0 for VPE where the interrupt is not desired -+ * 3) set both GIMR = 0 to mask (disabled) interrupt -+ * 4) set GIMR = 1 to unmask (enable) interrupt but only for VPE where IRRx > 0 - */ -+ - #define IRR_OFFSET(idx) (4 * (3 - (idx * 4) / 32)) - #define IRR_SHIFT(idx) ((idx * 4) % 32) - -@@ -65,19 +84,33 @@ static inline void write_irr(void __iome - writel(irr, irr0 + offset); - } - -+static inline void enable_gimr(int hwirq, int cpu) -+{ -+ u32 value; -+ -+ value = readl(REG(RTL_ICTL_GIMR, cpu)); -+ value |= (BIT(hwirq) & realtek_ictl_unmask[cpu]); -+ writel(value, REG(RTL_ICTL_GIMR, cpu)); -+} -+ -+static inline void disable_gimr(int hwirq, int cpu) -+{ -+ u32 value; -+ -+ value = readl(REG(RTL_ICTL_GIMR, cpu)); -+ value &= ~BIT(hwirq); -+ writel(value, REG(RTL_ICTL_GIMR, cpu)); -+} -+ - static void realtek_ictl_unmask_irq(struct irq_data *i) - { - unsigned long flags; -- u32 value; - int cpu; - - raw_spin_lock_irqsave(&irq_lock, flags); - -- for_each_cpu(cpu, &realtek_ictl_cpu_configurable) { -- value = readl(REG(RTL_ICTL_GIMR, cpu)); -- value |= BIT(i->hwirq); -- writel(value, REG(RTL_ICTL_GIMR, cpu)); -- } -+ for_each_cpu(cpu, &realtek_ictl_cpu_configurable) -+ enable_gimr(i->hwirq, cpu); - - raw_spin_unlock_irqrestore(&irq_lock, flags); - } -@@ -85,16 +118,12 @@ static void realtek_ictl_unmask_irq(stru - static void realtek_ictl_mask_irq(struct irq_data *i) - { - unsigned long flags; -- u32 value; - int cpu; - - raw_spin_lock_irqsave(&irq_lock, flags); - -- for_each_cpu(cpu, &realtek_ictl_cpu_configurable) { -- value = readl(REG(RTL_ICTL_GIMR, cpu)); -- value &= ~BIT(i->hwirq); -- writel(value, REG(RTL_ICTL_GIMR, cpu)); -- } -+ for_each_cpu(cpu, &realtek_ictl_cpu_configurable) -+ disable_gimr(i->hwirq, cpu); - - raw_spin_unlock_irqrestore(&irq_lock, flags); - } -@@ -116,11 +145,17 @@ static int __maybe_unused realtek_ictl_i - cpumask_and(&cpu_enable, &cpu_configure, dest); - cpumask_andnot(&cpu_disable, &cpu_configure, dest); - -- for_each_cpu(cpu, &cpu_disable) -+ for_each_cpu(cpu, &cpu_disable) { - write_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, 0); -+ realtek_ictl_unmask[cpu] &= ~BIT(i->hwirq); -+ disable_gimr(i->hwirq, cpu); -+ } - -- for_each_cpu(cpu, &cpu_enable) -+ for_each_cpu(cpu, &cpu_enable) { - write_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, output->output_index + 1); -+ realtek_ictl_unmask[cpu] |= BIT(i->hwirq); -+ enable_gimr(i->hwirq, cpu); -+ } - - irq_data_update_effective_affinity(i, &cpu_enable); - -@@ -149,6 +184,7 @@ static int intc_map(struct irq_domain *d - - output->child_mask |= BIT(hw); - write_irr(REG(RTL_ICTL_IRR0, 0), hw, output->output_index + 1); -+ realtek_ictl_unmask[0] |= BIT(hw); - - raw_spin_unlock_irqrestore(&irq_lock, flags); - -@@ -279,9 +315,11 @@ static int __init realtek_rtl_of_init(st - cpumask_set_cpu(cpu, &realtek_ictl_cpu_configurable); - - /* Disable all cascaded interrupts and clear routing */ -- writel(0, REG(RTL_ICTL_GIMR, cpu)); -- for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) -+ for (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++) { - write_irr(REG(RTL_ICTL_IRR0, cpu), soc_irq, 0); -+ realtek_ictl_unmask[cpu] &= ~BIT(soc_irq); -+ disable_gimr(soc_irq, cpu); -+ } - } - } - diff --git a/target/linux/realtek/patches-5.10/700-net-dsa-add-support-for-rtl838x-switch.patch b/target/linux/realtek/patches-5.10/700-net-dsa-add-support-for-rtl838x-switch.patch deleted file mode 100644 index f97ea94d9b..0000000000 --- a/target/linux/realtek/patches-5.10/700-net-dsa-add-support-for-rtl838x-switch.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: net: dsa: Add support for rtl838x switch - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - drivers/net/dsa/rtl83xx/Kconfig | 2 ++ - drivers/net/dsa/rtl83xx/Makefile | 1 + - 2 files changed, 3 insertions(+) - ---- a/drivers/net/dsa/Kconfig -+++ b/drivers/net/dsa/Kconfig -@@ -68,6 +68,8 @@ config NET_DSA_QCA8K - This enables support for the Qualcomm Atheros QCA8K Ethernet - switch chips. - -+source "drivers/net/dsa/rtl83xx/Kconfig" -+ - config NET_DSA_REALTEK_SMI - tristate "Realtek SMI Ethernet switch family support" - depends on NET_DSA ---- a/drivers/net/dsa/Makefile -+++ b/drivers/net/dsa/Makefile -@@ -23,3 +23,4 @@ obj-y += mv88e6xxx/ - obj-y += ocelot/ - obj-y += qca/ - obj-y += sja1105/ -+obj-y += rtl83xx/ diff --git a/target/linux/realtek/patches-5.10/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch b/target/linux/realtek/patches-5.10/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch deleted file mode 100644 index 27299f17de..0000000000 --- a/target/linux/realtek/patches-5.10/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: net: dsa: Add rtl838x support for tag trailer - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - net/dsa/tag_trailer.c | 16 +++++++++++++- - 1 file changed, 17 insertions(+), 1 deletion(-) - ---- a/net/dsa/tag_trailer.c -+++ b/net/dsa/tag_trailer.c -@@ -17,7 +17,12 @@ static struct sk_buff *trailer_xmit(stru - - trailer = skb_put(skb, 4); - trailer[0] = 0x80; -+ -+#ifdef CONFIG_NET_DSA_RTL83XX -+ trailer[1] = dp->index; -+#else - trailer[1] = 1 << dp->index; -+#endif /* CONFIG_NET_DSA_RTL838X */ - trailer[2] = 0x10; - trailer[3] = 0x00; - -@@ -34,12 +39,23 @@ static struct sk_buff *trailer_rcv(struc - return NULL; - - trailer = skb_tail_pointer(skb) - 4; -+ -+#ifdef CONFIG_NET_DSA_RTL83XX -+ if (trailer[0] != 0x80 || (trailer[1] & 0x80) != 0x00 || -+ (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00) -+ return NULL; -+ -+ if (trailer[1] & 0x40) -+ skb->offload_fwd_mark = 1; -+ -+ source_port = trailer[1] & 0x3f; -+#else - if (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 || - (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00) - return NULL; - - source_port = trailer[1] & 7; -- -+#endif - skb->dev = dsa_master_find_slave(dev, 0, source_port); - if (!skb->dev) - return NULL; diff --git a/target/linux/realtek/patches-5.10/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch b/target/linux/realtek/patches-5.10/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch deleted file mode 100644 index 63991d373c..0000000000 --- a/target/linux/realtek/patches-5.10/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: net: dsa: Increase max ports for rtl838x - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - include/linux/platform_data/dsa.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/include/linux/platform_data/dsa.h -+++ b/include/linux/platform_data/dsa.h -@@ -6,7 +6,7 @@ struct device; - struct net_device; - - #define DSA_MAX_SWITCHES 4 --#define DSA_MAX_PORTS 12 -+#define DSA_MAX_PORTS 54 - #define DSA_RTABLE_NONE -1 - - struct dsa_chip_data { diff --git a/target/linux/realtek/patches-5.10/702-net-ethernet-add-support-for-rtl838x-ethernet.patch b/target/linux/realtek/patches-5.10/702-net-ethernet-add-support-for-rtl838x-ethernet.patch deleted file mode 100644 index 9f50e8b564..0000000000 --- a/target/linux/realtek/patches-5.10/702-net-ethernet-add-support-for-rtl838x-ethernet.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: net: ethernet: Add support for RTL838x ethernet - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - drivers/net/ethernet/Kconfig | 7 +- - drivers/net/ethernet/Makefile | 1 + - 2 files changed, 8 insertions(+) - ---- a/drivers/net/ethernet/Kconfig -+++ b/drivers/net/ethernet/Kconfig -@@ -163,6 +163,13 @@ source "drivers/net/ethernet/rdc/Kconfig - source "drivers/net/ethernet/realtek/Kconfig" - source "drivers/net/ethernet/renesas/Kconfig" - source "drivers/net/ethernet/rocker/Kconfig" -+ -+config NET_RTL838X -+ tristate "Realtek rtl838x Ethernet MAC support" -+ depends on RTL83XX -+ help -+ Say Y here if you want to use the Realtek rtl838x Gbps Ethernet MAC. -+ - source "drivers/net/ethernet/samsung/Kconfig" - source "drivers/net/ethernet/seeq/Kconfig" - source "drivers/net/ethernet/sfc/Kconfig" ---- a/drivers/net/ethernet/Makefile -+++ b/drivers/net/ethernet/Makefile -@@ -75,6 +75,7 @@ obj-$(CONFIG_NET_VENDOR_REALTEK) += real - obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/ - obj-$(CONFIG_NET_VENDOR_RDC) += rdc/ - obj-$(CONFIG_NET_VENDOR_ROCKER) += rocker/ -+obj-$(CONFIG_NET_RTL838X) += rtl838x_eth.o - obj-$(CONFIG_NET_VENDOR_SAMSUNG) += samsung/ - obj-$(CONFIG_NET_VENDOR_SEEQ) += seeq/ - obj-$(CONFIG_NET_VENDOR_SILAN) += silan/ diff --git a/target/linux/realtek/patches-5.10/703-include-linux-add-phy-ops-for-rtl838x.patch b/target/linux/realtek/patches-5.10/703-include-linux-add-phy-ops-for-rtl838x.patch deleted file mode 100644 index 8f68dd4e88..0000000000 --- a/target/linux/realtek/patches-5.10/703-include-linux-add-phy-ops-for-rtl838x.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: phy: Add PHY ops for rtl838x EEE - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - include/linux/phy.h | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -885,6 +885,10 @@ struct phy_driver { - int (*get_sqi)(struct phy_device *dev); - /** @get_sqi_max: Get the maximum signal quality indication */ - int (*get_sqi_max)(struct phy_device *dev); -+ int (*get_port)(struct phy_device *dev); -+ int (*set_port)(struct phy_device *dev, int port); -+ int (*get_eee)(struct phy_device *dev, struct ethtool_eee *e); -+ int (*set_eee)(struct phy_device *dev, struct ethtool_eee *e); - }; - #define to_phy_driver(d) container_of(to_mdio_common_driver(d), \ - struct phy_driver, mdiodrv) diff --git a/target/linux/realtek/patches-5.10/704-drivers-net-phy-eee-support-for-rtl838x.patch b/target/linux/realtek/patches-5.10/704-drivers-net-phy-eee-support-for-rtl838x.patch deleted file mode 100644 index c46be91fe0..0000000000 --- a/target/linux/realtek/patches-5.10/704-drivers-net-phy-eee-support-for-rtl838x.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: net: phy: EEE support for rtl838x - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - drivers/net/phy/phylink. | 14 +++++++++++-- - 1 file changed, 12 insertions(+), 2 deletions(-) - ---- a/drivers/net/phy/phylink.c -+++ b/drivers/net/phy/phylink.c -@@ -1449,6 +1449,11 @@ int phylink_ethtool_ksettings_set(struct - * the presence of a PHY, this should not be changed as that - * should be determined from the media side advertisement. - */ -+ if (pl->phydev->drv->get_port && pl->phydev->drv->set_port) { -+ if(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) { -+ pl->phydev->drv->set_port(pl->phydev, kset->base.port); -+ } -+ } - return phy_ethtool_ksettings_set(pl->phydev, kset); - } - -@@ -1750,8 +1755,11 @@ int phylink_ethtool_get_eee(struct phyli - - ASSERT_RTNL(); - -- if (pl->phydev) -+ if (pl->phydev) { -+ if (pl->phydev->drv->get_eee) -+ return pl->phydev->drv->get_eee(pl->phydev, eee); - ret = phy_ethtool_get_eee(pl->phydev, eee); -+ } - - return ret; - } -@@ -1768,8 +1776,11 @@ int phylink_ethtool_set_eee(struct phyli - - ASSERT_RTNL(); - -- if (pl->phydev) -+ if (pl->phydev) { -+ if (pl->phydev->drv->set_eee) -+ return pl->phydev->drv->set_eee(pl->phydev, eee); - ret = phy_ethtool_set_eee(pl->phydev, eee); -+ } - - return ret; - } diff --git a/target/linux/realtek/patches-5.10/704-include-linux-add-phy-hsgmii-mode.patch b/target/linux/realtek/patches-5.10/704-include-linux-add-phy-hsgmii-mode.patch deleted file mode 100644 index 442bff82fa..0000000000 --- a/target/linux/realtek/patches-5.10/704-include-linux-add-phy-hsgmii-mode.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 9d9bf16aa8d966834ac1280f96c37d22552c33d1 Mon Sep 17 00:00:00 2001 -From: Birger Koblitz -Date: Wed, 8 Sep 2021 16:13:18 +0200 -Subject: phy: Add PHY hsgmii mode - -This adds RTL93xx-specific MAC configuration routines that allow also configuration -of 10GBit links for phylink. There is support for the Realtek-specific HISGMI -protocol. - -Submitted-by: Birger Koblitz ---- - include/linux/phy.h | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -134,6 +134,7 @@ typedef enum { - PHY_INTERFACE_MODE_XGMII, - PHY_INTERFACE_MODE_XLGMII, - PHY_INTERFACE_MODE_MOCA, -+ PHY_INTERFACE_MODE_HSGMII, - PHY_INTERFACE_MODE_QSGMII, - PHY_INTERFACE_MODE_TRGMII, - PHY_INTERFACE_MODE_100BASEX, -@@ -201,6 +202,8 @@ static inline const char *phy_modes(phy_ - return "xlgmii"; - case PHY_INTERFACE_MODE_MOCA: - return "moca"; -+ case PHY_INTERFACE_MODE_HSGMII: -+ return "hsgmii"; - case PHY_INTERFACE_MODE_QSGMII: - return "qsgmii"; - case PHY_INTERFACE_MODE_TRGMII: diff --git a/target/linux/realtek/patches-5.10/705-add-rtl-phy.patch b/target/linux/realtek/patches-5.10/705-add-rtl-phy.patch deleted file mode 100644 index 47041262fc..0000000000 --- a/target/linux/realtek/patches-5.10/705-add-rtl-phy.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 89f71ebb355c624320c2b0ace8ae9488ff53cbeb Mon Sep 17 00:00:00 2001 -From: Birger Koblitz -Date: Tue, 5 Jan 2021 20:40:52 +0100 -Subject: PHY: Add realtek PHY - -This fixes the build problems for the REALTEK target by adding a proper -configuration option for the phy module. - -Submitted-by: Birger Koblitz ---- - drivers/net/phy/Kconfig | 6 ++++++ - drivers/net/phy/Makefile | 1 + - 2 files changed, 7 insertions(+) - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -330,6 +330,12 @@ config REALTEK_PHY - help - Supports the Realtek 821x PHY. - -+config REALTEK_SOC_PHY -+ tristate "Realtek SoC PHYs" -+ depends on RTL83XX -+ help -+ Supports the PHYs found in combination with Realtek Switch SoCs -+ - config RENESAS_PHY - tristate "Renesas PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -89,6 +89,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o - obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o - obj-$(CONFIG_QSEMI_PHY) += qsemi.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o -+obj-$(CONFIG_REALTEK_SOC_PHY) += rtl83xx-phy.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o - obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o - obj-$(CONFIG_SMSC_PHY) += smsc.o diff --git a/target/linux/realtek/patches-5.10/705-include-linux-phy-increase-phy-address-number-for-rtl839x.patch b/target/linux/realtek/patches-5.10/705-include-linux-phy-increase-phy-address-number-for-rtl839x.patch deleted file mode 100644 index bba6fd7182..0000000000 --- a/target/linux/realtek/patches-5.10/705-include-linux-phy-increase-phy-address-number-for-rtl839x.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 26 Nov 2020 12:02:21 +0100 -Subject: PHY: Increase max PHY adddress number - -* rename the target to realtek -* add refactored DSA driver -* add latest gpio driver -* lots of arch cleanups -* new irq driver -* additional boards - -Submitted-by: Bert Vermeulen -Submitted-by: Birger Koblitz -Submitted-by: Sander Vanheule -Submitted-by: Bjørn Mork -Submitted-by: John Crispin ---- - include/linux/phy.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -233,7 +233,7 @@ static inline const char *phy_modes(phy_ - #define PHY_INIT_TIMEOUT 100000 - #define PHY_FORCE_TIMEOUT 10 - --#define PHY_MAX_ADDR 32 -+#define PHY_MAX_ADDR 64 - - /* Used when trying to connect to a specific phy (mii bus id:phy device id) */ - #define PHY_ID_FMT "%s:%02x" diff --git a/target/linux/realtek/patches-5.10/708-brflood-api.patch b/target/linux/realtek/patches-5.10/708-brflood-api.patch deleted file mode 100644 index 2716933ae7..0000000000 --- a/target/linux/realtek/patches-5.10/708-brflood-api.patch +++ /dev/null @@ -1,162 +0,0 @@ -From afa3ab54c03d5126b14651f367b38165fab5b3cc Mon Sep 17 00:00:00 2001 -From: Birger Koblitz -Date: Tue, 18 Jan 2022 17:18:43 +0100 -Subject: net: brflood API - -Adds the DSA API for bridge configuration (flooding, L2 learning, -and aging) offload as found in Linux 5.12 so that we can implement -it in our drivver. - -Submitted-by: Sebastian Gottschall -Submitted-by: Birger Koblitz ---- - include/net/dsa.h | 6 +++++++-- - net/dsa/dsa_priv.h | 6 +++--- - net/dsa/port.c | 28 ++++++++---- - net/dsa/slave.c | 6 +++--- - 4 file changed, 29 insertions(+), 13 deletions(-) - ---- a/include/net/dsa.h -+++ b/include/net/dsa.h -@@ -552,8 +552,14 @@ struct dsa_switch_ops { - void (*port_stp_state_set)(struct dsa_switch *ds, int port, - u8 state); - void (*port_fast_age)(struct dsa_switch *ds, int port); -- int (*port_egress_floods)(struct dsa_switch *ds, int port, -- bool unicast, bool multicast); -+ int (*port_pre_bridge_flags)(struct dsa_switch *ds, int port, -+ unsigned long flags, -+ struct netlink_ext_ack *extack); -+ int (*port_bridge_flags)(struct dsa_switch *ds, int port, -+ unsigned long flags, -+ struct netlink_ext_ack *extack); -+ int (*port_set_mrouter)(struct dsa_switch *ds, int port, bool mrouter, -+ struct netlink_ext_ack *extack); - - /* - * VLAN support ---- a/net/dsa/dsa_priv.h -+++ b/net/dsa/dsa_priv.h -@@ -167,11 +167,11 @@ int dsa_port_mdb_add(const struct dsa_po - int dsa_port_mdb_del(const struct dsa_port *dp, - const struct switchdev_obj_port_mdb *mdb); - int dsa_port_pre_bridge_flags(const struct dsa_port *dp, unsigned long flags, -- struct switchdev_trans *trans); -+ struct switchdev_trans *trans, struct netlink_ext_ack *extack); - int dsa_port_bridge_flags(const struct dsa_port *dp, unsigned long flags, -- struct switchdev_trans *trans); -+ struct switchdev_trans *trans, struct netlink_ext_ack *extack); - int dsa_port_mrouter(struct dsa_port *dp, bool mrouter, -- struct switchdev_trans *trans); -+ struct switchdev_trans *trans, struct netlink_ext_ack *extack); - int dsa_port_vlan_add(struct dsa_port *dp, - const struct switchdev_obj_port_vlan *vlan, - struct switchdev_trans *trans); ---- a/net/dsa/port.c -+++ b/net/dsa/port.c -@@ -145,7 +145,7 @@ int dsa_port_bridge_join(struct dsa_port - int err; - - /* Set the flooding mode before joining the port in the switch */ -- err = dsa_port_bridge_flags(dp, BR_FLOOD | BR_MCAST_FLOOD, NULL); -+ err = dsa_port_bridge_flags(dp, BR_FLOOD | BR_MCAST_FLOOD, NULL, NULL); - if (err) - return err; - -@@ -158,7 +158,7 @@ int dsa_port_bridge_join(struct dsa_port - - /* The bridging is rolled back on error */ - if (err) { -- dsa_port_bridge_flags(dp, 0, NULL); -+ dsa_port_bridge_flags(dp, 0, NULL, NULL); - dp->bridge_dev = NULL; - } - -@@ -185,7 +185,7 @@ void dsa_port_bridge_leave(struct dsa_po - pr_err("DSA: failed to notify DSA_NOTIFIER_BRIDGE_LEAVE\n"); - - /* Port is leaving the bridge, disable flooding */ -- dsa_port_bridge_flags(dp, 0, NULL); -+ dsa_port_bridge_flags(dp, 0, NULL, NULL); - - /* Port left the bridge, put in BR_STATE_DISABLED by the bridge layer, - * so allow it to be in BR_STATE_FORWARDING to be kept functional -@@ -333,44 +333,44 @@ int dsa_port_ageing_time(struct dsa_port - } - - int dsa_port_pre_bridge_flags(const struct dsa_port *dp, unsigned long flags, -- struct switchdev_trans *trans) -+ struct switchdev_trans *trans, struct netlink_ext_ack *extack) - { - struct dsa_switch *ds = dp->ds; - -- if (!ds->ops->port_egress_floods || -- (flags & ~(BR_FLOOD | BR_MCAST_FLOOD))) -+ if (!ds->ops->port_pre_bridge_flags) - return -EINVAL; - -- return 0; -+ return ds->ops->port_pre_bridge_flags(ds, dp->index, flags, extack); - } - - int dsa_port_bridge_flags(const struct dsa_port *dp, unsigned long flags, -- struct switchdev_trans *trans) -+ struct switchdev_trans *trans, struct netlink_ext_ack *extack) - { - struct dsa_switch *ds = dp->ds; -- int port = dp->index; -- int err = 0; - - if (switchdev_trans_ph_prepare(trans)) - return 0; - -- if (ds->ops->port_egress_floods) -- err = ds->ops->port_egress_floods(ds, port, flags & BR_FLOOD, -- flags & BR_MCAST_FLOOD); -+ if (!ds->ops->port_bridge_flags) -+ return -EINVAL; -+ -+ return ds->ops->port_bridge_flags(ds, dp->index, flags, extack); - -- return err; - } - - int dsa_port_mrouter(struct dsa_port *dp, bool mrouter, -- struct switchdev_trans *trans) -+ struct switchdev_trans *trans, -+ struct netlink_ext_ack *extack) - { - struct dsa_switch *ds = dp->ds; -- int port = dp->index; - - if (switchdev_trans_ph_prepare(trans)) -- return ds->ops->port_egress_floods ? 0 : -EOPNOTSUPP; -+ return ds->ops->port_set_mrouter ? 0 : -EOPNOTSUPP; -+ -+ if (!ds->ops->port_set_mrouter) -+ return -EOPNOTSUPP; - -- return ds->ops->port_egress_floods(ds, port, true, mrouter); -+ return ds->ops->port_set_mrouter(ds, dp->index, mrouter, extack); - } - - int dsa_port_mtu_change(struct dsa_port *dp, int new_mtu, ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -290,13 +290,13 @@ static int dsa_slave_port_attr_set(struc - break; - case SWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS: - ret = dsa_port_pre_bridge_flags(dp, attr->u.brport_flags, -- trans); -+ trans, NULL); - break; - case SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS: -- ret = dsa_port_bridge_flags(dp, attr->u.brport_flags, trans); -+ ret = dsa_port_bridge_flags(dp, attr->u.brport_flags, trans, NULL); - break; - case SWITCHDEV_ATTR_ID_BRIDGE_MROUTER: -- ret = dsa_port_mrouter(dp->cpu_dp, attr->u.mrouter, trans); -+ ret = dsa_port_mrouter(dp->cpu_dp, attr->u.mrouter, trans, NULL); - break; - default: - ret = -EOPNOTSUPP; diff --git a/target/linux/realtek/patches-5.10/709-lag-offloading.patch b/target/linux/realtek/patches-5.10/709-lag-offloading.patch deleted file mode 100644 index f84687ff4a..0000000000 --- a/target/linux/realtek/patches-5.10/709-lag-offloading.patch +++ /dev/null @@ -1,781 +0,0 @@ -From afa3ab54c03d5126b14651f367b38165fab5b3cc Mon Sep 17 00:00:00 2001 -From: Birger Koblitz -Date: Tue, 18 Jan 2022 17:18:43 +0100 -Subject: [PATCH] realtek: Backport bridge configuration for DSA - -Adds the DSA API for bridge configuration (flooding, L2 learning, -and aging) offload as found in Linux 5.12 so that we can implement -it in our drivver. - -Submitted-by: Sebastian Gottschall -Submitted-by: Birger Koblitz ---- - drivers/net/bonding/bond_main.c | 2 ++ - include/net/dsa.h | 79 ++++++++++++++++- - net/dsa/dsa2.c | 88 +++++++++++++++++++ - net/dsa/dsa_priv.h | 74 ++++++++++++++ - net/dsa/port.c | 92 ++++++++++++++++++++ - net/dsa/slave.c | 88 ++++++++++++++++--- - net/dsa/switch.c | 49 ++++++++++ - net/sda/tag_dsa.c | 13 +++++- - 8 file changed, 460 insertions(+), 25 deletions(-) - ---- a/drivers/net/bonding/bond_main.c -+++ b/drivers/net/bonding/bond_main.c -@@ -2045,6 +2045,8 @@ int bond_enslave(struct net_device *bond - goto err_unregister; - } - -+ bond_lower_state_changed(new_slave); -+ - res = bond_sysfs_slave_add(new_slave); - if (res) { - slave_dbg(bond_dev, slave_dev, "Error %d calling bond_sysfs_slave_add\n", res); ---- a/include/net/dsa.h -+++ b/include/net/dsa.h -@@ -149,8 +149,41 @@ struct dsa_switch_tree { - - /* List of DSA links composing the routing table */ - struct list_head rtable; -+ -+ /* Maps offloaded LAG netdevs to a zero-based linear ID for -+ * drivers that need it. -+ */ -+ struct net_device **lags; -+ unsigned int lags_len; - }; - -+#define dsa_lags_foreach_id(_id, _dst) \ -+ for ((_id) = 0; (_id) < (_dst)->lags_len; (_id)++) \ -+ if ((_dst)->lags[(_id)]) -+ -+#define dsa_lag_foreach_port(_dp, _dst, _lag) \ -+ list_for_each_entry((_dp), &(_dst)->ports, list) \ -+ if ((_dp)->lag_dev == (_lag)) -+ -+static inline struct net_device *dsa_lag_dev(struct dsa_switch_tree *dst, -+ unsigned int id) -+{ -+ return dst->lags[id]; -+} -+ -+static inline int dsa_lag_id(struct dsa_switch_tree *dst, -+ struct net_device *lag) -+{ -+ unsigned int id; -+ -+ dsa_lags_foreach_id(id, dst) { -+ if (dsa_lag_dev(dst, id) == lag) -+ return id; -+ } -+ -+ return -ENODEV; -+} -+ - /* TC matchall action types */ - enum dsa_port_mall_action_type { - DSA_PORT_MALL_MIRROR, -@@ -220,6 +253,8 @@ struct dsa_port { - bool devlink_port_setup; - struct phylink *pl; - struct phylink_config pl_config; -+ struct net_device *lag_dev; -+ bool lag_tx_enabled; - - struct list_head list; - -@@ -340,6 +375,14 @@ struct dsa_switch { - */ - bool mtu_enforcement_ingress; - -+ /* Drivers that benefit from having an ID associated with each -+ * offloaded LAG should set this to the maximum number of -+ * supported IDs. DSA will then maintain a mapping of _at -+ * least_ these many IDs, accessible to drivers via -+ * dsa_lag_id(). -+ */ -+ unsigned int num_lag_ids; -+ - size_t num_ports; - }; - -@@ -432,6 +475,18 @@ static inline bool dsa_port_is_vlan_filt - return dp->vlan_filtering; - } - -+static inline -+struct net_device *dsa_port_to_bridge_port(const struct dsa_port *dp) -+{ -+ if (!dp->bridge_dev) -+ return NULL; -+ -+ if (dp->lag_dev) -+ return dp->lag_dev; -+ -+ return dp->slave; -+} -+ - typedef int dsa_fdb_dump_cb_t(const unsigned char *addr, u16 vid, - bool is_static, void *data); - struct dsa_switch_ops { -@@ -629,6 +684,13 @@ struct dsa_switch_ops { - void (*crosschip_bridge_leave)(struct dsa_switch *ds, int tree_index, - int sw_index, int port, - struct net_device *br); -+ int (*crosschip_lag_change)(struct dsa_switch *ds, int sw_index, -+ int port); -+ int (*crosschip_lag_join)(struct dsa_switch *ds, int sw_index, -+ int port, struct net_device *lag, -+ struct netdev_lag_upper_info *info); -+ int (*crosschip_lag_leave)(struct dsa_switch *ds, int sw_index, -+ int port, struct net_device *lag); - - /* - * PTP functionality -@@ -660,6 +722,16 @@ struct dsa_switch_ops { - int (*port_change_mtu)(struct dsa_switch *ds, int port, - int new_mtu); - int (*port_max_mtu)(struct dsa_switch *ds, int port); -+ -+ /* -+ * LAG integration -+ */ -+ int (*port_lag_change)(struct dsa_switch *ds, int port); -+ int (*port_lag_join)(struct dsa_switch *ds, int port, -+ struct net_device *lag, -+ struct netdev_lag_upper_info *info); -+ int (*port_lag_leave)(struct dsa_switch *ds, int port, -+ struct net_device *lag); - }; - - #define DSA_DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes) \ ---- a/net/dsa/dsa.c -+++ b/net/dsa/dsa.c -@@ -220,11 +220,21 @@ static int dsa_switch_rcv(struct sk_buff - } - - skb = nskb; -- p = netdev_priv(skb->dev); - skb_push(skb, ETH_HLEN); - skb->pkt_type = PACKET_HOST; - skb->protocol = eth_type_trans(skb, skb->dev); - -+ if (unlikely(!dsa_slave_dev_check(skb->dev))) { -+ /* Packet is to be injected directly on an upper -+ * device, e.g. a team/bond, so skip all DSA-port -+ * specific actions. -+ */ -+ netif_rx(skb); -+ return 0; -+ } -+ -+ p = netdev_priv(skb->dev); -+ - if (unlikely(cpu_dp->ds->untag_bridge_pvid)) { - nskb = dsa_untag_bridge_pvid(skb); - if (!nskb) { ---- a/net/dsa/dsa2.c -+++ b/net/dsa/dsa2.c -@@ -21,6 +21,65 @@ - static DEFINE_MUTEX(dsa2_mutex); - LIST_HEAD(dsa_tree_list); - -+/** -+ * dsa_lag_map() - Map LAG netdev to a linear LAG ID -+ * @dst: Tree in which to record the mapping. -+ * @lag: Netdev that is to be mapped to an ID. -+ * -+ * dsa_lag_id/dsa_lag_dev can then be used to translate between the -+ * two spaces. The size of the mapping space is determined by the -+ * driver by setting ds->num_lag_ids. It is perfectly legal to leave -+ * it unset if it is not needed, in which case these functions become -+ * no-ops. -+ */ -+void dsa_lag_map(struct dsa_switch_tree *dst, struct net_device *lag) -+{ -+ unsigned int id; -+ -+ if (dsa_lag_id(dst, lag) >= 0) -+ /* Already mapped */ -+ return; -+ -+ for (id = 0; id < dst->lags_len; id++) { -+ if (!dsa_lag_dev(dst, id)) { -+ dst->lags[id] = lag; -+ return; -+ } -+ } -+ -+ /* No IDs left, which is OK. Some drivers do not need it. The -+ * ones that do, e.g. mv88e6xxx, will discover that dsa_lag_id -+ * returns an error for this device when joining the LAG. The -+ * driver can then return -EOPNOTSUPP back to DSA, which will -+ * fall back to a software LAG. -+ */ -+} -+ -+/** -+ * dsa_lag_unmap() - Remove a LAG ID mapping -+ * @dst: Tree in which the mapping is recorded. -+ * @lag: Netdev that was mapped. -+ * -+ * As there may be multiple users of the mapping, it is only removed -+ * if there are no other references to it. -+ */ -+void dsa_lag_unmap(struct dsa_switch_tree *dst, struct net_device *lag) -+{ -+ struct dsa_port *dp; -+ unsigned int id; -+ -+ dsa_lag_foreach_port(dp, dst, lag) -+ /* There are remaining users of this mapping */ -+ return; -+ -+ dsa_lags_foreach_id(id, dst) { -+ if (dsa_lag_dev(dst, id) == lag) { -+ dst->lags[id] = NULL; -+ break; -+ } -+ } -+} -+ - struct dsa_switch *dsa_switch_find(int tree_index, int sw_index) - { - struct dsa_switch_tree *dst; -@@ -597,6 +656,32 @@ static void dsa_tree_teardown_master(str - dsa_master_teardown(dp->master); - } - -+static int dsa_tree_setup_lags(struct dsa_switch_tree *dst) -+{ -+ unsigned int len = 0; -+ struct dsa_port *dp; -+ -+ list_for_each_entry(dp, &dst->ports, list) { -+ if (dp->ds->num_lag_ids > len) -+ len = dp->ds->num_lag_ids; -+ } -+ -+ if (!len) -+ return 0; -+ -+ dst->lags = kcalloc(len, sizeof(*dst->lags), GFP_KERNEL); -+ if (!dst->lags) -+ return -ENOMEM; -+ -+ dst->lags_len = len; -+ return 0; -+} -+ -+static void dsa_tree_teardown_lags(struct dsa_switch_tree *dst) -+{ -+ kfree(dst->lags); -+} -+ - static int dsa_tree_setup(struct dsa_switch_tree *dst) - { - bool complete; -@@ -624,12 +709,18 @@ static int dsa_tree_setup(struct dsa_swi - if (err) - goto teardown_switches; - -+ err = dsa_tree_setup_lags(dst); -+ if (err) -+ goto teardown_master; -+ - dst->setup = true; - - pr_info("DSA: tree %d setup\n", dst->index); - - return 0; - -+teardown_master: -+ dsa_tree_teardown_master(dst); - teardown_switches: - dsa_tree_teardown_switches(dst); - teardown_default_cpu: -@@ -645,6 +736,8 @@ static void dsa_tree_teardown(struct dsa - if (!dst->setup) - return; - -+ dsa_tree_teardown_lags(dst); -+ - dsa_tree_teardown_master(dst); - - dsa_tree_teardown_switches(dst); ---- a/net/dsa/dsa_priv.h -+++ b/net/dsa/dsa_priv.h -@@ -20,6 +20,9 @@ enum { - DSA_NOTIFIER_BRIDGE_LEAVE, - DSA_NOTIFIER_FDB_ADD, - DSA_NOTIFIER_FDB_DEL, -+ DSA_NOTIFIER_LAG_CHANGE, -+ DSA_NOTIFIER_LAG_JOIN, -+ DSA_NOTIFIER_LAG_LEAVE, - DSA_NOTIFIER_MDB_ADD, - DSA_NOTIFIER_MDB_DEL, - DSA_NOTIFIER_VLAN_ADD, -@@ -57,6 +60,15 @@ struct dsa_notifier_mdb_info { - int port; - }; - -+/* DSA_NOTIFIER_LAG_* */ -+struct dsa_notifier_lag_info { -+ struct net_device *lag; -+ int sw_index; -+ int port; -+ -+ struct netdev_lag_upper_info *info; -+}; -+ - /* DSA_NOTIFIER_VLAN_* */ - struct dsa_notifier_vlan_info { - const struct switchdev_obj_port_vlan *vlan; -@@ -149,6 +161,11 @@ void dsa_port_disable_rt(struct dsa_port - void dsa_port_disable(struct dsa_port *dp); - int dsa_port_bridge_join(struct dsa_port *dp, struct net_device *br); - void dsa_port_bridge_leave(struct dsa_port *dp, struct net_device *br); -+int dsa_port_lag_change(struct dsa_port *dp, -+ struct netdev_lag_lower_state_info *linfo); -+int dsa_port_lag_join(struct dsa_port *dp, struct net_device *lag_dev, -+ struct netdev_lag_upper_info *uinfo); -+void dsa_port_lag_leave(struct dsa_port *dp, struct net_device *lag_dev); - int dsa_port_vlan_filtering(struct dsa_port *dp, bool vlan_filtering, - struct switchdev_trans *trans); - bool dsa_port_skip_vlan_configuration(struct dsa_port *dp); -@@ -181,6 +198,71 @@ int dsa_port_link_register_of(struct dsa - void dsa_port_link_unregister_of(struct dsa_port *dp); - extern const struct phylink_mac_ops dsa_port_phylink_mac_ops; - -+static inline bool dsa_port_offloads_netdev(struct dsa_port *dp, -+ struct net_device *dev) -+{ -+ /* Switchdev offloading can be configured on: */ -+ -+ if (dev == dp->slave) -+ /* DSA ports directly connected to a bridge, and event -+ * was emitted for the ports themselves. -+ */ -+ return true; -+ -+ if (dp->bridge_dev == dev) -+ /* DSA ports connected to a bridge, and event was emitted -+ * for the bridge. -+ */ -+ return true; -+ -+ if (dp->lag_dev == dev) -+ /* DSA ports connected to a bridge via a LAG */ -+ return true; -+ -+ return false; -+} -+ -+static inline bool dsa_port_offloads_bridge_port(struct dsa_port *dp, -+ struct net_device *dev) -+{ -+ return dsa_port_to_bridge_port(dp) == dev; -+} -+ -+static inline bool dsa_port_offloads_bridge(struct dsa_port *dp, -+ struct net_device *bridge_dev) -+{ -+ /* DSA ports connected to a bridge, and event was emitted -+ * for the bridge. -+ */ -+ return dp->bridge_dev == bridge_dev; -+} -+ -+/* Returns true if any port of this tree offloads the given net_device */ -+static inline bool dsa_tree_offloads_bridge_port(struct dsa_switch_tree *dst, -+ struct net_device *dev) -+{ -+ struct dsa_port *dp; -+ -+ list_for_each_entry(dp, &dst->ports, list) -+ if (dsa_port_offloads_bridge_port(dp, dev)) -+ return true; -+ -+ return false; -+} -+ -+/* Returns true if any port of this tree offloads the given net_device */ -+static inline bool dsa_tree_offloads_netdev(struct dsa_switch_tree *dst, -+ struct net_device *dev) -+{ -+ struct dsa_port *dp; -+ -+ list_for_each_entry(dp, &dst->ports, list) -+ if (dsa_port_offloads_netdev(dp, dev)) -+ return true; -+ -+ return false; -+} -+ - /* slave.c */ - extern const struct dsa_device_ops notag_netdev_ops; - void dsa_slave_mii_bus_init(struct dsa_switch *ds); -@@ -285,6 +367,9 @@ int dsa_switch_register_notifier(struct - void dsa_switch_unregister_notifier(struct dsa_switch *ds); - - /* dsa2.c */ -+void dsa_lag_map(struct dsa_switch_tree *dst, struct net_device *lag); -+void dsa_lag_unmap(struct dsa_switch_tree *dst, struct net_device *lag); -+ - extern struct list_head dsa_tree_list; - - #endif ---- a/net/dsa/port.c -+++ b/net/dsa/port.c -@@ -193,6 +193,99 @@ void dsa_port_bridge_leave(struct dsa_po - dsa_port_set_state_now(dp, BR_STATE_FORWARDING); - } - -+int dsa_port_lag_change(struct dsa_port *dp, -+ struct netdev_lag_lower_state_info *linfo) -+{ -+ struct dsa_notifier_lag_info info = { -+ .sw_index = dp->ds->index, -+ .port = dp->index, -+ }; -+ bool tx_enabled; -+ -+ if (!dp->lag_dev) -+ return 0; -+ -+ /* On statically configured aggregates (e.g. loadbalance -+ * without LACP) ports will always be tx_enabled, even if the -+ * link is down. Thus we require both link_up and tx_enabled -+ * in order to include it in the tx set. -+ */ -+ tx_enabled = linfo->link_up && linfo->tx_enabled; -+ -+ if (tx_enabled == dp->lag_tx_enabled) -+ return 0; -+ -+ dp->lag_tx_enabled = tx_enabled; -+ -+ return dsa_port_notify(dp, DSA_NOTIFIER_LAG_CHANGE, &info); -+} -+ -+int dsa_port_lag_join(struct dsa_port *dp, struct net_device *lag, -+ struct netdev_lag_upper_info *uinfo) -+{ -+ struct dsa_notifier_lag_info info = { -+ .sw_index = dp->ds->index, -+ .port = dp->index, -+ .lag = lag, -+ .info = uinfo, -+ }; -+ struct net_device *bridge_dev; -+ int err; -+ -+ dsa_lag_map(dp->ds->dst, lag); -+ dp->lag_dev = lag; -+ -+ err = dsa_port_notify(dp, DSA_NOTIFIER_LAG_JOIN, &info); -+ if (err) -+ goto err_lag_join; -+ -+ bridge_dev = netdev_master_upper_dev_get(lag); -+ if (!bridge_dev || !netif_is_bridge_master(bridge_dev)) -+ return 0; -+ -+ err = dsa_port_bridge_join(dp, bridge_dev); -+ if (err) -+ goto err_bridge_join; -+ -+ return 0; -+ -+err_bridge_join: -+ dsa_port_notify(dp, DSA_NOTIFIER_LAG_LEAVE, &info); -+err_lag_join: -+ dp->lag_dev = NULL; -+ dsa_lag_unmap(dp->ds->dst, lag); -+ return err; -+} -+ -+void dsa_port_lag_leave(struct dsa_port *dp, struct net_device *lag) -+{ -+ struct dsa_notifier_lag_info info = { -+ .sw_index = dp->ds->index, -+ .port = dp->index, -+ .lag = lag, -+ }; -+ int err; -+ -+ if (!dp->lag_dev) -+ return; -+ -+ /* Port might have been part of a LAG that in turn was -+ * attached to a bridge. -+ */ -+ if (dp->bridge_dev) -+ dsa_port_bridge_leave(dp, dp->bridge_dev); -+ -+ dp->lag_tx_enabled = false; -+ dp->lag_dev = NULL; -+ -+ err = dsa_port_notify(dp, DSA_NOTIFIER_LAG_LEAVE, &info); -+ if (err) -+ pr_err("DSA: failed to notify DSA_NOTIFIER_LAG_LEAVE: %d\n", -+ err); -+ -+ dsa_lag_unmap(dp->ds->dst, lag); -+} -+ - /* Must be called under rcu_read_lock() */ - static bool dsa_port_can_apply_vlan_filtering(struct dsa_port *dp, - bool vlan_filtering) ---- a/net/dsa/slave.c -+++ b/net/dsa/slave.c -@@ -337,9 +337,6 @@ static int dsa_slave_vlan_add(struct net - struct switchdev_obj_port_vlan vlan; - int vid, err; - -- if (obj->orig_dev != dev) -- return -EOPNOTSUPP; -- - if (dsa_port_skip_vlan_configuration(dp)) - return 0; - -@@ -394,11 +391,13 @@ static int dsa_slave_port_obj_add(struct - - switch (obj->id) { - case SWITCHDEV_OBJ_ID_PORT_MDB: -- if (obj->orig_dev != dev) -+ if (!dsa_port_offloads_bridge_port(dp, obj->orig_dev)) - return -EOPNOTSUPP; - err = dsa_port_mdb_add(dp, SWITCHDEV_OBJ_PORT_MDB(obj), trans); - break; - case SWITCHDEV_OBJ_ID_HOST_MDB: -+ if (!dsa_port_offloads_bridge(dp, obj->orig_dev)) -+ return -EOPNOTSUPP; - /* DSA can directly translate this to a normal MDB add, - * but on the CPU port. - */ -@@ -406,6 +405,9 @@ static int dsa_slave_port_obj_add(struct - trans); - break; - case SWITCHDEV_OBJ_ID_PORT_VLAN: -+ if (!dsa_port_offloads_bridge_port(dp, obj->orig_dev)) -+ return -EOPNOTSUPP; -+ - err = dsa_slave_vlan_add(dev, obj, trans); - break; - default: -@@ -424,9 +426,6 @@ static int dsa_slave_vlan_del(struct net - struct switchdev_obj_port_vlan *vlan; - int vid, err; - -- if (obj->orig_dev != dev) -- return -EOPNOTSUPP; -- - if (dsa_port_skip_vlan_configuration(dp)) - return 0; - -@@ -453,17 +452,22 @@ static int dsa_slave_port_obj_del(struct - - switch (obj->id) { - case SWITCHDEV_OBJ_ID_PORT_MDB: -- if (obj->orig_dev != dev) -+ if (!dsa_port_offloads_bridge_port(dp, obj->orig_dev)) - return -EOPNOTSUPP; - err = dsa_port_mdb_del(dp, SWITCHDEV_OBJ_PORT_MDB(obj)); - break; - case SWITCHDEV_OBJ_ID_HOST_MDB: -+ if (!dsa_port_offloads_bridge(dp, obj->orig_dev)) -+ return -EOPNOTSUPP; - /* DSA can directly translate this to a normal MDB add, - * but on the CPU port. - */ - err = dsa_port_mdb_del(dp->cpu_dp, SWITCHDEV_OBJ_PORT_MDB(obj)); - break; - case SWITCHDEV_OBJ_ID_PORT_VLAN: -+ if (!dsa_port_offloads_bridge_port(dp, obj->orig_dev)) -+ return -EOPNOTSUPP; -+ - err = dsa_slave_vlan_del(dev, obj); - break; - default: -@@ -1993,6 +1997,46 @@ static int dsa_slave_changeupper(struct - dsa_port_bridge_leave(dp, info->upper_dev); - err = NOTIFY_OK; - } -+ } else if (netif_is_lag_master(info->upper_dev)) { -+ if (info->linking) { -+ err = dsa_port_lag_join(dp, info->upper_dev, -+ info->upper_info); -+ if (err == -EOPNOTSUPP) { -+ NL_SET_ERR_MSG_MOD(info->info.extack, -+ "Offloading not supported"); -+ err = 0; -+ } -+ err = notifier_from_errno(err); -+ } else { -+ dsa_port_lag_leave(dp, info->upper_dev); -+ err = NOTIFY_OK; -+ } -+ } -+ -+ return err; -+} -+ -+static int -+dsa_slave_lag_changeupper(struct net_device *dev, -+ struct netdev_notifier_changeupper_info *info) -+{ -+ struct net_device *lower; -+ struct list_head *iter; -+ int err = NOTIFY_DONE; -+ struct dsa_port *dp; -+ -+ netdev_for_each_lower_dev(dev, lower, iter) { -+ if (!dsa_slave_dev_check(lower)) -+ continue; -+ -+ dp = dsa_slave_to_port(lower); -+ if (!dp->lag_dev) -+ /* Software LAG */ -+ continue; -+ -+ err = dsa_slave_changeupper(lower, info); -+ if (notifier_to_errno(err)) -+ break; - } - - return err; -@@ -2078,10 +2122,26 @@ static int dsa_slave_netdevice_event(str - break; - } - case NETDEV_CHANGEUPPER: -+ if (dsa_slave_dev_check(dev)) -+ return dsa_slave_changeupper(dev, ptr); -+ -+ if (netif_is_lag_master(dev)) -+ return dsa_slave_lag_changeupper(dev, ptr); -+ -+ break; -+ case NETDEV_CHANGELOWERSTATE: { -+ struct netdev_notifier_changelowerstate_info *info = ptr; -+ struct dsa_port *dp; -+ int err; -+ - if (!dsa_slave_dev_check(dev)) -- return NOTIFY_DONE; -+ break; - -- return dsa_slave_changeupper(dev, ptr); -+ dp = dsa_slave_to_port(dev); -+ -+ err = dsa_port_lag_change(dp, info->lower_state_info); -+ return notifier_from_errno(err); -+ } - } - - return NOTIFY_DONE; -@@ -2229,6 +2289,15 @@ static int dsa_slave_switchdev_event(str - if (!fdb_info->added_by_user && - !dp->ds->assisted_learning_on_cpu_port) - return NOTIFY_DONE; -+ -+ /* When the bridge learns an address on an offloaded -+ * LAG we don't want to send traffic to the CPU, the -+ * other ports bridged with the LAG should be able to -+ * autonomously forward towards it. -+ */ -+ if (dsa_tree_offloads_netdev(dp->ds->dst, dev)) -+ return NOTIFY_DONE; -+ - } - - if (!dp->ds->ops->port_fdb_add || !dp->ds->ops->port_fdb_del) ---- a/net/dsa/switch.c -+++ b/net/dsa/switch.c -@@ -193,6 +193,47 @@ static int dsa_switch_fdb_del(struct dsa - return ds->ops->port_fdb_del(ds, port, info->addr, info->vid); - } - -+static int dsa_switch_lag_change(struct dsa_switch *ds, -+ struct dsa_notifier_lag_info *info) -+{ -+ if (ds->index == info->sw_index && ds->ops->port_lag_change) -+ return ds->ops->port_lag_change(ds, info->port); -+ -+ if (ds->index != info->sw_index && ds->ops->crosschip_lag_change) -+ return ds->ops->crosschip_lag_change(ds, info->sw_index, -+ info->port); -+ -+ return 0; -+} -+ -+static int dsa_switch_lag_join(struct dsa_switch *ds, -+ struct dsa_notifier_lag_info *info) -+{ -+ if (ds->index == info->sw_index && ds->ops->port_lag_join) -+ return ds->ops->port_lag_join(ds, info->port, info->lag, -+ info->info); -+ -+ if (ds->index != info->sw_index && ds->ops->crosschip_lag_join) -+ return ds->ops->crosschip_lag_join(ds, info->sw_index, -+ info->port, info->lag, -+ info->info); -+ -+ return -EOPNOTSUPP; -+} -+ -+static int dsa_switch_lag_leave(struct dsa_switch *ds, -+ struct dsa_notifier_lag_info *info) -+{ -+ if (ds->index == info->sw_index && ds->ops->port_lag_leave) -+ return ds->ops->port_lag_leave(ds, info->port, info->lag); -+ -+ if (ds->index != info->sw_index && ds->ops->crosschip_lag_leave) -+ return ds->ops->crosschip_lag_leave(ds, info->sw_index, -+ info->port, info->lag); -+ -+ return -EOPNOTSUPP; -+} -+ - static bool dsa_switch_mdb_match(struct dsa_switch *ds, int port, - struct dsa_notifier_mdb_info *info) - { -@@ -340,6 +381,15 @@ static int dsa_switch_event(struct notif - case DSA_NOTIFIER_FDB_DEL: - err = dsa_switch_fdb_del(ds, info); - break; -+ case DSA_NOTIFIER_LAG_CHANGE: -+ err = dsa_switch_lag_change(ds, info); -+ break; -+ case DSA_NOTIFIER_LAG_JOIN: -+ err = dsa_switch_lag_join(ds, info); -+ break; -+ case DSA_NOTIFIER_LAG_LEAVE: -+ err = dsa_switch_lag_leave(ds, info); -+ break; - case DSA_NOTIFIER_MDB_ADD: - err = dsa_switch_mdb_add(ds, info); - break; ---- a/net/dsa/tag_dsa.c -+++ b/net/dsa/tag_dsa.c -@@ -82,7 +82,19 @@ static struct sk_buff *dsa_rcv(struct sk - source_device = dsa_header[0] & 0x1f; - source_port = (dsa_header[1] >> 3) & 0x1f; - -- skb->dev = dsa_master_find_slave(dev, source_device, source_port); -+ if (trunk) { -+ struct dsa_port *cpu_dp = dev->dsa_ptr; -+ -+ /* The exact source port is not available in the tag, -+ * so we inject the frame directly on the upper -+ * team/bond. -+ */ -+ skb->dev = dsa_lag_dev(cpu_dp->dst, source_port); -+ } else { -+ skb->dev = dsa_master_find_slave(dev, source_device, -+ source_port); -+ } -+ - if (!skb->dev) - return NULL; - diff --git a/target/linux/realtek/patches-5.10/710-net-phy-sfp-re-probe-modules-on-DEV_UP-event.patch b/target/linux/realtek/patches-5.10/710-net-phy-sfp-re-probe-modules-on-DEV_UP-event.patch deleted file mode 100644 index 53fbbccd55..0000000000 --- a/target/linux/realtek/patches-5.10/710-net-phy-sfp-re-probe-modules-on-DEV_UP-event.patch +++ /dev/null @@ -1,26 +0,0 @@ -From a381ac0aa281fdb0b41a39d8a2bc08fd88f6db92 Mon Sep 17 00:00:00 2001 -From: Antoine Tenart -Date: Tue, 25 Feb 2020 16:32:37 +0100 -Subject: [PATCH 1/3] net: phy: sfp: re-probe modules on DEV_UP event - -Signed-off-by: Antoine Tenart ---- - drivers/net/phy/sfp.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -1968,6 +1968,13 @@ static void sfp_sm_module(struct sfp *sf - return; - } - -+ /* Re-probe the SFP modules when an interface is brought up, as the MAC -+ * do not report its link status (This means Phylink wouldn't be -+ * triggered if the PHY had a link before a MAC is brought up). -+ */ -+ if (event == SFP_E_DEV_UP && sfp->sm_mod_state == SFP_MOD_PRESENT) -+ sfp_sm_mod_next(sfp, SFP_MOD_PROBE, T_SERIAL); -+ - switch (sfp->sm_mod_state) { - default: - if (event == SFP_E_INSERT) { diff --git a/target/linux/realtek/patches-5.10/711-net-phy-add-an-MDIO-SMBus-library.patch b/target/linux/realtek/patches-5.10/711-net-phy-add-an-MDIO-SMBus-library.patch deleted file mode 100644 index 5e1053ca6c..0000000000 --- a/target/linux/realtek/patches-5.10/711-net-phy-add-an-MDIO-SMBus-library.patch +++ /dev/null @@ -1,168 +0,0 @@ -From d585c55b9f70cf9e8c66820d7efe7130c683f19e Mon Sep 17 00:00:00 2001 -From: Antoine Tenart -Date: Fri, 21 Feb 2020 11:51:27 +0100 -Subject: [PATCH 2/3] net: phy: add an MDIO SMBus library - -Signed-off-by: Antoine Tenart ---- - drivers/net/mdio/Kconfig | 11 +++++++ - drivers/net/mdio/Makefile | 1 + - drivers/net/mdio/mdio-smbus.c | 62 +++++++++++++++++++++++++++++++++++ - drivers/net/phy/Kconfig | 1 + - include/linux/mdio/mdio-i2c.h | 16 +++++++++ - 5 files changed, 91 insertions(+) - create mode 100644 drivers/net/mdio/mdio-smbus.c - ---- a/drivers/net/mdio/Kconfig -+++ b/drivers/net/mdio/Kconfig -@@ -40,6 +40,17 @@ config MDIO_SUN4I - interface units of the Allwinner SoC that have an EMAC (A10, - A12, A10s, etc.) - -+config MDIO_SMBUS -+ tristate -+ depends on I2C_SMBUS -+ help -+ Support SMBus based PHYs. This provides a MDIO bus bridged -+ to SMBus to allow PHYs connected in SMBus mode to be accessed -+ using the existing infrastructure. -+ -+ This is library mode. -+ -+ - config MDIO_XGENE - tristate "APM X-Gene SoC MDIO bus controller" - depends on ARCH_XGENE || COMPILE_TEST ---- a/drivers/net/mdio/Makefile -+++ b/drivers/net/mdio/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_MDIO_MOXART) += mdio-moxar - obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o - obj-$(CONFIG_MDIO_MVUSB) += mdio-mvusb.o - obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o -+obj-$(CONFIG_MDIO_SMBUS) += mdio-smbus.o - obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o - obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o - obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o ---- /dev/null -+++ b/drivers/net/mdio/mdio-smbus.c -@@ -0,0 +1,62 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * MDIO SMBus bridge -+ * -+ * Copyright (C) 2020 Antoine Tenart -+ * -+ * Network PHYs can appear on SMBus when they are part of SFP modules. -+ */ -+#include -+#include -+#include -+ -+static int smbus_mii_read(struct mii_bus *mii, int phy_id, int reg) -+{ -+ struct i2c_adapter *i2c = mii->priv; -+ union i2c_smbus_data data; -+ int ret; -+ -+ ret = i2c_smbus_xfer(i2c, i2c_mii_phy_addr(phy_id), 0, I2C_SMBUS_READ, -+ reg, I2C_SMBUS_BYTE_DATA, &data); -+ if (ret < 0) -+ return 0xff; -+ -+ return data.byte; -+} -+ -+static int smbus_mii_write(struct mii_bus *mii, int phy_id, int reg, u16 val) -+{ -+ struct i2c_adapter *i2c = mii->priv; -+ union i2c_smbus_data data; -+ int ret; -+ -+ data.byte = val; -+ -+ ret = i2c_smbus_xfer(i2c, i2c_mii_phy_addr(phy_id), 0, I2C_SMBUS_WRITE, -+ reg, I2C_SMBUS_BYTE_DATA, &data); -+ return ret < 0 ? ret : 0; -+} -+ -+struct mii_bus *mdio_smbus_alloc(struct device *parent, struct i2c_adapter *i2c) -+{ -+ struct mii_bus *mii; -+ -+ if (!i2c_check_functionality(i2c, I2C_FUNC_SMBUS_BYTE_DATA)) -+ return ERR_PTR(-EINVAL); -+ -+ mii = mdiobus_alloc(); -+ if (!mii) -+ return ERR_PTR(-ENOMEM); -+ -+ snprintf(mii->id, MII_BUS_ID_SIZE, "smbus:%s", dev_name(parent)); -+ mii->parent = parent; -+ mii->read = smbus_mii_read; -+ mii->write = smbus_mii_write; -+ mii->priv = i2c; -+ -+ return mii; -+} -+ -+MODULE_AUTHOR("Antoine Tenart"); -+MODULE_DESCRIPTION("MDIO SMBus bridge library"); -+MODULE_LICENSE("GPL"); ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -60,6 +60,7 @@ config SFP - depends on I2C && PHYLINK - depends on HWMON || HWMON=n - select MDIO_I2C -+ select MDIO_SMBUS - - comment "Switch configuration API + drivers" - ---- a/include/linux/mdio/mdio-i2c.h -+++ b/include/linux/mdio/mdio-i2c.h -@@ -12,5 +12,21 @@ struct i2c_adapter; - struct mii_bus; - - struct mii_bus *mdio_i2c_alloc(struct device *parent, struct i2c_adapter *i2c); -+struct mii_bus *mdio_smbus_alloc(struct device *parent, struct i2c_adapter *i2c); -+ -+/* -+ * I2C bus addresses 0x50 and 0x51 are normally an EEPROM, which is -+ * specified to be present in SFP modules. These correspond with PHY -+ * addresses 16 and 17. Disallow access to these "phy" addresses. -+ */ -+static bool i2c_mii_valid_phy_id(int phy_id) -+{ -+ return phy_id != 0x10 && phy_id != 0x11; -+} -+ -+static unsigned int i2c_mii_phy_addr(int phy_id) -+{ -+ return phy_id + 0x40; -+} - - #endif ---- a/drivers/net/mdio/mdio-i2c.c -+++ b/drivers/net/mdio/mdio-i2c.c -@@ -13,21 +13,6 @@ - #include - #include - --/* -- * I2C bus addresses 0x50 and 0x51 are normally an EEPROM, which is -- * specified to be present in SFP modules. These correspond with PHY -- * addresses 16 and 17. Disallow access to these "phy" addresses. -- */ --static bool i2c_mii_valid_phy_id(int phy_id) --{ -- return phy_id != 0x10 && phy_id != 0x11; --} -- --static unsigned int i2c_mii_phy_addr(int phy_id) --{ -- return phy_id + 0x40; --} -- - static int i2c_mii_read(struct mii_bus *bus, int phy_id, int reg) - { - struct i2c_adapter *i2c = bus->priv; diff --git a/target/linux/realtek/patches-5.10/712-net-phy-sfp-add-support-for-SMBus.patch b/target/linux/realtek/patches-5.10/712-net-phy-sfp-add-support-for-SMBus.patch deleted file mode 100644 index e2540d4512..0000000000 --- a/target/linux/realtek/patches-5.10/712-net-phy-sfp-add-support-for-SMBus.patch +++ /dev/null @@ -1,99 +0,0 @@ -From 3cb0bde365d913c484d20224367a54a0eac780a7 Mon Sep 17 00:00:00 2001 -From: Antoine Tenart -Date: Fri, 21 Feb 2020 11:55:29 +0100 -Subject: [PATCH 3/3] net: phy: sfp: add support for SMBus - -Signed-off-by: Antoine Tenart ---- - drivers/net/phy/sfp.c | 68 ++++++++++++++++++++++++++++++++++--------- - 1 file changed, 54 insertions(+), 14 deletions(-) - ---- a/drivers/net/phy/sfp.c -+++ b/drivers/net/phy/sfp.c -@@ -419,32 +419,72 @@ static int sfp_i2c_write(struct sfp *sfp - return ret == ARRAY_SIZE(msgs) ? len : 0; - } - -+static int sfp_smbus_read(struct sfp *sfp, bool a2, u8 dev_addr, void *buf, -+ size_t len) -+{ -+ u8 bus_addr = a2 ? 0x51 : 0x50, *val = buf; -+ -+ bus_addr -= 0x40; -+ -+ while (len > 0) { -+ *val = sfp->i2c_mii->read(sfp->i2c_mii, bus_addr, dev_addr); -+ -+ val++; -+ dev_addr++; -+ len--; -+ } -+ -+ return val - (u8 *)buf; -+} -+ -+static int sfp_smbus_write(struct sfp *sfp, bool a2, u8 dev_addr, void *buf, -+ size_t len) -+{ -+ u8 bus_addr = a2 ? 0x51 : 0x50; -+ u16 val; -+ -+ memcpy(&val, buf, len); -+ -+ return sfp->i2c_mii->write(sfp->i2c_mii, bus_addr, dev_addr, val); -+} -+ - static int sfp_i2c_configure(struct sfp *sfp, struct i2c_adapter *i2c) - { -- struct mii_bus *i2c_mii; -+ struct mii_bus *mii; - int ret; - -- if (!i2c_check_functionality(i2c, I2C_FUNC_I2C)) -- return -EINVAL; -- - sfp->i2c = i2c; -- sfp->read = sfp_i2c_read; -- sfp->write = sfp_i2c_write; - -- i2c_mii = mdio_i2c_alloc(sfp->dev, i2c); -- if (IS_ERR(i2c_mii)) -- return PTR_ERR(i2c_mii); -+ if (i2c_check_functionality(i2c, I2C_FUNC_I2C)) { -+ sfp->read = sfp_i2c_read; -+ sfp->write = sfp_i2c_write; -+ -+ mii = mdio_i2c_alloc(sfp->dev, i2c); -+ if (IS_ERR(mii)) -+ return PTR_ERR(mii); -+ -+ mii->name = "SFP I2C Bus"; -+ } else if (i2c_check_functionality(i2c, I2C_FUNC_SMBUS_BYTE_DATA)) { -+ sfp->read = sfp_smbus_read; -+ sfp->write = sfp_smbus_write; -+ -+ mii = mdio_smbus_alloc(sfp->dev, i2c); -+ if (IS_ERR(mii)) -+ return PTR_ERR(mii); - -- i2c_mii->name = "SFP I2C Bus"; -- i2c_mii->phy_mask = ~0; -+ mii->name = "SFP SMBus"; -+ } else { -+ return -EINVAL; -+ } - -- ret = mdiobus_register(i2c_mii); -+ mii->phy_mask = ~0; -+ ret = mdiobus_register(mii); - if (ret < 0) { -- mdiobus_free(i2c_mii); -+ mdiobus_free(mii); - return ret; - } - -- sfp->i2c_mii = i2c_mii; -+ sfp->i2c_mii = mii; - - return 0; - } diff --git a/target/linux/realtek/patches-5.10/713-v5.12-net-dsa-configure-better-brport-flags-when-ports-lea.patch b/target/linux/realtek/patches-5.10/713-v5.12-net-dsa-configure-better-brport-flags-when-ports-lea.patch deleted file mode 100644 index a3bfec59ab..0000000000 --- a/target/linux/realtek/patches-5.10/713-v5.12-net-dsa-configure-better-brport-flags-when-ports-lea.patch +++ /dev/null @@ -1,148 +0,0 @@ -From: Vladimir Oltean -Date: Fri, 12 Feb 2021 17:15:54 +0200 -Subject: [PATCH] net: dsa: configure better brport flags when ports leave the - bridge - -Bugfixed version of upstream commit 5e38c15856e9 ("net: dsa: configure -better brport flags when ports leave the bridge") - -For a DSA switch port operating in standalone mode, address learning -doesn't make much sense since that is a bridge function. In fact, -address learning even breaks setups such as this one: - - +---------------------------------------------+ - | | - | +-------------------+ | - | | br0 | send receive | - | +--------+-+--------+ +--------+ +--------+ | - | | | | | | | | | | - | | swp0 | | swp1 | | swp2 | | swp3 | | - | | | | | | | | | | - +-+--------+-+--------+-+--------+-+--------+-+ - | ^ | ^ - | | | | - | +-----------+ | - | | - +--------------------------------+ - -because if the switch has a single FDB (can offload a single bridge) -then source address learning on swp3 can "steal" the source MAC address -of swp2 from br0's FDB, because learning frames coming from swp2 will be -done twice: first on the swp1 ingress port, second on the swp3 ingress -port. So the hardware FDB will become out of sync with the software -bridge, and when swp2 tries to send one more packet towards swp1, the -ASIC will attempt to short-circuit the forwarding path and send it -directly to swp3 (since that's the last port it learned that address on), -which it obviously can't, because swp3 operates in standalone mode. - -So DSA drivers operating in standalone mode should still configure a -list of bridge port flags even when they are standalone. Currently DSA -attempts to call dsa_port_bridge_flags with 0, which disables egress -flooding of unknown unicast and multicast, something which doesn't make -much sense. For the switches that implement .port_egress_floods - b53 -and mv88e6xxx, it probably doesn't matter too much either, since they -can possibly inject traffic from the CPU into a standalone port, -regardless of MAC DA, even if egress flooding is turned off for that -port, but certainly not all DSA switches can do that - sja1105, for -example, can't. So it makes sense to use a better common default there, -such as "flood everything". - -It should also be noted that what DSA calls "dsa_port_bridge_flags()" -is a degenerate name for just calling .port_egress_floods(), since -nothing else is implemented - not learning, in particular. But disabling -address learning, something that this driver is also coding up for, will -be supported by individual drivers once .port_egress_floods is replaced -with a more generic .port_bridge_flags. - -Previous attempts to code up this logic have been in the common bridge -layer, but as pointed out by Ido Schimmel, there are corner cases that -are missed when doing that: -https://patchwork.kernel.org/project/netdevbpf/patch/20210209151936.97382-5-olteanv@gmail.com/ - -So, at least for now, let's leave DSA in charge of setting port flags -before and after the bridge join and leave. - -Signed-off-by: Vladimir Oltean -Reviewed-by: Florian Fainelli -Signed-off-by: David S. Miller -[ backport and bugfix: break dsa_port_bridge_flags() out of loop ] -Signed-off-by: Bjørn Mork ---- - net/dsa/port.c | 45 ++++++++++++++++++++++++++++++++++++++------- - 1 file changed, 38 insertions(+), 7 deletions(-) - ---- a/net/dsa/port.c -+++ b/net/dsa/port.c -@@ -134,6 +134,27 @@ void dsa_port_disable(struct dsa_port *d - rtnl_unlock(); - } - -+static void dsa_port_change_brport_flags(struct dsa_port *dp, -+ bool bridge_offload) -+{ -+ unsigned long mask, flags; -+ int flag, err; -+ -+ mask = BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD; -+ if (bridge_offload) -+ flags = mask; -+ else -+ flags = mask & ~BR_LEARNING; -+ -+ for_each_set_bit(flag, &mask, 32) { -+ err = dsa_port_pre_bridge_flags(dp, BIT(flag), NULL, NULL); -+ if (err) -+ flags &= ~BIT(flag); -+ } -+ -+ dsa_port_bridge_flags(dp, flags, NULL, NULL); -+} -+ - int dsa_port_bridge_join(struct dsa_port *dp, struct net_device *br) - { - struct dsa_notifier_bridge_info info = { -@@ -144,10 +165,10 @@ int dsa_port_bridge_join(struct dsa_port - }; - int err; - -- /* Set the flooding mode before joining the port in the switch */ -- err = dsa_port_bridge_flags(dp, BR_FLOOD | BR_MCAST_FLOOD, NULL, NULL); -- if (err) -- return err; -+ /* Notify the port driver to set its configurable flags in a way that -+ * matches the initial settings of a bridge port. -+ */ -+ dsa_port_change_brport_flags(dp, true); - - /* Here the interface is already bridged. Reflect the current - * configuration so that drivers can program their chips accordingly. -@@ -158,7 +179,7 @@ int dsa_port_bridge_join(struct dsa_port - - /* The bridging is rolled back on error */ - if (err) { -- dsa_port_bridge_flags(dp, 0, NULL, NULL); -+ dsa_port_change_brport_flags(dp, false); - dp->bridge_dev = NULL; - } - -@@ -184,8 +205,18 @@ void dsa_port_bridge_leave(struct dsa_po - if (err) - pr_err("DSA: failed to notify DSA_NOTIFIER_BRIDGE_LEAVE\n"); - -- /* Port is leaving the bridge, disable flooding */ -- dsa_port_bridge_flags(dp, 0, NULL, NULL); -+ /* Configure the port for standalone mode (no address learning, -+ * flood everything). -+ * The bridge only emits SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS events -+ * when the user requests it through netlink or sysfs, but not -+ * automatically at port join or leave, so we need to handle resetting -+ * the brport flags ourselves. But we even prefer it that way, because -+ * otherwise, some setups might never get the notification they need, -+ * for example, when a port leaves a LAG that offloads the bridge, -+ * it becomes standalone, but as far as the bridge is concerned, no -+ * port ever left. -+ */ -+ dsa_port_change_brport_flags(dp, false); - - /* Port left the bridge, put in BR_STATE_DISABLED by the bridge layer, - * so allow it to be in BR_STATE_FORWARDING to be kept functional diff --git a/target/linux/realtek/patches-5.10/800-net-mdio-support-hardware-assisted-indirect-access.patch b/target/linux/realtek/patches-5.10/800-net-mdio-support-hardware-assisted-indirect-access.patch deleted file mode 100644 index aca017c03a..0000000000 --- a/target/linux/realtek/patches-5.10/800-net-mdio-support-hardware-assisted-indirect-access.patch +++ /dev/null @@ -1,840 +0,0 @@ -From 5d84f16b0036b33487b94abef15ad3c224c81ee9 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 3 Feb 2022 16:38:50 +0000 -Subject: [PATCH] net: mdio: support hardware-assisted indirect access - -MDIO controllers found in Switch-SoCs can offload some MDIO operations -to the hardware: - * MMD register access via Clause-22 - Instead of using multiple operations to access MMD registers via - MII register MII_MMD_CTRL and MII_MMD_DATA some controllers - allow transparent access to MMD PHY registers. - - * paged MII register access - Some PHYs (namely RealTek and Vitesse) use vendor-defined MII - register 0x1f for paged access. Some MDIO host controllers support - transparent paged access when used with such PHYs. - - * add convenience accessors to fully support paged access also on - multi-PHY packages (like the embedded PHYs in RTL83xx): - phy_package_read_paged and phy_package_write_paged - phy_package_port_read and phy_package_port_write - phy_package_port_read_paged and phy_package_port_write_paged - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/mdio_bus.c | 335 ++++++++++++++++++++++++++++++++++++- - drivers/net/phy/phy-core.c | 66 +++++++- - include/linux/mdio.h | 59 +++++++ - include/linux/phy.h | 129 ++++++++++++++ - include/uapi/linux/mii.h | 1 + - 5 files changed, 580 insertions(+), 10 deletions(-) - ---- a/drivers/net/phy/mdio_bus.c -+++ b/drivers/net/phy/mdio_bus.c -@@ -739,6 +739,32 @@ out: - } - - /** -+ * __mdiobus_select_page - Unlocked version of the mdiobus_select_page function -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: register page to select -+ * -+ * Selects a MDIO bus register page. Caller must hold the mdio bus lock. -+ * -+ * NOTE: MUST NOT be called from interrupt context. -+ */ -+int __mdiobus_select_page(struct mii_bus *bus, int addr, u16 page) -+{ -+ lockdep_assert_held_once(&bus->mdio_lock); -+ -+ if (bus->selected_page[addr] == page) -+ return 0; -+ -+ bus->selected_page[addr] = page; -+ if (bus->read_paged) -+ return 0; -+ -+ return bus->write(bus, addr, MII_MAINPAGE, page); -+ -+} -+EXPORT_SYMBOL(__mdiobus_select_page); -+ -+/** - * __mdiobus_read - Unlocked version of the mdiobus_read function - * @bus: the mii_bus struct - * @addr: the phy address -@@ -754,7 +780,10 @@ int __mdiobus_read(struct mii_bus *bus, - - WARN_ON_ONCE(!mutex_is_locked(&bus->mdio_lock)); - -- retval = bus->read(bus, addr, regnum); -+ if (bus->read_paged) -+ retval = bus->read_paged(bus, addr, bus->selected_page[addr], regnum); -+ else -+ retval = bus->read(bus, addr, regnum); - - trace_mdio_access(bus, 1, addr, regnum, retval, retval); - mdiobus_stats_acct(&bus->stats[addr], true, retval); -@@ -764,6 +793,40 @@ int __mdiobus_read(struct mii_bus *bus, - EXPORT_SYMBOL(__mdiobus_read); - - /** -+ * __mdiobus_read_paged - Unlocked version of the mdiobus_read_paged function -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: the register page to access -+ * @regnum: register number to read -+ * -+ * Read a MDIO bus register. Caller must hold the mdio bus lock. -+ * -+ * NOTE: MUST NOT be called from interrupt context. -+ */ -+int __mdiobus_read_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum) -+{ -+ int retval; -+ int oldpage; -+ -+ lockdep_assert_held_once(&bus->mdio_lock); -+ -+ if (bus->read_paged) { -+ retval = bus->read_paged(bus, addr, page, regnum); -+ } else { -+ oldpage = bus->selected_page[addr]; -+ __mdiobus_select_page(bus, addr, page); -+ retval = bus->read(bus, addr, regnum); -+ __mdiobus_select_page(bus, addr, oldpage); -+ } -+ -+ trace_mdio_access(bus, 1, addr, regnum, retval, retval); -+ mdiobus_stats_acct(&bus->stats[addr], true, retval); -+ -+ return retval; -+} -+EXPORT_SYMBOL(__mdiobus_read_paged); -+ -+/** - * __mdiobus_write - Unlocked version of the mdiobus_write function - * @bus: the mii_bus struct - * @addr: the phy address -@@ -780,7 +843,10 @@ int __mdiobus_write(struct mii_bus *bus, - - WARN_ON_ONCE(!mutex_is_locked(&bus->mdio_lock)); - -- err = bus->write(bus, addr, regnum, val); -+ if (bus->write_paged) -+ err = bus->write_paged(bus, addr, bus->selected_page[addr], regnum, val); -+ else -+ err = bus->write(bus, addr, regnum, val); - - trace_mdio_access(bus, 0, addr, regnum, val, err); - mdiobus_stats_acct(&bus->stats[addr], false, err); -@@ -790,6 +856,39 @@ int __mdiobus_write(struct mii_bus *bus, - EXPORT_SYMBOL(__mdiobus_write); - - /** -+ * __mdiobus_write_paged - Unlocked version of the mdiobus_write_paged function -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: the register page to access -+ * @regnum: register number to write -+ * @val: value to write to @regnum -+ * -+ * Write a MDIO bus register. Caller must hold the mdio bus lock. -+ * -+ * NOTE: MUST NOT be called from interrupt context. -+ */ -+int __mdiobus_write_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val) -+{ -+ int err, oldpage; -+ -+ lockdep_assert_held_once(&bus->mdio_lock); -+ -+ if (bus->write_paged) { -+ err = bus->write_paged(bus, addr, page, regnum, val); -+ } else { -+ oldpage = bus->selected_page[addr]; -+ __mdiobus_select_page(bus, addr, page); -+ err = bus->write(bus, addr, regnum, val); -+ __mdiobus_select_page(bus, addr, oldpage); -+ } -+ trace_mdio_access(bus, 0, addr, regnum, val, err); -+ mdiobus_stats_acct(&bus->stats[addr], false, err); -+ return err; -+} -+EXPORT_SYMBOL(__mdiobus_write_paged); -+ -+ -+/** - * __mdiobus_modify_changed - Unlocked version of the mdiobus_modify function - * @bus: the mii_bus struct - * @addr: the phy address -@@ -822,6 +921,43 @@ int __mdiobus_modify_changed(struct mii_ - EXPORT_SYMBOL_GPL(__mdiobus_modify_changed); - - /** -+ * __mdiobus_modify_changed_paged - Unlocked version of the mdiobus_modify_paged function -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @regnum: register number to modify -+ * @mask: bit mask of bits to clear -+ * @set: bit mask of bits to set -+ * -+ * Read, modify, and if any change, write the register value back to the -+ * device. Any error returns a negative number. -+ * -+ * NOTE: MUST NOT be called from interrupt context. -+ */ -+int __mdiobus_modify_changed_paged(struct mii_bus *bus, int addr, u32 regnum, u16 page, -+ u16 mask, u16 set) -+{ -+ int new, ret, oldpage; -+ -+ oldpage = bus->selected_page[addr]; -+ __mdiobus_select_page(bus, addr, page); -+ -+ ret = __mdiobus_read_paged(bus, addr, page, regnum); -+ if (ret < 0) -+ return ret; -+ -+ new = (ret & ~mask) | set; -+ if (new == ret) -+ return 0; -+ -+ ret = __mdiobus_write_paged(bus, addr, page, regnum, new); -+ -+ __mdiobus_select_page(bus, addr, oldpage); -+ -+ return ret < 0 ? ret : 1; -+} -+EXPORT_SYMBOL_GPL(__mdiobus_modify_changed_paged); -+ -+/** - * mdiobus_read_nested - Nested version of the mdiobus_read function - * @bus: the mii_bus struct - * @addr: the phy address -@@ -847,6 +983,79 @@ int mdiobus_read_nested(struct mii_bus * - EXPORT_SYMBOL(mdiobus_read_nested); - - /** -+ * mdiobus_select_page_nested - Nested version of the mdiobus_select_page function -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: register page to access -+ * -+ * In case of nested MDIO bus access avoid lockdep false positives by -+ * using mutex_lock_nested(). -+ * -+ * NOTE: MUST NOT be called from interrupt context, -+ * because the bus read/write functions may wait for an interrupt -+ * to conclude the operation. -+ */ -+int mdiobus_select_page_nested(struct mii_bus *bus, int addr, u16 page) -+{ -+ int retval; -+ -+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); -+ retval = __mdiobus_select_page(bus, addr, page); -+ mutex_unlock(&bus->mdio_lock); -+ -+ return retval; -+} -+EXPORT_SYMBOL(mdiobus_select_page_nested); -+ -+/** -+ * mdiobus_read_paged_nested - Nested version of the mdiobus_read_paged function -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: register page to access -+ * @regnum: register number to read -+ * -+ * In case of nested MDIO bus access avoid lockdep false positives by -+ * using mutex_lock_nested(). -+ * -+ * NOTE: MUST NOT be called from interrupt context, -+ * because the bus read/write functions may wait for an interrupt -+ * to conclude the operation. -+ */ -+int mdiobus_read_paged_nested(struct mii_bus *bus, int addr, u16 page, u32 regnum) -+{ -+ int retval; -+ -+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); -+ retval = __mdiobus_read_paged(bus, addr, page, regnum); -+ mutex_unlock(&bus->mdio_lock); -+ -+ return retval; -+} -+EXPORT_SYMBOL(mdiobus_read_paged_nested); -+ -+/** -+ * mdiobus_select_page - Convenience function for setting the MII register page -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: the register page to set -+ * -+ * NOTE: MUST NOT be called from interrupt context, -+ * because the bus read/write functions may wait for an interrupt -+ * to conclude the operation. -+ */ -+int mdiobus_select_page(struct mii_bus *bus, int addr, u16 page) -+{ -+ int retval; -+ -+ mutex_lock(&bus->mdio_lock); -+ retval = __mdiobus_select_page(bus, addr, page); -+ mutex_unlock(&bus->mdio_lock); -+ -+ return retval; -+} -+EXPORT_SYMBOL(mdiobus_select_page); -+ -+/** - * mdiobus_read - Convenience function for reading a given MII mgmt register - * @bus: the mii_bus struct - * @addr: the phy address -@@ -869,6 +1078,29 @@ int mdiobus_read(struct mii_bus *bus, in - EXPORT_SYMBOL(mdiobus_read); - - /** -+ * mdiobus_read_paged - Convenience function for reading a given paged MII mgmt register -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: register page to access -+ * @regnum: register number to read -+ * -+ * NOTE: MUST NOT be called from interrupt context, -+ * because the bus read/write functions may wait for an interrupt -+ * to conclude the operation. -+ */ -+int mdiobus_read_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum) -+{ -+ int retval; -+ -+ mutex_lock(&bus->mdio_lock); -+ retval = __mdiobus_read_paged(bus, addr, page, regnum); -+ mutex_unlock(&bus->mdio_lock); -+ -+ return retval; -+} -+EXPORT_SYMBOL(mdiobus_read_paged); -+ -+/** - * mdiobus_write_nested - Nested version of the mdiobus_write function - * @bus: the mii_bus struct - * @addr: the phy address -@@ -895,6 +1127,33 @@ int mdiobus_write_nested(struct mii_bus - EXPORT_SYMBOL(mdiobus_write_nested); - - /** -+ * mdiobus_write_paged_nested - Nested version of the mdiobus_write_aged function -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: the register page to access -+ * @regnum: register number to write -+ * @val: value to write to @regnum -+ * -+ * In case of nested MDIO bus access avoid lockdep false positives by -+ * using mutex_lock_nested(). -+ * -+ * NOTE: MUST NOT be called from interrupt context, -+ * because the bus read/write functions may wait for an interrupt -+ * to conclude the operation. -+ */ -+int mdiobus_write_paged_nested(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val) -+{ -+ int err; -+ -+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); -+ err = __mdiobus_write_paged(bus, addr, page, regnum, val); -+ mutex_unlock(&bus->mdio_lock); -+ -+ return err; -+} -+EXPORT_SYMBOL(mdiobus_write_paged_nested); -+ -+/** - * mdiobus_write - Convenience function for writing a given MII mgmt register - * @bus: the mii_bus struct - * @addr: the phy address -@@ -918,6 +1177,30 @@ int mdiobus_write(struct mii_bus *bus, i - EXPORT_SYMBOL(mdiobus_write); - - /** -+ * mdiobus_write_paged - Convenience function for writing a given paged MII mgmt register -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: the register page to access -+ * @regnum: register number to write -+ * @val: value to write to @regnum -+ * -+ * NOTE: MUST NOT be called from interrupt context, -+ * because the bus read/write functions may wait for an interrupt -+ * to conclude the operation. -+ */ -+int mdiobus_write_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val) -+{ -+ int err; -+ -+ mutex_lock(&bus->mdio_lock); -+ err = __mdiobus_write_paged(bus, addr, page, regnum, val); -+ mutex_unlock(&bus->mdio_lock); -+ -+ return err; -+} -+EXPORT_SYMBOL(mdiobus_write_paged); -+ -+/** - * mdiobus_modify - Convenience function for modifying a given mdio device - * register - * @bus: the mii_bus struct -@@ -939,6 +1222,51 @@ int mdiobus_modify(struct mii_bus *bus, - EXPORT_SYMBOL_GPL(mdiobus_modify); - - /** -+ * mdiobus_modify_paged - Convenience function for modifying a given mdio device -+ * register -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: the register page to access -+ * @regnum: register number to write -+ * @mask: bit mask of bits to clear -+ * @set: bit mask of bits to set -+ */ -+int mdiobus_modify_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 mask, u16 set) -+{ -+ int err; -+ -+ mutex_lock(&bus->mdio_lock); -+ err = __mdiobus_modify_changed_paged(bus, addr, page, regnum, mask, set); -+ mutex_unlock(&bus->mdio_lock); -+ -+ return err < 0 ? err : 0; -+} -+EXPORT_SYMBOL_GPL(mdiobus_modify_paged); -+ -+/** -+ * mdiobus_modify_changed_paged - Convenience function for modifying a given paged -+ * mdio device register and returning if it changed -+ * @bus: the mii_bus struct -+ * @addr: the phy address -+ * @page: the register page to access -+ * @regnum: register number to write -+ * @mask: bit mask of bits to clear -+ * @set: bit mask of bits to set -+ */ -+int mdiobus_modify_changed_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, -+ u16 mask, u16 set) -+{ -+ int err; -+ -+ mutex_lock(&bus->mdio_lock); -+ err = __mdiobus_modify_changed_paged(bus, addr, page, regnum, mask, set); -+ mutex_unlock(&bus->mdio_lock); -+ -+ return err; -+} -+EXPORT_SYMBOL_GPL(mdiobus_modify_changed_paged); -+ -+/** - * mdio_bus_match - determine if given MDIO driver supports the given - * MDIO device - * @dev: target MDIO device ---- a/drivers/net/phy/phy-core.c -+++ b/drivers/net/phy/phy-core.c -@@ -481,10 +481,16 @@ int __phy_read_mmd(struct phy_device *ph - struct mii_bus *bus = phydev->mdio.bus; - int phy_addr = phydev->mdio.addr; - -- mmd_phy_indirect(bus, phy_addr, devad, regnum); -- -- /* Read the content of the MMD's selected register */ -- val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA); -+ if (bus->access_capabilities & MDIOBUS_ACCESS_C22_MMD) { -+ val = __mdiobus_c22_mmd_read(phydev->mdio.bus, -+ phydev->mdio.addr, -+ devad, regnum); -+ } else { -+ mmd_phy_indirect(bus, phy_addr, devad, regnum); -+ -+ /* Read the content of the MMD's selected register */ -+ val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA); -+ } - } - return val; - } -@@ -537,12 +543,18 @@ int __phy_write_mmd(struct phy_device *p - struct mii_bus *bus = phydev->mdio.bus; - int phy_addr = phydev->mdio.addr; - -- mmd_phy_indirect(bus, phy_addr, devad, regnum); -+ if (bus->access_capabilities & MDIOBUS_ACCESS_C22_MMD) { -+ ret = __mdiobus_c22_mmd_write(phydev->mdio.bus, -+ phydev->mdio.addr, -+ devad, regnum, val); -+ } else { -+ mmd_phy_indirect(bus, phy_addr, devad, regnum); - -- /* Write the data into MMD's selected register */ -- __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val); -+ /* Write the data into MMD's selected register */ -+ __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val); - -- ret = 0; -+ ret = 0; -+ } - } - return ret; - } -@@ -748,6 +760,13 @@ EXPORT_SYMBOL_GPL(phy_modify_mmd); - - static int __phy_read_page(struct phy_device *phydev) - { -+ if (phydev->drv && phydev->drv->flags & PHY_HAS_REALTEK_PAGES) { -+ struct mii_bus *bus = phydev->mdio.bus; -+ int phy_addr = phydev->mdio.addr; -+ -+ return bus->selected_page[phy_addr]; -+ } -+ - if (WARN_ONCE(!phydev->drv->read_page, "read_page callback not available, PHY driver not loaded?\n")) - return -EOPNOTSUPP; - -@@ -756,6 +775,13 @@ static int __phy_read_page(struct phy_de - - static int __phy_write_page(struct phy_device *phydev, int page) - { -+ if (phydev->drv && phydev->drv->flags & PHY_HAS_REALTEK_PAGES) { -+ struct mii_bus *bus = phydev->mdio.bus; -+ int phy_addr = phydev->mdio.addr; -+ -+ return __mdiobus_select_page(bus, phy_addr, page); -+ } -+ - if (WARN_ONCE(!phydev->drv->write_page, "write_page callback not available, PHY driver not loaded?\n")) - return -EOPNOTSUPP; - -@@ -857,6 +883,18 @@ int phy_read_paged(struct phy_device *ph - { - int ret = 0, oldpage; - -+ if (phydev->drv && phydev->drv->flags & PHY_HAS_REALTEK_PAGES) { -+ struct mii_bus *bus = phydev->mdio.bus; -+ int phy_addr = phydev->mdio.addr; -+ -+ if (bus->read_paged) { -+ phy_lock_mdio_bus(phydev); -+ ret = bus->read_paged(bus, phy_addr, page, regnum); -+ phy_unlock_mdio_bus(phydev); -+ return ret; -+ } -+ } -+ - oldpage = phy_select_page(phydev, page); - if (oldpage >= 0) - ret = __phy_read(phydev, regnum); -@@ -878,6 +916,18 @@ int phy_write_paged(struct phy_device *p - { - int ret = 0, oldpage; - -+ if (phydev->drv && phydev->drv->flags & PHY_HAS_REALTEK_PAGES) { -+ struct mii_bus *bus = phydev->mdio.bus; -+ int phy_addr = phydev->mdio.addr; -+ -+ if (bus->write_paged) { -+ phy_lock_mdio_bus(phydev); -+ ret = bus->write_paged(bus, phy_addr, page, regnum, val); -+ phy_unlock_mdio_bus(phydev); -+ return ret; -+ } -+ } -+ - oldpage = phy_select_page(phydev, page); - if (oldpage >= 0) - ret = __phy_write(phydev, regnum, val); ---- a/include/linux/mdio.h -+++ b/include/linux/mdio.h -@@ -14,6 +14,7 @@ - * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. - */ - #define MII_ADDR_C45 (1<<30) -+#define MII_ADDR_C22_MMD (1<<29) - #define MII_DEVADDR_C45_SHIFT 16 - #define MII_DEVADDR_C45_MASK GENMASK(20, 16) - #define MII_REGADDR_C45_MASK GENMASK(15, 0) -@@ -327,11 +328,19 @@ static inline void mii_10gbt_stat_mod_li - advertising, lpa & MDIO_AN_10GBT_STAT_LP10G); - } - -+int __mdiobus_select_page(struct mii_bus *bus, int addr, u16 page); - int __mdiobus_read(struct mii_bus *bus, int addr, u32 regnum); - int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val); - int __mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum, - u16 mask, u16 set); - -+int __mdiobus_read_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum); -+int __mdiobus_write_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val); -+int __mdiobus_modify_changed_paged(struct mii_bus *bus, int addr, u32 regnum, u16 page, -+ u16 mask, u16 set); -+ -+int mdiobus_select_page(struct mii_bus *bus, int addr, u16 page); -+int mdiobus_select_page_nested(struct mii_bus *bus, int addr, u16 page); - int mdiobus_read(struct mii_bus *bus, int addr, u32 regnum); - int mdiobus_read_nested(struct mii_bus *bus, int addr, u32 regnum); - int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val); -@@ -339,11 +348,51 @@ int mdiobus_write_nested(struct mii_bus - int mdiobus_modify(struct mii_bus *bus, int addr, u32 regnum, u16 mask, - u16 set); - -+int mdiobus_read_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum); -+int mdiobus_read_nested_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum); -+int mdiobus_write_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val); -+int mdiobus_write_nested_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val); -+int mdiobus_modify_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 mask, -+ u16 set); -+int mdiobus_modify_changed_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, -+ u16 mask, u16 set); -+ -+static inline int mdiodev_read_paged(struct mdio_device *mdiodev, u16 page, -+ u32 regnum) -+{ -+ return mdiobus_read_paged(mdiodev->bus, mdiodev->addr, page, regnum); -+} -+ -+static inline int mdiodev_write_paged(struct mdio_device *mdiodev, u16 page, -+ u32 regnum, u16 val) -+{ -+ return mdiobus_write_paged(mdiodev->bus, mdiodev->addr, page, regnum, val); -+} -+ -+static inline int mdiodev_modify_paged(struct mdio_device *mdiodev, u16 page, -+ u32 regnum, u16 mask, u16 set) -+{ -+ return mdiobus_modify_paged(mdiodev->bus, mdiodev->addr, page, regnum, -+ mask, set); -+} -+ -+static inline int mdiodev_modify_changed_paged(struct mdio_device *mdiodev, u16 page, -+ u32 regnum, u16 mask, u16 set) -+{ -+ return mdiobus_modify_changed_paged(mdiodev->bus, mdiodev->addr, page, regnum, -+ mask, set); -+} -+ - static inline u32 mdiobus_c45_addr(int devad, u16 regnum) - { - return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; - } - -+static inline u32 mdiobus_c22_mmd_addr(int devad, u16 regnum) -+{ -+ return MII_ADDR_C22_MMD | devad << MII_DEVADDR_C45_SHIFT | regnum; -+} -+ - static inline u16 mdiobus_c45_regad(u32 regnum) - { - return FIELD_GET(MII_REGADDR_C45_MASK, regnum); -@@ -367,6 +416,19 @@ static inline int __mdiobus_c45_write(st - val); - } - -+static inline int __mdiobus_c22_mmd_read(struct mii_bus *bus, int prtad, -+ int devad, u16 regnum) -+{ -+ return __mdiobus_read(bus, prtad, mdiobus_c22_mmd_addr(devad, regnum)); -+} -+ -+static inline int __mdiobus_c22_mmd_write(struct mii_bus *bus, int prtad, -+ int devad, u16 regnum, u16 val) -+{ -+ return __mdiobus_write(bus, prtad, mdiobus_c22_mmd_addr(devad, regnum), -+ val); -+} -+ - static inline int mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad, - u16 regnum) - { ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -80,6 +80,7 @@ extern const int phy_10gbit_features_arr - #define PHY_IS_INTERNAL 0x00000001 - #define PHY_RST_AFTER_CLK_EN 0x00000002 - #define PHY_POLL_CABLE_TEST 0x00000004 -+#define PHY_HAS_REALTEK_PAGES 0x00000010 - #define MDIO_DEVICE_IS_PHY 0x80000000 - - /** -@@ -374,6 +375,22 @@ struct mii_bus { - - /** @shared: shared state across different PHYs */ - struct phy_package_shared *shared[PHY_MAX_ADDR]; -+ -+ /** @access_capabilities: hardware-assisted access capabilties */ -+ enum { -+ MDIOBUS_ACCESS_SOFTWARE_ONLY = 0, -+ MDIOBUS_ACCESS_C22_MMD = 0x1, -+ } access_capabilities; -+ -+ /** @read: Perform a read transfer on the bus, offloading page access */ -+ int (*read_paged)(struct mii_bus *bus, int addr, u16 page, int regnum); -+ /** @write: Perform a write transfer on the bus, offloading page access */ -+ int (*write_paged)(struct mii_bus *bus, int addr, u16 page, int regnum, u16 val); -+ /** currently selected page when page access is offloaded -+ * array should be PHY_MAX_ADDR+1size, but current design of the MDIO driver -+ * uses port addresses as phy addresses and they are up to 6 bit. -+ */ -+ u16 selected_page[64]; - }; - #define to_mii_bus(d) container_of(d, struct mii_bus, dev) - -@@ -1651,6 +1668,66 @@ static inline int __phy_package_read(str - return __mdiobus_read(phydev->mdio.bus, shared->addr, regnum); - } - -+static inline int phy_package_read_port(struct phy_device *phydev, u16 port, u32 regnum) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return mdiobus_read(phydev->mdio.bus, shared->addr + port, regnum); -+} -+ -+static inline int __phy_package_read_port(struct phy_device *phydev, u16 port, u32 regnum) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return __mdiobus_read(phydev->mdio.bus, shared->addr + port, regnum); -+} -+ -+static inline int phy_package_read_paged(struct phy_device *phydev, u16 page, u32 regnum) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return mdiobus_read_paged(phydev->mdio.bus, shared->addr, page, regnum); -+} -+ -+static inline int __phy_package_read_paged(struct phy_device *phydev, u16 page, u32 regnum) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return __mdiobus_read_paged(phydev->mdio.bus, shared->addr, page, regnum); -+} -+ -+static inline int phy_package_port_read_paged(struct phy_device *phydev, u16 port, u16 page, u32 regnum) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return mdiobus_read_paged(phydev->mdio.bus, shared->addr + port, page, regnum); -+} -+ -+static inline int __phy_package_port_read_paged(struct phy_device *phydev, u16 port, u16 page, u32 regnum) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return __mdiobus_read_paged(phydev->mdio.bus, shared->addr + port, page, regnum); -+} -+ - static inline int phy_package_write(struct phy_device *phydev, - u32 regnum, u16 val) - { -@@ -1673,6 +1750,72 @@ static inline int __phy_package_write(st - return __mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val); - } - -+static inline int phy_package_port_write(struct phy_device *phydev, -+ u16 port, u32 regnum, u16 val) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return mdiobus_write(phydev->mdio.bus, shared->addr + port, regnum, val); -+} -+ -+static inline int __phy_package_port_write(struct phy_device *phydev, -+ u16 port, u32 regnum, u16 val) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return __mdiobus_write(phydev->mdio.bus, shared->addr + port, regnum, val); -+} -+ -+static inline int phy_package_port_write_paged(struct phy_device *phydev, -+ u16 port, u16 page, u32 regnum, u16 val) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return mdiobus_write_paged(phydev->mdio.bus, shared->addr + port, page, regnum, val); -+} -+ -+static inline int __phy_package_port_write_paged(struct phy_device *phydev, -+ u16 port, u16 page, u32 regnum, u16 val) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return __mdiobus_write_paged(phydev->mdio.bus, shared->addr + port, page, regnum, val); -+} -+ -+static inline int phy_package_write_paged(struct phy_device *phydev, -+ u16 page, u32 regnum, u16 val) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return mdiobus_write_paged(phydev->mdio.bus, shared->addr, page, regnum, val); -+} -+ -+static inline int __phy_package_write_paged(struct phy_device *phydev, -+ u16 page, u32 regnum, u16 val) -+{ -+ struct phy_package_shared *shared = phydev->shared; -+ -+ if (!shared) -+ return -EIO; -+ -+ return __mdiobus_write_paged(phydev->mdio.bus, shared->addr, page, regnum, val); -+} -+ - static inline bool __phy_package_set_once(struct phy_device *phydev, - unsigned int b) - { ---- a/include/uapi/linux/mii.h -+++ b/include/uapi/linux/mii.h -@@ -36,6 +36,7 @@ - #define MII_RESV2 0x1a /* Reserved... */ - #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ - #define MII_NCONFIG 0x1c /* Network interface config */ -+#define MII_MAINPAGE 0x1f /* Page register */ - - /* Basic mode control register. */ - #define BMCR_RESV 0x003f /* Unused... */ diff --git a/target/linux/realtek/rtl838x/config-5.10 b/target/linux/realtek/rtl838x/config-5.10 deleted file mode 100644 index e763557a9f..0000000000 --- a/target/linux/realtek/rtl838x/config-5.10 +++ /dev/null @@ -1,227 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BMIPS_CPUFREQ is not set -# CONFIG_CEVT_R4K is not set -# CONFIG_CEVT_RTL9300 is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_COMMON_CLK_REALTEK=y -CONFIG_COMMON_CLK_RTL83XX=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_CPUFREQ=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_RNG2=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EARLY_PRINTK_8250=y -CONFIG_EXTRA_FIRMWARE="rtl838x_phy/rtl838x_8214fc.fw rtl838x_phy/rtl838x_8218b.fw rtl838x_phy/rtl838x_8380.fw" -CONFIG_EXTRA_FIRMWARE_DIR="firmware" -CONFIG_FIXED_PHY=y -CONFIG_FORCE_MAX_ZONEORDER=13 -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_REALTEK_OTTO=y -CONFIG_GPIO_RTL8231=y -CONFIG_GPIO_WATCHDOG=y -# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HWMON=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_MUX=y -# CONFIG_I2C_RTL9300 is not set -# CONFIG_I2C_MUX_RTL9300 is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_JFFS2_ZLIB=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_I2C=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_EXTERNAL_TIMER=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_BRNIMAGE_FW=y -CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_H3C_VFS=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_RTL83XX=y -CONFIG_NET_DSA_TAG_TRAILER=y -CONFIG_NET_RTL838X=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NO_EXCEPT_FILL=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_RATIONAL=y -CONFIG_REALTEK_OTTO_TIMER=y -CONFIG_REALTEK_OTTO_WDT=y -CONFIG_REALTEK_PHY=y -CONFIG_REALTEK_SOC_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RTL83XX=y -CONFIG_RTL838X=y -# CONFIG_RTL839X is not set -# CONFIG_RTL930X is not set -# CONFIG_RTL931X is not set -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SFP=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRAM=y -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/realtek/rtl839x/config-5.10 b/target/linux/realtek/rtl839x/config-5.10 deleted file mode 100644 index d464c72225..0000000000 --- a/target/linux/realtek/rtl839x/config-5.10 +++ /dev/null @@ -1,223 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BMIPS_CPUFREQ is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -CONFIG_COMMON_CLK_REALTEK=y -CONFIG_COMMON_CLK_RTL83XX=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_CPUFREQ=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EARLY_PRINTK_8250=y -CONFIG_FIXED_PHY=y -CONFIG_FORCE_MAX_ZONEORDER=13 -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_PCA953X_IRQ=y -CONFIG_GPIO_REALTEK_OTTO=y -CONFIG_GPIO_RTL8231=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HWMON=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_GPIO=y -# CONFIG_I2C_RTL9300 is not set -# CONFIG_I2C_MUX_RTL9300 is not set -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_JFFS2_ZLIB=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LLD_VERSION=0 -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_I2C=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_EXTERNAL_TIMER=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_MT_SMP=y -# CONFIG_MIPS_MT_FPAFF is not set -CONFIG_NR_CPUS=2 -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_BRNIMAGE_FW=y -CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_VIRT_CONCAT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_RTL83XX=y -CONFIG_NET_DSA_TAG_TRAILER=y -CONFIG_NET_RTL838X=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NO_EXCEPT_FILL=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_RATIONAL=y -CONFIG_REALTEK_OTTO_TIMER=y -CONFIG_REALTEK_OTTO_WDT=y -CONFIG_REALTEK_PHY=y -CONFIG_REALTEK_SOC_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RTL83XX=y -# CONFIG_RTL838X is not set -CONFIG_RTL839X=y -# CONFIG_RTL930X is not set -# CONFIG_RTL931X is not set -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SFP=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRAM=y -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/realtek/rtl930x/config-5.10 b/target/linux/realtek/rtl930x/config-5.10 deleted file mode 100644 index f61a200c91..0000000000 --- a/target/linux/realtek/rtl930x/config-5.10 +++ /dev/null @@ -1,210 +0,0 @@ -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_CEVT_RTL9300=y -# CONFIG_CEVT_R4K is not set -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -# CONFIG_COMMON_CLK_REALTEK is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_EARLY_PRINTK_8250=y -CONFIG_FIXED_PHY=y -CONFIG_FORCE_MAX_ZONEORDER=13 -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_PCA953X=y -CONFIG_GPIO_REALTEK_OTTO=y -CONFIG_GPIO_RTL8231=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HWMON=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_RTL9300=y -CONFIG_I2C_RTL9300=y -CONFIG_I2C_SMBUS=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_JFFS2_ZLIB=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LLD_VERSION=0 -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_I2C=y -CONFIG_MDIO_SMBUS=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_FPAFF is not set -CONFIG_NR_CPUS=2 -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_BRNIMAGE_FW=y -CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_RTL83XX=y -CONFIG_NET_DSA_TAG_TRAILER=y -CONFIG_NET_RTL838X=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NO_EXCEPT_FILL=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_RATIONAL=y -# CONFIG_REALTEK_OTTO_TIMER is not set -CONFIG_REALTEK_OTTO_WDT=y -CONFIG_REALTEK_PHY=y -CONFIG_REALTEK_SOC_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RTL83XX=y -# CONFIG_RTL838X is not set -# CONFIG_RTL839X is not set -CONFIG_RTL930X=y -# CONFIG_RTL931X is not set -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SFP=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y -CONFIG_USE_OF=y -CONFIG_WATCHDOG_CORE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/realtek/rtl931x/config-5.10 b/target/linux/realtek/rtl931x/config-5.10 deleted file mode 100644 index 36e7486804..0000000000 --- a/target/linux/realtek/rtl931x/config-5.10 +++ /dev/null @@ -1,224 +0,0 @@ -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MMAP_RND_BITS_MAX=15 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15 -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_BOSTON is not set -# CONFIG_COMMON_CLK_REALTEK is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_DIEI=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_MIPS_MT=y -CONFIG_MIPS_MT_FPAFF=y -CONFIG_MIPS_MT_SMP=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_NR_CPU_NR_MAP=4 -CONFIG_HIGHMEM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2 -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CSRC_R4K=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -CONFIG_EARLY_PRINTK=y -CONFIG_FIXED_PHY=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_LIB_ASHLDI3=y -CONFIG_GENERIC_LIB_ASHRDI3=y -CONFIG_GENERIC_LIB_CMPDI2=y -CONFIG_GENERIC_LIB_LSHRDI3=y -CONFIG_GENERIC_LIB_UCMPDI2=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_REALTEK_OTTO=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_RTL8231=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_HWMON=y -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_GPIO=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MUX_RTL9300=y -CONFIG_I2C_RTL9300=y -CONFIG_I2C_SMBUS=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_JFFS2_ZLIB=y -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_LLD_VERSION=0 -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_MARVELL_PHY=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_I2C=y -CONFIG_MDIO_SMBUS=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CBPF_JIT=y -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_MIPS_LD_CAN_LINK_VDSO=y -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_BRNIMAGE_FW=y -CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_RTL83XX=y -CONFIG_NET_DSA_TAG_RTL83XX=y -CONFIG_NET_DSA_TAG_TRAILER=y -CONFIG_NET_RTL838X=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NO_EXCEPT_FILL=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PINCTRL=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_RATIONAL=y -# CONFIG_REALTEK_OTTO_TIMER is not set -# CONFIG_REALTEK_PHY is not set -CONFIG_REALTEK_SOC_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RTL838X=y -# CONFIG_RTL9300_TIMER is not set -CONFIG_SENSORS_GPIO_FAN=y -CONFIG_SENSORS_LM75=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SFP=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SRCU=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_TARGET_ISA_REV=2 -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TINY_SRCU=y -# CONFIG_USE_GENERIC_EARLY_PRINTK_8250 is not set -CONFIG_USE_OF=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_FORCE_MAX_ZONEORDER=13 -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_MIPS_CPU_SCACHE=y -CONFIG_SPI_RTL838X=y -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_CPC=y -CONFIG_MIPS_CPS=y -CONFIG_MIPS_PM=y -# CONFIG_MIPS_CMP is not set -CONFIG_MIPS_CPS_CPUIDLE=y -# CONFIG_MIPS_CPS_NS16550_BOOL is not set -CONFIG_SMP=y -CONFIG_NR_CPUS=2 -CONFIG_RTL83XX=y -# CONFIG_RTL838X is not set -# CONFIG_RTL839X is not set -CONFIG_RTL930X=y -CONFIG_RTL931X=y -CONFIG_REALTEK_OTTO_WDT=y diff --git a/target/linux/rockchip/armv8/config-5.10 b/target/linux/rockchip/armv8/config-5.10 deleted file mode 100644 index 637c54be6f..0000000000 --- a/target/linux/rockchip/armv8/config-5.10 +++ /dev/null @@ -1,644 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=33 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARC_EMAC_CORE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CNP=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_ERRATUM_858921=y -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_MODULE_PLTS=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PAN=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_SVE=y -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_UAO=y -CONFIG_ARM64_VA_BITS=48 -# CONFIG_ARM64_VA_BITS_39 is not set -CONFIG_ARM64_VA_BITS_48=y -CONFIG_ARM64_VHE=y -CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -# CONFIG_ARMV8_DEPRECATED is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_CPUIDLE=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MHU=y -CONFIG_ARM_PSCI_CPUIDLE=y -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set -# CONFIG_ARM_SCMI_PROTOCOL is not set -CONFIG_ARM_SCPI_CPUFREQ=y -CONFIG_ARM_SCPI_POWER_DOMAIN=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y -# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set -CONFIG_ARM_SMMU_V3=y -# CONFIG_ARM_SMMU_V3_SVA is not set -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BRCMSTB_GISB_ARB=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -# CONFIG_CHARGER_BQ25980 is not set -CONFIG_CHARGER_GPIO=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLK_PX30=y -CONFIG_CLK_RK3036=y -CONFIG_CLK_RK312X=y -CONFIG_CLK_RK3188=y -CONFIG_CLK_RK322X=y -CONFIG_CLK_RK3308=y -CONFIG_CLK_RK3328=y -CONFIG_CLK_RK3368=y -CONFIG_CLK_RK3399=y -CONFIG_CLK_RV110X=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=5 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_RK808=y -CONFIG_COMMON_CLK_ROCKCHIP=y -CONFIG_COMMON_CLK_SCPI=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTIG_ALLOC=y -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_ISOLATION=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CRC_T10DIF=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_DEV_ROCKCHIP is not set -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SIMD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DEVMEM=y -# CONFIG_DEVPORT is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DNOTIFY=y -# CONFIG_DRM_ROCKCHIP is not set -CONFIG_DTC=y -CONFIG_DT_IDLE_STATES=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DWMAC_DWC_QOS_ETH=y -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_ROCKCHIP=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EEPROM_AT24=y -CONFIG_EMAC_ROCKCHIP=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_ENERGY_MODEL=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FANOTIFY=y -CONFIG_FHANDLE=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FLATMEM_MANUAL is not set -# CONFIG_FORTIFY_SOURCE is not set -CONFIG_FRAME_POINTER=y -CONFIG_FRAME_WARN=2048 -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_DWAPB=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HID=y -CONFIG_HID_GENERIC=y -# CONFIG_HISI_HIKEY_USB is not set -CONFIG_HOLES_IN_ZONE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_PCIE is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set -CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_HWMON=y -CONFIG_HWSPINLOCK=y -CONFIG_HW_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_RK3X=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INDIRECT_PIO=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_MATRIXKMAP=y -# CONFIG_INPUT_RK805_PWRKEY is not set -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_IO_PGTABLE=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_SUPPORT=y -# CONFIG_IO_STRICT_DEVMEM is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JFFS2_ZLIB=y -CONFIG_JUMP_LABEL=y -CONFIG_KALLSYMS=y -CONFIG_KEXEC_CORE=y -CONFIG_KEXEC_FILE=y -CONFIG_KSM=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LEDS_GPIO=y -# CONFIG_LEDS_LP50XX is not set -CONFIG_LEDS_PWM=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LIBCRC32C=y -CONFIG_LIBFDT=y -CONFIG_LOCALVERSION_AUTO=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOG_BUF_SHIFT=19 -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MANDATORY_FILE_LOCKING=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_BUS_MUX=y -CONFIG_MDIO_BUS_MUX_GPIO=y -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_DEVICE=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_KHADAS_MCU is not set -CONFIG_MFD_RK808=y -# CONFIG_MFD_ROHM_BD71828 is not set -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_CQHCI=y -CONFIG_MMC_DW=y -# CONFIG_MMC_DW_BLUEFIELD is not set -# CONFIG_MMC_DW_EXYNOS is not set -# CONFIG_MMC_DW_HI3798CV200 is not set -# CONFIG_MMC_DW_K3 is not set -# CONFIG_MMC_DW_PCI is not set -CONFIG_MMC_DW_PLTFM=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_OF_ARASAN=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MQ_IOSCHED_DEADLINE=y -# CONFIG_MTD_CFI is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=256 -CONFIG_NVMEM=y -CONFIG_NVMEM_ROCKCHIP_EFUSE=y -# CONFIG_NVMEM_ROCKCHIP_OTP is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_NVME_CORE=y -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_MULTIPATH is not set -# CONFIG_NVME_TCP is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGSUSPEND3=y -# CONFIG_OVERLAY_FS_XINO_AUTO is not set -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_PME=y -CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_HOST=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_STUB=y -CONFIG_PCS_XPCS=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_ROCKCHIP_DP=y -# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set -CONFIG_PHY_ROCKCHIP_EMMC=y -# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_PCIE=y -CONFIG_PHY_ROCKCHIP_TYPEC=y -CONFIG_PHY_ROCKCHIP_USB=y -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_RK805 is not set -CONFIG_PINCTRL_ROCKCHIP=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PL330_DMA=y -CONFIG_PLATFORM_MHU=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_VMCORE=y -CONFIG_PWM=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_PWM_SYSFS=y -# CONFIG_QFMT_V1 is not set -# CONFIG_QFMT_V2 is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_QUOTA=y -CONFIG_QUOTACTL=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_RAID_ATTRS=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_RANDOMIZE_MODULE_REGION_FULL=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_RCU_TRACE=y -CONFIG_REALTEK_PHY=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_IRQ=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_RK808=y -# CONFIG_REGULATOR_RT4801 is not set -# CONFIG_REGULATOR_RTMV20 is not set -CONFIG_RELOCATABLE=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_ROCKCHIP_GRF=y -CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_IOMMU=y -CONFIG_ROCKCHIP_MBOX=y -CONFIG_ROCKCHIP_PHY=y -CONFIG_ROCKCHIP_PM_DOMAINS=y -# CONFIG_ROCKCHIP_SARADC is not set -CONFIG_ROCKCHIP_THERMAL=y -CONFIG_ROCKCHIP_TIMER=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RSEQ=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_RK808=y -# CONFIG_RTC_DRV_RV3032 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_NVMEM=y -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SCSI_SAS_ATTRS=y -CONFIG_SCSI_SAS_HOST_SMP=y -CONFIG_SCSI_SAS_LIBSAS=y -# CONFIG_SECURITY_DMESG_RESTRICT is not set -CONFIG_SENSORS_ARM_SCPI=y -# CONFIG_SENSORS_MR75203 is not set -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_DWLIB=y -CONFIG_SERIAL_8250_EXAR=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_AMBA_PL011=y -CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIO=y -CONFIG_SERIO_AMBAKMI=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SG_POOL=y -CONFIG_SIMPLE_PM_BUS=y -CONFIG_SLUB_DEBUG=y -CONFIG_SMP=y -# CONFIG_SND_SOC_ROCKCHIP is not set -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_SPIDEV=y -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -CONFIG_SRAM=y -CONFIG_SRCU=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_PLATFORM=y -# CONFIG_STMMAC_SELFTESTS is not set -CONFIG_STRICT_DEVMEM=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_SWAP is not set -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYNC_FILE=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -# CONFIG_TEXTSEARCH is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_CLOCK=y -CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_TYPEC=y -# CONFIG_TYPEC_DP_ALTMODE is not set -CONFIG_TYPEC_FUSB302=y -# CONFIG_TYPEC_HD3SS3220 is not set -# CONFIG_TYPEC_MUX_PI3USB30532 is not set -# CONFIG_TYPEC_STUSB160X is not set -# CONFIG_TYPEC_TCPCI is not set -CONFIG_TYPEC_TCPM=y -# CONFIG_TYPEC_TPS6598X is not set -# CONFIG_UACCE is not set -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UEVENT_HELPER is not set -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_HOST=y -CONFIG_USB_DWC3_OF_SIMPLE=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_HID=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -# CONFIG_VIRTIO_MENU is not set -CONFIG_VMAP_STACK=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_WATCHDOG is not set -CONFIG_XARRAY_MULTI=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/rockchip/patches-5.10/004-v5.13-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.10/004-v5.13-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch deleted file mode 100644 index 461a5ae7dd..0000000000 --- a/target/linux/rockchip/patches-5.10/004-v5.13-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch +++ /dev/null @@ -1,177 +0,0 @@ -From db792e9adbf85ffc9d6b0b060ac3c8e3148c8992 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Fri, 19 Mar 2021 13:16:27 +0800 -Subject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S - -This adds support for the NanoPi R4S from FriendlyArm. - -Rockchip RK3399 SoC -1GB DDR3 or 4GB LPDDR4 RAM -Gigabit Ethernet (WAN) -Gigabit Ethernet (PCIe) (LAN) -USB 3.0 Port x 2 -MicroSD slot -Reset button -WAN - LAN - SYS LED - -Co-developed-by: Jensen Huang -Signed-off-by: Jensen Huang -[minor adjustments] -Co-developed-by: Marty Jones -Signed-off-by: Marty Jones -[further adjustments, fixed format issues] -Signed-off-by: Tianling Shen -Link: https://lore.kernel.org/r/20210319051627.814-2-cnsztl@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 133 +++++++++++++++++++++ - 2 files changed, 134 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -0,0 +1,133 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * FriendlyElec NanoPC-T4 board device tree source -+ * -+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2018 Collabora Ltd. -+ * -+ * Copyright (c) 2020 Jensen Huang -+ * Copyright (c) 2020 Marty Jones -+ * Copyright (c) 2021 Tianling Shen -+ */ -+ -+/dts-v1/; -+#include "rk3399-nanopi4.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R4S"; -+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; -+ -+ /delete-node/ display-subsystem; -+ -+ gpio-leds { -+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -+ -+ /delete-node/ led-0; -+ -+ lan_led: led-lan { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "green:lan"; -+ }; -+ -+ sys_led: led-sys { -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ label = "red:sys"; -+ default-state = "on"; -+ }; -+ -+ wan_led: led-wan { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "green:wan"; -+ }; -+ }; -+ -+ gpio-keys { -+ pinctrl-0 = <&reset_button_pin>; -+ -+ /delete-node/ power; -+ -+ reset { -+ debounce-interval = <50>; -+ gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ label = "reset"; -+ linux,code = ; -+ }; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+}; -+ -+&emmc_phy { -+ status = "disabled"; -+}; -+ -+&i2c4 { -+ status = "disabled"; -+}; -+ -+&pcie0 { -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ /delete-node/ status-led-pin; -+ -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ rockchip-key { -+ /delete-node/ power-key; -+ -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&sdhci { -+ status = "disabled"; -+}; -+ -+&sdio0 { -+ status = "disabled"; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vdd_5v>; -+}; -+ -+&u2phy1_host { -+ status = "disabled"; -+}; -+ -+&uart0 { -+ status = "disabled"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+}; -+ -+&vcc3v3_sys { -+ vin-supply = <&vcc5v0_sys>; -+}; diff --git a/target/linux/rockchip/patches-5.10/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.10/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch deleted file mode 100644 index 792028b292..0000000000 --- a/target/linux/rockchip/patches-5.10/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch +++ /dev/null @@ -1,31 +0,0 @@ -From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Mon, 7 Jun 2021 15:45:37 +0800 -Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S - -NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which -stores the MAC address. - -Signed-off-by: Tianling Shen ---- - arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++ - 1 file changed, 9 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -68,6 +68,15 @@ - status = "disabled"; - }; - -+&i2c2 { -+ eeprom@51 { -+ compatible = "microchip,24c02", "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ read-only; /* This holds our MAC */ -+ }; -+}; -+ - &i2c4 { - status = "disabled"; - }; diff --git a/target/linux/rockchip/patches-5.10/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.10/100-rockchip-use-system-LED-for-OpenWrt.patch deleted file mode 100644 index 7b3b50ffd8..0000000000 --- a/target/linux/rockchip/patches-5.10/100-rockchip-use-system-LED-for-OpenWrt.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Fri, 10 Jul 2020 21:38:20 +0200 -Subject: [PATCH] rockchip: use system LED for OpenWrt - -Use the SYS LED on the casing for showing system status. - -This patch is kept separate from the NanoPi R2S support patch, as i plan -on submitting the device support upstream. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -13,6 +13,13 @@ - model = "FriendlyElec NanoPi R2S"; - compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; - -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ }; -+ - chosen { - stdout-path = "serial2:1500000n8"; - }; diff --git a/target/linux/rockchip/patches-5.10/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch b/target/linux/rockchip/patches-5.10/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch deleted file mode 100644 index 2dd6e40ebf..0000000000 --- a/target/linux/rockchip/patches-5.10/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch +++ /dev/null @@ -1,70 +0,0 @@ -From: William Wu - -RK3328 has one USB 3.0 OTG controller which uses DWC_USB3 -core's general architecture. It can act as static xHCI host -controller, static device controller, USB 3.0/2.0 OTG basing -on ID of USB3.0 PHY. - -Signed-off-by: William Wu -Signed-off-by: Leonidas P. Papadakos - ---- - -NOTE: This binding still has issues. From the original thread: - -the rk3328 usb3-phy has an issue with detecting any plugin events -after a previous device got removed - see the inno-usb3-phy driver -in the vendor kernel. - -The current state is good-enough for enabling the USB3 attached LAN -port of the NanoPi R2S. However, it might explode depending on your -use-case. You've been warned. - ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -985,22 +985,30 @@ - }; - - usbdrd3: usb@ff600000 { -- compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; -- reg = <0x0 0xff600000 0x0 0x100000>; -- interrupts = ; -+ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3"; - clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, - <&cru ACLK_USB3OTG>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk"; -- dr_mode = "otg"; -- phy_type = "utmi_wide"; -- snps,dis-del-phy-power-chg-quirk; -- snps,dis_enblslpm_quirk; -- snps,dis-tx-ipgap-linecheck-quirk; -- snps,dis-u2-freeclk-exists-quirk; -- snps,dis_u2_susphy_quirk; -- snps,dis_u3_susphy_quirk; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; - status = "disabled"; -+ -+ usbdrd_dwc3: dwc3@ff600000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0xff600000 0x0 0x100000>; -+ interrupts = ; -+ dr_mode = "otg"; -+ phy_type = "utmi_wide"; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ status = "disabled"; -+ }; - }; - - gic: interrupt-controller@ff811000 { diff --git a/target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch deleted file mode 100644 index 48e8d472c8..0000000000 --- a/target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Fri, 10 Jul 2020 21:12:16 +0200 -Subject: [PATCH] rockchip: enabled LAN port on NanoPi R2S - -Enable the USB3 port on the FriendlyARM NanoPi R2S. -This is required for the USB3 attached LAN port to work. - -Signed-off-by: David Bauer ---- - .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 27 +++++++++++++++++++ - 1 file changed, 27 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -44,6 +44,18 @@ - }; - }; - -+ vcc_rtl8153: vcc-rtl8153-regulator { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rtl8153_en_drv>; -+ regulator-always-on; -+ regulator-name = "vcc_rtl8153"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ }; -+ - leds { - compatible = "gpio-leds"; - pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; -@@ -271,6 +283,12 @@ - }; - }; - }; -+ -+ usb { -+ rtl8153_en_drv: rtl8153-en-drv { -+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; - }; - - &io_domains { -@@ -377,3 +395,12 @@ - &usb_host0_ohci { - status = "okay"; - }; -+ -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch deleted file mode 100644 index dfc71a2701..0000000000 --- a/target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Sun, 26 Jul 2020 13:32:59 +0200 -Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S - -This adds the OF node for the USB3 ethernet adapter on the FriendlyARM -NanoPi R2S. Add the correct value for the RTL8153 LED configuration -register to match the blink behavior of the other port on the device. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -403,4 +403,11 @@ - &usbdrd_dwc3 { - dr_mode = "host"; - status = "okay"; -+ -+ usb-eth@2 { -+ compatible = "realtek,rtl8153"; -+ reg = <2>; -+ -+ realtek,led-data = <0x87>; -+ }; - }; diff --git a/target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch b/target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch deleted file mode 100644 index 56166783a5..0000000000 --- a/target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch +++ /dev/null @@ -1,32 +0,0 @@ -From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001 -From: Vicente Bergas -Date: Tue, 1 Dec 2020 16:41:32 +0100 -Subject: arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4 - -Based on the board schematics at -https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf -on page 19 there is an USB Type-A receptacle being used as an USB-OTG port. - -But the Type-A connector is not valid for OTG operation, for this reason -there is a switch to select host or device role. -This is non-compliant and error prone because switching is manual. -So, use host mode as it corresponds for a Type-A receptacle. - -Signed-off-by: Vicente Bergas -Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -679,7 +679,7 @@ - - &usbdrd_dwc3_0 { - status = "okay"; -- dr_mode = "otg"; -+ dr_mode = "host"; - }; - - &usbdrd3_1 { diff --git a/target/linux/rockchip/patches-5.10/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-5.10/105-nanopi-r4s-sd-signalling.patch deleted file mode 100644 index a04c14b70a..0000000000 --- a/target/linux/rockchip/patches-5.10/105-nanopi-r4s-sd-signalling.patch +++ /dev/null @@ -1,26 +0,0 @@ -From: David Bauer -Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S - -The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting -while U-Boot requires the card to be in 3.3V mode. - -Remove UHS support from the SD controller so the card remains in 3.3V -mode. This reduces transfer speeds but ensures a reboot whether from -userspace or following a kernel panic is always working. - -Signed-off-by: David Bauer - ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -121,6 +121,11 @@ - status = "disabled"; - }; - -+&sdmmc { -+ /delete-property/ sd-uhs-sdr104; -+ cap-sd-highspeed; -+}; -+ - &u2phy0_host { - phy-supply = <&vdd_5v>; - }; diff --git a/target/linux/rockchip/patches-5.10/106-r4s-openwrt-leds.patch b/target/linux/rockchip/patches-5.10/106-r4s-openwrt-leds.patch deleted file mode 100644 index d7579d61e9..0000000000 --- a/target/linux/rockchip/patches-5.10/106-r4s-openwrt-leds.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -19,6 +19,13 @@ - model = "FriendlyElec NanoPi R4S"; - compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ }; -+ - /delete-node/ display-subsystem; - - gpio-leds { diff --git a/target/linux/sunxi/cortexa53/config-5.10 b/target/linux/sunxi/cortexa53/config-5.10 deleted file mode 100644 index 952b09b6ea..0000000000 --- a/target/linux/sunxi/cortexa53/config-5.10 +++ /dev/null @@ -1,96 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -# CONFIG_ARM64_PTR_AUTH is not set -# CONFIG_ARM64_SVE is not set -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SIMD=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DWMAC_SUN8I=y -CONFIG_EEPROM_AT24=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_FRAME_POINTER=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_MDIO_BUS_MUX=y -CONFIG_MICREL_PHY=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MUSB_PIO_ONLY=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_IOPORT_MAP=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PHY_SUN50I_USB3=y -CONFIG_PINCTRL_SUN50I_A100=y -CONFIG_PINCTRL_SUN50I_A100_R=y -CONFIG_PINCTRL_SUN50I_A64=y -CONFIG_PINCTRL_SUN50I_A64_R=y -CONFIG_PINCTRL_SUN50I_H5=y -CONFIG_PINCTRL_SUN50I_H6=y -CONFIG_PINCTRL_SUN50I_H6_R=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RTC_DRV_SUN6I=y -# CONFIG_SND_SUN50I_CODEC_ANALOG is not set -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SUN50I_A100_CCU=y -CONFIG_SUN50I_A100_R_CCU=y -CONFIG_SUN50I_A64_CCU=y -CONFIG_SUN50I_DE2_BUS=y -CONFIG_SUN50I_ERRATUM_UNKNOWN1=y -CONFIG_SUN50I_H6_CCU=y -CONFIG_SUN50I_H6_R_CCU=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_UNMAP_KERNEL_AT_EL0=y -CONFIG_USB_MUSB_DUAL_ROLE=y -# CONFIG_USB_MUSB_GADGET is not set -CONFIG_USB_MUSB_HDRC=y -# CONFIG_USB_MUSB_HOST is not set -CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_PHY=y -CONFIG_VMAP_STACK=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/sunxi/cortexa7/config-5.10 b/target/linux/sunxi/cortexa7/config-5.10 deleted file mode 100644 index 90e977b566..0000000000 --- a/target/linux/sunxi/cortexa7/config-5.10 +++ /dev/null @@ -1,26 +0,0 @@ -CONFIG_B53=y -CONFIG_B53_MDIO_DRIVER=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_DWMAC_SUN8I=y -CONFIG_GRO_CELLS=y -# CONFIG_MACH_SUN4I is not set -# CONFIG_MACH_SUN5I is not set -CONFIG_MDIO_BUS_MUX=y -CONFIG_MICREL_PHY=y -CONFIG_MUSB_PIO_ONLY=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_TAG_BRCM=y -CONFIG_NET_DSA_TAG_BRCM_COMMON=y -CONFIG_NET_DSA_TAG_BRCM_LEGACY=y -CONFIG_NET_DSA_TAG_BRCM_PREPEND=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_RTC_DRV_SUN6I=y -CONFIG_USB_MUSB_DUAL_ROLE=y -# CONFIG_USB_MUSB_GADGET is not set -CONFIG_USB_MUSB_HDRC=y -# CONFIG_USB_MUSB_HOST is not set -CONFIG_USB_MUSB_SUNXI=y -CONFIG_USB_PHY=y diff --git a/target/linux/sunxi/cortexa8/config-5.10 b/target/linux/sunxi/cortexa8/config-5.10 deleted file mode 100644 index 5dab93095d..0000000000 --- a/target/linux/sunxi/cortexa8/config-5.10 +++ /dev/null @@ -1,12 +0,0 @@ -# CONFIG_ARM_LPAE is not set -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -# CONFIG_MACH_SUN6I is not set -# CONFIG_MACH_SUN7I is not set -# CONFIG_MACH_SUN8I is not set -# CONFIG_MACH_SUN9I is not set -CONFIG_PGTABLE_LEVELS=2 -# CONFIG_PHY_SUN9I_USB is not set -# CONFIG_SPI_SUN6I is not set -# CONFIG_SUN8I_A83T_CCU is not set -# CONFIG_SUN8I_THERMAL is not set diff --git a/target/linux/tegra/config-5.10 b/target/linux/tegra/config-5.10 deleted file mode 100644 index 9c80b5595b..0000000000 --- a/target/linux/tegra/config-5.10 +++ /dev/null @@ -1,483 +0,0 @@ -CONFIG_AC97_BUS=y -# CONFIG_AHCI_TEGRA is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y -CONFIG_ARCH_NR_GPIO=1024 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_TEGRA=y -# CONFIG_ARCH_TEGRA_114_SOC is not set -# CONFIG_ARCH_TEGRA_124_SOC is not set -CONFIG_ARCH_TEGRA_2x_SOC=y -# CONFIG_ARCH_TEGRA_3x_SOC is not set -CONFIG_ARM=y -CONFIG_ARM_AMBA=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARM_CRYPTO=y -CONFIG_ARM_ERRATA_720789=y -CONFIG_ARM_ERRATA_754327=y -CONFIG_ARM_ERRATA_764369=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_PL172_MPMC is not set -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_TEGRA_CPUIDLE=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASN1=y -CONFIG_ATA=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -CONFIG_CACHE_L2X0=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CLZ_TAB=y -CONFIG_CMA=y -CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTIG_ALLOC=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -# CONFIG_CPU_FREQ_STAT is not set -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AES_ARM=y -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZ4=y -CONFIG_CRYPTO_LZ4HC=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA1_ARM=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM=y -CONFIG_CRYPTO_SHA512_ARM=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_TWOFISH_COMMON=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -# CONFIG_DEVPORT is not set -CONFIG_DMADEVICES=y -CONFIG_DMA_CMA=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DNOTIFY=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_TEGRA=y -# CONFIG_DRM_TEGRA_DEBUG is not set -# CONFIG_DRM_TEGRA_STAGING is not set -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -# CONFIG_FW_CACHE is not set -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GLOB=y -CONFIG_GPIO_TEGRA=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HIDRAW=y -CONFIG_HID_GENERIC=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HZ_FIXED=0 -CONFIG_HZ_PERIODIC=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_TEGRA=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_IOVA=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KCMP=y -CONFIG_KEYBOARD_ATKBD=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZ4HC_COMPRESS=y -CONFIG_LZ4_COMPRESS=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MEMORY_ISOLATION=y -# CONFIG_MFD_NVEC is not set -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_TEGRA=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MPILIB=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -# CONFIG_NEON is not set -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_ARCH_FALLBACKS=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_TEGRA=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHY_TEGRA_XUSB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_TEGRA=y -CONFIG_PINCTRL_TEGRA20=y -CONFIG_PINCTRL_TEGRA_XUSB=y -CONFIG_PL310_ERRATA_727915=y -CONFIG_PL310_ERRATA_769419=y -CONFIG_PL353_SMC=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PWM=y -CONFIG_PWM_SYSFS=y -CONFIG_PWM_TEGRA=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGMAP_SPI=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TEGRA=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_RTC_NVMEM=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_PROC_FS is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_TEGRA=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SERIAL_TEGRA=y -CONFIG_SERIO=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SND=y -# CONFIG_SND_COMPRESS_OFFLOAD is not set -CONFIG_SND_DMAENGINE_PCM=y -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_HDA_TEGRA is not set -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -# CONFIG_SND_PCI is not set -CONFIG_SND_PCM=y -# CONFIG_SND_PROC_FS is not set -CONFIG_SND_SIMPLE_CARD=y -CONFIG_SND_SIMPLE_CARD_UTILS=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_AC97_BUS=y -CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -CONFIG_SND_SOC_I2C_AND_SPI=y -CONFIG_SND_SOC_TEGRA=y -# CONFIG_SND_SOC_TEGRA186_DSPK is not set -CONFIG_SND_SOC_TEGRA20_AC97=y -CONFIG_SND_SOC_TEGRA20_DAS=y -CONFIG_SND_SOC_TEGRA20_I2S=y -CONFIG_SND_SOC_TEGRA20_SPDIF=y -# CONFIG_SND_SOC_TEGRA210_ADMAIF is not set -# CONFIG_SND_SOC_TEGRA210_AHUB is not set -# CONFIG_SND_SOC_TEGRA210_DMIC is not set -# CONFIG_SND_SOC_TEGRA210_I2S is not set -# CONFIG_SND_SOC_TEGRA30_AHUB is not set -# CONFIG_SND_SOC_TEGRA30_I2S is not set -# CONFIG_SND_SOC_TEGRA_ALC5632 is not set -# CONFIG_SND_SOC_TEGRA_MAX98090 is not set -# CONFIG_SND_SOC_TEGRA_RT5640 is not set -# CONFIG_SND_SOC_TEGRA_RT5677 is not set -# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set -CONFIG_SND_SOC_TEGRA_TRIMSLICE=y -# CONFIG_SND_SOC_TEGRA_WM8753 is not set -# CONFIG_SND_SOC_TEGRA_WM8903 is not set -# CONFIG_SND_SOC_TEGRA_WM9712 is not set -CONFIG_SND_SOC_TLV320AIC23=y -CONFIG_SND_SOC_TLV320AIC23_I2C=y -# CONFIG_SND_USB is not set -CONFIG_SOC_BUS=y -CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER=y -CONFIG_SOC_TEGRA_FLOWCTRL=y -CONFIG_SOC_TEGRA_FUSE=y -CONFIG_SOC_TEGRA_PMC=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -# CONFIG_SPI_TEGRA114 is not set -CONFIG_SPI_TEGRA20_SFLASH=y -CONFIG_SPI_TEGRA20_SLINK=y -CONFIG_SRCU=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TEGRA20_APB_DMA=y -CONFIG_TEGRA20_EMC=y -CONFIG_TEGRA_AHB=y -CONFIG_TEGRA_GMI=y -CONFIG_TEGRA_HOST1X=y -CONFIG_TEGRA_HOST1X_FIREWALL=y -CONFIG_TEGRA_IOMMU_GART=y -# CONFIG_TEGRA_IOMMU_SMMU is not set -# CONFIG_TEGRA_IVC is not set -CONFIG_TEGRA_MC=y -# CONFIG_TEGRA_SOCTHERM is not set -CONFIG_TEGRA_TIMER=y -CONFIG_TEGRA_WATCHDOG=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -# CONFIG_UCLAMP_TASK is not set -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_CONN_GPIO=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_EHCI_TEGRA=y -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_TEGRA_PHY=y -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_USB_XHCI_TEGRA is not set -CONFIG_XPS=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/tegra/patches-5.10/100-serial8250-on-tegra-hsuart-recover-from-spurious-interrupts-due-to-tegra2-silicon-bug.patch b/target/linux/tegra/patches-5.10/100-serial8250-on-tegra-hsuart-recover-from-spurious-interrupts-due-to-tegra2-silicon-bug.patch deleted file mode 100644 index 8f01f73eb2..0000000000 --- a/target/linux/tegra/patches-5.10/100-serial8250-on-tegra-hsuart-recover-from-spurious-interrupts-due-to-tegra2-silicon-bug.patch +++ /dev/null @@ -1,77 +0,0 @@ -From patchwork Fri Jul 13 11:32:42 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: serial8250 on tegra hsuart: recover from spurious interrupts due to - tegra2 silicon bug -X-Patchwork-Submitter: "David R. Piegdon" -X-Patchwork-Id: 943440 -Message-Id: <4676ea34-69ce-5422-1ded-94218b89f7d9@p23q.org> -To: linux-tegra@vger.kernel.org -Date: Fri, 13 Jul 2018 11:32:42 +0000 -From: "David R. Piegdon" -List-Id: - -Hi, -a while back I sent a few mails regarding spurious interrupts in the -UARTA (hsuart) block of the Tegra2 SoC, when using the 8250 driver for -it instead of the hsuart driver. After going down a pretty deep -debugging/testing hole, I think I found a patch that fixes the issue. So -far testing in a reboot-cycle suggests that the error frequency dropped -from >3% of all reboots to at least <0.05% of all reboots. Tests -continue to run over the weekend. - -The patch below already is a second iteration; the first did not reset -the MCR or contain the lines below '// clear interrupts'. This resulted -in no more spurious interrupts, but in a few % of spurious interrupts -that were recovered the UART block did not receive any characters any -more. So further resetting was required to fully reacquire operational -state of the UART block. - -I'd love any comments/suggestions on this! - -Cheers, - -David - ---- a/drivers/tty/serial/8250/8250_core.c -+++ b/drivers/tty/serial/8250/8250_core.c -@@ -134,6 +134,38 @@ static irqreturn_t serial8250_interrupt( - - if (l == i->head && pass_counter++ > PASS_LIMIT) - break; -+ -+#ifdef CONFIG_ARCH_TEGRA_2x_SOC -+ if (!handled && (port->type == PORT_TEGRA)) { -+ /* -+ * Fix Tegra 2 CPU silicon bug where sometimes -+ * "TX holding register empty" interrupts result in a -+ * bad (metastable?) state in Tegras HSUART IP core. -+ * Only way to recover seems to be to reset all -+ * interrupts as well as the TX queue and the MCR. -+ * But we don't want to loose any outgoing characters, -+ * so only do it if the RX and TX queues are empty. -+ */ -+ unsigned char lsr = port->serial_in(port, UART_LSR); -+ const unsigned char fifo_empty_mask = -+ (UART_LSR_TEMT | UART_LSR_THRE); -+ if (((lsr & (UART_LSR_DR | fifo_empty_mask)) == -+ fifo_empty_mask)) { -+ port->serial_out(port, UART_IER, 0); -+ port->serial_out(port, UART_MCR, 0); -+ serial8250_clear_and_reinit_fifos(up); -+ port->serial_out(port, UART_MCR, up->mcr); -+ port->serial_out(port, UART_IER, up->ier); -+ // clear interrupts -+ serial_port_in(port, UART_LSR); -+ serial_port_in(port, UART_RX); -+ serial_port_in(port, UART_IIR); -+ serial_port_in(port, UART_MSR); -+ up->lsr_saved_flags = 0; -+ up->msr_saved_flags = 0; -+ } -+ } -+#endif - } while (l != end); - - spin_unlock(&i->lock); diff --git a/target/linux/tegra/patches-5.10/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch b/target/linux/tegra/patches-5.10/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch deleted file mode 100644 index b1e210b212..0000000000 --- a/target/linux/tegra/patches-5.10/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch +++ /dev/null @@ -1,46 +0,0 @@ ---- a/arch/arm/boot/dts/tegra20-trimslice.dts -+++ b/arch/arm/boot/dts/tegra20-trimslice.dts -@@ -201,16 +201,17 @@ - conf_ata { - nvidia,pins = "ata", "atc", "atd", "ate", - "crtp", "dap2", "dap3", "dap4", "dta", -- "dtb", "dtc", "dtd", "dte", "gmb", -- "gme", "i2cp", "pta", "slxc", "slxd", -- "spdi", "spdo", "uda"; -+ "dtb", "dtc", "dtd", "gmb", "gme", -+ "i2cp", "pta", "slxc", "slxd", "spdi", -+ "spdo", "uda"; - nvidia,pull = ; - nvidia,tristate = ; - }; - conf_atb { - nvidia,pins = "atb", "cdev1", "cdev2", "dap1", -- "gma", "gmc", "gmd", "gpu", "gpu7", -- "gpv", "sdio1", "slxa", "slxk", "uac"; -+ "dte", "gma", "gmc", "gmd", "gpu", -+ "gpu7", "gpv", "sdio1", "slxa", "slxk", -+ "uac"; - nvidia,pull = ; - nvidia,tristate = ; - }; -@@ -396,6 +397,20 @@ - }; - }; - -+ gpio-leds { -+ compatible = "gpio-leds"; -+ -+ ds2 { -+ label = "trimslice:green:right"; -+ gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_LOW>; -+ }; -+ -+ ds3 { -+ label = "trimslice:green:left"; -+ gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ - poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; diff --git a/target/linux/uml/config-5.10 b/target/linux/uml/config-5.10 deleted file mode 100644 index 1c432abe68..0000000000 --- a/target/linux/uml/config-5.10 +++ /dev/null @@ -1,135 +0,0 @@ -CONFIG_3_LEVEL_PGTABLES=y -CONFIG_64BIT=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_NO_PREEMPT=y -CONFIG_BLK_DEV_COW_COMMON=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_UBD=y -CONFIG_BLK_DEV_UBD_SYNC=y -CONFIG_BLK_MQ_VIRTIO=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_CDROM=y -# CONFIG_COMMON_CLK is not set -# CONFIG_COMPAT_32BIT_TIME is not set -CONFIG_CON_CHAN="xterm" -CONFIG_CON_ZERO_CHAN="fd:0,fd:1" -CONFIG_CPU_SUP_AMD=y -CONFIG_CPU_SUP_CENTAUR=y -CONFIG_CPU_SUP_HYGON=y -CONFIG_CPU_SUP_INTEL=y -CONFIG_CPU_SUP_ZHAOXIN=y -CONFIG_CRC16=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_TWOFISH_X86_64 is not set -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DNOTIFY=y -# CONFIG_EARLY_PRINTK is not set -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FAILOVER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_GENERIC_CPU is not set -CONFIG_GENERIC_CPU_DEVICES=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_HOSTFS=y -CONFIG_HVC_DRIVER=y -CONFIG_HW_RANDOM=y -CONFIG_HZ_PERIODIC=y -CONFIG_IA32_FEAT_CTL=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INIT_ENV_ARG_LIMIT=128 -CONFIG_IRQ_WORK=y -CONFIG_ISO9660_FS=y -CONFIG_JBD2=y -# CONFIG_JFFS2_FS is not set -CONFIG_KALLSYMS=y -CONFIG_KERNEL_STACK_ORDER=2 -CONFIG_LOCK_DEBUGGING_SUPPORT=y -# CONFIG_MATOM is not set -CONFIG_MAY_HAVE_RUNTIME_DEPS=y -CONFIG_MCONSOLE=y -# CONFIG_MCORE2 is not set -CONFIG_MEMFD_CREATE=y -CONFIG_MIGRATION=y -CONFIG_MK8=y -# CONFIG_MMAPPER is not set -CONFIG_MODULES_USE_ELF_RELA=y -# CONFIG_MPSC is not set -CONFIG_NAMESPACES=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NET_FAILOVER=y -# CONFIG_NET_NS is not set -CONFIG_NLS=y -CONFIG_NO_DMA=y -CONFIG_NO_IOMEM=y -CONFIG_NR_CPUS=1 -CONFIG_NULL_CHAN=y -# CONFIG_OF is not set -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PORT_CHAN=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -# CONFIG_PROCESSOR_SELECT is not set -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PTY_CHAN=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RELAY=y -CONFIG_SOFT_WATCHDOG=m -CONFIG_SRCU=y -CONFIG_SSL=y -CONFIG_SSL_CHAN="pty" -CONFIG_STACKTRACE=y -CONFIG_STDERR_CONSOLE=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -CONFIG_TTY_CHAN=y -CONFIG_UML=y -CONFIG_UML_NET=y -CONFIG_UML_NET_DAEMON=y -CONFIG_UML_NET_DETERMINISTIC_MAC=y -CONFIG_UML_NET_ETHERTAP=y -CONFIG_UML_NET_MCAST=y -# CONFIG_UML_NET_PCAP is not set -CONFIG_UML_NET_SLIP=y -CONFIG_UML_NET_SLIRP=y -CONFIG_UML_NET_TUNTAP=y -# CONFIG_UML_NET_VDE is not set -CONFIG_UML_NET_VECTOR=y -CONFIG_UML_RANDOM=y -# CONFIG_UML_SOUND is not set -CONFIG_UML_TIME_TRAVEL_SUPPORT=y -CONFIG_UML_WATCHDOG=y -CONFIG_UML_X86=y -# CONFIG_USER_NS is not set -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_VIRTIO_NET=y -CONFIG_VIRTIO_UML=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WATCHDOG_CORE=y -CONFIG_X86_64=y -CONFIG_X86_CMOV=y -CONFIG_X86_CMPXCHG64=y -CONFIG_X86_INTEL_USERCOPY=y -CONFIG_X86_INTERNODE_CACHE_SHIFT=6 -CONFIG_X86_L1_CACHE_SHIFT=6 -CONFIG_X86_MINIMUM_CPU_FAMILY=64 -CONFIG_X86_TSC=y -CONFIG_X86_USE_PPRO_CHECKSUM=y -CONFIG_XTERM_CHAN=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/uml/patches-5.10/001-um-Fix-build-w-o-CONFIG_PM_SLEEP.patch b/target/linux/uml/patches-5.10/001-um-Fix-build-w-o-CONFIG_PM_SLEEP.patch deleted file mode 100644 index acee358dd7..0000000000 --- a/target/linux/uml/patches-5.10/001-um-Fix-build-w-o-CONFIG_PM_SLEEP.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 1fb1abc83636f5329c26cd29f0f19f3faeb697a5 Mon Sep 17 00:00:00 2001 -From: Johannes Berg -Date: Mon, 14 Dec 2020 20:51:02 +0100 -Subject: [PATCH] um: Fix build w/o CONFIG_PM_SLEEP - -uml_pm_wake() is unconditionally called from the SIGUSR1 wakeup -handler since that's in the userspace portion of UML, and thus -a bit tricky to ifdef out. Since pm_system_wakeup() can always -be called (but may be an empty inline), also simply always have -uml_pm_wake() to fix the build. - -Reported-by: Randy Dunlap -Acked-by: Randy Dunlap # build-tested -Signed-off-by: Johannes Berg -Signed-off-by: Richard Weinberger ---- ---- a/arch/um/kernel/um_arch.c -+++ b/arch/um/kernel/um_arch.c -@@ -387,12 +387,12 @@ void text_poke_sync(void) - { - } - --#ifdef CONFIG_PM_SLEEP - void uml_pm_wake(void) - { - pm_system_wakeup(); - } - -+#ifdef CONFIG_PM_SLEEP - static int init_pm_wake_signal(void) - { - /* diff --git a/target/linux/uml/patches-5.10/101-mconsole-exec.patch b/target/linux/uml/patches-5.10/101-mconsole-exec.patch deleted file mode 100644 index dae84d6bf5..0000000000 --- a/target/linux/uml/patches-5.10/101-mconsole-exec.patch +++ /dev/null @@ -1,213 +0,0 @@ -# -# Minimalist mconsole exec patch -# -# 3.10 version (with bit more synchronous behavior) by fingon at iki dot fi -# Adaptation to kernel 3.3.8 made by David Fernández (david at dit.upm.es) for -# Starting point: mconsole-exec-2.6.30.patch for kernel 2.6.30 -# Author of original patch: Paolo Giarrusso, aka Blaisorblade -# (http://www.user-mode-linux.org/~blaisorblade) -# -# Known misfeatures: -# -# - If output is too long, blocks (and breaks horribly) -# (this misfeature from 3.10 patches, when minimalizing the patch; -# workaround: redirect to a shared filesystem if long output is expected) -# -# - Nothing useful is done with stdin -# ---- a/arch/um/drivers/mconsole.h -+++ b/arch/um/drivers/mconsole.h -@@ -85,6 +85,7 @@ extern void mconsole_cad(struct mc_reque - extern void mconsole_stop(struct mc_request *req); - extern void mconsole_go(struct mc_request *req); - extern void mconsole_log(struct mc_request *req); -+extern void mconsole_exec(struct mc_request *req); - extern void mconsole_proc(struct mc_request *req); - extern void mconsole_stack(struct mc_request *req); - ---- a/arch/um/drivers/mconsole_kern.c -+++ b/arch/um/drivers/mconsole_kern.c -@@ -4,6 +4,7 @@ - * Copyright (C) 2001 - 2008 Jeff Dike (jdike@{addtoit,linux.intel}.com) - */ - -+#include - #include - #include - #include -@@ -26,6 +27,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -123,6 +125,59 @@ void mconsole_log(struct mc_request *req - mconsole_reply(req, "", 0, 0); - } - -+void mconsole_exec(struct mc_request *req) -+{ -+ struct subprocess_info *sub_info; -+ int res, len; -+ struct file *out; -+ char buf[MCONSOLE_MAX_DATA]; -+ -+ char *envp[] = { -+ "HOME=/", "TERM=linux", -+ "PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin", -+ NULL -+ }; -+ char *argv[] = { -+ "/bin/sh", "-c", -+ req->request.data + strlen("exec "), -+ NULL -+ }; -+ -+ sub_info = call_usermodehelper_setup("/bin/sh", argv, envp, GFP_ATOMIC, NULL, NULL, NULL); -+ if (sub_info == NULL) { -+ mconsole_reply(req, "call_usermodehelper_setup failed", 1, 0); -+ return; -+ } -+ res = call_usermodehelper_stdoutpipe(sub_info, &out); -+ if (res < 0) { -+ kfree(sub_info); -+ mconsole_reply(req, "call_usermodehelper_stdoutpipe failed", 1, 0); -+ return; -+ } -+ -+ res = call_usermodehelper_exec(sub_info, UMH_WAIT_PROC); -+ if (res < 0) { -+ kfree(sub_info); -+ mconsole_reply(req, "call_usermodehelper_exec failed", 1, 0); -+ return; -+ } -+ -+ for (;;) { -+ len = out->f_op->read(out, buf, sizeof(buf), &out->f_pos); -+ if (len < 0) { -+ mconsole_reply(req, "reading output failed", 1, 0); -+ break; -+ } -+ if (len == 0) -+ break; -+ mconsole_reply_len(req, buf, len, 0, 1); -+ } -+ fput(out); -+ -+ mconsole_reply_len(req, NULL, 0, 0, 0); -+} -+ -+ - void mconsole_proc(struct mc_request *req) - { - struct vfsmount *mnt = proc_mnt; -@@ -189,6 +244,7 @@ void mconsole_proc(struct mc_request *re - stop - pause the UML; it will do nothing until it receives a 'go' \n\ - go - continue the UML after a 'stop' \n\ - log - make UML enter into the kernel log\n\ -+ exec - pass to /bin/sh -c synchronously\n\ - proc - returns the contents of the UML's /proc/\n\ - stack - returns the stack of the specified pid\n\ - " ---- a/arch/um/drivers/mconsole_user.c -+++ b/arch/um/drivers/mconsole_user.c -@@ -30,6 +30,7 @@ static struct mconsole_command commands[ - { "stop", mconsole_stop, MCONSOLE_PROC }, - { "go", mconsole_go, MCONSOLE_INTR }, - { "log", mconsole_log, MCONSOLE_INTR }, -+ { "exec", mconsole_exec, MCONSOLE_PROC }, - { "proc", mconsole_proc, MCONSOLE_PROC }, - { "stack", mconsole_stack, MCONSOLE_INTR }, - }; ---- a/arch/um/os-Linux/file.c -+++ b/arch/um/os-Linux/file.c -@@ -560,6 +560,8 @@ int os_create_unix_socket(const char *fi - - addr.sun_family = AF_UNIX; - -+ if (len > sizeof(addr.sun_path)) -+ len = sizeof(addr.sun_path); - snprintf(addr.sun_path, len, "%s", file); - - err = bind(sock, (struct sockaddr *) &addr, sizeof(addr)); ---- a/include/linux/kmod.h -+++ b/include/linux/kmod.h -@@ -32,4 +32,6 @@ static inline int request_module_nowait( - #define try_then_request_module(x, mod...) (x) - #endif - -+int call_usermodehelper_stdoutpipe(struct subprocess_info *sub_info, struct file **filp); -+ - #endif /* __LINUX_KMOD_H__ */ ---- a/include/linux/umh.h -+++ b/include/linux/umh.h -@@ -22,6 +22,7 @@ struct subprocess_info { - const char *path; - char **argv; - char **envp; -+ struct file *stdout; - int wait; - int retval; - int (*init)(struct subprocess_info *info, struct cred *new); ---- a/kernel/umh.c -+++ b/kernel/umh.c -@@ -27,6 +27,7 @@ - #include - #include - #include -+#include - - #include - -@@ -72,6 +73,28 @@ static int call_usermodehelper_exec_asyn - flush_signal_handlers(current, 1); - spin_unlock_irq(¤t->sighand->siglock); - -+ /* Install output when needed */ -+ if (sub_info->stdout) { -+ struct files_struct *f = current->files; -+ struct fdtable *fdt; -+ -+ sys_close(1); -+ sys_close(2); -+ get_file(sub_info->stdout); -+ fd_install(1, sub_info->stdout); -+ fd_install(2, sub_info->stdout); -+ spin_lock(&f->file_lock); -+ fdt = files_fdtable(f); -+ __set_bit(1, fdt->open_fds); -+ __clear_bit(1, fdt->close_on_exec); -+ __set_bit(2, fdt->open_fds); -+ __clear_bit(2, fdt->close_on_exec); -+ spin_unlock(&f->file_lock); -+ -+ /* disallow core files */ -+ current->signal->rlim[RLIMIT_CORE] = (struct rlimit){0, 0}; -+ } -+ - /* - * Initial kernel threads share ther FS with init, in order to - * get the init root directory. But we've now created a new -@@ -330,6 +353,20 @@ static void helper_unlock(void) - wake_up(&running_helpers_waitq); - } - -+int call_usermodehelper_stdoutpipe(struct subprocess_info *sub_info, -+ struct file **filp) -+{ -+ struct file *f[2]; -+ -+ if (create_pipe_files(f, 0) < 0) -+ return PTR_ERR(f); -+ -+ sub_info->stdout = f[1]; -+ *filp = f[0]; -+ return 0; -+} -+EXPORT_SYMBOL(call_usermodehelper_stdoutpipe); -+ - /** - * call_usermodehelper_setup - prepare to call a usermode helper - * @path: path to usermode executable diff --git a/target/linux/uml/patches-5.10/102-pseudo-random-mac.patch b/target/linux/uml/patches-5.10/102-pseudo-random-mac.patch deleted file mode 100644 index a4e6500f94..0000000000 --- a/target/linux/uml/patches-5.10/102-pseudo-random-mac.patch +++ /dev/null @@ -1,147 +0,0 @@ -=============================================================================== - -This patch makes MAC addresses of network interfaces predictable. In -particular, it adds a small routine that computes MAC addresses of based on -a SHA1 hash of the virtual machine name and interface ID. - -TECHNICAL INFORMATION: - -Applies to vanilla kernel 3.9.4. - -=============================================================================== ---- a/arch/um/drivers/Kconfig -+++ b/arch/um/drivers/Kconfig -@@ -146,6 +146,20 @@ config UML_NET - enable at least one of the following transport options to actually - make use of UML networking. - -+config UML_NET_DETERMINISTIC_MAC -+ bool "Use deterministic MAC addresses for network interfaces" -+ default y -+ depends on UML_NET -+ select CRYPTO_SHA1 -+ help -+ Virtual network devices inside a User-Mode Linux instance must be -+ assigned a MAC (Ethernet) address. If none is specified on the UML -+ command line, one must be automatically computed. If this option is -+ enabled, a randomly generated address is used. Otherwise, if this -+ option is disabled, the address is generated from a SHA1 hash of -+ the umid of the UML instance and the interface name. The latter choice -+ is useful to make MAC addresses predictable. -+ - config UML_NET_ETHERTAP - bool "Ethertap transport (obsolete)" - depends on UML_NET ---- a/arch/um/drivers/net_kern.c -+++ b/arch/um/drivers/net_kern.c -@@ -25,6 +25,14 @@ - #include - #include - -+#include -+#include -+#include -+#include -+#include -+#include -+#include "os.h" -+ - #define DRIVER_NAME "uml-netdev" - - static DEFINE_SPINLOCK(opened_lock); -@@ -274,9 +282,51 @@ static const struct ethtool_ops uml_net_ - .get_ts_info = ethtool_op_get_ts_info, - }; - -+#ifdef CONFIG_UML_NET_DETERMINISTIC_MAC -+ -+/* Compute a SHA1 hash of the UML instance's id and -+ * * an interface name. */ -+static int compute_hash(const char *umid, const char *ifname, char *hash) -+{ -+ struct ahash_request *desc; -+ struct crypto_ahash *tfm; -+ struct scatterlist sg; -+ char vmif[1024]; -+ int ret; -+ -+ strcpy (vmif, umid); -+ strcat (vmif, ifname); -+ -+ tfm = crypto_alloc_ahash("sha1", 0, CRYPTO_ALG_ASYNC); -+ if (IS_ERR(tfm)) -+ return -ENOMEM; -+ -+ desc = ahash_request_alloc(tfm, GFP_KERNEL); -+ if (!desc) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ crypto_ahash_clear_flags(tfm, ~0); -+ -+ sg_init_table(&sg, 1); -+ sg_set_buf(&sg, vmif, strlen(vmif)); -+ -+ ahash_request_set_crypt(desc, &sg, hash, strlen(vmif)); -+ -+ ret = crypto_ahash_digest(desc); -+out: -+ crypto_free_ahash(tfm); -+ -+ return ret; -+} -+ -+#endif -+ - void uml_net_setup_etheraddr(struct net_device *dev, char *str) - { - unsigned char *addr = dev->dev_addr; -+ u8 hash[SHA1_DIGEST_SIZE]; - char *end; - int i; - -@@ -319,9 +369,26 @@ void uml_net_setup_etheraddr(struct net_ - return; - - random: -+#ifndef CONFIG_UML_NET_DETERMINISTIC_MAC - printk(KERN_INFO - "Choosing a random ethernet address for device %s\n", dev->name); - eth_hw_addr_random(dev); -+#else -+ printk(KERN_INFO -+ "Computing a digest to use as ethernet address for device %s\n", dev->name); -+ if (compute_hash(get_umid(), dev->name, hash) < 0) { -+ printk(KERN_WARNING -+ "Could not compute digest to use as ethernet address for device %s. " -+ "Using random address instead.\n", dev->name); -+ random_ether_addr(addr); -+ } -+ else { -+ for (i=0; i < 6; i++) -+ addr[i] = (hash[i] + hash[i+6]) % 0x100; -+ } -+ addr [0] &= 0xfe; /* clear multicast bit */ -+ addr [0] |= 0x02; /* set local assignment bit (IEEE802) */ -+#endif - } - - static DEFINE_SPINLOCK(devices_lock); ---- a/kernel/umh.c -+++ b/kernel/umh.c -@@ -354,12 +354,12 @@ static void helper_unlock(void) - } - - int call_usermodehelper_stdoutpipe(struct subprocess_info *sub_info, -- struct file **filp) -+ struct file **filp) - { - struct file *f[2]; - - if (create_pipe_files(f, 0) < 0) -- return PTR_ERR(f); -+ return PTR_ERR(f); - - sub_info->stdout = f[1]; - *filp = f[0]; diff --git a/target/linux/x86/64/config-5.10 b/target/linux/x86/64/config-5.10 deleted file mode 100644 index 1515f90932..0000000000 --- a/target/linux/x86/64/config-5.10 +++ /dev/null @@ -1,510 +0,0 @@ -CONFIG_64BIT=y -CONFIG_ACPI=y -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -# CONFIG_ACPI_BGRT is not set -CONFIG_ACPI_BUTTON=y -# CONFIG_ACPI_CMPC is not set -CONFIG_ACPI_CONTAINER=y -CONFIG_ACPI_CPPC_LIB=y -CONFIG_ACPI_CPU_FREQ_PSS=y -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUGGER is not set -# CONFIG_ACPI_DOCK is not set -# CONFIG_ACPI_DPTF is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -CONFIG_ACPI_FAN=y -CONFIG_ACPI_HOTPLUG_CPU=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y -# CONFIG_ACPI_I2C_OPREGION is not set -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -CONFIG_ACPI_LPIT=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_PROCESSOR=y -# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y -# CONFIG_ACPI_SBS is not set -CONFIG_ACPI_SPCR_TABLE=y -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -# CONFIG_ACPI_TAD is not set -CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_VIDEO=y -# CONFIG_ACPI_WMI is not set -# CONFIG_ACRN_GUEST is not set -CONFIG_AGP=y -# CONFIG_AGP_AMD64 is not set -CONFIG_AGP_INTEL=y -# CONFIG_AGP_SIS is not set -# CONFIG_AGP_VIA is not set -CONFIG_AMD_IOMMU=y -# CONFIG_AMD_IOMMU_V2 is not set -CONFIG_ARCH_CPUIDLE_HALTPOLL=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_ARCH_MMAP_RND_BITS=28 -CONFIG_ARCH_MMAP_RND_BITS_MAX=32 -CONFIG_ARCH_MMAP_RND_BITS_MIN=28 -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_AUDIT_ARCH=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BALLOON_COMPACTION=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -CONFIG_BLK_DEV_NVME=y -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_MQ_VIRTIO=y -CONFIG_BLK_PM=y -# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set -CONFIG_BTT=y -CONFIG_CDROM=y -CONFIG_CONNECTOR=y -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set -CONFIG_CPU_RMAP=y -CONFIG_CRC_T10DIF=y -CONFIG_CRYPTO_AES_NI_INTEL=y -CONFIG_CRYPTO_BLAKE2S_X86=y -# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set -# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set -CONFIG_CRYPTO_CRCT10DIF=y -# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set -CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_GLUE_HELPER_X86=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 -CONFIG_CRYPTO_LRW=y -# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set -# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set -# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set -# CONFIG_CRYPTO_SHA1_SSSE3 is not set -# CONFIG_CRYPTO_SHA256_SSSE3 is not set -# CONFIG_CRYPTO_SHA512_SSSE3 is not set -CONFIG_CRYPTO_SIMD=y -# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set -# CONFIG_CRYPTO_TWOFISH_X86_64 is not set -# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set -CONFIG_CRYPTO_XTS=y -# CONFIG_DEBUG_HOTPLUG_CPU0 is not set -CONFIG_DMA_ACPI=y -CONFIG_DMA_OPS=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DRM=y -CONFIG_DRM_BOCHS=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_I915=y -CONFIG_DRM_I915_CAPTURE_ERROR=y -CONFIG_DRM_I915_COMPRESS_ERROR=y -# CONFIG_DRM_I915_DEBUG is not set -# CONFIG_DRM_I915_DEBUG_GUC is not set -# CONFIG_DRM_I915_DEBUG_MMIO is not set -# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set -# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set -CONFIG_DRM_I915_FENCE_TIMEOUT=10000 -CONFIG_DRM_I915_FORCE_PROBE="" -CONFIG_DRM_I915_GVT=y -CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 -# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set -CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 -CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 -# CONFIG_DRM_I915_SELFTEST is not set -CONFIG_DRM_I915_STOP_TIMEOUT=100 -# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set -# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set -CONFIG_DRM_I915_TIMESLICE_DURATION=1 -CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 -CONFIG_DRM_I915_USERPTR=y -# CONFIG_DRM_I915_WERROR is not set -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_TTM=y -CONFIG_DRM_TTM_DMA_PAGE_POOL=y -CONFIG_DRM_TTM_HELPER=y -CONFIG_DRM_VIRTIO_GPU=y -CONFIG_DRM_VRAM_HELPER=y -CONFIG_EFI=y -CONFIG_EFIVAR_FS=m -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_ESRT=y -# CONFIG_EFI_FAKE_MEMMAP is not set -CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y -# CONFIG_EFI_MIXED is not set -# CONFIG_EFI_PGT_DUMP is not set -# CONFIG_EFI_RCI2_TABLE is not set -CONFIG_EFI_RUNTIME_MAP=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_STUB=y -# CONFIG_EFI_TEST is not set -# CONFIG_EFI_VARS is not set -CONFIG_FAILOVER=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_EFI=y -CONFIG_FB_HYPERV=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_SIMPLE=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FB_TILEBLITTING=y -# CONFIG_FB_VESA is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_FREEZER=y -CONFIG_FUSION_SAS=y -CONFIG_FW_CACHE=y -CONFIG_GART_IOMMU=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CPU=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_GPIO_ACPI=y -CONFIG_GPIO_ICH=y -CONFIG_GPIO_SCH=y -CONFIG_HALTPOLL_CPUIDLE=y -CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y -CONFIG_HDMI=y -CONFIG_HIBERNATE_CALLBACKS=y -CONFIG_HID_BATTERY_STRENGTH=y -CONFIG_HID_GENERIC=y -CONFIG_HID_HYPERV_MOUSE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_PCIE is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set -CONFIG_HOTPLUG_SMT=y -CONFIG_HPET=y -CONFIG_HPET_MMAP=y -# CONFIG_HP_ACCEL is not set -CONFIG_HVC_DRIVER=y -CONFIG_HVC_IRQ=y -CONFIG_HVC_XEN=y -CONFIG_HVC_XEN_FRONTEND=y -CONFIG_HWMON=y -CONFIG_HWMON_VID=y -CONFIG_HW_RANDOM_AMD=y -CONFIG_HW_RANDOM_INTEL=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_HYPERV=y -CONFIG_HYPERVISOR_GUEST=y -CONFIG_HYPERV_BALLOON=y -CONFIG_HYPERV_IOMMU=y -CONFIG_HYPERV_KEYBOARD=y -CONFIG_HYPERV_NET=y -CONFIG_HYPERV_STORAGE=y -# CONFIG_HYPERV_TESTING is not set -CONFIG_HYPERV_TIMER=y -CONFIG_HYPERV_UTILS=y -# CONFIG_HYPERV_VSOCKETS is not set -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -# CONFIG_I2C_AMD_MP2 is not set -CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_MULTI_INSTANTIATE is not set -# CONFIG_IA32_EMULATION is not set -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set -CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y -CONFIG_INTEL_GTT=y -CONFIG_INTEL_IDLE=y -CONFIG_INTEL_IOMMU=y -# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set -CONFIG_INTEL_IOMMU_FLOPPY_WA=y -# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set -# CONFIG_INTEL_IOMMU_SVM is not set -# CONFIG_INTEL_IPS is not set -# CONFIG_INTEL_MEI_HDCP is not set -# CONFIG_INTEL_MENLOW is not set -CONFIG_INTEL_PCH_THERMAL=y -# CONFIG_INTEL_SCU_PLATFORM is not set -CONFIG_INTEL_SOC_DTS_IOSF_CORE=y -CONFIG_INTEL_SOC_DTS_THERMAL=y -# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set -# CONFIG_INTEL_TURBO_MAX_3 is not set -# CONFIG_INTEL_TXT is not set -# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set -CONFIG_INTERVAL_TREE=y -CONFIG_IOASID=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUG is not set -# CONFIG_IOMMU_DEBUGFS is not set -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_HELPER=y -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_SUPPORT=y -CONFIG_IOSF_MBI=y -# CONFIG_IOSF_MBI_DEBUG is not set -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_IRQ_REMAP=y -# CONFIG_ISCSI_IBFT is not set -CONFIG_ISO9660_FS=y -CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y -CONFIG_KCMP=y -CONFIG_KVM_GUEST=y -CONFIG_LEDS_GPIO=y -# CONFIG_LEGACY_VSYSCALL_EMULATE is not set -CONFIG_LEGACY_VSYSCALL_NONE=y -# CONFIG_LEGACY_VSYSCALL_XONLY is not set -CONFIG_LIBNVDIMM=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LPC_ICH=y -CONFIG_LPC_SCH=y -CONFIG_MAILBOX=y -# CONFIG_MAXSMP is not set -CONFIG_MEMORY_BALLOON=y -CONFIG_MEMREGION=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_INTEL_LPSS_ACPI is not set -# CONFIG_MFD_INTEL_PMC_BXT is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_RICOH_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ACPI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_PCI=y -# CONFIG_MMC_SDHCI_PLTFM is not set -# CONFIG_MMC_WBSD is not set -CONFIG_MMU_NOTIFIER=y -CONFIG_MODULES_USE_ELF_RELA=y -# CONFIG_MPSC is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_ND_BLK=y -CONFIG_ND_BTT=y -CONFIG_ND_CLAIM=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FAILOVER=y -CONFIG_NET_FLOW_LIMIT=y -# CONFIG_NITRO_ENCLAVES is not set -CONFIG_NR_CPUS=512 -CONFIG_NR_CPUS_DEFAULT=512 -CONFIG_NR_CPUS_RANGE_BEGIN=2 -CONFIG_NR_CPUS_RANGE_END=512 -CONFIG_NVME_CORE=y -# CONFIG_NVME_HWMON is not set -CONFIG_NVME_MULTIPATH=y -# CONFIG_NVME_TCP is not set -CONFIG_OUTPUT_FORMAT="elf64-x86-64" -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_REPORTING=y -CONFIG_PAGE_TABLE_ISOLATION=y -CONFIG_PARAVIRT=y -CONFIG_PARAVIRT_CLOCK=y -# CONFIG_PARAVIRT_DEBUG is not set -CONFIG_PARAVIRT_SPINLOCKS=y -CONFIG_PARAVIRT_XXL=y -CONFIG_PATA_AMD=y -CONFIG_PATA_ATIIXP=y -CONFIG_PATA_MPIIX=y -CONFIG_PATA_OLDPIIX=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_TIMINGS=y -CONFIG_PATA_VIA=y -CONFIG_PCC=y -# CONFIG_PCENGINES_APU2 is not set -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_PME=y -CONFIG_PCI_HYPERV=y -CONFIG_PCI_HYPERV_INTERFACE=y -# CONFIG_PCI_MMCONFIG is not set -CONFIG_PCI_XEN=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_PHYSICAL_ALIGN=0x1000000 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_BAYTRAIL=y -CONFIG_PINCTRL_BROXTON=y -CONFIG_PINCTRL_CANNONLAKE=y -CONFIG_PINCTRL_CHERRYVIEW=y -CONFIG_PINCTRL_DENVERTON=y -CONFIG_PINCTRL_EMMITSBURG=y -CONFIG_PINCTRL_GEMINILAKE=y -CONFIG_PINCTRL_INTEL=y -CONFIG_PINCTRL_JASPERLAKE=y -CONFIG_PINCTRL_LEWISBURG=y -CONFIG_PINCTRL_LYNXPOINT=y -CONFIG_PINCTRL_SUNRISEPOINT=y -CONFIG_PINCTRL_TIGERLAKE=y -CONFIG_PM=y -# CONFIG_PMIC_OPREGION is not set -CONFIG_PM_CLK=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_PNP=y -CONFIG_PNPACPI=y -CONFIG_PNP_DEBUG_MESSAGES=y -CONFIG_PROC_EVENTS=y -CONFIG_PVH=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -CONFIG_RELAY=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_ATTACK_MITIGATION=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SAMSUNG_Q10 is not set -CONFIG_SATA_AHCI=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_MC_PRIO=y -CONFIG_SCHED_SMT=y -CONFIG_SCSI_VIRTIO=y -# CONFIG_SENSORS_AMD_ENERGY is not set -CONFIG_SENSORS_CORETEMP=y -CONFIG_SENSORS_FAM15H_POWER=y -CONFIG_SENSORS_I5500=y -CONFIG_SENSORS_K10TEMP=y -CONFIG_SENSORS_K8TEMP=y -CONFIG_SENSORS_VIA_CPUTEMP=y -CONFIG_SERIAL_8250_PNP=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SMP=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -# CONFIG_SPARSEMEM_VMEMMAP is not set -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_STACK_VALIDATION=y -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set -CONFIG_SWIOTLB=y -CONFIG_SWIOTLB_XEN=y -CONFIG_SYNC_FILE=y -# CONFIG_SYSTEM76_ACPI is not set -CONFIG_SYS_HYPERVISOR=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -# CONFIG_TOSHIBA_BT_RFKILL is not set -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -# CONFIG_UCLAMP_TASK is not set -CONFIG_UCS2_STRING=y -# CONFIG_UNWINDER_ORC is not set -CONFIG_USB_STORAGE=y -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_VIRTIO_DMA_SHARED_BUFFER=y -CONFIG_VIRTIO_MMIO=y -CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y -CONFIG_VIRTIO_NET=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y -# CONFIG_VIRTIO_PMEM is not set -# CONFIG_VIRTIO_VSOCKETS is not set -CONFIG_VIRTIO_VSOCKETS_COMMON=y -CONFIG_VIRT_DRIVERS=y -CONFIG_VMAP_PFN=y -CONFIG_VMAP_STACK=y -# CONFIG_VMD is not set -CONFIG_VMWARE_BALLOON=y -CONFIG_VMWARE_PVSCSI=y -CONFIG_VMWARE_VMCI=y -CONFIG_VMWARE_VMCI_VSOCKETS=y -CONFIG_VMXNET3=y -CONFIG_VSOCKETS=y -CONFIG_VSOCKETS_LOOPBACK=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_X86_5LEVEL is not set -CONFIG_X86_64=y -CONFIG_X86_64_SMP=y -CONFIG_X86_ACPI_CPUFREQ=y -# CONFIG_X86_ACPI_CPUFREQ_CPB is not set -CONFIG_X86_AMD_FREQ_SENSITIVITY=y -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -CONFIG_X86_CPUID=y -CONFIG_X86_DIRECT_GBPAGES=y -CONFIG_X86_HV_CALLBACK_VECTOR=y -CONFIG_X86_INTEL_LPSS=y -# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set -CONFIG_X86_INTEL_PSTATE=y -CONFIG_X86_MINIMUM_CPU_FAMILY=64 -# CONFIG_X86_PCC_CPUFREQ is not set -CONFIG_X86_PKG_TEMP_THERMAL=y -# CONFIG_X86_PMEM_LEGACY is not set -CONFIG_X86_PM_TIMER=y -# CONFIG_X86_POWERNOW_K8 is not set -# CONFIG_X86_VSYSCALL_EMULATION is not set -CONFIG_X86_X2APIC=y -# CONFIG_X86_X32 is not set -CONFIG_XEN=y -CONFIG_XENFS=y -CONFIG_XEN_512GB=y -CONFIG_XEN_ACPI=y -CONFIG_XEN_ACPI_PROCESSOR=y -CONFIG_XEN_AUTO_XLATE=y -# CONFIG_XEN_BACKEND is not set -CONFIG_XEN_BALLOON=y -CONFIG_XEN_BLKDEV_FRONTEND=y -CONFIG_XEN_COMPAT_XENFS=y -CONFIG_XEN_DEBUG_FS=y -CONFIG_XEN_DEV_EVTCHN=y -CONFIG_XEN_DOM0=y -CONFIG_XEN_EFI=y -CONFIG_XEN_FBDEV_FRONTEND=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_XEN_HAVE_PVMMU=y -CONFIG_XEN_HAVE_VPMU=y -# CONFIG_XEN_MCE_LOG is not set -CONFIG_XEN_NETDEV_FRONTEND=y -CONFIG_XEN_PCIDEV_FRONTEND=y -CONFIG_XEN_PRIVCMD=y -CONFIG_XEN_PV=y -CONFIG_XEN_PVH=y -CONFIG_XEN_PVHVM=y -CONFIG_XEN_PVHVM_SMP=y -CONFIG_XEN_PV_SMP=y -CONFIG_XEN_SAVE_RESTORE=y -CONFIG_XEN_SCSI_FRONTEND=y -CONFIG_XEN_SYMS=y -CONFIG_XEN_SYS_HYPERVISOR=y -CONFIG_XEN_WDT=y -CONFIG_XEN_XENBUS_FRONTEND=y -CONFIG_XPS=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/x86/config-5.10 b/target/linux/x86/config-5.10 deleted file mode 100644 index 4616fcba07..0000000000 --- a/target/linux/x86/config-5.10 +++ /dev/null @@ -1,432 +0,0 @@ -# CONFIG_60XX_WDT is not set -# CONFIG_64BIT is not set -# CONFIG_ACPI is not set -# CONFIG_ACQUIRE_WDT is not set -# CONFIG_ADVANTECH_WDT is not set -# CONFIG_ALIM1535_WDT is not set -# CONFIG_ALIX is not set -CONFIG_AMD_NB=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_CLOCKSOURCE_INIT=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_RANDOM=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPLIT_ARG64=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USES_PG_UNCACHED=y -CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y -CONFIG_ATA=y -CONFIG_ATA_GENERIC=y -CONFIG_ATA_PIIX=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BOUNCE=y -CONFIG_CLKBLD_I8253=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKEVT_I8253=y -CONFIG_CLKSRC_I8253=y -CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMPAT_32=y -CONFIG_COMPAT_32BIT_TIME=y -# CONFIG_COMPAT_VDSO is not set -CONFIG_CONSOLE_TRANSLATIONS=y -# CONFIG_CPU5_WDT is not set -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_IBPB_ENTRY=y -CONFIG_CPU_IBRS_ENTRY=y -# CONFIG_SLS is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_SUP_AMD=y -CONFIG_CPU_SUP_CENTAUR=y -CONFIG_CPU_SUP_CYRIX_32=y -CONFIG_CPU_SUP_HYGON=y -CONFIG_CPU_SUP_INTEL=y -CONFIG_CPU_SUP_TRANSMETA_32=y -CONFIG_CPU_SUP_UMC_32=y -CONFIG_CPU_SUP_ZHAOXIN=y -CONFIG_CPU_UNRET_ENTRY=y -CONFIG_CRASH_CORE=y -CONFIG_CRC16=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_CRC32_PCLMUL is not set -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 -CONFIG_CRYPTO_RNG2=y -# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set -# CONFIG_CX_ECAT is not set -CONFIG_DCACHE_WORD_ACCESS=y -# CONFIG_DCDBAS is not set -# CONFIG_DEBUG_BOOT_PARAMS is not set -# CONFIG_DEBUG_ENTRY is not set -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_DEBUG_MISC=y -# CONFIG_DEBUG_NMI_SELFTEST is not set -# CONFIG_DEBUG_TLBFLUSH is not set -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_GZIP=y -# CONFIG_DELL_RBU is not set -CONFIG_DMADEVICES=y -CONFIG_DMI=y -CONFIG_DMIID=y -CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y -CONFIG_DMI_SYSFS=y -CONFIG_DNOTIFY=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -# CONFIG_EARLY_PRINTK_DBGP is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -# CONFIG_EDD is not set -# CONFIG_EISA is not set -# CONFIG_EUROTECH_WDT is not set -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -# CONFIG_F71808E_WDT is not set -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FUSION=y -# CONFIG_FUSION_CTL is not set -# CONFIG_FUSION_LOGGING is not set -CONFIG_FUSION_MAX_SGE=128 -CONFIG_FUSION_SPI=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_ENTRY=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IOMAP=y -CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y -CONFIG_GENERIC_IRQ_RESERVATION_MODE=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -# CONFIG_GEOS is not set -CONFIG_GLOB=y -# CONFIG_HANGCHECK_TIMER is not set -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HID=y -CONFIG_HIGHMEM=y -CONFIG_HIGHMEM4G=y -# CONFIG_HIGHMEM64G is not set -CONFIG_HIGHPTE=y -CONFIG_HPET_EMULATE_RTC=y -CONFIG_HPET_TIMER=y -# CONFIG_HP_WATCHDOG is not set -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_GEODE=y -CONFIG_HW_RANDOM_VIA=y -# CONFIG_HYPERVISOR_GUEST is not set -CONFIG_HZ_PERIODIC=y -CONFIG_I8253_LOCK=y -# CONFIG_I8K is not set -CONFIG_IA32_FEAT_CTL=y -# CONFIG_IB700_WDT is not set -# CONFIG_IBMASR is not set -# CONFIG_IBM_RTL is not set -# CONFIG_IE6XX_WDT is not set -CONFIG_ILLEGAL_POINTER_VALUE=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INSTRUCTION_DECODER=y -# CONFIG_INTEL_PCH_THERMAL is not set -# CONFIG_INTEL_POWERCLAMP is not set -# CONFIG_INTEL_SCU_PCI is not set -# CONFIG_IOSF_MBI is not set -CONFIG_IO_DELAY_0X80=y -# CONFIG_IO_DELAY_0XED is not set -# CONFIG_IO_DELAY_NONE is not set -# CONFIG_IO_DELAY_UDELAY is not set -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -# CONFIG_ISA is not set -CONFIG_ISA_DMA_API=y -# CONFIG_IT8712F_WDT is not set -# CONFIG_IT87_WDT is not set -# CONFIG_ITCO_WDT is not set -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KEXEC=y -CONFIG_KEXEC_CORE=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_LEDS_CLEVO_MAIL is not set -CONFIG_LOCK_DEBUGGING_SUPPORT=y -# CONFIG_M486 is not set -# CONFIG_M486SX is not set -# CONFIG_M586 is not set -# CONFIG_M586MMX is not set -# CONFIG_M586TSC is not set -CONFIG_M686=y -# CONFIG_MACHZ_WDT is not set -# CONFIG_MATOM is not set -# CONFIG_MCORE2 is not set -# CONFIG_MCRUSOE is not set -# CONFIG_MCYRIXIII is not set -# CONFIG_MEFFICEON is not set -# CONFIG_MELAN is not set -CONFIG_MEMFD_CREATE=y -# CONFIG_MFD_INTEL_LPSS_PCI is not set -# CONFIG_MGEODEGX1 is not set -# CONFIG_MGEODE_LX is not set -CONFIG_MICROCODE=y -CONFIG_MICROCODE_AMD=y -CONFIG_MICROCODE_INTEL=y -CONFIG_MICROCODE_LATE_LOADING=y -CONFIG_MIGRATION=y -# CONFIG_MK6 is not set -# CONFIG_MK7 is not set -# CONFIG_MK8 is not set -# CONFIG_MODIFY_LDT_SYSCALL is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MPENTIUM4 is not set -# CONFIG_MPENTIUMII is not set -# CONFIG_MPENTIUMIII is not set -# CONFIG_MPENTIUMM is not set -# CONFIG_MTD is not set -CONFIG_MTRR=y -# CONFIG_MTRR_SANITIZER is not set -# CONFIG_MVIAC3_2 is not set -# CONFIG_MVIAC7 is not set -# CONFIG_MWINCHIP3D is not set -# CONFIG_MWINCHIPC6 is not set -CONFIG_NAMESPACES=y -CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y -CONFIG_NEED_SG_DMA_LENGTH=y -# CONFIG_NET5501 is not set -# CONFIG_NET_NS is not set -CONFIG_NLS=y -# CONFIG_NOHIGHMEM is not set -CONFIG_NR_CPUS=1 -CONFIG_NR_CPUS_DEFAULT=1 -CONFIG_NR_CPUS_RANGE_BEGIN=1 -CONFIG_NR_CPUS_RANGE_END=1 -# CONFIG_NSC_GPIO is not set -CONFIG_NVRAM=y -# CONFIG_OF is not set -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -# CONFIG_OLPC is not set -CONFIG_OPROFILE_NMI_TIMER=y -CONFIG_OUTPUT_FORMAT="elf32-i386" -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PC104=y -# CONFIG_PC8736x_GPIO is not set -# CONFIG_PC87413_WDT is not set -CONFIG_PCI=y -CONFIG_PCI_ATS=y -CONFIG_PCI_BIOS=y -CONFIG_PCI_DIRECT=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_GOANY=y -# CONFIG_PCI_GOBIOS is not set -# CONFIG_PCI_GODIRECT is not set -# CONFIG_PCI_GOMMCONFIG is not set -CONFIG_PCI_IOV=y -CONFIG_PCI_LABEL=y -CONFIG_PCI_LOCKLESS_CONFIG=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_PERF_EVENTS=y -CONFIG_PERF_EVENTS_INTEL_CSTATE=y -CONFIG_PERF_EVENTS_INTEL_RAPL=y -CONFIG_PERF_EVENTS_INTEL_UNCORE=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYSICAL_ALIGN=0x100000 -CONFIG_PHYSICAL_START=0x1000000 -# CONFIG_PHY_INTEL_LGM_EMMC is not set -CONFIG_PMC_ATOM=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_SUPPLY=y -# CONFIG_PROCESSOR_SELECT is not set -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_PID_ARCH_STATUS=y -# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_PUNIT_ATOM_DEBUG is not set -CONFIG_RATIONAL=y -CONFIG_RD_BZIP2=y -CONFIG_RD_GZIP=y -CONFIG_RETHUNK=y -CONFIG_RETPOLINE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_MC146818_LIB=y -CONFIG_SATA_HOST=y -# CONFIG_SBC7240_WDT is not set -# CONFIG_SBC8360_WDT is not set -# CONFIG_SBC_EPX_C3_WATCHDOG is not set -# CONFIG_SC1200_WDT is not set -CONFIG_SCSI=y -CONFIG_SCSI_SPI_ATTRS=y -CONFIG_SCx200=y -CONFIG_SCx200HR_TIMER=y -# CONFIG_SCx200_GPIO is not set -# CONFIG_SCx200_WDT is not set -CONFIG_SERIAL_8250_PCI=y -# CONFIG_SERIAL_LANTIQ is not set -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIO_SERPORT=y -CONFIG_SG_POOL=y -# CONFIG_SMSC37B787_WDT is not set -# CONFIG_SMSC_SCH311X_WDT is not set -CONFIG_SPARSEMEM_STATIC=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPECULATION_MITIGATIONS=y -CONFIG_SRCU=y -# CONFIG_STATIC_CALL_SELFTEST is not set -CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_TELCLOCK is not set -# CONFIG_TEST_FPU is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TINY_SRCU=y -# CONFIG_TOSHIBA is not set -# CONFIG_TQMX86_WDT is not set -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_UNWINDER_FRAME_POINTER=y -# CONFIG_UNWINDER_GUESS is not set -CONFIG_UP_LATE_INIT=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_HCD_PLATFORM is not set -CONFIG_USB_EHCI_PCI=y -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PCI=y -# CONFIG_USB_OHCI_HCD_PLATFORM is not set -CONFIG_USB_PCI=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI=y -# CONFIG_USB_XHCI_PLATFORM is not set -# CONFIG_USER_NS is not set -CONFIG_USER_STACKTRACE_SUPPORT=y -CONFIG_VGA_CONSOLE=y -# CONFIG_VIA_WDT is not set -# CONFIG_VMWARE_VMCI is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -# CONFIG_WAFER_WDT is not set -CONFIG_X86=y -CONFIG_X86_32=y -# CONFIG_X86_32_IRIS is not set -CONFIG_X86_32_LAZY_GS=y -# CONFIG_X86_ANCIENT_MCE is not set -# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set -CONFIG_X86_CMOV=y -CONFIG_X86_CMPXCHG64=y -# CONFIG_X86_CPA_STATISTICS is not set -# CONFIG_X86_CPUFREQ_NFORCE2 is not set -# CONFIG_X86_CPUID is not set -# CONFIG_X86_CPU_RESCTRL is not set -CONFIG_X86_DEBUGCTLMSR=y -# CONFIG_X86_DEBUG_FPU is not set -# CONFIG_X86_DECODER_SELFTEST is not set -# CONFIG_X86_EXTENDED_PLATFORM is not set -CONFIG_X86_FEATURE_NAMES=y -CONFIG_X86_GENERIC=y -# CONFIG_X86_GX_SUSPMOD is not set -# CONFIG_X86_INTEL_PSTATE is not set -# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set -CONFIG_X86_INTEL_TSX_MODE_OFF=y -# CONFIG_X86_INTEL_TSX_MODE_ON is not set -CONFIG_X86_INTEL_USERCOPY=y -CONFIG_X86_INTERNODE_CACHE_SHIFT=6 -CONFIG_X86_IOPL_IOPERM=y -CONFIG_X86_IO_APIC=y -CONFIG_X86_L1_CACHE_SHIFT=6 -# CONFIG_X86_LEGACY_VM86 is not set -CONFIG_X86_LOCAL_APIC=y -# CONFIG_X86_LONGRUN is not set -CONFIG_X86_MCE=y -# CONFIG_X86_MCELOG_LEGACY is not set -CONFIG_X86_MCE_AMD=y -# CONFIG_X86_MCE_INJECT is not set -CONFIG_X86_MCE_INTEL=y -CONFIG_X86_MCE_THRESHOLD=y -CONFIG_X86_MINIMUM_CPU_FAMILY=6 -CONFIG_X86_MPPARSE=y -CONFIG_X86_MSR=y -# CONFIG_X86_P4_CLOCKMOD is not set -CONFIG_X86_PAT=y -CONFIG_X86_PLATFORM_DEVICES=y -# CONFIG_X86_POWERNOW_K6 is not set -# CONFIG_X86_POWERNOW_K7 is not set -# CONFIG_X86_REBOOTFIXUPS is not set -CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y -CONFIG_X86_RESERVE_LOW=64 -CONFIG_X86_SMAP=y -# CONFIG_X86_SPEEDSTEP_CENTRINO is not set -# CONFIG_X86_SPEEDSTEP_ICH is not set -# CONFIG_X86_SPEEDSTEP_SMI is not set -CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y -CONFIG_X86_THERMAL_VECTOR=y -CONFIG_X86_TSC=y -CONFIG_X86_UMIP=y -CONFIG_X86_UP_APIC=y -CONFIG_X86_UP_IOAPIC=y -CONFIG_X86_USE_PPRO_CHECKSUM=y -CONFIG_X86_VERBOSE_BOOTUP=y -CONFIG_X86_VMX_FEATURE_NAMES=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_XZ_DEC_X86=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/x86/generic/config-5.10 b/target/linux/x86/generic/config-5.10 deleted file mode 100644 index b683720bf8..0000000000 --- a/target/linux/x86/generic/config-5.10 +++ /dev/null @@ -1,449 +0,0 @@ -# CONFIG_3C515 is not set -CONFIG_ACPI=y -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -# CONFIG_ACPI_BGRT is not set -CONFIG_ACPI_BUTTON=y -# CONFIG_ACPI_CMPC is not set -CONFIG_ACPI_CONTAINER=y -CONFIG_ACPI_CPU_FREQ_PSS=y -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUGGER is not set -# CONFIG_ACPI_DOCK is not set -# CONFIG_ACPI_DPTF is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -# CONFIG_ACPI_FAN is not set -CONFIG_ACPI_HOTPLUG_CPU=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y -# CONFIG_ACPI_I2C_OPREGION is not set -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_PROCESSOR=y -# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y -# CONFIG_ACPI_SBS is not set -CONFIG_ACPI_SPCR_TABLE=y -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -CONFIG_ACPI_TAD=y -CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_VIDEO=y -# CONFIG_ACPI_WMI is not set -CONFIG_AGP=y -# CONFIG_AGP_ALI is not set -# CONFIG_AGP_AMD is not set -# CONFIG_AGP_AMD64 is not set -# CONFIG_AGP_ATI is not set -# CONFIG_AGP_EFFICEON is not set -CONFIG_AGP_INTEL=y -# CONFIG_AGP_NVIDIA is not set -# CONFIG_AGP_SIS is not set -# CONFIG_AGP_SWORKS is not set -# CONFIG_AGP_VIA is not set -# CONFIG_APM is not set -CONFIG_ARCH_CPUIDLE_HALTPOLL=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BALLOON_COMPACTION=y -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_MQ_VIRTIO=y -CONFIG_BLK_PM=y -# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set -CONFIG_BTT=y -CONFIG_CDROM=y -CONFIG_CONNECTOR=y -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_RMAP=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -# CONFIG_DEBUG_HOTPLUG_CPU0 is not set -CONFIG_DMA_ACPI=y -CONFIG_DMA_OPS=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DRM=y -CONFIG_DRM_BOCHS=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_I915=y -CONFIG_DRM_I915_CAPTURE_ERROR=y -CONFIG_DRM_I915_COMPRESS_ERROR=y -# CONFIG_DRM_I915_DEBUG is not set -# CONFIG_DRM_I915_DEBUG_GUC is not set -# CONFIG_DRM_I915_DEBUG_MMIO is not set -# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set -# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set -CONFIG_DRM_I915_FENCE_TIMEOUT=10000 -CONFIG_DRM_I915_FORCE_PROBE="" -CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 -# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set -CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 -CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 -# CONFIG_DRM_I915_SELFTEST is not set -CONFIG_DRM_I915_STOP_TIMEOUT=100 -# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set -# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set -CONFIG_DRM_I915_TIMESLICE_DURATION=1 -CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 -CONFIG_DRM_I915_USERPTR=y -# CONFIG_DRM_I915_WERROR is not set -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_TTM=y -CONFIG_DRM_TTM_DMA_PAGE_POOL=y -CONFIG_DRM_TTM_HELPER=y -CONFIG_DRM_VIRTIO_GPU=y -CONFIG_DRM_VRAM_HELPER=y -CONFIG_EFI=y -CONFIG_EFIVAR_FS=m -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH is not set -# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_ESRT=y -# CONFIG_EFI_FAKE_MEMMAP is not set -CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y -# CONFIG_EFI_PGT_DUMP is not set -# CONFIG_EFI_RCI2_TABLE is not set -CONFIG_EFI_RUNTIME_MAP=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_STUB=y -# CONFIG_EFI_TEST is not set -# CONFIG_EFI_VARS is not set -# CONFIG_EL3 is not set -CONFIG_FAILOVER=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_EFI=y -CONFIG_FB_HYPERV=y -# CONFIG_FB_I810 is not set -CONFIG_FB_SIMPLE=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_VESA is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_FREEZER=y -CONFIG_FW_CACHE=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GPIOLIB_IRQCHIP=y -CONFIG_GPIO_ACPI=y -CONFIG_GUP_GET_PTE_LOW_HIGH=y -CONFIG_HALTPOLL_CPUIDLE=y -CONFIG_HDMI=y -CONFIG_HIBERNATE_CALLBACKS=y -CONFIG_HID_BATTERY_STRENGTH=y -CONFIG_HID_GENERIC=y -CONFIG_HID_HYPERV_MOUSE=y -# CONFIG_HIGHMEM4G is not set -CONFIG_HIGHMEM64G=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HOTPLUG_PCI=y -CONFIG_HOTPLUG_PCI_ACPI=y -# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set -# CONFIG_HOTPLUG_PCI_COMPAQ is not set -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_IBM is not set -CONFIG_HOTPLUG_PCI_PCIE=y -# CONFIG_HOTPLUG_PCI_SHPC is not set -CONFIG_HOTPLUG_SMT=y -CONFIG_HPET=y -CONFIG_HPET_MMAP=y -# CONFIG_HP_ACCEL is not set -CONFIG_HVC_DRIVER=y -CONFIG_HVC_IRQ=y -CONFIG_HVC_XEN=y -CONFIG_HVC_XEN_FRONTEND=y -CONFIG_HWMON=y -CONFIG_HWMON_VID=y -CONFIG_HW_RANDOM_VIRTIO=y -CONFIG_HYPERV=y -CONFIG_HYPERVISOR_GUEST=y -CONFIG_HYPERV_BALLOON=y -CONFIG_HYPERV_KEYBOARD=y -CONFIG_HYPERV_NET=y -CONFIG_HYPERV_STORAGE=y -# CONFIG_HYPERV_TESTING is not set -CONFIG_HYPERV_TIMER=y -CONFIG_HYPERV_UTILS=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -# CONFIG_I2C_AMD_MP2 is not set -CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_MULTI_INSTANTIATE is not set -# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y -CONFIG_INTEL_GTT=y -CONFIG_INTEL_IDLE=y -# CONFIG_INTEL_IPS is not set -# CONFIG_INTEL_MEI_HDCP is not set -# CONFIG_INTEL_MENLOW is not set -CONFIG_INTEL_PCH_THERMAL=y -# CONFIG_INTEL_SCU_PLATFORM is not set -CONFIG_INTEL_SOC_DTS_IOSF_CORE=y -CONFIG_INTEL_SOC_DTS_THERMAL=y -CONFIG_INTERVAL_TREE=y -CONFIG_IOSF_MBI=y -# CONFIG_IOSF_MBI_DEBUG is not set -CONFIG_IRQ_BYPASS_MANAGER=y -CONFIG_ISA=y -CONFIG_ISAPNP=y -CONFIG_ISA_BUS_API=y -# CONFIG_ISCSI_IBFT is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -CONFIG_KCMP=y -CONFIG_KVM=y -CONFIG_KVM_AMD=y -CONFIG_KVM_ASYNC_PF=y -CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y -CONFIG_KVM_GUEST=y -CONFIG_KVM_INTEL=y -CONFIG_KVM_MMIO=y -CONFIG_KVM_VFIO=y -CONFIG_KVM_XFER_TO_GUEST_WORK=y -# CONFIG_LANCE is not set -CONFIG_LIBNVDIMM=y -CONFIG_LOCK_SPIN_ON_OWNER=y -# CONFIG_M686 is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_MEMORY_BALLOON=y -CONFIG_MEMREGION=y -CONFIG_MFD_CORE=y -CONFIG_MFD_INTEL_LPSS=y -CONFIG_MFD_INTEL_LPSS_ACPI=y -# CONFIG_MFD_INTEL_PMC_BXT is not set -# CONFIG_MIXCOMWD is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_RICOH_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y -CONFIG_MMC_SDHCI_PCI=y -# CONFIG_MMC_SDHCI_PLTFM is not set -# CONFIG_MMC_WBSD is not set -CONFIG_MMU_NOTIFIER=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -# CONFIG_MOUSE_PS2_BYD is not set -# CONFIG_MOUSE_PS2_CYPRESS is not set -# CONFIG_MOUSE_PS2_ELANTECH is not set -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SMBUS=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_VMMOUSE is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_MPENTIUM4=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_ND_BLK=y -CONFIG_ND_BTT=y -CONFIG_ND_CLAIM=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NET_FAILOVER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NO_HZ=y -CONFIG_NR_CPUS=4 -CONFIG_NR_CPUS_DEFAULT=8 -CONFIG_NR_CPUS_RANGE_BEGIN=2 -CONFIG_NR_CPUS_RANGE_END=8 -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_REPORTING=y -CONFIG_PAGE_TABLE_ISOLATION=y -CONFIG_PARAVIRT=y -CONFIG_PARAVIRT_CLOCK=y -# CONFIG_PARAVIRT_DEBUG is not set -CONFIG_PARAVIRT_SPINLOCKS=y -CONFIG_PATA_AMD=y -CONFIG_PATA_ATIIXP=y -CONFIG_PATA_MPIIX=y -CONFIG_PATA_OLDPIIX=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_SC1200=y -CONFIG_PATA_TIMINGS=y -CONFIG_PATA_VIA=y -# CONFIG_PCENGINES_APU2 is not set -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_PME=y -CONFIG_PCI_MMCONFIG=y -CONFIG_PCI_XEN=y -# CONFIG_PCWATCHDOG is not set -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_BAYTRAIL=y -CONFIG_PINCTRL_BROXTON=y -CONFIG_PINCTRL_CANNONLAKE=y -CONFIG_PINCTRL_CHERRYVIEW=y -CONFIG_PINCTRL_DENVERTON=y -CONFIG_PINCTRL_EMMITSBURG=y -CONFIG_PINCTRL_GEMINILAKE=y -CONFIG_PINCTRL_INTEL=y -CONFIG_PINCTRL_JASPERLAKE=y -CONFIG_PINCTRL_LEWISBURG=y -CONFIG_PINCTRL_LYNXPOINT=y -CONFIG_PINCTRL_SUNRISEPOINT=y -CONFIG_PINCTRL_TIGERLAKE=y -CONFIG_PM=y -# CONFIG_PMIC_OPREGION is not set -CONFIG_PM_CLK=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_PNP=y -CONFIG_PNPACPI=y -# CONFIG_PNPBIOS is not set -CONFIG_PNP_DEBUG_MESSAGES=y -CONFIG_PREEMPT_NOTIFIERS=y -CONFIG_PROC_EVENTS=y -CONFIG_PVH=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -CONFIG_RELAY=y -CONFIG_RELOCATABLE=y -CONFIG_RESET_ATTACK_MITIGATION=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SAMSUNG_Q10 is not set -CONFIG_SATA_AHCI=y -CONFIG_SATA_VIA=y -CONFIG_SCHED_INFO=y -CONFIG_SCHED_SMT=y -# CONFIG_SCSI_FDOMAIN_ISA is not set -CONFIG_SCSI_VIRTIO=y -# CONFIG_SENSORS_AMD_ENERGY is not set -CONFIG_SENSORS_CORETEMP=y -CONFIG_SENSORS_FAM15H_POWER=y -CONFIG_SENSORS_I5500=y -CONFIG_SENSORS_K10TEMP=y -CONFIG_SENSORS_K8TEMP=y -CONFIG_SENSORS_VIA_CPUTEMP=y -CONFIG_SERIAL_8250_PNP=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SMP=y -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set -CONFIG_SWIOTLB=y -CONFIG_SWIOTLB_XEN=y -CONFIG_SYNC_FILE=y -# CONFIG_SYSTEM76_ACPI is not set -CONFIG_SYS_HYPERVISOR=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -# CONFIG_TOSHIBA_BT_RFKILL is not set -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UCLAMP_TASK is not set -CONFIG_UCS2_STRING=y -CONFIG_USB_STORAGE=y -CONFIG_USER_RETURN_NOTIFIER=y -CONFIG_VHOST=y -CONFIG_VHOST_IOTLB=y -CONFIG_VHOST_NET=y -CONFIG_VIRTIO=y -CONFIG_VIRTIO_BALLOON=y -CONFIG_VIRTIO_BLK=y -CONFIG_VIRTIO_CONSOLE=y -CONFIG_VIRTIO_DMA_SHARED_BUFFER=y -CONFIG_VIRTIO_INPUT=y -CONFIG_VIRTIO_MMIO=y -CONFIG_VIRTIO_NET=y -CONFIG_VIRTIO_PCI=y -CONFIG_VIRTIO_PCI_LEGACY=y -# CONFIG_VIRTIO_PMEM is not set -CONFIG_VIRTUALIZATION=y -CONFIG_VMAP_PFN=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WDT is not set -CONFIG_X86_32_SMP=y -CONFIG_X86_ACPI_CPUFREQ=y -# CONFIG_X86_ACPI_CPUFREQ_CPB is not set -CONFIG_X86_AMD_FREQ_SENSITIVITY=y -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -# CONFIG_X86_BIGSMP is not set -CONFIG_X86_CPUID=y -# CONFIG_X86_E_POWERSAVER is not set -CONFIG_X86_HV_CALLBACK_VECTOR=y -CONFIG_X86_INTEL_LPSS=y -CONFIG_X86_INTEL_PSTATE=y -CONFIG_X86_INTERNODE_CACHE_SHIFT=7 -CONFIG_X86_L1_CACHE_SHIFT=7 -# CONFIG_X86_LONGHAUL is not set -CONFIG_X86_NEED_RELOCS=y -CONFIG_X86_PAE=y -# CONFIG_X86_PCC_CPUFREQ is not set -CONFIG_X86_PKG_TEMP_THERMAL=y -# CONFIG_X86_PMEM_LEGACY is not set -CONFIG_X86_PM_TIMER=y -# CONFIG_X86_POWERNOW_K8 is not set -CONFIG_XEN=y -CONFIG_XENFS=y -CONFIG_XEN_ACPI=y -CONFIG_XEN_AUTO_XLATE=y -# CONFIG_XEN_BACKEND is not set -CONFIG_XEN_BALLOON=y -CONFIG_XEN_BLKDEV_FRONTEND=y -CONFIG_XEN_COMPAT_XENFS=y -CONFIG_XEN_DEBUG_FS=y -CONFIG_XEN_DEV_EVTCHN=y -CONFIG_XEN_FBDEV_FRONTEND=y -CONFIG_XEN_GNTDEV=y -CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_XEN_NETDEV_FRONTEND=y -CONFIG_XEN_PCIDEV_FRONTEND=y -CONFIG_XEN_PRIVCMD=y -CONFIG_XEN_PVH=y -CONFIG_XEN_PVHVM=y -CONFIG_XEN_PVHVM_SMP=y -CONFIG_XEN_SAVE_RESTORE=y -CONFIG_XEN_SCSI_FRONTEND=y -CONFIG_XEN_SYS_HYPERVISOR=y -CONFIG_XEN_WDT=y -CONFIG_XEN_XENBUS_FRONTEND=y -CONFIG_XPS=y -CONFIG_ZLIB_DEFLATE=y diff --git a/target/linux/x86/geode/config-5.10 b/target/linux/x86/geode/config-5.10 deleted file mode 100644 index 579f316914..0000000000 --- a/target/linux/x86/geode/config-5.10 +++ /dev/null @@ -1,139 +0,0 @@ -# CONFIG_3C515 is not set -CONFIG_8139CP=y -CONFIG_8139TOO=y -CONFIG_8139TOO_8129=y -CONFIG_8139TOO_PIO=y -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139_OLD_RX_RESET is not set -CONFIG_ACPI=y -CONFIG_ACPI_AC=y -# CONFIG_ACPI_BATTERY is not set -# CONFIG_ACPI_CMPC is not set -# CONFIG_ACPI_CONTAINER is not set -CONFIG_ACPI_CPU_FREQ_PSS=y -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUGGER is not set -# CONFIG_ACPI_DOCK is not set -# CONFIG_ACPI_DPTF is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -CONFIG_ACPI_FAN=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y -CONFIG_ACPI_I2C_OPREGION=y -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_PROCESSOR=y -# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y -# CONFIG_ACPI_SBS is not set -CONFIG_ACPI_SPCR_TABLE=y -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -CONFIG_ACPI_THERMAL=y -# CONFIG_ACPI_TINY_POWER_BUTTON is not set -# CONFIG_ACPI_WMI is not set -CONFIG_ALIX=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -# CONFIG_ATA_PIIX is not set -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CS5535_CLOCK_EVENT_SRC=y -CONFIG_CS5535_MFGPT=y -CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7 -CONFIG_DMA_ACPI=y -# CONFIG_EL3 is not set -CONFIG_GEODE_WDT=y -CONFIG_GEOS=y -CONFIG_GPIO_ACPI=y -CONFIG_GPIO_CS5535=y -# CONFIG_HPET is not set -# CONFIG_HP_ACCEL is not set -CONFIG_HWMON=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_ALGOPCA=y -CONFIG_I2C_ALGOPCF=y -# CONFIG_I2C_AMD_MP2 is not set -CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_MULTI_INSTANTIATE is not set -# CONFIG_INTEL_IPS is not set -# CONFIG_INTEL_MENLOW is not set -# CONFIG_INTEL_SCU_PLATFORM is not set -# CONFIG_INTEL_SOC_DTS_THERMAL is not set -CONFIG_IOSF_MBI=y -# CONFIG_IOSF_MBI_DEBUG is not set -CONFIG_ISA=y -# CONFIG_ISAPNP is not set -CONFIG_ISA_BUS_API=y -# CONFIG_ISCSI_IBFT is not set -# CONFIG_LANCE is not set -CONFIG_LEDS_GPIO=y -# CONFIG_M686 is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_MFD_CORE=y -CONFIG_MFD_CS5535=y -# CONFIG_MFD_INTEL_LPSS_ACPI is not set -# CONFIG_MFD_INTEL_PMC_BXT is not set -CONFIG_MGEODEGX1=y -# CONFIG_MIXCOMWD is not set -CONFIG_NATSEMI=y -CONFIG_NET5501=y -CONFIG_NSC_GPIO=y -CONFIG_PATA_CS5520=y -CONFIG_PATA_CS5530=y -CONFIG_PATA_CS5535=y -CONFIG_PATA_CS5536=y -CONFIG_PATA_SC1200=y -CONFIG_PC8736x_GPIO=y -# CONFIG_PCENGINES_APU2 is not set -CONFIG_PCI_MMCONFIG=y -# CONFIG_PCWATCHDOG is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_BAYTRAIL is not set -# CONFIG_PINCTRL_BROXTON is not set -# CONFIG_PINCTRL_CANNONLAKE is not set -# CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_DENVERTON is not set -# CONFIG_PINCTRL_EMMITSBURG is not set -# CONFIG_PINCTRL_GEMINILAKE is not set -# CONFIG_PINCTRL_JASPERLAKE is not set -# CONFIG_PINCTRL_LEWISBURG is not set -# CONFIG_PINCTRL_LYNXPOINT is not set -# CONFIG_PINCTRL_SUNRISEPOINT is not set -# CONFIG_PINCTRL_TIGERLAKE is not set -# CONFIG_PMIC_OPREGION is not set -CONFIG_PNP=y -CONFIG_PNPACPI=y -# CONFIG_PNPBIOS is not set -CONFIG_PNP_DEBUG_MESSAGES=y -CONFIG_RTC_I2C_AND_SPI=y -# CONFIG_SAMSUNG_Q10 is not set -CONFIG_SC1200_WDT=y -# CONFIG_SCSI_FDOMAIN_ISA is not set -CONFIG_SCx200_ACB=y -CONFIG_SCx200_WDT=y -# CONFIG_SENSORS_AMD_ENERGY is not set -CONFIG_SENSORS_LM90=y -CONFIG_SERIAL_8250_PNP=y -CONFIG_SERIAL_MCTRL_GPIO=y -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set -# CONFIG_SYSTEM76_ACPI is not set -# CONFIG_TOSHIBA_BT_RFKILL is not set -# CONFIG_USB_UHCI_HCD is not set -CONFIG_VIA_RHINE=y -CONFIG_VIA_RHINE_MMIO=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WDT is not set -# CONFIG_X86_ACPI_CPUFREQ is not set -CONFIG_X86_ALIGNMENT_16=y -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -CONFIG_X86_CPUID=y -# CONFIG_X86_E_POWERSAVER is not set -CONFIG_X86_INTEL_LPSS=y -# CONFIG_X86_LONGHAUL is not set -# CONFIG_X86_MCE is not set -CONFIG_X86_MINIMUM_CPU_FAMILY=5 -# CONFIG_X86_PCC_CPUFREQ is not set -CONFIG_X86_PM_TIMER=y -CONFIG_X86_REBOOTFIXUPS=y diff --git a/target/linux/x86/legacy/config-5.10 b/target/linux/x86/legacy/config-5.10 deleted file mode 100644 index 12330ba92f..0000000000 --- a/target/linux/x86/legacy/config-5.10 +++ /dev/null @@ -1,220 +0,0 @@ -# CONFIG_3C515 is not set -CONFIG_ACPI=y -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -CONFIG_ACPI_BUTTON=y -# CONFIG_ACPI_CMPC is not set -# CONFIG_ACPI_CONTAINER is not set -CONFIG_ACPI_CPU_FREQ_PSS=y -# CONFIG_ACPI_DEBUG is not set -# CONFIG_ACPI_DEBUGGER is not set -# CONFIG_ACPI_DOCK is not set -# CONFIG_ACPI_DPTF is not set -# CONFIG_ACPI_EC_DEBUGFS is not set -# CONFIG_ACPI_FAN is not set -CONFIG_ACPI_HOTPLUG_IOAPIC=y -# CONFIG_ACPI_I2C_OPREGION is not set -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -# CONFIG_ACPI_PCI_SLOT is not set -CONFIG_ACPI_PROCESSOR=y -# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y -# CONFIG_ACPI_SBS is not set -CONFIG_ACPI_SPCR_TABLE=y -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_VIDEO=y -# CONFIG_ACPI_WMI is not set -CONFIG_AGP=y -# CONFIG_AGP_ALI is not set -# CONFIG_AGP_AMD is not set -# CONFIG_AGP_AMD64 is not set -# CONFIG_AGP_ATI is not set -# CONFIG_AGP_EFFICEON is not set -CONFIG_AGP_INTEL=y -# CONFIG_AGP_NVIDIA is not set -# CONFIG_AGP_SIS is not set -# CONFIG_AGP_SWORKS is not set -# CONFIG_AGP_VIA is not set -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BLK_DEV_SR=y -CONFIG_CDROM=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CRYPTO_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_DMA_ACPI=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DRM=y -CONFIG_DRM_AMDGPU=y -# CONFIG_DRM_AMD_DC is not set -CONFIG_DRM_BOCHS=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_I915=y -CONFIG_DRM_I915_CAPTURE_ERROR=y -CONFIG_DRM_I915_COMPRESS_ERROR=y -# CONFIG_DRM_I915_DEBUG is not set -# CONFIG_DRM_I915_DEBUG_GUC is not set -# CONFIG_DRM_I915_DEBUG_MMIO is not set -# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set -# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set -CONFIG_DRM_I915_FENCE_TIMEOUT=10000 -CONFIG_DRM_I915_FORCE_PROBE="" -CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 -# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set -CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 -CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 -# CONFIG_DRM_I915_SELFTEST is not set -CONFIG_DRM_I915_STOP_TIMEOUT=100 -# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set -# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set -CONFIG_DRM_I915_TIMESLICE_DURATION=1 -CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 -CONFIG_DRM_I915_USERPTR=y -# CONFIG_DRM_I915_WERROR is not set -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_RADEON=y -CONFIG_DRM_SCHED=y -CONFIG_DRM_TTM=y -CONFIG_DRM_TTM_HELPER=y -CONFIG_DRM_VRAM_HELPER=y -# CONFIG_EL3 is not set -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_I810 is not set -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_VESA is not set -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -CONFIG_HDMI=y -CONFIG_HID_BATTERY_STRENGTH=y -# CONFIG_HIGHMEM4G is not set -CONFIG_HPET=y -CONFIG_HPET_MMAP=y -# CONFIG_HP_ACCEL is not set -CONFIG_HWMON=y -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -# CONFIG_I2C_AMD_MP2 is not set -CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_MULTI_INSTANTIATE is not set -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INTEL_GTT=y -CONFIG_INTEL_IDLE=y -# CONFIG_INTEL_IPS is not set -# CONFIG_INTEL_MEI_HDCP is not set -# CONFIG_INTEL_MENLOW is not set -# CONFIG_INTEL_SCU_PLATFORM is not set -# CONFIG_INTEL_SOC_DTS_THERMAL is not set -CONFIG_INTERVAL_TREE=y -CONFIG_IOSF_MBI=y -# CONFIG_IOSF_MBI_DEBUG is not set -CONFIG_ISA=y -CONFIG_ISAPNP=y -CONFIG_ISA_BUS_API=y -# CONFIG_ISCSI_IBFT is not set -CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -CONFIG_KCMP=y -# CONFIG_LANCE is not set -CONFIG_M586MMX=y -# CONFIG_M686 is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_MFD_CORE=y -CONFIG_MFD_INTEL_LPSS=y -CONFIG_MFD_INTEL_LPSS_ACPI=y -# CONFIG_MFD_INTEL_PMC_BXT is not set -# CONFIG_MIXCOMWD is not set -CONFIG_MMU_NOTIFIER=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -# CONFIG_MOUSE_PS2_BYD is not set -# CONFIG_MOUSE_PS2_CYPRESS is not set -# CONFIG_MOUSE_PS2_ELANTECH is not set -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SMBUS=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_NOHIGHMEM=y -CONFIG_NO_HZ=y -CONFIG_PATA_AMD=y -CONFIG_PATA_ATIIXP=y -CONFIG_PATA_LEGACY=y -CONFIG_PATA_MPIIX=y -CONFIG_PATA_OLDPIIX=y -CONFIG_PATA_PLATFORM=y -CONFIG_PATA_SC1200=y -CONFIG_PATA_SIS=y -CONFIG_PATA_TIMINGS=y -CONFIG_PATA_VIA=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_MMCONFIG=y -# CONFIG_PCWATCHDOG is not set -# CONFIG_PMIC_OPREGION is not set -CONFIG_PNP=y -CONFIG_PNPACPI=y -# CONFIG_PNPBIOS is not set -CONFIG_PNP_DEBUG_MESSAGES=y -CONFIG_RAS=y -CONFIG_RELAY=y -CONFIG_RTC_I2C_AND_SPI=y -# CONFIG_SAMSUNG_Q10 is not set -CONFIG_SATA_AHCI=y -# CONFIG_SCSI_FDOMAIN_ISA is not set -# CONFIG_SENSORS_AMD_ENERGY is not set -CONFIG_SERIAL_8250_PNP=y -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set -CONFIG_SYNC_FILE=y -# CONFIG_SYSTEM76_ACPI is not set -# CONFIG_TOSHIBA_BT_RFKILL is not set -CONFIG_USB_STORAGE=y -CONFIG_VMAP_PFN=y -# CONFIG_WDT is not set -CONFIG_X86_ACPI_CPUFREQ=y -# CONFIG_X86_ACPI_CPUFREQ_CPB is not set -CONFIG_X86_ALIGNMENT_16=y -# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -# CONFIG_X86_E_POWERSAVER is not set -CONFIG_X86_F00F_BUG=y -# CONFIG_X86_INTEL_LPSS is not set -# CONFIG_X86_LONGHAUL is not set -CONFIG_X86_MINIMUM_CPU_FAMILY=5 -# CONFIG_X86_PAE is not set -# CONFIG_X86_PCC_CPUFREQ is not set -CONFIG_X86_PM_TIMER=y -# CONFIG_X86_POWERNOW_K8 is not set -CONFIG_ZLIB_DEFLATE=y diff --git a/target/linux/x86/patches-5.10/100-fix_cs5535_clockevt.patch b/target/linux/x86/patches-5.10/100-fix_cs5535_clockevt.patch deleted file mode 100644 index d4de2027ba..0000000000 --- a/target/linux/x86/patches-5.10/100-fix_cs5535_clockevt.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/drivers/clocksource/timer-cs5535.c -+++ b/drivers/clocksource/timer-cs5535.c -@@ -127,7 +127,9 @@ static irqreturn_t mfgpt_tick(int irq, v - cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP, - MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); - -- cs5535_clockevent.event_handler(&cs5535_clockevent); -+ if (cs5535_clockevent.event_handler) -+ cs5535_clockevent.event_handler(&cs5535_clockevent); -+ - return IRQ_HANDLED; - } - diff --git a/target/linux/x86/patches-5.10/101-v5.15-mfd-lpc_ich-Enable-GPIO-driver-for-DH89xxCC.patch b/target/linux/x86/patches-5.10/101-v5.15-mfd-lpc_ich-Enable-GPIO-driver-for-DH89xxCC.patch deleted file mode 100644 index a5bd2459ab..0000000000 --- a/target/linux/x86/patches-5.10/101-v5.15-mfd-lpc_ich-Enable-GPIO-driver-for-DH89xxCC.patch +++ /dev/null @@ -1,28 +0,0 @@ -From ef0eea5b151aefe1efea78e2fa7c507ff3c56bf0 Mon Sep 17 00:00:00 2001 -From: Chris Blake -Date: Mon, 7 Jun 2021 18:35:35 -0500 -Subject: mfd: lpc_ich: Enable GPIO driver for DH89xxCC - -Based on the Intel Datasheet for the DH89xxCC PCH, the GPIO driver -is the same as ICH_v5_GPIO, minus the fact the DH89xxCC also has -blink support. However, blink support isn't supported by the GPIO -driver so we should use ICH_v5_GPIO. Tested and working on a Meraki -MX100-HW. - -Signed-off-by: Chris Blake -Co-developed-by: Christian Lamparter -Signed-off-by: Lee Jones ---- - drivers/mfd/lpc_ich.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/mfd/lpc_ich.c -+++ b/drivers/mfd/lpc_ich.c -@@ -491,6 +491,7 @@ static struct lpc_ich_info lpc_chipset_i - [LPC_DH89XXCC] = { - .name = "DH89xxCC", - .iTCO_version = 2, -+ .gpio_version = ICH_V5_GPIO, - }, - [LPC_PPT] = { - .name = "Panther Point", diff --git a/target/linux/x86/patches-5.10/102-v5.15-platform-x86-add-meraki-mx100-platform-driver.patch b/target/linux/x86/patches-5.10/102-v5.15-platform-x86-add-meraki-mx100-platform-driver.patch deleted file mode 100644 index 0babc73b06..0000000000 --- a/target/linux/x86/patches-5.10/102-v5.15-platform-x86-add-meraki-mx100-platform-driver.patch +++ /dev/null @@ -1,291 +0,0 @@ -From 636a1e697555e73c28cdd6952a409edbfdd16475 Mon Sep 17 00:00:00 2001 -From: Chris Blake -Date: Mon, 9 Aug 2021 19:40:21 -0500 -Subject: platform/x86: add meraki-mx100 platform driver - -This adds platform support for the Cisco Meraki MX100 (Tinkerbell) -network appliance. This sets up the network LEDs and Reset -button. - -Depends-on: ef0eea5b151ae ("mfd: lpc_ich: Enable GPIO driver for DH89xxCC") -Co-developed-by: Christian Lamparter -Signed-off-by: Christian Lamparter -Signed-off-by: Chris Blake -Reviewed-by: Andy Shevchenko -Link: https://lore.kernel.org/r/20210810004021.2538308-1-chrisrblake93@gmail.com -Reviewed-by: Hans de Goede -Signed-off-by: Hans de Goede ---- - drivers/platform/x86/Kconfig | 13 ++ - drivers/platform/x86/Makefile | 3 + - drivers/platform/x86/meraki-mx100.c | 230 ++++++++++++++++++++++++++++++++++++ - 3 files changed, 246 insertions(+) - create mode 100644 drivers/platform/x86/meraki-mx100.c - ---- a/drivers/platform/x86/Kconfig -+++ b/drivers/platform/x86/Kconfig -@@ -267,6 +267,19 @@ config ASUS_NB_WMI - If you have an ACPI-WMI compatible Asus Notebook, say Y or M - here. - -+config MERAKI_MX100 -+ tristate "Cisco Meraki MX100 Platform Driver" -+ depends on GPIOLIB -+ depends on GPIO_ICH -+ depends on LEDS_CLASS -+ select LEDS_GPIO -+ help -+ This driver provides support for the front button and LEDs on -+ the Cisco Meraki MX100 (Tinkerbell) 1U appliance. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called meraki-mx100. -+ - config EEEPC_LAPTOP - tristate "Eee PC Hotkey Driver" - depends on ACPI ---- a/drivers/platform/x86/Makefile -+++ b/drivers/platform/x86/Makefile -@@ -33,6 +33,9 @@ obj-$(CONFIG_ASUS_NB_WMI) += asus-nb-wmi - obj-$(CONFIG_EEEPC_LAPTOP) += eeepc-laptop.o - obj-$(CONFIG_EEEPC_WMI) += eeepc-wmi.o - -+# Cisco/Meraki -+obj-$(CONFIG_MERAKI_MX100) += meraki-mx100.o -+ - # Dell - obj-$(CONFIG_DCDBAS) += dcdbas.o - obj-$(CONFIG_DELL_SMBIOS) += dell-smbios.o ---- /dev/null -+++ b/drivers/platform/x86/meraki-mx100.c -@@ -0,0 +1,230 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+/* -+ * Cisco Meraki MX100 (Tinkerbell) board platform driver -+ * -+ * Based off of arch/x86/platform/meraki/tink.c from the -+ * Meraki GPL release meraki-firmware-sources-r23-20150601 -+ * -+ * Format inspired by platform/x86/pcengines-apuv2.c -+ * -+ * Copyright (C) 2021 Chris Blake -+ */ -+ -+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TINK_GPIO_DRIVER_NAME "gpio_ich" -+ -+/* LEDs */ -+static const struct gpio_led tink_leds[] = { -+ { -+ .name = "mx100:green:internet", -+ .default_trigger = "default-on", -+ }, -+ { -+ .name = "mx100:green:lan2", -+ }, -+ { -+ .name = "mx100:green:lan3", -+ }, -+ { -+ .name = "mx100:green:lan4", -+ }, -+ { -+ .name = "mx100:green:lan5", -+ }, -+ { -+ .name = "mx100:green:lan6", -+ }, -+ { -+ .name = "mx100:green:lan7", -+ }, -+ { -+ .name = "mx100:green:lan8", -+ }, -+ { -+ .name = "mx100:green:lan9", -+ }, -+ { -+ .name = "mx100:green:lan10", -+ }, -+ { -+ .name = "mx100:green:lan11", -+ }, -+ { -+ .name = "mx100:green:ha", -+ }, -+ { -+ .name = "mx100:orange:ha", -+ }, -+ { -+ .name = "mx100:green:usb", -+ }, -+ { -+ .name = "mx100:orange:usb", -+ }, -+}; -+ -+static const struct gpio_led_platform_data tink_leds_pdata = { -+ .num_leds = ARRAY_SIZE(tink_leds), -+ .leds = tink_leds, -+}; -+ -+static struct gpiod_lookup_table tink_leds_table = { -+ .dev_id = "leds-gpio", -+ .table = { -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 11, -+ NULL, 0, GPIO_ACTIVE_LOW), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 18, -+ NULL, 1, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 20, -+ NULL, 2, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 22, -+ NULL, 3, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 23, -+ NULL, 4, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 32, -+ NULL, 5, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 34, -+ NULL, 6, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 35, -+ NULL, 7, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 36, -+ NULL, 8, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 37, -+ NULL, 9, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 48, -+ NULL, 10, GPIO_ACTIVE_HIGH), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 16, -+ NULL, 11, GPIO_ACTIVE_LOW), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 7, -+ NULL, 12, GPIO_ACTIVE_LOW), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 21, -+ NULL, 13, GPIO_ACTIVE_LOW), -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 19, -+ NULL, 14, GPIO_ACTIVE_LOW), -+ {} /* Terminating entry */ -+ } -+}; -+ -+/* Reset Button */ -+static struct gpio_keys_button tink_buttons[] = { -+ { -+ .desc = "Reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .active_low = 1, -+ .debounce_interval = 100, -+ }, -+}; -+ -+static const struct gpio_keys_platform_data tink_buttons_pdata = { -+ .buttons = tink_buttons, -+ .nbuttons = ARRAY_SIZE(tink_buttons), -+ .poll_interval = 20, -+ .rep = 0, -+ .name = "mx100-keys", -+}; -+ -+static struct gpiod_lookup_table tink_keys_table = { -+ .dev_id = "gpio-keys-polled", -+ .table = { -+ GPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 60, -+ NULL, 0, GPIO_ACTIVE_LOW), -+ {} /* Terminating entry */ -+ } -+}; -+ -+/* Board setup */ -+static const struct dmi_system_id tink_systems[] __initconst = { -+ { -+ .matches = { -+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Cisco"), -+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "MX100-HW"), -+ }, -+ }, -+ {} /* Terminating entry */ -+}; -+MODULE_DEVICE_TABLE(dmi, tink_systems); -+ -+static struct platform_device *tink_leds_pdev; -+static struct platform_device *tink_keys_pdev; -+ -+static struct platform_device * __init tink_create_dev( -+ const char *name, const void *pdata, size_t sz) -+{ -+ struct platform_device *pdev; -+ -+ pdev = platform_device_register_data(NULL, -+ name, PLATFORM_DEVID_NONE, pdata, sz); -+ if (IS_ERR(pdev)) -+ pr_err("failed registering %s: %ld\n", name, PTR_ERR(pdev)); -+ -+ return pdev; -+} -+ -+static int __init tink_board_init(void) -+{ -+ int ret; -+ -+ if (!dmi_first_match(tink_systems)) -+ return -ENODEV; -+ -+ /* -+ * We need to make sure that GPIO60 isn't set to native mode as is default since it's our -+ * Reset Button. To do this, write to GPIO_USE_SEL2 to have GPIO60 set to GPIO mode. -+ * This is documented on page 1609 of the PCH datasheet, order number 327879-005US -+ */ -+ outl(inl(0x530) | BIT(28), 0x530); -+ -+ gpiod_add_lookup_table(&tink_leds_table); -+ gpiod_add_lookup_table(&tink_keys_table); -+ -+ tink_leds_pdev = tink_create_dev("leds-gpio", -+ &tink_leds_pdata, sizeof(tink_leds_pdata)); -+ if (IS_ERR(tink_leds_pdev)) { -+ ret = PTR_ERR(tink_leds_pdev); -+ goto err; -+ } -+ -+ tink_keys_pdev = tink_create_dev("gpio-keys-polled", -+ &tink_buttons_pdata, sizeof(tink_buttons_pdata)); -+ if (IS_ERR(tink_keys_pdev)) { -+ ret = PTR_ERR(tink_keys_pdev); -+ platform_device_unregister(tink_leds_pdev); -+ goto err; -+ } -+ -+ return 0; -+ -+err: -+ gpiod_remove_lookup_table(&tink_keys_table); -+ gpiod_remove_lookup_table(&tink_leds_table); -+ return ret; -+} -+module_init(tink_board_init); -+ -+static void __exit tink_board_exit(void) -+{ -+ platform_device_unregister(tink_keys_pdev); -+ platform_device_unregister(tink_leds_pdev); -+ gpiod_remove_lookup_table(&tink_keys_table); -+ gpiod_remove_lookup_table(&tink_leds_table); -+} -+module_exit(tink_board_exit); -+ -+MODULE_AUTHOR("Chris Blake "); -+MODULE_DESCRIPTION("Cisco Meraki MX100 Platform Driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:meraki-mx100"); diff --git a/target/linux/x86/patches-5.10/113-v5.21-platform-x86-pmc_atom-Add-Lex-3I380NX-industrial-PC-.patch b/target/linux/x86/patches-5.10/113-v5.21-platform-x86-pmc_atom-Add-Lex-3I380NX-industrial-PC-.patch deleted file mode 100644 index 1be5c62424..0000000000 --- a/target/linux/x86/patches-5.10/113-v5.21-platform-x86-pmc_atom-Add-Lex-3I380NX-industrial-PC-.patch +++ /dev/null @@ -1,52 +0,0 @@ -From: Hans de Goede -Date: Thu, 28 Jul 2022 20:06:35 +0200 -Subject: platform/x86: pmc_atom: Match all Lex BayTrail boards with - critclk_systems DMI table - -The critclk_systems[] DMI match table already contains 2 Lex BayTrail -boards and patches were just submitted to add 3 more entries for the -following models: 3I380NX, 3I380A, 3I380CW. - -Looking at: https://www.lex.com.tw/products/embedded-ipc-board/ -we can see that Lex BayTrail makes many embedded boards with -multiple ethernet boards and none of their products are battery -powered so we don't need to worry (too much) about power consumption -when suspended. - -Add a new DMI match which simply matches all Lex BayTrail boards and drop -the 2 existing board specific quirks. - -Reported-by: Michael Schöne -Reported-by: Paul Spooren -Reported-by: Matwey V. Kornilov -Signed-off-by: Hans de Goede ---- ---- a/drivers/platform/x86/pmc_atom.c -+++ b/drivers/platform/x86/pmc_atom.c -@@ -376,19 +376,15 @@ static const struct dmi_system_id critcl - }, - }, - { -- /* pmc_plt_clk0 - 3 are used for the 4 ethernet controllers */ -- .ident = "Lex 3I380D", -+ /* -+ * Lex System / Lex Computech Co. makes a lot of Bay Trail -+ * based embedded boards which often come with multiple -+ * ethernet controllers using multiple pmc_plt_clks. See: -+ * https://www.lex.com.tw/products/embedded-ipc-board/ -+ */ -+ .ident = "Lex BayTrail", - .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"), -- DMI_MATCH(DMI_PRODUCT_NAME, "3I380D"), -- }, -- }, -- { -- /* pmc_plt_clk* - are used for ethernet controllers */ -- .ident = "Lex 2I385SW", -- .matches = { -- DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"), -- DMI_MATCH(DMI_PRODUCT_NAME, "2I385SW"), - }, - }, - { diff --git a/target/linux/x86/patches-5.10/300-pcengines_apu1_led.patch b/target/linux/x86/patches-5.10/300-pcengines_apu1_led.patch deleted file mode 100644 index 9d1e4ab9c2..0000000000 --- a/target/linux/x86/patches-5.10/300-pcengines_apu1_led.patch +++ /dev/null @@ -1,41 +0,0 @@ -From: Andreas Eberlein -Subject: x86: add LED support for PC Engines APU1 with mainline bios - -This adds support for the LEDs on PC Engines APU1 with the mainline bios. - -Signed-off-by: Andreas Eberlein ---- ---- a/drivers/leds/leds-apu.c -+++ b/drivers/leds/leds-apu.c -@@ -83,6 +83,7 @@ static const struct apu_led_profile apu1 - }; - - static const struct dmi_system_id apu_led_dmi_table[] __initconst = { -+ /* PC Engines APU with "Legacy" bios < 4.0.8 */ - { - .ident = "apu", - .matches = { -@@ -90,6 +91,14 @@ static const struct dmi_system_id apu_le - DMI_MATCH(DMI_PRODUCT_NAME, "APU") - } - }, -+ /* PC Engines APU with "Mainline" bios >= 4.0.8 */ -+ { -+ .ident = "apu", -+ .matches = { -+ DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"), -+ DMI_MATCH(DMI_PRODUCT_NAME, "apu1") -+ } -+ }, - {} - }; - MODULE_DEVICE_TABLE(dmi, apu_led_dmi_table); -@@ -173,7 +182,7 @@ static int __init apu_led_init(void) - int err; - - if (!(dmi_match(DMI_SYS_VENDOR, "PC Engines") && -- dmi_match(DMI_PRODUCT_NAME, "APU"))) { -+ (dmi_match(DMI_PRODUCT_NAME, "APU") || dmi_match(DMI_PRODUCT_NAME, "apu1")))) { - pr_err("No PC Engines APUv1 board detected. For APUv2,3 support, enable CONFIG_PCENGINES_APU2\n"); - return -ENODEV; - }