From: Lars-Peter Clausen Date: Wed, 4 Aug 2010 13:33:55 +0000 (+0000) Subject: Drop 2.6.32 patches X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=1980190a5a96fba4d36be8f8037ba9925c263b57;p=openwrt%2Fstaging%2Fldir.git Drop 2.6.32 patches SVN-Revision: 22485 --- diff --git a/target/linux/xburst/config-2.6.32 b/target/linux/xburst/config-2.6.32 deleted file mode 100644 index bf119e4663..0000000000 --- a/target/linux/xburst/config-2.6.32 +++ /dev/null @@ -1,376 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -# CONFIG_ALCHEMY_GPIO_INDIRECT is not set -# CONFIG_AR7 is not set -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_ARCH_REQUIRE_GPIOLIB=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_ARPD is not set -# CONFIG_BACKLIGHT_CLASS_DEVICE is not set -# CONFIG_BACKLIGHT_GENERIC is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set -# CONFIG_BATTERY_JZ4740 is not set -# CONFIG_BCM47XX is not set -# CONFIG_BCM63XX is not set -CONFIG_BITREVERSE=y -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_BRIDGE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set -# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -CONFIG_CHARGER_GPIO=y -CONFIG_CONSOLE_TRANSLATIONS=y -# CONFIG_CPU_BIG_ENDIAN is not set -# CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_LITTLE_ENDIAN=y -# CONFIG_CPU_LOONGSON2E is not set -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR1=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -CONFIG_ELF_CORE=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_FAT_FS=y -# CONFIG_FB_JZ4740 is not set -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FONT_10x18 is not set -# CONFIG_FONT_6x11 is not set -# CONFIG_FONT_7x14 is not set -# CONFIG_FONT_8x16 is not set -# CONFIG_FONT_8x8 is not set -# CONFIG_FONT_ACORN_8x8 is not set -# CONFIG_FONT_MINI_4x6 is not set -# CONFIG_FONT_PEARL_8x8 is not set -# CONFIG_FONT_SUN12x22 is not set -CONFIG_FONT_SUN8x16=y -CONFIG_FONTS=y -CONFIG_FORCE_MAX_ZONEORDER=12 -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FRAMEBUFFER_CONSOLE is not set -CONFIG_FREEZER=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_GPIOLIB=y -# CONFIG_HAMRADIO is not set -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_HIBERNATION is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_HW_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_GPIO_BUTTONS is not set -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_MULTICAST is not set -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_RARP is not set -CONFIG_IP_PNP=y -CONFIG_IRQ_CPU=y -CONFIG_JBD=y -# CONFIG_JZ4740_ADC is not set -# CONFIG_JZ4740_N516 is not set -# CONFIG_JZ4740_N526 is not set -# CONFIG_JZ4740_QI_LB60 is not set -CONFIG_JZRISC=y -CONFIG_JZSOC=y -CONFIG_KALLSYMS=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_LCD_CLASS_DEVICE is not set -# CONFIG_LCD_GPM940B0 is not set -# CONFIG_LCD_ILI9320 is not set -# CONFIG_LCD_LMS283GF05 is not set -# CONFIG_LCD_LTV350QV is not set -# CONFIG_LCD_PLATFORM is not set -# CONFIG_LCD_TDO24M is not set -# CONFIG_LCD_VGG2432A4 is not set -CONFIG_LEGACY_PTY_COUNT=2 -CONFIG_LEGACY_PTYS=y -CONFIG_LOCK_KERNEL=y -# CONFIG_LOGO_LINUX_CLUT224 is not set -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_OPENWRT_CLUT224 is not set -# CONFIG_LOGO is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -CONFIG_MACH_JZ=y -# CONFIG_MACH_LOONGSON is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_MIKROTIK_RB532 is not set -# CONFIG_MINI_FO is not set -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MACHINE is not set -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SIM is not set -CONFIG_MIPS=y -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MMC_BLOCK_BOUNCE is not set -CONFIG_MMC_BLOCK=y -CONFIG_MMC_JZ=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_MMC=y -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_NAND_JZ4740=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI=y -# CONFIG_N516_LPC is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_SCHED is not set -# CONFIG_NETWORK_FILESYSTEMS is not set -# CONFIG_NEW_LEDS is not set -CONFIG_NLS_ASCII=y -CONFIG_NLS_CODEPAGE_1250=y -CONFIG_NLS_CODEPAGE_1251=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=y -CONFIG_NLS_CODEPAGE_775=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=y -CONFIG_NLS_CODEPAGE_855=y -CONFIG_NLS_CODEPAGE_857=y -CONFIG_NLS_CODEPAGE_860=y -CONFIG_NLS_CODEPAGE_861=y -CONFIG_NLS_CODEPAGE_862=y -CONFIG_NLS_CODEPAGE_863=y -CONFIG_NLS_CODEPAGE_864=y -CONFIG_NLS_CODEPAGE_865=y -CONFIG_NLS_CODEPAGE_866=y -CONFIG_NLS_CODEPAGE_869=y -CONFIG_NLS_CODEPAGE_874=y -CONFIG_NLS_CODEPAGE_932=y -CONFIG_NLS_CODEPAGE_936=y -CONFIG_NLS_CODEPAGE_949=y -CONFIG_NLS_CODEPAGE_950=y -CONFIG_NLS_ISO8859_13=y -CONFIG_NLS_ISO8859_14=y -CONFIG_NLS_ISO8859_15=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=y -CONFIG_NLS_ISO8859_3=y -CONFIG_NLS_ISO8859_4=y -CONFIG_NLS_ISO8859_5=y -CONFIG_NLS_ISO8859_6=y -CONFIG_NLS_ISO8859_7=y -CONFIG_NLS_ISO8859_8=y -CONFIG_NLS_ISO8859_9=y -CONFIG_NLS_KOI8_R=y -CONFIG_NLS_KOI8_U=y -CONFIG_NLS_UTF8=y -CONFIG_NLS=y -# CONFIG_NO_IOPORT is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -# CONFIG_PACKET_MMAP is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PCSPKR_PLATFORM=y -# CONFIG_PDA_POWER is not set -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PM_DEBUG is not set -# CONFIG_PM_RUNTIME is not set -CONFIG_PM_SLEEP=y -CONFIG_PM=y -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_POWER_SUPPLY_DEBUG is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT=y -CONFIG_PRINTK_TIME=y -CONFIG_RELAY=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RTC_DRV_JZ4740=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -# CONFIG_SCSI_DMA is not set -# CONFIG_SDIO_UART is not set -CONFIG_SECCOMP=y -# CONFIG_SERIAL_8250_EXTENDED is not set -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -CONFIG_SERIO_SERPORT=y -CONFIG_SERIO=y -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SND_SOC_ALL_CODECS is not set -# CONFIG_SND_SOC_JZCODEC is not set -# CONFIG_SND_SOC_JZ4740 is not set -# CONFIG_SND_JZ4740_SOC_N516 is not set -# CONFIG_SND_JZ4740_SOC_N526 is not set -# CONFIG_SND_JZ4740_SOC_QI_LB60 is not set -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SQUASHFS is not set -# CONFIG_STAGING is not set -CONFIG_SUSPEND_FREEZER=y -CONFIG_SUSPEND=y -# CONFIG_SYN_COOKIES is not set -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TRAD_SIGNALS=y -# CONFIG_TREE_PREEMPT_RCU is not set -CONFIG_TREE_RCU=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -# CONFIG_UBIFS_FS_DEBUG is not set -CONFIG_UBIFS_FS_LZO=y -# CONFIG_UBIFS_FS_XATTR is not set -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_AUDIO is not set -# CONFIG_USB_CDC_COMPOSITE is not set -# CONFIG_USB_ETH_EEM is not set -CONFIG_USB_ETH_RNDIS=y -CONFIG_USB_ETH=y -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_IMX is not set -CONFIG_USB_GADGET_JZ4740=y -# CONFIG_USB_GADGET_LANGWELL is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_R8A66597 is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_S3C_HSOTG is not set -CONFIG_USB_GADGET_SELECTED=y -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET=y -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_G_SERIAL is not set -CONFIG_USB_JZ4740=y -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_SUPPORT=y -# CONFIG_USB_ZERO is not set -CONFIG_VFAT_FS=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_VLAN_8021Q is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_VT=y -# CONFIG_WATCHDOG is not set -# CONFIG_WLAN_80211 is not set -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile deleted file mode 100644 index 90f36e63c4..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -# -# linux/arch/mips/boot/compressed/Makefile -# -# create a compressed zImage from the original vmlinux -# - -targets := zImage vmlinuz vmlinux.bin.gz head.o misc.o piggy.o dummy.o - -OBJS := $(obj)/head.o $(obj)/misc.o - -LD_ARGS := -T $(obj)/ld.script -Ttext 0x80600000 -Bstatic -OBJCOPY_ARGS := -O elf32-tradlittlemips - -ENTRY := $(obj)/../tools/entry -FILESIZE := $(obj)/../tools/filesize - -drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options -strip-flags = $(addprefix --remove-section=,$(drop-sections)) - - -$(obj)/vmlinux.bin.gz: vmlinux - rm -f $(obj)/vmlinux.bin.gz - $(OBJCOPY) -O binary $(strip-flags) vmlinux $(obj)/vmlinux.bin - gzip -v9f $(obj)/vmlinux.bin - -$(obj)/head.o: $(obj)/head.S $(obj)/vmlinux.bin.gz vmlinux - $(CC) $(KBUILD_AFLAGS) \ - -DIMAGESIZE=$(shell sh $(FILESIZE) $(obj)/vmlinux.bin.gz) \ - -DKERNEL_ENTRY=$(shell sh $(ENTRY) $(NM) vmlinux ) \ - -DLOADADDR=$(loadaddr) \ - -c -o $(obj)/head.o $< - -$(obj)/vmlinuz: $(OBJS) $(obj)/ld.script $(obj)/vmlinux.bin.gz $(obj)/dummy.o - $(OBJCOPY) \ - --add-section=.image=$(obj)/vmlinux.bin.gz \ - --set-section-flags=.image=contents,alloc,load,readonly,data \ - $(obj)/dummy.o $(obj)/piggy.o - $(LD) $(LD_ARGS) -o $@ $(OBJS) $(obj)/piggy.o - $(OBJCOPY) $(OBJCOPY_ARGS) $@ $@ -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap - -zImage: $(obj)/vmlinuz - $(OBJCOPY) -O binary $(obj)/vmlinuz $(obj)/zImage diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c deleted file mode 100644 index 31dbf45bf9..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/dummy.c +++ /dev/null @@ -1,4 +0,0 @@ -int main(void) -{ - return 0; -} diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S deleted file mode 100644 index d9700eb502..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S +++ /dev/null @@ -1,85 +0,0 @@ -/* - * linux/arch/mips/boot/compressed/head.S - * - * Copyright (C) 2005-2008 Ingenic Semiconductor Inc. - */ - -#include -#include -#include -#include - -#define IndexInvalidate_I 0x00 -#define IndexWriteBack_D 0x01 - - .set noreorder - LEAF(startup) -startup: - move s0, a0 /* Save the boot loader transfered args */ - move s1, a1 - move s2, a2 - move s3, a3 - - la a0, _edata - la a1, _end -1: sw zero, 0(a0) /* Clear BSS section */ - bne a1, a0, 1b - addu a0, 4 - - la sp, (.stack + 8192) - - la a0, __image_begin - la a1, IMAGESIZE - la a2, LOADADDR - la ra, 1f - la k0, decompress_kernel - jr k0 - nop -1: - - move a0, s0 - move a1, s1 - move a2, s2 - move a3, s3 - li k0, KERNEL_ENTRY - jr k0 - nop -2: - b 32 - END(startup) - - - LEAF(flushcaches) - la t0, 1f - la t1, 0xa0000000 - or t0, t0, t1 - jr t0 - nop -1: - li k0, 0x80000000 # start address - li k1, 0x80004000 # end address (16KB I-Cache) - subu k1, 128 - -2: - .set mips3 - cache IndexWriteBack_D, 0(k0) - cache IndexWriteBack_D, 32(k0) - cache IndexWriteBack_D, 64(k0) - cache IndexWriteBack_D, 96(k0) - cache IndexInvalidate_I, 0(k0) - cache IndexInvalidate_I, 32(k0) - cache IndexInvalidate_I, 64(k0) - cache IndexInvalidate_I, 96(k0) - .set mips0 - - bne k0, k1, 2b - addu k0, k0, 128 - la t0, 3f - jr t0 - nop -3: - jr ra - nop - END(flushcaches) - - .comm .stack,4096*2,4 diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script deleted file mode 100644 index fcf8ba0417..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/ld.script +++ /dev/null @@ -1,151 +0,0 @@ -OUTPUT_ARCH(mips) -ENTRY(startup) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - - .init : { *(.init) } =0 - .text : - { - _ftext = . ; - *(.text) - *(.rodata) - *(.rodata1) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - } =0 - .kstrtab : { *(.kstrtab) } - - . = ALIGN(16); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - __start___dbe_table = .; /* Exception table for data bus errors */ - __dbe_table : { *(__dbe_table) } - __stop___dbe_table = .; - - __start___ksymtab = .; /* Kernel symbol table */ - __ksymtab : { *(__ksymtab) } - __stop___ksymtab = .; - - _etext = .; - - . = ALIGN(8192); - .data.init_task : { *(.data.init_task) } - - /* Startup code */ - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(16); - __setup_start = .; - .setup.init : { *(.setup.init) } - __setup_end = .; - __initcall_start = .; - .initcall.init : { *(.initcall.init) } - __initcall_end = .; - . = ALIGN(4096); /* Align double page for init_task_union */ - __init_end = .; - - . = ALIGN(4096); - .data.page_aligned : { *(.data.idt) } - - . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - - .fini : { *(.fini) } =0 - .reginfo : { *(.reginfo) } - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. It would - be more correct to do this: - . = .; - The current expression does not correctly handle the case of a - text segment ending precisely at the end of a page; it causes the - data segment to skip a page. The above expression does not have - this problem, but it will currently (2/95) cause BFD to allocate - a single segment, combining both text and data, for this case. - This will prevent the text segment from being shared among - multiple executions of the program; I think that is more - important than losing a page of the virtual address space (note - that no actual memory is lost; the page which is skipped can not - be referenced). */ - . = .; - .data : - { - _fdata = . ; - *(.data) - - /* Put the compressed image here, so bss is on the end. */ - __image_begin = .; - *(.image) - __image_end = .; - /* Align the initial ramdisk image (INITRD) on page boundaries. */ - . = ALIGN(4096); - __ramdisk_begin = .; - *(.initrd) - __ramdisk_end = .; - . = ALIGN(4096); - - CONSTRUCTORS - } - .data1 : { *(.data1) } - _gp = . + 0x8000; - .lit8 : { *(.lit8) } - .lit4 : { *(.lit4) } - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - .got : { *(.got.plt) *(.got) } - .dynamic : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - . = ALIGN(4); - _edata = .; - PROVIDE (edata = .); - - __bss_start = .; - _fbss = .; - .sbss : { *(.sbss) *(.scommon) } - .bss : - { - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _end = . ; - PROVIDE (end = .); - } - - /* Sections to be discarded */ - /DISCARD/ : - { - *(.text.exit) - *(.data.exit) - *(.exitcall.exit) - } - - /* This is the MIPS specific mdebug section. */ - .mdebug : { *(.mdebug) } - /* These are needed for ELF backends which have not yet been - converted to the new style linker. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - /* DWARF debug sections. - Symbols in the .debug DWARF section are relative to the beginning of the - section so we begin .debug at 0. It's not clear yet what needs to happen - for the others. */ - .debug 0 : { *(.debug) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .line 0 : { *(.line) } - /* These must appear regardless of . */ - .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } - .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - .comment : { *(.comment) } - .note : { *(.note) } -} diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c deleted file mode 100644 index 2309feea36..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/misc.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * linux/arch/mips/boot/compressed/misc.c - * - * This is a collection of several routines from gzip-1.0.3 - * adapted for Linux. - * - * malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994 - * - * Adapted for JZSOC by Peter Wei, 2008 - * - */ - -#define size_t int -#define NULL 0 - -/* - * gzip declarations - */ - -#define OF(args) args -#define STATIC static - -#undef memset -#undef memcpy -#define memzero(s, n) memset ((s), 0, (n)) - -typedef unsigned char uch; -typedef unsigned short ush; -typedef unsigned long ulg; - -#define WSIZE 0x8000 /* Window size must be at least 32k, */ - /* and a power of two */ - -static uch *inbuf; /* input buffer */ -static uch window[WSIZE]; /* Sliding window buffer */ - -static unsigned insize = 0; /* valid bytes in inbuf */ -static unsigned inptr = 0; /* index of next byte to be processed in inbuf */ -static unsigned outcnt = 0; /* bytes in output buffer */ - -/* gzip flag byte */ -#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */ -#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */ -#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */ -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ -#define COMMENT 0x10 /* bit 4 set: file comment present */ -#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */ -#define RESERVED 0xC0 /* bit 6,7: reserved */ - -#define get_byte() (inptr < insize ? inbuf[inptr++] : fill_inbuf()) - -/* Diagnostic functions */ -#ifdef DEBUG -# define Assert(cond,msg) {if(!(cond)) error(msg);} -# define Trace(x) fprintf x -# define Tracev(x) {if (verbose) fprintf x ;} -# define Tracevv(x) {if (verbose>1) fprintf x ;} -# define Tracec(c,x) {if (verbose && (c)) fprintf x ;} -# define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;} -#else -# define Assert(cond,msg) -# define Trace(x) -# define Tracev(x) -# define Tracevv(x) -# define Tracec(c,x) -# define Tracecv(c,x) -#endif - -static int fill_inbuf(void); -static void flush_window(void); -static void error(char *m); -static void gzip_mark(void **); -static void gzip_release(void **); - -void* memset(void* s, int c, size_t n); -void* memcpy(void* __dest, __const void* __src, size_t __n); - -extern void flushcaches(void); /* defined in head.S */ - -char *input_data; -int input_len; - -static long bytes_out = 0; -static uch *output_data; -static unsigned long output_ptr = 0; - - -static void *malloc(int size); -static void free(void *where); -static void error(char *m); -static void gzip_mark(void **); -static void gzip_release(void **); - -static void puts(const char *str) -{ -} - -extern unsigned char _end[]; -static unsigned long free_mem_ptr; -static unsigned long free_mem_end_ptr; - -#define HEAP_SIZE 0x10000 - -#include "../../../../lib/inflate.c" - -static void *malloc(int size) -{ - void *p; - - if (size <0) error("Malloc error\n"); - if (free_mem_ptr == 0) error("Memory error\n"); - - free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */ - - p = (void *)free_mem_ptr; - free_mem_ptr += size; - - if (free_mem_ptr >= free_mem_end_ptr) - error("\nOut of memory\n"); - - return p; -} - -static void free(void *where) -{ /* Don't care */ -} - -static void gzip_mark(void **ptr) -{ - *ptr = (void *) free_mem_ptr; -} - -static void gzip_release(void **ptr) -{ - free_mem_ptr = (long) *ptr; -} - -void* memset(void* s, int c, size_t n) -{ - int i; - char *ss = (char*)s; - - for (i=0;i> 3; i > 0; i--) { - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - } - - if (__n & 1 << 2) { - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - } - - if (__n & 1 << 1) { - *d++ = *s++; - *d++ = *s++; - } - - if (__n & 1) - *d++ = *s++; - - return __dest; -} - -/* =========================================================================== - * Fill the input buffer. This is called only when the buffer is empty - * and at least one byte is really needed. - */ -static int fill_inbuf(void) -{ - if (insize != 0) { - error("ran out of input data\n"); - } - - inbuf = input_data; - insize = input_len; - inptr = 1; - return inbuf[0]; -} - -/* =========================================================================== - * Write the output window window[0..outcnt-1] and update crc and bytes_out. - * (Used for the decompressed data only.) - */ -static void flush_window(void) -{ - ulg c = crc; /* temporary variable */ - unsigned n; - uch *in, *out, ch; - - in = window; - out = &output_data[output_ptr]; - for (n = 0; n < outcnt; n++) { - ch = *out++ = *in++; - c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8); - } - crc = c; - bytes_out += (ulg)outcnt; - output_ptr += (ulg)outcnt; - outcnt = 0; -} - -static void error(char *x) -{ - puts("\n\n"); - puts(x); - puts("\n\n -- System halted"); - - while(1); /* Halt */ -} - -void decompress_kernel(unsigned int imageaddr, unsigned int imagesize, unsigned int loadaddr) -{ - input_data = (char *)imageaddr; - input_len = imagesize; - output_ptr = 0; - output_data = (uch *)loadaddr; - free_mem_ptr = (unsigned long)_end; - free_mem_end_ptr = free_mem_ptr + HEAP_SIZE; - - makecrc(); - puts("Uncompressing Linux..."); - gunzip(); - flushcaches(); - puts("Ok, booting the kernel."); -} diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry b/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry deleted file mode 100644 index 376e822a63..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/entry +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - -# grab the kernel_entry address from the vmlinux elf image -entry=`$1 $2 | grep kernel_entry` - -fs=`echo $entry | grep ffffffff` # check toolchain output - -if [ -n "$fs" ]; then - echo "0x"`$1 $2 | grep kernel_entry | cut -c9- | awk '{print $1}'` -else - echo "0x"`$1 $2 | grep kernel_entry | cut -c1- | awk '{print $1}'` -fi diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize b/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize deleted file mode 100644 index 2142ad5af9..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/boot/tools/filesize +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh -HOSTNAME=`uname` -if [ "$HOSTNAME" = "Linux" ]; then -echo `ls -l $1 | awk '{print $5}'` -else -echo `ls -l $1 | awk '{print $6}'` -fi diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-n516.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-n516.h deleted file mode 100644 index cbe6544778..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-n516.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * linux/include/asm-mips/mach-jz4740/board-n516.h - * - * JZ4730-based N516 board definition. - * - * Copyright (C) 2009, Yauhen Kharuzhy - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __ASM_JZ4740_N516_H__ -#define __ASM_JZ4740_N516_H__ - -#include - -/* - * GPIO - */ -#define GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(17) -#define GPIO_SD_CD_N JZ_GPIO_PORTD(7) -#define GPIO_SD_WP JZ_GPIO_PORTD(15) -#define GPIO_USB_DETECT JZ_GPIO_PORTD(19) -#define GPIO_CHARG_STAT_N JZ_GPIO_PORTD(16) -#define GPIO_LED_ENABLE JZ_GPIO_PORTD(28) -#define GPIO_LPC_INT JZ_GPIO_PORTD(14) -#define GPIO_HPHONE_DETECT JZ_GPIO_PORTD(20) -#define GPIO_SPEAKER_ENABLE JZ_GPIO_PORTD(21) - -/* Display */ -#define GPIO_DISPLAY_RST_L JZ_GPIO_PORTB(18) -#define GPIO_DISPLAY_RDY JZ_GPIO_PORTB(17) -#define GPIO_DISPLAY_STBY JZ_GPIO_PORTC(22) -#define GPIO_DISPLAY_ERR JZ_GPIO_PORTC(23) -#define GPIO_DISPLAY_OFF_N JZ_GPIO_PORTD(1) - -#endif /* __ASM_JZ4740_N516_H__ */ diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h deleted file mode 100644 index cfbf0733b2..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/board-qi_lb60.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2009 Qi Hardware Inc., - * Author: Xiangfu Liu - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __ASM_JZ4740_QI_LB60_H__ -#define __ASM_JZ4740_QI_LB60_H__ - -#include - -/* - * GPIO - */ -#define GPIO_DC_DETE_N JZ_GPIO_PORTC(26) -#define GPIO_CHARG_STAT_N JZ_GPIO_PORTC(27) -#define GPIO_LED_EN JZ_GPIO_PORTC(28) -#define GPIO_LCD_CS JZ_GPIO_PORTC(21) -#define GPIO_DISP_OFF_N JZ_GPIO_PORTD(21) -#define GPIO_PWM JZ_GPIO_PORTD(27) -#define GPIO_WAKEUP_N JZ_GPIO_PORTD(29) - -#define GPIO_AMP_EN JZ_GPIO_PORTD(4) - -#define GPIO_SD_CD_N JZ_GPIO_PORTD(0) -#define GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(2) - -#define GPIO_USB_DETE JZ_GPIO_PORTD(28) -#define GPIO_BUZZ_PWM JZ_GPIO_PORTD(27) -#define GPIO_UDC_HOTPLUG GPIO_USB_DETE - -#define GPIO_AUDIO_POP JZ_GPIO_PORTB(29) -#define GPIO_COB_TEST JZ_GPIO_PORTB(30) - -#define GPIO_KEYOUT_BASE JZ_GPIO_PORTC(10) -#define GPIO_KEYIN_BASE JZ_GPIO_PORTD(18) -#define GPIO_KEYIN_8 JZ_GPIO_PORTD(26) - -#endif /* __ASM_JZ4740_QI_LB60_H__ */ diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h deleted file mode 100644 index 1f8e53b25a..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/clock.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * linux/include/asm-mips/mach-jz4740/clock.h - * - * JZ4740 clocks definition. - * - * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. - * - * Author: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_JZ4740_CLOCK_H__ -#define __ASM_JZ4740_CLOCK_H__ - -#include - -enum jz4740_wait_mode -{ - JZ4740_WAIT_MODE_IDLE, - JZ4740_WAIT_MODE_SLEEP, -}; - -void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode); - -void jz4740_clock_udc_enable_auto_suspend(void); -void jz4740_clock_udc_disable_auto_suspend(void); - -#endif /* __ASM_JZ4740_CLOCK_H__ */ diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h deleted file mode 100644 index e7f474e4c5..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/dma.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen - * JZ7420/JZ4740 DMA definitions - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __ASM_MACH_JZ4740_DMA_H__ -#define __ASM_MACH_JZ4740_DMA_H__ - -struct jz4740_dma_chan; - -enum jz4740_dma_request_type { - JZ4740_DMA_TYPE_AUTO_REQUEST = 8, - JZ4740_DMA_TYPE_UART_TRANSMIT = 20, - JZ4740_DMA_TYPE_UART_RECEIVE = 21, - JZ4740_DMA_TYPE_SPI_TRANSMIT = 22, - JZ4740_DMA_TYPE_SPI_RECEIVE = 23, - JZ4740_DMA_TYPE_AIC_TRANSMIT = 24, - JZ4740_DMA_TYPE_AIC_RECEIVE = 25, - JZ4740_DMA_TYPE_MMC_TRANSMIT = 26, - JZ4740_DMA_TYPE_MMC_RECEIVE = 27, - JZ4740_DMA_TYPE_TCU = 28, - JZ4740_DMA_TYPE_SADC = 29, - JZ4740_DMA_TYPE_SLCD = 30, -}; - -enum jz4740_dma_width { - JZ4740_DMA_WIDTH_8BIT, - JZ4740_DMA_WIDTH_16BIT, - JZ4740_DMA_WIDTH_32BIT, -}; - -enum jz4740_dma_transfer_size { - JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0, - JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1, - JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2, - JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3, - JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4, -}; - -enum jz4740_dma_flags { - JZ4740_DMA_SRC_AUTOINC = 0x2, - JZ4740_DMA_DST_AUTOINC = 0x1, -}; - -enum jz4740_dma_mode { - JZ4740_DMA_MODE_SINGLE = 0, - JZ4740_DMA_MODE_BLOCK = 1, -}; - -struct jz4740_dma_config { - enum jz4740_dma_width src_width; - enum jz4740_dma_width dst_width; - enum jz4740_dma_transfer_size transfer_size; - enum jz4740_dma_request_type request_type; - enum jz4740_dma_flags flags; - enum jz4740_dma_mode mode; -}; - -typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int , void *); - -struct jz4740_dma_chan* jz4740_dma_request(void *dev, const char *name); -void jz4740_dma_free(struct jz4740_dma_chan *dma); - -void jz4740_dma_configure(struct jz4740_dma_chan *dma, - const struct jz4740_dma_config *config); - - -void jz4740_dma_enable(struct jz4740_dma_chan *dma); -void jz4740_dma_disable(struct jz4740_dma_chan *dma); - -void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src); -void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst); -void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count); - -uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma); - -void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma, - jz4740_dma_complete_callback_t cb); - -#endif /* __ASM_JZ4740_DMA_H__ */ diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h deleted file mode 100644 index 99206dd7b4..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/gpio.h +++ /dev/null @@ -1,393 +0,0 @@ -/* - * Copyright (C) 2009, Lars-Peter Clausen - * JZ7420/JZ4740 GPIO pin definitions - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef _JZ_GPIO_H -#define _JZ_GPIO_H - -#include - -enum jz_gpio_function { - JZ_GPIO_FUNC_NONE, - JZ_GPIO_FUNC1, - JZ_GPIO_FUNC2, - JZ_GPIO_FUNC3, -}; - - -/* - Usually a driver for a SoC component has to request several gpio pins and - configure them as funcion pins. - jz_gpio_bulk_request can be used to ease this process. - Usually one would do something like: - - const static struct jz_gpio_bulk_request i2c_pins[] = { - JZ_GPIO_BULK_PIN(I2C_SDA), - JZ_GPIO_BULK_PIN(I2C_SCK), - }; - - inside the probe function: - - ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins)); - if (ret) { - ... - - inside the remove function: - - jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins)); - - -*/ -struct jz_gpio_bulk_request { - int gpio; - const char *name; - enum jz_gpio_function function; -}; - -#define JZ_GPIO_BULK_PIN(pin) { \ - .gpio = JZ_GPIO_ ## pin, \ - .name = #pin, \ - .function = JZ_GPIO_FUNC_ ## pin \ -} - -int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num); -void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num); -void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num); -void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num); -void jz_gpio_enable_pullup(unsigned gpio); -void jz_gpio_disable_pullup(unsigned gpio); -int jz_gpio_set_function(int gpio, enum jz_gpio_function function); - -int jz_gpio_port_direction_input(int port, uint32_t mask); -int jz_gpio_port_direction_output(int port, uint32_t mask); -void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask); -uint32_t jz_gpio_port_get_value(int port, uint32_t mask); - -#include - -#define JZ_GPIO_PORTA(x) ((x) + 32 * 0) -#define JZ_GPIO_PORTB(x) ((x) + 32 * 1) -#define JZ_GPIO_PORTC(x) ((x) + 32 * 2) -#define JZ_GPIO_PORTD(x) ((x) + 32 * 3) - -/* Port A function pins */ -#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0) -#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1) -#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2) -#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3) -#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4) -#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5) -#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6) -#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7) -#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8) -#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9) -#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10) -#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11) -#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12) -#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13) -#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14) -#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15) -#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16) -#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17) -#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18) -#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19) -#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20) -#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21) -#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22) -#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23) -#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24) -#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25) -#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26) -#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27) -#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28) -#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29) -#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30) -#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31) - -#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1 - -/* Port B function pins */ -#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0) -#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1) -#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2) -#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3) -#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4) -#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5) -#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6) -#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7) -#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8) -#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9) -#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10) -#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11) -#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12) -#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13) -#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14) -#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15) -#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16) -#define JZ_GPIO_MEM_CLS JZ_GPIO_PORTB(17) -#define JZ_GPIO_MEM_SPL JZ_GPIO_PORTB(18) -#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19) -#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20) -#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21) -#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22) -#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23) -#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24) -#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25) -#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26) -#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27) -#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28) -#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29) -#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30) -#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31) - -#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CLS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_SPL JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1 - - -#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17) -#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18) - -#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2 - -/* Port C function pins */ -#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0) -#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1) -#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2) -#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3) -#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4) -#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5) -#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6) -#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7) -#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8) -#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9) -#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10) -#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11) -#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12) -#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13) -#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14) -#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15) -#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16) -#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17) -#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18) -#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19) -#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20) -#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21) -#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22) -#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23) -#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24) -#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25) -#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26) -#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27) -#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28) -#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29) - -#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1 - - -#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22) -#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23) - -#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2 - -/* Port D function pins */ -#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0) -#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1) -#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2) -#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3) -#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4) -#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5) -#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6) -#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7) -#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8) -#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9) -#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10) -#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11) -#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12) -#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13) -#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14) -#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15) -#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16) -#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17) -#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18) -#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19) -#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20) -#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21) -#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22) -#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23) -#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24) -#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25) -#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26) -#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27) -#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28) -#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30) -#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31) - -#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC1 - -#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18) -#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19) -#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20) -#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21) -#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22) -#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23) -#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24) -#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25) -#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26) -#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27) -#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28) -#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30) -#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31) - -#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2 - -#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30) -#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31) - -#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3 -#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3 - -#endif diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h deleted file mode 100644 index 59f0ea51a6..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/irq.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2009-2010, Lars-Peter Clausen - * JZ7420/JZ4740 IRQ definitions - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __ASM_MACH_JZ4740_IRQ_H__ -#define __ASM_MACH_JZ4740_IRQ_H__ - -#define MIPS_CPU_IRQ_BASE 0 -#define JZ_IRQ_BASE 8 - -/* 1st-level interrupts */ -#define JZ_IRQ(x) (JZ_IRQ_BASE + (x)) -#define JZ_IRQ_I2C JZ_IRQ(1) -#define JZ_IRQ_UHC JZ_IRQ(3) -#define JZ_IRQ_UART1 JZ_IRQ(8) -#define JZ_IRQ_UART0 JZ_IRQ(9) -#define JZ_IRQ_SADC JZ_IRQ(12) -#define JZ_IRQ_MSC JZ_IRQ(14) -#define JZ_IRQ_RTC JZ_IRQ(15) -#define JZ_IRQ_SSI JZ_IRQ(16) -#define JZ_IRQ_CIM JZ_IRQ(17) -#define JZ_IRQ_AIC JZ_IRQ(18) -#define JZ_IRQ_ETH JZ_IRQ(19) -#define JZ_IRQ_DMAC JZ_IRQ(20) -#define JZ_IRQ_TCU2 JZ_IRQ(21) -#define JZ_IRQ_TCU1 JZ_IRQ(22) -#define JZ_IRQ_TCU0 JZ_IRQ(23) -#define JZ_IRQ_UDC JZ_IRQ(24) -#define JZ_IRQ_GPIO3 JZ_IRQ(25) -#define JZ_IRQ_GPIO2 JZ_IRQ(26) -#define JZ_IRQ_GPIO1 JZ_IRQ(27) -#define JZ_IRQ_GPIO0 JZ_IRQ(28) -#define JZ_IRQ_IPU JZ_IRQ(29) -#define JZ_IRQ_LCD JZ_IRQ(30) - -/* 2nd-level interrupts */ -#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */ - -#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x)) -#define JZ_IRQ_GPIO(x) (JZ_IRQ(48) + (x)) - -#define NR_IRQS (JZ_IRQ_GPIO(127) + 1) - -#endif diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h deleted file mode 100644 index 9885db2430..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/jz4740.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * linux/include/asm-mips/mach-jz4740/jz4740.h - * - * JZ4740 common definition. - * - * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. - * - * Author: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_JZ4740_H__ -#define __ASM_JZ4740_H__ - -#include -#include - -/*------------------------------------------------------------------ - * Platform definitions - */ - -#ifdef CONFIG_JZ4740_QI_LB60 -#include -#endif - -/*------------------------------------------------------------------ - * Follows are related to platform definitions - */ - -#include - -#endif /* __ASM_JZ4740_H__ */ diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h deleted file mode 100644 index 42de1c13ad..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/platform.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2009, Lars-Peter Clausen - * JZ7420/JZ4740 platform device definitions - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - - -#ifndef __JZ4740_PLATFORM_H -#define __JZ4740_PLATFORM_H - -#include - -extern struct platform_device jz4740_usb_ohci_device; -extern struct platform_device jz4740_usb_gdt_device; -extern struct platform_device jz4740_mmc_device; -extern struct platform_device jz4740_rtc_device; -extern struct platform_device jz4740_i2c_device; -extern struct platform_device jz4740_nand_device; -extern struct platform_device jz4740_framebuffer_device; -extern struct platform_device jz4740_i2s_device; -extern struct platform_device jz4740_codec_device; -extern struct platform_device jz4740_adc_device; -extern struct platform_device jz4740_battery_device; - -#endif diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h deleted file mode 100644 index 2ea90ca062..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/regs.h +++ /dev/null @@ -1,519 +0,0 @@ -/* - * linux/include/asm-mips/mach-jz4740/regs.h - * - * Ingenic's JZ4740 common include. - * - * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. - * - * Author: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __JZ4740_REGS_H__ -#define __JZ4740_REGS_H__ - -#if defined(__ASSEMBLY__) || defined(__LANGUAGE_ASSEMBLY) -#define REG8(addr) (addr) -#define REG16(addr) (addr) -#define REG32(addr) (addr) -#else -#define REG8(addr) *((volatile unsigned char *)(addr)) -#define REG16(addr) *((volatile unsigned short *)(addr)) -#define REG32(addr) *((volatile unsigned int *)(addr)) -#endif - -/* - * Define the module base addresses - */ -#define CPM_BASE 0xB0000000 -#define INTC_BASE 0xB0001000 -#define TCU_BASE 0xB0002000 -#define WDT_BASE 0xB0002000 -#define RTC_BASE 0xB0003000 -#define GPIO_BASE 0xB0010000 -#define AIC_BASE 0xB0020000 -#define ICDC_BASE 0xB0020000 -#define MSC_BASE 0xB0021000 -#define UART0_BASE 0xB0030000 -#define UART1_BASE 0xB0031000 -#define I2C_BASE 0xB0042000 -#define SSI_BASE 0xB0043000 -#define SADC_BASE 0xB0070000 -#define EMC_BASE 0xB3010000 -#define DMAC_BASE 0xB3020000 -#define UHC_BASE 0xB3030000 -#define UDC_BASE 0xB3040000 -#define LCD_BASE 0xB3050000 -#define SLCD_BASE 0xB3050000 -#define CIM_BASE 0xB3060000 -#define IPU_BASE 0xB3080000 -#define ETH_BASE 0xB3100000 - -/************************************************************************* - * UART - *************************************************************************/ - -#define IRDA_BASE UART0_BASE -#define UART_BASE UART0_BASE -#define UART_OFF 0x1000 - -/* Register Offset */ -#define OFF_RDR (0x00) /* R 8b H'xx */ -#define OFF_TDR (0x00) /* W 8b H'xx */ -#define OFF_DLLR (0x00) /* RW 8b H'00 */ -#define OFF_DLHR (0x04) /* RW 8b H'00 */ -#define OFF_IER (0x04) /* RW 8b H'00 */ -#define OFF_ISR (0x08) /* R 8b H'01 */ -#define OFF_FCR (0x08) /* W 8b H'00 */ -#define OFF_LCR (0x0C) /* RW 8b H'00 */ -#define OFF_MCR (0x10) /* RW 8b H'00 */ -#define OFF_LSR (0x14) /* R 8b H'00 */ -#define OFF_MSR (0x18) /* R 8b H'00 */ -#define OFF_SPR (0x1C) /* RW 8b H'00 */ -#define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */ -#define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */ -#define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */ - -/* Register Address */ -#define UART0_RDR (UART0_BASE + OFF_RDR) -#define UART0_TDR (UART0_BASE + OFF_TDR) -#define UART0_DLLR (UART0_BASE + OFF_DLLR) -#define UART0_DLHR (UART0_BASE + OFF_DLHR) -#define UART0_IER (UART0_BASE + OFF_IER) -#define UART0_ISR (UART0_BASE + OFF_ISR) -#define UART0_FCR (UART0_BASE + OFF_FCR) -#define UART0_LCR (UART0_BASE + OFF_LCR) -#define UART0_MCR (UART0_BASE + OFF_MCR) -#define UART0_LSR (UART0_BASE + OFF_LSR) -#define UART0_MSR (UART0_BASE + OFF_MSR) -#define UART0_SPR (UART0_BASE + OFF_SPR) -#define UART0_SIRCR (UART0_BASE + OFF_SIRCR) -#define UART0_UMR (UART0_BASE + OFF_UMR) -#define UART0_UACR (UART0_BASE + OFF_UACR) - -/* - * Define macros for UARTIER - * UART Interrupt Enable Register - */ -#define UARTIER_RIE (1 << 0) /* 0: receive fifo full interrupt disable */ -#define UARTIER_TIE (1 << 1) /* 0: transmit fifo empty interrupt disable */ -#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */ -#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */ -#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */ - -/* - * Define macros for UARTISR - * UART Interrupt Status Register - */ -#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */ -#define UARTISR_IID (7 << 1) /* Source of Interrupt */ -#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */ -#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */ -#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */ -#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */ -#define UARTISR_IID_RTO (6 << 1) /* Receive timeout */ -#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */ -#define UARTISR_FFMS_NO_FIFO (0 << 6) -#define UARTISR_FFMS_FIFO_MODE (3 << 6) - -/* - * Define macros for UARTFCR - * UART FIFO Control Register - */ -#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */ -#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */ -#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */ -#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */ -#define UARTFCR_UUE (1 << 4) /* 0: disable UART */ -#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */ -#define UARTFCR_RTRG_1 (0 << 6) -#define UARTFCR_RTRG_4 (1 << 6) -#define UARTFCR_RTRG_8 (2 << 6) -#define UARTFCR_RTRG_15 (3 << 6) - -/* - * Define macros for UARTLCR - * UART Line Control Register - */ -#define UARTLCR_WLEN (3 << 0) /* word length */ -#define UARTLCR_WLEN_5 (0 << 0) -#define UARTLCR_WLEN_6 (1 << 0) -#define UARTLCR_WLEN_7 (2 << 0) -#define UARTLCR_WLEN_8 (3 << 0) -#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8 - 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ -#define UARTLCR_STOP1 (0 << 2) -#define UARTLCR_STOP2 (1 << 2) -#define UARTLCR_PE (1 << 3) /* 0: parity disable */ -#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */ -#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */ -#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */ -#define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */ - -/* - * Define macros for UARTLSR - * UART Line Status Register - */ -#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */ -#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */ -#define UARTLSR_PER (1 << 2) /* 0: no parity error */ -#define UARTLSR_FER (1 << 3) /* 0; no framing error */ -#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */ -#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */ -#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */ -#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */ - -/* - * Define macros for UARTMCR - * UART Modem Control Register - */ -#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high, 1: RTS_ output low */ -#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */ -#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */ - -/* - * Define macros for UARTMSR - * UART Modem Status Register - */ -#define UARTMSR_CCTS (1 << 0) /* 1: a change on CTS_ pin */ -#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */ - -/* - * Define macros for SIRCR - * Slow IrDA Control Register - */ -#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: SIR mode */ -#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: SIR mode */ -#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length - 1: 0 pulse width is 1.6us for 115.2Kbps */ -#define SIRCR_TDPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */ -#define SIRCR_RDPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */ - - -/************************************************************************* - * EMC (External Memory Controller) - *************************************************************************/ -#define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */ -#define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */ -#define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */ -#define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */ -#define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */ -#define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */ -#define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */ -#define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */ -#define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */ -#define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */ - -#define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */ -#define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */ -#define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */ -#define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */ -#define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */ -#define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */ -#define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */ -#define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */ -#define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */ -#define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */ -#define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */ -#define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */ - -#define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */ -#define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */ -#define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */ -#define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */ -#define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */ -#define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */ - - -#define REG_EMC_SMCR0 REG32(EMC_SMCR0) -#define REG_EMC_SMCR1 REG32(EMC_SMCR1) -#define REG_EMC_SMCR2 REG32(EMC_SMCR2) -#define REG_EMC_SMCR3 REG32(EMC_SMCR3) -#define REG_EMC_SMCR4 REG32(EMC_SMCR4) -#define REG_EMC_SACR0 REG32(EMC_SACR0) -#define REG_EMC_SACR1 REG32(EMC_SACR1) -#define REG_EMC_SACR2 REG32(EMC_SACR2) -#define REG_EMC_SACR3 REG32(EMC_SACR3) -#define REG_EMC_SACR4 REG32(EMC_SACR4) - -#define REG_EMC_NFCSR REG32(EMC_NFCSR) -#define REG_EMC_NFECR REG32(EMC_NFECR) -#define REG_EMC_NFECC REG32(EMC_NFECC) -#define REG_EMC_NFPAR0 REG32(EMC_NFPAR0) -#define REG_EMC_NFPAR1 REG32(EMC_NFPAR1) -#define REG_EMC_NFPAR2 REG32(EMC_NFPAR2) -#define REG_EMC_NFINTS REG32(EMC_NFINTS) -#define REG_EMC_NFINTE REG32(EMC_NFINTE) -#define REG_EMC_NFERR0 REG32(EMC_NFERR0) -#define REG_EMC_NFERR1 REG32(EMC_NFERR1) -#define REG_EMC_NFERR2 REG32(EMC_NFERR2) -#define REG_EMC_NFERR3 REG32(EMC_NFERR3) - -#define REG_EMC_DMCR REG32(EMC_DMCR) -#define REG_EMC_RTCSR REG16(EMC_RTCSR) -#define REG_EMC_RTCNT REG16(EMC_RTCNT) -#define REG_EMC_RTCOR REG16(EMC_RTCOR) -#define REG_EMC_DMAR0 REG32(EMC_DMAR0) - -/* Static Memory Control Register */ -#define EMC_SMCR_STRV_BIT 24 -#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) -#define EMC_SMCR_TAW_BIT 20 -#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) -#define EMC_SMCR_TBP_BIT 16 -#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) -#define EMC_SMCR_TAH_BIT 12 -#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) -#define EMC_SMCR_TAS_BIT 8 -#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) -#define EMC_SMCR_BW_BIT 6 -#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) - #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) -#define EMC_SMCR_BCM (1 << 3) -#define EMC_SMCR_BL_BIT 1 -#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) - #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) -#define EMC_SMCR_SMT (1 << 0) - -/* Static Memory Bank Addr Config Reg */ -#define EMC_SACR_BASE_BIT 8 -#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) -#define EMC_SACR_MASK_BIT 0 -#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) - -/* NAND Flash Control/Status Register */ -#define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */ -#define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */ -#define EMC_NFCSR_NFCE3 (1 << 5) -#define EMC_NFCSR_NFE3 (1 << 4) -#define EMC_NFCSR_NFCE2 (1 << 3) -#define EMC_NFCSR_NFE2 (1 << 2) -#define EMC_NFCSR_NFCE1 (1 << 1) -#define EMC_NFCSR_NFE1 (1 << 0) - -/* NAND Flash ECC Control Register */ -#define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */ -#define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */ -#define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */ -#define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */ -#define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */ -#define EMC_NFECR_ERST (1 << 1) /* ECC Reset */ -#define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */ - -/* NAND Flash ECC Data Register */ -#define EMC_NFECC_ECC2_BIT 16 -#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) -#define EMC_NFECC_ECC1_BIT 8 -#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) -#define EMC_NFECC_ECC0_BIT 0 -#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) - -/* NAND Flash Interrupt Status Register */ -#define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */ -#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) -#define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */ -#define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */ -#define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */ -#define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */ -#define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */ - -/* NAND Flash Interrupt Enable Register */ -#define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */ -#define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */ -#define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */ -#define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */ -#define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */ - -/* NAND Flash RS Error Report Register */ -#define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */ -#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) -#define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */ -#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) - - -/* DRAM Control Register */ -#define EMC_DMCR_BW_BIT 31 -#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) -#define EMC_DMCR_CA_BIT 26 -#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) - #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) -#define EMC_DMCR_RMODE (1 << 25) -#define EMC_DMCR_RFSH (1 << 24) -#define EMC_DMCR_MRSET (1 << 23) -#define EMC_DMCR_RA_BIT 20 -#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) - #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) -#define EMC_DMCR_BA_BIT 19 -#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) -#define EMC_DMCR_PDM (1 << 18) -#define EMC_DMCR_EPIN (1 << 17) -#define EMC_DMCR_TRAS_BIT 13 -#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) -#define EMC_DMCR_RCD_BIT 11 -#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) -#define EMC_DMCR_TPC_BIT 8 -#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) -#define EMC_DMCR_TRWL_BIT 5 -#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) -#define EMC_DMCR_TRC_BIT 2 -#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) -#define EMC_DMCR_TCL_BIT 0 -#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) - -/* Refresh Time Control/Status Register */ -#define EMC_RTCSR_CMF (1 << 7) -#define EMC_RTCSR_CKS_BIT 0 -#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) - #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) - -/* SDRAM Bank Address Configuration Register */ -#define EMC_DMAR_BASE_BIT 8 -#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) -#define EMC_DMAR_MASK_BIT 0 -#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) - -/* Mode Register of SDRAM bank 0 */ -#define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */ -#define EMC_SDMR_OM_BIT 7 /* Operating Mode */ -#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) - #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) -#define EMC_SDMR_CAS_BIT 4 /* CAS Latency */ -#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) - #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) -#define EMC_SDMR_BT_BIT 3 /* Burst Type */ -#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) - #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */ - #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */ -#define EMC_SDMR_BL_BIT 0 /* Burst Length */ -#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) - #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) - -#define EMC_SDMR_CAS2_16BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS2_32BIT \ - (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) -#define EMC_SDMR_CAS3_16BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) -#define EMC_SDMR_CAS3_32BIT \ - (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) - -/************************************************************************* - * WDT (WatchDog Timer) - *************************************************************************/ -#define WDT_TDR (WDT_BASE + 0x00) -#define WDT_TCER (WDT_BASE + 0x04) -#define WDT_TCNT (WDT_BASE + 0x08) -#define WDT_TCSR (WDT_BASE + 0x0C) - -#define REG_WDT_TDR REG16(WDT_TDR) -#define REG_WDT_TCER REG8(WDT_TCER) -#define REG_WDT_TCNT REG16(WDT_TCNT) -#define REG_WDT_TCSR REG16(WDT_TCSR) - -// Register definition -#define WDT_TCSR_PRESCALE_BIT 3 -#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - -/************************************************************************* - * RTC - *************************************************************************/ -#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ -#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ -#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ -#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ - -#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ -#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ -#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ -#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ -#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ -#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ - -#define REG_RTC_RCR REG32(RTC_RCR) -#define REG_RTC_RSR REG32(RTC_RSR) -#define REG_RTC_RSAR REG32(RTC_RSAR) -#define REG_RTC_RGR REG32(RTC_RGR) -#define REG_RTC_HCR REG32(RTC_HCR) -#define REG_RTC_HWFCR REG32(RTC_HWFCR) -#define REG_RTC_HRCR REG32(RTC_HRCR) -#define REG_RTC_HWCR REG32(RTC_HWCR) -#define REG_RTC_HWRSR REG32(RTC_HWRSR) -#define REG_RTC_HSPR REG32(RTC_HSPR) - -/* RTC Control Register */ -#define RTC_RCR_WRDY_BIT 7 -#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ -#define RTC_RCR_1HZ_BIT 6 -#define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) /* 1Hz Flag */ -#define RTC_RCR_1HZIE (1 << 5) /* 1Hz Interrupt Enable */ -#define RTC_RCR_AF_BIT 4 -#define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) /* Alarm Flag */ -#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ -#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ -#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ - -/* RTC Regulator Register */ -#define RTC_RGR_LOCK (1 << 31) /* Lock Bit */ -#define RTC_RGR_ADJC_BIT 16 -#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) -#define RTC_RGR_NC1HZ_BIT 0 -#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) - -/* Hibernate Control Register */ -#define RTC_HCR_PD (1 << 0) /* Power Down */ - -/* Hibernate Wakeup Filter Counter Register */ -#define RTC_HWFCR_BIT 5 -#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) - -/* Hibernate Reset Counter Register */ -#define RTC_HRCR_BIT 5 -#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) - -/* Hibernate Wakeup Control Register */ -#define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */ - -/* Hibernate Wakeup Status Register */ -#define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */ -#define RTC_HWRSR_PPR (1 << 4) /* PPR reset */ -#define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */ -#define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */ - -#endif /* __JZ4740_REGS_H__ */ diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h deleted file mode 100644 index c4819b9825..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/serial.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * linux/include/asm-mips/mach-jz4740/serial.h - * - * Ingenic's JZ4740 common include. - * - * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc. - * - * Author: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_BOARD_SERIAL_H__ -#define __ASM_BOARD_SERIAL_H__ - -#ifndef CONFIG_SERIAL_MANY_PORTS -#undef RS_TABLE_SIZE -#define RS_TABLE_SIZE 1 -#endif - -#define JZ_BASE_BAUD (12000000/16) - -#define JZ_SERIAL_PORT_DEFNS \ - { .baud_base = JZ_BASE_BAUD, .irq = IRQ_UART0, \ - .flags = STD_COM_FLAGS, .iomem_base = (u8 *)UART0_BASE, \ - .iomem_reg_shift = 2, .io_type = SERIAL_IO_MEM }, - -#endif /* __ASM_BORAD_SERIAL_H__ */ diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h deleted file mode 100644 index 3214f36115..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/timer.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2010, Lars-Peter Clausen - * JZ4740 platform timer support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __ASM_MACH_JZ4740_TIMER -#define __ASM_MACH_JZ4740_TIMER - -void jz4740_timer_enable_watchdog(void); -void jz4740_timer_disable_watchdog(void); - -#endif diff --git a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h b/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h deleted file mode 100644 index 3a5bc17e28..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/include/asm/mach-jz4740/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H -#define __ASM_MIPS_MACH_JZ4740_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */ diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig deleted file mode 100644 index 71d35f7a09..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -choice - prompt "Machine type" - depends on MACH_JZ - default JZ4740_QI_LB60 - -config JZ4740_QI_LB60 - bool "Qi Hardware Ben NanoNote" - select DMA_NONCOHERENT - select SOC_JZ4740 - -config JZ4740_N516 - bool "Hanvon n516 eBook reader" - select DMA_NONCOHERENT - select SOC_JZ4740 - -config JZ4740_N526 - bool "Hanvon n526 eBook reader" - select DMA_NONCOHERENT - select SOC_JZ4740 - - -endchoice - -config SOC_JZ4740 - bool - select JZSOC - select GENERIC_GPIO - select ARCH_REQUIRE_GPIOLIB - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_LITTLE_ENDIAN - select IRQ_CPU - -config JZSOC - bool - select JZRISC - select SYS_HAS_CPU_MIPS32_R1 - select SYS_SUPPORTS_32BIT_KERNEL - -config JZRISC - bool diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile deleted file mode 100644 index f298174e5a..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Makefile for the Ingenic JZ4740. -# - -# Object file lists. - -obj-y += prom.o irq.o time.o reset.o setup.o dma.o \ - gpio.o clock.o platform.o - -obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o - -# board specific support - -obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o -obj-$(CONFIG_JZ4740_N516) += board-n516.o board-n516-display.o -obj-$(CONFIG_JZ4740_N526) += board-n526.o - -# PM support - -obj-$(CONFIG_PM) += pm.o - diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516-display.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516-display.c deleted file mode 100644 index a0485da204..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/board-n516-display.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * board-n516-display.c -- Platform device for N516 display - * - * Copyright (C) 2009, Yauhen Kharuzhy - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive for - * more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include