From: James Liao <jamesjj.liao@mediatek.com>
Date: Fri, 10 Jul 2015 08:39:33 +0000 (+0800)
Subject: clk: mediatek: Fix calculation of PLL rate settings
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=196de71a9d9e9090406a87362d22b67ae633fa7a;p=openwrt%2Fstaging%2Fblogic.git

clk: mediatek: Fix calculation of PLL rate settings

Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 68af5183cda0..0e3f4ef0e871 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -144,9 +144,9 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
 	if (freq > pll->data->fmax)
 		freq = pll->data->fmax;
 
-	for (val = 0; val < 4; val++) {
+	for (val = 0; val < 5; val++) {
 		*postdiv = 1 << val;
-		if (freq * *postdiv >= fmin)
+		if ((u64)freq * *postdiv >= fmin)
 			break;
 	}