From: Alexander Stein Date: Thu, 2 Apr 2015 09:55:49 +0000 (+0200) Subject: pinctrl: at91: Add set_multiple GPIO chip feature X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=1893b2cfad0829f8d93f6d88bd396d353ec024c3;p=openwrt%2Fstaging%2Fblogic.git pinctrl: at91: Add set_multiple GPIO chip feature This adds the callback for set_multiple. As this controller has a separate set and clear register, we can't write directly to PIO_ODSR as this would required a cached variable and would race with at91_gpio_set. So build masks for the PIO_SODR and PIO_CODR registers and write them together. Signed-off-by: Alexander Stein Signed-off-by: Linus Walleij --- diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 2f797cb7e205..d80ade23fd1b 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1326,6 +1326,21 @@ static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); } +static void at91_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, unsigned long *bits) +{ + struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); + void __iomem *pio = at91_gpio->regbase; + +#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) + /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ + uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); + uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); + + writel_relaxed(set_mask, pio + PIO_SODR); + writel_relaxed(clear_mask, pio + PIO_CODR); +} + static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int val) { @@ -1685,6 +1700,7 @@ static struct gpio_chip at91_gpio_template = { .get = at91_gpio_get, .direction_output = at91_gpio_direction_output, .set = at91_gpio_set, + .set_multiple = at91_gpio_set_multiple, .dbg_show = at91_gpio_dbg_show, .can_sleep = false, .ngpio = MAX_NB_GPIO_PER_BANK,