From: John Crispin Date: Tue, 24 Nov 2015 18:28:54 +0000 (+0000) Subject: ramips: add second spi master sysclk X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=12b6f4cf71787950b606dd61f4a649a73453f2f8;p=openwrt%2Fstaging%2Fneocturne.git ramips: add second spi master sysclk for mt7620, rt3883 and rt5350 Signed-off-by: Michael Lee SVN-Revision: 47616 --- diff --git a/target/linux/ramips/patches-3.18/0305-second_spi_sysclk.patch b/target/linux/ramips/patches-3.18/0305-second_spi_sysclk.patch new file mode 100644 index 0000000000..dffec5e9e7 --- /dev/null +++ b/target/linux/ramips/patches-3.18/0305-second_spi_sysclk.patch @@ -0,0 +1,30 @@ +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -434,6 +434,7 @@ void __init ralink_clk_init(void) + ralink_clk_add("10000100.timer", periph_rate); + ralink_clk_add("10000120.watchdog", periph_rate); + ralink_clk_add("10000b00.spi", sys_rate); ++ ralink_clk_add("10000b40.spi", sys_rate); + ralink_clk_add("10000c00.uartlite", periph_rate); + ralink_clk_add("10000d00.uart1", periph_rate); + ralink_clk_add("10000e00.uart2", periph_rate); +--- a/arch/mips/ralink/rt305x.c ++++ b/arch/mips/ralink/rt305x.c +@@ -199,6 +199,7 @@ void __init ralink_clk_init(void) + ralink_clk_add("cpu", cpu_rate); + ralink_clk_add("sys", sys_rate); + ralink_clk_add("10000b00.spi", sys_rate); ++ ralink_clk_add("10000b40.spi", sys_rate); + ralink_clk_add("10000100.timer", wdt_rate); + ralink_clk_add("10000120.watchdog", wdt_rate); + ralink_clk_add("10000500.uart", uart_rate); +--- a/arch/mips/ralink/rt3883.c ++++ b/arch/mips/ralink/rt3883.c +@@ -109,6 +109,7 @@ void __init ralink_clk_init(void) + ralink_clk_add("10000120.watchdog", sys_rate); + ralink_clk_add("10000500.uart", 40000000); + ralink_clk_add("10000b00.spi", sys_rate); ++ ralink_clk_add("10000b40.spi", sys_rate); + ralink_clk_add("10000c00.uartlite", 40000000); + ralink_clk_add("10100000.ethernet", sys_rate); + ralink_clk_add("10180000.wmac", 40000000);