From: Daniel Golle Date: Wed, 31 Aug 2022 12:31:02 +0000 (+0100) Subject: uboot-mediatek: replace patches with updated versions X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=0ea329fec4c693443066faffe864edba17facc27;p=openwrt%2Fstaging%2Fnbd.git uboot-mediatek: replace patches with updated versions Weijie Gao has submitted an updated version of the patchset adding support for MT7986 and MT7981 to U-Boot. Use that v2 patchset. Changes of v2: - Add cpu driver for print_cpuinfo() - Fix NULL pointer dereference in mtk_image (was already fixed in OpenWrt) - Fix coding style - Minor changes https://patchwork.ozlabs.org/project/uboot/list/?series=316148 Signed-off-by: Daniel Golle --- diff --git a/package/boot/uboot-mediatek/patches/002-0000-serial-Replace-CONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch b/package/boot/uboot-mediatek/patches/002-0000-serial-Replace-CONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch new file mode 100644 index 0000000000..a94ea18dd5 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/002-0000-serial-Replace-CONFIG_DEBUG_UART_BASE-by-CONFIG_VAL-.patch @@ -0,0 +1,494 @@ +From b62450cf229c50ad2ce819dd02a09726909cc89a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Fri, 27 May 2022 22:15:24 +0200 +Subject: [PATCH] serial: Replace CONFIG_DEBUG_UART_BASE by + CONFIG_VAL(DEBUG_UART_BASE) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +CONFIG_VAL(DEBUG_UART_BASE) expands to CONFIG_DEBUG_UART_BASE or +CONFIG_SPL_DEBUG_UART_BASE or CONFIG_TPL_DEBUG_UART_BASE and allows boards +to set different values for SPL, TPL and U-Boot Proper. + +For ns16550 driver this support is there since commit d293759d55cc +("serial: ns16550: Add support for SPL_DEBUG_UART_BASE"). + +Signed-off-by: Pali Rohár +--- + arch/arm/mach-uniphier/debug-uart/debug-uart.c | 4 ++-- + arch/x86/cpu/apollolake/cpu_common.c | 2 +- + board/eets/pdu001/board.c | 2 +- + drivers/serial/altera_jtag_uart.c | 2 +- + drivers/serial/altera_uart.c | 4 ++-- + drivers/serial/atmel_usart.c | 4 ++-- + drivers/serial/serial_ar933x.c | 4 ++-- + drivers/serial/serial_arc.c | 4 ++-- + drivers/serial/serial_bcm6345.c | 4 ++-- + drivers/serial/serial_linflexuart.c | 4 ++-- + drivers/serial/serial_meson.c | 2 +- + drivers/serial/serial_msm_geni.c | 6 +++--- + drivers/serial/serial_mt7620.c | 4 ++-- + drivers/serial/serial_mtk.c | 4 ++-- + drivers/serial/serial_mvebu_a3700.c | 4 ++-- + drivers/serial/serial_mxc.c | 4 ++-- + drivers/serial/serial_omap.c | 4 ++-- + drivers/serial/serial_pic32.c | 4 ++-- + drivers/serial/serial_pl01x.c | 4 ++-- + drivers/serial/serial_s5p.c | 4 ++-- + drivers/serial/serial_sifive.c | 4 ++-- + drivers/serial/serial_stm32.c | 4 ++-- + drivers/serial/serial_xuartlite.c | 4 ++-- + drivers/serial/serial_zynq.c | 4 ++-- + 24 files changed, 45 insertions(+), 45 deletions(-) + +--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c ++++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c +@@ -18,7 +18,7 @@ + + static void _debug_uart_putc(int c) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE)) + ; +@@ -57,7 +57,7 @@ void sg_set_iectrl(unsigned int pin) + void _debug_uart_init(void) + { + #ifdef CONFIG_SPL_BUILD +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + unsigned int divisor; + + switch (uniphier_get_soc_id()) { +--- a/arch/x86/cpu/apollolake/cpu_common.c ++++ b/arch/x86/cpu/apollolake/cpu_common.c +@@ -72,7 +72,7 @@ static void pch_uart_init(void) + } + + #ifdef CONFIG_DEBUG_UART +- apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE); ++ apl_uart_init(PCH_DEV_UART, CONFIG_VAL(DEBUG_UART_BASE)); + #endif + } + +--- a/board/eets/pdu001/board.c ++++ b/board/eets/pdu001/board.c +@@ -273,7 +273,7 @@ void board_debug_uart_init(void) + setup_early_clocks(); + + /* done by pin controller driver if not debugging */ +- enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE); ++ enable_uart_pin_mux(CONFIG_VAL(DEBUG_UART_BASE)); + } + #endif + +--- a/drivers/serial/altera_jtag_uart.c ++++ b/drivers/serial/altera_jtag_uart.c +@@ -134,7 +134,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct altera_jtaguart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ struct altera_jtaguart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + + while (1) { + u32 st = readl(®s->control); +--- a/drivers/serial/altera_uart.c ++++ b/drivers/serial/altera_uart.c +@@ -123,7 +123,7 @@ U_BOOT_DRIVER(altera_uart) = { + + static inline void _debug_uart_init(void) + { +- struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + u32 div; + + div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1; +@@ -132,7 +132,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ struct altera_uart_regs *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + + while (1) { + u32 st = readl(®s->status); +--- a/drivers/serial/atmel_usart.c ++++ b/drivers/serial/atmel_usart.c +@@ -319,14 +319,14 @@ U_BOOT_DRIVER(serial_atmel) = { + #ifdef CONFIG_DEBUG_UART_ATMEL + static inline void _debug_uart_init(void) + { +- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE; ++ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE); + + _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); + } + + static inline void _debug_uart_putc(int ch) + { +- atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE; ++ atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(&usart->csr) & USART3_BIT(TXRDY))) + ; +--- a/drivers/serial/serial_ar933x.c ++++ b/drivers/serial/serial_ar933x.c +@@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_ar933x) = { + + static inline void _debug_uart_init(void) + { +- void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + u32 val, scale, step; + + /* +@@ -227,7 +227,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int c) + { +- void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + u32 data; + + do { +--- a/drivers/serial/serial_arc.c ++++ b/drivers/serial/serial_arc.c +@@ -137,7 +137,7 @@ U_BOOT_DRIVER(serial_arc) = { + + static inline void _debug_uart_init(void) + { +- struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE; ++ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE); + int arc_console_baud = CONFIG_DEBUG_UART_CLOCK / (CONFIG_BAUDRATE * 4) - 1; + + writeb(arc_console_baud & 0xff, ®s->baudl); +@@ -146,7 +146,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int c) + { +- struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE; ++ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readb(®s->status) & UART_TXEMPTY)) + ; +--- a/drivers/serial/serial_bcm6345.c ++++ b/drivers/serial/serial_bcm6345.c +@@ -269,7 +269,7 @@ U_BOOT_DRIVER(bcm6345_serial) = { + #ifdef CONFIG_DEBUG_UART_BCM6345 + static inline void _debug_uart_init(void) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); + } +@@ -285,7 +285,7 @@ static inline void wait_xfered(void __io + + static inline void _debug_uart_putc(int ch) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + wait_xfered(base); + writel(ch, base + UART_FIFO_REG); +--- a/drivers/serial/serial_linflexuart.c ++++ b/drivers/serial/serial_linflexuart.c +@@ -201,14 +201,14 @@ U_BOOT_DRIVER(serial_linflex) = { + + static inline void _debug_uart_init(void) + { +- struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE; ++ struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE); + + linflex_serial_init_internal(base); + } + + static inline void _debug_uart_putc(int ch) + { +- struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_DEBUG_UART_BASE; ++ struct linflex_fsl *base = (struct linflex_fsl *)CONFIG_VAL(DEBUG_UART_BASE); + + /* XXX: Is this OK? Should this use the non-DM version? */ + _linflex_serial_putc(base, ch); +--- a/drivers/serial/serial_meson.c ++++ b/drivers/serial/serial_meson.c +@@ -182,7 +182,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE; ++ struct meson_uart *regs = (struct meson_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + while (readl(®s->status) & AML_UART_TX_FULL) + ; +--- a/drivers/serial/serial_msm_geni.c ++++ b/drivers/serial/serial_msm_geni.c +@@ -569,7 +569,7 @@ U_BOOT_DRIVER(serial_msm_geni) = { + #ifdef CONFIG_DEBUG_UART_MSM_GENI + + static struct msm_serial_data init_serial_data = { +- .base = CONFIG_DEBUG_UART_BASE ++ .base = CONFIG_VAL(DEBUG_UART_BASE) + }; + + /* Serial dumb device, to reuse driver code */ +@@ -587,7 +587,7 @@ static struct udevice init_dev = { + + static inline void _debug_uart_init(void) + { +- phys_addr_t base = CONFIG_DEBUG_UART_BASE; ++ phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + + geni_serial_init(&init_dev); + geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE); +@@ -596,7 +596,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- phys_addr_t base = CONFIG_DEBUG_UART_BASE; ++ phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + + writel(DEF_TX_WM, base + SE_GENI_TX_WATERMARK_REG); + qcom_geni_serial_setup_tx(base, 1); +--- a/drivers/serial/serial_mt7620.c ++++ b/drivers/serial/serial_mt7620.c +@@ -220,7 +220,7 @@ static inline void _debug_uart_init(void + { + struct mt7620_serial_plat plat; + +- plat.regs = (void *)CONFIG_DEBUG_UART_BASE; ++ plat.regs = (void *)CONFIG_VAL(DEBUG_UART_BASE); + plat.clock = CONFIG_DEBUG_UART_CLOCK; + + writel(0, &plat.regs->ier); +@@ -233,7 +233,7 @@ static inline void _debug_uart_init(void + static inline void _debug_uart_putc(int ch) + { + struct mt7620_serial_regs __iomem *regs = +- (void *)CONFIG_DEBUG_UART_BASE; ++ (void *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(®s->lsr) & UART_LSR_THRE)) + ; +--- a/drivers/serial/serial_mtk.c ++++ b/drivers/serial/serial_mtk.c +@@ -426,7 +426,7 @@ static inline void _debug_uart_init(void + { + struct mtk_serial_priv priv; + +- priv.regs = (void *) CONFIG_DEBUG_UART_BASE; ++ priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE); + priv.clock = CONFIG_DEBUG_UART_CLOCK; + + writel(0, &priv.regs->ier); +@@ -439,7 +439,7 @@ static inline void _debug_uart_init(void + static inline void _debug_uart_putc(int ch) + { + struct mtk_serial_regs __iomem *regs = +- (void *) CONFIG_DEBUG_UART_BASE; ++ (void *) CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(®s->lsr) & UART_LSR_THRE)) + ; +--- a/drivers/serial/serial_mvebu_a3700.c ++++ b/drivers/serial/serial_mvebu_a3700.c +@@ -321,7 +321,7 @@ U_BOOT_DRIVER(serial_mvebu) = { + + static inline void _debug_uart_init(void) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + u32 parent_rate, divider; + + /* reset FIFOs */ +@@ -349,7 +349,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL) + ; +--- a/drivers/serial/serial_mxc.c ++++ b/drivers/serial/serial_mxc.c +@@ -372,7 +372,7 @@ U_BOOT_DRIVER(serial_mxc) = { + + static inline void _debug_uart_init(void) + { +- struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE; ++ struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + _mxc_serial_init(base, false); + _mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK, +@@ -381,7 +381,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE; ++ struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(readl(&base->ts) & UTS_TXEMPTY)) + WATCHDOG_RESET(); +--- a/drivers/serial/serial_omap.c ++++ b/drivers/serial/serial_omap.c +@@ -66,7 +66,7 @@ static inline int serial_in_shift(void * + + static inline void _debug_uart_init(void) + { +- struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE; ++ struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); + int baud_divisor; + + baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, +@@ -85,7 +85,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE; ++ struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE); + + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) + ; +--- a/drivers/serial/serial_pic32.c ++++ b/drivers/serial/serial_pic32.c +@@ -187,14 +187,14 @@ U_BOOT_DRIVER(pic32_serial) = { + + static inline void _debug_uart_init(void) + { +- void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; ++ void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); + + pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); + } + + static inline void _debug_uart_putc(int ch) + { +- writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR); ++ writel(ch, CONFIG_VAL(DEBUG_UART_BASE) + U_TXR); + } + + DEBUG_UART_FUNCS +--- a/drivers/serial/serial_pl01x.c ++++ b/drivers/serial/serial_pl01x.c +@@ -403,7 +403,7 @@ U_BOOT_DRIVER(serial_pl01x) = { + static void _debug_uart_init(void) + { + #ifndef CONFIG_DEBUG_UART_SKIP_INIT +- struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; ++ struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE); + enum pl01x_type type; + + if (IS_ENABLED(CONFIG_DEBUG_UART_PL011)) +@@ -419,7 +419,7 @@ static void _debug_uart_init(void) + + static inline void _debug_uart_putc(int ch) + { +- struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; ++ struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_VAL(DEBUG_UART_BASE); + + while (pl01x_putc(regs, ch) == -EAGAIN) + ; +--- a/drivers/serial/serial_s5p.c ++++ b/drivers/serial/serial_s5p.c +@@ -276,7 +276,7 @@ static inline void _debug_uart_init(void + if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT)) + return; + +- struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; ++ struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + s5p_serial_init(uart); + #if CONFIG_IS_ENABLED(ARCH_APPLE) +@@ -288,7 +288,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct s5p_uart *uart = (struct s5p_uart *)CONFIG_DEBUG_UART_BASE; ++ struct s5p_uart *uart = (struct s5p_uart *)CONFIG_VAL(DEBUG_UART_BASE); + + #if CONFIG_IS_ENABLED(ARCH_APPLE) + while (readl(&uart->ufstat) & S5L_TX_FIFO_FULL); +--- a/drivers/serial/serial_sifive.c ++++ b/drivers/serial/serial_sifive.c +@@ -212,7 +212,7 @@ U_BOOT_DRIVER(serial_sifive) = { + static inline void _debug_uart_init(void) + { + struct uart_sifive *regs = +- (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; ++ (struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE); + + _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); +@@ -222,7 +222,7 @@ static inline void _debug_uart_init(void + static inline void _debug_uart_putc(int ch) + { + struct uart_sifive *regs = +- (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; ++ (struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE); + + while (_sifive_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); +--- a/drivers/serial/serial_stm32.c ++++ b/drivers/serial/serial_stm32.c +@@ -270,7 +270,7 @@ static inline struct stm32_uart_info *_d + + static inline void _debug_uart_init(void) + { +- fdt_addr_t base = CONFIG_DEBUG_UART_BASE; ++ fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + struct stm32_uart_info *uart_info = _debug_uart_info(); + + _stm32_serial_init(base, uart_info); +@@ -281,7 +281,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int c) + { +- fdt_addr_t base = CONFIG_DEBUG_UART_BASE; ++ fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + struct stm32_uart_info *uart_info = _debug_uart_info(); + + while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN) +--- a/drivers/serial/serial_xuartlite.c ++++ b/drivers/serial/serial_xuartlite.c +@@ -143,7 +143,7 @@ U_BOOT_DRIVER(serial_uartlite) = { + + static inline void _debug_uart_init(void) + { +- struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; ++ struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE); + int ret; + + uart_out32(®s->control, 0); +@@ -159,7 +159,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct uartlite *regs = (struct uartlite *)CONFIG_DEBUG_UART_BASE; ++ struct uartlite *regs = (struct uartlite *)CONFIG_VAL(DEBUG_UART_BASE); + + while (uart_in32(®s->status) & SR_TX_FIFO_FULL) + ; +--- a/drivers/serial/serial_zynq.c ++++ b/drivers/serial/serial_zynq.c +@@ -295,7 +295,7 @@ U_BOOT_DRIVER(serial_zynq) = { + #ifdef CONFIG_DEBUG_UART_ZYNQ + static inline void _debug_uart_init(void) + { +- struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; ++ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE); + + _uart_zynq_serial_init(regs); + _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, +@@ -304,7 +304,7 @@ static inline void _debug_uart_init(void + + static inline void _debug_uart_putc(int ch) + { +- struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; ++ struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE); + + while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); diff --git a/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch index 663f06c22c..07d7e4a6ae 100644 --- a/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0001-arm-mediatek-add-support-for-MediaTek-MT7986-SoC.patch @@ -1,7 +1,7 @@ -From a299de45833df13d4ec28092201ea5fec0ba24fe Mon Sep 17 00:00:00 2001 +From 13d81db4723241e33316d7d134e4d279116e3158 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 15:17:58 +0800 -Subject: [PATCH 01/31] arm: mediatek: add support for MediaTek MT7986 SoC +Date: Wed, 31 Aug 2022 19:00:17 +0800 +Subject: [PATCH 01/32] arm: mediatek: add support for MediaTek MT7986 SoC This patch adds basic support for MediaTek MT7986 SoC. This include the file that will initialize the SoC after boot and its @@ -10,11 +10,11 @@ device tree. Signed-off-by: Weijie Gao --- arch/arm/dts/mt7986-u-boot.dtsi | 33 ++ - arch/arm/dts/mt7986.dtsi | 341 ++++++++++++++++++ - arch/arm/mach-mediatek/Kconfig | 11 + + arch/arm/dts/mt7986.dtsi | 346 ++++++++++++++++++ + arch/arm/mach-mediatek/Kconfig | 12 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt7986/Makefile | 4 + - arch/arm/mach-mediatek/mt7986/init.c | 51 +++ + arch/arm/mach-mediatek/mt7986/init.c | 45 +++ arch/arm/mach-mediatek/mt7986/lowlevel_init.S | 32 ++ 7 files changed, 473 insertions(+) create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi @@ -61,7 +61,7 @@ Signed-off-by: Weijie Gao +}; --- /dev/null +++ b/arch/arm/dts/mt7986.dtsi -@@ -0,0 +1,341 @@ +@@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. @@ -118,6 +118,11 @@ Signed-off-by: Weijie Gao + u-boot,dm-pre-reloc; + }; + ++ hwver: hwver { ++ compatible = "mediatek,hwver"; ++ reg = <0x8000000 0x1000>; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; @@ -405,13 +410,14 @@ Signed-off-by: Weijie Gao +}; --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -40,6 +40,14 @@ config TARGET_MT7629 +@@ -40,6 +40,15 @@ config TARGET_MT7629 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, switch, USB3.0, PCIe, UART, SPI, I2C and PWM. +config TARGET_MT7986 + bool "MediaTek MT7986 SoC" + select ARM64 ++ select CPU + help + The MediaTek MT7986 is a ARM64-based SoC with a quad-core Cortex-A53. + including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, @@ -420,7 +426,7 @@ Signed-off-by: Weijie Gao config TARGET_MT8183 bool "MediaTek MT8183 SoC" select ARM64 -@@ -84,6 +92,7 @@ config SYS_BOARD +@@ -84,6 +93,7 @@ config SYS_BOARD default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -428,7 +434,7 @@ Signed-off-by: Weijie Gao default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 -@@ -99,6 +108,7 @@ config SYS_CONFIG_NAME +@@ -99,6 +109,7 @@ config SYS_CONFIG_NAME default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -436,7 +442,7 @@ Signed-off-by: Weijie Gao default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 -@@ -113,6 +123,7 @@ config MTK_BROM_HEADER_INFO +@@ -113,6 +124,7 @@ config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 @@ -463,7 +469,7 @@ Signed-off-by: Weijie Gao +obj-y += lowlevel_init.o --- /dev/null +++ b/arch/arm/mach-mediatek/mt7986/init.c -@@ -0,0 +1,51 @@ +@@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. @@ -477,12 +483,6 @@ Signed-off-by: Weijie Gao + +DECLARE_GLOBAL_DATA_PTR; + -+int print_cpuinfo(void) -+{ -+ printf("CPU: MediaTek MT7986\n"); -+ return 0; -+} -+ +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); diff --git a/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch index 93596af53d..425f0de1b4 100644 --- a/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0002-arm-mediatek-add-support-for-MediaTek-MT7981-SoC.patch @@ -1,7 +1,7 @@ -From 38faebb811868f9e6734dea7894d0fa5a61f3a22 Mon Sep 17 00:00:00 2001 +From 5512a2e8257b0a733cf90ec247f34094ff31f750 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 15:58:11 +0800 -Subject: [PATCH 02/31] arm: mediatek: add support for MediaTek MT7981 SoC +Date: Wed, 31 Aug 2022 19:00:20 +0800 +Subject: [PATCH 02/32] arm: mediatek: add support for MediaTek MT7981 SoC This patch adds basic support for MediaTek MT7981 SoC. This include the file that will initialize the SoC after boot and its @@ -9,11 +9,11 @@ device tree. Signed-off-by: Weijie Gao --- - arch/arm/dts/mt7981.dtsi | 288 ++++++++++++++++++ - arch/arm/mach-mediatek/Kconfig | 12 +- + arch/arm/dts/mt7981.dtsi | 293 ++++++++++++++++++ + arch/arm/mach-mediatek/Kconfig | 13 +- arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt7981/Makefile | 4 + - arch/arm/mach-mediatek/mt7981/init.c | 51 ++++ + arch/arm/mach-mediatek/mt7981/init.c | 45 +++ arch/arm/mach-mediatek/mt7981/lowlevel_init.S | 32 ++ 6 files changed, 387 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/mt7981.dtsi @@ -23,7 +23,7 @@ Signed-off-by: Weijie Gao --- /dev/null +++ b/arch/arm/dts/mt7981.dtsi -@@ -0,0 +1,288 @@ +@@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. @@ -63,6 +63,11 @@ Signed-off-by: Weijie Gao + u-boot,dm-pre-reloc; + }; + ++ hwver: hwver { ++ compatible = "mediatek,hwver"; ++ reg = <0x8000000 0x1000>; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; @@ -314,13 +319,14 @@ Signed-off-by: Weijie Gao +}; --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -40,6 +40,14 @@ config TARGET_MT7629 +@@ -40,6 +40,15 @@ config TARGET_MT7629 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, switch, USB3.0, PCIe, UART, SPI, I2C and PWM. +config TARGET_MT7981 + bool "MediaTek MT7981 SoC" + select ARM64 ++ select CPU + help + The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53. + including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C, @@ -329,7 +335,7 @@ Signed-off-by: Weijie Gao config TARGET_MT7986 bool "MediaTek MT7986 SoC" select ARM64 -@@ -92,6 +100,7 @@ config SYS_BOARD +@@ -93,6 +102,7 @@ config SYS_BOARD default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -337,7 +343,7 @@ Signed-off-by: Weijie Gao default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 -@@ -108,6 +117,7 @@ config SYS_CONFIG_NAME +@@ -109,6 +119,7 @@ config SYS_CONFIG_NAME default "mt7622" if TARGET_MT7622 default "mt7623" if TARGET_MT7623 default "mt7629" if TARGET_MT7629 @@ -345,7 +351,7 @@ Signed-off-by: Weijie Gao default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 -@@ -123,7 +133,7 @@ config MTK_BROM_HEADER_INFO +@@ -124,7 +135,7 @@ config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 @@ -373,7 +379,7 @@ Signed-off-by: Weijie Gao +obj-y += lowlevel_init.o --- /dev/null +++ b/arch/arm/mach-mediatek/mt7981/init.c -@@ -0,0 +1,51 @@ +@@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. @@ -387,12 +393,6 @@ Signed-off-by: Weijie Gao + +DECLARE_GLOBAL_DATA_PTR; + -+int print_cpuinfo(void) -+{ -+ printf("CPU: MediaTek MT7981\n"); -+ return 0; -+} -+ +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); diff --git a/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch b/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch index 8cbd57459d..2c1d50481b 100644 --- a/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch +++ b/package/boot/uboot-mediatek/patches/002-0003-board-mediatek-add-MT7986-reference-boards.patch @@ -1,7 +1,7 @@ -From ab3f81920b4e47bd2894388540363700d5b1e59c Mon Sep 17 00:00:00 2001 +From bad27c737d27f8afc4d597b6de1bdbc26a152ad9 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 15:26:31 +0800 -Subject: [PATCH 03/31] board: mediatek: add MT7986 reference boards +Date: Wed, 31 Aug 2022 19:00:22 +0800 +Subject: [PATCH 03/32] board: mediatek: add MT7986 reference boards Add general board files based on MT7986 SoCs. diff --git a/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch b/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch index 6e08843bdc..401aa11cda 100644 --- a/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch +++ b/package/boot/uboot-mediatek/patches/002-0004-board-mediatek-add-MT7981-reference-boards.patch @@ -1,7 +1,7 @@ -From 89a31bfa05c384a2b4e56ddb9814633325b7feab Mon Sep 17 00:00:00 2001 +From 37bcf4d1acb5f7ce93fa0bd59dc313a79004ae34 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 16:02:37 +0800 -Subject: [PATCH 04/31] board: mediatek: add MT7981 reference boards +Date: Wed, 31 Aug 2022 19:00:25 +0800 +Subject: [PATCH 04/32] board: mediatek: add MT7981 reference boards This patch adds general board files based on MT7981 SoCs. diff --git a/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch b/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch index 281c289c6a..aa9adf40ff 100644 --- a/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch +++ b/package/boot/uboot-mediatek/patches/002-0005-mmc-mediatek-add-support-for-MediaTek-MT7891-MT7986-.patch @@ -1,7 +1,7 @@ -From 3831266fedf14ef415791a93dd03a9e637eb8b5e Mon Sep 17 00:00:00 2001 +From 9a10182f21cc4007f46284d5c64c49dc892336be Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Tue, 26 Jul 2022 09:24:13 +0800 -Subject: [PATCH 05/31] mmc: mediatek: add support for MediaTek MT7891/MT7986 +Date: Wed, 31 Aug 2022 19:04:12 +0800 +Subject: [PATCH 05/32] mmc: mediatek: add support for MediaTek MT7891/MT7986 SoCs Add eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs diff --git a/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch b/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch index 2a1f5892d8..08cad1bb53 100644 --- a/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch +++ b/package/boot/uboot-mediatek/patches/002-0006-net-mediatek-use-a-struct-to-cover-variations-of-all.patch @@ -1,7 +1,7 @@ -From 5c5af768c4cceaa9d7497c3e5bfbc9d1ea8b279c Mon Sep 17 00:00:00 2001 +From ba6af13fd58c0ec418720d959152e0db47e91b02 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Tue, 26 Jul 2022 10:44:57 +0800 -Subject: [PATCH 06/31] net: mediatek: use a struct to cover variations of all +Date: Wed, 31 Aug 2022 19:04:19 +0800 +Subject: [PATCH 06/32] net: mediatek: use a struct to cover variations of all SoCs Using a single soc id to control different initialization and TX/RX flow diff --git a/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch b/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch index 3cf45b7f3e..41f5ce6335 100644 --- a/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch +++ b/package/boot/uboot-mediatek/patches/002-0007-net-mediatek-stop-using-bitfileds-for-DMA-descriptor.patch @@ -1,7 +1,7 @@ -From b978c067075fddbac341bf551ebef29e78767b75 Mon Sep 17 00:00:00 2001 +From 5f6f3600a334398e27802de33a6a8726aacbe88c Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 09:32:29 +0800 -Subject: [PATCH 07/31] net: mediatek: stop using bitfileds for DMA descriptors +Date: Wed, 31 Aug 2022 19:04:23 +0800 +Subject: [PATCH 07/32] net: mediatek: stop using bitfileds for DMA descriptors This patch is a preparation for adding a new version of PDMA of which the DMA descriptor fields has changed. Using bitfields will result in a complex diff --git a/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch b/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch index 0fc0f4cafb..043e9a91d4 100644 --- a/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch +++ b/package/boot/uboot-mediatek/patches/002-0008-net-mediatek-add-support-for-PDMA-v2.patch @@ -1,7 +1,7 @@ -From 2f53795aac940d960bc5f3b08a730c4d480fc5f6 Mon Sep 17 00:00:00 2001 +From 72241607b955639a51b79297776991de7dd59915 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 09:56:30 +0800 -Subject: [PATCH 08/31] net: mediatek: add support for PDMA v2 +Date: Wed, 31 Aug 2022 19:04:27 +0800 +Subject: [PATCH 08/32] net: mediatek: add support for PDMA v2 This patch adds support for PDMA v2 hardware. The PDMA v2 has extended the DMA descriptor to 8-words, and some of its fields have changed comparing diff --git a/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch b/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch index 7afd49d457..e2a16e2d6d 100644 --- a/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch +++ b/package/boot/uboot-mediatek/patches/002-0009-net-mediatek-add-support-for-MediaTek-MT7981-MT7986.patch @@ -1,7 +1,7 @@ -From 5e06e9a78bbc81f64fdb4c8502a8e7175d8b6216 Mon Sep 17 00:00:00 2001 +From 4bbe44513bf9dc7041b2ce4aac6e841a0e10d2e6 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 10:03:17 +0800 -Subject: [PATCH 09/31] net: mediatek: add support for MediaTek MT7981/MT7986 +Date: Wed, 31 Aug 2022 19:04:29 +0800 +Subject: [PATCH 09/32] net: mediatek: add support for MediaTek MT7981/MT7986 This patch adds support for MediaTek MT7981 and MT7986. Both chips uses PDMA v2. diff --git a/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch b/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch index ff7f66f067..d2f28f2bc9 100644 --- a/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch +++ b/package/boot/uboot-mediatek/patches/002-0010-serial-mtk-add-support-for-using-dynamic-baud-clock-.patch @@ -1,7 +1,7 @@ -From 55ed87efb110d13fce6d1a7ee6cb04fac1a2c08a Mon Sep 17 00:00:00 2001 +From d19ad7515a7ef4ee58b5c6606ee9f74c94f28932 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 10:28:05 +0800 -Subject: [PATCH 10/31] serial: mtk: add support for using dynamic baud clock +Date: Wed, 31 Aug 2022 19:04:32 +0800 +Subject: [PATCH 10/32] serial: mtk: add support for using dynamic baud clock souce The baud clock on some platform may change due to assigned-clock-parent @@ -187,7 +187,7 @@ Signed-off-by: Weijie Gao @@ -427,13 +441,13 @@ static inline void _debug_uart_init(void struct mtk_serial_priv priv; - priv.regs = (void *) CONFIG_DEBUG_UART_BASE; + priv.regs = (void *) CONFIG_VAL(DEBUG_UART_BASE); - priv.clock = CONFIG_DEBUG_UART_CLOCK; + priv.fixed_clk_rate = CONFIG_DEBUG_UART_CLOCK; diff --git a/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch b/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch index 7ed6083c89..0777848f01 100644 --- a/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch +++ b/package/boot/uboot-mediatek/patches/002-0011-arm-dts-mt7622-force-high-speed-mode-for-uart.patch @@ -1,7 +1,7 @@ -From 893368e64049fd770e55fffcc8758d2619dc337d Mon Sep 17 00:00:00 2001 +From 79786aa175010dde78f95970939e8efadd7a3295 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Mon, 25 Jul 2022 16:33:13 +0800 -Subject: [PATCH 11/31] arm: dts: mt7622: force high-speed mode for uart +Date: Wed, 31 Aug 2022 19:04:34 +0800 +Subject: [PATCH 11/32] arm: dts: mt7622: force high-speed mode for uart The input clock for uart is too slow (25MHz) which introduces frequent data error on both receiving and transmitting even if the baudrate is 115200. diff --git a/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch index a19b69a53c..da5f53f49c 100644 --- a/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0012-pwm-mtk-add-support-for-MediaTek-MT7986-SoC.patch @@ -1,7 +1,7 @@ -From 63acbf4ffe328809ca479e5c7d344882810d412c Mon Sep 17 00:00:00 2001 +From d7dae84aad997f4f9b5d039f7ab180bd1f54fa37 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 11:00:15 +0800 -Subject: [PATCH 12/31] pwm: mtk: add support for MediaTek MT7986 SoC +Date: Wed, 31 Aug 2022 19:04:35 +0800 +Subject: [PATCH 12/32] pwm: mtk: add support for MediaTek MT7986 SoC This patch adds PWM support for MediaTek MT7986 SoC. diff --git a/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch index 2da5b960a3..cd8ecd5917 100644 --- a/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0013-pwm-mtk-add-support-for-MediaTek-MT7981-SoC.patch @@ -1,7 +1,7 @@ -From 4569ef02981f20b236a8cdc3a57b4d27fbdbc22e Mon Sep 17 00:00:00 2001 +From 230003c14f7beedf4042bf2258b04e2cd5aac270 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 11:01:34 +0800 -Subject: [PATCH 13/31] pwm: mtk: add support for MediaTek MT7981 SoC +Date: Wed, 31 Aug 2022 19:04:38 +0800 +Subject: [PATCH 13/32] pwm: mtk: add support for MediaTek MT7981 SoC This patch adds PWM support for MediaTek MT7981 SoC. MT7981 uses a different register offset so we have to add a version field diff --git a/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch index 7889401931..d02841951d 100644 --- a/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0014-timer-mtk-add-support-for-MediaTek-MT7981-MT7986-SoC.patch @@ -1,7 +1,7 @@ -From 7860bc58c43dfa939d2664be518c28aea591aeef Mon Sep 17 00:00:00 2001 +From a77b8f6d9aa90f80090e505d823a6dcf6b877136 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 11:38:33 +0800 -Subject: [PATCH 14/31] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs +Date: Wed, 31 Aug 2022 19:04:40 +0800 +Subject: [PATCH 14/32] timer: mtk: add support for MediaTek MT7981/MT7986 SoCs This patch add general-purpose timer support for MediaTek MT7981/MT7986. These two SoCs uses a newer version of timer with its register definition diff --git a/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch b/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch index 09ffc5c7d9..3215d17050 100644 --- a/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch +++ b/package/boot/uboot-mediatek/patches/002-0015-watchdog-mediatek-add-support-for-MediaTek-MT7986-So.patch @@ -1,7 +1,7 @@ -From ec7e5d3e4d6e9239f3d7ac861f07ca4a52bec9fa Mon Sep 17 00:00:00 2001 +From 18f761770d7aa53abf187fa64bbd92f0682d154c Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 11:47:50 +0800 -Subject: [PATCH 15/31] watchdog: mediatek: add support for MediaTek MT7986 SoC +Date: Wed, 31 Aug 2022 19:04:42 +0800 +Subject: [PATCH 15/32] watchdog: mediatek: add support for MediaTek MT7986 SoC Add watchdog support for MediaTek MT7986 SoC diff --git a/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch b/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch index 04c2df3b48..0e0d72d5eb 100644 --- a/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch +++ b/package/boot/uboot-mediatek/patches/002-0016-spi-add-support-for-MediaTek-spi-mem-controller.patch @@ -1,7 +1,7 @@ -From f85493e3c2d1e4fd411061540b4f4943c09114df Mon Sep 17 00:00:00 2001 +From e6b225ff8990635dc2d6d8dbd72e78dec1f36c62 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 16:58:38 +0800 -Subject: [PATCH 16/31] spi: add support for MediaTek spi-mem controller +Date: Wed, 31 Aug 2022 19:04:45 +0800 +Subject: [PATCH 16/32] spi: add support for MediaTek spi-mem controller This patch adds support for spi-mem controller found on newer MediaTek SoCs This controller supports Single/Dual/Quad SPI mode. diff --git a/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch b/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch index c2bc33cdaa..a9abefa940 100644 --- a/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch +++ b/package/boot/uboot-mediatek/patches/002-0017-i2c-add-support-for-MediaTek-I2C-interface.patch @@ -1,7 +1,7 @@ -From de6f2293ab087f405dbcf7b8df45d1f9b03fc091 Mon Sep 17 00:00:00 2001 +From 987dc8d079cd399e753e10fce12d526b42f90ed0 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Wed, 27 Jul 2022 17:16:38 +0800 -Subject: [PATCH 17/31] i2c: add support for MediaTek I2C interface +Date: Wed, 31 Aug 2022 19:04:47 +0800 +Subject: [PATCH 17/32] i2c: add support for MediaTek I2C interface This patch adds support for MediaTek I2C interface diff --git a/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch b/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch index 378078882e..c87f17f6ef 100644 --- a/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch +++ b/package/boot/uboot-mediatek/patches/002-0018-arm-dts-mt7622-add-i2c-support.patch @@ -1,7 +1,7 @@ -From 9ae337317d5634569bda83dfc5e0658fce34b1e2 Mon Sep 17 00:00:00 2001 +From ceb4b900586299b12e2c8edffecef1d09b57eb30 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Mon, 25 Jul 2022 16:30:30 +0800 -Subject: [PATCH 18/31] arm: dts: mt7622: add i2c support +Date: Wed, 31 Aug 2022 19:04:49 +0800 +Subject: [PATCH 18/32] arm: dts: mt7622: add i2c support Add both hardware and software i2c support for mt7622. diff --git a/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch b/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch index 385ec1395b..b4b38f26a4 100644 --- a/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch +++ b/package/boot/uboot-mediatek/patches/002-0019-dt-bindings-pinctrl-mediatek-add-a-header-for-common.patch @@ -1,7 +1,7 @@ -From 920ba7b9ba1787fd03dad7a5bdc894073936c197 Mon Sep 17 00:00:00 2001 +From e1c55c0ad21daafcb3551b4f5286c1e11c51acc3 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Thu, 28 Jul 2022 09:37:26 +0800 -Subject: [PATCH 19/31] dt-bindings: pinctrl: mediatek: add a header for common +Date: Wed, 31 Aug 2022 19:04:51 +0800 +Subject: [PATCH 19/32] dt-bindings: pinctrl: mediatek: add a header for common pinconf parameters This patch adds a pinctrl header for common pinconf parameters such as diff --git a/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch b/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch index 809b3cbc9b..f4bc27f93d 100644 --- a/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0020-pinctrl-mediatek-add-pinctrl-driver-for-MT7981-SoC.patch @@ -1,7 +1,7 @@ -From 49e7b1e01cf80437c7e22f8b6579d4a81e7f8a3a Mon Sep 17 00:00:00 2001 +From 95df7f4bfacf810be4f94112ab2a4215f6de288d Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Thu, 28 Jul 2022 09:57:58 +0800 -Subject: [PATCH 20/31] pinctrl: mediatek: add pinctrl driver for MT7981 SoC +Date: Wed, 31 Aug 2022 19:04:55 +0800 +Subject: [PATCH 20/32] pinctrl: mediatek: add pinctrl driver for MT7981 SoC This patch adds pinctrl and gpio support for MT7981 SoC diff --git a/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch b/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch index d0675ed4f8..56bb68c8b6 100644 --- a/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch +++ b/package/boot/uboot-mediatek/patches/002-0021-pinctrl-mediatek-add-pinctrl-driver-for-MT7986-SoC.patch @@ -1,7 +1,7 @@ -From a018800db986d63cf95b0779ebb33b5e246072a7 Mon Sep 17 00:00:00 2001 +From 201880cacf1498dd4c6749780163157148d0445d Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Thu, 28 Jul 2022 10:01:00 +0800 -Subject: [PATCH 21/31] pinctrl: mediatek: add pinctrl driver for MT7986 SoC +Date: Wed, 31 Aug 2022 19:04:57 +0800 +Subject: [PATCH 21/32] pinctrl: mediatek: add pinctrl driver for MT7986 SoC This patch adds pinctrl and gpio support for MT7986 SoC diff --git a/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch b/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch index c26fc8090e..b9f0954401 100644 --- a/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch +++ b/package/boot/uboot-mediatek/patches/002-0022-clk-mediatek-add-CLK_BYPASS_XTAL-flag-to-allow-bypas.patch @@ -1,7 +1,7 @@ -From 7f6c8bdfe020c45c398c01b417460e3319476606 Mon Sep 17 00:00:00 2001 +From 907d65c5020fefc9944ec57a9e0bd66dc648823e Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 10:43:39 +0800 -Subject: [PATCH 22/31] clk: mediatek: add CLK_BYPASS_XTAL flag to allow +Date: Wed, 31 Aug 2022 19:04:59 +0800 +Subject: [PATCH 22/32] clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock The mtk clock framework in u-boot uses array index for searching clock @@ -22,26 +22,20 @@ with ID=0 to call mtk_topckgen_get_mux_rate. Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- - drivers/clk/mediatek/clk-mtk.c | 5 ++++- + drivers/clk/mediatek/clk-mtk.c | 4 +++- drivers/clk/mediatek/clk-mtk.h | 6 ++++++ - 2 files changed, 10 insertions(+), 1 deletion(-) + 2 files changed, 9 insertions(+), 1 deletion(-) --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c -@@ -314,12 +314,15 @@ static ulong mtk_topckgen_get_mux_rate(s - struct mtk_clk_priv *priv = dev_get_priv(clk->dev); - const struct mtk_composite *mux = &priv->tree->muxes[off]; - u32 index; -+ u32 flag = 0; - - index = readl(priv->base + mux->mux_reg); +@@ -319,7 +319,9 @@ static ulong mtk_topckgen_get_mux_rate(s index &= mux->mux_mask << mux->mux_shift; index = index >> mux->mux_shift; - if (mux->parent[index]) -+ if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL) -+ flag = 1; -+ if (mux->parent[index] > 0 || flag == 1) ++ if (mux->parent[index] > 0 || ++ (mux->parent[index] == CLK_XTAL && ++ priv->tree->flags & CLK_BYPASS_XTAL)) return mtk_clk_find_parent_rate(clk, mux->parent[index], NULL); diff --git a/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch b/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch index 41600a96b5..c8af7e3191 100644 --- a/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch +++ b/package/boot/uboot-mediatek/patches/002-0023-clk-mediatek-add-support-to-configure-clock-driver-p.patch @@ -1,7 +1,7 @@ -From cd4d6be5ed0488de2e0df9c388d89ad93d781caa Mon Sep 17 00:00:00 2001 +From 50859bea6a3334834b8250e7e5406507f0d0918a Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 10:57:05 +0800 -Subject: [PATCH 23/31] clk: mediatek: add support to configure clock driver +Date: Wed, 31 Aug 2022 19:05:06 +0800 +Subject: [PATCH 23/32] clk: mediatek: add support to configure clock driver parent This patch adds support for a clock node to configure its parent clock @@ -50,14 +50,14 @@ Signed-off-by: Weijie Gao break; case CLK_PARENT_TOPCKGEN: rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); -@@ -322,9 +316,18 @@ static ulong mtk_topckgen_get_mux_rate(s +@@ -321,9 +315,18 @@ static ulong mtk_topckgen_get_mux_rate(s - if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL) - flag = 1; -- if (mux->parent[index] > 0 || flag == 1) + if (mux->parent[index] > 0 || + (mux->parent[index] == CLK_XTAL && +- priv->tree->flags & CLK_BYPASS_XTAL)) - return mtk_clk_find_parent_rate(clk, mux->parent[index], - NULL); -+ if (mux->parent[index] > 0 || flag == 1) { ++ priv->tree->flags & CLK_BYPASS_XTAL)) { + switch (mux->flags & CLK_PARENT_MASK) { + case CLK_PARENT_APMIXED: + return mtk_clk_find_parent_rate(clk, mux->parent[index], @@ -72,7 +72,7 @@ Signed-off-by: Weijie Gao return priv->tree->xtal_rate; } -@@ -343,7 +346,7 @@ static ulong mtk_topckgen_get_rate(struc +@@ -342,7 +345,7 @@ static ulong mtk_topckgen_get_rate(struc priv->tree->muxes_offs); } @@ -81,7 +81,7 @@ Signed-off-by: Weijie Gao { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux; -@@ -376,7 +379,7 @@ static int mtk_topckgen_enable(struct cl +@@ -375,7 +378,7 @@ static int mtk_topckgen_enable(struct cl return 0; } @@ -90,7 +90,7 @@ Signed-off-by: Weijie Gao { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); const struct mtk_composite *mux; -@@ -402,7 +405,7 @@ static int mtk_topckgen_disable(struct c +@@ -401,7 +404,7 @@ static int mtk_topckgen_disable(struct c return 0; } @@ -99,7 +99,7 @@ Signed-off-by: Weijie Gao { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -474,19 +477,7 @@ static ulong mtk_clk_gate_get_rate(struc +@@ -473,19 +476,7 @@ static ulong mtk_clk_gate_get_rate(struc struct mtk_cg_priv *priv = dev_get_priv(clk->dev); const struct mtk_gate *gate = &priv->gates[clk->id]; @@ -120,7 +120,7 @@ Signed-off-by: Weijie Gao } const struct clk_ops mtk_clk_apmixedsys_ops = { -@@ -497,10 +488,10 @@ const struct clk_ops mtk_clk_apmixedsys_ +@@ -496,10 +487,10 @@ const struct clk_ops mtk_clk_apmixedsys_ }; const struct clk_ops mtk_clk_topckgen_ops = { @@ -134,7 +134,7 @@ Signed-off-by: Weijie Gao }; const struct clk_ops mtk_clk_gate_ops = { -@@ -513,11 +504,22 @@ int mtk_common_clk_init(struct udevice * +@@ -512,11 +503,22 @@ int mtk_common_clk_init(struct udevice * const struct mtk_clk_tree *tree) { struct mtk_clk_priv *priv = dev_get_priv(dev); @@ -157,7 +157,7 @@ Signed-off-by: Weijie Gao priv->tree = tree; return 0; -@@ -528,11 +530,22 @@ int mtk_common_clk_gate_init(struct udev +@@ -527,11 +529,22 @@ int mtk_common_clk_gate_init(struct udev const struct mtk_gate *gates) { struct mtk_cg_priv *priv = dev_get_priv(dev); diff --git a/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch b/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch index f84fdec2b4..6475dde388 100644 --- a/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch +++ b/package/boot/uboot-mediatek/patches/002-0024-clk-mediatek-add-infrasys-clock-mux-support.patch @@ -1,16 +1,16 @@ -From e9c0c2ebd346aa578007c2aa88fc0974af6afb40 Mon Sep 17 00:00:00 2001 +From c53d249df9a75f77f5d0abb986a8913bc13070d0 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 11:14:33 +0800 -Subject: [PATCH 24/31] clk: mediatek: add infrasys clock mux support +Date: Wed, 31 Aug 2022 19:05:09 +0800 +Subject: [PATCH 24/32] clk: mediatek: add infrasys clock mux support This patch adds infrasys clock mux support for mediatek clock drivers. Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- - drivers/clk/mediatek/clk-mtk.c | 72 ++++++++++++++++++++++++++++++++++ + drivers/clk/mediatek/clk-mtk.c | 71 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 4 +- - 2 files changed, 75 insertions(+), 1 deletion(-) + 2 files changed, 74 insertions(+), 1 deletion(-) --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -39,7 +39,7 @@ Signed-off-by: Weijie Gao static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -332,6 +350,34 @@ static ulong mtk_topckgen_get_mux_rate(s +@@ -331,6 +349,33 @@ static ulong mtk_topckgen_get_mux_rate(s return priv->tree->xtal_rate; } @@ -48,15 +48,14 @@ Signed-off-by: Weijie Gao + struct mtk_clk_priv *priv = dev_get_priv(clk->dev); + const struct mtk_composite *mux = &priv->tree->muxes[off]; + u32 index; -+ u32 flag; + + index = readl(priv->base + mux->mux_reg); + index &= mux->mux_mask << mux->mux_shift; + index = index >> mux->mux_shift; + -+ if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL) -+ flag = 1; -+ if (mux->parent[index] > 0 || flag == 1) { ++ if (mux->parent[index] > 0 || ++ (mux->parent[index] == CLK_XTAL && ++ priv->tree->flags & CLK_BYPASS_XTAL)) { + switch (mux->flags & CLK_PARENT_MASK) { + case CLK_PARENT_TOPCKGEN: + return mtk_clk_find_parent_rate(clk, mux->parent[index], @@ -74,7 +73,7 @@ Signed-off-by: Weijie Gao static ulong mtk_topckgen_get_rate(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -346,6 +392,25 @@ static ulong mtk_topckgen_get_rate(struc +@@ -345,6 +390,25 @@ static ulong mtk_topckgen_get_rate(struc priv->tree->muxes_offs); } @@ -100,7 +99,7 @@ Signed-off-by: Weijie Gao static int mtk_clk_mux_enable(struct clk *clk) { struct mtk_clk_priv *priv = dev_get_priv(clk->dev); -@@ -494,6 +559,13 @@ const struct clk_ops mtk_clk_topckgen_op +@@ -493,6 +557,13 @@ const struct clk_ops mtk_clk_topckgen_op .set_parent = mtk_common_clk_set_parent, }; diff --git a/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch b/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch index 37619d22f0..b03ca7384f 100644 --- a/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch +++ b/package/boot/uboot-mediatek/patches/002-0025-clk-mediatek-add-CLK_XTAL-support-for-clock-driver.patch @@ -1,10 +1,10 @@ -From cf70b726c9844bb5d1ba4bc3c202c5ab3ba4d421 Mon Sep 17 00:00:00 2001 +From 0a2cd71e3b16eaa8797b5eec78356970186e552e Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 11:15:35 +0800 -Subject: [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver +Date: Wed, 31 Aug 2022 19:05:11 +0800 +Subject: [PATCH 25/32] clk: mediatek: add CLK_XTAL support for clock driver -This add CLK_XTAL macro and flag to mediatek clock driver common part, -to make thi SoC that has clock directlly connect to XTAL working. +This adds the CLK_XTAL macro/flag to allow modeling clocks which are +directly connected to the xtal clock. Signed-off-by: Weijie Gao --- diff --git a/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch index f42e497141..da2506d93e 100644 --- a/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch +++ b/package/boot/uboot-mediatek/patches/002-0026-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch @@ -1,11 +1,12 @@ -From ba4acf55044a8a11fc7e11a558a8a93e3c126391 Mon Sep 17 00:00:00 2001 +From 54b66dd24310dba4798caa6e4c02b8571f522602 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 11:21:59 +0800 -Subject: [PATCH 26/31] clk: mediatek: add clock driver support for MediaTek +Date: Wed, 31 Aug 2022 19:05:13 +0800 +Subject: [PATCH 26/32] clk: mediatek: add clock driver support for MediaTek MT7986 SoC This patch adds clock driver support for MediaTek MT7986 SoC +Reviewed-by: Sean Anderson Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- diff --git a/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch b/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch index 26084a6535..cc90fa1944 100644 --- a/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch +++ b/package/boot/uboot-mediatek/patches/002-0027-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch @@ -1,11 +1,12 @@ -From 79bca945dbfafcd08d71437b11e8ee57d64b4305 Mon Sep 17 00:00:00 2001 +From d525836896235c4678f6144cc4608d5b15e02660 Mon Sep 17 00:00:00 2001 From: Weijie Gao -Date: Fri, 29 Jul 2022 11:22:51 +0800 -Subject: [PATCH 27/31] clk: mediatek: add clock driver support for MediaTek +Date: Wed, 31 Aug 2022 19:05:16 +0800 +Subject: [PATCH 27/32] clk: mediatek: add clock driver support for MediaTek MT7981 SoC This patch adds clock driver support for MediaTek MT7981 SoC +Reviewed-by: Sean Anderson Reviewed-by: Simon Glass Signed-off-by: Weijie Gao --- diff --git a/package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch b/package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch new file mode 100644 index 0000000000..01871781f0 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/002-0028-cpu-add-basic-cpu-driver-for-MediaTek-ARM-chips.patch @@ -0,0 +1,133 @@ +From e3c707d23a3a5bc1ba9b8c03731a32c3714ae56a Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 31 Aug 2022 19:05:20 +0800 +Subject: [PATCH 28/32] cpu: add basic cpu driver for MediaTek ARM chips + +Add basic CPU driver used to retrieve CPU model information. + +Signed-off-by: Weijie Gao +--- + drivers/cpu/Makefile | 1 + + drivers/cpu/mtk_cpu.c | 106 ++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 107 insertions(+) + create mode 100644 drivers/cpu/mtk_cpu.c + +--- a/drivers/cpu/Makefile ++++ b/drivers/cpu/Makefile +@@ -9,6 +9,7 @@ obj-$(CONFIG_CPU) += cpu-uclass.o + obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o + obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o + obj-$(CONFIG_ARCH_AT91) += at91_cpu.o ++obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o + obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o + obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o + obj-$(CONFIG_SANDBOX) += cpu_sandbox.o +--- /dev/null ++++ b/drivers/cpu/mtk_cpu.c +@@ -0,0 +1,106 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2022 MediaTek Inc. All rights reserved. ++ * ++ * Author: Weijie Gao ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++struct mtk_cpu_plat { ++ void __iomem *hwver_base; ++}; ++ ++static int mtk_cpu_get_desc(const struct udevice *dev, char *buf, int size) ++{ ++ struct mtk_cpu_plat *plat = dev_get_plat(dev); ++ ++ snprintf(buf, size, "MediaTek MT%04X", readl(plat->hwver_base)); ++ ++ return 0; ++} ++ ++static int mtk_cpu_get_count(const struct udevice *dev) ++{ ++ return 1; ++} ++ ++static int mtk_cpu_get_vendor(const struct udevice *dev, char *buf, int size) ++{ ++ snprintf(buf, size, "MediaTek"); ++ ++ return 0; ++} ++ ++static int mtk_cpu_probe(struct udevice *dev) ++{ ++ struct mtk_cpu_plat *plat = dev_get_plat(dev); ++ const void *fdt = gd->fdt_blob, *reg; ++ int offset, parent, len, na, ns; ++ u64 addr; ++ ++ if (!fdt) ++ return -ENODEV; ++ ++ offset = fdt_path_offset(fdt, "/hwver"); ++ if (offset < 0) ++ return -ENODEV; ++ ++ parent = fdt_parent_offset(fdt, offset); ++ if (parent < 0) ++ return -ENODEV; ++ ++ na = fdt_address_cells(fdt, parent); ++ if (na < 1) ++ return -ENODEV; ++ ++ ns = fdt_size_cells(gd->fdt_blob, parent); ++ if (ns < 0) ++ return -ENODEV; ++ ++ reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); ++ if (!reg) ++ return -ENODEV; ++ ++ if (ns) ++ addr = fdt_translate_address(fdt, offset, reg); ++ else ++ addr = fdt_read_number(reg, na); ++ ++ plat->hwver_base = map_sysmem(addr, 0); ++ if (!plat->hwver_base) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static const struct cpu_ops mtk_cpu_ops = { ++ .get_desc = mtk_cpu_get_desc, ++ .get_count = mtk_cpu_get_count, ++ .get_vendor = mtk_cpu_get_vendor, ++}; ++ ++static const struct udevice_id mtk_cpu_ids[] = { ++ { .compatible = "arm,cortex-a7" }, ++ { .compatible = "arm,cortex-a53" }, ++ { .compatible = "arm,cortex-a73" }, ++ { /* sentinel */ } ++}; ++ ++U_BOOT_DRIVER(cpu_mtk) = { ++ .name = "mtk-cpu", ++ .id = UCLASS_CPU, ++ .of_match = mtk_cpu_ids, ++ .ops = &mtk_cpu_ops, ++ .probe = mtk_cpu_probe, ++ .plat_auto = sizeof(struct mtk_cpu_plat), ++ .flags = DM_FLAG_PRE_RELOC, ++}; diff --git a/package/boot/uboot-mediatek/patches/002-0028-tools-mtk_image-split-gfh-header-verification-into-a.patch b/package/boot/uboot-mediatek/patches/002-0028-tools-mtk_image-split-gfh-header-verification-into-a.patch deleted file mode 100644 index c8747ae154..0000000000 --- a/package/boot/uboot-mediatek/patches/002-0028-tools-mtk_image-split-gfh-header-verification-into-a.patch +++ /dev/null @@ -1,89 +0,0 @@ -From b6bb61fd3818f4a3025fedbe4d15dbeeaef6ee82 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 2 Aug 2022 17:21:34 +0800 -Subject: [PATCH 28/31] tools: mtk_image: split gfh header verification into a - new function - -The verification code of gfh header for NAND and non-NAND are identical. -It's better to define a individual function to reduce redundancy. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - tools/mtk_image.c | 51 +++++++++++++++++++---------------------------- - 1 file changed, 21 insertions(+), 30 deletions(-) - ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -480,6 +480,25 @@ static int mtk_image_vrec_header(struct - return SHA256_SUM_LEN; - } - -+static int mtk_image_verify_gfh(struct gfh_header *gfh, uint32_t type, int print) -+{ -+ if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -+ return -1; -+ -+ if (le32_to_cpu(gfh->file_info.flash_type) != type) -+ return -1; -+ -+ if (print) -+ printf("Load Address: %08x\n", -+ le32_to_cpu(gfh->file_info.load_addr) + -+ le32_to_cpu(gfh->file_info.jump_offset)); -+ -+ if (print) -+ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -+ -+ return 0; -+} -+ - static int mtk_image_verify_gen_header(const uint8_t *ptr, int print) - { - union gen_boot_header *gbh = (union gen_boot_header *)ptr; -@@ -542,21 +561,7 @@ static int mtk_image_verify_gen_header(c - - gfh = (struct gfh_header *)(ptr + gfh_offset); - -- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -- return -1; -- -- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_GEN) -- return -1; -- -- if (print) -- printf("Load Address: %08x\n", -- le32_to_cpu(gfh->file_info.load_addr) + -- le32_to_cpu(gfh->file_info.jump_offset)); -- -- if (print) -- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -- -- return 0; -+ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_GEN, print); - } - - static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) -@@ -610,21 +615,7 @@ static int mtk_image_verify_nand_header( - - gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); - -- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) -- return -1; -- -- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_NAND) -- return -1; -- -- if (print) -- printf("Load Address: %08x\n", -- le32_to_cpu(gfh->file_info.load_addr) + -- le32_to_cpu(gfh->file_info.jump_offset)); -- -- if (print) -- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); -- -- return 0; -+ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); - } - - static uint32_t crc32be_cal(const void *data, size_t length) diff --git a/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch b/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch new file mode 100644 index 0000000000..54c92eaaf7 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-gfh-header-verification-into-a.patch @@ -0,0 +1,89 @@ +From 1c9174cbf57ddc75bb5a25b2563333d974fd1a55 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 31 Aug 2022 19:05:22 +0800 +Subject: [PATCH 29/32] tools: mtk_image: split gfh header verification into a + new function + +The verification code of gfh header for NAND and non-NAND are identical. +It's better to define a individual function to reduce redundancy. + +Reviewed-by: Simon Glass +Signed-off-by: Weijie Gao +--- + tools/mtk_image.c | 51 +++++++++++++++++++---------------------------- + 1 file changed, 21 insertions(+), 30 deletions(-) + +--- a/tools/mtk_image.c ++++ b/tools/mtk_image.c +@@ -480,6 +480,25 @@ static int mtk_image_vrec_header(struct + return SHA256_SUM_LEN; + } + ++static int mtk_image_verify_gfh(struct gfh_header *gfh, uint32_t type, int print) ++{ ++ if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) ++ return -1; ++ ++ if (le32_to_cpu(gfh->file_info.flash_type) != type) ++ return -1; ++ ++ if (print) ++ printf("Load Address: %08x\n", ++ le32_to_cpu(gfh->file_info.load_addr) + ++ le32_to_cpu(gfh->file_info.jump_offset)); ++ ++ if (print) ++ printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); ++ ++ return 0; ++} ++ + static int mtk_image_verify_gen_header(const uint8_t *ptr, int print) + { + union gen_boot_header *gbh = (union gen_boot_header *)ptr; +@@ -542,21 +561,7 @@ static int mtk_image_verify_gen_header(c + + gfh = (struct gfh_header *)(ptr + gfh_offset); + +- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) +- return -1; +- +- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_GEN) +- return -1; +- +- if (print) +- printf("Load Address: %08x\n", +- le32_to_cpu(gfh->file_info.load_addr) + +- le32_to_cpu(gfh->file_info.jump_offset)); +- +- if (print) +- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); +- +- return 0; ++ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_GEN, print); + } + + static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) +@@ -610,21 +615,7 @@ static int mtk_image_verify_nand_header( + + gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); + +- if (strcmp(gfh->file_info.name, GFH_FILE_INFO_NAME)) +- return -1; +- +- if (le32_to_cpu(gfh->file_info.flash_type) != GFH_FLASH_TYPE_NAND) +- return -1; +- +- if (print) +- printf("Load Address: %08x\n", +- le32_to_cpu(gfh->file_info.load_addr) + +- le32_to_cpu(gfh->file_info.jump_offset)); +- +- if (print) +- printf("Architecture: %s\n", is_arm64_image ? "ARM64" : "ARM"); +- +- return 0; ++ return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); + } + + static uint32_t crc32be_cal(const void *data, size_t length) diff --git a/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-the-code-of-generating-NAND-he.patch b/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-the-code-of-generating-NAND-he.patch deleted file mode 100644 index 9a5332f695..0000000000 --- a/package/boot/uboot-mediatek/patches/002-0029-tools-mtk_image-split-the-code-of-generating-NAND-he.patch +++ /dev/null @@ -1,821 +0,0 @@ -From 20ebf03eab571b25e9f62b2764ab84932111dcd6 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Tue, 2 Aug 2022 17:23:57 +0800 -Subject: [PATCH 29/31] tools: mtk_image: split the code of generating NAND - header into a new file - -The predefined NAND headers take too much spaces in the mtk_image.c. -Moving them into a new file can significantly improve the readability of -both mtk_image.c and the new mtk_nand_headers.c. - -This is a preparation for adding more NAND headers. - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - tools/Makefile | 1 + - tools/mtk_image.c | 305 ++++++--------------------------------- - tools/mtk_image.h | 25 ---- - tools/mtk_nand_headers.c | 286 ++++++++++++++++++++++++++++++++++++ - tools/mtk_nand_headers.h | 61 ++++++++ - 5 files changed, 389 insertions(+), 289 deletions(-) - create mode 100644 tools/mtk_nand_headers.c - create mode 100644 tools/mtk_nand_headers.h - ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -147,6 +147,7 @@ dumpimage-mkimage-objs := aisimage.o \ - gpimage.o \ - gpimage-common.o \ - mtk_image.o \ -+ mtk_nand_headers.o \ - $(ECDSA_OBJS-y) \ - $(RSA_OBJS-y) \ - $(AES_OBJS-y) ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -12,216 +12,7 @@ - #include - #include "imagetool.h" - #include "mtk_image.h" -- --/* NAND header for SPI-NAND with 2KB page + 64B spare */ --static const union nand_boot_header snand_hdr_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, -- 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, -- 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, -- 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 -- } --}; -- --/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ --static const union nand_boot_header snand_hdr_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, -- 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, -- 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, -- 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 -- } --}; -- --/* NAND header for SPI-NAND with 4KB page + 256B spare */ --static const union nand_boot_header snand_hdr_4k_256_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, -- 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, -- 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, -- 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_1gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, -- 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, -- 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, -- 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_2gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, -- 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, -- 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, -- 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ --static const union nand_boot_header nand_hdr_4gb_2k_64_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, -- 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, -- 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, -- 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ --static const union nand_boot_header nand_hdr_2gb_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, -- 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, -- 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, -- 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 -- } --}; -- --/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ --static const union nand_boot_header nand_hdr_4gb_2k_128_data = { -- .data = { -- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -- 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, -- 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, -- 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, -- 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 -- } --}; -- --static const struct nand_header_type { -- const char *name; -- const union nand_boot_header *data; --} nand_headers[] = { -- { -- .name = "2k+64", -- .data = &snand_hdr_2k_64_data -- }, { -- .name = "2k+120", -- .data = &snand_hdr_2k_128_data -- }, { -- .name = "2k+128", -- .data = &snand_hdr_2k_128_data -- }, { -- .name = "4k+256", -- .data = &snand_hdr_4k_256_data -- }, { -- .name = "1g:2k+64", -- .data = &nand_hdr_1gb_2k_64_data -- }, { -- .name = "2g:2k+64", -- .data = &nand_hdr_2gb_2k_64_data -- }, { -- .name = "4g:2k+64", -- .data = &nand_hdr_4gb_2k_64_data -- }, { -- .name = "2g:2k+128", -- .data = &nand_hdr_2gb_2k_128_data -- }, { -- .name = "4g:2k+128", -- .data = &nand_hdr_4gb_2k_128_data -- } --}; -+#include "mtk_nand_headers.h" - - static const struct brom_img_type { - const char *name; -@@ -264,6 +55,7 @@ static uint32_t crc32tbl[256]; - - /* NAND header selected by user */ - static const union nand_boot_header *hdr_nand; -+static uint32_t hdr_nand_size; - - /* GFH header + 2 * 4KB pages of NAND */ - static char hdr_tmp[sizeof(struct gfh_header) + 0x2000]; -@@ -402,12 +194,7 @@ static int mtk_brom_parse_imagename(cons - } - - /* parse nand header type */ -- for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { -- if (!strcmp(nand_headers[i].name, nandinfo)) { -- hdr_nand = nand_headers[i].data; -- break; -- } -- } -+ hdr_nand = mtk_nand_header_find(nandinfo); - - /* parse device header offset */ - if (hdr_offs && hdr_offs[0]) -@@ -432,6 +219,9 @@ static int mtk_brom_parse_imagename(cons - return -EINVAL; - } - -+ if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) -+ hdr_nand_size = mtk_nand_header_size(hdr_nand); -+ - return 0; - } - -@@ -468,7 +258,7 @@ static int mtk_image_vrec_header(struct - } - - if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) -- tparams->header_size = 2 * le16_to_cpu(hdr_nand->pagesize); -+ tparams->header_size = hdr_nand_size; - else - tparams->header_size = sizeof(struct gen_device_header); - -@@ -566,16 +356,17 @@ static int mtk_image_verify_gen_header(c - - static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - struct brom_layout_header *bh; -+ struct nand_header_info info; - struct gfh_header *gfh; - const char *bootmedia; -+ int ret; - -- if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || -- strcmp(nh->id, NAND_BOOT_ID)) -- return -1; -+ ret = mtk_nand_header_info(ptr, &info); -+ if (ret < 0) -+ return ret; - -- bh = (struct brom_layout_header *)(ptr + le16_to_cpu(nh->pagesize)); -+ bh = (struct brom_layout_header *)(ptr + info.page_size); - - if (strcmp(bh->name, BRLYT_NAME)) - return -1; -@@ -586,34 +377,23 @@ static int mtk_image_verify_nand_header( - if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) - bootmedia = "Parallel NAND"; - else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) -- bootmedia = "Serial NAND"; -+ bootmedia = "Serial NAND (SNFI/AP)"; - else - return -1; - } - - if (print) { -- printf("Boot Media: %s\n", bootmedia); -- -- if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) { -- uint64_t capacity = -- (uint64_t)le16_to_cpu(nh->numblocks) * -- (uint64_t)le16_to_cpu(nh->pages_of_block) * -- (uint64_t)le16_to_cpu(nh->pagesize) * 8; -- printf("Capacity: %dGb\n", -- (uint32_t)(capacity >> 30)); -- } -+ printf("Boot Media: %s\n", bootmedia); - -- if (le16_to_cpu(nh->pagesize) >= 1024) -- printf("Page Size: %dKB\n", -- le16_to_cpu(nh->pagesize) >> 10); -+ if (info.page_size >= 1024) -+ printf("Page Size: %dKB\n", info.page_size >> 10); - else -- printf("Page Size: %dB\n", -- le16_to_cpu(nh->pagesize)); -+ printf("Page Size: %dB\n", info.page_size); - -- printf("Spare Size: %dB\n", le16_to_cpu(nh->oobsize)); -+ printf("Spare Size: %dB\n", info.spare_size); - } - -- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); -+ gfh = (struct gfh_header *)(ptr + info.gfh_offset); - - return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); - } -@@ -713,7 +493,7 @@ static int mtk_image_verify_header(unsig - if (image_get_magic(hdr) == IH_MAGIC) - return mtk_image_verify_mt7621_header(ptr, 0); - -- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ if (is_mtk_nand_header(ptr)) - return mtk_image_verify_nand_header(ptr, 0); - else - return mtk_image_verify_gen_header(ptr, 0); -@@ -739,7 +519,7 @@ static void mtk_image_print_header(const - return; - } - -- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ if (is_mtk_nand_header(ptr)) - mtk_image_verify_nand_header(ptr, 1); - else - mtk_image_verify_gen_header(ptr, 1); -@@ -870,36 +650,33 @@ static void mtk_image_set_gen_header(voi - static void mtk_image_set_nand_header(void *ptr, off_t filesize, - uint32_t loadaddr) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - struct brom_layout_header *brlyt; - struct gfh_header *gfh; -- uint32_t payload_pages; -- int i; -+ uint32_t payload_pages, nand_page_size; - -- /* NAND device header, repeat 4 times */ -- for (i = 0; i < 4; i++) -- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ /* NAND header */ -+ nand_page_size = mtk_nand_header_put(hdr_nand, ptr); - -- /* BRLYT header */ -- payload_pages = (filesize + le16_to_cpu(hdr_nand->pagesize) - 1) / -- le16_to_cpu(hdr_nand->pagesize); -- brlyt = (struct brom_layout_header *) -- (ptr + le16_to_cpu(hdr_nand->pagesize)); -- put_brom_layout_header(brlyt, hdr_media); -- brlyt->header_size = cpu_to_le32(2); -- brlyt->total_size = cpu_to_le32(payload_pages); -- brlyt->header_size_2 = brlyt->header_size; -- brlyt->total_size_2 = brlyt->total_size; -- brlyt->unused = cpu_to_le32(1); -+ if (nand_page_size) { -+ /* BRLYT header */ -+ payload_pages = (filesize + nand_page_size - 1) / -+ nand_page_size; -+ brlyt = (struct brom_layout_header *)(ptr + nand_page_size); -+ put_brom_layout_header(brlyt, hdr_media); -+ brlyt->header_size = cpu_to_le32(2); -+ brlyt->total_size = cpu_to_le32(payload_pages); -+ brlyt->header_size_2 = brlyt->header_size; -+ brlyt->total_size_2 = brlyt->total_size; -+ brlyt->unused = cpu_to_le32(1); -+ } - - /* GFH header */ -- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(hdr_nand->pagesize)); -- put_ghf_header(gfh, filesize, 2 * le16_to_cpu(hdr_nand->pagesize), -- loadaddr, GFH_FLASH_TYPE_NAND); -+ gfh = (struct gfh_header *)(ptr + hdr_nand_size); -+ put_ghf_header(gfh, filesize, hdr_nand_size, loadaddr, -+ GFH_FLASH_TYPE_NAND); - - /* Generate SHA256 hash */ -- put_hash((uint8_t *)gfh, -- filesize - 2 * le16_to_cpu(hdr_nand->pagesize) - SHA256_SUM_LEN); -+ put_hash((uint8_t *)gfh, filesize - hdr_nand_size - SHA256_SUM_LEN); - } - - static void mtk_image_set_mt7621_header(void *ptr, off_t filesize, ---- a/tools/mtk_image.h -+++ b/tools/mtk_image.h -@@ -26,31 +26,6 @@ union gen_boot_header { - #define SF_BOOT_NAME "SF_BOOT" - #define SDMMC_BOOT_NAME "SDMMC_BOOT" - --/* Header for NAND */ --union nand_boot_header { -- struct { -- char name[12]; -- char version[4]; -- char id[8]; -- uint16_t ioif; -- uint16_t pagesize; -- uint16_t addrcycles; -- uint16_t oobsize; -- uint16_t pages_of_block; -- uint16_t numblocks; -- uint16_t writesize_shift; -- uint16_t erasesize_shift; -- uint8_t dummy[60]; -- uint8_t ecc_parity[28]; -- }; -- -- uint8_t data[0x80]; --}; -- --#define NAND_BOOT_NAME "BOOTLOADER!" --#define NAND_BOOT_VERSION "V006" --#define NAND_BOOT_ID "NFIINFO" -- - /* BootROM layout header */ - struct brom_layout_header { - char name[8]; ---- /dev/null -+++ b/tools/mtk_nand_headers.c -@@ -0,0 +1,286 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * MediaTek BootROM NAND header definitions -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Weijie Gao -+ */ -+ -+#include -+#include -+#include "imagetool.h" -+#include "mtk_image.h" -+#include "mtk_nand_headers.h" -+ -+/* NAND header for SPI-NAND with 2KB page + 64B spare */ -+static const union nand_boot_header snand_hdr_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, -+ 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, -+ 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, -+ 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ -+static const union nand_boot_header snand_hdr_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, -+ 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, -+ 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, -+ 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for SPI-NAND with 4KB page + 256B spare */ -+static const union nand_boot_header snand_hdr_4k_256_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, -+ 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, -+ 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, -+ 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_1gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, -+ 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, -+ 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, -+ 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_2gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, -+ 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, -+ 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, -+ 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ -+static const union nand_boot_header nand_hdr_4gb_2k_64_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, -+ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, -+ 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, -+ 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, -+ 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ -+static const union nand_boot_header nand_hdr_2gb_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, -+ 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, -+ 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, -+ 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 -+ } -+}; -+ -+/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ -+static const union nand_boot_header nand_hdr_4gb_2k_128_data = { -+ .data = { -+ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, -+ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, -+ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, -+ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, -+ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, -+ 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, -+ 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, -+ 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 -+ } -+}; -+ -+static const struct nand_header_type { -+ const char *name; -+ const union nand_boot_header *data; -+} nand_headers[] = { -+ { -+ .name = "2k+64", -+ .data = &snand_hdr_2k_64_data -+ }, { -+ .name = "2k+120", -+ .data = &snand_hdr_2k_128_data -+ }, { -+ .name = "2k+128", -+ .data = &snand_hdr_2k_128_data -+ }, { -+ .name = "4k+256", -+ .data = &snand_hdr_4k_256_data -+ }, { -+ .name = "1g:2k+64", -+ .data = &nand_hdr_1gb_2k_64_data -+ }, { -+ .name = "2g:2k+64", -+ .data = &nand_hdr_2gb_2k_64_data -+ }, { -+ .name = "4g:2k+64", -+ .data = &nand_hdr_4gb_2k_64_data -+ }, { -+ .name = "2g:2k+128", -+ .data = &nand_hdr_2gb_2k_128_data -+ }, { -+ .name = "4g:2k+128", -+ .data = &nand_hdr_4gb_2k_128_data -+ } -+}; -+ -+const union nand_boot_header *mtk_nand_header_find(const char *name) -+{ -+ uint32_t i; -+ -+ for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { -+ if (!strcmp(nand_headers[i].name, name)) -+ return nand_headers[i].data; -+ } -+ -+ return NULL; -+} -+ -+uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) -+{ -+ return 2 * le16_to_cpu(hdr_nand->pagesize); -+} -+ -+static int mtk_nand_header_ap_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union nand_boot_header *nh = (union nand_boot_header *)ptr; -+ -+ if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || -+ strcmp(nh->id, NAND_BOOT_ID)) -+ return -1; -+ -+ info->page_size = le16_to_cpu(nh->pagesize); -+ info->spare_size = le16_to_cpu(nh->oobsize); -+ info->gfh_offset = 2 * info->page_size; -+ -+ return 0; -+} -+ -+int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) -+{ -+ if (!strcmp((char *)ptr, NAND_BOOT_NAME)) -+ return mtk_nand_header_ap_info(ptr, info); -+ -+ return -1; -+} -+ -+bool is_mtk_nand_header(const void *ptr) -+{ -+ struct nand_header_info info; -+ -+ if (mtk_nand_header_info(ptr, &info) >= 0) -+ return true; -+ -+ return false; -+} -+ -+uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) -+{ -+ union nand_boot_header *nh = (union nand_boot_header *)ptr; -+ int i; -+ -+ /* NAND device header, repeat 4 times */ -+ for (i = 0; i < 4; i++) -+ memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ -+ return le16_to_cpu(hdr_nand->pagesize); -+} ---- /dev/null -+++ b/tools/mtk_nand_headers.h -@@ -0,0 +1,61 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * MediaTek BootROM NAND header definitions -+ * -+ * Copyright (C) 2022 MediaTek Inc. -+ * Author: Weijie Gao -+ */ -+ -+#ifndef _MTK_NAND_HEADERS_H -+#define _MTK_NAND_HEADERS_H -+ -+#include -+#include -+ -+struct nand_header_info { -+ uint32_t page_size; -+ uint32_t spare_size; -+ uint32_t gfh_offset; -+}; -+ -+/* AP BROM Header for NAND */ -+union nand_boot_header { -+ struct { -+ char name[12]; -+ char version[4]; -+ char id[8]; -+ uint16_t ioif; /* I/O interface */ -+ uint16_t pagesize; /* NAND page size */ -+ uint16_t addrcycles; /* Address cycles */ -+ uint16_t oobsize; /* NAND page spare size */ -+ uint16_t pages_of_block; /* Pages of one block */ -+ uint16_t numblocks; /* Total blocks of NAND chip */ -+ uint16_t writesize_shift; -+ uint16_t erasesize_shift; -+ uint8_t dummy[60]; -+ uint8_t ecc_parity[28]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0x80]; -+}; -+ -+#define NAND_BOOT_NAME "BOOTLOADER!" -+#define NAND_BOOT_VERSION "V006" -+#define NAND_BOOT_ID "NFIINFO" -+ -+/* Find nand header data by name */ -+const union nand_boot_header *mtk_nand_header_find(const char *name); -+ -+/* Device header size using this nand header */ -+uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); -+ -+/* Get nand info from nand header (page size, spare size, ...) */ -+int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); -+ -+/* Whether given header data is valid */ -+bool is_mtk_nand_header(const void *ptr); -+ -+/* Generate Device header using give nand header */ -+uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); -+ -+#endif /* _MTK_NAND_HEADERS_H */ diff --git a/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-add-support-for-nand-headers-used-by.patch b/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-add-support-for-nand-headers-used-by.patch deleted file mode 100644 index 0ce095998f..0000000000 --- a/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-add-support-for-nand-headers-used-by.patch +++ /dev/null @@ -1,702 +0,0 @@ -From fbf296f9ed5daab70020686e9ba072efe663bbab Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Wed, 3 Aug 2022 11:14:36 +0800 -Subject: [PATCH 30/31] tools: mtk_image: add support for nand headers used by - newer chips - -This patch adds more nand headers in two new types: -1. HSM header, used for spi-nand thru SNFI interface -2. SPIM header, used for spi-nand thru spi-mem interface - -The original nand header is renamed to AP header. - -Signed-off-by: Weijie Gao ---- - tools/mtk_image.c | 23 ++- - tools/mtk_nand_headers.c | 422 +++++++++++++++++++++++++++++++++++++-- - tools/mtk_nand_headers.h | 110 +++++++++- - 3 files changed, 525 insertions(+), 30 deletions(-) - ---- a/tools/mtk_image.c -+++ b/tools/mtk_image.c -@@ -33,6 +33,9 @@ static const struct brom_img_type { - }, { - .name = "snand", - .type = BRLYT_TYPE_SNAND -+ }, { -+ .name = "spim-nand", -+ .type = BRLYT_TYPE_SNAND - } - }; - -@@ -54,7 +57,7 @@ static char lk_name[32] = "U-Boot"; - static uint32_t crc32tbl[256]; - - /* NAND header selected by user */ --static const union nand_boot_header *hdr_nand; -+static const struct nand_header_type *hdr_nand; - static uint32_t hdr_nand_size; - - /* GFH header + 2 * 4KB pages of NAND */ -@@ -366,20 +369,26 @@ static int mtk_image_verify_nand_header( - if (ret < 0) - return ret; - -- bh = (struct brom_layout_header *)(ptr + info.page_size); -+ if (!ret) { -+ bh = (struct brom_layout_header *)(ptr + info.page_size); - -- if (strcmp(bh->name, BRLYT_NAME)) -- return -1; -+ if (strcmp(bh->name, BRLYT_NAME)) -+ return -1; -+ -+ if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) -+ return -1; - -- if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) { -- return -1; -- } else { - if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) - bootmedia = "Parallel NAND"; - else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) - bootmedia = "Serial NAND (SNFI/AP)"; - else - return -1; -+ } else { -+ if (info.snfi) -+ bootmedia = "Serial NAND (SNFI/HSM)"; -+ else -+ bootmedia = "Serial NAND (SPIM)"; - } - - if (print) { ---- a/tools/mtk_nand_headers.c -+++ b/tools/mtk_nand_headers.c -@@ -188,55 +188,346 @@ static const union nand_boot_header nand - } - }; - --static const struct nand_header_type { -+/* HSM BROM NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_2k_64_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x21, 0xD2, 0xEE, 0xF6, -+ 0xAE, 0xDD, 0x5E, 0xC2, 0x82, 0x8E, 0x9A, 0x62, -+ 0x09, 0x8E, 0x80, 0xE2, 0x37, 0x0D, 0xC9, 0xFA, -+ 0xA9, 0xDD, 0xFC, 0x92, 0x34, 0x2A, 0xED, 0x51, -+ 0xA4, 0x1B, 0xF7, 0x63, 0xCC, 0x5A, 0xC7, 0xFB, -+ 0xED, 0x21, 0x02, 0x23, 0x51, 0x31 -+ } -+}; -+ -+/* HSM BROM NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_2k_128_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x71, 0x7f, 0x71, 0xAC, -+ 0x42, 0xD0, 0x5B, 0xD2, 0x12, 0x81, 0x15, 0x0A, -+ 0x0C, 0xD4, 0xF6, 0x32, 0x1E, 0x63, 0xE7, 0x81, -+ 0x8A, 0x7F, 0xDE, 0xF9, 0x4B, 0x91, 0xEC, 0xC2, -+ 0x70, 0x00, 0x7F, 0x57, 0xAF, 0xDC, 0xE4, 0x24, -+ 0x57, 0x09, 0xBC, 0xC5, 0x35, 0xDC -+ } -+}; -+ -+/* HSM BROM NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union hsm_nand_boot_header hsm_nand_hdr_4k_256_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, -+ 0xFF, 0x00, 0x00, 0x00, 0x62, 0x04, 0xD6, 0x1F, -+ 0x2B, 0x57, 0x7A, 0x2D, 0xFE, 0xBB, 0x4A, 0x50, -+ 0xEC, 0xF8, 0x70, 0x1A, 0x44, 0x15, 0xF6, 0xA2, -+ 0x8E, 0xB0, 0xFD, 0xFA, 0xDC, 0xAA, 0x5A, 0x4E, -+ 0xCB, 0x8E, 0xC9, 0x72, 0x08, 0xDC, 0x20, 0xB9, -+ 0x98, 0xC8, 0x82, 0xD8, 0xBE, 0x44 -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_64_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x5F, 0x4B, 0xB2, 0x5B, 0x8B, 0x1C, 0x35, 0xDA, -+ 0x83, 0xE6, 0x6C, 0xC3, 0xFB, 0x8C, 0x78, 0x23, -+ 0xD0, 0x89, 0x24, 0xD9, 0x6C, 0x35, 0x2C, 0x5D, -+ 0x8F, 0xBB, 0xFC, 0x10, 0xD0, 0xE2, 0x22, 0x7D, -+ 0xC8, 0x97, 0x9A, 0xEF, 0xC6, 0xB5, 0xA7, 0x4E, -+ 0x4E, 0x0E -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_128_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0xF8, 0x7E, 0xC1, 0x5D, 0x61, 0x54, 0xEA, 0x9F, -+ 0x5E, 0x66, 0x39, 0x66, 0x21, 0xFF, 0x8C, 0x3B, -+ 0xBE, 0xA7, 0x5A, 0x9E, 0xD7, 0xBD, 0x9E, 0x89, -+ 0xEE, 0x7E, 0x10, 0x31, 0x9A, 0x1D, 0x82, 0x49, -+ 0xA3, 0x4E, 0xD8, 0x47, 0xD7, 0x19, 0xF4, 0x2D, -+ 0x8E, 0x53 -+ } -+}; -+ -+/* HSM2.0 BROM NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union hsm20_nand_boot_header hsm20_nand_hdr_4k_256_data = { -+ .data = { -+ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, -+ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, -+ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, -+ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, -+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x79, 0x01, 0x1F, 0x86, 0x62, 0x6A, 0x43, 0xAE, -+ 0xE6, 0xF8, 0xDD, 0x5B, 0x29, 0xB7, 0xA2, 0x7F, -+ 0x29, 0x72, 0x54, 0x37, 0xBE, 0x50, 0xD4, 0x24, -+ 0xAB, 0x60, 0xF4, 0x44, 0x97, 0x3B, 0x65, 0x21, -+ 0x73, 0x24, 0x1F, 0x93, 0x0E, 0x9E, 0x96, 0x88, -+ 0x78, 0x6C -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 2KB page + 64B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_2k_64_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 2KB page + 128B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_2k_128_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, -+ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+/* SPIM-NAND header for SPI NAND with 4KB page + 256B spare */ -+static const union spim_nand_boot_header spim_nand_hdr_4k_256_data = { -+ .data = { -+ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, -+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, -+ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, -+ 0x40, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x20, 0x30, -+ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -+ } -+}; -+ -+struct nand_header_type { - const char *name; -- const union nand_boot_header *data; -+ enum nand_boot_header_type type; -+ union { -+ const union nand_boot_header *ap; -+ const union hsm_nand_boot_header *hsm; -+ const union hsm20_nand_boot_header *hsm20; -+ const union spim_nand_boot_header *spim; -+ }; - } nand_headers[] = { - { - .name = "2k+64", -- .data = &snand_hdr_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_64_data, - }, { - .name = "2k+120", -- .data = &snand_hdr_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_128_data, - }, { - .name = "2k+128", -- .data = &snand_hdr_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_2k_128_data, - }, { - .name = "4k+256", -- .data = &snand_hdr_4k_256_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &snand_hdr_4k_256_data, - }, { - .name = "1g:2k+64", -- .data = &nand_hdr_1gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_1gb_2k_64_data, - }, { - .name = "2g:2k+64", -- .data = &nand_hdr_2gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_2gb_2k_64_data, - }, { - .name = "4g:2k+64", -- .data = &nand_hdr_4gb_2k_64_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_4gb_2k_64_data, - }, { - .name = "2g:2k+128", -- .data = &nand_hdr_2gb_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_2gb_2k_128_data, - }, { - .name = "4g:2k+128", -- .data = &nand_hdr_4gb_2k_128_data -+ .type = NAND_BOOT_AP_HEADER, -+ .ap = &nand_hdr_4gb_2k_128_data, -+ }, { -+ .name = "hsm:2k+64", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_2k_64_data, -+ }, { -+ .name = "hsm:2k+128", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_2k_128_data, -+ }, { -+ .name = "hsm:4k+256", -+ .type = NAND_BOOT_HSM_HEADER, -+ .hsm = &hsm_nand_hdr_4k_256_data, -+ }, { -+ .name = "hsm20:2k+64", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_2k_64_data, -+ }, { -+ .name = "hsm20:2k+128", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_2k_128_data, -+ }, { -+ .name = "hsm20:4k+256", -+ .type = NAND_BOOT_HSM20_HEADER, -+ .hsm20 = &hsm20_nand_hdr_4k_256_data, -+ }, { -+ .name = "spim:2k+64", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_2k_64_data, -+ }, { -+ .name = "spim:2k+128", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_2k_128_data, -+ }, { -+ .name = "spim:4k+256", -+ .type = NAND_BOOT_SPIM_HEADER, -+ .spim = &spim_nand_hdr_4k_256_data, - } - }; - --const union nand_boot_header *mtk_nand_header_find(const char *name) -+const struct nand_header_type *mtk_nand_header_find(const char *name) - { - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { - if (!strcmp(nand_headers[i].name, name)) -- return nand_headers[i].data; -+ return &nand_headers[i]; - } - - return NULL; - } - --uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) -+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand) - { -- return 2 * le16_to_cpu(hdr_nand->pagesize); -+ switch (hdr_nand->type) { -+ case NAND_BOOT_HSM_HEADER: -+ return le32_to_cpu(hdr_nand->hsm->page_size); -+ -+ case NAND_BOOT_HSM20_HEADER: -+ return le32_to_cpu(hdr_nand->hsm20->page_size); -+ -+ case NAND_BOOT_SPIM_HEADER: -+ return le32_to_cpu(hdr_nand->spim->page_size); -+ -+ default: -+ return 2 * le16_to_cpu(hdr_nand->ap->pagesize); -+ } - } - - static int mtk_nand_header_ap_info(const void *ptr, -@@ -251,14 +542,45 @@ static int mtk_nand_header_ap_info(const - info->page_size = le16_to_cpu(nh->pagesize); - info->spare_size = le16_to_cpu(nh->oobsize); - info->gfh_offset = 2 * info->page_size; -+ info->snfi = true; - - return 0; - } - -+static int mtk_nand_header_hsm_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union hsm_nand_boot_header *nh = (union hsm_nand_boot_header *)ptr; -+ -+ info->page_size = le16_to_cpu(nh->page_size); -+ info->spare_size = le16_to_cpu(nh->spare_size); -+ info->gfh_offset = info->page_size; -+ info->snfi = true; -+ -+ return 1; -+} -+ -+static int mtk_nand_header_spim_info(const void *ptr, -+ struct nand_header_info *info) -+{ -+ union spim_nand_boot_header *nh = (union spim_nand_boot_header *)ptr; -+ -+ info->page_size = le16_to_cpu(nh->page_size); -+ info->spare_size = le16_to_cpu(nh->spare_size); -+ info->gfh_offset = info->page_size; -+ info->snfi = false; -+ -+ return 1; -+} -+ - int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) - { - if (!strcmp((char *)ptr, NAND_BOOT_NAME)) - return mtk_nand_header_ap_info(ptr, info); -+ else if (!strncmp((char *)ptr, HSM_NAND_BOOT_NAME, 8)) -+ return mtk_nand_header_hsm_info(ptr, info); -+ else if (!strncmp((char *)ptr, SPIM_NAND_BOOT_NAME, 8)) -+ return mtk_nand_header_spim_info(ptr, info); - - return -1; - } -@@ -273,14 +595,74 @@ bool is_mtk_nand_header(const void *ptr) - return false; - } - --uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) -+static uint16_t crc16(const uint8_t *p, uint32_t len) -+{ -+ uint16_t crc = 0x4f4e; -+ uint32_t i; -+ -+ while (len--) { -+ crc ^= *p++ << 8; -+ for (i = 0; i < 8; i++) -+ crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); -+ } -+ -+ return crc; -+} -+ -+static uint32_t mtk_nand_header_put_ap(const struct nand_header_type *hdr_nand, -+ void *ptr) - { -- union nand_boot_header *nh = (union nand_boot_header *)ptr; - int i; - - /* NAND device header, repeat 4 times */ -- for (i = 0; i < 4; i++) -- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); -+ for (i = 0; i < 4; i++) { -+ memcpy(ptr, hdr_nand->ap, sizeof(*hdr_nand->ap)); -+ ptr += sizeof(*hdr_nand->ap); -+ } -+ -+ return le16_to_cpu(hdr_nand->ap->pagesize); -+} - -- return le16_to_cpu(hdr_nand->pagesize); -+static uint32_t mtk_nand_header_put_hsm(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ memcpy(ptr, hdr_nand->hsm, sizeof(*hdr_nand->hsm)); -+ return 0; -+} -+ -+static uint32_t mtk_nand_header_put_hsm20(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ memcpy(ptr, hdr_nand->hsm20, sizeof(*hdr_nand->hsm20)); -+ return 0; -+} -+ -+static uint32_t mtk_nand_header_put_spim(const struct nand_header_type *hdr_nand, -+ void *ptr) -+{ -+ uint16_t crc; -+ -+ memcpy(ptr, hdr_nand->spim, sizeof(*hdr_nand->spim)); -+ -+ crc = crc16(ptr, 0x4e); -+ memcpy(ptr + 0x4e, &crc, sizeof(uint16_t)); -+ -+ return 0; -+} -+ -+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, void *ptr) -+{ -+ switch (hdr_nand->type) { -+ case NAND_BOOT_HSM_HEADER: -+ return mtk_nand_header_put_hsm(hdr_nand, ptr); -+ -+ case NAND_BOOT_HSM20_HEADER: -+ return mtk_nand_header_put_hsm20(hdr_nand, ptr); -+ -+ case NAND_BOOT_SPIM_HEADER: -+ return mtk_nand_header_put_spim(hdr_nand, ptr); -+ -+ default: -+ return mtk_nand_header_put_ap(hdr_nand, ptr); -+ } - } ---- a/tools/mtk_nand_headers.h -+++ b/tools/mtk_nand_headers.h -@@ -16,6 +16,7 @@ struct nand_header_info { - uint32_t page_size; - uint32_t spare_size; - uint32_t gfh_offset; -+ bool snfi; - }; - - /* AP BROM Header for NAND */ -@@ -39,15 +40,117 @@ union nand_boot_header { - uint8_t data[0x80]; - }; - -+/* HSM BROM Header for NAND */ -+union hsm_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t sector_size; /* ECC step size */ -+ uint32_t fdm_size; /* User OOB size of a step */ -+ uint32_t fdm_ecc_size; /* ECC parity size of a step */ -+ uint32_t lbs; -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint32_t page_per_block; /* Pages of one block */ -+ uint32_t blocks; /* Total blocks of NAND chip */ -+ uint32_t plane_sel_position; /* Plane bit position */ -+ uint32_t pll; /* Value of pll reg */ -+ uint32_t acccon; /* Value of access timing reg */ -+ uint32_t strobe_sel; /* Value of DQS selection reg*/ -+ uint32_t acccon1; /* Value of access timing reg */ -+ uint32_t dqs_mux; /* Value of DQS mux reg */ -+ uint32_t dqs_ctrl; /* Value of DQS control reg */ -+ uint32_t delay_ctrl; /* Value of delay ctrl reg */ -+ uint32_t latch_lat; /* Value of latch latency reg */ -+ uint32_t sample_delay; /* Value of sample delay reg */ -+ uint32_t driving; /* Value of driving reg */ -+ uint32_t bl_start; /* Bootloader start addr */ -+ uint32_t bl_end; /* Bootloader end addr */ -+ uint8_t ecc_parity[42]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0x8E]; -+}; -+ -+/* HSM2.0 BROM Header for NAND */ -+union hsm20_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t sector_size; /* ECC step size */ -+ uint32_t fdm_size; /* User OOB size of a step */ -+ uint32_t fdm_ecc_size; /* ECC parity size of a step */ -+ uint32_t lbs; -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint32_t page_per_block; /* Pages of one block */ -+ uint32_t blocks; /* Total blocks of NAND chip */ -+ uint32_t plane_sel_position; /* Plane bit position */ -+ uint32_t pll; /* Value of pll reg */ -+ uint32_t acccon; /* Value of access timing reg */ -+ uint32_t strobe_sel; /* Value of DQS selection reg*/ -+ uint32_t acccon1; /* Value of access timing reg */ -+ uint32_t dqs_mux; /* Value of DQS mux reg */ -+ uint32_t dqs_ctrl; /* Value of DQS control reg */ -+ uint32_t delay_ctrl; /* Value of delay ctrl reg */ -+ uint32_t latch_lat; /* Value of latch latency reg */ -+ uint32_t sample_delay; /* Value of sample delay reg */ -+ uint32_t driving; /* Value of driving reg */ -+ uint32_t reserved; -+ uint32_t bl0_start; /* Bootloader start addr */ -+ uint32_t bl0_end; /* Bootloader end addr */ -+ uint32_t bl0_type; /* Bootloader type */ -+ uint8_t bl_reserve[84]; -+ uint8_t ecc_parity[42]; /* ECC parity of this header */ -+ }; -+ -+ uint8_t data[0xEA]; -+}; -+ -+/* SPIM BROM Header for SPI-NAND */ -+union spim_nand_boot_header { -+ struct { -+ char id[8]; -+ uint32_t version; /* Header version */ -+ uint32_t config; /* Header config */ -+ uint32_t page_size; /* NAND page size */ -+ uint32_t spare_size; /* NAND page spare size */ -+ uint16_t page_per_block; /* Pages of one block */ -+ uint16_t plane_sel_position; /* Plane bit position */ -+ uint16_t reserve_reg; -+ uint16_t reserve_val; -+ uint16_t ecc_error; /* ECC error reg addr */ -+ uint16_t ecc_mask; /* ECC error bit mask */ -+ uint32_t bl_start; /* Bootloader start addr */ -+ uint32_t bl_end; /* Bootloader end addr */ -+ uint8_t ecc_parity[32]; /* ECC parity of this header */ -+ uint32_t integrity_crc; /* CRC of this header */ -+ }; -+ -+ uint8_t data[0x50]; -+}; -+ -+enum nand_boot_header_type { -+ NAND_BOOT_AP_HEADER, -+ NAND_BOOT_HSM_HEADER, -+ NAND_BOOT_HSM20_HEADER, -+ NAND_BOOT_SPIM_HEADER -+}; -+ - #define NAND_BOOT_NAME "BOOTLOADER!" - #define NAND_BOOT_VERSION "V006" - #define NAND_BOOT_ID "NFIINFO" - -+#define HSM_NAND_BOOT_NAME "NANDCFG!" -+#define SPIM_NAND_BOOT_NAME "SPINAND!" -+ - /* Find nand header data by name */ --const union nand_boot_header *mtk_nand_header_find(const char *name); -+const struct nand_header_type *mtk_nand_header_find(const char *name); - - /* Device header size using this nand header */ --uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); -+uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand); - - /* Get nand info from nand header (page size, spare size, ...) */ - int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); -@@ -56,6 +159,7 @@ int mtk_nand_header_info(const void *ptr - bool is_mtk_nand_header(const void *ptr); - - /* Generate Device header using give nand header */ --uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); -+uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, -+ void *ptr); - - #endif /* _MTK_NAND_HEADERS_H */ diff --git a/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch b/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch new file mode 100644 index 0000000000..2f5c935356 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/002-0030-tools-mtk_image-split-the-code-of-generating-NAND-he.patch @@ -0,0 +1,821 @@ +From 8867a5e66369d4a7da667e0f505597e1ac91209e Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 31 Aug 2022 19:05:24 +0800 +Subject: [PATCH 30/32] tools: mtk_image: split the code of generating NAND + header into a new file + +The predefined NAND headers take too much spaces in the mtk_image.c. +Moving them into a new file can significantly improve the readability of +both mtk_image.c and the new mtk_nand_headers.c. + +This is a preparation for adding more NAND headers. + +Reviewed-by: Simon Glass +Signed-off-by: Weijie Gao +--- + tools/Makefile | 1 + + tools/mtk_image.c | 305 ++++++--------------------------------- + tools/mtk_image.h | 25 ---- + tools/mtk_nand_headers.c | 286 ++++++++++++++++++++++++++++++++++++ + tools/mtk_nand_headers.h | 61 ++++++++ + 5 files changed, 389 insertions(+), 289 deletions(-) + create mode 100644 tools/mtk_nand_headers.c + create mode 100644 tools/mtk_nand_headers.h + +--- a/tools/Makefile ++++ b/tools/Makefile +@@ -147,6 +147,7 @@ dumpimage-mkimage-objs := aisimage.o \ + gpimage.o \ + gpimage-common.o \ + mtk_image.o \ ++ mtk_nand_headers.o \ + $(ECDSA_OBJS-y) \ + $(RSA_OBJS-y) \ + $(AES_OBJS-y) +--- a/tools/mtk_image.c ++++ b/tools/mtk_image.c +@@ -12,216 +12,7 @@ + #include + #include "imagetool.h" + #include "mtk_image.h" +- +-/* NAND header for SPI-NAND with 2KB page + 64B spare */ +-static const union nand_boot_header snand_hdr_2k_64_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, +- 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, +- 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, +- 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 +- } +-}; +- +-/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ +-static const union nand_boot_header snand_hdr_2k_128_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, +- 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, +- 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, +- 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 +- } +-}; +- +-/* NAND header for SPI-NAND with 4KB page + 256B spare */ +-static const union nand_boot_header snand_hdr_4k_256_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, +- 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, +- 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, +- 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ +-static const union nand_boot_header nand_hdr_1gb_2k_64_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, +- 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, +- 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, +- 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, +- 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ +-static const union nand_boot_header nand_hdr_2gb_2k_64_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, +- 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, +- 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, +- 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ +-static const union nand_boot_header nand_hdr_4gb_2k_64_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, +- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, +- 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, +- 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, +- 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ +-static const union nand_boot_header nand_hdr_2gb_2k_128_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, +- 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, +- 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, +- 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, +- 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 +- } +-}; +- +-/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ +-static const union nand_boot_header nand_hdr_4gb_2k_128_data = { +- .data = { +- 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, +- 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, +- 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, +- 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, +- 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +- 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, +- 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, +- 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, +- 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 +- } +-}; +- +-static const struct nand_header_type { +- const char *name; +- const union nand_boot_header *data; +-} nand_headers[] = { +- { +- .name = "2k+64", +- .data = &snand_hdr_2k_64_data +- }, { +- .name = "2k+120", +- .data = &snand_hdr_2k_128_data +- }, { +- .name = "2k+128", +- .data = &snand_hdr_2k_128_data +- }, { +- .name = "4k+256", +- .data = &snand_hdr_4k_256_data +- }, { +- .name = "1g:2k+64", +- .data = &nand_hdr_1gb_2k_64_data +- }, { +- .name = "2g:2k+64", +- .data = &nand_hdr_2gb_2k_64_data +- }, { +- .name = "4g:2k+64", +- .data = &nand_hdr_4gb_2k_64_data +- }, { +- .name = "2g:2k+128", +- .data = &nand_hdr_2gb_2k_128_data +- }, { +- .name = "4g:2k+128", +- .data = &nand_hdr_4gb_2k_128_data +- } +-}; ++#include "mtk_nand_headers.h" + + static const struct brom_img_type { + const char *name; +@@ -264,6 +55,7 @@ static uint32_t crc32tbl[256]; + + /* NAND header selected by user */ + static const union nand_boot_header *hdr_nand; ++static uint32_t hdr_nand_size; + + /* GFH header + 2 * 4KB pages of NAND */ + static char hdr_tmp[sizeof(struct gfh_header) + 0x2000]; +@@ -402,12 +194,7 @@ static int mtk_brom_parse_imagename(cons + } + + /* parse nand header type */ +- for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { +- if (!strcmp(nand_headers[i].name, nandinfo)) { +- hdr_nand = nand_headers[i].data; +- break; +- } +- } ++ hdr_nand = mtk_nand_header_find(nandinfo); + + /* parse device header offset */ + if (hdr_offs && hdr_offs[0]) +@@ -432,6 +219,9 @@ static int mtk_brom_parse_imagename(cons + return -EINVAL; + } + ++ if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) ++ hdr_nand_size = mtk_nand_header_size(hdr_nand); ++ + return 0; + } + +@@ -468,7 +258,7 @@ static int mtk_image_vrec_header(struct + } + + if (hdr_media == BRLYT_TYPE_NAND || hdr_media == BRLYT_TYPE_SNAND) +- tparams->header_size = 2 * le16_to_cpu(hdr_nand->pagesize); ++ tparams->header_size = hdr_nand_size; + else + tparams->header_size = sizeof(struct gen_device_header); + +@@ -566,16 +356,17 @@ static int mtk_image_verify_gen_header(c + + static int mtk_image_verify_nand_header(const uint8_t *ptr, int print) + { +- union nand_boot_header *nh = (union nand_boot_header *)ptr; + struct brom_layout_header *bh; ++ struct nand_header_info info; + struct gfh_header *gfh; + const char *bootmedia; ++ int ret; + +- if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || +- strcmp(nh->id, NAND_BOOT_ID)) +- return -1; ++ ret = mtk_nand_header_info(ptr, &info); ++ if (ret < 0) ++ return ret; + +- bh = (struct brom_layout_header *)(ptr + le16_to_cpu(nh->pagesize)); ++ bh = (struct brom_layout_header *)(ptr + info.page_size); + + if (strcmp(bh->name, BRLYT_NAME)) + return -1; +@@ -586,34 +377,23 @@ static int mtk_image_verify_nand_header( + if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) + bootmedia = "Parallel NAND"; + else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) +- bootmedia = "Serial NAND"; ++ bootmedia = "Serial NAND (SNFI/AP)"; + else + return -1; + } + + if (print) { +- printf("Boot Media: %s\n", bootmedia); +- +- if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) { +- uint64_t capacity = +- (uint64_t)le16_to_cpu(nh->numblocks) * +- (uint64_t)le16_to_cpu(nh->pages_of_block) * +- (uint64_t)le16_to_cpu(nh->pagesize) * 8; +- printf("Capacity: %dGb\n", +- (uint32_t)(capacity >> 30)); +- } ++ printf("Boot Media: %s\n", bootmedia); + +- if (le16_to_cpu(nh->pagesize) >= 1024) +- printf("Page Size: %dKB\n", +- le16_to_cpu(nh->pagesize) >> 10); ++ if (info.page_size >= 1024) ++ printf("Page Size: %dKB\n", info.page_size >> 10); + else +- printf("Page Size: %dB\n", +- le16_to_cpu(nh->pagesize)); ++ printf("Page Size: %dB\n", info.page_size); + +- printf("Spare Size: %dB\n", le16_to_cpu(nh->oobsize)); ++ printf("Spare Size: %dB\n", info.spare_size); + } + +- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(nh->pagesize)); ++ gfh = (struct gfh_header *)(ptr + info.gfh_offset); + + return mtk_image_verify_gfh(gfh, GFH_FLASH_TYPE_NAND, print); + } +@@ -713,7 +493,7 @@ static int mtk_image_verify_header(unsig + if (image_get_magic(hdr) == IH_MAGIC) + return mtk_image_verify_mt7621_header(ptr, 0); + +- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) ++ if (is_mtk_nand_header(ptr)) + return mtk_image_verify_nand_header(ptr, 0); + else + return mtk_image_verify_gen_header(ptr, 0); +@@ -739,7 +519,7 @@ static void mtk_image_print_header(const + return; + } + +- if (!strcmp((char *)ptr, NAND_BOOT_NAME)) ++ if (is_mtk_nand_header(ptr)) + mtk_image_verify_nand_header(ptr, 1); + else + mtk_image_verify_gen_header(ptr, 1); +@@ -870,36 +650,33 @@ static void mtk_image_set_gen_header(voi + static void mtk_image_set_nand_header(void *ptr, off_t filesize, + uint32_t loadaddr) + { +- union nand_boot_header *nh = (union nand_boot_header *)ptr; + struct brom_layout_header *brlyt; + struct gfh_header *gfh; +- uint32_t payload_pages; +- int i; ++ uint32_t payload_pages, nand_page_size; + +- /* NAND device header, repeat 4 times */ +- for (i = 0; i < 4; i++) +- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); ++ /* NAND header */ ++ nand_page_size = mtk_nand_header_put(hdr_nand, ptr); + +- /* BRLYT header */ +- payload_pages = (filesize + le16_to_cpu(hdr_nand->pagesize) - 1) / +- le16_to_cpu(hdr_nand->pagesize); +- brlyt = (struct brom_layout_header *) +- (ptr + le16_to_cpu(hdr_nand->pagesize)); +- put_brom_layout_header(brlyt, hdr_media); +- brlyt->header_size = cpu_to_le32(2); +- brlyt->total_size = cpu_to_le32(payload_pages); +- brlyt->header_size_2 = brlyt->header_size; +- brlyt->total_size_2 = brlyt->total_size; +- brlyt->unused = cpu_to_le32(1); ++ if (nand_page_size) { ++ /* BRLYT header */ ++ payload_pages = (filesize + nand_page_size - 1) / ++ nand_page_size; ++ brlyt = (struct brom_layout_header *)(ptr + nand_page_size); ++ put_brom_layout_header(brlyt, hdr_media); ++ brlyt->header_size = cpu_to_le32(2); ++ brlyt->total_size = cpu_to_le32(payload_pages); ++ brlyt->header_size_2 = brlyt->header_size; ++ brlyt->total_size_2 = brlyt->total_size; ++ brlyt->unused = cpu_to_le32(1); ++ } + + /* GFH header */ +- gfh = (struct gfh_header *)(ptr + 2 * le16_to_cpu(hdr_nand->pagesize)); +- put_ghf_header(gfh, filesize, 2 * le16_to_cpu(hdr_nand->pagesize), +- loadaddr, GFH_FLASH_TYPE_NAND); ++ gfh = (struct gfh_header *)(ptr + hdr_nand_size); ++ put_ghf_header(gfh, filesize, hdr_nand_size, loadaddr, ++ GFH_FLASH_TYPE_NAND); + + /* Generate SHA256 hash */ +- put_hash((uint8_t *)gfh, +- filesize - 2 * le16_to_cpu(hdr_nand->pagesize) - SHA256_SUM_LEN); ++ put_hash((uint8_t *)gfh, filesize - hdr_nand_size - SHA256_SUM_LEN); + } + + static void mtk_image_set_mt7621_header(void *ptr, off_t filesize, +--- a/tools/mtk_image.h ++++ b/tools/mtk_image.h +@@ -26,31 +26,6 @@ union gen_boot_header { + #define SF_BOOT_NAME "SF_BOOT" + #define SDMMC_BOOT_NAME "SDMMC_BOOT" + +-/* Header for NAND */ +-union nand_boot_header { +- struct { +- char name[12]; +- char version[4]; +- char id[8]; +- uint16_t ioif; +- uint16_t pagesize; +- uint16_t addrcycles; +- uint16_t oobsize; +- uint16_t pages_of_block; +- uint16_t numblocks; +- uint16_t writesize_shift; +- uint16_t erasesize_shift; +- uint8_t dummy[60]; +- uint8_t ecc_parity[28]; +- }; +- +- uint8_t data[0x80]; +-}; +- +-#define NAND_BOOT_NAME "BOOTLOADER!" +-#define NAND_BOOT_VERSION "V006" +-#define NAND_BOOT_ID "NFIINFO" +- + /* BootROM layout header */ + struct brom_layout_header { + char name[8]; +--- /dev/null ++++ b/tools/mtk_nand_headers.c +@@ -0,0 +1,286 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * MediaTek BootROM NAND header definitions ++ * ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Weijie Gao ++ */ ++ ++#include ++#include ++#include "imagetool.h" ++#include "mtk_image.h" ++#include "mtk_nand_headers.h" ++ ++/* NAND header for SPI-NAND with 2KB page + 64B spare */ ++static const union nand_boot_header snand_hdr_2k_64_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D, ++ 0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7, ++ 0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8, ++ 0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for SPI-NAND with 2KB page + 120B/128B spare */ ++static const union nand_boot_header snand_hdr_2k_128_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x90, 0x28, 0xED, 0x13, ++ 0x7F, 0x12, 0x22, 0xCD, 0x3D, 0x06, 0xF1, 0xB3, ++ 0x6F, 0x2E, 0xD9, 0xA0, 0x9D, 0x7A, 0xBD, 0xD7, ++ 0xB3, 0x28, 0x3C, 0x13, 0xDB, 0x4E, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for SPI-NAND with 4KB page + 256B spare */ ++static const union nand_boot_header snand_hdr_4k_256_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x10, 0x05, 0x00, 0xE0, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x47, 0xED, 0x0E, 0xC3, ++ 0x83, 0xBF, 0x41, 0xD2, 0x85, 0x21, 0x97, 0x57, ++ 0xC4, 0x2E, 0x6B, 0x7A, 0x40, 0xE0, 0xCF, 0x8F, ++ 0x37, 0xBD, 0x17, 0xB6, 0xC7, 0xFE, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 1Gb with 2KB page + 64B spare */ ++static const union nand_boot_header nand_hdr_1gb_2k_64_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, ++ 0x40, 0x00, 0x00, 0x04, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x12, 0x28, 0x1C, 0x12, ++ 0x8F, 0xFD, 0xF8, 0x32, 0x6F, 0x6D, 0xCF, 0x6C, ++ 0xDA, 0x21, 0x70, 0x8C, 0xDA, 0x0A, 0x22, 0x82, ++ 0xAA, 0x59, 0xFA, 0x7C, 0x42, 0x2D, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 2Gb with 2KB page + 64B spare */ ++static const union nand_boot_header nand_hdr_2gb_2k_64_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x20, 0x9C, 0x3D, 0x2D, ++ 0x7B, 0x68, 0x63, 0x52, 0x2E, 0x04, 0x63, 0xF1, ++ 0x35, 0x4E, 0x44, 0x3E, 0xF8, 0xAC, 0x9B, 0x95, ++ 0xAB, 0xFE, 0xE4, 0xE1, 0xD5, 0xF9, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 4Gb with 2KB page + 64B spare */ ++static const union nand_boot_header nand_hdr_4gb_2k_64_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x40, 0x00, ++ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xE3, 0x0F, 0x86, 0x32, ++ 0x68, 0x05, 0xD9, 0xC8, 0x13, 0xDF, 0xC5, 0x0B, ++ 0x35, 0x3A, 0x68, 0xA5, 0x3C, 0x0C, 0x73, 0x87, ++ 0x63, 0xB0, 0xBE, 0xCC, 0x84, 0x47, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 2Gb with 2KB page + 128B spare */ ++static const union nand_boot_header nand_hdr_2gb_2k_128_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, ++ 0x40, 0x00, 0x00, 0x08, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x01, 0xA5, 0xE9, 0x5A, ++ 0xDF, 0x58, 0x62, 0x41, 0xD6, 0x26, 0x77, 0xBC, ++ 0x76, 0x1F, 0x27, 0x4E, 0x4F, 0x6C, 0xC3, 0xF0, ++ 0x36, 0xDE, 0xD9, 0xB3, 0xFF, 0x93, 0x00, 0x00 ++ } ++}; ++ ++/* NAND header for Parallel NAND 4Gb with 2KB page + 128B spare */ ++static const union nand_boot_header nand_hdr_4gb_2k_128_data = { ++ .data = { ++ 0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44, ++ 0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36, ++ 0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x05, 0x00, 0x70, 0x00, ++ 0x40, 0x00, 0x00, 0x10, 0x0B, 0x00, 0x11, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xC2, 0x36, 0x52, 0x45, ++ 0xCC, 0x35, 0xD8, 0xDB, 0xEB, 0xFD, 0xD1, 0x46, ++ 0x76, 0x6B, 0x0B, 0xD5, 0x8B, 0xCC, 0x2B, 0xE2, ++ 0xFE, 0x90, 0x83, 0x9E, 0xAE, 0x2D, 0x00, 0x00 ++ } ++}; ++ ++static const struct nand_header_type { ++ const char *name; ++ const union nand_boot_header *data; ++} nand_headers[] = { ++ { ++ .name = "2k+64", ++ .data = &snand_hdr_2k_64_data ++ }, { ++ .name = "2k+120", ++ .data = &snand_hdr_2k_128_data ++ }, { ++ .name = "2k+128", ++ .data = &snand_hdr_2k_128_data ++ }, { ++ .name = "4k+256", ++ .data = &snand_hdr_4k_256_data ++ }, { ++ .name = "1g:2k+64", ++ .data = &nand_hdr_1gb_2k_64_data ++ }, { ++ .name = "2g:2k+64", ++ .data = &nand_hdr_2gb_2k_64_data ++ }, { ++ .name = "4g:2k+64", ++ .data = &nand_hdr_4gb_2k_64_data ++ }, { ++ .name = "2g:2k+128", ++ .data = &nand_hdr_2gb_2k_128_data ++ }, { ++ .name = "4g:2k+128", ++ .data = &nand_hdr_4gb_2k_128_data ++ } ++}; ++ ++const union nand_boot_header *mtk_nand_header_find(const char *name) ++{ ++ uint32_t i; ++ ++ for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { ++ if (!strcmp(nand_headers[i].name, name)) ++ return nand_headers[i].data; ++ } ++ ++ return NULL; ++} ++ ++uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) ++{ ++ return 2 * le16_to_cpu(hdr_nand->pagesize); ++} ++ ++static int mtk_nand_header_ap_info(const void *ptr, ++ struct nand_header_info *info) ++{ ++ union nand_boot_header *nh = (union nand_boot_header *)ptr; ++ ++ if (strncmp(nh->version, NAND_BOOT_VERSION, sizeof(nh->version)) || ++ strcmp(nh->id, NAND_BOOT_ID)) ++ return -1; ++ ++ info->page_size = le16_to_cpu(nh->pagesize); ++ info->spare_size = le16_to_cpu(nh->oobsize); ++ info->gfh_offset = 2 * info->page_size; ++ ++ return 0; ++} ++ ++int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) ++{ ++ if (!strcmp((char *)ptr, NAND_BOOT_NAME)) ++ return mtk_nand_header_ap_info(ptr, info); ++ ++ return -1; ++} ++ ++bool is_mtk_nand_header(const void *ptr) ++{ ++ struct nand_header_info info; ++ ++ if (mtk_nand_header_info(ptr, &info) >= 0) ++ return true; ++ ++ return false; ++} ++ ++uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) ++{ ++ union nand_boot_header *nh = (union nand_boot_header *)ptr; ++ int i; ++ ++ /* NAND device header, repeat 4 times */ ++ for (i = 0; i < 4; i++) ++ memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); ++ ++ return le16_to_cpu(hdr_nand->pagesize); ++} +--- /dev/null ++++ b/tools/mtk_nand_headers.h +@@ -0,0 +1,61 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * MediaTek BootROM NAND header definitions ++ * ++ * Copyright (C) 2022 MediaTek Inc. ++ * Author: Weijie Gao ++ */ ++ ++#ifndef _MTK_NAND_HEADERS_H ++#define _MTK_NAND_HEADERS_H ++ ++#include ++#include ++ ++struct nand_header_info { ++ uint32_t page_size; ++ uint32_t spare_size; ++ uint32_t gfh_offset; ++}; ++ ++/* AP BROM Header for NAND */ ++union nand_boot_header { ++ struct { ++ char name[12]; ++ char version[4]; ++ char id[8]; ++ uint16_t ioif; /* I/O interface */ ++ uint16_t pagesize; /* NAND page size */ ++ uint16_t addrcycles; /* Address cycles */ ++ uint16_t oobsize; /* NAND page spare size */ ++ uint16_t pages_of_block; /* Pages of one block */ ++ uint16_t numblocks; /* Total blocks of NAND chip */ ++ uint16_t writesize_shift; ++ uint16_t erasesize_shift; ++ uint8_t dummy[60]; ++ uint8_t ecc_parity[28]; /* ECC parity of this header */ ++ }; ++ ++ uint8_t data[0x80]; ++}; ++ ++#define NAND_BOOT_NAME "BOOTLOADER!" ++#define NAND_BOOT_VERSION "V006" ++#define NAND_BOOT_ID "NFIINFO" ++ ++/* Find nand header data by name */ ++const union nand_boot_header *mtk_nand_header_find(const char *name); ++ ++/* Device header size using this nand header */ ++uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); ++ ++/* Get nand info from nand header (page size, spare size, ...) */ ++int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); ++ ++/* Whether given header data is valid */ ++bool is_mtk_nand_header(const void *ptr); ++ ++/* Generate Device header using give nand header */ ++uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); ++ ++#endif /* _MTK_NAND_HEADERS_H */ diff --git a/package/boot/uboot-mediatek/patches/002-0031-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch b/package/boot/uboot-mediatek/patches/002-0031-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch deleted file mode 100644 index 227fa07527..0000000000 --- a/package/boot/uboot-mediatek/patches/002-0031-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch +++ /dev/null @@ -1,42 +0,0 @@ -From ca90c165157c19af9bf46a69dcf719b8aab636b1 Mon Sep 17 00:00:00 2001 -From: Weijie Gao -Date: Thu, 4 Aug 2022 09:50:40 +0800 -Subject: [PATCH 31/31] MAINTAINERS: update maintainer for MediaTek ARM - platform - -Add new files for MediaTek ARM platform - -Reviewed-by: Simon Glass -Signed-off-by: Weijie Gao ---- - MAINTAINERS | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -340,20 +340,25 @@ F: doc/device-tree-bindings/phy/phy-mtk- - F: doc/device-tree-bindings/usb/mediatek,* - F: doc/README.mediatek - F: drivers/clk/mediatek/ -+F: drivers/i2c/mtk_i2c.c - F: drivers/mmc/mtk-sd.c - F: drivers/phy/phy-mtk-* - F: drivers/pinctrl/mediatek/ - F: drivers/power/domain/mtk-power-domain.c - F: drivers/ram/mediatek/ - F: drivers/spi/mtk_snfi_spi.c -+F: drivers/spi/mtk_spim.c - F: drivers/timer/mtk_timer.c - F: drivers/usb/host/xhci-mtk.c - F: drivers/usb/mtu3/ - F: drivers/watchdog/mtk_wdt.c - F: drivers/net/mtk_eth.c -+F: drivers/net/mtk_eth.h - F: drivers/reset/reset-mediatek.c - F: tools/mtk_image.c - F: tools/mtk_image.h -+F: tools/mtk_nand_headers.c -+F: tools/mtk_nand_headers.h - N: mediatek - - ARM MICROCHIP/ATMEL AT91 diff --git a/package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch b/package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch new file mode 100644 index 0000000000..c20dffdb36 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/002-0031-tools-mtk_image-add-support-for-nand-headers-used-by.patch @@ -0,0 +1,702 @@ +From d459092aca25e081401606e18b7097f33b575188 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 31 Aug 2022 19:05:26 +0800 +Subject: [PATCH 31/32] tools: mtk_image: add support for nand headers used by + newer chips + +This patch adds more nand headers in two new types: +1. HSM header, used for spi-nand thru SNFI interface +2. SPIM header, used for spi-nand thru spi-mem interface + +The original nand header is renamed to AP header. + +Signed-off-by: Weijie Gao +--- + tools/mtk_image.c | 23 ++- + tools/mtk_nand_headers.c | 422 +++++++++++++++++++++++++++++++++++++-- + tools/mtk_nand_headers.h | 110 +++++++++- + 3 files changed, 525 insertions(+), 30 deletions(-) + +--- a/tools/mtk_image.c ++++ b/tools/mtk_image.c +@@ -33,6 +33,9 @@ static const struct brom_img_type { + }, { + .name = "snand", + .type = BRLYT_TYPE_SNAND ++ }, { ++ .name = "spim-nand", ++ .type = BRLYT_TYPE_SNAND + } + }; + +@@ -54,7 +57,7 @@ static char lk_name[32] = "U-Boot"; + static uint32_t crc32tbl[256]; + + /* NAND header selected by user */ +-static const union nand_boot_header *hdr_nand; ++static const struct nand_header_type *hdr_nand; + static uint32_t hdr_nand_size; + + /* GFH header + 2 * 4KB pages of NAND */ +@@ -366,20 +369,26 @@ static int mtk_image_verify_nand_header( + if (ret < 0) + return ret; + +- bh = (struct brom_layout_header *)(ptr + info.page_size); ++ if (!ret) { ++ bh = (struct brom_layout_header *)(ptr + info.page_size); + +- if (strcmp(bh->name, BRLYT_NAME)) +- return -1; ++ if (strcmp(bh->name, BRLYT_NAME)) ++ return -1; ++ ++ if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) ++ return -1; + +- if (le32_to_cpu(bh->magic) != BRLYT_MAGIC) { +- return -1; +- } else { + if (le32_to_cpu(bh->type) == BRLYT_TYPE_NAND) + bootmedia = "Parallel NAND"; + else if (le32_to_cpu(bh->type) == BRLYT_TYPE_SNAND) + bootmedia = "Serial NAND (SNFI/AP)"; + else + return -1; ++ } else { ++ if (info.snfi) ++ bootmedia = "Serial NAND (SNFI/HSM)"; ++ else ++ bootmedia = "Serial NAND (SPIM)"; + } + + if (print) { +--- a/tools/mtk_nand_headers.c ++++ b/tools/mtk_nand_headers.c +@@ -188,55 +188,346 @@ static const union nand_boot_header nand + } + }; + +-static const struct nand_header_type { ++/* HSM BROM NAND header for SPI NAND with 2KB page + 64B spare */ ++static const union hsm_nand_boot_header hsm_nand_hdr_2k_64_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, ++ 0xFF, 0x00, 0x00, 0x00, 0x21, 0xD2, 0xEE, 0xF6, ++ 0xAE, 0xDD, 0x5E, 0xC2, 0x82, 0x8E, 0x9A, 0x62, ++ 0x09, 0x8E, 0x80, 0xE2, 0x37, 0x0D, 0xC9, 0xFA, ++ 0xA9, 0xDD, 0xFC, 0x92, 0x34, 0x2A, 0xED, 0x51, ++ 0xA4, 0x1B, 0xF7, 0x63, 0xCC, 0x5A, 0xC7, 0xFB, ++ 0xED, 0x21, 0x02, 0x23, 0x51, 0x31 ++ } ++}; ++ ++/* HSM BROM NAND header for SPI NAND with 2KB page + 128B spare */ ++static const union hsm_nand_boot_header hsm_nand_hdr_2k_128_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, ++ 0xFF, 0x00, 0x00, 0x00, 0x71, 0x7f, 0x71, 0xAC, ++ 0x42, 0xD0, 0x5B, 0xD2, 0x12, 0x81, 0x15, 0x0A, ++ 0x0C, 0xD4, 0xF6, 0x32, 0x1E, 0x63, 0xE7, 0x81, ++ 0x8A, 0x7F, 0xDE, 0xF9, 0x4B, 0x91, 0xEC, 0xC2, ++ 0x70, 0x00, 0x7F, 0x57, 0xAF, 0xDC, 0xE4, 0x24, ++ 0x57, 0x09, 0xBC, 0xC5, 0x35, 0xDC ++ } ++}; ++ ++/* HSM BROM NAND header for SPI NAND with 4KB page + 256B spare */ ++static const union hsm_nand_boot_header hsm_nand_hdr_4k_256_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, ++ 0xFF, 0x00, 0x00, 0x00, 0x62, 0x04, 0xD6, 0x1F, ++ 0x2B, 0x57, 0x7A, 0x2D, 0xFE, 0xBB, 0x4A, 0x50, ++ 0xEC, 0xF8, 0x70, 0x1A, 0x44, 0x15, 0xF6, 0xA2, ++ 0x8E, 0xB0, 0xFD, 0xFA, 0xDC, 0xAA, 0x5A, 0x4E, ++ 0xCB, 0x8E, 0xC9, 0x72, 0x08, 0xDC, 0x20, 0xB9, ++ 0x98, 0xC8, 0x82, 0xD8, 0xBE, 0x44 ++ } ++}; ++ ++/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 64B spare */ ++static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_64_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x5F, 0x4B, 0xB2, 0x5B, 0x8B, 0x1C, 0x35, 0xDA, ++ 0x83, 0xE6, 0x6C, 0xC3, 0xFB, 0x8C, 0x78, 0x23, ++ 0xD0, 0x89, 0x24, 0xD9, 0x6C, 0x35, 0x2C, 0x5D, ++ 0x8F, 0xBB, 0xFC, 0x10, 0xD0, 0xE2, 0x22, 0x7D, ++ 0xC8, 0x97, 0x9A, 0xEF, 0xC6, 0xB5, 0xA7, 0x4E, ++ 0x4E, 0x0E ++ } ++}; ++ ++/* HSM2.0 BROM NAND header for SPI NAND with 2KB page + 128B spare */ ++static const union hsm20_nand_boot_header hsm20_nand_hdr_2k_128_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xF8, 0x7E, 0xC1, 0x5D, 0x61, 0x54, 0xEA, 0x9F, ++ 0x5E, 0x66, 0x39, 0x66, 0x21, 0xFF, 0x8C, 0x3B, ++ 0xBE, 0xA7, 0x5A, 0x9E, 0xD7, 0xBD, 0x9E, 0x89, ++ 0xEE, 0x7E, 0x10, 0x31, 0x9A, 0x1D, 0x82, 0x49, ++ 0xA3, 0x4E, 0xD8, 0x47, 0xD7, 0x19, 0xF4, 0x2D, ++ 0x8E, 0x53 ++ } ++}; ++ ++/* HSM2.0 BROM NAND header for SPI NAND with 4KB page + 256B spare */ ++static const union hsm20_nand_boot_header hsm20_nand_hdr_4k_256_data = { ++ .data = { ++ 0x4E, 0x41, 0x4E, 0x44, 0x43, 0x46, 0x47, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, ++ 0x00, 0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, ++ 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x79, 0x01, 0x1F, 0x86, 0x62, 0x6A, 0x43, 0xAE, ++ 0xE6, 0xF8, 0xDD, 0x5B, 0x29, 0xB7, 0xA2, 0x7F, ++ 0x29, 0x72, 0x54, 0x37, 0xBE, 0x50, 0xD4, 0x24, ++ 0xAB, 0x60, 0xF4, 0x44, 0x97, 0x3B, 0x65, 0x21, ++ 0x73, 0x24, 0x1F, 0x93, 0x0E, 0x9E, 0x96, 0x88, ++ 0x78, 0x6C ++ } ++}; ++ ++/* SPIM-NAND header for SPI NAND with 2KB page + 64B spare */ ++static const union spim_nand_boot_header spim_nand_hdr_2k_64_data = { ++ .data = { ++ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, ++ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ } ++}; ++ ++/* SPIM-NAND header for SPI NAND with 2KB page + 128B spare */ ++static const union spim_nand_boot_header spim_nand_hdr_2k_128_data = { ++ .data = { ++ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, ++ 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, ++ 0x40, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x20, 0x30, ++ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ } ++}; ++ ++/* SPIM-NAND header for SPI NAND with 4KB page + 256B spare */ ++static const union spim_nand_boot_header spim_nand_hdr_4k_256_data = { ++ .data = { ++ 0x53, 0x50, 0x49, 0x4e, 0x41, 0x4e, 0x44, 0x21, ++ 0x01, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, ++ 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++ 0x40, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x20, 0x30, ++ 0x01, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ++ } ++}; ++ ++struct nand_header_type { + const char *name; +- const union nand_boot_header *data; ++ enum nand_boot_header_type type; ++ union { ++ const union nand_boot_header *ap; ++ const union hsm_nand_boot_header *hsm; ++ const union hsm20_nand_boot_header *hsm20; ++ const union spim_nand_boot_header *spim; ++ }; + } nand_headers[] = { + { + .name = "2k+64", +- .data = &snand_hdr_2k_64_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &snand_hdr_2k_64_data, + }, { + .name = "2k+120", +- .data = &snand_hdr_2k_128_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &snand_hdr_2k_128_data, + }, { + .name = "2k+128", +- .data = &snand_hdr_2k_128_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &snand_hdr_2k_128_data, + }, { + .name = "4k+256", +- .data = &snand_hdr_4k_256_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &snand_hdr_4k_256_data, + }, { + .name = "1g:2k+64", +- .data = &nand_hdr_1gb_2k_64_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_1gb_2k_64_data, + }, { + .name = "2g:2k+64", +- .data = &nand_hdr_2gb_2k_64_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_2gb_2k_64_data, + }, { + .name = "4g:2k+64", +- .data = &nand_hdr_4gb_2k_64_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_4gb_2k_64_data, + }, { + .name = "2g:2k+128", +- .data = &nand_hdr_2gb_2k_128_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_2gb_2k_128_data, + }, { + .name = "4g:2k+128", +- .data = &nand_hdr_4gb_2k_128_data ++ .type = NAND_BOOT_AP_HEADER, ++ .ap = &nand_hdr_4gb_2k_128_data, ++ }, { ++ .name = "hsm:2k+64", ++ .type = NAND_BOOT_HSM_HEADER, ++ .hsm = &hsm_nand_hdr_2k_64_data, ++ }, { ++ .name = "hsm:2k+128", ++ .type = NAND_BOOT_HSM_HEADER, ++ .hsm = &hsm_nand_hdr_2k_128_data, ++ }, { ++ .name = "hsm:4k+256", ++ .type = NAND_BOOT_HSM_HEADER, ++ .hsm = &hsm_nand_hdr_4k_256_data, ++ }, { ++ .name = "hsm20:2k+64", ++ .type = NAND_BOOT_HSM20_HEADER, ++ .hsm20 = &hsm20_nand_hdr_2k_64_data, ++ }, { ++ .name = "hsm20:2k+128", ++ .type = NAND_BOOT_HSM20_HEADER, ++ .hsm20 = &hsm20_nand_hdr_2k_128_data, ++ }, { ++ .name = "hsm20:4k+256", ++ .type = NAND_BOOT_HSM20_HEADER, ++ .hsm20 = &hsm20_nand_hdr_4k_256_data, ++ }, { ++ .name = "spim:2k+64", ++ .type = NAND_BOOT_SPIM_HEADER, ++ .spim = &spim_nand_hdr_2k_64_data, ++ }, { ++ .name = "spim:2k+128", ++ .type = NAND_BOOT_SPIM_HEADER, ++ .spim = &spim_nand_hdr_2k_128_data, ++ }, { ++ .name = "spim:4k+256", ++ .type = NAND_BOOT_SPIM_HEADER, ++ .spim = &spim_nand_hdr_4k_256_data, + } + }; + +-const union nand_boot_header *mtk_nand_header_find(const char *name) ++const struct nand_header_type *mtk_nand_header_find(const char *name) + { + uint32_t i; + + for (i = 0; i < ARRAY_SIZE(nand_headers); i++) { + if (!strcmp(nand_headers[i].name, name)) +- return nand_headers[i].data; ++ return &nand_headers[i]; + } + + return NULL; + } + +-uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand) ++uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand) + { +- return 2 * le16_to_cpu(hdr_nand->pagesize); ++ switch (hdr_nand->type) { ++ case NAND_BOOT_HSM_HEADER: ++ return le32_to_cpu(hdr_nand->hsm->page_size); ++ ++ case NAND_BOOT_HSM20_HEADER: ++ return le32_to_cpu(hdr_nand->hsm20->page_size); ++ ++ case NAND_BOOT_SPIM_HEADER: ++ return le32_to_cpu(hdr_nand->spim->page_size); ++ ++ default: ++ return 2 * le16_to_cpu(hdr_nand->ap->pagesize); ++ } + } + + static int mtk_nand_header_ap_info(const void *ptr, +@@ -251,14 +542,45 @@ static int mtk_nand_header_ap_info(const + info->page_size = le16_to_cpu(nh->pagesize); + info->spare_size = le16_to_cpu(nh->oobsize); + info->gfh_offset = 2 * info->page_size; ++ info->snfi = true; + + return 0; + } + ++static int mtk_nand_header_hsm_info(const void *ptr, ++ struct nand_header_info *info) ++{ ++ union hsm_nand_boot_header *nh = (union hsm_nand_boot_header *)ptr; ++ ++ info->page_size = le16_to_cpu(nh->page_size); ++ info->spare_size = le16_to_cpu(nh->spare_size); ++ info->gfh_offset = info->page_size; ++ info->snfi = true; ++ ++ return 1; ++} ++ ++static int mtk_nand_header_spim_info(const void *ptr, ++ struct nand_header_info *info) ++{ ++ union spim_nand_boot_header *nh = (union spim_nand_boot_header *)ptr; ++ ++ info->page_size = le16_to_cpu(nh->page_size); ++ info->spare_size = le16_to_cpu(nh->spare_size); ++ info->gfh_offset = info->page_size; ++ info->snfi = false; ++ ++ return 1; ++} ++ + int mtk_nand_header_info(const void *ptr, struct nand_header_info *info) + { + if (!strcmp((char *)ptr, NAND_BOOT_NAME)) + return mtk_nand_header_ap_info(ptr, info); ++ else if (!strncmp((char *)ptr, HSM_NAND_BOOT_NAME, 8)) ++ return mtk_nand_header_hsm_info(ptr, info); ++ else if (!strncmp((char *)ptr, SPIM_NAND_BOOT_NAME, 8)) ++ return mtk_nand_header_spim_info(ptr, info); + + return -1; + } +@@ -273,14 +595,74 @@ bool is_mtk_nand_header(const void *ptr) + return false; + } + +-uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr) ++static uint16_t crc16(const uint8_t *p, uint32_t len) ++{ ++ uint16_t crc = 0x4f4e; ++ uint32_t i; ++ ++ while (len--) { ++ crc ^= *p++ << 8; ++ for (i = 0; i < 8; i++) ++ crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); ++ } ++ ++ return crc; ++} ++ ++static uint32_t mtk_nand_header_put_ap(const struct nand_header_type *hdr_nand, ++ void *ptr) + { +- union nand_boot_header *nh = (union nand_boot_header *)ptr; + int i; + + /* NAND device header, repeat 4 times */ +- for (i = 0; i < 4; i++) +- memcpy(nh + i, hdr_nand, sizeof(union nand_boot_header)); ++ for (i = 0; i < 4; i++) { ++ memcpy(ptr, hdr_nand->ap, sizeof(*hdr_nand->ap)); ++ ptr += sizeof(*hdr_nand->ap); ++ } ++ ++ return le16_to_cpu(hdr_nand->ap->pagesize); ++} + +- return le16_to_cpu(hdr_nand->pagesize); ++static uint32_t mtk_nand_header_put_hsm(const struct nand_header_type *hdr_nand, ++ void *ptr) ++{ ++ memcpy(ptr, hdr_nand->hsm, sizeof(*hdr_nand->hsm)); ++ return 0; ++} ++ ++static uint32_t mtk_nand_header_put_hsm20(const struct nand_header_type *hdr_nand, ++ void *ptr) ++{ ++ memcpy(ptr, hdr_nand->hsm20, sizeof(*hdr_nand->hsm20)); ++ return 0; ++} ++ ++static uint32_t mtk_nand_header_put_spim(const struct nand_header_type *hdr_nand, ++ void *ptr) ++{ ++ uint16_t crc; ++ ++ memcpy(ptr, hdr_nand->spim, sizeof(*hdr_nand->spim)); ++ ++ crc = crc16(ptr, 0x4e); ++ memcpy(ptr + 0x4e, &crc, sizeof(uint16_t)); ++ ++ return 0; ++} ++ ++uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, void *ptr) ++{ ++ switch (hdr_nand->type) { ++ case NAND_BOOT_HSM_HEADER: ++ return mtk_nand_header_put_hsm(hdr_nand, ptr); ++ ++ case NAND_BOOT_HSM20_HEADER: ++ return mtk_nand_header_put_hsm20(hdr_nand, ptr); ++ ++ case NAND_BOOT_SPIM_HEADER: ++ return mtk_nand_header_put_spim(hdr_nand, ptr); ++ ++ default: ++ return mtk_nand_header_put_ap(hdr_nand, ptr); ++ } + } +--- a/tools/mtk_nand_headers.h ++++ b/tools/mtk_nand_headers.h +@@ -16,6 +16,7 @@ struct nand_header_info { + uint32_t page_size; + uint32_t spare_size; + uint32_t gfh_offset; ++ bool snfi; + }; + + /* AP BROM Header for NAND */ +@@ -39,15 +40,117 @@ union nand_boot_header { + uint8_t data[0x80]; + }; + ++/* HSM BROM Header for NAND */ ++union hsm_nand_boot_header { ++ struct { ++ char id[8]; ++ uint32_t version; /* Header version */ ++ uint32_t config; /* Header config */ ++ uint32_t sector_size; /* ECC step size */ ++ uint32_t fdm_size; /* User OOB size of a step */ ++ uint32_t fdm_ecc_size; /* ECC parity size of a step */ ++ uint32_t lbs; ++ uint32_t page_size; /* NAND page size */ ++ uint32_t spare_size; /* NAND page spare size */ ++ uint32_t page_per_block; /* Pages of one block */ ++ uint32_t blocks; /* Total blocks of NAND chip */ ++ uint32_t plane_sel_position; /* Plane bit position */ ++ uint32_t pll; /* Value of pll reg */ ++ uint32_t acccon; /* Value of access timing reg */ ++ uint32_t strobe_sel; /* Value of DQS selection reg*/ ++ uint32_t acccon1; /* Value of access timing reg */ ++ uint32_t dqs_mux; /* Value of DQS mux reg */ ++ uint32_t dqs_ctrl; /* Value of DQS control reg */ ++ uint32_t delay_ctrl; /* Value of delay ctrl reg */ ++ uint32_t latch_lat; /* Value of latch latency reg */ ++ uint32_t sample_delay; /* Value of sample delay reg */ ++ uint32_t driving; /* Value of driving reg */ ++ uint32_t bl_start; /* Bootloader start addr */ ++ uint32_t bl_end; /* Bootloader end addr */ ++ uint8_t ecc_parity[42]; /* ECC parity of this header */ ++ }; ++ ++ uint8_t data[0x8E]; ++}; ++ ++/* HSM2.0 BROM Header for NAND */ ++union hsm20_nand_boot_header { ++ struct { ++ char id[8]; ++ uint32_t version; /* Header version */ ++ uint32_t config; /* Header config */ ++ uint32_t sector_size; /* ECC step size */ ++ uint32_t fdm_size; /* User OOB size of a step */ ++ uint32_t fdm_ecc_size; /* ECC parity size of a step */ ++ uint32_t lbs; ++ uint32_t page_size; /* NAND page size */ ++ uint32_t spare_size; /* NAND page spare size */ ++ uint32_t page_per_block; /* Pages of one block */ ++ uint32_t blocks; /* Total blocks of NAND chip */ ++ uint32_t plane_sel_position; /* Plane bit position */ ++ uint32_t pll; /* Value of pll reg */ ++ uint32_t acccon; /* Value of access timing reg */ ++ uint32_t strobe_sel; /* Value of DQS selection reg*/ ++ uint32_t acccon1; /* Value of access timing reg */ ++ uint32_t dqs_mux; /* Value of DQS mux reg */ ++ uint32_t dqs_ctrl; /* Value of DQS control reg */ ++ uint32_t delay_ctrl; /* Value of delay ctrl reg */ ++ uint32_t latch_lat; /* Value of latch latency reg */ ++ uint32_t sample_delay; /* Value of sample delay reg */ ++ uint32_t driving; /* Value of driving reg */ ++ uint32_t reserved; ++ uint32_t bl0_start; /* Bootloader start addr */ ++ uint32_t bl0_end; /* Bootloader end addr */ ++ uint32_t bl0_type; /* Bootloader type */ ++ uint8_t bl_reserve[84]; ++ uint8_t ecc_parity[42]; /* ECC parity of this header */ ++ }; ++ ++ uint8_t data[0xEA]; ++}; ++ ++/* SPIM BROM Header for SPI-NAND */ ++union spim_nand_boot_header { ++ struct { ++ char id[8]; ++ uint32_t version; /* Header version */ ++ uint32_t config; /* Header config */ ++ uint32_t page_size; /* NAND page size */ ++ uint32_t spare_size; /* NAND page spare size */ ++ uint16_t page_per_block; /* Pages of one block */ ++ uint16_t plane_sel_position; /* Plane bit position */ ++ uint16_t reserve_reg; ++ uint16_t reserve_val; ++ uint16_t ecc_error; /* ECC error reg addr */ ++ uint16_t ecc_mask; /* ECC error bit mask */ ++ uint32_t bl_start; /* Bootloader start addr */ ++ uint32_t bl_end; /* Bootloader end addr */ ++ uint8_t ecc_parity[32]; /* ECC parity of this header */ ++ uint32_t integrity_crc; /* CRC of this header */ ++ }; ++ ++ uint8_t data[0x50]; ++}; ++ ++enum nand_boot_header_type { ++ NAND_BOOT_AP_HEADER, ++ NAND_BOOT_HSM_HEADER, ++ NAND_BOOT_HSM20_HEADER, ++ NAND_BOOT_SPIM_HEADER ++}; ++ + #define NAND_BOOT_NAME "BOOTLOADER!" + #define NAND_BOOT_VERSION "V006" + #define NAND_BOOT_ID "NFIINFO" + ++#define HSM_NAND_BOOT_NAME "NANDCFG!" ++#define SPIM_NAND_BOOT_NAME "SPINAND!" ++ + /* Find nand header data by name */ +-const union nand_boot_header *mtk_nand_header_find(const char *name); ++const struct nand_header_type *mtk_nand_header_find(const char *name); + + /* Device header size using this nand header */ +-uint32_t mtk_nand_header_size(const union nand_boot_header *hdr_nand); ++uint32_t mtk_nand_header_size(const struct nand_header_type *hdr_nand); + + /* Get nand info from nand header (page size, spare size, ...) */ + int mtk_nand_header_info(const void *ptr, struct nand_header_info *info); +@@ -56,6 +159,7 @@ int mtk_nand_header_info(const void *ptr + bool is_mtk_nand_header(const void *ptr); + + /* Generate Device header using give nand header */ +-uint32_t mtk_nand_header_put(const union nand_boot_header *hdr_nand, void *ptr); ++uint32_t mtk_nand_header_put(const struct nand_header_type *hdr_nand, ++ void *ptr); + + #endif /* _MTK_NAND_HEADERS_H */ diff --git a/package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch b/package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch new file mode 100644 index 0000000000..5b0b263fd5 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/002-0032-MAINTAINERS-update-maintainer-for-MediaTek-ARM-platf.patch @@ -0,0 +1,43 @@ +From 180f8ce7cac9277406ee702ea9390a6f78981bda Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Wed, 31 Aug 2022 19:05:28 +0800 +Subject: [PATCH 32/32] MAINTAINERS: update maintainer for MediaTek ARM + platform + +Add new files for MediaTek ARM platform + +Reviewed-by: Simon Glass +Signed-off-by: Weijie Gao +--- + MAINTAINERS | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -340,20 +340,26 @@ F: doc/device-tree-bindings/phy/phy-mtk- + F: doc/device-tree-bindings/usb/mediatek,* + F: doc/README.mediatek + F: drivers/clk/mediatek/ ++F: drivers/cpu/mtk_cpu.c ++F: drivers/i2c/mtk_i2c.c + F: drivers/mmc/mtk-sd.c + F: drivers/phy/phy-mtk-* + F: drivers/pinctrl/mediatek/ + F: drivers/power/domain/mtk-power-domain.c + F: drivers/ram/mediatek/ + F: drivers/spi/mtk_snfi_spi.c ++F: drivers/spi/mtk_spim.c + F: drivers/timer/mtk_timer.c + F: drivers/usb/host/xhci-mtk.c + F: drivers/usb/mtu3/ + F: drivers/watchdog/mtk_wdt.c + F: drivers/net/mtk_eth.c ++F: drivers/net/mtk_eth.h + F: drivers/reset/reset-mediatek.c + F: tools/mtk_image.c + F: tools/mtk_image.h ++F: tools/mtk_nand_headers.c ++F: tools/mtk_nand_headers.h + N: mediatek + + ARM MICROCHIP/ATMEL AT91 diff --git a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch index b6243db9c2..571b883fb9 100644 --- a/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch +++ b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch @@ -89,7 +89,7 @@ Signed-off-by: Weijie Gao reg = <0x11014000 0x1000>; --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -131,9 +131,11 @@ config SYS_CONFIG_NAME +@@ -133,9 +133,11 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string diff --git a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch index 9fae6d056f..63301fd535 100644 --- a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch @@ -40,7 +40,7 @@ } --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig -@@ -138,4 +138,8 @@ config MTK_BROM_HEADER_INFO +@@ -140,4 +140,8 @@ config MTK_BROM_HEADER_INFO source "board/mediatek/mt7629/Kconfig" diff --git a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch index 48835e43af..d48de66064 100644 --- a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch +++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch @@ -51,6 +51,7 @@ +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y @@ -246,6 +247,7 @@ +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y @@ -442,6 +444,7 @@ +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y @@ -637,6 +640,7 @@ +CONFIG_CMD_BUTTON=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_DM=y +CONFIG_CMD_DNS=y