From: Gabor Juhos Date: Thu, 15 Jul 2010 19:45:40 +0000 (+0000) Subject: ramips: add mdio_cfg configuration for the ethernet driver X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=0d8c036e56d462a0aa77f1ab410dcf1c38130aec;p=openwrt%2Fstaging%2Fzorun.git ramips: add mdio_cfg configuration for the ethernet driver SVN-Revision: 22211 --- diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h index ec1e7d4fa2..25e91fec6d 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/ramips_eth_platform.h @@ -25,6 +25,11 @@ struct ramips_eth_platform_data void (*reset_fe)(void); int min_pkt_len; unsigned long sys_freq; + + int speed; + int duplex; + int tx_fc; + int rx_fc; }; #endif /* _RAMIPS_ETH_PLATFORM_H */ diff --git a/target/linux/ramips/files/drivers/net/ramips.c b/target/linux/ramips/files/drivers/net/ramips.c index 4274c923bb..a979fe04c7 100644 --- a/target/linux/ramips/files/drivers/net/ramips.c +++ b/target/linux/ramips/files/drivers/net/ramips.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -77,6 +78,47 @@ ramips_hw_set_macaddr(unsigned char *mac) RAMIPS_GDMA1_MAC_ADRL); } +#ifdef CONFIG_RALINK_RT288X +static void +ramips_setup_mdio_cfg(struct raeth_priv *re) +{ + unsigned int mdio_cfg; + + mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 | + RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 | + RAMIPS_MDIO_CFG_GP1_FRC_EN; + + if (re->duplex == DUPLEX_FULL) + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX; + + if (re->tx_fc) + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX; + + if (re->rx_fc) + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX; + + switch (re->speed) { + case SPEED_10: + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10; + break; + case SPEED_100: + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100; + break; + case SPEED_1000: + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000; + break; + default: + BUG(); + } + + ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG); +} +#else +static inline void ramips_setup_mdio_cfg(struct raeth_priv *re) +{ +} +#endif /* CONFIG_RALINK_RT288X */ + static void ramips_cleanup_dma(struct raeth_priv *re) { @@ -334,6 +376,8 @@ ramips_eth_open(struct net_device *dev) (unsigned long)dev); tasklet_init(&priv->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev); + ramips_setup_mdio_cfg(priv); + ramips_fe_wr(RAMIPS_DELAY_INIT, RAMIPS_DLY_INT_CFG); ramips_fe_wr(RAMIPS_TX_DLY_INT | RAMIPS_RX_DLY_INT, RAMIPS_FE_INT_ENABLE); ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) & @@ -442,6 +486,11 @@ ramips_eth_plat_probe(struct platform_device *plat) ramips_dev->netdev_ops = &ramips_eth_netdev_ops; priv = netdev_priv(ramips_dev); + + priv->speed = data->speed; + priv->duplex = data->duplex; + priv->rx_fc = data->rx_fc; + priv->tx_fc = data->tx_fc; priv->plat = data; err = register_netdev(ramips_dev); diff --git a/target/linux/ramips/files/drivers/net/ramips_eth.h b/target/linux/ramips/files/drivers/net/ramips_eth.h index 593dd1d87a..ef644c11b7 100644 --- a/target/linux/ramips/files/drivers/net/ramips_eth.h +++ b/target/linux/ramips/files/drivers/net/ramips_eth.h @@ -122,6 +122,33 @@ #define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68) #define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C) +/* MDIO_CFG register bits */ +#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29) +#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16) +#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15) +#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13) +#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13) +#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13) +#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12) +#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11) +#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10) +#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9) +#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6) +#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5) +#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2) +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3 + /* uni-cast port */ #define RAMIPS_GDM1_ICS_EN BIT(22) #define RAMIPS_GDM1_TCS_EN BIT(21) @@ -201,6 +228,11 @@ struct raeth_priv spinlock_t page_lock; struct ramips_eth_platform_data *plat; + + int speed; + int duplex; + int tx_fc; + int rx_fc; }; #endif /* RAMIPS_ETH_H */