From: Jack Xiao <Jack.Xiao@amd.com>
Date: Thu, 18 Apr 2019 09:37:14 +0000 (+0800)
Subject: drm/amdgpu/vcn2: don't access register when power gated
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=0b8794e252fcf47d840985dde1d7a4f8802b61a7;p=openwrt%2Fstaging%2Fblogic.git

drm/amdgpu/vcn2: don't access register when power gated

It will cause bus hang to access register UVD_STATUS
when VCN is in the state of power gated.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 36a80e487b8d..04cac0bb5900 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -277,7 +277,8 @@ static int vcn_v2_0_hw_fini(void *handle)
 	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
 	int i;
 
-	if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
+	if (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+	    RREG32_SOC15(VCN, 0, mmUVD_STATUS))
 		vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 
 	ring->sched.ready = false;