From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Thu, 24 Jan 2013 13:29:51 +0000 (+0200)
Subject: drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=07ec7ec55baec26a3b77d310b0399d2e20f0f67b;p=openwrt%2Fstaging%2Fblogic.git

drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable

Instead of 0x18xxxx use (VLV_DISPLAY_BASE + xxxx).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86c4ffa3c050..06a37a09245e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -554,7 +554,7 @@
 #define IIR		0x020a4
 #define IMR		0x020a8
 #define ISR		0x020ac
-#define VLV_GUNIT_CLOCK_GATE	0x182060
+#define VLV_GUNIT_CLOCK_GATE	(VLV_DISPLAY_BASE + 0x2060)
 #define   GCFG_DIS		(1<<8)
 #define VLV_IIR_RW	0x182084
 #define VLV_IER		0x1820a0