From: Nicolas Thill <nico@openwrt.org>
Date: Mon, 1 Oct 2007 10:16:14 +0000 (+0000)
Subject: revert to vlynq bus clock divisor guessing
X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=05f07554267ea9c054c6b2b05628c85330cf894f;p=openwrt%2Fstaging%2Fstintel.git

revert to vlynq bus clock divisor guessing

SVN-Revision: 9086
---

diff --git a/target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c b/target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c
index bffea51355..7a640dbef7 100644
--- a/target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c
+++ b/target/linux/ar7/files/arch/mips/ar7/vlynq-pci.c
@@ -313,7 +313,7 @@ static int vlynq_pci_probe(struct vlynq_device *dev)
 	if (result)
 		return result;
 
-	dev->divisor = vlynq_ldiv4;
+	dev->divisor = vlynq_div_auto;
 	result = vlynq_device_enable(dev);
 	if (result)
 		return result;