From: Daniel Dickinson Date: Fri, 19 Nov 2010 13:41:54 +0000 (+0000) Subject: Initial support for Telsey CPVA642 boards (no vlans, no DSL, GPIO led/buttons not... X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=049e59a27be91dc9731f53b4868795adde682fd4;p=openwrt%2Fstaging%2Fwigyori.git Initial support for Telsey CPVA642 boards (no vlans, no DSL, GPIO led/buttons not known). SVN-Revision: 24040 --- diff --git a/target/linux/brcm63xx/image/Makefile b/target/linux/brcm63xx/image/Makefile index 56d048bbbd..4f41889a52 100644 --- a/target/linux/brcm63xx/image/Makefile +++ b/target/linux/brcm63xx/image/Makefile @@ -172,6 +172,9 @@ define Image/Build # RG100A,DB120 etc. $(call Image/Build/RG100A,$(1),96358VW2,6358,0x20000,RG100A_DB120) + # Telsey CPVA642-type (e.g. CPA-ZNTE60T) + $(call Image/Build/CFE,$(1),CPVA642,6358,CPA-ZNTE60T,,--signature "Telsey Tlc",--signature2 "99.99.999",--second-image-flag "0") + endef $(eval $(call BuildImage)) diff --git a/target/linux/brcm63xx/patches-2.6.35/310-CPVA642_board.patch b/target/linux/brcm63xx/patches-2.6.35/310-CPVA642_board.patch new file mode 100644 index 0000000000..bc71425d94 --- /dev/null +++ b/target/linux/brcm63xx/patches-2.6.35/310-CPVA642_board.patch @@ -0,0 +1,37 @@ +--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c ++++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c +@@ -677,6 +677,26 @@ static struct board_info __initdata boar + }, + }; + ++static struct board_info __initdata board_CPVA642 = { ++ .name = "CPVA642", ++ .expected_cpu_id = 0x6358, ++ ++ .has_uart0 = 1, ++ .has_enet1 = 1, ++ .has_pci = 1, ++ ++ .enet1 = { ++ .force_speed_100 = 1, ++ .force_duplex_full = 1, ++ }, ++ ++ .has_ohci0 = 1, ++ .has_ehci0 = 1, ++ ++ /* GPIOs not yet known for this device */ ++}; ++ ++ + static struct board_info __initdata board_AGPFS0 = { + .name = "AGPF-S0", + .expected_cpu_id = 0x6358, +@@ -1339,6 +1359,7 @@ static const struct board_info __initdat + &board_96358vw, + &board_96358vw2, + &board_AGPFS0, ++ &board_CPVA642, + &board_DWVS0, + &board_nb4_ser_r0, + &board_nb4_ser_r1,