From: Luka Perkov Date: Wed, 2 Oct 2013 00:33:47 +0000 (+0000) Subject: kirkwood: add linux 3.10 support X-Git-Tag: reboot~9045 X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=0331657a4f65aef4fb28eb0e537b5d227cc2eb4f;p=openwrt%2Fopenwrt.git kirkwood: add linux 3.10 support Backport appropriate patches to allow using device tree only board defintions. Signed-off-by: Jonas Gorski SVN-Revision: 38280 --- diff --git a/target/linux/kirkwood/config-3.10 b/target/linux/kirkwood/config-3.10 new file mode 100644 index 0000000000..b66b7a3268 --- /dev/null +++ b/target/linux/kirkwood/config-3.10 @@ -0,0 +1,269 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_KIRKWOOD=y +CONFIG_ARCH_KIRKWOOD_DT=y +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_NR_BANKS=8 +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_THUMB is not set +# CONFIG_ARPD is not set +CONFIG_ATAGS=y +CONFIG_BLK_DEV_SD=y +CONFIG_CACHE_FEROCEON_L2=y +# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set +# CONFIG_CACHE_L2X0 is not set +# CONFIG_CHARGER_MANAGER is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMDLINE="rootdelay=1 root=/dev/mmcblk0p1 noinitrd console=ttyS0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_COMMON_CLK=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_FEROCEON=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FEROCEON=y +# CONFIG_CPU_FEROCEON_OLD_ID is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_TLB_FEROCEON=y +CONFIG_CPU_USE_DOMAINS=y +CONFIG_CRC16=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DLCI is not set +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ATOMIC64=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MVEBU=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HAMRADIO is not set +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_AOUT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HW_RANDOM=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_INET_LRO=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_WORK=y +CONFIG_KTIME_SCALAR=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MACH_D2NET_V2 is not set +# CONFIG_MACH_DLINK_KIRKWOOD_DT is not set +# CONFIG_MACH_DOCKSTAR is not set +CONFIG_MACH_ESATA_SHEEVAPLUG=y +# CONFIG_MACH_GURUPLUG is not set +# CONFIG_MACH_INETSPACE_V2 is not set +# CONFIG_MACH_MV88F6281GTW_GE is not set +# CONFIG_MACH_NET2BIG_V2 is not set +# CONFIG_MACH_NET5BIG_V2 is not set +# CONFIG_MACH_NETSPACE_MAX_V2 is not set +# CONFIG_MACH_NETSPACE_V2 is not set +CONFIG_MACH_OPENRD=y +CONFIG_MACH_OPENRD_BASE=y +CONFIG_MACH_OPENRD_CLIENT=y +# CONFIG_MACH_OPENRD_ULTIMATE is not set +# CONFIG_MACH_RD88F6192_NAS is not set +# CONFIG_MACH_RD88F6281 is not set +CONFIG_MACH_SHEEVAPLUG=y +# CONFIG_MACH_T5325 is not set +# CONFIG_MACH_TS219 is not set +# CONFIG_MACH_TS219_DT is not set +# CONFIG_MACH_TS41X is not set +CONFIG_MDIO_BOARDINFO=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_MVSDIO=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_SM_COMMON is not set +CONFIG_MTD_UIMAGE_SPLIT=y +CONFIG_MV643XX_ETH=y +CONFIG_MVEBU_CLK_CORE=y +CONFIG_MVEBU_CLK_GATING=y +CONFIG_MVEBU_MBUS=y +CONFIG_MVMDIO=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_PER_CPU_KM=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MV88E6123_61_65=y +CONFIG_NET_DSA_MV88E6131=y +CONFIG_NET_DSA_MV88E6XXX=y +CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y +CONFIG_NET_DSA_TAG_DSA=y +CONFIG_NET_DSA_TAG_EDSA=y +# CONFIG_NET_IP_TUNNEL is not set +CONFIG_NLS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DEVICE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_I2C=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OUTER_CACHE=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_MVEBU=y +# CONFIG_PDA_POWER is not set +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PINCONF=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_KIRKWOOD=y +CONFIG_PINCTRL_MVEBU=y +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_PINMUX=y +CONFIG_PLAT_ORION=y +CONFIG_PLAT_ORION_LEGACY=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +# CONFIG_POWER_RESET_QNAP is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_PROC_DEVICETREE=y +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_RFKILL_REGULATOR is not set +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MV is not set +CONFIG_SCHED_HRTICK=y +CONFIG_SCSI=y +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_ORION=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_UID16=y +CONFIG_UIDGID_CONVERTED=y +CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" +CONFIG_USB=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB_COMMON=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_ORION=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USE_OF=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFP is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WAN=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/kirkwood/patches-3.10/0001-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch b/target/linux/kirkwood/patches-3.10/0001-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch new file mode 100644 index 0000000000..8f6f547c7a --- /dev/null +++ b/target/linux/kirkwood/patches-3.10/0001-of-pci-Provide-support-for-parsing-PCI-DT-ranges-pro.patch @@ -0,0 +1,203 @@ +From 6b5917890ada1dc078ee64af2500cd6289fcf9bc Mon Sep 17 00:00:00 2001 +From: Andrew Murray +Date: Tue, 7 May 2013 16:31:12 +0100 +Subject: [PATCH 01/29] of/pci: Provide support for parsing PCI DT ranges + property + +This patch factors out common implementation patterns to reduce overall kernel +code and provide a means for host bridge drivers to directly obtain struct +resources from the DT's ranges property without relying on architecture specific +DT handling. This will make it easier to write archiecture independent host bridge +drivers and mitigate against further duplication of DT parsing code. + +This patch can be used in the following way: + + struct of_pci_range_parser parser; + struct of_pci_range range; + + if (of_pci_range_parser_init(&parser, np)) + ; //no ranges property + + for_each_of_pci_range(&parser, &range) { + + /* + directly access properties of the address range, e.g.: + range.pci_space, range.pci_addr, range.cpu_addr, + range.size, range.flags + + alternatively obtain a struct resource, e.g.: + struct resource res; + of_pci_range_to_resource(&range, np, &res); + */ + } + +Additionally the implementation takes care of adjacent ranges and merges them +into a single range (as was the case with powerpc and microblaze). + +Signed-off-by: Andrew Murray +Signed-off-by: Liviu Dudau +Signed-off-by: Thomas Petazzoni +Reviewed-by: Rob Herring +Tested-by: Thomas Petazzoni +Tested-by: Linus Walleij +Tested-by: Jingoo Han +Acked-by: Grant Likely +--- + drivers/of/address.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++ + include/linux/of_address.h | 48 +++++++++++++++++++++++++++++++++ + 2 files changed, 115 insertions(+) + +diff --git a/drivers/of/address.c b/drivers/of/address.c +index 7c8221d..b55c218 100644 +--- a/drivers/of/address.c ++++ b/drivers/of/address.c +@@ -231,6 +231,73 @@ int of_pci_address_to_resource(struct device_node *dev, int bar, + return __of_address_to_resource(dev, addrp, size, flags, NULL, r); + } + EXPORT_SYMBOL_GPL(of_pci_address_to_resource); ++ ++int of_pci_range_parser_init(struct of_pci_range_parser *parser, ++ struct device_node *node) ++{ ++ const int na = 3, ns = 2; ++ int rlen; ++ ++ parser->node = node; ++ parser->pna = of_n_addr_cells(node); ++ parser->np = parser->pna + na + ns; ++ ++ parser->range = of_get_property(node, "ranges", &rlen); ++ if (parser->range == NULL) ++ return -ENOENT; ++ ++ parser->end = parser->range + rlen / sizeof(__be32); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(of_pci_range_parser_init); ++ ++struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser, ++ struct of_pci_range *range) ++{ ++ const int na = 3, ns = 2; ++ ++ if (!range) ++ return NULL; ++ ++ if (!parser->range || parser->range + parser->np > parser->end) ++ return NULL; ++ ++ range->pci_space = parser->range[0]; ++ range->flags = of_bus_pci_get_flags(parser->range); ++ range->pci_addr = of_read_number(parser->range + 1, ns); ++ range->cpu_addr = of_translate_address(parser->node, ++ parser->range + na); ++ range->size = of_read_number(parser->range + parser->pna + na, ns); ++ ++ parser->range += parser->np; ++ ++ /* Now consume following elements while they are contiguous */ ++ while (parser->range + parser->np <= parser->end) { ++ u32 flags, pci_space; ++ u64 pci_addr, cpu_addr, size; ++ ++ pci_space = be32_to_cpup(parser->range); ++ flags = of_bus_pci_get_flags(parser->range); ++ pci_addr = of_read_number(parser->range + 1, ns); ++ cpu_addr = of_translate_address(parser->node, ++ parser->range + na); ++ size = of_read_number(parser->range + parser->pna + na, ns); ++ ++ if (flags != range->flags) ++ break; ++ if (pci_addr != range->pci_addr + range->size || ++ cpu_addr != range->cpu_addr + range->size) ++ break; ++ ++ range->size += size; ++ parser->range += parser->np; ++ } ++ ++ return range; ++} ++EXPORT_SYMBOL_GPL(of_pci_range_parser_one); ++ + #endif /* CONFIG_PCI */ + + /* +diff --git a/include/linux/of_address.h b/include/linux/of_address.h +index 0506eb5..4c2e6f2 100644 +--- a/include/linux/of_address.h ++++ b/include/linux/of_address.h +@@ -4,6 +4,36 @@ + #include + #include + ++struct of_pci_range_parser { ++ struct device_node *node; ++ const __be32 *range; ++ const __be32 *end; ++ int np; ++ int pna; ++}; ++ ++struct of_pci_range { ++ u32 pci_space; ++ u64 pci_addr; ++ u64 cpu_addr; ++ u64 size; ++ u32 flags; ++}; ++ ++#define for_each_of_pci_range(parser, range) \ ++ for (; of_pci_range_parser_one(parser, range);) ++ ++static inline void of_pci_range_to_resource(struct of_pci_range *range, ++ struct device_node *np, ++ struct resource *res) ++{ ++ res->flags = range->flags; ++ res->start = range->cpu_addr; ++ res->end = range->cpu_addr + range->size - 1; ++ res->parent = res->child = res->sibling = NULL; ++ res->name = np->full_name; ++} ++ + #ifdef CONFIG_OF_ADDRESS + extern u64 of_translate_address(struct device_node *np, const __be32 *addr); + extern bool of_can_translate_address(struct device_node *dev); +@@ -27,6 +57,11 @@ static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } + #define pci_address_to_pio pci_address_to_pio + #endif + ++extern int of_pci_range_parser_init(struct of_pci_range_parser *parser, ++ struct device_node *node); ++extern struct of_pci_range *of_pci_range_parser_one( ++ struct of_pci_range_parser *parser, ++ struct of_pci_range *range); + #else /* CONFIG_OF_ADDRESS */ + #ifndef of_address_to_resource + static inline int of_address_to_resource(struct device_node *dev, int index, +@@ -53,6 +88,19 @@ static inline const __be32 *of_get_address(struct device_node *dev, int index, + { + return NULL; + } ++ ++static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser, ++ struct device_node *node) ++{ ++ return -1; ++} ++ ++static inline struct of_pci_range *of_pci_range_parser_one( ++ struct of_pci_range_parser *parser, ++ struct of_pci_range *range) ++{ ++ return NULL; ++} + #endif /* CONFIG_OF_ADDRESS */ + + +-- +1.8.4.rc1 + diff --git a/target/linux/kirkwood/patches-3.10/0003-of-pci-Add-of_pci_parse_bus_range-function.patch b/target/linux/kirkwood/patches-3.10/0003-of-pci-Add-of_pci_parse_bus_range-function.patch new file mode 100644 index 0000000000..74a839701c --- /dev/null +++ b/target/linux/kirkwood/patches-3.10/0003-of-pci-Add-of_pci_parse_bus_range-function.patch @@ -0,0 +1,61 @@ +From 6275a8e0bacac9702350b6a003470a9ce67c9139 Mon Sep 17 00:00:00 2001 +From: Thierry Reding +Date: Mon, 11 Feb 2013 09:22:20 +0100 +Subject: [PATCH 03/29] of/pci: Add of_pci_parse_bus_range() function + +This function can be used to parse a bus-range property as specified by +device nodes representing PCI bridges. + +Signed-off-by: Thierry Reding +--- + drivers/of/of_pci.c | 25 +++++++++++++++++++++++++ + include/linux/of_pci.h | 1 + + 2 files changed, 26 insertions(+) + +diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c +index 4dd7b9b..42c687a 100644 +--- a/drivers/of/of_pci.c ++++ b/drivers/of/of_pci.c +@@ -64,3 +64,28 @@ int of_pci_get_devfn(struct device_node *np) + return (be32_to_cpup(reg) >> 8) & 0xff; + } + EXPORT_SYMBOL_GPL(of_pci_get_devfn); ++ ++/** ++ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device ++ * @node: device node ++ * @res: address to a struct resource to return the bus-range ++ * ++ * Returns 0 on success or a negative error-code on failure. ++ */ ++int of_pci_parse_bus_range(struct device_node *node, struct resource *res) ++{ ++ const __be32 *values; ++ int len; ++ ++ values = of_get_property(node, "bus-range", &len); ++ if (!values || len < sizeof(*values) * 2) ++ return -EINVAL; ++ ++ res->name = node->name; ++ res->start = be32_to_cpup(values++); ++ res->end = be32_to_cpup(values); ++ res->flags = IORESOURCE_BUS; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(of_pci_parse_bus_range); +diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h +index 91ec484..7a04826 100644 +--- a/include/linux/of_pci.h ++++ b/include/linux/of_pci.h +@@ -11,5 +11,6 @@ struct device_node; + struct device_node *of_pci_find_child_device(struct device_node *parent, + unsigned int devfn); + int of_pci_get_devfn(struct device_node *np); ++int of_pci_parse_bus_range(struct device_node *node, struct resource *res); + + #endif +-- +1.8.4.rc1 + diff --git a/target/linux/kirkwood/patches-3.10/0004-clk-mvebu-create-parent-child-relation-for-PCIe-cloc.patch b/target/linux/kirkwood/patches-3.10/0004-clk-mvebu-create-parent-child-relation-for-PCIe-cloc.patch new file mode 100644 index 0000000000..faf9de6738 --- /dev/null +++ b/target/linux/kirkwood/patches-3.10/0004-clk-mvebu-create-parent-child-relation-for-PCIe-cloc.patch @@ -0,0 +1,35 @@ +From adebeab033de18cabf880f98d2167095520243f2 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Fri, 7 Dec 2012 20:35:20 +0100 +Subject: [PATCH 04/29] clk: mvebu: create parent-child relation for PCIe + clocks on Armada 370 + +The Armada 370 has two gatable clocks for each PCIe interface, and we +want both of them to be enabled. We therefore make one of the two +clocks a child of the other, as we did for the sataX and sataXlnk +clocks on Armada XP. + +Signed-off-by: Thomas Petazzoni +Cc: Mike Turquette +--- + drivers/clk/mvebu/clk-gating-ctrl.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c +index ebf141d..b35785a 100644 +--- a/drivers/clk/mvebu/clk-gating-ctrl.c ++++ b/drivers/clk/mvebu/clk-gating-ctrl.c +@@ -119,8 +119,8 @@ static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = { + { "pex1_en", NULL, 2 }, + { "ge1", NULL, 3 }, + { "ge0", NULL, 4 }, +- { "pex0", NULL, 5 }, +- { "pex1", NULL, 9 }, ++ { "pex0", "pex0_en", 5 }, ++ { "pex1", "pex1_en", 9 }, + { "sata0", NULL, 15 }, + { "sdio", NULL, 17 }, + { "tdm", NULL, 25 }, +-- +1.8.4.rc1 + diff --git a/target/linux/kirkwood/patches-3.10/0005-clk-mvebu-add-more-PCIe-clocks-for-Armada-XP.patch b/target/linux/kirkwood/patches-3.10/0005-clk-mvebu-add-more-PCIe-clocks-for-Armada-XP.patch new file mode 100644 index 0000000000..b41c8f7f7b --- /dev/null +++ b/target/linux/kirkwood/patches-3.10/0005-clk-mvebu-add-more-PCIe-clocks-for-Armada-XP.patch @@ -0,0 +1,55 @@ +From 7bda5e7704872a2f01a6c980bb7616d689520ea5 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Fri, 18 Jan 2013 16:42:01 +0100 +Subject: [PATCH 05/29] clk: mvebu: add more PCIe clocks for Armada XP + +The current revision of the datasheet only mentions the gatable clocks +for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention +the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0 +interfaces. After confirmation with Marvell engineers, this patch adds +the missing gatable clocks for those PCIe interfaces. + +It also changes the name of the previously existing PCIe gatable +clocks, in order to match the naming using the datasheets. + +Signed-off-by: Thomas Petazzoni +Cc: Mike Turquette +--- + drivers/clk/mvebu/clk-gating-ctrl.c | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c +index b35785a..2f03723 100644 +--- a/drivers/clk/mvebu/clk-gating-ctrl.c ++++ b/drivers/clk/mvebu/clk-gating-ctrl.c +@@ -137,10 +137,14 @@ static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = { + { "ge2", NULL, 2 }, + { "ge1", NULL, 3 }, + { "ge0", NULL, 4 }, +- { "pex0", NULL, 5 }, +- { "pex1", NULL, 6 }, +- { "pex2", NULL, 7 }, +- { "pex3", NULL, 8 }, ++ { "pex00", NULL, 5 }, ++ { "pex01", NULL, 6 }, ++ { "pex02", NULL, 7 }, ++ { "pex03", NULL, 8 }, ++ { "pex10", NULL, 9 }, ++ { "pex11", NULL, 10 }, ++ { "pex12", NULL, 11 }, ++ { "pex13", NULL, 12 }, + { "bp", NULL, 13 }, + { "sata0lnk", NULL, 14 }, + { "sata0", "sata0lnk", 15 }, +@@ -152,6 +156,8 @@ static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = { + { "xor0", NULL, 22 }, + { "crypto", NULL, 23 }, + { "tdm", NULL, 25 }, ++ { "pex20", NULL, 26 }, ++ { "pex30", NULL, 27 }, + { "xor1", NULL, 28 }, + { "sata1lnk", NULL, 29 }, + { "sata1", "sata1lnk", 30 }, +-- +1.8.4.rc1 + diff --git a/target/linux/kirkwood/patches-3.10/0006-pci-PCIe-driver-for-Marvell-Armada-370-XP-systems.patch b/target/linux/kirkwood/patches-3.10/0006-pci-PCIe-driver-for-Marvell-Armada-370-XP-systems.patch new file mode 100644 index 0000000000..50396e0d69 --- /dev/null +++ b/target/linux/kirkwood/patches-3.10/0006-pci-PCIe-driver-for-Marvell-Armada-370-XP-systems.patch @@ -0,0 +1,1195 @@ +From b18ed8465d6c2e3b7057d5bb2fc3da5cb15e3fb1 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Fri, 18 Jan 2013 17:42:58 +0100 +Subject: [PATCH 06/29] pci: PCIe driver for Marvell Armada 370/XP systems + +This driver implements the support for the PCIe interfaces on the +Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to +cover earlier families of Marvell SoCs, such as Dove, Orion and +Kirkwood. + +The driver implements the hw_pci operations needed by the core ARM PCI +code to setup PCI devices and get their corresponding IRQs, and the +pci_ops operations that are used by the PCI core to read/write the +configuration space of PCI devices. + +Since the PCIe interfaces of Marvell SoCs are completely separate and +not linked together in a bus, this driver sets up an emulated PCI host +bridge, with one PCI-to-PCI bridge as child for each hardware PCIe +interface. + +In addition, this driver enumerates the different PCIe slots, and for +those having a device plugged in, it sets up the necessary address +decoding windows, using the mvebu-mbus driver. + +Signed-off-by: Thomas Petazzoni +Acked-by: Bjorn Helgaas +--- + .../devicetree/bindings/pci/mvebu-pci.txt | 220 ++++++ + drivers/pci/Kconfig | 2 + + drivers/pci/Makefile | 3 + + drivers/pci/host/Kconfig | 8 + + drivers/pci/host/Makefile | 1 + + drivers/pci/host/pci-mvebu.c | 879 +++++++++++++++++++++ + 6 files changed, 1113 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt + create mode 100644 drivers/pci/host/Kconfig + create mode 100644 drivers/pci/host/Makefile + create mode 100644 drivers/pci/host/pci-mvebu.c + +diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt +new file mode 100644 +index 0000000..eb69d92 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt +@@ -0,0 +1,220 @@ ++* Marvell EBU PCIe interfaces ++ ++Mandatory properties: ++- compatible: one of the following values: ++ marvell,armada-370-pcie ++ marvell,armada-xp-pcie ++- #address-cells, set to <3> ++- #size-cells, set to <2> ++- #interrupt-cells, set to <1> ++- bus-range: PCI bus numbers covered ++- device_type, set to "pci" ++- ranges: ranges for the PCI memory and I/O regions, as well as the ++ MMIO registers to control the PCIe interfaces. ++ ++In addition, the Device Tree node must have sub-nodes describing each ++PCIe interface, having the following mandatory properties: ++- reg: used only for interrupt mapping, so only the first four bytes ++ are used to refer to the correct bus number and device number. ++- assigned-addresses: reference to the MMIO registers used to control ++ this PCIe interface. ++- clocks: the clock associated to this PCIe interface ++- marvell,pcie-port: the physical PCIe port number ++- status: either "disabled" or "okay" ++- device_type, set to "pci" ++- #address-cells, set to <3> ++- #size-cells, set to <2> ++- #interrupt-cells, set to <1> ++- ranges, empty property. ++- interrupt-map-mask and interrupt-map, standard PCI properties to ++ define the mapping of the PCIe interface to interrupt numbers. ++ ++and the following optional properties: ++- marvell,pcie-lane: the physical PCIe lane number, for ports having ++ multiple lanes. If this property is not found, we assume that the ++ value is 0. ++ ++Example: ++ ++pcie-controller { ++ compatible = "marvell,armada-xp-pcie"; ++ status = "disabled"; ++ device_type = "pci"; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x00 0xff>; ++ ++ ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ ++ 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ ++ 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ ++ 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ ++ 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ ++ 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ ++ 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ ++ 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */ ++ 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */ ++ 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */ ++ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ ++ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ ++ ++ pcie@1,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 58>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 5>; ++ status = "disabled"; ++ }; ++ ++ pcie@2,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>; ++ reg = <0x1000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 59>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <1>; ++ clocks = <&gateclk 6>; ++ status = "disabled"; ++ }; ++ ++ pcie@3,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>; ++ reg = <0x1800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 60>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <2>; ++ clocks = <&gateclk 7>; ++ status = "disabled"; ++ }; ++ ++ pcie@4,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>; ++ reg = <0x2000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 61>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <3>; ++ clocks = <&gateclk 8>; ++ status = "disabled"; ++ }; ++ ++ pcie@5,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; ++ reg = <0x2800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 62>; ++ marvell,pcie-port = <1>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 9>; ++ status = "disabled"; ++ }; ++ ++ pcie@6,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>; ++ reg = <0x3000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 63>; ++ marvell,pcie-port = <1>; ++ marvell,pcie-lane = <1>; ++ clocks = <&gateclk 10>; ++ status = "disabled"; ++ }; ++ ++ pcie@7,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>; ++ reg = <0x3800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 64>; ++ marvell,pcie-port = <1>; ++ marvell,pcie-lane = <2>; ++ clocks = <&gateclk 11>; ++ status = "disabled"; ++ }; ++ ++ pcie@8,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>; ++ reg = <0x4000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 65>; ++ marvell,pcie-port = <1>; ++ marvell,pcie-lane = <3>; ++ clocks = <&gateclk 12>; ++ status = "disabled"; ++ }; ++ pcie@9,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>; ++ reg = <0x4800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 99>; ++ marvell,pcie-port = <2>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 26>; ++ status = "disabled"; ++ }; ++ ++ pcie@10,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>; ++ reg = <0x5000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 103>; ++ marvell,pcie-port = <3>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 27>; ++ status = "disabled"; ++ }; ++}; +diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig +index 6d51aa6..ac45398 100644 +--- a/drivers/pci/Kconfig ++++ b/drivers/pci/Kconfig +@@ -119,3 +119,5 @@ config PCI_IOAPIC + config PCI_LABEL + def_bool y if (DMI || ACPI) + select NLS ++ ++source "drivers/pci/host/Kconfig" +diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile +index 0c3efcf..6ebf5bf 100644 +--- a/drivers/pci/Makefile ++++ b/drivers/pci/Makefile +@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o + obj-$(CONFIG_OF) += of.o + + ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG ++ ++# PCI host controller drivers ++obj-y += host/ +diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig +new file mode 100644 +index 0000000..6918fbc +--- /dev/null ++++ b/drivers/pci/host/Kconfig +@@ -0,0 +1,8 @@ ++menu "PCI host controller drivers" ++ depends on PCI ++ ++config PCI_MVEBU ++ bool "Marvell EBU PCIe controller" ++ depends on ARCH_MVEBU ++ ++endmenu +diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile +new file mode 100644 +index 0000000..5ea2d8b +--- /dev/null ++++ b/drivers/pci/host/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o +diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c +new file mode 100644 +index 0000000..b0ee63b +--- /dev/null ++++ b/drivers/pci/host/pci-mvebu.c +@@ -0,0 +1,879 @@ ++/* ++ * PCIe driver for Marvell Armada 370 and Armada XP SoCs ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * PCIe unit register offsets. ++ */ ++#define PCIE_DEV_ID_OFF 0x0000 ++#define PCIE_CMD_OFF 0x0004 ++#define PCIE_DEV_REV_OFF 0x0008 ++#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) ++#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) ++#define PCIE_HEADER_LOG_4_OFF 0x0128 ++#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) ++#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) ++#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) ++#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) ++#define PCIE_WIN5_CTRL_OFF 0x1880 ++#define PCIE_WIN5_BASE_OFF 0x1884 ++#define PCIE_WIN5_REMAP_OFF 0x188c ++#define PCIE_CONF_ADDR_OFF 0x18f8 ++#define PCIE_CONF_ADDR_EN 0x80000000 ++#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) ++#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) ++#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) ++#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) ++#define PCIE_CONF_ADDR(bus, devfn, where) \ ++ (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ ++ PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ ++ PCIE_CONF_ADDR_EN) ++#define PCIE_CONF_DATA_OFF 0x18fc ++#define PCIE_MASK_OFF 0x1910 ++#define PCIE_MASK_ENABLE_INTS 0x0f000000 ++#define PCIE_CTRL_OFF 0x1a00 ++#define PCIE_CTRL_X1_MODE 0x0001 ++#define PCIE_STAT_OFF 0x1a04 ++#define PCIE_STAT_BUS 0xff00 ++#define PCIE_STAT_LINK_DOWN BIT(0) ++#define PCIE_DEBUG_CTRL 0x1a60 ++#define PCIE_DEBUG_SOFT_RESET BIT(20) ++ ++/* ++ * This product ID is registered by Marvell, and used when the Marvell ++ * SoC is not the root complex, but an endpoint on the PCIe bus. It is ++ * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI ++ * bridge. ++ */ ++#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846 ++ ++/* PCI configuration space of a PCI-to-PCI bridge */ ++struct mvebu_sw_pci_bridge { ++ u16 vendor; ++ u16 device; ++ u16 command; ++ u16 status; ++ u16 class; ++ u8 interface; ++ u8 revision; ++ u8 bist; ++ u8 header_type; ++ u8 latency_timer; ++ u8 cache_line_size; ++ u32 bar[2]; ++ u8 primary_bus; ++ u8 secondary_bus; ++ u8 subordinate_bus; ++ u8 secondary_latency_timer; ++ u8 iobase; ++ u8 iolimit; ++ u16 secondary_status; ++ u16 membase; ++ u16 memlimit; ++ u16 prefmembase; ++ u16 prefmemlimit; ++ u32 prefbaseupper; ++ u32 preflimitupper; ++ u16 iobaseupper; ++ u16 iolimitupper; ++ u8 cappointer; ++ u8 reserved1; ++ u16 reserved2; ++ u32 romaddr; ++ u8 intline; ++ u8 intpin; ++ u16 bridgectrl; ++}; ++ ++struct mvebu_pcie_port; ++ ++/* Structure representing all PCIe interfaces */ ++struct mvebu_pcie { ++ struct platform_device *pdev; ++ struct mvebu_pcie_port *ports; ++ struct resource io; ++ struct resource realio; ++ struct resource mem; ++ struct resource busn; ++ int nports; ++}; ++ ++/* Structure representing one PCIe interface */ ++struct mvebu_pcie_port { ++ char *name; ++ void __iomem *base; ++ spinlock_t conf_lock; ++ int haslink; ++ u32 port; ++ u32 lane; ++ int devfn; ++ struct clk *clk; ++ struct mvebu_sw_pci_bridge bridge; ++ struct device_node *dn; ++ struct mvebu_pcie *pcie; ++ phys_addr_t memwin_base; ++ size_t memwin_size; ++ phys_addr_t iowin_base; ++ size_t iowin_size; ++}; ++ ++static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) ++{ ++ return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); ++} ++ ++static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) ++{ ++ u32 stat; ++ ++ stat = readl(port->base + PCIE_STAT_OFF); ++ stat &= ~PCIE_STAT_BUS; ++ stat |= nr << 8; ++ writel(stat, port->base + PCIE_STAT_OFF); ++} ++ ++/* ++ * Setup PCIE BARs and Address Decode Wins: ++ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks ++ * WIN[0-3] -> DRAM bank[0-3] ++ */ ++static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) ++{ ++ const struct mbus_dram_target_info *dram; ++ u32 size; ++ int i; ++ ++ dram = mv_mbus_dram_info(); ++ ++ /* First, disable and clear BARs and windows. */ ++ for (i = 1; i < 3; i++) { ++ writel(0, port->base + PCIE_BAR_CTRL_OFF(i)); ++ writel(0, port->base + PCIE_BAR_LO_OFF(i)); ++ writel(0, port->base + PCIE_BAR_HI_OFF(i)); ++ } ++ ++ for (i = 0; i < 5; i++) { ++ writel(0, port->base + PCIE_WIN04_CTRL_OFF(i)); ++ writel(0, port->base + PCIE_WIN04_BASE_OFF(i)); ++ writel(0, port->base + PCIE_WIN04_REMAP_OFF(i)); ++ } ++ ++ writel(0, port->base + PCIE_WIN5_CTRL_OFF); ++ writel(0, port->base + PCIE_WIN5_BASE_OFF); ++ writel(0, port->base + PCIE_WIN5_REMAP_OFF); ++ ++ /* Setup windows for DDR banks. Count total DDR size on the fly. */ ++ size = 0; ++ for (i = 0; i < dram->num_cs; i++) { ++ const struct mbus_dram_window *cs = dram->cs + i; ++ ++ writel(cs->base & 0xffff0000, ++ port->base + PCIE_WIN04_BASE_OFF(i)); ++ writel(0, port->base + PCIE_WIN04_REMAP_OFF(i)); ++ writel(((cs->size - 1) & 0xffff0000) | ++ (cs->mbus_attr << 8) | ++ (dram->mbus_dram_target_id << 4) | 1, ++ port->base + PCIE_WIN04_CTRL_OFF(i)); ++ ++ size += cs->size; ++ } ++ ++ /* Round up 'size' to the nearest power of two. */ ++ if ((size & (size - 1)) != 0) ++ size = 1 << fls(size); ++ ++ /* Setup BAR[1] to all DRAM banks. */ ++ writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1)); ++ writel(0, port->base + PCIE_BAR_HI_OFF(1)); ++ writel(((size - 1) & 0xffff0000) | 1, ++ port->base + PCIE_BAR_CTRL_OFF(1)); ++} ++ ++static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) ++{ ++ u16 cmd; ++ u32 mask; ++ ++ /* Point PCIe unit MBUS decode windows to DRAM space. */ ++ mvebu_pcie_setup_wins(port); ++ ++ /* Master + slave enable. */ ++ cmd = readw(port->base + PCIE_CMD_OFF); ++ cmd |= PCI_COMMAND_IO; ++ cmd |= PCI_COMMAND_MEMORY; ++ cmd |= PCI_COMMAND_MASTER; ++ writew(cmd, port->base + PCIE_CMD_OFF); ++ ++ /* Enable interrupt lines A-D. */ ++ mask = readl(port->base + PCIE_MASK_OFF); ++ mask |= PCIE_MASK_ENABLE_INTS; ++ writel(mask, port->base + PCIE_MASK_OFF); ++} ++ ++static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port, ++ struct pci_bus *bus, ++ u32 devfn, int where, int size, u32 *val) ++{ ++ writel(PCIE_CONF_ADDR(bus->number, devfn, where), ++ port->base + PCIE_CONF_ADDR_OFF); ++ ++ *val = readl(port->base + PCIE_CONF_DATA_OFF); ++ ++ if (size == 1) ++ *val = (*val >> (8 * (where & 3))) & 0xff; ++ else if (size == 2) ++ *val = (*val >> (8 * (where & 3))) & 0xffff; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port, ++ struct pci_bus *bus, ++ u32 devfn, int where, int size, u32 val) ++{ ++ int ret = PCIBIOS_SUCCESSFUL; ++ ++ writel(PCIE_CONF_ADDR(bus->number, devfn, where), ++ port->base + PCIE_CONF_ADDR_OFF); ++ ++ if (size == 4) ++ writel(val, port->base + PCIE_CONF_DATA_OFF); ++ else if (size == 2) ++ writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3)); ++ else if (size == 1) ++ writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3)); ++ else ++ ret = PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ return ret; ++} ++ ++static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) ++{ ++ phys_addr_t iobase; ++ ++ /* Are the new iobase/iolimit values invalid? */ ++ if (port->bridge.iolimit < port->bridge.iobase || ++ port->bridge.iolimitupper < port->bridge.iobaseupper) { ++ ++ /* If a window was configured, remove it */ ++ if (port->iowin_base) { ++ mvebu_mbus_del_window(port->iowin_base, ++ port->iowin_size); ++ port->iowin_base = 0; ++ port->iowin_size = 0; ++ } ++ ++ return; ++ } ++ ++ /* ++ * We read the PCI-to-PCI bridge emulated registers, and ++ * calculate the base address and size of the address decoding ++ * window to setup, according to the PCI-to-PCI bridge ++ * specifications. iobase is the bus address, port->iowin_base ++ * is the CPU address. ++ */ ++ iobase = ((port->bridge.iobase & 0xF0) << 8) | ++ (port->bridge.iobaseupper << 16); ++ port->iowin_base = port->pcie->io.start + iobase; ++ port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) | ++ (port->bridge.iolimitupper << 16)) - ++ iobase); ++ ++ mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base, ++ port->iowin_size, ++ iobase, ++ MVEBU_MBUS_PCI_IO); ++ ++ pci_ioremap_io(iobase, port->iowin_base); ++} ++ ++static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) ++{ ++ /* Are the new membase/memlimit values invalid? */ ++ if (port->bridge.memlimit < port->bridge.membase) { ++ ++ /* If a window was configured, remove it */ ++ if (port->memwin_base) { ++ mvebu_mbus_del_window(port->memwin_base, ++ port->memwin_size); ++ port->memwin_base = 0; ++ port->memwin_size = 0; ++ } ++ ++ return; ++ } ++ ++ /* ++ * We read the PCI-to-PCI bridge emulated registers, and ++ * calculate the base address and size of the address decoding ++ * window to setup, according to the PCI-to-PCI bridge ++ * specifications. ++ */ ++ port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16); ++ port->memwin_size = ++ (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) - ++ port->memwin_base; ++ ++ mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base, ++ port->memwin_size, ++ MVEBU_MBUS_NO_REMAP, ++ MVEBU_MBUS_PCI_MEM); ++} ++ ++/* ++ * Initialize the configuration space of the PCI-to-PCI bridge ++ * associated with the given PCIe interface. ++ */ ++static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port) ++{ ++ struct mvebu_sw_pci_bridge *bridge = &port->bridge; ++ ++ memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge)); ++ ++ bridge->status = PCI_STATUS_CAP_LIST; ++ bridge->class = PCI_CLASS_BRIDGE_PCI; ++ bridge->vendor = PCI_VENDOR_ID_MARVELL; ++ bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID; ++ bridge->header_type = PCI_HEADER_TYPE_BRIDGE; ++ bridge->cache_line_size = 0x10; ++ ++ /* We support 32 bits I/O addressing */ ++ bridge->iobase = PCI_IO_RANGE_TYPE_32; ++ bridge->iolimit = PCI_IO_RANGE_TYPE_32; ++} ++ ++/* ++ * Read the configuration space of the PCI-to-PCI bridge associated to ++ * the given PCIe interface. ++ */ ++static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port, ++ unsigned int where, int size, u32 *value) ++{ ++ struct mvebu_sw_pci_bridge *bridge = &port->bridge; ++ ++ switch (where & ~3) { ++ case PCI_VENDOR_ID: ++ *value = bridge->device << 16 | bridge->vendor; ++ break; ++ ++ case PCI_COMMAND: ++ *value = bridge->status << 16 | bridge->command; ++ break; ++ ++ case PCI_CLASS_REVISION: ++ *value = bridge->class << 16 | bridge->interface << 8 | ++ bridge->revision; ++ break; ++ ++ case PCI_CACHE_LINE_SIZE: ++ *value = bridge->bist << 24 | bridge->header_type << 16 | ++ bridge->latency_timer << 8 | bridge->cache_line_size; ++ break; ++ ++ case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: ++ *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4]; ++ break; ++ ++ case PCI_PRIMARY_BUS: ++ *value = (bridge->secondary_latency_timer << 24 | ++ bridge->subordinate_bus << 16 | ++ bridge->secondary_bus << 8 | ++ bridge->primary_bus); ++ break; ++ ++ case PCI_IO_BASE: ++ *value = (bridge->secondary_status << 16 | ++ bridge->iolimit << 8 | ++ bridge->iobase); ++ break; ++ ++ case PCI_MEMORY_BASE: ++ *value = (bridge->memlimit << 16 | bridge->membase); ++ break; ++ ++ case PCI_PREF_MEMORY_BASE: ++ *value = (bridge->prefmemlimit << 16 | bridge->prefmembase); ++ break; ++ ++ case PCI_PREF_BASE_UPPER32: ++ *value = bridge->prefbaseupper; ++ break; ++ ++ case PCI_PREF_LIMIT_UPPER32: ++ *value = bridge->preflimitupper; ++ break; ++ ++ case PCI_IO_BASE_UPPER16: ++ *value = (bridge->iolimitupper << 16 | bridge->iobaseupper); ++ break; ++ ++ case PCI_ROM_ADDRESS1: ++ *value = 0; ++ break; ++ ++ default: ++ *value = 0xffffffff; ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ } ++ ++ if (size == 2) ++ *value = (*value >> (8 * (where & 3))) & 0xffff; ++ else if (size == 1) ++ *value = (*value >> (8 * (where & 3))) & 0xff; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++/* Write to the PCI-to-PCI bridge configuration space */ ++static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port, ++ unsigned int where, int size, u32 value) ++{ ++ struct mvebu_sw_pci_bridge *bridge = &port->bridge; ++ u32 mask, reg; ++ int err; ++ ++ if (size == 4) ++ mask = 0x0; ++ else if (size == 2) ++ mask = ~(0xffff << ((where & 3) * 8)); ++ else if (size == 1) ++ mask = ~(0xff << ((where & 3) * 8)); ++ else ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®); ++ if (err) ++ return err; ++ ++ value = (reg & mask) | value << ((where & 3) * 8); ++ ++ switch (where & ~3) { ++ case PCI_COMMAND: ++ bridge->command = value & 0xffff; ++ bridge->status = value >> 16; ++ break; ++ ++ case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1: ++ bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value; ++ break; ++ ++ case PCI_IO_BASE: ++ /* ++ * We also keep bit 1 set, it is a read-only bit that ++ * indicates we support 32 bits addressing for the ++ * I/O ++ */ ++ bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32; ++ bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32; ++ bridge->secondary_status = value >> 16; ++ mvebu_pcie_handle_iobase_change(port); ++ break; ++ ++ case PCI_MEMORY_BASE: ++ bridge->membase = value & 0xffff; ++ bridge->memlimit = value >> 16; ++ mvebu_pcie_handle_membase_change(port); ++ break; ++ ++ case PCI_PREF_MEMORY_BASE: ++ bridge->prefmembase = value & 0xffff; ++ bridge->prefmemlimit = value >> 16; ++ break; ++ ++ case PCI_PREF_BASE_UPPER32: ++ bridge->prefbaseupper = value; ++ break; ++ ++ case PCI_PREF_LIMIT_UPPER32: ++ bridge->preflimitupper = value; ++ break; ++ ++ case PCI_IO_BASE_UPPER16: ++ bridge->iobaseupper = value & 0xffff; ++ bridge->iolimitupper = value >> 16; ++ mvebu_pcie_handle_iobase_change(port); ++ break; ++ ++ case PCI_PRIMARY_BUS: ++ bridge->primary_bus = value & 0xff; ++ bridge->secondary_bus = (value >> 8) & 0xff; ++ bridge->subordinate_bus = (value >> 16) & 0xff; ++ bridge->secondary_latency_timer = (value >> 24) & 0xff; ++ mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus); ++ break; ++ ++ default: ++ break; ++ } ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) ++{ ++ return sys->private_data; ++} ++ ++static struct mvebu_pcie_port * ++mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus, ++ int devfn) ++{ ++ int i; ++ ++ for (i = 0; i < pcie->nports; i++) { ++ struct mvebu_pcie_port *port = &pcie->ports[i]; ++ if (bus->number == 0 && port->devfn == devfn) ++ return port; ++ if (bus->number != 0 && ++ port->bridge.secondary_bus == bus->number) ++ return port; ++ } ++ ++ return NULL; ++} ++ ++/* PCI configuration space write function */ ++static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, ++ int where, int size, u32 val) ++{ ++ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); ++ struct mvebu_pcie_port *port; ++ unsigned long flags; ++ int ret; ++ ++ port = mvebu_pcie_find_port(pcie, bus, devfn); ++ if (!port) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ /* Access the emulated PCI-to-PCI bridge */ ++ if (bus->number == 0) ++ return mvebu_sw_pci_bridge_write(port, where, size, val); ++ ++ if (!port->haslink || PCI_SLOT(devfn) != 0) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ /* Access the real PCIe interface */ ++ spin_lock_irqsave(&port->conf_lock, flags); ++ ret = mvebu_pcie_hw_wr_conf(port, bus, ++ PCI_DEVFN(1, PCI_FUNC(devfn)), ++ where, size, val); ++ spin_unlock_irqrestore(&port->conf_lock, flags); ++ ++ return ret; ++} ++ ++/* PCI configuration space read function */ ++static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, ++ int size, u32 *val) ++{ ++ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata); ++ struct mvebu_pcie_port *port; ++ unsigned long flags; ++ int ret; ++ ++ port = mvebu_pcie_find_port(pcie, bus, devfn); ++ if (!port) { ++ *val = 0xffffffff; ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } ++ ++ /* Access the emulated PCI-to-PCI bridge */ ++ if (bus->number == 0) ++ return mvebu_sw_pci_bridge_read(port, where, size, val); ++ ++ if (!port->haslink || PCI_SLOT(devfn) != 0) { ++ *val = 0xffffffff; ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } ++ ++ /* Access the real PCIe interface */ ++ spin_lock_irqsave(&port->conf_lock, flags); ++ ret = mvebu_pcie_hw_rd_conf(port, bus, ++ PCI_DEVFN(1, PCI_FUNC(devfn)), ++ where, size, val); ++ spin_unlock_irqrestore(&port->conf_lock, flags); ++ ++ return ret; ++} ++ ++static struct pci_ops mvebu_pcie_ops = { ++ .read = mvebu_pcie_rd_conf, ++ .write = mvebu_pcie_wr_conf, ++}; ++ ++static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys) ++{ ++ struct mvebu_pcie *pcie = sys_to_pcie(sys); ++ int i; ++ ++ pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset); ++ pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset); ++ pci_add_resource(&sys->resources, &pcie->busn); ++ ++ for (i = 0; i < pcie->nports; i++) { ++ struct mvebu_pcie_port *port = &pcie->ports[i]; ++ mvebu_pcie_setup_hw(port); ++ } ++ ++ return 1; ++} ++ ++static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ struct of_irq oirq; ++ int ret; ++ ++ ret = of_irq_map_pci(dev, &oirq); ++ if (ret) ++ return ret; ++ ++ return irq_create_of_mapping(oirq.controller, oirq.specifier, ++ oirq.size); ++} ++ ++static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys) ++{ ++ struct mvebu_pcie *pcie = sys_to_pcie(sys); ++ struct pci_bus *bus; ++ ++ bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr, ++ &mvebu_pcie_ops, sys, &sys->resources); ++ if (!bus) ++ return NULL; ++ ++ pci_scan_child_bus(bus); ++ ++ return bus; ++} ++ ++resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, ++ const struct resource *res, ++ resource_size_t start, ++ resource_size_t size, ++ resource_size_t align) ++{ ++ if (dev->bus->number != 0) ++ return start; ++ ++ /* ++ * On the PCI-to-PCI bridge side, the I/O windows must have at ++ * least a 64 KB size and be aligned on their size, and the ++ * memory windows must have at least a 1 MB size and be ++ * aligned on their size ++ */ ++ if (res->flags & IORESOURCE_IO) ++ return round_up(start, max((resource_size_t)SZ_64K, size)); ++ else if (res->flags & IORESOURCE_MEM) ++ return round_up(start, max((resource_size_t)SZ_1M, size)); ++ else ++ return start; ++} ++ ++static void mvebu_pcie_enable(struct mvebu_pcie *pcie) ++{ ++ struct hw_pci hw; ++ ++ memset(&hw, 0, sizeof(hw)); ++ ++ hw.nr_controllers = 1; ++ hw.private_data = (void **)&pcie; ++ hw.setup = mvebu_pcie_setup; ++ hw.scan = mvebu_pcie_scan_bus; ++ hw.map_irq = mvebu_pcie_map_irq; ++ hw.ops = &mvebu_pcie_ops; ++ hw.align_resource = mvebu_pcie_align_resource; ++ ++ pci_common_init(&hw); ++} ++ ++/* ++ * Looks up the list of register addresses encoded into the reg = ++ * <...> property for one that matches the given port/lane. Once ++ * found, maps it. ++ */ ++static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, ++ struct device_node *np, ++ struct mvebu_pcie_port *port) ++{ ++ struct resource regs; ++ int ret = 0; ++ ++ ret = of_address_to_resource(np, 0, ®s); ++ if (ret) ++ return NULL; ++ ++ return devm_request_and_ioremap(&pdev->dev, ®s); ++} ++ ++static int __init mvebu_pcie_probe(struct platform_device *pdev) ++{ ++ struct mvebu_pcie *pcie; ++ struct device_node *np = pdev->dev.of_node; ++ struct of_pci_range range; ++ struct of_pci_range_parser parser; ++ struct device_node *child; ++ int i, ret; ++ ++ pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie), ++ GFP_KERNEL); ++ if (!pcie) ++ return -ENOMEM; ++ ++ pcie->pdev = pdev; ++ ++ if (of_pci_range_parser_init(&parser, np)) ++ return -EINVAL; ++ ++ /* Get the I/O and memory ranges from DT */ ++ for_each_of_pci_range(&parser, &range) { ++ unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; ++ if (restype == IORESOURCE_IO) { ++ of_pci_range_to_resource(&range, np, &pcie->io); ++ of_pci_range_to_resource(&range, np, &pcie->realio); ++ pcie->io.name = "I/O"; ++ pcie->realio.start = max_t(resource_size_t, ++ PCIBIOS_MIN_IO, ++ range.pci_addr); ++ pcie->realio.end = min_t(resource_size_t, ++ IO_SPACE_LIMIT, ++ range.pci_addr + range.size); ++ } ++ if (restype == IORESOURCE_MEM) { ++ of_pci_range_to_resource(&range, np, &pcie->mem); ++ pcie->mem.name = "MEM"; ++ } ++ } ++ ++ /* Get the bus range */ ++ ret = of_pci_parse_bus_range(np, &pcie->busn); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to parse bus-range property: %d\n", ++ ret); ++ return ret; ++ } ++ ++ for_each_child_of_node(pdev->dev.of_node, child) { ++ if (!of_device_is_available(child)) ++ continue; ++ pcie->nports++; ++ } ++ ++ pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports * ++ sizeof(struct mvebu_pcie_port), ++ GFP_KERNEL); ++ if (!pcie->ports) ++ return -ENOMEM; ++ ++ i = 0; ++ for_each_child_of_node(pdev->dev.of_node, child) { ++ struct mvebu_pcie_port *port = &pcie->ports[i]; ++ ++ if (!of_device_is_available(child)) ++ continue; ++ ++ port->pcie = pcie; ++ ++ if (of_property_read_u32(child, "marvell,pcie-port", ++ &port->port)) { ++ dev_warn(&pdev->dev, ++ "ignoring PCIe DT node, missing pcie-port property\n"); ++ continue; ++ } ++ ++ if (of_property_read_u32(child, "marvell,pcie-lane", ++ &port->lane)) ++ port->lane = 0; ++ ++ port->name = kasprintf(GFP_KERNEL, "pcie%d.%d", ++ port->port, port->lane); ++ ++ port->devfn = of_pci_get_devfn(child); ++ if (port->devfn < 0) ++ continue; ++ ++ port->base = mvebu_pcie_map_registers(pdev, child, port); ++ if (!port->base) { ++ dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n", ++ port->port, port->lane); ++ continue; ++ } ++ ++ if (mvebu_pcie_link_up(port)) { ++ port->haslink = 1; ++ dev_info(&pdev->dev, "PCIe%d.%d: link up\n", ++ port->port, port->lane); ++ } else { ++ port->haslink = 0; ++ dev_info(&pdev->dev, "PCIe%d.%d: link down\n", ++ port->port, port->lane); ++ } ++ ++ port->clk = of_clk_get_by_name(child, NULL); ++ if (!port->clk) { ++ dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n", ++ port->port, port->lane); ++ iounmap(port->base); ++ port->haslink = 0; ++ continue; ++ } ++ ++ port->dn = child; ++ ++ clk_prepare_enable(port->clk); ++ spin_lock_init(&port->conf_lock); ++ ++ mvebu_sw_pci_bridge_init(port); ++ ++ i++; ++ } ++ ++ mvebu_pcie_enable(pcie); ++ ++ return 0; ++} ++ ++static const struct of_device_id mvebu_pcie_of_match_table[] = { ++ { .compatible = "marvell,armada-xp-pcie", }, ++ { .compatible = "marvell,armada-370-pcie", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); ++ ++static struct platform_driver mvebu_pcie_driver = { ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "mvebu-pcie", ++ .of_match_table = ++ of_match_ptr(mvebu_pcie_of_match_table), ++ }, ++}; ++ ++static int mvebu_pcie_init(void) ++{ ++ return platform_driver_probe(&mvebu_pcie_driver, ++ mvebu_pcie_probe); ++} ++ ++subsys_initcall(mvebu_pcie_init); ++ ++MODULE_AUTHOR("Thomas Petazzoni "); ++MODULE_DESCRIPTION("Marvell EBU PCIe driver"); ++MODULE_LICENSE("GPLv2"); +-- +1.8.4.rc1 + diff --git a/target/linux/kirkwood/patches-3.10/0007-arm-mvebu-PCIe-support-is-now-available-on-mvebu.patch b/target/linux/kirkwood/patches-3.10/0007-arm-mvebu-PCIe-support-is-now-available-on-mvebu.patch new file mode 100644 index 0000000000..9467b2fefa --- /dev/null +++ b/target/linux/kirkwood/patches-3.10/0007-arm-mvebu-PCIe-support-is-now-available-on-mvebu.patch @@ -0,0 +1,30 @@ +From d8bb1510b06f29bb6b63ebafe23656faae60d87f Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Fri, 7 Dec 2012 20:56:52 +0100 +Subject: [PATCH 07/29] arm: mvebu: PCIe support is now available on mvebu + +Now that the PCIe driver for mvebu has been integrated and all its +relevant dependencies, we can mark the ARCH_MVEBU platform has +MIGHT_HAVE_PCI, which allows to select the PCI bus support if needed. + +Signed-off-by: Thomas Petazzoni +--- + arch/arm/mach-mvebu/Kconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig +index 80a8bca..fb827ac 100644 +--- a/arch/arm/mach-mvebu/Kconfig ++++ b/arch/arm/mach-mvebu/Kconfig +@@ -16,6 +16,8 @@ config ARCH_MVEBU + select MVEBU_MBUS + select ZONE_DMA if ARM_LPAE + select ARCH_REQUIRE_GPIOLIB ++ select MIGHT_HAVE_PCI ++ select PCI_QUIRKS if PCI + + if ARCH_MVEBU + +-- +1.8.4.rc1 + diff --git a/target/linux/kirkwood/patches-3.10/0008-arm-mvebu-update-defconfig-with-PCI-and-USB-support.patch b/target/linux/kirkwood/patches-3.10/0008-arm-mvebu-update-defconfig-with-PCI-and-USB-support.patch new file mode 100644 index 0000000000..e4a3e9da8a --- /dev/null +++ b/target/linux/kirkwood/patches-3.10/0008-arm-mvebu-update-defconfig-with-PCI-and-USB-support.patch @@ -0,0 +1,41 @@ +From 3339170f8adf10c32ad8ba4069f94f1bcd40f46d Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Fri, 7 Dec 2012 22:49:57 +0100 +Subject: [PATCH 08/29] arm: mvebu: update defconfig with PCI and USB support + +Now that we have the necessary drivers and Device Tree informations to +support PCIe on Armada 370 and Armada XP, enable the CONFIG_PCI +option. + +Also, since the Armada 370 Mirabox has a built-in USB XHCI controller +connected on the PCIe bus, enable the corresponding options as well. + +Signed-off-by: Thomas Petazzoni +--- + arch/arm/configs/mvebu_defconfig | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig +index f3e8ae0..966281e 100644 +--- a/arch/arm/configs/mvebu_defconfig ++++ b/arch/arm/configs/mvebu_defconfig +@@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y + CONFIG_MACH_ARMADA_XP=y + # CONFIG_CACHE_L2X0 is not set + # CONFIG_SWP_EMULATE is not set ++CONFIG_PCI=y ++CONFIG_PCI_MVEBU=y + CONFIG_SMP=y + CONFIG_AEABI=y + CONFIG_HIGHMEM=y +@@ -60,6 +62,7 @@ CONFIG_USB_SUPPORT=y + CONFIG_USB=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_XHCI_HCD=y + CONFIG_MMC=y + CONFIG_MMC_MVSDIO=y + CONFIG_NEW_LEDS=y +-- +1.8.4.rc1 + diff --git a/target/linux/kirkwood/patches-3.10/0009-pci-mvebu-enable-driver-usage-on-Kirkwood.patch b/target/linux/kirkwood/patches-3.10/0009-pci-mvebu-enable-driver-usage-on-Kirkwood.patch new file mode 100644 index 0000000000..c1f4b1ccbd --- /dev/null +++ b/target/linux/kirkwood/patches-3.10/0009-pci-mvebu-enable-driver-usage-on-Kirkwood.patch @@ -0,0 +1,56 @@ +From 3b93e75d1b66353b8f8ad7d965e17aad68982c55 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Wed, 27 Mar 2013 18:48:13 +0100 +Subject: [PATCH 09/29] pci: mvebu: enable driver usage on Kirkwood + +We allow the pci-mvebu driver to be compiled on the Kirkwood platform, +and add the 'marvell,kirkwood-pcie' as a compatible string supported +by the driver. + +Signed-off-by: Thomas Petazzoni +Tested-by: Andrew Lunn +--- + Documentation/devicetree/bindings/pci/mvebu-pci.txt | 1 + + drivers/pci/host/Kconfig | 2 +- + drivers/pci/host/pci-mvebu.c | 1 + + 3 files changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt +index eb69d92..f8d4058 100644 +--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt ++++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt +@@ -4,6 +4,7 @@ Mandatory properties: + - compatible: one of the following values: + marvell,armada-370-pcie + marvell,armada-xp-pcie ++ marvell,kirkwood-pcie + - #address-cells, set to <3> + - #size-cells, set to <2> + - #interrupt-cells, set to <1> +diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig +index 6918fbc..1f1d67f 100644 +--- a/drivers/pci/host/Kconfig ++++ b/drivers/pci/host/Kconfig +@@ -3,6 +3,6 @@ menu "PCI host controller drivers" + + config PCI_MVEBU + bool "Marvell EBU PCIe controller" +- depends on ARCH_MVEBU ++ depends on ARCH_MVEBU || ARCH_KIRKWOOD + + endmenu +diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c +index b0ee63b..6fe8b90 100644 +--- a/drivers/pci/host/pci-mvebu.c ++++ b/drivers/pci/host/pci-mvebu.c +@@ -853,6 +853,7 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev) + static const struct of_device_id mvebu_pcie_of_match_table[] = { + { .compatible = "marvell,armada-xp-pcie", }, + { .compatible = "marvell,armada-370-pcie", }, ++ { .compatible = "marvell,kirkwood-pcie", }, + {}, + }; + MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); +-- +1.8.4.rc1 + diff --git a/target/linux/kirkwood/patches-3.10/0010-arm-kirkwood-move-PCIe-window-init-to-legacy-driver.patch b/target/linux/kirkwood/patches-3.10/0010-arm-kirkwood-move-PCIe-window-init-to-legacy-driver.patch new file mode 100644 index 0000000000..096ee6f847 --- /dev/null +++ b/target/linux/kirkwood/patches-3.10/0010-arm-kirkwood-move-PCIe-window-init-to-legacy-driver.patch @@ -0,0 +1,102 @@ +From 080dc44291ff143d84b63e5ff9fda963d46a7dce Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Wed, 27 Mar 2013 18:51:25 +0100 +Subject: [PATCH 10/29] arm: kirkwood: move PCIe window init to legacy driver + +Since we are going to enable the usage of the mvebu PCIe driver on +Kirkwood, we don't want the PCIe windows to be unconditionally created +by kirkwood_setup_wins(). Therefore, we move the PCIe window +initialization into the legacy PCIe driver +(arch/arm/mach-kirkwood/pcie.c). + +The platforms using the legacy driver will see their windows +statically allocated by +arch/arm/mach-kirkwood/pcie.c:kirkwood_pcie_init(). The platforms +using the new driver in drivers/pci/ will see their windows +dynamically allocated directly by the driver. + +Signed-off-by: Thomas Petazzoni +Tested-by: Andrew Lunn +--- + arch/arm/mach-kirkwood/common.c | 24 ------------------------ + arch/arm/mach-kirkwood/pcie.c | 22 ++++++++++++++++++++++ + 2 files changed, 22 insertions(+), 24 deletions(-) + +diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c +index f389228..41ea98d 100644 +--- a/arch/arm/mach-kirkwood/common.c ++++ b/arch/arm/mach-kirkwood/common.c +@@ -648,30 +648,6 @@ char * __init kirkwood_id(void) + + void __init kirkwood_setup_wins(void) + { +- /* +- * The PCIe windows will no longer be statically allocated +- * here once Kirkwood is migrated to the pci-mvebu driver. +- */ +- mvebu_mbus_add_window_remap_flags("pcie0.0", +- KIRKWOOD_PCIE_IO_PHYS_BASE, +- KIRKWOOD_PCIE_IO_SIZE, +- KIRKWOOD_PCIE_IO_BUS_BASE, +- MVEBU_MBUS_PCI_IO); +- mvebu_mbus_add_window_remap_flags("pcie0.0", +- KIRKWOOD_PCIE_MEM_PHYS_BASE, +- KIRKWOOD_PCIE_MEM_SIZE, +- MVEBU_MBUS_NO_REMAP, +- MVEBU_MBUS_PCI_MEM); +- mvebu_mbus_add_window_remap_flags("pcie1.0", +- KIRKWOOD_PCIE1_IO_PHYS_BASE, +- KIRKWOOD_PCIE1_IO_SIZE, +- KIRKWOOD_PCIE1_IO_BUS_BASE, +- MVEBU_MBUS_PCI_IO); +- mvebu_mbus_add_window_remap_flags("pcie1.0", +- KIRKWOOD_PCIE1_MEM_PHYS_BASE, +- KIRKWOOD_PCIE1_MEM_SIZE, +- MVEBU_MBUS_NO_REMAP, +- MVEBU_MBUS_PCI_MEM); + mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, + KIRKWOOD_NAND_MEM_SIZE); + mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, +diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c +index 7f43e6c..ddcb09f 100644 +--- a/arch/arm/mach-kirkwood/pcie.c ++++ b/arch/arm/mach-kirkwood/pcie.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include