From: David Decotigny Date: Mon, 8 Jun 2015 00:43:02 +0000 (-0700) Subject: staging: rtl8723au: core: remove redundant endianness conversion X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=02632342d4831dc3d197a45f83de291e2d3980cc;p=openwrt%2Fstaging%2Fblogic.git staging: rtl8723au: core: remove redundant endianness conversion Source and destination have the same little-endian annotation: this patch removes incorrect byte-swap on non-LE cpus. This addresses the following sparse warning: drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56: warning: incorrect type in argument 1 (different base types) drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56: expected unsigned short [unsigned] [usertype] val drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56: got restricted __le16 [usertype] BA_timeout_value Signed-off-by: David Decotigny Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/staging/rtl8723au/core/rtw_mlme_ext.c b/drivers/staging/rtl8723au/core/rtw_mlme_ext.c index 7c3b5dd177d2..142f214108c6 100644 --- a/drivers/staging/rtl8723au/core/rtw_mlme_ext.c +++ b/drivers/staging/rtl8723au/core/rtw_mlme_ext.c @@ -3906,8 +3906,8 @@ void issue_action_BA23a(struct rtw_adapter *padapter, put_unaligned_le16(BA_para_set, &mgmt->u.action.u.addba_resp.capab); - put_unaligned_le16(pmlmeinfo->ADDBA_req.BA_timeout_value, - &mgmt->u.action.u.addba_resp.timeout); + mgmt->u.action.u.addba_resp.timeout + = pmlmeinfo->ADDBA_req.BA_timeout_value; pattrib->pktlen += 8; break;