From: Anshuman Gupta Date: Sun, 11 Aug 2019 10:02:32 +0000 (+0530) Subject: drm/i915/tgl: Fixing up list of PG3 power domains. X-Git-Url: http://git.lede-project.org./?a=commitdiff_plain;h=015341da9888b58fbdeafd369c43f7a95fe4e763;p=openwrt%2Fstaging%2Fblogic.git drm/i915/tgl: Fixing up list of PG3 power domains. The DDI-IO power wells (PWR_WELL_CTL_DDI) are backing the IO/PHY functionality, which doesn't need the PG3 power power well. Accordingly fixing up the list of PG3 power domains. Cc: Imre Deak Cc: Ville Syrjälä Signed-off-by: Anshuman Gupta Signed-off-by: Imre Deak Reviewed-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20190811100232.27964-1-anshuman.gupta@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 99ed4b4d7c3c..374b75602141 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -2570,17 +2570,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) | \ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) | \ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) | \ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) | \ BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) | \ - BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) | \ BIT_ULL(POWER_DOMAIN_AUX_TC1) | \ BIT_ULL(POWER_DOMAIN_AUX_TC2) | \ BIT_ULL(POWER_DOMAIN_AUX_TC3) | \