ramips: DTS modifications
authorStanislav Galabov <sgalabov@gmail.com>
Tue, 10 May 2016 13:23:54 +0000 (16:23 +0300)
committerJohn Crispin <john@phrozen.org>
Thu, 12 May 2016 01:29:36 +0000 (03:29 +0200)
This commit makes the following modifications to ramips dts files:
1. Add clkctrl node to all dtsi files (although not used for now)
2. Add clocks and clock-names properties to some nodes (usbphy, pci)
3. Add usbphy node for rt3050 (although not used for now)
4. Add clock-frequency to uart nodes in mt7621.dtsi and mt7628an.dtsi

These modifications, although not fully used at the moment, will make
it easier for FreeBSD to adopt and use LEDE ramips dts files with
minimal changes for easier maintenance.

Signed-off-by: Stanislav Galabov <sgalabov@gmail.com>
target/linux/ramips/dts/mt7620a.dtsi
target/linux/ramips/dts/mt7620n.dtsi
target/linux/ramips/dts/mt7621.dtsi
target/linux/ramips/dts/mt7628an.dtsi
target/linux/ramips/dts/rt2880.dtsi
target/linux/ramips/dts/rt3050.dtsi
target/linux/ramips/dts/rt3352.dtsi
target/linux/ramips/dts/rt3883.dtsi
target/linux/ramips/dts/rt5350.dtsi

index 352b2d1188cdb6ade235404d00f581acf03a4779..2450f7d0081823c7598b9f01d7c7eeb4f91f3c46 100644 (file)
                #reset-cells = <1>;
        };
 
+       clkctrl: clkctrl {
+               compatible = "ralink,rt2880-clock";
+               #clock-cells = <1>;
+       };
+
        usbphy: usbphy {
                compatible = "mediatek,mt7620-usbphy";
                #phy-cells = <1>;
 
                resets = <&rstctrl 22 &rstctrl 25>;
                reset-names = "host", "device";
+
+               clocks = <&clkctrl 22 &clkctrl 25>;
+               clock-names = "host", "device";
        };
 
        ethernet: ethernet@10100000 {
                resets = <&rstctrl 26>;
                reset-names = "pcie0";
 
+               clocks = <&clkctrl 26>;
+               clock-names = "pcie0";
+
                interrupt-parent = <&cpuintc>;
                interrupts = <4>;
 
index d1cf36f29abbcdb9abe46340f4339caf2ee696a3..1df9544ae7473598d605ead2637bc440ab38391a 100644 (file)
                #reset-cells = <1>;
        };
 
+       clkctrl: clkctrl {
+               compatible = "ralink,rt2880-clock";
+               #clock-cells = <1>;
+       };
+
        usbphy: usbphy {
                compatible = "mediatek,mt7620-usbphy";
                #phy-cells = <1>;
 
                resets = <&rstctrl 22 &rstctrl 25>;
                reset-names = "host", "device";
+
+               clocks = <&clkctrl 22 &clkctrl 25>;
+               clock-names = "host", "device";
        };
 
        ethernet: ethernet@10100000 {
index bc30597fdd286c600bcd2b50bf249492c412cc8e..2ce07d78af8926473db32787db39a4b93611a522 100644 (file)
                        reg = <0xc00 0x100>;
 
                        clocks = <&sysclock>;
+                       clock-frequency = <50000000>;
 
                        interrupt-parent = <&gic>;
                        interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
                #reset-cells = <1>;
        };
 
+       clkctrl: clkctrl {
+               compatible = "ralink,rt2880-clock";
+               #clock-cells = <1>;
+       };
+
        sdhci: sdhci@1E130000 {
                compatible = "ralink,mt7620-sdhci";
                reg = <0x1E130000 0x4000>;
 
                status = "okay";
 
+               resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
+               reset-names = "pcie0", "pcie1", "pcie2";
+               clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
+               clock-names = "pcie0", "pcie1", "pcie2";
+
                pcie0 {
                        reg = <0x0000 0 0 0 0>;
 
index b242e48d21ac35a58634ad8ee56a0a2f313c8048..6b8b1b73d088663f3d07f7d7e9f6915475ef578d 100644 (file)
                        reg-io-width = <4>;
                        no-loopback-test;
 
+                       clock-frequency = <40000000>;
+
                        resets = <&rstctrl 12>;
                        reset-names = "uartl";
 
                        reg-io-width = <4>;
                        no-loopback-test;
 
+                       clock-frequency = <40000000>;
+
                        resets = <&rstctrl 19>;
                        reset-names = "uart1";
 
                        reg-io-width = <4>;
                        no-loopback-test;
 
+                       clock-frequency = <40000000>;
+
                        resets = <&rstctrl 20>;
                        reset-names = "uart2";
 
                #reset-cells = <1>;
        };
 
+       clkctrl: clkctrl {
+               compatible = "ralink,rt2880-clock";
+               #clock-cells = <1>;
+       };
+
        usbphy: usbphy@10120000 {
                compatible = "ralink,mt7628an-usbphy", "mediatek,mt7620-usbphy";
                reg = <0x10120000 0x4000>;
 
                resets = <&rstctrl 22 &rstctrl 25>;
                reset-names = "host", "device";
+               clocks = <&clkctrl 22 &clkctrl 25>;
+               clock-names = "host", "device";
        };
 
        sdhci: sdhci@10130000 {
                #address-cells = <3>;
                #size-cells = <2>;
 
-               resets = <&rstctrl 26>;
-               reset-names = "pcie0";
-
                interrupt-parent = <&cpuintc>;
                interrupts = <4>;
 
+               resets = <&rstctrl 26 &rstctrl 27>;
+               reset-names = "pcie0", "pcie1";
+               clocks = <&clkctrl 26 &clkctrl 27>;
+               clock-names = "pcie0", "pcie1";
+
                status = "disabled";
 
                device_type = "pci";
index e96b800a3314a41dc68761bb6e0a46a46ac8aeb2..ad882547f794c05b30ba6192beec5f2c80c0deee 100644 (file)
                #reset-cells = <1>;
        };
 
+       clkctrl: clkctrl {
+               compatible = "ralink,rt2880-clock";
+               #clock-cells = <1>;
+       };
+
        ethernet: ethernet@400000 {
                compatible = "ralink,rt2880-eth";
                reg = <0x00400000 0x10000>;
index 1ddc1515b34038501d3ed2a5f18012bbcc0381a8..caf448bd160c3738048afec1a500cc1af4c95843 100644 (file)
                #reset-cells = <1>;
        };
 
+       clkctrl: clkctrl {
+               compatible = "ralink,rt2880-clock";
+               #clock-cells = <1>;
+       };
+
+       usbphy: usbphy {
+               compatible = "ralink,rt3050-usbphy";
+               resets = <&rstctrl 22>;
+               reset-names = "host";
+               clocks = <&clkctrl 18>;
+               clock-names = "host";
+       };
+
        ethernet: ethernet@10100000 {
                compatible = "ralink,rt3050-eth";
                reg = <0x10100000 0x10000>;
index 386ac51ffb7f9108ee53640dc4b7d679b2a782d4..a818a18d222b88bdff93b99bc95f02e982675a3f 100644 (file)
                #reset-cells = <1>;
        };
 
+       clkctrl: clkctrl {
+               compatible = "ralink,rt2880-clock";
+               #clock-cells = <1>;
+       };
+
        ethernet: ethernet@10100000 {
                compatible = "ralink,rt3352-eth", "ralink,rt3050-eth";
                reg = <0x10100000 0x10000>;
 
                resets = <&rstctrl 22 &rstctrl 25>;
                reset-names = "host", "device";
+               clocks = <&clkctrl 18 &clkctrl 20>;
+               clock-names = "host", "device";
        };
 
        wmac: wmac@10180000 {
index ba1f9a9c8aa8606816cf24b4ada0a206c7ad3348..d92cb65b7ad917f179bc73e54ab529422e7a31dd 100644 (file)
                #reset-cells = <1>;
        };
 
+       clkctrl: clkctrl {
+               compatible = "ralink,rt2880-clock";
+               #clock-cells = <1>;
+       };
+
        pci: pci@10140000 {
                compatible = "ralink,rt3883-pci";
                reg = <0x10140000 0x20000>;
 
                resets = <&rstctrl 22 &rstctrl 25>;
                reset-names = "host", "device";
+               clocks = <&clkctrl 22 &clkctrl 25>;
+               clock-names = "host", "device";
        };
 
        wmac: wmac@10180000 {
index 6f30f2df597cc647609635f1b3a1234d1f49bd87..8733d4f550e5ecf0d24b439edc96812848b0da86 100644 (file)
                #reset-cells = <1>;
        };
 
+       clkctrl: clkctrl {
+               compatible = "ralink,rt2880-clock";
+               #clock-cells = <1>;
+       };
+
        usbphy: usbphy {
                compatible = "ralink,rt3352-usbphy";
                #phy-cells = <1>;
 
                resets = <&rstctrl 22 &rstctrl 25>;
                reset-names = "host", "device";
+               clocks = <&clkctrl 18>;
+               clock-names = "host";
        };
 
        ethernet: ethernet@10100000 {