drm/radeon: add get_allowed_info_register for EG/BTC
authorAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Oct 2014 13:43:38 +0000 (09:43 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 19 Mar 2015 16:26:39 +0000 (12:26 -0400)
Registers that can be fetched from the info ioctl.

Tested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/evergreend.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_asic.h

index 973df064c14feb193a81c99109665c2186d03dc6..21cbd2e90f3b41f588f32b55029e33ba102ecb18 100644 (file)
@@ -1006,6 +1006,34 @@ static void evergreen_init_golden_registers(struct radeon_device *rdev)
        }
 }
 
+/**
+ * evergreen_get_allowed_info_register - fetch the register for the info ioctl
+ *
+ * @rdev: radeon_device pointer
+ * @reg: register offset in bytes
+ * @val: register value
+ *
+ * Returns 0 for success or -EINVAL for an invalid register
+ *
+ */
+int evergreen_get_allowed_info_register(struct radeon_device *rdev,
+                                       u32 reg, u32 *val)
+{
+       switch (reg) {
+       case GRBM_STATUS:
+       case GRBM_STATUS_SE0:
+       case GRBM_STATUS_SE1:
+       case SRBM_STATUS:
+       case SRBM_STATUS2:
+       case DMA_STATUS_REG:
+       case UVD_STATUS:
+               *val = RREG32(reg);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
                             unsigned *bankh, unsigned *mtaspect,
                             unsigned *tile_split)
index a8d1d5240fcb3088d1ea391ebcc8955c46f8c237..4aa5f755572b1593a8b6f7876cf5f7aed183715d 100644 (file)
 #define UVD_UDEC_DBW_ADDR_CONFIG                       0xef54
 #define UVD_RBC_RB_RPTR                                        0xf690
 #define UVD_RBC_RB_WPTR                                        0xf694
+#define UVD_STATUS                                     0xf6bc
 
 /*
  * PM4
index f2c343717c4b5f7acfe14edad298ac6885655ee0..0db4ee71fa698502ee24b9031ec261bcf61f3e8c 100644 (file)
@@ -1344,6 +1344,7 @@ static struct radeon_asic evergreen_asic = {
        .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
        .get_xclk = &rv770_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = evergreen_get_allowed_info_register,
        .gart = {
                .tlb_flush = &evergreen_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
@@ -1437,6 +1438,7 @@ static struct radeon_asic sumo_asic = {
        .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
        .get_xclk = &r600_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = evergreen_get_allowed_info_register,
        .gart = {
                .tlb_flush = &evergreen_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
@@ -1529,6 +1531,7 @@ static struct radeon_asic btc_asic = {
        .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
        .get_xclk = &rv770_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = evergreen_get_allowed_info_register,
        .gart = {
                .tlb_flush = &evergreen_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
index 3e1346d585b3e3641a5685c8b16840b8c29e1bf8..b632e35248b1025bfe5f058bb10c0f8a21d81f81 100644 (file)
@@ -548,6 +548,8 @@ struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
                                        unsigned num_gpu_pages,
                                        struct reservation_object *resv);
 int evergreen_get_temp(struct radeon_device *rdev);
+int evergreen_get_allowed_info_register(struct radeon_device *rdev,
+                                       u32 reg, u32 *val);
 int sumo_get_temp(struct radeon_device *rdev);
 int tn_get_temp(struct radeon_device *rdev);
 int cypress_dpm_init(struct radeon_device *rdev);