ppc4xx: Fix ndfc HW ECC byte order

The current ndfc HW ECC implementation swaps the first two ECC bytes.
But the 4xx NDFC already uses the SMC (Smart Media Card) ECC ordering,
so this swapping in the HW ECC driver is bogus. This patch fixes this
problem and now really uses the SMC ECC byte order.

Thanks to Sean MacLennan for pointing this out.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c
index ec1b38cffa35177a18959c502e9a6e348bbd0a97..9e2229daf998d388107cee21d686215f2deaacf2 100644 (file)
--- a/cpu/ppc4xx/ndfc.c
+++ b/cpu/ppc4xx/ndfc.c
@@ -121,8 +121,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
 
        /* The NDFC uses Smart Media (SMC) bytes order
         */
-       ecc_code[0] = p[2];
-       ecc_code[1] = p[1];
+       ecc_code[0] = p[1];
+       ecc_code[1] = p[2];
        ecc_code[2] = p[3];
 
        return 0;