ar71xx: reset the phy in the ethernet init on ar724x
authorFelix Fietkau <nbd@openwrt.org>
Wed, 20 Jul 2011 12:04:34 +0000 (12:04 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Wed, 20 Jul 2011 12:04:34 +0000 (12:04 +0000)
SVN-Revision: 27703

target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_main.c

index 05ce97765bc0b9fbd69f1101cc03933f5ec5b9df..088d27a346bf1be88941a8c14d96985099315a0f 100644 (file)
@@ -558,8 +558,10 @@ void __init ar71xx_add_device_eth(unsigned int id)
                break;
 
        case AR71XX_SOC_AR7242:
-               ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
-               ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
+               ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO |
+                                             RESET_MODULE_GE0_PHY;
+               ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO |
+                                             RESET_MODULE_GE1_PHY;
                pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
                                      : ar724x_ddr_flush_ge0;
                pdata->set_pll =  id ? ar724x_set_pll_ge1
@@ -580,6 +582,8 @@ void __init ar71xx_add_device_eth(unsigned int id)
                ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
                /* fall through */
        case AR71XX_SOC_AR7240:
+               ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY;
+               ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY;
                pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
                                      : ar724x_ddr_flush_ge0;
                pdata->set_pll =  id ? ar724x_set_pll_ge1
index c1143161afdc736d2603060568a2b4f1aec8e75d..ce2af538cbd2d13e40c7eb198fc7d7fb75766125 100644 (file)
@@ -433,9 +433,22 @@ static void ag71xx_hw_stop(struct ag71xx *ag)
 static void ag71xx_hw_init(struct ag71xx *ag)
 {
        struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+       u32 reset_mask = pdata->reset_bit;
 
        ag71xx_hw_stop(ag);
 
+       if (pdata->is_ar724x) {
+               u32 reset_phy = reset_mask;
+
+               reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY;
+               reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY);
+
+               ar71xx_device_stop(reset_phy);
+               mdelay(50);
+               ar71xx_device_start(reset_phy);
+               mdelay(200);
+       }
+
        ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
        udelay(20);