MIPS: JZ4740: Cleanup the mechanical irq_chip conversion

The conversion did not make use of the new chip flag which signals the
core code to mask the chip before calling the set_type callback. Sigh.
Use the new lockdep helper as well.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2183/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
index 9bb0770fa76e326772de7f05ab56d4ccaa6cd97b..bd2fc29b95e0920ed73e34d1f1de0b1ca09f236f 100644 (file)
--- a/arch/mips/jz4740/gpio.c
+++ b/arch/mips/jz4740/gpio.c
@@ -347,22 +347,14 @@ static void jz_gpio_irq_unmask(struct irq_data *data)
 /* TODO: Check if function is gpio */
 static unsigned int jz_gpio_irq_startup(struct irq_data *data)
 {
-       struct irq_desc *desc = irq_to_desc(data->irq);
-
        jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
-
-       desc->status &= ~IRQ_MASKED;
        jz_gpio_irq_unmask(data);
-
        return 0;
 }
 
 static void jz_gpio_irq_shutdown(struct irq_data *data)
 {
-       struct irq_desc *desc = irq_to_desc(data->irq);
-
        jz_gpio_irq_mask(data);
-       desc->status |= IRQ_MASKED;
 
        /* Set direction to input */
        jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
@@ -377,11 +369,8 @@ static void jz_gpio_irq_ack(struct irq_data *data)
 static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
 {
        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
-       struct irq_desc *desc = irq_to_desc(data->irq);
        unsigned int irq = data->irq;
 
-       jz_gpio_irq_mask(data);
-
        if (flow_type == IRQ_TYPE_EDGE_BOTH) {
                uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
                if (value & IRQ_TO_BIT(irq))
@@ -414,9 +403,6 @@ static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
                return -EINVAL;
        }
 
-       if (!(desc->status & IRQ_MASKED))
-               jz_gpio_irq_unmask(data);
-
        return 0;
 }
 
@@ -443,6 +429,7 @@ static struct irq_chip jz_gpio_irq_chip = {
        .irq_shutdown = jz_gpio_irq_shutdown,
        .irq_set_type = jz_gpio_irq_set_type,
        .irq_set_wake = jz_gpio_irq_set_wake,
+       .flags = IRQCHIP_SET_TYPE_MASKED,
 };
 
 /*
@@ -527,7 +514,7 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
        set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
 
        for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
-               lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
+               irq_set_lockdep_class(irq, &gpio_lock_class);
                set_irq_chip_data(irq, chip);
                set_irq_chip_and_handler(irq, &jz_gpio_irq_chip,
                        handle_level_irq);