endif
endif
-# If MBEDTLS_KEY_ALG build flag is defined use it to set TF_MBEDTLS_KEY_ALG for
-# backward compatibility
-ifdef MBEDTLS_KEY_ALG
- ifeq (${ERROR_DEPRECATED},1)
- $(error "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
- endif
- $(warning "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
- TF_MBEDTLS_KEY_ALG := ${MBEDTLS_KEY_ALG}
-endif
-
ifeq (${HASH_ALG}, sha384)
TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA384
else ifeq (${HASH_ALG}, sha512)
.fill \label + (32 * 4) - .
.endm
- /*
- * This macro verifies that the given vector doesn't exceed the
- * architectural limit of 32 instructions. This is meant to be placed
- * immediately after the last instruction in the vector. It takes the
- * vector entry as the parameter
- */
- .macro check_vector_size since
-#if ERROR_DEPRECATED
- .error "check_vector_size must not be used. Use end_vector_entry instead"
-#endif
- end_vector_entry \since
- .endm
-
/*
* This macro calculates the base address of the current CPU's MP stack
* using the plat_my_core_pos() index, the name of the stack storage
/* Prevent mbed TLS from using snprintf so that it can use tf_snprintf. */
#define MBEDTLS_PLATFORM_SNPRINTF_ALT
-#if !ERROR_DEPRECATED
-#define MBEDTLS_PKCS1_V15
-#endif
#define MBEDTLS_PKCS1_V21
#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
#define SDCR_SPD_ENABLE U(0x3)
#define SDCR_RESET_VAL U(0x0)
-#if !ERROR_DEPRECATED
-#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
-#endif
-
/* HSCTLR definitions */
#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
(U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
#define NSASEDIS_BIT (U(1) << 15)
#define NSTRCDIS_BIT (U(1) << 20)
/* NOTE: correct typo in the definitions */
-#if !ERROR_DEPRECATED
-#define NASCR_CP11_BIT (U(1) << 11)
-#define NASCR_CP10_BIT (U(1) << 10)
-#endif
#define NSACR_CP11_BIT (U(1) << 11)
#define NSACR_CP10_BIT (U(1) << 10)
#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
+++ /dev/null
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SMCC_HELPERS_H__
-#define __SMCC_HELPERS_H__
-
-#if !ERROR_DEPRECATED
-#include <smccc_helpers.h>
-#endif
-
-#endif /* __SMCC_HELPERS_H__ */
+++ /dev/null
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef __SMCC_MACROS_S__
-#define __SMCC_MACROS_S__
-
-#if !ERROR_DEPRECATED
-#include <smccc_macros.S>
-
-#define smcc_save_gp_mode_regs smccc_save_gp_mode_regs
-#endif
-
-#endif /* __SMCC_MACROS_S__ */
#define MDCR_TPM_BIT (U(1) << 6)
#define MDCR_EL3_RESET_VAL U(0x0)
-#if !ERROR_DEPRECATED
-#define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
-#endif
-
/* MDCR_EL2 definitions */
#define MDCR_EL2_TPMS (U(1) << 14)
#define MDCR_EL2_E2PB(x) ((x) << 12)
+++ /dev/null
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SMCC_HELPERS_H__
-#define __SMCC_HELPERS_H__
-
-#if !ERROR_DEPRECATED
-#include <smccc_helpers.h>
-#endif
-
-#endif /* __SMCC_HELPERS_H__ */
******************************************************************************/
#define CORTEX_A53_L2MERRSR p15, 3, c15
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A53_ACTLR CORTEX_A53_CPUACTLR
-
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT
-#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_ENDCCASCI
-#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_DTAH
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A53_H__ */
******************************************************************************/
#define CORTEX_A57_L2MERRSR p15, 3, c15
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A57_ACTLR CORTEX_A57_CPUACTLR
-
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
-#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_DIS_OVERREAD
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_DCC_AS_DCCI
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
-#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_DIS_STREAMING
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_DIS_L1_STREAMING
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A57_H__ */
******************************************************************************/
#define CORTEX_A72_L2MERRSR p15, 3, c15
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR
-
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_DCC_AS_DCCI
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A72_H__ */
******************************************************************************/
#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions
- * so as not to break platforms that continue using them.
- */
-#define CORTEX_A53_ACTLR_EL1 CORTEX_A53_CPUACTLR_EL1
-
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT
-#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
-#define CORTEX_A53_ACTLR_RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT
-#define CORTEX_A53_ACTLR_RADIS CORTEX_A53_CPUACTLR_EL1_RADIS
-#define CORTEX_A53_ACTLR_L1RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT
-#define CORTEX_A53_ACTLR_L1RADIS CORTEX_A53_CPUACTLR_EL1_L1RADIS
-#define CORTEX_A53_ACTLR_DTAH_SHIFT CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT
-#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_EL1_DTAH
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A53_H__ */
******************************************************************************/
#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A57_ACTLR_EL1 CORTEX_A57_CPUACTLR_EL1
-
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
-#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
-#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A57_H__ */
******************************************************************************/
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR_EL1
-
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A72_H__ */
+++ /dev/null
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SMCC_H__
-#define __SMCC_H__
-
-#if !ERROR_DEPRECATED
-#include <smccc.h>
-#endif
-
-#endif /* __SMCC_H__ */
* does not equal SMC_UNK. This is to ensure that the caller won't mistake the
* returned UUID in x0 for an invalid SMC error return
*/
-#if !ERROR_DEPRECATED
-#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \
- _n0, _n1, _n2, _n3, _n4, _n5) \
- CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
- static const uuid_t _name = { \
- _tl, _tm, _th, _cl, _ch, \
- { _n0, _n1, _n2, _n3, _n4, _n5 } \
- }
-#endif
-
-
#define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch, \
_n0, _n1, _n2, _n3, _n4, _n5) \
CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
#define SMC_32 U(0)
#define SMC_TYPE_FAST ULL(1)
-#if !ERROR_DEPRECATED
-#define SMC_TYPE_STD ULL(0)
-#endif
#define SMC_TYPE_YIELD ULL(0)
#define SMC_OK ULL(0)
#ifndef __UTILS_H__
#define __UTILS_H__
-#if !ERROR_DEPRECATED
-#include <utils_def.h>
-#endif
-
/*
* C code should be put in this part of the header to avoid breaking ASM files
* or linker scripts including it.
/*******************************************************************************
* Mandatory common functions
******************************************************************************/
-unsigned long long plat_get_syscnt_freq(void) __deprecated;
unsigned int plat_get_syscnt_freq2(void);
int plat_get_image_source(unsigned int image_id,
smc #0
endfunc smc
-/* -----------------------------------------------------------------------
- * void zeromem16(void *mem, unsigned int length);
- *
- * Initialise a memory region to 0.
- * The memory address must be 16-byte aligned.
- * NOTE: This function is deprecated and zeromem should be used instead.
- * -----------------------------------------------------------------------
- */
-.equ zeromem16, zeromem
-
/* -----------------------------------------------------------------------
* void zero_normalmem(void *mem, unsigned int length);
*
+++ /dev/null
-/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/spinlock.S"
-#endif
wfi
no_ret plat_panic_handler
endfunc psci_power_down_wfi
-
-/* -----------------------------------------------------------------------
- * void psci_entrypoint(void);
- * The deprecated entry point for PSCI on warm boot for AArch64.
- * -----------------------------------------------------------------------
- */
-func_deprecated psci_entrypoint
- b bl31_warm_entrypoint
-endfunc_deprecated psci_entrypoint
* platforms but may also be overridden by a platform if required.
*/
#pragma weak bl31_plat_runtime_setup
-#if !ERROR_DEPRECATED
-#pragma weak plat_get_syscnt_freq2
-#endif /* ERROR_DEPRECATED */
#if SDEI_SUPPORT
#pragma weak plat_sdei_handle_masked_trigger
return idx;
}
-#if !ERROR_DEPRECATED
-unsigned int plat_get_syscnt_freq2(void)
-{
- WARN("plat_get_syscnt_freq() is deprecated\n");
- WARN("Please define plat_get_syscnt_freq2()\n");
- /*
- * Suppress deprecated declaration warning in compatibility function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
- unsigned long long freq = plat_get_syscnt_freq();
-#pragma GCC diagnostic pop
-
- assert(freq >> 32 == 0);
-
- return (unsigned int)freq;
-}
-#endif /* ERROR_DEPRECATED */
-
#if SDEI_SUPPORT
/*
* Function that handles spurious SDEI interrupts while events are masked.
#define MPIDR_RES_BIT_MASK 0xff000000
- /* ------------------------------------------------------------------
- * int platform_get_core_pos(int mpidr)
- * Returns the CPU index of the CPU specified by mpidr. This is
- * defined when platform compatibility is disabled to enable Trusted
- * Firmware components like SPD using the old platform API to work.
- * This API is deprecated and it assumes that the mpidr specified is
- * that of a valid and present CPU. Instead, plat_my_core_pos()
- * should be used for CPU index of the current CPU and
- * plat_core_pos_by_mpidr() should be used for CPU index of a
- * CPU specified by its mpidr.
- * ------------------------------------------------------------------
- */
-func_deprecated platform_get_core_pos
- bic x0, x0, #MPIDR_RES_BIT_MASK
- mrs x1, mpidr_el1
- bic x1, x1, #MPIDR_RES_BIT_MASK
- cmp x0, x1
- beq plat_my_core_pos
- b platform_core_pos_helper
-endfunc_deprecated platform_get_core_pos
-
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform.
* --------------------------------------------------------------------
*/
- /* -------------------------------------------------------
- * unsigned long platform_get_stack (unsigned long mpidr)
- *
- * For the current CPU, this function returns the stack
- * pointer for a stack allocated in device memory. The
- * 'mpidr' should correspond to that of the current CPU.
- * This function is deprecated and plat_get_my_stack()
- * should be used instead.
- * -------------------------------------------------------
- */
-func_deprecated platform_get_stack
-#if ENABLE_ASSERTIONS
- mrs x1, mpidr_el1
- cmp x0, x1
- ASM_ASSERT(eq)
-#endif
- b plat_get_my_stack
-endfunc_deprecated platform_get_stack
-
- /* -----------------------------------------------------
- * void platform_set_stack (unsigned long mpidr)
- *
- * For the current CPU, this function sets the stack pointer
- * to a stack allocated in normal memory. The
- * 'mpidr' should correspond to that of the current CPU.
- * This function is deprecated and plat_get_my_stack()
- * should be used instead.
- * -----------------------------------------------------
- */
-func_deprecated platform_set_stack
-#if ENABLE_ASSERTIONS
- mrs x1, mpidr_el1
- cmp x0, x1
- ASM_ASSERT(eq)
-#endif
- b plat_set_my_stack
-endfunc_deprecated platform_set_stack
-
/* -----------------------------------------------------
* uintptr_t plat_get_my_stack ()
*
ret
endfunc plat_set_my_stack
- /* -----------------------------------------------------
- * unsigned long platform_get_stack ()
- *
- * For cold-boot BL images, only the primary CPU needs a
- * stack. This function returns the stack pointer for a
- * stack allocated in device memory. This function
- * is deprecated.
- * -----------------------------------------------------
- */
-func_deprecated platform_get_stack
- b plat_get_my_stack
-endfunc_deprecated platform_get_stack
-
- /* -----------------------------------------------------
- * void platform_set_stack ()
- *
- * For cold-boot BL images, only the primary CPU needs a
- * stack. This function sets the stack pointer to a stack
- * allocated in normal memory.This function is
- * deprecated.
- * -----------------------------------------------------
- */
-func_deprecated platform_set_stack
- b plat_set_my_stack
-endfunc_deprecated platform_set_stack
-
/* -----------------------------------------------------
* Single cpu stack in normal memory.
* Used for C code during boot, PLATFORM_STACK_SIZE bytes
# generated while the code is executing in S-EL1/0.
TSP_NS_INTR_ASYNC_PREEMPT := 0
-# If TSPD_ROUTE_IRQ_TO_EL3 build flag is defined, use it to define value for
-# TSP_NS_INTR_ASYNC_PREEMPT for backward compatibility.
-ifdef TSPD_ROUTE_IRQ_TO_EL3
-ifeq (${ERROR_DEPRECATED},1)
-$(error "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT")
-endif
-$(warning "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT")
-TSP_NS_INTR_ASYNC_PREEMPT := ${TSPD_ROUTE_IRQ_TO_EL3}
-endif
-
ifeq ($(EL3_EXCEPTION_HANDLING),1)
ifeq ($(TSP_NS_INTR_ASYNC_PREEMPT),0)
$(error When EL3_EXCEPTION_HANDLING=1, TSP_NS_INTR_ASYNC_PREEMPT must also be 1)
projects / project / bcm63xx / atf.git / commitdiff