sunxi: cortexa7: fix ethernet link detection on a20-olinuxino-lime2

a20-olinuxino-lime2 is currently having hard time with link detection of
certain 1000Mbit partners due to usage of generic PHY driver, probably
due to following missing workaround introduced in upstream in commit
3aed3e2a143c ("net: phy: micrel: add Asym Pause workaround"):

 The Micrel KSZ9031 PHY may fail to establish a link when the Asymmetric
 Pause capability is set. This issue is described in a Silicon Errata
 (DS80000691D or DS80000692D), which advises to always disable the
 capability. This patch implements the workaround by defining a KSZ9031
 specific get_feature callback to force the Asymmetric Pause capability
 bit to be cleared.

 This fixes issues where the link would not come up at boot time, or when
 the Asym Pause bit was set later on.

As a20-olinuxino-lime2 has Micrel KSZ9031RNXCC-TR Gigabit PHY since
revision H, so we need to use Micrel PHY driver on those devices.

Signed-off-by: Petr Štetiar <ynezz@true.cz>
(cherry picked from commit ffa1088f63267f817a3adf34c84b8e8089b1a938)

diff --git a/target/linux/sunxi/cortexa7/config-5.4 b/target/linux/sunxi/cortexa7/config-5.4
index 0b3697028facf1efe277dd08d9d29e3312b9eb1f..cc56cc0e1ba414a264feb98016d28fc12f6e8813 100644 (file)
--- a/target/linux/sunxi/cortexa7/config-5.4
+++ b/target/linux/sunxi/cortexa7/config-5.4
@@ -7,6 +7,7 @@ CONFIG_DWMAC_SUN8I=y
 # CONFIG_MACH_SUN4I is not set
 # CONFIG_MACH_SUN5I is not set
 CONFIG_MDIO_BUS_MUX=y
+CONFIG_MICREL_PHY=y
 # CONFIG_PINCTRL_SUN50I_A64 is not set
 # CONFIG_PINCTRL_SUN50I_A64_R is not set
 # CONFIG_PINCTRL_SUN50I_H5 is not set