endif
ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
+# We can't do this yet due to the need for binary blobs
+# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+
# enable combined SPL/u-boot/dtb rules for tegra
ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_SPL),y)
u-boot.hex u-boot.srec: u-boot FORCE
$(call if_changed,objcopy)
-OBJCOPYFLAGS_u-boot.bin := -O binary
+OBJCOPYFLAGS_u-boot.bin := -O binary \
+ $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
binary_size_check: u-boot.bin FORCE
@file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
+# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
+# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
+# the middle.
+ifneq ($(CONFIG_X86_RESET_VECTOR),)
+rom: u-boot.rom FORCE
+
+u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \
+ $(srctree)/board/$(BOARDDIR)/mrc.bin
+ $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) u-boot.tmp
+ if [ -n "$(CONFIG_HAVE_INTEL_ME)" ]; then \
+ $(objtree)/tools/ifdtool -D \
+ $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp; \
+ $(objtree)/tools/ifdtool \
+ -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp; \
+ fi
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \
+ u-boot.tmp
+ $(objtree)/tools/ifdtool -w \
+ $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
+ u-boot.tmp
+ mv u-boot.tmp $@
+
+OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
+u-boot-x86-16bit.bin: u-boot FORCE
+ $(call if_changed,objcopy)
+endif
+
ifneq ($(CONFIG_SUNXI),)
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
endchoice
+config ROM_SIZE
+ hex
+ default 0x800000
+
+config HAVE_INTEL_ME
+ bool "Platform requires Intel Management Engine"
+ help
+ Newer higher-end devices have an Intel Management Engine (ME)
+ which is a very large binary blob (typically 1.5MB) which is
+ required for the platform to work. This enforces a particular
+ SPI flash format. You will need to supply the me.bin file in
+ your board directory.
+
source "arch/x86/cpu/ivybridge/Kconfig"
source "board/chromebook-x86/coreboot/Kconfig"