rcar_gen3: drivers: ddr_b: Clean up camel case
authorMarek Vasut <marek.vasut+renesas@gmail.com>
Wed, 7 Aug 2019 17:17:42 +0000 (19:17 +0200)
committerMarek Vasut <marek.vasut+renesas@gmail.com>
Thu, 29 Aug 2019 11:02:30 +0000 (13:02 +0200)
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ifda28578f326b1d4518560384d50ae98806db26e

drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c

index c8e9ae802015b8d5a34982de5f5a92f5f94fc1c9..244caf6e53971a13efd068679ab223a18771f54a 100644 (file)
 #ifdef RCAR_DDR_FIXED_LSI_TYPE
 #ifndef RCAR_AUTO
 #define RCAR_AUTO      99
-#define RCAR_H3        0
-#define RCAR_M3        1
+#define RCAR_H3                0
+#define RCAR_M3                1
 #define RCAR_M3N       2
-#define RCAR_E3        3               /*  NON */
+#define RCAR_E3                3       /* NON */
 #define RCAR_H3N       4
 
 #define RCAR_CUT_10    0
 #ifndef RCAR_LSI
 #define RCAR_LSI       RCAR_AUTO
 #endif
+
 #if (RCAR_LSI == RCAR_AUTO)
-static uint32_t Prr_Product;
-static uint32_t Prr_Cut;
+static uint32_t prr_product;
+static uint32_t prr_cut;
 #else
 #if (RCAR_LSI == RCAR_H3)
-static const uint32_t Prr_Product = PRR_PRODUCT_H3;
+static const uint32_t prr_product = PRR_PRODUCT_H3;
 #elif(RCAR_LSI == RCAR_M3)
-static const uint32_t Prr_Product = PRR_PRODUCT_M3;
+static const uint32_t prr_product = PRR_PRODUCT_M3;
 #elif(RCAR_LSI == RCAR_M3N)
-static const uint32_t Prr_Product = PRR_PRODUCT_M3N;
+static const uint32_t prr_product = PRR_PRODUCT_M3N;
 #elif(RCAR_LSI == RCAR_H3N)
-static const uint32_t Prr_Product = PRR_PRODUCT_H3;
+static const uint32_t prr_product = PRR_PRODUCT_H3;
 #endif /* RCAR_LSI */
 
 #ifndef RCAR_LSI_CUT
-static uint32_t Prr_Cut;
+static uint32_t prr_cut;
 #else /* RCAR_LSI_CUT */
 #if (RCAR_LSI_CUT == RCAR_CUT_10)
-static const uint32_t Prr_Cut = PRR_PRODUCT_10;
+static const uint32_t prr_cut = PRR_PRODUCT_10;
 #elif(RCAR_LSI_CUT == RCAR_CUT_11)
-static const uint32_t Prr_Cut = PRR_PRODUCT_11;
+static const uint32_t prr_cut = PRR_PRODUCT_11;
 #elif(RCAR_LSI_CUT == RCAR_CUT_20)
-static const uint32_t Prr_Cut = PRR_PRODUCT_20;
+static const uint32_t prr_cut = PRR_PRODUCT_20;
 #elif(RCAR_LSI_CUT == RCAR_CUT_30)
-static const uint32_t Prr_Cut = PRR_PRODUCT_30;
+static const uint32_t prr_cut = PRR_PRODUCT_30;
 #endif /* RCAR_LSI_CUT */
 #endif /* RCAR_LSI_CUT */
 #endif /* RCAR_AUTO_NON */
 #else /* RCAR_DDR_FIXED_LSI_TYPE */
-static uint32_t Prr_Product;
-static uint32_t Prr_Cut;
+static uint32_t prr_product;
+static uint32_t prr_cut;
 #endif /* RCAR_DDR_FIXED_LSI_TYPE */
 
-char *pRCAR_DDR_VERSION;
-uint32_t _cnf_BOARDTYPE;
-static const uint32_t *pDDR_REGDEF_TBL;
+static const uint32_t *p_ddr_regdef_tbl;
 static uint32_t brd_clk;
 static uint32_t brd_clkdiv;
 static uint32_t brd_clkdiva;
@@ -88,7 +87,7 @@ static uint32_t ddr_mbps;
 static uint32_t ddr_mbpsdiv;
 static uint32_t ddr_tccd;
 static uint32_t ddr_phycaslice;
-static const struct _boardcnf *Boardcnf;
+static const struct _boardcnf *board_cnf;
 static uint32_t ddr_phyvalid;
 static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
 static uint32_t ch_have_this_cs[CS_CNT] __attribute__ ((aligned(64)));
@@ -119,10 +118,10 @@ static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
 static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
 static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
 static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
-static uint32_t Pll3Mode;
+static uint32_t pll3_mode;
 static uint32_t loop_max;
 #ifdef DDR_BACKUPMODE
-uint32_t ddrBackup;
+uint32_t ddr_backup;
 /* #define DDR_BACKUPMODE_HALF           //for Half channel(ch0,1 only) */
 #endif
 
@@ -292,13 +291,13 @@ static uint32_t rx_offset_cal_hw(void);
 static void adjust_rddqs_latency(void);
 static void adjust_wpath_latency(void);
 
-struct DdrtData {
+struct ddrt_data {
        int32_t init_temp;      /*  Initial Temperature (do) */
        uint32_t init_cal[4];   /*  Initial io-code (4 is for H3) */
        uint32_t tcomp_cal[4];  /*  Temperature compensated io-code (4 is for H3) */
 };
 
-struct DdrtData tcal;
+static struct ddrt_data tcal;
 
 static void pvtcode_update(void);
 static void pvtcode_update2(void);
@@ -363,129 +362,129 @@ static void cpg_write_32(uint32_t a, uint32_t v)
 
 static void pll3_control(uint32_t high)
 {
-       uint32_t dataL, dataDIV, dataMUL, tmpDIV;
+       uint32_t data_l, data_div, data_mul, tmp_div;
 
        if (high) {
-               tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+               tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
                        (brd_clk * ddr_mul) / 2;
-               dataMUL = (((ddr_mul * tmpDIV) - 1) << 24) |
+               data_mul = (((ddr_mul * tmp_div) - 1) << 24) |
                        (brd_clkdiva << 7);
-               Pll3Mode = 1;
+               pll3_mode = 1;
                loop_max = 2;
        } else {
-               tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+               tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
                        (brd_clk * ddr0800_mul) / 2;
-               dataMUL = (((ddr0800_mul * tmpDIV) - 1) << 24) |
+               data_mul = (((ddr0800_mul * tmp_div) - 1) << 24) |
                        (brd_clkdiva << 7);
-               Pll3Mode = 0;
+               pll3_mode = 0;
                loop_max = 8;
        }
 
-       switch (tmpDIV) {
+       switch (tmp_div) {
        case 1:
-               dataDIV = 0;
+               data_div = 0;
                break;
        case 2:
        case 3:
        case 4:
-               dataDIV = tmpDIV;
+               data_div = tmp_div;
                break;
        default:
-               dataDIV = 6;
-               dataMUL = (dataMUL * tmpDIV) / 3;
+               data_div = 6;
+               data_mul = (data_mul * tmp_div) / 3;
                break;
        }
-       dataMUL = dataMUL | (brd_clkdiva << 7);
+       data_mul = data_mul | (brd_clkdiva << 7);
 
        /* PLL3 disable */
-       dataL = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
-       cpg_write_32(CPG_PLLECR, dataL);
+       data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
+       cpg_write_32(CPG_PLLECR, data_l);
        dsb_sev();
 
-       if ((Prr_Product == PRR_PRODUCT_M3) ||
-           ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+       if ((prr_product == PRR_PRODUCT_M3) ||
+           ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) {
                /* PLL3 DIV resetting(Lowest value:3) */
-               dataL = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-               cpg_write_32(CPG_FRQCRD, dataL);
+               data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+               cpg_write_32(CPG_FRQCRD, data_l);
                dsb_sev();
 
                /* zb3 clk stop */
-               dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
-               cpg_write_32(CPG_ZB3CKCR, dataL);
+               data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
+               cpg_write_32(CPG_ZB3CKCR, data_l);
                dsb_sev();
 
                /* PLL3 enable */
-               dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
-               cpg_write_32(CPG_PLLECR, dataL);
+               data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+               cpg_write_32(CPG_PLLECR, data_l);
                dsb_sev();
 
                do {
-                       dataL = mmio_read_32(CPG_PLLECR);
-               } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+                       data_l = mmio_read_32(CPG_PLLECR);
+               } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
                dsb_sev();
 
                /* PLL3 DIV resetting (Highest value:0) */
-               dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-               cpg_write_32(CPG_FRQCRD, dataL);
+               data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+               cpg_write_32(CPG_FRQCRD, data_l);
                dsb_sev();
 
                /* DIV SET KICK */
-               dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-               cpg_write_32(CPG_FRQCRB, dataL);
+               data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+               cpg_write_32(CPG_FRQCRB, data_l);
                dsb_sev();
 
                /* PLL3 multiplie set */
-               cpg_write_32(CPG_PLL3CR, dataMUL);
+               cpg_write_32(CPG_PLL3CR, data_mul);
                dsb_sev();
 
                do {
-                       dataL = mmio_read_32(CPG_PLLECR);
-               } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+                       data_l = mmio_read_32(CPG_PLLECR);
+               } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
                dsb_sev();
 
                /* PLL3 DIV resetting(Target value) */
-               dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-               cpg_write_32(CPG_FRQCRD, dataL);
+               data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+               cpg_write_32(CPG_FRQCRD, data_l);
                dsb_sev();
 
                /* DIV SET KICK */
-               dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-               cpg_write_32(CPG_FRQCRB, dataL);
+               data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+               cpg_write_32(CPG_FRQCRB, data_l);
                dsb_sev();
 
                do {
-                       dataL = mmio_read_32(CPG_PLLECR);
-               } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+                       data_l = mmio_read_32(CPG_PLLECR);
+               } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
                dsb_sev();
 
                /* zb3 clk start */
-               dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
-               cpg_write_32(CPG_ZB3CKCR, dataL);
+               data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
+               cpg_write_32(CPG_ZB3CKCR, data_l);
                dsb_sev();
 
        } else { /*  H3Ver.3.0/M3N/V3H */
 
                /* PLL3 multiplie set */
-               cpg_write_32(CPG_PLL3CR, dataMUL);
+               cpg_write_32(CPG_PLL3CR, data_mul);
                dsb_sev();
 
                /* PLL3 DIV set(Target value) */
-               dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
-               cpg_write_32(CPG_FRQCRD, dataL);
+               data_l = (data_div << 16) | data_div | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+               cpg_write_32(CPG_FRQCRD, data_l);
 
                /* DIV SET KICK */
-               dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
-               cpg_write_32(CPG_FRQCRB, dataL);
+               data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+               cpg_write_32(CPG_FRQCRB, data_l);
                dsb_sev();
 
                /* PLL3 enable */
-               dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
-               cpg_write_32(CPG_PLLECR, dataL);
+               data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+               cpg_write_32(CPG_PLLECR, data_l);
                dsb_sev();
 
                do {
-                       dataL = mmio_read_32(CPG_PLLECR);
-               } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+                       data_l = mmio_read_32(CPG_PLLECR);
+               } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
                dsb_sev();
        }
 }
@@ -503,15 +502,15 @@ static inline void dsb_sev(void)
  ******************************************************************************/
 static void wait_dbcmd(void)
 {
-       uint32_t dataL;
+       uint32_t data_l;
        /* dummy read */
-       dataL = mmio_read_32(DBSC_DBCMD);
+       data_l = mmio_read_32(DBSC_DBCMD);
        dsb_sev();
        while (1) {
                /* wait DBCMD 1=busy, 0=ready */
-               dataL = mmio_read_32(DBSC_DBWAIT);
+               data_l = mmio_read_32(DBSC_DBWAIT);
                dsb_sev();
-               if ((dataL & 0x00000001) == 0x00)
+               if ((data_l & 0x00000001) == 0x00)
                        break;
        }
 }
@@ -533,8 +532,8 @@ static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
        uint32_t loop;
 
        val = 0;
-       if ((Prr_Product != PRR_PRODUCT_M3N)
-           && (Prr_Product != PRR_PRODUCT_V3H)) {
+       if ((prr_product != PRR_PRODUCT_M3N)
+           && (prr_product != PRR_PRODUCT_V3H)) {
                mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
                dsb_sev();
 
@@ -580,8 +579,8 @@ static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
        uint32_t val;
        uint32_t loop;
 
-       if ((Prr_Product != PRR_PRODUCT_M3N)
-           && (Prr_Product != PRR_PRODUCT_V3H)) {
+       if ((prr_product != PRR_PRODUCT_M3N)
+           && (prr_product != PRR_PRODUCT_V3H)) {
                mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
                dsb_sev();
                for (loop = 0; loop < loop_max; loop++) {
@@ -629,8 +628,8 @@ static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
        uint32_t val;
        uint32_t loop;
 
-       if ((Prr_Product != PRR_PRODUCT_M3N)
-           && (Prr_Product != PRR_PRODUCT_V3H)) {
+       if ((prr_product != PRR_PRODUCT_M3N)
+           && (prr_product != PRR_PRODUCT_V3H)) {
                foreach_vch(ch) {
                        mmio_write_32(DBSC_DBPDRGA(ch), regadd);
                        dsb_sev();
@@ -668,17 +667,17 @@ static inline void ddrphy_regif_idle(void)
  ******************************************************************************/
 static inline uint32_t ddr_regdef(uint32_t _regdef)
 {
-       return pDDR_REGDEF_TBL[_regdef];
+       return p_ddr_regdef_tbl[_regdef];
 }
 
 static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
 {
-       return DDR_REGDEF_ADR(pDDR_REGDEF_TBL[_regdef]);
+       return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]);
 }
 
 static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
 {
-       return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]);
+       return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]);
 }
 
 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
@@ -864,8 +863,8 @@ static uint32_t ddrphy_regif_chk(void)
        uint32_t err;
        uint32_t PI_VERSION_CODE;
 
-       if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-           || (Prr_Product == PRR_PRODUCT_M3)) {
+       if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
+           || (prr_product == PRR_PRODUCT_M3)) {
                PI_VERSION_CODE = 0x2041;       /* H3 Ver.1.x/M3-W */
        } else {
                PI_VERSION_CODE = 0x2040;       /* H3 Ver.2.0 or later/M3-N/V3H */
@@ -885,11 +884,11 @@ static uint32_t ddrphy_regif_chk(void)
  ******************************************************************************/
 struct _jedec_spec1 {
        uint16_t fx3;
-       uint8_t RLwoDBI;
-       uint8_t RLwDBI;
+       uint8_t rlwodbi;
+       uint8_t rlwdbi;
        uint8_t WL;
-       uint8_t nWR;
-       uint8_t nRTP;
+       uint8_t nwr;
+       uint8_t nrtp;
        uint8_t MR1;
        uint8_t MR2;
 };
@@ -915,33 +914,33 @@ struct _jedec_spec2 {
        uint16_t cyc;
 };
 
-#define JS2_tSR 0
-#define JS2_tXP 1
-#define JS2_tRTP 2
-#define JS2_tRCD 3
-#define JS2_tRPpb 4
-#define JS2_tRPab 5
-#define JS2_tRAS 6
-#define JS2_tWR 7
-#define JS2_tWTR 8
-#define JS2_tRRD 9
-#define JS2_tPPD 10
-#define JS2_tFAW 11
-#define JS2_tDQSCK 12
-#define JS2_tCKEHCMD 13
-#define JS2_tCKELCMD 14
-#define JS2_tCKELPD 15
-#define JS2_tMRR 16
-#define JS2_tMRW 17
-#define JS2_tMRD 18
-#define JS2_tZQCALns 19
-#define JS2_tZQLAT 20
-#define JS2_tIEdly 21
+#define js2_tsr 0
+#define js2_txp 1
+#define js2_trtp 2
+#define js2_trcd 3
+#define js2_trppb 4
+#define js2_trpab 5
+#define js2_tras 6
+#define js2_twr 7
+#define js2_twtr 8
+#define js2_trrd 9
+#define js2_tppd 10
+#define js2_tfaw 11
+#define js2_tdqsck 12
+#define js2_tckehcmd 13
+#define js2_tckelcmd 14
+#define js2_tckelpd 15
+#define js2_tmrr 16
+#define js2_tmrw 17
+#define js2_tmrd 18
+#define js2_tzqcalns 19
+#define js2_tzqlat 20
+#define js2_tiedly 21
 #define JS2_TBLCNT 22
 
-#define JS2_tRCpb (JS2_TBLCNT)
-#define JS2_tRCab (JS2_TBLCNT + 1)
-#define JS2_tRFCab (JS2_TBLCNT + 2)
+#define js2_trcpb (JS2_TBLCNT)
+#define js2_trcab (JS2_TBLCNT + 1)
+#define js2_trfcab (JS2_TBLCNT + 2)
 #define JS2_CNT (JS2_TBLCNT + 3)
 
 #ifndef JS2_DERATE
@@ -997,7 +996,7 @@ const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
        }
 };
 
-const uint16_t jedec_spec2_tRFC_ab[7] = {
+const uint16_t jedec_spec2_trfc_ab[7] = {
 /*     4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non)  */
         130, 180, 180, 280, 280, 560, 560
 };
@@ -1034,8 +1033,8 @@ static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
                                  jedec_spec2[JS2_DERATE][i].cyc);
        }
 
-       js2[JS2_tRCpb] = js2[JS2_tRAS] + js2[JS2_tRPpb];
-       js2[JS2_tRCab] = js2[JS2_tRAS] + js2[JS2_tRPab];
+       js2[js2_trcpb] = js2[js2_tras] + js2[js2_trppb];
+       js2[js2_trcab] = js2[js2_tras] + js2[js2_trpab];
 }
 
 /* scaler for DELAY value */
@@ -1055,7 +1054,7 @@ static int16_t _f_scale_adj(int16_t ps)
        return (int16_t)tmp;
 }
 
-const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = {
+static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = {
        {
         _reg_PI_MR1_DATA_F0_0,
         _reg_PI_MR1_DATA_F0_1,
@@ -1068,7 +1067,7 @@ const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = {
         _reg_PI_MR1_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = {
+static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = {
        {
         _reg_PI_MR2_DATA_F0_0,
         _reg_PI_MR2_DATA_F0_1,
@@ -1081,7 +1080,7 @@ const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = {
         _reg_PI_MR2_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = {
+static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = {
        {
         _reg_PI_MR3_DATA_F0_0,
         _reg_PI_MR3_DATA_F0_1,
@@ -1094,7 +1093,7 @@ const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = {
         _reg_PI_MR3_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = {
+const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = {
        {
         _reg_PI_MR11_DATA_F0_0,
         _reg_PI_MR11_DATA_F0_1,
@@ -1107,7 +1106,7 @@ const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = {
         _reg_PI_MR11_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = {
+const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = {
        {
         _reg_PI_MR12_DATA_F0_0,
         _reg_PI_MR12_DATA_F0_1,
@@ -1120,7 +1119,7 @@ const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = {
         _reg_PI_MR12_DATA_F1_3}
 };
 
-const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = {
+const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = {
        {
         _reg_PI_MR14_DATA_F0_0,
         _reg_PI_MR14_DATA_F0_1,
@@ -1140,7 +1139,7 @@ static void regif_pll_wa(void)
 {
        uint32_t ch;
 
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                // PLL setting for PHY : H3 Ver.1.x
                reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
                                   (0x0064U <<
@@ -1188,7 +1187,7 @@ static void regif_pll_wa(void)
        ddrphy_regif_idle();
        pll3_control(0);
 
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                /*  non */
        } else {
                reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
@@ -1221,7 +1220,7 @@ static void regif_pll_wa(void)
        dsb_sev();
 
        foreach_ech(ch)
-       if (((Boardcnf->phyvalid) & (1U << ch)))
+       if (((board_cnf->phyvalid) & (1U << ch)))
                while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f);
        dsb_sev();
 }
@@ -1235,7 +1234,7 @@ static void ddrtbl_load(void)
        uint32_t slice;
        uint32_t csab;
        uint32_t adr;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t tmp[3];
        uint16_t dataS;
 
@@ -1252,10 +1251,10 @@ static void ddrtbl_load(void)
        else
                js1_ind = i;
 
-       if (Boardcnf->dbi_en)
-               RL = js1[js1_ind].RLwDBI;
+       if (board_cnf->dbi_en)
+               RL = js1[js1_ind].rlwdbi;
        else
-               RL = js1[js1_ind].RLwoDBI;
+               RL = js1[js1_ind].rlwodbi;
 
        WL = js1[js1_ind].WL;
 
@@ -1265,8 +1264,8 @@ static void ddrtbl_load(void)
        /***********************************************************************
        PREPARE TBL
        ***********************************************************************/
-       if (Prr_Product == PRR_PRODUCT_H3) {
-               if (Prr_Cut <= PRR_PRODUCT_11) {
+       if (prr_product == PRR_PRODUCT_H3) {
+               if (prr_cut <= PRR_PRODUCT_11) {
                        /*  H3 Ver.1.x */
                        _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
                                 DDR_PHY_SLICE_REGSET_H3,
@@ -1342,7 +1341,7 @@ static void ddrtbl_load(void)
 
                        DDR_PHY_ADR_I_NUM = 0;
                }
-       } else if (Prr_Product == PRR_PRODUCT_M3) {
+       } else if (prr_product == PRR_PRODUCT_M3) {
                /*  M3-W */
                _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
                         DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3);
@@ -1408,7 +1407,7 @@ static void ddrtbl_load(void)
        /***********************************************************************
        PLL CODE CHANGE
        ***********************************************************************/
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
                ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL,
                              0x1142);
                ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
@@ -1418,7 +1417,7 @@ static void ddrtbl_load(void)
        /***********************************************************************
        on fly gate adjust
        ***********************************************************************/
-       if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10)) {
+       if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) {
                ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
                              _reg_ON_FLY_GATE_ADJUST_EN, 0x00);
        }
@@ -1430,7 +1429,7 @@ static void ddrtbl_load(void)
        for (i = 0; i < 2; i++) {
                for (csab = 0; csab < CSAB_CNT; csab++) {
                        ddrtbl_setval(_cnf_DDR_PI_REGSET,
-                                     _reg_PI_MR11_DATA_Fx_CSx[i][csab],
+                                     reg_pi_mr11_data_fx_csx[i][csab],
                                      _def_LPDDR4_ODT);
                }
        }
@@ -1440,43 +1439,43 @@ static void ddrtbl_load(void)
        for (i = 0; i < 2; i++) {
                for (csab = 0; csab < CSAB_CNT; csab++) {
                        ddrtbl_setval(_cnf_DDR_PI_REGSET,
-                                     _reg_PI_MR12_DATA_Fx_CSx[i][csab],
+                                     reg_pi_mr12_data_fx_csx[i][csab],
                                      _def_LPDDR4_VREFCA);
                }
        }
 #endif /* _def_LPDDR4_VREFCA */
-       if ((Prr_Product == PRR_PRODUCT_M3N)
-           || (Prr_Product == PRR_PRODUCT_V3H)) {
-               js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
-               if (js2[JS2_tIEdly] > (RL))
-                       js2[JS2_tIEdly] = RL;
-       } else if ((Prr_Product == PRR_PRODUCT_H3)
-                  && (Prr_Cut > PRR_PRODUCT_11)) {
-               js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
-       } else if ((Prr_Product == PRR_PRODUCT_H3)
-                  && (Prr_Cut <= PRR_PRODUCT_11)) {
-               js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
-       }
-
-       if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-           || (Prr_Product == PRR_PRODUCT_M3N)
-           || (Prr_Product == PRR_PRODUCT_V3H)) {
-               if ((js2[JS2_tIEdly]) >= 0x1e)
+       if ((prr_product == PRR_PRODUCT_M3N)
+           || (prr_product == PRR_PRODUCT_V3H)) {
+               js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
+               if (js2[js2_tiedly] > (RL))
+                       js2[js2_tiedly] = RL;
+       } else if ((prr_product == PRR_PRODUCT_H3)
+                  && (prr_cut > PRR_PRODUCT_11)) {
+               js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
+       } else if ((prr_product == PRR_PRODUCT_H3)
+                  && (prr_cut <= PRR_PRODUCT_11)) {
+               js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
+       }
+
+       if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11))
+           || (prr_product == PRR_PRODUCT_M3N)
+           || (prr_product == PRR_PRODUCT_V3H)) {
+               if ((js2[js2_tiedly]) >= 0x1e)
                        dataS = 0x1e;
                else
-                       dataS = js2[JS2_tIEdly];
+                       dataS = js2[js2_tiedly];
        } else {
-               if ((js2[JS2_tIEdly]) >= 0x0e)
+               if ((js2[js2_tiedly]) >= 0x0e)
                        dataS = 0x0e;
                else
-                       dataS = js2[JS2_tIEdly];
+                       dataS = js2[js2_tiedly];
        }
 
        ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
        ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
                      (dataS - 2));
-       if ((Prr_Product == PRR_PRODUCT_M3N)
-           || (Prr_Product == PRR_PRODUCT_V3H)) {
+       if ((prr_product == PRR_PRODUCT_M3N)
+           || (prr_product == PRR_PRODUCT_V3H)) {
                ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
                              _reg_PHY_RDDATA_EN_OE_DLY, dataS);
        }
@@ -1484,14 +1483,14 @@ static void ddrtbl_load(void)
 
        if (ddrtbl_getval
            (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) {
-               dataL = WL - 1;
+               data_l = WL - 1;
        } else {
-               dataL = WL;
+               data_l = WL;
        }
-       ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, dataL - 2);
-       ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, dataL);
+       ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2);
+       ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l);
 
-       if (Boardcnf->dbi_en) {
+       if (board_cnf->dbi_en) {
                ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
                              0x01);
                ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
@@ -1505,27 +1504,27 @@ static void ddrtbl_load(void)
 
        tmp[0] = js1[js1_ind].MR1;
        tmp[1] = js1[js1_ind].MR2;
-       dataL = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
-       if (Boardcnf->dbi_en)
-               tmp[2] = dataL | 0xc0;
+       data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
+       if (board_cnf->dbi_en)
+               tmp[2] = data_l | 0xc0;
        else
-               tmp[2] = dataL & (~0xc0);
+               tmp[2] = data_l & (~0xc0);
 
        for (i = 0; i < 2; i++) {
                for (csab = 0; csab < CSAB_CNT; csab++) {
                        ddrtbl_setval(_cnf_DDR_PI_REGSET,
-                                     _reg_PI_MR1_DATA_Fx_CSx[i][csab], tmp[0]);
+                                     reg_pi_mr1_data_fx_csx[i][csab], tmp[0]);
                        ddrtbl_setval(_cnf_DDR_PI_REGSET,
-                                     _reg_PI_MR2_DATA_Fx_CSx[i][csab], tmp[1]);
+                                     reg_pi_mr2_data_fx_csx[i][csab], tmp[1]);
                        ddrtbl_setval(_cnf_DDR_PI_REGSET,
-                                     _reg_PI_MR3_DATA_Fx_CSx[i][csab], tmp[2]);
+                                     reg_pi_mr3_data_fx_csx[i][csab], tmp[2]);
                }
        }
 
        /***********************************************************************
         DDRPHY INT START
        ***********************************************************************/
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                /*  non */
        } else {
                regif_pll_wa();
@@ -1559,9 +1558,9 @@ static void ddrtbl_load(void)
                reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
        }
 
-       if (((Prr_Product == PRR_PRODUCT_M3)
-           || (Prr_Product == PRR_PRODUCT_M3N)) &&
-           ((0x00ffffff & (uint32_t)((Boardcnf->ch[0].ca_swap) >> 40))
+       if (((prr_product == PRR_PRODUCT_M3)
+           || (prr_product == PRR_PRODUCT_M3N)) &&
+           ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40))
            != 0x00)) {
                adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
                for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
@@ -1576,7 +1575,7 @@ static void ddrtbl_load(void)
                for (i = 0; i < 2; i++) {
                        for (csab = 0; csab < CSAB_CNT; csab++) {
                                ddrtbl_setval(_cnf_DDR_PI_REGSET,
-                                             _reg_PI_MR11_DATA_Fx_CSx[i][csab],
+                                             reg_pi_mr11_data_fx_csx[i][csab],
                                              0x66);
                        }
                }
@@ -1622,7 +1621,7 @@ static void ddr_config_sub(void)
 {
        uint32_t i;
        uint32_t ch, slice;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t tmp;
        uint8_t high_byte[SLICE_CNT];
        const uint32_t _par_CALVL_DEVICE_MAP = 1;
@@ -1633,11 +1632,11 @@ static void ddr_config_sub(void)
        ***********************************************************************/
                for (slice = 0; slice < SLICE_CNT; slice++) {
                        high_byte[slice] =
-                           (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
+                           (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
                        ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
-                                    Boardcnf->ch[ch].dq_swap[slice]);
+                                    board_cnf->ch[ch].dq_swap[slice]);
                        ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
-                                    Boardcnf->ch[ch].dm_swap[slice]);
+                                    board_cnf->ch[ch].dm_swap[slice]);
                        if (high_byte[slice]) {
                                /* HIGHER 16 BYTE */
                                ddr_setval_s(ch, slice,
@@ -1654,56 +1653,56 @@ static void ddr_config_sub(void)
        /***********************************************************************
                BOARD SETTINGS (CA,ADDR_SEL)
        ***********************************************************************/
-               dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) |
+               data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
                        0x00888888;
 
                /* --- ADR_CALVL_SWIZZLE --- */
-               if (Prr_Product == PRR_PRODUCT_M3) {
-                       ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
+               if (prr_product == PRR_PRODUCT_M3) {
+                       ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
                        ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
                                   0x00000000);
-                       ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
+                       ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
                        ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
                                   0x00000000);
                        ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
                                   _par_CALVL_DEVICE_MAP);
                } else {
-                       ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
+                       ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
                        ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
                        ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
                                   _par_CALVL_DEVICE_MAP);
                }
 
                /* --- ADR_ADDR_SEL --- */
-               if ((Prr_Product == PRR_PRODUCT_H3)
-                   && (Prr_Cut > PRR_PRODUCT_11)) {
-                       dataL = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+               if ((prr_product == PRR_PRODUCT_H3)
+                   && (prr_cut > PRR_PRODUCT_11)) {
+                       data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
                } else {
-                       dataL = 0;
-                       tmp = Boardcnf->ch[ch].ca_swap;
+                       data_l = 0;
+                       tmp = board_cnf->ch[ch].ca_swap;
                        for (i = 0; i < 6; i++) {
-                               dataL |= ((tmp & 0x0f) << (i * 5));
+                               data_l |= ((tmp & 0x0f) << (i * 5));
                                tmp = tmp >> 4;
                        }
                }
-               ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL);
+               ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
                if (ddr_phycaslice == 1) {
                        /* ----------- adr slice2 swap ----------- */
-                       tmp  = (uint32_t)((Boardcnf->ch[ch].ca_swap) >> 40);
-                       dataL = (tmp & 0x00ffffff) | 0x00888888;
+                       tmp  = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
+                       data_l = (tmp & 0x00ffffff) | 0x00888888;
 
                        /* --- ADR_CALVL_SWIZZLE --- */
-                       if (Prr_Product == PRR_PRODUCT_M3) {
-                               ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
+                       if (prr_product == PRR_PRODUCT_M3) {
+                               ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
                                ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
                                             0x00000000);
-                               ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
+                               ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
                                ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
                                             0x00000000);
                                ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP,
                                             _par_CALVL_DEVICE_MAP);
                        } else {
-                               ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
+                               ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
                                ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1,
                                             0x00000000);
                                ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP,
@@ -1711,42 +1710,42 @@ static void ddr_config_sub(void)
                        }
 
                        /* --- ADR_ADDR_SEL --- */
-                       dataL = 0;
+                       data_l = 0;
                        for (i = 0; i < 6; i++) {
-                               dataL |= ((tmp & 0x0f) << (i * 5));
+                               data_l |= ((tmp & 0x0f) << (i * 5));
                                tmp = tmp >> 4;
                        }
 
-                       ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, dataL);
+                       ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
                }
 
        /***********************************************************************
                BOARD SETTINGS (BYTE_ORDER_SEL)
        ***********************************************************************/
-               if (Prr_Product == PRR_PRODUCT_M3) {
+               if (prr_product == PRR_PRODUCT_M3) {
                        /* --- DATA_BYTE_SWAP --- */
-                       dataL = 0;
-                       tmp = Boardcnf->ch[ch].dqs_swap;
+                       data_l = 0;
+                       tmp = board_cnf->ch[ch].dqs_swap;
                        for (i = 0; i < 4; i++) {
-                               dataL |= ((tmp & 0x03) << (i * 2));
+                               data_l |= ((tmp & 0x03) << (i * 2));
                                tmp = tmp >> 4;
                        }
                } else {
                        /* --- DATA_BYTE_SWAP --- */
-                       dataL = Boardcnf->ch[ch].dqs_swap;
+                       data_l = board_cnf->ch[ch].dqs_swap;
                        ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
                        ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
-                                  (dataL) & 0x0f);
+                                  (data_l) & 0x0f);
                        ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
-                                  (dataL >> 4 * 1) & 0x0f);
+                                  (data_l >> 4 * 1) & 0x0f);
                        ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
-                                  (dataL >> 4 * 2) & 0x0f);
+                                  (data_l >> 4 * 2) & 0x0f);
                        ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
-                                  (dataL >> 4 * 3) & 0x0f);
+                                  (data_l >> 4 * 3) & 0x0f);
 
                        ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00);
                }
-               ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL);
+               ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
        }
 }
 
@@ -1763,11 +1762,11 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz)
        }
 
        for (slice = 0; slice < SLICE_CNT; slice++) {
-               tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+               tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
                if (tgt == tmp)
                        break;
        }
-       tmp = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+       tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
        if (slice % 2)
                tmp |= 0x00888888;
        *p_swz = tmp;
@@ -1776,7 +1775,7 @@ static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz)
 static void ddr_config_sub_h3v1x(void)
 {
        uint32_t ch, slice;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t tmp;
        uint8_t high_byte[SLICE_CNT];
        uint32_t ca_swizzle;
@@ -1798,14 +1797,14 @@ static void ddr_config_sub_h3v1x(void)
        ***********************************************************************/
                csmap = 0;
                for (slice = 0; slice < SLICE_CNT; slice++) {
-                       tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+                       tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
                        high_byte[slice] = tmp % 2;
                        if (tmp == 1 && (slice >= 2))
                                csmap |= 0x05;
                        if (tmp == 3 && (slice >= 2))
                                csmap |= 0x50;
                        ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING,
-                                    Boardcnf->ch[ch].dq_swap[slice]);
+                                    board_cnf->ch[ch].dq_swap[slice]);
                        if (high_byte[slice]) {
                                /* HIGHER 16 BYTE */
                                ddr_setval_s(ch, slice,
@@ -1821,7 +1820,7 @@ static void ddr_config_sub_h3v1x(void)
        /***********************************************************************
                BOARD SETTINGS (CA,ADDR_SEL)
        ***********************************************************************/
-               ca = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+               ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
                ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
                ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap);
 
@@ -1844,7 +1843,7 @@ static void ddr_config_sub_h3v1x(void)
                        else
                                o_inv = o_mr15;
 
-                       tmp = Boardcnf->ch[ch].dq_swap[slice];
+                       tmp = board_cnf->ch[ch].dq_swap[slice];
                        inv = 0;
                        j = 0;
                        for (bit_soc = 0; bit_soc < 8; bit_soc++) {
@@ -1853,13 +1852,13 @@ static void ddr_config_sub_h3v1x(void)
                                if (o_inv & (1U << bit_mem))
                                        inv |= (1U << bit_soc);
                        }
-                       dataL = o_mr32_mr40;
+                       data_l = o_mr32_mr40;
                        if (!high_byte[slice])
-                               dataL |= (inv << 24);
+                               data_l |= (inv << 24);
                        if (high_byte[slice])
-                               dataL |= (inv << 16);
+                               data_l |= (inv << 16);
                        ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8,
-                                    dataL);
+                                    data_l);
                }
        }
 }
@@ -1868,7 +1867,7 @@ static void ddr_config(void)
 {
        int32_t i;
        uint32_t ch, slice;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t tmp;
        int8_t _adj;
        int16_t adj;
@@ -1882,7 +1881,7 @@ static void ddr_config(void)
        /***********************************************************************
        configure ddrphy registers
        ***********************************************************************/
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                ddr_config_sub_h3v1x();
        } else {
                ddr_config_sub();       /*  H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */
@@ -1895,7 +1894,7 @@ static void ddr_config(void)
                for (slice = 0; slice < SLICE_CNT; slice++) {
                        patm = 0;
                        for (i = 0; i < 16; i++) {
-                               tmp = Boardcnf->ch[ch].wdqlvl_patt[i];
+                               tmp = board_cnf->ch[ch].wdqlvl_patt[i];
                                patt.ui8[i] = tmp & 0xff;
                                if (tmp & 0x100)
                                        patm |= (1U << i);
@@ -1915,14 +1914,14 @@ static void ddr_config(void)
        /***********************************************************************
        CACS DLY
        ***********************************************************************/
-       dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
+       data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
        reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U);
        foreach_vch(ch) {
                for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) {
-                       adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+                       adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
                        ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
                                      _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-                                     dataL + adj);
+                                     data_l + adj);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(
                                        _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
@@ -1934,10 +1933,10 @@ static void ddr_config(void)
 
                for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4);
                     i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
-                       adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+                       adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
                        ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
                                      _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-                                     dataL + adj);
+                                     data_l + adj);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(
                                        _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
@@ -1950,11 +1949,11 @@ static void ddr_config(void)
                if (ddr_phycaslice == 1) {
                        for (i = 0; i < 6; i++) {
                                adj = _f_scale_adj(
-                                       Boardcnf->ch[ch].cacs_adj[
+                                       board_cnf->ch[ch].cacs_adj[
                                        i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
                                ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
                                              _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-                                             dataL + adj);
+                                             data_l + adj);
                                reg_ddrphy_write(ch,
                                                 ddr_regdef_adr(
                                        _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
@@ -1973,19 +1972,19 @@ static void ddr_config(void)
        /***********************************************************************
        WDQDM DLY
        ***********************************************************************/
-       dataL = Boardcnf->dqdm_dly_w;
+       data_l = board_cnf->dqdm_dly_w;
        foreach_vch(ch) {
                for (slice = 0; slice < SLICE_CNT; slice++) {
                        for (i = 0; i <= 8; i++) {
                                dq = slice * 8 + i;
                                if (i == 8)
-                                       _adj = Boardcnf->ch[ch].dm_adj_w[slice];
+                                       _adj = board_cnf->ch[ch].dm_adj_w[slice];
                                else
-                                       _adj = Boardcnf->ch[ch].dq_adj_w[dq];
+                                       _adj = board_cnf->ch[ch].dq_adj_w[dq];
                                adj = _f_scale_adj(_adj);
                                ddr_setval_s(ch, slice,
                                             _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
-                                            dataL + adj);
+                                            data_l + adj);
                        }
                }
        }
@@ -1993,22 +1992,22 @@ static void ddr_config(void)
        /***********************************************************************
        RDQDM DLY
        ***********************************************************************/
-       dataL = Boardcnf->dqdm_dly_r;
+       data_l = board_cnf->dqdm_dly_r;
        foreach_vch(ch) {
                for (slice = 0; slice < SLICE_CNT; slice++) {
                        for (i = 0; i <= 8; i++) {
                                dq = slice * 8 + i;
                                if (i == 8)
-                                       _adj = Boardcnf->ch[ch].dm_adj_r[slice];
+                                       _adj = board_cnf->ch[ch].dm_adj_r[slice];
                                else
-                                       _adj = Boardcnf->ch[ch].dq_adj_r[dq];
+                                       _adj = board_cnf->ch[ch].dq_adj_r[dq];
                                adj = _f_scale_adj(_adj);
                                ddr_setval_s(ch, slice,
                                             _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
-                                            [i], dataL + adj);
+                                            [i], data_l + adj);
                                ddr_setval_s(ch, slice,
                                             _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
-                                            [i], dataL + adj);
+                                            [i], data_l + adj);
                        }
                }
        }
@@ -2020,7 +2019,7 @@ static void ddr_config(void)
 static void dbsc_regset_pre(void)
 {
        uint32_t ch, csab;
-       uint32_t dataL;
+       uint32_t data_l;
 
        /***********************************************************************
        PRIMARY SETTINGS
@@ -2034,7 +2033,7 @@ static void dbsc_regset_pre(void)
        mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
 
        /* Chanel map (H3 Ver.1.x) */
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
                mmio_write_32(DBSC_DBSCHCNT1, 0x00001010);
 
        /* DRAM SIZE REGISTER:
@@ -2044,20 +2043,20 @@ static void dbsc_regset_pre(void)
        for (csab = 0; csab < 4; csab++)
                mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0));
 
-       if (Prr_Product == PRR_PRODUCT_M3) {
-               dataL = 0xe4e4e4e4;
+       if (prr_product == PRR_PRODUCT_M3) {
+               data_l = 0xe4e4e4e4;
                foreach_ech(ch) {
                        if ((ddr_phyvalid & (1U << ch)))
-                               dataL = (dataL & (~(0x000000FF << (ch * 8))))
-                                   | (((Boardcnf->ch[ch].dqs_swap & 0x0003)
-                                       | ((Boardcnf->ch[ch].dqs_swap & 0x0030)
+                               data_l = (data_l & (~(0x000000FF << (ch * 8))))
+                                   | (((board_cnf->ch[ch].dqs_swap & 0x0003)
+                                       | ((board_cnf->ch[ch].dqs_swap & 0x0030)
                                           >> 2)
-                                       | ((Boardcnf->ch[ch].dqs_swap & 0x0300)
+                                       | ((board_cnf->ch[ch].dqs_swap & 0x0300)
                                           >> 4)
-                                       | ((Boardcnf->ch[ch].dqs_swap & 0x3000)
+                                       | ((board_cnf->ch[ch].dqs_swap & 0x3000)
                                           >> 6)) << (ch * 8));
                }
-               mmio_write_32(DBSC_DBBSWAP, dataL);
+               mmio_write_32(DBSC_DBBSWAP, data_l);
        }
 }
 
@@ -2065,20 +2064,20 @@ static void dbsc_regset(void)
 {
        int32_t i;
        uint32_t ch;
-       uint32_t dataL;
-       uint32_t dataL2;
+       uint32_t data_l;
+       uint32_t data_l2;
        uint32_t tmp[4];
 
        /* RFC */
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20)
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20)
            && (max_density == 0)) {
-               js2[JS2_tRFCab] =
+               js2[js2_trfcab] =
                    _f_scale(ddr_mbps, ddr_mbpsdiv,
-                            1UL * jedec_spec2_tRFC_ab[1] * 1000, 0);
+                            1UL * jedec_spec2_trfc_ab[1] * 1000, 0);
        } else {
-               js2[JS2_tRFCab] =
+               js2[js2_trfcab] =
                    _f_scale(ddr_mbps, ddr_mbpsdiv,
-                            1UL * jedec_spec2_tRFC_ab[max_density] *
+                            1UL * jedec_spec2_trfc_ab[max_density] *
                             1000, 0);
        }
 
@@ -2092,46 +2091,46 @@ static void dbsc_regset(void)
        mmio_write_32(DBSC_DBTR(2), 0);
 
        /* DBTR3.TRCD: tRCD */
-       mmio_write_32(DBSC_DBTR(3), js2[JS2_tRCD]);
+       mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]);
 
        /* DBTR4.TRPA,TRP: tRPab,tRPpb */
-       mmio_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]);
+       mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]);
 
        /* DBTR5.TRC : use tRCpb */
-       mmio_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]);
+       mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]);
 
        /* DBTR6.TRAS : tRAS */
-       mmio_write_32(DBSC_DBTR(6), js2[JS2_tRAS]);
+       mmio_write_32(DBSC_DBTR(6), js2[js2_tras]);
 
        /* DBTR7.TRRD : tRRD */
-       mmio_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]);
+       mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]);
 
        /* DBTR8.TFAW : tFAW */
-       mmio_write_32(DBSC_DBTR(8), js2[JS2_tFAW]);
+       mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]);
 
        /* DBTR9.TRDPR : tRTP */
-       mmio_write_32(DBSC_DBTR(9), js2[JS2_tRTP]);
+       mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
 
-       /* DBTR10.TWR : nWR */
-       mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nWR);
+       /* DBTR10.TWR : nwr */
+       mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
 
        /* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */
        mmio_write_32(DBSC_DBTR(11),
-                     RL + js2[JS2_tDQSCK] + (16 / 2) + 1 - WL + 2 + 2);
+                     RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2);
 
        /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
-       dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR];
-       mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL);
+       data_l = WL + 1 + (16 / 2) + js2[js2_twtr];
+       mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l);
 
        /* DBTR13.TRFCAB : tRFCab */
-       mmio_write_32(DBSC_DBTR(13), (js2[JS2_tRFCab]));
+       mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab]));
 
        /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
        mmio_write_32(DBSC_DBTR(14),
-                     (js2[JS2_tCKEHCMD] << 16) | (js2[JS2_tCKEHCMD]));
+                     (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd]));
 
        /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
-       mmio_write_32(DBSC_DBTR(15), (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD]));
+       mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd]));
 
        /* DBTR16 */
        /* WDQL : tphy_wrlat + tphy_wrdata */
@@ -2154,13 +2153,13 @@ static void dbsc_regset(void)
        /* WRCSGAP = 5 */
        tmp[1] = 5;
        /* RDCSLAT = RDLAT_ADJ +2 */
-       if (Prr_Product == PRR_PRODUCT_M3) {
+       if (prr_product == PRR_PRODUCT_M3) {
                tmp[2] = tmp[3];
        } else {
                tmp[2] = tmp[3] + 2;
        }
        /* RDCSGAP = 6 */
-       if (Prr_Product == PRR_PRODUCT_M3) {
+       if (prr_product == PRR_PRODUCT_M3) {
                tmp[3] = 4;
        } else {
                tmp[3] = 6;
@@ -2170,7 +2169,7 @@ static void dbsc_regset(void)
 
        /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
        mmio_write_32(DBSC_DBTR(17),
-                     (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16));
+                     (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16));
 
        /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
        mmio_write_32(DBSC_DBTR(18), 0);
@@ -2179,32 +2178,32 @@ static void dbsc_regset(void)
        mmio_write_32(DBSC_DBTR(19), 0);
 
        /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
-       dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD];
-       mmio_write_32(DBSC_DBTR(20), (dataL << 16) | dataL);
+       data_l = js2[js2_trfcab] + js2[js2_tckehcmd];
+       mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l);
 
        /* DBTR21.TCCD */
        /* DBTR23.TCCD */
        /* H3 Ver.1.0 cannot use TBTR23 feature */
        if (ddr_tccd == 8 &&
-           !((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_10))
+           !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10))
            ) {
-               dataL = 8;
-               mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+               data_l = 8;
+               mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
                mmio_write_32(DBSC_DBTR(23), 0x00000002);
        } else if (ddr_tccd <= 11) {
-               dataL = 11;
-               mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+               data_l = 11;
+               mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
                mmio_write_32(DBSC_DBTR(23), 0x00000000);
        } else {
-               dataL = ddr_tccd;
-               mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+               data_l = ddr_tccd;
+               mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
                mmio_write_32(DBSC_DBTR(23), 0x00000000);
        }
 
        /* DBTR22.ZQLAT : */
-       dataL = js2[JS2_tZQCALns] * 100;        /*  1000 * 1000 ps */
-       dataL = (dataL << 16) | (js2[JS2_tZQLAT] + 24 + 20);
-       mmio_write_32(DBSC_DBTR(22), dataL);
+       data_l = js2[js2_tzqcalns] * 100;       /*  1000 * 1000 ps */
+       data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20);
+       mmio_write_32(DBSC_DBTR(22), data_l);
 
        /* DBTR25 : do not use in LPDDR4 */
        mmio_write_32(DBSC_DBTR(25), 0);
@@ -2219,16 +2218,16 @@ static void dbsc_regset(void)
 #define _par_DBRNK_VAL         (0x7007)
 
        for (i = 0; i < 4; i++) {
-               dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
-               if ((Prr_Product == PRR_PRODUCT_H3)
-                   && (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) {
-                       dataL += 1;
+               data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
+               if ((prr_product == PRR_PRODUCT_H3)
+                   && (prr_cut > PRR_PRODUCT_11) && (i == 0)) {
+                       data_l += 1;
                }
-               dataL2 = 0;
+               data_l2 = 0;
                foreach_vch(ch) {
-                       dataL2 = dataL2 | (dataL << (4 * ch));
+                       data_l2 = data_l2 | (data_l << (4 * ch));
                }
-               mmio_write_32(DBSC_DBRNK(2 + i), dataL2);
+               mmio_write_32(DBSC_DBRNK(2 + i), data_l2);
        }
        mmio_write_32(DBSC_DBADJ0, 0x00000000);
 
@@ -2237,17 +2236,17 @@ static void dbsc_regset(void)
        ***********************************************************************/
        /* SCFCTST0 */
        /* SCFCTST0 ACT-ACT */
-       tmp[3] = 1UL * js2[JS2_tRCpb] * 800 * ddr_mbpsdiv / ddr_mbps;
+       tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps;
        /* SCFCTST0 RDA-ACT */
        tmp[2] =
-           1UL * ((16 / 2) + js2[JS2_tRTP] - 8 +
-                  js2[JS2_tRPpb]) * 800 * ddr_mbpsdiv / ddr_mbps;
+           1UL * ((16 / 2) + js2[js2_trtp] - 8 +
+                  js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps;
        /* SCFCTST0 WRA-ACT */
        tmp[1] =
            1UL * (WL + 1 + (16 / 2) +
-                  js1[js1_ind].nWR) * 800 * ddr_mbpsdiv / ddr_mbps;
+                  js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps;
        /* SCFCTST0 PRE-ACT */
-       tmp[0] = 1UL * js2[JS2_tRPpb];
+       tmp[0] = 1UL * js2[js2_trppb];
        mmio_write_32(DBSC_SCFCTST0,
                      (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
 
@@ -2261,7 +2260,7 @@ static void dbsc_regset(void)
            1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv /
            ddr_mbps;
        /* SCFCTST1 ACT-RD/WR */
-       tmp[1] = 1UL * js2[JS2_tRCD] * 800 * ddr_mbpsdiv / ddr_mbps;
+       tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps;
        /* SCFCTST1 ASYNCOFS */
        tmp[0] = 12;
        mmio_write_32(DBSC_SCFCTST1,
@@ -2269,14 +2268,14 @@ static void dbsc_regset(void)
 
        /* DBSCHRW1 */
        /* DBSCHRW1 SCTRFCAB */
-       tmp[0] = 1UL * js2[JS2_tRFCab] * 800 * ddr_mbpsdiv / ddr_mbps;
-       dataL = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16)
+       tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps;
+       data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16)
                 + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
                 + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7;
-       if (tmp[0] < dataL)
-               tmp[0] = dataL;
+       if (tmp[0] < data_l)
+               tmp[0] = data_l;
 
-       if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
+       if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
                mmio_write_32(DBSC_DBSCHRW1, tmp[0]
                        + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
                        * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3);
@@ -2334,18 +2333,18 @@ static void dbsc_regset(void)
        mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
 #endif /* ddr_qos_init_setting */
        /* H3 Ver.1.1 need to set monitor function */
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
                mmio_write_32(DBSC_DBMONCONF4, 0x00700000);
        }
 
-       if (Prr_Product == PRR_PRODUCT_H3) {
-               if (Prr_Cut == PRR_PRODUCT_10) {
+       if (prr_product == PRR_PRODUCT_H3) {
+               if (prr_cut == PRR_PRODUCT_10) {
                        /* resrdis, simple mode, sc off */
                        mmio_write_32(DBSC_DBBCAMDIS, 0x00000007);
-               } else if (Prr_Cut == PRR_PRODUCT_11) {
+               } else if (prr_cut == PRR_PRODUCT_11) {
                        /* resrdis, simple mode         */
                        mmio_write_32(DBSC_DBBCAMDIS, 0x00000005);
-               } else if (Prr_Cut < PRR_PRODUCT_30) {
+               } else if (prr_cut < PRR_PRODUCT_30) {
                        /* H3 Ver.2.0                   */
                        /* resrdis                      */
                        mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
@@ -2362,7 +2361,7 @@ static void dbsc_regset(void)
 static void dbsc_regset_post(void)
 {
        uint32_t ch, cs;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t slice, rdlat_max, rdlat_min;
 
        rdlat_max = 0;
@@ -2374,18 +2373,18 @@ static void dbsc_regset_post(void)
                                        ddr_setval_s(ch, slice,
                                                     _reg_PHY_PER_CS_TRAINING_INDEX,
                                                     cs);
-                                       dataL =
+                                       data_l =
                                            ddr_getval_s(ch, slice,
                                                         _reg_PHY_RDDQS_LATENCY_ADJUST);
-                                       if (dataL > rdlat_max)
-                                               rdlat_max = dataL;
-                                       if (dataL < rdlat_min)
-                                               rdlat_min = dataL;
+                                       if (data_l > rdlat_max)
+                                               rdlat_max = data_l;
+                                       if (data_l < rdlat_min)
+                                               rdlat_min = data_l;
                                }
                        }
                }
        }
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) {
                mmio_write_32(DBSC_DBTR(24),
                              ((rdlat_max * 2 - rdlat_min + 4) << 24) +
                              ((rdlat_min + 2) << 16) +
@@ -2415,24 +2414,24 @@ static void dbsc_regset_post(void)
        mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
 
        /*set DBI */
-       if (Boardcnf->dbi_en)
+       if (board_cnf->dbi_en)
                mmio_write_32(DBSC_DBDBICNT, 0x00000003);
 
        /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */
-       if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-            || (Prr_Product == PRR_PRODUCT_M3N)
-            || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en))
+       if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11))
+            || (prr_product == PRR_PRODUCT_M3N)
+            || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en))
                reg_ddrphy_write_a(0x00001010, 0x01000000);
 
        /*set REFCYCLE */
-       dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
-       mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff));
+       data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
+       mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff));
        mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
 
 #ifdef DDR_BACKUPMODE
-       if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
+       if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
 #ifdef DDR_BACKUPMODE_HALF     /* for Half channel(ch0,1 only) */
-               PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
+               DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
                send_dbcmd(0x08040001);
                wait_dbcmd();
                send_dbcmd(0x0A040001);
@@ -2440,7 +2439,7 @@ static void dbsc_regset_post(void)
                send_dbcmd(0x04040010);
                wait_dbcmd();
 
-               if (Prr_Product == PRR_PRODUCT_H3) {
+               if (prr_product == PRR_PRODUCT_H3) {
                        send_dbcmd(0x08140001);
                        wait_dbcmd();
                        send_dbcmd(0x0A140001);
@@ -2462,8 +2461,8 @@ static void dbsc_regset_post(void)
 
 #if RCAR_REWT_TRAINING != 0
        /* Periodic-WriteDQ Training seeting */
-       if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-           || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) {
+       if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
+           || ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10))) {
                /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
        } else {
                /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H -> Periodic-WriteDQ Training seeting */
@@ -2487,7 +2486,7 @@ static void dbsc_regset_post(void)
                ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
                ddr_setval_ach(_reg_PI_TREF_F2, 0x0000);
 
-               if (Prr_Product == PRR_PRODUCT_M3) {
+               if (prr_product == PRR_PRODUCT_M3) {
                        ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02);
                } else {
                        ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02);
@@ -2500,13 +2499,13 @@ static void dbsc_regset_post(void)
 #endif /* RCAR_REWT_TRAINING */
        /* periodic dram zqcal and phy ctrl update enable */
        mmio_write_32(DBSC_DBCALCNF, 0x01000010);
-       if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-           || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
+       if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
+           || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
                /* non : H3 Ver.1.x/M3-W Ver.1.x not support */
        } else {
 #if RCAR_DRAM_SPLIT == 2
-               if ((Prr_Product == PRR_PRODUCT_H3)
-                   && (Boardcnf->phyvalid == 0x05))
+               if ((prr_product == PRR_PRODUCT_H3)
+                   && (board_cnf->phyvalid == 0x05))
                        mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001);
                else
                        mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001);
@@ -2531,10 +2530,10 @@ static uint32_t dfi_init_start(void)
        uint32_t ch;
        uint32_t phytrainingok;
        uint32_t retry;
-       uint32_t dataL;
+       uint32_t data_l;
        const uint32_t RETRY_MAX = 0x10000;
 
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
        /***********************************************************************
                PLL3 Disable
        ***********************************************************************/
@@ -2584,8 +2583,8 @@ static uint32_t dfi_init_start(void)
        retry = 0;
        while (retry++ < RETRY_MAX) {
                foreach_vch(ch) {
-                       dataL = mmio_read_32(DBSC_DBDFISTAT(ch));
-                       if (dataL & 0x00000001)
+                       data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
+                       if (data_l & 0x00000001)
                                phytrainingok |= (1U << ch);
                }
                dsb_sev();
@@ -2621,7 +2620,7 @@ static void change_lpddr4_en(uint32_t mode)
 {
        uint32_t ch;
        uint32_t i;
-       uint32_t dataL;
+       uint32_t data_l;
        const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
                _reg_PHY_PAD_ADDR_DRIVE,
                _reg_PHY_PAD_CLK_DRIVE,
@@ -2630,13 +2629,13 @@ static void change_lpddr4_en(uint32_t mode)
 
        foreach_vch(ch) {
                for (i = 0; i < 3; i++) {
-                       dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
+                       data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
                        if (mode) {
-                               dataL |= (1U << 14);
+                               data_l |= (1U << 14);
                        } else {
-                               dataL &= ~(1U << 14);
+                               data_l &= ~(1U << 14);
                        }
-                       ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], dataL);
+                       ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
                }
        }
 }
@@ -2648,7 +2647,7 @@ static uint32_t set_term_code(void)
 {
        int32_t i;
        uint32_t ch, index;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t chip_id[2];
        uint32_t term_code;
        uint32_t override;
@@ -2664,12 +2663,12 @@ static uint32_t set_term_code(void)
 
        index = 0;
        while (1) {
-               if (TermcodeBySample[index][0] == 0xffffffff) {
+               if (termcode_by_sample[index][0] == 0xffffffff) {
                        break;
                }
-               if ((TermcodeBySample[index][0] == chip_id[0])
-                   && (TermcodeBySample[index][1] == chip_id[1])) {
-                       term_code = TermcodeBySample[index][2];
+               if ((termcode_by_sample[index][0] == chip_id[0])
+                   && (termcode_by_sample[index][1] == chip_id[1])) {
+                       term_code = termcode_by_sample[index][2];
                        override = 1;
                        break;
                }
@@ -2678,14 +2677,14 @@ static uint32_t set_term_code(void)
 
        if (override) {
                for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
-                       dataL =
+                       data_l =
                            ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
                                          _reg_PHY_PAD_TERM_X[index]);
-                       dataL = (dataL & 0xfffe0000) | term_code;
-                       ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL);
+                       data_l = (data_l & 0xfffe0000) | term_code;
+                       ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l);
                }
-       } else if ((Prr_Product == PRR_PRODUCT_M3)
-                  && (Prr_Cut == PRR_PRODUCT_10)) {
+       } else if ((prr_product == PRR_PRODUCT_M3)
+                  && (prr_cut == PRR_PRODUCT_10)) {
                /*  non */
        } else {
                ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
@@ -2696,55 +2695,55 @@ static uint32_t set_term_code(void)
                ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01);
                foreach_vch(ch) {
                        do {
-                               dataL =
+                               data_l =
                                    ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
-                       } while (!(dataL & 0x00800000));
+                       } while (!(data_l & 0x00800000));
                }
-               if ((Prr_Product == PRR_PRODUCT_H3)
-                   && (Prr_Cut <= PRR_PRODUCT_11)) {
+               if ((prr_product == PRR_PRODUCT_H3)
+                   && (prr_cut <= PRR_PRODUCT_11)) {
                        foreach_vch(ch) {
-                               dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
-                               pvtr = (dataL >> 12) & 0x1f;
+                               data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
+                               pvtr = (data_l >> 12) & 0x1f;
                                pvtr += 8;
                                if (pvtr > 0x1f)
                                        pvtr = 0x1f;
-                               dataL =
+                               data_l =
                                    ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
-                               pvtn = (dataL >> 6) & 0x03f;
-                               pvtp = (dataL >> 0) & 0x03f;
+                               pvtn = (data_l >> 6) & 0x03f;
+                               pvtp = (data_l >> 0) & 0x03f;
 
                                for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
                                     index++) {
-                                       dataL =
+                                       data_l =
                                            ddrtbl_getval
                                            (_cnf_DDR_PHY_ADR_G_REGSET,
                                             _reg_PHY_PAD_TERM_X[index]);
-                                       dataL = (dataL & 0xfffe0000)
+                                       data_l = (data_l & 0xfffe0000)
                                            | (pvtr << 12)
                                            | (pvtn << 6)
                                            | (pvtp);
                                        ddr_setval(ch,
                                                   _reg_PHY_PAD_TERM_X[index],
-                                                  dataL);
+                                                  data_l);
                                }
                        }
                } else {        /*  M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */
                        foreach_vch(ch) {
                                for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
                                     index++) {
-                                       dataL =
+                                       data_l =
                                            ddr_getval(ch,
                                                       _reg_PHY_PAD_TERM_X
                                                       [index]);
                                        ddr_setval(ch,
                                                   _reg_PHY_PAD_TERM_X[index],
-                                                  (dataL & 0xFFFE0FFF) |
+                                                  (data_l & 0xFFFE0FFF) |
                                                   0x00015000);
                                }
                        }
                }
        }
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                /*  non */
        } else {
                ddr_padcal_tcompensate_getinit(override);
@@ -2766,32 +2765,32 @@ static void ddr_register_set(void)
 
                tmp =
                    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-                                 _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]);
+                                 reg_pi_mr1_data_fx_csx[fspwp][0]);
                send_dbcmd(0x0e840100 | tmp);
 
                tmp =
                    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-                                 _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]);
+                                 reg_pi_mr2_data_fx_csx[fspwp][0]);
                send_dbcmd(0x0e840200 | tmp);
 
                tmp =
                    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-                                 _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]);
+                                 reg_pi_mr3_data_fx_csx[fspwp][0]);
                send_dbcmd(0x0e840300 | tmp);
 
                tmp =
                    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-                                 _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]);
+                                 reg_pi_mr11_data_fx_csx[fspwp][0]);
                send_dbcmd(0x0e840b00 | tmp);
 
                tmp =
                    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-                                 _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]);
+                                 reg_pi_mr12_data_fx_csx[fspwp][0]);
                send_dbcmd(0x0e840c00 | tmp);
 
                tmp =
                    ddrtbl_getval(_cnf_DDR_PI_REGSET,
-                                 _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]);
+                                 reg_pi_mr14_data_fx_csx[fspwp][0]);
                send_dbcmd(0x0e840e00 | tmp);
                /* MR22 */
                send_dbcmd(0x0e841616);
@@ -2803,33 +2802,33 @@ static void ddr_register_set(void)
  ******************************************************************************/
 static inline uint32_t wait_freqchgreq(uint32_t assert)
 {
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t count;
        uint32_t ch;
 
        count = 100000;
 
        /* H3 Ver.1.x cannot see frqchg_req */
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                return 0;
        }
 
        if (assert) {
                do {
-                       dataL = 1;
+                       data_l = 1;
                        foreach_vch(ch) {
-                               dataL &= mmio_read_32(DBSC_DBPDSTAT(ch));
+                               data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
                        }
                        count = count - 1;
-               } while (((dataL & 0x01) != 0x01) & (count != 0));
+               } while (((data_l & 0x01) != 0x01) & (count != 0));
        } else {
                do {
-                       dataL = 0;
+                       data_l = 0;
                        foreach_vch(ch) {
-                               dataL |= mmio_read_32(DBSC_DBPDSTAT(ch));
+                               data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
                        }
                        count = count - 1;
-               } while (((dataL & 0x01) != 0x00) & (count != 0));
+               } while (((data_l & 0x01) != 0x00) & (count != 0));
        }
 
        return (count == 0);
@@ -2838,22 +2837,22 @@ static inline uint32_t wait_freqchgreq(uint32_t assert)
 static inline void set_freqchgack(uint32_t assert)
 {
        uint32_t ch;
-       uint32_t dataL;
+       uint32_t data_l;
 
        if (assert)
-               dataL = 0x0CF20000;
+               data_l = 0x0CF20000;
        else
-               dataL = 0x00000000;
+               data_l = 0x00000000;
 
        foreach_vch(ch)
-           mmio_write_32(DBSC_DBPDCNT2(ch), dataL);
+           mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
 }
 
 static inline void set_dfifrequency(uint32_t freq)
 {
        uint32_t ch;
 
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                foreach_vch(ch)
                    mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
        } else {
@@ -2904,7 +2903,7 @@ static void update_dly(void)
 static uint32_t pi_training_go(void)
 {
        uint32_t flag;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t retry;
        const uint32_t RETRY_MAX = 4096 * 16;
        uint32_t ch;
@@ -2939,8 +2938,8 @@ static uint32_t pi_training_go(void)
                frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
 
                /* H3 Ver.1.x cannot see frqchg_req */
-               if ((Prr_Product == PRR_PRODUCT_H3)
-                   && (Prr_Cut <= PRR_PRODUCT_11)) {
+               if ((prr_product == PRR_PRODUCT_H3)
+                   && (prr_cut <= PRR_PRODUCT_11)) {
                        if ((retry % 4096) == 1) {
                                frqchg_req = 1;
                        } else {
@@ -2965,9 +2964,9 @@ static uint32_t pi_training_go(void)
                                foreach_vch(ch) {
                                        if (complete & (1U << ch))
                                                continue;
-                                       dataL =
+                                       data_l =
                                            ddr_getval(ch, _reg_PI_INT_STATUS);
-                                       if (dataL & 0x01) {
+                                       if (data_l & 0x01) {
                                                complete |= (1U << ch);
                                        }
                                }
@@ -2978,9 +2977,9 @@ static uint32_t pi_training_go(void)
        } while (--retry);
        foreach_vch(ch) {
                /* dummy read */
-               dataL = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
-               dataL = ddr_getval(ch, _reg_PI_INT_STATUS);
-               ddr_setval(ch, _reg_PI_INT_ACK, dataL);
+               data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
+               data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
+               ddr_setval(ch, _reg_PI_INT_ACK, data_l);
        }
        if (ddrphy_regif_chk()) {
                return (0xfd);
@@ -2994,7 +2993,7 @@ static uint32_t pi_training_go(void)
 static uint32_t init_ddr(void)
 {
        int32_t i;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t phytrainingok;
        uint32_t ch, slice;
        uint32_t err;
@@ -3003,7 +3002,7 @@ static uint32_t init_ddr(void)
        MSG_LF("init_ddr:0\n");
 
 #ifdef DDR_BACKUPMODE
-       rcar_dram_get_boot_status(&ddrBackup);
+       rcar_dram_get_boot_status(&ddr_backup);
 #endif
 
        /***********************************************************************
@@ -3014,9 +3013,9 @@ static uint32_t init_ddr(void)
            mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A);
        dsb_sev();
 
-       if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-            || (Prr_Product == PRR_PRODUCT_M3N)
-            || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en))
+       if ((((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11))
+            || (prr_product == PRR_PRODUCT_M3N)
+            || (prr_product == PRR_PRODUCT_V3H)) && (board_cnf->dbi_en))
                reg_ddrphy_write_a(0x00001010, 0x01000001);
        else
                reg_ddrphy_write_a(0x00001010, 0x00000001);
@@ -3069,12 +3068,12 @@ static uint32_t init_ddr(void)
        ddr backupmode end
        ***********************************************************************/
 #ifdef DDR_BACKUPMODE
-       if (ddrBackup) {
+       if (ddr_backup) {
                NOTICE("BL2: [WARM_BOOT]\n");
        } else {
                NOTICE("BL2: [COLD_BOOT]\n");
        }
-       err = rcar_dram_update_boot_status(ddrBackup);
+       err = rcar_dram_update_boot_status(ddr_backup);
        if (err) {
                NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
                return INITDRAM_ERR_I;
@@ -3094,8 +3093,8 @@ static uint32_t init_ddr(void)
        /***********************************************************************
        rx offset calibration
        ***********************************************************************/
-       if ((Prr_Cut > PRR_PRODUCT_11) || (Prr_Product == PRR_PRODUCT_M3N)
-           || (Prr_Product == PRR_PRODUCT_V3H)) {
+       if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N)
+           || (prr_product == PRR_PRODUCT_V3H)) {
                err = rx_offset_cal_hw();
        } else {
                err = rx_offset_cal();
@@ -3139,8 +3138,8 @@ static uint32_t init_ddr(void)
        Thermal sensor setting
        ***********************************************************************/
        /* THCTR Bit6: PONM=0 , Bit0: THSST=1  */
-       dataL = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
-       mmio_write_32(THS1_THCTR, dataL);
+       data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
+       mmio_write_32(THS1_THCTR, data_l);
 
        /* LPDDR4 MODE */
        change_lpddr4_en(1);
@@ -3151,10 +3150,10 @@ static uint32_t init_ddr(void)
        mask CS_MAP if RANKx is not found
        ***********************************************************************/
        foreach_vch(ch) {
-               dataL = ddr_getval(ch, _reg_PI_CS_MAP);
+               data_l = ddr_getval(ch, _reg_PI_CS_MAP);
                if (!(ch_have_this_cs[1] & (1U << ch)))
-                       dataL = dataL & 0x05;
-               ddr_setval(ch, _reg_PI_CS_MAP, dataL);
+                       data_l = data_l & 0x05;
+               ddr_setval(ch, _reg_PI_CS_MAP, data_l);
        }
 
        /***********************************************************************
@@ -3164,7 +3163,7 @@ static uint32_t init_ddr(void)
                           BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
        ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
 
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
        ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
        } else {
                foreach_vch(ch) {
@@ -3188,19 +3187,19 @@ static uint32_t init_ddr(void)
        /***********************************************************************
        CACS DLY ADJUST
        ***********************************************************************/
-       dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
+       data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
        foreach_vch(ch) {
                for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
-                       adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+                       adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
                        ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-                                  dataL + adj);
+                                  data_l + adj);
                }
 
                if (ddr_phycaslice == 1) {
                        for (i = 0; i < 6; i++) {
-                               adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+                               adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
                                ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
-                                            dataL + adj
+                                            data_l + adj
                                );
                        }
                }
@@ -3212,7 +3211,7 @@ static uint32_t init_ddr(void)
        /***********************************************************************
        H3 fix rd latency to avoid bug in elasitic buffe
        ***********************************************************************/
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                adjust_rddqs_latency();
        }
 
@@ -3255,9 +3254,9 @@ static uint32_t init_ddr(void)
        /***********************************************************************
        training complete, setup dbsc
        ***********************************************************************/
-       if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-           || (Prr_Product == PRR_PRODUCT_M3N)
-           || (Prr_Product == PRR_PRODUCT_V3H)) {
+       if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11))
+           || (prr_product == PRR_PRODUCT_M3N)
+           || (prr_product == PRR_PRODUCT_V3H)) {
                ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00);
                ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00);
        }
@@ -3274,7 +3273,7 @@ static uint32_t init_ddr(void)
 static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
 {
        uint32_t ch;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t retry;
        uint32_t waiting;
        uint32_t err;
@@ -3303,8 +3302,8 @@ static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
                foreach_vch(ch) {
                        if (!(waiting & (1U << ch)))
                                continue;
-                       dataL = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
-                       if (dataL & 0x01)
+                       data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
+                       if (data_l & 0x01)
                                waiting &= ~(1U << ch);
                }
                retry--;
@@ -3329,15 +3328,15 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
 {
        int32_t i, k;
        uint32_t cs, slice;
-       uint32_t dataL;
+       uint32_t data_l;
 
        /***********************************************************************
        clr of training results buffer
        ***********************************************************************/
        cs = ddr_csn % 2;
-       dataL = Boardcnf->dqdm_dly_w;
+       data_l = board_cnf->dqdm_dly_w;
        for (slice = 0; slice < SLICE_CNT; slice++) {
-               k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+               k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
                if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
                        continue;
 
@@ -3346,7 +3345,7 @@ static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
                                wdqdm_dly[ch][cs][slice][i] =
                                    wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
                        else
-                               wdqdm_dly[ch][cs][slice][i] = dataL;
+                               wdqdm_dly[ch][cs][slice][i] = data_l;
                        wdqdm_le[ch][cs][slice][i] = 0;
                        wdqdm_te[ch][cs][slice][i] = 0;
                }
@@ -3359,7 +3358,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 {
        int32_t i, k;
        uint32_t cs, slice;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t err;
        const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0;
 
@@ -3374,7 +3373,7 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
        ***********************************************************************/
        err = 0;
        for (slice = 0; slice < SLICE_CNT; slice += 1) {
-               k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+               k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
                if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
                        continue;
 
@@ -3383,44 +3382,44 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
                for (i = 0; i < 9; i++) {
                        dq = slice * 8 + i;
                        if (i == 8)
-                               _adj = Boardcnf->ch[ch].dm_adj_w[slice];
+                               _adj = board_cnf->ch[ch].dm_adj_w[slice];
                        else
-                               _adj = Boardcnf->ch[ch].dq_adj_w[dq];
+                               _adj = board_cnf->ch[ch].dq_adj_w[dq];
                        adj = _f_scale_adj(_adj);
 
-                       dataL =
+                       data_l =
                            ddr_getval_s(ch, slice,
                                         _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
                        ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
-                                    dataL);
-                       wdqdm_dly[ch][cs][slice][i] = dataL;
+                                    data_l);
+                       wdqdm_dly[ch][cs][slice][i] = data_l;
                }
                ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
-               dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
-               wdqdm_st[ch][cs][slice] = dataL;
+               data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
+               wdqdm_st[ch][cs][slice] = data_l;
                min_win = INT_LEAST32_MAX;
                for (i = 0; i <= 8; i++) {
                        ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
                                     i);
 
-                       dataL =
+                       data_l =
                            ddr_getval_s(ch, slice,
                                         _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
-                       wdqdm_te[ch][cs][slice][i] = dataL;
-                       dataL =
+                       wdqdm_te[ch][cs][slice][i] = data_l;
+                       data_l =
                            ddr_getval_s(ch, slice,
                                         _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
-                       wdqdm_le[ch][cs][slice][i] = dataL;
+                       wdqdm_le[ch][cs][slice][i] = data_l;
                        win =
                            (int32_t)wdqdm_te[ch][cs][slice][i] -
                            wdqdm_le[ch][cs][slice][i];
                        if (min_win > win)
                                min_win = win;
-                       if (dataL >= _par_WDQLVL_RETRY_THRES)
+                       if (data_l >= _par_WDQLVL_RETRY_THRES)
                                err = 2;
                }
                wdqdm_win[ch][cs][slice] = min_win;
-               if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+               if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01);
                } else {
                        ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
@@ -3474,7 +3473,7 @@ static uint32_t wdqdm_man1(void)
        int32_t k;
        uint32_t ch, cs, slice;
        uint32_t ddr_csn;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t err;
        uint32_t high_dq[DRAM_CH_CNT];
        uint32_t mr14_csab0_bak[DRAM_CH_CNT];
@@ -3485,11 +3484,11 @@ static uint32_t wdqdm_man1(void)
        /***********************************************************************
        manual execution of training
        ***********************************************************************/
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                foreach_vch(ch) {
                        high_dq[ch] = 0;
                        for (slice = 0; slice < SLICE_CNT; slice++) {
-                               k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+                               k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
                                if (k >= 2)
                                        high_dq[ch] |= (1U << slice);
                        }
@@ -3500,10 +3499,10 @@ static uint32_t wdqdm_man1(void)
        /* CLEAR PREV RESULT */
        for (cs = 0; cs < CS_CNT; cs++) {
                ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
-               if (((Prr_Product == PRR_PRODUCT_H3)
-                    && (Prr_Cut > PRR_PRODUCT_11))
-                   || (Prr_Product == PRR_PRODUCT_M3N)
-                   || (Prr_Product == PRR_PRODUCT_V3H)) {
+               if (((prr_product == PRR_PRODUCT_H3)
+                    && (prr_cut > PRR_PRODUCT_11))
+                   || (prr_product == PRR_PRODUCT_M3N)
+                   || (prr_product == PRR_PRODUCT_V3H)) {
                        ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS,
                                          0x01);
                } else {
@@ -3517,33 +3516,33 @@ static uint32_t wdqdm_man1(void)
        err_flg = 0;
 #endif/* DDR_FAST_INIT */
        for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
-               if ((Prr_Product == PRR_PRODUCT_H3)
-                   && (Prr_Cut <= PRR_PRODUCT_11)) {
+               if ((prr_product == PRR_PRODUCT_H3)
+                   && (prr_cut <= PRR_PRODUCT_11)) {
                        foreach_vch(ch) {
-                               dataL = mmio_read_32(DBSC_DBDFICNT(ch));
-                               dataL &= ~(0x00ffU << 16);
+                               data_l = mmio_read_32(DBSC_DBDFICNT(ch));
+                               data_l &= ~(0x00ffU << 16);
 
                                if (ddr_csn >= 2)
                                        k = (high_dq[ch] ^ 0x0f);
                                else
                                        k = high_dq[ch];
-                               dataL |= (k << 16);
-                               mmio_write_32(DBSC_DBDFICNT(ch), dataL);
+                               data_l |= (k << 16);
+                               mmio_write_32(DBSC_DBDFICNT(ch), data_l);
                                ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k);
                        }
                }
-               if (((Prr_Product == PRR_PRODUCT_H3)
-                    && (Prr_Cut <= PRR_PRODUCT_11))
-                   || ((Prr_Product == PRR_PRODUCT_M3)
-                       && (Prr_Cut == PRR_PRODUCT_10))) {
+               if (((prr_product == PRR_PRODUCT_H3)
+                    && (prr_cut <= PRR_PRODUCT_11))
+                   || ((prr_product == PRR_PRODUCT_M3)
+                       && (prr_cut == PRR_PRODUCT_10))) {
                        wdqdm_cp(ddr_csn, 0);
                }
 
                foreach_vch(ch) {
-                       dataL =
+                       data_l =
                            ddr_getval(ch,
-                                      _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]);
-                       ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], dataL);
+                                      reg_pi_mr14_data_fx_csx[1][ddr_csn]);
+                       ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
                }
 
                /* KICK WDQLVL */
@@ -3554,10 +3553,10 @@ static uint32_t wdqdm_man1(void)
                if (ddr_csn == 0)
                        foreach_vch(ch) {
                        mr14_csab0_bak[ch] =
-                           ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0]);
+                           ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]);
                } else
                        foreach_vch(ch) {
-                       ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0],
+                       ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
                                   mr14_csab0_bak[ch]);
                        }
 #ifndef DDR_FAST_INIT
@@ -3577,12 +3576,12 @@ err_exit:
 #ifndef DDR_FAST_INIT
        err |= err_flg;
 #endif/* DDR_FAST_INIT */
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01);
                foreach_vch(ch) {
-                       dataL = mmio_read_32(DBSC_DBDFICNT(ch));
-                       dataL &= ~(0x00ffU << 16);
-                       mmio_write_32(DBSC_DBDFICNT(ch), dataL);
+                       data_l = mmio_read_32(DBSC_DBDFICNT(ch));
+                       data_l &= ~(0x00ffU << 16);
+                       mmio_write_32(DBSC_DBDFICNT(ch), data_l);
                        ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
                }
        }
@@ -3596,9 +3595,9 @@ static uint32_t wdqdm_man(void)
        uint32_t ch, ddr_csn, mr14_bkup[4][4];
 
        ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12);
-       if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
-           || (Prr_Product == PRR_PRODUCT_M3N)
-           || (Prr_Product == PRR_PRODUCT_V3H)) {
+       if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11))
+           || (prr_product == PRR_PRODUCT_M3N)
+           || (prr_product == PRR_PRODUCT_V3H)) {
                ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1,
                               (DBSC_DBTR(12) & 0xFF) + 1);
        } else {
@@ -3610,15 +3609,15 @@ static uint32_t wdqdm_man(void)
        retry_cnt = 0;
        err = 0;
        do {
-               if ((Prr_Product == PRR_PRODUCT_H3)
-                   && (Prr_Cut <= PRR_PRODUCT_11)) {
+               if ((prr_product == PRR_PRODUCT_H3)
+                   && (prr_cut <= PRR_PRODUCT_11)) {
                        err = wdqdm_man1();
                } else {
                        ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
                        ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
                                       0x01);
-                       if ((Prr_Product == PRR_PRODUCT_M3N)
-                           || (Prr_Product == PRR_PRODUCT_V3H)) {
+                       if ((prr_product == PRR_PRODUCT_M3N)
+                           || (prr_product == PRR_PRODUCT_V3H)) {
                                ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
                                               0x0C);
                        } else {
@@ -3630,14 +3629,14 @@ static uint32_t wdqdm_man(void)
                                for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
                                        mr14_bkup[ch][ddr_csn] =
                                            ddr_getval(ch,
-                                                      _reg_PI_MR14_DATA_Fx_CSx
+                                                      reg_pi_mr14_data_fx_csx
                                                       [1][ddr_csn]);
                                        dsb_sev();
                                }
                        }
 
-                       if ((Prr_Product == PRR_PRODUCT_M3N)
-                           || (Prr_Product == PRR_PRODUCT_V3H)) {
+                       if ((prr_product == PRR_PRODUCT_M3N)
+                           || (prr_product == PRR_PRODUCT_V3H)) {
                                ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
                                               0x04);
                        } else {
@@ -3650,10 +3649,10 @@ static uint32_t wdqdm_man(void)
                                        mr14_bkup[ch][ddr_csn] =
                                            (mr14_bkup[ch][ddr_csn] +
                                             ddr_getval(ch,
-                                                       _reg_PI_MR14_DATA_Fx_CSx
+                                                       reg_pi_mr14_data_fx_csx
                                                        [1][ddr_csn])) / 2;
                                        ddr_setval(ch,
-                                                  _reg_PI_MR14_DATA_Fx_CSx[1]
+                                                  reg_pi_mr14_data_fx_csx[1]
                                                   [ddr_csn],
                                                   mr14_bkup[ch][ddr_csn]);
                                }
@@ -3661,8 +3660,8 @@ static uint32_t wdqdm_man(void)
 
                        ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
                                       0x00);
-                       if ((Prr_Product == PRR_PRODUCT_M3N)
-                           || (Prr_Product == PRR_PRODUCT_V3H)) {
+                       if ((prr_product == PRR_PRODUCT_M3N)
+                           || (prr_product == PRR_PRODUCT_V3H)) {
                                ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
                                               0x00);
                                ddr_setval_ach
@@ -3689,8 +3688,8 @@ static uint32_t wdqdm_man(void)
                }
        } while (err && (++retry_cnt < retry_max));
 
-       if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-           || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_10))) {
+       if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
+           || ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) {
                wdqdm_cp(0, 1);
        }
 
@@ -3705,15 +3704,15 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
 {
        int32_t i, k;
        uint32_t cs, slice;
-       uint32_t dataL;
+       uint32_t data_l;
 
        /***********************************************************************
        clr of training results buffer
        ***********************************************************************/
        cs = ddr_csn % 2;
-       dataL = Boardcnf->dqdm_dly_r;
+       data_l = board_cnf->dqdm_dly_r;
        for (slice = 0; slice < SLICE_CNT; slice++) {
-               k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+               k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
                if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
                        continue;
 
@@ -3726,8 +3725,8 @@ static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
                                                                   SLICE_CNT]
                                    [i];
                        } else {
-                               rdqdm_dly[ch][cs][slice][i] = dataL;
-                               rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL;
+                               rdqdm_dly[ch][cs][slice][i] = data_l;
+                               rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
                        }
                        rdqdm_le[ch][cs][slice][i] = 0;
                        rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0;
@@ -3745,7 +3744,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
 {
        int32_t i, k;
        uint32_t cs, slice;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t err;
        int8_t _adj;
        int16_t adj;
@@ -3759,7 +3758,7 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
        ***********************************************************************/
        err = 0;
        for (slice = 0; slice < SLICE_CNT; slice++) {
-               k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+               k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
                if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
                        continue;
 
@@ -3773,36 +3772,36 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
                for (i = 0; i <= 8; i++) {
                        dq = slice * 8 + i;
                        if (i == 8)
-                               _adj = Boardcnf->ch[ch].dm_adj_r[slice];
+                               _adj = board_cnf->ch[ch].dm_adj_r[slice];
                        else
-                               _adj = Boardcnf->ch[ch].dq_adj_r[dq];
+                               _adj = board_cnf->ch[ch].dq_adj_r[dq];
 
                        adj = _f_scale_adj(_adj);
 
-                       dataL =
+                       data_l =
                            ddr_getval_s(ch, slice,
                                         _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) +
                            adj;
                        ddr_setval_s(ch, slice,
                                     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
-                                    dataL);
-                       rdqdm_dly[ch][cs][slice][i] = dataL;
+                                    data_l);
+                       rdqdm_dly[ch][cs][slice][i] = data_l;
 
-                       dataL =
+                       data_l =
                            ddr_getval_s(ch, slice,
                                         _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) +
                            adj;
                        ddr_setval_s(ch, slice,
                                     _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
-                                    dataL);
-                       rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL;
+                                    data_l);
+                       rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
                }
                min_win = INT_LEAST32_MAX;
                for (i = 0; i <= 8; i++) {
-                       dataL =
+                       data_l =
                            ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
-                       rdqdm_st[ch][cs][slice] = dataL;
-                       rdqdm_st[ch][cs][slice + SLICE_CNT] = dataL;
+                       rdqdm_st[ch][cs][slice] = data_l;
+                       rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
                        /* k : rise/fall */
                        for (k = 0; k < 2; k++) {
                                if (i == 8) {
@@ -3814,23 +3813,23 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
                                             _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
                                             rdq_status_obs_select);
 
-                               dataL =
+                               data_l =
                                    ddr_getval_s(ch, slice,
                                                 _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
                                rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] =
-                                   dataL;
+                                   data_l;
 
-                               dataL =
+                               data_l =
                                    ddr_getval_s(ch, slice,
                                                 _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
                                rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] =
-                                   dataL;
+                                   data_l;
 
-                               dataL =
+                               data_l =
                                    ddr_getval_s(ch, slice,
                                                 _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
                                rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] =
-                                   dataL;
+                                   data_l;
 
                                win =
                                    (int32_t)rdqdm_te[ch][cs][slice +
@@ -3858,7 +3857,7 @@ static uint32_t rdqdm_man1(void)
        uint32_t ddr_csn;
 #ifdef DDR_FAST_INIT
        uint32_t slice;
-       uint32_t i, adj, dataL;
+       uint32_t i, adj, data_l;
 #endif/* DDR_FAST_INIT */
        uint32_t err;
 
@@ -3897,26 +3896,26 @@ static uint32_t rdqdm_man1(void)
                                        }
                                }
                        }
-                       if (((Prr_Product == PRR_PRODUCT_H3)
-                           && (Prr_Cut <= PRR_PRODUCT_11))
-                           || ((Prr_Product == PRR_PRODUCT_M3)
-                           && (Prr_Cut <= PRR_PRODUCT_10))) {
+                       if (((prr_product == PRR_PRODUCT_H3)
+                           && (prr_cut <= PRR_PRODUCT_11))
+                           || ((prr_product == PRR_PRODUCT_M3)
+                           && (prr_cut <= PRR_PRODUCT_10))) {
                                for (slice = 0; slice < SLICE_CNT; slice++) {
                                        for (i = 0; i <= 8; i++) {
                                                if (i == 8)
-                                                       adj = _f_scale_adj(Boardcnf->ch[ch].dm_adj_r[slice]);
+                                                       adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
                                                else
-                                                       adj = _f_scale_adj(Boardcnf->ch[ch].dq_adj_r[slice * 8 + i]);
+                                                       adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]);
                                                ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
-                                               dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
-                                               ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL);
-                                               rdqdm_dly[ch][ddr_csn][slice][i] = dataL;
-                                               rdqdm_dly[ch][ddr_csn | 1][slice][i] = dataL;
-
-                                               dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
-                                               ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL);
-                                               rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = dataL;
-                                               rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = dataL;
+                                               data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
+                                               ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
+                                               rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
+                                               rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l;
+
+                                               data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
+                                               ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
+                                               rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
+                                               rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l;
                                        }
                                }
                        }
@@ -4003,7 +4002,7 @@ static uint32_t _rx_offset_cal_updn(uint32_t code)
        const uint32_t CODE_MAX = 0x40;
        uint32_t tmp;
 
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
                if (code == 0)
                        tmp = (1U << 6) | (CODE_MAX - 1);
                else if (code <= 0x20)
@@ -4117,10 +4116,10 @@ static uint32_t rx_offset_cal_hw(void)
                        for (slice = 0; slice < SLICE_CNT; slice++) {
                                tmp = tmp_ach_as[ch][slice];
                                tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f);
-                               if (((Prr_Product == PRR_PRODUCT_H3)
-                                    && (Prr_Cut > PRR_PRODUCT_11))
-                                   || (Prr_Product == PRR_PRODUCT_M3N)
-                                   || (Prr_Product == PRR_PRODUCT_V3H)) {
+                               if (((prr_product == PRR_PRODUCT_H3)
+                                    && (prr_cut > PRR_PRODUCT_11))
+                                   || (prr_product == PRR_PRODUCT_M3N)
+                                   || (prr_product == PRR_PRODUCT_V3H)) {
                                        if (tmp != 0x3E)
                                                complete = 0;
                                } else {
@@ -4222,60 +4221,61 @@ static void adjust_wpath_latency(void)
 int32_t rcar_dram_init(void)
 {
        uint32_t ch, cs;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t bus_mbps, bus_mbpsdiv;
        uint32_t tmp_tccd;
        uint32_t failcount;
+       uint32_t cnf_boardtype;
 
        /***********************************************************************
        Thermal sensor setting
        ***********************************************************************/
-       dataL = mmio_read_32(CPG_MSTPSR5);
-       if (dataL & BIT(22)) {  /*  case THS/TSC Standby */
-               dataL &= ~(BIT(22));
-               cpg_write_32(CPG_SMSTPCR5, dataL);
+       data_l = mmio_read_32(CPG_MSTPSR5);
+       if (data_l & BIT(22)) { /*  case THS/TSC Standby */
+               data_l &= ~(BIT(22));
+               cpg_write_32(CPG_SMSTPCR5, data_l);
                while ((BIT(22)) & mmio_read_32(CPG_MSTPSR5));  /*  wait bit=0 */
        }
 
        /* THCTR Bit6: PONM=0 , Bit0: THSST=0   */
-       dataL = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
-       mmio_write_32(THS1_THCTR, dataL);
+       data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
+       mmio_write_32(THS1_THCTR, data_l);
 
        /***********************************************************************
        Judge product and cut
        ***********************************************************************/
 #ifdef RCAR_DDR_FIXED_LSI_TYPE
 #if (RCAR_LSI == RCAR_AUTO)
-       Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
-       Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+       prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+       prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
 #else /* RCAR_LSI */
 #ifndef RCAR_LSI_CUT
-       Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+       prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
 #endif /* RCAR_LSI_CUT */
 #endif /* RCAR_LSI */
 #else /* RCAR_DDR_FIXED_LSI_TYPE */
-       Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
-       Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+       prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+       prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
 #endif /* RCAR_DDR_FIXED_LSI_TYPE */
 
-       if (Prr_Product == PRR_PRODUCT_H3) {
-               if (Prr_Cut <= PRR_PRODUCT_11) {
-                       pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[0][0];
+       if (prr_product == PRR_PRODUCT_H3) {
+               if (prr_cut <= PRR_PRODUCT_11) {
+                       p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[0][0];
                } else {
-                       pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[2][0];
+                       p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[2][0];
                }
-       } else if (Prr_Product == PRR_PRODUCT_M3) {
-               pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[1][0];
-       } else if ((Prr_Product == PRR_PRODUCT_M3N)
-                  || (Prr_Product == PRR_PRODUCT_V3H)) {
-               pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[3][0];
+       } else if (prr_product == PRR_PRODUCT_M3) {
+               p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[1][0];
+       } else if ((prr_product == PRR_PRODUCT_M3N)
+                  || (prr_product == PRR_PRODUCT_V3H)) {
+               p_ddr_regdef_tbl = (const uint32_t *)&DDR_REGDEF_TBL[3][0];
        } else {
                FATAL_MSG("BL2: DDR:Unknown Product\n");
                return 0xff;
        }
 
-       if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-           || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
+       if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
+           || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
                /* non : H3 Ver.1.x/M3-W Ver.1.x not support */
        } else {
                mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
@@ -4284,26 +4284,26 @@ int32_t rcar_dram_init(void)
        /***********************************************************************
        Judge board type
        ***********************************************************************/
-       _cnf_BOARDTYPE = boardcnf_get_brd_type();
-       if (_cnf_BOARDTYPE >= BOARDNUM) {
+       cnf_boardtype = boardcnf_get_brd_type();
+       if (cnf_boardtype >= BOARDNUM) {
                FATAL_MSG("BL2: DDR:Unknown Board\n");
                return 0xff;
        }
-       Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
+       board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype];
 
 /* RCAR_DRAM_SPLIT_2CH           (2U) */
 #if RCAR_DRAM_SPLIT == 2
        /***********************************************************************
        H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split
        ***********************************************************************/
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Boardcnf->phyvalid == 0x05)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) {
                mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006);
                ddr_phyvalid = 0x03;
        } else {
-               ddr_phyvalid = Boardcnf->phyvalid;
+               ddr_phyvalid = board_cnf->phyvalid;
        }
 #else /* RCAR_DRAM_SPLIT_2CH */
-       ddr_phyvalid = Boardcnf->phyvalid;
+       ddr_phyvalid = board_cnf->phyvalid;
 #endif /* RCAR_DRAM_SPLIT_2CH */
 
        max_density = 0;
@@ -4318,15 +4318,15 @@ int32_t rcar_dram_init(void)
 
        foreach_vch(ch) {
                for (cs = 0; cs < CS_CNT; cs++) {
-                       dataL = Boardcnf->ch[ch].ddr_density[cs];
-                       ddr_density[ch][cs] = dataL;
+                       data_l = board_cnf->ch[ch].ddr_density[cs];
+                       ddr_density[ch][cs] = data_l;
 
-                       if (dataL == 0xff)
+                       if (data_l == 0xff)
                                continue;
-                       if (dataL > max_density)
-                               max_density = dataL;
-                       if ((cs == 1) && (Prr_Product == PRR_PRODUCT_H3)
-                           && (Prr_Cut <= PRR_PRODUCT_11))
+                       if (data_l > max_density)
+                               max_density = data_l;
+                       if ((cs == 1) && (prr_product == PRR_PRODUCT_H3)
+                           && (prr_cut <= PRR_PRODUCT_11))
                                continue;
                        ch_have_this_cs[cs] |= (1U << ch);
                }
@@ -4335,7 +4335,7 @@ int32_t rcar_dram_init(void)
        /***********************************************************************
        Judge board clock frequency (in MHz)
        ***********************************************************************/
-       boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv);
+       boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv);
        if ((brd_clk / brd_clkdiv) > 25) {
                brd_clkdiva = 1;
        } else {
@@ -4345,7 +4345,7 @@ int32_t rcar_dram_init(void)
        /***********************************************************************
        Judge ddr operating frequency clock(in Mbps)
        ***********************************************************************/
-       boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv);
+       boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv);
 
        ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1));
 
@@ -4355,10 +4355,10 @@ int32_t rcar_dram_init(void)
        /***********************************************************************
        Adjust tccd
        ***********************************************************************/
-       dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
+       data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
        bus_mbps = 0;
        bus_mbpsdiv = 0;
-       switch (dataL) {
+       switch (data_l) {
        case 0:
                bus_mbps = brd_clk * 0x60 * 2;
                bus_mbpsdiv = brd_clkdiv * 1;
@@ -4401,8 +4401,8 @@ int32_t rcar_dram_init(void)
        /***********************************************************************
        initialize DDR
        ***********************************************************************/
-       dataL = init_ddr();
-       if (dataL == ddr_phyvalid) {
+       data_l = init_ddr();
+       if (data_l == ddr_phyvalid) {
                failcount = 0;
        } else {
                failcount = 1;
@@ -4410,8 +4410,8 @@ int32_t rcar_dram_init(void)
 
        foreach_vch(ch)
            mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
-       if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
-           || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
+       if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
+           || ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
                /* non : H3 Ver.1.x/M3-W Ver.1.x not support */
        } else {
                mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
@@ -4427,7 +4427,7 @@ int32_t rcar_dram_init(void)
 void pvtcode_update(void)
 {
        uint32_t ch;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
        int32_t pvtp_tmp, pvtn_tmp;
 
@@ -4453,41 +4453,41 @@ void pvtcode_update(void)
                                          pvtn_init) / (pvtn_tmp) +
                            6 * pvtp_tmp + pvtp_init;
                }
-               if ((Prr_Product == PRR_PRODUCT_H3)
-                   && (Prr_Cut <= PRR_PRODUCT_11)) {
-                       dataL = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000);
+               if ((prr_product == PRR_PRODUCT_H3)
+                   && (prr_cut <= PRR_PRODUCT_11)) {
+                       data_l = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-                                        dataL | 0x00020000);
+                                        data_l | 0x00020000);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-                                        dataL);
+                                        data_l);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-                                        dataL);
+                                        data_l);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-                                        dataL);
+                                        data_l);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-                                        dataL);
+                                        data_l);
                } else {
-                       dataL = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
+                       data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
-                                        dataL | 0x00020000);
+                                        data_l | 0x00020000);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
-                                        dataL);
+                                        data_l);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
-                                        dataL);
+                                        data_l);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
-                                        dataL);
+                                        data_l);
                        reg_ddrphy_write(ch,
                                         ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
-                                        dataL);
+                                        data_l);
                }
        }
 }
@@ -4513,7 +4513,7 @@ void pvtcode_update2(void)
 void ddr_padcal_tcompensate_getinit(uint32_t override)
 {
        uint32_t ch;
-       uint32_t dataL;
+       uint32_t data_l;
        uint32_t pvtp, pvtn;
 
        tcal.init_temp = 0;
@@ -4528,13 +4528,13 @@ void ddr_padcal_tcompensate_getinit(uint32_t override)
        }
 
        if (!override) {
-               dataL = mmio_read_32(THS1_TEMP);
-               if (dataL < 2800) {
+               data_l = mmio_read_32(THS1_TEMP);
+               if (data_l < 2800) {
                        tcal.init_temp =
-                           (143 * (int32_t)dataL - 359000) / 1000;
+                           (143 * (int32_t)data_l - 359000) / 1000;
                } else {
                        tcal.init_temp =
-                           (121 * (int32_t)dataL - 296300) / 1000;
+                           (121 * (int32_t)data_l - 296300) / 1000;
                }
 
                foreach_vch(ch) {
@@ -4556,8 +4556,8 @@ void ddr_padcal_tcompensate_getinit(uint32_t override)
                        else
                                pvtn = 0;
 
-                       if ((Prr_Product == PRR_PRODUCT_H3)
-                           && (Prr_Cut <= PRR_PRODUCT_11)) {
+                       if ((prr_product == PRR_PRODUCT_H3)
+                           && (prr_cut <= PRR_PRODUCT_11)) {
                                tcal.init_cal[ch] =
                                    (tcal.
                                     init_cal[ch] & 0xfffff000) | (pvtn << 6) |
index 58c9a7a4ff14222f49ba5dd9bb94016532469016..cb3a482eb223faa0e600b4e5d2c5535771fb8aad 100644 (file)
@@ -1533,7 +1533,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
 {
        uint32_t md;
 
-       if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_10)) {
+       if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_10)) {
                *clk = 50;
                *div = 3;
        } else {
@@ -1599,7 +1599,7 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
 #define M3_SAMPLE_SS_E28        0xB866CC10, 0x3C231421
 #define M3_SAMPLE_SS_E32        0xB866CC10, 0x3C241421
 
-static const uint32_t TermcodeBySample[20][3] = {
+static const uint32_t termcode_by_sample[20][3] = {
        {M3_SAMPLE_TT_A84, 0x000158D5},
        {M3_SAMPLE_TT_A85, 0x00015955},
        {M3_SAMPLE_TT_A86, 0x00015955},
@@ -1701,8 +1701,8 @@ static uint32_t _board_judge(void)
        uint32_t brd;
 #if (RCAR_GEN3_ULCB == 1)
        /* Starter Kit */
-       if (Prr_Product == PRR_PRODUCT_H3) {
-               if (Prr_Cut <= PRR_PRODUCT_11) {
+       if (prr_product == PRR_PRODUCT_H3) {
+               if (prr_cut <= PRR_PRODUCT_11) {
                        /* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */
                        brd = 2;
                } else {
@@ -1713,7 +1713,7 @@ static uint32_t _board_judge(void)
                        brd = 8;
 #endif
                }
-       } else if (Prr_Product == PRR_PRODUCT_M3) {
+       } else if (prr_product == PRR_PRODUCT_M3) {
                /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
                brd = 3;
        } else {
@@ -1727,31 +1727,31 @@ static uint32_t _board_judge(void)
 
        /* RENESAS Eva-board */
        brd = 99;
-       if (Prr_Product == PRR_PRODUCT_V3H) {
+       if (prr_product == PRR_PRODUCT_V3H) {
                /* RENESAS Condor board */
                brd = 12;
        } else if (usb2_ovc_open) {
-               if (Prr_Product == PRR_PRODUCT_M3N) {
+               if (prr_product == PRR_PRODUCT_M3N) {
                        /* RENESAS Kriek board with M3-N */
                        brd = 10;
-               } else if (Prr_Product == PRR_PRODUCT_M3) {
+               } else if (prr_product == PRR_PRODUCT_M3) {
                        /* RENESAS Kriek board with M3-W */
                        brd = 1;
-               } else if ((Prr_Product == PRR_PRODUCT_H3)
-                          && (Prr_Cut <= PRR_PRODUCT_11)) {
+               } else if ((prr_product == PRR_PRODUCT_H3)
+                          && (prr_cut <= PRR_PRODUCT_11)) {
                        /* RENESAS Kriek board with PM3 */
                        brd = 13;
-               } else if ((Prr_Product == PRR_PRODUCT_H3)
-                          && (Prr_Cut > PRR_PRODUCT_20)) {
+               } else if ((prr_product == PRR_PRODUCT_H3)
+                          && (prr_cut > PRR_PRODUCT_20)) {
                        /* RENESAS Kriek board with H3N */
                        brd = 15;
                }
        } else {
-               if (Prr_Product == PRR_PRODUCT_H3) {
-                       if (Prr_Cut <= PRR_PRODUCT_11) {
+               if (prr_product == PRR_PRODUCT_H3) {
+                       if (prr_cut <= PRR_PRODUCT_11) {
                                /* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */
                                brd = 2;
-                       } else if (Prr_Cut < PRR_PRODUCT_30) {
+                       } else if (prr_cut < PRR_PRODUCT_30) {
                                /* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */
                                brd = 7;        //  8Gbit/1rank
                        } else {
@@ -1762,16 +1762,16 @@ static uint32_t _board_judge(void)
                                brd = 8;
 #endif
                        }
-               } else if (Prr_Product == PRR_PRODUCT_M3N) {
+               } else if (prr_product == PRR_PRODUCT_M3N) {
                        /* RENESAS SALVATOR-X (M3-N/SIP) */
                        brd = 11;
-               } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20)) {
+               } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_20)) {
                        /* RENESAS SALVATOR-X (M3-W/SIP) */
                        brd = 0;
-               } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
+               } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
                        /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */
                        brd = 19;
-               } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
+               } else if ((prr_product == PRR_PRODUCT_M3) && (prr_cut >= PRR_PRODUCT_30)) {
                        /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
                        brd = 18;
                }