clocksource: ARM sp804: allow clocksource name to be specified
authorRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 12 May 2011 11:08:23 +0000 (12:08 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 23 May 2011 17:04:53 +0000 (18:04 +0100)
This allows platforms to specify the clocksource name upon
registration, which is necessary should they wish to register more
than one sp804 clocksource.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/common/timer-sp.c
arch/arm/include/asm/hardware/timer-sp.h
arch/arm/mach-integrator/integrator_cp.c
arch/arm/mach-realview/core.c
arch/arm/mach-versatile/core.c
arch/arm/mach-vexpress/ct-ca9x4.c
arch/arm/mach-vexpress/v2m.c

index 445b05ee8511d1aa9371df4ed7e3e8b7470d4876..f6b9011744aaebe469a8137ad7b4c34d71cb8fa3 100644 (file)
@@ -32,7 +32,7 @@
 #define TIMER_FREQ_KHZ (1000)
 #define TIMER_RELOAD   (TIMER_FREQ_KHZ * 1000 / HZ)
 
-void __init sp804_clocksource_init(void __iomem *base)
+void __init sp804_clocksource_init(void __iomem *base, const char *name)
 {
        /* setup timer 0 as free-running clocksource */
        writel(0, base + TIMER_CTRL);
@@ -41,7 +41,7 @@ void __init sp804_clocksource_init(void __iomem *base)
        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
                base + TIMER_CTRL);
 
-       clocksource_mmio_init(base + TIMER_VALUE, "timer3",
+       clocksource_mmio_init(base + TIMER_VALUE, name,
                TIMER_FREQ_KHZ * 1000, 200, 32, clocksource_mmio_readl_down);
 }
 
index 21e75e30d497e3b4c282385e938733ba0588d440..11c386bbbf3631daf2ab2d2f9d7d463a36c0d838 100644 (file)
@@ -1,2 +1,2 @@
-void sp804_clocksource_init(void __iomem *);
+void sp804_clocksource_init(void __iomem *, const char *);
 void sp804_clockevents_init(void __iomem *, unsigned int);
index 9e3ce26023e87fc70fbdb947e677cee2e6a7006b..46fb7f580fef510508f2af2d3ddad168db580916 100644 (file)
@@ -476,7 +476,7 @@ static void __init intcp_timer_init(void)
        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 
-       sp804_clocksource_init(TIMER2_VA_BASE);
+       sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
        sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
 }
 
index 75dbc8791d05e5fea4df2da1407071a527f31c95..6356b5e2e111af7f63e67e220ff30052c0a6c54d 100644 (file)
@@ -545,7 +545,7 @@ void __init realview_timer_init(unsigned int timer_irq)
        writel(0, timer2_va_base + TIMER_CTRL);
        writel(0, timer3_va_base + TIMER_CTRL);
 
-       sp804_clocksource_init(timer3_va_base);
+       sp804_clocksource_init(timer3_va_base, "timer3");
        sp804_clockevents_init(timer0_va_base, timer_irq);
 }
 
index eb7ffa0ee8b544d77caf42cc542892413b055952..aad6d395be447fbe5df66ed404bc920a2afa11ab 100644 (file)
@@ -764,7 +764,7 @@ static void __init versatile_timer_init(void)
        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 
-       sp804_clocksource_init(TIMER3_VA_BASE);
+       sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
        sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
 }
 
index ebc22e759325a8b11efa731e49f6ea451cce8cfc..c833fd9505c5cd4c311b91882b7f94e94dff7fa2 100644 (file)
@@ -71,7 +71,7 @@ static void __init ct_ca9x4_timer_init(void)
        writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
        writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
 
-       sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
+       sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
        sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
 }
 
index ba46e8e0743713b4ddbfed79c2615600b8e37506..ccf1f899ac21b0eecd9f93785c553662bf45f12a 100644 (file)
@@ -65,7 +65,7 @@ static void __init v2m_timer_init(void)
        writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
        writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
 
-       sp804_clocksource_init(MMIO_P2V(V2M_TIMER1));
+       sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
        sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0);
 }