ARM: imx: Use INT_MEM_CLK_LPM as the bit name

Bit 17 of register CCM_CGPR is called INT_MEM_CLK_LPM as per the mx6
reference manual, so use this name instead.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index baf439dc22d8268d65bd269f508c968aae822046..cdbddfa2a42f5dd2abe43326c4d033f46a30f8d6 100644 (file)
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -139,7 +139,7 @@ void imx_anatop_init(void);
 void imx_anatop_pre_suspend(void);
 void imx_anatop_post_resume(void);
 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
-void imx6q_set_chicken_bit(void);
+void imx6q_set_int_mem_clk_lpm(void);
 
 void imx_cpu_die(unsigned int cpu);
 int imx_cpu_kill(unsigned int cpu);

diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index 23ddfb693b2d01f606612dbe8b7eaf146aad8da1..6bcae047904905696c3cb0fbe238f74b1e54100f 100644 (file)
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -68,8 +68,8 @@ int __init imx6q_cpuidle_init(void)
        /* Need to enable SCU standby for entering WAIT modes */
        imx_scu_standby_enable();
 
-       /* Set chicken bit to get a reliable WAIT mode support */
-       imx6q_set_chicken_bit();
+       /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
+       imx6q_set_int_mem_clk_lpm();
 
        return cpuidle_register(&imx6q_cpuidle_driver, NULL);
 }

diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index 7a9b98589db7260ea0c56deca6872b3667158c2a..30af3c0e1bf32b46df8e556f4b9d537b5bc2faef 100644 (file)
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -56,15 +56,15 @@
 #define BM_CLPCR_MASK_L2CC_IDLE                (0x1 << 27)
 
 #define CGPR                           0x64
-#define BM_CGPR_CHICKEN_BIT            (0x1 << 17)
+#define BM_CGPR_INT_MEM_CLK_LPM                (0x1 << 17)
 
 static void __iomem *ccm_base;
 
-void imx6q_set_chicken_bit(void)
+void imx6q_set_int_mem_clk_lpm(void)
 {
        u32 val = readl_relaxed(ccm_base + CGPR);
 
-       val |= BM_CGPR_CHICKEN_BIT;
+       val |= BM_CGPR_INT_MEM_CLK_LPM;
        writel_relaxed(val, ccm_base + CGPR);
 }