x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 00-1f, 30-3f, 60-7f)

Manually enable a 64GB 64-bit BAR so we have enough room for graphics
devices with large framebuffers.

Most BIOSes don't enable this for compatibility reasons.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>

diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index f2228b150faa69caf10bc40574897597e3cd686a..e59378bf37d94936683229cd8cafc846a488c0b9 100644 (file)
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -635,3 +635,88 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
+
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+
+#define AMD_141b_MMIO_BASE(x)  (0x80 + (x) * 0x8)
+#define AMD_141b_MMIO_BASE_RE_MASK             BIT(0)
+#define AMD_141b_MMIO_BASE_WE_MASK             BIT(1)
+#define AMD_141b_MMIO_BASE_MMIOBASE_MASK       GENMASK(31,8)
+
+#define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8)
+#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK     GENMASK(31,8)
+
+#define AMD_141b_MMIO_HIGH(x)  (0x180 + (x) * 0x4)
+#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK       GENMASK(7,0)
+#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT     16
+#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK      GENMASK(23,16)
+
+/*
+ * The PCI Firmware Spec, rev 3.2, notes that ACPI should optionally allow
+ * configuring host bridge windows using the _PRS and _SRS methods.
+ *
+ * But this is rarely implemented, so we manually enable a large 64bit BAR for
+ * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors
+ * here.
+ */
+static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
+{
+       unsigned i;
+       u32 base, limit, high;
+       struct resource *res, *conflict;
+
+       for (i = 0; i < 8; i++) {
+               pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base);
+               pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high);
+
+               /* Is this slot free? */
+               if (!(base & (AMD_141b_MMIO_BASE_RE_MASK |
+                             AMD_141b_MMIO_BASE_WE_MASK)))
+                       break;
+
+               base >>= 8;
+               base |= high << 24;
+
+               /* Abort if a slot already configures a 64bit BAR. */
+               if (base > 0x10000)
+                       return;
+       }
+       if (i == 8)
+               return;
+
+       res = kzalloc(sizeof(*res), GFP_KERNEL);
+       if (!res)
+               return;
+
+       res->name = "PCI Bus 0000:00";
+       res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
+               IORESOURCE_MEM_64 | IORESOURCE_WINDOW;
+       res->start = 0x100000000ull;
+       res->end = 0xfd00000000ull - 1;
+
+       /* Just grab the free area behind system memory for this */
+       while ((conflict = request_resource_conflict(&iomem_resource, res)))
+               res->start = conflict->end + 1;
+
+       dev_info(&dev->dev, "adding root bus resource %pR\n", res);
+
+       base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
+               AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
+       limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK;
+       high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) |
+               ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT)
+                & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK);
+
+       pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high);
+       pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit);
+       pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base);
+
+       pci_bus_add_resource(dev->bus, res, 0);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
+
+#endif