/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \
MT_MEMORY | MT_RO | MT_SECURE)
+#define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \
+ MT_MEMORY | MT_RO | MT_SECURE)
+
/*
* Table of regions for various BL stages to map using the MMU.
* This doesn't include TZRAM as the 'mem_layout' argument passed to
#ifdef IMAGE_BL1
static const mmap_region_t plat_qemu_mmap[] = {
MAP_FLASH0,
+ MAP_FLASH1,
MAP_SHARED_RAM,
MAP_DEVICE0,
#ifdef MAP_DEVICE1
#ifdef IMAGE_BL2
static const mmap_region_t plat_qemu_mmap[] = {
MAP_FLASH0,
+ MAP_FLASH1,
MAP_SHARED_RAM,
MAP_DEVICE0,
#ifdef MAP_DEVICE1
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#define MAX_MMAP_REGIONS 10
+#define MAX_MMAP_REGIONS 11
#define MAX_XLAT_TABLES 6
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
#define PLAT_QEMU_CONSOLE_BAUDRATE 115200
-#define QEMU_FLASH0_BASE 0x04000000
+#define QEMU_FLASH0_BASE 0x00000000
#define QEMU_FLASH0_SIZE 0x04000000
+#define QEMU_FLASH1_BASE 0x04000000
+#define QEMU_FLASH1_SIZE 0x04000000
-#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE
-#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE
+#define PLAT_QEMU_FIP_BASE QEMU_FLASH1_BASE
+#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH1_SIZE
#define DEVICE0_BASE 0x08000000
#define DEVICE0_SIZE 0x01000000
#define QEMU_FLASH1_BASE 0x10000000
#define QEMU_FLASH1_SIZE 0x10000000
-#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE
-#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE
+#define PLAT_QEMU_FIP_BASE 0x00008000
+#define PLAT_QEMU_FIP_MAX_SIZE 0x00020000
/* This is map from GIC_DIST up to last CPU (255) GIC_REDISTR */
#define DEVICE0_BASE 0x40000000