Watchdog: allow orion_wdt to be built for Dove
authorRussell King <rmk+kernel@arm.linux.org.uk>
Tue, 18 Jun 2013 16:19:32 +0000 (17:19 +0100)
committerWim Van Sebroeck <wim@iguana.be>
Thu, 11 Jul 2013 20:17:56 +0000 (22:17 +0200)
The watchdog infrastructure in Dove is no different from that in
Orion5x or Kirkwood, so let's enable it for Dove.  The only things
missing are a few register settings in Dove's bridge-regs.h.

Rather than duplicating the same register bit masks for the RSTOUTn_MASK
and BRIDGE_CAUSE registers, move the definitions into the watchdog
driver itself.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
arch/arm/mach-dove/include/mach/bridge-regs.h
arch/arm/mach-kirkwood/include/mach/bridge-regs.h
arch/arm/mach-orion5x/include/mach/bridge-regs.h
drivers/watchdog/Kconfig
drivers/watchdog/orion_wdt.c

index 99f259e8cf33133b73f2b9712746cf7ade80fcbb..5362df3df89f9b816f9db721e4188d3820d63e50 100644 (file)
@@ -26,6 +26,7 @@
 #define SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE + 0x010c)
 #define  SOFT_RESET            0x00000001
 
+#define BRIDGE_CAUSE           (BRIDGE_VIRT_BASE + 0x0110)
 #define  BRIDGE_INT_TIMER1_CLR (~0x0004)
 
 #define IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE + 0x0200)
index d4cbe5e81bb4dcac1e5048fb79e10a3b1ad83d18..91242c944d7aeefc7f62cc51dd93b30486390f2e 100644 (file)
 #define CPU_RESET              0x00000002
 
 #define RSTOUTn_MASK           (BRIDGE_VIRT_BASE + 0x0108)
-#define WDT_RESET_OUT_EN       0x00000002
 #define SOFT_RESET_OUT_EN      0x00000004
 
 #define SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET             0x00000001
 
 #define BRIDGE_CAUSE           (BRIDGE_VIRT_BASE + 0x0110)
-#define WDT_INT_REQ            0x0008
 
 #define BRIDGE_INT_TIMER1_CLR  (~0x0004)
 
index 461fd69a10ae58f7d7acd0672c95d9837b451d1a..f727d03f16885491dbe81dff36b74a90f6d1d874 100644 (file)
@@ -18,7 +18,6 @@
 #define CPU_CTRL               (ORION5X_BRIDGE_VIRT_BASE + 0x104)
 
 #define RSTOUTn_MASK           (ORION5X_BRIDGE_VIRT_BASE + 0x108)
-#define WDT_RESET_OUT_EN       0x0002
 
 #define CPU_SOFT_RESET         (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
 
@@ -26,8 +25,6 @@
 
 #define POWER_MNG_CTRL_REG     (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
 
-#define WDT_INT_REQ            0x0008
-
 #define BRIDGE_INT_TIMER1_CLR  (~0x0004)
 
 #define MAIN_IRQ_CAUSE         (ORION5X_BRIDGE_VIRT_BASE + 0x200)
index f17ffdb75bb0f3ceba524bd6562f50b1f1fe7f39..b69e4821d668f015236afefdbe7e776928c89069 100644 (file)
@@ -282,7 +282,7 @@ config DAVINCI_WATCHDOG
 
 config ORION_WATCHDOG
        tristate "Orion watchdog"
-       depends on ARCH_ORION5X || ARCH_KIRKWOOD
+       depends on ARCH_ORION5X || ARCH_KIRKWOOD || ARCH_DOVE
        select WATCHDOG_CORE
        help
          Say Y here if to include support for the watchdog timer
index da577980d390cbe5df8343f3de64240b4f04c528..4074244c71834f2b2648395437b95a95a7c9fe9b 100644 (file)
@@ -38,6 +38,9 @@
 #define WDT_IN_USE             0
 #define WDT_OK_TO_CLOSE                1
 
+#define WDT_RESET_OUT_EN       BIT(1)
+#define WDT_INT_REQ            BIT(3)
+
 static bool nowayout = WATCHDOG_NOWAYOUT;
 static int heartbeat = -1;             /* module parameter (seconds) */
 static unsigned int wdt_max_duration;  /* (seconds) */