fixed ethernet phy configuration for plu405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index 37b92fb65a8dd482a433e0a592c9e5ba33a4ed6a..59171f8f4c5cfbaf0fda5dcdb864ccbb5f320306 100644 (file)
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -215,12 +215,6 @@ int checkboard (void)
        }
 
        putc ('\n');
-
-       /*
-        * Disable sleep mode in LXT971
-        */
-       lxt971_no_sleep();
-
        return 0;
 }
 
@@ -292,3 +286,14 @@ void board_auto_update_show(int au_active)
        }
 }
 #endif
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+       /*
+        * Disable sleep mode in LXT971
+        */
+       lxt971_no_sleep();
+#endif
+}

diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index dd5d83168042f121c85a6c7938e2234bfabcb2d9..d02c39b28f96b4b88271f873b05a367fb5c6857c 100644 (file)
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -51,17 +51,13 @@
 
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
 
-#if 0 /* test-only */
 #define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
-#define CONFIG_PHY1_ADDR       1       /* PHY address                  */
-#else
-#define CONFIG_MII             1       /* MII PHY management           */
-#define CONFIG_PHY_ADDR                0       /* PHY address                  */
-#endif
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
 
 #define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/