le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
adev->gfx.config.double_offchip_lds_buf =
gfx_info->v24.gc_double_offchip_lds_buffer;
- adev->gfx.cu_info.wave_front_size = gfx_info->v24.gc_wave_size;
- adev->gfx.cu_info.max_waves_per_simd =
- le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
- adev->gfx.cu_info.max_scratch_slots_per_cu =
- gfx_info->v24.gc_max_scratch_slots_per_cu;
+ adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
+ adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
+ adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
return 0;
default:
uint8_t active_cu_per_sh;
uint8_t active_rb_per_se;
uint16_t gcgoldenoffset;
- uint32_t rm21_sram_vmin_value;
uint16_t gc_num_gprs;
uint16_t gc_gsprim_buff_depth;
uint16_t gc_parameter_cache_depth;
uint8_t gc_gs_table_depth;
uint8_t gc_double_offchip_lds_buffer;
uint8_t gc_max_scratch_slots_per_cu;
+ uint32_t sram_rm_fuses_val;
+ uint32_t sram_custom_rm_fuses_val;
};
/*