MIPS: Octeon: Handle Octeon II caches.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1664/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 0f9c488044d155aa0c9a7c262edfe6e1777d405e..16c4d256b76f3f7179e5a77b856bd3a7a3825a52 100644 (file)
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -181,10 +181,10 @@ static void __cpuinit probe_octeon(void)
        unsigned int config1;
        struct cpuinfo_mips *c = &current_cpu_data;
 
+       config1 = read_c0_config1();
        switch (c->cputype) {
        case CPU_CAVIUM_OCTEON:
        case CPU_CAVIUM_OCTEON_PLUS:
-               config1 = read_c0_config1();
                c->icache.linesz = 2 << ((config1 >> 19) & 7);
                c->icache.sets = 64 << ((config1 >> 22) & 7);
                c->icache.ways = 1 + ((config1 >> 16) & 7);
@@ -204,6 +204,20 @@ static void __cpuinit probe_octeon(void)
                c->options |= MIPS_CPU_PREFETCH;
                break;
 
+       case CPU_CAVIUM_OCTEON2:
+               c->icache.linesz = 2 << ((config1 >> 19) & 7);
+               c->icache.sets = 8;
+               c->icache.ways = 37;
+               c->icache.flags |= MIPS_CACHE_VTAG;
+               icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+
+               c->dcache.linesz = 128;
+               c->dcache.ways = 32;
+               c->dcache.sets = 8;
+               dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+               c->options |= MIPS_CPU_PREFETCH;
+               break;
+
        default:
                panic("Unsupported Cavium Networks CPU type\n");
                break;