powerpc/85xx: Refactor P2041RDB to use common p_corenet files

The P2041RDB has almost identical setup for TLB, LAWS, and PCI with
other P-Series CoreNet platforms.

The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the
CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the
TLB and LAW setup tables.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 79f9de262f3d5b82559faab103e6d2283cbecd32..b27f054dfef8425151bbd7cbaf9f057536cfb036 100644 (file)
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -54,6 +54,7 @@ COBJS-$(CONFIG_P4080DS)               += ics307_clk.o
 COBJS-$(CONFIG_P5020DS)                += ics307_clk.o
 
 # deal with common files for P-series corenet based devices
+SUBLIB-$(CONFIG_P2041RDB)      += p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P3041DS)       += p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P4080DS)       += p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P5020DS)       += p_corenet/libp_corenet.o

diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index 58f23c5a24a21bd9cbd52ec2f025fb40253b60f3..09ef5615d26e1db1b9599d89f945b68a05382d56 100644 (file)
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -35,7 +35,12 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
        SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
 #endif
+#ifdef PIXIS_BASE_PHYS
        SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CPLD_BASE_PHYS
+       SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
        /* Limit DCSR to 32M to access NPC Trace Buffer */
        SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),

diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 5e48d6c6352b310f3502395c3e484615008299d0..6a0026a2cf7b5a7955a79eb212d0f28f25bd28ce 100644 (file)
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -44,10 +44,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
                      MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
+#ifdef CPLD_BASE
+       SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+#endif
 
+#ifdef PIXIS_BASE
        SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 0, BOOKE_PAGESZ_4K, 0),
+#endif
 
        /* TLB 1 */
        /* *I*** - Covers boot page */

diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile
index b4cb83e5bf9774e6c6b1a16a2327b0fc3e70fe35..8d4da3a384207eeb7b4e0c01ac17dac4e26daa7c 100644 (file)
--- a/board/freescale/p2041rdb/Makefile
+++ b/board/freescale/p2041rdb/Makefile
@@ -30,9 +30,6 @@ COBJS-y       += $(BOARD).o
 COBJS-y += cpld.o
 COBJS-y        += ddr.o
 COBJS-y        += eth.o
-COBJS-y        += law.o
-COBJS-y        += tlb.o
-COBJS-$(CONFIG_PCI) += pci.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))

diff --git a/board/freescale/p2041rdb/law.c b/board/freescale/p2041rdb/law.c
deleted file mode 100644 (file)
index 127a478..0000000
--- a/board/freescale/p2041rdb/law.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-       SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-       SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
-       SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
-       SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-       SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);

diff --git a/board/freescale/p2041rdb/pci.c b/board/freescale/p2041rdb/pci.c
deleted file mode 100644 (file)
index 1ab4cdf..0000000
--- a/board/freescale/p2041rdb/pci.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-       fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-       FT_FSL_PCI_SETUP;
-}

diff --git a/board/freescale/p2041rdb/tlb.c b/board/freescale/p2041rdb/tlb.c
deleted file mode 100644 (file)
index 1ee0493..0000000
--- a/board/freescale/p2041rdb/tlb.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-       /* TLB 0 - for temp stack in cache */
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-                     CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-                     MAS3_SW|MAS3_SR, 0,
-                     0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-                     MAS3_SW|MAS3_SR, 0,
-                     0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-                     MAS3_SW|MAS3_SR, 0,
-                     0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-                     MAS3_SW|MAS3_SR, 0,
-                     0, 0, BOOKE_PAGESZ_4K, 0),
-
-       SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
-                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 0, BOOKE_PAGESZ_4K, 0),
-
-       /* TLB 1 */
-       /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-       /*
-        * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
-        * SRAM is at 0xfff00000, it covered the 0xfffff000.
-        */
-       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 0, BOOKE_PAGESZ_1M, 1),
-#else
-       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-       /* *I*G* - CCSRBAR */
-       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 1, BOOKE_PAGESZ_16M, 1),
-
-       /* *I*G* - Flash, localbus */
-       /* This will be changed to *I*G* after relocation to RAM. */
-       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-                     MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-                     0, 2, BOOKE_PAGESZ_256M, 1),
-
-       /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 3, BOOKE_PAGESZ_1G, 1),
-
-       /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
-                     CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
-                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 4, BOOKE_PAGESZ_256M, 1),
-
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
-                     CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
-                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 5, BOOKE_PAGESZ_256M, 1),
-
-       /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 6, BOOKE_PAGESZ_256K, 1),
-
-       /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-                     MAS3_SW|MAS3_SR, 0,
-                     0, 9, BOOKE_PAGESZ_1M, 1),
-       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
-                     CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
-                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-                     MAS3_SW|MAS3_SR, 0,
-                     0, 11, BOOKE_PAGESZ_1M, 1),
-       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
-                     CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
-                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 12, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-       SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 13, BOOKE_PAGESZ_4M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);