85xx: Using proper I2C source clock divider for MPC8544

The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being
bit 26, instead it should be bit 28.  This caused in incorrect
interpretation of the i2c_clk which is the same as the SEC clk on
MPC8544.  The SEC clk is controlled by cfg_sec_freq that is reported
in PORDEVSR2.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 50c9ddefd22d9bb7a762145ce15c5a1a082deacd..6c81c3996314e1eac5614d5744960c6976578709 100644 (file)
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1579,7 +1579,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_RIO_DEV_ID    0x00000007
        uint    pordbgmsr;      /* 0xe0010 - POR debug mode status register */
        uint    pordevsr2;      /* 0xe0014 - POR I/O device status regsiter 2 */
-#define MPC85xx_PORDEVSR2_SEC_CFG      0x00000020
+#define MPC85xx_PORDEVSR2_SEC_CFG      0x00000080
        char    res1[8];
        uint    gpporcr;        /* 0xe0020 - General-purpose POR configuration register */
        char    res2[12];