if (!(cx18_debug & CX18_DBGFLG_INFO))
return;
- for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
+ for (i = 0; i <= CX18_MAX_MMIO_WR_RETRIES; i++)
CX18_DEBUG_INFO("retried_write[%d] = %d\n", i,
atomic_read(&cx->mmio_stats.retried_write[i]));
- for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
+ for (i = 0; i <= CX18_MAX_MMIO_RD_RETRIES; i++)
CX18_DEBUG_INFO("retried_read[%d] = %d\n", i,
atomic_read(&cx->mmio_stats.retried_read[i]));
return;
void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
{
int i;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_raw_writel_noretry(cx, val, addr);
if (val == cx18_raw_readl_noretry(cx, addr))
break;
{
int i;
u32 val;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_raw_readl_noretry(cx, addr);
if (val != 0xffffffff) /* PCI bus read error */
break;
{
int i;
u16 val;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_raw_readw_noretry(cx, addr);
if (val != 0xffff) /* PCI bus read error */
break;
void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
{
int i;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writel_noretry(cx, val, addr);
if (val == cx18_readl_noretry(cx, addr))
break;
{
int i;
eval &= mask;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writel_noretry(cx, val, addr);
if (eval == (cx18_readl_noretry(cx, addr) & mask))
break;
void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
{
int i;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writew_noretry(cx, val, addr);
if (val == cx18_readw_noretry(cx, addr))
break;
void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr)
{
int i;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
cx18_writeb_noretry(cx, val, addr);
if (val == cx18_readb_noretry(cx, addr))
break;
{
int i;
u32 val;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_readl_noretry(cx, addr);
if (val != 0xffffffff) /* PCI bus read error */
break;
{
int i;
u16 val;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_readw_noretry(cx, addr);
if (val != 0xffff) /* PCI bus read error */
break;
{
int i;
u8 val;
- for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
+ for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
val = cx18_readb_noretry(cx, addr);
if (val != 0xff) /* PCI bus read error */
break;
static inline
void cx18_log_write_retries(struct cx18 *cx, int i, const void __iomem *addr)
{
- if (i > CX18_MAX_MMIO_RETRIES)
- i = CX18_MAX_MMIO_RETRIES;
+ if (i > CX18_MAX_MMIO_WR_RETRIES)
+ i = CX18_MAX_MMIO_WR_RETRIES;
atomic_inc(&cx->mmio_stats.retried_write[i]);
return;
}
static inline
void cx18_log_read_retries(struct cx18 *cx, int i, const void __iomem *addr)
{
- if (i > CX18_MAX_MMIO_RETRIES)
- i = CX18_MAX_MMIO_RETRIES;
+ if (i > CX18_MAX_MMIO_RD_RETRIES)
+ i = CX18_MAX_MMIO_RD_RETRIES;
atomic_inc(&cx->mmio_stats.retried_read[i]);
return;
}