New DRM core in 3.6 needs these in order to detect the maximum
link speed of the underlying bus.
This backports:
commit
cdcac9cd7741af2c2b9255cbf060f772596907bb
Author: Dave Airlie <airlied@redhat.com>
Date: Wed Jun 27 08:35:52 2012 +0100
pci_regs: define LNKSTA2 pcie cap + bits.
We need these for detecting the max link speed for drm drivers.
Acked-by: Bjorn Helgaas <bhelgass@google.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
[root@ozan linux-2.6]# git describe --contains
cdcac9cd
v3.6-rc1~83^2~26
Trying kernel 3.5.0-030500-generic [OK]
Trying kernel 3.4.4-030404-generic [OK]
Trying kernel 3.3.7-030307-generic [OK]
Trying kernel 3.2.2-030202-generic [OK]
Trying kernel 3.1.10-030110-generic [OK]
Trying kernel 3.0.18-030018-generic [OK]
Trying kernel 2.6.39-
02063904-generic [OK]
Trying kernel 2.6.38-
02063808-generic [OK]
Trying kernel 2.6.37-
02063706-generic [OK]
Trying kernel 2.6.36-
02063604-generic [OK]
Trying kernel 2.6.35-
02063512-generic [OK]
Trying kernel 2.6.34-
02063410-generic [OK]
Trying kernel 2.6.33-
02063305-generic [OK]
Trying kernel 2.6.32-
02063255-generic [OK]
Trying kernel 2.6.31-
02063113-generic [OK]
Trying kernel 2.6.30-
02063010-generic [OK]
Trying kernel 2.6.29-
02062906-generic [OK]
Trying kernel 2.6.28-
02062810-generic [OK]
Trying kernel 2.6.27-020627-generic [OK]
Trying kernel 2.6.26-020626-generic [OK]
Trying kernel 2.6.25-020625-generic [OK]
Trying kernel 2.6.24-020624-generic [OK]
Signed-off-by: Ozan Çağlayan <ozancag@gmail.com>
Signed-off-by: Luis R. Rodriguez <mcgrof@frijolero.org>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
+/**
+ * Backports
+ *
+ * commit cdcac9cd7741af2c2b9255cbf060f772596907bb
+ * Author: Dave Airlie <airlied@redhat.com>
+ * Date: Wed Jun 27 08:35:52 2012 +0100
+ *
+ * pci_regs: define LNKSTA2 pcie cap + bits.
+ *
+ * We need these for detecting the max link speed for drm drivers.
+ *
+ * Acked-by: Bjorn Helgaas <bhelgass@google.com>
+ * Signed-off-by: Dave Airlie <airlied@redhat.com>
+ */
+
+#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
+#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
+#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
+#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */
+#define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */
+
#include <net/genetlink.h>
#include <linux/etherdevice.h>