--- /dev/null
+/*
+ * Device Tree file for the Edimax BR-6478AC V2
+ * based on Linksys E1700
+ *
+ * Copyright (C) 2016 Rohan Murch <rohan.murch@gmail.com>
+ * Copyright (C) 2016 Hans Ulli Kroll <ulli.kroll@googlemail.com>
+ * Copyright (C) 2017 James McKenzie <openwrt@madingley.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/include/ "mt7620a.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ compatible = "edimax,br-6478ac-v2", "ralink,mt7620a-soc";
+ model = "Edimax BR-6478AC v2";
+
+ aliases {
+ led-status = &led_power;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ poll-interval = <20>;
+
+ reset_wps {
+ label = "reset_wps";
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_power: power {
+ label = "br-6478ac-v2:white:power";
+ gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+ };
+ wan {
+ label = "br-6478ac-v2:blue:wan";
+ gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ };
+ wlan {
+ label = "br-6478ac-v2:blue:wlan";
+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+ };
+ usb {
+ label = "br-6478ac-v2:blue:usb";
+ gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+
+ gpio_export {
+ compatible = "gpio-export";
+ #size-cells = <0>;
+ usb-power {
+ gpio-export,name="usb-power";
+ gpio-export,output=<1>;
+ gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* pin45 */
+ };
+ };
+};
+
+
+&gpio2 {
+ status = "okay";
+};
+
+
+&spi0 {
+ status = "okay";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0 0>;
+ linux,modalias = "m25p80", "mx25l6405d";
+ spi-max-frequency = <10000000>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
+
+ partition@30000 {
+ label = "u-boot-env";
+ reg = <0x30000 0x10000>;
+ read-only;
+ };
+
+ factory: partition@40000 {
+ label = "factory";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "cimage";
+ reg = <0x50000 0x20000>;
+ read-only;
+ };
+
+ partition@70000 {
+ label = "firmware";
+ reg = <0x00070000 0x00790000>;
+ };
+ };
+};
+
+&pinctrl {
+ state_default: pinctrl0 {
+ gpio {
+ ralink,group = "i2c", "uartf", "wdt", "pa",
+ "ephy", "nd_sd", "wled";
+ ralink,function = "gpio";
+ };
+ };
+};
+
+ðernet {
+ status = "okay";
+ mtd-mac-address = <&factory 0x4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
+ mediatek,portmap = "wllll";
+
+ port@5 {
+ status = "okay";
+ mediatek,fixed-link = <1000 1 1 1>;
+ phy-mode = "rgmii";
+ };
+
+ mdio-bus {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ phy-mode = "rgmii";
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ phy-mode = "rgmii";
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ phy-mode = "rgmii";
+ };
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ phy-mode = "rgmii";
+ };
+
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ phy-mode = "rgmii";
+ };
+
+ phy1f: ethernet-phy@1f {
+ reg = <0x1f>;
+ phy-mode = "rgmii";
+ };
+ };
+};
+
+&gsw {
+ mediatek,port4 = "gmac";
+ mediatek,mt7530 = <1>;
+};
+
+
+&wmac {
+ ralink,mtd-eeprom = <&factory 0>;
+};
+
+&pcie {
+ status = "okay";
+
+ pcie-bridge {
+ mt76@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ device_type = "pci";
+ mediatek,mtd-eeprom = <&factory 0x8000>;
+ mediatek,2ghz = <0>;
+ };
+ };
+
+};
+
+&ehci {
+ status = "okay";
+};
+
+&ohci {
+ status = "okay";
+};
projects / openwrt / staging / ynezz.git / commitdiff