lantiq: fix pci driver once again
authorMartin Schiller <ms@dev.tdt.de>
Mon, 17 Jun 2024 06:27:59 +0000 (08:27 +0200)
committerRobert Marko <robimarko@gmail.com>
Thu, 20 Jun 2024 07:56:50 +0000 (09:56 +0200)
In my previous attempt to solve the PCI problems for the lantiq targets,
I did not pay attention to the fact that the original accesses to the
GPIO took place in RAW mode. As a result, the polarity defined in the
device trees (apart from the initial value) was irrelevant.

In addition, the expected name of the GPIO in the dts has changed due to
the upstream change and therefore no RESET is currently performed.

As discussed in [1] on the linux-mips mailing list, we will now adapt
the dts files accordingly instead of patching the driver:

- dts property will be renamed to "reset-gpios"
- Polarity is set to "GPIO_ACTIVE_LOW".

I have verified this with a TP-Link TD-W8980. The PCI device is now
recognized by the system.

[1] https://patchwork.kernel.org/project/linux-mips/patch/20240607090400.1816612-1-ms@dev.tdt.de/

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Tested-by: Aleksander Jan Bajkowski <olek2@wp.pl> # Tested on AVM 7330 (ar9)
Link: https://github.com/openwrt/openwrt/pull/15731
Signed-off-by: Robert Marko <robimarko@gmail.com>
28 files changed:
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vrv9510kwac23.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi
target/linux/lantiq/patches-6.1/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch [deleted file]
target/linux/lantiq/patches-6.6/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch [deleted file]

index c6f0454d10fdf3be40130cc20b996f3521304469..9ea6c3929cb7c7b801623336b37265daccb89af5 100644 (file)
        pinctrl-names = "default";
 
        req-mask = <0xf>;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@0,0 {
                compatible = "pci0,0";
index 96adb0ddad2a1c3a8f7869c67349c00cc9a0707a..953a8ccbf740acb51e4f04e3c1fa31a863321365 100644 (file)
                    <&pci_req3_pins>, <&pci_req4_pins>;
 
        req-mask = <0xf>;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@0,0 {
                compatible = "pci0,0";
index fdc3c3037b35bfb87f032d9404e4f59b94602062..c76357279ef4cc47705585e8b6d62b4f95e2d63e 100644 (file)
        pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;
        pinctrl-names = "default";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@7000 {
                reg = <0x7000 0 0 0 0>;
index 8409e079431b0f29751ec8d6c782039a54e33c01..9108db1bd6f8bccc1fc4c4b47812f2c026a2b3f5 100644 (file)
        pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;
        pinctrl-names = "default";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@168c,0029 {
                compatible = "pci168c,0029";
index a6a8b93a2454b200cd77efa32cf085332195d89c..e988da14e7f5692030664a1721b5a8d105bce473 100644 (file)
                0x7800 0 0 2 &icu0 66
                0x7800 0 0 3 &icu0 66
        >;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        req-mask = <0x7>;
 };
 
index 45ae57856745b570bee7dc5764addcf9c4955e7f..45162435bf7fbf17720033d5969bbf2c5720f405 100644 (file)
                    <&pci_req1_pins>, <&pci_req2_pins>;
        pinctrl-names = "default";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        req-mask = <0xf>;
 };
 
index 55ac2038c85f38e26f87b50257955ced8f1b22f5..9866b91fb41e13cbd5b95dac2e6f938e087c3ea9 100644 (file)
 &pci0 {
        status = "okay";
        lantiq,external-clock;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        req-mask = <0xf>;
 };
 
index 487a107ff278629c78a89f497b174566fb91b9d1..3b9ee0fcb4dbf4c9fd36b5f88e990333e79b523a 100644 (file)
        pinctrl-names = "default";
 
        lantiq,external-clock;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
 &usb_phy {
index e781be33910fd06b90ef068aa25ed8ed3e8d6856..03f7afcd19157d903e002b94ce826c750dd85401 100644 (file)
        pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;
        pinctrl-names = "default";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
 /* #define ARV4525PW_RELAY             31 */
index 1fd192d221a0143ac8608538b3f8b269d8091a0f..42c50e1e82296dd95c1ba33240805e76970bf332 100644 (file)
        pinctrl-names = "default";
 
        lantiq,external-clock;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
 &usb_phy {
index 1c1fa2f77dd833c27cfb7392e19de3e58a82e53e..f4fd7397d3f0158057cc89cf9c60f5d48b4f14f1 100644 (file)
        pinctrl-names = "default";
 
        lantiq,external-clock;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@1814,3592 {
                compatible = "pci1814,3592";
index 237188137b7cd11226d4d08d7e108d348fb25d3a..4c9c9e524d5ea22d262be1b489f3da2defb32908 100644 (file)
                0x7800 0 0 2 &icu0 135
                0x7800 0 0 3 &icu0 135
        >;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        req-mask = <0x3>;
 
        wifi@1814,3592 {
index fe642b643fb1d413ac05bc5c3abf7c91463fa3a1..dc4f6d302185d2343ad32fc28ff02975b03a7b49 100644 (file)
        pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;
        pinctrl-names = "default";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        lantiq,external-clock;
        req-mask = <0xf>;
 
index 1f8db69f3096d030b1f1e4b1e053fbc2f257e64b..6b7c5f9b054d23e9fed9ee673104854f36a106b1 100644 (file)
        pinctrl-names = "default";
 
        lantiq,external-clock;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        req-mask = <0xf>;
 
        wifi@0,0 {
index c5362a4d4891157e2d7bd2623f469a2b255528a2..17b04846f93891a7d6c3a29cc3294bb7fe5e8311 100644 (file)
        pinctrl-names = "default";
 
        lantiq,external-clock;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        interrupt-map = <0x7000 0 0 1 &icu0 135>;
        req-mask = <0x3>;
 
index 9522e57f5e4bd531c71765c4e41b3638d81bfdbd..1d8e521370110dd23925e53aca3430c93aa4b466 100644 (file)
                0x7800 0 0 2 &icu0 135
                0x7800 0 0 3 &icu0 135
        >;
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        req-mask = <0x3>;
 
        wifi@1814,3592 {
index 46b98c8c20b9fe4f5e02e76e546a538a1b89315d..768e13c627362f8201e942c7b6ae9c533cfe8908 100644 (file)
        pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;
        pinctrl-names = "default";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@168c,0029 {
                compatible = "pci168c,0029";
index 4a422c6f4af6a72d227595219ad609ea0d43bb47..a1f7af075c9209c157ca58a57a556aac68532a80 100644 (file)
        pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;
        pinctrl-names = "default";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@168c,0027 {
                compatible = "pci168c,0027";
index 5b57f70c9da8adbebff0c12324ee7f412715319c..3296a44b4efba6b9ad3e06ae592e06a93dd737f3 100644 (file)
@@ -99,7 +99,7 @@
 
 &pci0 {
        status = "okay";
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
 &usb_phy {
index 6b2aa2b974cb40e425f86646f2ced856d785e9fc..daf115088bdd5a952e0b683fd27350939c476b02 100644 (file)
 
 &pci0 {
        status = "okay";
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@1814,3592 {
                compatible = "pci1814,3592";
index 5056f3c7091f53fffcb773574510740553a97ddc..52501b4d2a92ffd60d8c37a44cb6a63ebb5c4654 100644 (file)
 
 &pci0 {
        status = "okay";
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@1814,3091 {
                compatible = "pci1814,3091";
index 9d9f981e951cb1ceb1636e5cfa822871267bb688..0fb7347d736704127dda6732598e897614c48709 100644 (file)
        pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;
        pinctrl-names = "default";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
 &pcie0 {
index 0ee2cf74d1f146e2b9b290fa1d025119b6d08629..cb6cb74af82aa8470e2da50ab5b14d8c3b4b4186 100644 (file)
 
 &pci0 {
        status = "okay";
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
        wifi@168c,002d {
                compatible = "pci168c,002d";
index 1b8d2c6a0f620baa82d68f011b1e8cf2a0eac07a..8221e0d5c5200fce12909f3dc9cbb095421a91dc 100644 (file)
@@ -25,5 +25,5 @@
 &pci0 {
        status = "okay";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
index 0fc54677db9f7effdc85e42acc079b0d848c36ca..34b58cd0b419d8a92d103c240f38da0e140ff170 100644 (file)
 
 &pci0 {
        status = "okay";
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
 &spi {
index ac536e7a7a269e1791fb22ffa4b50514ea8cbc62..2b8dc285cbd03bf0829791ae7057ed77ca718637 100644 (file)
        pinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;
        pinctrl-names = "default";
 
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+       reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
 &stp {
diff --git a/target/linux/lantiq/patches-6.1/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch b/target/linux/lantiq/patches-6.1/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch
deleted file mode 100644 (file)
index 6b70f8b..0000000
+++ /dev/null
@@ -1,62 +0,0 @@
-From f038380835033e376d89c72516f087254792bbad Mon Sep 17 00:00:00 2001
-From: Martin Schiller <ms@dev.tdt.de>
-Date: Mon, 6 May 2024 09:41:42 +0200
-Subject: [PATCH] MIPS: pci: lantiq: restore reset gpio polarity
-
-Commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") not
-only switched to the gpiod API, but also inverted / changed the polarity
-of the GPIO.
-
-According to the PCI specification, the RST# pin is an active-low
-signal. However, most of the device trees that have been widely used for
-a long time (mainly in the openWrt project) define this GPIO as
-active-high and the old driver code inverted the signal internally.
-
-Apparently there are actually boards where the reset gpio must be
-operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH
-flag for initialization. Instead, we must explicitly set the gpio to
-value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that
-may have been set.
-
-In order to remain compatible with all these existing device trees, we
-should therefore keep the logic as it was before the commit.
-
-Fixes: 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API")
-Cc: stable@vger.kernel.org
-Signed-off-by: Martin Schiller <ms@dev.tdt.de>
----
- arch/mips/pci/pci-lantiq.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/mips/pci/pci-lantiq.c
-+++ b/arch/mips/pci/pci-lantiq.c
-@@ -124,14 +124,14 @@ static int ltq_pci_startup(struct platfo
-               clk_disable(clk_external);
-       /* setup reset gpio used by pci */
--      reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
--                                           GPIOD_OUT_LOW);
-+      reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS);
-       error = PTR_ERR_OR_ZERO(reset_gpio);
-       if (error) {
-               dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
-               return error;
-       }
-       gpiod_set_consumer_name(reset_gpio, "pci_reset");
-+      gpiod_direction_output(reset_gpio, 1);
-       /* enable auto-switching between PCI and EBU */
-       ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
-@@ -194,10 +194,10 @@ static int ltq_pci_startup(struct platfo
-       /* toggle reset pin */
-       if (reset_gpio) {
--              gpiod_set_value_cansleep(reset_gpio, 1);
-+              gpiod_set_value_cansleep(reset_gpio, 0);
-               wmb();
-               mdelay(1);
--              gpiod_set_value_cansleep(reset_gpio, 0);
-+              gpiod_set_value_cansleep(reset_gpio, 1);
-       }
-       return 0;
- }
diff --git a/target/linux/lantiq/patches-6.6/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch b/target/linux/lantiq/patches-6.6/0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch
deleted file mode 100644 (file)
index 6b70f8b..0000000
+++ /dev/null
@@ -1,62 +0,0 @@
-From f038380835033e376d89c72516f087254792bbad Mon Sep 17 00:00:00 2001
-From: Martin Schiller <ms@dev.tdt.de>
-Date: Mon, 6 May 2024 09:41:42 +0200
-Subject: [PATCH] MIPS: pci: lantiq: restore reset gpio polarity
-
-Commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") not
-only switched to the gpiod API, but also inverted / changed the polarity
-of the GPIO.
-
-According to the PCI specification, the RST# pin is an active-low
-signal. However, most of the device trees that have been widely used for
-a long time (mainly in the openWrt project) define this GPIO as
-active-high and the old driver code inverted the signal internally.
-
-Apparently there are actually boards where the reset gpio must be
-operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH
-flag for initialization. Instead, we must explicitly set the gpio to
-value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that
-may have been set.
-
-In order to remain compatible with all these existing device trees, we
-should therefore keep the logic as it was before the commit.
-
-Fixes: 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API")
-Cc: stable@vger.kernel.org
-Signed-off-by: Martin Schiller <ms@dev.tdt.de>
----
- arch/mips/pci/pci-lantiq.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/mips/pci/pci-lantiq.c
-+++ b/arch/mips/pci/pci-lantiq.c
-@@ -124,14 +124,14 @@ static int ltq_pci_startup(struct platfo
-               clk_disable(clk_external);
-       /* setup reset gpio used by pci */
--      reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
--                                           GPIOD_OUT_LOW);
-+      reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS);
-       error = PTR_ERR_OR_ZERO(reset_gpio);
-       if (error) {
-               dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
-               return error;
-       }
-       gpiod_set_consumer_name(reset_gpio, "pci_reset");
-+      gpiod_direction_output(reset_gpio, 1);
-       /* enable auto-switching between PCI and EBU */
-       ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
-@@ -194,10 +194,10 @@ static int ltq_pci_startup(struct platfo
-       /* toggle reset pin */
-       if (reset_gpio) {
--              gpiod_set_value_cansleep(reset_gpio, 1);
-+              gpiod_set_value_cansleep(reset_gpio, 0);
-               wmb();
-               mdelay(1);
--              gpiod_set_value_cansleep(reset_gpio, 0);
-+              gpiod_set_value_cansleep(reset_gpio, 1);
-       }
-       return 0;
- }