ath10k: Fix DMA burst size
authorSujith Manoharan <c_manoha@qca.qualcomm.com>
Mon, 12 Jan 2015 10:30:02 +0000 (12:30 +0200)
committerKalle Valo <kvalo@qca.qualcomm.com>
Mon, 12 Jan 2015 11:51:57 +0000 (13:51 +0200)
A value of zero indicates that 128B is the maximum
DMA request size for read/writes. But PCI cards based
on AR9880 can support 256B, so enable this for
the 10.2 firmware.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
drivers/net/wireless/ath/ath10k/hw.h
drivers/net/wireless/ath/ath10k/wmi.c

index 5729901923ac8674210c4be50a0a59705025ef6d..7b771ae7789fb1fc66f113a03d48e7401cded65a 100644 (file)
@@ -183,6 +183,9 @@ struct ath10k_pktlog_hdr {
 #define TARGET_10X_NUM_MSDU_DESC               (1024 + 400)
 #define TARGET_10X_MAX_FRAG_ENTRIES            0
 
+/* 10.2 parameters */
+#define TARGET_10_2_DMA_BURST_SIZE             1
+
 /* Target specific defines for WMI-TLV firmware */
 #define TARGET_TLV_NUM_VDEVS                   3
 #define TARGET_TLV_NUM_STATIONS                        32
index ac742905331bd08aad670d9903c2c6d7b036ace7..b103122c587420e331f8f1d8f7c5568bd2c71c64 100644 (file)
@@ -3744,7 +3744,7 @@ static struct sk_buff *ath10k_wmi_10_2_op_gen_init(struct ath10k *ar)
        config.mcast2ucast_mode = __cpu_to_le32(TARGET_10X_MCAST2UCAST_MODE);
        config.tx_dbg_log_size = __cpu_to_le32(TARGET_10X_TX_DBG_LOG_SIZE);
        config.num_wds_entries = __cpu_to_le32(TARGET_10X_NUM_WDS_ENTRIES);
-       config.dma_burst_size = __cpu_to_le32(TARGET_10X_DMA_BURST_SIZE);
+       config.dma_burst_size = __cpu_to_le32(TARGET_10_2_DMA_BURST_SIZE);
        config.mac_aggr_delim = __cpu_to_le32(TARGET_10X_MAC_AGGR_DELIM);
 
        val = TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;