drm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode start

Apply new UMC enable for VNC Dynamic Power Gate mode start

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 5740cca49f210cd1c2873b817adc89f8602ae649..624a255cffa3fad4d932054fad09fd644c7ebf07 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1023,13 +1023,14 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
 
-       /* enable UMC */
-       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
-                       0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
-
        /* boot up the VCPU */
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
 
+       /* enable UMC */
+       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
+               0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
+               0xFFFFFFFF, 0);
+
        /* enable master interrupt */
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
                        UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);