drm/i915: Introduce an HAS_IPS() macro

Follow the trend and don't code conditions with platforms but with
features.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d4e78b64ca874a2c6a12d6ea9602538193ea19ec..f72d5a3fdfbac732d8982eb298c305f29ce734f9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1483,7 +1483,7 @@ static int i915_ips_status(struct seq_file *m, void *unused)
        struct drm_device *dev = node->minor->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
 
-       if (!IS_ULT(dev)) {
+       if (!HAS_IPS(dev)) {
                seq_puts(m, "not supported\n");
                return 0;
        }

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9e1bf6dcbb2af8ece697e4d23861c7f5a3f62b1b..cc1d6056ab70238eb059d899be50efde6c4d05f6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1474,6 +1474,8 @@ struct drm_i915_file_private {
 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 
+#define HAS_IPS(dev)           (IS_ULT(dev))
+
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 
 #define HAS_DDI(dev)           (INTEL_INFO(dev)->has_ddi)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b08d1f9ce0de77a9360b7263ff64bb09875548c0..17d5c7a3468b81d5f68d0ab380d38ac2b312652d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3250,7 +3250,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 /* IPS only exists on ULT machines and is tied to pipe A. */
 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
 {
-       return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
+       return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
 }
 
 static void hsw_enable_ips(struct intel_crtc *crtc)
@@ -4069,7 +4069,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
                pipe_config->pipe_bpp = 8*3;
        }
 
-       if (IS_HASWELL(dev))
+       if (HAS_IPS(dev))
                hsw_compute_ips_config(crtc, pipe_config);
 
        /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old