#include <imx_sip_svc.h>
#include <sci/sci.h>
-#if defined(PLAT_IMX8QM) || defined(PLAT_IMX8QX)
+#if defined(PLAT_imx8qm) || defined(PLAT_imx8qx)
-#ifdef PLAT_IMX8QM
+#ifdef PLAT_imx8qm
const static int ap_cluster_index[PLATFORM_CLUSTER_COUNT] = {
SC_R_A53, SC_R_A72,
};
{
sc_pm_clock_rate_t rate = (sc_pm_clock_rate_t)freq;
-#ifdef PLAT_IMX8QM
+#ifdef PLAT_imx8qm
sc_pm_set_clock_rate(ipc_handle, ap_cluster_index[cluster_id], SC_PM_CLK_CPU, &rate);
#endif
-#ifdef PLAT_IMX8QX
+#ifdef PLAT_imx8qx
sc_pm_set_clock_rate(ipc_handle, SC_R_A35, SC_PM_CLK_CPU, &rate);
#endif
}
return sc_misc_set_temp(ipc_handle, x1, x2, x3, x4);
}
-#endif /* defined(PLAT_IMX8QM) || defined(PLAT_IMX8QX) */
+#endif /* defined(PLAT_imx8qm) || defined(PLAT_imx8qx) */
static uint64_t imx_get_commit_hash(u_register_t x2,
u_register_t x3,
SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3));
break;
#endif
-#if (defined(PLAT_IMX8QM) || defined(PLAT_IMX8QX))
+#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
case IMX_SIP_SRTC:
return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4);
case IMX_SIP_CPUFREQ:
u_register_t x2, u_register_t x3);
#endif
-#if (defined(PLAT_IMX8QM) || defined(PLAT_IMX8QX))
+#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3);
int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1,
#define DEBUG_CONSOLE 0
#define IMX_WDOG_B_RESET
-#define PLAT_IMX8M 1
#define CAAM_JR0MID U(0x30900010)
#define CAAM_JR1MID U(0x30900018)
#define DEBUG_CONSOLE 0
#define DEBUG_CONSOLE_A53 0
-#define PLAT_IMX8QM 1
#endif /* PLATFORM_DEF_H */
#define DEBUG_CONSOLE 0
#define DEBUG_CONSOLE_A35 0
-#define PLAT_IMX8QX 1
#endif /* PLATFORM_DEF_H */