drm/i915: make PCH_GMBUS* definitions private to gvt
authorLucas De Marchi <lucas.demarchi@intel.com>
Fri, 27 Jul 2018 19:36:45 +0000 (12:36 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 16 Aug 2018 18:52:05 +0000 (11:52 -0700)
This is the only place that they are being used - the others use the
GMBUS* macros that rely on dev_priv being already properly initialized.

Cc: intel-gvt-dev@lists.freedesktop.org
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180727193647.8639-1-lucas.demarchi@intel.com
drivers/gpu/drm/i915/gvt/reg.h
drivers/gpu/drm/i915/i915_reg.h

index d4f7ce6dc1d738f0e31bead53e6d6cf45beb7cf4..fd5fd25d0a0fa0f4f20d2d7239de3d5f625d50b6 100644 (file)
 #define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
                I915_GTT_PAGE_SIZE)
 
+#define PCH_GMBUS0     _MMIO(0xc5100)
+#define PCH_GMBUS1     _MMIO(0xc5104)
+#define PCH_GMBUS2     _MMIO(0xc5108)
+#define PCH_GMBUS3     _MMIO(0xc510c)
+#define PCH_GMBUS4     _MMIO(0xc5110)
+#define PCH_GMBUS5     _MMIO(0xc5120)
+
 #endif
index 0c9f03dda569dc2ffea8666810a5dd7e0fa66f00..14b47f431a2341f7f78022e1eaf1bc1bec91c56f 100644 (file)
@@ -7790,13 +7790,6 @@ enum {
 #define PCH_GPIOE               _MMIO(0xc5020)
 #define PCH_GPIOF               _MMIO(0xc5024)
 
-#define PCH_GMBUS0             _MMIO(0xc5100)
-#define PCH_GMBUS1             _MMIO(0xc5104)
-#define PCH_GMBUS2             _MMIO(0xc5108)
-#define PCH_GMBUS3             _MMIO(0xc510c)
-#define PCH_GMBUS4             _MMIO(0xc5110)
-#define PCH_GMBUS5             _MMIO(0xc5120)
-
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)