Add macro to check whether the CPU implements an EL

Replace all instances of checks with the new macro.

Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c
index 972c7f68cd18aa746bf12284efee7a5c995d6eb2..d226f61a0e8266563a7c9830369e33472c683b50 100644 (file)
--- a/bl1/aarch64/bl1_context_mgmt.c
+++ b/bl1/aarch64/bl1_context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -72,8 +72,7 @@ void bl1_prepare_next_image(unsigned int image_id)
         * Ensure that the build flag to save AArch32 system registers in CPU
         * context is not set for AArch64-only platforms.
         */
-       if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT)
-                       & ID_AA64PFR0_ELX_MASK) == 0x1) {
+       if (EL_IMPLEMENTED(1) == EL_IMPL_A64ONLY) {
                ERROR("EL1 supports AArch64-only. Please set build flag "
                                "CTX_INCLUDE_AARCH32_REGS = 0");
                panic();
@@ -99,9 +98,8 @@ void bl1_prepare_next_image(unsigned int image_id)
                next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
                                   DISABLE_ALL_EXCEPTIONS);
        } else {
-               /* Use EL2 if supported else use EL1. */
-               if (read_id_aa64pfr0_el1() &
-                       (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) {
+               /* Use EL2 if supported; else use EL1. */
+               if (EL_IMPLEMENTED(2)) {
                        next_bl_ep->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
                                DISABLE_ALL_EXCEPTIONS);
                } else {

diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index c74b72b71c697bb297b4c1c50ca92bd5b195e4be..55d0bd91e12105d0ab6dfb5895c70171e7c8b235 100644 (file)
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -172,8 +172,7 @@ void bl31_prepare_next_image_entry(void)
         * Ensure that the build flag to save AArch32 system registers in CPU
         * context is not set for AArch64-only platforms.
         */
-       if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT)
-                       & ID_AA64PFR0_ELX_MASK) == 0x1) {
+       if (EL_IMPLEMENTED(1) == EL_IMPL_A64ONLY) {
                ERROR("EL1 supports AArch64-only. Please set build flag "
                                "CTX_INCLUDE_AARCH32_REGS = 0");
                panic();

diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index ef7241d3b7279449869186135b4d3e471d08898e..834434eea2bccf89f21de3c6bcf9614f57e31a99 100644 (file)
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -134,6 +134,10 @@
 #define ID_AA64PFR0_EL3_SHIFT  12
 #define ID_AA64PFR0_ELX_MASK   0xf
 
+#define EL_IMPL_NONE           0
+#define EL_IMPL_A64ONLY                1
+#define EL_IMPL_A64_A32                2
+
 #define ID_AA64PFR0_GIC_SHIFT  24
 #define ID_AA64PFR0_GIC_WIDTH  4
 #define ID_AA64PFR0_GIC_MASK   ((1 << ID_AA64PFR0_GIC_WIDTH) - 1)

diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 4f7110562962e77404f257e54be3a6f434893117..b195ffa247df9c71758acc0f8fa6068d487ee1ec 100644 (file)
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -352,6 +352,14 @@ DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
 #define IS_IN_EL1() IS_IN_EL(1)
 #define IS_IN_EL3() IS_IN_EL(3)
 
+/*
+ * Check if an EL is implemented from AA64PFR0 register fields. 'el' argument
+ * must be one of 1, 2 or 3.
+ */
+#define EL_IMPLEMENTED(el) \
+       ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL##el##_SHIFT) \
+               & ID_AA64PFR0_ELX_MASK)
+
 /* Previously defined accesor functions with incomplete register names  */
 
 #define read_current_el()      read_CurrentEl()

diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 5cce8793dfad6abde4cec5734adb2fabdfe95747..b16e55d9057c68510d994020457de295bed0b53c 100644 (file)
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -229,8 +229,7 @@ void cm_prepare_el3_exit(uint32_t security_state)
                        sctlr_elx &= ~SCTLR_EE_BIT;
                        sctlr_elx |= SCTLR_EL2_RES1;
                        write_sctlr_el2(sctlr_elx);
-               } else if (read_id_aa64pfr0_el1() &
-                          (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) {
+               } else if (EL_IMPLEMENTED(2)) {
                        /* EL2 present but unused, need to disable safely */
 
                        /* HCR_EL2 = 0, except RW bit set to match SCR_EL3 */

diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index 3d67ef76735b521e84b4ccf93b9c494c4b00ddf4..ffd7b7eecdaeb6a8f11b85dfb61355b95ba1a559 100644 (file)
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -137,15 +137,11 @@ uint32_t arm_get_spsr_for_bl32_entry(void)
 #ifndef AARCH32
 uint32_t arm_get_spsr_for_bl33_entry(void)
 {
-       unsigned long el_status;
        unsigned int mode;
        uint32_t spsr;
 
        /* Figure out what mode we enter the non-secure world in */
-       el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
-       el_status &= ID_AA64PFR0_ELX_MASK;
-
-       mode = (el_status) ? MODE_EL2 : MODE_EL1;
+       mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
 
        /*
         * TODO: Consider the possibility of specifying the SPSR in

diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c
index af0858f0bbd1a10a1dbeae5653fdd1d4bba0c503..1ba8b1450ec04ecc669f456008b7810e24da3df9 100644 (file)
--- a/plat/mediatek/mt6795/bl31_plat_setup.c
+++ b/plat/mediatek/mt6795/bl31_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -360,20 +360,15 @@ void enable_ns_access_to_cpuectlr(void)
 static entry_point_info_t *bl31_plat_get_next_kernel64_ep_info(void)
 {
        entry_point_info_t *next_image_info;
-       unsigned long el_status;
        unsigned int mode;
 
-       el_status = 0;
        mode = 0;
 
        /* Kernel image is always non-secured */
        next_image_info = &bl33_image_ep_info;
 
        /* Figure out what mode we enter the non-secure world in */
-       el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
-       el_status &= ID_AA64PFR0_ELX_MASK;
-
-       if (el_status) {
+       if (EL_IMPLEMENTED(2)) {
                INFO("Kernel_EL2\n");
                mode = MODE_EL2;
        } else{

diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index 738d671ad851e5294b115171e124607a8447bb87..6c599744fe23115586025da91f0d05e35b2e0455 100644 (file)
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -226,15 +226,11 @@ static uint32_t qemu_get_spsr_for_bl32_entry(void)
  ******************************************************************************/
 static uint32_t qemu_get_spsr_for_bl33_entry(void)
 {
-       unsigned long el_status;
        unsigned int mode;
        uint32_t spsr;
 
        /* Figure out what mode we enter the non-secure world in */
-       el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
-       el_status &= ID_AA64PFR0_ELX_MASK;
-
-       mode = (el_status) ? MODE_EL2 : MODE_EL1;
+       mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
 
        /*
         * TODO: Consider the possibility of specifying the SPSR in