pr_err("Unsupported core_unit %d\n", core->core_unit);
return -ENOTSUPP;
}
-@@ -1534,8 +1538,7 @@ static int bgmac_probe(struct bcma_devic
+@@ -1473,8 +1477,7 @@ static int bgmac_probe(struct bcma_devic
+ }
+ bgmac->cmn = core->bus->drv_gmac_cmn.core;
+
+- bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
+- sprom->et0phyaddr;
++ bgmac->phyaddr = BGMAC_PHY_NOREGS; // core->core_unit ? sprom->et1phyaddr : sprom->et0phyaddr;
+ bgmac->phyaddr &= BGMAC_PHY_MASK;
+ if (bgmac->phyaddr == BGMAC_PHY_MASK) {
+ bgmac_err(bgmac, "No PHY found\n");
+@@ -1526,8 +1529,7 @@ static int bgmac_probe(struct bcma_devic
/* TODO: reset the external phy. Specs are needed */
bgmac_phy_reset(bgmac);
-patches for bgmac backported from net-next/master
-
--- a/drivers/net/ethernet/broadcom/Kconfig
+++ b/drivers/net/ethernet/broadcom/Kconfig
@@ -132,7 +132,8 @@ config BNX2X_SRIOV
They can be found on BCM47xx SoCs and provide gigabit ethernet.
--- a/drivers/net/ethernet/broadcom/bgmac.c
+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -149,6 +149,8 @@ static netdev_tx_t bgmac_dma_tx_add(stru
+@@ -96,6 +96,19 @@ static void bgmac_dma_tx_enable(struct b
+ u32 ctl;
+
+ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
++ if (bgmac->core->id.rev >= 4) {
++ ctl &= ~BGMAC_DMA_TX_BL_MASK;
++ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
++
++ ctl &= ~BGMAC_DMA_TX_MR_MASK;
++ ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
++
++ ctl &= ~BGMAC_DMA_TX_PC_MASK;
++ ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
++
++ ctl &= ~BGMAC_DMA_TX_PT_MASK;
++ ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
++ }
+ ctl |= BGMAC_DMA_TX_ENABLE;
+ ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
+ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
+@@ -149,6 +162,8 @@ static netdev_tx_t bgmac_dma_tx_add(stru
dma_desc->ctl0 = cpu_to_le32(ctl0);
dma_desc->ctl1 = cpu_to_le32(ctl1);
wmb();
/* Increase ring->end to point empty slot. We tell hardware the first
-@@ -157,6 +159,7 @@ static netdev_tx_t bgmac_dma_tx_add(stru
+@@ -157,6 +172,7 @@ static netdev_tx_t bgmac_dma_tx_add(stru
if (++ring->end >= BGMAC_TX_RING_SLOTS)
ring->end = 0;
bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
ring->end * sizeof(struct bgmac_dma_desc));
/* Always keep one slot free to allow detecting bugged calls. */
-@@ -177,10 +180,13 @@ static void bgmac_dma_tx_free(struct bgm
+@@ -177,10 +193,13 @@ static void bgmac_dma_tx_free(struct bgm
struct device *dma_dev = bgmac->core->dma_dev;
int empty_slot;
bool freed = false;
empty_slot /= sizeof(struct bgmac_dma_desc);
while (ring->start != empty_slot) {
-@@ -192,6 +198,9 @@ static void bgmac_dma_tx_free(struct bgm
+@@ -192,6 +211,9 @@ static void bgmac_dma_tx_free(struct bgm
slot->skb->len, DMA_TO_DEVICE);
slot->dma_addr = 0;
/* Free memory! :) */
dev_kfree_skb(slot->skb);
slot->skb = NULL;
-@@ -205,6 +214,8 @@ static void bgmac_dma_tx_free(struct bgm
+@@ -205,6 +227,8 @@ static void bgmac_dma_tx_free(struct bgm
freed = true;
}
if (freed && netif_queue_stopped(bgmac->net_dev))
netif_wake_queue(bgmac->net_dev);
}
-@@ -241,31 +252,59 @@ static int bgmac_dma_rx_skb_for_slot(str
+@@ -229,6 +253,16 @@ static void bgmac_dma_rx_enable(struct b
+ u32 ctl;
+
+ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
++ if (bgmac->core->id.rev >= 4) {
++ ctl &= ~BGMAC_DMA_RX_BL_MASK;
++ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
++
++ ctl &= ~BGMAC_DMA_RX_PC_MASK;
++ ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
++
++ ctl &= ~BGMAC_DMA_RX_PT_MASK;
++ ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
++ }
+ ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
+ ctl |= BGMAC_DMA_RX_ENABLE;
+ ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
+@@ -241,31 +275,59 @@ static int bgmac_dma_rx_skb_for_slot(str
struct bgmac_slot_info *slot)
{
struct device *dma_dev = bgmac->core->dma_dev;
static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
int weight)
{
-@@ -274,6 +313,8 @@ static int bgmac_dma_rx_read(struct bgma
+@@ -274,6 +336,8 @@ static int bgmac_dma_rx_read(struct bgma
end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
end_slot &= BGMAC_DMA_RX_STATDPTR;
end_slot /= sizeof(struct bgmac_dma_desc);
ring->end = end_slot;
-@@ -282,7 +323,6 @@ static int bgmac_dma_rx_read(struct bgma
+@@ -282,7 +346,6 @@ static int bgmac_dma_rx_read(struct bgma
struct device *dma_dev = bgmac->core->dma_dev;
struct bgmac_slot_info *slot = &ring->slots[ring->start];
struct sk_buff *skb = slot->skb;
struct bgmac_rx_header *rx;
u16 len, flags;
-@@ -295,38 +335,51 @@ static int bgmac_dma_rx_read(struct bgma
+@@ -295,38 +358,51 @@ static int bgmac_dma_rx_read(struct bgma
len = le16_to_cpu(rx->len);
flags = le16_to_cpu(rx->flags);
if (++ring->start >= BGMAC_RX_RING_SLOTS)
ring->start = 0;
-@@ -418,9 +471,6 @@ static int bgmac_dma_alloc(struct bgmac
+@@ -418,9 +494,6 @@ static int bgmac_dma_alloc(struct bgmac
ring = &bgmac->tx_ring[i];
ring->num_slots = BGMAC_TX_RING_SLOTS;
ring->mmio_base = ring_base[i];
/* Alloc ring of descriptors */
size = ring->num_slots * sizeof(struct bgmac_dma_desc);
-@@ -435,6 +485,13 @@ static int bgmac_dma_alloc(struct bgmac
+@@ -435,6 +508,13 @@ static int bgmac_dma_alloc(struct bgmac
if (ring->dma_base & 0xC0000000)
bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
/* No need to alloc TX slots yet */
}
-@@ -444,9 +501,6 @@ static int bgmac_dma_alloc(struct bgmac
+@@ -444,9 +524,6 @@ static int bgmac_dma_alloc(struct bgmac
ring = &bgmac->rx_ring[i];
ring->num_slots = BGMAC_RX_RING_SLOTS;
ring->mmio_base = ring_base[i];
/* Alloc ring of descriptors */
size = ring->num_slots * sizeof(struct bgmac_dma_desc);
-@@ -462,6 +516,13 @@ static int bgmac_dma_alloc(struct bgmac
+@@ -462,6 +539,13 @@ static int bgmac_dma_alloc(struct bgmac
if (ring->dma_base & 0xC0000000)
bgmac_warn(bgmac, "DMA address using 0xC0000000 bit(s), it may need translation trick\n");
/* Alloc RX slots */
for (j = 0; j < ring->num_slots; j++) {
err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
-@@ -482,19 +543,19 @@ err_dma_free:
+@@ -482,19 +566,19 @@ err_dma_free:
static void bgmac_dma_init(struct bgmac *bgmac)
{
struct bgmac_dma_ring *ring;
ring->start = 0;
ring->end = 0; /* Points the slot that should *not* be read */
-@@ -505,32 +566,20 @@ static void bgmac_dma_init(struct bgmac
+@@ -505,32 +589,20 @@ static void bgmac_dma_init(struct bgmac
ring = &bgmac->rx_ring[i];
ring->num_slots * sizeof(struct bgmac_dma_desc));
ring->start = 0;
-@@ -633,70 +682,6 @@ static int bgmac_phy_write(struct bgmac
+@@ -633,70 +705,6 @@ static int bgmac_phy_write(struct bgmac
return 0;
}
/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
static void bgmac_phy_init(struct bgmac *bgmac)
{
-@@ -827,19 +812,28 @@ static void bgmac_clear_mib(struct bgmac
+@@ -740,11 +748,9 @@ static void bgmac_phy_reset(struct bgmac
+ if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
+ return;
+
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
+- BGMAC_PHY_CTL_RESET);
++ bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
+ udelay(100);
+- if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
+- BGMAC_PHY_CTL_RESET)
++ if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
+ bgmac_err(bgmac, "PHY reset failed\n");
+ bgmac_phy_init(bgmac);
+ }
+@@ -762,13 +768,13 @@ static void bgmac_cmdcfg_maskset(struct
+ u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
+ u32 new_val = (cmdcfg & mask) | set;
+
+- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
++ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
+ udelay(2);
+
+ if (new_val != cmdcfg || force)
+ bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
+
+- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
++ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
+ udelay(2);
+ }
+
+@@ -827,31 +833,56 @@ static void bgmac_clear_mib(struct bgmac
}
/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
set |= BGMAC_CMDCFG_ES_1000;
- if (!bgmac->full_duplex)
+ break;
++ case SPEED_2500:
++ set |= BGMAC_CMDCFG_ES_2500;
++ break;
+ default:
+ bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
+ }
bgmac_cmdcfg_maskset(bgmac, mask, set, true);
}
-@@ -848,10 +842,9 @@ static void bgmac_miiconfig(struct bgmac
- u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
- BGMAC_DS_MM_SHIFT;
- if (imode == 0 || imode == 1) {
+ static void bgmac_miiconfig(struct bgmac *bgmac)
+ {
+- u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
+- BGMAC_DS_MM_SHIFT;
+- if (imode == 0 || imode == 1) {
- if (bgmac->autoneg)
- bgmac_speed(bgmac, BGMAC_SPEED_100);
- else
- bgmac_speed(bgmac, bgmac->speed);
-+ bgmac->mac_speed = SPEED_100;
++ struct bcma_device *core = bgmac->core;
++ struct bcma_chipinfo *ci = &core->bus->chipinfo;
++ u8 imode;
++
++ if (ci->id == BCMA_CHIP_ID_BCM4707 ||
++ ci->id == BCMA_CHIP_ID_BCM53018) {
++ bcma_awrite32(core, BCMA_IOCTL,
++ bcma_aread32(core, BCMA_IOCTL) | 0x40 |
++ BGMAC_BCMA_IOCTL_SW_CLKEN);
++ bgmac->mac_speed = SPEED_2500;
+ bgmac->mac_duplex = DUPLEX_FULL;
+ bgmac_mac_speed(bgmac);
++ } else {
++ imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
++ BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
++ if (imode == 0 || imode == 1) {
++ bgmac->mac_speed = SPEED_100;
++ bgmac->mac_duplex = DUPLEX_FULL;
++ bgmac_mac_speed(bgmac);
++ }
}
}
-@@ -884,9 +877,9 @@ static void bgmac_chip_reset(struct bgma
+@@ -861,7 +892,7 @@ static void bgmac_chip_reset(struct bgma
+ struct bcma_device *core = bgmac->core;
+ struct bcma_bus *bus = core->bus;
+ struct bcma_chipinfo *ci = &bus->chipinfo;
+- u32 flags = 0;
++ u32 flags;
+ u32 iost;
+ int i;
+
+@@ -884,44 +915,55 @@ static void bgmac_chip_reset(struct bgma
}
iost = bcma_aread32(core, BCMA_IOST);
+ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
iost &= ~BGMAC_BCMA_IOST_ATTACHED;
- if (iost & BGMAC_BCMA_IOST_ATTACHED) {
-@@ -898,30 +891,35 @@ static void bgmac_chip_reset(struct bgma
- bcma_core_enable(core, flags);
+- if (iost & BGMAC_BCMA_IOST_ATTACHED) {
+- flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
+- if (!bgmac->has_robosw)
+- flags |= BGMAC_BCMA_IOCTL_SW_RESET;
++ /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
++ if (ci->id != BCMA_CHIP_ID_BCM4707) {
++ flags = 0;
++ if (iost & BGMAC_BCMA_IOST_ATTACHED) {
++ flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
++ if (!bgmac->has_robosw)
++ flags |= BGMAC_BCMA_IOCTL_SW_RESET;
++ }
++ bcma_core_enable(core, flags);
+ }
- if (core->id.rev > 2) {
+- bcma_core_enable(core, flags);
+-
+- if (core->id.rev > 2) {
- bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
- bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
++ /* Request Misc PLL for corerev > 2 */
++ if (core->id.rev > 2 &&
++ ci->id != BCMA_CHIP_ID_BCM4707 &&
++ ci->id != BCMA_CHIP_ID_BCM53018) {
+ bgmac_set(bgmac, BCMA_CLKCTLST,
+ BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
+ bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
}
-@@ -960,6 +958,8 @@ static void bgmac_chip_reset(struct bgma
+@@ -958,8 +1000,10 @@ static void bgmac_chip_reset(struct bgma
+ BGMAC_CMDCFG_PROM |
+ BGMAC_CMDCFG_NLC |
BGMAC_CMDCFG_CFE |
- BGMAC_CMDCFG_SR,
+- BGMAC_CMDCFG_SR,
++ BGMAC_CMDCFG_SR(core->id.rev),
false);
+ bgmac->mac_speed = SPEED_UNKNOWN;
+ bgmac->mac_duplex = DUPLEX_UNKNOWN;
bgmac_clear_mib(bgmac);
if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
-@@ -970,6 +970,8 @@ static void bgmac_chip_reset(struct bgma
+@@ -970,6 +1014,8 @@ static void bgmac_chip_reset(struct bgma
bgmac_miiconfig(bgmac);
bgmac_phy_init(bgmac);
bgmac->int_status = 0;
}
-@@ -1057,13 +1059,6 @@ static void bgmac_chip_init(struct bgmac
+@@ -997,7 +1043,7 @@ static void bgmac_enable(struct bgmac *b
+
+ cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
+ bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
+- BGMAC_CMDCFG_SR, true);
++ BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
+ udelay(2);
+ cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
+ bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
+@@ -1026,12 +1072,16 @@ static void bgmac_enable(struct bgmac *b
+ break;
+ }
+
+- rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
+- rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
+- bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
+- mdp = (bp_clk * 128 / 1000) - 3;
+- rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
+- bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
++ if (ci->id != BCMA_CHIP_ID_BCM4707 &&
++ ci->id != BCMA_CHIP_ID_BCM53018) {
++ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
++ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
++ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
++ 1000000;
++ mdp = (bp_clk * 128 / 1000) - 3;
++ rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
++ bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
++ }
+ }
+
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
+@@ -1057,13 +1107,6 @@ static void bgmac_chip_init(struct bgmac
bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
if (full_init) {
bgmac_dma_init(bgmac);
if (1) /* FIXME: is there any case we don't want IRQs? */
-@@ -1153,6 +1148,8 @@ static int bgmac_open(struct net_device
+@@ -1153,6 +1196,8 @@ static int bgmac_open(struct net_device
}
napi_enable(&bgmac->napi);
netif_carrier_on(net_dev);
err_out:
-@@ -1165,6 +1162,8 @@ static int bgmac_stop(struct net_device
+@@ -1165,6 +1210,8 @@ static int bgmac_stop(struct net_device
netif_carrier_off(net_dev);
napi_disable(&bgmac->napi);
bgmac_chip_intrs_off(bgmac);
free_irq(bgmac->core->irq, net_dev);
-@@ -1243,61 +1242,16 @@ static int bgmac_get_settings(struct net
+@@ -1201,27 +1248,11 @@ static int bgmac_set_mac_address(struct
+ static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
+ {
+ struct bgmac *bgmac = netdev_priv(net_dev);
+- struct mii_ioctl_data *data = if_mii(ifr);
+
+- switch (cmd) {
+- case SIOCGMIIPHY:
+- data->phy_id = bgmac->phyaddr;
+- /* fallthru */
+- case SIOCGMIIREG:
+- if (!netif_running(net_dev))
+- return -EAGAIN;
+- data->val_out = bgmac_phy_read(bgmac, data->phy_id,
+- data->reg_num & 0x1f);
+- return 0;
+- case SIOCSMIIREG:
+- if (!netif_running(net_dev))
+- return -EAGAIN;
+- bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
+- data->val_in);
+- return 0;
+- default:
+- return -EOPNOTSUPP;
+- }
++ if (!netif_running(net_dev))
++ return -EINVAL;
++
++ return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
+ }
+
+ static const struct net_device_ops bgmac_netdev_ops = {
+@@ -1243,61 +1274,16 @@ static int bgmac_get_settings(struct net
{
struct bgmac *bgmac = netdev_priv(net_dev);
static void bgmac_get_drvinfo(struct net_device *net_dev,
struct ethtool_drvinfo *info)
-@@ -1308,6 +1262,7 @@ static void bgmac_get_drvinfo(struct net
+@@ -1308,6 +1294,7 @@ static void bgmac_get_drvinfo(struct net
static const struct ethtool_ops bgmac_ethtool_ops = {
.get_settings = bgmac_get_settings,
.get_drvinfo = bgmac_get_drvinfo,
};
-@@ -1326,9 +1281,35 @@ static int bgmac_mii_write(struct mii_bu
+@@ -1326,9 +1313,35 @@ static int bgmac_mii_write(struct mii_bu
return bgmac_phy_write(bus->priv, mii_id, regnum, value);
}
int i, err = 0;
mii_bus = mdiobus_alloc();
-@@ -1360,8 +1341,22 @@ static int bgmac_mii_register(struct bgm
+@@ -1360,8 +1373,22 @@ static int bgmac_mii_register(struct bgm
bgmac->mii_bus = mii_bus;
err_free_irq:
kfree(mii_bus->irq);
err_free_bus:
-@@ -1416,9 +1411,6 @@ static int bgmac_probe(struct bcma_devic
+@@ -1416,9 +1443,6 @@ static int bgmac_probe(struct bcma_devic
bcma_set_drvdata(core, bgmac);
/* Defaults */
memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
/* On BCM4706 we need common core to access PHY */
+@@ -1449,6 +1473,27 @@ static int bgmac_probe(struct bcma_devic
+
+ bgmac_chip_reset(bgmac);
+
++ /* For Northstar, we have to take all GMAC core out of reset */
++ if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
++ core->id.id == BCMA_CHIP_ID_BCM53018) {
++ struct bcma_device *ns_core;
++ int ns_gmac;
++
++ /* Northstar has 4 GMAC cores */
++ for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
++ /* As Northstar requirement, we have to reset all GMACs
++ * before accessing one. bgmac_chip_reset() call
++ * bcma_core_enable() for this core. Then the other
++ * three GMACs didn't reset. We do it here.
++ */
++ ns_core = bcma_find_core_unit(core->bus,
++ BCMA_CORE_MAC_GBIT,
++ ns_gmac);
++ if (ns_core && !bcma_core_is_enabled(ns_core))
++ bcma_core_enable(ns_core, 0);
++ }
++ }
++
+ err = bgmac_dma_alloc(bgmac);
+ if (err) {
+ bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
+@@ -1473,14 +1518,12 @@ static int bgmac_probe(struct bcma_devic
+ err = bgmac_mii_register(bgmac);
+ if (err) {
+ bgmac_err(bgmac, "Cannot register MDIO\n");
+- err = -ENOTSUPP;
+ goto err_dma_free;
+ }
+
+ err = register_netdev(bgmac->net_dev);
+ if (err) {
+ bgmac_err(bgmac, "Cannot register net device\n");
+- err = -ENOTSUPP;
+ goto err_mii_unregister;
+ }
+
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
@@ -95,7 +95,11 @@
#define BGMAC_HW_WAR 0x1e4
#define BGMAC_PWR_CTL 0x1e8
#define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */
-@@ -342,10 +346,6 @@
+@@ -185,6 +189,7 @@
+ #define BGMAC_CMDCFG_ES_10 0x00000000
+ #define BGMAC_CMDCFG_ES_100 0x00000004
+ #define BGMAC_CMDCFG_ES_1000 0x00000008
++#define BGMAC_CMDCFG_ES_2500 0x0000000C
+ #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
+ #define BGMAC_CMDCFG_PAD_EN 0x00000020
+ #define BGMAC_CMDCFG_CF 0x00000040
+@@ -193,7 +198,9 @@
+ #define BGMAC_CMDCFG_TAI 0x00000200
+ #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
+ #define BGMAC_CMDCFG_HD_SHIFT 10
+-#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
++#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */
++#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
++#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
+ #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
+ #define BGMAC_CMDCFG_AE 0x00400000
+ #define BGMAC_CMDCFG_CFE 0x00800000
+@@ -216,27 +223,6 @@
+ #define BGMAC_RX_STATUS 0xb38
+ #define BGMAC_TX_STATUS 0xb3c
+
+-#define BGMAC_PHY_CTL 0x00
+-#define BGMAC_PHY_CTL_SPEED_MSB 0x0040
+-#define BGMAC_PHY_CTL_DUPLEX 0x0100 /* duplex mode */
+-#define BGMAC_PHY_CTL_RESTART 0x0200 /* restart autonegotiation */
+-#define BGMAC_PHY_CTL_ANENAB 0x1000 /* enable autonegotiation */
+-#define BGMAC_PHY_CTL_SPEED 0x2000
+-#define BGMAC_PHY_CTL_LOOP 0x4000 /* loopback */
+-#define BGMAC_PHY_CTL_RESET 0x8000 /* reset */
+-/* Helpers */
+-#define BGMAC_PHY_CTL_SPEED_10 0
+-#define BGMAC_PHY_CTL_SPEED_100 BGMAC_PHY_CTL_SPEED
+-#define BGMAC_PHY_CTL_SPEED_1000 BGMAC_PHY_CTL_SPEED_MSB
+-#define BGMAC_PHY_ADV 0x04
+-#define BGMAC_PHY_ADV_10HALF 0x0020 /* advertise 10MBits/s half duplex */
+-#define BGMAC_PHY_ADV_10FULL 0x0040 /* advertise 10MBits/s full duplex */
+-#define BGMAC_PHY_ADV_100HALF 0x0080 /* advertise 100MBits/s half duplex */
+-#define BGMAC_PHY_ADV_100FULL 0x0100 /* advertise 100MBits/s full duplex */
+-#define BGMAC_PHY_ADV2 0x09
+-#define BGMAC_PHY_ADV2_1000HALF 0x0100 /* advertise 1000MBits/s half duplex */
+-#define BGMAC_PHY_ADV2_1000FULL 0x0200 /* advertise 1000MBits/s full duplex */
+-
+ /* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
+ #define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
+ #define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */
+@@ -254,9 +240,34 @@
+ #define BGMAC_DMA_TX_SUSPEND 0x00000002
+ #define BGMAC_DMA_TX_LOOPBACK 0x00000004
+ #define BGMAC_DMA_TX_FLUSH 0x00000010
++#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
++#define BGMAC_DMA_TX_MR_SHIFT 6
++#define BGMAC_DMA_TX_MR_1 0
++#define BGMAC_DMA_TX_MR_2 1
+ #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
+ #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
+ #define BGMAC_DMA_TX_ADDREXT_SHIFT 16
++#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
++#define BGMAC_DMA_TX_BL_SHIFT 18
++#define BGMAC_DMA_TX_BL_16 0
++#define BGMAC_DMA_TX_BL_32 1
++#define BGMAC_DMA_TX_BL_64 2
++#define BGMAC_DMA_TX_BL_128 3
++#define BGMAC_DMA_TX_BL_256 4
++#define BGMAC_DMA_TX_BL_512 5
++#define BGMAC_DMA_TX_BL_1024 6
++#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
++#define BGMAC_DMA_TX_PC_SHIFT 21
++#define BGMAC_DMA_TX_PC_0 0
++#define BGMAC_DMA_TX_PC_4 1
++#define BGMAC_DMA_TX_PC_8 2
++#define BGMAC_DMA_TX_PC_16 3
++#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
++#define BGMAC_DMA_TX_PT_SHIFT 24
++#define BGMAC_DMA_TX_PT_1 0
++#define BGMAC_DMA_TX_PT_2 1
++#define BGMAC_DMA_TX_PT_4 2
++#define BGMAC_DMA_TX_PT_8 3
+ #define BGMAC_DMA_TX_INDEX 0x04
+ #define BGMAC_DMA_TX_RINGLO 0x08
+ #define BGMAC_DMA_TX_RINGHI 0x0C
+@@ -284,8 +295,33 @@
+ #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
+ #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
+ #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
++#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
++#define BGMAC_DMA_RX_MR_SHIFT 6
++#define BGMAC_DMA_TX_MR_1 0
++#define BGMAC_DMA_TX_MR_2 1
+ #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
+ #define BGMAC_DMA_RX_ADDREXT_SHIFT 16
++#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
++#define BGMAC_DMA_RX_BL_SHIFT 18
++#define BGMAC_DMA_RX_BL_16 0
++#define BGMAC_DMA_RX_BL_32 1
++#define BGMAC_DMA_RX_BL_64 2
++#define BGMAC_DMA_RX_BL_128 3
++#define BGMAC_DMA_RX_BL_256 4
++#define BGMAC_DMA_RX_BL_512 5
++#define BGMAC_DMA_RX_BL_1024 6
++#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
++#define BGMAC_DMA_RX_PC_SHIFT 21
++#define BGMAC_DMA_RX_PC_0 0
++#define BGMAC_DMA_RX_PC_4 1
++#define BGMAC_DMA_RX_PC_8 2
++#define BGMAC_DMA_RX_PC_16 3
++#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
++#define BGMAC_DMA_RX_PT_SHIFT 24
++#define BGMAC_DMA_RX_PT_1 0
++#define BGMAC_DMA_RX_PT_2 1
++#define BGMAC_DMA_RX_PT_4 2
++#define BGMAC_DMA_RX_PT_8 3
+ #define BGMAC_DMA_RX_INDEX 0x24
+ #define BGMAC_DMA_RX_RINGLO 0x28
+ #define BGMAC_DMA_RX_RINGHI 0x2C
+@@ -342,10 +378,6 @@
#define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0
#define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000
#define BGMAC_WEIGHT 64
#define ETHER_MAX_LEN 1518
-@@ -384,6 +384,8 @@ struct bgmac_dma_ring {
+@@ -384,6 +416,8 @@ struct bgmac_dma_ring {
u16 mmio_base;
struct bgmac_dma_desc *cpu_base;
dma_addr_t dma_base;
struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS];
};
-@@ -400,6 +402,7 @@ struct bgmac {
+@@ -400,6 +434,7 @@ struct bgmac {
struct net_device *net_dev;
struct napi_struct napi;
struct mii_bus *mii_bus;
/* DMA */
struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
-@@ -414,10 +417,9 @@ struct bgmac {
+@@ -414,10 +449,9 @@ struct bgmac {
u32 int_mask;
u32 int_status;
+++ /dev/null
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -725,11 +725,9 @@ static void bgmac_phy_reset(struct bgmac
- if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
- return;
-
-- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
-- BGMAC_PHY_CTL_RESET);
-+ bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
- udelay(100);
-- if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
-- BGMAC_PHY_CTL_RESET)
-+ if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
- bgmac_err(bgmac, "PHY reset failed\n");
- bgmac_phy_init(bgmac);
- }
-@@ -1200,27 +1198,11 @@ static int bgmac_set_mac_address(struct
- static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
- {
- struct bgmac *bgmac = netdev_priv(net_dev);
-- struct mii_ioctl_data *data = if_mii(ifr);
-
-- switch (cmd) {
-- case SIOCGMIIPHY:
-- data->phy_id = bgmac->phyaddr;
-- /* fallthru */
-- case SIOCGMIIREG:
-- if (!netif_running(net_dev))
-- return -EAGAIN;
-- data->val_out = bgmac_phy_read(bgmac, data->phy_id,
-- data->reg_num & 0x1f);
-- return 0;
-- case SIOCSMIIREG:
-- if (!netif_running(net_dev))
-- return -EAGAIN;
-- bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
-- data->val_in);
-- return 0;
-- default:
-- return -EOPNOTSUPP;
-- }
-+ if (!netif_running(net_dev))
-+ return -EINVAL;
-+
-+ return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
- }
-
- static const struct net_device_ops bgmac_netdev_ops = {
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -220,27 +220,6 @@
- #define BGMAC_RX_STATUS 0xb38
- #define BGMAC_TX_STATUS 0xb3c
-
--#define BGMAC_PHY_CTL 0x00
--#define BGMAC_PHY_CTL_SPEED_MSB 0x0040
--#define BGMAC_PHY_CTL_DUPLEX 0x0100 /* duplex mode */
--#define BGMAC_PHY_CTL_RESTART 0x0200 /* restart autonegotiation */
--#define BGMAC_PHY_CTL_ANENAB 0x1000 /* enable autonegotiation */
--#define BGMAC_PHY_CTL_SPEED 0x2000
--#define BGMAC_PHY_CTL_LOOP 0x4000 /* loopback */
--#define BGMAC_PHY_CTL_RESET 0x8000 /* reset */
--/* Helpers */
--#define BGMAC_PHY_CTL_SPEED_10 0
--#define BGMAC_PHY_CTL_SPEED_100 BGMAC_PHY_CTL_SPEED
--#define BGMAC_PHY_CTL_SPEED_1000 BGMAC_PHY_CTL_SPEED_MSB
--#define BGMAC_PHY_ADV 0x04
--#define BGMAC_PHY_ADV_10HALF 0x0020 /* advertise 10MBits/s half duplex */
--#define BGMAC_PHY_ADV_10FULL 0x0040 /* advertise 10MBits/s full duplex */
--#define BGMAC_PHY_ADV_100HALF 0x0080 /* advertise 100MBits/s half duplex */
--#define BGMAC_PHY_ADV_100FULL 0x0100 /* advertise 100MBits/s full duplex */
--#define BGMAC_PHY_ADV2 0x09
--#define BGMAC_PHY_ADV2_1000HALF 0x0100 /* advertise 1000MBits/s half duplex */
--#define BGMAC_PHY_ADV2_1000FULL 0x0200 /* advertise 1000MBits/s full duplex */
--
- /* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
- #define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
- #define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */
+++ /dev/null
-From 2e3759f95d3c96282c19e6f57274d816c6cf1a0e Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sun, 10 Nov 2013 21:13:20 +0100
-Subject: [PATCH 4/5] bgmac: reset all cores on Northstar SoC
-
-On the Northstar SoC (BCM4707 and BCM53018) we have to enable all GMAC
-cores when we just want to use on. We iterate over all the cores and
-activate them.
-
-Subject: [PATCH 5/5] bgmac: add support for Northstar SoC (BCM4707, BCM53018)
-
-This adds support for the Northstar SoC. This SoC does not have a PMU in
-bcma and no register on it should be called. In addition it support 2.5
-GBit/s Ethernet to the PHY.
-
-This GMAC core is not fully working there are still problems with the
-DMA controller.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -825,6 +825,9 @@ static void bgmac_mac_speed(struct bgmac
- case SPEED_1000:
- set |= BGMAC_CMDCFG_ES_1000;
- break;
-+ case SPEED_2500:
-+ set |= BGMAC_CMDCFG_ES_2500;
-+ break;
- default:
- bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
- }
-@@ -837,12 +840,26 @@ static void bgmac_mac_speed(struct bgmac
-
- static void bgmac_miiconfig(struct bgmac *bgmac)
- {
-- u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
-- BGMAC_DS_MM_SHIFT;
-- if (imode == 0 || imode == 1) {
-- bgmac->mac_speed = SPEED_100;
-+ struct bcma_device *core = bgmac->core;
-+ struct bcma_chipinfo *ci = &core->bus->chipinfo;
-+ u8 imode;
-+
-+ if (ci->id == BCMA_CHIP_ID_BCM4707 ||
-+ ci->id == BCMA_CHIP_ID_BCM53018) {
-+ bcma_awrite32(core, BCMA_IOCTL,
-+ bcma_aread32(core, BCMA_IOCTL) | 0x40 |
-+ BGMAC_BCMA_IOCTL_SW_CLKEN);
-+ bgmac->mac_speed = SPEED_2500;
- bgmac->mac_duplex = DUPLEX_FULL;
- bgmac_mac_speed(bgmac);
-+ } else {
-+ imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
-+ BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
-+ if (imode == 0 || imode == 1) {
-+ bgmac->mac_speed = SPEED_100;
-+ bgmac->mac_duplex = DUPLEX_FULL;
-+ bgmac_mac_speed(bgmac);
-+ }
- }
- }
-
-@@ -886,9 +903,14 @@ static void bgmac_chip_reset(struct bgma
- flags |= BGMAC_BCMA_IOCTL_SW_RESET;
- }
-
-- bcma_core_enable(core, flags);
--
-- if (core->id.rev > 2) {
-+ /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
-+ if (ci->id != BCMA_CHIP_ID_BCM4707)
-+ bcma_core_enable(core, flags);
-+
-+ /* Request Misc PLL for corerev > 2 */
-+ if (core->id.rev > 2 &&
-+ ci->id != BCMA_CHIP_ID_BCM4707 &&
-+ ci->id != BCMA_CHIP_ID_BCM53018) {
- bgmac_set(bgmac, BCMA_CLKCTLST,
- BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
- bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
-@@ -1026,12 +1048,16 @@ static void bgmac_enable(struct bgmac *b
- break;
- }
-
-- rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
-- rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
-- bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
-- mdp = (bp_clk * 128 / 1000) - 3;
-- rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
-- bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
-+ if (ci->id != BCMA_CHIP_ID_BCM4707 &&
-+ ci->id != BCMA_CHIP_ID_BCM53018) {
-+ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
-+ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
-+ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
-+ 1000000;
-+ mdp = (bp_clk * 128 / 1000) - 3;
-+ rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
-+ bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
-+ }
- }
-
- /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
-@@ -1366,6 +1392,7 @@ static int bgmac_probe(struct bcma_devic
- struct bgmac *bgmac;
- struct ssb_sprom *sprom = &core->bus->sprom;
- u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
-+ struct bcma_chipinfo *ci = &core->bus->chipinfo;
- int err;
-
- /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
-@@ -1404,8 +1431,16 @@ static int bgmac_probe(struct bcma_devic
- }
- bgmac->cmn = core->bus->drv_gmac_cmn.core;
-
-- bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
-- sprom->et0phyaddr;
-+ /*
-+ * Too much can go wrong in scanning MDC/MDIO playing "whos my phy?" .
-+ * Instead, explicitly use the phy address 30.
-+ */
-+ if (ci->id == BCMA_CHIP_ID_BCM4707 || ci->id == BCMA_CHIP_ID_BCM53018)
-+ bgmac->phyaddr = BGMAC_PHY_NOREGS;
-+ else
-+ bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
-+ sprom->et0phyaddr;
-+
- bgmac->phyaddr &= BGMAC_PHY_MASK;
- if (bgmac->phyaddr == BGMAC_PHY_MASK) {
- bgmac_err(bgmac, "No PHY found\n");
-@@ -1423,6 +1458,27 @@ static int bgmac_probe(struct bcma_devic
-
- bgmac_chip_reset(bgmac);
-
-+ /* For Northstar, we have to take all GMAC core out of reset */
-+ if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
-+ core->id.id == BCMA_CHIP_ID_BCM53018) {
-+ struct bcma_device *ns_core;
-+ int ns_gmac;
-+
-+ /* Northstar has 4 GMAC cores */
-+ for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
-+ /* As northstar requirement, we have to reset all GAMCs
-+ * before accessing one. bgmac_chip_reset() call
-+ * bcma_core_enable() for this core. Then the other
-+ * three GAMCs didn't reset. We do it here.
-+ */
-+ ns_core = bcma_find_core_unit(core->bus,
-+ BCMA_CORE_MAC_GBIT,
-+ ns_gmac);
-+ if (ns_core && !bcma_core_is_enabled(ns_core))
-+ bcma_core_enable(ns_core, 0);
-+ }
-+ }
-+
- err = bgmac_dma_alloc(bgmac);
- if (err) {
- bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -189,6 +189,7 @@
- #define BGMAC_CMDCFG_ES_10 0x00000000
- #define BGMAC_CMDCFG_ES_100 0x00000004
- #define BGMAC_CMDCFG_ES_1000 0x00000008
-+#define BGMAC_CMDCFG_ES_2500 0x0000000C
- #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
- #define BGMAC_CMDCFG_PAD_EN 0x00000020
- #define BGMAC_CMDCFG_CF 0x00000040
#include <bcm47xx_nvram.h>
static const struct bcma_device_id bgmac_bcma_tbl[] = {
-@@ -1381,6 +1382,17 @@ static void bgmac_mii_unregister(struct
+@@ -1405,6 +1406,17 @@ static void bgmac_mii_unregister(struct
mdiobus_free(mii_bus);
}
/**************************************************
* BCMA bus ops
**************************************************/
-@@ -1507,6 +1519,16 @@ static int bgmac_probe(struct bcma_devic
+@@ -1521,6 +1533,16 @@ static int bgmac_probe(struct bcma_devic
goto err_dma_free;
}
err = register_netdev(bgmac->net_dev);
if (err) {
bgmac_err(bgmac, "Cannot register net device\n");
-@@ -1536,6 +1558,10 @@ static void bgmac_remove(struct bcma_dev
+@@ -1549,6 +1571,10 @@ static void bgmac_remove(struct bcma_dev
{
struct bgmac *bgmac = bcma_get_drvdata(core);
bgmac_mii_unregister(bgmac);
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -405,6 +405,9 @@ struct bgmac {
+@@ -457,6 +457,9 @@ struct bgmac {
bool has_robosw;
bool loopback;
+++ /dev/null
-From adada33c4ee27efdec0b08e43768a68285a5710d Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Thu, 2 Jan 2014 19:49:56 +0100
-Subject: [PATCH 2/5] bgmac: initialize the DMA controller of core rev >= 4
-
-The DMA controller used in the device supported by GMAC with core rev
->= 4 has some new options which are now set to the default values used
-in the Broadcom SDK.
-
-Subject: [PATCH 3/5] bgmac: add support for new BGMAC_CMDCFG_SR position on
- core rev >= 4
-
-The BGMAC_CMDCFG_SR register is at a different position on core rev >= 4
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -97,6 +97,19 @@ static void bgmac_dma_tx_enable(struct b
- u32 ctl;
-
- ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
-+ if (bgmac->core->id.rev >= 4) {
-+ ctl &= ~BGMAC_DMA_TX_BL_MASK;
-+ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
-+
-+ ctl &= ~BGMAC_DMA_TX_MR_MASK;
-+ ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
-+
-+ ctl &= ~BGMAC_DMA_TX_PC_MASK;
-+ ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
-+
-+ ctl &= ~BGMAC_DMA_TX_PT_MASK;
-+ ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
-+ }
- ctl |= BGMAC_DMA_TX_ENABLE;
- ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
- bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
-@@ -241,6 +254,16 @@ static void bgmac_dma_rx_enable(struct b
- u32 ctl;
-
- ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
-+ if (bgmac->core->id.rev >= 4) {
-+ ctl &= ~BGMAC_DMA_RX_BL_MASK;
-+ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
-+
-+ ctl &= ~BGMAC_DMA_RX_PC_MASK;
-+ ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
-+
-+ ctl &= ~BGMAC_DMA_RX_PT_MASK;
-+ ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
-+ }
- ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
- ctl |= BGMAC_DMA_RX_ENABLE;
- ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
-@@ -746,13 +769,13 @@ static void bgmac_cmdcfg_maskset(struct
- u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
- u32 new_val = (cmdcfg & mask) | set;
-
-- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
-+ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
- udelay(2);
-
- if (new_val != cmdcfg || force)
- bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
-
-- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
-+ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
- udelay(2);
- }
-
-@@ -977,7 +1000,7 @@ static void bgmac_chip_reset(struct bgma
- BGMAC_CMDCFG_PROM |
- BGMAC_CMDCFG_NLC |
- BGMAC_CMDCFG_CFE |
-- BGMAC_CMDCFG_SR,
-+ BGMAC_CMDCFG_SR(core->id.rev),
- false);
- bgmac->mac_speed = SPEED_UNKNOWN;
- bgmac->mac_duplex = DUPLEX_UNKNOWN;
-@@ -1020,7 +1043,7 @@ static void bgmac_enable(struct bgmac *b
-
- cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
- bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
-- BGMAC_CMDCFG_SR, true);
-+ BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
- udelay(2);
- cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
- bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -198,7 +198,9 @@
- #define BGMAC_CMDCFG_TAI 0x00000200
- #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
- #define BGMAC_CMDCFG_HD_SHIFT 10
--#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
-+#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */
-+#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
-+#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
- #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
- #define BGMAC_CMDCFG_AE 0x00400000
- #define BGMAC_CMDCFG_CFE 0x00800000
-@@ -238,9 +240,34 @@
- #define BGMAC_DMA_TX_SUSPEND 0x00000002
- #define BGMAC_DMA_TX_LOOPBACK 0x00000004
- #define BGMAC_DMA_TX_FLUSH 0x00000010
-+#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
-+#define BGMAC_DMA_TX_MR_SHIFT 6
-+#define BGMAC_DMA_TX_MR_1 0
-+#define BGMAC_DMA_TX_MR_2 1
- #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
- #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
- #define BGMAC_DMA_TX_ADDREXT_SHIFT 16
-+#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
-+#define BGMAC_DMA_TX_BL_SHIFT 18
-+#define BGMAC_DMA_TX_BL_16 0
-+#define BGMAC_DMA_TX_BL_32 1
-+#define BGMAC_DMA_TX_BL_64 2
-+#define BGMAC_DMA_TX_BL_128 3
-+#define BGMAC_DMA_TX_BL_256 4
-+#define BGMAC_DMA_TX_BL_512 5
-+#define BGMAC_DMA_TX_BL_1024 6
-+#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
-+#define BGMAC_DMA_TX_PC_SHIFT 21
-+#define BGMAC_DMA_TX_PC_0 0
-+#define BGMAC_DMA_TX_PC_4 1
-+#define BGMAC_DMA_TX_PC_8 2
-+#define BGMAC_DMA_TX_PC_16 3
-+#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
-+#define BGMAC_DMA_TX_PT_SHIFT 24
-+#define BGMAC_DMA_TX_PT_1 0
-+#define BGMAC_DMA_TX_PT_2 1
-+#define BGMAC_DMA_TX_PT_4 2
-+#define BGMAC_DMA_TX_PT_8 3
- #define BGMAC_DMA_TX_INDEX 0x04
- #define BGMAC_DMA_TX_RINGLO 0x08
- #define BGMAC_DMA_TX_RINGHI 0x0C
-@@ -268,8 +295,33 @@
- #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
- #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
- #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
-+#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
-+#define BGMAC_DMA_RX_MR_SHIFT 6
-+#define BGMAC_DMA_TX_MR_1 0
-+#define BGMAC_DMA_TX_MR_2 1
- #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
- #define BGMAC_DMA_RX_ADDREXT_SHIFT 16
-+#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
-+#define BGMAC_DMA_RX_BL_SHIFT 18
-+#define BGMAC_DMA_RX_BL_16 0
-+#define BGMAC_DMA_RX_BL_32 1
-+#define BGMAC_DMA_RX_BL_64 2
-+#define BGMAC_DMA_RX_BL_128 3
-+#define BGMAC_DMA_RX_BL_256 4
-+#define BGMAC_DMA_RX_BL_512 5
-+#define BGMAC_DMA_RX_BL_1024 6
-+#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
-+#define BGMAC_DMA_RX_PC_SHIFT 21
-+#define BGMAC_DMA_RX_PC_0 0
-+#define BGMAC_DMA_RX_PC_4 1
-+#define BGMAC_DMA_RX_PC_8 2
-+#define BGMAC_DMA_RX_PC_16 3
-+#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
-+#define BGMAC_DMA_RX_PT_SHIFT 24
-+#define BGMAC_DMA_RX_PT_1 0
-+#define BGMAC_DMA_RX_PT_2 1
-+#define BGMAC_DMA_RX_PT_4 2
-+#define BGMAC_DMA_RX_PT_8 3
- #define BGMAC_DMA_RX_INDEX 0x24
- #define BGMAC_DMA_RX_RINGLO 0x28
- #define BGMAC_DMA_RX_RINGHI 0x2C
-patches for bgmac backported from net-next/master
-
+--- a/drivers/net/ethernet/broadcom/Kconfig
++++ b/drivers/net/ethernet/broadcom/Kconfig
+@@ -23,6 +23,7 @@ config B44
+ depends on SSB_POSSIBLE && HAS_DMA
+ select SSB
+ select MII
++ select PHYLIB
+ ---help---
+ If you have a network (Ethernet) controller of this type, say Y
+ or M and read the Ethernet-HOWTO, available from
--- a/drivers/net/ethernet/broadcom/bgmac.c
+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -149,6 +149,8 @@ static netdev_tx_t bgmac_dma_tx_add(stru
+@@ -96,6 +96,19 @@ static void bgmac_dma_tx_enable(struct b
+ u32 ctl;
+
+ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
++ if (bgmac->core->id.rev >= 4) {
++ ctl &= ~BGMAC_DMA_TX_BL_MASK;
++ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
++
++ ctl &= ~BGMAC_DMA_TX_MR_MASK;
++ ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
++
++ ctl &= ~BGMAC_DMA_TX_PC_MASK;
++ ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
++
++ ctl &= ~BGMAC_DMA_TX_PT_MASK;
++ ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
++ }
+ ctl |= BGMAC_DMA_TX_ENABLE;
+ ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
+ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
+@@ -149,6 +162,8 @@ static netdev_tx_t bgmac_dma_tx_add(stru
dma_desc->ctl0 = cpu_to_le32(ctl0);
dma_desc->ctl1 = cpu_to_le32(ctl1);
wmb();
/* Increase ring->end to point empty slot. We tell hardware the first
-@@ -178,6 +180,7 @@ static void bgmac_dma_tx_free(struct bgm
+@@ -178,6 +193,7 @@ static void bgmac_dma_tx_free(struct bgm
struct device *dma_dev = bgmac->core->dma_dev;
int empty_slot;
bool freed = false;
/* The last slot that hardware didn't consume yet */
empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
-@@ -195,6 +198,9 @@ static void bgmac_dma_tx_free(struct bgm
+@@ -195,6 +211,9 @@ static void bgmac_dma_tx_free(struct bgm
slot->skb->len, DMA_TO_DEVICE);
slot->dma_addr = 0;
/* Free memory! :) */
dev_kfree_skb(slot->skb);
slot->skb = NULL;
-@@ -208,6 +214,8 @@ static void bgmac_dma_tx_free(struct bgm
+@@ -208,6 +227,8 @@ static void bgmac_dma_tx_free(struct bgm
freed = true;
}
if (freed && netif_queue_stopped(bgmac->net_dev))
netif_wake_queue(bgmac->net_dev);
}
-@@ -244,31 +252,59 @@ static int bgmac_dma_rx_skb_for_slot(str
+@@ -232,6 +253,16 @@ static void bgmac_dma_rx_enable(struct b
+ u32 ctl;
+
+ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
++ if (bgmac->core->id.rev >= 4) {
++ ctl &= ~BGMAC_DMA_RX_BL_MASK;
++ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
++
++ ctl &= ~BGMAC_DMA_RX_PC_MASK;
++ ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
++
++ ctl &= ~BGMAC_DMA_RX_PT_MASK;
++ ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
++ }
+ ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
+ ctl |= BGMAC_DMA_RX_ENABLE;
+ ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
+@@ -244,31 +275,59 @@ static int bgmac_dma_rx_skb_for_slot(str
struct bgmac_slot_info *slot)
{
struct device *dma_dev = bgmac->core->dma_dev;
static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
int weight)
{
-@@ -287,7 +323,6 @@ static int bgmac_dma_rx_read(struct bgma
+@@ -287,7 +346,6 @@ static int bgmac_dma_rx_read(struct bgma
struct device *dma_dev = bgmac->core->dma_dev;
struct bgmac_slot_info *slot = &ring->slots[ring->start];
struct sk_buff *skb = slot->skb;
struct bgmac_rx_header *rx;
u16 len, flags;
-@@ -300,38 +335,51 @@ static int bgmac_dma_rx_read(struct bgma
+@@ -300,38 +358,51 @@ static int bgmac_dma_rx_read(struct bgma
len = le16_to_cpu(rx->len);
flags = le16_to_cpu(rx->flags);
if (++ring->start >= BGMAC_RX_RING_SLOTS)
ring->start = 0;
-@@ -495,8 +543,6 @@ err_dma_free:
+@@ -495,8 +566,6 @@ err_dma_free:
static void bgmac_dma_init(struct bgmac *bgmac)
{
struct bgmac_dma_ring *ring;
int i;
for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
-@@ -529,23 +575,8 @@ static void bgmac_dma_init(struct bgmac
+@@ -529,23 +598,8 @@ static void bgmac_dma_init(struct bgmac
if (ring->unaligned)
bgmac_dma_rx_enable(bgmac, ring);
bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
ring->index_base +
-@@ -988,6 +1019,8 @@ static void bgmac_chip_reset(struct bgma
+@@ -651,70 +705,6 @@ static int bgmac_phy_write(struct bgmac
+ return 0;
+ }
+
+-/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */
+-static void bgmac_phy_force(struct bgmac *bgmac)
+-{
+- u16 ctl;
+- u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB |
+- BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX);
+-
+- if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
+- return;
+-
+- if (bgmac->autoneg)
+- return;
+-
+- ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL);
+- ctl &= mask;
+- if (bgmac->full_duplex)
+- ctl |= BGMAC_PHY_CTL_DUPLEX;
+- if (bgmac->speed == BGMAC_SPEED_100)
+- ctl |= BGMAC_PHY_CTL_SPEED_100;
+- else if (bgmac->speed == BGMAC_SPEED_1000)
+- ctl |= BGMAC_PHY_CTL_SPEED_1000;
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl);
+-}
+-
+-/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyadvertise */
+-static void bgmac_phy_advertise(struct bgmac *bgmac)
+-{
+- u16 adv;
+-
+- if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
+- return;
+-
+- if (!bgmac->autoneg)
+- return;
+-
+- /* Adv selected 10/100 speeds */
+- adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV);
+- adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL |
+- BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL);
+- if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
+- adv |= BGMAC_PHY_ADV_10HALF;
+- if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
+- adv |= BGMAC_PHY_ADV_100HALF;
+- if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
+- adv |= BGMAC_PHY_ADV_10FULL;
+- if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
+- adv |= BGMAC_PHY_ADV_100FULL;
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv);
+-
+- /* Adv selected 1000 speeds */
+- adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2);
+- adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL);
+- if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
+- adv |= BGMAC_PHY_ADV2_1000HALF;
+- if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
+- adv |= BGMAC_PHY_ADV2_1000FULL;
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv);
+-
+- /* Restart */
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
+- bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) |
+- BGMAC_PHY_CTL_RESTART);
+-}
+-
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
+ static void bgmac_phy_init(struct bgmac *bgmac)
+ {
+@@ -758,11 +748,9 @@ static void bgmac_phy_reset(struct bgmac
+ if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
+ return;
+
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
+- BGMAC_PHY_CTL_RESET);
++ bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
+ udelay(100);
+- if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
+- BGMAC_PHY_CTL_RESET)
++ if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
+ bgmac_err(bgmac, "PHY reset failed\n");
+ bgmac_phy_init(bgmac);
+ }
+@@ -780,13 +768,13 @@ static void bgmac_cmdcfg_maskset(struct
+ u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
+ u32 new_val = (cmdcfg & mask) | set;
+
+- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
++ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
+ udelay(2);
+
+ if (new_val != cmdcfg || force)
+ bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
+
+- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
++ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
+ udelay(2);
+ }
+
+@@ -845,31 +833,56 @@ static void bgmac_clear_mib(struct bgmac
+ }
+
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
+-static void bgmac_speed(struct bgmac *bgmac, int speed)
++static void bgmac_mac_speed(struct bgmac *bgmac)
+ {
+ u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
+ u32 set = 0;
+
+- if (speed & BGMAC_SPEED_10)
++ switch (bgmac->mac_speed) {
++ case SPEED_10:
+ set |= BGMAC_CMDCFG_ES_10;
+- if (speed & BGMAC_SPEED_100)
++ break;
++ case SPEED_100:
+ set |= BGMAC_CMDCFG_ES_100;
+- if (speed & BGMAC_SPEED_1000)
++ break;
++ case SPEED_1000:
+ set |= BGMAC_CMDCFG_ES_1000;
+- if (!bgmac->full_duplex)
++ break;
++ case SPEED_2500:
++ set |= BGMAC_CMDCFG_ES_2500;
++ break;
++ default:
++ bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
++ }
++
++ if (bgmac->mac_duplex == DUPLEX_HALF)
+ set |= BGMAC_CMDCFG_HD;
++
+ bgmac_cmdcfg_maskset(bgmac, mask, set, true);
+ }
+
+ static void bgmac_miiconfig(struct bgmac *bgmac)
+ {
+- u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
+- BGMAC_DS_MM_SHIFT;
+- if (imode == 0 || imode == 1) {
+- if (bgmac->autoneg)
+- bgmac_speed(bgmac, BGMAC_SPEED_100);
+- else
+- bgmac_speed(bgmac, bgmac->speed);
++ struct bcma_device *core = bgmac->core;
++ struct bcma_chipinfo *ci = &core->bus->chipinfo;
++ u8 imode;
++
++ if (ci->id == BCMA_CHIP_ID_BCM4707 ||
++ ci->id == BCMA_CHIP_ID_BCM53018) {
++ bcma_awrite32(core, BCMA_IOCTL,
++ bcma_aread32(core, BCMA_IOCTL) | 0x40 |
++ BGMAC_BCMA_IOCTL_SW_CLKEN);
++ bgmac->mac_speed = SPEED_2500;
++ bgmac->mac_duplex = DUPLEX_FULL;
++ bgmac_mac_speed(bgmac);
++ } else {
++ imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
++ BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
++ if (imode == 0 || imode == 1) {
++ bgmac->mac_speed = SPEED_100;
++ bgmac->mac_duplex = DUPLEX_FULL;
++ bgmac_mac_speed(bgmac);
++ }
+ }
+ }
+
+@@ -879,7 +892,7 @@ static void bgmac_chip_reset(struct bgma
+ struct bcma_device *core = bgmac->core;
+ struct bcma_bus *bus = core->bus;
+ struct bcma_chipinfo *ci = &bus->chipinfo;
+- u32 flags = 0;
++ u32 flags;
+ u32 iost;
+ int i;
+
+@@ -902,26 +915,36 @@ static void bgmac_chip_reset(struct bgma
+ }
+
+ iost = bcma_aread32(core, BCMA_IOST);
+- if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) ||
++ if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
+ (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
+- (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9))
++ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
+ iost &= ~BGMAC_BCMA_IOST_ATTACHED;
+
+- if (iost & BGMAC_BCMA_IOST_ATTACHED) {
+- flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
+- if (!bgmac->has_robosw)
+- flags |= BGMAC_BCMA_IOCTL_SW_RESET;
++ /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
++ if (ci->id != BCMA_CHIP_ID_BCM4707) {
++ flags = 0;
++ if (iost & BGMAC_BCMA_IOST_ATTACHED) {
++ flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
++ if (!bgmac->has_robosw)
++ flags |= BGMAC_BCMA_IOCTL_SW_RESET;
++ }
++ bcma_core_enable(core, flags);
+ }
+
+- bcma_core_enable(core, flags);
+-
+- if (core->id.rev > 2) {
+- bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
+- bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
++ /* Request Misc PLL for corerev > 2 */
++ if (core->id.rev > 2 &&
++ ci->id != BCMA_CHIP_ID_BCM4707 &&
++ ci->id != BCMA_CHIP_ID_BCM53018) {
++ bgmac_set(bgmac, BCMA_CLKCTLST,
++ BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
++ bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
++ BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
++ BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
+ 1000);
+ }
+
+- if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 ||
++ if (ci->id == BCMA_CHIP_ID_BCM5357 ||
++ ci->id == BCMA_CHIP_ID_BCM4749 ||
+ ci->id == BCMA_CHIP_ID_BCM53572) {
+ struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
+ u8 et_swtype = 0;
+@@ -936,10 +959,11 @@ static void bgmac_chip_reset(struct bgma
+ et_swtype &= 0x0f;
+ et_swtype <<= 4;
+ sw_type = et_swtype;
+- } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
++ } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
+ sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
+- } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
+- (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
++ } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
++ (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
++ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
+ sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
+ BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
+ }
+@@ -976,8 +1000,10 @@ static void bgmac_chip_reset(struct bgma
+ BGMAC_CMDCFG_PROM |
+ BGMAC_CMDCFG_NLC |
+ BGMAC_CMDCFG_CFE |
+- BGMAC_CMDCFG_SR,
++ BGMAC_CMDCFG_SR(core->id.rev),
+ false);
++ bgmac->mac_speed = SPEED_UNKNOWN;
++ bgmac->mac_duplex = DUPLEX_UNKNOWN;
+
+ bgmac_clear_mib(bgmac);
+ if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
+@@ -988,6 +1014,8 @@ static void bgmac_chip_reset(struct bgma
bgmac_miiconfig(bgmac);
bgmac_phy_init(bgmac);
bgmac->int_status = 0;
}
+@@ -1015,7 +1043,7 @@ static void bgmac_enable(struct bgmac *b
+
+ cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
+ bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
+- BGMAC_CMDCFG_SR, true);
++ BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
+ udelay(2);
+ cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
+ bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
+@@ -1044,12 +1072,16 @@ static void bgmac_enable(struct bgmac *b
+ break;
+ }
+
+- rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
+- rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
+- bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
+- mdp = (bp_clk * 128 / 1000) - 3;
+- rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
+- bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
++ if (ci->id != BCMA_CHIP_ID_BCM4707 &&
++ ci->id != BCMA_CHIP_ID_BCM53018) {
++ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
++ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
++ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
++ 1000000;
++ mdp = (bp_clk * 128 / 1000) - 3;
++ rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
++ bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
++ }
+ }
+
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
+@@ -1075,13 +1107,6 @@ static void bgmac_chip_init(struct bgmac
+
+ bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
+
+- if (!bgmac->autoneg) {
+- bgmac_speed(bgmac, bgmac->speed);
+- bgmac_phy_force(bgmac);
+- } else if (bgmac->speed) { /* if there is anything to adv */
+- bgmac_phy_advertise(bgmac);
+- }
+-
+ if (full_init) {
+ bgmac_dma_init(bgmac);
+ if (1) /* FIXME: is there any case we don't want IRQs? */
+@@ -1171,6 +1196,8 @@ static int bgmac_open(struct net_device
+ }
+ napi_enable(&bgmac->napi);
+
++ phy_start(bgmac->phy_dev);
++
+ netif_carrier_on(net_dev);
+
+ err_out:
+@@ -1183,6 +1210,8 @@ static int bgmac_stop(struct net_device
+
+ netif_carrier_off(net_dev);
+
++ phy_stop(bgmac->phy_dev);
++
+ napi_disable(&bgmac->napi);
+ bgmac_chip_intrs_off(bgmac);
+ free_irq(bgmac->core->irq, net_dev);
+@@ -1219,27 +1248,11 @@ static int bgmac_set_mac_address(struct
+ static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
+ {
+ struct bgmac *bgmac = netdev_priv(net_dev);
+- struct mii_ioctl_data *data = if_mii(ifr);
+
+- switch (cmd) {
+- case SIOCGMIIPHY:
+- data->phy_id = bgmac->phyaddr;
+- /* fallthru */
+- case SIOCGMIIREG:
+- if (!netif_running(net_dev))
+- return -EAGAIN;
+- data->val_out = bgmac_phy_read(bgmac, data->phy_id,
+- data->reg_num & 0x1f);
+- return 0;
+- case SIOCSMIIREG:
+- if (!netif_running(net_dev))
+- return -EAGAIN;
+- bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
+- data->val_in);
+- return 0;
+- default:
+- return -EOPNOTSUPP;
+- }
++ if (!netif_running(net_dev))
++ return -EINVAL;
++
++ return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
+ }
+
+ static const struct net_device_ops bgmac_netdev_ops = {
+@@ -1261,61 +1274,16 @@ static int bgmac_get_settings(struct net
+ {
+ struct bgmac *bgmac = netdev_priv(net_dev);
+
+- cmd->supported = SUPPORTED_10baseT_Half |
+- SUPPORTED_10baseT_Full |
+- SUPPORTED_100baseT_Half |
+- SUPPORTED_100baseT_Full |
+- SUPPORTED_1000baseT_Half |
+- SUPPORTED_1000baseT_Full |
+- SUPPORTED_Autoneg;
+-
+- if (bgmac->autoneg) {
+- WARN_ON(cmd->advertising);
+- if (bgmac->full_duplex) {
+- if (bgmac->speed & BGMAC_SPEED_10)
+- cmd->advertising |= ADVERTISED_10baseT_Full;
+- if (bgmac->speed & BGMAC_SPEED_100)
+- cmd->advertising |= ADVERTISED_100baseT_Full;
+- if (bgmac->speed & BGMAC_SPEED_1000)
+- cmd->advertising |= ADVERTISED_1000baseT_Full;
+- } else {
+- if (bgmac->speed & BGMAC_SPEED_10)
+- cmd->advertising |= ADVERTISED_10baseT_Half;
+- if (bgmac->speed & BGMAC_SPEED_100)
+- cmd->advertising |= ADVERTISED_100baseT_Half;
+- if (bgmac->speed & BGMAC_SPEED_1000)
+- cmd->advertising |= ADVERTISED_1000baseT_Half;
+- }
+- } else {
+- switch (bgmac->speed) {
+- case BGMAC_SPEED_10:
+- ethtool_cmd_speed_set(cmd, SPEED_10);
+- break;
+- case BGMAC_SPEED_100:
+- ethtool_cmd_speed_set(cmd, SPEED_100);
+- break;
+- case BGMAC_SPEED_1000:
+- ethtool_cmd_speed_set(cmd, SPEED_1000);
+- break;
+- }
+- }
+-
+- cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
+-
+- cmd->autoneg = bgmac->autoneg;
+-
+- return 0;
++ return phy_ethtool_gset(bgmac->phy_dev, cmd);
+ }
+
+-#if 0
+ static int bgmac_set_settings(struct net_device *net_dev,
+ struct ethtool_cmd *cmd)
+ {
+ struct bgmac *bgmac = netdev_priv(net_dev);
+
+- return -1;
++ return phy_ethtool_sset(bgmac->phy_dev, cmd);
+ }
+-#endif
+
+ static void bgmac_get_drvinfo(struct net_device *net_dev,
+ struct ethtool_drvinfo *info)
+@@ -1326,6 +1294,7 @@ static void bgmac_get_drvinfo(struct net
+
+ static const struct ethtool_ops bgmac_ethtool_ops = {
+ .get_settings = bgmac_get_settings,
++ .set_settings = bgmac_set_settings,
+ .get_drvinfo = bgmac_get_drvinfo,
+ };
+
+@@ -1344,9 +1313,35 @@ static int bgmac_mii_write(struct mii_bu
+ return bgmac_phy_write(bus->priv, mii_id, regnum, value);
+ }
+
++static void bgmac_adjust_link(struct net_device *net_dev)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++ struct phy_device *phy_dev = bgmac->phy_dev;
++ bool update = false;
++
++ if (phy_dev->link) {
++ if (phy_dev->speed != bgmac->mac_speed) {
++ bgmac->mac_speed = phy_dev->speed;
++ update = true;
++ }
++
++ if (phy_dev->duplex != bgmac->mac_duplex) {
++ bgmac->mac_duplex = phy_dev->duplex;
++ update = true;
++ }
++ }
++
++ if (update) {
++ bgmac_mac_speed(bgmac);
++ phy_print_status(phy_dev);
++ }
++}
++
+ static int bgmac_mii_register(struct bgmac *bgmac)
+ {
+ struct mii_bus *mii_bus;
++ struct phy_device *phy_dev;
++ char bus_id[MII_BUS_ID_SIZE + 3];
+ int i, err = 0;
+
+ mii_bus = mdiobus_alloc();
+@@ -1378,8 +1373,22 @@ static int bgmac_mii_register(struct bgm
+
+ bgmac->mii_bus = mii_bus;
+
++ /* Connect to the PHY */
++ snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
++ bgmac->phyaddr);
++ phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
++ PHY_INTERFACE_MODE_MII);
++ if (IS_ERR(phy_dev)) {
++ bgmac_err(bgmac, "PHY connecton failed\n");
++ err = PTR_ERR(phy_dev);
++ goto err_unregister_bus;
++ }
++ bgmac->phy_dev = phy_dev;
++
+ return err;
+
++err_unregister_bus:
++ mdiobus_unregister(mii_bus);
+ err_free_irq:
+ kfree(mii_bus->irq);
+ err_free_bus:
+@@ -1434,9 +1443,6 @@ static int bgmac_probe(struct bcma_devic
+ bcma_set_drvdata(core, bgmac);
+
+ /* Defaults */
+- bgmac->autoneg = true;
+- bgmac->full_duplex = true;
+- bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000;
+ memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
+
+ /* On BCM4706 we need common core to access PHY */
+@@ -1467,6 +1473,27 @@ static int bgmac_probe(struct bcma_devic
+
+ bgmac_chip_reset(bgmac);
+
++ /* For Northstar, we have to take all GMAC core out of reset */
++ if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
++ core->id.id == BCMA_CHIP_ID_BCM53018) {
++ struct bcma_device *ns_core;
++ int ns_gmac;
++
++ /* Northstar has 4 GMAC cores */
++ for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
++ /* As Northstar requirement, we have to reset all GMACs
++ * before accessing one. bgmac_chip_reset() call
++ * bcma_core_enable() for this core. Then the other
++ * three GMACs didn't reset. We do it here.
++ */
++ ns_core = bcma_find_core_unit(core->bus,
++ BCMA_CORE_MAC_GBIT,
++ ns_gmac);
++ if (ns_core && !bcma_core_is_enabled(ns_core))
++ bcma_core_enable(ns_core, 0);
++ }
++ }
++
+ err = bgmac_dma_alloc(bgmac);
+ if (err) {
+ bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
+@@ -1491,14 +1518,12 @@ static int bgmac_probe(struct bcma_devic
+ err = bgmac_mii_register(bgmac);
+ if (err) {
+ bgmac_err(bgmac, "Cannot register MDIO\n");
+- err = -ENOTSUPP;
+ goto err_dma_free;
+ }
+
+ err = register_netdev(bgmac->net_dev);
+ if (err) {
+ bgmac_err(bgmac, "Cannot register net device\n");
+- err = -ENOTSUPP;
+ goto err_mii_unregister;
+ }
+
+--- a/drivers/net/ethernet/broadcom/bgmac.h
++++ b/drivers/net/ethernet/broadcom/bgmac.h
+@@ -95,7 +95,11 @@
+ #define BGMAC_RXQ_CTL_MDP_SHIFT 24
+ #define BGMAC_GPIO_SELECT 0x194
+ #define BGMAC_GPIO_OUTPUT_EN 0x198
+-/* For 0x1e0 see BCMA_CLKCTLST */
++
++/* For 0x1e0 see BCMA_CLKCTLST. Below are BGMAC specific bits */
++#define BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ 0x00000100
++#define BGMAC_BCMA_CLKCTLST_MISC_PLL_ST 0x01000000
++
+ #define BGMAC_HW_WAR 0x1e4
+ #define BGMAC_PWR_CTL 0x1e8
+ #define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */
+@@ -185,6 +189,7 @@
+ #define BGMAC_CMDCFG_ES_10 0x00000000
+ #define BGMAC_CMDCFG_ES_100 0x00000004
+ #define BGMAC_CMDCFG_ES_1000 0x00000008
++#define BGMAC_CMDCFG_ES_2500 0x0000000C
+ #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
+ #define BGMAC_CMDCFG_PAD_EN 0x00000020
+ #define BGMAC_CMDCFG_CF 0x00000040
+@@ -193,7 +198,9 @@
+ #define BGMAC_CMDCFG_TAI 0x00000200
+ #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
+ #define BGMAC_CMDCFG_HD_SHIFT 10
+-#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
++#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */
++#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
++#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
+ #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
+ #define BGMAC_CMDCFG_AE 0x00400000
+ #define BGMAC_CMDCFG_CFE 0x00800000
+@@ -216,27 +223,6 @@
+ #define BGMAC_RX_STATUS 0xb38
+ #define BGMAC_TX_STATUS 0xb3c
+
+-#define BGMAC_PHY_CTL 0x00
+-#define BGMAC_PHY_CTL_SPEED_MSB 0x0040
+-#define BGMAC_PHY_CTL_DUPLEX 0x0100 /* duplex mode */
+-#define BGMAC_PHY_CTL_RESTART 0x0200 /* restart autonegotiation */
+-#define BGMAC_PHY_CTL_ANENAB 0x1000 /* enable autonegotiation */
+-#define BGMAC_PHY_CTL_SPEED 0x2000
+-#define BGMAC_PHY_CTL_LOOP 0x4000 /* loopback */
+-#define BGMAC_PHY_CTL_RESET 0x8000 /* reset */
+-/* Helpers */
+-#define BGMAC_PHY_CTL_SPEED_10 0
+-#define BGMAC_PHY_CTL_SPEED_100 BGMAC_PHY_CTL_SPEED
+-#define BGMAC_PHY_CTL_SPEED_1000 BGMAC_PHY_CTL_SPEED_MSB
+-#define BGMAC_PHY_ADV 0x04
+-#define BGMAC_PHY_ADV_10HALF 0x0020 /* advertise 10MBits/s half duplex */
+-#define BGMAC_PHY_ADV_10FULL 0x0040 /* advertise 10MBits/s full duplex */
+-#define BGMAC_PHY_ADV_100HALF 0x0080 /* advertise 100MBits/s half duplex */
+-#define BGMAC_PHY_ADV_100FULL 0x0100 /* advertise 100MBits/s full duplex */
+-#define BGMAC_PHY_ADV2 0x09
+-#define BGMAC_PHY_ADV2_1000HALF 0x0100 /* advertise 1000MBits/s half duplex */
+-#define BGMAC_PHY_ADV2_1000FULL 0x0200 /* advertise 1000MBits/s full duplex */
+-
+ /* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
+ #define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
+ #define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */
+@@ -254,9 +240,34 @@
+ #define BGMAC_DMA_TX_SUSPEND 0x00000002
+ #define BGMAC_DMA_TX_LOOPBACK 0x00000004
+ #define BGMAC_DMA_TX_FLUSH 0x00000010
++#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
++#define BGMAC_DMA_TX_MR_SHIFT 6
++#define BGMAC_DMA_TX_MR_1 0
++#define BGMAC_DMA_TX_MR_2 1
+ #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
+ #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
+ #define BGMAC_DMA_TX_ADDREXT_SHIFT 16
++#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
++#define BGMAC_DMA_TX_BL_SHIFT 18
++#define BGMAC_DMA_TX_BL_16 0
++#define BGMAC_DMA_TX_BL_32 1
++#define BGMAC_DMA_TX_BL_64 2
++#define BGMAC_DMA_TX_BL_128 3
++#define BGMAC_DMA_TX_BL_256 4
++#define BGMAC_DMA_TX_BL_512 5
++#define BGMAC_DMA_TX_BL_1024 6
++#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
++#define BGMAC_DMA_TX_PC_SHIFT 21
++#define BGMAC_DMA_TX_PC_0 0
++#define BGMAC_DMA_TX_PC_4 1
++#define BGMAC_DMA_TX_PC_8 2
++#define BGMAC_DMA_TX_PC_16 3
++#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
++#define BGMAC_DMA_TX_PT_SHIFT 24
++#define BGMAC_DMA_TX_PT_1 0
++#define BGMAC_DMA_TX_PT_2 1
++#define BGMAC_DMA_TX_PT_4 2
++#define BGMAC_DMA_TX_PT_8 3
+ #define BGMAC_DMA_TX_INDEX 0x04
+ #define BGMAC_DMA_TX_RINGLO 0x08
+ #define BGMAC_DMA_TX_RINGHI 0x0C
+@@ -284,8 +295,33 @@
+ #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
+ #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
+ #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
++#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
++#define BGMAC_DMA_RX_MR_SHIFT 6
++#define BGMAC_DMA_TX_MR_1 0
++#define BGMAC_DMA_TX_MR_2 1
+ #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
+ #define BGMAC_DMA_RX_ADDREXT_SHIFT 16
++#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
++#define BGMAC_DMA_RX_BL_SHIFT 18
++#define BGMAC_DMA_RX_BL_16 0
++#define BGMAC_DMA_RX_BL_32 1
++#define BGMAC_DMA_RX_BL_64 2
++#define BGMAC_DMA_RX_BL_128 3
++#define BGMAC_DMA_RX_BL_256 4
++#define BGMAC_DMA_RX_BL_512 5
++#define BGMAC_DMA_RX_BL_1024 6
++#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
++#define BGMAC_DMA_RX_PC_SHIFT 21
++#define BGMAC_DMA_RX_PC_0 0
++#define BGMAC_DMA_RX_PC_4 1
++#define BGMAC_DMA_RX_PC_8 2
++#define BGMAC_DMA_RX_PC_16 3
++#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
++#define BGMAC_DMA_RX_PT_SHIFT 24
++#define BGMAC_DMA_RX_PT_1 0
++#define BGMAC_DMA_RX_PT_2 1
++#define BGMAC_DMA_RX_PT_4 2
++#define BGMAC_DMA_RX_PT_8 3
+ #define BGMAC_DMA_RX_INDEX 0x24
+ #define BGMAC_DMA_RX_RINGLO 0x28
+ #define BGMAC_DMA_RX_RINGHI 0x2C
+@@ -342,10 +378,6 @@
+ #define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0
+ #define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000
+
+-#define BGMAC_SPEED_10 0x0001
+-#define BGMAC_SPEED_100 0x0002
+-#define BGMAC_SPEED_1000 0x0004
+-
+ #define BGMAC_WEIGHT 64
+
+ #define ETHER_MAX_LEN 1518
+@@ -402,6 +434,7 @@ struct bgmac {
+ struct net_device *net_dev;
+ struct napi_struct napi;
+ struct mii_bus *mii_bus;
++ struct phy_device *phy_dev;
+
+ /* DMA */
+ struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
+@@ -416,10 +449,9 @@ struct bgmac {
+ u32 int_mask;
+ u32 int_status;
+
+- /* Speed-related */
+- int speed;
+- bool autoneg;
+- bool full_duplex;
++ /* Current MAC state */
++ int mac_speed;
++ int mac_duplex;
+
+ u8 phyaddr;
+ bool has_robosw;
+++ /dev/null
-Use phy lib for the phy. This is needed to get the switch connected to
-the phy and driven by b53 working.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -1252,27 +1252,14 @@ static int bgmac_set_mac_address(struct
- static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
- {
- struct bgmac *bgmac = netdev_priv(net_dev);
-- struct mii_ioctl_data *data = if_mii(ifr);
-
-- switch (cmd) {
-- case SIOCGMIIPHY:
-- data->phy_id = bgmac->phyaddr;
-- /* fallthru */
-- case SIOCGMIIREG:
-- if (!netif_running(net_dev))
-- return -EAGAIN;
-- data->val_out = bgmac_phy_read(bgmac, data->phy_id,
-- data->reg_num & 0x1f);
-- return 0;
-- case SIOCSMIIREG:
-- if (!netif_running(net_dev))
-- return -EAGAIN;
-- bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
-- data->val_in);
-- return 0;
-- default:
-- return -EOPNOTSUPP;
-- }
-+ if (!netif_running(net_dev))
-+ return -EINVAL;
-+
-+ if (!bgmac->phydev)
-+ return -EINVAL;
-+
-+ return phy_mii_ioctl(bgmac->phydev, ifr, cmd);
- }
-
- static const struct net_device_ops bgmac_netdev_ops = {
-@@ -1294,61 +1281,16 @@ static int bgmac_get_settings(struct net
- {
- struct bgmac *bgmac = netdev_priv(net_dev);
-
-- cmd->supported = SUPPORTED_10baseT_Half |
-- SUPPORTED_10baseT_Full |
-- SUPPORTED_100baseT_Half |
-- SUPPORTED_100baseT_Full |
-- SUPPORTED_1000baseT_Half |
-- SUPPORTED_1000baseT_Full |
-- SUPPORTED_Autoneg;
--
-- if (bgmac->autoneg) {
-- WARN_ON(cmd->advertising);
-- if (bgmac->full_duplex) {
-- if (bgmac->speed & BGMAC_SPEED_10)
-- cmd->advertising |= ADVERTISED_10baseT_Full;
-- if (bgmac->speed & BGMAC_SPEED_100)
-- cmd->advertising |= ADVERTISED_100baseT_Full;
-- if (bgmac->speed & BGMAC_SPEED_1000)
-- cmd->advertising |= ADVERTISED_1000baseT_Full;
-- } else {
-- if (bgmac->speed & BGMAC_SPEED_10)
-- cmd->advertising |= ADVERTISED_10baseT_Half;
-- if (bgmac->speed & BGMAC_SPEED_100)
-- cmd->advertising |= ADVERTISED_100baseT_Half;
-- if (bgmac->speed & BGMAC_SPEED_1000)
-- cmd->advertising |= ADVERTISED_1000baseT_Half;
-- }
-- } else {
-- switch (bgmac->speed) {
-- case BGMAC_SPEED_10:
-- ethtool_cmd_speed_set(cmd, SPEED_10);
-- break;
-- case BGMAC_SPEED_100:
-- ethtool_cmd_speed_set(cmd, SPEED_100);
-- break;
-- case BGMAC_SPEED_1000:
-- ethtool_cmd_speed_set(cmd, SPEED_1000);
-- break;
-- }
-- }
--
-- cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
--
-- cmd->autoneg = bgmac->autoneg;
--
-- return 0;
-+ return phy_ethtool_gset(bgmac->phydev, cmd);
- }
-
--#if 0
- static int bgmac_set_settings(struct net_device *net_dev,
- struct ethtool_cmd *cmd)
- {
- struct bgmac *bgmac = netdev_priv(net_dev);
-
-- return -1;
-+ return phy_ethtool_sset(bgmac->phydev, cmd);
- }
--#endif
-
- static void bgmac_get_drvinfo(struct net_device *net_dev,
- struct ethtool_drvinfo *info)
-@@ -1359,6 +1301,7 @@ static void bgmac_get_drvinfo(struct net
-
- static const struct ethtool_ops bgmac_ethtool_ops = {
- .get_settings = bgmac_get_settings,
-+ .set_settings = bgmac_set_settings,
- .get_drvinfo = bgmac_get_drvinfo,
- };
-
-@@ -1377,10 +1320,36 @@ static int bgmac_mii_write(struct mii_bu
- return bgmac_phy_write(bus->priv, mii_id, regnum, value);
- }
-
-+static void bgmac_adjust_link(struct net_device *dev)
-+{
-+ struct bgmac *bgmac = netdev_priv(dev);
-+ struct phy_device *phydev = bgmac->phydev;
-+ bool status_changed = 0;
-+
-+ BUG_ON(!phydev);
-+
-+ if (bgmac->old_link != phydev->link) {
-+ status_changed = 1;
-+ bgmac->old_link = phydev->link;
-+ }
-+
-+ /* reflect duplex change */
-+ if (phydev->link && (bgmac->old_duplex != phydev->duplex)) {
-+ status_changed = 1;
-+ bgmac->old_duplex = phydev->duplex;
-+ }
-+
-+ if (status_changed)
-+ phy_print_status(phydev);
-+}
-+
- static int bgmac_mii_register(struct bgmac *bgmac)
- {
- struct mii_bus *mii_bus;
- int i, err = 0;
-+ struct phy_device *phydev = NULL;
-+ char phy_id[MII_BUS_ID_SIZE + 3];
-+ struct net_device *net_dev = bgmac->net_dev;
-
- mii_bus = mdiobus_alloc();
- if (!mii_bus)
-@@ -1411,7 +1380,28 @@ static int bgmac_mii_register(struct bgm
-
- bgmac->mii_bus = mii_bus;
-
-- return err;
-+ /* connect to PHY */
-+ snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
-+ mii_bus->id, bgmac->phyaddr);
-+
-+ phydev = phy_connect(net_dev, phy_id, &bgmac_adjust_link,
-+ PHY_INTERFACE_MODE_MII);
-+
-+ if (IS_ERR(phydev)) {
-+ netdev_err(net_dev, "could not attach PHY: %s\n", phy_id);
-+ bgmac->phyaddr = BGMAC_PHY_NOREGS;
-+ return PTR_ERR(phydev);
-+ }
-+
-+ bgmac->phydev = phydev;
-+ bgmac->old_link = 0;
-+ bgmac->old_duplex = -1;
-+ bgmac->phyaddr = phydev->addr;
-+
-+ netdev_info(net_dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
-+ phydev->drv->name, dev_name(&phydev->dev));
-+
-+ return 0;
-
- err_free_irq:
- kfree(mii_bus->irq);
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -401,7 +401,10 @@ struct bgmac {
- struct bcma_device *cmn; /* Reference to CMN core for BCM4706 */
- struct net_device *net_dev;
- struct napi_struct napi;
-+ struct phy_device *phydev;
- struct mii_bus *mii_bus;
-+ int old_link;
-+ int old_duplex;
-
- /* DMA */
- struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
+++ /dev/null
-bgmac: add supprot for BCM4707
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -887,6 +887,8 @@ static void bgmac_speed(struct bgmac *bg
- set |= BGMAC_CMDCFG_ES_100;
- if (speed & BGMAC_SPEED_1000)
- set |= BGMAC_CMDCFG_ES_1000;
-+ if (speed & BGMAC_SPEED_2500)
-+ set |= BGMAC_CMDCFG_ES_2500;
- if (!bgmac->full_duplex)
- set |= BGMAC_CMDCFG_HD;
- bgmac_cmdcfg_maskset(bgmac, mask, set, true);
-@@ -894,13 +896,28 @@ static void bgmac_speed(struct bgmac *bg
-
- static void bgmac_miiconfig(struct bgmac *bgmac)
- {
-- u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
-- BGMAC_DS_MM_SHIFT;
-- if (imode == 0 || imode == 1) {
-- if (bgmac->autoneg)
-- bgmac_speed(bgmac, BGMAC_SPEED_100);
-- else
-+ struct bcma_device *core = bgmac->core;
-+ struct bcma_chipinfo *ci = &core->bus->chipinfo;
-+
-+ if (ci->id == BCMA_CHIP_ID_BCM4707 ||
-+ ci->id == BCMA_CHIP_ID_BCM53018) {
-+ if (bgmac->autoneg) {
-+ bcma_awrite32(core, BCMA_IOCTL,
-+ bcma_aread32(core, BCMA_IOCTL) | 0x44);
-+
-+ bgmac_speed(bgmac, BGMAC_SPEED_2500);
-+ } else {
- bgmac_speed(bgmac, bgmac->speed);
-+ }
-+ } else {
-+ u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
-+ BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
-+ if (imode == 0 || imode == 1) {
-+ if (bgmac->autoneg)
-+ bgmac_speed(bgmac, BGMAC_SPEED_100);
-+ else
-+ bgmac_speed(bgmac, bgmac->speed);
-+ }
- }
- }
-
-@@ -946,7 +963,8 @@ static void bgmac_chip_reset(struct bgma
-
- bcma_core_enable(core, flags);
-
-- if (core->id.rev > 2) {
-+ if (core->id.rev > 2 && ci->id != BCMA_CHIP_ID_BCM4707 &&
-+ ci->id != BCMA_CHIP_ID_BCM53018) {
- bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
- bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
- 1000);
-@@ -967,10 +985,13 @@ static void bgmac_chip_reset(struct bgma
- et_swtype &= 0x0f;
- et_swtype <<= 4;
- sw_type = et_swtype;
-- } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
-+ } else if (ci->id == BCMA_CHIP_ID_BCM5357 &&
-+ ci->pkg == BCMA_PKG_ID_BCM5358) {
- sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
-- } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
-- (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
-+ } else if ((ci->id != BCMA_CHIP_ID_BCM53572 &&
-+ ci->pkg == BCMA_PKG_ID_BCM47186) ||
-+ (ci->id == BCMA_CHIP_ID_BCM53572 &&
-+ ci->pkg == BCMA_PKG_ID_BCM47188)) {
- sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
- BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
- }
-@@ -1077,12 +1098,15 @@ static void bgmac_enable(struct bgmac *b
- break;
- }
-
-- rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
-- rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
-- bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
-- mdp = (bp_clk * 128 / 1000) - 3;
-- rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
-- bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
-+ if (ci->id != BCMA_CHIP_ID_BCM4707 &&
-+ ci->id != BCMA_CHIP_ID_BCM53018) {
-+ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
-+ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
-+ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
-+ mdp = (bp_clk * 128 / 1000) - 3;
-+ rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
-+ bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
-+ }
- }
-
- /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
-@@ -1488,6 +1512,25 @@ static int bgmac_probe(struct bcma_devic
- goto err_netdev_free;
- }
-
-+ /* Northstar, take all GMAC cores out of reset */
-+ if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
-+ core->id.id == BCMA_CHIP_ID_BCM53018) {
-+ struct bcma_device *ns_core;
-+ int ns_gmac;
-+
-+ for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
-+ /* As northstar requirement, we have to reset all GAMCs before
-+ * accessing them. et_probe() call pci_enable_device() for etx
-+ * and do si_core_reset for GAMCx only. Then the other three
-+ * GAMCs didn't reset. We do it here.
-+ */
-+ ns_core = bcma_find_core_unit(core->bus, BCMA_CORE_MAC_GBIT, ns_gmac);
-+ if (!bcma_core_is_enabled(ns_core)) {
-+ bcma_core_enable(ns_core, 0);
-+ }
-+ }
-+ }
-+
- bgmac_chip_reset(bgmac);
-
- err = bgmac_dma_alloc(bgmac);
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -185,6 +185,7 @@
- #define BGMAC_CMDCFG_ES_10 0x00000000
- #define BGMAC_CMDCFG_ES_100 0x00000004
- #define BGMAC_CMDCFG_ES_1000 0x00000008
-+#define BGMAC_CMDCFG_ES_2500 0x0000000C
- #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
- #define BGMAC_CMDCFG_PAD_EN 0x00000020
- #define BGMAC_CMDCFG_CF 0x00000040
-@@ -345,6 +346,7 @@
- #define BGMAC_SPEED_10 0x0001
- #define BGMAC_SPEED_100 0x0002
- #define BGMAC_SPEED_1000 0x0004
-+#define BGMAC_SPEED_2500 0x0008
-
- #define BGMAC_WEIGHT 64
-
#include <bcm47xx_nvram.h>
static const struct bcma_device_id bgmac_bcma_tbl[] = {
-@@ -1443,6 +1444,17 @@ static void bgmac_mii_unregister(struct
+@@ -1405,6 +1406,17 @@ static void bgmac_mii_unregister(struct
mdiobus_free(mii_bus);
}
/**************************************************
* BCMA bus ops
**************************************************/
-@@ -1561,6 +1573,16 @@ static int bgmac_probe(struct bcma_devic
+@@ -1521,6 +1533,16 @@ static int bgmac_probe(struct bcma_devic
goto err_dma_free;
}
err = register_netdev(bgmac->net_dev);
if (err) {
bgmac_err(bgmac, "Cannot register net device\n");
-@@ -1590,6 +1612,10 @@ static void bgmac_remove(struct bcma_dev
+@@ -1549,6 +1571,10 @@ static void bgmac_remove(struct bcma_dev
{
struct bgmac *bgmac = bcma_get_drvdata(core);
bgmac_mii_unregister(bgmac);
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -430,6 +430,9 @@ struct bgmac {
+@@ -457,6 +457,9 @@ struct bgmac {
bool has_robosw;
bool loopback;
+++ /dev/null
-From ec12b94d22fa8715561bdffe6da0781dac08423e Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sun, 10 Nov 2013 21:23:57 +0100
-Subject: [PATCH] bgmac: add some workaround for rev 4
-
----
- drivers/net/ethernet/broadcom/bgmac.c | 8 ++++----
- drivers/net/ethernet/broadcom/bgmac.h | 4 +++-
- 2 files changed, 7 insertions(+), 5 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -97,6 +97,16 @@ static void bgmac_dma_tx_enable(struct b
- u32 ctl;
-
- ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
-+ if (bgmac->core->id.rev == 4) {
-+ ctl &= ~BGMAC_DMA_TX_BL_MASK;
-+ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
-+ ctl &= ~BGMAC_DMA_TX_MR_MASK;
-+ ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
-+ ctl &= ~BGMAC_DMA_TX_PC_MASK;
-+ ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
-+ ctl &= ~BGMAC_DMA_TX_PT_MASK;
-+ ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
-+ }
- ctl |= BGMAC_DMA_TX_ENABLE;
- ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
- bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
-@@ -246,6 +256,17 @@ static void bgmac_dma_rx_enable(struct b
- ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
- ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
- ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
-+
-+ if (bgmac->core->id.rev == 4) {
-+ ctl &= ~BGMAC_DMA_RX_BL_MASK;
-+ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
-+
-+ ctl &= ~BGMAC_DMA_RX_PC_MASK;
-+ ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
-+
-+ ctl &= ~BGMAC_DMA_RX_PT_MASK;
-+ ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
-+ }
- bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
- }
-
-@@ -812,13 +833,13 @@ static void bgmac_cmdcfg_maskset(struct
- u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
- u32 new_val = (cmdcfg & mask) | set;
-
-- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
-+ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
- udelay(2);
-
- if (new_val != cmdcfg || force)
- bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
-
-- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
-+ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
- udelay(2);
- }
-
-@@ -1029,7 +1050,7 @@ static void bgmac_chip_reset(struct bgma
- BGMAC_CMDCFG_PROM |
- BGMAC_CMDCFG_NLC |
- BGMAC_CMDCFG_CFE |
-- BGMAC_CMDCFG_SR,
-+ BGMAC_CMDCFG_SR(core->id.rev),
- false);
-
- bgmac_clear_mib(bgmac);
-@@ -1070,7 +1091,7 @@ static void bgmac_enable(struct bgmac *b
-
- cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
- bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
-- BGMAC_CMDCFG_SR, true);
-+ BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
- udelay(2);
- cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
- bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -194,7 +194,9 @@
- #define BGMAC_CMDCFG_TAI 0x00000200
- #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
- #define BGMAC_CMDCFG_HD_SHIFT 10
--#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
-+#define BGMAC_CMDCFG_SR_REVO 0x00000800 /* Set to reset mode, for other revs */
-+#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
-+#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REVO)
- #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
- #define BGMAC_CMDCFG_AE 0x00400000
- #define BGMAC_CMDCFG_CFE 0x00800000
-@@ -255,9 +257,34 @@
- #define BGMAC_DMA_TX_SUSPEND 0x00000002
- #define BGMAC_DMA_TX_LOOPBACK 0x00000004
- #define BGMAC_DMA_TX_FLUSH 0x00000010
-+#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
-+#define BGMAC_DMA_TX_MR_SHIFT 6
-+#define BGMAC_DMA_TX_MR_1 0
-+#define BGMAC_DMA_TX_MR_2 1
- #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
- #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
- #define BGMAC_DMA_TX_ADDREXT_SHIFT 16
-+#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
-+#define BGMAC_DMA_TX_BL_SHIFT 18
-+#define BGMAC_DMA_TX_BL_16 0
-+#define BGMAC_DMA_TX_BL_32 1
-+#define BGMAC_DMA_TX_BL_64 2
-+#define BGMAC_DMA_TX_BL_128 3
-+#define BGMAC_DMA_TX_BL_256 4
-+#define BGMAC_DMA_TX_BL_512 5
-+#define BGMAC_DMA_TX_BL_1024 6
-+#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
-+#define BGMAC_DMA_TX_PC_SHIFT 21
-+#define BGMAC_DMA_TX_PC_0 0
-+#define BGMAC_DMA_TX_PC_4 1
-+#define BGMAC_DMA_TX_PC_8 2
-+#define BGMAC_DMA_TX_PC_16 3
-+#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
-+#define BGMAC_DMA_TX_PT_SHIFT 24
-+#define BGMAC_DMA_TX_PT_1 0
-+#define BGMAC_DMA_TX_PT_2 1
-+#define BGMAC_DMA_TX_PT_4 2
-+#define BGMAC_DMA_TX_PT_8 3
- #define BGMAC_DMA_TX_INDEX 0x04
- #define BGMAC_DMA_TX_RINGLO 0x08
- #define BGMAC_DMA_TX_RINGHI 0x0C
-@@ -285,8 +312,33 @@
- #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
- #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
- #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
-+#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
-+#define BGMAC_DMA_RX_MR_SHIFT 6
-+#define BGMAC_DMA_TX_MR_1 0
-+#define BGMAC_DMA_TX_MR_2 1
- #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
- #define BGMAC_DMA_RX_ADDREXT_SHIFT 16
-+#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
-+#define BGMAC_DMA_RX_BL_SHIFT 18
-+#define BGMAC_DMA_RX_BL_16 0
-+#define BGMAC_DMA_RX_BL_32 1
-+#define BGMAC_DMA_RX_BL_64 2
-+#define BGMAC_DMA_RX_BL_128 3
-+#define BGMAC_DMA_RX_BL_256 4
-+#define BGMAC_DMA_RX_BL_512 5
-+#define BGMAC_DMA_RX_BL_1024 6
-+#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
-+#define BGMAC_DMA_RX_PC_SHIFT 21
-+#define BGMAC_DMA_RX_PC_0 0
-+#define BGMAC_DMA_RX_PC_4 1
-+#define BGMAC_DMA_RX_PC_8 2
-+#define BGMAC_DMA_RX_PC_16 3
-+#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
-+#define BGMAC_DMA_RX_PT_SHIFT 24
-+#define BGMAC_DMA_RX_PT_1 0
-+#define BGMAC_DMA_RX_PT_2 1
-+#define BGMAC_DMA_RX_PT_4 2
-+#define BGMAC_DMA_RX_PT_8 3
- #define BGMAC_DMA_RX_INDEX 0x24
- #define BGMAC_DMA_RX_RINGLO 0x28
- #define BGMAC_DMA_RX_RINGHI 0x2C
--- /dev/null
+--- a/drivers/net/ethernet/broadcom/Kconfig
++++ b/drivers/net/ethernet/broadcom/Kconfig
+@@ -23,6 +23,7 @@ config B44
+ depends on SSB_POSSIBLE && HAS_DMA
+ select SSB
+ select MII
++ select PHYLIB
+ ---help---
+ If you have a network (Ethernet) controller of this type, say Y
+ or M and read the Ethernet-HOWTO, available from
+--- a/drivers/net/ethernet/broadcom/bgmac.c
++++ b/drivers/net/ethernet/broadcom/bgmac.c
+@@ -96,6 +96,19 @@ static void bgmac_dma_tx_enable(struct b
+ u32 ctl;
+
+ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
++ if (bgmac->core->id.rev >= 4) {
++ ctl &= ~BGMAC_DMA_TX_BL_MASK;
++ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
++
++ ctl &= ~BGMAC_DMA_TX_MR_MASK;
++ ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
++
++ ctl &= ~BGMAC_DMA_TX_PC_MASK;
++ ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
++
++ ctl &= ~BGMAC_DMA_TX_PT_MASK;
++ ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
++ }
+ ctl |= BGMAC_DMA_TX_ENABLE;
+ ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
+ bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
+@@ -240,6 +253,16 @@ static void bgmac_dma_rx_enable(struct b
+ u32 ctl;
+
+ ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
++ if (bgmac->core->id.rev >= 4) {
++ ctl &= ~BGMAC_DMA_RX_BL_MASK;
++ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
++
++ ctl &= ~BGMAC_DMA_RX_PC_MASK;
++ ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
++
++ ctl &= ~BGMAC_DMA_RX_PT_MASK;
++ ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
++ }
+ ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
+ ctl |= BGMAC_DMA_RX_ENABLE;
+ ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
+@@ -682,70 +705,6 @@ static int bgmac_phy_write(struct bgmac
+ return 0;
+ }
+
+-/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyforce */
+-static void bgmac_phy_force(struct bgmac *bgmac)
+-{
+- u16 ctl;
+- u16 mask = ~(BGMAC_PHY_CTL_SPEED | BGMAC_PHY_CTL_SPEED_MSB |
+- BGMAC_PHY_CTL_ANENAB | BGMAC_PHY_CTL_DUPLEX);
+-
+- if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
+- return;
+-
+- if (bgmac->autoneg)
+- return;
+-
+- ctl = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL);
+- ctl &= mask;
+- if (bgmac->full_duplex)
+- ctl |= BGMAC_PHY_CTL_DUPLEX;
+- if (bgmac->speed == BGMAC_SPEED_100)
+- ctl |= BGMAC_PHY_CTL_SPEED_100;
+- else if (bgmac->speed == BGMAC_SPEED_1000)
+- ctl |= BGMAC_PHY_CTL_SPEED_1000;
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL, ctl);
+-}
+-
+-/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyadvertise */
+-static void bgmac_phy_advertise(struct bgmac *bgmac)
+-{
+- u16 adv;
+-
+- if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
+- return;
+-
+- if (!bgmac->autoneg)
+- return;
+-
+- /* Adv selected 10/100 speeds */
+- adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV);
+- adv &= ~(BGMAC_PHY_ADV_10HALF | BGMAC_PHY_ADV_10FULL |
+- BGMAC_PHY_ADV_100HALF | BGMAC_PHY_ADV_100FULL);
+- if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
+- adv |= BGMAC_PHY_ADV_10HALF;
+- if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
+- adv |= BGMAC_PHY_ADV_100HALF;
+- if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_10)
+- adv |= BGMAC_PHY_ADV_10FULL;
+- if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_100)
+- adv |= BGMAC_PHY_ADV_100FULL;
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV, adv);
+-
+- /* Adv selected 1000 speeds */
+- adv = bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2);
+- adv &= ~(BGMAC_PHY_ADV2_1000HALF | BGMAC_PHY_ADV2_1000FULL);
+- if (!bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
+- adv |= BGMAC_PHY_ADV2_1000HALF;
+- if (bgmac->full_duplex && bgmac->speed & BGMAC_SPEED_1000)
+- adv |= BGMAC_PHY_ADV2_1000FULL;
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_ADV2, adv);
+-
+- /* Restart */
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
+- bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) |
+- BGMAC_PHY_CTL_RESTART);
+-}
+-
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
+ static void bgmac_phy_init(struct bgmac *bgmac)
+ {
+@@ -789,11 +748,9 @@ static void bgmac_phy_reset(struct bgmac
+ if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
+ return;
+
+- bgmac_phy_write(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL,
+- BGMAC_PHY_CTL_RESET);
++ bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
+ udelay(100);
+- if (bgmac_phy_read(bgmac, bgmac->phyaddr, BGMAC_PHY_CTL) &
+- BGMAC_PHY_CTL_RESET)
++ if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
+ bgmac_err(bgmac, "PHY reset failed\n");
+ bgmac_phy_init(bgmac);
+ }
+@@ -811,13 +768,13 @@ static void bgmac_cmdcfg_maskset(struct
+ u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
+ u32 new_val = (cmdcfg & mask) | set;
+
+- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
++ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
+ udelay(2);
+
+ if (new_val != cmdcfg || force)
+ bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
+
+- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
++ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
+ udelay(2);
+ }
+
+@@ -876,31 +833,56 @@ static void bgmac_clear_mib(struct bgmac
+ }
+
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
+-static void bgmac_speed(struct bgmac *bgmac, int speed)
++static void bgmac_mac_speed(struct bgmac *bgmac)
+ {
+ u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
+ u32 set = 0;
+
+- if (speed & BGMAC_SPEED_10)
++ switch (bgmac->mac_speed) {
++ case SPEED_10:
+ set |= BGMAC_CMDCFG_ES_10;
+- if (speed & BGMAC_SPEED_100)
++ break;
++ case SPEED_100:
+ set |= BGMAC_CMDCFG_ES_100;
+- if (speed & BGMAC_SPEED_1000)
++ break;
++ case SPEED_1000:
+ set |= BGMAC_CMDCFG_ES_1000;
+- if (!bgmac->full_duplex)
++ break;
++ case SPEED_2500:
++ set |= BGMAC_CMDCFG_ES_2500;
++ break;
++ default:
++ bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
++ }
++
++ if (bgmac->mac_duplex == DUPLEX_HALF)
+ set |= BGMAC_CMDCFG_HD;
++
+ bgmac_cmdcfg_maskset(bgmac, mask, set, true);
+ }
+
+ static void bgmac_miiconfig(struct bgmac *bgmac)
+ {
+- u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
+- BGMAC_DS_MM_SHIFT;
+- if (imode == 0 || imode == 1) {
+- if (bgmac->autoneg)
+- bgmac_speed(bgmac, BGMAC_SPEED_100);
+- else
+- bgmac_speed(bgmac, bgmac->speed);
++ struct bcma_device *core = bgmac->core;
++ struct bcma_chipinfo *ci = &core->bus->chipinfo;
++ u8 imode;
++
++ if (ci->id == BCMA_CHIP_ID_BCM4707 ||
++ ci->id == BCMA_CHIP_ID_BCM53018) {
++ bcma_awrite32(core, BCMA_IOCTL,
++ bcma_aread32(core, BCMA_IOCTL) | 0x40 |
++ BGMAC_BCMA_IOCTL_SW_CLKEN);
++ bgmac->mac_speed = SPEED_2500;
++ bgmac->mac_duplex = DUPLEX_FULL;
++ bgmac_mac_speed(bgmac);
++ } else {
++ imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
++ BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
++ if (imode == 0 || imode == 1) {
++ bgmac->mac_speed = SPEED_100;
++ bgmac->mac_duplex = DUPLEX_FULL;
++ bgmac_mac_speed(bgmac);
++ }
+ }
+ }
+
+@@ -910,7 +892,7 @@ static void bgmac_chip_reset(struct bgma
+ struct bcma_device *core = bgmac->core;
+ struct bcma_bus *bus = core->bus;
+ struct bcma_chipinfo *ci = &bus->chipinfo;
+- u32 flags = 0;
++ u32 flags;
+ u32 iost;
+ int i;
+
+@@ -933,26 +915,36 @@ static void bgmac_chip_reset(struct bgma
+ }
+
+ iost = bcma_aread32(core, BCMA_IOST);
+- if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 10) ||
++ if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
+ (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
+- (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9))
++ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
+ iost &= ~BGMAC_BCMA_IOST_ATTACHED;
+
+- if (iost & BGMAC_BCMA_IOST_ATTACHED) {
+- flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
+- if (!bgmac->has_robosw)
+- flags |= BGMAC_BCMA_IOCTL_SW_RESET;
++ /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
++ if (ci->id != BCMA_CHIP_ID_BCM4707) {
++ flags = 0;
++ if (iost & BGMAC_BCMA_IOST_ATTACHED) {
++ flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
++ if (!bgmac->has_robosw)
++ flags |= BGMAC_BCMA_IOCTL_SW_RESET;
++ }
++ bcma_core_enable(core, flags);
+ }
+
+- bcma_core_enable(core, flags);
+-
+- if (core->id.rev > 2) {
+- bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
+- bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
++ /* Request Misc PLL for corerev > 2 */
++ if (core->id.rev > 2 &&
++ ci->id != BCMA_CHIP_ID_BCM4707 &&
++ ci->id != BCMA_CHIP_ID_BCM53018) {
++ bgmac_set(bgmac, BCMA_CLKCTLST,
++ BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
++ bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
++ BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
++ BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
+ 1000);
+ }
+
+- if (ci->id == BCMA_CHIP_ID_BCM5357 || ci->id == BCMA_CHIP_ID_BCM4749 ||
++ if (ci->id == BCMA_CHIP_ID_BCM5357 ||
++ ci->id == BCMA_CHIP_ID_BCM4749 ||
+ ci->id == BCMA_CHIP_ID_BCM53572) {
+ struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
+ u8 et_swtype = 0;
+@@ -967,10 +959,11 @@ static void bgmac_chip_reset(struct bgma
+ et_swtype &= 0x0f;
+ et_swtype <<= 4;
+ sw_type = et_swtype;
+- } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
++ } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
+ sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
+- } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
+- (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
++ } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
++ (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
++ (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
+ sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
+ BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
+ }
+@@ -1007,8 +1000,10 @@ static void bgmac_chip_reset(struct bgma
+ BGMAC_CMDCFG_PROM |
+ BGMAC_CMDCFG_NLC |
+ BGMAC_CMDCFG_CFE |
+- BGMAC_CMDCFG_SR,
++ BGMAC_CMDCFG_SR(core->id.rev),
+ false);
++ bgmac->mac_speed = SPEED_UNKNOWN;
++ bgmac->mac_duplex = DUPLEX_UNKNOWN;
+
+ bgmac_clear_mib(bgmac);
+ if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
+@@ -1048,7 +1043,7 @@ static void bgmac_enable(struct bgmac *b
+
+ cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
+ bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
+- BGMAC_CMDCFG_SR, true);
++ BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
+ udelay(2);
+ cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
+ bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
+@@ -1077,12 +1072,16 @@ static void bgmac_enable(struct bgmac *b
+ break;
+ }
+
+- rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
+- rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
+- bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
+- mdp = (bp_clk * 128 / 1000) - 3;
+- rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
+- bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
++ if (ci->id != BCMA_CHIP_ID_BCM4707 &&
++ ci->id != BCMA_CHIP_ID_BCM53018) {
++ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
++ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
++ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
++ 1000000;
++ mdp = (bp_clk * 128 / 1000) - 3;
++ rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
++ bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
++ }
+ }
+
+ /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
+@@ -1108,13 +1107,6 @@ static void bgmac_chip_init(struct bgmac
+
+ bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
+
+- if (!bgmac->autoneg) {
+- bgmac_speed(bgmac, bgmac->speed);
+- bgmac_phy_force(bgmac);
+- } else if (bgmac->speed) { /* if there is anything to adv */
+- bgmac_phy_advertise(bgmac);
+- }
+-
+ if (full_init) {
+ bgmac_dma_init(bgmac);
+ if (1) /* FIXME: is there any case we don't want IRQs? */
+@@ -1204,6 +1196,8 @@ static int bgmac_open(struct net_device
+ }
+ napi_enable(&bgmac->napi);
+
++ phy_start(bgmac->phy_dev);
++
+ netif_carrier_on(net_dev);
+
+ err_out:
+@@ -1216,6 +1210,8 @@ static int bgmac_stop(struct net_device
+
+ netif_carrier_off(net_dev);
+
++ phy_stop(bgmac->phy_dev);
++
+ napi_disable(&bgmac->napi);
+ bgmac_chip_intrs_off(bgmac);
+ free_irq(bgmac->core->irq, net_dev);
+@@ -1252,27 +1248,11 @@ static int bgmac_set_mac_address(struct
+ static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
+ {
+ struct bgmac *bgmac = netdev_priv(net_dev);
+- struct mii_ioctl_data *data = if_mii(ifr);
+
+- switch (cmd) {
+- case SIOCGMIIPHY:
+- data->phy_id = bgmac->phyaddr;
+- /* fallthru */
+- case SIOCGMIIREG:
+- if (!netif_running(net_dev))
+- return -EAGAIN;
+- data->val_out = bgmac_phy_read(bgmac, data->phy_id,
+- data->reg_num & 0x1f);
+- return 0;
+- case SIOCSMIIREG:
+- if (!netif_running(net_dev))
+- return -EAGAIN;
+- bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
+- data->val_in);
+- return 0;
+- default:
+- return -EOPNOTSUPP;
+- }
++ if (!netif_running(net_dev))
++ return -EINVAL;
++
++ return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
+ }
+
+ static const struct net_device_ops bgmac_netdev_ops = {
+@@ -1294,61 +1274,16 @@ static int bgmac_get_settings(struct net
+ {
+ struct bgmac *bgmac = netdev_priv(net_dev);
+
+- cmd->supported = SUPPORTED_10baseT_Half |
+- SUPPORTED_10baseT_Full |
+- SUPPORTED_100baseT_Half |
+- SUPPORTED_100baseT_Full |
+- SUPPORTED_1000baseT_Half |
+- SUPPORTED_1000baseT_Full |
+- SUPPORTED_Autoneg;
+-
+- if (bgmac->autoneg) {
+- WARN_ON(cmd->advertising);
+- if (bgmac->full_duplex) {
+- if (bgmac->speed & BGMAC_SPEED_10)
+- cmd->advertising |= ADVERTISED_10baseT_Full;
+- if (bgmac->speed & BGMAC_SPEED_100)
+- cmd->advertising |= ADVERTISED_100baseT_Full;
+- if (bgmac->speed & BGMAC_SPEED_1000)
+- cmd->advertising |= ADVERTISED_1000baseT_Full;
+- } else {
+- if (bgmac->speed & BGMAC_SPEED_10)
+- cmd->advertising |= ADVERTISED_10baseT_Half;
+- if (bgmac->speed & BGMAC_SPEED_100)
+- cmd->advertising |= ADVERTISED_100baseT_Half;
+- if (bgmac->speed & BGMAC_SPEED_1000)
+- cmd->advertising |= ADVERTISED_1000baseT_Half;
+- }
+- } else {
+- switch (bgmac->speed) {
+- case BGMAC_SPEED_10:
+- ethtool_cmd_speed_set(cmd, SPEED_10);
+- break;
+- case BGMAC_SPEED_100:
+- ethtool_cmd_speed_set(cmd, SPEED_100);
+- break;
+- case BGMAC_SPEED_1000:
+- ethtool_cmd_speed_set(cmd, SPEED_1000);
+- break;
+- }
+- }
+-
+- cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
+-
+- cmd->autoneg = bgmac->autoneg;
+-
+- return 0;
++ return phy_ethtool_gset(bgmac->phy_dev, cmd);
+ }
+
+-#if 0
+ static int bgmac_set_settings(struct net_device *net_dev,
+ struct ethtool_cmd *cmd)
+ {
+ struct bgmac *bgmac = netdev_priv(net_dev);
+
+- return -1;
++ return phy_ethtool_sset(bgmac->phy_dev, cmd);
+ }
+-#endif
+
+ static void bgmac_get_drvinfo(struct net_device *net_dev,
+ struct ethtool_drvinfo *info)
+@@ -1359,6 +1294,7 @@ static void bgmac_get_drvinfo(struct net
+
+ static const struct ethtool_ops bgmac_ethtool_ops = {
+ .get_settings = bgmac_get_settings,
++ .set_settings = bgmac_set_settings,
+ .get_drvinfo = bgmac_get_drvinfo,
+ };
+
+@@ -1377,9 +1313,35 @@ static int bgmac_mii_write(struct mii_bu
+ return bgmac_phy_write(bus->priv, mii_id, regnum, value);
+ }
+
++static void bgmac_adjust_link(struct net_device *net_dev)
++{
++ struct bgmac *bgmac = netdev_priv(net_dev);
++ struct phy_device *phy_dev = bgmac->phy_dev;
++ bool update = false;
++
++ if (phy_dev->link) {
++ if (phy_dev->speed != bgmac->mac_speed) {
++ bgmac->mac_speed = phy_dev->speed;
++ update = true;
++ }
++
++ if (phy_dev->duplex != bgmac->mac_duplex) {
++ bgmac->mac_duplex = phy_dev->duplex;
++ update = true;
++ }
++ }
++
++ if (update) {
++ bgmac_mac_speed(bgmac);
++ phy_print_status(phy_dev);
++ }
++}
++
+ static int bgmac_mii_register(struct bgmac *bgmac)
+ {
+ struct mii_bus *mii_bus;
++ struct phy_device *phy_dev;
++ char bus_id[MII_BUS_ID_SIZE + 3];
+ int i, err = 0;
+
+ mii_bus = mdiobus_alloc();
+@@ -1411,8 +1373,22 @@ static int bgmac_mii_register(struct bgm
+
+ bgmac->mii_bus = mii_bus;
+
++ /* Connect to the PHY */
++ snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
++ bgmac->phyaddr);
++ phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
++ PHY_INTERFACE_MODE_MII);
++ if (IS_ERR(phy_dev)) {
++ bgmac_err(bgmac, "PHY connecton failed\n");
++ err = PTR_ERR(phy_dev);
++ goto err_unregister_bus;
++ }
++ bgmac->phy_dev = phy_dev;
++
+ return err;
+
++err_unregister_bus:
++ mdiobus_unregister(mii_bus);
+ err_free_irq:
+ kfree(mii_bus->irq);
+ err_free_bus:
+@@ -1467,9 +1443,6 @@ static int bgmac_probe(struct bcma_devic
+ bcma_set_drvdata(core, bgmac);
+
+ /* Defaults */
+- bgmac->autoneg = true;
+- bgmac->full_duplex = true;
+- bgmac->speed = BGMAC_SPEED_10 | BGMAC_SPEED_100 | BGMAC_SPEED_1000;
+ memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
+
+ /* On BCM4706 we need common core to access PHY */
+@@ -1500,6 +1473,27 @@ static int bgmac_probe(struct bcma_devic
+
+ bgmac_chip_reset(bgmac);
+
++ /* For Northstar, we have to take all GMAC core out of reset */
++ if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
++ core->id.id == BCMA_CHIP_ID_BCM53018) {
++ struct bcma_device *ns_core;
++ int ns_gmac;
++
++ /* Northstar has 4 GMAC cores */
++ for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
++ /* As Northstar requirement, we have to reset all GMACs
++ * before accessing one. bgmac_chip_reset() call
++ * bcma_core_enable() for this core. Then the other
++ * three GMACs didn't reset. We do it here.
++ */
++ ns_core = bcma_find_core_unit(core->bus,
++ BCMA_CORE_MAC_GBIT,
++ ns_gmac);
++ if (ns_core && !bcma_core_is_enabled(ns_core))
++ bcma_core_enable(ns_core, 0);
++ }
++ }
++
+ err = bgmac_dma_alloc(bgmac);
+ if (err) {
+ bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
+@@ -1524,14 +1518,12 @@ static int bgmac_probe(struct bcma_devic
+ err = bgmac_mii_register(bgmac);
+ if (err) {
+ bgmac_err(bgmac, "Cannot register MDIO\n");
+- err = -ENOTSUPP;
+ goto err_dma_free;
+ }
+
+ err = register_netdev(bgmac->net_dev);
+ if (err) {
+ bgmac_err(bgmac, "Cannot register net device\n");
+- err = -ENOTSUPP;
+ goto err_mii_unregister;
+ }
+
+--- a/drivers/net/ethernet/broadcom/bgmac.h
++++ b/drivers/net/ethernet/broadcom/bgmac.h
+@@ -95,7 +95,11 @@
+ #define BGMAC_RXQ_CTL_MDP_SHIFT 24
+ #define BGMAC_GPIO_SELECT 0x194
+ #define BGMAC_GPIO_OUTPUT_EN 0x198
+-/* For 0x1e0 see BCMA_CLKCTLST */
++
++/* For 0x1e0 see BCMA_CLKCTLST. Below are BGMAC specific bits */
++#define BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ 0x00000100
++#define BGMAC_BCMA_CLKCTLST_MISC_PLL_ST 0x01000000
++
+ #define BGMAC_HW_WAR 0x1e4
+ #define BGMAC_PWR_CTL 0x1e8
+ #define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */
+@@ -185,6 +189,7 @@
+ #define BGMAC_CMDCFG_ES_10 0x00000000
+ #define BGMAC_CMDCFG_ES_100 0x00000004
+ #define BGMAC_CMDCFG_ES_1000 0x00000008
++#define BGMAC_CMDCFG_ES_2500 0x0000000C
+ #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
+ #define BGMAC_CMDCFG_PAD_EN 0x00000020
+ #define BGMAC_CMDCFG_CF 0x00000040
+@@ -193,7 +198,9 @@
+ #define BGMAC_CMDCFG_TAI 0x00000200
+ #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
+ #define BGMAC_CMDCFG_HD_SHIFT 10
+-#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
++#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */
++#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
++#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0)
+ #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
+ #define BGMAC_CMDCFG_AE 0x00400000
+ #define BGMAC_CMDCFG_CFE 0x00800000
+@@ -216,27 +223,6 @@
+ #define BGMAC_RX_STATUS 0xb38
+ #define BGMAC_TX_STATUS 0xb3c
+
+-#define BGMAC_PHY_CTL 0x00
+-#define BGMAC_PHY_CTL_SPEED_MSB 0x0040
+-#define BGMAC_PHY_CTL_DUPLEX 0x0100 /* duplex mode */
+-#define BGMAC_PHY_CTL_RESTART 0x0200 /* restart autonegotiation */
+-#define BGMAC_PHY_CTL_ANENAB 0x1000 /* enable autonegotiation */
+-#define BGMAC_PHY_CTL_SPEED 0x2000
+-#define BGMAC_PHY_CTL_LOOP 0x4000 /* loopback */
+-#define BGMAC_PHY_CTL_RESET 0x8000 /* reset */
+-/* Helpers */
+-#define BGMAC_PHY_CTL_SPEED_10 0
+-#define BGMAC_PHY_CTL_SPEED_100 BGMAC_PHY_CTL_SPEED
+-#define BGMAC_PHY_CTL_SPEED_1000 BGMAC_PHY_CTL_SPEED_MSB
+-#define BGMAC_PHY_ADV 0x04
+-#define BGMAC_PHY_ADV_10HALF 0x0020 /* advertise 10MBits/s half duplex */
+-#define BGMAC_PHY_ADV_10FULL 0x0040 /* advertise 10MBits/s full duplex */
+-#define BGMAC_PHY_ADV_100HALF 0x0080 /* advertise 100MBits/s half duplex */
+-#define BGMAC_PHY_ADV_100FULL 0x0100 /* advertise 100MBits/s full duplex */
+-#define BGMAC_PHY_ADV2 0x09
+-#define BGMAC_PHY_ADV2_1000HALF 0x0100 /* advertise 1000MBits/s half duplex */
+-#define BGMAC_PHY_ADV2_1000FULL 0x0200 /* advertise 1000MBits/s full duplex */
+-
+ /* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
+ #define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
+ #define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */
+@@ -254,9 +240,34 @@
+ #define BGMAC_DMA_TX_SUSPEND 0x00000002
+ #define BGMAC_DMA_TX_LOOPBACK 0x00000004
+ #define BGMAC_DMA_TX_FLUSH 0x00000010
++#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
++#define BGMAC_DMA_TX_MR_SHIFT 6
++#define BGMAC_DMA_TX_MR_1 0
++#define BGMAC_DMA_TX_MR_2 1
+ #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
+ #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
+ #define BGMAC_DMA_TX_ADDREXT_SHIFT 16
++#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
++#define BGMAC_DMA_TX_BL_SHIFT 18
++#define BGMAC_DMA_TX_BL_16 0
++#define BGMAC_DMA_TX_BL_32 1
++#define BGMAC_DMA_TX_BL_64 2
++#define BGMAC_DMA_TX_BL_128 3
++#define BGMAC_DMA_TX_BL_256 4
++#define BGMAC_DMA_TX_BL_512 5
++#define BGMAC_DMA_TX_BL_1024 6
++#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
++#define BGMAC_DMA_TX_PC_SHIFT 21
++#define BGMAC_DMA_TX_PC_0 0
++#define BGMAC_DMA_TX_PC_4 1
++#define BGMAC_DMA_TX_PC_8 2
++#define BGMAC_DMA_TX_PC_16 3
++#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
++#define BGMAC_DMA_TX_PT_SHIFT 24
++#define BGMAC_DMA_TX_PT_1 0
++#define BGMAC_DMA_TX_PT_2 1
++#define BGMAC_DMA_TX_PT_4 2
++#define BGMAC_DMA_TX_PT_8 3
+ #define BGMAC_DMA_TX_INDEX 0x04
+ #define BGMAC_DMA_TX_RINGLO 0x08
+ #define BGMAC_DMA_TX_RINGHI 0x0C
+@@ -284,8 +295,33 @@
+ #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
+ #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
+ #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
++#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
++#define BGMAC_DMA_RX_MR_SHIFT 6
++#define BGMAC_DMA_TX_MR_1 0
++#define BGMAC_DMA_TX_MR_2 1
+ #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
+ #define BGMAC_DMA_RX_ADDREXT_SHIFT 16
++#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
++#define BGMAC_DMA_RX_BL_SHIFT 18
++#define BGMAC_DMA_RX_BL_16 0
++#define BGMAC_DMA_RX_BL_32 1
++#define BGMAC_DMA_RX_BL_64 2
++#define BGMAC_DMA_RX_BL_128 3
++#define BGMAC_DMA_RX_BL_256 4
++#define BGMAC_DMA_RX_BL_512 5
++#define BGMAC_DMA_RX_BL_1024 6
++#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
++#define BGMAC_DMA_RX_PC_SHIFT 21
++#define BGMAC_DMA_RX_PC_0 0
++#define BGMAC_DMA_RX_PC_4 1
++#define BGMAC_DMA_RX_PC_8 2
++#define BGMAC_DMA_RX_PC_16 3
++#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
++#define BGMAC_DMA_RX_PT_SHIFT 24
++#define BGMAC_DMA_RX_PT_1 0
++#define BGMAC_DMA_RX_PT_2 1
++#define BGMAC_DMA_RX_PT_4 2
++#define BGMAC_DMA_RX_PT_8 3
+ #define BGMAC_DMA_RX_INDEX 0x24
+ #define BGMAC_DMA_RX_RINGLO 0x28
+ #define BGMAC_DMA_RX_RINGHI 0x2C
+@@ -342,10 +378,6 @@
+ #define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0
+ #define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000
+
+-#define BGMAC_SPEED_10 0x0001
+-#define BGMAC_SPEED_100 0x0002
+-#define BGMAC_SPEED_1000 0x0004
+-
+ #define BGMAC_WEIGHT 64
+
+ #define ETHER_MAX_LEN 1518
+@@ -402,6 +434,7 @@ struct bgmac {
+ struct net_device *net_dev;
+ struct napi_struct napi;
+ struct mii_bus *mii_bus;
++ struct phy_device *phy_dev;
+
+ /* DMA */
+ struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
+@@ -416,10 +449,9 @@ struct bgmac {
+ u32 int_mask;
+ u32 int_status;
+
+- /* Speed-related */
+- int speed;
+- bool autoneg;
+- bool full_duplex;
++ /* Current MAC state */
++ int mac_speed;
++ int mac_duplex;
+
+ u8 phyaddr;
+ bool has_robosw;
+++ /dev/null
-Use phy lib for the phy. This is needed to get the switch connected to
-the phy and driven by b53 working.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -1252,27 +1252,14 @@ static int bgmac_set_mac_address(struct
- static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
- {
- struct bgmac *bgmac = netdev_priv(net_dev);
-- struct mii_ioctl_data *data = if_mii(ifr);
-
-- switch (cmd) {
-- case SIOCGMIIPHY:
-- data->phy_id = bgmac->phyaddr;
-- /* fallthru */
-- case SIOCGMIIREG:
-- if (!netif_running(net_dev))
-- return -EAGAIN;
-- data->val_out = bgmac_phy_read(bgmac, data->phy_id,
-- data->reg_num & 0x1f);
-- return 0;
-- case SIOCSMIIREG:
-- if (!netif_running(net_dev))
-- return -EAGAIN;
-- bgmac_phy_write(bgmac, data->phy_id, data->reg_num & 0x1f,
-- data->val_in);
-- return 0;
-- default:
-- return -EOPNOTSUPP;
-- }
-+ if (!netif_running(net_dev))
-+ return -EINVAL;
-+
-+ if (!bgmac->phydev)
-+ return -EINVAL;
-+
-+ return phy_mii_ioctl(bgmac->phydev, ifr, cmd);
- }
-
- static const struct net_device_ops bgmac_netdev_ops = {
-@@ -1294,61 +1281,16 @@ static int bgmac_get_settings(struct net
- {
- struct bgmac *bgmac = netdev_priv(net_dev);
-
-- cmd->supported = SUPPORTED_10baseT_Half |
-- SUPPORTED_10baseT_Full |
-- SUPPORTED_100baseT_Half |
-- SUPPORTED_100baseT_Full |
-- SUPPORTED_1000baseT_Half |
-- SUPPORTED_1000baseT_Full |
-- SUPPORTED_Autoneg;
--
-- if (bgmac->autoneg) {
-- WARN_ON(cmd->advertising);
-- if (bgmac->full_duplex) {
-- if (bgmac->speed & BGMAC_SPEED_10)
-- cmd->advertising |= ADVERTISED_10baseT_Full;
-- if (bgmac->speed & BGMAC_SPEED_100)
-- cmd->advertising |= ADVERTISED_100baseT_Full;
-- if (bgmac->speed & BGMAC_SPEED_1000)
-- cmd->advertising |= ADVERTISED_1000baseT_Full;
-- } else {
-- if (bgmac->speed & BGMAC_SPEED_10)
-- cmd->advertising |= ADVERTISED_10baseT_Half;
-- if (bgmac->speed & BGMAC_SPEED_100)
-- cmd->advertising |= ADVERTISED_100baseT_Half;
-- if (bgmac->speed & BGMAC_SPEED_1000)
-- cmd->advertising |= ADVERTISED_1000baseT_Half;
-- }
-- } else {
-- switch (bgmac->speed) {
-- case BGMAC_SPEED_10:
-- ethtool_cmd_speed_set(cmd, SPEED_10);
-- break;
-- case BGMAC_SPEED_100:
-- ethtool_cmd_speed_set(cmd, SPEED_100);
-- break;
-- case BGMAC_SPEED_1000:
-- ethtool_cmd_speed_set(cmd, SPEED_1000);
-- break;
-- }
-- }
--
-- cmd->duplex = bgmac->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
--
-- cmd->autoneg = bgmac->autoneg;
--
-- return 0;
-+ return phy_ethtool_gset(bgmac->phydev, cmd);
- }
-
--#if 0
- static int bgmac_set_settings(struct net_device *net_dev,
- struct ethtool_cmd *cmd)
- {
- struct bgmac *bgmac = netdev_priv(net_dev);
-
-- return -1;
-+ return phy_ethtool_sset(bgmac->phydev, cmd);
- }
--#endif
-
- static void bgmac_get_drvinfo(struct net_device *net_dev,
- struct ethtool_drvinfo *info)
-@@ -1359,6 +1301,7 @@ static void bgmac_get_drvinfo(struct net
-
- static const struct ethtool_ops bgmac_ethtool_ops = {
- .get_settings = bgmac_get_settings,
-+ .set_settings = bgmac_set_settings,
- .get_drvinfo = bgmac_get_drvinfo,
- };
-
-@@ -1377,10 +1320,36 @@ static int bgmac_mii_write(struct mii_bu
- return bgmac_phy_write(bus->priv, mii_id, regnum, value);
- }
-
-+static void bgmac_adjust_link(struct net_device *dev)
-+{
-+ struct bgmac *bgmac = netdev_priv(dev);
-+ struct phy_device *phydev = bgmac->phydev;
-+ bool status_changed = 0;
-+
-+ BUG_ON(!phydev);
-+
-+ if (bgmac->old_link != phydev->link) {
-+ status_changed = 1;
-+ bgmac->old_link = phydev->link;
-+ }
-+
-+ /* reflect duplex change */
-+ if (phydev->link && (bgmac->old_duplex != phydev->duplex)) {
-+ status_changed = 1;
-+ bgmac->old_duplex = phydev->duplex;
-+ }
-+
-+ if (status_changed)
-+ phy_print_status(phydev);
-+}
-+
- static int bgmac_mii_register(struct bgmac *bgmac)
- {
- struct mii_bus *mii_bus;
- int i, err = 0;
-+ struct phy_device *phydev = NULL;
-+ char phy_id[MII_BUS_ID_SIZE + 3];
-+ struct net_device *net_dev = bgmac->net_dev;
-
- mii_bus = mdiobus_alloc();
- if (!mii_bus)
-@@ -1411,7 +1380,28 @@ static int bgmac_mii_register(struct bgm
-
- bgmac->mii_bus = mii_bus;
-
-- return err;
-+ /* connect to PHY */
-+ snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
-+ mii_bus->id, bgmac->phyaddr);
-+
-+ phydev = phy_connect(net_dev, phy_id, &bgmac_adjust_link,
-+ PHY_INTERFACE_MODE_MII);
-+
-+ if (IS_ERR(phydev)) {
-+ netdev_err(net_dev, "could not attach PHY: %s\n", phy_id);
-+ bgmac->phyaddr = BGMAC_PHY_NOREGS;
-+ return PTR_ERR(phydev);
-+ }
-+
-+ bgmac->phydev = phydev;
-+ bgmac->old_link = 0;
-+ bgmac->old_duplex = -1;
-+ bgmac->phyaddr = phydev->addr;
-+
-+ netdev_info(net_dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
-+ phydev->drv->name, dev_name(&phydev->dev));
-+
-+ return 0;
-
- err_free_irq:
- kfree(mii_bus->irq);
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -401,7 +401,10 @@ struct bgmac {
- struct bcma_device *cmn; /* Reference to CMN core for BCM4706 */
- struct net_device *net_dev;
- struct napi_struct napi;
-+ struct phy_device *phydev;
- struct mii_bus *mii_bus;
-+ int old_link;
-+ int old_duplex;
-
- /* DMA */
- struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
+++ /dev/null
-bgmac: add supprot for BCM4707
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
-
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -887,6 +887,8 @@ static void bgmac_speed(struct bgmac *bg
- set |= BGMAC_CMDCFG_ES_100;
- if (speed & BGMAC_SPEED_1000)
- set |= BGMAC_CMDCFG_ES_1000;
-+ if (speed & BGMAC_SPEED_2500)
-+ set |= BGMAC_CMDCFG_ES_2500;
- if (!bgmac->full_duplex)
- set |= BGMAC_CMDCFG_HD;
- bgmac_cmdcfg_maskset(bgmac, mask, set, true);
-@@ -894,13 +896,28 @@ static void bgmac_speed(struct bgmac *bg
-
- static void bgmac_miiconfig(struct bgmac *bgmac)
- {
-- u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
-- BGMAC_DS_MM_SHIFT;
-- if (imode == 0 || imode == 1) {
-- if (bgmac->autoneg)
-- bgmac_speed(bgmac, BGMAC_SPEED_100);
-- else
-+ struct bcma_device *core = bgmac->core;
-+ struct bcma_chipinfo *ci = &core->bus->chipinfo;
-+
-+ if (ci->id == BCMA_CHIP_ID_BCM4707 ||
-+ ci->id == BCMA_CHIP_ID_BCM53018) {
-+ if (bgmac->autoneg) {
-+ bcma_awrite32(core, BCMA_IOCTL,
-+ bcma_aread32(core, BCMA_IOCTL) | 0x44);
-+
-+ bgmac_speed(bgmac, BGMAC_SPEED_2500);
-+ } else {
- bgmac_speed(bgmac, bgmac->speed);
-+ }
-+ } else {
-+ u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
-+ BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
-+ if (imode == 0 || imode == 1) {
-+ if (bgmac->autoneg)
-+ bgmac_speed(bgmac, BGMAC_SPEED_100);
-+ else
-+ bgmac_speed(bgmac, bgmac->speed);
-+ }
- }
- }
-
-@@ -946,7 +963,8 @@ static void bgmac_chip_reset(struct bgma
-
- bcma_core_enable(core, flags);
-
-- if (core->id.rev > 2) {
-+ if (core->id.rev > 2 && ci->id != BCMA_CHIP_ID_BCM4707 &&
-+ ci->id != BCMA_CHIP_ID_BCM53018) {
- bgmac_set(bgmac, BCMA_CLKCTLST, 1 << 8);
- bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, 1 << 24, 1 << 24,
- 1000);
-@@ -967,10 +985,13 @@ static void bgmac_chip_reset(struct bgma
- et_swtype &= 0x0f;
- et_swtype <<= 4;
- sw_type = et_swtype;
-- } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == 9) {
-+ } else if (ci->id == BCMA_CHIP_ID_BCM5357 &&
-+ ci->pkg == BCMA_PKG_ID_BCM5358) {
- sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
-- } else if ((ci->id != BCMA_CHIP_ID_BCM53572 && ci->pkg == 10) ||
-- (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == 9)) {
-+ } else if ((ci->id != BCMA_CHIP_ID_BCM53572 &&
-+ ci->pkg == BCMA_PKG_ID_BCM47186) ||
-+ (ci->id == BCMA_CHIP_ID_BCM53572 &&
-+ ci->pkg == BCMA_PKG_ID_BCM47188)) {
- sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
- BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
- }
-@@ -1077,12 +1098,15 @@ static void bgmac_enable(struct bgmac *b
- break;
- }
-
-- rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
-- rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
-- bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
-- mdp = (bp_clk * 128 / 1000) - 3;
-- rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
-- bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
-+ if (ci->id != BCMA_CHIP_ID_BCM4707 &&
-+ ci->id != BCMA_CHIP_ID_BCM53018) {
-+ rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
-+ rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
-+ bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000;
-+ mdp = (bp_clk * 128 / 1000) - 3;
-+ rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
-+ bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
-+ }
- }
-
- /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
-@@ -1488,6 +1512,25 @@ static int bgmac_probe(struct bcma_devic
- goto err_netdev_free;
- }
-
-+ /* Northstar, take all GMAC cores out of reset */
-+ if (core->id.id == BCMA_CHIP_ID_BCM4707 ||
-+ core->id.id == BCMA_CHIP_ID_BCM53018) {
-+ struct bcma_device *ns_core;
-+ int ns_gmac;
-+
-+ for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
-+ /* As northstar requirement, we have to reset all GAMCs before
-+ * accessing them. et_probe() call pci_enable_device() for etx
-+ * and do si_core_reset for GAMCx only. Then the other three
-+ * GAMCs didn't reset. We do it here.
-+ */
-+ ns_core = bcma_find_core_unit(core->bus, BCMA_CORE_MAC_GBIT, ns_gmac);
-+ if (!bcma_core_is_enabled(ns_core)) {
-+ bcma_core_enable(ns_core, 0);
-+ }
-+ }
-+ }
-+
- bgmac_chip_reset(bgmac);
-
- err = bgmac_dma_alloc(bgmac);
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -185,6 +185,7 @@
- #define BGMAC_CMDCFG_ES_10 0x00000000
- #define BGMAC_CMDCFG_ES_100 0x00000004
- #define BGMAC_CMDCFG_ES_1000 0x00000008
-+#define BGMAC_CMDCFG_ES_2500 0x0000000C
- #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
- #define BGMAC_CMDCFG_PAD_EN 0x00000020
- #define BGMAC_CMDCFG_CF 0x00000040
-@@ -345,6 +346,7 @@
- #define BGMAC_SPEED_10 0x0001
- #define BGMAC_SPEED_100 0x0002
- #define BGMAC_SPEED_1000 0x0004
-+#define BGMAC_SPEED_2500 0x0008
-
- #define BGMAC_WEIGHT 64
-
#include <bcm47xx_nvram.h>
static const struct bcma_device_id bgmac_bcma_tbl[] = {
-@@ -1443,6 +1444,17 @@ static void bgmac_mii_unregister(struct
+@@ -1405,6 +1406,17 @@ static void bgmac_mii_unregister(struct
mdiobus_free(mii_bus);
}
/**************************************************
* BCMA bus ops
**************************************************/
-@@ -1561,6 +1573,16 @@ static int bgmac_probe(struct bcma_devic
+@@ -1521,6 +1533,16 @@ static int bgmac_probe(struct bcma_devic
goto err_dma_free;
}
err = register_netdev(bgmac->net_dev);
if (err) {
bgmac_err(bgmac, "Cannot register net device\n");
-@@ -1590,6 +1612,10 @@ static void bgmac_remove(struct bcma_dev
+@@ -1549,6 +1571,10 @@ static void bgmac_remove(struct bcma_dev
{
struct bgmac *bgmac = bcma_get_drvdata(core);
bgmac_mii_unregister(bgmac);
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -430,6 +430,9 @@ struct bgmac {
+@@ -457,6 +457,9 @@ struct bgmac {
bool has_robosw;
bool loopback;
+++ /dev/null
-From ec12b94d22fa8715561bdffe6da0781dac08423e Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sun, 10 Nov 2013 21:23:57 +0100
-Subject: [PATCH] bgmac: add some workaround for rev 4
-
----
- drivers/net/ethernet/broadcom/bgmac.c | 8 ++++----
- drivers/net/ethernet/broadcom/bgmac.h | 4 +++-
- 2 files changed, 7 insertions(+), 5 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bgmac.c
-+++ b/drivers/net/ethernet/broadcom/bgmac.c
-@@ -97,6 +97,16 @@ static void bgmac_dma_tx_enable(struct b
- u32 ctl;
-
- ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
-+ if (bgmac->core->id.rev == 4) {
-+ ctl &= ~BGMAC_DMA_TX_BL_MASK;
-+ ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
-+ ctl &= ~BGMAC_DMA_TX_MR_MASK;
-+ ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
-+ ctl &= ~BGMAC_DMA_TX_PC_MASK;
-+ ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
-+ ctl &= ~BGMAC_DMA_TX_PT_MASK;
-+ ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
-+ }
- ctl |= BGMAC_DMA_TX_ENABLE;
- ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
- bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
-@@ -246,6 +256,17 @@ static void bgmac_dma_rx_enable(struct b
- ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
- ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
- ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
-+
-+ if (bgmac->core->id.rev == 4) {
-+ ctl &= ~BGMAC_DMA_RX_BL_MASK;
-+ ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
-+
-+ ctl &= ~BGMAC_DMA_RX_PC_MASK;
-+ ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
-+
-+ ctl &= ~BGMAC_DMA_RX_PT_MASK;
-+ ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
-+ }
- bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
- }
-
-@@ -812,13 +833,13 @@ static void bgmac_cmdcfg_maskset(struct
- u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
- u32 new_val = (cmdcfg & mask) | set;
-
-- bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR);
-+ bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
- udelay(2);
-
- if (new_val != cmdcfg || force)
- bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
-
-- bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR);
-+ bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
- udelay(2);
- }
-
-@@ -1029,7 +1050,7 @@ static void bgmac_chip_reset(struct bgma
- BGMAC_CMDCFG_PROM |
- BGMAC_CMDCFG_NLC |
- BGMAC_CMDCFG_CFE |
-- BGMAC_CMDCFG_SR,
-+ BGMAC_CMDCFG_SR(core->id.rev),
- false);
-
- bgmac_clear_mib(bgmac);
-@@ -1070,7 +1091,7 @@ static void bgmac_enable(struct bgmac *b
-
- cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
- bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
-- BGMAC_CMDCFG_SR, true);
-+ BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
- udelay(2);
- cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
- bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -194,7 +194,9 @@
- #define BGMAC_CMDCFG_TAI 0x00000200
- #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
- #define BGMAC_CMDCFG_HD_SHIFT 10
--#define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */
-+#define BGMAC_CMDCFG_SR_REVO 0x00000800 /* Set to reset mode, for other revs */
-+#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */
-+#define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REVO)
- #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
- #define BGMAC_CMDCFG_AE 0x00400000
- #define BGMAC_CMDCFG_CFE 0x00800000
-@@ -255,9 +257,34 @@
- #define BGMAC_DMA_TX_SUSPEND 0x00000002
- #define BGMAC_DMA_TX_LOOPBACK 0x00000004
- #define BGMAC_DMA_TX_FLUSH 0x00000010
-+#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
-+#define BGMAC_DMA_TX_MR_SHIFT 6
-+#define BGMAC_DMA_TX_MR_1 0
-+#define BGMAC_DMA_TX_MR_2 1
- #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
- #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
- #define BGMAC_DMA_TX_ADDREXT_SHIFT 16
-+#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
-+#define BGMAC_DMA_TX_BL_SHIFT 18
-+#define BGMAC_DMA_TX_BL_16 0
-+#define BGMAC_DMA_TX_BL_32 1
-+#define BGMAC_DMA_TX_BL_64 2
-+#define BGMAC_DMA_TX_BL_128 3
-+#define BGMAC_DMA_TX_BL_256 4
-+#define BGMAC_DMA_TX_BL_512 5
-+#define BGMAC_DMA_TX_BL_1024 6
-+#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
-+#define BGMAC_DMA_TX_PC_SHIFT 21
-+#define BGMAC_DMA_TX_PC_0 0
-+#define BGMAC_DMA_TX_PC_4 1
-+#define BGMAC_DMA_TX_PC_8 2
-+#define BGMAC_DMA_TX_PC_16 3
-+#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
-+#define BGMAC_DMA_TX_PT_SHIFT 24
-+#define BGMAC_DMA_TX_PT_1 0
-+#define BGMAC_DMA_TX_PT_2 1
-+#define BGMAC_DMA_TX_PT_4 2
-+#define BGMAC_DMA_TX_PT_8 3
- #define BGMAC_DMA_TX_INDEX 0x04
- #define BGMAC_DMA_TX_RINGLO 0x08
- #define BGMAC_DMA_TX_RINGHI 0x0C
-@@ -285,8 +312,33 @@
- #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
- #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
- #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
-+#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
-+#define BGMAC_DMA_RX_MR_SHIFT 6
-+#define BGMAC_DMA_TX_MR_1 0
-+#define BGMAC_DMA_TX_MR_2 1
- #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
- #define BGMAC_DMA_RX_ADDREXT_SHIFT 16
-+#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
-+#define BGMAC_DMA_RX_BL_SHIFT 18
-+#define BGMAC_DMA_RX_BL_16 0
-+#define BGMAC_DMA_RX_BL_32 1
-+#define BGMAC_DMA_RX_BL_64 2
-+#define BGMAC_DMA_RX_BL_128 3
-+#define BGMAC_DMA_RX_BL_256 4
-+#define BGMAC_DMA_RX_BL_512 5
-+#define BGMAC_DMA_RX_BL_1024 6
-+#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
-+#define BGMAC_DMA_RX_PC_SHIFT 21
-+#define BGMAC_DMA_RX_PC_0 0
-+#define BGMAC_DMA_RX_PC_4 1
-+#define BGMAC_DMA_RX_PC_8 2
-+#define BGMAC_DMA_RX_PC_16 3
-+#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
-+#define BGMAC_DMA_RX_PT_SHIFT 24
-+#define BGMAC_DMA_RX_PT_1 0
-+#define BGMAC_DMA_RX_PT_2 1
-+#define BGMAC_DMA_RX_PT_4 2
-+#define BGMAC_DMA_RX_PT_8 3
- #define BGMAC_DMA_RX_INDEX 0x24
- #define BGMAC_DMA_RX_RINGLO 0x28
- #define BGMAC_DMA_RX_RINGHI 0x2C
projects / openwrt / staging / ansuel.git / commitdiff