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at91: Move at91 global data into arch_global_data
authorSimon Glass <sjg@chromium.org>
Thu, 13 Dec 2012 20:48:31 +0000 (20:48 +0000)
committerTom Rini <trini@ti.com>
Fri, 1 Feb 2013 20:07:49 +0000 (15:07 -0500)
Move these fields into arch_global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/arm/cpu/arm920t/at91/clock.c patch | blob | history
arch/arm/cpu/arm926ejs/at91/clock.c patch | blob | history
arch/arm/cpu/arm926ejs/at91/timer.c patch | blob | history
arch/arm/include/asm/arch-at91/clk.h patch | blob | history
arch/arm/include/asm/global_data.h patch | blob | history

diff --git a/arch/arm/cpu/arm920t/at91/clock.c b/arch/arm/cpu/arm920t/at91/clock.c
index 09d2799831a2511293c984b21413f4c478918232..696200d04a027658b1761a1c6347dc24b2330abb 100644 (file)
--- a/arch/arm/cpu/arm920t/at91/clock.c
+++ b/arch/arm/cpu/arm920t/at91/clock.c
@@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
        case AT91_PMC_MCKR_CSS_SLOW:
                return CONFIG_SYS_AT91_SLOW_CLOCK;
        case AT91_PMC_MCKR_CSS_MAIN:
-               return gd->main_clk_rate_hz;
+               return gd->arch.main_clk_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLA:
-               return gd->plla_rate_hz;
+               return gd->arch.plla_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLB:
-               return gd->pllb_rate_hz;
+               return gd->arch.pllb_rate_hz;
        }
 
        return 0;
@@ -124,10 +124,10 @@ int at91_clock_init(unsigned long main_clock)
                main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
        }
 #endif
-       gd->main_clk_rate_hz = main_clock;
+       gd->arch.main_clk_rate_hz = main_clock;
 
        /* report if PLLA is more than mildly overclocked */
-       gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+       gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 
 #ifdef CONFIG_USB_ATMEL
        /*
@@ -136,9 +136,10 @@ int at91_clock_init(unsigned long main_clock)
         *
         * REVISIT:  assumes MCK doesn't derive from PLLB!
         */
-       gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+       gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
                             AT91_PMC_PLLBR_USBDIV_2;
-       gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+       gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+                                             gd->arch.at91_pllb_usb_init);
 #endif
 
        /*
@@ -146,13 +147,14 @@ int at91_clock_init(unsigned long main_clock)
         * For now, assume this parentage won't change.
         */
        mckr = readl(&pmc->mckr);
-       gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-       freq = gd->mck_rate_hz;
+       gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+       freq = gd->arch.mck_rate_hz;
 
        freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
        /* mdiv */
-       gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-       gd->cpu_clk_rate_hz = freq;
+       gd->arch.mck_rate_hz = freq /
+                       (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+       gd->arch.cpu_clk_rate_hz = freq;
 
        return 0;
 }
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
index dc5c6c4b0b29b0f2f69a3ec732b6a87185c1c219..f825388ae994f3dde7dca9fd1bb4cbe67beac897 100644 (file)
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
        case AT91_PMC_MCKR_CSS_SLOW:
                return CONFIG_SYS_AT91_SLOW_CLOCK;
        case AT91_PMC_MCKR_CSS_MAIN:
-               return gd->main_clk_rate_hz;
+               return gd->arch.main_clk_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLA:
-               return gd->plla_rate_hz;
+               return gd->arch.plla_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLB:
-               return gd->pllb_rate_hz;
+               return gd->arch.pllb_rate_hz;
        }
 
        return 0;
@@ -132,10 +132,10 @@ int at91_clock_init(unsigned long main_clock)
                main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
        }
 #endif
-       gd->main_clk_rate_hz = main_clock;
+       gd->arch.main_clk_rate_hz = main_clock;
 
        /* report if PLLA is more than mildly overclocked */
-       gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+       gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 
 #ifdef CONFIG_USB_ATMEL
        /*
@@ -144,9 +144,10 @@ int at91_clock_init(unsigned long main_clock)
         *
         * REVISIT:  assumes MCK doesn't derive from PLLB!
         */
-       gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+       gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
                             AT91_PMC_PLLBR_USBDIV_2;
-       gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+       gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+                                             gd->arch.at91_pllb_usb_init);
 #endif
 
        /*
@@ -157,15 +158,15 @@ int at91_clock_init(unsigned long main_clock)
 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
                || defined(CONFIG_AT91SAM9X5)
        /* plla divisor by 2 */
-       gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+       gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 #endif
-       gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-       freq = gd->mck_rate_hz;
+       gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+       freq = gd->arch.mck_rate_hz;
 
        freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
 #if defined(CONFIG_AT91SAM9G20)
        /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
-       gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+       gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
                freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
        if (mckr & AT91_PMC_MCKR_MDIV_MASK)
                freq /= 2;                      /* processor clock division */
@@ -177,14 +178,15 @@ int at91_clock_init(unsigned long main_clock)
         *  2   <==>   4
         *  3   <==>   3
         */
-       gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+       gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
                (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
                ? freq / 3
                : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #else
-       gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+       gd->arch.mck_rate_hz = freq /
+                       (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #endif
-       gd->cpu_clk_rate_hz = freq;
+       gd->arch.cpu_clk_rate_hz = freq;
 
        return 0;
 }
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c
index f70ce83f08391e5378e96f5269a52f86ce4e984a..641ae3ef996095b989559fd26fc15e4e2036e143 100644 (file)
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ b/arch/arm/cpu/arm926ejs/at91/timer.c
@@ -79,7 +79,7 @@ int timer_init(void)
        /* Enable PITC */
        writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
 
-       gd->timer_rate_hz = gd->mck_rate_hz / 16;
+       gd->timer_rate_hz = gd->arch.mck_rate_hz / 16;
        gd->tbu = gd->tbl = 0;
 
        return 0;
diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h
index 1e8522b83980a4eb32e94133e19777d3c52f796d..d4852a38c19c3eb25b960626f03eaad9d55fc39f 100644 (file)
--- a/arch/arm/include/asm/arch-at91/clk.h
+++ b/arch/arm/include/asm/arch-at91/clk.h
@@ -31,37 +31,37 @@
 static inline unsigned long get_cpu_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->cpu_clk_rate_hz;
+       return gd->arch.cpu_clk_rate_hz;
 }
 
 static inline unsigned long get_main_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->main_clk_rate_hz;
+       return gd->arch.main_clk_rate_hz;
 }
 
 static inline unsigned long get_mck_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->mck_rate_hz;
+       return gd->arch.mck_rate_hz;
 }
 
 static inline unsigned long get_plla_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->plla_rate_hz;
+       return gd->arch.plla_rate_hz;
 }
 
 static inline unsigned long get_pllb_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->pllb_rate_hz;
+       return gd->arch.pllb_rate_hz;
 }
 
 static inline u32 get_pllb_init(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->at91_pllb_usb_init;
+       return gd->arch.at91_pllb_usb_init;
 }
 
 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 9fddf3b8d68d83158261157eae2d8c0d610eae68..d147899dd3ac6d1dec33547cb144ef66f8807c75 100644 (file)
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -26,6 +26,15 @@
 
 /* Architecture-specific global data */
 struct arch_global_data {
+#ifdef CONFIG_AT91FAMILY
+       /* "static data" needed by at91's clock.c */
+       unsigned long   cpu_clk_rate_hz;
+       unsigned long   main_clk_rate_hz;
+       unsigned long   mck_rate_hz;
+       unsigned long   plla_rate_hz;
+       unsigned long   pllb_rate_hz;
+       unsigned long   at91_pllb_usb_init;
+#endif
 };
 
 /*
@@ -50,15 +59,6 @@ typedef      struct  global_data {
 #ifdef CONFIG_FSL_ESDHC
        unsigned long   sdhc_clk;
 #endif
-#ifdef CONFIG_AT91FAMILY
-       /* "static data" needed by at91's clock.c */
-       unsigned long   cpu_clk_rate_hz;
-       unsigned long   main_clk_rate_hz;
-       unsigned long   mck_rate_hz;
-       unsigned long   plla_rate_hz;
-       unsigned long   pllb_rate_hz;
-       unsigned long   at91_pllb_usb_init;
-#endif
 #ifdef CONFIG_ARM
        /* "static data" needed by most of timer.c on ARM platforms */
        unsigned long   timer_rate_hz;
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