soc/tegra: fuse: Add cell information

Create nvmem cells for all the fuses currently used by consumers.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index 430a47963a5723229875daa18f64accea4d3836f..cbe3d6f1907412864dd9d7c3eb03fdc076b900a4 100644 (file)
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -86,6 +86,94 @@ static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
        return 0;
 }
 
+static const struct nvmem_cell_info tegra_fuse_cells[] = {
+       {
+               .name = "tsensor-cpu1",
+               .offset = 0x084,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "tsensor-cpu2",
+               .offset = 0x088,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "tsensor-cpu0",
+               .offset = 0x098,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "xusb-pad-calibration",
+               .offset = 0x0f0,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "tsensor-cpu3",
+               .offset = 0x12c,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "sata-calibration",
+               .offset = 0x124,
+               .bytes = 1,
+               .bit_offset = 0,
+               .nbits = 2,
+       }, {
+               .name = "tsensor-gpu",
+               .offset = 0x154,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "tsensor-mem0",
+               .offset = 0x158,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "tsensor-mem1",
+               .offset = 0x15c,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "tsensor-pllx",
+               .offset = 0x160,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "tsensor-common",
+               .offset = 0x180,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "tsensor-realignment",
+               .offset = 0x1fc,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "gpu-calibration",
+               .offset = 0x204,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       }, {
+               .name = "xusb-pad-calibration-ext",
+               .offset = 0x250,
+               .bytes = 4,
+               .bit_offset = 0,
+               .nbits = 32,
+       },
+};
+
 static int tegra_fuse_probe(struct platform_device *pdev)
 {
        void __iomem *base = fuse->base;
@@ -127,6 +215,8 @@ static int tegra_fuse_probe(struct platform_device *pdev)
        nvmem.name = "fuse";
        nvmem.id = -1;
        nvmem.owner = THIS_MODULE;
+       nvmem.cells = tegra_fuse_cells;
+       nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells);
        nvmem.type = NVMEM_TYPE_OTP;
        nvmem.read_only = true;
        nvmem.root_only = true;