arm64: dts: imx8mm: Add cpu speed grading and all OPPs

Add a nvmem cell on cpu node referencing speed grade and the 1.8 Ghz
cpufreq opp.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 6b407a94c06e7f6ae6ec77310ea60ccc6eb19235..7e458dbbd0173ea311c3d4e7901cced021d6828f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -53,6 +53,8 @@
                        enable-method = "psci";
                        next-level-cache = <&A53_L2>;
                        operating-points-v2 = <&a53_opp_table>;
+                       nvmem-cells = <&cpu_speed_grade>;
+                       nvmem-cell-names = "speed_grade";
                };
 
                A53_1: cpu@1 {
@@ -100,14 +102,23 @@
                opp-1200000000 {
                        opp-hz = /bits/ 64 <1200000000>;
                        opp-microvolt = <850000>;
+                       opp-supported-hw = <0xe>, <0x7>;
                        clock-latency-ns = <150000>;
                };
 
                opp-1600000000 {
                        opp-hz = /bits/ 64 <1600000000>;
                        opp-microvolt = <900000>;
+                       opp-supported-hw = <0xc>, <0x7>;
+                       clock-latency-ns = <150000>;
+               };
+
+               opp-1800000000 {
+                       opp-hz = /bits/ 64 <1800000000>;
+                       opp-microvolt = <1000000>;
+                       /* Consumer only but rely on speed grading */
+                       opp-supported-hw = <0x8>, <0x7>;
                        clock-latency-ns = <150000>;
-                       opp-suspend;
                };
        };
 
@@ -319,6 +330,10 @@
                                /* For nvmem subnodes */
                                #address-cells = <1>;
                                #size-cells = <1>;
+
+                               cpu_speed_grade: speed-grade@10 {
+                                       reg = <0x10 4>;
+                               };
                        };
 
                        anatop: anatop@30360000 {