sh: Add support SH7706

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/arch/sh/include/asm/cpu_sh3.h b/arch/sh/include/asm/cpu_sh3.h
index 6db38a2f84ed61806e0913211fa3e54fdc9a8c8c..385f5dc8e03bdaeb5a3e0851faef582174c5c6ae 100644 (file)
--- a/arch/sh/include/asm/cpu_sh3.h
+++ b/arch/sh/include/asm/cpu_sh3.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  *
  * This program is free software; you can redistribute it and/or
@@ -31,7 +31,9 @@
 #define CACHE_OC_NUM_ENTRIES   256
 #define CACHE_OC_ENTRY_SHIFT   4
 
-#if defined(CONFIG_CPU_SH7710)
+#if defined(CONFIG_CPU_SH7706)
+#include <asm/cpu_sh7706.h>
+#elif defined(CONFIG_CPU_SH7710)
 #include <asm/cpu_sh7710.h>
 #elif defined(CONFIG_CPU_SH7720)
 #include <asm/cpu_sh7720.h>

diff --git a/arch/sh/include/asm/cpu_sh7706.h b/arch/sh/include/asm/cpu_sh7706.h
new file mode 100644 (file)
index 0000000..d093f88
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7706.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_CPU_SH7706_H_
+#define _ASM_CPU_SH7706_H_
+
+#define CACHE_OC_NUM_WAYS      4
+#define CCR_CACHE_INIT 0x0000000D
+
+/* MMU and Cache control */
+#define MMUCR  0xFFFFFFE0
+#define CCR            0xFFFFFFEC
+
+/* PFC */
+#define PACR           0xA4050100
+#define PBCR           0xA4050102
+#define PCCR           0xA4050104
+#define PETCR          0xA4050106
+
+/* Port Data Registers */
+#define PADR           0xA4050120
+#define PBDR           0xA4050122
+#define PCDR           0xA4050124
+
+/* BSC */
+#define        FRQCR   0xffffff80
+#define        BCR1    0xffffff60
+#define        BCR2    0xffffff62
+#define        WCR1    0xffffff64
+#define        WCR2    0xffffff66
+#define        MCR             0xffffff68
+
+/* SDRAM controller */
+#define        DCR             0xffffff6a
+#define        RTCSR   0xffffff6e
+#define        RTCNT   0xffffff70
+#define        RTCOR   0xffffff72
+#define        RFCR    0xffffff74
+#define SDMR   0xFFFFD000
+#define CS3_R  0xFFFFE460
+
+/* SCIF */
+#define SCSMR_2                0xA4000150
+#define SCIF0_BASE     SCSMR_2
+
+/* Timer */
+#define TSTR0          0xFFFFFE92
+#define TSTR           TSTR0
+#define TCNT0          0xFFFFFE98
+#define TCR0           0xFFFFFE9C
+
+/* On chip oscillator circuits */
+#define        WTCNT   0xFFFFFF84
+#define        WTCSR   0xFFFFFF86
+
+#endif /* _ASM_CPU_SH7706_H_ */