drm/radeon: optimize SI VM handling
authorChristian König <christian.koenig@amd.com>
Tue, 27 May 2014 14:47:38 +0000 (16:47 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 2 Jun 2014 14:25:14 +0000 (10:25 -0400)
Fill VM page tables from the GART page table if applicable.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/si_dma.c

index cf0fdad8c278ef6921bbab3677c2cd596bcf1575..952166930fb80ae97ebbac6bcc8302c08d004897 100644 (file)
@@ -79,7 +79,25 @@ void si_dma_vm_set_page(struct radeon_device *rdev,
 
        trace_radeon_vm_set_page(pe, addr, count, incr, flags);
 
-       if (flags & R600_PTE_SYSTEM) {
+       if (flags == R600_PTE_GART) {
+               uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
+               while (count) {
+                       unsigned bytes = count * 8;
+                       if (bytes > 0xFFFF8)
+                               bytes = 0xFFFF8;
+
+                       ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
+                                                             1, 0, 0, bytes);
+                       ib->ptr[ib->length_dw++] = pe & 0xffffffff;
+                       ib->ptr[ib->length_dw++] = src & 0xffffffff;
+                       ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
+                       ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff;
+
+                       pe += bytes;
+                       src += bytes;
+                       count -= bytes / 8;
+               }
+       } else if (flags & R600_PTE_SYSTEM) {
                while (count) {
                        ndw = count * 2;
                        if (ndw > 0xFFFFE)