: [res] "=r" (result), [texasr] "=r" (texasr)
: [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt),
[sprn_texasr] "i" (SPRN_TEXASR)
- : "memory", "r0", "r1", "r2", "r3", "r4",
- "r8", "r9", "r10", "r11"
+ : "memory", "r0", "r1", "r3", "r4",
+ "r7", "r8", "r9", "r10", "r11"
);
if (result) {
: [tfhar] "=r" (tfhar), [res] "=r" (result),
[texasr] "=r" (texasr), [cptr1] "=r" (cptr1)
: [sprn_texasr] "i" (SPRN_TEXASR)
- : "memory", "r0", "r1", "r2", "r3", "r4",
- "r8", "r9", "r10", "r11", "r31"
+ : "memory", "r0", "r8", "r31"
);
/* There are 2 32bit instructions before tbegin. */
: [res] "=r" (result), [texasr] "=r" (texasr)
: [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt),
[sprn_texasr] "i" (SPRN_TEXASR), [cptr1] "r" (&cptr[1])
- : "memory", "r0", "r1", "r2", "r3", "r4",
+ : "memory", "r0", "r1", "r3", "r4",
"r7", "r8", "r9", "r10", "r11"
);